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megaraid_sas: Support for Intruder (12 Gbps) controller
[mirror_ubuntu-artful-kernel.git] / drivers / scsi / megaraid / megaraid_sas.h
CommitLineData
c4a3e0a5 1/*
3f1530c1 2 * Linux MegaRAID driver for SAS based RAID controllers
c4a3e0a5 3 *
e399065b
SS		 4 * Copyright (c) 2003-2013 LSI Corporation
5 * Copyright (c) 2013-2014 Avago Technologies
c4a3e0a5 6 *
3f1530c1
AR		 7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
c4a3e0a5 11 *
3f1530c1
AR		 12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
c4a3e0a5 16 *
3f1530c1 17 * You should have received a copy of the GNU General Public License
e399065b 18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
3f1530c1
AR		 19 *
20 * FILE: megaraid_sas.h
21 *
e399065b
SS		 22 * Authors: Avago Technologies
23 * Kashyap Desai <kashyap.desai@avagotech.com>
24 * Sumit Saxena <sumit.saxena@avagotech.com>
3f1530c1 25 *
e399065b 26 * Send feedback to: megaraidlinux.pdl@avagotech.com
3f1530c1 27 *
e399065b
SS		 28 * Mail to: Avago Technologies, 350 West Trimble Road, Building 90,
29 * San Jose, California 95131
c4a3e0a5
BS		 30 */
31
32#ifndef LSI_MEGARAID_SAS_H
33#define LSI_MEGARAID_SAS_H
34
a69b74d3 35/*
c4a3e0a5
BS		 36 * MegaRAID SAS Driver meta data
37 */
609fb07b 38#define MEGASAS_VERSION "06.808.14.00-rc1"
39#define MEGASAS_RELDATE "Jul 31, 2015"
0e98936c
SP		 40
41/*
42 * Device IDs
43 */
44#define PCI_DEVICE_ID_LSI_SAS1078R 0x0060
af7a5647 45#define PCI_DEVICE_ID_LSI_SAS1078DE 0x007C
0e98936c 46#define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413
6610a6b3
YB		 47#define PCI_DEVICE_ID_LSI_SAS1078GEN2 0x0078
48#define PCI_DEVICE_ID_LSI_SAS0079GEN2 0x0079
87911122
YB		 49#define PCI_DEVICE_ID_LSI_SAS0073SKINNY 0x0073
50#define PCI_DEVICE_ID_LSI_SAS0071SKINNY 0x0071
9c915a8c 51#define PCI_DEVICE_ID_LSI_FUSION 0x005b
229fe47c 52#define PCI_DEVICE_ID_LSI_PLASMA 0x002f
36807e67 53#define PCI_DEVICE_ID_LSI_INVADER 0x005d
21d3c710 54#define PCI_DEVICE_ID_LSI_FURY 0x005f
90c204bc 55#define PCI_DEVICE_ID_LSI_INTRUDER 0x00ce
56#define PCI_DEVICE_ID_LSI_INTRUDER_24 0x00cf
0e98936c 57
39b72c3c
SS		 58/*
59 * Intel HBA SSDIDs
60 */
61#define MEGARAID_INTEL_RS3DC080_SSDID 0x9360
62#define MEGARAID_INTEL_RS3DC040_SSDID 0x9362
63#define MEGARAID_INTEL_RS3SC008_SSDID 0x9380
64#define MEGARAID_INTEL_RS3MC044_SSDID 0x9381
65#define MEGARAID_INTEL_RS3WC080_SSDID 0x9341
66#define MEGARAID_INTEL_RS3WC040_SSDID 0x9343
67
90c204bc 68/*
69 * Intruder HBA SSDIDs
70 */
71#define MEGARAID_INTRUDER_SSDID1 0x9371
72#define MEGARAID_INTRUDER_SSDID2 0x9390
73#define MEGARAID_INTRUDER_SSDID3 0x9370
74
39b72c3c
SS		 75/*
76 * Intel HBA branding
77 */
78#define MEGARAID_INTEL_RS3DC080_BRANDING \
79 "Intel(R) RAID Controller RS3DC080"
80#define MEGARAID_INTEL_RS3DC040_BRANDING \
81 "Intel(R) RAID Controller RS3DC040"
82#define MEGARAID_INTEL_RS3SC008_BRANDING \
83 "Intel(R) RAID Controller RS3SC008"
84#define MEGARAID_INTEL_RS3MC044_BRANDING \
85 "Intel(R) RAID Controller RS3MC044"
86#define MEGARAID_INTEL_RS3WC080_BRANDING \
87 "Intel(R) RAID Controller RS3WC080"
88#define MEGARAID_INTEL_RS3WC040_BRANDING \
89 "Intel(R) RAID Controller RS3WC040"
90
c4a3e0a5
BS		 91/*
92 * =====================================
93 * MegaRAID SAS MFI firmware definitions
94 * =====================================
95 */
96
97/*
98 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for
99 * protocol between the software and firmware. Commands are issued using
100 * "message frames"
101 */
102
a69b74d3 103/*
c4a3e0a5
BS		 104 * FW posts its state in upper 4 bits of outbound_msg_0 register
105 */
106#define MFI_STATE_MASK 0xF0000000
107#define MFI_STATE_UNDEFINED 0x00000000
108#define MFI_STATE_BB_INIT 0x10000000
109#define MFI_STATE_FW_INIT 0x40000000
110#define MFI_STATE_WAIT_HANDSHAKE 0x60000000
111#define MFI_STATE_FW_INIT_2 0x70000000
112#define MFI_STATE_DEVICE_SCAN 0x80000000
e3bbff9f 113#define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000
c4a3e0a5
BS		 114#define MFI_STATE_FLUSH_CACHE 0xA0000000
115#define MFI_STATE_READY 0xB0000000
116#define MFI_STATE_OPERATIONAL 0xC0000000
117#define MFI_STATE_FAULT 0xF0000000
fc62b3fc
SS		 118#define MFI_STATE_FORCE_OCR 0x00000080
119#define MFI_STATE_DMADONE 0x00000008
120#define MFI_STATE_CRASH_DUMP_DONE 0x00000004
7e70e733
AR		 121#define MFI_RESET_REQUIRED 0x00000001
122#define MFI_RESET_ADAPTER 0x00000002
c4a3e0a5
BS		 123#define MEGAMFI_FRAME_SIZE 64
124
a69b74d3 125/*
c4a3e0a5
BS		 126 * During FW init, clear pending cmds & reset state using inbound_msg_0
127 *
128 * ABORT : Abort all pending cmds
129 * READY : Move from OPERATIONAL to READY state; discard queue info
130 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??)
131 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
e3bbff9f
SP		 132 * HOTPLUG : Resume from Hotplug
133 * MFI_STOP_ADP : Send signal to FW to stop processing
c4a3e0a5 134 */
39a98554 135#define WRITE_SEQUENCE_OFFSET (0x0000000FC) /* I20 */
136#define HOST_DIAGNOSTIC_OFFSET (0x000000F8) /* I20 */
137#define DIAG_WRITE_ENABLE (0x00000080)
138#define DIAG_RESET_ADAPTER (0x00000004)
139
140#define MFI_ADP_RESET 0x00000040
e3bbff9f 141#define MFI_INIT_ABORT 0x00000001
c4a3e0a5
BS		 142#define MFI_INIT_READY 0x00000002
143#define MFI_INIT_MFIMODE 0x00000004
144#define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
e3bbff9f
SP		 145#define MFI_INIT_HOTPLUG 0x00000010
146#define MFI_STOP_ADP 0x00000020
147#define MFI_RESET_FLAGS MFI_INIT_READY| \
148 MFI_INIT_MFIMODE| \
149 MFI_INIT_ABORT
c4a3e0a5 150
a69b74d3 151/*
c4a3e0a5
BS		 152 * MFI frame flags
153 */
154#define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
155#define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
156#define MFI_FRAME_SGL32 0x0000
157#define MFI_FRAME_SGL64 0x0002
158#define MFI_FRAME_SENSE32 0x0000
159#define MFI_FRAME_SENSE64 0x0004
160#define MFI_FRAME_DIR_NONE 0x0000
161#define MFI_FRAME_DIR_WRITE 0x0008
162#define MFI_FRAME_DIR_READ 0x0010
163#define MFI_FRAME_DIR_BOTH 0x0018
f4c9a131 164#define MFI_FRAME_IEEE 0x0020
c4a3e0a5 165
4026e9aa
SS		 166/* Driver internal */
167#define DRV_DCMD_POLLED_MODE 0x1
168
a69b74d3 169/*
c4a3e0a5
BS		 170 * Definition for cmd_status
171 */
172#define MFI_CMD_STATUS_POLL_MODE 0xFF
173
a69b74d3 174/*
c4a3e0a5
BS		 175 * MFI command opcodes
176 */
177#define MFI_CMD_INIT 0x00
178#define MFI_CMD_LD_READ 0x01
179#define MFI_CMD_LD_WRITE 0x02
180#define MFI_CMD_LD_SCSI_IO 0x03
181#define MFI_CMD_PD_SCSI_IO 0x04
182#define MFI_CMD_DCMD 0x05
183#define MFI_CMD_ABORT 0x06
184#define MFI_CMD_SMP 0x07
185#define MFI_CMD_STP 0x08
e5f93a36 186#define MFI_CMD_INVALID 0xff
c4a3e0a5
BS		 187
188#define MR_DCMD_CTRL_GET_INFO 0x01010000
bdc6fb8d 189#define MR_DCMD_LD_GET_LIST 0x03010000
21c9e160 190#define MR_DCMD_LD_LIST_QUERY 0x03010100
c4a3e0a5
BS		 191
192#define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
193#define MR_FLUSH_CTRL_CACHE 0x01
194#define MR_FLUSH_DISK_CACHE 0x02
195
196#define MR_DCMD_CTRL_SHUTDOWN 0x01050000
31ea7088 197#define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000
c4a3e0a5
BS		 198#define MR_ENABLE_DRIVE_SPINDOWN 0x01
199
200#define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
201#define MR_DCMD_CTRL_EVENT_GET 0x01040300
202#define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
203#define MR_DCMD_LD_GET_PROPERTIES 0x03030000
204
205#define MR_DCMD_CLUSTER 0x08000000
206#define MR_DCMD_CLUSTER_RESET_ALL 0x08010100
207#define MR_DCMD_CLUSTER_RESET_LD 0x08010200
81e403ce 208#define MR_DCMD_PD_LIST_QUERY 0x02010100
c4a3e0a5 209
fc62b3fc
SS		 210#define MR_DCMD_CTRL_SET_CRASH_DUMP_PARAMS 0x01190100
211#define MR_DRIVER_SET_APP_CRASHDUMP_MODE (0xF0010000 | 0x0600)
212
bc93d425
SS		 213/*
214 * Global functions
215 */
216extern u8 MR_ValidateMapInfo(struct megasas_instance *instance);
217
218
a69b74d3 219/*
c4a3e0a5
BS		 220 * MFI command completion codes
221 */
222enum MFI_STAT {
223 MFI_STAT_OK = 0x00,
224 MFI_STAT_INVALID_CMD = 0x01,
225 MFI_STAT_INVALID_DCMD = 0x02,
226 MFI_STAT_INVALID_PARAMETER = 0x03,
227 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
228 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
229 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
230 MFI_STAT_APP_IN_USE = 0x07,
231 MFI_STAT_APP_NOT_INITIALIZED = 0x08,
232 MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
233 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
234 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
235 MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
236 MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
237 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
238 MFI_STAT_FLASH_BUSY = 0x0f,
239 MFI_STAT_FLASH_ERROR = 0x10,
240 MFI_STAT_FLASH_IMAGE_BAD = 0x11,
241 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
242 MFI_STAT_FLASH_NOT_OPEN = 0x13,
243 MFI_STAT_FLASH_NOT_STARTED = 0x14,
244 MFI_STAT_FLUSH_FAILED = 0x15,
245 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
246 MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
247 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
248 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
249 MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
250 MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
251 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
252 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
253 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
254 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
255 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
256 MFI_STAT_MFC_HW_ERROR = 0x21,
257 MFI_STAT_NO_HW_PRESENT = 0x22,
258 MFI_STAT_NOT_FOUND = 0x23,
259 MFI_STAT_NOT_IN_ENCL = 0x24,
260 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
261 MFI_STAT_PD_TYPE_WRONG = 0x26,
262 MFI_STAT_PR_DISABLED = 0x27,
263 MFI_STAT_ROW_INDEX_INVALID = 0x28,
264 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
265 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
266 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
267 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
268 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
269 MFI_STAT_SCSI_IO_FAILED = 0x2e,
270 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
271 MFI_STAT_SHUTDOWN_FAILED = 0x30,
272 MFI_STAT_TIME_NOT_SET = 0x31,
273 MFI_STAT_WRONG_STATE = 0x32,
274 MFI_STAT_LD_OFFLINE = 0x33,
275 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34,
276 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35,
277 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36,
278 MFI_STAT_I2C_ERRORS_DETECTED = 0x37,
279 MFI_STAT_PCI_ERRORS_DETECTED = 0x38,
36807e67 280 MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67,
c4a3e0a5
BS		 281
282 MFI_STAT_INVALID_STATUS = 0xFF
283};
284
714f5177 285enum mfi_evt_class {
286 MFI_EVT_CLASS_DEBUG = -2,
287 MFI_EVT_CLASS_PROGRESS = -1,
288 MFI_EVT_CLASS_INFO = 0,
289 MFI_EVT_CLASS_WARNING = 1,
290 MFI_EVT_CLASS_CRITICAL = 2,
291 MFI_EVT_CLASS_FATAL = 3,
292 MFI_EVT_CLASS_DEAD = 4
293};
294
fc62b3fc
SS		 295/*
296 * Crash dump related defines
297 */
298#define MAX_CRASH_DUMP_SIZE 512
299#define CRASH_DMA_BUF_SIZE (1024 * 1024)
300
301enum MR_FW_CRASH_DUMP_STATE {
302 UNAVAILABLE = 0,
303 AVAILABLE = 1,
304 COPYING = 2,
305 COPIED = 3,
306 COPY_ERROR = 4,
307};
308
309enum _MR_CRASH_BUF_STATUS {
310 MR_CRASH_BUF_TURN_OFF = 0,
311 MR_CRASH_BUF_TURN_ON = 1,
312};
313
c4a3e0a5
BS		 314/*
315 * Number of mailbox bytes in DCMD message frame
316 */
317#define MFI_MBOX_SIZE 12
318
319enum MR_EVT_CLASS {
320
321 MR_EVT_CLASS_DEBUG = -2,
322 MR_EVT_CLASS_PROGRESS = -1,
323 MR_EVT_CLASS_INFO = 0,
324 MR_EVT_CLASS_WARNING = 1,
325 MR_EVT_CLASS_CRITICAL = 2,
326 MR_EVT_CLASS_FATAL = 3,
327 MR_EVT_CLASS_DEAD = 4,
328
329};
330
331enum MR_EVT_LOCALE {
332
333 MR_EVT_LOCALE_LD = 0x0001,
334 MR_EVT_LOCALE_PD = 0x0002,
335 MR_EVT_LOCALE_ENCL = 0x0004,
336 MR_EVT_LOCALE_BBU = 0x0008,
337 MR_EVT_LOCALE_SAS = 0x0010,
338 MR_EVT_LOCALE_CTRL = 0x0020,
339 MR_EVT_LOCALE_CONFIG = 0x0040,
340 MR_EVT_LOCALE_CLUSTER = 0x0080,
341 MR_EVT_LOCALE_ALL = 0xffff,
342
343};
344
345enum MR_EVT_ARGS {
346
347 MR_EVT_ARGS_NONE,
348 MR_EVT_ARGS_CDB_SENSE,
349 MR_EVT_ARGS_LD,
350 MR_EVT_ARGS_LD_COUNT,
351 MR_EVT_ARGS_LD_LBA,
352 MR_EVT_ARGS_LD_OWNER,
353 MR_EVT_ARGS_LD_LBA_PD_LBA,
354 MR_EVT_ARGS_LD_PROG,
355 MR_EVT_ARGS_LD_STATE,
356 MR_EVT_ARGS_LD_STRIP,
357 MR_EVT_ARGS_PD,
358 MR_EVT_ARGS_PD_ERR,
359 MR_EVT_ARGS_PD_LBA,
360 MR_EVT_ARGS_PD_LBA_LD,
361 MR_EVT_ARGS_PD_PROG,
362 MR_EVT_ARGS_PD_STATE,
363 MR_EVT_ARGS_PCI,
364 MR_EVT_ARGS_RATE,
365 MR_EVT_ARGS_STR,
366 MR_EVT_ARGS_TIME,
367 MR_EVT_ARGS_ECC,
81e403ce
YB		 368 MR_EVT_ARGS_LD_PROP,
369 MR_EVT_ARGS_PD_SPARE,
370 MR_EVT_ARGS_PD_INDEX,
371 MR_EVT_ARGS_DIAG_PASS,
372 MR_EVT_ARGS_DIAG_FAIL,
373 MR_EVT_ARGS_PD_LBA_LBA,
374 MR_EVT_ARGS_PORT_PHY,
375 MR_EVT_ARGS_PD_MISSING,
376 MR_EVT_ARGS_PD_ADDRESS,
377 MR_EVT_ARGS_BITMAP,
378 MR_EVT_ARGS_CONNECTOR,
379 MR_EVT_ARGS_PD_PD,
380 MR_EVT_ARGS_PD_FRU,
381 MR_EVT_ARGS_PD_PATHINFO,
382 MR_EVT_ARGS_PD_POWER_STATE,
383 MR_EVT_ARGS_GENERIC,
384};
c4a3e0a5 385
81e403ce
YB		 386/*
387 * define constants for device list query options
388 */
389enum MR_PD_QUERY_TYPE {
390 MR_PD_QUERY_TYPE_ALL = 0,
391 MR_PD_QUERY_TYPE_STATE = 1,
392 MR_PD_QUERY_TYPE_POWER_STATE = 2,
393 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3,
394 MR_PD_QUERY_TYPE_SPEED = 4,
395 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5,
c4a3e0a5
BS		 396};
397
21c9e160
AR		 398enum MR_LD_QUERY_TYPE {
399 MR_LD_QUERY_TYPE_ALL = 0,
400 MR_LD_QUERY_TYPE_EXPOSED_TO_HOST = 1,
401 MR_LD_QUERY_TYPE_USED_TGT_IDS = 2,
402 MR_LD_QUERY_TYPE_CLUSTER_ACCESS = 3,
403 MR_LD_QUERY_TYPE_CLUSTER_LOCALE = 4,
404};
405
406
7e8a75f4
YB		 407#define MR_EVT_CFG_CLEARED 0x0004
408#define MR_EVT_LD_STATE_CHANGE 0x0051
409#define MR_EVT_PD_INSERTED 0x005b
410#define MR_EVT_PD_REMOVED 0x0070
411#define MR_EVT_LD_CREATED 0x008a
412#define MR_EVT_LD_DELETED 0x008b
413#define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db
414#define MR_EVT_LD_OFFLINE 0x00fc
415#define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152
7e8a75f4 416
81e403ce
YB		 417enum MR_PD_STATE {
418 MR_PD_STATE_UNCONFIGURED_GOOD = 0x00,
419 MR_PD_STATE_UNCONFIGURED_BAD = 0x01,
420 MR_PD_STATE_HOT_SPARE = 0x02,
421 MR_PD_STATE_OFFLINE = 0x10,
422 MR_PD_STATE_FAILED = 0x11,
423 MR_PD_STATE_REBUILD = 0x14,
424 MR_PD_STATE_ONLINE = 0x18,
425 MR_PD_STATE_COPYBACK = 0x20,
426 MR_PD_STATE_SYSTEM = 0x40,
427 };
428
429
430 /*
431 * defines the physical drive address structure
432 */
433struct MR_PD_ADDRESS {
9ab9ed38 434 __le16 deviceId;
81e403ce
YB		 435 u16 enclDeviceId;
436
437 union {
438 struct {
439 u8 enclIndex;
440 u8 slotNumber;
441 } mrPdAddress;
442 struct {
443 u8 enclPosition;
444 u8 enclConnectorIndex;
445 } mrEnclAddress;
446 };
447 u8 scsiDevType;
448 union {
449 u8 connectedPortBitmap;
450 u8 connectedPortNumbers;
451 };
452 u64 sasAddr[2];
453} __packed;
454
455/*
456 * defines the physical drive list structure
457 */
458struct MR_PD_LIST {
9ab9ed38
CH		 459 __le32 size;
460 __le32 count;
81e403ce
YB		 461 struct MR_PD_ADDRESS addr[1];
462} __packed;
463
464struct megasas_pd_list {
465 u16 tid;
466 u8 driveType;
467 u8 driveState;
468} __packed;
469
bdc6fb8d
YB		 470 /*
471 * defines the logical drive reference structure
472 */
473union MR_LD_REF {
474 struct {
475 u8 targetId;
476 u8 reserved;
9ab9ed38 477 __le16 seqNum;
bdc6fb8d 478 };
9ab9ed38 479 __le32 ref;
bdc6fb8d
YB		 480} __packed;
481
482/*
483 * defines the logical drive list structure
484 */
485struct MR_LD_LIST {
9ab9ed38
CH		 486 __le32 ldCount;
487 __le32 reserved;
bdc6fb8d
YB		 488 struct {
489 union MR_LD_REF ref;
490 u8 state;
491 u8 reserved[3];
9ab9ed38 492 __le64 size;
51087a86 493 } ldList[MAX_LOGICAL_DRIVES_EXT];
bdc6fb8d
YB		 494} __packed;
495
21c9e160 496struct MR_LD_TARGETID_LIST {
9ab9ed38
CH		 497 __le32 size;
498 __le32 count;
21c9e160 499 u8 pad[3];
51087a86 500 u8 targetId[MAX_LOGICAL_DRIVES_EXT];
21c9e160
AR		 501};
502
503
c4a3e0a5
BS		 504/*
505 * SAS controller properties
506 */
507struct megasas_ctrl_prop {
508
509 u16 seq_num;
510 u16 pred_fail_poll_interval;
511 u16 intr_throttle_count;
512 u16 intr_throttle_timeouts;
513 u8 rebuild_rate;
514 u8 patrol_read_rate;
515 u8 bgi_rate;
516 u8 cc_rate;
517 u8 recon_rate;
518 u8 cache_flush_interval;
519 u8 spinup_drv_count;
520 u8 spinup_delay;
521 u8 cluster_enable;
522 u8 coercion_mode;
523 u8 alarm_enable;
524 u8 disable_auto_rebuild;
525 u8 disable_battery_warn;
526 u8 ecc_bucket_size;
527 u16 ecc_bucket_leak_rate;
528 u8 restore_hotspare_on_insertion;
529 u8 expose_encl_devices;
39a98554 530 u8 maintainPdFailHistory;
531 u8 disallowHostRequestReordering;
532 u8 abortCCOnError;
533 u8 loadBalanceMode;
534 u8 disableAutoDetectBackplane;
535
536 u8 snapVDSpace;
537
538 /*
539 * Add properties that can be controlled by
540 * a bit in the following structure.
541 */
39a98554 542 struct {
94cd65dd
SS		 543#if defined(__BIG_ENDIAN_BITFIELD)
544 u32 reserved:18;
545 u32 enableJBOD:1;
546 u32 disableSpinDownHS:1;
547 u32 allowBootWithPinnedCache:1;
548 u32 disableOnlineCtrlReset:1;
549 u32 enableSecretKeyControl:1;
550 u32 autoEnhancedImport:1;
551 u32 enableSpinDownUnconfigured:1;
552 u32 SSDPatrolReadEnabled:1;
553 u32 SSDSMARTerEnabled:1;
554 u32 disableNCQ:1;
555 u32 useFdeOnly:1;
556 u32 prCorrectUnconfiguredAreas:1;
557 u32 SMARTerEnabled:1;
558 u32 copyBackDisabled:1;
559#else
560 u32 copyBackDisabled:1;
561 u32 SMARTerEnabled:1;
562 u32 prCorrectUnconfiguredAreas:1;
563 u32 useFdeOnly:1;
564 u32 disableNCQ:1;
565 u32 SSDSMARTerEnabled:1;
566 u32 SSDPatrolReadEnabled:1;
567 u32 enableSpinDownUnconfigured:1;
568 u32 autoEnhancedImport:1;
569 u32 enableSecretKeyControl:1;
570 u32 disableOnlineCtrlReset:1;
571 u32 allowBootWithPinnedCache:1;
572 u32 disableSpinDownHS:1;
573 u32 enableJBOD:1;
574 u32 reserved:18;
575#endif
39a98554 576 } OnOffProperties;
577 u8 autoSnapVDSpace;
578 u8 viewSpace;
9ab9ed38 579 __le16 spinDownTime;
39a98554 580 u8 reserved[24];
81e403ce 581} __packed;
c4a3e0a5
BS		 582
583/*
584 * SAS controller information
585 */
586struct megasas_ctrl_info {
587
588 /*
589 * PCI device information
590 */
591 struct {
592
9ab9ed38
CH		 593 __le16 vendor_id;
594 __le16 device_id;
595 __le16 sub_vendor_id;
596 __le16 sub_device_id;
c4a3e0a5
BS		 597 u8 reserved[24];
598
599 } __attribute__ ((packed)) pci;
600
601 /*
602 * Host interface information
603 */
604 struct {
605
606 u8 PCIX:1;
607 u8 PCIE:1;
608 u8 iSCSI:1;
609 u8 SAS_3G:1;
229fe47c
AR		 610 u8 SRIOV:1;
611 u8 reserved_0:3;
c4a3e0a5
BS		 612 u8 reserved_1[6];
613 u8 port_count;
614 u64 port_addr[8];
615
616 } __attribute__ ((packed)) host_interface;
617
618 /*
619 * Device (backend) interface information
620 */
621 struct {
622
623 u8 SPI:1;
624 u8 SAS_3G:1;
625 u8 SATA_1_5G:1;
626 u8 SATA_3G:1;
627 u8 reserved_0:4;
628 u8 reserved_1[6];
629 u8 port_count;
630 u64 port_addr[8];
631
632 } __attribute__ ((packed)) device_interface;
633
634 /*
635 * List of components residing in flash. All str are null terminated
636 */
9ab9ed38
CH		 637 __le32 image_check_word;
638 __le32 image_component_count;
c4a3e0a5
BS		 639
640 struct {
641
642 char name[8];
643 char version[32];
644 char build_date[16];
645 char built_time[16];
646
647 } __attribute__ ((packed)) image_component[8];
648
649 /*
650 * List of flash components that have been flashed on the card, but
651 * are not in use, pending reset of the adapter. This list will be
652 * empty if a flash operation has not occurred. All stings are null
653 * terminated
654 */
9ab9ed38 655 __le32 pending_image_component_count;
c4a3e0a5
BS		 656
657 struct {
658
659 char name[8];
660 char version[32];
661 char build_date[16];
662 char build_time[16];
663
664 } __attribute__ ((packed)) pending_image_component[8];
665
666 u8 max_arms;
667 u8 max_spans;
668 u8 max_arrays;
669 u8 max_lds;
670
671 char product_name[80];
672 char serial_no[32];
673
674 /*
675 * Other physical/controller/operation information. Indicates the
676 * presence of the hardware
677 */
678 struct {
679
680 u32 bbu:1;
681 u32 alarm:1;
682 u32 nvram:1;
683 u32 uart:1;
684 u32 reserved:28;
685
686 } __attribute__ ((packed)) hw_present;
687
9ab9ed38 688 __le32 current_fw_time;
c4a3e0a5
BS		 689
690 /*
691 * Maximum data transfer sizes
692 */
9ab9ed38
CH		 693 __le16 max_concurrent_cmds;
694 __le16 max_sge_count;
695 __le32 max_request_size;
c4a3e0a5
BS		 696
697 /*
698 * Logical and physical device counts
699 */
9ab9ed38
CH		 700 __le16 ld_present_count;
701 __le16 ld_degraded_count;
702 __le16 ld_offline_count;
c4a3e0a5 703
9ab9ed38
CH		 704 __le16 pd_present_count;
705 __le16 pd_disk_present_count;
706 __le16 pd_disk_pred_failure_count;
707 __le16 pd_disk_failed_count;
c4a3e0a5
BS		 708
709 /*
710 * Memory size information
711 */
9ab9ed38
CH		 712 __le16 nvram_size;
713 __le16 memory_size;
714 __le16 flash_size;
c4a3e0a5
BS		 715
716 /*
717 * Error counters
718 */
9ab9ed38
CH		 719 __le16 mem_correctable_error_count;
720 __le16 mem_uncorrectable_error_count;
c4a3e0a5
BS		 721
722 /*
723 * Cluster information
724 */
725 u8 cluster_permitted;
726 u8 cluster_active;
727
728 /*
729 * Additional max data transfer sizes
730 */
9ab9ed38 731 __le16 max_strips_per_io;
c4a3e0a5
BS		 732
733 /*
734 * Controller capabilities structures
735 */
736 struct {
737
738 u32 raid_level_0:1;
739 u32 raid_level_1:1;
740 u32 raid_level_5:1;
741 u32 raid_level_1E:1;
742 u32 raid_level_6:1;
743 u32 reserved:27;
744
745 } __attribute__ ((packed)) raid_levels;
746
747 struct {
748
749 u32 rbld_rate:1;
750 u32 cc_rate:1;
751 u32 bgi_rate:1;
752 u32 recon_rate:1;
753 u32 patrol_rate:1;
754 u32 alarm_control:1;
755 u32 cluster_supported:1;
756 u32 bbu:1;
757 u32 spanning_allowed:1;
758 u32 dedicated_hotspares:1;
759 u32 revertible_hotspares:1;
760 u32 foreign_config_import:1;
761 u32 self_diagnostic:1;
762 u32 mixed_redundancy_arr:1;
763 u32 global_hot_spares:1;
764 u32 reserved:17;
765
766 } __attribute__ ((packed)) adapter_operations;
767
768 struct {
769
770 u32 read_policy:1;
771 u32 write_policy:1;
772 u32 io_policy:1;
773 u32 access_policy:1;
774 u32 disk_cache_policy:1;
775 u32 reserved:27;
776
777 } __attribute__ ((packed)) ld_operations;
778
779 struct {
780
781 u8 min;
782 u8 max;
783 u8 reserved[2];
784
785 } __attribute__ ((packed)) stripe_sz_ops;
786
787 struct {
788
789 u32 force_online:1;
790 u32 force_offline:1;
791 u32 force_rebuild:1;
792 u32 reserved:29;
793
794 } __attribute__ ((packed)) pd_operations;
795
796 struct {
797
798 u32 ctrl_supports_sas:1;
799 u32 ctrl_supports_sata:1;
800 u32 allow_mix_in_encl:1;
801 u32 allow_mix_in_ld:1;
802 u32 allow_sata_in_cluster:1;
803 u32 reserved:27;
804
805 } __attribute__ ((packed)) pd_mix_support;
806
807 /*
808 * Define ECC single-bit-error bucket information
809 */
810 u8 ecc_bucket_count;
811 u8 reserved_2[11];
812
813 /*
814 * Include the controller properties (changeable items)
815 */
816 struct megasas_ctrl_prop properties;
817
818 /*
819 * Define FW pkg version (set in envt v'bles on OEM basis)
820 */
821 char package_version[0x60];
822
c4a3e0a5 823
bc93d425
SS		 824 /*
825 * If adapterOperations.supportMoreThan8Phys is set,
826 * and deviceInterface.portCount is greater than 8,
827 * SAS Addrs for first 8 ports shall be populated in
828 * deviceInterface.portAddr, and the rest shall be
829 * populated in deviceInterfacePortAddr2.
830 */
9ab9ed38 831 __le64 deviceInterfacePortAddr2[8]; /*6a0h */
bc93d425
SS		 832 u8 reserved3[128]; /*6e0h */
833
834 struct { /*760h */
835 u16 minPdRaidLevel_0:4;
836 u16 maxPdRaidLevel_0:12;
837
838 u16 minPdRaidLevel_1:4;
839 u16 maxPdRaidLevel_1:12;
840
841 u16 minPdRaidLevel_5:4;
842 u16 maxPdRaidLevel_5:12;
843
844 u16 minPdRaidLevel_1E:4;
845 u16 maxPdRaidLevel_1E:12;
846
847 u16 minPdRaidLevel_6:4;
848 u16 maxPdRaidLevel_6:12;
849
850 u16 minPdRaidLevel_10:4;
851 u16 maxPdRaidLevel_10:12;
852
853 u16 minPdRaidLevel_50:4;
854 u16 maxPdRaidLevel_50:12;
855
856 u16 minPdRaidLevel_60:4;
857 u16 maxPdRaidLevel_60:12;
858
859 u16 minPdRaidLevel_1E_RLQ0:4;
860 u16 maxPdRaidLevel_1E_RLQ0:12;
861
862 u16 minPdRaidLevel_1E0_RLQ0:4;
863 u16 maxPdRaidLevel_1E0_RLQ0:12;
864
865 u16 reserved[6];
866 } pdsForRaidLevels;
867
9ab9ed38
CH		 868 __le16 maxPds; /*780h */
869 __le16 maxDedHSPs; /*782h */
870 __le16 maxGlobalHSP; /*784h */
871 __le16 ddfSize; /*786h */
bc93d425
SS		 872 u8 maxLdsPerArray; /*788h */
873 u8 partitionsInDDF; /*789h */
874 u8 lockKeyBinding; /*78ah */
875 u8 maxPITsPerLd; /*78bh */
876 u8 maxViewsPerLd; /*78ch */
877 u8 maxTargetId; /*78dh */
9ab9ed38 878 __le16 maxBvlVdSize; /*78eh */
bc93d425 879
9ab9ed38
CH		 880 __le16 maxConfigurableSSCSize; /*790h */
881 __le16 currentSSCsize; /*792h */
bc93d425
SS		 882
883 char expanderFwVersion[12]; /*794h */
884
9ab9ed38 885 __le16 PFKTrialTimeRemaining; /*7A0h */
bc93d425 886
9ab9ed38 887 __le16 cacheMemorySize; /*7A2h */
bc93d425
SS		 888
889 struct { /*7A4h */
94cd65dd 890#if defined(__BIG_ENDIAN_BITFIELD)
229fe47c
AR		 891 u32 reserved:5;
892 u32 activePassive:2;
893 u32 supportConfigAutoBalance:1;
894 u32 mpio:1;
895 u32 supportDataLDonSSCArray:1;
896 u32 supportPointInTimeProgress:1;
94cd65dd
SS		 897 u32 supportUnevenSpans:1;
898 u32 dedicatedHotSparesLimited:1;
899 u32 headlessMode:1;
900 u32 supportEmulatedDrives:1;
901 u32 supportResetNow:1;
902 u32 realTimeScheduler:1;
903 u32 supportSSDPatrolRead:1;
904 u32 supportPerfTuning:1;
905 u32 disableOnlinePFKChange:1;
906 u32 supportJBOD:1;
907 u32 supportBootTimePFKChange:1;
908 u32 supportSetLinkSpeed:1;
909 u32 supportEmergencySpares:1;
910 u32 supportSuspendResumeBGops:1;
911 u32 blockSSDWriteCacheChange:1;
912 u32 supportShieldState:1;
913 u32 supportLdBBMInfo:1;
914 u32 supportLdPIType3:1;
915 u32 supportLdPIType2:1;
916 u32 supportLdPIType1:1;
917 u32 supportPIcontroller:1;
918#else
bc93d425
SS		 919 u32 supportPIcontroller:1;
920 u32 supportLdPIType1:1;
921 u32 supportLdPIType2:1;
922 u32 supportLdPIType3:1;
923 u32 supportLdBBMInfo:1;
924 u32 supportShieldState:1;
925 u32 blockSSDWriteCacheChange:1;
926 u32 supportSuspendResumeBGops:1;
927 u32 supportEmergencySpares:1;
928 u32 supportSetLinkSpeed:1;
929 u32 supportBootTimePFKChange:1;
930 u32 supportJBOD:1;
931 u32 disableOnlinePFKChange:1;
932 u32 supportPerfTuning:1;
933 u32 supportSSDPatrolRead:1;
934 u32 realTimeScheduler:1;
935
936 u32 supportResetNow:1;
937 u32 supportEmulatedDrives:1;
938 u32 headlessMode:1;
939 u32 dedicatedHotSparesLimited:1;
940
941
942 u32 supportUnevenSpans:1;
229fe47c
AR		 943 u32 supportPointInTimeProgress:1;
944 u32 supportDataLDonSSCArray:1;
945 u32 mpio:1;
946 u32 supportConfigAutoBalance:1;
947 u32 activePassive:2;
948 u32 reserved:5;
94cd65dd 949#endif
bc93d425
SS		 950 } adapterOperations2;
951
952 u8 driverVersion[32]; /*7A8h */
953 u8 maxDAPdCountSpinup60; /*7C8h */
954 u8 temperatureROC; /*7C9h */
955 u8 temperatureCtrl; /*7CAh */
956 u8 reserved4; /*7CBh */
9ab9ed38 957 __le16 maxConfigurablePds; /*7CCh */
bc93d425
SS		 958
959
960 u8 reserved5[2]; /*0x7CDh */
961
962 /*
963 * HA cluster information
964 */
965 struct {
51087a86
SS		 966#if defined(__BIG_ENDIAN_BITFIELD)
967 u32 reserved:26;
968 u32 premiumFeatureMismatch:1;
969 u32 ctrlPropIncompatible:1;
970 u32 fwVersionMismatch:1;
971 u32 hwIncompatible:1;
972 u32 peerIsIncompatible:1;
973 u32 peerIsPresent:1;
974#else
bc93d425
SS		 975 u32 peerIsPresent:1;
976 u32 peerIsIncompatible:1;
977 u32 hwIncompatible:1;
978 u32 fwVersionMismatch:1;
979 u32 ctrlPropIncompatible:1;
980 u32 premiumFeatureMismatch:1;
981 u32 reserved:26;
51087a86 982#endif
bc93d425
SS		 983 } cluster;
984
985 char clusterId[16]; /*7D4h */
229fe47c
AR		 986 struct {
987 u8 maxVFsSupported; /*0x7E4*/
988 u8 numVFsEnabled; /*0x7E5*/
989 u8 requestorId; /*0x7E6 0:PF, 1:VF1, 2:VF2*/
990 u8 reserved; /*0x7E7*/
991 } iov;
bc93d425 992
fc62b3fc
SS		 993 struct {
994#if defined(__BIG_ENDIAN_BITFIELD)
3761cb4c 995 u32 reserved:7;
996 u32 useSeqNumJbodFP:1;
0be3f4c9 997 u32 supportExtendedSSCSize:1;
998 u32 supportDiskCacheSettingForSysPDs:1;
999 u32 supportCPLDUpdate:1;
1000 u32 supportTTYLogCompression:1;
7497cde8
SS		 1001 u32 discardCacheDuringLDDelete:1;
1002 u32 supportSecurityonJBOD:1;
1003 u32 supportCacheBypassModes:1;
1004 u32 supportDisableSESMonitoring:1;
1005 u32 supportForceFlash:1;
1006 u32 supportNVDRAM:1;
1007 u32 supportDrvActivityLEDSetting:1;
1008 u32 supportAllowedOpsforDrvRemoval:1;
1009 u32 supportHOQRebuild:1;
1010 u32 supportForceTo512e:1;
1011 u32 supportNVCacheErase:1;
1012 u32 supportDebugQueue:1;
1013 u32 supportSwZone:1;
fc62b3fc 1014 u32 supportCrashDump:1;
51087a86
SS		 1015 u32 supportMaxExtLDs:1;
1016 u32 supportT10RebuildAssist:1;
1017 u32 supportDisableImmediateIO:1;
1018 u32 supportThermalPollInterval:1;
1019 u32 supportPersonalityChange:2;
fc62b3fc 1020#else
51087a86
SS		 1021 u32 supportPersonalityChange:2;
1022 u32 supportThermalPollInterval:1;
1023 u32 supportDisableImmediateIO:1;
1024 u32 supportT10RebuildAssist:1;
7497cde8
SS		 1025 u32 supportMaxExtLDs:1;
1026 u32 supportCrashDump:1;
1027 u32 supportSwZone:1;
1028 u32 supportDebugQueue:1;
1029 u32 supportNVCacheErase:1;
1030 u32 supportForceTo512e:1;
1031 u32 supportHOQRebuild:1;
1032 u32 supportAllowedOpsforDrvRemoval:1;
1033 u32 supportDrvActivityLEDSetting:1;
1034 u32 supportNVDRAM:1;
1035 u32 supportForceFlash:1;
1036 u32 supportDisableSESMonitoring:1;
1037 u32 supportCacheBypassModes:1;
1038 u32 supportSecurityonJBOD:1;
1039 u32 discardCacheDuringLDDelete:1;
0be3f4c9 1040 u32 supportTTYLogCompression:1;
1041 u32 supportCPLDUpdate:1;
1042 u32 supportDiskCacheSettingForSysPDs:1;
1043 u32 supportExtendedSSCSize:1;
3761cb4c 1044 u32 useSeqNumJbodFP:1;
1045 u32 reserved:7;
fc62b3fc
SS		 1046#endif
1047 } adapterOperations3;
1048
1049 u8 pad[0x800-0x7EC];
81e403ce 1050} __packed;
c4a3e0a5
BS		 1051
1052/*
1053 * ===============================
1054 * MegaRAID SAS driver definitions
1055 * ===============================
1056 */
1057#define MEGASAS_MAX_PD_CHANNELS 2
51087a86 1058#define MEGASAS_MAX_LD_CHANNELS 2
c4a3e0a5
BS		 1059#define MEGASAS_MAX_CHANNELS (MEGASAS_MAX_PD_CHANNELS + \
1060 MEGASAS_MAX_LD_CHANNELS)
1061#define MEGASAS_MAX_DEV_PER_CHANNEL 128
1062#define MEGASAS_DEFAULT_INIT_ID -1
1063#define MEGASAS_MAX_LUN 8
6bf579a3 1064#define MEGASAS_DEFAULT_CMD_PER_LUN 256
81e403ce
YB		 1065#define MEGASAS_MAX_PD (MEGASAS_MAX_PD_CHANNELS * \
1066 MEGASAS_MAX_DEV_PER_CHANNEL)
bdc6fb8d
YB		 1067#define MEGASAS_MAX_LD_IDS (MEGASAS_MAX_LD_CHANNELS * \
1068 MEGASAS_MAX_DEV_PER_CHANNEL)
c4a3e0a5 1069
1fd10685 1070#define MEGASAS_MAX_SECTORS (2*1024)
42a8d2b3 1071#define MEGASAS_MAX_SECTORS_IEEE (2*128)
658dcedb
SP		 1072#define MEGASAS_DBG_LVL 1
1073
05e9ebbe
SP		 1074#define MEGASAS_FW_BUSY 1
1075
51087a86
SS		 1076#define VD_EXT_DEBUG 0
1077
90dc9d98 1078
7497cde8
SS		 1079enum MR_SCSI_CMD_TYPE {
1080 READ_WRITE_LDIO = 0,
1081 NON_READ_WRITE_LDIO = 1,
1082 READ_WRITE_SYSPDIO = 2,
1083 NON_READ_WRITE_SYSPDIO = 3,
1084};
1085
d532dbe2 1086/* Frame Type */
1087#define IO_FRAME 0
1088#define PTHRU_FRAME 1
1089
c4a3e0a5
BS		 1090/*
1091 * When SCSI mid-layer calls driver's reset routine, driver waits for
1092 * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note
1093 * that the driver cannot _actually_ abort or reset pending commands. While
1094 * it is waiting for the commands to complete, it prints a diagnostic message
1095 * every MEGASAS_RESET_NOTICE_INTERVAL seconds
1096 */
1097#define MEGASAS_RESET_WAIT_TIME 180
2a3681e5 1098#define MEGASAS_INTERNAL_CMD_WAIT_TIME 180
c4a3e0a5 1099#define MEGASAS_RESET_NOTICE_INTERVAL 5
c4a3e0a5 1100#define MEGASAS_IOCTL_CMD 0
05e9ebbe 1101#define MEGASAS_DEFAULT_CMD_TIMEOUT 90
c5daa6a9 1102#define MEGASAS_THROTTLE_QUEUE_DEPTH 16
90dc9d98 1103#define MEGASAS_BLOCKED_CMD_TIMEOUT 60
c4a3e0a5
BS		 1104/*
1105 * FW reports the maximum of number of commands that it can accept (maximum
1106 * commands that can be outstanding) at any time. The driver must report a
1107 * lower number to the mid layer because it can issue a few internal commands
1108 * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs
1109 * is shown below
1110 */
1111#define MEGASAS_INT_CMDS 32
7bebf5c7 1112#define MEGASAS_SKINNY_INT_CMDS 5
ae09a6c1
SS		 1113#define MEGASAS_FUSION_INTERNAL_CMDS 5
1114#define MEGASAS_FUSION_IOCTL_CMDS 3
f26ac3a1 1115#define MEGASAS_MFI_IOCTL_CMDS 27
c4a3e0a5 1116
d46a3ad6 1117#define MEGASAS_MAX_MSIX_QUEUES 128
c4a3e0a5
BS		 1118/*
1119 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
1120 * SGLs based on the size of dma_addr_t
1121 */
1122#define IS_DMA64 (sizeof(dma_addr_t) == 8)
1123
39a98554 1124#define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001
1125
1126#define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001
1127#define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002
1128#define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004
1129
c4a3e0a5 1130#define MFI_OB_INTR_STATUS_MASK 0x00000002
14faea9f 1131#define MFI_POLL_TIMEOUT_SECS 60
229fe47c
AR		 1132#define MEGASAS_SRIOV_HEARTBEAT_INTERVAL_VF (5 * HZ)
1133#define MEGASAS_OCR_SETTLE_TIME_VF (1000 * 30)
1134#define MEGASAS_ROUTINE_WAIT_TIME_VF 300
f9876f0b 1135#define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000
6610a6b3
YB		 1136#define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001
1137#define MFI_GEN2_ENABLE_INTERRUPT_MASK (0x00000001 | 0x00000004)
87911122
YB		 1138#define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000
1139#define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001)
0e98936c 1140
39a98554 1141#define MFI_1068_PCSR_OFFSET 0x84
1142#define MFI_1068_FW_HANDSHAKE_OFFSET 0x64
1143#define MFI_1068_FW_READY 0xDDDD0000
d46a3ad6
SS		 1144
1145#define MR_MAX_REPLY_QUEUES_OFFSET 0X0000001F
1146#define MR_MAX_REPLY_QUEUES_EXT_OFFSET 0X003FC000
1147#define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT 14
1148#define MR_MAX_MSIX_REG_ARRAY 16
0e98936c
SP		 1149/*
1150* register set for both 1068 and 1078 controllers
1151* structure extended for 1078 registers
1152*/
f9876f0b 1153
c4a3e0a5 1154struct megasas_register_set {
9c915a8c
AR		 1155 u32 doorbell; /*0000h*/
1156 u32 fusion_seq_offset; /*0004h*/
1157 u32 fusion_host_diag; /*0008h*/
1158 u32 reserved_01; /*000Ch*/
c4a3e0a5 1159
f9876f0b
SP		 1160 u32 inbound_msg_0; /*0010h*/
1161 u32 inbound_msg_1; /*0014h*/
1162 u32 outbound_msg_0; /*0018h*/
1163 u32 outbound_msg_1; /*001Ch*/
c4a3e0a5 1164
f9876f0b
SP		 1165 u32 inbound_doorbell; /*0020h*/
1166 u32 inbound_intr_status; /*0024h*/
1167 u32 inbound_intr_mask; /*0028h*/
c4a3e0a5 1168
f9876f0b
SP		 1169 u32 outbound_doorbell; /*002Ch*/
1170 u32 outbound_intr_status; /*0030h*/
1171 u32 outbound_intr_mask; /*0034h*/
c4a3e0a5 1172
f9876f0b 1173 u32 reserved_1[2]; /*0038h*/
c4a3e0a5 1174
f9876f0b
SP		 1175 u32 inbound_queue_port; /*0040h*/
1176 u32 outbound_queue_port; /*0044h*/
c4a3e0a5 1177
9c915a8c
AR		 1178 u32 reserved_2[9]; /*0048h*/
1179 u32 reply_post_host_index; /*006Ch*/
1180 u32 reserved_2_2[12]; /*0070h*/
c4a3e0a5 1181
f9876f0b 1182 u32 outbound_doorbell_clear; /*00A0h*/
c4a3e0a5 1183
f9876f0b
SP		 1184 u32 reserved_3[3]; /*00A4h*/
1185
1186 u32 outbound_scratch_pad ; /*00B0h*/
9c915a8c 1187 u32 outbound_scratch_pad_2; /*00B4h*/
f9876f0b 1188
9c915a8c 1189 u32 reserved_4[2]; /*00B8h*/
f9876f0b
SP		 1190
1191 u32 inbound_low_queue_port ; /*00C0h*/
1192
1193 u32 inbound_high_queue_port ; /*00C4h*/
1194
1195 u32 reserved_5; /*00C8h*/
39a98554 1196 u32 res_6[11]; /*CCh*/
1197 u32 host_diag;
1198 u32 seq_offset;
1199 u32 index_registers[807]; /*00CCh*/
c4a3e0a5
BS		 1200} __attribute__ ((packed));
1201
1202struct megasas_sge32 {
1203
9ab9ed38
CH		 1204 __le32 phys_addr;
1205 __le32 length;
c4a3e0a5
BS		 1206
1207} __attribute__ ((packed));
1208
1209struct megasas_sge64 {
1210
9ab9ed38
CH		 1211 __le64 phys_addr;
1212 __le32 length;
c4a3e0a5
BS		 1213
1214} __attribute__ ((packed));
1215
f4c9a131 1216struct megasas_sge_skinny {
9ab9ed38
CH		 1217 __le64 phys_addr;
1218 __le32 length;
1219 __le32 flag;
f4c9a131
YB		 1220} __packed;
1221
c4a3e0a5
BS		 1222union megasas_sgl {
1223
1224 struct megasas_sge32 sge32[1];
1225 struct megasas_sge64 sge64[1];
f4c9a131 1226 struct megasas_sge_skinny sge_skinny[1];
c4a3e0a5
BS		 1227
1228} __attribute__ ((packed));
1229
1230struct megasas_header {
1231
1232 u8 cmd; /*00h */
1233 u8 sense_len; /*01h */
1234 u8 cmd_status; /*02h */
1235 u8 scsi_status; /*03h */
1236
1237 u8 target_id; /*04h */
1238 u8 lun; /*05h */
1239 u8 cdb_len; /*06h */
1240 u8 sge_count; /*07h */
1241
9ab9ed38
CH		 1242 __le32 context; /*08h */
1243 __le32 pad_0; /*0Ch */
c4a3e0a5 1244
9ab9ed38
CH		 1245 __le16 flags; /*10h */
1246 __le16 timeout; /*12h */
1247 __le32 data_xferlen; /*14h */
c4a3e0a5
BS		 1248
1249} __attribute__ ((packed));
1250
1251union megasas_sgl_frame {
1252
1253 struct megasas_sge32 sge32[8];
1254 struct megasas_sge64 sge64[5];
1255
1256} __attribute__ ((packed));
1257
d46a3ad6
SS		 1258typedef union _MFI_CAPABILITIES {
1259 struct {
94cd65dd 1260#if defined(__BIG_ENDIAN_BITFIELD)
bd5f9484 1261 u32 reserved:23;
1262 u32 support_ext_io_size:1;
0be3f4c9 1263 u32 support_ext_queue_depth:1;
7497cde8
SS		 1264 u32 security_protocol_cmds_fw:1;
1265 u32 support_core_affinity:1;
d2552ebe 1266 u32 support_ndrive_r1_lb:1;
51087a86 1267 u32 support_max_255lds:1;
7497cde8 1268 u32 support_fastpath_wb:1;
94cd65dd
SS		 1269 u32 support_additional_msix:1;
1270 u32 support_fp_remote_lun:1;
1271#else
d46a3ad6
SS		 1272 u32 support_fp_remote_lun:1;
1273 u32 support_additional_msix:1;
7497cde8 1274 u32 support_fastpath_wb:1;
51087a86 1275 u32 support_max_255lds:1;
d2552ebe 1276 u32 support_ndrive_r1_lb:1;
7497cde8
SS		 1277 u32 support_core_affinity:1;
1278 u32 security_protocol_cmds_fw:1;
0be3f4c9 1279 u32 support_ext_queue_depth:1;
bd5f9484 1280 u32 support_ext_io_size:1;
1281 u32 reserved:23;
94cd65dd 1282#endif
d46a3ad6 1283 } mfi_capabilities;
9ab9ed38 1284 __le32 reg;
d46a3ad6
SS		 1285} MFI_CAPABILITIES;
1286
c4a3e0a5
BS		 1287struct megasas_init_frame {
1288
1289 u8 cmd; /*00h */
1290 u8 reserved_0; /*01h */
1291 u8 cmd_status; /*02h */
1292
1293 u8 reserved_1; /*03h */
d46a3ad6 1294 MFI_CAPABILITIES driver_operations; /*04h*/
c4a3e0a5 1295
9ab9ed38
CH		 1296 __le32 context; /*08h */
1297 __le32 pad_0; /*0Ch */
c4a3e0a5 1298
9ab9ed38
CH		 1299 __le16 flags; /*10h */
1300 __le16 reserved_3; /*12h */
1301 __le32 data_xfer_len; /*14h */
c4a3e0a5 1302
9ab9ed38
CH		 1303 __le32 queue_info_new_phys_addr_lo; /*18h */
1304 __le32 queue_info_new_phys_addr_hi; /*1Ch */
1305 __le32 queue_info_old_phys_addr_lo; /*20h */
1306 __le32 queue_info_old_phys_addr_hi; /*24h */
1307 __le32 reserved_4[2]; /*28h */
1308 __le32 system_info_lo; /*30h */
1309 __le32 system_info_hi; /*34h */
1310 __le32 reserved_5[2]; /*38h */
c4a3e0a5
BS		 1311
1312} __attribute__ ((packed));
1313
1314struct megasas_init_queue_info {
1315
9ab9ed38
CH		 1316 __le32 init_flags; /*00h */
1317 __le32 reply_queue_entries; /*04h */
c4a3e0a5 1318
9ab9ed38
CH		 1319 __le32 reply_queue_start_phys_addr_lo; /*08h */
1320 __le32 reply_queue_start_phys_addr_hi; /*0Ch */
1321 __le32 producer_index_phys_addr_lo; /*10h */
1322 __le32 producer_index_phys_addr_hi; /*14h */
1323 __le32 consumer_index_phys_addr_lo; /*18h */
1324 __le32 consumer_index_phys_addr_hi; /*1Ch */
c4a3e0a5
BS		 1325
1326} __attribute__ ((packed));
1327
1328struct megasas_io_frame {
1329
1330 u8 cmd; /*00h */
1331 u8 sense_len; /*01h */
1332 u8 cmd_status; /*02h */
1333 u8 scsi_status; /*03h */
1334
1335 u8 target_id; /*04h */
1336 u8 access_byte; /*05h */
1337 u8 reserved_0; /*06h */
1338 u8 sge_count; /*07h */
1339
9ab9ed38
CH		 1340 __le32 context; /*08h */
1341 __le32 pad_0; /*0Ch */
c4a3e0a5 1342
9ab9ed38
CH		 1343 __le16 flags; /*10h */
1344 __le16 timeout; /*12h */
1345 __le32 lba_count; /*14h */
c4a3e0a5 1346
9ab9ed38
CH		 1347 __le32 sense_buf_phys_addr_lo; /*18h */
1348 __le32 sense_buf_phys_addr_hi; /*1Ch */
c4a3e0a5 1349
9ab9ed38
CH		 1350 __le32 start_lba_lo; /*20h */
1351 __le32 start_lba_hi; /*24h */
c4a3e0a5
BS		 1352
1353 union megasas_sgl sgl; /*28h */
1354
1355} __attribute__ ((packed));
1356
1357struct megasas_pthru_frame {
1358
1359 u8 cmd; /*00h */
1360 u8 sense_len; /*01h */
1361 u8 cmd_status; /*02h */
1362 u8 scsi_status; /*03h */
1363
1364 u8 target_id; /*04h */
1365 u8 lun; /*05h */
1366 u8 cdb_len; /*06h */
1367 u8 sge_count; /*07h */
1368
9ab9ed38
CH		 1369 __le32 context; /*08h */
1370 __le32 pad_0; /*0Ch */
c4a3e0a5 1371
9ab9ed38
CH		 1372 __le16 flags; /*10h */
1373 __le16 timeout; /*12h */
1374 __le32 data_xfer_len; /*14h */
c4a3e0a5 1375
9ab9ed38
CH		 1376 __le32 sense_buf_phys_addr_lo; /*18h */
1377 __le32 sense_buf_phys_addr_hi; /*1Ch */
c4a3e0a5
BS		 1378
1379 u8 cdb[16]; /*20h */
1380 union megasas_sgl sgl; /*30h */
1381
1382} __attribute__ ((packed));
1383
1384struct megasas_dcmd_frame {
1385
1386 u8 cmd; /*00h */
1387 u8 reserved_0; /*01h */
1388 u8 cmd_status; /*02h */
1389 u8 reserved_1[4]; /*03h */
1390 u8 sge_count; /*07h */
1391
9ab9ed38
CH		 1392 __le32 context; /*08h */
1393 __le32 pad_0; /*0Ch */
c4a3e0a5 1394
9ab9ed38
CH		 1395 __le16 flags; /*10h */
1396 __le16 timeout; /*12h */
c4a3e0a5 1397
9ab9ed38
CH		 1398 __le32 data_xfer_len; /*14h */
1399 __le32 opcode; /*18h */
c4a3e0a5
BS		 1400
1401 union { /*1Ch */
1402 u8 b[12];
9ab9ed38
CH		 1403 __le16 s[6];
1404 __le32 w[3];
c4a3e0a5
BS		 1405 } mbox;
1406
1407 union megasas_sgl sgl; /*28h */
1408
1409} __attribute__ ((packed));
1410
1411struct megasas_abort_frame {
1412
1413 u8 cmd; /*00h */
1414 u8 reserved_0; /*01h */
1415 u8 cmd_status; /*02h */
1416
1417 u8 reserved_1; /*03h */
9ab9ed38 1418 __le32 reserved_2; /*04h */
c4a3e0a5 1419
9ab9ed38
CH		 1420 __le32 context; /*08h */
1421 __le32 pad_0; /*0Ch */
c4a3e0a5 1422
9ab9ed38
CH		 1423 __le16 flags; /*10h */
1424 __le16 reserved_3; /*12h */
1425 __le32 reserved_4; /*14h */
c4a3e0a5 1426
9ab9ed38
CH		 1427 __le32 abort_context; /*18h */
1428 __le32 pad_1; /*1Ch */
c4a3e0a5 1429
9ab9ed38
CH		 1430 __le32 abort_mfi_phys_addr_lo; /*20h */
1431 __le32 abort_mfi_phys_addr_hi; /*24h */
c4a3e0a5 1432
9ab9ed38 1433 __le32 reserved_5[6]; /*28h */
c4a3e0a5
BS		 1434
1435} __attribute__ ((packed));
1436
1437struct megasas_smp_frame {
1438
1439 u8 cmd; /*00h */
1440 u8 reserved_1; /*01h */
1441 u8 cmd_status; /*02h */
1442 u8 connection_status; /*03h */
1443
1444 u8 reserved_2[3]; /*04h */
1445 u8 sge_count; /*07h */
1446
9ab9ed38
CH		 1447 __le32 context; /*08h */
1448 __le32 pad_0; /*0Ch */
c4a3e0a5 1449
9ab9ed38
CH		 1450 __le16 flags; /*10h */
1451 __le16 timeout; /*12h */
c4a3e0a5 1452
9ab9ed38
CH		 1453 __le32 data_xfer_len; /*14h */
1454 __le64 sas_addr; /*18h */
c4a3e0a5
BS		 1455
1456 union {
1457 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: req */
1458 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: req */
1459 } sgl;
1460
1461} __attribute__ ((packed));
1462
1463struct megasas_stp_frame {
1464
1465 u8 cmd; /*00h */
1466 u8 reserved_1; /*01h */
1467 u8 cmd_status; /*02h */
1468 u8 reserved_2; /*03h */
1469
1470 u8 target_id; /*04h */
1471 u8 reserved_3[2]; /*05h */
1472 u8 sge_count; /*07h */
1473
9ab9ed38
CH		 1474 __le32 context; /*08h */
1475 __le32 pad_0; /*0Ch */
c4a3e0a5 1476
9ab9ed38
CH		 1477 __le16 flags; /*10h */
1478 __le16 timeout; /*12h */
c4a3e0a5 1479
9ab9ed38 1480 __le32 data_xfer_len; /*14h */
c4a3e0a5 1481
9ab9ed38
CH		 1482 __le16 fis[10]; /*18h */
1483 __le32 stp_flags;
c4a3e0a5
BS		 1484
1485 union {
1486 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: data */
1487 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: data */
1488 } sgl;
1489
1490} __attribute__ ((packed));
1491
1492union megasas_frame {
1493
1494 struct megasas_header hdr;
1495 struct megasas_init_frame init;
1496 struct megasas_io_frame io;
1497 struct megasas_pthru_frame pthru;
1498 struct megasas_dcmd_frame dcmd;
1499 struct megasas_abort_frame abort;
1500 struct megasas_smp_frame smp;
1501 struct megasas_stp_frame stp;
1502
1503 u8 raw_bytes[64];
1504};
1505
1506struct megasas_cmd;
1507
1508union megasas_evt_class_locale {
1509
1510 struct {
be26374b 1511#ifndef __BIG_ENDIAN_BITFIELD
c4a3e0a5
BS		 1512 u16 locale;
1513 u8 reserved;
1514 s8 class;
be26374b
SS		 1515#else
1516 s8 class;
1517 u8 reserved;
1518 u16 locale;
1519#endif
c4a3e0a5
BS		 1520 } __attribute__ ((packed)) members;
1521
1522 u32 word;
1523
1524} __attribute__ ((packed));
1525
1526struct megasas_evt_log_info {
9ab9ed38
CH		 1527 __le32 newest_seq_num;
1528 __le32 oldest_seq_num;
1529 __le32 clear_seq_num;
1530 __le32 shutdown_seq_num;
1531 __le32 boot_seq_num;
c4a3e0a5
BS		 1532
1533} __attribute__ ((packed));
1534
1535struct megasas_progress {
1536
9ab9ed38
CH		 1537 __le16 progress;
1538 __le16 elapsed_seconds;
c4a3e0a5
BS		 1539
1540} __attribute__ ((packed));
1541
1542struct megasas_evtarg_ld {
1543
1544 u16 target_id;
1545 u8 ld_index;
1546 u8 reserved;
1547
1548} __attribute__ ((packed));
1549
1550struct megasas_evtarg_pd {
1551 u16 device_id;
1552 u8 encl_index;
1553 u8 slot_number;
1554
1555} __attribute__ ((packed));
1556
1557struct megasas_evt_detail {
1558
9ab9ed38
CH		 1559 __le32 seq_num;
1560 __le32 time_stamp;
1561 __le32 code;
c4a3e0a5
BS		 1562 union megasas_evt_class_locale cl;
1563 u8 arg_type;
1564 u8 reserved1[15];
1565
1566 union {
1567 struct {
1568 struct megasas_evtarg_pd pd;
1569 u8 cdb_length;
1570 u8 sense_length;
1571 u8 reserved[2];
1572 u8 cdb[16];
1573 u8 sense[64];
1574 } __attribute__ ((packed)) cdbSense;
1575
1576 struct megasas_evtarg_ld ld;
1577
1578 struct {
1579 struct megasas_evtarg_ld ld;
9ab9ed38 1580 __le64 count;
c4a3e0a5
BS		 1581 } __attribute__ ((packed)) ld_count;
1582
1583 struct {
9ab9ed38 1584 __le64 lba;
c4a3e0a5
BS		 1585 struct megasas_evtarg_ld ld;
1586 } __attribute__ ((packed)) ld_lba;
1587
1588 struct {
1589 struct megasas_evtarg_ld ld;
9ab9ed38
CH		 1590 __le32 prevOwner;
1591 __le32 newOwner;
c4a3e0a5
BS		 1592 } __attribute__ ((packed)) ld_owner;
1593
1594 struct {
1595 u64 ld_lba;
1596 u64 pd_lba;
1597 struct megasas_evtarg_ld ld;
1598 struct megasas_evtarg_pd pd;
1599 } __attribute__ ((packed)) ld_lba_pd_lba;
1600
1601 struct {
1602 struct megasas_evtarg_ld ld;
1603 struct megasas_progress prog;
1604 } __attribute__ ((packed)) ld_prog;
1605
1606 struct {
1607 struct megasas_evtarg_ld ld;
1608 u32 prev_state;
1609 u32 new_state;
1610 } __attribute__ ((packed)) ld_state;
1611
1612 struct {
1613 u64 strip;
1614 struct megasas_evtarg_ld ld;
1615 } __attribute__ ((packed)) ld_strip;
1616
1617 struct megasas_evtarg_pd pd;
1618
1619 struct {
1620 struct megasas_evtarg_pd pd;
1621 u32 err;
1622 } __attribute__ ((packed)) pd_err;
1623
1624 struct {
1625 u64 lba;
1626 struct megasas_evtarg_pd pd;
1627 } __attribute__ ((packed)) pd_lba;
1628
1629 struct {
1630 u64 lba;
1631 struct megasas_evtarg_pd pd;
1632 struct megasas_evtarg_ld ld;
1633 } __attribute__ ((packed)) pd_lba_ld;
1634
1635 struct {
1636 struct megasas_evtarg_pd pd;
1637 struct megasas_progress prog;
1638 } __attribute__ ((packed)) pd_prog;
1639
1640 struct {
1641 struct megasas_evtarg_pd pd;
1642 u32 prevState;
1643 u32 newState;
1644 } __attribute__ ((packed)) pd_state;
1645
1646 struct {
1647 u16 vendorId;
9ab9ed38 1648 __le16 deviceId;
c4a3e0a5
BS		 1649 u16 subVendorId;
1650 u16 subDeviceId;
1651 } __attribute__ ((packed)) pci;
1652
1653 u32 rate;
1654 char str[96];
1655
1656 struct {
1657 u32 rtc;
1658 u32 elapsedSeconds;
1659 } __attribute__ ((packed)) time;
1660
1661 struct {
1662 u32 ecar;
1663 u32 elog;
1664 char str[64];
1665 } __attribute__ ((packed)) ecc;
1666
1667 u8 b[96];
9ab9ed38
CH		 1668 __le16 s[48];
1669 __le32 w[24];
1670 __le64 d[12];
c4a3e0a5
BS		 1671 } args;
1672
1673 char description[128];
1674
1675} __attribute__ ((packed));
1676
7e8a75f4 1677struct megasas_aen_event {
c1d390d8 1678 struct delayed_work hotplug_work;
7e8a75f4
YB		 1679 struct megasas_instance *instance;
1680};
1681
c8e858fe
AR		 1682struct megasas_irq_context {
1683 struct megasas_instance *instance;
1684 u32 MSIxIndex;
1685};
1686
5765c5b8
SS		 1687struct MR_DRV_SYSTEM_INFO {
1688 u8 infoVersion;
1689 u8 systemIdLength;
1690 u16 reserved0;
1691 u8 systemId[64];
1692 u8 reserved[1980];
1693};
1694
c4a3e0a5
BS		 1695struct megasas_instance {
1696
9ab9ed38 1697 __le32 *producer;
c4a3e0a5 1698 dma_addr_t producer_h;
9ab9ed38 1699 __le32 *consumer;
c4a3e0a5 1700 dma_addr_t consumer_h;
5765c5b8
SS		 1701 struct MR_DRV_SYSTEM_INFO *system_info_buf;
1702 dma_addr_t system_info_h;
229fe47c
AR		 1703 struct MR_LD_VF_AFFILIATION *vf_affiliation;
1704 dma_addr_t vf_affiliation_h;
1705 struct MR_LD_VF_AFFILIATION_111 *vf_affiliation_111;
1706 dma_addr_t vf_affiliation_111_h;
1707 struct MR_CTRL_HB_HOST_MEM *hb_host_mem;
1708 dma_addr_t hb_host_mem_h;
c4a3e0a5 1709
9ab9ed38 1710 __le32 *reply_queue;
c4a3e0a5
BS		 1711 dma_addr_t reply_queue_h;
1712
fc62b3fc
SS		 1713 u32 *crash_dump_buf;
1714 dma_addr_t crash_dump_h;
1715 void *crash_buf[MAX_CRASH_DUMP_SIZE];
1716 u32 crash_buf_pages;
1717 unsigned int fw_crash_buffer_size;
1718 unsigned int fw_crash_state;
1719 unsigned int fw_crash_buffer_offset;
1720 u32 drv_buf_index;
1721 u32 drv_buf_alloc;
1722 u32 crash_dump_fw_support;
1723 u32 crash_dump_drv_support;
1724 u32 crash_dump_app_support;
7497cde8 1725 u32 secure_jbod_support;
3761cb4c 1726 bool use_seqnum_jbod_fp; /* Added for PD sequence */
fc62b3fc
SS		 1727 spinlock_t crashdump_lock;
1728
c4a3e0a5 1729 struct megasas_register_set __iomem *reg_set;
8a232bb3 1730 u32 __iomem *reply_post_host_index_addr[MR_MAX_MSIX_REG_ARRAY];
81e403ce 1731 struct megasas_pd_list pd_list[MEGASAS_MAX_PD];
999ece0a 1732 struct megasas_pd_list local_pd_list[MEGASAS_MAX_PD];
7497cde8 1733 u8 ld_ids[MEGASAS_MAX_LD_IDS];
c4a3e0a5 1734 s8 init_id;
c4a3e0a5
BS		 1735
1736 u16 max_num_sge;
1737 u16 max_fw_cmds;
9c915a8c 1738 u16 max_mfi_cmds;
ae09a6c1 1739 u16 max_scsi_cmds;
c4a3e0a5 1740 u32 max_sectors_per_req;
7e8a75f4 1741 struct megasas_aen_event *ev;
c4a3e0a5
BS		 1742
1743 struct megasas_cmd **cmd_list;
1744 struct list_head cmd_pool;
39a98554 1745 /* used to sync fire the cmd to fw */
90dc9d98 1746 spinlock_t mfi_pool_lock;
39a98554 1747 /* used to sync fire the cmd to fw */
1748 spinlock_t hba_lock;
7343eb65 1749 /* used to synch producer, consumer ptrs in dpc */
1750 spinlock_t completion_lock;
c4a3e0a5
BS		 1751 struct dma_pool *frame_dma_pool;
1752 struct dma_pool *sense_dma_pool;
1753
1754 struct megasas_evt_detail *evt_detail;
1755 dma_addr_t evt_detail_h;
1756 struct megasas_cmd *aen_cmd;
e5a69e27 1757 struct mutex aen_mutex;
c4a3e0a5
BS		 1758 struct semaphore ioctl_sem;
1759
1760 struct Scsi_Host *host;
1761
1762 wait_queue_head_t int_cmd_wait_q;
1763 wait_queue_head_t abort_cmd_wait_q;
1764
1765 struct pci_dev *pdev;
1766 u32 unique_id;
39a98554 1767 u32 fw_support_ieee;
c4a3e0a5 1768
e4a082c7 1769 atomic_t fw_outstanding;
39a98554 1770 atomic_t fw_reset_no_pci_access;
1341c939
SP		 1771
1772 struct megasas_instance_template *instancet;
5d018ad0 1773 struct tasklet_struct isr_tasklet;
39a98554 1774 struct work_struct work_init;
fc62b3fc 1775 struct work_struct crash_init;
05e9ebbe
SP		 1776
1777 u8 flag;
c3518837 1778 u8 unload;
f4c9a131 1779 u8 flag_ieee;
39a98554 1780 u8 issuepend_done;
1781 u8 disableOnlineCtrlReset;
bc93d425 1782 u8 UnevenSpanSupport;
51087a86
SS		 1783
1784 u8 supportmax256vd;
1785 u16 fw_supported_vd_count;
1786 u16 fw_supported_pd_count;
1787
1788 u16 drv_supported_vd_count;
1789 u16 drv_supported_pd_count;
1790
39a98554 1791 u8 adprecovery;
05e9ebbe 1792 unsigned long last_time;
39a98554 1793 u32 mfiStatus;
1794 u32 last_seq_num;
ad84db2e 1795
39a98554 1796 struct list_head internal_reset_pending_q;
80d9da98 1797
25985edc 1798 /* Ptr to hba specific information */
9c915a8c 1799 void *ctrl_context;
51087a86
SS		 1800 u32 ctrl_context_pages;
1801 struct megasas_ctrl_info *ctrl_info;
c8e858fe
AR		 1802 unsigned int msix_vectors;
1803 struct msix_entry msixentry[MEGASAS_MAX_MSIX_QUEUES];
1804 struct megasas_irq_context irq_context[MEGASAS_MAX_MSIX_QUEUES];
9c915a8c 1805 u64 map_id;
3761cb4c 1806 u64 pd_seq_map_id;
9c915a8c 1807 struct megasas_cmd *map_update_cmd;
3761cb4c 1808 struct megasas_cmd *jbod_seq_cmd;
b6d5d880 1809 unsigned long bar;
9c915a8c
AR		 1810 long reset_flags;
1811 struct mutex reset_mutex;
229fe47c
AR		 1812 struct timer_list sriov_heartbeat_timer;
1813 char skip_heartbeat_timer_del;
1814 u8 requestorId;
229fe47c
AR		 1815 char PlasmaFW111;
1816 char mpio;
ae09a6c1 1817 u16 throttlequeuedepth;
d46a3ad6 1818 u8 mask_interrupts;
bd5f9484 1819 u16 max_chain_frame_sz;
404a8a1a 1820 u8 is_imr;
5765c5b8 1821 bool dev_handle;
39a98554 1822};
229fe47c
AR		 1823struct MR_LD_VF_MAP {
1824 u32 size;
1825 union MR_LD_REF ref;
1826 u8 ldVfCount;
1827 u8 reserved[6];
1828 u8 policy[1];
1829};
1830
1831struct MR_LD_VF_AFFILIATION {
1832 u32 size;
1833 u8 ldCount;
1834 u8 vfCount;
1835 u8 thisVf;
1836 u8 reserved[9];
1837 struct MR_LD_VF_MAP map[1];
1838};
1839
1840/* Plasma 1.11 FW backward compatibility structures */
1841#define IOV_111_OFFSET 0x7CE
1842#define MAX_VIRTUAL_FUNCTIONS 8
4cbfea88 1843#define MR_LD_ACCESS_HIDDEN 15
229fe47c
AR		 1844
1845struct IOV_111 {
1846 u8 maxVFsSupported;
1847 u8 numVFsEnabled;
1848 u8 requestorId;
1849 u8 reserved[5];
1850};
1851
1852struct MR_LD_VF_MAP_111 {
1853 u8 targetId;
1854 u8 reserved[3];
1855 u8 policy[MAX_VIRTUAL_FUNCTIONS];
1856};
1857
1858struct MR_LD_VF_AFFILIATION_111 {
1859 u8 vdCount;
1860 u8 vfCount;
1861 u8 thisVf;
1862 u8 reserved[5];
1863 struct MR_LD_VF_MAP_111 map[MAX_LOGICAL_DRIVES];
1864};
1865
1866struct MR_CTRL_HB_HOST_MEM {
1867 struct {
1868 u32 fwCounter; /* Firmware heart beat counter */
1869 struct {
1870 u32 debugmode:1; /* 1=Firmware is in debug mode.
1871 Heart beat will not be updated. */
1872 u32 reserved:31;
1873 } debug;
1874 u32 reserved_fw[6];
1875 u32 driverCounter; /* Driver heart beat counter. 0x20 */
1876 u32 reserved_driver[7];
1877 } HB;
1878 u8 pad[0x400-0x40];
1879};
39a98554 1880
1881enum {
1882 MEGASAS_HBA_OPERATIONAL = 0,
1883 MEGASAS_ADPRESET_SM_INFAULT = 1,
1884 MEGASAS_ADPRESET_SM_FW_RESET_SUCCESS = 2,
1885 MEGASAS_ADPRESET_SM_OPERATIONAL = 3,
1886 MEGASAS_HW_CRITICAL_ERROR = 4,
229fe47c 1887 MEGASAS_ADPRESET_SM_POLLING = 5,
39a98554 1888 MEGASAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD,
c4a3e0a5
BS		 1889};
1890
0c79e681
YB		 1891struct megasas_instance_template {
1892 void (*fire_cmd)(struct megasas_instance *, dma_addr_t, \
1893 u32, struct megasas_register_set __iomem *);
1894
d46a3ad6
SS		 1895 void (*enable_intr)(struct megasas_instance *);
1896 void (*disable_intr)(struct megasas_instance *);
0c79e681
YB		 1897
1898 int (*clear_intr)(struct megasas_register_set __iomem *);
1899
1900 u32 (*read_fw_status_reg)(struct megasas_register_set __iomem *);
39a98554 1901 int (*adp_reset)(struct megasas_instance *, \
1902 struct megasas_register_set __iomem *);
1903 int (*check_reset)(struct megasas_instance *, \
1904 struct megasas_register_set __iomem *);
cd50ba8e
AR		 1905 irqreturn_t (*service_isr)(int irq, void *devp);
1906 void (*tasklet)(unsigned long);
1907 u32 (*init_adapter)(struct megasas_instance *);
1908 u32 (*build_and_issue_cmd) (struct megasas_instance *,
1909 struct scsi_cmnd *);
1910 void (*issue_dcmd) (struct megasas_instance *instance,
1911 struct megasas_cmd *cmd);
0c79e681
YB		 1912};
1913
c4a3e0a5
BS		 1914#define MEGASAS_IS_LOGICAL(scp) \
1915 (scp->device->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1
1916
4a5c814d
SS		 1917#define MEGASAS_DEV_INDEX(scp) \
1918 (((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + \
1919 scp->device->id)
1920
1921#define MEGASAS_PD_INDEX(scp) \
1922 ((scp->device->channel * MEGASAS_MAX_DEV_PER_CHANNEL) + \
1923 scp->device->id)
c4a3e0a5
BS		 1924
1925struct megasas_cmd {
1926
1927 union megasas_frame *frame;
1928 dma_addr_t frame_phys_addr;
1929 u8 *sense;
1930 dma_addr_t sense_phys_addr;
1931
1932 u32 index;
1933 u8 sync_cmd;
2be2a988 1934 u8 cmd_status_drv;
39a98554 1935 u8 abort_aen;
1936 u8 retry_for_fw_reset;
1937
c4a3e0a5
BS		 1938
1939 struct list_head list;
1940 struct scsi_cmnd *scmd;
4026e9aa 1941 u8 flags;
90dc9d98 1942
c4a3e0a5 1943 struct megasas_instance *instance;
9c915a8c
AR		 1944 union {
1945 struct {
1946 u16 smid;
1947 u16 resvd;
1948 } context;
1949 u32 frame_count;
1950 };
c4a3e0a5
BS		 1951};
1952
1953#define MAX_MGMT_ADAPTERS 1024
1954#define MAX_IOCTL_SGE 16
1955
1956struct megasas_iocpacket {
1957
1958 u16 host_no;
1959 u16 __pad1;
1960 u32 sgl_off;
1961 u32 sge_count;
1962 u32 sense_off;
1963 u32 sense_len;
1964 union {
1965 u8 raw[128];
1966 struct megasas_header hdr;
1967 } frame;
1968
1969 struct iovec sgl[MAX_IOCTL_SGE];
1970
1971} __attribute__ ((packed));
1972
1973struct megasas_aen {
1974 u16 host_no;
1975 u16 __pad1;
1976 u32 seq_num;
1977 u32 class_locale_word;
1978} __attribute__ ((packed));
1979
1980#ifdef CONFIG_COMPAT
1981struct compat_megasas_iocpacket {
1982 u16 host_no;
1983 u16 __pad1;
1984 u32 sgl_off;
1985 u32 sge_count;
1986 u32 sense_off;
1987 u32 sense_len;
1988 union {
1989 u8 raw[128];
1990 struct megasas_header hdr;
1991 } frame;
1992 struct compat_iovec sgl[MAX_IOCTL_SGE];
1993} __attribute__ ((packed));
1994
0e98936c 1995#define MEGASAS_IOC_FIRMWARE32 _IOWR('M', 1, struct compat_megasas_iocpacket)
c4a3e0a5
BS		 1996#endif
1997
cb59aa6a 1998#define MEGASAS_IOC_FIRMWARE _IOWR('M', 1, struct megasas_iocpacket)
c4a3e0a5
BS		 1999#define MEGASAS_IOC_GET_AEN _IOW('M', 3, struct megasas_aen)
2000
2001struct megasas_mgmt_info {
2002
2003 u16 count;
2004 struct megasas_instance *instance[MAX_MGMT_ADAPTERS];
2005 int max_index;
2006};
2007
21c9e160
AR		 2008u8
2009MR_BuildRaidContext(struct megasas_instance *instance,
2010 struct IO_REQUEST_INFO *io_info,
2011 struct RAID_CONTEXT *pRAID_Context,
51087a86
SS		 2012 struct MR_DRV_RAID_MAP_ALL *map, u8 **raidLUN);
2013u8 MR_TargetIdToLdGet(u32 ldTgtId, struct MR_DRV_RAID_MAP_ALL *map);
2014struct MR_LD_RAID *MR_LdRaidGet(u32 ld, struct MR_DRV_RAID_MAP_ALL *map);
2015u16 MR_ArPdGet(u32 ar, u32 arm, struct MR_DRV_RAID_MAP_ALL *map);
2016u16 MR_LdSpanArrayGet(u32 ld, u32 span, struct MR_DRV_RAID_MAP_ALL *map);
9ab9ed38 2017__le16 MR_PdDevHandleGet(u32 pd, struct MR_DRV_RAID_MAP_ALL *map);
51087a86
SS		 2018u16 MR_GetLDTgtId(u32 ld, struct MR_DRV_RAID_MAP_ALL *map);
2019
9ab9ed38 2020__le16 get_updated_dev_handle(struct megasas_instance *instance,
d2552ebe 2021 struct LD_LOAD_BALANCE_INFO *lbInfo, struct IO_REQUEST_INFO *in_info);
51087a86
SS		 2022void mr_update_load_balance_params(struct MR_DRV_RAID_MAP_ALL *map,
2023 struct LD_LOAD_BALANCE_INFO *lbInfo);
d009b576 2024int megasas_get_ctrl_info(struct megasas_instance *instance);
3761cb4c 2025/* PD sequence */
2026int
2027megasas_sync_pd_seq_num(struct megasas_instance *instance, bool pend);
fc62b3fc 2028int megasas_set_crash_dump_params(struct megasas_instance *instance,
51087a86 2029 u8 crash_buf_state);
fc62b3fc
SS		 2030void megasas_free_host_crash_buffer(struct megasas_instance *instance);
2031void megasas_fusion_crash_dump_wq(struct work_struct *work);
51087a86 2032
90dc9d98
SS		 2033void megasas_return_cmd_fusion(struct megasas_instance *instance,
2034 struct megasas_cmd_fusion *cmd);
2035int megasas_issue_blocked_cmd(struct megasas_instance *instance,
2036 struct megasas_cmd *cmd, int timeout);
2037void __megasas_return_cmd(struct megasas_instance *instance,
2038 struct megasas_cmd *cmd);
2039
2040void megasas_return_mfi_mpt_pthr(struct megasas_instance *instance,
2041 struct megasas_cmd *cmd_mfi, struct megasas_cmd_fusion *cmd_fusion);
7497cde8 2042int megasas_cmd_type(struct scsi_cmnd *cmd);
3761cb4c 2043void megasas_setup_jbod_map(struct megasas_instance *instance);
90dc9d98 2044
c4a3e0a5 2045#endif /*LSI_MEGARAID_SAS_H */
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