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megaraid_sas : N-drive primary raid level 1 load balancing
[mirror_ubuntu-artful-kernel.git] / drivers / scsi / megaraid / megaraid_sas.h
CommitLineData
c4a3e0a5 1/*
3f1530c1 2 * Linux MegaRAID driver for SAS based RAID controllers
c4a3e0a5 3 *
ae59057b 4 * Copyright (c) 2003-2012 LSI Corporation.
c4a3e0a5 5 *
3f1530c1
AR		 6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
c4a3e0a5 10 *
3f1530c1
AR		 11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
c4a3e0a5 15 *
3f1530c1
AR		 16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 * FILE: megaraid_sas.h
21 *
22 * Authors: LSI Corporation
23 *
24 * Send feedback to: <megaraidlinux@lsi.com>
25 *
26 * Mail to: LSI Corporation, 1621 Barber Lane, Milpitas, CA 95035
27 * ATTN: Linuxraid
c4a3e0a5
BS		 28 */
29
30#ifndef LSI_MEGARAID_SAS_H
31#define LSI_MEGARAID_SAS_H
32
a69b74d3 33/*
c4a3e0a5
BS		 34 * MegaRAID SAS Driver meta data
35 */
5e8d9007
AR		 36#define MEGASAS_VERSION "06.803.02.00-rc1"
37#define MEGASAS_RELDATE "Jun. 19, 2014"
38#define MEGASAS_EXT_VERSION "Thu. Jun. 19 17:00:00 PDT 2014"
0e98936c
SP		 39
40/*
41 * Device IDs
42 */
43#define PCI_DEVICE_ID_LSI_SAS1078R 0x0060
af7a5647 44#define PCI_DEVICE_ID_LSI_SAS1078DE 0x007C
0e98936c 45#define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413
6610a6b3
YB		 46#define PCI_DEVICE_ID_LSI_SAS1078GEN2 0x0078
47#define PCI_DEVICE_ID_LSI_SAS0079GEN2 0x0079
87911122
YB		 48#define PCI_DEVICE_ID_LSI_SAS0073SKINNY 0x0073
49#define PCI_DEVICE_ID_LSI_SAS0071SKINNY 0x0071
9c915a8c 50#define PCI_DEVICE_ID_LSI_FUSION 0x005b
229fe47c 51#define PCI_DEVICE_ID_LSI_PLASMA 0x002f
36807e67 52#define PCI_DEVICE_ID_LSI_INVADER 0x005d
21d3c710 53#define PCI_DEVICE_ID_LSI_FURY 0x005f
0e98936c 54
39b72c3c
SS		 55/*
56 * Intel HBA SSDIDs
57 */
58#define MEGARAID_INTEL_RS3DC080_SSDID 0x9360
59#define MEGARAID_INTEL_RS3DC040_SSDID 0x9362
60#define MEGARAID_INTEL_RS3SC008_SSDID 0x9380
61#define MEGARAID_INTEL_RS3MC044_SSDID 0x9381
62#define MEGARAID_INTEL_RS3WC080_SSDID 0x9341
63#define MEGARAID_INTEL_RS3WC040_SSDID 0x9343
64
65/*
66 * Intel HBA branding
67 */
68#define MEGARAID_INTEL_RS3DC080_BRANDING \
69 "Intel(R) RAID Controller RS3DC080"
70#define MEGARAID_INTEL_RS3DC040_BRANDING \
71 "Intel(R) RAID Controller RS3DC040"
72#define MEGARAID_INTEL_RS3SC008_BRANDING \
73 "Intel(R) RAID Controller RS3SC008"
74#define MEGARAID_INTEL_RS3MC044_BRANDING \
75 "Intel(R) RAID Controller RS3MC044"
76#define MEGARAID_INTEL_RS3WC080_BRANDING \
77 "Intel(R) RAID Controller RS3WC080"
78#define MEGARAID_INTEL_RS3WC040_BRANDING \
79 "Intel(R) RAID Controller RS3WC040"
80
c4a3e0a5
BS		 81/*
82 * =====================================
83 * MegaRAID SAS MFI firmware definitions
84 * =====================================
85 */
86
87/*
88 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for
89 * protocol between the software and firmware. Commands are issued using
90 * "message frames"
91 */
92
a69b74d3 93/*
c4a3e0a5
BS		 94 * FW posts its state in upper 4 bits of outbound_msg_0 register
95 */
96#define MFI_STATE_MASK 0xF0000000
97#define MFI_STATE_UNDEFINED 0x00000000
98#define MFI_STATE_BB_INIT 0x10000000
99#define MFI_STATE_FW_INIT 0x40000000
100#define MFI_STATE_WAIT_HANDSHAKE 0x60000000
101#define MFI_STATE_FW_INIT_2 0x70000000
102#define MFI_STATE_DEVICE_SCAN 0x80000000
e3bbff9f 103#define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000
c4a3e0a5
BS		 104#define MFI_STATE_FLUSH_CACHE 0xA0000000
105#define MFI_STATE_READY 0xB0000000
106#define MFI_STATE_OPERATIONAL 0xC0000000
107#define MFI_STATE_FAULT 0xF0000000
fc62b3fc
SS		 108#define MFI_STATE_FORCE_OCR 0x00000080
109#define MFI_STATE_DMADONE 0x00000008
110#define MFI_STATE_CRASH_DUMP_DONE 0x00000004
7e70e733
AR		 111#define MFI_RESET_REQUIRED 0x00000001
112#define MFI_RESET_ADAPTER 0x00000002
c4a3e0a5
BS		 113#define MEGAMFI_FRAME_SIZE 64
114
a69b74d3 115/*
c4a3e0a5
BS		 116 * During FW init, clear pending cmds & reset state using inbound_msg_0
117 *
118 * ABORT : Abort all pending cmds
119 * READY : Move from OPERATIONAL to READY state; discard queue info
120 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??)
121 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
e3bbff9f
SP		 122 * HOTPLUG : Resume from Hotplug
123 * MFI_STOP_ADP : Send signal to FW to stop processing
c4a3e0a5 124 */
39a98554 125#define WRITE_SEQUENCE_OFFSET (0x0000000FC) /* I20 */
126#define HOST_DIAGNOSTIC_OFFSET (0x000000F8) /* I20 */
127#define DIAG_WRITE_ENABLE (0x00000080)
128#define DIAG_RESET_ADAPTER (0x00000004)
129
130#define MFI_ADP_RESET 0x00000040
e3bbff9f 131#define MFI_INIT_ABORT 0x00000001
c4a3e0a5
BS		 132#define MFI_INIT_READY 0x00000002
133#define MFI_INIT_MFIMODE 0x00000004
134#define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
e3bbff9f
SP		 135#define MFI_INIT_HOTPLUG 0x00000010
136#define MFI_STOP_ADP 0x00000020
137#define MFI_RESET_FLAGS MFI_INIT_READY| \
138 MFI_INIT_MFIMODE| \
139 MFI_INIT_ABORT
c4a3e0a5 140
a69b74d3 141/*
c4a3e0a5
BS		 142 * MFI frame flags
143 */
144#define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
145#define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
146#define MFI_FRAME_SGL32 0x0000
147#define MFI_FRAME_SGL64 0x0002
148#define MFI_FRAME_SENSE32 0x0000
149#define MFI_FRAME_SENSE64 0x0004
150#define MFI_FRAME_DIR_NONE 0x0000
151#define MFI_FRAME_DIR_WRITE 0x0008
152#define MFI_FRAME_DIR_READ 0x0010
153#define MFI_FRAME_DIR_BOTH 0x0018
f4c9a131 154#define MFI_FRAME_IEEE 0x0020
c4a3e0a5 155
a69b74d3 156/*
c4a3e0a5
BS		 157 * Definition for cmd_status
158 */
159#define MFI_CMD_STATUS_POLL_MODE 0xFF
160
a69b74d3 161/*
c4a3e0a5
BS		 162 * MFI command opcodes
163 */
164#define MFI_CMD_INIT 0x00
165#define MFI_CMD_LD_READ 0x01
166#define MFI_CMD_LD_WRITE 0x02
167#define MFI_CMD_LD_SCSI_IO 0x03
168#define MFI_CMD_PD_SCSI_IO 0x04
169#define MFI_CMD_DCMD 0x05
170#define MFI_CMD_ABORT 0x06
171#define MFI_CMD_SMP 0x07
172#define MFI_CMD_STP 0x08
e5f93a36 173#define MFI_CMD_INVALID 0xff
c4a3e0a5
BS		 174
175#define MR_DCMD_CTRL_GET_INFO 0x01010000
bdc6fb8d 176#define MR_DCMD_LD_GET_LIST 0x03010000
21c9e160 177#define MR_DCMD_LD_LIST_QUERY 0x03010100
c4a3e0a5
BS		 178
179#define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
180#define MR_FLUSH_CTRL_CACHE 0x01
181#define MR_FLUSH_DISK_CACHE 0x02
182
183#define MR_DCMD_CTRL_SHUTDOWN 0x01050000
31ea7088 184#define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000
c4a3e0a5
BS		 185#define MR_ENABLE_DRIVE_SPINDOWN 0x01
186
187#define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
188#define MR_DCMD_CTRL_EVENT_GET 0x01040300
189#define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
190#define MR_DCMD_LD_GET_PROPERTIES 0x03030000
191
192#define MR_DCMD_CLUSTER 0x08000000
193#define MR_DCMD_CLUSTER_RESET_ALL 0x08010100
194#define MR_DCMD_CLUSTER_RESET_LD 0x08010200
81e403ce 195#define MR_DCMD_PD_LIST_QUERY 0x02010100
c4a3e0a5 196
fc62b3fc
SS		 197#define MR_DCMD_CTRL_SET_CRASH_DUMP_PARAMS 0x01190100
198#define MR_DRIVER_SET_APP_CRASHDUMP_MODE (0xF0010000 | 0x0600)
199
bc93d425
SS		 200/*
201 * Global functions
202 */
203extern u8 MR_ValidateMapInfo(struct megasas_instance *instance);
204
205
a69b74d3 206/*
c4a3e0a5
BS		 207 * MFI command completion codes
208 */
209enum MFI_STAT {
210 MFI_STAT_OK = 0x00,
211 MFI_STAT_INVALID_CMD = 0x01,
212 MFI_STAT_INVALID_DCMD = 0x02,
213 MFI_STAT_INVALID_PARAMETER = 0x03,
214 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
215 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
216 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
217 MFI_STAT_APP_IN_USE = 0x07,
218 MFI_STAT_APP_NOT_INITIALIZED = 0x08,
219 MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
220 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
221 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
222 MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
223 MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
224 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
225 MFI_STAT_FLASH_BUSY = 0x0f,
226 MFI_STAT_FLASH_ERROR = 0x10,
227 MFI_STAT_FLASH_IMAGE_BAD = 0x11,
228 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
229 MFI_STAT_FLASH_NOT_OPEN = 0x13,
230 MFI_STAT_FLASH_NOT_STARTED = 0x14,
231 MFI_STAT_FLUSH_FAILED = 0x15,
232 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
233 MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
234 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
235 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
236 MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
237 MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
238 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
239 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
240 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
241 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
242 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
243 MFI_STAT_MFC_HW_ERROR = 0x21,
244 MFI_STAT_NO_HW_PRESENT = 0x22,
245 MFI_STAT_NOT_FOUND = 0x23,
246 MFI_STAT_NOT_IN_ENCL = 0x24,
247 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
248 MFI_STAT_PD_TYPE_WRONG = 0x26,
249 MFI_STAT_PR_DISABLED = 0x27,
250 MFI_STAT_ROW_INDEX_INVALID = 0x28,
251 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
252 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
253 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
254 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
255 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
256 MFI_STAT_SCSI_IO_FAILED = 0x2e,
257 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
258 MFI_STAT_SHUTDOWN_FAILED = 0x30,
259 MFI_STAT_TIME_NOT_SET = 0x31,
260 MFI_STAT_WRONG_STATE = 0x32,
261 MFI_STAT_LD_OFFLINE = 0x33,
262 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34,
263 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35,
264 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36,
265 MFI_STAT_I2C_ERRORS_DETECTED = 0x37,
266 MFI_STAT_PCI_ERRORS_DETECTED = 0x38,
36807e67 267 MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67,
c4a3e0a5
BS		 268
269 MFI_STAT_INVALID_STATUS = 0xFF
270};
271
fc62b3fc
SS		 272/*
273 * Crash dump related defines
274 */
275#define MAX_CRASH_DUMP_SIZE 512
276#define CRASH_DMA_BUF_SIZE (1024 * 1024)
277
278enum MR_FW_CRASH_DUMP_STATE {
279 UNAVAILABLE = 0,
280 AVAILABLE = 1,
281 COPYING = 2,
282 COPIED = 3,
283 COPY_ERROR = 4,
284};
285
286enum _MR_CRASH_BUF_STATUS {
287 MR_CRASH_BUF_TURN_OFF = 0,
288 MR_CRASH_BUF_TURN_ON = 1,
289};
290
c4a3e0a5
BS		 291/*
292 * Number of mailbox bytes in DCMD message frame
293 */
294#define MFI_MBOX_SIZE 12
295
296enum MR_EVT_CLASS {
297
298 MR_EVT_CLASS_DEBUG = -2,
299 MR_EVT_CLASS_PROGRESS = -1,
300 MR_EVT_CLASS_INFO = 0,
301 MR_EVT_CLASS_WARNING = 1,
302 MR_EVT_CLASS_CRITICAL = 2,
303 MR_EVT_CLASS_FATAL = 3,
304 MR_EVT_CLASS_DEAD = 4,
305
306};
307
308enum MR_EVT_LOCALE {
309
310 MR_EVT_LOCALE_LD = 0x0001,
311 MR_EVT_LOCALE_PD = 0x0002,
312 MR_EVT_LOCALE_ENCL = 0x0004,
313 MR_EVT_LOCALE_BBU = 0x0008,
314 MR_EVT_LOCALE_SAS = 0x0010,
315 MR_EVT_LOCALE_CTRL = 0x0020,
316 MR_EVT_LOCALE_CONFIG = 0x0040,
317 MR_EVT_LOCALE_CLUSTER = 0x0080,
318 MR_EVT_LOCALE_ALL = 0xffff,
319
320};
321
322enum MR_EVT_ARGS {
323
324 MR_EVT_ARGS_NONE,
325 MR_EVT_ARGS_CDB_SENSE,
326 MR_EVT_ARGS_LD,
327 MR_EVT_ARGS_LD_COUNT,
328 MR_EVT_ARGS_LD_LBA,
329 MR_EVT_ARGS_LD_OWNER,
330 MR_EVT_ARGS_LD_LBA_PD_LBA,
331 MR_EVT_ARGS_LD_PROG,
332 MR_EVT_ARGS_LD_STATE,
333 MR_EVT_ARGS_LD_STRIP,
334 MR_EVT_ARGS_PD,
335 MR_EVT_ARGS_PD_ERR,
336 MR_EVT_ARGS_PD_LBA,
337 MR_EVT_ARGS_PD_LBA_LD,
338 MR_EVT_ARGS_PD_PROG,
339 MR_EVT_ARGS_PD_STATE,
340 MR_EVT_ARGS_PCI,
341 MR_EVT_ARGS_RATE,
342 MR_EVT_ARGS_STR,
343 MR_EVT_ARGS_TIME,
344 MR_EVT_ARGS_ECC,
81e403ce
YB		 345 MR_EVT_ARGS_LD_PROP,
346 MR_EVT_ARGS_PD_SPARE,
347 MR_EVT_ARGS_PD_INDEX,
348 MR_EVT_ARGS_DIAG_PASS,
349 MR_EVT_ARGS_DIAG_FAIL,
350 MR_EVT_ARGS_PD_LBA_LBA,
351 MR_EVT_ARGS_PORT_PHY,
352 MR_EVT_ARGS_PD_MISSING,
353 MR_EVT_ARGS_PD_ADDRESS,
354 MR_EVT_ARGS_BITMAP,
355 MR_EVT_ARGS_CONNECTOR,
356 MR_EVT_ARGS_PD_PD,
357 MR_EVT_ARGS_PD_FRU,
358 MR_EVT_ARGS_PD_PATHINFO,
359 MR_EVT_ARGS_PD_POWER_STATE,
360 MR_EVT_ARGS_GENERIC,
361};
c4a3e0a5 362
81e403ce
YB		 363/*
364 * define constants for device list query options
365 */
366enum MR_PD_QUERY_TYPE {
367 MR_PD_QUERY_TYPE_ALL = 0,
368 MR_PD_QUERY_TYPE_STATE = 1,
369 MR_PD_QUERY_TYPE_POWER_STATE = 2,
370 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3,
371 MR_PD_QUERY_TYPE_SPEED = 4,
372 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5,
c4a3e0a5
BS		 373};
374
21c9e160
AR		 375enum MR_LD_QUERY_TYPE {
376 MR_LD_QUERY_TYPE_ALL = 0,
377 MR_LD_QUERY_TYPE_EXPOSED_TO_HOST = 1,
378 MR_LD_QUERY_TYPE_USED_TGT_IDS = 2,
379 MR_LD_QUERY_TYPE_CLUSTER_ACCESS = 3,
380 MR_LD_QUERY_TYPE_CLUSTER_LOCALE = 4,
381};
382
383
7e8a75f4
YB		 384#define MR_EVT_CFG_CLEARED 0x0004
385#define MR_EVT_LD_STATE_CHANGE 0x0051
386#define MR_EVT_PD_INSERTED 0x005b
387#define MR_EVT_PD_REMOVED 0x0070
388#define MR_EVT_LD_CREATED 0x008a
389#define MR_EVT_LD_DELETED 0x008b
390#define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db
391#define MR_EVT_LD_OFFLINE 0x00fc
392#define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152
7e8a75f4 393
81e403ce
YB		 394enum MR_PD_STATE {
395 MR_PD_STATE_UNCONFIGURED_GOOD = 0x00,
396 MR_PD_STATE_UNCONFIGURED_BAD = 0x01,
397 MR_PD_STATE_HOT_SPARE = 0x02,
398 MR_PD_STATE_OFFLINE = 0x10,
399 MR_PD_STATE_FAILED = 0x11,
400 MR_PD_STATE_REBUILD = 0x14,
401 MR_PD_STATE_ONLINE = 0x18,
402 MR_PD_STATE_COPYBACK = 0x20,
403 MR_PD_STATE_SYSTEM = 0x40,
404 };
405
406
407 /*
408 * defines the physical drive address structure
409 */
410struct MR_PD_ADDRESS {
411 u16 deviceId;
412 u16 enclDeviceId;
413
414 union {
415 struct {
416 u8 enclIndex;
417 u8 slotNumber;
418 } mrPdAddress;
419 struct {
420 u8 enclPosition;
421 u8 enclConnectorIndex;
422 } mrEnclAddress;
423 };
424 u8 scsiDevType;
425 union {
426 u8 connectedPortBitmap;
427 u8 connectedPortNumbers;
428 };
429 u64 sasAddr[2];
430} __packed;
431
432/*
433 * defines the physical drive list structure
434 */
435struct MR_PD_LIST {
436 u32 size;
437 u32 count;
438 struct MR_PD_ADDRESS addr[1];
439} __packed;
440
441struct megasas_pd_list {
442 u16 tid;
443 u8 driveType;
444 u8 driveState;
445} __packed;
446
bdc6fb8d
YB		 447 /*
448 * defines the logical drive reference structure
449 */
450union MR_LD_REF {
451 struct {
452 u8 targetId;
453 u8 reserved;
454 u16 seqNum;
455 };
456 u32 ref;
457} __packed;
458
459/*
460 * defines the logical drive list structure
461 */
462struct MR_LD_LIST {
463 u32 ldCount;
464 u32 reserved;
465 struct {
466 union MR_LD_REF ref;
467 u8 state;
468 u8 reserved[3];
469 u64 size;
51087a86 470 } ldList[MAX_LOGICAL_DRIVES_EXT];
bdc6fb8d
YB		 471} __packed;
472
21c9e160
AR		 473struct MR_LD_TARGETID_LIST {
474 u32 size;
475 u32 count;
476 u8 pad[3];
51087a86 477 u8 targetId[MAX_LOGICAL_DRIVES_EXT];
21c9e160
AR		 478};
479
480
c4a3e0a5
BS		 481/*
482 * SAS controller properties
483 */
484struct megasas_ctrl_prop {
485
486 u16 seq_num;
487 u16 pred_fail_poll_interval;
488 u16 intr_throttle_count;
489 u16 intr_throttle_timeouts;
490 u8 rebuild_rate;
491 u8 patrol_read_rate;
492 u8 bgi_rate;
493 u8 cc_rate;
494 u8 recon_rate;
495 u8 cache_flush_interval;
496 u8 spinup_drv_count;
497 u8 spinup_delay;
498 u8 cluster_enable;
499 u8 coercion_mode;
500 u8 alarm_enable;
501 u8 disable_auto_rebuild;
502 u8 disable_battery_warn;
503 u8 ecc_bucket_size;
504 u16 ecc_bucket_leak_rate;
505 u8 restore_hotspare_on_insertion;
506 u8 expose_encl_devices;
39a98554 507 u8 maintainPdFailHistory;
508 u8 disallowHostRequestReordering;
509 u8 abortCCOnError;
510 u8 loadBalanceMode;
511 u8 disableAutoDetectBackplane;
512
513 u8 snapVDSpace;
514
515 /*
516 * Add properties that can be controlled by
517 * a bit in the following structure.
518 */
39a98554 519 struct {
94cd65dd
SS		 520#if defined(__BIG_ENDIAN_BITFIELD)
521 u32 reserved:18;
522 u32 enableJBOD:1;
523 u32 disableSpinDownHS:1;
524 u32 allowBootWithPinnedCache:1;
525 u32 disableOnlineCtrlReset:1;
526 u32 enableSecretKeyControl:1;
527 u32 autoEnhancedImport:1;
528 u32 enableSpinDownUnconfigured:1;
529 u32 SSDPatrolReadEnabled:1;
530 u32 SSDSMARTerEnabled:1;
531 u32 disableNCQ:1;
532 u32 useFdeOnly:1;
533 u32 prCorrectUnconfiguredAreas:1;
534 u32 SMARTerEnabled:1;
535 u32 copyBackDisabled:1;
536#else
537 u32 copyBackDisabled:1;
538 u32 SMARTerEnabled:1;
539 u32 prCorrectUnconfiguredAreas:1;
540 u32 useFdeOnly:1;
541 u32 disableNCQ:1;
542 u32 SSDSMARTerEnabled:1;
543 u32 SSDPatrolReadEnabled:1;
544 u32 enableSpinDownUnconfigured:1;
545 u32 autoEnhancedImport:1;
546 u32 enableSecretKeyControl:1;
547 u32 disableOnlineCtrlReset:1;
548 u32 allowBootWithPinnedCache:1;
549 u32 disableSpinDownHS:1;
550 u32 enableJBOD:1;
551 u32 reserved:18;
552#endif
39a98554 553 } OnOffProperties;
554 u8 autoSnapVDSpace;
555 u8 viewSpace;
556 u16 spinDownTime;
557 u8 reserved[24];
81e403ce 558} __packed;
c4a3e0a5
BS		 559
560/*
561 * SAS controller information
562 */
563struct megasas_ctrl_info {
564
565 /*
566 * PCI device information
567 */
568 struct {
569
570 u16 vendor_id;
571 u16 device_id;
572 u16 sub_vendor_id;
573 u16 sub_device_id;
574 u8 reserved[24];
575
576 } __attribute__ ((packed)) pci;
577
578 /*
579 * Host interface information
580 */
581 struct {
582
583 u8 PCIX:1;
584 u8 PCIE:1;
585 u8 iSCSI:1;
586 u8 SAS_3G:1;
229fe47c
AR		 587 u8 SRIOV:1;
588 u8 reserved_0:3;
c4a3e0a5
BS		 589 u8 reserved_1[6];
590 u8 port_count;
591 u64 port_addr[8];
592
593 } __attribute__ ((packed)) host_interface;
594
595 /*
596 * Device (backend) interface information
597 */
598 struct {
599
600 u8 SPI:1;
601 u8 SAS_3G:1;
602 u8 SATA_1_5G:1;
603 u8 SATA_3G:1;
604 u8 reserved_0:4;
605 u8 reserved_1[6];
606 u8 port_count;
607 u64 port_addr[8];
608
609 } __attribute__ ((packed)) device_interface;
610
611 /*
612 * List of components residing in flash. All str are null terminated
613 */
614 u32 image_check_word;
615 u32 image_component_count;
616
617 struct {
618
619 char name[8];
620 char version[32];
621 char build_date[16];
622 char built_time[16];
623
624 } __attribute__ ((packed)) image_component[8];
625
626 /*
627 * List of flash components that have been flashed on the card, but
628 * are not in use, pending reset of the adapter. This list will be
629 * empty if a flash operation has not occurred. All stings are null
630 * terminated
631 */
632 u32 pending_image_component_count;
633
634 struct {
635
636 char name[8];
637 char version[32];
638 char build_date[16];
639 char build_time[16];
640
641 } __attribute__ ((packed)) pending_image_component[8];
642
643 u8 max_arms;
644 u8 max_spans;
645 u8 max_arrays;
646 u8 max_lds;
647
648 char product_name[80];
649 char serial_no[32];
650
651 /*
652 * Other physical/controller/operation information. Indicates the
653 * presence of the hardware
654 */
655 struct {
656
657 u32 bbu:1;
658 u32 alarm:1;
659 u32 nvram:1;
660 u32 uart:1;
661 u32 reserved:28;
662
663 } __attribute__ ((packed)) hw_present;
664
665 u32 current_fw_time;
666
667 /*
668 * Maximum data transfer sizes
669 */
670 u16 max_concurrent_cmds;
671 u16 max_sge_count;
672 u32 max_request_size;
673
674 /*
675 * Logical and physical device counts
676 */
677 u16 ld_present_count;
678 u16 ld_degraded_count;
679 u16 ld_offline_count;
680
681 u16 pd_present_count;
682 u16 pd_disk_present_count;
683 u16 pd_disk_pred_failure_count;
684 u16 pd_disk_failed_count;
685
686 /*
687 * Memory size information
688 */
689 u16 nvram_size;
690 u16 memory_size;
691 u16 flash_size;
692
693 /*
694 * Error counters
695 */
696 u16 mem_correctable_error_count;
697 u16 mem_uncorrectable_error_count;
698
699 /*
700 * Cluster information
701 */
702 u8 cluster_permitted;
703 u8 cluster_active;
704
705 /*
706 * Additional max data transfer sizes
707 */
708 u16 max_strips_per_io;
709
710 /*
711 * Controller capabilities structures
712 */
713 struct {
714
715 u32 raid_level_0:1;
716 u32 raid_level_1:1;
717 u32 raid_level_5:1;
718 u32 raid_level_1E:1;
719 u32 raid_level_6:1;
720 u32 reserved:27;
721
722 } __attribute__ ((packed)) raid_levels;
723
724 struct {
725
726 u32 rbld_rate:1;
727 u32 cc_rate:1;
728 u32 bgi_rate:1;
729 u32 recon_rate:1;
730 u32 patrol_rate:1;
731 u32 alarm_control:1;
732 u32 cluster_supported:1;
733 u32 bbu:1;
734 u32 spanning_allowed:1;
735 u32 dedicated_hotspares:1;
736 u32 revertible_hotspares:1;
737 u32 foreign_config_import:1;
738 u32 self_diagnostic:1;
739 u32 mixed_redundancy_arr:1;
740 u32 global_hot_spares:1;
741 u32 reserved:17;
742
743 } __attribute__ ((packed)) adapter_operations;
744
745 struct {
746
747 u32 read_policy:1;
748 u32 write_policy:1;
749 u32 io_policy:1;
750 u32 access_policy:1;
751 u32 disk_cache_policy:1;
752 u32 reserved:27;
753
754 } __attribute__ ((packed)) ld_operations;
755
756 struct {
757
758 u8 min;
759 u8 max;
760 u8 reserved[2];
761
762 } __attribute__ ((packed)) stripe_sz_ops;
763
764 struct {
765
766 u32 force_online:1;
767 u32 force_offline:1;
768 u32 force_rebuild:1;
769 u32 reserved:29;
770
771 } __attribute__ ((packed)) pd_operations;
772
773 struct {
774
775 u32 ctrl_supports_sas:1;
776 u32 ctrl_supports_sata:1;
777 u32 allow_mix_in_encl:1;
778 u32 allow_mix_in_ld:1;
779 u32 allow_sata_in_cluster:1;
780 u32 reserved:27;
781
782 } __attribute__ ((packed)) pd_mix_support;
783
784 /*
785 * Define ECC single-bit-error bucket information
786 */
787 u8 ecc_bucket_count;
788 u8 reserved_2[11];
789
790 /*
791 * Include the controller properties (changeable items)
792 */
793 struct megasas_ctrl_prop properties;
794
795 /*
796 * Define FW pkg version (set in envt v'bles on OEM basis)
797 */
798 char package_version[0x60];
799
c4a3e0a5 800
bc93d425
SS		 801 /*
802 * If adapterOperations.supportMoreThan8Phys is set,
803 * and deviceInterface.portCount is greater than 8,
804 * SAS Addrs for first 8 ports shall be populated in
805 * deviceInterface.portAddr, and the rest shall be
806 * populated in deviceInterfacePortAddr2.
807 */
808 u64 deviceInterfacePortAddr2[8]; /*6a0h */
809 u8 reserved3[128]; /*6e0h */
810
811 struct { /*760h */
812 u16 minPdRaidLevel_0:4;
813 u16 maxPdRaidLevel_0:12;
814
815 u16 minPdRaidLevel_1:4;
816 u16 maxPdRaidLevel_1:12;
817
818 u16 minPdRaidLevel_5:4;
819 u16 maxPdRaidLevel_5:12;
820
821 u16 minPdRaidLevel_1E:4;
822 u16 maxPdRaidLevel_1E:12;
823
824 u16 minPdRaidLevel_6:4;
825 u16 maxPdRaidLevel_6:12;
826
827 u16 minPdRaidLevel_10:4;
828 u16 maxPdRaidLevel_10:12;
829
830 u16 minPdRaidLevel_50:4;
831 u16 maxPdRaidLevel_50:12;
832
833 u16 minPdRaidLevel_60:4;
834 u16 maxPdRaidLevel_60:12;
835
836 u16 minPdRaidLevel_1E_RLQ0:4;
837 u16 maxPdRaidLevel_1E_RLQ0:12;
838
839 u16 minPdRaidLevel_1E0_RLQ0:4;
840 u16 maxPdRaidLevel_1E0_RLQ0:12;
841
842 u16 reserved[6];
843 } pdsForRaidLevels;
844
845 u16 maxPds; /*780h */
846 u16 maxDedHSPs; /*782h */
847 u16 maxGlobalHSPs; /*784h */
848 u16 ddfSize; /*786h */
849 u8 maxLdsPerArray; /*788h */
850 u8 partitionsInDDF; /*789h */
851 u8 lockKeyBinding; /*78ah */
852 u8 maxPITsPerLd; /*78bh */
853 u8 maxViewsPerLd; /*78ch */
854 u8 maxTargetId; /*78dh */
855 u16 maxBvlVdSize; /*78eh */
856
857 u16 maxConfigurableSSCSize; /*790h */
858 u16 currentSSCsize; /*792h */
859
860 char expanderFwVersion[12]; /*794h */
861
862 u16 PFKTrialTimeRemaining; /*7A0h */
863
864 u16 cacheMemorySize; /*7A2h */
865
866 struct { /*7A4h */
94cd65dd 867#if defined(__BIG_ENDIAN_BITFIELD)
229fe47c
AR		 868 u32 reserved:5;
869 u32 activePassive:2;
870 u32 supportConfigAutoBalance:1;
871 u32 mpio:1;
872 u32 supportDataLDonSSCArray:1;
873 u32 supportPointInTimeProgress:1;
94cd65dd
SS		 874 u32 supportUnevenSpans:1;
875 u32 dedicatedHotSparesLimited:1;
876 u32 headlessMode:1;
877 u32 supportEmulatedDrives:1;
878 u32 supportResetNow:1;
879 u32 realTimeScheduler:1;
880 u32 supportSSDPatrolRead:1;
881 u32 supportPerfTuning:1;
882 u32 disableOnlinePFKChange:1;
883 u32 supportJBOD:1;
884 u32 supportBootTimePFKChange:1;
885 u32 supportSetLinkSpeed:1;
886 u32 supportEmergencySpares:1;
887 u32 supportSuspendResumeBGops:1;
888 u32 blockSSDWriteCacheChange:1;
889 u32 supportShieldState:1;
890 u32 supportLdBBMInfo:1;
891 u32 supportLdPIType3:1;
892 u32 supportLdPIType2:1;
893 u32 supportLdPIType1:1;
894 u32 supportPIcontroller:1;
895#else
bc93d425
SS		 896 u32 supportPIcontroller:1;
897 u32 supportLdPIType1:1;
898 u32 supportLdPIType2:1;
899 u32 supportLdPIType3:1;
900 u32 supportLdBBMInfo:1;
901 u32 supportShieldState:1;
902 u32 blockSSDWriteCacheChange:1;
903 u32 supportSuspendResumeBGops:1;
904 u32 supportEmergencySpares:1;
905 u32 supportSetLinkSpeed:1;
906 u32 supportBootTimePFKChange:1;
907 u32 supportJBOD:1;
908 u32 disableOnlinePFKChange:1;
909 u32 supportPerfTuning:1;
910 u32 supportSSDPatrolRead:1;
911 u32 realTimeScheduler:1;
912
913 u32 supportResetNow:1;
914 u32 supportEmulatedDrives:1;
915 u32 headlessMode:1;
916 u32 dedicatedHotSparesLimited:1;
917
918
919 u32 supportUnevenSpans:1;
229fe47c
AR		 920 u32 supportPointInTimeProgress:1;
921 u32 supportDataLDonSSCArray:1;
922 u32 mpio:1;
923 u32 supportConfigAutoBalance:1;
924 u32 activePassive:2;
925 u32 reserved:5;
94cd65dd 926#endif
bc93d425
SS		 927 } adapterOperations2;
928
929 u8 driverVersion[32]; /*7A8h */
930 u8 maxDAPdCountSpinup60; /*7C8h */
931 u8 temperatureROC; /*7C9h */
932 u8 temperatureCtrl; /*7CAh */
933 u8 reserved4; /*7CBh */
934 u16 maxConfigurablePds; /*7CCh */
935
936
937 u8 reserved5[2]; /*0x7CDh */
938
939 /*
940 * HA cluster information
941 */
942 struct {
51087a86
SS		 943#if defined(__BIG_ENDIAN_BITFIELD)
944 u32 reserved:26;
945 u32 premiumFeatureMismatch:1;
946 u32 ctrlPropIncompatible:1;
947 u32 fwVersionMismatch:1;
948 u32 hwIncompatible:1;
949 u32 peerIsIncompatible:1;
950 u32 peerIsPresent:1;
951#else
bc93d425
SS		 952 u32 peerIsPresent:1;
953 u32 peerIsIncompatible:1;
954 u32 hwIncompatible:1;
955 u32 fwVersionMismatch:1;
956 u32 ctrlPropIncompatible:1;
957 u32 premiumFeatureMismatch:1;
958 u32 reserved:26;
51087a86 959#endif
bc93d425
SS		 960 } cluster;
961
962 char clusterId[16]; /*7D4h */
229fe47c
AR		 963 struct {
964 u8 maxVFsSupported; /*0x7E4*/
965 u8 numVFsEnabled; /*0x7E5*/
966 u8 requestorId; /*0x7E6 0:PF, 1:VF1, 2:VF2*/
967 u8 reserved; /*0x7E7*/
968 } iov;
bc93d425 969
fc62b3fc
SS		 970 struct {
971#if defined(__BIG_ENDIAN_BITFIELD)
972 u32 reserved:25;
973 u32 supportCrashDump:1;
51087a86
SS		 974 u32 supportMaxExtLDs:1;
975 u32 supportT10RebuildAssist:1;
976 u32 supportDisableImmediateIO:1;
977 u32 supportThermalPollInterval:1;
978 u32 supportPersonalityChange:2;
fc62b3fc 979#else
51087a86
SS		 980 u32 supportPersonalityChange:2;
981 u32 supportThermalPollInterval:1;
982 u32 supportDisableImmediateIO:1;
983 u32 supportT10RebuildAssist:1;
984 u32 supportMaxExtLDs:1;
fc62b3fc
SS		 985 u32 supportCrashDump:1;
986 u32 reserved:25;
987#endif
988 } adapterOperations3;
989
990 u8 pad[0x800-0x7EC];
81e403ce 991} __packed;
c4a3e0a5
BS		 992
993/*
994 * ===============================
995 * MegaRAID SAS driver definitions
996 * ===============================
997 */
998#define MEGASAS_MAX_PD_CHANNELS 2
51087a86 999#define MEGASAS_MAX_LD_CHANNELS 2
c4a3e0a5
BS		 1000#define MEGASAS_MAX_CHANNELS (MEGASAS_MAX_PD_CHANNELS + \
1001 MEGASAS_MAX_LD_CHANNELS)
1002#define MEGASAS_MAX_DEV_PER_CHANNEL 128
1003#define MEGASAS_DEFAULT_INIT_ID -1
1004#define MEGASAS_MAX_LUN 8
6bf579a3 1005#define MEGASAS_DEFAULT_CMD_PER_LUN 256
81e403ce
YB		 1006#define MEGASAS_MAX_PD (MEGASAS_MAX_PD_CHANNELS * \
1007 MEGASAS_MAX_DEV_PER_CHANNEL)
bdc6fb8d
YB		 1008#define MEGASAS_MAX_LD_IDS (MEGASAS_MAX_LD_CHANNELS * \
1009 MEGASAS_MAX_DEV_PER_CHANNEL)
c4a3e0a5 1010
1fd10685 1011#define MEGASAS_MAX_SECTORS (2*1024)
42a8d2b3 1012#define MEGASAS_MAX_SECTORS_IEEE (2*128)
658dcedb
SP		 1013#define MEGASAS_DBG_LVL 1
1014
05e9ebbe
SP		 1015#define MEGASAS_FW_BUSY 1
1016
51087a86
SS		 1017#define VD_EXT_DEBUG 0
1018
d532dbe2 1019/* Frame Type */
1020#define IO_FRAME 0
1021#define PTHRU_FRAME 1
1022
c4a3e0a5
BS		 1023/*
1024 * When SCSI mid-layer calls driver's reset routine, driver waits for
1025 * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note
1026 * that the driver cannot _actually_ abort or reset pending commands. While
1027 * it is waiting for the commands to complete, it prints a diagnostic message
1028 * every MEGASAS_RESET_NOTICE_INTERVAL seconds
1029 */
1030#define MEGASAS_RESET_WAIT_TIME 180
2a3681e5 1031#define MEGASAS_INTERNAL_CMD_WAIT_TIME 180
c4a3e0a5 1032#define MEGASAS_RESET_NOTICE_INTERVAL 5
c4a3e0a5 1033#define MEGASAS_IOCTL_CMD 0
05e9ebbe 1034#define MEGASAS_DEFAULT_CMD_TIMEOUT 90
c5daa6a9 1035#define MEGASAS_THROTTLE_QUEUE_DEPTH 16
c4a3e0a5
BS		 1036
1037/*
1038 * FW reports the maximum of number of commands that it can accept (maximum
1039 * commands that can be outstanding) at any time. The driver must report a
1040 * lower number to the mid layer because it can issue a few internal commands
1041 * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs
1042 * is shown below
1043 */
1044#define MEGASAS_INT_CMDS 32
7bebf5c7 1045#define MEGASAS_SKINNY_INT_CMDS 5
c4a3e0a5 1046
d46a3ad6 1047#define MEGASAS_MAX_MSIX_QUEUES 128
c4a3e0a5
BS		 1048/*
1049 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
1050 * SGLs based on the size of dma_addr_t
1051 */
1052#define IS_DMA64 (sizeof(dma_addr_t) == 8)
1053
39a98554 1054#define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001
1055
1056#define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001
1057#define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002
1058#define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004
1059
c4a3e0a5 1060#define MFI_OB_INTR_STATUS_MASK 0x00000002
14faea9f 1061#define MFI_POLL_TIMEOUT_SECS 60
229fe47c
AR		 1062#define MEGASAS_SRIOV_HEARTBEAT_INTERVAL_VF (5 * HZ)
1063#define MEGASAS_OCR_SETTLE_TIME_VF (1000 * 30)
1064#define MEGASAS_ROUTINE_WAIT_TIME_VF 300
f9876f0b 1065#define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000
6610a6b3
YB		 1066#define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001
1067#define MFI_GEN2_ENABLE_INTERRUPT_MASK (0x00000001 | 0x00000004)
87911122
YB		 1068#define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000
1069#define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001)
0e98936c 1070
39a98554 1071#define MFI_1068_PCSR_OFFSET 0x84
1072#define MFI_1068_FW_HANDSHAKE_OFFSET 0x64
1073#define MFI_1068_FW_READY 0xDDDD0000
d46a3ad6
SS		 1074
1075#define MR_MAX_REPLY_QUEUES_OFFSET 0X0000001F
1076#define MR_MAX_REPLY_QUEUES_EXT_OFFSET 0X003FC000
1077#define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT 14
1078#define MR_MAX_MSIX_REG_ARRAY 16
0e98936c
SP		 1079/*
1080* register set for both 1068 and 1078 controllers
1081* structure extended for 1078 registers
1082*/
f9876f0b 1083
c4a3e0a5 1084struct megasas_register_set {
9c915a8c
AR		 1085 u32 doorbell; /*0000h*/
1086 u32 fusion_seq_offset; /*0004h*/
1087 u32 fusion_host_diag; /*0008h*/
1088 u32 reserved_01; /*000Ch*/
c4a3e0a5 1089
f9876f0b
SP		 1090 u32 inbound_msg_0; /*0010h*/
1091 u32 inbound_msg_1; /*0014h*/
1092 u32 outbound_msg_0; /*0018h*/
1093 u32 outbound_msg_1; /*001Ch*/
c4a3e0a5 1094
f9876f0b
SP		 1095 u32 inbound_doorbell; /*0020h*/
1096 u32 inbound_intr_status; /*0024h*/
1097 u32 inbound_intr_mask; /*0028h*/
c4a3e0a5 1098
f9876f0b
SP		 1099 u32 outbound_doorbell; /*002Ch*/
1100 u32 outbound_intr_status; /*0030h*/
1101 u32 outbound_intr_mask; /*0034h*/
c4a3e0a5 1102
f9876f0b 1103 u32 reserved_1[2]; /*0038h*/
c4a3e0a5 1104
f9876f0b
SP		 1105 u32 inbound_queue_port; /*0040h*/
1106 u32 outbound_queue_port; /*0044h*/
c4a3e0a5 1107
9c915a8c
AR		 1108 u32 reserved_2[9]; /*0048h*/
1109 u32 reply_post_host_index; /*006Ch*/
1110 u32 reserved_2_2[12]; /*0070h*/
c4a3e0a5 1111
f9876f0b 1112 u32 outbound_doorbell_clear; /*00A0h*/
c4a3e0a5 1113
f9876f0b
SP		 1114 u32 reserved_3[3]; /*00A4h*/
1115
1116 u32 outbound_scratch_pad ; /*00B0h*/
9c915a8c 1117 u32 outbound_scratch_pad_2; /*00B4h*/
f9876f0b 1118
9c915a8c 1119 u32 reserved_4[2]; /*00B8h*/
f9876f0b
SP		 1120
1121 u32 inbound_low_queue_port ; /*00C0h*/
1122
1123 u32 inbound_high_queue_port ; /*00C4h*/
1124
1125 u32 reserved_5; /*00C8h*/
39a98554 1126 u32 res_6[11]; /*CCh*/
1127 u32 host_diag;
1128 u32 seq_offset;
1129 u32 index_registers[807]; /*00CCh*/
c4a3e0a5
BS		 1130} __attribute__ ((packed));
1131
1132struct megasas_sge32 {
1133
1134 u32 phys_addr;
1135 u32 length;
1136
1137} __attribute__ ((packed));
1138
1139struct megasas_sge64 {
1140
1141 u64 phys_addr;
1142 u32 length;
1143
1144} __attribute__ ((packed));
1145
f4c9a131
YB		 1146struct megasas_sge_skinny {
1147 u64 phys_addr;
1148 u32 length;
1149 u32 flag;
1150} __packed;
1151
c4a3e0a5
BS		 1152union megasas_sgl {
1153
1154 struct megasas_sge32 sge32[1];
1155 struct megasas_sge64 sge64[1];
f4c9a131 1156 struct megasas_sge_skinny sge_skinny[1];
c4a3e0a5
BS		 1157
1158} __attribute__ ((packed));
1159
1160struct megasas_header {
1161
1162 u8 cmd; /*00h */
1163 u8 sense_len; /*01h */
1164 u8 cmd_status; /*02h */
1165 u8 scsi_status; /*03h */
1166
1167 u8 target_id; /*04h */
1168 u8 lun; /*05h */
1169 u8 cdb_len; /*06h */
1170 u8 sge_count; /*07h */
1171
1172 u32 context; /*08h */
1173 u32 pad_0; /*0Ch */
1174
1175 u16 flags; /*10h */
1176 u16 timeout; /*12h */
1177 u32 data_xferlen; /*14h */
1178
1179} __attribute__ ((packed));
1180
1181union megasas_sgl_frame {
1182
1183 struct megasas_sge32 sge32[8];
1184 struct megasas_sge64 sge64[5];
1185
1186} __attribute__ ((packed));
1187
d46a3ad6
SS		 1188typedef union _MFI_CAPABILITIES {
1189 struct {
94cd65dd 1190#if defined(__BIG_ENDIAN_BITFIELD)
d2552ebe
SS		 1191 u32 reserved:27;
1192 u32 support_ndrive_r1_lb:1;
51087a86
SS		 1193 u32 support_max_255lds:1;
1194 u32 reserved1:1;
94cd65dd
SS		 1195 u32 support_additional_msix:1;
1196 u32 support_fp_remote_lun:1;
1197#else
d46a3ad6
SS		 1198 u32 support_fp_remote_lun:1;
1199 u32 support_additional_msix:1;
51087a86
SS		 1200 u32 reserved1:1;
1201 u32 support_max_255lds:1;
d2552ebe
SS		 1202 u32 support_ndrive_r1_lb:1;
1203 u32 reserved:27;
94cd65dd 1204#endif
d46a3ad6
SS		 1205 } mfi_capabilities;
1206 u32 reg;
1207} MFI_CAPABILITIES;
1208
c4a3e0a5
BS		 1209struct megasas_init_frame {
1210
1211 u8 cmd; /*00h */
1212 u8 reserved_0; /*01h */
1213 u8 cmd_status; /*02h */
1214
1215 u8 reserved_1; /*03h */
d46a3ad6 1216 MFI_CAPABILITIES driver_operations; /*04h*/
c4a3e0a5
BS		 1217
1218 u32 context; /*08h */
1219 u32 pad_0; /*0Ch */
1220
1221 u16 flags; /*10h */
1222 u16 reserved_3; /*12h */
1223 u32 data_xfer_len; /*14h */
1224
1225 u32 queue_info_new_phys_addr_lo; /*18h */
1226 u32 queue_info_new_phys_addr_hi; /*1Ch */
1227 u32 queue_info_old_phys_addr_lo; /*20h */
1228 u32 queue_info_old_phys_addr_hi; /*24h */
1229
1230 u32 reserved_4[6]; /*28h */
1231
1232} __attribute__ ((packed));
1233
1234struct megasas_init_queue_info {
1235
1236 u32 init_flags; /*00h */
1237 u32 reply_queue_entries; /*04h */
1238
1239 u32 reply_queue_start_phys_addr_lo; /*08h */
1240 u32 reply_queue_start_phys_addr_hi; /*0Ch */
1241 u32 producer_index_phys_addr_lo; /*10h */
1242 u32 producer_index_phys_addr_hi; /*14h */
1243 u32 consumer_index_phys_addr_lo; /*18h */
1244 u32 consumer_index_phys_addr_hi; /*1Ch */
1245
1246} __attribute__ ((packed));
1247
1248struct megasas_io_frame {
1249
1250 u8 cmd; /*00h */
1251 u8 sense_len; /*01h */
1252 u8 cmd_status; /*02h */
1253 u8 scsi_status; /*03h */
1254
1255 u8 target_id; /*04h */
1256 u8 access_byte; /*05h */
1257 u8 reserved_0; /*06h */
1258 u8 sge_count; /*07h */
1259
1260 u32 context; /*08h */
1261 u32 pad_0; /*0Ch */
1262
1263 u16 flags; /*10h */
1264 u16 timeout; /*12h */
1265 u32 lba_count; /*14h */
1266
1267 u32 sense_buf_phys_addr_lo; /*18h */
1268 u32 sense_buf_phys_addr_hi; /*1Ch */
1269
1270 u32 start_lba_lo; /*20h */
1271 u32 start_lba_hi; /*24h */
1272
1273 union megasas_sgl sgl; /*28h */
1274
1275} __attribute__ ((packed));
1276
1277struct megasas_pthru_frame {
1278
1279 u8 cmd; /*00h */
1280 u8 sense_len; /*01h */
1281 u8 cmd_status; /*02h */
1282 u8 scsi_status; /*03h */
1283
1284 u8 target_id; /*04h */
1285 u8 lun; /*05h */
1286 u8 cdb_len; /*06h */
1287 u8 sge_count; /*07h */
1288
1289 u32 context; /*08h */
1290 u32 pad_0; /*0Ch */
1291
1292 u16 flags; /*10h */
1293 u16 timeout; /*12h */
1294 u32 data_xfer_len; /*14h */
1295
1296 u32 sense_buf_phys_addr_lo; /*18h */
1297 u32 sense_buf_phys_addr_hi; /*1Ch */
1298
1299 u8 cdb[16]; /*20h */
1300 union megasas_sgl sgl; /*30h */
1301
1302} __attribute__ ((packed));
1303
1304struct megasas_dcmd_frame {
1305
1306 u8 cmd; /*00h */
1307 u8 reserved_0; /*01h */
1308 u8 cmd_status; /*02h */
1309 u8 reserved_1[4]; /*03h */
1310 u8 sge_count; /*07h */
1311
1312 u32 context; /*08h */
1313 u32 pad_0; /*0Ch */
1314
1315 u16 flags; /*10h */
1316 u16 timeout; /*12h */
1317
1318 u32 data_xfer_len; /*14h */
1319 u32 opcode; /*18h */
1320
1321 union { /*1Ch */
1322 u8 b[12];
1323 u16 s[6];
1324 u32 w[3];
1325 } mbox;
1326
1327 union megasas_sgl sgl; /*28h */
1328
1329} __attribute__ ((packed));
1330
1331struct megasas_abort_frame {
1332
1333 u8 cmd; /*00h */
1334 u8 reserved_0; /*01h */
1335 u8 cmd_status; /*02h */
1336
1337 u8 reserved_1; /*03h */
1338 u32 reserved_2; /*04h */
1339
1340 u32 context; /*08h */
1341 u32 pad_0; /*0Ch */
1342
1343 u16 flags; /*10h */
1344 u16 reserved_3; /*12h */
1345 u32 reserved_4; /*14h */
1346
1347 u32 abort_context; /*18h */
1348 u32 pad_1; /*1Ch */
1349
1350 u32 abort_mfi_phys_addr_lo; /*20h */
1351 u32 abort_mfi_phys_addr_hi; /*24h */
1352
1353 u32 reserved_5[6]; /*28h */
1354
1355} __attribute__ ((packed));
1356
1357struct megasas_smp_frame {
1358
1359 u8 cmd; /*00h */
1360 u8 reserved_1; /*01h */
1361 u8 cmd_status; /*02h */
1362 u8 connection_status; /*03h */
1363
1364 u8 reserved_2[3]; /*04h */
1365 u8 sge_count; /*07h */
1366
1367 u32 context; /*08h */
1368 u32 pad_0; /*0Ch */
1369
1370 u16 flags; /*10h */
1371 u16 timeout; /*12h */
1372
1373 u32 data_xfer_len; /*14h */
1374 u64 sas_addr; /*18h */
1375
1376 union {
1377 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: req */
1378 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: req */
1379 } sgl;
1380
1381} __attribute__ ((packed));
1382
1383struct megasas_stp_frame {
1384
1385 u8 cmd; /*00h */
1386 u8 reserved_1; /*01h */
1387 u8 cmd_status; /*02h */
1388 u8 reserved_2; /*03h */
1389
1390 u8 target_id; /*04h */
1391 u8 reserved_3[2]; /*05h */
1392 u8 sge_count; /*07h */
1393
1394 u32 context; /*08h */
1395 u32 pad_0; /*0Ch */
1396
1397 u16 flags; /*10h */
1398 u16 timeout; /*12h */
1399
1400 u32 data_xfer_len; /*14h */
1401
1402 u16 fis[10]; /*18h */
1403 u32 stp_flags;
1404
1405 union {
1406 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: data */
1407 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: data */
1408 } sgl;
1409
1410} __attribute__ ((packed));
1411
1412union megasas_frame {
1413
1414 struct megasas_header hdr;
1415 struct megasas_init_frame init;
1416 struct megasas_io_frame io;
1417 struct megasas_pthru_frame pthru;
1418 struct megasas_dcmd_frame dcmd;
1419 struct megasas_abort_frame abort;
1420 struct megasas_smp_frame smp;
1421 struct megasas_stp_frame stp;
1422
1423 u8 raw_bytes[64];
1424};
1425
1426struct megasas_cmd;
1427
1428union megasas_evt_class_locale {
1429
1430 struct {
be26374b 1431#ifndef __BIG_ENDIAN_BITFIELD
c4a3e0a5
BS		 1432 u16 locale;
1433 u8 reserved;
1434 s8 class;
be26374b
SS		 1435#else
1436 s8 class;
1437 u8 reserved;
1438 u16 locale;
1439#endif
c4a3e0a5
BS		 1440 } __attribute__ ((packed)) members;
1441
1442 u32 word;
1443
1444} __attribute__ ((packed));
1445
1446struct megasas_evt_log_info {
1447 u32 newest_seq_num;
1448 u32 oldest_seq_num;
1449 u32 clear_seq_num;
1450 u32 shutdown_seq_num;
1451 u32 boot_seq_num;
1452
1453} __attribute__ ((packed));
1454
1455struct megasas_progress {
1456
1457 u16 progress;
1458 u16 elapsed_seconds;
1459
1460} __attribute__ ((packed));
1461
1462struct megasas_evtarg_ld {
1463
1464 u16 target_id;
1465 u8 ld_index;
1466 u8 reserved;
1467
1468} __attribute__ ((packed));
1469
1470struct megasas_evtarg_pd {
1471 u16 device_id;
1472 u8 encl_index;
1473 u8 slot_number;
1474
1475} __attribute__ ((packed));
1476
1477struct megasas_evt_detail {
1478
1479 u32 seq_num;
1480 u32 time_stamp;
1481 u32 code;
1482 union megasas_evt_class_locale cl;
1483 u8 arg_type;
1484 u8 reserved1[15];
1485
1486 union {
1487 struct {
1488 struct megasas_evtarg_pd pd;
1489 u8 cdb_length;
1490 u8 sense_length;
1491 u8 reserved[2];
1492 u8 cdb[16];
1493 u8 sense[64];
1494 } __attribute__ ((packed)) cdbSense;
1495
1496 struct megasas_evtarg_ld ld;
1497
1498 struct {
1499 struct megasas_evtarg_ld ld;
1500 u64 count;
1501 } __attribute__ ((packed)) ld_count;
1502
1503 struct {
1504 u64 lba;
1505 struct megasas_evtarg_ld ld;
1506 } __attribute__ ((packed)) ld_lba;
1507
1508 struct {
1509 struct megasas_evtarg_ld ld;
1510 u32 prevOwner;
1511 u32 newOwner;
1512 } __attribute__ ((packed)) ld_owner;
1513
1514 struct {
1515 u64 ld_lba;
1516 u64 pd_lba;
1517 struct megasas_evtarg_ld ld;
1518 struct megasas_evtarg_pd pd;
1519 } __attribute__ ((packed)) ld_lba_pd_lba;
1520
1521 struct {
1522 struct megasas_evtarg_ld ld;
1523 struct megasas_progress prog;
1524 } __attribute__ ((packed)) ld_prog;
1525
1526 struct {
1527 struct megasas_evtarg_ld ld;
1528 u32 prev_state;
1529 u32 new_state;
1530 } __attribute__ ((packed)) ld_state;
1531
1532 struct {
1533 u64 strip;
1534 struct megasas_evtarg_ld ld;
1535 } __attribute__ ((packed)) ld_strip;
1536
1537 struct megasas_evtarg_pd pd;
1538
1539 struct {
1540 struct megasas_evtarg_pd pd;
1541 u32 err;
1542 } __attribute__ ((packed)) pd_err;
1543
1544 struct {
1545 u64 lba;
1546 struct megasas_evtarg_pd pd;
1547 } __attribute__ ((packed)) pd_lba;
1548
1549 struct {
1550 u64 lba;
1551 struct megasas_evtarg_pd pd;
1552 struct megasas_evtarg_ld ld;
1553 } __attribute__ ((packed)) pd_lba_ld;
1554
1555 struct {
1556 struct megasas_evtarg_pd pd;
1557 struct megasas_progress prog;
1558 } __attribute__ ((packed)) pd_prog;
1559
1560 struct {
1561 struct megasas_evtarg_pd pd;
1562 u32 prevState;
1563 u32 newState;
1564 } __attribute__ ((packed)) pd_state;
1565
1566 struct {
1567 u16 vendorId;
1568 u16 deviceId;
1569 u16 subVendorId;
1570 u16 subDeviceId;
1571 } __attribute__ ((packed)) pci;
1572
1573 u32 rate;
1574 char str[96];
1575
1576 struct {
1577 u32 rtc;
1578 u32 elapsedSeconds;
1579 } __attribute__ ((packed)) time;
1580
1581 struct {
1582 u32 ecar;
1583 u32 elog;
1584 char str[64];
1585 } __attribute__ ((packed)) ecc;
1586
1587 u8 b[96];
1588 u16 s[48];
1589 u32 w[24];
1590 u64 d[12];
1591 } args;
1592
1593 char description[128];
1594
1595} __attribute__ ((packed));
1596
7e8a75f4 1597struct megasas_aen_event {
c1d390d8 1598 struct delayed_work hotplug_work;
7e8a75f4
YB		 1599 struct megasas_instance *instance;
1600};
1601
c8e858fe
AR		 1602struct megasas_irq_context {
1603 struct megasas_instance *instance;
1604 u32 MSIxIndex;
1605};
1606
c4a3e0a5
BS		 1607struct megasas_instance {
1608
1609 u32 *producer;
1610 dma_addr_t producer_h;
1611 u32 *consumer;
1612 dma_addr_t consumer_h;
229fe47c
AR		 1613 struct MR_LD_VF_AFFILIATION *vf_affiliation;
1614 dma_addr_t vf_affiliation_h;
1615 struct MR_LD_VF_AFFILIATION_111 *vf_affiliation_111;
1616 dma_addr_t vf_affiliation_111_h;
1617 struct MR_CTRL_HB_HOST_MEM *hb_host_mem;
1618 dma_addr_t hb_host_mem_h;
c4a3e0a5
BS		 1619
1620 u32 *reply_queue;
1621 dma_addr_t reply_queue_h;
1622
fc62b3fc
SS		 1623 u32 *crash_dump_buf;
1624 dma_addr_t crash_dump_h;
1625 void *crash_buf[MAX_CRASH_DUMP_SIZE];
1626 u32 crash_buf_pages;
1627 unsigned int fw_crash_buffer_size;
1628 unsigned int fw_crash_state;
1629 unsigned int fw_crash_buffer_offset;
1630 u32 drv_buf_index;
1631 u32 drv_buf_alloc;
1632 u32 crash_dump_fw_support;
1633 u32 crash_dump_drv_support;
1634 u32 crash_dump_app_support;
1635 spinlock_t crashdump_lock;
1636
c4a3e0a5 1637 struct megasas_register_set __iomem *reg_set;
d46a3ad6 1638 u32 *reply_post_host_index_addr[MR_MAX_MSIX_REG_ARRAY];
81e403ce 1639 struct megasas_pd_list pd_list[MEGASAS_MAX_PD];
999ece0a 1640 struct megasas_pd_list local_pd_list[MEGASAS_MAX_PD];
bdc6fb8d 1641 u8 ld_ids[MEGASAS_MAX_LD_IDS];
c4a3e0a5 1642 s8 init_id;
c4a3e0a5
BS		 1643
1644 u16 max_num_sge;
1645 u16 max_fw_cmds;
9c915a8c
AR		 1646 /* For Fusion its num IOCTL cmds, for others MFI based its
1647 max_fw_cmds */
1648 u16 max_mfi_cmds;
c4a3e0a5 1649 u32 max_sectors_per_req;
7e8a75f4 1650 struct megasas_aen_event *ev;
c4a3e0a5
BS		 1651
1652 struct megasas_cmd **cmd_list;
1653 struct list_head cmd_pool;
39a98554 1654 /* used to sync fire the cmd to fw */
c4a3e0a5 1655 spinlock_t cmd_pool_lock;
39a98554 1656 /* used to sync fire the cmd to fw */
1657 spinlock_t hba_lock;
7343eb65 1658 /* used to synch producer, consumer ptrs in dpc */
1659 spinlock_t completion_lock;
c4a3e0a5
BS		 1660 struct dma_pool *frame_dma_pool;
1661 struct dma_pool *sense_dma_pool;
1662
1663 struct megasas_evt_detail *evt_detail;
1664 dma_addr_t evt_detail_h;
1665 struct megasas_cmd *aen_cmd;
e5a69e27 1666 struct mutex aen_mutex;
c4a3e0a5
BS		 1667 struct semaphore ioctl_sem;
1668
1669 struct Scsi_Host *host;
1670
1671 wait_queue_head_t int_cmd_wait_q;
1672 wait_queue_head_t abort_cmd_wait_q;
1673
1674 struct pci_dev *pdev;
1675 u32 unique_id;
39a98554 1676 u32 fw_support_ieee;
c4a3e0a5 1677
e4a082c7 1678 atomic_t fw_outstanding;
39a98554 1679 atomic_t fw_reset_no_pci_access;
1341c939
SP		 1680
1681 struct megasas_instance_template *instancet;
5d018ad0 1682 struct tasklet_struct isr_tasklet;
39a98554 1683 struct work_struct work_init;
fc62b3fc 1684 struct work_struct crash_init;
05e9ebbe
SP		 1685
1686 u8 flag;
c3518837 1687 u8 unload;
f4c9a131 1688 u8 flag_ieee;
39a98554 1689 u8 issuepend_done;
1690 u8 disableOnlineCtrlReset;
bc93d425 1691 u8 UnevenSpanSupport;
51087a86
SS		 1692
1693 u8 supportmax256vd;
1694 u16 fw_supported_vd_count;
1695 u16 fw_supported_pd_count;
1696
1697 u16 drv_supported_vd_count;
1698 u16 drv_supported_pd_count;
1699
39a98554 1700 u8 adprecovery;
05e9ebbe 1701 unsigned long last_time;
39a98554 1702 u32 mfiStatus;
1703 u32 last_seq_num;
ad84db2e 1704
39a98554 1705 struct list_head internal_reset_pending_q;
80d9da98 1706
25985edc 1707 /* Ptr to hba specific information */
9c915a8c 1708 void *ctrl_context;
51087a86
SS		 1709 u32 ctrl_context_pages;
1710 struct megasas_ctrl_info *ctrl_info;
c8e858fe
AR		 1711 unsigned int msix_vectors;
1712 struct msix_entry msixentry[MEGASAS_MAX_MSIX_QUEUES];
1713 struct megasas_irq_context irq_context[MEGASAS_MAX_MSIX_QUEUES];
9c915a8c
AR		 1714 u64 map_id;
1715 struct megasas_cmd *map_update_cmd;
b6d5d880 1716 unsigned long bar;
9c915a8c
AR		 1717 long reset_flags;
1718 struct mutex reset_mutex;
229fe47c
AR		 1719 struct timer_list sriov_heartbeat_timer;
1720 char skip_heartbeat_timer_del;
1721 u8 requestorId;
229fe47c
AR		 1722 char PlasmaFW111;
1723 char mpio;
c5daa6a9 1724 int throttlequeuedepth;
d46a3ad6 1725 u8 mask_interrupts;
404a8a1a 1726 u8 is_imr;
39a98554 1727};
229fe47c
AR		 1728struct MR_LD_VF_MAP {
1729 u32 size;
1730 union MR_LD_REF ref;
1731 u8 ldVfCount;
1732 u8 reserved[6];
1733 u8 policy[1];
1734};
1735
1736struct MR_LD_VF_AFFILIATION {
1737 u32 size;
1738 u8 ldCount;
1739 u8 vfCount;
1740 u8 thisVf;
1741 u8 reserved[9];
1742 struct MR_LD_VF_MAP map[1];
1743};
1744
1745/* Plasma 1.11 FW backward compatibility structures */
1746#define IOV_111_OFFSET 0x7CE
1747#define MAX_VIRTUAL_FUNCTIONS 8
4cbfea88 1748#define MR_LD_ACCESS_HIDDEN 15
229fe47c
AR		 1749
1750struct IOV_111 {
1751 u8 maxVFsSupported;
1752 u8 numVFsEnabled;
1753 u8 requestorId;
1754 u8 reserved[5];
1755};
1756
1757struct MR_LD_VF_MAP_111 {
1758 u8 targetId;
1759 u8 reserved[3];
1760 u8 policy[MAX_VIRTUAL_FUNCTIONS];
1761};
1762
1763struct MR_LD_VF_AFFILIATION_111 {
1764 u8 vdCount;
1765 u8 vfCount;
1766 u8 thisVf;
1767 u8 reserved[5];
1768 struct MR_LD_VF_MAP_111 map[MAX_LOGICAL_DRIVES];
1769};
1770
1771struct MR_CTRL_HB_HOST_MEM {
1772 struct {
1773 u32 fwCounter; /* Firmware heart beat counter */
1774 struct {
1775 u32 debugmode:1; /* 1=Firmware is in debug mode.
1776 Heart beat will not be updated. */
1777 u32 reserved:31;
1778 } debug;
1779 u32 reserved_fw[6];
1780 u32 driverCounter; /* Driver heart beat counter. 0x20 */
1781 u32 reserved_driver[7];
1782 } HB;
1783 u8 pad[0x400-0x40];
1784};
39a98554 1785
1786enum {
1787 MEGASAS_HBA_OPERATIONAL = 0,
1788 MEGASAS_ADPRESET_SM_INFAULT = 1,
1789 MEGASAS_ADPRESET_SM_FW_RESET_SUCCESS = 2,
1790 MEGASAS_ADPRESET_SM_OPERATIONAL = 3,
1791 MEGASAS_HW_CRITICAL_ERROR = 4,
229fe47c 1792 MEGASAS_ADPRESET_SM_POLLING = 5,
39a98554 1793 MEGASAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD,
c4a3e0a5
BS		 1794};
1795
0c79e681
YB		 1796struct megasas_instance_template {
1797 void (*fire_cmd)(struct megasas_instance *, dma_addr_t, \
1798 u32, struct megasas_register_set __iomem *);
1799
d46a3ad6
SS		 1800 void (*enable_intr)(struct megasas_instance *);
1801 void (*disable_intr)(struct megasas_instance *);
0c79e681
YB		 1802
1803 int (*clear_intr)(struct megasas_register_set __iomem *);
1804
1805 u32 (*read_fw_status_reg)(struct megasas_register_set __iomem *);
39a98554 1806 int (*adp_reset)(struct megasas_instance *, \
1807 struct megasas_register_set __iomem *);
1808 int (*check_reset)(struct megasas_instance *, \
1809 struct megasas_register_set __iomem *);
cd50ba8e
AR		 1810 irqreturn_t (*service_isr)(int irq, void *devp);
1811 void (*tasklet)(unsigned long);
1812 u32 (*init_adapter)(struct megasas_instance *);
1813 u32 (*build_and_issue_cmd) (struct megasas_instance *,
1814 struct scsi_cmnd *);
1815 void (*issue_dcmd) (struct megasas_instance *instance,
1816 struct megasas_cmd *cmd);
0c79e681
YB		 1817};
1818
c4a3e0a5
BS		 1819#define MEGASAS_IS_LOGICAL(scp) \
1820 (scp->device->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1
1821
1822#define MEGASAS_DEV_INDEX(inst, scp) \
1823 ((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + \
1824 scp->device->id
1825
1826struct megasas_cmd {
1827
1828 union megasas_frame *frame;
1829 dma_addr_t frame_phys_addr;
1830 u8 *sense;
1831 dma_addr_t sense_phys_addr;
1832
1833 u32 index;
1834 u8 sync_cmd;
1835 u8 cmd_status;
39a98554 1836 u8 abort_aen;
1837 u8 retry_for_fw_reset;
1838
c4a3e0a5
BS		 1839
1840 struct list_head list;
1841 struct scsi_cmnd *scmd;
1842 struct megasas_instance *instance;
9c915a8c
AR		 1843 union {
1844 struct {
1845 u16 smid;
1846 u16 resvd;
1847 } context;
1848 u32 frame_count;
1849 };
c4a3e0a5
BS		 1850};
1851
1852#define MAX_MGMT_ADAPTERS 1024
1853#define MAX_IOCTL_SGE 16
1854
1855struct megasas_iocpacket {
1856
1857 u16 host_no;
1858 u16 __pad1;
1859 u32 sgl_off;
1860 u32 sge_count;
1861 u32 sense_off;
1862 u32 sense_len;
1863 union {
1864 u8 raw[128];
1865 struct megasas_header hdr;
1866 } frame;
1867
1868 struct iovec sgl[MAX_IOCTL_SGE];
1869
1870} __attribute__ ((packed));
1871
1872struct megasas_aen {
1873 u16 host_no;
1874 u16 __pad1;
1875 u32 seq_num;
1876 u32 class_locale_word;
1877} __attribute__ ((packed));
1878
1879#ifdef CONFIG_COMPAT
1880struct compat_megasas_iocpacket {
1881 u16 host_no;
1882 u16 __pad1;
1883 u32 sgl_off;
1884 u32 sge_count;
1885 u32 sense_off;
1886 u32 sense_len;
1887 union {
1888 u8 raw[128];
1889 struct megasas_header hdr;
1890 } frame;
1891 struct compat_iovec sgl[MAX_IOCTL_SGE];
1892} __attribute__ ((packed));
1893
0e98936c 1894#define MEGASAS_IOC_FIRMWARE32 _IOWR('M', 1, struct compat_megasas_iocpacket)
c4a3e0a5
BS		 1895#endif
1896
cb59aa6a 1897#define MEGASAS_IOC_FIRMWARE _IOWR('M', 1, struct megasas_iocpacket)
c4a3e0a5
BS		 1898#define MEGASAS_IOC_GET_AEN _IOW('M', 3, struct megasas_aen)
1899
1900struct megasas_mgmt_info {
1901
1902 u16 count;
1903 struct megasas_instance *instance[MAX_MGMT_ADAPTERS];
1904 int max_index;
1905};
1906
21c9e160
AR		 1907u8
1908MR_BuildRaidContext(struct megasas_instance *instance,
1909 struct IO_REQUEST_INFO *io_info,
1910 struct RAID_CONTEXT *pRAID_Context,
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SS		 1911 struct MR_DRV_RAID_MAP_ALL *map, u8 **raidLUN);
1912u8 MR_TargetIdToLdGet(u32 ldTgtId, struct MR_DRV_RAID_MAP_ALL *map);
1913struct MR_LD_RAID *MR_LdRaidGet(u32 ld, struct MR_DRV_RAID_MAP_ALL *map);
1914u16 MR_ArPdGet(u32 ar, u32 arm, struct MR_DRV_RAID_MAP_ALL *map);
1915u16 MR_LdSpanArrayGet(u32 ld, u32 span, struct MR_DRV_RAID_MAP_ALL *map);
1916u16 MR_PdDevHandleGet(u32 pd, struct MR_DRV_RAID_MAP_ALL *map);
1917u16 MR_GetLDTgtId(u32 ld, struct MR_DRV_RAID_MAP_ALL *map);
1918
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SS		 1919u16 get_updated_dev_handle(struct megasas_instance *instance,
1920 struct LD_LOAD_BALANCE_INFO *lbInfo, struct IO_REQUEST_INFO *in_info);
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SS		 1921void mr_update_load_balance_params(struct MR_DRV_RAID_MAP_ALL *map,
1922 struct LD_LOAD_BALANCE_INFO *lbInfo);
1923int megasas_get_ctrl_info(struct megasas_instance *instance,
1924 struct megasas_ctrl_info *ctrl_info);
fc62b3fc 1925int megasas_set_crash_dump_params(struct megasas_instance *instance,
51087a86 1926 u8 crash_buf_state);
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SS		 1927void megasas_free_host_crash_buffer(struct megasas_instance *instance);
1928void megasas_fusion_crash_dump_wq(struct work_struct *work);
51087a86 1929
c4a3e0a5 1930#endif /*LSI_MEGARAID_SAS_H */
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