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9c915a8c AR |
1 | /* |
2 | * Linux MegaRAID driver for SAS based RAID controllers | |
3 | * | |
e399065b SS |
4 | * Copyright (c) 2009-2013 LSI Corporation |
5 | * Copyright (c) 2013-2014 Avago Technologies | |
9c915a8c AR |
6 | * |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; either version 2 | |
10 | * of the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
e399065b | 18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
9c915a8c AR |
19 | * |
20 | * FILE: megaraid_sas_fp.c | |
21 | * | |
e399065b | 22 | * Authors: Avago Technologies |
9c915a8c AR |
23 | * Sumant Patro |
24 | * Varad Talamacki | |
25 | * Manoj Jose | |
e399065b SS |
26 | * Kashyap Desai <kashyap.desai@avagotech.com> |
27 | * Sumit Saxena <sumit.saxena@avagotech.com> | |
9c915a8c | 28 | * |
e399065b | 29 | * Send feedback to: megaraidlinux.pdl@avagotech.com |
9c915a8c | 30 | * |
e399065b SS |
31 | * Mail to: Avago Technologies, 350 West Trimble Road, Building 90, |
32 | * San Jose, California 95131 | |
9c915a8c AR |
33 | */ |
34 | ||
35 | #include <linux/kernel.h> | |
36 | #include <linux/types.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/list.h> | |
39 | #include <linux/moduleparam.h> | |
40 | #include <linux/module.h> | |
41 | #include <linux/spinlock.h> | |
42 | #include <linux/interrupt.h> | |
43 | #include <linux/delay.h> | |
9c915a8c AR |
44 | #include <linux/uio.h> |
45 | #include <linux/uaccess.h> | |
46 | #include <linux/fs.h> | |
47 | #include <linux/compat.h> | |
48 | #include <linux/blkdev.h> | |
49 | #include <linux/poll.h> | |
50 | ||
51 | #include <scsi/scsi.h> | |
52 | #include <scsi/scsi_cmnd.h> | |
53 | #include <scsi/scsi_device.h> | |
54 | #include <scsi/scsi_host.h> | |
55 | ||
56 | #include "megaraid_sas_fusion.h" | |
36807e67 | 57 | #include "megaraid_sas.h" |
9c915a8c AR |
58 | #include <asm/div64.h> |
59 | ||
d2552ebe SS |
60 | #define LB_PENDING_CMDS_DEFAULT 4 |
61 | static unsigned int lb_pending_cmds = LB_PENDING_CMDS_DEFAULT; | |
62 | module_param(lb_pending_cmds, int, S_IRUGO); | |
63 | MODULE_PARM_DESC(lb_pending_cmds, "Change raid-1 load balancing outstanding " | |
64 | "threshold. Valid Values are 1-128. Default: 4"); | |
65 | ||
66 | ||
9c915a8c AR |
67 | #define ABS_DIFF(a, b) (((a) > (b)) ? ((a) - (b)) : ((b) - (a))) |
68 | #define MR_LD_STATE_OPTIMAL 3 | |
ad466c6c SS |
69 | |
70 | #ifdef FALSE | |
71 | #undef FALSE | |
72 | #endif | |
9c915a8c | 73 | #define FALSE 0 |
ad466c6c SS |
74 | |
75 | #ifdef TRUE | |
76 | #undef TRUE | |
77 | #endif | |
9c915a8c AR |
78 | #define TRUE 1 |
79 | ||
bc93d425 SS |
80 | #define SPAN_DEBUG 0 |
81 | #define SPAN_ROW_SIZE(map, ld, index_) (MR_LdSpanPtrGet(ld, index_, map)->spanRowSize) | |
82 | #define SPAN_ROW_DATA_SIZE(map_, ld, index_) (MR_LdSpanPtrGet(ld, index_, map)->spanRowDataSize) | |
83 | #define SPAN_INVALID 0xff | |
84 | ||
9c915a8c | 85 | /* Prototypes */ |
51087a86 | 86 | static void mr_update_span_set(struct MR_DRV_RAID_MAP_ALL *map, |
bc93d425 SS |
87 | PLD_SPAN_INFO ldSpanInfo); |
88 | static u8 mr_spanset_get_phy_params(struct megasas_instance *instance, u32 ld, | |
89 | u64 stripRow, u16 stripRef, struct IO_REQUEST_INFO *io_info, | |
51087a86 | 90 | struct RAID_CONTEXT *pRAID_Context, struct MR_DRV_RAID_MAP_ALL *map); |
bc93d425 | 91 | static u64 get_row_from_strip(struct megasas_instance *instance, u32 ld, |
51087a86 | 92 | u64 strip, struct MR_DRV_RAID_MAP_ALL *map); |
9c915a8c AR |
93 | |
94 | u32 mega_mod64(u64 dividend, u32 divisor) | |
95 | { | |
96 | u64 d; | |
97 | u32 remainder; | |
98 | ||
99 | if (!divisor) | |
100 | printk(KERN_ERR "megasas : DIVISOR is zero, in div fn\n"); | |
101 | d = dividend; | |
102 | remainder = do_div(d, divisor); | |
103 | return remainder; | |
104 | } | |
105 | ||
106 | /** | |
107 | * @param dividend : Dividend | |
108 | * @param divisor : Divisor | |
109 | * | |
110 | * @return quotient | |
111 | **/ | |
112 | u64 mega_div64_32(uint64_t dividend, uint32_t divisor) | |
113 | { | |
114 | u32 remainder; | |
115 | u64 d; | |
116 | ||
117 | if (!divisor) | |
118 | printk(KERN_ERR "megasas : DIVISOR is zero in mod fn\n"); | |
119 | ||
120 | d = dividend; | |
121 | remainder = do_div(d, divisor); | |
122 | ||
123 | return d; | |
124 | } | |
125 | ||
51087a86 | 126 | struct MR_LD_RAID *MR_LdRaidGet(u32 ld, struct MR_DRV_RAID_MAP_ALL *map) |
9c915a8c AR |
127 | { |
128 | return &map->raidMap.ldSpanMap[ld].ldRaid; | |
129 | } | |
130 | ||
131 | static struct MR_SPAN_BLOCK_INFO *MR_LdSpanInfoGet(u32 ld, | |
51087a86 | 132 | struct MR_DRV_RAID_MAP_ALL |
9c915a8c AR |
133 | *map) |
134 | { | |
135 | return &map->raidMap.ldSpanMap[ld].spanBlock[0]; | |
136 | } | |
137 | ||
51087a86 | 138 | static u8 MR_LdDataArmGet(u32 ld, u32 armIdx, struct MR_DRV_RAID_MAP_ALL *map) |
9c915a8c AR |
139 | { |
140 | return map->raidMap.ldSpanMap[ld].dataArmMap[armIdx]; | |
141 | } | |
142 | ||
51087a86 | 143 | u16 MR_ArPdGet(u32 ar, u32 arm, struct MR_DRV_RAID_MAP_ALL *map) |
9c915a8c | 144 | { |
94cd65dd | 145 | return le16_to_cpu(map->raidMap.arMapInfo[ar].pd[arm]); |
9c915a8c AR |
146 | } |
147 | ||
51087a86 | 148 | u16 MR_LdSpanArrayGet(u32 ld, u32 span, struct MR_DRV_RAID_MAP_ALL *map) |
9c915a8c | 149 | { |
94cd65dd | 150 | return le16_to_cpu(map->raidMap.ldSpanMap[ld].spanBlock[span].span.arrayRef); |
9c915a8c AR |
151 | } |
152 | ||
9ab9ed38 | 153 | __le16 MR_PdDevHandleGet(u32 pd, struct MR_DRV_RAID_MAP_ALL *map) |
9c915a8c AR |
154 | { |
155 | return map->raidMap.devHndlInfo[pd].curDevHdl; | |
156 | } | |
157 | ||
51087a86 | 158 | u16 MR_GetLDTgtId(u32 ld, struct MR_DRV_RAID_MAP_ALL *map) |
9c915a8c | 159 | { |
be26374b | 160 | return le16_to_cpu(map->raidMap.ldSpanMap[ld].ldRaid.targetId); |
9c915a8c AR |
161 | } |
162 | ||
51087a86 | 163 | u8 MR_TargetIdToLdGet(u32 ldTgtId, struct MR_DRV_RAID_MAP_ALL *map) |
9c915a8c | 164 | { |
be26374b | 165 | return map->raidMap.ldTgtIdToLd[ldTgtId]; |
9c915a8c AR |
166 | } |
167 | ||
168 | static struct MR_LD_SPAN *MR_LdSpanPtrGet(u32 ld, u32 span, | |
51087a86 | 169 | struct MR_DRV_RAID_MAP_ALL *map) |
9c915a8c AR |
170 | { |
171 | return &map->raidMap.ldSpanMap[ld].spanBlock[span].span; | |
172 | } | |
173 | ||
51087a86 SS |
174 | /* |
175 | * This function will Populate Driver Map using firmware raid map | |
176 | */ | |
177 | void MR_PopulateDrvRaidMap(struct megasas_instance *instance) | |
178 | { | |
179 | struct fusion_context *fusion = instance->ctrl_context; | |
180 | struct MR_FW_RAID_MAP_ALL *fw_map_old = NULL; | |
181 | struct MR_FW_RAID_MAP *pFwRaidMap = NULL; | |
182 | int i; | |
200aed58 | 183 | u16 ld_count; |
51087a86 SS |
184 | |
185 | ||
186 | struct MR_DRV_RAID_MAP_ALL *drv_map = | |
187 | fusion->ld_drv_map[(instance->map_id & 1)]; | |
188 | struct MR_DRV_RAID_MAP *pDrvRaidMap = &drv_map->raidMap; | |
189 | ||
190 | if (instance->supportmax256vd) { | |
191 | memcpy(fusion->ld_drv_map[instance->map_id & 1], | |
192 | fusion->ld_map[instance->map_id & 1], | |
193 | fusion->current_map_sz); | |
194 | /* New Raid map will not set totalSize, so keep expected value | |
195 | * for legacy code in ValidateMapInfo | |
196 | */ | |
6e755ddc SS |
197 | pDrvRaidMap->totalSize = |
198 | cpu_to_le32(sizeof(struct MR_FW_RAID_MAP_EXT)); | |
51087a86 SS |
199 | } else { |
200 | fw_map_old = (struct MR_FW_RAID_MAP_ALL *) | |
201 | fusion->ld_map[(instance->map_id & 1)]; | |
202 | pFwRaidMap = &fw_map_old->raidMap; | |
200aed58 | 203 | ld_count = (u16)le32_to_cpu(pFwRaidMap->ldCount); |
51087a86 SS |
204 | |
205 | #if VD_EXT_DEBUG | |
200aed58 | 206 | for (i = 0; i < ld_count; i++) { |
51087a86 SS |
207 | dev_dbg(&instance->pdev->dev, "(%d) :Index 0x%x " |
208 | "Target Id 0x%x Seq Num 0x%x Size 0/%llx\n", | |
209 | instance->unique_id, i, | |
210 | fw_map_old->raidMap.ldSpanMap[i].ldRaid.targetId, | |
211 | fw_map_old->raidMap.ldSpanMap[i].ldRaid.seqNum, | |
212 | fw_map_old->raidMap.ldSpanMap[i].ldRaid.size); | |
213 | } | |
214 | #endif | |
215 | ||
216 | memset(drv_map, 0, fusion->drv_map_sz); | |
217 | pDrvRaidMap->totalSize = pFwRaidMap->totalSize; | |
200aed58 | 218 | pDrvRaidMap->ldCount = (__le16)cpu_to_le16(ld_count); |
51087a86 SS |
219 | pDrvRaidMap->fpPdIoTimeoutSec = pFwRaidMap->fpPdIoTimeoutSec; |
220 | for (i = 0; i < MAX_RAIDMAP_LOGICAL_DRIVES + MAX_RAIDMAP_VIEWS; i++) | |
221 | pDrvRaidMap->ldTgtIdToLd[i] = | |
222 | (u8)pFwRaidMap->ldTgtIdToLd[i]; | |
ab2f0608 SS |
223 | for (i = (MAX_RAIDMAP_LOGICAL_DRIVES + MAX_RAIDMAP_VIEWS); |
224 | i < MAX_LOGICAL_DRIVES_EXT; i++) | |
225 | pDrvRaidMap->ldTgtIdToLd[i] = 0xff; | |
200aed58 | 226 | for (i = 0; i < ld_count; i++) { |
51087a86 SS |
227 | pDrvRaidMap->ldSpanMap[i] = pFwRaidMap->ldSpanMap[i]; |
228 | #if VD_EXT_DEBUG | |
229 | dev_dbg(&instance->pdev->dev, | |
230 | "pFwRaidMap->ldSpanMap[%d].ldRaid.targetId 0x%x " | |
231 | "pFwRaidMap->ldSpanMap[%d].ldRaid.seqNum 0x%x " | |
232 | "size 0x%x\n", i, i, | |
233 | pFwRaidMap->ldSpanMap[i].ldRaid.targetId, | |
234 | pFwRaidMap->ldSpanMap[i].ldRaid.seqNum, | |
235 | (u32)pFwRaidMap->ldSpanMap[i].ldRaid.rowSize); | |
236 | dev_dbg(&instance->pdev->dev, | |
237 | "pDrvRaidMap->ldSpanMap[%d].ldRaid.targetId 0x%x " | |
238 | "pDrvRaidMap->ldSpanMap[%d].ldRaid.seqNum 0x%x " | |
239 | "size 0x%x\n", i, i, | |
240 | pDrvRaidMap->ldSpanMap[i].ldRaid.targetId, | |
241 | pDrvRaidMap->ldSpanMap[i].ldRaid.seqNum, | |
242 | (u32)pDrvRaidMap->ldSpanMap[i].ldRaid.rowSize); | |
243 | dev_dbg(&instance->pdev->dev, "Driver raid map all %p " | |
244 | "raid map %p LD RAID MAP %p/%p\n", drv_map, | |
245 | pDrvRaidMap, &pFwRaidMap->ldSpanMap[i].ldRaid, | |
246 | &pDrvRaidMap->ldSpanMap[i].ldRaid); | |
247 | #endif | |
248 | } | |
249 | memcpy(pDrvRaidMap->arMapInfo, pFwRaidMap->arMapInfo, | |
250 | sizeof(struct MR_ARRAY_INFO) * MAX_RAIDMAP_ARRAYS); | |
251 | memcpy(pDrvRaidMap->devHndlInfo, pFwRaidMap->devHndlInfo, | |
252 | sizeof(struct MR_DEV_HANDLE_INFO) * | |
253 | MAX_RAIDMAP_PHYSICAL_DEVICES); | |
254 | } | |
255 | } | |
256 | ||
9c915a8c AR |
257 | /* |
258 | * This function will validate Map info data provided by FW | |
259 | */ | |
bc93d425 | 260 | u8 MR_ValidateMapInfo(struct megasas_instance *instance) |
9c915a8c | 261 | { |
51087a86 SS |
262 | struct fusion_context *fusion; |
263 | struct MR_DRV_RAID_MAP_ALL *drv_map; | |
264 | struct MR_DRV_RAID_MAP *pDrvRaidMap; | |
265 | struct LD_LOAD_BALANCE_INFO *lbInfo; | |
266 | PLD_SPAN_INFO ldSpanInfo; | |
94cd65dd | 267 | struct MR_LD_RAID *raid; |
200aed58 | 268 | u16 ldCount, num_lds; |
94cd65dd | 269 | u16 ld; |
51087a86 | 270 | u32 expected_size; |
94cd65dd | 271 | |
9c915a8c | 272 | |
51087a86 SS |
273 | MR_PopulateDrvRaidMap(instance); |
274 | ||
275 | fusion = instance->ctrl_context; | |
276 | drv_map = fusion->ld_drv_map[(instance->map_id & 1)]; | |
277 | pDrvRaidMap = &drv_map->raidMap; | |
278 | ||
279 | lbInfo = fusion->load_balance_info; | |
280 | ldSpanInfo = fusion->log_to_span; | |
281 | ||
282 | if (instance->supportmax256vd) | |
283 | expected_size = sizeof(struct MR_FW_RAID_MAP_EXT); | |
284 | else | |
285 | expected_size = | |
286 | (sizeof(struct MR_FW_RAID_MAP) - sizeof(struct MR_LD_SPAN_MAP) + | |
6e755ddc | 287 | (sizeof(struct MR_LD_SPAN_MAP) * le16_to_cpu(pDrvRaidMap->ldCount))); |
51087a86 SS |
288 | |
289 | if (le32_to_cpu(pDrvRaidMap->totalSize) != expected_size) { | |
290 | dev_err(&instance->pdev->dev, "map info structure size 0x%x is not matching with ld count\n", | |
291 | (unsigned int) expected_size); | |
292 | dev_err(&instance->pdev->dev, "megasas: span map %x, pDrvRaidMap->totalSize : %x\n", | |
293 | (unsigned int)sizeof(struct MR_LD_SPAN_MAP), | |
294 | le32_to_cpu(pDrvRaidMap->totalSize)); | |
9c915a8c AR |
295 | return 0; |
296 | } | |
297 | ||
bc93d425 | 298 | if (instance->UnevenSpanSupport) |
51087a86 | 299 | mr_update_span_set(drv_map, ldSpanInfo); |
bc93d425 | 300 | |
51087a86 | 301 | mr_update_load_balance_params(drv_map, lbInfo); |
9c915a8c | 302 | |
6e755ddc | 303 | num_lds = le16_to_cpu(drv_map->raidMap.ldCount); |
94cd65dd SS |
304 | |
305 | /*Convert Raid capability values to CPU arch */ | |
306 | for (ldCount = 0; ldCount < num_lds; ldCount++) { | |
51087a86 SS |
307 | ld = MR_TargetIdToLdGet(ldCount, drv_map); |
308 | raid = MR_LdRaidGet(ld, drv_map); | |
94cd65dd SS |
309 | le32_to_cpus((u32 *)&raid->capability); |
310 | } | |
311 | ||
9c915a8c AR |
312 | return 1; |
313 | } | |
314 | ||
315 | u32 MR_GetSpanBlock(u32 ld, u64 row, u64 *span_blk, | |
51087a86 | 316 | struct MR_DRV_RAID_MAP_ALL *map) |
9c915a8c AR |
317 | { |
318 | struct MR_SPAN_BLOCK_INFO *pSpanBlock = MR_LdSpanInfoGet(ld, map); | |
319 | struct MR_QUAD_ELEMENT *quad; | |
320 | struct MR_LD_RAID *raid = MR_LdRaidGet(ld, map); | |
321 | u32 span, j; | |
322 | ||
323 | for (span = 0; span < raid->spanDepth; span++, pSpanBlock++) { | |
324 | ||
94cd65dd | 325 | for (j = 0; j < le32_to_cpu(pSpanBlock->block_span_info.noElements); j++) { |
9c915a8c AR |
326 | quad = &pSpanBlock->block_span_info.quad[j]; |
327 | ||
94cd65dd | 328 | if (le32_to_cpu(quad->diff) == 0) |
bc93d425 | 329 | return SPAN_INVALID; |
94cd65dd SS |
330 | if (le64_to_cpu(quad->logStart) <= row && row <= |
331 | le64_to_cpu(quad->logEnd) && (mega_mod64(row - le64_to_cpu(quad->logStart), | |
332 | le32_to_cpu(quad->diff))) == 0) { | |
9c915a8c AR |
333 | if (span_blk != NULL) { |
334 | u64 blk, debugBlk; | |
94cd65dd | 335 | blk = mega_div64_32((row-le64_to_cpu(quad->logStart)), le32_to_cpu(quad->diff)); |
9c915a8c AR |
336 | debugBlk = blk; |
337 | ||
94cd65dd | 338 | blk = (blk + le64_to_cpu(quad->offsetInSpan)) << raid->stripeShift; |
9c915a8c AR |
339 | *span_blk = blk; |
340 | } | |
341 | return span; | |
342 | } | |
343 | } | |
344 | } | |
bc93d425 SS |
345 | return SPAN_INVALID; |
346 | } | |
347 | ||
348 | /* | |
349 | ****************************************************************************** | |
350 | * | |
351 | * Function to print info about span set created in driver from FW raid map | |
352 | * | |
353 | * Inputs : | |
354 | * map - LD map | |
355 | * ldSpanInfo - ldSpanInfo per HBA instance | |
356 | */ | |
357 | #if SPAN_DEBUG | |
51087a86 SS |
358 | static int getSpanInfo(struct MR_DRV_RAID_MAP_ALL *map, |
359 | PLD_SPAN_INFO ldSpanInfo) | |
bc93d425 SS |
360 | { |
361 | ||
362 | u8 span; | |
363 | u32 element; | |
364 | struct MR_LD_RAID *raid; | |
365 | LD_SPAN_SET *span_set; | |
366 | struct MR_QUAD_ELEMENT *quad; | |
367 | int ldCount; | |
368 | u16 ld; | |
369 | ||
51087a86 | 370 | for (ldCount = 0; ldCount < MAX_LOGICAL_DRIVES_EXT; ldCount++) { |
bc93d425 | 371 | ld = MR_TargetIdToLdGet(ldCount, map); |
200aed58 | 372 | if (ld >= (MAX_LOGICAL_DRIVES_EXT - 1)) |
bc93d425 SS |
373 | continue; |
374 | raid = MR_LdRaidGet(ld, map); | |
375 | dev_dbg(&instance->pdev->dev, "LD %x: span_depth=%x\n", | |
376 | ld, raid->spanDepth); | |
377 | for (span = 0; span < raid->spanDepth; span++) | |
378 | dev_dbg(&instance->pdev->dev, "Span=%x," | |
379 | " number of quads=%x\n", span, | |
94cd65dd SS |
380 | le32_to_cpu(map->raidMap.ldSpanMap[ld].spanBlock[span]. |
381 | block_span_info.noElements)); | |
bc93d425 SS |
382 | for (element = 0; element < MAX_QUAD_DEPTH; element++) { |
383 | span_set = &(ldSpanInfo[ld].span_set[element]); | |
384 | if (span_set->span_row_data_width == 0) | |
385 | break; | |
386 | ||
387 | dev_dbg(&instance->pdev->dev, "Span Set %x:" | |
388 | "width=%x, diff=%x\n", element, | |
389 | (unsigned int)span_set->span_row_data_width, | |
390 | (unsigned int)span_set->diff); | |
391 | dev_dbg(&instance->pdev->dev, "logical LBA" | |
392 | "start=0x%08lx, end=0x%08lx\n", | |
393 | (long unsigned int)span_set->log_start_lba, | |
394 | (long unsigned int)span_set->log_end_lba); | |
395 | dev_dbg(&instance->pdev->dev, "span row start=0x%08lx," | |
396 | " end=0x%08lx\n", | |
397 | (long unsigned int)span_set->span_row_start, | |
398 | (long unsigned int)span_set->span_row_end); | |
399 | dev_dbg(&instance->pdev->dev, "data row start=0x%08lx," | |
400 | " end=0x%08lx\n", | |
401 | (long unsigned int)span_set->data_row_start, | |
402 | (long unsigned int)span_set->data_row_end); | |
403 | dev_dbg(&instance->pdev->dev, "data strip start=0x%08lx," | |
404 | " end=0x%08lx\n", | |
405 | (long unsigned int)span_set->data_strip_start, | |
406 | (long unsigned int)span_set->data_strip_end); | |
407 | ||
408 | for (span = 0; span < raid->spanDepth; span++) { | |
94cd65dd SS |
409 | if (le32_to_cpu(map->raidMap.ldSpanMap[ld].spanBlock[span]. |
410 | block_span_info.noElements) >= | |
bc93d425 SS |
411 | element + 1) { |
412 | quad = &map->raidMap.ldSpanMap[ld]. | |
413 | spanBlock[span].block_span_info. | |
414 | quad[element]; | |
415 | dev_dbg(&instance->pdev->dev, "Span=%x," | |
416 | "Quad=%x, diff=%x\n", span, | |
94cd65dd | 417 | element, le32_to_cpu(quad->diff)); |
bc93d425 SS |
418 | dev_dbg(&instance->pdev->dev, |
419 | "offset_in_span=0x%08lx\n", | |
94cd65dd | 420 | (long unsigned int)le64_to_cpu(quad->offsetInSpan)); |
bc93d425 SS |
421 | dev_dbg(&instance->pdev->dev, |
422 | "logical start=0x%08lx, end=0x%08lx\n", | |
94cd65dd SS |
423 | (long unsigned int)le64_to_cpu(quad->logStart), |
424 | (long unsigned int)le64_to_cpu(quad->logEnd)); | |
bc93d425 SS |
425 | } |
426 | } | |
427 | } | |
428 | } | |
429 | return 0; | |
430 | } | |
431 | #endif | |
432 | ||
433 | /* | |
434 | ****************************************************************************** | |
435 | * | |
436 | * This routine calculates the Span block for given row using spanset. | |
437 | * | |
438 | * Inputs : | |
439 | * instance - HBA instance | |
440 | * ld - Logical drive number | |
441 | * row - Row number | |
442 | * map - LD map | |
443 | * | |
444 | * Outputs : | |
445 | * | |
446 | * span - Span number | |
447 | * block - Absolute Block number in the physical disk | |
448 | * div_error - Devide error code. | |
449 | */ | |
450 | ||
451 | u32 mr_spanset_get_span_block(struct megasas_instance *instance, | |
51087a86 | 452 | u32 ld, u64 row, u64 *span_blk, struct MR_DRV_RAID_MAP_ALL *map) |
bc93d425 SS |
453 | { |
454 | struct fusion_context *fusion = instance->ctrl_context; | |
455 | struct MR_LD_RAID *raid = MR_LdRaidGet(ld, map); | |
456 | LD_SPAN_SET *span_set; | |
457 | struct MR_QUAD_ELEMENT *quad; | |
458 | u32 span, info; | |
459 | PLD_SPAN_INFO ldSpanInfo = fusion->log_to_span; | |
460 | ||
461 | for (info = 0; info < MAX_QUAD_DEPTH; info++) { | |
462 | span_set = &(ldSpanInfo[ld].span_set[info]); | |
463 | ||
464 | if (span_set->span_row_data_width == 0) | |
465 | break; | |
466 | ||
467 | if (row > span_set->data_row_end) | |
468 | continue; | |
469 | ||
470 | for (span = 0; span < raid->spanDepth; span++) | |
94cd65dd SS |
471 | if (le32_to_cpu(map->raidMap.ldSpanMap[ld].spanBlock[span]. |
472 | block_span_info.noElements) >= info+1) { | |
bc93d425 SS |
473 | quad = &map->raidMap.ldSpanMap[ld]. |
474 | spanBlock[span]. | |
475 | block_span_info.quad[info]; | |
6e755ddc | 476 | if (le32_to_cpu(quad->diff) == 0) |
bc93d425 | 477 | return SPAN_INVALID; |
94cd65dd SS |
478 | if (le64_to_cpu(quad->logStart) <= row && |
479 | row <= le64_to_cpu(quad->logEnd) && | |
480 | (mega_mod64(row - le64_to_cpu(quad->logStart), | |
481 | le32_to_cpu(quad->diff))) == 0) { | |
bc93d425 SS |
482 | if (span_blk != NULL) { |
483 | u64 blk; | |
484 | blk = mega_div64_32 | |
94cd65dd SS |
485 | ((row - le64_to_cpu(quad->logStart)), |
486 | le32_to_cpu(quad->diff)); | |
487 | blk = (blk + le64_to_cpu(quad->offsetInSpan)) | |
bc93d425 SS |
488 | << raid->stripeShift; |
489 | *span_blk = blk; | |
490 | } | |
491 | return span; | |
492 | } | |
493 | } | |
494 | } | |
495 | return SPAN_INVALID; | |
496 | } | |
497 | ||
498 | /* | |
499 | ****************************************************************************** | |
500 | * | |
501 | * This routine calculates the row for given strip using spanset. | |
502 | * | |
503 | * Inputs : | |
504 | * instance - HBA instance | |
505 | * ld - Logical drive number | |
506 | * Strip - Strip | |
507 | * map - LD map | |
508 | * | |
509 | * Outputs : | |
510 | * | |
511 | * row - row associated with strip | |
512 | */ | |
513 | ||
514 | static u64 get_row_from_strip(struct megasas_instance *instance, | |
51087a86 | 515 | u32 ld, u64 strip, struct MR_DRV_RAID_MAP_ALL *map) |
bc93d425 SS |
516 | { |
517 | struct fusion_context *fusion = instance->ctrl_context; | |
518 | struct MR_LD_RAID *raid = MR_LdRaidGet(ld, map); | |
519 | LD_SPAN_SET *span_set; | |
520 | PLD_SPAN_INFO ldSpanInfo = fusion->log_to_span; | |
521 | u32 info, strip_offset, span, span_offset; | |
522 | u64 span_set_Strip, span_set_Row, retval; | |
523 | ||
524 | for (info = 0; info < MAX_QUAD_DEPTH; info++) { | |
525 | span_set = &(ldSpanInfo[ld].span_set[info]); | |
526 | ||
527 | if (span_set->span_row_data_width == 0) | |
528 | break; | |
529 | if (strip > span_set->data_strip_end) | |
530 | continue; | |
531 | ||
532 | span_set_Strip = strip - span_set->data_strip_start; | |
533 | strip_offset = mega_mod64(span_set_Strip, | |
534 | span_set->span_row_data_width); | |
535 | span_set_Row = mega_div64_32(span_set_Strip, | |
536 | span_set->span_row_data_width) * span_set->diff; | |
537 | for (span = 0, span_offset = 0; span < raid->spanDepth; span++) | |
94cd65dd | 538 | if (le32_to_cpu(map->raidMap.ldSpanMap[ld].spanBlock[span]. |
6e755ddc | 539 | block_span_info.noElements) >= info+1) { |
bc93d425 SS |
540 | if (strip_offset >= |
541 | span_set->strip_offset[span]) | |
542 | span_offset++; | |
543 | else | |
544 | break; | |
545 | } | |
546 | #if SPAN_DEBUG | |
547 | dev_info(&instance->pdev->dev, "Strip 0x%llx," | |
548 | "span_set_Strip 0x%llx, span_set_Row 0x%llx" | |
549 | "data width 0x%llx span offset 0x%x\n", strip, | |
550 | (unsigned long long)span_set_Strip, | |
551 | (unsigned long long)span_set_Row, | |
552 | (unsigned long long)span_set->span_row_data_width, | |
553 | span_offset); | |
554 | dev_info(&instance->pdev->dev, "For strip 0x%llx" | |
555 | "row is 0x%llx\n", strip, | |
556 | (unsigned long long) span_set->data_row_start + | |
557 | (unsigned long long) span_set_Row + (span_offset - 1)); | |
558 | #endif | |
559 | retval = (span_set->data_row_start + span_set_Row + | |
560 | (span_offset - 1)); | |
561 | return retval; | |
562 | } | |
563 | return -1LLU; | |
564 | } | |
565 | ||
566 | ||
567 | /* | |
568 | ****************************************************************************** | |
569 | * | |
570 | * This routine calculates the Start Strip for given row using spanset. | |
571 | * | |
572 | * Inputs : | |
573 | * instance - HBA instance | |
574 | * ld - Logical drive number | |
575 | * row - Row number | |
576 | * map - LD map | |
577 | * | |
578 | * Outputs : | |
579 | * | |
580 | * Strip - Start strip associated with row | |
581 | */ | |
582 | ||
583 | static u64 get_strip_from_row(struct megasas_instance *instance, | |
51087a86 | 584 | u32 ld, u64 row, struct MR_DRV_RAID_MAP_ALL *map) |
bc93d425 SS |
585 | { |
586 | struct fusion_context *fusion = instance->ctrl_context; | |
587 | struct MR_LD_RAID *raid = MR_LdRaidGet(ld, map); | |
588 | LD_SPAN_SET *span_set; | |
589 | struct MR_QUAD_ELEMENT *quad; | |
590 | PLD_SPAN_INFO ldSpanInfo = fusion->log_to_span; | |
591 | u32 span, info; | |
592 | u64 strip; | |
593 | ||
594 | for (info = 0; info < MAX_QUAD_DEPTH; info++) { | |
595 | span_set = &(ldSpanInfo[ld].span_set[info]); | |
596 | ||
597 | if (span_set->span_row_data_width == 0) | |
598 | break; | |
599 | if (row > span_set->data_row_end) | |
600 | continue; | |
601 | ||
602 | for (span = 0; span < raid->spanDepth; span++) | |
94cd65dd SS |
603 | if (le32_to_cpu(map->raidMap.ldSpanMap[ld].spanBlock[span]. |
604 | block_span_info.noElements) >= info+1) { | |
bc93d425 SS |
605 | quad = &map->raidMap.ldSpanMap[ld]. |
606 | spanBlock[span].block_span_info.quad[info]; | |
94cd65dd SS |
607 | if (le64_to_cpu(quad->logStart) <= row && |
608 | row <= le64_to_cpu(quad->logEnd) && | |
609 | mega_mod64((row - le64_to_cpu(quad->logStart)), | |
610 | le32_to_cpu(quad->diff)) == 0) { | |
bc93d425 SS |
611 | strip = mega_div64_32 |
612 | (((row - span_set->data_row_start) | |
94cd65dd SS |
613 | - le64_to_cpu(quad->logStart)), |
614 | le32_to_cpu(quad->diff)); | |
bc93d425 SS |
615 | strip *= span_set->span_row_data_width; |
616 | strip += span_set->data_strip_start; | |
617 | strip += span_set->strip_offset[span]; | |
618 | return strip; | |
619 | } | |
620 | } | |
621 | } | |
622 | dev_err(&instance->pdev->dev, "get_strip_from_row" | |
623 | "returns invalid strip for ld=%x, row=%lx\n", | |
624 | ld, (long unsigned int)row); | |
625 | return -1; | |
626 | } | |
627 | ||
628 | /* | |
629 | ****************************************************************************** | |
630 | * | |
631 | * This routine calculates the Physical Arm for given strip using spanset. | |
632 | * | |
633 | * Inputs : | |
634 | * instance - HBA instance | |
635 | * ld - Logical drive number | |
636 | * strip - Strip | |
637 | * map - LD map | |
638 | * | |
639 | * Outputs : | |
640 | * | |
641 | * Phys Arm - Phys Arm associated with strip | |
642 | */ | |
643 | ||
644 | static u32 get_arm_from_strip(struct megasas_instance *instance, | |
51087a86 | 645 | u32 ld, u64 strip, struct MR_DRV_RAID_MAP_ALL *map) |
bc93d425 SS |
646 | { |
647 | struct fusion_context *fusion = instance->ctrl_context; | |
648 | struct MR_LD_RAID *raid = MR_LdRaidGet(ld, map); | |
649 | LD_SPAN_SET *span_set; | |
650 | PLD_SPAN_INFO ldSpanInfo = fusion->log_to_span; | |
651 | u32 info, strip_offset, span, span_offset, retval; | |
652 | ||
653 | for (info = 0 ; info < MAX_QUAD_DEPTH; info++) { | |
654 | span_set = &(ldSpanInfo[ld].span_set[info]); | |
655 | ||
656 | if (span_set->span_row_data_width == 0) | |
657 | break; | |
658 | if (strip > span_set->data_strip_end) | |
659 | continue; | |
660 | ||
661 | strip_offset = (uint)mega_mod64 | |
662 | ((strip - span_set->data_strip_start), | |
663 | span_set->span_row_data_width); | |
664 | ||
665 | for (span = 0, span_offset = 0; span < raid->spanDepth; span++) | |
94cd65dd SS |
666 | if (le32_to_cpu(map->raidMap.ldSpanMap[ld].spanBlock[span]. |
667 | block_span_info.noElements) >= info+1) { | |
bc93d425 SS |
668 | if (strip_offset >= |
669 | span_set->strip_offset[span]) | |
670 | span_offset = | |
671 | span_set->strip_offset[span]; | |
672 | else | |
673 | break; | |
674 | } | |
675 | #if SPAN_DEBUG | |
676 | dev_info(&instance->pdev->dev, "get_arm_from_strip:" | |
677 | "for ld=0x%x strip=0x%lx arm is 0x%x\n", ld, | |
678 | (long unsigned int)strip, (strip_offset - span_offset)); | |
679 | #endif | |
680 | retval = (strip_offset - span_offset); | |
681 | return retval; | |
682 | } | |
683 | ||
684 | dev_err(&instance->pdev->dev, "get_arm_from_strip" | |
685 | "returns invalid arm for ld=%x strip=%lx\n", | |
686 | ld, (long unsigned int)strip); | |
687 | ||
688 | return -1; | |
689 | } | |
690 | ||
691 | /* This Function will return Phys arm */ | |
692 | u8 get_arm(struct megasas_instance *instance, u32 ld, u8 span, u64 stripe, | |
51087a86 | 693 | struct MR_DRV_RAID_MAP_ALL *map) |
bc93d425 SS |
694 | { |
695 | struct MR_LD_RAID *raid = MR_LdRaidGet(ld, map); | |
696 | /* Need to check correct default value */ | |
697 | u32 arm = 0; | |
698 | ||
699 | switch (raid->level) { | |
700 | case 0: | |
701 | case 5: | |
702 | case 6: | |
703 | arm = mega_mod64(stripe, SPAN_ROW_SIZE(map, ld, span)); | |
704 | break; | |
705 | case 1: | |
706 | /* start with logical arm */ | |
707 | arm = get_arm_from_strip(instance, ld, stripe, map); | |
fec3c1b4 | 708 | if (arm != -1U) |
bc93d425 SS |
709 | arm *= 2; |
710 | break; | |
711 | } | |
712 | ||
713 | return arm; | |
714 | } | |
715 | ||
716 | ||
717 | /* | |
718 | ****************************************************************************** | |
719 | * | |
720 | * This routine calculates the arm, span and block for the specified stripe and | |
721 | * reference in stripe using spanset | |
722 | * | |
723 | * Inputs : | |
724 | * | |
725 | * ld - Logical drive number | |
726 | * stripRow - Stripe number | |
727 | * stripRef - Reference in stripe | |
728 | * | |
729 | * Outputs : | |
730 | * | |
731 | * span - Span number | |
732 | * block - Absolute Block number in the physical disk | |
733 | */ | |
734 | static u8 mr_spanset_get_phy_params(struct megasas_instance *instance, u32 ld, | |
735 | u64 stripRow, u16 stripRef, struct IO_REQUEST_INFO *io_info, | |
736 | struct RAID_CONTEXT *pRAID_Context, | |
51087a86 | 737 | struct MR_DRV_RAID_MAP_ALL *map) |
bc93d425 SS |
738 | { |
739 | struct MR_LD_RAID *raid = MR_LdRaidGet(ld, map); | |
740 | u32 pd, arRef; | |
741 | u8 physArm, span; | |
742 | u64 row; | |
743 | u8 retval = TRUE; | |
bc93d425 | 744 | u64 *pdBlock = &io_info->pdBlock; |
9ab9ed38 | 745 | __le16 *pDevHandle = &io_info->devHandle; |
bc93d425 | 746 | u32 logArm, rowMod, armQ, arm; |
5a8cb85b | 747 | struct fusion_context *fusion; |
bc93d425 | 748 | |
5a8cb85b | 749 | fusion = instance->ctrl_context; |
bc93d425 SS |
750 | |
751 | /*Get row and span from io_info for Uneven Span IO.*/ | |
752 | row = io_info->start_row; | |
753 | span = io_info->start_span; | |
754 | ||
755 | ||
756 | if (raid->level == 6) { | |
757 | logArm = get_arm_from_strip(instance, ld, stripRow, map); | |
fec3c1b4 | 758 | if (logArm == -1U) |
bc93d425 SS |
759 | return FALSE; |
760 | rowMod = mega_mod64(row, SPAN_ROW_SIZE(map, ld, span)); | |
761 | armQ = SPAN_ROW_SIZE(map, ld, span) - 1 - rowMod; | |
762 | arm = armQ + 1 + logArm; | |
763 | if (arm >= SPAN_ROW_SIZE(map, ld, span)) | |
764 | arm -= SPAN_ROW_SIZE(map, ld, span); | |
765 | physArm = (u8)arm; | |
766 | } else | |
767 | /* Calculate the arm */ | |
768 | physArm = get_arm(instance, ld, span, stripRow, map); | |
769 | if (physArm == 0xFF) | |
770 | return FALSE; | |
771 | ||
772 | arRef = MR_LdSpanArrayGet(ld, span, map); | |
773 | pd = MR_ArPdGet(arRef, physArm, map); | |
774 | ||
775 | if (pd != MR_PD_INVALID) | |
776 | *pDevHandle = MR_PdDevHandleGet(pd, map); | |
777 | else { | |
c6f5bf81 | 778 | *pDevHandle = cpu_to_le16(MR_PD_INVALID); |
bc93d425 | 779 | if ((raid->level >= 5) && |
5a8cb85b | 780 | ((fusion->adapter_type == THUNDERBOLT_SERIES) || |
781 | ((fusion->adapter_type == INVADER_SERIES) && | |
bc93d425 SS |
782 | (raid->regTypeReqOnRead != REGION_TYPE_UNUSED)))) |
783 | pRAID_Context->regLockFlags = REGION_TYPE_EXCLUSIVE; | |
784 | else if (raid->level == 1) { | |
b3e3827b KD |
785 | physArm = physArm + 1; |
786 | pd = MR_ArPdGet(arRef, physArm, map); | |
bc93d425 SS |
787 | if (pd != MR_PD_INVALID) |
788 | *pDevHandle = MR_PdDevHandleGet(pd, map); | |
789 | } | |
790 | } | |
791 | ||
94cd65dd | 792 | *pdBlock += stripRef + le64_to_cpu(MR_LdSpanPtrGet(ld, span, map)->startBlk); |
bc93d425 SS |
793 | pRAID_Context->spanArm = (span << RAID_CTX_SPANARM_SPAN_SHIFT) | |
794 | physArm; | |
d2552ebe | 795 | io_info->span_arm = pRAID_Context->spanArm; |
bc93d425 | 796 | return retval; |
9c915a8c AR |
797 | } |
798 | ||
799 | /* | |
800 | ****************************************************************************** | |
801 | * | |
802 | * This routine calculates the arm, span and block for the specified stripe and | |
803 | * reference in stripe. | |
804 | * | |
805 | * Inputs : | |
806 | * | |
807 | * ld - Logical drive number | |
808 | * stripRow - Stripe number | |
809 | * stripRef - Reference in stripe | |
810 | * | |
811 | * Outputs : | |
812 | * | |
813 | * span - Span number | |
814 | * block - Absolute Block number in the physical disk | |
815 | */ | |
36807e67 | 816 | u8 MR_GetPhyParams(struct megasas_instance *instance, u32 ld, u64 stripRow, |
bc93d425 SS |
817 | u16 stripRef, struct IO_REQUEST_INFO *io_info, |
818 | struct RAID_CONTEXT *pRAID_Context, | |
51087a86 | 819 | struct MR_DRV_RAID_MAP_ALL *map) |
9c915a8c AR |
820 | { |
821 | struct MR_LD_RAID *raid = MR_LdRaidGet(ld, map); | |
822 | u32 pd, arRef; | |
823 | u8 physArm, span; | |
824 | u64 row; | |
825 | u8 retval = TRUE; | |
bc93d425 | 826 | u64 *pdBlock = &io_info->pdBlock; |
9ab9ed38 | 827 | __le16 *pDevHandle = &io_info->devHandle; |
5a8cb85b | 828 | struct fusion_context *fusion; |
829 | ||
830 | fusion = instance->ctrl_context; | |
21d3c710 | 831 | |
9c915a8c AR |
832 | |
833 | row = mega_div64_32(stripRow, raid->rowDataSize); | |
834 | ||
835 | if (raid->level == 6) { | |
836 | /* logical arm within row */ | |
837 | u32 logArm = mega_mod64(stripRow, raid->rowDataSize); | |
838 | u32 rowMod, armQ, arm; | |
839 | ||
840 | if (raid->rowSize == 0) | |
841 | return FALSE; | |
842 | /* get logical row mod */ | |
843 | rowMod = mega_mod64(row, raid->rowSize); | |
844 | armQ = raid->rowSize-1-rowMod; /* index of Q drive */ | |
845 | arm = armQ+1+logArm; /* data always logically follows Q */ | |
846 | if (arm >= raid->rowSize) /* handle wrap condition */ | |
847 | arm -= raid->rowSize; | |
848 | physArm = (u8)arm; | |
849 | } else { | |
850 | if (raid->modFactor == 0) | |
851 | return FALSE; | |
852 | physArm = MR_LdDataArmGet(ld, mega_mod64(stripRow, | |
853 | raid->modFactor), | |
854 | map); | |
855 | } | |
856 | ||
857 | if (raid->spanDepth == 1) { | |
858 | span = 0; | |
859 | *pdBlock = row << raid->stripeShift; | |
860 | } else { | |
bc93d425 SS |
861 | span = (u8)MR_GetSpanBlock(ld, row, pdBlock, map); |
862 | if (span == SPAN_INVALID) | |
9c915a8c AR |
863 | return FALSE; |
864 | } | |
865 | ||
866 | /* Get the array on which this span is present */ | |
867 | arRef = MR_LdSpanArrayGet(ld, span, map); | |
868 | pd = MR_ArPdGet(arRef, physArm, map); /* Get the pd */ | |
869 | ||
870 | if (pd != MR_PD_INVALID) | |
871 | /* Get dev handle from Pd. */ | |
872 | *pDevHandle = MR_PdDevHandleGet(pd, map); | |
873 | else { | |
c6f5bf81 CH |
874 | /* set dev handle as invalid. */ |
875 | *pDevHandle = cpu_to_le16(MR_PD_INVALID); | |
36807e67 | 876 | if ((raid->level >= 5) && |
5a8cb85b | 877 | ((fusion->adapter_type == THUNDERBOLT_SERIES) || |
878 | ((fusion->adapter_type == INVADER_SERIES) && | |
21d3c710 | 879 | (raid->regTypeReqOnRead != REGION_TYPE_UNUSED)))) |
9c915a8c AR |
880 | pRAID_Context->regLockFlags = REGION_TYPE_EXCLUSIVE; |
881 | else if (raid->level == 1) { | |
882 | /* Get alternate Pd. */ | |
b3e3827b KD |
883 | physArm = physArm + 1; |
884 | pd = MR_ArPdGet(arRef, physArm, map); | |
9c915a8c AR |
885 | if (pd != MR_PD_INVALID) |
886 | /* Get dev handle from Pd */ | |
887 | *pDevHandle = MR_PdDevHandleGet(pd, map); | |
888 | } | |
9c915a8c AR |
889 | } |
890 | ||
94cd65dd | 891 | *pdBlock += stripRef + le64_to_cpu(MR_LdSpanPtrGet(ld, span, map)->startBlk); |
9c915a8c AR |
892 | pRAID_Context->spanArm = (span << RAID_CTX_SPANARM_SPAN_SHIFT) | |
893 | physArm; | |
d2552ebe | 894 | io_info->span_arm = pRAID_Context->spanArm; |
9c915a8c AR |
895 | return retval; |
896 | } | |
897 | ||
898 | /* | |
899 | ****************************************************************************** | |
900 | * | |
901 | * MR_BuildRaidContext function | |
902 | * | |
903 | * This function will initiate command processing. The start/end row and strip | |
904 | * information is calculated then the lock is acquired. | |
905 | * This function will return 0 if region lock was acquired OR return num strips | |
906 | */ | |
907 | u8 | |
36807e67 AR |
908 | MR_BuildRaidContext(struct megasas_instance *instance, |
909 | struct IO_REQUEST_INFO *io_info, | |
9c915a8c | 910 | struct RAID_CONTEXT *pRAID_Context, |
51087a86 | 911 | struct MR_DRV_RAID_MAP_ALL *map, u8 **raidLUN) |
9c915a8c | 912 | { |
5a8cb85b | 913 | struct fusion_context *fusion; |
9c915a8c AR |
914 | struct MR_LD_RAID *raid; |
915 | u32 ld, stripSize, stripe_mask; | |
916 | u64 endLba, endStrip, endRow, start_row, start_strip; | |
917 | u64 regStart; | |
918 | u32 regSize; | |
919 | u8 num_strips, numRows; | |
920 | u16 ref_in_start_stripe, ref_in_end_stripe; | |
921 | u64 ldStartBlock; | |
922 | u32 numBlocks, ldTgtId; | |
923 | u8 isRead; | |
924 | u8 retval = 0; | |
bc93d425 SS |
925 | u8 startlba_span = SPAN_INVALID; |
926 | u64 *pdBlock = &io_info->pdBlock; | |
9c915a8c AR |
927 | |
928 | ldStartBlock = io_info->ldStartBlock; | |
929 | numBlocks = io_info->numBlocks; | |
930 | ldTgtId = io_info->ldTgtId; | |
931 | isRead = io_info->isRead; | |
bc93d425 SS |
932 | io_info->IoforUnevenSpan = 0; |
933 | io_info->start_span = SPAN_INVALID; | |
5a8cb85b | 934 | fusion = instance->ctrl_context; |
9c915a8c AR |
935 | |
936 | ld = MR_TargetIdToLdGet(ldTgtId, map); | |
937 | raid = MR_LdRaidGet(ld, map); | |
938 | ||
bc93d425 SS |
939 | /* |
940 | * if rowDataSize @RAID map and spanRowDataSize @SPAN INFO are zero | |
941 | * return FALSE | |
942 | */ | |
943 | if (raid->rowDataSize == 0) { | |
944 | if (MR_LdSpanPtrGet(ld, 0, map)->spanRowDataSize == 0) | |
945 | return FALSE; | |
946 | else if (instance->UnevenSpanSupport) { | |
947 | io_info->IoforUnevenSpan = 1; | |
948 | } else { | |
949 | dev_info(&instance->pdev->dev, | |
950 | "raid->rowDataSize is 0, but has SPAN[0]" | |
951 | "rowDataSize = 0x%0x," | |
952 | "but there is _NO_ UnevenSpanSupport\n", | |
953 | MR_LdSpanPtrGet(ld, 0, map)->spanRowDataSize); | |
954 | return FALSE; | |
955 | } | |
956 | } | |
957 | ||
9c915a8c AR |
958 | stripSize = 1 << raid->stripeShift; |
959 | stripe_mask = stripSize-1; | |
bc93d425 SS |
960 | |
961 | ||
9c915a8c AR |
962 | /* |
963 | * calculate starting row and stripe, and number of strips and rows | |
964 | */ | |
965 | start_strip = ldStartBlock >> raid->stripeShift; | |
966 | ref_in_start_stripe = (u16)(ldStartBlock & stripe_mask); | |
967 | endLba = ldStartBlock + numBlocks - 1; | |
968 | ref_in_end_stripe = (u16)(endLba & stripe_mask); | |
969 | endStrip = endLba >> raid->stripeShift; | |
970 | num_strips = (u8)(endStrip - start_strip + 1); /* End strip */ | |
bc93d425 SS |
971 | |
972 | if (io_info->IoforUnevenSpan) { | |
973 | start_row = get_row_from_strip(instance, ld, start_strip, map); | |
974 | endRow = get_row_from_strip(instance, ld, endStrip, map); | |
975 | if (start_row == -1ULL || endRow == -1ULL) { | |
976 | dev_info(&instance->pdev->dev, "return from %s %d." | |
977 | "Send IO w/o region lock.\n", | |
978 | __func__, __LINE__); | |
979 | return FALSE; | |
980 | } | |
981 | ||
982 | if (raid->spanDepth == 1) { | |
983 | startlba_span = 0; | |
984 | *pdBlock = start_row << raid->stripeShift; | |
985 | } else | |
986 | startlba_span = (u8)mr_spanset_get_span_block(instance, | |
987 | ld, start_row, pdBlock, map); | |
988 | if (startlba_span == SPAN_INVALID) { | |
989 | dev_info(&instance->pdev->dev, "return from %s %d" | |
990 | "for row 0x%llx,start strip %llx" | |
991 | "endSrip %llx\n", __func__, __LINE__, | |
992 | (unsigned long long)start_row, | |
993 | (unsigned long long)start_strip, | |
994 | (unsigned long long)endStrip); | |
995 | return FALSE; | |
996 | } | |
997 | io_info->start_span = startlba_span; | |
998 | io_info->start_row = start_row; | |
999 | #if SPAN_DEBUG | |
1000 | dev_dbg(&instance->pdev->dev, "Check Span number from %s %d" | |
1001 | "for row 0x%llx, start strip 0x%llx end strip 0x%llx" | |
1002 | " span 0x%x\n", __func__, __LINE__, | |
1003 | (unsigned long long)start_row, | |
1004 | (unsigned long long)start_strip, | |
1005 | (unsigned long long)endStrip, startlba_span); | |
1006 | dev_dbg(&instance->pdev->dev, "start_row 0x%llx endRow 0x%llx" | |
1007 | "Start span 0x%x\n", (unsigned long long)start_row, | |
1008 | (unsigned long long)endRow, startlba_span); | |
1009 | #endif | |
1010 | } else { | |
1011 | start_row = mega_div64_32(start_strip, raid->rowDataSize); | |
1012 | endRow = mega_div64_32(endStrip, raid->rowDataSize); | |
1013 | } | |
1014 | numRows = (u8)(endRow - start_row + 1); | |
9c915a8c AR |
1015 | |
1016 | /* | |
1017 | * calculate region info. | |
1018 | */ | |
1019 | ||
1020 | /* assume region is at the start of the first row */ | |
1021 | regStart = start_row << raid->stripeShift; | |
1022 | /* assume this IO needs the full row - we'll adjust if not true */ | |
1023 | regSize = stripSize; | |
1024 | ||
8f05024c SS |
1025 | io_info->do_fp_rlbypass = raid->capability.fpBypassRegionLock; |
1026 | ||
c1529fa2 AR |
1027 | /* Check if we can send this I/O via FastPath */ |
1028 | if (raid->capability.fpCapable) { | |
1029 | if (isRead) | |
1030 | io_info->fpOkForIo = (raid->capability.fpReadCapable && | |
1031 | ((num_strips == 1) || | |
1032 | raid->capability. | |
1033 | fpReadAcrossStripe)); | |
1034 | else | |
1035 | io_info->fpOkForIo = (raid->capability.fpWriteCapable && | |
1036 | ((num_strips == 1) || | |
1037 | raid->capability. | |
1038 | fpWriteAcrossStripe)); | |
1039 | } else | |
9c915a8c | 1040 | io_info->fpOkForIo = FALSE; |
9c915a8c AR |
1041 | |
1042 | if (numRows == 1) { | |
1043 | /* single-strip IOs can always lock only the data needed */ | |
1044 | if (num_strips == 1) { | |
1045 | regStart += ref_in_start_stripe; | |
1046 | regSize = numBlocks; | |
1047 | } | |
1048 | /* multi-strip IOs always need to full stripe locked */ | |
bc93d425 SS |
1049 | } else if (io_info->IoforUnevenSpan == 0) { |
1050 | /* | |
1051 | * For Even span region lock optimization. | |
1052 | * If the start strip is the last in the start row | |
1053 | */ | |
9c915a8c | 1054 | if (start_strip == (start_row + 1) * raid->rowDataSize - 1) { |
9c915a8c | 1055 | regStart += ref_in_start_stripe; |
9c915a8c AR |
1056 | /* initialize count to sectors from startref to end |
1057 | of strip */ | |
bc93d425 | 1058 | regSize = stripSize - ref_in_start_stripe; |
9c915a8c AR |
1059 | } |
1060 | ||
bc93d425 | 1061 | /* add complete rows in the middle of the transfer */ |
9c915a8c | 1062 | if (numRows > 2) |
9c915a8c AR |
1063 | regSize += (numRows-2) << raid->stripeShift; |
1064 | ||
bc93d425 | 1065 | /* if IO ends within first strip of last row*/ |
9c915a8c AR |
1066 | if (endStrip == endRow*raid->rowDataSize) |
1067 | regSize += ref_in_end_stripe+1; | |
1068 | else | |
1069 | regSize += stripSize; | |
bc93d425 SS |
1070 | } else { |
1071 | /* | |
1072 | * For Uneven span region lock optimization. | |
1073 | * If the start strip is the last in the start row | |
1074 | */ | |
1075 | if (start_strip == (get_strip_from_row(instance, ld, start_row, map) + | |
1076 | SPAN_ROW_DATA_SIZE(map, ld, startlba_span) - 1)) { | |
1077 | regStart += ref_in_start_stripe; | |
1078 | /* initialize count to sectors from | |
1079 | * startRef to end of strip | |
1080 | */ | |
1081 | regSize = stripSize - ref_in_start_stripe; | |
1082 | } | |
1083 | /* Add complete rows in the middle of the transfer*/ | |
1084 | ||
1085 | if (numRows > 2) | |
1086 | /* Add complete rows in the middle of the transfer*/ | |
1087 | regSize += (numRows-2) << raid->stripeShift; | |
1088 | ||
1089 | /* if IO ends within first strip of last row */ | |
1090 | if (endStrip == get_strip_from_row(instance, ld, endRow, map)) | |
1091 | regSize += ref_in_end_stripe + 1; | |
1092 | else | |
1093 | regSize += stripSize; | |
9c915a8c AR |
1094 | } |
1095 | ||
26a077e7 AR |
1096 | pRAID_Context->timeoutValue = |
1097 | cpu_to_le16(raid->fpIoTimeoutForLd ? | |
1098 | raid->fpIoTimeoutForLd : | |
1099 | map->raidMap.fpPdIoTimeoutSec); | |
5a8cb85b | 1100 | if (fusion->adapter_type == INVADER_SERIES) |
36807e67 AR |
1101 | pRAID_Context->regLockFlags = (isRead) ? |
1102 | raid->regTypeReqOnRead : raid->regTypeReqOnWrite; | |
1103 | else | |
1104 | pRAID_Context->regLockFlags = (isRead) ? | |
1105 | REGION_TYPE_SHARED_READ : raid->regTypeReqOnWrite; | |
9c915a8c | 1106 | pRAID_Context->VirtualDiskTgtId = raid->targetId; |
94cd65dd SS |
1107 | pRAID_Context->regLockRowLBA = cpu_to_le64(regStart); |
1108 | pRAID_Context->regLockLength = cpu_to_le32(regSize); | |
9c915a8c | 1109 | pRAID_Context->configSeqNum = raid->seqNum; |
21c9e160 AR |
1110 | /* save pointer to raid->LUN array */ |
1111 | *raidLUN = raid->LUN; | |
1112 | ||
9c915a8c AR |
1113 | |
1114 | /*Get Phy Params only if FP capable, or else leave it to MR firmware | |
1115 | to do the calculation.*/ | |
1116 | if (io_info->fpOkForIo) { | |
bc93d425 SS |
1117 | retval = io_info->IoforUnevenSpan ? |
1118 | mr_spanset_get_phy_params(instance, ld, | |
1119 | start_strip, ref_in_start_stripe, | |
1120 | io_info, pRAID_Context, map) : | |
1121 | MR_GetPhyParams(instance, ld, start_strip, | |
1122 | ref_in_start_stripe, io_info, | |
1123 | pRAID_Context, map); | |
1124 | /* If IO on an invalid Pd, then FP is not possible.*/ | |
c6f5bf81 | 1125 | if (io_info->devHandle == cpu_to_le16(MR_PD_INVALID)) |
9c915a8c AR |
1126 | io_info->fpOkForIo = FALSE; |
1127 | return retval; | |
1128 | } else if (isRead) { | |
1129 | uint stripIdx; | |
1130 | for (stripIdx = 0; stripIdx < num_strips; stripIdx++) { | |
bc93d425 SS |
1131 | retval = io_info->IoforUnevenSpan ? |
1132 | mr_spanset_get_phy_params(instance, ld, | |
1133 | start_strip + stripIdx, | |
1134 | ref_in_start_stripe, io_info, | |
1135 | pRAID_Context, map) : | |
1136 | MR_GetPhyParams(instance, ld, | |
1137 | start_strip + stripIdx, ref_in_start_stripe, | |
1138 | io_info, pRAID_Context, map); | |
1139 | if (!retval) | |
9c915a8c AR |
1140 | return TRUE; |
1141 | } | |
1142 | } | |
bc93d425 SS |
1143 | |
1144 | #if SPAN_DEBUG | |
1145 | /* Just for testing what arm we get for strip.*/ | |
1146 | if (io_info->IoforUnevenSpan) | |
1147 | get_arm_from_strip(instance, ld, start_strip, map); | |
1148 | #endif | |
9c915a8c AR |
1149 | return TRUE; |
1150 | } | |
1151 | ||
bc93d425 SS |
1152 | /* |
1153 | ****************************************************************************** | |
1154 | * | |
1155 | * This routine pepare spanset info from Valid Raid map and store it into | |
1156 | * local copy of ldSpanInfo per instance data structure. | |
1157 | * | |
1158 | * Inputs : | |
1159 | * map - LD map | |
1160 | * ldSpanInfo - ldSpanInfo per HBA instance | |
1161 | * | |
1162 | */ | |
51087a86 | 1163 | void mr_update_span_set(struct MR_DRV_RAID_MAP_ALL *map, |
d2552ebe | 1164 | PLD_SPAN_INFO ldSpanInfo) |
bc93d425 SS |
1165 | { |
1166 | u8 span, count; | |
1167 | u32 element, span_row_width; | |
1168 | u64 span_row; | |
1169 | struct MR_LD_RAID *raid; | |
1170 | LD_SPAN_SET *span_set, *span_set_prev; | |
1171 | struct MR_QUAD_ELEMENT *quad; | |
1172 | int ldCount; | |
1173 | u16 ld; | |
1174 | ||
1175 | ||
51087a86 | 1176 | for (ldCount = 0; ldCount < MAX_LOGICAL_DRIVES_EXT; ldCount++) { |
bc93d425 | 1177 | ld = MR_TargetIdToLdGet(ldCount, map); |
200aed58 | 1178 | if (ld >= (MAX_LOGICAL_DRIVES_EXT - 1)) |
bc93d425 SS |
1179 | continue; |
1180 | raid = MR_LdRaidGet(ld, map); | |
1181 | for (element = 0; element < MAX_QUAD_DEPTH; element++) { | |
1182 | for (span = 0; span < raid->spanDepth; span++) { | |
94cd65dd SS |
1183 | if (le32_to_cpu(map->raidMap.ldSpanMap[ld].spanBlock[span]. |
1184 | block_span_info.noElements) < | |
bc93d425 SS |
1185 | element + 1) |
1186 | continue; | |
1187 | span_set = &(ldSpanInfo[ld].span_set[element]); | |
1188 | quad = &map->raidMap.ldSpanMap[ld]. | |
1189 | spanBlock[span].block_span_info. | |
1190 | quad[element]; | |
1191 | ||
94cd65dd | 1192 | span_set->diff = le32_to_cpu(quad->diff); |
bc93d425 SS |
1193 | |
1194 | for (count = 0, span_row_width = 0; | |
1195 | count < raid->spanDepth; count++) { | |
94cd65dd | 1196 | if (le32_to_cpu(map->raidMap.ldSpanMap[ld]. |
bc93d425 SS |
1197 | spanBlock[count]. |
1198 | block_span_info. | |
94cd65dd | 1199 | noElements) >= element + 1) { |
bc93d425 SS |
1200 | span_set->strip_offset[count] = |
1201 | span_row_width; | |
1202 | span_row_width += | |
1203 | MR_LdSpanPtrGet | |
1204 | (ld, count, map)->spanRowDataSize; | |
bc93d425 SS |
1205 | } |
1206 | } | |
1207 | ||
1208 | span_set->span_row_data_width = span_row_width; | |
94cd65dd SS |
1209 | span_row = mega_div64_32(((le64_to_cpu(quad->logEnd) - |
1210 | le64_to_cpu(quad->logStart)) + le32_to_cpu(quad->diff)), | |
1211 | le32_to_cpu(quad->diff)); | |
bc93d425 SS |
1212 | |
1213 | if (element == 0) { | |
1214 | span_set->log_start_lba = 0; | |
1215 | span_set->log_end_lba = | |
1216 | ((span_row << raid->stripeShift) | |
1217 | * span_row_width) - 1; | |
1218 | ||
1219 | span_set->span_row_start = 0; | |
1220 | span_set->span_row_end = span_row - 1; | |
1221 | ||
1222 | span_set->data_strip_start = 0; | |
1223 | span_set->data_strip_end = | |
1224 | (span_row * span_row_width) - 1; | |
1225 | ||
1226 | span_set->data_row_start = 0; | |
1227 | span_set->data_row_end = | |
94cd65dd | 1228 | (span_row * le32_to_cpu(quad->diff)) - 1; |
bc93d425 SS |
1229 | } else { |
1230 | span_set_prev = &(ldSpanInfo[ld]. | |
1231 | span_set[element - 1]); | |
1232 | span_set->log_start_lba = | |
1233 | span_set_prev->log_end_lba + 1; | |
1234 | span_set->log_end_lba = | |
1235 | span_set->log_start_lba + | |
1236 | ((span_row << raid->stripeShift) | |
1237 | * span_row_width) - 1; | |
1238 | ||
1239 | span_set->span_row_start = | |
1240 | span_set_prev->span_row_end + 1; | |
1241 | span_set->span_row_end = | |
1242 | span_set->span_row_start + span_row - 1; | |
1243 | ||
1244 | span_set->data_strip_start = | |
1245 | span_set_prev->data_strip_end + 1; | |
1246 | span_set->data_strip_end = | |
1247 | span_set->data_strip_start + | |
1248 | (span_row * span_row_width) - 1; | |
1249 | ||
1250 | span_set->data_row_start = | |
1251 | span_set_prev->data_row_end + 1; | |
1252 | span_set->data_row_end = | |
1253 | span_set->data_row_start + | |
94cd65dd | 1254 | (span_row * le32_to_cpu(quad->diff)) - 1; |
bc93d425 SS |
1255 | } |
1256 | break; | |
1257 | } | |
1258 | if (span == raid->spanDepth) | |
1259 | break; | |
1260 | } | |
1261 | } | |
1262 | #if SPAN_DEBUG | |
1263 | getSpanInfo(map, ldSpanInfo); | |
1264 | #endif | |
1265 | ||
1266 | } | |
1267 | ||
d2552ebe SS |
1268 | void mr_update_load_balance_params(struct MR_DRV_RAID_MAP_ALL *drv_map, |
1269 | struct LD_LOAD_BALANCE_INFO *lbInfo) | |
9c915a8c AR |
1270 | { |
1271 | int ldCount; | |
1272 | u16 ld; | |
1273 | struct MR_LD_RAID *raid; | |
1274 | ||
d2552ebe SS |
1275 | if (lb_pending_cmds > 128 || lb_pending_cmds < 1) |
1276 | lb_pending_cmds = LB_PENDING_CMDS_DEFAULT; | |
1277 | ||
51087a86 | 1278 | for (ldCount = 0; ldCount < MAX_LOGICAL_DRIVES_EXT; ldCount++) { |
d2552ebe | 1279 | ld = MR_TargetIdToLdGet(ldCount, drv_map); |
51087a86 | 1280 | if (ld >= MAX_LOGICAL_DRIVES_EXT) { |
9c915a8c AR |
1281 | lbInfo[ldCount].loadBalanceFlag = 0; |
1282 | continue; | |
1283 | } | |
1284 | ||
d2552ebe SS |
1285 | raid = MR_LdRaidGet(ld, drv_map); |
1286 | if ((raid->level != 1) || | |
1287 | (raid->ldState != MR_LD_STATE_OPTIMAL)) { | |
9c915a8c | 1288 | lbInfo[ldCount].loadBalanceFlag = 0; |
d2552ebe SS |
1289 | continue; |
1290 | } | |
1291 | lbInfo[ldCount].loadBalanceFlag = 1; | |
9c915a8c AR |
1292 | } |
1293 | } | |
1294 | ||
d2552ebe SS |
1295 | u8 megasas_get_best_arm_pd(struct megasas_instance *instance, |
1296 | struct LD_LOAD_BALANCE_INFO *lbInfo, struct IO_REQUEST_INFO *io_info) | |
9c915a8c | 1297 | { |
d2552ebe SS |
1298 | struct fusion_context *fusion; |
1299 | struct MR_LD_RAID *raid; | |
1300 | struct MR_DRV_RAID_MAP_ALL *drv_map; | |
1301 | u16 pend0, pend1, ld; | |
9c915a8c | 1302 | u64 diff0, diff1; |
d2552ebe SS |
1303 | u8 bestArm, pd0, pd1, span, arm; |
1304 | u32 arRef, span_row_size; | |
1305 | ||
1306 | u64 block = io_info->ldStartBlock; | |
1307 | u32 count = io_info->numBlocks; | |
1308 | ||
1309 | span = ((io_info->span_arm & RAID_CTX_SPANARM_SPAN_MASK) | |
1310 | >> RAID_CTX_SPANARM_SPAN_SHIFT); | |
1311 | arm = (io_info->span_arm & RAID_CTX_SPANARM_ARM_MASK); | |
1312 | ||
1313 | ||
1314 | fusion = instance->ctrl_context; | |
1315 | drv_map = fusion->ld_drv_map[(instance->map_id & 1)]; | |
1316 | ld = MR_TargetIdToLdGet(io_info->ldTgtId, drv_map); | |
1317 | raid = MR_LdRaidGet(ld, drv_map); | |
1318 | span_row_size = instance->UnevenSpanSupport ? | |
1319 | SPAN_ROW_SIZE(drv_map, ld, span) : raid->rowSize; | |
1320 | ||
1321 | arRef = MR_LdSpanArrayGet(ld, span, drv_map); | |
1322 | pd0 = MR_ArPdGet(arRef, arm, drv_map); | |
1323 | pd1 = MR_ArPdGet(arRef, (arm + 1) >= span_row_size ? | |
1324 | (arm + 1 - span_row_size) : arm + 1, drv_map); | |
9c915a8c AR |
1325 | |
1326 | /* get the pending cmds for the data and mirror arms */ | |
d2552ebe SS |
1327 | pend0 = atomic_read(&lbInfo->scsi_pending_cmds[pd0]); |
1328 | pend1 = atomic_read(&lbInfo->scsi_pending_cmds[pd1]); | |
9c915a8c AR |
1329 | |
1330 | /* Determine the disk whose head is nearer to the req. block */ | |
d2552ebe SS |
1331 | diff0 = ABS_DIFF(block, lbInfo->last_accessed_block[pd0]); |
1332 | diff1 = ABS_DIFF(block, lbInfo->last_accessed_block[pd1]); | |
1333 | bestArm = (diff0 <= diff1 ? arm : arm ^ 1); | |
9c915a8c | 1334 | |
d2552ebe SS |
1335 | if ((bestArm == arm && pend0 > pend1 + lb_pending_cmds) || |
1336 | (bestArm != arm && pend1 > pend0 + lb_pending_cmds)) | |
9c915a8c AR |
1337 | bestArm ^= 1; |
1338 | ||
1339 | /* Update the last accessed block on the correct pd */ | |
d2552ebe SS |
1340 | io_info->pd_after_lb = (bestArm == arm) ? pd0 : pd1; |
1341 | lbInfo->last_accessed_block[io_info->pd_after_lb] = block + count - 1; | |
1342 | io_info->span_arm = (span << RAID_CTX_SPANARM_SPAN_SHIFT) | bestArm; | |
1343 | #if SPAN_DEBUG | |
1344 | if (arm != bestArm) | |
1345 | dev_dbg(&instance->pdev->dev, "LSI Debug R1 Load balance " | |
1346 | "occur - span 0x%x arm 0x%x bestArm 0x%x " | |
1347 | "io_info->span_arm 0x%x\n", | |
1348 | span, arm, bestArm, io_info->span_arm); | |
1349 | #endif | |
1350 | return io_info->pd_after_lb; | |
9c915a8c AR |
1351 | } |
1352 | ||
9ab9ed38 | 1353 | __le16 get_updated_dev_handle(struct megasas_instance *instance, |
d2552ebe | 1354 | struct LD_LOAD_BALANCE_INFO *lbInfo, struct IO_REQUEST_INFO *io_info) |
9c915a8c | 1355 | { |
d2552ebe | 1356 | u8 arm_pd; |
9ab9ed38 | 1357 | __le16 devHandle; |
d2552ebe SS |
1358 | struct fusion_context *fusion; |
1359 | struct MR_DRV_RAID_MAP_ALL *drv_map; | |
9c915a8c | 1360 | |
d2552ebe SS |
1361 | fusion = instance->ctrl_context; |
1362 | drv_map = fusion->ld_drv_map[(instance->map_id & 1)]; | |
9c915a8c | 1363 | |
d2552ebe SS |
1364 | /* get best new arm (PD ID) */ |
1365 | arm_pd = megasas_get_best_arm_pd(instance, lbInfo, io_info); | |
1366 | devHandle = MR_PdDevHandleGet(arm_pd, drv_map); | |
1367 | atomic_inc(&lbInfo->scsi_pending_cmds[arm_pd]); | |
9c915a8c AR |
1368 | return devHandle; |
1369 | } |