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9c915a8c AR |
1 | /* |
2 | * Linux MegaRAID driver for SAS based RAID controllers | |
3 | * | |
ae59057b | 4 | * Copyright (c) 2009-2012 LSI Corporation. |
9c915a8c AR |
5 | * |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | * | |
20 | * FILE: megaraid_sas_fusion.h | |
21 | * | |
22 | * Authors: LSI Corporation | |
23 | * Manoj Jose | |
24 | * Sumant Patro | |
25 | * | |
26 | * Send feedback to: <megaraidlinux@lsi.com> | |
27 | * | |
28 | * Mail to: LSI Corporation, 1621 Barber Lane, Milpitas, CA 95035 | |
29 | * ATTN: Linuxraid | |
30 | */ | |
31 | ||
32 | #ifndef _MEGARAID_SAS_FUSION_H_ | |
33 | #define _MEGARAID_SAS_FUSION_H_ | |
34 | ||
35 | /* Fusion defines */ | |
36 | #define MEGASAS_MAX_SZ_CHAIN_FRAME 1024 | |
37 | #define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000009) | |
38 | #define MEGA_MPI2_RAID_DEFAULT_IO_FRAME_SIZE 256 | |
39 | #define MEGASAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0 | |
40 | #define MEGASAS_MPI2_FUNCTION_LD_IO_REQUEST 0xF1 | |
41 | #define MEGASAS_LOAD_BALANCE_FLAG 0x1 | |
42 | #define MEGASAS_DCMD_MBOX_PEND_FLAG 0x1 | |
43 | #define HOST_DIAG_WRITE_ENABLE 0x80 | |
44 | #define HOST_DIAG_RESET_ADAPTER 0x4 | |
45 | #define MEGASAS_FUSION_MAX_RESET_TRIES 3 | |
d46a3ad6 | 46 | #define MAX_MSIX_QUEUES_FUSION 128 |
9c915a8c | 47 | |
36807e67 AR |
48 | /* Invader defines */ |
49 | #define MPI2_TYPE_CUDA 0x2 | |
50 | #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH 0x4000 | |
51 | #define MR_RL_FLAGS_GRANT_DESTINATION_CPU0 0x00 | |
52 | #define MR_RL_FLAGS_GRANT_DESTINATION_CPU1 0x10 | |
53 | #define MR_RL_FLAGS_GRANT_DESTINATION_CUDA 0x80 | |
54 | #define MR_RL_FLAGS_SEQ_NUM_ENABLE 0x8 | |
55 | ||
9c915a8c AR |
56 | /* T10 PI defines */ |
57 | #define MR_PROT_INFO_TYPE_CONTROLLER 0x8 | |
58 | #define MEGASAS_SCSI_VARIABLE_LENGTH_CMD 0x7f | |
59 | #define MEGASAS_SCSI_SERVICE_ACTION_READ32 0x9 | |
60 | #define MEGASAS_SCSI_SERVICE_ACTION_WRITE32 0xB | |
61 | #define MEGASAS_SCSI_ADDL_CDB_LEN 0x18 | |
62 | #define MEGASAS_RD_WR_PROTECT_CHECK_ALL 0x20 | |
63 | #define MEGASAS_RD_WR_PROTECT_CHECK_NONE 0x60 | |
9c915a8c | 64 | |
d46a3ad6 SS |
65 | #define MPI2_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C) |
66 | #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C) | |
67 | ||
9c915a8c AR |
68 | /* |
69 | * Raid context flags | |
70 | */ | |
71 | ||
72 | #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT 0x4 | |
73 | #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK 0x30 | |
74 | enum MR_RAID_FLAGS_IO_SUB_TYPE { | |
75 | MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0, | |
76 | MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1, | |
77 | }; | |
78 | ||
79 | /* | |
80 | * Request descriptor types | |
81 | */ | |
82 | #define MEGASAS_REQ_DESCRIPT_FLAGS_LD_IO 0x7 | |
83 | #define MEGASAS_REQ_DESCRIPT_FLAGS_MFA 0x1 | |
36807e67 | 84 | #define MEGASAS_REQ_DESCRIPT_FLAGS_NO_LOCK 0x2 |
9c915a8c AR |
85 | #define MEGASAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT 1 |
86 | ||
87 | #define MEGASAS_FP_CMD_LEN 16 | |
88 | #define MEGASAS_FUSION_IN_RESET 0 | |
89 | ||
90 | /* | |
3948ff8b | 91 | * Raid Context structure which describes MegaRAID specific IO Parameters |
9c915a8c AR |
92 | * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames |
93 | */ | |
94 | ||
95 | struct RAID_CONTEXT { | |
94cd65dd SS |
96 | #if defined(__BIG_ENDIAN_BITFIELD) |
97 | u8 nseg:4; | |
98 | u8 Type:4; | |
99 | #else | |
36807e67 AR |
100 | u8 Type:4; |
101 | u8 nseg:4; | |
94cd65dd | 102 | #endif |
36807e67 | 103 | u8 resvd0; |
9c915a8c AR |
104 | u16 timeoutValue; |
105 | u8 regLockFlags; | |
106 | u8 resvd1; | |
107 | u16 VirtualDiskTgtId; | |
108 | u64 regLockRowLBA; | |
109 | u32 regLockLength; | |
110 | u16 nextLMId; | |
111 | u8 exStatus; | |
112 | u8 status; | |
113 | u8 RAIDFlags; | |
114 | u8 numSGE; | |
115 | u16 configSeqNum; | |
116 | u8 spanArm; | |
117 | u8 resvd2[3]; | |
118 | }; | |
119 | ||
120 | #define RAID_CTX_SPANARM_ARM_SHIFT (0) | |
121 | #define RAID_CTX_SPANARM_ARM_MASK (0x1f) | |
122 | ||
123 | #define RAID_CTX_SPANARM_SPAN_SHIFT (5) | |
124 | #define RAID_CTX_SPANARM_SPAN_MASK (0xE0) | |
125 | ||
126 | /* | |
127 | * define region lock types | |
128 | */ | |
129 | enum REGION_TYPE { | |
130 | REGION_TYPE_UNUSED = 0, | |
131 | REGION_TYPE_SHARED_READ = 1, | |
132 | REGION_TYPE_SHARED_WRITE = 2, | |
133 | REGION_TYPE_EXCLUSIVE = 3, | |
134 | }; | |
135 | ||
136 | /* MPI2 defines */ | |
137 | #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ | |
138 | #define MPI2_WHOINIT_HOST_DRIVER (0x04) | |
139 | #define MPI2_VERSION_MAJOR (0x02) | |
140 | #define MPI2_VERSION_MINOR (0x00) | |
141 | #define MPI2_VERSION_MAJOR_MASK (0xFF00) | |
142 | #define MPI2_VERSION_MAJOR_SHIFT (8) | |
143 | #define MPI2_VERSION_MINOR_MASK (0x00FF) | |
144 | #define MPI2_VERSION_MINOR_SHIFT (0) | |
145 | #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ | |
146 | MPI2_VERSION_MINOR) | |
147 | #define MPI2_HEADER_VERSION_UNIT (0x10) | |
148 | #define MPI2_HEADER_VERSION_DEV (0x00) | |
149 | #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) | |
150 | #define MPI2_HEADER_VERSION_UNIT_SHIFT (8) | |
151 | #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) | |
152 | #define MPI2_HEADER_VERSION_DEV_SHIFT (0) | |
153 | #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \ | |
154 | MPI2_HEADER_VERSION_DEV) | |
155 | #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) | |
156 | #define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG (0x8000) | |
157 | #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG (0x0400) | |
158 | #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP (0x0003) | |
159 | #define MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG (0x0200) | |
160 | #define MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD (0x0100) | |
161 | #define MPI2_SCSIIO_EEDPFLAGS_INSERT_OP (0x0004) | |
162 | #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ | |
163 | #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) | |
164 | #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) | |
165 | #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) | |
166 | #define MPI2_SCSIIO_CONTROL_WRITE (0x01000000) | |
167 | #define MPI2_SCSIIO_CONTROL_READ (0x02000000) | |
168 | #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) | |
169 | #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) | |
170 | #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) | |
171 | #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) | |
172 | #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0) | |
173 | #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004) | |
174 | #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF) | |
175 | #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4) | |
176 | #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB) | |
177 | #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2) | |
178 | #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7) | |
179 | #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD) | |
180 | ||
181 | struct MPI25_IEEE_SGE_CHAIN64 { | |
182 | u64 Address; | |
183 | u32 Length; | |
184 | u16 Reserved1; | |
185 | u8 NextChainOffset; | |
186 | u8 Flags; | |
187 | }; | |
188 | ||
189 | struct MPI2_SGE_SIMPLE_UNION { | |
190 | u32 FlagsLength; | |
191 | union { | |
192 | u32 Address32; | |
193 | u64 Address64; | |
194 | } u; | |
195 | }; | |
196 | ||
197 | struct MPI2_SCSI_IO_CDB_EEDP32 { | |
198 | u8 CDB[20]; /* 0x00 */ | |
199 | u32 PrimaryReferenceTag; /* 0x14 */ | |
200 | u16 PrimaryApplicationTag; /* 0x18 */ | |
201 | u16 PrimaryApplicationTagMask; /* 0x1A */ | |
202 | u32 TransferLength; /* 0x1C */ | |
203 | }; | |
204 | ||
205 | struct MPI2_SGE_CHAIN_UNION { | |
206 | u16 Length; | |
207 | u8 NextChainOffset; | |
208 | u8 Flags; | |
209 | union { | |
210 | u32 Address32; | |
211 | u64 Address64; | |
212 | } u; | |
213 | }; | |
214 | ||
215 | struct MPI2_IEEE_SGE_SIMPLE32 { | |
216 | u32 Address; | |
217 | u32 FlagsLength; | |
218 | }; | |
219 | ||
220 | struct MPI2_IEEE_SGE_CHAIN32 { | |
221 | u32 Address; | |
222 | u32 FlagsLength; | |
223 | }; | |
224 | ||
225 | struct MPI2_IEEE_SGE_SIMPLE64 { | |
226 | u64 Address; | |
227 | u32 Length; | |
228 | u16 Reserved1; | |
229 | u8 Reserved2; | |
230 | u8 Flags; | |
231 | }; | |
232 | ||
233 | struct MPI2_IEEE_SGE_CHAIN64 { | |
234 | u64 Address; | |
235 | u32 Length; | |
236 | u16 Reserved1; | |
237 | u8 Reserved2; | |
238 | u8 Flags; | |
239 | }; | |
240 | ||
241 | union MPI2_IEEE_SGE_SIMPLE_UNION { | |
242 | struct MPI2_IEEE_SGE_SIMPLE32 Simple32; | |
243 | struct MPI2_IEEE_SGE_SIMPLE64 Simple64; | |
244 | }; | |
245 | ||
246 | union MPI2_IEEE_SGE_CHAIN_UNION { | |
247 | struct MPI2_IEEE_SGE_CHAIN32 Chain32; | |
248 | struct MPI2_IEEE_SGE_CHAIN64 Chain64; | |
249 | }; | |
250 | ||
251 | union MPI2_SGE_IO_UNION { | |
252 | struct MPI2_SGE_SIMPLE_UNION MpiSimple; | |
253 | struct MPI2_SGE_CHAIN_UNION MpiChain; | |
254 | union MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; | |
255 | union MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; | |
256 | }; | |
257 | ||
258 | union MPI2_SCSI_IO_CDB_UNION { | |
259 | u8 CDB32[32]; | |
260 | struct MPI2_SCSI_IO_CDB_EEDP32 EEDP32; | |
261 | struct MPI2_SGE_SIMPLE_UNION SGE; | |
262 | }; | |
263 | ||
264 | /* | |
265 | * RAID SCSI IO Request Message | |
266 | * Total SGE count will be one less than _MPI2_SCSI_IO_REQUEST | |
267 | */ | |
268 | struct MPI2_RAID_SCSI_IO_REQUEST { | |
269 | u16 DevHandle; /* 0x00 */ | |
270 | u8 ChainOffset; /* 0x02 */ | |
271 | u8 Function; /* 0x03 */ | |
272 | u16 Reserved1; /* 0x04 */ | |
273 | u8 Reserved2; /* 0x06 */ | |
274 | u8 MsgFlags; /* 0x07 */ | |
275 | u8 VP_ID; /* 0x08 */ | |
276 | u8 VF_ID; /* 0x09 */ | |
277 | u16 Reserved3; /* 0x0A */ | |
278 | u32 SenseBufferLowAddress; /* 0x0C */ | |
279 | u16 SGLFlags; /* 0x10 */ | |
280 | u8 SenseBufferLength; /* 0x12 */ | |
281 | u8 Reserved4; /* 0x13 */ | |
282 | u8 SGLOffset0; /* 0x14 */ | |
283 | u8 SGLOffset1; /* 0x15 */ | |
284 | u8 SGLOffset2; /* 0x16 */ | |
285 | u8 SGLOffset3; /* 0x17 */ | |
286 | u32 SkipCount; /* 0x18 */ | |
287 | u32 DataLength; /* 0x1C */ | |
288 | u32 BidirectionalDataLength; /* 0x20 */ | |
289 | u16 IoFlags; /* 0x24 */ | |
290 | u16 EEDPFlags; /* 0x26 */ | |
291 | u32 EEDPBlockSize; /* 0x28 */ | |
292 | u32 SecondaryReferenceTag; /* 0x2C */ | |
293 | u16 SecondaryApplicationTag; /* 0x30 */ | |
294 | u16 ApplicationTagTranslationMask; /* 0x32 */ | |
295 | u8 LUN[8]; /* 0x34 */ | |
296 | u32 Control; /* 0x3C */ | |
297 | union MPI2_SCSI_IO_CDB_UNION CDB; /* 0x40 */ | |
298 | struct RAID_CONTEXT RaidContext; /* 0x60 */ | |
299 | union MPI2_SGE_IO_UNION SGL; /* 0x80 */ | |
300 | }; | |
301 | ||
302 | /* | |
303 | * MPT RAID MFA IO Descriptor. | |
304 | */ | |
305 | struct MEGASAS_RAID_MFA_IO_REQUEST_DESCRIPTOR { | |
94cd65dd SS |
306 | #if defined(__BIG_ENDIAN_BITFIELD) |
307 | u32 MessageAddress1:24; /* bits 31:8*/ | |
308 | u32 RequestFlags:8; | |
309 | #else | |
9c915a8c AR |
310 | u32 RequestFlags:8; |
311 | u32 MessageAddress1:24; /* bits 31:8*/ | |
94cd65dd | 312 | #endif |
9c915a8c AR |
313 | u32 MessageAddress2; /* bits 61:32 */ |
314 | }; | |
315 | ||
316 | /* Default Request Descriptor */ | |
317 | struct MPI2_DEFAULT_REQUEST_DESCRIPTOR { | |
318 | u8 RequestFlags; /* 0x00 */ | |
319 | u8 MSIxIndex; /* 0x01 */ | |
320 | u16 SMID; /* 0x02 */ | |
321 | u16 LMID; /* 0x04 */ | |
322 | u16 DescriptorTypeDependent; /* 0x06 */ | |
323 | }; | |
324 | ||
325 | /* High Priority Request Descriptor */ | |
326 | struct MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR { | |
327 | u8 RequestFlags; /* 0x00 */ | |
328 | u8 MSIxIndex; /* 0x01 */ | |
329 | u16 SMID; /* 0x02 */ | |
330 | u16 LMID; /* 0x04 */ | |
331 | u16 Reserved1; /* 0x06 */ | |
332 | }; | |
333 | ||
334 | /* SCSI IO Request Descriptor */ | |
335 | struct MPI2_SCSI_IO_REQUEST_DESCRIPTOR { | |
336 | u8 RequestFlags; /* 0x00 */ | |
337 | u8 MSIxIndex; /* 0x01 */ | |
338 | u16 SMID; /* 0x02 */ | |
339 | u16 LMID; /* 0x04 */ | |
340 | u16 DevHandle; /* 0x06 */ | |
341 | }; | |
342 | ||
343 | /* SCSI Target Request Descriptor */ | |
344 | struct MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR { | |
345 | u8 RequestFlags; /* 0x00 */ | |
346 | u8 MSIxIndex; /* 0x01 */ | |
347 | u16 SMID; /* 0x02 */ | |
348 | u16 LMID; /* 0x04 */ | |
349 | u16 IoIndex; /* 0x06 */ | |
350 | }; | |
351 | ||
352 | /* RAID Accelerator Request Descriptor */ | |
353 | struct MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR { | |
354 | u8 RequestFlags; /* 0x00 */ | |
355 | u8 MSIxIndex; /* 0x01 */ | |
356 | u16 SMID; /* 0x02 */ | |
357 | u16 LMID; /* 0x04 */ | |
358 | u16 Reserved; /* 0x06 */ | |
359 | }; | |
360 | ||
361 | /* union of Request Descriptors */ | |
362 | union MEGASAS_REQUEST_DESCRIPTOR_UNION { | |
363 | struct MPI2_DEFAULT_REQUEST_DESCRIPTOR Default; | |
364 | struct MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority; | |
365 | struct MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO; | |
366 | struct MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget; | |
367 | struct MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator; | |
368 | struct MEGASAS_RAID_MFA_IO_REQUEST_DESCRIPTOR MFAIo; | |
369 | union { | |
370 | struct { | |
371 | u32 low; | |
372 | u32 high; | |
373 | } u; | |
374 | u64 Words; | |
375 | }; | |
376 | }; | |
377 | ||
378 | /* Default Reply Descriptor */ | |
379 | struct MPI2_DEFAULT_REPLY_DESCRIPTOR { | |
380 | u8 ReplyFlags; /* 0x00 */ | |
381 | u8 MSIxIndex; /* 0x01 */ | |
382 | u16 DescriptorTypeDependent1; /* 0x02 */ | |
383 | u32 DescriptorTypeDependent2; /* 0x04 */ | |
384 | }; | |
385 | ||
386 | /* Address Reply Descriptor */ | |
387 | struct MPI2_ADDRESS_REPLY_DESCRIPTOR { | |
388 | u8 ReplyFlags; /* 0x00 */ | |
389 | u8 MSIxIndex; /* 0x01 */ | |
390 | u16 SMID; /* 0x02 */ | |
391 | u32 ReplyFrameAddress; /* 0x04 */ | |
392 | }; | |
393 | ||
394 | /* SCSI IO Success Reply Descriptor */ | |
395 | struct MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR { | |
396 | u8 ReplyFlags; /* 0x00 */ | |
397 | u8 MSIxIndex; /* 0x01 */ | |
398 | u16 SMID; /* 0x02 */ | |
399 | u16 TaskTag; /* 0x04 */ | |
400 | u16 Reserved1; /* 0x06 */ | |
401 | }; | |
402 | ||
403 | /* TargetAssist Success Reply Descriptor */ | |
404 | struct MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR { | |
405 | u8 ReplyFlags; /* 0x00 */ | |
406 | u8 MSIxIndex; /* 0x01 */ | |
407 | u16 SMID; /* 0x02 */ | |
408 | u8 SequenceNumber; /* 0x04 */ | |
409 | u8 Reserved1; /* 0x05 */ | |
410 | u16 IoIndex; /* 0x06 */ | |
411 | }; | |
412 | ||
413 | /* Target Command Buffer Reply Descriptor */ | |
414 | struct MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR { | |
415 | u8 ReplyFlags; /* 0x00 */ | |
416 | u8 MSIxIndex; /* 0x01 */ | |
417 | u8 VP_ID; /* 0x02 */ | |
418 | u8 Flags; /* 0x03 */ | |
419 | u16 InitiatorDevHandle; /* 0x04 */ | |
420 | u16 IoIndex; /* 0x06 */ | |
421 | }; | |
422 | ||
423 | /* RAID Accelerator Success Reply Descriptor */ | |
424 | struct MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR { | |
425 | u8 ReplyFlags; /* 0x00 */ | |
426 | u8 MSIxIndex; /* 0x01 */ | |
427 | u16 SMID; /* 0x02 */ | |
428 | u32 Reserved; /* 0x04 */ | |
429 | }; | |
430 | ||
431 | /* union of Reply Descriptors */ | |
432 | union MPI2_REPLY_DESCRIPTORS_UNION { | |
433 | struct MPI2_DEFAULT_REPLY_DESCRIPTOR Default; | |
434 | struct MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply; | |
435 | struct MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess; | |
436 | struct MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess; | |
437 | struct MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer; | |
438 | struct MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR | |
439 | RAIDAcceleratorSuccess; | |
440 | u64 Words; | |
441 | }; | |
442 | ||
443 | /* IOCInit Request message */ | |
444 | struct MPI2_IOC_INIT_REQUEST { | |
445 | u8 WhoInit; /* 0x00 */ | |
446 | u8 Reserved1; /* 0x01 */ | |
447 | u8 ChainOffset; /* 0x02 */ | |
448 | u8 Function; /* 0x03 */ | |
449 | u16 Reserved2; /* 0x04 */ | |
450 | u8 Reserved3; /* 0x06 */ | |
451 | u8 MsgFlags; /* 0x07 */ | |
452 | u8 VP_ID; /* 0x08 */ | |
453 | u8 VF_ID; /* 0x09 */ | |
454 | u16 Reserved4; /* 0x0A */ | |
455 | u16 MsgVersion; /* 0x0C */ | |
456 | u16 HeaderVersion; /* 0x0E */ | |
457 | u32 Reserved5; /* 0x10 */ | |
458 | u16 Reserved6; /* 0x14 */ | |
459 | u8 Reserved7; /* 0x16 */ | |
460 | u8 HostMSIxVectors; /* 0x17 */ | |
461 | u16 Reserved8; /* 0x18 */ | |
462 | u16 SystemRequestFrameSize; /* 0x1A */ | |
463 | u16 ReplyDescriptorPostQueueDepth; /* 0x1C */ | |
464 | u16 ReplyFreeQueueDepth; /* 0x1E */ | |
465 | u32 SenseBufferAddressHigh; /* 0x20 */ | |
466 | u32 SystemReplyAddressHigh; /* 0x24 */ | |
467 | u64 SystemRequestFrameBaseAddress; /* 0x28 */ | |
468 | u64 ReplyDescriptorPostQueueAddress;/* 0x30 */ | |
469 | u64 ReplyFreeQueueAddress; /* 0x38 */ | |
470 | u64 TimeStamp; /* 0x40 */ | |
471 | }; | |
472 | ||
473 | /* mrpriv defines */ | |
474 | #define MR_PD_INVALID 0xFFFF | |
475 | #define MAX_SPAN_DEPTH 8 | |
bc93d425 | 476 | #define MAX_QUAD_DEPTH MAX_SPAN_DEPTH |
9c915a8c AR |
477 | #define MAX_RAIDMAP_SPAN_DEPTH (MAX_SPAN_DEPTH) |
478 | #define MAX_ROW_SIZE 32 | |
479 | #define MAX_RAIDMAP_ROW_SIZE (MAX_ROW_SIZE) | |
480 | #define MAX_LOGICAL_DRIVES 64 | |
481 | #define MAX_RAIDMAP_LOGICAL_DRIVES (MAX_LOGICAL_DRIVES) | |
482 | #define MAX_RAIDMAP_VIEWS (MAX_LOGICAL_DRIVES) | |
483 | #define MAX_ARRAYS 128 | |
484 | #define MAX_RAIDMAP_ARRAYS (MAX_ARRAYS) | |
485 | #define MAX_PHYSICAL_DEVICES 256 | |
486 | #define MAX_RAIDMAP_PHYSICAL_DEVICES (MAX_PHYSICAL_DEVICES) | |
487 | #define MR_DCMD_LD_MAP_GET_INFO 0x0300e101 | |
229fe47c AR |
488 | #define MR_DCMD_CTRL_SHARED_HOST_MEM_ALLOC 0x010e8485 /* SR-IOV HB alloc*/ |
489 | #define MR_DCMD_LD_VF_MAP_GET_ALL_LDS_111 0x03200200 | |
490 | #define MR_DCMD_LD_VF_MAP_GET_ALL_LDS 0x03150200 | |
9c915a8c AR |
491 | |
492 | struct MR_DEV_HANDLE_INFO { | |
493 | u16 curDevHdl; | |
494 | u8 validHandles; | |
495 | u8 reserved; | |
496 | u16 devHandle[2]; | |
497 | }; | |
498 | ||
499 | struct MR_ARRAY_INFO { | |
500 | u16 pd[MAX_RAIDMAP_ROW_SIZE]; | |
501 | }; | |
502 | ||
503 | struct MR_QUAD_ELEMENT { | |
504 | u64 logStart; | |
505 | u64 logEnd; | |
506 | u64 offsetInSpan; | |
507 | u32 diff; | |
508 | u32 reserved1; | |
509 | }; | |
510 | ||
511 | struct MR_SPAN_INFO { | |
512 | u32 noElements; | |
513 | u32 reserved1; | |
514 | struct MR_QUAD_ELEMENT quad[MAX_RAIDMAP_SPAN_DEPTH]; | |
515 | }; | |
516 | ||
517 | struct MR_LD_SPAN { | |
518 | u64 startBlk; | |
519 | u64 numBlks; | |
520 | u16 arrayRef; | |
bc93d425 SS |
521 | u8 spanRowSize; |
522 | u8 spanRowDataSize; | |
523 | u8 reserved[4]; | |
9c915a8c AR |
524 | }; |
525 | ||
526 | struct MR_SPAN_BLOCK_INFO { | |
527 | u64 num_rows; | |
528 | struct MR_LD_SPAN span; | |
529 | struct MR_SPAN_INFO block_span_info; | |
530 | }; | |
531 | ||
532 | struct MR_LD_RAID { | |
533 | struct { | |
94cd65dd SS |
534 | #if defined(__BIG_ENDIAN_BITFIELD) |
535 | u32 reserved4:7; | |
536 | u32 fpNonRWCapable:1; | |
537 | u32 fpReadAcrossStripe:1; | |
538 | u32 fpWriteAcrossStripe:1; | |
539 | u32 fpReadCapable:1; | |
540 | u32 fpWriteCapable:1; | |
541 | u32 encryptionType:8; | |
542 | u32 pdPiMode:4; | |
543 | u32 ldPiMode:4; | |
544 | u32 reserved5:3; | |
545 | u32 fpCapable:1; | |
546 | #else | |
9c915a8c AR |
547 | u32 fpCapable:1; |
548 | u32 reserved5:3; | |
549 | u32 ldPiMode:4; | |
550 | u32 pdPiMode:4; | |
551 | u32 encryptionType:8; | |
552 | u32 fpWriteCapable:1; | |
553 | u32 fpReadCapable:1; | |
554 | u32 fpWriteAcrossStripe:1; | |
555 | u32 fpReadAcrossStripe:1; | |
21c9e160 AR |
556 | u32 fpNonRWCapable:1; |
557 | u32 reserved4:7; | |
94cd65dd | 558 | #endif |
9c915a8c AR |
559 | } capability; |
560 | u32 reserved6; | |
561 | u64 size; | |
562 | u8 spanDepth; | |
563 | u8 level; | |
564 | u8 stripeShift; | |
565 | u8 rowSize; | |
566 | u8 rowDataSize; | |
567 | u8 writeMode; | |
568 | u8 PRL; | |
569 | u8 SRL; | |
570 | u16 targetId; | |
571 | u8 ldState; | |
572 | u8 regTypeReqOnWrite; | |
573 | u8 modFactor; | |
36807e67 | 574 | u8 regTypeReqOnRead; |
9c915a8c AR |
575 | u16 seqNum; |
576 | ||
577 | struct { | |
578 | u32 ldSyncRequired:1; | |
579 | u32 reserved:31; | |
580 | } flags; | |
581 | ||
21c9e160 AR |
582 | u8 LUN[8]; /* 0x24 8 byte LUN field used for SCSI IO's */ |
583 | u8 fpIoTimeoutForLd;/*0x2C timeout value used by driver in FP IO*/ | |
584 | u8 reserved3[0x80-0x2D]; /* 0x2D */ | |
9c915a8c AR |
585 | }; |
586 | ||
587 | struct MR_LD_SPAN_MAP { | |
588 | struct MR_LD_RAID ldRaid; | |
589 | u8 dataArmMap[MAX_RAIDMAP_ROW_SIZE]; | |
590 | struct MR_SPAN_BLOCK_INFO spanBlock[MAX_RAIDMAP_SPAN_DEPTH]; | |
591 | }; | |
592 | ||
593 | struct MR_FW_RAID_MAP { | |
594 | u32 totalSize; | |
595 | union { | |
596 | struct { | |
597 | u32 maxLd; | |
598 | u32 maxSpanDepth; | |
599 | u32 maxRowSize; | |
600 | u32 maxPdCount; | |
601 | u32 maxArrays; | |
602 | } validationInfo; | |
603 | u32 version[5]; | |
604 | u32 reserved1[5]; | |
605 | }; | |
606 | ||
607 | u32 ldCount; | |
608 | u32 Reserved1; | |
609 | u8 ldTgtIdToLd[MAX_RAIDMAP_LOGICAL_DRIVES+ | |
610 | MAX_RAIDMAP_VIEWS]; | |
611 | u8 fpPdIoTimeoutSec; | |
612 | u8 reserved2[7]; | |
613 | struct MR_ARRAY_INFO arMapInfo[MAX_RAIDMAP_ARRAYS]; | |
614 | struct MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES]; | |
615 | struct MR_LD_SPAN_MAP ldSpanMap[1]; | |
616 | }; | |
617 | ||
618 | struct IO_REQUEST_INFO { | |
619 | u64 ldStartBlock; | |
620 | u32 numBlocks; | |
621 | u16 ldTgtId; | |
622 | u8 isRead; | |
623 | u16 devHandle; | |
624 | u64 pdBlock; | |
625 | u8 fpOkForIo; | |
bc93d425 SS |
626 | u8 IoforUnevenSpan; |
627 | u8 start_span; | |
628 | u8 reserved; | |
629 | u64 start_row; | |
9c915a8c AR |
630 | }; |
631 | ||
632 | struct MR_LD_TARGET_SYNC { | |
633 | u8 targetId; | |
634 | u8 reserved; | |
635 | u16 seqNum; | |
636 | }; | |
637 | ||
638 | #define IEEE_SGE_FLAGS_ADDR_MASK (0x03) | |
639 | #define IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) | |
640 | #define IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) | |
641 | #define IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) | |
642 | #define IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) | |
643 | #define IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) | |
644 | #define IEEE_SGE_FLAGS_END_OF_LIST (0x40) | |
645 | ||
646 | struct megasas_register_set; | |
647 | struct megasas_instance; | |
648 | ||
649 | union desc_word { | |
650 | u64 word; | |
651 | struct { | |
652 | u32 low; | |
653 | u32 high; | |
654 | } u; | |
655 | }; | |
656 | ||
657 | struct megasas_cmd_fusion { | |
658 | struct MPI2_RAID_SCSI_IO_REQUEST *io_request; | |
659 | dma_addr_t io_request_phys_addr; | |
660 | ||
661 | union MPI2_SGE_IO_UNION *sg_frame; | |
662 | dma_addr_t sg_frame_phys_addr; | |
663 | ||
664 | u8 *sense; | |
665 | dma_addr_t sense_phys_addr; | |
666 | ||
667 | struct list_head list; | |
668 | struct scsi_cmnd *scmd; | |
669 | struct megasas_instance *instance; | |
670 | ||
671 | u8 retry_for_fw_reset; | |
672 | union MEGASAS_REQUEST_DESCRIPTOR_UNION *request_desc; | |
673 | ||
674 | /* | |
675 | * Context for a MFI frame. | |
676 | * Used to get the mfi cmd from list when a MFI cmd is completed | |
677 | */ | |
678 | u32 sync_cmd_idx; | |
679 | u32 index; | |
680 | u8 flags; | |
681 | }; | |
682 | ||
683 | struct LD_LOAD_BALANCE_INFO { | |
684 | u8 loadBalanceFlag; | |
685 | u8 reserved1; | |
686 | u16 raid1DevHandle[2]; | |
687 | atomic_t scsi_pending_cmds[2]; | |
688 | u64 last_accessed_block[2]; | |
689 | }; | |
690 | ||
bc93d425 SS |
691 | /* SPAN_SET is info caclulated from span info from Raid map per LD */ |
692 | typedef struct _LD_SPAN_SET { | |
693 | u64 log_start_lba; | |
694 | u64 log_end_lba; | |
695 | u64 span_row_start; | |
696 | u64 span_row_end; | |
697 | u64 data_strip_start; | |
698 | u64 data_strip_end; | |
699 | u64 data_row_start; | |
700 | u64 data_row_end; | |
701 | u8 strip_offset[MAX_SPAN_DEPTH]; | |
702 | u32 span_row_data_width; | |
703 | u32 diff; | |
704 | u32 reserved[2]; | |
705 | } LD_SPAN_SET, *PLD_SPAN_SET; | |
706 | ||
707 | typedef struct LOG_BLOCK_SPAN_INFO { | |
708 | LD_SPAN_SET span_set[MAX_SPAN_DEPTH]; | |
709 | } LD_SPAN_INFO, *PLD_SPAN_INFO; | |
710 | ||
9c915a8c AR |
711 | struct MR_FW_RAID_MAP_ALL { |
712 | struct MR_FW_RAID_MAP raidMap; | |
713 | struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES - 1]; | |
714 | } __attribute__ ((packed)); | |
715 | ||
716 | struct fusion_context { | |
717 | struct megasas_cmd_fusion **cmd_list; | |
718 | struct list_head cmd_pool; | |
719 | ||
720 | spinlock_t cmd_pool_lock; | |
721 | ||
722 | dma_addr_t req_frames_desc_phys; | |
723 | u8 *req_frames_desc; | |
724 | ||
725 | struct dma_pool *io_request_frames_pool; | |
726 | dma_addr_t io_request_frames_phys; | |
727 | u8 *io_request_frames; | |
728 | ||
729 | struct dma_pool *sg_dma_pool; | |
730 | struct dma_pool *sense_dma_pool; | |
731 | ||
732 | dma_addr_t reply_frames_desc_phys; | |
733 | union MPI2_REPLY_DESCRIPTORS_UNION *reply_frames_desc; | |
734 | struct dma_pool *reply_frames_desc_pool; | |
735 | ||
c8e858fe | 736 | u16 last_reply_idx[MAX_MSIX_QUEUES_FUSION]; |
9c915a8c AR |
737 | |
738 | u32 reply_q_depth; | |
739 | u32 request_alloc_sz; | |
740 | u32 reply_alloc_sz; | |
741 | u32 io_frames_alloc_sz; | |
742 | ||
743 | u16 max_sge_in_main_msg; | |
744 | u16 max_sge_in_chain; | |
745 | ||
746 | u8 chain_offset_io_request; | |
747 | u8 chain_offset_mfi_pthru; | |
748 | ||
749 | struct MR_FW_RAID_MAP_ALL *ld_map[2]; | |
750 | dma_addr_t ld_map_phys[2]; | |
751 | ||
752 | u32 map_sz; | |
753 | u8 fast_path_io; | |
754 | struct LD_LOAD_BALANCE_INFO load_balance_info[MAX_LOGICAL_DRIVES]; | |
bc93d425 | 755 | LD_SPAN_INFO log_to_span[MAX_LOGICAL_DRIVES]; |
9c915a8c AR |
756 | }; |
757 | ||
758 | union desc_value { | |
759 | u64 word; | |
760 | struct { | |
761 | u32 low; | |
762 | u32 high; | |
763 | } u; | |
764 | }; | |
765 | ||
766 | #endif /* _MEGARAID_SAS_FUSION_H_ */ |