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UBUNTU: Ubuntu-4.15.0-96.97
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / megaraid / megaraid_sas_fusion.h
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9c915a8c
AR		 1/*
2 * Linux MegaRAID driver for SAS based RAID controllers
3 *
e399065b
SS		 4 * Copyright (c) 2009-2013 LSI Corporation
5 * Copyright (c) 2013-2014 Avago Technologies
9c915a8c
AR		 6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
e399065b 18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
9c915a8c
AR		 19 *
20 * FILE: megaraid_sas_fusion.h
21 *
e399065b 22 * Authors: Avago Technologies
9c915a8c
AR		 23 * Manoj Jose
24 * Sumant Patro
e399065b
SS		 25 * Kashyap Desai <kashyap.desai@avagotech.com>
26 * Sumit Saxena <sumit.saxena@avagotech.com>
9c915a8c 27 *
e399065b 28 * Send feedback to: megaraidlinux.pdl@avagotech.com
9c915a8c 29 *
e399065b
SS		 30 * Mail to: Avago Technologies, 350 West Trimble Road, Building 90,
31 * San Jose, California 95131
9c915a8c
AR		 32 */
33
34#ifndef _MEGARAID_SAS_FUSION_H_
35#define _MEGARAID_SAS_FUSION_H_
36
37/* Fusion defines */
bd5f9484 38#define MEGASAS_CHAIN_FRAME_SZ_MIN 1024
9c915a8c 39#define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000009)
bd5f9484 40#define MEGASAS_MAX_CHAIN_SHIFT 5
41#define MEGASAS_MAX_CHAIN_SIZE_UNITS_MASK 0x400000
42#define MEGASAS_MAX_CHAIN_SIZE_MASK 0x3E0
43#define MEGASAS_256K_IO 128
44#define MEGASAS_1MB_IO (MEGASAS_256K_IO * 4)
9c915a8c
AR		 45#define MEGA_MPI2_RAID_DEFAULT_IO_FRAME_SIZE 256
46#define MEGASAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0
47#define MEGASAS_MPI2_FUNCTION_LD_IO_REQUEST 0xF1
48#define MEGASAS_LOAD_BALANCE_FLAG 0x1
49#define MEGASAS_DCMD_MBOX_PEND_FLAG 0x1
50#define HOST_DIAG_WRITE_ENABLE 0x80
51#define HOST_DIAG_RESET_ADAPTER 0x4
52#define MEGASAS_FUSION_MAX_RESET_TRIES 3
d46a3ad6 53#define MAX_MSIX_QUEUES_FUSION 128
107a60dd
S		 54#define RDPQ_MAX_INDEX_IN_ONE_CHUNK 16
55#define RDPQ_MAX_CHUNK_COUNT (MAX_MSIX_QUEUES_FUSION / RDPQ_MAX_INDEX_IN_ONE_CHUNK)
9c915a8c 56
36807e67
AR		 57/* Invader defines */
58#define MPI2_TYPE_CUDA 0x2
59#define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH 0x4000
60#define MR_RL_FLAGS_GRANT_DESTINATION_CPU0 0x00
61#define MR_RL_FLAGS_GRANT_DESTINATION_CPU1 0x10
62#define MR_RL_FLAGS_GRANT_DESTINATION_CUDA 0x80
63#define MR_RL_FLAGS_SEQ_NUM_ENABLE 0x8
d889344e
SC		 64#define MR_RL_WRITE_THROUGH_MODE 0x00
65#define MR_RL_WRITE_BACK_MODE 0x01
36807e67 66
9c915a8c
AR		 67/* T10 PI defines */
68#define MR_PROT_INFO_TYPE_CONTROLLER 0x8
69#define MEGASAS_SCSI_VARIABLE_LENGTH_CMD 0x7f
70#define MEGASAS_SCSI_SERVICE_ACTION_READ32 0x9
71#define MEGASAS_SCSI_SERVICE_ACTION_WRITE32 0xB
72#define MEGASAS_SCSI_ADDL_CDB_LEN 0x18
73#define MEGASAS_RD_WR_PROTECT_CHECK_ALL 0x20
74#define MEGASAS_RD_WR_PROTECT_CHECK_NONE 0x60
9c915a8c 75
d46a3ad6
SS		 76#define MPI2_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C)
77#define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C)
78
9c915a8c
AR		 79/*
80 * Raid context flags
81 */
82
83#define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT 0x4
84#define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK 0x30
85enum MR_RAID_FLAGS_IO_SUB_TYPE {
86 MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0,
87 MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1,
d889344e
SC		 88 MR_RAID_FLAGS_IO_SUB_TYPE_RMW_DATA = 2,
89 MR_RAID_FLAGS_IO_SUB_TYPE_RMW_P = 3,
90 MR_RAID_FLAGS_IO_SUB_TYPE_RMW_Q = 4,
91 MR_RAID_FLAGS_IO_SUB_TYPE_CACHE_BYPASS = 6,
92 MR_RAID_FLAGS_IO_SUB_TYPE_LDIO_BW_LIMIT = 7
9c915a8c
AR		 93};
94
95/*
96 * Request descriptor types
97 */
98#define MEGASAS_REQ_DESCRIPT_FLAGS_LD_IO 0x7
99#define MEGASAS_REQ_DESCRIPT_FLAGS_MFA 0x1
36807e67 100#define MEGASAS_REQ_DESCRIPT_FLAGS_NO_LOCK 0x2
9c915a8c
AR		 101#define MEGASAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT 1
102
103#define MEGASAS_FP_CMD_LEN 16
104#define MEGASAS_FUSION_IN_RESET 0
129e6210 105#define MEGASAS_FUSION_OCR_NOT_POSSIBLE 1
db4fc864 106#define THRESHOLD_REPLY_COUNT 50
a73b0a4b 107#define RAID_1_PEER_CMDS 2
3761cb4c 108#define JBOD_MAPS_COUNT 2
e97e673c 109#define MEGASAS_REDUCE_QD_COUNT 64
b9637d14 110#define IOC_INIT_FRAME_SIZE 4096
9c915a8c
AR		 111
112/*
3948ff8b 113 * Raid Context structure which describes MegaRAID specific IO Parameters
9c915a8c
AR		 114 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames
115 */
116
117struct RAID_CONTEXT {
94cd65dd 118#if defined(__BIG_ENDIAN_BITFIELD)
d889344e
SC		 119 u8 nseg:4;
120 u8 type:4;
94cd65dd 121#else
d889344e
SC		 122 u8 type:4;
123 u8 nseg:4;
94cd65dd 124#endif
d889344e
SC		 125 u8 resvd0;
126 __le16 timeout_value;
127 u8 reg_lock_flags;
128 u8 resvd1;
129 __le16 virtual_disk_tgt_id;
130 __le64 reg_lock_row_lba;
131 __le32 reg_lock_length;
132 __le16 next_lmid;
133 u8 ex_status;
134 u8 status;
135 u8 raid_flags;
136 u8 num_sge;
137 __le16 config_seq_num;
138 u8 span_arm;
139 u8 priority;
140 u8 num_sge_ext;
141 u8 resvd2;
9c915a8c
AR		 142};
143
fdd84e25
SC		 144/*
145 * Raid Context structure which describes ventura MegaRAID specific
146 * IO Paramenters ,This resides at offset 0x60 where the SGL normally
147 * starts in MPT IO Frames
148 */
149struct RAID_CONTEXT_G35 {
a174118b
S		 150 #define RAID_CONTEXT_NSEG_MASK 0x00F0
151 #define RAID_CONTEXT_NSEG_SHIFT 4
152 #define RAID_CONTEXT_TYPE_MASK 0x000F
153 #define RAID_CONTEXT_TYPE_SHIFT 0
154 u16 nseg_type;
fdd84e25 155 u16 timeout_value; /* 0x02 -0x03 */
a174118b 156 u16 routing_flags; // 0x04 -0x05 routing flags
fdd84e25
SC		 157 u16 virtual_disk_tgt_id; /* 0x06 -0x07 */
158 u64 reg_lock_row_lba; /* 0x08 - 0x0F */
159 u32 reg_lock_length; /* 0x10 - 0x13 */
160 union {
161 u16 next_lmid; /* 0x14 - 0x15 */
162 u16 peer_smid; /* used for the raid 1/10 fp writes */
163 } smid;
164 u8 ex_status; /* 0x16 : OUT */
165 u8 status; /* 0x17 status */
d889344e 166 u8 raid_flags; /* 0x18 resvd[7:6], ioSubType[5:4],
fdd84e25
SC		 167 * resvd[3:1], preferredCpu[0]
168 */
169 u8 span_arm; /* 0x1C span[7:5], arm[4:0] */
170 u16 config_seq_num; /* 0x1A -0x1B */
a174118b
S		 171 union {
172 /*
173 * Bit format:
174 * ---------------------------------
175 * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
176 * ---------------------------------
177 * Byte0 | numSGE[7]- numSGE[0] |
178 * ---------------------------------
179 * Byte1 |SD | resvd | numSGE 8-11 |
180 * --------------------------------
181 */
182 #define NUM_SGE_MASK_LOWER 0xFF
183 #define NUM_SGE_MASK_UPPER 0x0F
184 #define NUM_SGE_SHIFT_UPPER 8
185 #define STREAM_DETECT_SHIFT 7
186 #define STREAM_DETECT_MASK 0x80
187 struct {
fdd84e25 188#if defined(__BIG_ENDIAN_BITFIELD) /* 0x1C - 0x1D */
a174118b
S		 189 u16 stream_detected:1;
190 u16 reserved:3;
191 u16 num_sge:12;
fdd84e25 192#else
a174118b
S		 193 u16 num_sge:12;
194 u16 reserved:3;
195 u16 stream_detected:1;
fdd84e25 196#endif
a174118b
S		 197 } bits;
198 u8 bytes[2];
199 } u;
fdd84e25
SC		 200 u8 resvd2[2]; /* 0x1E-0x1F */
201};
202
a174118b
S		 203#define MR_RAID_CTX_ROUTINGFLAGS_SLD_SHIFT 1
204#define MR_RAID_CTX_ROUTINGFLAGS_C2D_SHIFT 2
205#define MR_RAID_CTX_ROUTINGFLAGS_FWD_SHIFT 3
206#define MR_RAID_CTX_ROUTINGFLAGS_SQN_SHIFT 4
207#define MR_RAID_CTX_ROUTINGFLAGS_SBS_SHIFT 5
208#define MR_RAID_CTX_ROUTINGFLAGS_RW_SHIFT 6
209#define MR_RAID_CTX_ROUTINGFLAGS_LOG_SHIFT 7
210#define MR_RAID_CTX_ROUTINGFLAGS_CPUSEL_SHIFT 8
211#define MR_RAID_CTX_ROUTINGFLAGS_CPUSEL_MASK 0x0F00
212#define MR_RAID_CTX_ROUTINGFLAGS_SETDIVERT_SHIFT 12
213#define MR_RAID_CTX_ROUTINGFLAGS_SETDIVERT_MASK 0xF000
214
215static inline void set_num_sge(struct RAID_CONTEXT_G35 *rctx_g35,
216 u16 sge_count)
217{
218 rctx_g35->u.bytes[0] = (u8)(sge_count & NUM_SGE_MASK_LOWER);
219 rctx_g35->u.bytes[1] |= (u8)((sge_count >> NUM_SGE_SHIFT_UPPER)
220 & NUM_SGE_MASK_UPPER);
221}
222
223static inline u16 get_num_sge(struct RAID_CONTEXT_G35 *rctx_g35)
224{
225 u16 sge_count;
226
227 sge_count = (u16)(((rctx_g35->u.bytes[1] & NUM_SGE_MASK_UPPER)
228 << NUM_SGE_SHIFT_UPPER) | (rctx_g35->u.bytes[0]));
229 return sge_count;
230}
231
232#define SET_STREAM_DETECTED(rctx_g35) \
233 (rctx_g35.u.bytes[1] |= STREAM_DETECT_MASK)
234
235#define CLEAR_STREAM_DETECTED(rctx_g35) \
236 (rctx_g35.u.bytes[1] &= ~(STREAM_DETECT_MASK))
237
238static inline bool is_stream_detected(struct RAID_CONTEXT_G35 *rctx_g35)
239{
240 return ((rctx_g35->u.bytes[1] & STREAM_DETECT_MASK));
241}
242
fdd84e25
SC		 243union RAID_CONTEXT_UNION {
244 struct RAID_CONTEXT raid_context;
245 struct RAID_CONTEXT_G35 raid_context_g35;
246};
247
9c915a8c
AR		 248#define RAID_CTX_SPANARM_ARM_SHIFT (0)
249#define RAID_CTX_SPANARM_ARM_MASK (0x1f)
250
251#define RAID_CTX_SPANARM_SPAN_SHIFT (5)
252#define RAID_CTX_SPANARM_SPAN_MASK (0xE0)
253
fdd84e25
SC		 254/* number of bits per index in U32 TrackStream */
255#define BITS_PER_INDEX_STREAM 4
256#define INVALID_STREAM_NUM 16
257#define MR_STREAM_BITMAP 0x76543210
258#define STREAM_MASK ((1 << BITS_PER_INDEX_STREAM) - 1)
259#define ZERO_LAST_STREAM 0x0fffffff
260#define MAX_STREAMS_TRACKED 8
261
9c915a8c
AR		 262/*
263 * define region lock types
264 */
265enum REGION_TYPE {
266 REGION_TYPE_UNUSED = 0,
267 REGION_TYPE_SHARED_READ = 1,
268 REGION_TYPE_SHARED_WRITE = 2,
269 REGION_TYPE_EXCLUSIVE = 3,
270};
271
272/* MPI2 defines */
273#define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */
274#define MPI2_WHOINIT_HOST_DRIVER (0x04)
275#define MPI2_VERSION_MAJOR (0x02)
276#define MPI2_VERSION_MINOR (0x00)
277#define MPI2_VERSION_MAJOR_MASK (0xFF00)
278#define MPI2_VERSION_MAJOR_SHIFT (8)
279#define MPI2_VERSION_MINOR_MASK (0x00FF)
280#define MPI2_VERSION_MINOR_SHIFT (0)
281#define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
282 MPI2_VERSION_MINOR)
283#define MPI2_HEADER_VERSION_UNIT (0x10)
284#define MPI2_HEADER_VERSION_DEV (0x00)
285#define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
286#define MPI2_HEADER_VERSION_UNIT_SHIFT (8)
287#define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
288#define MPI2_HEADER_VERSION_DEV_SHIFT (0)
289#define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \
290 MPI2_HEADER_VERSION_DEV)
291#define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
292#define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG (0x8000)
293#define MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG (0x0400)
294#define MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP (0x0003)
295#define MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG (0x0200)
296#define MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD (0x0100)
297#define MPI2_SCSIIO_EEDPFLAGS_INSERT_OP (0x0004)
45d44603
SC		 298/* EEDP escape mode */
299#define MPI25_SCSIIO_EEDPFLAGS_DO_NOT_DISABLE_MODE (0x0040)
9c915a8c 300#define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */
18365b13 301#define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01)
2c048351
SS		 302#define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x03)
303#define MPI2_REQ_DESCRIPT_FLAGS_FP_IO (0x06)
9c915a8c
AR		 304#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
305#define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02)
306#define MPI2_SCSIIO_CONTROL_WRITE (0x01000000)
307#define MPI2_SCSIIO_CONTROL_READ (0x02000000)
308#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E)
309#define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
310#define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
311#define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
312#define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0)
313#define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004)
314#define MPI2_WRSEQ_1ST_KEY_VALUE (0xF)
315#define MPI2_WRSEQ_2ND_KEY_VALUE (0x4)
316#define MPI2_WRSEQ_3RD_KEY_VALUE (0xB)
317#define MPI2_WRSEQ_4TH_KEY_VALUE (0x2)
318#define MPI2_WRSEQ_5TH_KEY_VALUE (0x7)
319#define MPI2_WRSEQ_6TH_KEY_VALUE (0xD)
320
321struct MPI25_IEEE_SGE_CHAIN64 {
9ab9ed38
CH		 322 __le64 Address;
323 __le32 Length;
324 __le16 Reserved1;
9c915a8c
AR		 325 u8 NextChainOffset;
326 u8 Flags;
327};
328
329struct MPI2_SGE_SIMPLE_UNION {
9ab9ed38 330 __le32 FlagsLength;
9c915a8c 331 union {
9ab9ed38
CH		 332 __le32 Address32;
333 __le64 Address64;
9c915a8c
AR		 334 } u;
335};
336
337struct MPI2_SCSI_IO_CDB_EEDP32 {
338 u8 CDB[20]; /* 0x00 */
9ab9ed38
CH		 339 __be32 PrimaryReferenceTag; /* 0x14 */
340 __be16 PrimaryApplicationTag; /* 0x18 */
341 __be16 PrimaryApplicationTagMask; /* 0x1A */
342 __le32 TransferLength; /* 0x1C */
9c915a8c
AR		 343};
344
345struct MPI2_SGE_CHAIN_UNION {
9ab9ed38 346 __le16 Length;
9c915a8c
AR		 347 u8 NextChainOffset;
348 u8 Flags;
349 union {
9ab9ed38
CH		 350 __le32 Address32;
351 __le64 Address64;
9c915a8c
AR		 352 } u;
353};
354
355struct MPI2_IEEE_SGE_SIMPLE32 {
9ab9ed38
CH		 356 __le32 Address;
357 __le32 FlagsLength;
9c915a8c
AR		 358};
359
360struct MPI2_IEEE_SGE_CHAIN32 {
9ab9ed38
CH		 361 __le32 Address;
362 __le32 FlagsLength;
9c915a8c
AR		 363};
364
365struct MPI2_IEEE_SGE_SIMPLE64 {
9ab9ed38
CH		 366 __le64 Address;
367 __le32 Length;
368 __le16 Reserved1;
9c915a8c
AR		 369 u8 Reserved2;
370 u8 Flags;
371};
372
373struct MPI2_IEEE_SGE_CHAIN64 {
9ab9ed38
CH		 374 __le64 Address;
375 __le32 Length;
376 __le16 Reserved1;
9c915a8c
AR		 377 u8 Reserved2;
378 u8 Flags;
379};
380
381union MPI2_IEEE_SGE_SIMPLE_UNION {
382 struct MPI2_IEEE_SGE_SIMPLE32 Simple32;
383 struct MPI2_IEEE_SGE_SIMPLE64 Simple64;
384};
385
386union MPI2_IEEE_SGE_CHAIN_UNION {
387 struct MPI2_IEEE_SGE_CHAIN32 Chain32;
388 struct MPI2_IEEE_SGE_CHAIN64 Chain64;
389};
390
391union MPI2_SGE_IO_UNION {
392 struct MPI2_SGE_SIMPLE_UNION MpiSimple;
393 struct MPI2_SGE_CHAIN_UNION MpiChain;
394 union MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
395 union MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
396};
397
398union MPI2_SCSI_IO_CDB_UNION {
399 u8 CDB32[32];
400 struct MPI2_SCSI_IO_CDB_EEDP32 EEDP32;
401 struct MPI2_SGE_SIMPLE_UNION SGE;
402};
403
18365b13
SS		 404/****************************************************************************
405* SCSI Task Management messages
406****************************************************************************/
407
408/*SCSI Task Management Request Message */
409struct MPI2_SCSI_TASK_MANAGE_REQUEST {
410 u16 DevHandle; /*0x00 */
411 u8 ChainOffset; /*0x02 */
412 u8 Function; /*0x03 */
413 u8 Reserved1; /*0x04 */
414 u8 TaskType; /*0x05 */
415 u8 Reserved2; /*0x06 */
416 u8 MsgFlags; /*0x07 */
417 u8 VP_ID; /*0x08 */
418 u8 VF_ID; /*0x09 */
419 u16 Reserved3; /*0x0A */
420 u8 LUN[8]; /*0x0C */
421 u32 Reserved4[7]; /*0x14 */
422 u16 TaskMID; /*0x30 */
423 u16 Reserved5; /*0x32 */
424};
425
426
427/*SCSI Task Management Reply Message */
428struct MPI2_SCSI_TASK_MANAGE_REPLY {
429 u16 DevHandle; /*0x00 */
430 u8 MsgLength; /*0x02 */
431 u8 Function; /*0x03 */
432 u8 ResponseCode; /*0x04 */
433 u8 TaskType; /*0x05 */
434 u8 Reserved1; /*0x06 */
435 u8 MsgFlags; /*0x07 */
436 u8 VP_ID; /*0x08 */
437 u8 VF_ID; /*0x09 */
438 u16 Reserved2; /*0x0A */
439 u16 Reserved3; /*0x0C */
440 u16 IOCStatus; /*0x0E */
441 u32 IOCLogInfo; /*0x10 */
442 u32 TerminationCount; /*0x14 */
443 u32 ResponseInfo; /*0x18 */
444};
445
446struct MR_TM_REQUEST {
447 char request[128];
448};
449
450struct MR_TM_REPLY {
451 char reply[128];
452};
453
454/* SCSI Task Management Request Message */
455struct MR_TASK_MANAGE_REQUEST {
456 /*To be type casted to struct MPI2_SCSI_TASK_MANAGE_REQUEST */
457 struct MR_TM_REQUEST TmRequest;
458 union {
459 struct {
460#if defined(__BIG_ENDIAN_BITFIELD)
461 u32 reserved1:30;
462 u32 isTMForPD:1;
463 u32 isTMForLD:1;
464#else
465 u32 isTMForLD:1;
466 u32 isTMForPD:1;
467 u32 reserved1:30;
468#endif
469 u32 reserved2;
470 } tmReqFlags;
471 struct MR_TM_REPLY TMReply;
472 };
473};
474
475/* TaskType values */
476
477#define MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK (0x01)
478#define MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET (0x02)
479#define MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET (0x03)
480#define MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET (0x05)
481#define MPI2_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET (0x06)
482#define MPI2_SCSITASKMGMT_TASKTYPE_QUERY_TASK (0x07)
483#define MPI2_SCSITASKMGMT_TASKTYPE_CLR_ACA (0x08)
484#define MPI2_SCSITASKMGMT_TASKTYPE_QRY_TASK_SET (0x09)
485#define MPI2_SCSITASKMGMT_TASKTYPE_QRY_ASYNC_EVENT (0x0A)
486
487/* ResponseCode values */
488
489#define MPI2_SCSITASKMGMT_RSP_TM_COMPLETE (0x00)
490#define MPI2_SCSITASKMGMT_RSP_INVALID_FRAME (0x02)
491#define MPI2_SCSITASKMGMT_RSP_TM_NOT_SUPPORTED (0x04)
492#define MPI2_SCSITASKMGMT_RSP_TM_FAILED (0x05)
493#define MPI2_SCSITASKMGMT_RSP_TM_SUCCEEDED (0x08)
494#define MPI2_SCSITASKMGMT_RSP_TM_INVALID_LUN (0x09)
495#define MPI2_SCSITASKMGMT_RSP_TM_OVERLAPPED_TAG (0x0A)
496#define MPI2_SCSITASKMGMT_RSP_IO_QUEUED_ON_IOC (0x80)
497
9c915a8c
AR		 498/*
499 * RAID SCSI IO Request Message
500 * Total SGE count will be one less than _MPI2_SCSI_IO_REQUEST
501 */
502struct MPI2_RAID_SCSI_IO_REQUEST {
9ab9ed38 503 __le16 DevHandle; /* 0x00 */
9c915a8c
AR		 504 u8 ChainOffset; /* 0x02 */
505 u8 Function; /* 0x03 */
9ab9ed38 506 __le16 Reserved1; /* 0x04 */
9c915a8c
AR		 507 u8 Reserved2; /* 0x06 */
508 u8 MsgFlags; /* 0x07 */
509 u8 VP_ID; /* 0x08 */
510 u8 VF_ID; /* 0x09 */
9ab9ed38
CH		 511 __le16 Reserved3; /* 0x0A */
512 __le32 SenseBufferLowAddress; /* 0x0C */
513 __le16 SGLFlags; /* 0x10 */
9c915a8c
AR		 514 u8 SenseBufferLength; /* 0x12 */
515 u8 Reserved4; /* 0x13 */
516 u8 SGLOffset0; /* 0x14 */
517 u8 SGLOffset1; /* 0x15 */
518 u8 SGLOffset2; /* 0x16 */
519 u8 SGLOffset3; /* 0x17 */
9ab9ed38
CH		 520 __le32 SkipCount; /* 0x18 */
521 __le32 DataLength; /* 0x1C */
522 __le32 BidirectionalDataLength; /* 0x20 */
523 __le16 IoFlags; /* 0x24 */
524 __le16 EEDPFlags; /* 0x26 */
525 __le32 EEDPBlockSize; /* 0x28 */
526 __le32 SecondaryReferenceTag; /* 0x2C */
527 __le16 SecondaryApplicationTag; /* 0x30 */
528 __le16 ApplicationTagTranslationMask; /* 0x32 */
9c915a8c 529 u8 LUN[8]; /* 0x34 */
9ab9ed38 530 __le32 Control; /* 0x3C */
9c915a8c 531 union MPI2_SCSI_IO_CDB_UNION CDB; /* 0x40 */
fdd84e25 532 union RAID_CONTEXT_UNION RaidContext; /* 0x60 */
9c915a8c
AR		 533 union MPI2_SGE_IO_UNION SGL; /* 0x80 */
534};
535
536/*
537 * MPT RAID MFA IO Descriptor.
538 */
539struct MEGASAS_RAID_MFA_IO_REQUEST_DESCRIPTOR {
540 u32 RequestFlags:8;
200aed58
SS		 541 u32 MessageAddress1:24;
542 u32 MessageAddress2;
9c915a8c
AR		 543};
544
545/* Default Request Descriptor */
546struct MPI2_DEFAULT_REQUEST_DESCRIPTOR {
547 u8 RequestFlags; /* 0x00 */
548 u8 MSIxIndex; /* 0x01 */
9ab9ed38
CH		 549 __le16 SMID; /* 0x02 */
550 __le16 LMID; /* 0x04 */
551 __le16 DescriptorTypeDependent; /* 0x06 */
9c915a8c
AR		 552};
553
554/* High Priority Request Descriptor */
555struct MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR {
556 u8 RequestFlags; /* 0x00 */
557 u8 MSIxIndex; /* 0x01 */
9ab9ed38
CH		 558 __le16 SMID; /* 0x02 */
559 __le16 LMID; /* 0x04 */
560 __le16 Reserved1; /* 0x06 */
9c915a8c
AR		 561};
562
563/* SCSI IO Request Descriptor */
564struct MPI2_SCSI_IO_REQUEST_DESCRIPTOR {
565 u8 RequestFlags; /* 0x00 */
566 u8 MSIxIndex; /* 0x01 */
9ab9ed38
CH		 567 __le16 SMID; /* 0x02 */
568 __le16 LMID; /* 0x04 */
569 __le16 DevHandle; /* 0x06 */
9c915a8c
AR		 570};
571
572/* SCSI Target Request Descriptor */
573struct MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR {
574 u8 RequestFlags; /* 0x00 */
575 u8 MSIxIndex; /* 0x01 */
9ab9ed38
CH		 576 __le16 SMID; /* 0x02 */
577 __le16 LMID; /* 0x04 */
578 __le16 IoIndex; /* 0x06 */
9c915a8c
AR		 579};
580
581/* RAID Accelerator Request Descriptor */
582struct MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR {
583 u8 RequestFlags; /* 0x00 */
584 u8 MSIxIndex; /* 0x01 */
9ab9ed38
CH		 585 __le16 SMID; /* 0x02 */
586 __le16 LMID; /* 0x04 */
587 __le16 Reserved; /* 0x06 */
9c915a8c
AR		 588};
589
590/* union of Request Descriptors */
591union MEGASAS_REQUEST_DESCRIPTOR_UNION {
592 struct MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;
593 struct MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;
594 struct MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;
595 struct MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;
596 struct MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;
597 struct MEGASAS_RAID_MFA_IO_REQUEST_DESCRIPTOR MFAIo;
598 union {
599 struct {
9ab9ed38
CH		 600 __le32 low;
601 __le32 high;
9c915a8c 602 } u;
9ab9ed38 603 __le64 Words;
9c915a8c
AR		 604 };
605};
606
607/* Default Reply Descriptor */
608struct MPI2_DEFAULT_REPLY_DESCRIPTOR {
609 u8 ReplyFlags; /* 0x00 */
610 u8 MSIxIndex; /* 0x01 */
9ab9ed38
CH		 611 __le16 DescriptorTypeDependent1; /* 0x02 */
612 __le32 DescriptorTypeDependent2; /* 0x04 */
9c915a8c
AR		 613};
614
615/* Address Reply Descriptor */
616struct MPI2_ADDRESS_REPLY_DESCRIPTOR {
617 u8 ReplyFlags; /* 0x00 */
618 u8 MSIxIndex; /* 0x01 */
9ab9ed38
CH		 619 __le16 SMID; /* 0x02 */
620 __le32 ReplyFrameAddress; /* 0x04 */
9c915a8c
AR		 621};
622
623/* SCSI IO Success Reply Descriptor */
624struct MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR {
625 u8 ReplyFlags; /* 0x00 */
626 u8 MSIxIndex; /* 0x01 */
9ab9ed38
CH		 627 __le16 SMID; /* 0x02 */
628 __le16 TaskTag; /* 0x04 */
629 __le16 Reserved1; /* 0x06 */
9c915a8c
AR		 630};
631
632/* TargetAssist Success Reply Descriptor */
633struct MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR {
634 u8 ReplyFlags; /* 0x00 */
635 u8 MSIxIndex; /* 0x01 */
9ab9ed38 636 __le16 SMID; /* 0x02 */
9c915a8c
AR		 637 u8 SequenceNumber; /* 0x04 */
638 u8 Reserved1; /* 0x05 */
9ab9ed38 639 __le16 IoIndex; /* 0x06 */
9c915a8c
AR		 640};
641
642/* Target Command Buffer Reply Descriptor */
643struct MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR {
644 u8 ReplyFlags; /* 0x00 */
645 u8 MSIxIndex; /* 0x01 */
646 u8 VP_ID; /* 0x02 */
647 u8 Flags; /* 0x03 */
9ab9ed38
CH		 648 __le16 InitiatorDevHandle; /* 0x04 */
649 __le16 IoIndex; /* 0x06 */
9c915a8c
AR		 650};
651
652/* RAID Accelerator Success Reply Descriptor */
653struct MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR {
654 u8 ReplyFlags; /* 0x00 */
655 u8 MSIxIndex; /* 0x01 */
9ab9ed38
CH		 656 __le16 SMID; /* 0x02 */
657 __le32 Reserved; /* 0x04 */
9c915a8c
AR		 658};
659
660/* union of Reply Descriptors */
661union MPI2_REPLY_DESCRIPTORS_UNION {
662 struct MPI2_DEFAULT_REPLY_DESCRIPTOR Default;
663 struct MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;
664 struct MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;
665 struct MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
666 struct MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
667 struct MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR
668 RAIDAcceleratorSuccess;
9ab9ed38 669 __le64 Words;
9c915a8c
AR		 670};
671
672/* IOCInit Request message */
673struct MPI2_IOC_INIT_REQUEST {
674 u8 WhoInit; /* 0x00 */
675 u8 Reserved1; /* 0x01 */
676 u8 ChainOffset; /* 0x02 */
677 u8 Function; /* 0x03 */
9ab9ed38 678 __le16 Reserved2; /* 0x04 */
9c915a8c
AR		 679 u8 Reserved3; /* 0x06 */
680 u8 MsgFlags; /* 0x07 */
681 u8 VP_ID; /* 0x08 */
682 u8 VF_ID; /* 0x09 */
9ab9ed38
CH		 683 __le16 Reserved4; /* 0x0A */
684 __le16 MsgVersion; /* 0x0C */
685 __le16 HeaderVersion; /* 0x0E */
9c915a8c 686 u32 Reserved5; /* 0x10 */
9ab9ed38 687 __le16 Reserved6; /* 0x14 */
15dd0381 688 u8 HostPageSize; /* 0x16 */
9c915a8c 689 u8 HostMSIxVectors; /* 0x17 */
9ab9ed38
CH		 690 __le16 Reserved8; /* 0x18 */
691 __le16 SystemRequestFrameSize; /* 0x1A */
692 __le16 ReplyDescriptorPostQueueDepth; /* 0x1C */
693 __le16 ReplyFreeQueueDepth; /* 0x1E */
694 __le32 SenseBufferAddressHigh; /* 0x20 */
695 __le32 SystemReplyAddressHigh; /* 0x24 */
696 __le64 SystemRequestFrameBaseAddress; /* 0x28 */
697 __le64 ReplyDescriptorPostQueueAddress;/* 0x30 */
698 __le64 ReplyFreeQueueAddress; /* 0x38 */
699 __le64 TimeStamp; /* 0x40 */
9c915a8c
AR		 700};
701
702/* mrpriv defines */
703#define MR_PD_INVALID 0xFFFF
8bf7c65d 704#define MR_DEVHANDLE_INVALID 0xFFFF
9c915a8c 705#define MAX_SPAN_DEPTH 8
bc93d425 706#define MAX_QUAD_DEPTH MAX_SPAN_DEPTH
9c915a8c
AR		 707#define MAX_RAIDMAP_SPAN_DEPTH (MAX_SPAN_DEPTH)
708#define MAX_ROW_SIZE 32
709#define MAX_RAIDMAP_ROW_SIZE (MAX_ROW_SIZE)
710#define MAX_LOGICAL_DRIVES 64
51087a86 711#define MAX_LOGICAL_DRIVES_EXT 256
d889344e 712#define MAX_LOGICAL_DRIVES_DYN 512
9c915a8c
AR		 713#define MAX_RAIDMAP_LOGICAL_DRIVES (MAX_LOGICAL_DRIVES)
714#define MAX_RAIDMAP_VIEWS (MAX_LOGICAL_DRIVES)
715#define MAX_ARRAYS 128
716#define MAX_RAIDMAP_ARRAYS (MAX_ARRAYS)
51087a86
SS		 717#define MAX_ARRAYS_EXT 256
718#define MAX_API_ARRAYS_EXT (MAX_ARRAYS_EXT)
d889344e 719#define MAX_API_ARRAYS_DYN 512
9c915a8c
AR		 720#define MAX_PHYSICAL_DEVICES 256
721#define MAX_RAIDMAP_PHYSICAL_DEVICES (MAX_PHYSICAL_DEVICES)
d889344e 722#define MAX_RAIDMAP_PHYSICAL_DEVICES_DYN 512
9c915a8c 723#define MR_DCMD_LD_MAP_GET_INFO 0x0300e101
3761cb4c 724#define MR_DCMD_SYSTEM_PD_MAP_GET_INFO 0x0200e102
96188a89 725#define MR_DCMD_DRV_GET_TARGET_PROP 0x0200e103
229fe47c
AR		 726#define MR_DCMD_CTRL_SHARED_HOST_MEM_ALLOC 0x010e8485 /* SR-IOV HB alloc*/
727#define MR_DCMD_LD_VF_MAP_GET_ALL_LDS_111 0x03200200
728#define MR_DCMD_LD_VF_MAP_GET_ALL_LDS 0x03150200
9c915a8c
AR		 729
730struct MR_DEV_HANDLE_INFO {
9ab9ed38 731 __le16 curDevHdl;
9c915a8c 732 u8 validHandles;
33203bc4 733 u8 interfaceType;
9ab9ed38 734 __le16 devHandle[2];
9c915a8c
AR		 735};
736
737struct MR_ARRAY_INFO {
9ab9ed38 738 __le16 pd[MAX_RAIDMAP_ROW_SIZE];
9c915a8c
AR		 739};
740
741struct MR_QUAD_ELEMENT {
9ab9ed38
CH		 742 __le64 logStart;
743 __le64 logEnd;
744 __le64 offsetInSpan;
745 __le32 diff;
746 __le32 reserved1;
9c915a8c
AR		 747};
748
749struct MR_SPAN_INFO {
9ab9ed38
CH		 750 __le32 noElements;
751 __le32 reserved1;
9c915a8c
AR		 752 struct MR_QUAD_ELEMENT quad[MAX_RAIDMAP_SPAN_DEPTH];
753};
754
755struct MR_LD_SPAN {
9ab9ed38
CH		 756 __le64 startBlk;
757 __le64 numBlks;
758 __le16 arrayRef;
bc93d425
SS		 759 u8 spanRowSize;
760 u8 spanRowDataSize;
761 u8 reserved[4];
9c915a8c
AR		 762};
763
764struct MR_SPAN_BLOCK_INFO {
9ab9ed38 765 __le64 num_rows;
9c915a8c
AR		 766 struct MR_LD_SPAN span;
767 struct MR_SPAN_INFO block_span_info;
768};
769
d889344e
SC		 770#define MR_RAID_CTX_CPUSEL_0 0
771#define MR_RAID_CTX_CPUSEL_1 1
772#define MR_RAID_CTX_CPUSEL_2 2
773#define MR_RAID_CTX_CPUSEL_3 3
774#define MR_RAID_CTX_CPUSEL_FCFS 0xF
775
776struct MR_CPU_AFFINITY_MASK {
777 union {
778 struct {
779#ifndef MFI_BIG_ENDIAN
780 u8 hw_path:1;
781 u8 cpu0:1;
782 u8 cpu1:1;
783 u8 cpu2:1;
784 u8 cpu3:1;
785 u8 reserved:3;
786#else
787 u8 reserved:3;
788 u8 cpu3:1;
789 u8 cpu2:1;
790 u8 cpu1:1;
791 u8 cpu0:1;
792 u8 hw_path:1;
793#endif
794 };
795 u8 core_mask;
796 };
797};
798
799struct MR_IO_AFFINITY {
800 union {
801 struct {
802 struct MR_CPU_AFFINITY_MASK pdRead;
803 struct MR_CPU_AFFINITY_MASK pdWrite;
804 struct MR_CPU_AFFINITY_MASK ldRead;
805 struct MR_CPU_AFFINITY_MASK ldWrite;
806 };
807 u32 word;
808 };
809 u8 maxCores; /* Total cores + HW Path in ROC */
810 u8 reserved[3];
811};
812
9c915a8c
AR		 813struct MR_LD_RAID {
814 struct {
94cd65dd 815#if defined(__BIG_ENDIAN_BITFIELD)
d889344e
SC		 816 u32 reserved4:2;
817 u32 fp_cache_bypass_capable:1;
818 u32 fp_rmw_capable:1;
819 u32 disable_coalescing:1;
8f05024c 820 u32 fpBypassRegionLock:1;
18365b13 821 u32 tmCapable:1;
94cd65dd
SS		 822 u32 fpNonRWCapable:1;
823 u32 fpReadAcrossStripe:1;
824 u32 fpWriteAcrossStripe:1;
825 u32 fpReadCapable:1;
826 u32 fpWriteCapable:1;
827 u32 encryptionType:8;
828 u32 pdPiMode:4;
829 u32 ldPiMode:4;
fdd84e25
SC		 830 u32 reserved5:2;
831 u32 ra_capable:1;
94cd65dd
SS		 832 u32 fpCapable:1;
833#else
9c915a8c 834 u32 fpCapable:1;
fdd84e25
SC		 835 u32 ra_capable:1;
836 u32 reserved5:2;
9c915a8c
AR		 837 u32 ldPiMode:4;
838 u32 pdPiMode:4;
839 u32 encryptionType:8;
840 u32 fpWriteCapable:1;
841 u32 fpReadCapable:1;
842 u32 fpWriteAcrossStripe:1;
843 u32 fpReadAcrossStripe:1;
21c9e160 844 u32 fpNonRWCapable:1;
18365b13 845 u32 tmCapable:1;
8f05024c 846 u32 fpBypassRegionLock:1;
d889344e
SC		 847 u32 disable_coalescing:1;
848 u32 fp_rmw_capable:1;
849 u32 fp_cache_bypass_capable:1;
850 u32 reserved4:2;
94cd65dd 851#endif
9c915a8c 852 } capability;
9ab9ed38
CH		 853 __le32 reserved6;
854 __le64 size;
9c915a8c
AR		 855 u8 spanDepth;
856 u8 level;
857 u8 stripeShift;
858 u8 rowSize;
859 u8 rowDataSize;
860 u8 writeMode;
861 u8 PRL;
862 u8 SRL;
9ab9ed38 863 __le16 targetId;
9c915a8c
AR		 864 u8 ldState;
865 u8 regTypeReqOnWrite;
866 u8 modFactor;
36807e67 867 u8 regTypeReqOnRead;
9ab9ed38 868 __le16 seqNum;
9c915a8c
AR		 869
870 struct {
871 u32 ldSyncRequired:1;
872 u32 reserved:31;
873 } flags;
874
21c9e160
AR		 875 u8 LUN[8]; /* 0x24 8 byte LUN field used for SCSI IO's */
876 u8 fpIoTimeoutForLd;/*0x2C timeout value used by driver in FP IO*/
d889344e
SC		 877 /* Ox2D This LD accept priority boost of this type */
878 u8 ld_accept_priority_type;
879 u8 reserved2[2]; /* 0x2E - 0x2F */
880 /* 0x30 - 0x33, Logical block size for the LD */
881 u32 logical_block_length;
882 struct {
883#ifndef MFI_BIG_ENDIAN
884 /* 0x34, P_I_EXPONENT from READ CAPACITY 16 */
885 u32 ld_pi_exp:4;
886 /* 0x34, LOGICAL BLOCKS PER PHYSICAL
887 * BLOCK EXPONENT from READ CAPACITY 16
888 */
889 u32 ld_logical_block_exp:4;
890 u32 reserved1:24; /* 0x34 */
891#else
892 u32 reserved1:24; /* 0x34 */
893 /* 0x34, LOGICAL BLOCKS PER PHYSICAL
894 * BLOCK EXPONENT from READ CAPACITY 16
895 */
896 u32 ld_logical_block_exp:4;
897 /* 0x34, P_I_EXPONENT from READ CAPACITY 16 */
898 u32 ld_pi_exp:4;
899#endif
900 }; /* 0x34 - 0x37 */
901 /* 0x38 - 0x3f, This will determine which
902 * core will process LD IO and PD IO.
903 */
904 struct MR_IO_AFFINITY cpuAffinity;
905 /* Bit definiations are specified by MR_IO_AFFINITY */
41064f1b 906 u8 reserved3[0x80 - 0x40]; /* 0x40 - 0x7f */
9c915a8c
AR		 907};
908
909struct MR_LD_SPAN_MAP {
910 struct MR_LD_RAID ldRaid;
911 u8 dataArmMap[MAX_RAIDMAP_ROW_SIZE];
912 struct MR_SPAN_BLOCK_INFO spanBlock[MAX_RAIDMAP_SPAN_DEPTH];
913};
914
915struct MR_FW_RAID_MAP {
9ab9ed38 916 __le32 totalSize;
9c915a8c
AR		 917 union {
918 struct {
9ab9ed38
CH		 919 __le32 maxLd;
920 __le32 maxSpanDepth;
921 __le32 maxRowSize;
922 __le32 maxPdCount;
923 __le32 maxArrays;
9c915a8c 924 } validationInfo;
9ab9ed38 925 __le32 version[5];
9c915a8c
AR		 926 };
927
9ab9ed38
CH		 928 __le32 ldCount;
929 __le32 Reserved1;
9c915a8c
AR		 930 u8 ldTgtIdToLd[MAX_RAIDMAP_LOGICAL_DRIVES+
931 MAX_RAIDMAP_VIEWS];
932 u8 fpPdIoTimeoutSec;
933 u8 reserved2[7];
934 struct MR_ARRAY_INFO arMapInfo[MAX_RAIDMAP_ARRAYS];
935 struct MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES];
936 struct MR_LD_SPAN_MAP ldSpanMap[1];
937};
938
939struct IO_REQUEST_INFO {
940 u64 ldStartBlock;
941 u32 numBlocks;
942 u16 ldTgtId;
943 u8 isRead;
9ab9ed38 944 __le16 devHandle;
33203bc4 945 u8 pd_interface;
9c915a8c
AR		 946 u64 pdBlock;
947 u8 fpOkForIo;
bc93d425
SS		 948 u8 IoforUnevenSpan;
949 u8 start_span;
8f05024c 950 u8 do_fp_rlbypass;
bc93d425 951 u64 start_row;
d2552ebe
SS		 952 u8 span_arm; /* span[7:5], arm[4:0] */
953 u8 pd_after_lb;
69c337c0 954 u16 r1_alt_dev_handle; /* raid 1/10 only */
fdd84e25 955 bool ra_capable;
9c915a8c
AR		 956};
957
958struct MR_LD_TARGET_SYNC {
959 u8 targetId;
960 u8 reserved;
9ab9ed38 961 __le16 seqNum;
9c915a8c
AR		 962};
963
d889344e
SC		 964/*
965 * RAID Map descriptor Types.
966 * Each element should uniquely idetify one data structure in the RAID map
967 */
968enum MR_RAID_MAP_DESC_TYPE {
969 /* MR_DEV_HANDLE_INFO data */
970 RAID_MAP_DESC_TYPE_DEVHDL_INFO = 0x0,
971 /* target to Ld num Index map */
972 RAID_MAP_DESC_TYPE_TGTID_INFO = 0x1,
973 /* MR_ARRAY_INFO data */
974 RAID_MAP_DESC_TYPE_ARRAY_INFO = 0x2,
975 /* MR_LD_SPAN_MAP data */
976 RAID_MAP_DESC_TYPE_SPAN_INFO = 0x3,
977 RAID_MAP_DESC_TYPE_COUNT,
978};
979
980/*
981 * This table defines the offset, size and num elements of each descriptor
982 * type in the RAID Map buffer
983 */
984struct MR_RAID_MAP_DESC_TABLE {
985 /* Raid map descriptor type */
986 u32 raid_map_desc_type;
987 /* Offset into the RAID map buffer where
988 * descriptor data is saved
989 */
990 u32 raid_map_desc_offset;
991 /* total size of the
992 * descriptor buffer
993 */
994 u32 raid_map_desc_buffer_size;
995 /* Number of elements contained in the
996 * descriptor buffer
997 */
998 u32 raid_map_desc_elements;
999};
1000
1001/*
1002 * Dynamic Raid Map Structure.
1003 */
1004struct MR_FW_RAID_MAP_DYNAMIC {
1005 u32 raid_map_size; /* total size of RAID Map structure */
1006 u32 desc_table_offset;/* Offset of desc table into RAID map*/
1007 u32 desc_table_size; /* Total Size of desc table */
1008 /* Total Number of elements in the desc table */
1009 u32 desc_table_num_elements;
18bbcabd 1010 u64 reserved1;
d889344e
SC		 1011 u32 reserved2[3]; /*future use */
1012 /* timeout value used by driver in FP IOs */
1013 u8 fp_pd_io_timeout_sec;
1014 u8 reserved3[3];
1015 /* when this seqNum increments, driver needs to
1016 * release RMW buffers asap
1017 */
1018 u32 rmw_fp_seq_num;
1019 u16 ld_count; /* count of lds. */
1020 u16 ar_count; /* count of arrays */
1021 u16 span_count; /* count of spans */
1022 u16 reserved4[3];
1023/*
1024 * The below structure of pointers is only to be used by the driver.
1025 * This is added in the ,API to reduce the amount of code changes
1026 * needed in the driver to support dynamic RAID map Firmware should
1027 * not update these pointers while preparing the raid map
1028 */
1029 union {
1030 struct {
1031 struct MR_DEV_HANDLE_INFO *dev_hndl_info;
1032 u16 *ld_tgt_id_to_ld;
1033 struct MR_ARRAY_INFO *ar_map_info;
1034 struct MR_LD_SPAN_MAP *ld_span_map;
1035 };
1036 u64 ptr_structure_size[RAID_MAP_DESC_TYPE_COUNT];
1037 };
1038/*
1039 * RAID Map descriptor table defines the layout of data in the RAID Map.
1040 * The size of the descriptor table itself could change.
1041 */
1042 /* Variable Size descriptor Table. */
1043 struct MR_RAID_MAP_DESC_TABLE
1044 raid_map_desc_table[RAID_MAP_DESC_TYPE_COUNT];
1045 /* Variable Size buffer containing all data */
1046 u32 raid_map_desc_data[1];
1047}; /* Dynamicaly sized RAID MAp structure */
1048
9c915a8c
AR		 1049#define IEEE_SGE_FLAGS_ADDR_MASK (0x03)
1050#define IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00)
1051#define IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01)
1052#define IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
1053#define IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
1054#define IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
1055#define IEEE_SGE_FLAGS_END_OF_LIST (0x40)
1056
33203bc4
S		 1057#define MPI2_SGE_FLAGS_SHIFT (0x02)
1058#define IEEE_SGE_FLAGS_FORMAT_MASK (0xC0)
1059#define IEEE_SGE_FLAGS_FORMAT_IEEE (0x00)
1060#define IEEE_SGE_FLAGS_FORMAT_NVME (0x02)
1061
1062#define MPI26_IEEE_SGE_FLAGS_NSF_MASK (0x1C)
1063#define MPI26_IEEE_SGE_FLAGS_NSF_MPI_IEEE (0x00)
1064#define MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP (0x08)
1065#define MPI26_IEEE_SGE_FLAGS_NSF_NVME_SGL (0x10)
1066
9c915a8c
AR		 1067struct megasas_register_set;
1068struct megasas_instance;
1069
1070union desc_word {
1071 u64 word;
1072 struct {
1073 u32 low;
1074 u32 high;
1075 } u;
1076};
1077
1078struct megasas_cmd_fusion {
1079 struct MPI2_RAID_SCSI_IO_REQUEST *io_request;
1080 dma_addr_t io_request_phys_addr;
1081
1082 union MPI2_SGE_IO_UNION *sg_frame;
1083 dma_addr_t sg_frame_phys_addr;
1084
1085 u8 *sense;
1086 dma_addr_t sense_phys_addr;
1087
1088 struct list_head list;
1089 struct scsi_cmnd *scmd;
1090 struct megasas_instance *instance;
1091
1092 u8 retry_for_fw_reset;
1093 union MEGASAS_REQUEST_DESCRIPTOR_UNION *request_desc;
1094
1095 /*
1096 * Context for a MFI frame.
1097 * Used to get the mfi cmd from list when a MFI cmd is completed
1098 */
1099 u32 sync_cmd_idx;
1100 u32 index;
d2552ebe 1101 u8 pd_r1_lb;
18365b13 1102 struct completion done;
33203bc4 1103 u8 pd_interface;
69c337c0
SC		 1104 u16 r1_alt_dev_handle; /* raid 1/10 only*/
1105 bool cmd_completed; /* raid 1/10 fp writes status holder */
1106
9c915a8c
AR		 1107};
1108
1109struct LD_LOAD_BALANCE_INFO {
1110 u8 loadBalanceFlag;
1111 u8 reserved1;
d2552ebe
SS		 1112 atomic_t scsi_pending_cmds[MAX_PHYSICAL_DEVICES];
1113 u64 last_accessed_block[MAX_PHYSICAL_DEVICES];
9c915a8c
AR		 1114};
1115
bc93d425
SS		 1116/* SPAN_SET is info caclulated from span info from Raid map per LD */
1117typedef struct _LD_SPAN_SET {
1118 u64 log_start_lba;
1119 u64 log_end_lba;
1120 u64 span_row_start;
1121 u64 span_row_end;
1122 u64 data_strip_start;
1123 u64 data_strip_end;
1124 u64 data_row_start;
1125 u64 data_row_end;
1126 u8 strip_offset[MAX_SPAN_DEPTH];
1127 u32 span_row_data_width;
1128 u32 diff;
1129 u32 reserved[2];
1130} LD_SPAN_SET, *PLD_SPAN_SET;
1131
1132typedef struct LOG_BLOCK_SPAN_INFO {
1133 LD_SPAN_SET span_set[MAX_SPAN_DEPTH];
1134} LD_SPAN_INFO, *PLD_SPAN_INFO;
1135
9c915a8c
AR		 1136struct MR_FW_RAID_MAP_ALL {
1137 struct MR_FW_RAID_MAP raidMap;
1138 struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES - 1];
1139} __attribute__ ((packed));
1140
51087a86
SS		 1141struct MR_DRV_RAID_MAP {
1142 /* total size of this structure, including this field.
1143 * This feild will be manupulated by driver for ext raid map,
1144 * else pick the value from firmware raid map.
1145 */
9ab9ed38 1146 __le32 totalSize;
51087a86
SS		 1147
1148 union {
1149 struct {
9ab9ed38
CH		 1150 __le32 maxLd;
1151 __le32 maxSpanDepth;
1152 __le32 maxRowSize;
1153 __le32 maxPdCount;
1154 __le32 maxArrays;
51087a86 1155 } validationInfo;
9ab9ed38 1156 __le32 version[5];
51087a86
SS		 1157 };
1158
1159 /* timeout value used by driver in FP IOs*/
1160 u8 fpPdIoTimeoutSec;
1161 u8 reserved2[7];
1162
9ab9ed38
CH		 1163 __le16 ldCount;
1164 __le16 arCount;
1165 __le16 spanCount;
1166 __le16 reserve3;
51087a86 1167
d889344e
SC		 1168 struct MR_DEV_HANDLE_INFO
1169 devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES_DYN];
1170 u16 ldTgtIdToLd[MAX_LOGICAL_DRIVES_DYN];
1171 struct MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_DYN];
51087a86
SS		 1172 struct MR_LD_SPAN_MAP ldSpanMap[1];
1173
1174};
1175
1176/* Driver raid map size is same as raid map ext
1177 * MR_DRV_RAID_MAP_ALL is created to sync with old raid.
1178 * And it is mainly for code re-use purpose.
1179 */
1180struct MR_DRV_RAID_MAP_ALL {
1181
1182 struct MR_DRV_RAID_MAP raidMap;
d889344e 1183 struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_DYN - 1];
51087a86
SS		 1184} __packed;
1185
1186
1187
1188struct MR_FW_RAID_MAP_EXT {
1189 /* Not usred in new map */
1190 u32 reserved;
1191
1192 union {
1193 struct {
1194 u32 maxLd;
1195 u32 maxSpanDepth;
1196 u32 maxRowSize;
1197 u32 maxPdCount;
1198 u32 maxArrays;
1199 } validationInfo;
1200 u32 version[5];
1201 };
1202
1203 u8 fpPdIoTimeoutSec;
1204 u8 reserved2[7];
1205
9ab9ed38
CH		 1206 __le16 ldCount;
1207 __le16 arCount;
1208 __le16 spanCount;
1209 __le16 reserve3;
51087a86
SS		 1210
1211 struct MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES];
1212 u8 ldTgtIdToLd[MAX_LOGICAL_DRIVES_EXT];
1213 struct MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_EXT];
1214 struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_EXT];
1215};
1216
3761cb4c 1217/*
1218 * * define MR_PD_CFG_SEQ structure for system PDs
1219 * */
1220struct MR_PD_CFG_SEQ {
18365b13
SS		 1221 u16 seqNum;
1222 u16 devHandle;
1223 struct {
1224#if defined(__BIG_ENDIAN_BITFIELD)
1225 u8 reserved:7;
1226 u8 tmCapable:1;
1227#else
1228 u8 tmCapable:1;
1229 u8 reserved:7;
1230#endif
1231 } capability;
ede7c3ce
SC		 1232 u8 reserved;
1233 u16 pd_target_id;
3761cb4c 1234} __packed;
1235
1236struct MR_PD_CFG_SEQ_NUM_SYNC {
1237 __le32 size;
1238 __le32 count;
1239 struct MR_PD_CFG_SEQ seq[1];
1240} __packed;
1241
fdd84e25
SC		 1242/* stream detection */
1243struct STREAM_DETECT {
1244 u64 next_seq_lba; /* next LBA to match sequential access */
1245 struct megasas_cmd_fusion *first_cmd_fusion; /* first cmd in group */
1246 struct megasas_cmd_fusion *last_cmd_fusion; /* last cmd in group */
1247 u32 count_cmds_in_stream; /* count of host commands in this stream */
1248 u16 num_sges_in_group; /* total number of SGEs in grouped IOs */
1249 u8 is_read; /* SCSI OpCode for this stream */
1250 u8 group_depth; /* total number of host commands in group */
1251 /* TRUE if cannot add any more commands to this group */
1252 bool group_flush;
1253 u8 reserved[7]; /* pad to 64-bit alignment */
1254};
1255
1256struct LD_STREAM_DETECT {
1257 bool write_back; /* TRUE if WB, FALSE if WT */
1258 bool fp_write_enabled;
1259 bool members_ssds;
1260 bool fp_cache_bypass_capable;
1261 u32 mru_bit_map; /* bitmap used to track MRU and LRU stream indicies */
1262 /* this is the array of stream detect structures (one per stream) */
1263 struct STREAM_DETECT stream_track[MAX_STREAMS_TRACKED];
1264};
1265
179ac142
SS		 1266struct MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY {
1267 u64 RDPQBaseAddress;
1268 u32 Reserved1;
1269 u32 Reserved2;
1270};
1271
107a60dd
S		 1272struct rdpq_alloc_detail {
1273 struct dma_pool *dma_pool_ptr;
1274 dma_addr_t pool_entry_phys;
1275 union MPI2_REPLY_DESCRIPTORS_UNION *pool_entry_virt;
1276};
1277
9c915a8c
AR		 1278struct fusion_context {
1279 struct megasas_cmd_fusion **cmd_list;
9c915a8c
AR		 1280 dma_addr_t req_frames_desc_phys;
1281 u8 *req_frames_desc;
1282
1283 struct dma_pool *io_request_frames_pool;
1284 dma_addr_t io_request_frames_phys;
1285 u8 *io_request_frames;
1286
1287 struct dma_pool *sg_dma_pool;
1288 struct dma_pool *sense_dma_pool;
1289
107a60dd
S		 1290 u8 *sense;
1291 dma_addr_t sense_phys_addr;
1292
179ac142
SS		 1293 dma_addr_t reply_frames_desc_phys[MAX_MSIX_QUEUES_FUSION];
1294 union MPI2_REPLY_DESCRIPTORS_UNION *reply_frames_desc[MAX_MSIX_QUEUES_FUSION];
107a60dd 1295 struct rdpq_alloc_detail rdpq_tracker[RDPQ_MAX_CHUNK_COUNT];
9c915a8c 1296 struct dma_pool *reply_frames_desc_pool;
107a60dd 1297 struct dma_pool *reply_frames_desc_pool_align;
9c915a8c 1298
c8e858fe 1299 u16 last_reply_idx[MAX_MSIX_QUEUES_FUSION];
9c915a8c
AR		 1300
1301 u32 reply_q_depth;
1302 u32 request_alloc_sz;
1303 u32 reply_alloc_sz;
1304 u32 io_frames_alloc_sz;
1305
179ac142
SS		 1306 struct MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY *rdpq_virt;
1307 dma_addr_t rdpq_phys;
9c915a8c
AR		 1308 u16 max_sge_in_main_msg;
1309 u16 max_sge_in_chain;
1310
1311 u8 chain_offset_io_request;
1312 u8 chain_offset_mfi_pthru;
1313
d889344e 1314 struct MR_FW_RAID_MAP_DYNAMIC *ld_map[2];
9c915a8c
AR		 1315 dma_addr_t ld_map_phys[2];
1316
51087a86
SS		 1317 /*Non dma-able memory. Driver local copy.*/
1318 struct MR_DRV_RAID_MAP_ALL *ld_drv_map[2];
1319
1320 u32 max_map_sz;
1321 u32 current_map_sz;
d889344e
SC		 1322 u32 old_map_sz;
1323 u32 new_map_sz;
51087a86
SS		 1324 u32 drv_map_sz;
1325 u32 drv_map_pages;
3761cb4c 1326 struct MR_PD_CFG_SEQ_NUM_SYNC *pd_seq_sync[JBOD_MAPS_COUNT];
1327 dma_addr_t pd_seq_phys[JBOD_MAPS_COUNT];
9c915a8c 1328 u8 fast_path_io;
5fc499b6
S		 1329 struct LD_LOAD_BALANCE_INFO *load_balance_info;
1330 u32 load_balance_info_pages;
2dd689c8
S		 1331 LD_SPAN_INFO *log_to_span;
1332 u32 log_to_span_pages;
fdd84e25 1333 struct LD_STREAM_DETECT **stream_detect_by_ld;
9b3d028f
S		 1334 dma_addr_t ioc_init_request_phys;
1335 struct MPI2_IOC_INIT_REQUEST *ioc_init_request;
b9637d14 1336 struct megasas_cmd *ioc_init_cmd;
9b3d028f 1337
9c915a8c
AR		 1338};
1339
1340union desc_value {
9ab9ed38 1341 __le64 word;
9c915a8c 1342 struct {
9ab9ed38
CH		 1343 __le32 low;
1344 __le32 high;
9c915a8c
AR		 1345 } u;
1346};
1347
2f3e7732
BX		 1348void megasas_free_cmds_fusion(struct megasas_instance *instance);
1349int megasas_ioc_init_fusion(struct megasas_instance *instance);
1350u8 megasas_get_map_info(struct megasas_instance *instance);
1351int megasas_sync_map_info(struct megasas_instance *instance);
1352void megasas_release_fusion(struct megasas_instance *instance);
1353void megasas_reset_reply_desc(struct megasas_instance *instance);
1354int megasas_check_mpio_paths(struct megasas_instance *instance,
1355 struct scsi_cmnd *scmd);
1356void megasas_fusion_ocr_wq(struct work_struct *work);
51087a86 1357
9c915a8c 1358#endif /* _MEGARAID_SAS_FUSION_H_ */
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