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scsi: mpi3mr: Don't reset IOC if cmnds flush with reset status
[mirror_ubuntu-jammy-kernel.git] / drivers / scsi / mpi3mr / mpi3mr_fw.c
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824a1566
KD		 1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Driver for Broadcom MPI3 Storage Controllers
4 *
5 * Copyright (C) 2017-2021 Broadcom Inc.
6 * (mailto: mpi3mr-linuxdrv.pdl@broadcom.com)
7 *
8 */
9
10#include "mpi3mr.h"
11#include <linux/io-64-nonatomic-lo-hi.h>
12
13#if defined(writeq) && defined(CONFIG_64BIT)
14static inline void mpi3mr_writeq(__u64 b, volatile void __iomem *addr)
15{
16 writeq(b, addr);
17}
18#else
19static inline void mpi3mr_writeq(__u64 b, volatile void __iomem *addr)
20{
21 __u64 data_out = b;
22
23 writel((u32)(data_out), addr);
24 writel((u32)(data_out >> 32), (addr + 4));
25}
26#endif
27
023ab2a9
KD		 28static inline bool
29mpi3mr_check_req_qfull(struct op_req_qinfo *op_req_q)
30{
31 u16 pi, ci, max_entries;
32 bool is_qfull = false;
33
34 pi = op_req_q->pi;
35 ci = READ_ONCE(op_req_q->ci);
36 max_entries = op_req_q->num_requests;
37
38 if ((ci == (pi + 1)) || ((!ci) && (pi == (max_entries - 1))))
39 is_qfull = true;
40
41 return is_qfull;
42}
43
824a1566
KD		 44static void mpi3mr_sync_irqs(struct mpi3mr_ioc *mrioc)
45{
46 u16 i, max_vectors;
47
48 max_vectors = mrioc->intr_info_count;
49
50 for (i = 0; i < max_vectors; i++)
51 synchronize_irq(pci_irq_vector(mrioc->pdev, i));
52}
53
54void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc)
55{
56 mrioc->intr_enabled = 0;
57 mpi3mr_sync_irqs(mrioc);
58}
59
60void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc)
61{
62 mrioc->intr_enabled = 1;
63}
64
65static void mpi3mr_cleanup_isr(struct mpi3mr_ioc *mrioc)
66{
67 u16 i;
68
69 mpi3mr_ioc_disable_intr(mrioc);
70
71 if (!mrioc->intr_info)
72 return;
73
74 for (i = 0; i < mrioc->intr_info_count; i++)
75 free_irq(pci_irq_vector(mrioc->pdev, i),
76 (mrioc->intr_info + i));
77
78 kfree(mrioc->intr_info);
79 mrioc->intr_info = NULL;
80 mrioc->intr_info_count = 0;
81 pci_free_irq_vectors(mrioc->pdev);
82}
83
84void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length,
85 dma_addr_t dma_addr)
86{
87 struct mpi3_sge_common *sgel = paddr;
88
89 sgel->flags = flags;
90 sgel->length = cpu_to_le32(length);
91 sgel->address = cpu_to_le64(dma_addr);
92}
93
94void mpi3mr_build_zero_len_sge(void *paddr)
95{
96 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
97
98 mpi3mr_add_sg_single(paddr, sgl_flags, 0, -1);
99}
100
101void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc,
102 dma_addr_t phys_addr)
103{
104 if (!phys_addr)
105 return NULL;
106
107 if ((phys_addr < mrioc->reply_buf_dma) ||
108 (phys_addr > mrioc->reply_buf_dma_max_address))
109 return NULL;
110
111 return mrioc->reply_buf + (phys_addr - mrioc->reply_buf_dma);
112}
113
114void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc,
115 dma_addr_t phys_addr)
116{
117 if (!phys_addr)
118 return NULL;
119
120 return mrioc->sense_buf + (phys_addr - mrioc->sense_buf_dma);
121}
122
123static void mpi3mr_repost_reply_buf(struct mpi3mr_ioc *mrioc,
124 u64 reply_dma)
125{
126 u32 old_idx = 0;
28848834 127 unsigned long flags;
824a1566 128
28848834 129 spin_lock_irqsave(&mrioc->reply_free_queue_lock, flags);
824a1566
KD		 130 old_idx = mrioc->reply_free_queue_host_index;
131 mrioc->reply_free_queue_host_index = (
132 (mrioc->reply_free_queue_host_index ==
133 (mrioc->reply_free_qsz - 1)) ? 0 :
134 (mrioc->reply_free_queue_host_index + 1));
135 mrioc->reply_free_q[old_idx] = cpu_to_le64(reply_dma);
136 writel(mrioc->reply_free_queue_host_index,
137 &mrioc->sysif_regs->reply_free_host_index);
28848834 138 spin_unlock_irqrestore(&mrioc->reply_free_queue_lock, flags);
824a1566
KD		 139}
140
141void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc,
142 u64 sense_buf_dma)
143{
144 u32 old_idx = 0;
28848834 145 unsigned long flags;
824a1566 146
28848834 147 spin_lock_irqsave(&mrioc->sbq_lock, flags);
824a1566
KD		 148 old_idx = mrioc->sbq_host_index;
149 mrioc->sbq_host_index = ((mrioc->sbq_host_index ==
150 (mrioc->sense_buf_q_sz - 1)) ? 0 :
151 (mrioc->sbq_host_index + 1));
152 mrioc->sense_buf_q[old_idx] = cpu_to_le64(sense_buf_dma);
153 writel(mrioc->sbq_host_index,
154 &mrioc->sysif_regs->sense_buffer_free_host_index);
28848834 155 spin_unlock_irqrestore(&mrioc->sbq_lock, flags);
824a1566
KD		 156}
157
9fc4abfe
KD		 158static void mpi3mr_print_event_data(struct mpi3mr_ioc *mrioc,
159 struct mpi3_event_notification_reply *event_reply)
160{
161 char *desc = NULL;
162 u16 event;
163
164 event = event_reply->event;
165
166 switch (event) {
167 case MPI3_EVENT_LOG_DATA:
168 desc = "Log Data";
169 break;
170 case MPI3_EVENT_CHANGE:
171 desc = "Event Change";
172 break;
173 case MPI3_EVENT_GPIO_INTERRUPT:
174 desc = "GPIO Interrupt";
175 break;
176 case MPI3_EVENT_TEMP_THRESHOLD:
177 desc = "Temperature Threshold";
178 break;
179 case MPI3_EVENT_CABLE_MGMT:
180 desc = "Cable Management";
181 break;
182 case MPI3_EVENT_ENERGY_PACK_CHANGE:
183 desc = "Energy Pack Change";
184 break;
185 case MPI3_EVENT_DEVICE_ADDED:
186 {
187 struct mpi3_device_page0 *event_data =
188 (struct mpi3_device_page0 *)event_reply->event_data;
189 ioc_info(mrioc, "Device Added: dev=0x%04x Form=0x%x\n",
190 event_data->dev_handle, event_data->device_form);
191 return;
192 }
193 case MPI3_EVENT_DEVICE_INFO_CHANGED:
194 {
195 struct mpi3_device_page0 *event_data =
196 (struct mpi3_device_page0 *)event_reply->event_data;
197 ioc_info(mrioc, "Device Info Changed: dev=0x%04x Form=0x%x\n",
198 event_data->dev_handle, event_data->device_form);
199 return;
200 }
201 case MPI3_EVENT_DEVICE_STATUS_CHANGE:
202 {
203 struct mpi3_event_data_device_status_change *event_data =
204 (struct mpi3_event_data_device_status_change *)event_reply->event_data;
205 ioc_info(mrioc, "Device status Change: dev=0x%04x RC=0x%x\n",
206 event_data->dev_handle, event_data->reason_code);
207 return;
208 }
209 case MPI3_EVENT_SAS_DISCOVERY:
210 {
211 struct mpi3_event_data_sas_discovery *event_data =
212 (struct mpi3_event_data_sas_discovery *)event_reply->event_data;
213 ioc_info(mrioc, "SAS Discovery: (%s) status (0x%08x)\n",
214 (event_data->reason_code == MPI3_EVENT_SAS_DISC_RC_STARTED) ?
215 "start" : "stop",
216 le32_to_cpu(event_data->discovery_status));
217 return;
218 }
219 case MPI3_EVENT_SAS_BROADCAST_PRIMITIVE:
220 desc = "SAS Broadcast Primitive";
221 break;
222 case MPI3_EVENT_SAS_NOTIFY_PRIMITIVE:
223 desc = "SAS Notify Primitive";
224 break;
225 case MPI3_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
226 desc = "SAS Init Device Status Change";
227 break;
228 case MPI3_EVENT_SAS_INIT_TABLE_OVERFLOW:
229 desc = "SAS Init Table Overflow";
230 break;
231 case MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
232 desc = "SAS Topology Change List";
233 break;
234 case MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE:
235 desc = "Enclosure Device Status Change";
236 break;
237 case MPI3_EVENT_HARD_RESET_RECEIVED:
238 desc = "Hard Reset Received";
239 break;
240 case MPI3_EVENT_SAS_PHY_COUNTER:
241 desc = "SAS PHY Counter";
242 break;
243 case MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR:
244 desc = "SAS Device Discovery Error";
245 break;
246 case MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST:
247 desc = "PCIE Topology Change List";
248 break;
249 case MPI3_EVENT_PCIE_ENUMERATION:
250 {
251 struct mpi3_event_data_pcie_enumeration *event_data =
252 (struct mpi3_event_data_pcie_enumeration *)event_reply->event_data;
253 ioc_info(mrioc, "PCIE Enumeration: (%s)",
254 (event_data->reason_code ==
255 MPI3_EVENT_PCIE_ENUM_RC_STARTED) ? "start" : "stop");
256 if (event_data->enumeration_status)
257 ioc_info(mrioc, "enumeration_status(0x%08x)\n",
258 le32_to_cpu(event_data->enumeration_status));
259 return;
260 }
261 case MPI3_EVENT_PREPARE_FOR_RESET:
262 desc = "Prepare For Reset";
263 break;
264 }
265
266 if (!desc)
267 return;
268
269 ioc_info(mrioc, "%s\n", desc);
270}
271
824a1566
KD		 272static void mpi3mr_handle_events(struct mpi3mr_ioc *mrioc,
273 struct mpi3_default_reply *def_reply)
274{
275 struct mpi3_event_notification_reply *event_reply =
276 (struct mpi3_event_notification_reply *)def_reply;
277
278 mrioc->change_count = le16_to_cpu(event_reply->ioc_change_count);
9fc4abfe 279 mpi3mr_print_event_data(mrioc, event_reply);
13ef29ea 280 mpi3mr_os_handle_events(mrioc, event_reply);
824a1566
KD		 281}
282
283static struct mpi3mr_drv_cmd *
284mpi3mr_get_drv_cmd(struct mpi3mr_ioc *mrioc, u16 host_tag,
285 struct mpi3_default_reply *def_reply)
286{
13ef29ea
KD		 287 u16 idx;
288
824a1566
KD		 289 switch (host_tag) {
290 case MPI3MR_HOSTTAG_INITCMDS:
291 return &mrioc->init_cmds;
e844adb1
KD		 292 case MPI3MR_HOSTTAG_BLK_TMS:
293 return &mrioc->host_tm_cmds;
824a1566
KD		 294 case MPI3MR_HOSTTAG_INVALID:
295 if (def_reply && def_reply->function ==
296 MPI3_FUNCTION_EVENT_NOTIFICATION)
297 mpi3mr_handle_events(mrioc, def_reply);
298 return NULL;
299 default:
300 break;
301 }
13ef29ea
KD		 302 if (host_tag >= MPI3MR_HOSTTAG_DEVRMCMD_MIN &&
303 host_tag <= MPI3MR_HOSTTAG_DEVRMCMD_MAX) {
304 idx = host_tag - MPI3MR_HOSTTAG_DEVRMCMD_MIN;
305 return &mrioc->dev_rmhs_cmds[idx];
306 }
824a1566
KD		 307
308 return NULL;
309}
310
311static void mpi3mr_process_admin_reply_desc(struct mpi3mr_ioc *mrioc,
312 struct mpi3_default_reply_descriptor *reply_desc, u64 *reply_dma)
313{
314 u16 reply_desc_type, host_tag = 0;
315 u16 ioc_status = MPI3_IOCSTATUS_SUCCESS;
316 u32 ioc_loginfo = 0;
317 struct mpi3_status_reply_descriptor *status_desc;
318 struct mpi3_address_reply_descriptor *addr_desc;
319 struct mpi3_success_reply_descriptor *success_desc;
320 struct mpi3_default_reply *def_reply = NULL;
321 struct mpi3mr_drv_cmd *cmdptr = NULL;
322 struct mpi3_scsi_io_reply *scsi_reply;
323 u8 *sense_buf = NULL;
324
325 *reply_dma = 0;
326 reply_desc_type = le16_to_cpu(reply_desc->reply_flags) &
327 MPI3_REPLY_DESCRIPT_FLAGS_TYPE_MASK;
328 switch (reply_desc_type) {
329 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_STATUS:
330 status_desc = (struct mpi3_status_reply_descriptor *)reply_desc;
331 host_tag = le16_to_cpu(status_desc->host_tag);
332 ioc_status = le16_to_cpu(status_desc->ioc_status);
333 if (ioc_status &
334 MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL)
335 ioc_loginfo = le32_to_cpu(status_desc->ioc_log_info);
336 ioc_status &= MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK;
337 break;
338 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_ADDRESS_REPLY:
339 addr_desc = (struct mpi3_address_reply_descriptor *)reply_desc;
340 *reply_dma = le64_to_cpu(addr_desc->reply_frame_address);
341 def_reply = mpi3mr_get_reply_virt_addr(mrioc, *reply_dma);
342 if (!def_reply)
343 goto out;
344 host_tag = le16_to_cpu(def_reply->host_tag);
345 ioc_status = le16_to_cpu(def_reply->ioc_status);
346 if (ioc_status &
347 MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL)
348 ioc_loginfo = le32_to_cpu(def_reply->ioc_log_info);
349 ioc_status &= MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK;
350 if (def_reply->function == MPI3_FUNCTION_SCSI_IO) {
351 scsi_reply = (struct mpi3_scsi_io_reply *)def_reply;
352 sense_buf = mpi3mr_get_sensebuf_virt_addr(mrioc,
353 le64_to_cpu(scsi_reply->sense_data_buffer_address));
354 }
355 break;
356 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_SUCCESS:
357 success_desc = (struct mpi3_success_reply_descriptor *)reply_desc;
358 host_tag = le16_to_cpu(success_desc->host_tag);
359 break;
360 default:
361 break;
362 }
363
364 cmdptr = mpi3mr_get_drv_cmd(mrioc, host_tag, def_reply);
365 if (cmdptr) {
366 if (cmdptr->state & MPI3MR_CMD_PENDING) {
367 cmdptr->state |= MPI3MR_CMD_COMPLETE;
368 cmdptr->ioc_loginfo = ioc_loginfo;
369 cmdptr->ioc_status = ioc_status;
370 cmdptr->state &= ~MPI3MR_CMD_PENDING;
371 if (def_reply) {
372 cmdptr->state |= MPI3MR_CMD_REPLY_VALID;
373 memcpy((u8 *)cmdptr->reply, (u8 *)def_reply,
374 mrioc->facts.reply_sz);
375 }
376 if (cmdptr->is_waiting) {
377 complete(&cmdptr->done);
378 cmdptr->is_waiting = 0;
379 } else if (cmdptr->callback)
380 cmdptr->callback(mrioc, cmdptr);
381 }
382 }
383out:
384 if (sense_buf)
385 mpi3mr_repost_sense_buf(mrioc,
386 le64_to_cpu(scsi_reply->sense_data_buffer_address));
387}
388
389static int mpi3mr_process_admin_reply_q(struct mpi3mr_ioc *mrioc)
390{
391 u32 exp_phase = mrioc->admin_reply_ephase;
392 u32 admin_reply_ci = mrioc->admin_reply_ci;
393 u32 num_admin_replies = 0;
394 u64 reply_dma = 0;
395 struct mpi3_default_reply_descriptor *reply_desc;
396
397 reply_desc = (struct mpi3_default_reply_descriptor *)mrioc->admin_reply_base +
398 admin_reply_ci;
399
400 if ((le16_to_cpu(reply_desc->reply_flags) &
401 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase)
402 return 0;
403
404 do {
405 mrioc->admin_req_ci = le16_to_cpu(reply_desc->request_queue_ci);
406 mpi3mr_process_admin_reply_desc(mrioc, reply_desc, &reply_dma);
407 if (reply_dma)
408 mpi3mr_repost_reply_buf(mrioc, reply_dma);
409 num_admin_replies++;
410 if (++admin_reply_ci == mrioc->num_admin_replies) {
411 admin_reply_ci = 0;
412 exp_phase ^= 1;
413 }
414 reply_desc =
415 (struct mpi3_default_reply_descriptor *)mrioc->admin_reply_base +
416 admin_reply_ci;
417 if ((le16_to_cpu(reply_desc->reply_flags) &
418 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase)
419 break;
420 } while (1);
421
422 writel(admin_reply_ci, &mrioc->sysif_regs->admin_reply_queue_ci);
423 mrioc->admin_reply_ci = admin_reply_ci;
424 mrioc->admin_reply_ephase = exp_phase;
425
426 return num_admin_replies;
427}
428
023ab2a9
KD		 429/**
430 * mpi3mr_get_reply_desc - get reply descriptor frame corresponding to
431 * queue's consumer index from operational reply descriptor queue.
432 * @op_reply_q: op_reply_qinfo object
433 * @reply_ci: operational reply descriptor's queue consumer index
434 *
435 * Returns reply descriptor frame address
436 */
437static inline struct mpi3_default_reply_descriptor *
438mpi3mr_get_reply_desc(struct op_reply_qinfo *op_reply_q, u32 reply_ci)
439{
440 void *segment_base_addr;
441 struct segments *segments = op_reply_q->q_segments;
442 struct mpi3_default_reply_descriptor *reply_desc = NULL;
443
444 segment_base_addr =
445 segments[reply_ci / op_reply_q->segment_qd].segment;
446 reply_desc = (struct mpi3_default_reply_descriptor *)segment_base_addr +
447 (reply_ci % op_reply_q->segment_qd);
448 return reply_desc;
449}
450
451static int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc,
452 struct mpi3mr_intr_info *intr_info)
453{
454 struct op_reply_qinfo *op_reply_q = intr_info->op_reply_q;
455 struct op_req_qinfo *op_req_q;
456 u32 exp_phase;
457 u32 reply_ci;
458 u32 num_op_reply = 0;
459 u64 reply_dma = 0;
460 struct mpi3_default_reply_descriptor *reply_desc;
461 u16 req_q_idx = 0, reply_qidx;
462
463 reply_qidx = op_reply_q->qid - 1;
464
463429f8
KD		 465 if (!atomic_add_unless(&op_reply_q->in_use, 1, 1))
466 return 0;
467
023ab2a9
KD		 468 exp_phase = op_reply_q->ephase;
469 reply_ci = op_reply_q->ci;
470
471 reply_desc = mpi3mr_get_reply_desc(op_reply_q, reply_ci);
472 if ((le16_to_cpu(reply_desc->reply_flags) &
473 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) {
463429f8 474 atomic_dec(&op_reply_q->in_use);
023ab2a9
KD		 475 return 0;
476 }
477
478 do {
479 req_q_idx = le16_to_cpu(reply_desc->request_queue_id) - 1;
480 op_req_q = &mrioc->req_qinfo[req_q_idx];
481
482 WRITE_ONCE(op_req_q->ci, le16_to_cpu(reply_desc->request_queue_ci));
483 mpi3mr_process_op_reply_desc(mrioc, reply_desc, &reply_dma,
484 reply_qidx);
463429f8 485 atomic_dec(&op_reply_q->pend_ios);
023ab2a9
KD		 486 if (reply_dma)
487 mpi3mr_repost_reply_buf(mrioc, reply_dma);
488 num_op_reply++;
489
490 if (++reply_ci == op_reply_q->num_replies) {
491 reply_ci = 0;
492 exp_phase ^= 1;
493 }
494
495 reply_desc = mpi3mr_get_reply_desc(op_reply_q, reply_ci);
496
497 if ((le16_to_cpu(reply_desc->reply_flags) &
498 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase)
499 break;
463429f8
KD		 500 /*
501 * Exit completion loop to avoid CPU lockup
502 * Ensure remaining completion happens from threaded ISR.
503 */
504 if (num_op_reply > mrioc->max_host_ios) {
505 intr_info->op_reply_q->enable_irq_poll = true;
506 break;
507 }
023ab2a9
KD		 508
509 } while (1);
510
511 writel(reply_ci,
512 &mrioc->sysif_regs->oper_queue_indexes[reply_qidx].consumer_index);
513 op_reply_q->ci = reply_ci;
514 op_reply_q->ephase = exp_phase;
515
463429f8 516 atomic_dec(&op_reply_q->in_use);
023ab2a9
KD		 517 return num_op_reply;
518}
519
824a1566
KD		 520static irqreturn_t mpi3mr_isr_primary(int irq, void *privdata)
521{
522 struct mpi3mr_intr_info *intr_info = privdata;
523 struct mpi3mr_ioc *mrioc;
524 u16 midx;
463429f8 525 u32 num_admin_replies = 0, num_op_reply = 0;
824a1566
KD		 526
527 if (!intr_info)
528 return IRQ_NONE;
529
530 mrioc = intr_info->mrioc;
531
532 if (!mrioc->intr_enabled)
533 return IRQ_NONE;
534
535 midx = intr_info->msix_index;
536
537 if (!midx)
538 num_admin_replies = mpi3mr_process_admin_reply_q(mrioc);
463429f8
KD		 539 if (intr_info->op_reply_q)
540 num_op_reply = mpi3mr_process_op_reply_q(mrioc, intr_info);
824a1566 541
463429f8 542 if (num_admin_replies || num_op_reply)
824a1566
KD		 543 return IRQ_HANDLED;
544 else
545 return IRQ_NONE;
546}
547
548static irqreturn_t mpi3mr_isr(int irq, void *privdata)
549{
550 struct mpi3mr_intr_info *intr_info = privdata;
463429f8
KD		 551 struct mpi3mr_ioc *mrioc;
552 u16 midx;
824a1566
KD		 553 int ret;
554
555 if (!intr_info)
556 return IRQ_NONE;
557
463429f8
KD		 558 mrioc = intr_info->mrioc;
559 midx = intr_info->msix_index;
824a1566
KD		 560 /* Call primary ISR routine */
561 ret = mpi3mr_isr_primary(irq, privdata);
562
463429f8
KD		 563 /*
564 * If more IOs are expected, schedule IRQ polling thread.
565 * Otherwise exit from ISR.
566 */
567 if (!intr_info->op_reply_q)
568 return ret;
569
570 if (!intr_info->op_reply_q->enable_irq_poll ||
571 !atomic_read(&intr_info->op_reply_q->pend_ios))
572 return ret;
573
574 disable_irq_nosync(pci_irq_vector(mrioc->pdev, midx));
575
576 return IRQ_WAKE_THREAD;
824a1566
KD		 577}
578
579/**
580 * mpi3mr_isr_poll - Reply queue polling routine
581 * @irq: IRQ
582 * @privdata: Interrupt info
583 *
584 * poll for pending I/O completions in a loop until pending I/Os
585 * present or controller queue depth I/Os are processed.
586 *
587 * Return: IRQ_NONE or IRQ_HANDLED
588 */
589static irqreturn_t mpi3mr_isr_poll(int irq, void *privdata)
590{
463429f8
KD		 591 struct mpi3mr_intr_info *intr_info = privdata;
592 struct mpi3mr_ioc *mrioc;
593 u16 midx;
594 u32 num_op_reply = 0;
595
596 if (!intr_info || !intr_info->op_reply_q)
597 return IRQ_NONE;
598
599 mrioc = intr_info->mrioc;
600 midx = intr_info->msix_index;
601
602 /* Poll for pending IOs completions */
603 do {
604 if (!mrioc->intr_enabled)
605 break;
606
607 if (!midx)
608 mpi3mr_process_admin_reply_q(mrioc);
609 if (intr_info->op_reply_q)
610 num_op_reply +=
611 mpi3mr_process_op_reply_q(mrioc, intr_info);
612
613 usleep_range(mrioc->irqpoll_sleep, 10 * mrioc->irqpoll_sleep);
614
615 } while (atomic_read(&intr_info->op_reply_q->pend_ios) &&
616 (num_op_reply < mrioc->max_host_ios));
617
618 intr_info->op_reply_q->enable_irq_poll = false;
619 enable_irq(pci_irq_vector(mrioc->pdev, midx));
620
824a1566
KD		 621 return IRQ_HANDLED;
622}
623
624/**
625 * mpi3mr_request_irq - Request IRQ and register ISR
626 * @mrioc: Adapter instance reference
627 * @index: IRQ vector index
628 *
629 * Request threaded ISR with primary ISR and secondary
630 *
631 * Return: 0 on success and non zero on failures.
632 */
633static inline int mpi3mr_request_irq(struct mpi3mr_ioc *mrioc, u16 index)
634{
635 struct pci_dev *pdev = mrioc->pdev;
636 struct mpi3mr_intr_info *intr_info = mrioc->intr_info + index;
637 int retval = 0;
638
639 intr_info->mrioc = mrioc;
640 intr_info->msix_index = index;
641 intr_info->op_reply_q = NULL;
642
643 snprintf(intr_info->name, MPI3MR_NAME_LENGTH, "%s%d-msix%d",
644 mrioc->driver_name, mrioc->id, index);
645
646 retval = request_threaded_irq(pci_irq_vector(pdev, index), mpi3mr_isr,
647 mpi3mr_isr_poll, IRQF_SHARED, intr_info->name, intr_info);
648 if (retval) {
649 ioc_err(mrioc, "%s: Unable to allocate interrupt %d!\n",
650 intr_info->name, pci_irq_vector(pdev, index));
651 return retval;
652 }
653
654 return retval;
655}
656
657/**
658 * mpi3mr_setup_isr - Setup ISR for the controller
659 * @mrioc: Adapter instance reference
660 * @setup_one: Request one IRQ or more
661 *
662 * Allocate IRQ vectors and call mpi3mr_request_irq to setup ISR
663 *
664 * Return: 0 on success and non zero on failures.
665 */
666static int mpi3mr_setup_isr(struct mpi3mr_ioc *mrioc, u8 setup_one)
667{
668 unsigned int irq_flags = PCI_IRQ_MSIX;
2938bedd
DC		 669 int max_vectors;
670 int retval;
671 int i;
824a1566
KD		 672 struct irq_affinity desc = { .pre_vectors = 1};
673
674 mpi3mr_cleanup_isr(mrioc);
675
676 if (setup_one || reset_devices)
677 max_vectors = 1;
678 else {
679 max_vectors =
680 min_t(int, mrioc->cpu_count + 1, mrioc->msix_count);
681
682 ioc_info(mrioc,
683 "MSI-X vectors supported: %d, no of cores: %d,",
684 mrioc->msix_count, mrioc->cpu_count);
685 ioc_info(mrioc,
686 "MSI-x vectors requested: %d\n", max_vectors);
687 }
688
689 irq_flags |= PCI_IRQ_AFFINITY | PCI_IRQ_ALL_TYPES;
690
c9566231 691 mrioc->op_reply_q_offset = (max_vectors > 1) ? 1 : 0;
2938bedd
DC		 692 retval = pci_alloc_irq_vectors_affinity(mrioc->pdev,
693 1, max_vectors, irq_flags, &desc);
694 if (retval < 0) {
824a1566
KD		 695 ioc_err(mrioc, "Cannot alloc irq vectors\n");
696 goto out_failed;
697 }
2938bedd 698 if (retval != max_vectors) {
824a1566
KD		 699 ioc_info(mrioc,
700 "allocated vectors (%d) are less than configured (%d)\n",
2938bedd 701 retval, max_vectors);
c9566231
KD		 702 /*
703 * If only one MSI-x is allocated, then MSI-x 0 will be shared
704 * between Admin queue and operational queue
705 */
2938bedd 706 if (retval == 1)
c9566231 707 mrioc->op_reply_q_offset = 0;
824a1566 708
2938bedd 709 max_vectors = retval;
824a1566
KD		 710 }
711 mrioc->intr_info = kzalloc(sizeof(struct mpi3mr_intr_info) * max_vectors,
712 GFP_KERNEL);
713 if (!mrioc->intr_info) {
2938bedd 714 retval = -ENOMEM;
824a1566
KD		 715 pci_free_irq_vectors(mrioc->pdev);
716 goto out_failed;
717 }
718 for (i = 0; i < max_vectors; i++) {
719 retval = mpi3mr_request_irq(mrioc, i);
720 if (retval) {
721 mrioc->intr_info_count = i;
722 goto out_failed;
723 }
724 }
725 mrioc->intr_info_count = max_vectors;
726 mpi3mr_ioc_enable_intr(mrioc);
2938bedd
DC		 727 return 0;
728
824a1566
KD		 729out_failed:
730 mpi3mr_cleanup_isr(mrioc);
731
732 return retval;
733}
734
735static const struct {
736 enum mpi3mr_iocstate value;
737 char *name;
738} mrioc_states[] = {
739 { MRIOC_STATE_READY, "ready" },
740 { MRIOC_STATE_FAULT, "fault" },
741 { MRIOC_STATE_RESET, "reset" },
742 { MRIOC_STATE_BECOMING_READY, "becoming ready" },
743 { MRIOC_STATE_RESET_REQUESTED, "reset requested" },
744 { MRIOC_STATE_UNRECOVERABLE, "unrecoverable error" },
745};
746
747static const char *mpi3mr_iocstate_name(enum mpi3mr_iocstate mrioc_state)
748{
749 int i;
750 char *name = NULL;
751
752 for (i = 0; i < ARRAY_SIZE(mrioc_states); i++) {
753 if (mrioc_states[i].value == mrioc_state) {
754 name = mrioc_states[i].name;
755 break;
756 }
757 }
758 return name;
759}
760
f061178e
KD		 761/* Reset reason to name mapper structure*/
762static const struct {
763 enum mpi3mr_reset_reason value;
764 char *name;
765} mpi3mr_reset_reason_codes[] = {
766 { MPI3MR_RESET_FROM_BRINGUP, "timeout in bringup" },
767 { MPI3MR_RESET_FROM_FAULT_WATCH, "fault" },
768 { MPI3MR_RESET_FROM_IOCTL, "application invocation" },
769 { MPI3MR_RESET_FROM_EH_HOS, "error handling" },
770 { MPI3MR_RESET_FROM_TM_TIMEOUT, "TM timeout" },
771 { MPI3MR_RESET_FROM_IOCTL_TIMEOUT, "IOCTL timeout" },
772 { MPI3MR_RESET_FROM_MUR_FAILURE, "MUR failure" },
773 { MPI3MR_RESET_FROM_CTLR_CLEANUP, "timeout in controller cleanup" },
774 { MPI3MR_RESET_FROM_CIACTIV_FAULT, "component image activation fault" },
775 { MPI3MR_RESET_FROM_PE_TIMEOUT, "port enable timeout" },
776 { MPI3MR_RESET_FROM_TSU_TIMEOUT, "time stamp update timeout" },
777 { MPI3MR_RESET_FROM_DELREQQ_TIMEOUT, "delete request queue timeout" },
778 { MPI3MR_RESET_FROM_DELREPQ_TIMEOUT, "delete reply queue timeout" },
779 {
780 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT,
781 "create request queue timeout"
782 },
783 {
784 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT,
785 "create reply queue timeout"
786 },
787 { MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT, "IOC facts timeout" },
788 { MPI3MR_RESET_FROM_IOCINIT_TIMEOUT, "IOC init timeout" },
789 { MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT, "event notify timeout" },
790 { MPI3MR_RESET_FROM_EVTACK_TIMEOUT, "event acknowledgment timeout" },
791 {
792 MPI3MR_RESET_FROM_CIACTVRST_TIMER,
793 "component image activation timeout"
794 },
795 {
796 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT,
797 "get package version timeout"
798 },
799 { MPI3MR_RESET_FROM_SYSFS, "sysfs invocation" },
800 { MPI3MR_RESET_FROM_SYSFS_TIMEOUT, "sysfs TM timeout" },
801};
802
803/**
804 * mpi3mr_reset_rc_name - get reset reason code name
805 * @reason_code: reset reason code value
806 *
807 * Map reset reason to an NULL terminated ASCII string
808 *
809 * Return: name corresponding to reset reason value or NULL.
810 */
811static const char *mpi3mr_reset_rc_name(enum mpi3mr_reset_reason reason_code)
812{
813 int i;
814 char *name = NULL;
815
816 for (i = 0; i < ARRAY_SIZE(mpi3mr_reset_reason_codes); i++) {
817 if (mpi3mr_reset_reason_codes[i].value == reason_code) {
818 name = mpi3mr_reset_reason_codes[i].name;
819 break;
820 }
821 }
822 return name;
823}
824
825/* Reset type to name mapper structure*/
826static const struct {
827 u16 reset_type;
828 char *name;
829} mpi3mr_reset_types[] = {
830 { MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, "soft" },
831 { MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, "diag fault" },
832};
833
834/**
835 * mpi3mr_reset_type_name - get reset type name
836 * @reset_type: reset type value
837 *
838 * Map reset type to an NULL terminated ASCII string
839 *
840 * Return: name corresponding to reset type value or NULL.
841 */
842static const char *mpi3mr_reset_type_name(u16 reset_type)
843{
844 int i;
845 char *name = NULL;
846
847 for (i = 0; i < ARRAY_SIZE(mpi3mr_reset_types); i++) {
848 if (mpi3mr_reset_types[i].reset_type == reset_type) {
849 name = mpi3mr_reset_types[i].name;
850 break;
851 }
852 }
853 return name;
854}
855
824a1566
KD		 856/**
857 * mpi3mr_print_fault_info - Display fault information
858 * @mrioc: Adapter instance reference
859 *
860 * Display the controller fault information if there is a
861 * controller fault.
862 *
863 * Return: Nothing.
864 */
865static void mpi3mr_print_fault_info(struct mpi3mr_ioc *mrioc)
866{
867 u32 ioc_status, code, code1, code2, code3;
868
869 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
870
871 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) {
872 code = readl(&mrioc->sysif_regs->fault);
873 code1 = readl(&mrioc->sysif_regs->fault_info[0]);
874 code2 = readl(&mrioc->sysif_regs->fault_info[1]);
875 code3 = readl(&mrioc->sysif_regs->fault_info[2]);
876
877 ioc_info(mrioc,
878 "fault code(0x%08X): Additional code: (0x%08X:0x%08X:0x%08X)\n",
879 code, code1, code2, code3);
880 }
881}
882
883/**
884 * mpi3mr_get_iocstate - Get IOC State
885 * @mrioc: Adapter instance reference
886 *
887 * Return a proper IOC state enum based on the IOC status and
888 * IOC configuration and unrcoverable state of the controller.
889 *
890 * Return: Current IOC state.
891 */
892enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc)
893{
894 u32 ioc_status, ioc_config;
895 u8 ready, enabled;
896
897 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
898 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
899
900 if (mrioc->unrecoverable)
901 return MRIOC_STATE_UNRECOVERABLE;
902 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)
903 return MRIOC_STATE_FAULT;
904
905 ready = (ioc_status & MPI3_SYSIF_IOC_STATUS_READY);
906 enabled = (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC);
907
908 if (ready && enabled)
909 return MRIOC_STATE_READY;
910 if ((!ready) && (!enabled))
911 return MRIOC_STATE_RESET;
912 if ((!ready) && (enabled))
913 return MRIOC_STATE_BECOMING_READY;
914
915 return MRIOC_STATE_RESET_REQUESTED;
916}
917
918/**
919 * mpi3mr_clear_reset_history - clear reset history
920 * @mrioc: Adapter instance reference
921 *
922 * Write the reset history bit in IOC status to clear the bit,
923 * if it is already set.
924 *
925 * Return: Nothing.
926 */
927static inline void mpi3mr_clear_reset_history(struct mpi3mr_ioc *mrioc)
928{
929 u32 ioc_status;
930
931 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
932 if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)
933 writel(ioc_status, &mrioc->sysif_regs->ioc_status);
934}
935
936/**
937 * mpi3mr_issue_and_process_mur - Message unit Reset handler
938 * @mrioc: Adapter instance reference
939 * @reset_reason: Reset reason code
940 *
941 * Issue Message unit Reset to the controller and wait for it to
942 * be complete.
943 *
944 * Return: 0 on success, -1 on failure.
945 */
946static int mpi3mr_issue_and_process_mur(struct mpi3mr_ioc *mrioc,
947 u32 reset_reason)
948{
949 u32 ioc_config, timeout, ioc_status;
950 int retval = -1;
951
952 ioc_info(mrioc, "Issuing Message unit Reset(MUR)\n");
953 if (mrioc->unrecoverable) {
954 ioc_info(mrioc, "IOC is unrecoverable MUR not issued\n");
955 return retval;
956 }
957 mpi3mr_clear_reset_history(mrioc);
958 writel(reset_reason, &mrioc->sysif_regs->scratchpad[0]);
959 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
960 ioc_config &= ~MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC;
961 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
962
963 timeout = mrioc->ready_timeout * 10;
964 do {
965 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
966 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)) {
967 mpi3mr_clear_reset_history(mrioc);
968 ioc_config =
969 readl(&mrioc->sysif_regs->ioc_configuration);
970 if (!((ioc_status & MPI3_SYSIF_IOC_STATUS_READY) ||
971 (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) ||
972 (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC))) {
973 retval = 0;
974 break;
975 }
976 }
977 msleep(100);
978 } while (--timeout);
979
980 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
981 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
982
983 ioc_info(mrioc, "Base IOC Sts/Config after %s MUR is (0x%x)/(0x%x)\n",
984 (!retval) ? "successful" : "failed", ioc_status, ioc_config);
985 return retval;
986}
987
988/**
989 * mpi3mr_bring_ioc_ready - Bring controller to ready state
990 * @mrioc: Adapter instance reference
991 *
992 * Set Enable IOC bit in IOC configuration register and wait for
993 * the controller to become ready.
994 *
995 * Return: 0 on success, -1 on failure.
996 */
997static int mpi3mr_bring_ioc_ready(struct mpi3mr_ioc *mrioc)
998{
999 u32 ioc_config, timeout;
1000 enum mpi3mr_iocstate current_state;
1001
1002 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1003 ioc_config |= MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC;
1004 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
1005
1006 timeout = mrioc->ready_timeout * 10;
1007 do {
1008 current_state = mpi3mr_get_iocstate(mrioc);
1009 if (current_state == MRIOC_STATE_READY)
1010 return 0;
1011 msleep(100);
1012 } while (--timeout);
1013
1014 return -1;
1015}
1016
f061178e
KD		 1017/**
1018 * mpi3mr_soft_reset_success - Check softreset is success or not
1019 * @ioc_status: IOC status register value
1020 * @ioc_config: IOC config register value
1021 *
1022 * Check whether the soft reset is successful or not based on
1023 * IOC status and IOC config register values.
1024 *
1025 * Return: True when the soft reset is success, false otherwise.
1026 */
1027static inline bool
1028mpi3mr_soft_reset_success(u32 ioc_status, u32 ioc_config)
1029{
1030 if (!((ioc_status & MPI3_SYSIF_IOC_STATUS_READY) ||
1031 (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) ||
1032 (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC)))
1033 return true;
1034 return false;
1035}
1036
1037/**
1038 * mpi3mr_diagfault_success - Check diag fault is success or not
1039 * @mrioc: Adapter reference
1040 * @ioc_status: IOC status register value
1041 *
1042 * Check whether the controller hit diag reset fault code.
1043 *
1044 * Return: True when there is diag fault, false otherwise.
1045 */
1046static inline bool mpi3mr_diagfault_success(struct mpi3mr_ioc *mrioc,
1047 u32 ioc_status)
1048{
1049 u32 fault;
1050
1051 if (!(ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT))
1052 return false;
1053 fault = readl(&mrioc->sysif_regs->fault) & MPI3_SYSIF_FAULT_CODE_MASK;
1054 if (fault == MPI3_SYSIF_FAULT_CODE_DIAG_FAULT_RESET)
1055 return true;
1056 return false;
1057}
1058
824a1566
KD		 1059/**
1060 * mpi3mr_set_diagsave - Set diag save bit for snapdump
1061 * @mrioc: Adapter reference
1062 *
1063 * Set diag save bit in IOC configuration register to enable
1064 * snapdump.
1065 *
1066 * Return: Nothing.
1067 */
1068static inline void mpi3mr_set_diagsave(struct mpi3mr_ioc *mrioc)
1069{
1070 u32 ioc_config;
1071
1072 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1073 ioc_config |= MPI3_SYSIF_IOC_CONFIG_DIAG_SAVE;
1074 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
1075}
1076
1077/**
1078 * mpi3mr_issue_reset - Issue reset to the controller
1079 * @mrioc: Adapter reference
1080 * @reset_type: Reset type
1081 * @reset_reason: Reset reason code
1082 *
f061178e
KD		 1083 * Unlock the host diagnostic registers and write the specific
1084 * reset type to that, wait for reset acknowledgment from the
1085 * controller, if the reset is not successful retry for the
1086 * predefined number of times.
824a1566
KD		 1087 *
1088 * Return: 0 on success, non-zero on failure.
1089 */
1090static int mpi3mr_issue_reset(struct mpi3mr_ioc *mrioc, u16 reset_type,
1091 u32 reset_reason)
1092{
f061178e
KD		 1093 int retval = -1;
1094 u8 unlock_retry_count, reset_retry_count = 0;
1095 u32 host_diagnostic, timeout, ioc_status, ioc_config;
1096
1097 pci_cfg_access_lock(mrioc->pdev);
1098 if ((reset_type != MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET) &&
1099 (reset_type != MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT))
1100 goto out;
1101 if (mrioc->unrecoverable)
1102 goto out;
1103retry_reset:
1104 unlock_retry_count = 0;
1105 mpi3mr_clear_reset_history(mrioc);
1106 do {
1107 ioc_info(mrioc,
1108 "Write magic sequence to unlock host diag register (retry=%d)\n",
1109 ++unlock_retry_count);
1110 if (unlock_retry_count >= MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT) {
1111 writel(reset_reason, &mrioc->sysif_regs->scratchpad[0]);
1112 mrioc->unrecoverable = 1;
1113 goto out;
1114 }
1115
1116 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_FLUSH,
1117 &mrioc->sysif_regs->write_sequence);
1118 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_1ST,
1119 &mrioc->sysif_regs->write_sequence);
1120 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND,
1121 &mrioc->sysif_regs->write_sequence);
1122 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_3RD,
1123 &mrioc->sysif_regs->write_sequence);
1124 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_4TH,
1125 &mrioc->sysif_regs->write_sequence);
1126 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_5TH,
1127 &mrioc->sysif_regs->write_sequence);
1128 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_6TH,
1129 &mrioc->sysif_regs->write_sequence);
1130 usleep_range(1000, 1100);
1131 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic);
1132 ioc_info(mrioc,
1133 "wrote magic sequence: retry_count(%d), host_diagnostic(0x%08x)\n",
1134 unlock_retry_count, host_diagnostic);
1135 } while (!(host_diagnostic & MPI3_SYSIF_HOST_DIAG_DIAG_WRITE_ENABLE));
1136
1137 writel(reset_reason, &mrioc->sysif_regs->scratchpad[0]);
1138 ioc_info(mrioc, "%s reset due to %s(0x%x)\n",
1139 mpi3mr_reset_type_name(reset_type),
1140 mpi3mr_reset_rc_name(reset_reason), reset_reason);
1141 writel(host_diagnostic | reset_type,
1142 &mrioc->sysif_regs->host_diagnostic);
1143 timeout = mrioc->ready_timeout * 10;
1144 if (reset_type == MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET) {
1145 do {
1146 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1147 if (ioc_status &
1148 MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) {
1149 mpi3mr_clear_reset_history(mrioc);
1150 ioc_config =
1151 readl(&mrioc->sysif_regs->ioc_configuration);
1152 if (mpi3mr_soft_reset_success(ioc_status,
1153 ioc_config)) {
1154 retval = 0;
1155 break;
1156 }
1157 }
1158 msleep(100);
1159 } while (--timeout);
1160 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND,
1161 &mrioc->sysif_regs->write_sequence);
1162 } else if (reset_type == MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT) {
1163 do {
1164 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1165 if (mpi3mr_diagfault_success(mrioc, ioc_status)) {
1166 retval = 0;
1167 break;
1168 }
1169 msleep(100);
1170 } while (--timeout);
1171 mpi3mr_clear_reset_history(mrioc);
1172 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND,
1173 &mrioc->sysif_regs->write_sequence);
1174 }
1175 if (retval && ((++reset_retry_count) < MPI3MR_MAX_RESET_RETRY_COUNT)) {
1176 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1177 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1178 ioc_info(mrioc,
1179 "Base IOC Sts/Config after reset try %d is (0x%x)/(0x%x)\n",
1180 reset_retry_count, ioc_status, ioc_config);
1181 goto retry_reset;
1182 }
1183
1184out:
1185 pci_cfg_access_unlock(mrioc->pdev);
1186 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1187 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1188
1189 ioc_info(mrioc,
1190 "Base IOC Sts/Config after %s reset is (0x%x)/(0x%x)\n",
1191 (!retval) ? "successful" : "failed", ioc_status,
1192 ioc_config);
1193 return retval;
824a1566
KD		 1194}
1195
1196/**
1197 * mpi3mr_admin_request_post - Post request to admin queue
1198 * @mrioc: Adapter reference
1199 * @admin_req: MPI3 request
1200 * @admin_req_sz: Request size
1201 * @ignore_reset: Ignore reset in process
1202 *
1203 * Post the MPI3 request into admin request queue and
1204 * inform the controller, if the queue is full return
1205 * appropriate error.
1206 *
1207 * Return: 0 on success, non-zero on failure.
1208 */
1209int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req,
1210 u16 admin_req_sz, u8 ignore_reset)
1211{
1212 u16 areq_pi = 0, areq_ci = 0, max_entries = 0;
1213 int retval = 0;
1214 unsigned long flags;
1215 u8 *areq_entry;
1216
1217 if (mrioc->unrecoverable) {
1218 ioc_err(mrioc, "%s : Unrecoverable controller\n", __func__);
1219 return -EFAULT;
1220 }
1221
1222 spin_lock_irqsave(&mrioc->admin_req_lock, flags);
1223 areq_pi = mrioc->admin_req_pi;
1224 areq_ci = mrioc->admin_req_ci;
1225 max_entries = mrioc->num_admin_req;
1226 if ((areq_ci == (areq_pi + 1)) || ((!areq_ci) &&
1227 (areq_pi == (max_entries - 1)))) {
1228 ioc_err(mrioc, "AdminReqQ full condition detected\n");
1229 retval = -EAGAIN;
1230 goto out;
1231 }
1232 if (!ignore_reset && mrioc->reset_in_progress) {
1233 ioc_err(mrioc, "AdminReqQ submit reset in progress\n");
1234 retval = -EAGAIN;
1235 goto out;
1236 }
1237 areq_entry = (u8 *)mrioc->admin_req_base +
1238 (areq_pi * MPI3MR_ADMIN_REQ_FRAME_SZ);
1239 memset(areq_entry, 0, MPI3MR_ADMIN_REQ_FRAME_SZ);
1240 memcpy(areq_entry, (u8 *)admin_req, admin_req_sz);
1241
1242 if (++areq_pi == max_entries)
1243 areq_pi = 0;
1244 mrioc->admin_req_pi = areq_pi;
1245
1246 writel(mrioc->admin_req_pi, &mrioc->sysif_regs->admin_request_queue_pi);
1247
1248out:
1249 spin_unlock_irqrestore(&mrioc->admin_req_lock, flags);
1250
1251 return retval;
1252}
1253
c9566231
KD		 1254/**
1255 * mpi3mr_free_op_req_q_segments - free request memory segments
1256 * @mrioc: Adapter instance reference
1257 * @q_idx: operational request queue index
1258 *
1259 * Free memory segments allocated for operational request queue
1260 *
1261 * Return: Nothing.
1262 */
1263static void mpi3mr_free_op_req_q_segments(struct mpi3mr_ioc *mrioc, u16 q_idx)
1264{
1265 u16 j;
1266 int size;
1267 struct segments *segments;
1268
1269 segments = mrioc->req_qinfo[q_idx].q_segments;
1270 if (!segments)
1271 return;
1272
1273 if (mrioc->enable_segqueue) {
1274 size = MPI3MR_OP_REQ_Q_SEG_SIZE;
1275 if (mrioc->req_qinfo[q_idx].q_segment_list) {
1276 dma_free_coherent(&mrioc->pdev->dev,
1277 MPI3MR_MAX_SEG_LIST_SIZE,
1278 mrioc->req_qinfo[q_idx].q_segment_list,
1279 mrioc->req_qinfo[q_idx].q_segment_list_dma);
6377de25 1280 mrioc->req_qinfo[q_idx].q_segment_list = NULL;
c9566231
KD		 1281 }
1282 } else
a60737a3 1283 size = mrioc->req_qinfo[q_idx].segment_qd *
c9566231
KD		 1284 mrioc->facts.op_req_sz;
1285
1286 for (j = 0; j < mrioc->req_qinfo[q_idx].num_segments; j++) {
1287 if (!segments[j].segment)
1288 continue;
1289 dma_free_coherent(&mrioc->pdev->dev,
1290 size, segments[j].segment, segments[j].segment_dma);
1291 segments[j].segment = NULL;
1292 }
1293 kfree(mrioc->req_qinfo[q_idx].q_segments);
1294 mrioc->req_qinfo[q_idx].q_segments = NULL;
1295 mrioc->req_qinfo[q_idx].qid = 0;
1296}
1297
1298/**
1299 * mpi3mr_free_op_reply_q_segments - free reply memory segments
1300 * @mrioc: Adapter instance reference
1301 * @q_idx: operational reply queue index
1302 *
1303 * Free memory segments allocated for operational reply queue
1304 *
1305 * Return: Nothing.
1306 */
1307static void mpi3mr_free_op_reply_q_segments(struct mpi3mr_ioc *mrioc, u16 q_idx)
1308{
1309 u16 j;
1310 int size;
1311 struct segments *segments;
1312
1313 segments = mrioc->op_reply_qinfo[q_idx].q_segments;
1314 if (!segments)
1315 return;
1316
1317 if (mrioc->enable_segqueue) {
1318 size = MPI3MR_OP_REP_Q_SEG_SIZE;
1319 if (mrioc->op_reply_qinfo[q_idx].q_segment_list) {
1320 dma_free_coherent(&mrioc->pdev->dev,
1321 MPI3MR_MAX_SEG_LIST_SIZE,
1322 mrioc->op_reply_qinfo[q_idx].q_segment_list,
1323 mrioc->op_reply_qinfo[q_idx].q_segment_list_dma);
1324 mrioc->op_reply_qinfo[q_idx].q_segment_list = NULL;
1325 }
1326 } else
1327 size = mrioc->op_reply_qinfo[q_idx].segment_qd *
1328 mrioc->op_reply_desc_sz;
1329
1330 for (j = 0; j < mrioc->op_reply_qinfo[q_idx].num_segments; j++) {
1331 if (!segments[j].segment)
1332 continue;
1333 dma_free_coherent(&mrioc->pdev->dev,
1334 size, segments[j].segment, segments[j].segment_dma);
1335 segments[j].segment = NULL;
1336 }
1337
1338 kfree(mrioc->op_reply_qinfo[q_idx].q_segments);
1339 mrioc->op_reply_qinfo[q_idx].q_segments = NULL;
1340 mrioc->op_reply_qinfo[q_idx].qid = 0;
1341}
1342
1343/**
1344 * mpi3mr_delete_op_reply_q - delete operational reply queue
1345 * @mrioc: Adapter instance reference
1346 * @qidx: operational reply queue index
1347 *
1348 * Delete operatinal reply queue by issuing MPI request
1349 * through admin queue.
1350 *
1351 * Return: 0 on success, non-zero on failure.
1352 */
1353static int mpi3mr_delete_op_reply_q(struct mpi3mr_ioc *mrioc, u16 qidx)
1354{
1355 struct mpi3_delete_reply_queue_request delq_req;
1356 int retval = 0;
1357 u16 reply_qid = 0, midx;
1358
1359 reply_qid = mrioc->op_reply_qinfo[qidx].qid;
1360
1361 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, mrioc->op_reply_q_offset);
1362
1363 if (!reply_qid) {
1364 retval = -1;
1365 ioc_err(mrioc, "Issue DelRepQ: called with invalid ReqQID\n");
1366 goto out;
1367 }
1368
1369 memset(&delq_req, 0, sizeof(delq_req));
1370 mutex_lock(&mrioc->init_cmds.mutex);
1371 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
1372 retval = -1;
1373 ioc_err(mrioc, "Issue DelRepQ: Init command is in use\n");
1374 mutex_unlock(&mrioc->init_cmds.mutex);
1375 goto out;
1376 }
1377 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
1378 mrioc->init_cmds.is_waiting = 1;
1379 mrioc->init_cmds.callback = NULL;
1380 delq_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
1381 delq_req.function = MPI3_FUNCTION_DELETE_REPLY_QUEUE;
1382 delq_req.queue_id = cpu_to_le16(reply_qid);
1383
1384 init_completion(&mrioc->init_cmds.done);
1385 retval = mpi3mr_admin_request_post(mrioc, &delq_req, sizeof(delq_req),
1386 1);
1387 if (retval) {
1388 ioc_err(mrioc, "Issue DelRepQ: Admin Post failed\n");
1389 goto out_unlock;
1390 }
1391 wait_for_completion_timeout(&mrioc->init_cmds.done,
1392 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
1393 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
1394 ioc_err(mrioc, "Issue DelRepQ: command timed out\n");
1395 mpi3mr_set_diagsave(mrioc);
1396 mpi3mr_issue_reset(mrioc,
1397 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
1398 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT);
1399 mrioc->unrecoverable = 1;
1400
1401 retval = -1;
1402 goto out_unlock;
1403 }
1404 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
1405 != MPI3_IOCSTATUS_SUCCESS) {
1406 ioc_err(mrioc,
1407 "Issue DelRepQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
1408 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
1409 mrioc->init_cmds.ioc_loginfo);
1410 retval = -1;
1411 goto out_unlock;
1412 }
1413 mrioc->intr_info[midx].op_reply_q = NULL;
1414
1415 mpi3mr_free_op_reply_q_segments(mrioc, qidx);
1416out_unlock:
1417 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
1418 mutex_unlock(&mrioc->init_cmds.mutex);
1419out:
1420
1421 return retval;
1422}
1423
1424/**
1425 * mpi3mr_alloc_op_reply_q_segments -Alloc segmented reply pool
1426 * @mrioc: Adapter instance reference
1427 * @qidx: request queue index
1428 *
1429 * Allocate segmented memory pools for operational reply
1430 * queue.
1431 *
1432 * Return: 0 on success, non-zero on failure.
1433 */
1434static int mpi3mr_alloc_op_reply_q_segments(struct mpi3mr_ioc *mrioc, u16 qidx)
1435{
1436 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
1437 int i, size;
1438 u64 *q_segment_list_entry = NULL;
1439 struct segments *segments;
1440
1441 if (mrioc->enable_segqueue) {
1442 op_reply_q->segment_qd =
1443 MPI3MR_OP_REP_Q_SEG_SIZE / mrioc->op_reply_desc_sz;
1444
1445 size = MPI3MR_OP_REP_Q_SEG_SIZE;
1446
1447 op_reply_q->q_segment_list = dma_alloc_coherent(&mrioc->pdev->dev,
1448 MPI3MR_MAX_SEG_LIST_SIZE, &op_reply_q->q_segment_list_dma,
1449 GFP_KERNEL);
1450 if (!op_reply_q->q_segment_list)
1451 return -ENOMEM;
1452 q_segment_list_entry = (u64 *)op_reply_q->q_segment_list;
1453 } else {
1454 op_reply_q->segment_qd = op_reply_q->num_replies;
1455 size = op_reply_q->num_replies * mrioc->op_reply_desc_sz;
1456 }
1457
1458 op_reply_q->num_segments = DIV_ROUND_UP(op_reply_q->num_replies,
1459 op_reply_q->segment_qd);
1460
1461 op_reply_q->q_segments = kcalloc(op_reply_q->num_segments,
1462 sizeof(struct segments), GFP_KERNEL);
1463 if (!op_reply_q->q_segments)
1464 return -ENOMEM;
1465
1466 segments = op_reply_q->q_segments;
1467 for (i = 0; i < op_reply_q->num_segments; i++) {
1468 segments[i].segment =
1469 dma_alloc_coherent(&mrioc->pdev->dev,
1470 size, &segments[i].segment_dma, GFP_KERNEL);
1471 if (!segments[i].segment)
1472 return -ENOMEM;
1473 if (mrioc->enable_segqueue)
1474 q_segment_list_entry[i] =
1475 (unsigned long)segments[i].segment_dma;
1476 }
1477
1478 return 0;
1479}
1480
1481/**
1482 * mpi3mr_alloc_op_req_q_segments - Alloc segmented req pool.
1483 * @mrioc: Adapter instance reference
1484 * @qidx: request queue index
1485 *
1486 * Allocate segmented memory pools for operational request
1487 * queue.
1488 *
1489 * Return: 0 on success, non-zero on failure.
1490 */
1491static int mpi3mr_alloc_op_req_q_segments(struct mpi3mr_ioc *mrioc, u16 qidx)
1492{
1493 struct op_req_qinfo *op_req_q = mrioc->req_qinfo + qidx;
1494 int i, size;
1495 u64 *q_segment_list_entry = NULL;
1496 struct segments *segments;
1497
1498 if (mrioc->enable_segqueue) {
1499 op_req_q->segment_qd =
1500 MPI3MR_OP_REQ_Q_SEG_SIZE / mrioc->facts.op_req_sz;
1501
1502 size = MPI3MR_OP_REQ_Q_SEG_SIZE;
1503
1504 op_req_q->q_segment_list = dma_alloc_coherent(&mrioc->pdev->dev,
1505 MPI3MR_MAX_SEG_LIST_SIZE, &op_req_q->q_segment_list_dma,
1506 GFP_KERNEL);
1507 if (!op_req_q->q_segment_list)
1508 return -ENOMEM;
1509 q_segment_list_entry = (u64 *)op_req_q->q_segment_list;
1510
1511 } else {
1512 op_req_q->segment_qd = op_req_q->num_requests;
1513 size = op_req_q->num_requests * mrioc->facts.op_req_sz;
1514 }
1515
1516 op_req_q->num_segments = DIV_ROUND_UP(op_req_q->num_requests,
1517 op_req_q->segment_qd);
1518
1519 op_req_q->q_segments = kcalloc(op_req_q->num_segments,
1520 sizeof(struct segments), GFP_KERNEL);
1521 if (!op_req_q->q_segments)
1522 return -ENOMEM;
1523
1524 segments = op_req_q->q_segments;
1525 for (i = 0; i < op_req_q->num_segments; i++) {
1526 segments[i].segment =
1527 dma_alloc_coherent(&mrioc->pdev->dev,
1528 size, &segments[i].segment_dma, GFP_KERNEL);
1529 if (!segments[i].segment)
1530 return -ENOMEM;
1531 if (mrioc->enable_segqueue)
1532 q_segment_list_entry[i] =
1533 (unsigned long)segments[i].segment_dma;
1534 }
1535
1536 return 0;
1537}
1538
1539/**
1540 * mpi3mr_create_op_reply_q - create operational reply queue
1541 * @mrioc: Adapter instance reference
1542 * @qidx: operational reply queue index
1543 *
1544 * Create operatinal reply queue by issuing MPI request
1545 * through admin queue.
1546 *
1547 * Return: 0 on success, non-zero on failure.
1548 */
1549static int mpi3mr_create_op_reply_q(struct mpi3mr_ioc *mrioc, u16 qidx)
1550{
1551 struct mpi3_create_reply_queue_request create_req;
1552 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
1553 int retval = 0;
1554 u16 reply_qid = 0, midx;
1555
1556 reply_qid = op_reply_q->qid;
1557
1558 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, mrioc->op_reply_q_offset);
1559
1560 if (reply_qid) {
1561 retval = -1;
1562 ioc_err(mrioc, "CreateRepQ: called for duplicate qid %d\n",
1563 reply_qid);
1564
1565 return retval;
1566 }
1567
1568 reply_qid = qidx + 1;
1569 op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD;
a60737a3
SR		 1570 if (!mrioc->pdev->revision)
1571 op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD4K;
c9566231
KD		 1572 op_reply_q->ci = 0;
1573 op_reply_q->ephase = 1;
463429f8
KD		 1574 atomic_set(&op_reply_q->pend_ios, 0);
1575 atomic_set(&op_reply_q->in_use, 0);
1576 op_reply_q->enable_irq_poll = false;
c9566231
KD		 1577
1578 if (!op_reply_q->q_segments) {
1579 retval = mpi3mr_alloc_op_reply_q_segments(mrioc, qidx);
1580 if (retval) {
1581 mpi3mr_free_op_reply_q_segments(mrioc, qidx);
1582 goto out;
1583 }
1584 }
1585
1586 memset(&create_req, 0, sizeof(create_req));
1587 mutex_lock(&mrioc->init_cmds.mutex);
1588 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
1589 retval = -1;
1590 ioc_err(mrioc, "CreateRepQ: Init command is in use\n");
f9dc034d 1591 goto out_unlock;
c9566231
KD		 1592 }
1593 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
1594 mrioc->init_cmds.is_waiting = 1;
1595 mrioc->init_cmds.callback = NULL;
1596 create_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
1597 create_req.function = MPI3_FUNCTION_CREATE_REPLY_QUEUE;
1598 create_req.queue_id = cpu_to_le16(reply_qid);
1599 create_req.flags = MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_ENABLE;
1600 create_req.msix_index = cpu_to_le16(mrioc->intr_info[midx].msix_index);
1601 if (mrioc->enable_segqueue) {
1602 create_req.flags |=
1603 MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED;
1604 create_req.base_address = cpu_to_le64(
1605 op_reply_q->q_segment_list_dma);
1606 } else
1607 create_req.base_address = cpu_to_le64(
1608 op_reply_q->q_segments[0].segment_dma);
1609
1610 create_req.size = cpu_to_le16(op_reply_q->num_replies);
1611
1612 init_completion(&mrioc->init_cmds.done);
1613 retval = mpi3mr_admin_request_post(mrioc, &create_req,
1614 sizeof(create_req), 1);
1615 if (retval) {
1616 ioc_err(mrioc, "CreateRepQ: Admin Post failed\n");
1617 goto out_unlock;
1618 }
1619 wait_for_completion_timeout(&mrioc->init_cmds.done,
1620 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
1621 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
1622 ioc_err(mrioc, "CreateRepQ: command timed out\n");
1623 mpi3mr_set_diagsave(mrioc);
1624 mpi3mr_issue_reset(mrioc,
1625 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
1626 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT);
1627 mrioc->unrecoverable = 1;
1628 retval = -1;
1629 goto out_unlock;
1630 }
1631 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
1632 != MPI3_IOCSTATUS_SUCCESS) {
1633 ioc_err(mrioc,
1634 "CreateRepQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
1635 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
1636 mrioc->init_cmds.ioc_loginfo);
1637 retval = -1;
1638 goto out_unlock;
1639 }
1640 op_reply_q->qid = reply_qid;
1641 mrioc->intr_info[midx].op_reply_q = op_reply_q;
1642
1643out_unlock:
1644 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
1645 mutex_unlock(&mrioc->init_cmds.mutex);
1646out:
1647
1648 return retval;
1649}
1650
1651/**
1652 * mpi3mr_create_op_req_q - create operational request queue
1653 * @mrioc: Adapter instance reference
1654 * @idx: operational request queue index
1655 * @reply_qid: Reply queue ID
1656 *
1657 * Create operatinal request queue by issuing MPI request
1658 * through admin queue.
1659 *
1660 * Return: 0 on success, non-zero on failure.
1661 */
1662static int mpi3mr_create_op_req_q(struct mpi3mr_ioc *mrioc, u16 idx,
1663 u16 reply_qid)
1664{
1665 struct mpi3_create_request_queue_request create_req;
1666 struct op_req_qinfo *op_req_q = mrioc->req_qinfo + idx;
1667 int retval = 0;
1668 u16 req_qid = 0;
1669
1670 req_qid = op_req_q->qid;
1671
1672 if (req_qid) {
1673 retval = -1;
1674 ioc_err(mrioc, "CreateReqQ: called for duplicate qid %d\n",
1675 req_qid);
1676
1677 return retval;
1678 }
1679 req_qid = idx + 1;
1680
1681 op_req_q->num_requests = MPI3MR_OP_REQ_Q_QD;
1682 op_req_q->ci = 0;
1683 op_req_q->pi = 0;
1684 op_req_q->reply_qid = reply_qid;
1685 spin_lock_init(&op_req_q->q_lock);
1686
1687 if (!op_req_q->q_segments) {
1688 retval = mpi3mr_alloc_op_req_q_segments(mrioc, idx);
1689 if (retval) {
1690 mpi3mr_free_op_req_q_segments(mrioc, idx);
1691 goto out;
1692 }
1693 }
1694
1695 memset(&create_req, 0, sizeof(create_req));
1696 mutex_lock(&mrioc->init_cmds.mutex);
1697 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
1698 retval = -1;
1699 ioc_err(mrioc, "CreateReqQ: Init command is in use\n");
f9dc034d 1700 goto out_unlock;
c9566231
KD		 1701 }
1702 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
1703 mrioc->init_cmds.is_waiting = 1;
1704 mrioc->init_cmds.callback = NULL;
1705 create_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
1706 create_req.function = MPI3_FUNCTION_CREATE_REQUEST_QUEUE;
1707 create_req.queue_id = cpu_to_le16(req_qid);
1708 if (mrioc->enable_segqueue) {
1709 create_req.flags =
1710 MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED;
1711 create_req.base_address = cpu_to_le64(
1712 op_req_q->q_segment_list_dma);
1713 } else
1714 create_req.base_address = cpu_to_le64(
1715 op_req_q->q_segments[0].segment_dma);
1716 create_req.reply_queue_id = cpu_to_le16(reply_qid);
1717 create_req.size = cpu_to_le16(op_req_q->num_requests);
1718
1719 init_completion(&mrioc->init_cmds.done);
1720 retval = mpi3mr_admin_request_post(mrioc, &create_req,
1721 sizeof(create_req), 1);
1722 if (retval) {
1723 ioc_err(mrioc, "CreateReqQ: Admin Post failed\n");
1724 goto out_unlock;
1725 }
1726 wait_for_completion_timeout(&mrioc->init_cmds.done,
1727 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
1728 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
1729 ioc_err(mrioc, "CreateReqQ: command timed out\n");
1730 mpi3mr_set_diagsave(mrioc);
1731 if (mpi3mr_issue_reset(mrioc,
1732 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
1733 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT))
1734 mrioc->unrecoverable = 1;
1735 retval = -1;
1736 goto out_unlock;
1737 }
1738 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
1739 != MPI3_IOCSTATUS_SUCCESS) {
1740 ioc_err(mrioc,
1741 "CreateReqQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
1742 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
1743 mrioc->init_cmds.ioc_loginfo);
1744 retval = -1;
1745 goto out_unlock;
1746 }
1747 op_req_q->qid = req_qid;
1748
1749out_unlock:
1750 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
1751 mutex_unlock(&mrioc->init_cmds.mutex);
1752out:
1753
1754 return retval;
1755}
1756
1757/**
1758 * mpi3mr_create_op_queues - create operational queue pairs
1759 * @mrioc: Adapter instance reference
1760 *
1761 * Allocate memory for operational queue meta data and call
1762 * create request and reply queue functions.
1763 *
1764 * Return: 0 on success, non-zero on failures.
1765 */
1766static int mpi3mr_create_op_queues(struct mpi3mr_ioc *mrioc)
1767{
1768 int retval = 0;
1769 u16 num_queues = 0, i = 0, msix_count_op_q = 1;
1770
1771 num_queues = min_t(int, mrioc->facts.max_op_reply_q,
1772 mrioc->facts.max_op_req_q);
1773
1774 msix_count_op_q =
1775 mrioc->intr_info_count - mrioc->op_reply_q_offset;
1776 if (!mrioc->num_queues)
1777 mrioc->num_queues = min_t(int, num_queues, msix_count_op_q);
1778 num_queues = mrioc->num_queues;
1779 ioc_info(mrioc, "Trying to create %d Operational Q pairs\n",
1780 num_queues);
1781
1782 if (!mrioc->req_qinfo) {
1783 mrioc->req_qinfo = kcalloc(num_queues,
1784 sizeof(struct op_req_qinfo), GFP_KERNEL);
1785 if (!mrioc->req_qinfo) {
1786 retval = -1;
1787 goto out_failed;
1788 }
1789
1790 mrioc->op_reply_qinfo = kzalloc(sizeof(struct op_reply_qinfo) *
1791 num_queues, GFP_KERNEL);
1792 if (!mrioc->op_reply_qinfo) {
1793 retval = -1;
1794 goto out_failed;
1795 }
1796 }
1797
1798 if (mrioc->enable_segqueue)
1799 ioc_info(mrioc,
1800 "allocating operational queues through segmented queues\n");
1801
1802 for (i = 0; i < num_queues; i++) {
1803 if (mpi3mr_create_op_reply_q(mrioc, i)) {
1804 ioc_err(mrioc, "Cannot create OP RepQ %d\n", i);
1805 break;
1806 }
1807 if (mpi3mr_create_op_req_q(mrioc, i,
1808 mrioc->op_reply_qinfo[i].qid)) {
1809 ioc_err(mrioc, "Cannot create OP ReqQ %d\n", i);
1810 mpi3mr_delete_op_reply_q(mrioc, i);
1811 break;
1812 }
1813 }
1814
1815 if (i == 0) {
1816 /* Not even one queue is created successfully*/
1817 retval = -1;
1818 goto out_failed;
1819 }
1820 mrioc->num_op_reply_q = mrioc->num_op_req_q = i;
1821 ioc_info(mrioc, "Successfully created %d Operational Q pairs\n",
1822 mrioc->num_op_reply_q);
1823
1824 return retval;
1825out_failed:
1826 kfree(mrioc->req_qinfo);
1827 mrioc->req_qinfo = NULL;
1828
1829 kfree(mrioc->op_reply_qinfo);
1830 mrioc->op_reply_qinfo = NULL;
1831
1832 return retval;
1833}
1834
023ab2a9
KD		 1835/**
1836 * mpi3mr_op_request_post - Post request to operational queue
1837 * @mrioc: Adapter reference
1838 * @op_req_q: Operational request queue info
1839 * @req: MPI3 request
1840 *
1841 * Post the MPI3 request into operational request queue and
1842 * inform the controller, if the queue is full return
1843 * appropriate error.
1844 *
1845 * Return: 0 on success, non-zero on failure.
1846 */
1847int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc,
1848 struct op_req_qinfo *op_req_q, u8 *req)
1849{
1850 u16 pi = 0, max_entries, reply_qidx = 0, midx;
1851 int retval = 0;
1852 unsigned long flags;
1853 u8 *req_entry;
1854 void *segment_base_addr;
1855 u16 req_sz = mrioc->facts.op_req_sz;
1856 struct segments *segments = op_req_q->q_segments;
1857
1858 reply_qidx = op_req_q->reply_qid - 1;
1859
1860 if (mrioc->unrecoverable)
1861 return -EFAULT;
1862
1863 spin_lock_irqsave(&op_req_q->q_lock, flags);
1864 pi = op_req_q->pi;
1865 max_entries = op_req_q->num_requests;
1866
1867 if (mpi3mr_check_req_qfull(op_req_q)) {
1868 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(
1869 reply_qidx, mrioc->op_reply_q_offset);
1870 mpi3mr_process_op_reply_q(mrioc, &mrioc->intr_info[midx]);
1871
1872 if (mpi3mr_check_req_qfull(op_req_q)) {
1873 retval = -EAGAIN;
1874 goto out;
1875 }
1876 }
1877
1878 if (mrioc->reset_in_progress) {
1879 ioc_err(mrioc, "OpReqQ submit reset in progress\n");
1880 retval = -EAGAIN;
1881 goto out;
1882 }
1883
1884 segment_base_addr = segments[pi / op_req_q->segment_qd].segment;
1885 req_entry = (u8 *)segment_base_addr +
1886 ((pi % op_req_q->segment_qd) * req_sz);
1887
1888 memset(req_entry, 0, req_sz);
1889 memcpy(req_entry, req, MPI3MR_ADMIN_REQ_FRAME_SZ);
1890
1891 if (++pi == max_entries)
1892 pi = 0;
1893 op_req_q->pi = pi;
1894
463429f8
KD		 1895 if (atomic_inc_return(&mrioc->op_reply_qinfo[reply_qidx].pend_ios)
1896 > MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT)
1897 mrioc->op_reply_qinfo[reply_qidx].enable_irq_poll = true;
1898
023ab2a9
KD		 1899 writel(op_req_q->pi,
1900 &mrioc->sysif_regs->oper_queue_indexes[reply_qidx].producer_index);
1901
1902out:
1903 spin_unlock_irqrestore(&op_req_q->q_lock, flags);
1904 return retval;
1905}
1906
54dfcffb
KD		 1907/**
1908 * mpi3mr_sync_timestamp - Issue time stamp sync request
1909 * @mrioc: Adapter reference
1910 *
1911 * Issue IO unit control MPI request to synchornize firmware
1912 * timestamp with host time.
1913 *
1914 * Return: 0 on success, non-zero on failure.
1915 */
1916static int mpi3mr_sync_timestamp(struct mpi3mr_ioc *mrioc)
1917{
1918 ktime_t current_time;
1919 struct mpi3_iounit_control_request iou_ctrl;
1920 int retval = 0;
1921
1922 memset(&iou_ctrl, 0, sizeof(iou_ctrl));
1923 mutex_lock(&mrioc->init_cmds.mutex);
1924 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
1925 retval = -1;
1926 ioc_err(mrioc, "Issue IOUCTL time_stamp: command is in use\n");
1927 mutex_unlock(&mrioc->init_cmds.mutex);
1928 goto out;
1929 }
1930 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
1931 mrioc->init_cmds.is_waiting = 1;
1932 mrioc->init_cmds.callback = NULL;
1933 iou_ctrl.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
1934 iou_ctrl.function = MPI3_FUNCTION_IO_UNIT_CONTROL;
1935 iou_ctrl.operation = MPI3_CTRL_OP_UPDATE_TIMESTAMP;
1936 current_time = ktime_get_real();
1937 iou_ctrl.param64[0] = cpu_to_le64(ktime_to_ms(current_time));
1938
1939 init_completion(&mrioc->init_cmds.done);
1940 retval = mpi3mr_admin_request_post(mrioc, &iou_ctrl,
1941 sizeof(iou_ctrl), 0);
1942 if (retval) {
1943 ioc_err(mrioc, "Issue IOUCTL time_stamp: Admin Post failed\n");
1944 goto out_unlock;
1945 }
1946
1947 wait_for_completion_timeout(&mrioc->init_cmds.done,
1948 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
1949 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
1950 ioc_err(mrioc, "Issue IOUCTL time_stamp: command timed out\n");
1951 mrioc->init_cmds.is_waiting = 0;
15d54852
SR		 1952 if (!(mrioc->init_cmds.state & MPI3MR_CMD_RESET))
1953 mpi3mr_soft_reset_handler(mrioc,
1954 MPI3MR_RESET_FROM_TSU_TIMEOUT, 1);
54dfcffb
KD		 1955 retval = -1;
1956 goto out_unlock;
1957 }
1958 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
1959 != MPI3_IOCSTATUS_SUCCESS) {
1960 ioc_err(mrioc,
1961 "Issue IOUCTL time_stamp: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
1962 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
1963 mrioc->init_cmds.ioc_loginfo);
1964 retval = -1;
1965 goto out_unlock;
1966 }
1967
1968out_unlock:
1969 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
1970 mutex_unlock(&mrioc->init_cmds.mutex);
1971
1972out:
1973 return retval;
1974}
1975
672ae26c
KD		 1976/**
1977 * mpi3mr_watchdog_work - watchdog thread to monitor faults
1978 * @work: work struct
1979 *
1980 * Watch dog work periodically executed (1 second interval) to
1981 * monitor firmware fault and to issue periodic timer sync to
1982 * the firmware.
1983 *
1984 * Return: Nothing.
1985 */
1986static void mpi3mr_watchdog_work(struct work_struct *work)
1987{
1988 struct mpi3mr_ioc *mrioc =
1989 container_of(work, struct mpi3mr_ioc, watchdog_work.work);
1990 unsigned long flags;
1991 enum mpi3mr_iocstate ioc_state;
1992 u32 fault, host_diagnostic;
1993
54dfcffb
KD		 1994 if (mrioc->ts_update_counter++ >= MPI3MR_TSUPDATE_INTERVAL) {
1995 mrioc->ts_update_counter = 0;
1996 mpi3mr_sync_timestamp(mrioc);
1997 }
1998
672ae26c
KD		 1999 /*Check for fault state every one second and issue Soft reset*/
2000 ioc_state = mpi3mr_get_iocstate(mrioc);
2001 if (ioc_state == MRIOC_STATE_FAULT) {
2002 fault = readl(&mrioc->sysif_regs->fault) &
2003 MPI3_SYSIF_FAULT_CODE_MASK;
2004 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic);
2005 if (host_diagnostic & MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS) {
2006 if (!mrioc->diagsave_timeout) {
2007 mpi3mr_print_fault_info(mrioc);
2008 ioc_warn(mrioc, "Diag save in progress\n");
2009 }
2010 if ((mrioc->diagsave_timeout++) <=
2011 MPI3_SYSIF_DIAG_SAVE_TIMEOUT)
2012 goto schedule_work;
2013 } else
2014 mpi3mr_print_fault_info(mrioc);
2015 mrioc->diagsave_timeout = 0;
2016
2017 if (fault == MPI3_SYSIF_FAULT_CODE_FACTORY_RESET) {
2018 ioc_info(mrioc,
2019 "Factory Reset fault occurred marking controller as unrecoverable"
2020 );
2021 mrioc->unrecoverable = 1;
2022 goto out;
2023 }
2024
2025 if ((fault == MPI3_SYSIF_FAULT_CODE_DIAG_FAULT_RESET) ||
2026 (fault == MPI3_SYSIF_FAULT_CODE_SOFT_RESET_IN_PROGRESS) ||
2027 (mrioc->reset_in_progress))
2028 goto out;
2029 if (fault == MPI3_SYSIF_FAULT_CODE_CI_ACTIVATION_RESET)
2030 mpi3mr_soft_reset_handler(mrioc,
2031 MPI3MR_RESET_FROM_CIACTIV_FAULT, 0);
2032 else
2033 mpi3mr_soft_reset_handler(mrioc,
2034 MPI3MR_RESET_FROM_FAULT_WATCH, 0);
2035 }
2036
2037schedule_work:
2038 spin_lock_irqsave(&mrioc->watchdog_lock, flags);
2039 if (mrioc->watchdog_work_q)
2040 queue_delayed_work(mrioc->watchdog_work_q,
2041 &mrioc->watchdog_work,
2042 msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL));
2043 spin_unlock_irqrestore(&mrioc->watchdog_lock, flags);
2044out:
2045 return;
2046}
2047
2048/**
2049 * mpi3mr_start_watchdog - Start watchdog
2050 * @mrioc: Adapter instance reference
2051 *
2052 * Create and start the watchdog thread to monitor controller
2053 * faults.
2054 *
2055 * Return: Nothing.
2056 */
2057void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc)
2058{
2059 if (mrioc->watchdog_work_q)
2060 return;
2061
2062 INIT_DELAYED_WORK(&mrioc->watchdog_work, mpi3mr_watchdog_work);
2063 snprintf(mrioc->watchdog_work_q_name,
2064 sizeof(mrioc->watchdog_work_q_name), "watchdog_%s%d", mrioc->name,
2065 mrioc->id);
2066 mrioc->watchdog_work_q =
2067 create_singlethread_workqueue(mrioc->watchdog_work_q_name);
2068 if (!mrioc->watchdog_work_q) {
2069 ioc_err(mrioc, "%s: failed (line=%d)\n", __func__, __LINE__);
2070 return;
2071 }
2072
2073 if (mrioc->watchdog_work_q)
2074 queue_delayed_work(mrioc->watchdog_work_q,
2075 &mrioc->watchdog_work,
2076 msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL));
2077}
2078
2079/**
2080 * mpi3mr_stop_watchdog - Stop watchdog
2081 * @mrioc: Adapter instance reference
2082 *
2083 * Stop the watchdog thread created to monitor controller
2084 * faults.
2085 *
2086 * Return: Nothing.
2087 */
2088void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc)
2089{
2090 unsigned long flags;
2091 struct workqueue_struct *wq;
2092
2093 spin_lock_irqsave(&mrioc->watchdog_lock, flags);
2094 wq = mrioc->watchdog_work_q;
2095 mrioc->watchdog_work_q = NULL;
2096 spin_unlock_irqrestore(&mrioc->watchdog_lock, flags);
2097 if (wq) {
2098 if (!cancel_delayed_work_sync(&mrioc->watchdog_work))
2099 flush_workqueue(wq);
2100 destroy_workqueue(wq);
2101 }
2102}
2103
fb9b0457
KD		 2104/**
2105 * mpi3mr_kill_ioc - Kill the controller
2106 * @mrioc: Adapter instance reference
2107 * @reason: reason for the failure.
2108 *
2109 * If fault debug is enabled, display the fault info else issue
2110 * diag fault and freeze the system for controller debug
2111 * purpose.
2112 *
2113 * Return: Nothing.
2114 */
2115static void mpi3mr_kill_ioc(struct mpi3mr_ioc *mrioc, u32 reason)
2116{
2117 enum mpi3mr_iocstate ioc_state;
2118
2119 if (!mrioc->fault_dbg)
2120 return;
2121
2122 dump_stack();
2123
2124 ioc_state = mpi3mr_get_iocstate(mrioc);
2125 if (ioc_state == MRIOC_STATE_FAULT)
2126 mpi3mr_print_fault_info(mrioc);
2127 else {
2128 ioc_err(mrioc, "Firmware is halted due to the reason %d\n",
2129 reason);
2130 mpi3mr_diagfault_reset_handler(mrioc, reason);
2131 }
2132 if (mrioc->fault_dbg == 2)
2133 for (;;)
2134 ;
2135 else
2136 panic("panic in %s\n", __func__);
2137}
2138
824a1566
KD		 2139/**
2140 * mpi3mr_setup_admin_qpair - Setup admin queue pair
2141 * @mrioc: Adapter instance reference
2142 *
2143 * Allocate memory for admin queue pair if required and register
2144 * the admin queue with the controller.
2145 *
2146 * Return: 0 on success, non-zero on failures.
2147 */
2148static int mpi3mr_setup_admin_qpair(struct mpi3mr_ioc *mrioc)
2149{
2150 int retval = 0;
2151 u32 num_admin_entries = 0;
2152
2153 mrioc->admin_req_q_sz = MPI3MR_ADMIN_REQ_Q_SIZE;
2154 mrioc->num_admin_req = mrioc->admin_req_q_sz /
2155 MPI3MR_ADMIN_REQ_FRAME_SZ;
2156 mrioc->admin_req_ci = mrioc->admin_req_pi = 0;
2157 mrioc->admin_req_base = NULL;
2158
2159 mrioc->admin_reply_q_sz = MPI3MR_ADMIN_REPLY_Q_SIZE;
2160 mrioc->num_admin_replies = mrioc->admin_reply_q_sz /
2161 MPI3MR_ADMIN_REPLY_FRAME_SZ;
2162 mrioc->admin_reply_ci = 0;
2163 mrioc->admin_reply_ephase = 1;
2164 mrioc->admin_reply_base = NULL;
2165
2166 if (!mrioc->admin_req_base) {
2167 mrioc->admin_req_base = dma_alloc_coherent(&mrioc->pdev->dev,
2168 mrioc->admin_req_q_sz, &mrioc->admin_req_dma, GFP_KERNEL);
2169
2170 if (!mrioc->admin_req_base) {
2171 retval = -1;
2172 goto out_failed;
2173 }
2174
2175 mrioc->admin_reply_base = dma_alloc_coherent(&mrioc->pdev->dev,
2176 mrioc->admin_reply_q_sz, &mrioc->admin_reply_dma,
2177 GFP_KERNEL);
2178
2179 if (!mrioc->admin_reply_base) {
2180 retval = -1;
2181 goto out_failed;
2182 }
2183 }
2184
2185 num_admin_entries = (mrioc->num_admin_replies << 16) |
2186 (mrioc->num_admin_req);
2187 writel(num_admin_entries, &mrioc->sysif_regs->admin_queue_num_entries);
2188 mpi3mr_writeq(mrioc->admin_req_dma,
2189 &mrioc->sysif_regs->admin_request_queue_address);
2190 mpi3mr_writeq(mrioc->admin_reply_dma,
2191 &mrioc->sysif_regs->admin_reply_queue_address);
2192 writel(mrioc->admin_req_pi, &mrioc->sysif_regs->admin_request_queue_pi);
2193 writel(mrioc->admin_reply_ci, &mrioc->sysif_regs->admin_reply_queue_ci);
2194 return retval;
2195
2196out_failed:
2197
2198 if (mrioc->admin_reply_base) {
2199 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_reply_q_sz,
2200 mrioc->admin_reply_base, mrioc->admin_reply_dma);
2201 mrioc->admin_reply_base = NULL;
2202 }
2203 if (mrioc->admin_req_base) {
2204 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_req_q_sz,
2205 mrioc->admin_req_base, mrioc->admin_req_dma);
2206 mrioc->admin_req_base = NULL;
2207 }
2208 return retval;
2209}
2210
2211/**
2212 * mpi3mr_issue_iocfacts - Send IOC Facts
2213 * @mrioc: Adapter instance reference
2214 * @facts_data: Cached IOC facts data
2215 *
2216 * Issue IOC Facts MPI request through admin queue and wait for
2217 * the completion of it or time out.
2218 *
2219 * Return: 0 on success, non-zero on failures.
2220 */
2221static int mpi3mr_issue_iocfacts(struct mpi3mr_ioc *mrioc,
2222 struct mpi3_ioc_facts_data *facts_data)
2223{
2224 struct mpi3_ioc_facts_request iocfacts_req;
2225 void *data = NULL;
2226 dma_addr_t data_dma;
2227 u32 data_len = sizeof(*facts_data);
2228 int retval = 0;
2229 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
2230
2231 data = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma,
2232 GFP_KERNEL);
2233
2234 if (!data) {
2235 retval = -1;
2236 goto out;
2237 }
2238
2239 memset(&iocfacts_req, 0, sizeof(iocfacts_req));
2240 mutex_lock(&mrioc->init_cmds.mutex);
2241 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2242 retval = -1;
2243 ioc_err(mrioc, "Issue IOCFacts: Init command is in use\n");
2244 mutex_unlock(&mrioc->init_cmds.mutex);
2245 goto out;
2246 }
2247 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2248 mrioc->init_cmds.is_waiting = 1;
2249 mrioc->init_cmds.callback = NULL;
2250 iocfacts_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2251 iocfacts_req.function = MPI3_FUNCTION_IOC_FACTS;
2252
2253 mpi3mr_add_sg_single(&iocfacts_req.sgl, sgl_flags, data_len,
2254 data_dma);
2255
2256 init_completion(&mrioc->init_cmds.done);
2257 retval = mpi3mr_admin_request_post(mrioc, &iocfacts_req,
2258 sizeof(iocfacts_req), 1);
2259 if (retval) {
2260 ioc_err(mrioc, "Issue IOCFacts: Admin Post failed\n");
2261 goto out_unlock;
2262 }
2263 wait_for_completion_timeout(&mrioc->init_cmds.done,
2264 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2265 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2266 ioc_err(mrioc, "Issue IOCFacts: command timed out\n");
2267 mpi3mr_set_diagsave(mrioc);
2268 mpi3mr_issue_reset(mrioc,
2269 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
2270 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT);
2271 mrioc->unrecoverable = 1;
2272 retval = -1;
2273 goto out_unlock;
2274 }
2275 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2276 != MPI3_IOCSTATUS_SUCCESS) {
2277 ioc_err(mrioc,
2278 "Issue IOCFacts: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
2279 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
2280 mrioc->init_cmds.ioc_loginfo);
2281 retval = -1;
2282 goto out_unlock;
2283 }
2284 memcpy(facts_data, (u8 *)data, data_len);
2285out_unlock:
2286 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2287 mutex_unlock(&mrioc->init_cmds.mutex);
2288
2289out:
2290 if (data)
2291 dma_free_coherent(&mrioc->pdev->dev, data_len, data, data_dma);
2292
2293 return retval;
2294}
2295
2296/**
2297 * mpi3mr_check_reset_dma_mask - Process IOC facts data
2298 * @mrioc: Adapter instance reference
2299 *
2300 * Check whether the new DMA mask requested through IOCFacts by
2301 * firmware needs to be set, if so set it .
2302 *
2303 * Return: 0 on success, non-zero on failure.
2304 */
2305static inline int mpi3mr_check_reset_dma_mask(struct mpi3mr_ioc *mrioc)
2306{
2307 struct pci_dev *pdev = mrioc->pdev;
2308 int r;
2309 u64 facts_dma_mask = DMA_BIT_MASK(mrioc->facts.dma_mask);
2310
2311 if (!mrioc->facts.dma_mask || (mrioc->dma_mask <= facts_dma_mask))
2312 return 0;
2313
2314 ioc_info(mrioc, "Changing DMA mask from 0x%016llx to 0x%016llx\n",
2315 mrioc->dma_mask, facts_dma_mask);
2316
2317 r = dma_set_mask_and_coherent(&pdev->dev, facts_dma_mask);
2318 if (r) {
2319 ioc_err(mrioc, "Setting DMA mask to 0x%016llx failed: %d\n",
2320 facts_dma_mask, r);
2321 return r;
2322 }
2323 mrioc->dma_mask = facts_dma_mask;
2324 return r;
2325}
2326
2327/**
2328 * mpi3mr_process_factsdata - Process IOC facts data
2329 * @mrioc: Adapter instance reference
2330 * @facts_data: Cached IOC facts data
2331 *
2332 * Convert IOC facts data into cpu endianness and cache it in
2333 * the driver .
2334 *
2335 * Return: Nothing.
2336 */
2337static void mpi3mr_process_factsdata(struct mpi3mr_ioc *mrioc,
2338 struct mpi3_ioc_facts_data *facts_data)
2339{
2340 u32 ioc_config, req_sz, facts_flags;
2341
2342 if ((le16_to_cpu(facts_data->ioc_facts_data_length)) !=
2343 (sizeof(*facts_data) / 4)) {
2344 ioc_warn(mrioc,
2345 "IOCFactsdata length mismatch driver_sz(%zu) firmware_sz(%d)\n",
2346 sizeof(*facts_data),
2347 le16_to_cpu(facts_data->ioc_facts_data_length) * 4);
2348 }
2349
2350 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
2351 req_sz = 1 << ((ioc_config & MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ) >>
2352 MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ_SHIFT);
2353 if (le16_to_cpu(facts_data->ioc_request_frame_size) != (req_sz / 4)) {
2354 ioc_err(mrioc,
2355 "IOCFacts data reqFrameSize mismatch hw_size(%d) firmware_sz(%d)\n",
2356 req_sz / 4, le16_to_cpu(facts_data->ioc_request_frame_size));
2357 }
2358
2359 memset(&mrioc->facts, 0, sizeof(mrioc->facts));
2360
2361 facts_flags = le32_to_cpu(facts_data->flags);
2362 mrioc->facts.op_req_sz = req_sz;
2363 mrioc->op_reply_desc_sz = 1 << ((ioc_config &
2364 MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ) >>
2365 MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ_SHIFT);
2366
2367 mrioc->facts.ioc_num = facts_data->ioc_number;
2368 mrioc->facts.who_init = facts_data->who_init;
2369 mrioc->facts.max_msix_vectors = le16_to_cpu(facts_data->max_msix_vectors);
2370 mrioc->facts.personality = (facts_flags &
2371 MPI3_IOCFACTS_FLAGS_PERSONALITY_MASK);
2372 mrioc->facts.dma_mask = (facts_flags &
2373 MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_MASK) >>
2374 MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_SHIFT;
2375 mrioc->facts.protocol_flags = facts_data->protocol_flags;
2376 mrioc->facts.mpi_version = le32_to_cpu(facts_data->mpi_version.word);
2377 mrioc->facts.max_reqs = le16_to_cpu(facts_data->max_outstanding_request);
2378 mrioc->facts.product_id = le16_to_cpu(facts_data->product_id);
2379 mrioc->facts.reply_sz = le16_to_cpu(facts_data->reply_frame_size) * 4;
2380 mrioc->facts.exceptions = le16_to_cpu(facts_data->ioc_exceptions);
2381 mrioc->facts.max_perids = le16_to_cpu(facts_data->max_persistent_id);
2382 mrioc->facts.max_pds = le16_to_cpu(facts_data->max_pds);
2383 mrioc->facts.max_vds = le16_to_cpu(facts_data->max_vds);
2384 mrioc->facts.max_hpds = le16_to_cpu(facts_data->max_host_pds);
2385 mrioc->facts.max_advhpds = le16_to_cpu(facts_data->max_advanced_host_pds);
2386 mrioc->facts.max_raidpds = le16_to_cpu(facts_data->max_raid_pds);
2387 mrioc->facts.max_nvme = le16_to_cpu(facts_data->max_nvme);
2388 mrioc->facts.max_pcie_switches =
2389 le16_to_cpu(facts_data->max_pc_ie_switches);
2390 mrioc->facts.max_sasexpanders =
2391 le16_to_cpu(facts_data->max_sas_expanders);
2392 mrioc->facts.max_sasinitiators =
2393 le16_to_cpu(facts_data->max_sas_initiators);
2394 mrioc->facts.max_enclosures = le16_to_cpu(facts_data->max_enclosures);
2395 mrioc->facts.min_devhandle = le16_to_cpu(facts_data->min_dev_handle);
2396 mrioc->facts.max_devhandle = le16_to_cpu(facts_data->max_dev_handle);
2397 mrioc->facts.max_op_req_q =
2398 le16_to_cpu(facts_data->max_operational_request_queues);
2399 mrioc->facts.max_op_reply_q =
2400 le16_to_cpu(facts_data->max_operational_reply_queues);
2401 mrioc->facts.ioc_capabilities =
2402 le32_to_cpu(facts_data->ioc_capabilities);
2403 mrioc->facts.fw_ver.build_num =
2404 le16_to_cpu(facts_data->fw_version.build_num);
2405 mrioc->facts.fw_ver.cust_id =
2406 le16_to_cpu(facts_data->fw_version.customer_id);
2407 mrioc->facts.fw_ver.ph_minor = facts_data->fw_version.phase_minor;
2408 mrioc->facts.fw_ver.ph_major = facts_data->fw_version.phase_major;
2409 mrioc->facts.fw_ver.gen_minor = facts_data->fw_version.gen_minor;
2410 mrioc->facts.fw_ver.gen_major = facts_data->fw_version.gen_major;
2411 mrioc->msix_count = min_t(int, mrioc->msix_count,
2412 mrioc->facts.max_msix_vectors);
2413 mrioc->facts.sge_mod_mask = facts_data->sge_modifier_mask;
2414 mrioc->facts.sge_mod_value = facts_data->sge_modifier_value;
2415 mrioc->facts.sge_mod_shift = facts_data->sge_modifier_shift;
2416 mrioc->facts.shutdown_timeout =
2417 le16_to_cpu(facts_data->shutdown_timeout);
2418
2419 ioc_info(mrioc, "ioc_num(%d), maxopQ(%d), maxopRepQ(%d), maxdh(%d),",
2420 mrioc->facts.ioc_num, mrioc->facts.max_op_req_q,
2421 mrioc->facts.max_op_reply_q, mrioc->facts.max_devhandle);
2422 ioc_info(mrioc,
2423 "maxreqs(%d), mindh(%d) maxPDs(%d) maxvectors(%d) maxperids(%d)\n",
2424 mrioc->facts.max_reqs, mrioc->facts.min_devhandle,
2425 mrioc->facts.max_pds, mrioc->facts.max_msix_vectors,
2426 mrioc->facts.max_perids);
2427 ioc_info(mrioc, "SGEModMask 0x%x SGEModVal 0x%x SGEModShift 0x%x ",
2428 mrioc->facts.sge_mod_mask, mrioc->facts.sge_mod_value,
2429 mrioc->facts.sge_mod_shift);
2430 ioc_info(mrioc, "DMA mask %d InitialPE status 0x%x\n",
2431 mrioc->facts.dma_mask, (facts_flags &
2432 MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_MASK));
2433
2434 mrioc->max_host_ios = mrioc->facts.max_reqs - MPI3MR_INTERNAL_CMDS_RESVD;
2435
2436 if (reset_devices)
2437 mrioc->max_host_ios = min_t(int, mrioc->max_host_ios,
2438 MPI3MR_HOST_IOS_KDUMP);
2439}
2440
2441/**
2442 * mpi3mr_alloc_reply_sense_bufs - Send IOC Init
2443 * @mrioc: Adapter instance reference
2444 *
2445 * Allocate and initialize the reply free buffers, sense
2446 * buffers, reply free queue and sense buffer queue.
2447 *
2448 * Return: 0 on success, non-zero on failures.
2449 */
2450static int mpi3mr_alloc_reply_sense_bufs(struct mpi3mr_ioc *mrioc)
2451{
2452 int retval = 0;
2453 u32 sz, i;
2454 dma_addr_t phy_addr;
2455
2456 if (mrioc->init_cmds.reply)
2457 goto post_reply_sbuf;
2458
2459 mrioc->init_cmds.reply = kzalloc(mrioc->facts.reply_sz, GFP_KERNEL);
2460 if (!mrioc->init_cmds.reply)
2461 goto out_failed;
2462
13ef29ea
KD		 2463 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) {
2464 mrioc->dev_rmhs_cmds[i].reply = kzalloc(mrioc->facts.reply_sz,
2465 GFP_KERNEL);
2466 if (!mrioc->dev_rmhs_cmds[i].reply)
2467 goto out_failed;
2468 }
2469
e844adb1
KD		 2470 mrioc->host_tm_cmds.reply = kzalloc(mrioc->facts.reply_sz, GFP_KERNEL);
2471 if (!mrioc->host_tm_cmds.reply)
2472 goto out_failed;
2473
2474 mrioc->dev_handle_bitmap_sz = mrioc->facts.max_devhandle / 8;
2475 if (mrioc->facts.max_devhandle % 8)
2476 mrioc->dev_handle_bitmap_sz++;
2477 mrioc->removepend_bitmap = kzalloc(mrioc->dev_handle_bitmap_sz,
2478 GFP_KERNEL);
2479 if (!mrioc->removepend_bitmap)
2480 goto out_failed;
2481
2482 mrioc->devrem_bitmap_sz = MPI3MR_NUM_DEVRMCMD / 8;
2483 if (MPI3MR_NUM_DEVRMCMD % 8)
2484 mrioc->devrem_bitmap_sz++;
2485 mrioc->devrem_bitmap = kzalloc(mrioc->devrem_bitmap_sz,
2486 GFP_KERNEL);
2487 if (!mrioc->devrem_bitmap)
2488 goto out_failed;
2489
824a1566
KD		 2490 mrioc->num_reply_bufs = mrioc->facts.max_reqs + MPI3MR_NUM_EVT_REPLIES;
2491 mrioc->reply_free_qsz = mrioc->num_reply_bufs + 1;
2492 mrioc->num_sense_bufs = mrioc->facts.max_reqs / MPI3MR_SENSEBUF_FACTOR;
2493 mrioc->sense_buf_q_sz = mrioc->num_sense_bufs + 1;
2494
2495 /* reply buffer pool, 16 byte align */
2496 sz = mrioc->num_reply_bufs * mrioc->facts.reply_sz;
2497 mrioc->reply_buf_pool = dma_pool_create("reply_buf pool",
2498 &mrioc->pdev->dev, sz, 16, 0);
2499 if (!mrioc->reply_buf_pool) {
2500 ioc_err(mrioc, "reply buf pool: dma_pool_create failed\n");
2501 goto out_failed;
2502 }
2503
2504 mrioc->reply_buf = dma_pool_zalloc(mrioc->reply_buf_pool, GFP_KERNEL,
2505 &mrioc->reply_buf_dma);
2506 if (!mrioc->reply_buf)
2507 goto out_failed;
2508
2509 mrioc->reply_buf_dma_max_address = mrioc->reply_buf_dma + sz;
2510
2511 /* reply free queue, 8 byte align */
2512 sz = mrioc->reply_free_qsz * 8;
2513 mrioc->reply_free_q_pool = dma_pool_create("reply_free_q pool",
2514 &mrioc->pdev->dev, sz, 8, 0);
2515 if (!mrioc->reply_free_q_pool) {
2516 ioc_err(mrioc, "reply_free_q pool: dma_pool_create failed\n");
2517 goto out_failed;
2518 }
2519 mrioc->reply_free_q = dma_pool_zalloc(mrioc->reply_free_q_pool,
2520 GFP_KERNEL, &mrioc->reply_free_q_dma);
2521 if (!mrioc->reply_free_q)
2522 goto out_failed;
2523
2524 /* sense buffer pool, 4 byte align */
2525 sz = mrioc->num_sense_bufs * MPI3MR_SENSEBUF_SZ;
2526 mrioc->sense_buf_pool = dma_pool_create("sense_buf pool",
2527 &mrioc->pdev->dev, sz, 4, 0);
2528 if (!mrioc->sense_buf_pool) {
2529 ioc_err(mrioc, "sense_buf pool: dma_pool_create failed\n");
2530 goto out_failed;
2531 }
2532 mrioc->sense_buf = dma_pool_zalloc(mrioc->sense_buf_pool, GFP_KERNEL,
2533 &mrioc->sense_buf_dma);
2534 if (!mrioc->sense_buf)
2535 goto out_failed;
2536
2537 /* sense buffer queue, 8 byte align */
2538 sz = mrioc->sense_buf_q_sz * 8;
2539 mrioc->sense_buf_q_pool = dma_pool_create("sense_buf_q pool",
2540 &mrioc->pdev->dev, sz, 8, 0);
2541 if (!mrioc->sense_buf_q_pool) {
2542 ioc_err(mrioc, "sense_buf_q pool: dma_pool_create failed\n");
2543 goto out_failed;
2544 }
2545 mrioc->sense_buf_q = dma_pool_zalloc(mrioc->sense_buf_q_pool,
2546 GFP_KERNEL, &mrioc->sense_buf_q_dma);
2547 if (!mrioc->sense_buf_q)
2548 goto out_failed;
2549
2550post_reply_sbuf:
2551 sz = mrioc->num_reply_bufs * mrioc->facts.reply_sz;
2552 ioc_info(mrioc,
2553 "reply buf pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), reply_dma(0x%llx)\n",
2554 mrioc->reply_buf, mrioc->num_reply_bufs, mrioc->facts.reply_sz,
2555 (sz / 1024), (unsigned long long)mrioc->reply_buf_dma);
2556 sz = mrioc->reply_free_qsz * 8;
2557 ioc_info(mrioc,
2558 "reply_free_q pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), reply_dma(0x%llx)\n",
2559 mrioc->reply_free_q, mrioc->reply_free_qsz, 8, (sz / 1024),
2560 (unsigned long long)mrioc->reply_free_q_dma);
2561 sz = mrioc->num_sense_bufs * MPI3MR_SENSEBUF_SZ;
2562 ioc_info(mrioc,
2563 "sense_buf pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), sense_dma(0x%llx)\n",
2564 mrioc->sense_buf, mrioc->num_sense_bufs, MPI3MR_SENSEBUF_SZ,
2565 (sz / 1024), (unsigned long long)mrioc->sense_buf_dma);
2566 sz = mrioc->sense_buf_q_sz * 8;
2567 ioc_info(mrioc,
2568 "sense_buf_q pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), sense_dma(0x%llx)\n",
2569 mrioc->sense_buf_q, mrioc->sense_buf_q_sz, 8, (sz / 1024),
2570 (unsigned long long)mrioc->sense_buf_q_dma);
2571
2572 /* initialize Reply buffer Queue */
2573 for (i = 0, phy_addr = mrioc->reply_buf_dma;
2574 i < mrioc->num_reply_bufs; i++, phy_addr += mrioc->facts.reply_sz)
2575 mrioc->reply_free_q[i] = cpu_to_le64(phy_addr);
2576 mrioc->reply_free_q[i] = cpu_to_le64(0);
2577
2578 /* initialize Sense Buffer Queue */
2579 for (i = 0, phy_addr = mrioc->sense_buf_dma;
2580 i < mrioc->num_sense_bufs; i++, phy_addr += MPI3MR_SENSEBUF_SZ)
2581 mrioc->sense_buf_q[i] = cpu_to_le64(phy_addr);
2582 mrioc->sense_buf_q[i] = cpu_to_le64(0);
2583 return retval;
2584
2585out_failed:
2586 retval = -1;
2587 return retval;
2588}
2589
2590/**
2591 * mpi3mr_issue_iocinit - Send IOC Init
2592 * @mrioc: Adapter instance reference
2593 *
2594 * Issue IOC Init MPI request through admin queue and wait for
2595 * the completion of it or time out.
2596 *
2597 * Return: 0 on success, non-zero on failures.
2598 */
2599static int mpi3mr_issue_iocinit(struct mpi3mr_ioc *mrioc)
2600{
2601 struct mpi3_ioc_init_request iocinit_req;
2602 struct mpi3_driver_info_layout *drv_info;
2603 dma_addr_t data_dma;
2604 u32 data_len = sizeof(*drv_info);
2605 int retval = 0;
2606 ktime_t current_time;
2607
2608 drv_info = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma,
2609 GFP_KERNEL);
2610 if (!drv_info) {
2611 retval = -1;
2612 goto out;
2613 }
2614 drv_info->information_length = cpu_to_le32(data_len);
aa0dc6a7
SR		 2615 strscpy(drv_info->driver_signature, "Broadcom", sizeof(drv_info->driver_signature));
2616 strscpy(drv_info->os_name, utsname()->sysname, sizeof(drv_info->os_name));
2617 strscpy(drv_info->os_version, utsname()->release, sizeof(drv_info->os_version));
2618 strscpy(drv_info->driver_name, MPI3MR_DRIVER_NAME, sizeof(drv_info->driver_name));
2619 strscpy(drv_info->driver_version, MPI3MR_DRIVER_VERSION, sizeof(drv_info->driver_version));
2620 strscpy(drv_info->driver_release_date, MPI3MR_DRIVER_RELDATE,
2621 sizeof(drv_info->driver_release_date));
824a1566
KD		 2622 drv_info->driver_capabilities = 0;
2623 memcpy((u8 *)&mrioc->driver_info, (u8 *)drv_info,
2624 sizeof(mrioc->driver_info));
2625
2626 memset(&iocinit_req, 0, sizeof(iocinit_req));
2627 mutex_lock(&mrioc->init_cmds.mutex);
2628 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2629 retval = -1;
2630 ioc_err(mrioc, "Issue IOCInit: Init command is in use\n");
2631 mutex_unlock(&mrioc->init_cmds.mutex);
2632 goto out;
2633 }
2634 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2635 mrioc->init_cmds.is_waiting = 1;
2636 mrioc->init_cmds.callback = NULL;
2637 iocinit_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2638 iocinit_req.function = MPI3_FUNCTION_IOC_INIT;
2639 iocinit_req.mpi_version.mpi3_version.dev = MPI3_VERSION_DEV;
2640 iocinit_req.mpi_version.mpi3_version.unit = MPI3_VERSION_UNIT;
2641 iocinit_req.mpi_version.mpi3_version.major = MPI3_VERSION_MAJOR;
2642 iocinit_req.mpi_version.mpi3_version.minor = MPI3_VERSION_MINOR;
2643 iocinit_req.who_init = MPI3_WHOINIT_HOST_DRIVER;
2644 iocinit_req.reply_free_queue_depth = cpu_to_le16(mrioc->reply_free_qsz);
2645 iocinit_req.reply_free_queue_address =
2646 cpu_to_le64(mrioc->reply_free_q_dma);
2647 iocinit_req.sense_buffer_length = cpu_to_le16(MPI3MR_SENSEBUF_SZ);
2648 iocinit_req.sense_buffer_free_queue_depth =
2649 cpu_to_le16(mrioc->sense_buf_q_sz);
2650 iocinit_req.sense_buffer_free_queue_address =
2651 cpu_to_le64(mrioc->sense_buf_q_dma);
2652 iocinit_req.driver_information_address = cpu_to_le64(data_dma);
2653
2654 current_time = ktime_get_real();
2655 iocinit_req.time_stamp = cpu_to_le64(ktime_to_ms(current_time));
2656
2657 init_completion(&mrioc->init_cmds.done);
2658 retval = mpi3mr_admin_request_post(mrioc, &iocinit_req,
2659 sizeof(iocinit_req), 1);
2660 if (retval) {
2661 ioc_err(mrioc, "Issue IOCInit: Admin Post failed\n");
2662 goto out_unlock;
2663 }
2664 wait_for_completion_timeout(&mrioc->init_cmds.done,
2665 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2666 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2667 mpi3mr_set_diagsave(mrioc);
2668 mpi3mr_issue_reset(mrioc,
2669 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
2670 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT);
2671 mrioc->unrecoverable = 1;
2672 ioc_err(mrioc, "Issue IOCInit: command timed out\n");
2673 retval = -1;
2674 goto out_unlock;
2675 }
2676 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2677 != MPI3_IOCSTATUS_SUCCESS) {
2678 ioc_err(mrioc,
2679 "Issue IOCInit: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
2680 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
2681 mrioc->init_cmds.ioc_loginfo);
2682 retval = -1;
2683 goto out_unlock;
2684 }
2685
2686out_unlock:
2687 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2688 mutex_unlock(&mrioc->init_cmds.mutex);
2689
2690out:
2691 if (drv_info)
2692 dma_free_coherent(&mrioc->pdev->dev, data_len, drv_info,
2693 data_dma);
2694
2695 return retval;
2696}
2697
13ef29ea
KD		 2698/**
2699 * mpi3mr_unmask_events - Unmask events in event mask bitmap
2700 * @mrioc: Adapter instance reference
2701 * @event: MPI event ID
2702 *
2703 * Un mask the specific event by resetting the event_mask
2704 * bitmap.
2705 *
2706 * Return: 0 on success, non-zero on failures.
2707 */
2708static void mpi3mr_unmask_events(struct mpi3mr_ioc *mrioc, u16 event)
2709{
2710 u32 desired_event;
2711 u8 word;
2712
2713 if (event >= 128)
2714 return;
2715
2716 desired_event = (1 << (event % 32));
2717 word = event / 32;
2718
2719 mrioc->event_masks[word] &= ~desired_event;
2720}
2721
2722/**
2723 * mpi3mr_issue_event_notification - Send event notification
2724 * @mrioc: Adapter instance reference
2725 *
2726 * Issue event notification MPI request through admin queue and
2727 * wait for the completion of it or time out.
2728 *
2729 * Return: 0 on success, non-zero on failures.
2730 */
2731static int mpi3mr_issue_event_notification(struct mpi3mr_ioc *mrioc)
2732{
2733 struct mpi3_event_notification_request evtnotify_req;
2734 int retval = 0;
2735 u8 i;
2736
2737 memset(&evtnotify_req, 0, sizeof(evtnotify_req));
2738 mutex_lock(&mrioc->init_cmds.mutex);
2739 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2740 retval = -1;
2741 ioc_err(mrioc, "Issue EvtNotify: Init command is in use\n");
2742 mutex_unlock(&mrioc->init_cmds.mutex);
2743 goto out;
2744 }
2745 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2746 mrioc->init_cmds.is_waiting = 1;
2747 mrioc->init_cmds.callback = NULL;
2748 evtnotify_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2749 evtnotify_req.function = MPI3_FUNCTION_EVENT_NOTIFICATION;
2750 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
2751 evtnotify_req.event_masks[i] =
2752 cpu_to_le32(mrioc->event_masks[i]);
2753 init_completion(&mrioc->init_cmds.done);
2754 retval = mpi3mr_admin_request_post(mrioc, &evtnotify_req,
2755 sizeof(evtnotify_req), 1);
2756 if (retval) {
2757 ioc_err(mrioc, "Issue EvtNotify: Admin Post failed\n");
2758 goto out_unlock;
2759 }
2760 wait_for_completion_timeout(&mrioc->init_cmds.done,
2761 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2762 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2763 ioc_err(mrioc, "Issue EvtNotify: command timed out\n");
2764 mpi3mr_set_diagsave(mrioc);
2765 mpi3mr_issue_reset(mrioc,
2766 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
2767 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT);
2768 mrioc->unrecoverable = 1;
2769 retval = -1;
2770 goto out_unlock;
2771 }
2772 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2773 != MPI3_IOCSTATUS_SUCCESS) {
2774 ioc_err(mrioc,
2775 "Issue EvtNotify: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
2776 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
2777 mrioc->init_cmds.ioc_loginfo);
2778 retval = -1;
2779 goto out_unlock;
2780 }
2781
2782out_unlock:
2783 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2784 mutex_unlock(&mrioc->init_cmds.mutex);
2785out:
2786 return retval;
2787}
2788
2789/**
2790 * mpi3mr_send_event_ack - Send event acknowledgment
2791 * @mrioc: Adapter instance reference
2792 * @event: MPI3 event ID
2793 * @event_ctx: Event context
2794 *
2795 * Send event acknowledgment through admin queue and wait for
2796 * it to complete.
2797 *
2798 * Return: 0 on success, non-zero on failures.
2799 */
2800int mpi3mr_send_event_ack(struct mpi3mr_ioc *mrioc, u8 event,
2801 u32 event_ctx)
2802{
2803 struct mpi3_event_ack_request evtack_req;
2804 int retval = 0;
2805
2806 memset(&evtack_req, 0, sizeof(evtack_req));
2807 mutex_lock(&mrioc->init_cmds.mutex);
2808 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2809 retval = -1;
2810 ioc_err(mrioc, "Send EvtAck: Init command is in use\n");
2811 mutex_unlock(&mrioc->init_cmds.mutex);
2812 goto out;
2813 }
2814 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2815 mrioc->init_cmds.is_waiting = 1;
2816 mrioc->init_cmds.callback = NULL;
2817 evtack_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2818 evtack_req.function = MPI3_FUNCTION_EVENT_ACK;
2819 evtack_req.event = event;
2820 evtack_req.event_context = cpu_to_le32(event_ctx);
2821
2822 init_completion(&mrioc->init_cmds.done);
2823 retval = mpi3mr_admin_request_post(mrioc, &evtack_req,
2824 sizeof(evtack_req), 1);
2825 if (retval) {
2826 ioc_err(mrioc, "Send EvtAck: Admin Post failed\n");
2827 goto out_unlock;
2828 }
2829 wait_for_completion_timeout(&mrioc->init_cmds.done,
2830 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2831 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2832 ioc_err(mrioc, "Issue EvtNotify: command timed out\n");
15d54852
SR		 2833 if (!(mrioc->init_cmds.state & MPI3MR_CMD_RESET))
2834 mpi3mr_soft_reset_handler(mrioc,
2835 MPI3MR_RESET_FROM_EVTACK_TIMEOUT, 1);
13ef29ea
KD		 2836 retval = -1;
2837 goto out_unlock;
2838 }
2839 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2840 != MPI3_IOCSTATUS_SUCCESS) {
2841 ioc_err(mrioc,
2842 "Send EvtAck: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
2843 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
2844 mrioc->init_cmds.ioc_loginfo);
2845 retval = -1;
2846 goto out_unlock;
2847 }
2848
2849out_unlock:
2850 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2851 mutex_unlock(&mrioc->init_cmds.mutex);
2852out:
2853 return retval;
2854}
2855
824a1566
KD		 2856/**
2857 * mpi3mr_alloc_chain_bufs - Allocate chain buffers
2858 * @mrioc: Adapter instance reference
2859 *
2860 * Allocate chain buffers and set a bitmap to indicate free
2861 * chain buffers. Chain buffers are used to pass the SGE
2862 * information along with MPI3 SCSI IO requests for host I/O.
2863 *
2864 * Return: 0 on success, non-zero on failure
2865 */
2866static int mpi3mr_alloc_chain_bufs(struct mpi3mr_ioc *mrioc)
2867{
2868 int retval = 0;
2869 u32 sz, i;
2870 u16 num_chains;
2871
2872 num_chains = mrioc->max_host_ios / MPI3MR_CHAINBUF_FACTOR;
2873
74e1f30a
KD		 2874 if (prot_mask & (SHOST_DIX_TYPE0_PROTECTION
2875 | SHOST_DIX_TYPE1_PROTECTION
2876 | SHOST_DIX_TYPE2_PROTECTION
2877 | SHOST_DIX_TYPE3_PROTECTION))
2878 num_chains += (num_chains / MPI3MR_CHAINBUFDIX_FACTOR);
2879
824a1566
KD		 2880 mrioc->chain_buf_count = num_chains;
2881 sz = sizeof(struct chain_element) * num_chains;
2882 mrioc->chain_sgl_list = kzalloc(sz, GFP_KERNEL);
2883 if (!mrioc->chain_sgl_list)
2884 goto out_failed;
2885
2886 sz = MPI3MR_PAGE_SIZE_4K;
2887 mrioc->chain_buf_pool = dma_pool_create("chain_buf pool",
2888 &mrioc->pdev->dev, sz, 16, 0);
2889 if (!mrioc->chain_buf_pool) {
2890 ioc_err(mrioc, "chain buf pool: dma_pool_create failed\n");
2891 goto out_failed;
2892 }
2893
2894 for (i = 0; i < num_chains; i++) {
2895 mrioc->chain_sgl_list[i].addr =
2896 dma_pool_zalloc(mrioc->chain_buf_pool, GFP_KERNEL,
2897 &mrioc->chain_sgl_list[i].dma_addr);
2898
2899 if (!mrioc->chain_sgl_list[i].addr)
2900 goto out_failed;
2901 }
2902 mrioc->chain_bitmap_sz = num_chains / 8;
2903 if (num_chains % 8)
2904 mrioc->chain_bitmap_sz++;
2905 mrioc->chain_bitmap = kzalloc(mrioc->chain_bitmap_sz, GFP_KERNEL);
2906 if (!mrioc->chain_bitmap)
2907 goto out_failed;
2908 return retval;
2909out_failed:
2910 retval = -1;
2911 return retval;
2912}
2913
023ab2a9
KD		 2914/**
2915 * mpi3mr_port_enable_complete - Mark port enable complete
2916 * @mrioc: Adapter instance reference
2917 * @drv_cmd: Internal command tracker
2918 *
2919 * Call back for asynchronous port enable request sets the
2920 * driver command to indicate port enable request is complete.
2921 *
2922 * Return: Nothing
2923 */
2924static void mpi3mr_port_enable_complete(struct mpi3mr_ioc *mrioc,
2925 struct mpi3mr_drv_cmd *drv_cmd)
2926{
2927 drv_cmd->state = MPI3MR_CMD_NOTUSED;
2928 drv_cmd->callback = NULL;
2929 mrioc->scan_failed = drv_cmd->ioc_status;
2930 mrioc->scan_started = 0;
2931}
2932
2933/**
2934 * mpi3mr_issue_port_enable - Issue Port Enable
2935 * @mrioc: Adapter instance reference
2936 * @async: Flag to wait for completion or not
2937 *
2938 * Issue Port Enable MPI request through admin queue and if the
2939 * async flag is not set wait for the completion of the port
2940 * enable or time out.
2941 *
2942 * Return: 0 on success, non-zero on failures.
2943 */
2944int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async)
2945{
2946 struct mpi3_port_enable_request pe_req;
2947 int retval = 0;
2948 u32 pe_timeout = MPI3MR_PORTENABLE_TIMEOUT;
2949
2950 memset(&pe_req, 0, sizeof(pe_req));
2951 mutex_lock(&mrioc->init_cmds.mutex);
2952 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2953 retval = -1;
2954 ioc_err(mrioc, "Issue PortEnable: Init command is in use\n");
2955 mutex_unlock(&mrioc->init_cmds.mutex);
2956 goto out;
2957 }
2958 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2959 if (async) {
2960 mrioc->init_cmds.is_waiting = 0;
2961 mrioc->init_cmds.callback = mpi3mr_port_enable_complete;
2962 } else {
2963 mrioc->init_cmds.is_waiting = 1;
2964 mrioc->init_cmds.callback = NULL;
2965 init_completion(&mrioc->init_cmds.done);
2966 }
2967 pe_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2968 pe_req.function = MPI3_FUNCTION_PORT_ENABLE;
2969
2970 retval = mpi3mr_admin_request_post(mrioc, &pe_req, sizeof(pe_req), 1);
2971 if (retval) {
2972 ioc_err(mrioc, "Issue PortEnable: Admin Post failed\n");
2973 goto out_unlock;
2974 }
2975 if (!async) {
2976 wait_for_completion_timeout(&mrioc->init_cmds.done,
2977 (pe_timeout * HZ));
2978 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2979 ioc_err(mrioc, "Issue PortEnable: command timed out\n");
2980 retval = -1;
2981 mrioc->scan_failed = MPI3_IOCSTATUS_INTERNAL_ERROR;
2982 mpi3mr_set_diagsave(mrioc);
2983 mpi3mr_issue_reset(mrioc,
2984 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
2985 MPI3MR_RESET_FROM_PE_TIMEOUT);
2986 mrioc->unrecoverable = 1;
2987 goto out_unlock;
2988 }
2989 mpi3mr_port_enable_complete(mrioc, &mrioc->init_cmds);
2990 }
2991out_unlock:
2992 mutex_unlock(&mrioc->init_cmds.mutex);
2993out:
2994 return retval;
2995}
2996
ff9561e9
KD		 2997/* Protocol type to name mapper structure*/
2998static const struct {
2999 u8 protocol;
3000 char *name;
3001} mpi3mr_protocols[] = {
3002 { MPI3_IOCFACTS_PROTOCOL_SCSI_INITIATOR, "Initiator" },
3003 { MPI3_IOCFACTS_PROTOCOL_SCSI_TARGET, "Target" },
3004 { MPI3_IOCFACTS_PROTOCOL_NVME, "NVMe attachment" },
3005};
3006
3007/* Capability to name mapper structure*/
3008static const struct {
3009 u32 capability;
3010 char *name;
3011} mpi3mr_capabilities[] = {
3012 { MPI3_IOCFACTS_CAPABILITY_RAID_CAPABLE, "RAID" },
3013};
3014
3015/**
3016 * mpi3mr_print_ioc_info - Display controller information
3017 * @mrioc: Adapter instance reference
3018 *
3019 * Display controller personalit, capability, supported
3020 * protocols etc.
3021 *
3022 * Return: Nothing
3023 */
3024static void
3025mpi3mr_print_ioc_info(struct mpi3mr_ioc *mrioc)
3026{
09f505ed 3027 int i = 0, bytes_written = 0;
ff9561e9
KD		 3028 char personality[16];
3029 char protocol[50] = {0};
3030 char capabilities[100] = {0};
ff9561e9
KD		 3031 struct mpi3mr_compimg_ver *fwver = &mrioc->facts.fw_ver;
3032
3033 switch (mrioc->facts.personality) {
3034 case MPI3_IOCFACTS_FLAGS_PERSONALITY_EHBA:
3035 strncpy(personality, "Enhanced HBA", sizeof(personality));
3036 break;
3037 case MPI3_IOCFACTS_FLAGS_PERSONALITY_RAID_DDR:
3038 strncpy(personality, "RAID", sizeof(personality));
3039 break;
3040 default:
3041 strncpy(personality, "Unknown", sizeof(personality));
3042 break;
3043 }
3044
3045 ioc_info(mrioc, "Running in %s Personality", personality);
3046
3047 ioc_info(mrioc, "FW version(%d.%d.%d.%d.%d.%d)\n",
3048 fwver->gen_major, fwver->gen_minor, fwver->ph_major,
3049 fwver->ph_minor, fwver->cust_id, fwver->build_num);
3050
3051 for (i = 0; i < ARRAY_SIZE(mpi3mr_protocols); i++) {
3052 if (mrioc->facts.protocol_flags &
3053 mpi3mr_protocols[i].protocol) {
102a085c 3054 bytes_written += scnprintf(protocol + bytes_written,
09f505ed
DC		 3055 sizeof(protocol) - bytes_written, "%s%s",
3056 bytes_written ? "," : "",
ff9561e9 3057 mpi3mr_protocols[i].name);
ff9561e9
KD		 3058 }
3059 }
3060
09f505ed 3061 bytes_written = 0;
ff9561e9
KD		 3062 for (i = 0; i < ARRAY_SIZE(mpi3mr_capabilities); i++) {
3063 if (mrioc->facts.protocol_flags &
3064 mpi3mr_capabilities[i].capability) {
102a085c 3065 bytes_written += scnprintf(capabilities + bytes_written,
09f505ed
DC		 3066 sizeof(capabilities) - bytes_written, "%s%s",
3067 bytes_written ? "," : "",
ff9561e9 3068 mpi3mr_capabilities[i].name);
ff9561e9
KD		 3069 }
3070 }
3071
3072 ioc_info(mrioc, "Protocol=(%s), Capabilities=(%s)\n",
09f505ed 3073 protocol, capabilities);
ff9561e9
KD		 3074}
3075
824a1566
KD		 3076/**
3077 * mpi3mr_cleanup_resources - Free PCI resources
3078 * @mrioc: Adapter instance reference
3079 *
3080 * Unmap PCI device memory and disable PCI device.
3081 *
3082 * Return: 0 on success and non-zero on failure.
3083 */
3084void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc)
3085{
3086 struct pci_dev *pdev = mrioc->pdev;
3087
3088 mpi3mr_cleanup_isr(mrioc);
3089
3090 if (mrioc->sysif_regs) {
3091 iounmap((void __iomem *)mrioc->sysif_regs);
3092 mrioc->sysif_regs = NULL;
3093 }
3094
3095 if (pci_is_enabled(pdev)) {
3096 if (mrioc->bars)
3097 pci_release_selected_regions(pdev, mrioc->bars);
3098 pci_disable_device(pdev);
3099 }
3100}
3101
3102/**
3103 * mpi3mr_setup_resources - Enable PCI resources
3104 * @mrioc: Adapter instance reference
3105 *
3106 * Enable PCI device memory, MSI-x registers and set DMA mask.
3107 *
3108 * Return: 0 on success and non-zero on failure.
3109 */
3110int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc)
3111{
3112 struct pci_dev *pdev = mrioc->pdev;
3113 u32 memap_sz = 0;
3114 int i, retval = 0, capb = 0;
3115 u16 message_control;
3116 u64 dma_mask = mrioc->dma_mask ? mrioc->dma_mask :
3117 (((dma_get_required_mask(&pdev->dev) > DMA_BIT_MASK(32)) &&
3118 (sizeof(dma_addr_t) > 4)) ? DMA_BIT_MASK(64) : DMA_BIT_MASK(32));
3119
3120 if (pci_enable_device_mem(pdev)) {
3121 ioc_err(mrioc, "pci_enable_device_mem: failed\n");
3122 retval = -ENODEV;
3123 goto out_failed;
3124 }
3125
3126 capb = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
3127 if (!capb) {
3128 ioc_err(mrioc, "Unable to find MSI-X Capabilities\n");
3129 retval = -ENODEV;
3130 goto out_failed;
3131 }
3132 mrioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
3133
3134 if (pci_request_selected_regions(pdev, mrioc->bars,
3135 mrioc->driver_name)) {
3136 ioc_err(mrioc, "pci_request_selected_regions: failed\n");
3137 retval = -ENODEV;
3138 goto out_failed;
3139 }
3140
3141 for (i = 0; (i < DEVICE_COUNT_RESOURCE); i++) {
3142 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3143 mrioc->sysif_regs_phys = pci_resource_start(pdev, i);
3144 memap_sz = pci_resource_len(pdev, i);
3145 mrioc->sysif_regs =
3146 ioremap(mrioc->sysif_regs_phys, memap_sz);
3147 break;
3148 }
3149 }
3150
3151 pci_set_master(pdev);
3152
3153 retval = dma_set_mask_and_coherent(&pdev->dev, dma_mask);
3154 if (retval) {
3155 if (dma_mask != DMA_BIT_MASK(32)) {
3156 ioc_warn(mrioc, "Setting 64 bit DMA mask failed\n");
3157 dma_mask = DMA_BIT_MASK(32);
3158 retval = dma_set_mask_and_coherent(&pdev->dev,
3159 dma_mask);
3160 }
3161 if (retval) {
3162 mrioc->dma_mask = 0;
3163 ioc_err(mrioc, "Setting 32 bit DMA mask also failed\n");
3164 goto out_failed;
3165 }
3166 }
3167 mrioc->dma_mask = dma_mask;
3168
3169 if (!mrioc->sysif_regs) {
3170 ioc_err(mrioc,
3171 "Unable to map adapter memory or resource not found\n");
3172 retval = -EINVAL;
3173 goto out_failed;
3174 }
3175
3176 pci_read_config_word(pdev, capb + 2, &message_control);
3177 mrioc->msix_count = (message_control & 0x3FF) + 1;
3178
3179 pci_save_state(pdev);
3180
3181 pci_set_drvdata(pdev, mrioc->shost);
3182
3183 mpi3mr_ioc_disable_intr(mrioc);
3184
3185 ioc_info(mrioc, "iomem(0x%016llx), mapped(0x%p), size(%d)\n",
3186 (unsigned long long)mrioc->sysif_regs_phys,
3187 mrioc->sysif_regs, memap_sz);
3188 ioc_info(mrioc, "Number of MSI-X vectors found in capabilities: (%d)\n",
3189 mrioc->msix_count);
3190 return retval;
3191
3192out_failed:
3193 mpi3mr_cleanup_resources(mrioc);
3194 return retval;
3195}
3196
3197/**
3198 * mpi3mr_init_ioc - Initialize the controller
3199 * @mrioc: Adapter instance reference
0da66348 3200 * @init_type: Flag to indicate is the init_type
824a1566
KD		 3201 *
3202 * This the controller initialization routine, executed either
3203 * after soft reset or from pci probe callback.
3204 * Setup the required resources, memory map the controller
3205 * registers, create admin and operational reply queue pairs,
3206 * allocate required memory for reply pool, sense buffer pool,
3207 * issue IOC init request to the firmware, unmask the events and
3208 * issue port enable to discover SAS/SATA/NVMe devies and RAID
3209 * volumes.
3210 *
3211 * Return: 0 on success and non-zero on failure.
3212 */
0da66348 3213int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc, u8 init_type)
824a1566
KD		 3214{
3215 int retval = 0;
3216 enum mpi3mr_iocstate ioc_state;
3217 u64 base_info;
3218 u32 timeout;
13ef29ea 3219 u32 ioc_status, ioc_config, i;
824a1566
KD		 3220 struct mpi3_ioc_facts_data facts_data;
3221
463429f8 3222 mrioc->irqpoll_sleep = MPI3MR_IRQ_POLL_SLEEP;
824a1566 3223 mrioc->change_count = 0;
0da66348 3224 if (init_type == MPI3MR_IT_INIT) {
fb9b0457
KD		 3225 mrioc->cpu_count = num_online_cpus();
3226 retval = mpi3mr_setup_resources(mrioc);
3227 if (retval) {
3228 ioc_err(mrioc, "Failed to setup resources:error %d\n",
3229 retval);
3230 goto out_nocleanup;
3231 }
824a1566 3232 }
fb9b0457 3233
824a1566
KD		 3234 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
3235 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
3236
3237 ioc_info(mrioc, "SOD status %x configuration %x\n",
3238 ioc_status, ioc_config);
3239
3240 base_info = lo_hi_readq(&mrioc->sysif_regs->ioc_information);
3241 ioc_info(mrioc, "SOD base_info %llx\n", base_info);
3242
3243 /*The timeout value is in 2sec unit, changing it to seconds*/
3244 mrioc->ready_timeout =
3245 ((base_info & MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_MASK) >>
3246 MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_SHIFT) * 2;
3247
3248 ioc_info(mrioc, "IOC ready timeout %d\n", mrioc->ready_timeout);
3249
3250 ioc_state = mpi3mr_get_iocstate(mrioc);
3251 ioc_info(mrioc, "IOC in %s state during detection\n",
3252 mpi3mr_iocstate_name(ioc_state));
3253
3254 if (ioc_state == MRIOC_STATE_BECOMING_READY ||
3255 ioc_state == MRIOC_STATE_RESET_REQUESTED) {
3256 timeout = mrioc->ready_timeout * 10;
3257 do {
3258 msleep(100);
3259 } while (--timeout);
3260
3261 ioc_state = mpi3mr_get_iocstate(mrioc);
3262 ioc_info(mrioc,
3263 "IOC in %s state after waiting for reset time\n",
3264 mpi3mr_iocstate_name(ioc_state));
3265 }
3266
3267 if (ioc_state == MRIOC_STATE_READY) {
3268 retval = mpi3mr_issue_and_process_mur(mrioc,
3269 MPI3MR_RESET_FROM_BRINGUP);
3270 if (retval) {
3271 ioc_err(mrioc, "Failed to MU reset IOC error %d\n",
3272 retval);
3273 }
3274 ioc_state = mpi3mr_get_iocstate(mrioc);
3275 }
3276 if (ioc_state != MRIOC_STATE_RESET) {
3277 mpi3mr_print_fault_info(mrioc);
3278 retval = mpi3mr_issue_reset(mrioc,
3279 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET,
3280 MPI3MR_RESET_FROM_BRINGUP);
3281 if (retval) {
3282 ioc_err(mrioc,
3283 "%s :Failed to soft reset IOC error %d\n",
3284 __func__, retval);
3285 goto out_failed;
3286 }
3287 }
3288 ioc_state = mpi3mr_get_iocstate(mrioc);
3289 if (ioc_state != MRIOC_STATE_RESET) {
a254eae3 3290 retval = -1;
824a1566
KD		 3291 ioc_err(mrioc, "Cannot bring IOC to reset state\n");
3292 goto out_failed;
3293 }
3294
3295 retval = mpi3mr_setup_admin_qpair(mrioc);
3296 if (retval) {
3297 ioc_err(mrioc, "Failed to setup admin Qs: error %d\n",
3298 retval);
3299 goto out_failed;
3300 }
3301
3302 retval = mpi3mr_bring_ioc_ready(mrioc);
3303 if (retval) {
3304 ioc_err(mrioc, "Failed to bring ioc ready: error %d\n",
3305 retval);
3306 goto out_failed;
3307 }
3308
0da66348 3309 if (init_type != MPI3MR_IT_RESET) {
fb9b0457
KD		 3310 retval = mpi3mr_setup_isr(mrioc, 1);
3311 if (retval) {
3312 ioc_err(mrioc, "Failed to setup ISR error %d\n",
3313 retval);
3314 goto out_failed;
3315 }
3316 } else
3317 mpi3mr_ioc_enable_intr(mrioc);
824a1566
KD		 3318
3319 retval = mpi3mr_issue_iocfacts(mrioc, &facts_data);
3320 if (retval) {
3321 ioc_err(mrioc, "Failed to Issue IOC Facts %d\n",
3322 retval);
3323 goto out_failed;
3324 }
3325
3326 mpi3mr_process_factsdata(mrioc, &facts_data);
0da66348 3327 if (init_type == MPI3MR_IT_INIT) {
fb9b0457
KD		 3328 retval = mpi3mr_check_reset_dma_mask(mrioc);
3329 if (retval) {
3330 ioc_err(mrioc, "Resetting dma mask failed %d\n",
3331 retval);
3332 goto out_failed;
3333 }
824a1566
KD		 3334 }
3335
ff9561e9
KD		 3336 mpi3mr_print_ioc_info(mrioc);
3337
824a1566
KD		 3338 retval = mpi3mr_alloc_reply_sense_bufs(mrioc);
3339 if (retval) {
3340 ioc_err(mrioc,
3341 "%s :Failed to allocated reply sense buffers %d\n",
3342 __func__, retval);
3343 goto out_failed;
3344 }
3345
0da66348 3346 if (init_type == MPI3MR_IT_INIT) {
fb9b0457
KD		 3347 retval = mpi3mr_alloc_chain_bufs(mrioc);
3348 if (retval) {
3349 ioc_err(mrioc, "Failed to allocated chain buffers %d\n",
3350 retval);
3351 goto out_failed;
3352 }
824a1566
KD		 3353 }
3354
3355 retval = mpi3mr_issue_iocinit(mrioc);
3356 if (retval) {
3357 ioc_err(mrioc, "Failed to Issue IOC Init %d\n",
3358 retval);
3359 goto out_failed;
3360 }
3361 mrioc->reply_free_queue_host_index = mrioc->num_reply_bufs;
3362 writel(mrioc->reply_free_queue_host_index,
3363 &mrioc->sysif_regs->reply_free_host_index);
3364
3365 mrioc->sbq_host_index = mrioc->num_sense_bufs;
3366 writel(mrioc->sbq_host_index,
3367 &mrioc->sysif_regs->sense_buffer_free_host_index);
3368
0da66348 3369 if (init_type != MPI3MR_IT_RESET) {
fb9b0457
KD		 3370 retval = mpi3mr_setup_isr(mrioc, 0);
3371 if (retval) {
3372 ioc_err(mrioc, "Failed to re-setup ISR, error %d\n",
3373 retval);
3374 goto out_failed;
3375 }
824a1566
KD		 3376 }
3377
c9566231
KD		 3378 retval = mpi3mr_create_op_queues(mrioc);
3379 if (retval) {
3380 ioc_err(mrioc, "Failed to create OpQueues error %d\n",
3381 retval);
3382 goto out_failed;
3383 }
3384
0da66348 3385 if ((init_type != MPI3MR_IT_INIT) &&
fb9b0457 3386 (mrioc->shost->nr_hw_queues > mrioc->num_op_reply_q)) {
a254eae3 3387 retval = -1;
fb9b0457
KD		 3388 ioc_err(mrioc,
3389 "Cannot create minimum number of OpQueues expected:%d created:%d\n",
3390 mrioc->shost->nr_hw_queues, mrioc->num_op_reply_q);
3391 goto out_failed;
3392 }
3393
13ef29ea
KD		 3394 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
3395 mrioc->event_masks[i] = -1;
3396
3397 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_ADDED);
3398 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_INFO_CHANGED);
3399 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_STATUS_CHANGE);
3400 mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE);
3401 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST);
3402 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_DISCOVERY);
3403 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR);
e36710dc 3404 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_BROADCAST_PRIMITIVE);
8e653455
KD		 3405 mpi3mr_unmask_events(mrioc, MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST);
3406 mpi3mr_unmask_events(mrioc, MPI3_EVENT_PCIE_ENUMERATION);
e36710dc
KD		 3407 mpi3mr_unmask_events(mrioc, MPI3_EVENT_CABLE_MGMT);
3408 mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENERGY_PACK_CHANGE);
13ef29ea
KD		 3409
3410 retval = mpi3mr_issue_event_notification(mrioc);
3411 if (retval) {
3412 ioc_err(mrioc, "Failed to issue event notification %d\n",
3413 retval);
3414 goto out_failed;
3415 }
3416
0da66348 3417 if (init_type != MPI3MR_IT_INIT) {
fb9b0457
KD		 3418 ioc_info(mrioc, "Issuing Port Enable\n");
3419 retval = mpi3mr_issue_port_enable(mrioc, 0);
3420 if (retval) {
3421 ioc_err(mrioc, "Failed to issue port enable %d\n",
3422 retval);
3423 goto out_failed;
3424 }
3425 }
824a1566
KD		 3426 return retval;
3427
3428out_failed:
0da66348
KD		 3429 if (init_type == MPI3MR_IT_INIT)
3430 mpi3mr_cleanup_ioc(mrioc, MPI3MR_COMPLETE_CLEANUP);
3431 else
3432 mpi3mr_cleanup_ioc(mrioc, MPI3MR_REINIT_FAILURE);
824a1566
KD		 3433out_nocleanup:
3434 return retval;
3435}
3436
fb9b0457
KD		 3437/**
3438 * mpi3mr_memset_op_reply_q_buffers - memset the operational reply queue's
3439 * segments
3440 * @mrioc: Adapter instance reference
3441 * @qidx: Operational reply queue index
3442 *
3443 * Return: Nothing.
3444 */
3445static void mpi3mr_memset_op_reply_q_buffers(struct mpi3mr_ioc *mrioc, u16 qidx)
3446{
3447 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
3448 struct segments *segments;
3449 int i, size;
3450
3451 if (!op_reply_q->q_segments)
3452 return;
3453
3454 size = op_reply_q->segment_qd * mrioc->op_reply_desc_sz;
3455 segments = op_reply_q->q_segments;
3456 for (i = 0; i < op_reply_q->num_segments; i++)
3457 memset(segments[i].segment, 0, size);
3458}
3459
3460/**
3461 * mpi3mr_memset_op_req_q_buffers - memset the operational request queue's
3462 * segments
3463 * @mrioc: Adapter instance reference
3464 * @qidx: Operational request queue index
3465 *
3466 * Return: Nothing.
3467 */
3468static void mpi3mr_memset_op_req_q_buffers(struct mpi3mr_ioc *mrioc, u16 qidx)
3469{
3470 struct op_req_qinfo *op_req_q = mrioc->req_qinfo + qidx;
3471 struct segments *segments;
3472 int i, size;
3473
3474 if (!op_req_q->q_segments)
3475 return;
3476
3477 size = op_req_q->segment_qd * mrioc->facts.op_req_sz;
3478 segments = op_req_q->q_segments;
3479 for (i = 0; i < op_req_q->num_segments; i++)
3480 memset(segments[i].segment, 0, size);
3481}
3482
3483/**
3484 * mpi3mr_memset_buffers - memset memory for a controller
3485 * @mrioc: Adapter instance reference
3486 *
3487 * clear all the memory allocated for a controller, typically
3488 * called post reset to reuse the memory allocated during the
3489 * controller init.
3490 *
3491 * Return: Nothing.
3492 */
0da66348 3493void mpi3mr_memset_buffers(struct mpi3mr_ioc *mrioc)
fb9b0457
KD		 3494{
3495 u16 i;
3496
3497 memset(mrioc->admin_req_base, 0, mrioc->admin_req_q_sz);
3498 memset(mrioc->admin_reply_base, 0, mrioc->admin_reply_q_sz);
3499
3500 memset(mrioc->init_cmds.reply, 0, sizeof(*mrioc->init_cmds.reply));
e844adb1
KD		 3501 memset(mrioc->host_tm_cmds.reply, 0,
3502 sizeof(*mrioc->host_tm_cmds.reply));
fb9b0457
KD		 3503 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++)
3504 memset(mrioc->dev_rmhs_cmds[i].reply, 0,
3505 sizeof(*mrioc->dev_rmhs_cmds[i].reply));
3506 memset(mrioc->removepend_bitmap, 0, mrioc->dev_handle_bitmap_sz);
3507 memset(mrioc->devrem_bitmap, 0, mrioc->devrem_bitmap_sz);
3508
3509 for (i = 0; i < mrioc->num_queues; i++) {
3510 mrioc->op_reply_qinfo[i].qid = 0;
3511 mrioc->op_reply_qinfo[i].ci = 0;
3512 mrioc->op_reply_qinfo[i].num_replies = 0;
3513 mrioc->op_reply_qinfo[i].ephase = 0;
463429f8
KD		 3514 atomic_set(&mrioc->op_reply_qinfo[i].pend_ios, 0);
3515 atomic_set(&mrioc->op_reply_qinfo[i].in_use, 0);
fb9b0457
KD		 3516 mpi3mr_memset_op_reply_q_buffers(mrioc, i);
3517
3518 mrioc->req_qinfo[i].ci = 0;
3519 mrioc->req_qinfo[i].pi = 0;
3520 mrioc->req_qinfo[i].num_requests = 0;
3521 mrioc->req_qinfo[i].qid = 0;
3522 mrioc->req_qinfo[i].reply_qid = 0;
3523 spin_lock_init(&mrioc->req_qinfo[i].q_lock);
3524 mpi3mr_memset_op_req_q_buffers(mrioc, i);
3525 }
3526}
3527
824a1566
KD		 3528/**
3529 * mpi3mr_free_mem - Free memory allocated for a controller
3530 * @mrioc: Adapter instance reference
3531 *
3532 * Free all the memory allocated for a controller.
3533 *
3534 * Return: Nothing.
3535 */
3536static void mpi3mr_free_mem(struct mpi3mr_ioc *mrioc)
3537{
3538 u16 i;
3539 struct mpi3mr_intr_info *intr_info;
3540
3541 if (mrioc->sense_buf_pool) {
3542 if (mrioc->sense_buf)
3543 dma_pool_free(mrioc->sense_buf_pool, mrioc->sense_buf,
3544 mrioc->sense_buf_dma);
3545 dma_pool_destroy(mrioc->sense_buf_pool);
3546 mrioc->sense_buf = NULL;
3547 mrioc->sense_buf_pool = NULL;
3548 }
3549 if (mrioc->sense_buf_q_pool) {
3550 if (mrioc->sense_buf_q)
3551 dma_pool_free(mrioc->sense_buf_q_pool,
3552 mrioc->sense_buf_q, mrioc->sense_buf_q_dma);
3553 dma_pool_destroy(mrioc->sense_buf_q_pool);
3554 mrioc->sense_buf_q = NULL;
3555 mrioc->sense_buf_q_pool = NULL;
3556 }
3557
3558 if (mrioc->reply_buf_pool) {
3559 if (mrioc->reply_buf)
3560 dma_pool_free(mrioc->reply_buf_pool, mrioc->reply_buf,
3561 mrioc->reply_buf_dma);
3562 dma_pool_destroy(mrioc->reply_buf_pool);
3563 mrioc->reply_buf = NULL;
3564 mrioc->reply_buf_pool = NULL;
3565 }
3566 if (mrioc->reply_free_q_pool) {
3567 if (mrioc->reply_free_q)
3568 dma_pool_free(mrioc->reply_free_q_pool,
3569 mrioc->reply_free_q, mrioc->reply_free_q_dma);
3570 dma_pool_destroy(mrioc->reply_free_q_pool);
3571 mrioc->reply_free_q = NULL;
3572 mrioc->reply_free_q_pool = NULL;
3573 }
3574
c9566231
KD		 3575 for (i = 0; i < mrioc->num_op_req_q; i++)
3576 mpi3mr_free_op_req_q_segments(mrioc, i);
3577
3578 for (i = 0; i < mrioc->num_op_reply_q; i++)
3579 mpi3mr_free_op_reply_q_segments(mrioc, i);
3580
824a1566
KD		 3581 for (i = 0; i < mrioc->intr_info_count; i++) {
3582 intr_info = mrioc->intr_info + i;
d46bdecd 3583 intr_info->op_reply_q = NULL;
824a1566
KD		 3584 }
3585
3586 kfree(mrioc->req_qinfo);
3587 mrioc->req_qinfo = NULL;
3588 mrioc->num_op_req_q = 0;
3589
3590 kfree(mrioc->op_reply_qinfo);
3591 mrioc->op_reply_qinfo = NULL;
3592 mrioc->num_op_reply_q = 0;
3593
3594 kfree(mrioc->init_cmds.reply);
3595 mrioc->init_cmds.reply = NULL;
3596
e844adb1
KD		 3597 kfree(mrioc->host_tm_cmds.reply);
3598 mrioc->host_tm_cmds.reply = NULL;
3599
3600 kfree(mrioc->removepend_bitmap);
3601 mrioc->removepend_bitmap = NULL;
3602
3603 kfree(mrioc->devrem_bitmap);
3604 mrioc->devrem_bitmap = NULL;
3605
824a1566
KD		 3606 kfree(mrioc->chain_bitmap);
3607 mrioc->chain_bitmap = NULL;
3608
13ef29ea
KD		 3609 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) {
3610 kfree(mrioc->dev_rmhs_cmds[i].reply);
3611 mrioc->dev_rmhs_cmds[i].reply = NULL;
3612 }
3613
824a1566
KD		 3614 if (mrioc->chain_buf_pool) {
3615 for (i = 0; i < mrioc->chain_buf_count; i++) {
3616 if (mrioc->chain_sgl_list[i].addr) {
3617 dma_pool_free(mrioc->chain_buf_pool,
3618 mrioc->chain_sgl_list[i].addr,
3619 mrioc->chain_sgl_list[i].dma_addr);
3620 mrioc->chain_sgl_list[i].addr = NULL;
3621 }
3622 }
3623 dma_pool_destroy(mrioc->chain_buf_pool);
3624 mrioc->chain_buf_pool = NULL;
3625 }
3626
3627 kfree(mrioc->chain_sgl_list);
3628 mrioc->chain_sgl_list = NULL;
3629
3630 if (mrioc->admin_reply_base) {
3631 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_reply_q_sz,
3632 mrioc->admin_reply_base, mrioc->admin_reply_dma);
3633 mrioc->admin_reply_base = NULL;
3634 }
3635 if (mrioc->admin_req_base) {
3636 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_req_q_sz,
3637 mrioc->admin_req_base, mrioc->admin_req_dma);
3638 mrioc->admin_req_base = NULL;
3639 }
3640}
3641
3642/**
3643 * mpi3mr_issue_ioc_shutdown - shutdown controller
3644 * @mrioc: Adapter instance reference
3645 *
3646 * Send shutodwn notification to the controller and wait for the
3647 * shutdown_timeout for it to be completed.
3648 *
3649 * Return: Nothing.
3650 */
3651static void mpi3mr_issue_ioc_shutdown(struct mpi3mr_ioc *mrioc)
3652{
3653 u32 ioc_config, ioc_status;
3654 u8 retval = 1;
3655 u32 timeout = MPI3MR_DEFAULT_SHUTDOWN_TIME * 10;
3656
3657 ioc_info(mrioc, "Issuing shutdown Notification\n");
3658 if (mrioc->unrecoverable) {
3659 ioc_warn(mrioc,
3660 "IOC is unrecoverable shutdown is not issued\n");
3661 return;
3662 }
3663 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
3664 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK)
3665 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS) {
3666 ioc_info(mrioc, "shutdown already in progress\n");
3667 return;
3668 }
3669
3670 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
3671 ioc_config |= MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NORMAL;
3672 ioc_config |= MPI3_SYSIF_IOC_CONFIG_DEVICE_SHUTDOWN;
3673
3674 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
3675
3676 if (mrioc->facts.shutdown_timeout)
3677 timeout = mrioc->facts.shutdown_timeout * 10;
3678
3679 do {
3680 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
3681 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK)
3682 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_COMPLETE) {
3683 retval = 0;
3684 break;
3685 }
3686 msleep(100);
3687 } while (--timeout);
3688
3689 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
3690 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
3691
3692 if (retval) {
3693 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK)
3694 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS)
3695 ioc_warn(mrioc,
3696 "shutdown still in progress after timeout\n");
3697 }
3698
3699 ioc_info(mrioc,
3700 "Base IOC Sts/Config after %s shutdown is (0x%x)/(0x%x)\n",
3701 (!retval) ? "successful" : "failed", ioc_status,
3702 ioc_config);
3703}
3704
3705/**
3706 * mpi3mr_cleanup_ioc - Cleanup controller
3707 * @mrioc: Adapter instance reference
0da66348 3708 * @reason: Cleanup reason
824a1566
KD		 3709 *
3710 * controller cleanup handler, Message unit reset or soft reset
3711 * and shutdown notification is issued to the controller and the
3712 * associated memory resources are freed.
3713 *
3714 * Return: Nothing.
3715 */
0da66348 3716void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc, u8 reason)
824a1566
KD		 3717{
3718 enum mpi3mr_iocstate ioc_state;
3719
0da66348 3720 if (reason == MPI3MR_COMPLETE_CLEANUP)
fb9b0457 3721 mpi3mr_stop_watchdog(mrioc);
672ae26c 3722
824a1566
KD		 3723 mpi3mr_ioc_disable_intr(mrioc);
3724
3725 ioc_state = mpi3mr_get_iocstate(mrioc);
3726
3727 if ((!mrioc->unrecoverable) && (!mrioc->reset_in_progress) &&
3728 (ioc_state == MRIOC_STATE_READY)) {
3729 if (mpi3mr_issue_and_process_mur(mrioc,
3730 MPI3MR_RESET_FROM_CTLR_CLEANUP))
3731 mpi3mr_issue_reset(mrioc,
3732 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET,
3733 MPI3MR_RESET_FROM_MUR_FAILURE);
3734
0da66348 3735 if (reason != MPI3MR_REINIT_FAILURE)
fb9b0457 3736 mpi3mr_issue_ioc_shutdown(mrioc);
824a1566
KD		 3737 }
3738
0da66348 3739 if (reason == MPI3MR_COMPLETE_CLEANUP) {
fb9b0457
KD		 3740 mpi3mr_free_mem(mrioc);
3741 mpi3mr_cleanup_resources(mrioc);
3742 }
3743}
3744
3745/**
3746 * mpi3mr_drv_cmd_comp_reset - Flush a internal driver command
3747 * @mrioc: Adapter instance reference
3748 * @cmdptr: Internal command tracker
3749 *
3750 * Complete an internal driver commands with state indicating it
3751 * is completed due to reset.
3752 *
3753 * Return: Nothing.
3754 */
3755static inline void mpi3mr_drv_cmd_comp_reset(struct mpi3mr_ioc *mrioc,
3756 struct mpi3mr_drv_cmd *cmdptr)
3757{
3758 if (cmdptr->state & MPI3MR_CMD_PENDING) {
3759 cmdptr->state |= MPI3MR_CMD_RESET;
3760 cmdptr->state &= ~MPI3MR_CMD_PENDING;
3761 if (cmdptr->is_waiting) {
3762 complete(&cmdptr->done);
3763 cmdptr->is_waiting = 0;
3764 } else if (cmdptr->callback)
3765 cmdptr->callback(mrioc, cmdptr);
3766 }
3767}
3768
3769/**
3770 * mpi3mr_flush_drv_cmds - Flush internaldriver commands
3771 * @mrioc: Adapter instance reference
3772 *
3773 * Flush all internal driver commands post reset
3774 *
3775 * Return: Nothing.
3776 */
3777static void mpi3mr_flush_drv_cmds(struct mpi3mr_ioc *mrioc)
3778{
3779 struct mpi3mr_drv_cmd *cmdptr;
3780 u8 i;
3781
3782 cmdptr = &mrioc->init_cmds;
3783 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
e844adb1
KD		 3784 cmdptr = &mrioc->host_tm_cmds;
3785 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
fb9b0457
KD		 3786
3787 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) {
3788 cmdptr = &mrioc->dev_rmhs_cmds[i];
3789 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
3790 }
3791}
3792
3793/**
3794 * mpi3mr_diagfault_reset_handler - Diag fault reset handler
3795 * @mrioc: Adapter instance reference
3796 * @reset_reason: Reset reason code
3797 *
3798 * This is an handler for issuing diag fault reset from the
3799 * applications through IOCTL path to stop the execution of the
3800 * controller
3801 *
3802 * Return: 0 on success, non-zero on failure.
3803 */
3804int mpi3mr_diagfault_reset_handler(struct mpi3mr_ioc *mrioc,
3805 u32 reset_reason)
3806{
3807 int retval = 0;
3808
f061178e
KD		 3809 ioc_info(mrioc, "Entry: reason code: %s\n",
3810 mpi3mr_reset_rc_name(reset_reason));
fb9b0457
KD		 3811 mrioc->reset_in_progress = 1;
3812
3813 mpi3mr_ioc_disable_intr(mrioc);
3814
3815 retval = mpi3mr_issue_reset(mrioc,
3816 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, reset_reason);
3817
3818 if (retval) {
3819 ioc_err(mrioc, "The diag fault reset failed: reason %d\n",
3820 reset_reason);
3821 mpi3mr_ioc_enable_intr(mrioc);
3822 }
3823 ioc_info(mrioc, "%s\n", ((retval == 0) ? "SUCCESS" : "FAILED"));
3824 mrioc->reset_in_progress = 0;
3825 return retval;
824a1566
KD		 3826}
3827
3828/**
3829 * mpi3mr_soft_reset_handler - Reset the controller
3830 * @mrioc: Adapter instance reference
3831 * @reset_reason: Reset reason code
3832 * @snapdump: Flag to generate snapdump in firmware or not
3833 *
fb9b0457
KD		 3834 * This is an handler for recovering controller by issuing soft
3835 * reset are diag fault reset. This is a blocking function and
3836 * when one reset is executed if any other resets they will be
3837 * blocked. All IOCTLs/IO will be blocked during the reset. If
3838 * controller reset is successful then the controller will be
3839 * reinitalized, otherwise the controller will be marked as not
3840 * recoverable
3841 *
3842 * In snapdump bit is set, the controller is issued with diag
3843 * fault reset so that the firmware can create a snap dump and
3844 * post that the firmware will result in F000 fault and the
3845 * driver will issue soft reset to recover from that.
824a1566
KD		 3846 *
3847 * Return: 0 on success, non-zero on failure.
3848 */
3849int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc,
3850 u32 reset_reason, u8 snapdump)
3851{
fb9b0457
KD		 3852 int retval = 0, i;
3853 unsigned long flags;
3854 u32 host_diagnostic, timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10;
3855
3856 if (mrioc->fault_dbg) {
3857 if (snapdump)
3858 mpi3mr_set_diagsave(mrioc);
3859 mpi3mr_kill_ioc(mrioc, reset_reason);
3860 }
3861
3862 /*
3863 * Block new resets until the currently executing one is finished and
3864 * return the status of the existing reset for all blocked resets
3865 */
3866 if (!mutex_trylock(&mrioc->reset_mutex)) {
3867 ioc_info(mrioc, "Another reset in progress\n");
3868 return -1;
3869 }
3870 mrioc->reset_in_progress = 1;
3871
3872 if ((!snapdump) && (reset_reason != MPI3MR_RESET_FROM_FAULT_WATCH) &&
3873 (reset_reason != MPI3MR_RESET_FROM_CIACTIV_FAULT)) {
3874 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
3875 mrioc->event_masks[i] = -1;
3876
3877 retval = mpi3mr_issue_event_notification(mrioc);
3878
3879 if (retval) {
3880 ioc_err(mrioc,
3881 "Failed to turn off events prior to reset %d\n",
3882 retval);
3883 }
3884 }
3885
44dc724f
KD		 3886 mpi3mr_wait_for_host_io(mrioc, MPI3MR_RESET_HOST_IOWAIT_TIMEOUT);
3887
fb9b0457
KD		 3888 mpi3mr_ioc_disable_intr(mrioc);
3889
3890 if (snapdump) {
3891 mpi3mr_set_diagsave(mrioc);
3892 retval = mpi3mr_issue_reset(mrioc,
3893 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, reset_reason);
3894 if (!retval) {
3895 do {
3896 host_diagnostic =
3897 readl(&mrioc->sysif_regs->host_diagnostic);
3898 if (!(host_diagnostic &
3899 MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS))
3900 break;
3901 msleep(100);
3902 } while (--timeout);
3903 }
3904 }
3905
3906 retval = mpi3mr_issue_reset(mrioc,
3907 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, reset_reason);
3908 if (retval) {
3909 ioc_err(mrioc, "Failed to issue soft reset to the ioc\n");
3910 goto out;
3911 }
3912
3913 mpi3mr_flush_delayed_rmhs_list(mrioc);
3914 mpi3mr_flush_drv_cmds(mrioc);
3915 memset(mrioc->devrem_bitmap, 0, mrioc->devrem_bitmap_sz);
3916 memset(mrioc->removepend_bitmap, 0, mrioc->dev_handle_bitmap_sz);
3917 mpi3mr_cleanup_fwevt_list(mrioc);
3918 mpi3mr_flush_host_io(mrioc);
3919 mpi3mr_invalidate_devhandles(mrioc);
3920 mpi3mr_memset_buffers(mrioc);
0da66348 3921 retval = mpi3mr_init_ioc(mrioc, MPI3MR_IT_RESET);
fb9b0457
KD		 3922 if (retval) {
3923 pr_err(IOCNAME "reinit after soft reset failed: reason %d\n",
3924 mrioc->name, reset_reason);
3925 goto out;
3926 }
3927 ssleep(10);
3928
3929out:
3930 if (!retval) {
3931 mrioc->reset_in_progress = 0;
3932 scsi_unblock_requests(mrioc->shost);
3933 mpi3mr_rfresh_tgtdevs(mrioc);
54dfcffb 3934 mrioc->ts_update_counter = 0;
fb9b0457
KD		 3935 spin_lock_irqsave(&mrioc->watchdog_lock, flags);
3936 if (mrioc->watchdog_work_q)
3937 queue_delayed_work(mrioc->watchdog_work_q,
3938 &mrioc->watchdog_work,
3939 msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL));
3940 spin_unlock_irqrestore(&mrioc->watchdog_lock, flags);
3941 } else {
3942 mpi3mr_issue_reset(mrioc,
3943 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, reset_reason);
3944 mrioc->unrecoverable = 1;
3945 mrioc->reset_in_progress = 0;
3946 retval = -1;
3947 }
3948
3949 mutex_unlock(&mrioc->reset_mutex);
3950 ioc_info(mrioc, "%s\n", ((retval == 0) ? "SUCCESS" : "FAILED"));
3951 return retval;
824a1566 3952}
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