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mpt3sas: fix for driver fails EEH, recovery from injected pci bus error
[mirror_ubuntu-artful-kernel.git] / drivers / scsi / mpt3sas / mpt3sas_base.c
CommitLineData
f92363d1
SR		 1/*
2 * This is the Fusion MPT base driver providing common API layer interface
3 * for access to MPT (Message Passing Technology) firmware.
4 *
5 * This code is based on drivers/scsi/mpt3sas/mpt3sas_base.c
a4ffce0d 6 * Copyright (C) 2012-2014 LSI Corporation
a03bd153
SR		 7 * Copyright (C) 2013-2014 Avago Technologies
8 * (mailto: MPT-FusionLinux.pdl@avagotech.com)
f92363d1
SR		 9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version 2
13 * of the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * NO WARRANTY
21 * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
22 * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
23 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
24 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
25 * solely responsible for determining the appropriateness of using and
26 * distributing the Program and assumes all risks associated with its
27 * exercise of rights under this Agreement, including but not limited to
28 * the risks and costs of program errors, damage to or loss of data,
29 * programs or equipment, and unavailability or interruption of operations.
30
31 * DISCLAIMER OF LIABILITY
32 * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
33 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34 * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
35 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
36 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
37 * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
38 * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
39
40 * You should have received a copy of the GNU General Public License
41 * along with this program; if not, write to the Free Software
42 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
43 * USA.
44 */
45
f92363d1
SR		 46#include <linux/kernel.h>
47#include <linux/module.h>
48#include <linux/errno.h>
49#include <linux/init.h>
50#include <linux/slab.h>
51#include <linux/types.h>
52#include <linux/pci.h>
53#include <linux/kdev_t.h>
54#include <linux/blkdev.h>
55#include <linux/delay.h>
56#include <linux/interrupt.h>
57#include <linux/dma-mapping.h>
58#include <linux/io.h>
59#include <linux/time.h>
60#include <linux/kthread.h>
61#include <linux/aer.h>
62
63
64#include "mpt3sas_base.h"
65
66static MPT_CALLBACK mpt_callbacks[MPT_MAX_CALLBACKS];
67
68
69#define FAULT_POLLING_INTERVAL 1000 /* in milliseconds */
70
71 /* maximum controller queue depth */
72#define MAX_HBA_QUEUE_DEPTH 30000
73#define MAX_CHAIN_DEPTH 100000
74static int max_queue_depth = -1;
75module_param(max_queue_depth, int, 0);
76MODULE_PARM_DESC(max_queue_depth, " max controller queue depth ");
77
78static int max_sgl_entries = -1;
79module_param(max_sgl_entries, int, 0);
80MODULE_PARM_DESC(max_sgl_entries, " max sg entries ");
81
82static int msix_disable = -1;
83module_param(msix_disable, int, 0);
84MODULE_PARM_DESC(msix_disable, " disable msix routed interrupts (default=0)");
85
fb77bb53 86static int max_msix_vectors = -1;
9c500060
SR		 87module_param(max_msix_vectors, int, 0);
88MODULE_PARM_DESC(max_msix_vectors,
fb77bb53 89 " max msix vectors");
f92363d1
SR		 90
91static int mpt3sas_fwfault_debug;
92MODULE_PARM_DESC(mpt3sas_fwfault_debug,
93 " enable detection of firmware fault and halt firmware - (default=0)");
94
9b05c91a
SR		 95static int
96_base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc, int sleep_flag);
f92363d1
SR		 97
98/**
99 * _scsih_set_fwfault_debug - global setting of ioc->fwfault_debug.
100 *
101 */
102static int
103_scsih_set_fwfault_debug(const char *val, struct kernel_param *kp)
104{
105 int ret = param_set_int(val, kp);
106 struct MPT3SAS_ADAPTER *ioc;
107
108 if (ret)
109 return ret;
110
111 pr_info("setting fwfault_debug(%d)\n", mpt3sas_fwfault_debug);
112 list_for_each_entry(ioc, &mpt3sas_ioc_list, list)
113 ioc->fwfault_debug = mpt3sas_fwfault_debug;
114 return 0;
115}
116module_param_call(mpt3sas_fwfault_debug, _scsih_set_fwfault_debug,
117 param_get_int, &mpt3sas_fwfault_debug, 0644);
118
119/**
120 * mpt3sas_remove_dead_ioc_func - kthread context to remove dead ioc
121 * @arg: input argument, used to derive ioc
122 *
123 * Return 0 if controller is removed from pci subsystem.
124 * Return -1 for other case.
125 */
126static int mpt3sas_remove_dead_ioc_func(void *arg)
127{
128 struct MPT3SAS_ADAPTER *ioc = (struct MPT3SAS_ADAPTER *)arg;
129 struct pci_dev *pdev;
130
131 if ((ioc == NULL))
132 return -1;
133
134 pdev = ioc->pdev;
135 if ((pdev == NULL))
136 return -1;
64cdb418 137 pci_stop_and_remove_bus_device_locked(pdev);
f92363d1
SR		 138 return 0;
139}
140
141/**
142 * _base_fault_reset_work - workq handling ioc fault conditions
143 * @work: input argument, used to derive ioc
144 * Context: sleep.
145 *
146 * Return nothing.
147 */
148static void
149_base_fault_reset_work(struct work_struct *work)
150{
151 struct MPT3SAS_ADAPTER *ioc =
152 container_of(work, struct MPT3SAS_ADAPTER, fault_reset_work.work);
153 unsigned long flags;
154 u32 doorbell;
155 int rc;
156 struct task_struct *p;
157
158
159 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
16e179bd 160 if (ioc->shost_recovery || ioc->pci_error_recovery)
f92363d1
SR		 161 goto rearm_timer;
162 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
163
164 doorbell = mpt3sas_base_get_iocstate(ioc, 0);
165 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_MASK) {
166 pr_err(MPT3SAS_FMT "SAS host is non-operational !!!!\n",
167 ioc->name);
168
16e179bd
SR		 169 /* It may be possible that EEH recovery can resolve some of
170 * pci bus failure issues rather removing the dead ioc function
171 * by considering controller is in a non-operational state. So
172 * here priority is given to the EEH recovery. If it doesn't
173 * not resolve this issue, mpt3sas driver will consider this
174 * controller to non-operational state and remove the dead ioc
175 * function.
176 */
177 if (ioc->non_operational_loop++ < 5) {
178 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock,
179 flags);
180 goto rearm_timer;
181 }
182
f92363d1
SR		 183 /*
184 * Call _scsih_flush_pending_cmds callback so that we flush all
185 * pending commands back to OS. This call is required to aovid
186 * deadlock at block layer. Dead IOC will fail to do diag reset,
187 * and this call is safe since dead ioc will never return any
188 * command back from HW.
189 */
190 ioc->schedule_dead_ioc_flush_running_cmds(ioc);
191 /*
192 * Set remove_host flag early since kernel thread will
193 * take some time to execute.
194 */
195 ioc->remove_host = 1;
196 /*Remove the Dead Host */
197 p = kthread_run(mpt3sas_remove_dead_ioc_func, ioc,
198 "mpt3sas_dead_ioc_%d", ioc->id);
199 if (IS_ERR(p))
200 pr_err(MPT3SAS_FMT
201 "%s: Running mpt3sas_dead_ioc thread failed !!!!\n",
202 ioc->name, __func__);
203 else
204 pr_err(MPT3SAS_FMT
205 "%s: Running mpt3sas_dead_ioc thread success !!!!\n",
206 ioc->name, __func__);
207 return; /* don't rearm timer */
208 }
209
16e179bd
SR		 210 ioc->non_operational_loop = 0;
211
f92363d1
SR		 212 if ((doorbell & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL) {
213 rc = mpt3sas_base_hard_reset_handler(ioc, CAN_SLEEP,
214 FORCE_BIG_HAMMER);
215 pr_warn(MPT3SAS_FMT "%s: hard reset: %s\n", ioc->name,
216 __func__, (rc == 0) ? "success" : "failed");
217 doorbell = mpt3sas_base_get_iocstate(ioc, 0);
218 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
219 mpt3sas_base_fault_info(ioc, doorbell &
220 MPI2_DOORBELL_DATA_MASK);
221 if (rc && (doorbell & MPI2_IOC_STATE_MASK) !=
222 MPI2_IOC_STATE_OPERATIONAL)
223 return; /* don't rearm timer */
224 }
225
226 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
227 rearm_timer:
228 if (ioc->fault_reset_work_q)
229 queue_delayed_work(ioc->fault_reset_work_q,
230 &ioc->fault_reset_work,
231 msecs_to_jiffies(FAULT_POLLING_INTERVAL));
232 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
233}
234
235/**
236 * mpt3sas_base_start_watchdog - start the fault_reset_work_q
237 * @ioc: per adapter object
238 * Context: sleep.
239 *
240 * Return nothing.
241 */
242void
243mpt3sas_base_start_watchdog(struct MPT3SAS_ADAPTER *ioc)
244{
245 unsigned long flags;
246
247 if (ioc->fault_reset_work_q)
248 return;
249
250 /* initialize fault polling */
251
252 INIT_DELAYED_WORK(&ioc->fault_reset_work, _base_fault_reset_work);
253 snprintf(ioc->fault_reset_work_q_name,
254 sizeof(ioc->fault_reset_work_q_name), "poll_%d_status", ioc->id);
255 ioc->fault_reset_work_q =
256 create_singlethread_workqueue(ioc->fault_reset_work_q_name);
257 if (!ioc->fault_reset_work_q) {
258 pr_err(MPT3SAS_FMT "%s: failed (line=%d)\n",
259 ioc->name, __func__, __LINE__);
260 return;
261 }
262 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
263 if (ioc->fault_reset_work_q)
264 queue_delayed_work(ioc->fault_reset_work_q,
265 &ioc->fault_reset_work,
266 msecs_to_jiffies(FAULT_POLLING_INTERVAL));
267 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
268}
269
270/**
271 * mpt3sas_base_stop_watchdog - stop the fault_reset_work_q
272 * @ioc: per adapter object
273 * Context: sleep.
274 *
275 * Return nothing.
276 */
277void
278mpt3sas_base_stop_watchdog(struct MPT3SAS_ADAPTER *ioc)
279{
280 unsigned long flags;
281 struct workqueue_struct *wq;
282
283 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
284 wq = ioc->fault_reset_work_q;
285 ioc->fault_reset_work_q = NULL;
286 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
287 if (wq) {
4dc06fd8 288 if (!cancel_delayed_work_sync(&ioc->fault_reset_work))
f92363d1
SR		 289 flush_workqueue(wq);
290 destroy_workqueue(wq);
291 }
292}
293
294/**
295 * mpt3sas_base_fault_info - verbose translation of firmware FAULT code
296 * @ioc: per adapter object
297 * @fault_code: fault code
298 *
299 * Return nothing.
300 */
301void
302mpt3sas_base_fault_info(struct MPT3SAS_ADAPTER *ioc , u16 fault_code)
303{
304 pr_err(MPT3SAS_FMT "fault_state(0x%04x)!\n",
305 ioc->name, fault_code);
306}
307
308/**
309 * mpt3sas_halt_firmware - halt's mpt controller firmware
310 * @ioc: per adapter object
311 *
312 * For debugging timeout related issues. Writing 0xCOFFEE00
313 * to the doorbell register will halt controller firmware. With
314 * the purpose to stop both driver and firmware, the enduser can
315 * obtain a ring buffer from controller UART.
316 */
317void
318mpt3sas_halt_firmware(struct MPT3SAS_ADAPTER *ioc)
319{
320 u32 doorbell;
321
322 if (!ioc->fwfault_debug)
323 return;
324
325 dump_stack();
326
327 doorbell = readl(&ioc->chip->Doorbell);
328 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
329 mpt3sas_base_fault_info(ioc , doorbell);
330 else {
331 writel(0xC0FFEE00, &ioc->chip->Doorbell);
332 pr_err(MPT3SAS_FMT "Firmware is halted due to command timeout\n",
333 ioc->name);
334 }
335
336 if (ioc->fwfault_debug == 2)
337 for (;;)
338 ;
339 else
340 panic("panic in %s\n", __func__);
341}
342
f92363d1
SR		 343/**
344 * _base_sas_ioc_info - verbose translation of the ioc status
345 * @ioc: per adapter object
346 * @mpi_reply: reply mf payload returned from firmware
347 * @request_hdr: request mf
348 *
349 * Return nothing.
350 */
351static void
352_base_sas_ioc_info(struct MPT3SAS_ADAPTER *ioc, MPI2DefaultReply_t *mpi_reply,
353 MPI2RequestHeader_t *request_hdr)
354{
355 u16 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) &
356 MPI2_IOCSTATUS_MASK;
357 char *desc = NULL;
358 u16 frame_sz;
359 char *func_str = NULL;
360
361 /* SCSI_IO, RAID_PASS are handled from _scsih_scsi_ioc_info */
362 if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST ||
363 request_hdr->Function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH ||
364 request_hdr->Function == MPI2_FUNCTION_EVENT_NOTIFICATION)
365 return;
366
367 if (ioc_status == MPI2_IOCSTATUS_CONFIG_INVALID_PAGE)
368 return;
369
370 switch (ioc_status) {
371
372/****************************************************************************
373* Common IOCStatus values for all replies
374****************************************************************************/
375
376 case MPI2_IOCSTATUS_INVALID_FUNCTION:
377 desc = "invalid function";
378 break;
379 case MPI2_IOCSTATUS_BUSY:
380 desc = "busy";
381 break;
382 case MPI2_IOCSTATUS_INVALID_SGL:
383 desc = "invalid sgl";
384 break;
385 case MPI2_IOCSTATUS_INTERNAL_ERROR:
386 desc = "internal error";
387 break;
388 case MPI2_IOCSTATUS_INVALID_VPID:
389 desc = "invalid vpid";
390 break;
391 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES:
392 desc = "insufficient resources";
393 break;
394 case MPI2_IOCSTATUS_INVALID_FIELD:
395 desc = "invalid field";
396 break;
397 case MPI2_IOCSTATUS_INVALID_STATE:
398 desc = "invalid state";
399 break;
400 case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED:
401 desc = "op state not supported";
402 break;
403
404/****************************************************************************
405* Config IOCStatus values
406****************************************************************************/
407
408 case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION:
409 desc = "config invalid action";
410 break;
411 case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE:
412 desc = "config invalid type";
413 break;
414 case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE:
415 desc = "config invalid page";
416 break;
417 case MPI2_IOCSTATUS_CONFIG_INVALID_DATA:
418 desc = "config invalid data";
419 break;
420 case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS:
421 desc = "config no defaults";
422 break;
423 case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT:
424 desc = "config cant commit";
425 break;
426
427/****************************************************************************
428* SCSI IO Reply
429****************************************************************************/
430
431 case MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR:
432 case MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE:
433 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
434 case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN:
435 case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN:
436 case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR:
437 case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR:
438 case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED:
439 case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH:
440 case MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED:
441 case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED:
442 case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED:
443 break;
444
445/****************************************************************************
446* For use by SCSI Initiator and SCSI Target end-to-end data protection
447****************************************************************************/
448
449 case MPI2_IOCSTATUS_EEDP_GUARD_ERROR:
450 desc = "eedp guard error";
451 break;
452 case MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR:
453 desc = "eedp ref tag error";
454 break;
455 case MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR:
456 desc = "eedp app tag error";
457 break;
458
459/****************************************************************************
460* SCSI Target values
461****************************************************************************/
462
463 case MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX:
464 desc = "target invalid io index";
465 break;
466 case MPI2_IOCSTATUS_TARGET_ABORTED:
467 desc = "target aborted";
468 break;
469 case MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE:
470 desc = "target no conn retryable";
471 break;
472 case MPI2_IOCSTATUS_TARGET_NO_CONNECTION:
473 desc = "target no connection";
474 break;
475 case MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH:
476 desc = "target xfer count mismatch";
477 break;
478 case MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR:
479 desc = "target data offset error";
480 break;
481 case MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA:
482 desc = "target too much write data";
483 break;
484 case MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT:
485 desc = "target iu too short";
486 break;
487 case MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT:
488 desc = "target ack nak timeout";
489 break;
490 case MPI2_IOCSTATUS_TARGET_NAK_RECEIVED:
491 desc = "target nak received";
492 break;
493
494/****************************************************************************
495* Serial Attached SCSI values
496****************************************************************************/
497
498 case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED:
499 desc = "smp request failed";
500 break;
501 case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN:
502 desc = "smp data overrun";
503 break;
504
505/****************************************************************************
506* Diagnostic Buffer Post / Diagnostic Release values
507****************************************************************************/
508
509 case MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED:
510 desc = "diagnostic released";
511 break;
512 default:
513 break;
514 }
515
516 if (!desc)
517 return;
518
519 switch (request_hdr->Function) {
520 case MPI2_FUNCTION_CONFIG:
521 frame_sz = sizeof(Mpi2ConfigRequest_t) + ioc->sge_size;
522 func_str = "config_page";
523 break;
524 case MPI2_FUNCTION_SCSI_TASK_MGMT:
525 frame_sz = sizeof(Mpi2SCSITaskManagementRequest_t);
526 func_str = "task_mgmt";
527 break;
528 case MPI2_FUNCTION_SAS_IO_UNIT_CONTROL:
529 frame_sz = sizeof(Mpi2SasIoUnitControlRequest_t);
530 func_str = "sas_iounit_ctl";
531 break;
532 case MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR:
533 frame_sz = sizeof(Mpi2SepRequest_t);
534 func_str = "enclosure";
535 break;
536 case MPI2_FUNCTION_IOC_INIT:
537 frame_sz = sizeof(Mpi2IOCInitRequest_t);
538 func_str = "ioc_init";
539 break;
540 case MPI2_FUNCTION_PORT_ENABLE:
541 frame_sz = sizeof(Mpi2PortEnableRequest_t);
542 func_str = "port_enable";
543 break;
544 case MPI2_FUNCTION_SMP_PASSTHROUGH:
545 frame_sz = sizeof(Mpi2SmpPassthroughRequest_t) + ioc->sge_size;
546 func_str = "smp_passthru";
547 break;
548 default:
549 frame_sz = 32;
550 func_str = "unknown";
551 break;
552 }
553
554 pr_warn(MPT3SAS_FMT "ioc_status: %s(0x%04x), request(0x%p),(%s)\n",
555 ioc->name, desc, ioc_status, request_hdr, func_str);
556
557 _debug_dump_mf(request_hdr, frame_sz/4);
558}
559
560/**
561 * _base_display_event_data - verbose translation of firmware asyn events
562 * @ioc: per adapter object
563 * @mpi_reply: reply mf payload returned from firmware
564 *
565 * Return nothing.
566 */
567static void
568_base_display_event_data(struct MPT3SAS_ADAPTER *ioc,
569 Mpi2EventNotificationReply_t *mpi_reply)
570{
571 char *desc = NULL;
572 u16 event;
573
574 if (!(ioc->logging_level & MPT_DEBUG_EVENTS))
575 return;
576
577 event = le16_to_cpu(mpi_reply->Event);
578
579 switch (event) {
580 case MPI2_EVENT_LOG_DATA:
581 desc = "Log Data";
582 break;
583 case MPI2_EVENT_STATE_CHANGE:
584 desc = "Status Change";
585 break;
586 case MPI2_EVENT_HARD_RESET_RECEIVED:
587 desc = "Hard Reset Received";
588 break;
589 case MPI2_EVENT_EVENT_CHANGE:
590 desc = "Event Change";
591 break;
592 case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE:
593 desc = "Device Status Change";
594 break;
595 case MPI2_EVENT_IR_OPERATION_STATUS:
596 desc = "IR Operation Status";
597 break;
598 case MPI2_EVENT_SAS_DISCOVERY:
599 {
600 Mpi2EventDataSasDiscovery_t *event_data =
601 (Mpi2EventDataSasDiscovery_t *)mpi_reply->EventData;
602 pr_info(MPT3SAS_FMT "Discovery: (%s)", ioc->name,
603 (event_data->ReasonCode == MPI2_EVENT_SAS_DISC_RC_STARTED) ?
604 "start" : "stop");
605 if (event_data->DiscoveryStatus)
606 pr_info("discovery_status(0x%08x)",
607 le32_to_cpu(event_data->DiscoveryStatus));
608 pr_info("\n");
609 return;
610 }
611 case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE:
612 desc = "SAS Broadcast Primitive";
613 break;
614 case MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
615 desc = "SAS Init Device Status Change";
616 break;
617 case MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW:
618 desc = "SAS Init Table Overflow";
619 break;
620 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
621 desc = "SAS Topology Change List";
622 break;
623 case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE:
624 desc = "SAS Enclosure Device Status Change";
625 break;
626 case MPI2_EVENT_IR_VOLUME:
627 desc = "IR Volume";
628 break;
629 case MPI2_EVENT_IR_PHYSICAL_DISK:
630 desc = "IR Physical Disk";
631 break;
632 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
633 desc = "IR Configuration Change List";
634 break;
635 case MPI2_EVENT_LOG_ENTRY_ADDED:
636 desc = "Log Entry Added";
637 break;
2d8ce8c9
SR		 638 case MPI2_EVENT_TEMP_THRESHOLD:
639 desc = "Temperature Threshold";
640 break;
f92363d1
SR		 641 }
642
643 if (!desc)
644 return;
645
646 pr_info(MPT3SAS_FMT "%s\n", ioc->name, desc);
647}
f92363d1
SR		 648
649/**
650 * _base_sas_log_info - verbose translation of firmware log info
651 * @ioc: per adapter object
652 * @log_info: log info
653 *
654 * Return nothing.
655 */
656static void
657_base_sas_log_info(struct MPT3SAS_ADAPTER *ioc , u32 log_info)
658{
659 union loginfo_type {
660 u32 loginfo;
661 struct {
662 u32 subcode:16;
663 u32 code:8;
664 u32 originator:4;
665 u32 bus_type:4;
666 } dw;
667 };
668 union loginfo_type sas_loginfo;
669 char *originator_str = NULL;
670
671 sas_loginfo.loginfo = log_info;
672 if (sas_loginfo.dw.bus_type != 3 /*SAS*/)
673 return;
674
675 /* each nexus loss loginfo */
676 if (log_info == 0x31170000)
677 return;
678
679 /* eat the loginfos associated with task aborts */
680 if (ioc->ignore_loginfos && (log_info == 0x30050000 || log_info ==
681 0x31140000 || log_info == 0x31130000))
682 return;
683
684 switch (sas_loginfo.dw.originator) {
685 case 0:
686 originator_str = "IOP";
687 break;
688 case 1:
689 originator_str = "PL";
690 break;
691 case 2:
692 originator_str = "IR";
693 break;
694 }
695
696 pr_warn(MPT3SAS_FMT
697 "log_info(0x%08x): originator(%s), code(0x%02x), sub_code(0x%04x)\n",
698 ioc->name, log_info,
699 originator_str, sas_loginfo.dw.code,
700 sas_loginfo.dw.subcode);
701}
702
703/**
704 * _base_display_reply_info -
705 * @ioc: per adapter object
706 * @smid: system request message index
707 * @msix_index: MSIX table index supplied by the OS
708 * @reply: reply message frame(lower 32bit addr)
709 *
710 * Return nothing.
711 */
712static void
713_base_display_reply_info(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
714 u32 reply)
715{
716 MPI2DefaultReply_t *mpi_reply;
717 u16 ioc_status;
718 u32 loginfo = 0;
719
720 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
721 if (unlikely(!mpi_reply)) {
722 pr_err(MPT3SAS_FMT "mpi_reply not valid at %s:%d/%s()!\n",
723 ioc->name, __FILE__, __LINE__, __func__);
724 return;
725 }
726 ioc_status = le16_to_cpu(mpi_reply->IOCStatus);
af009411 727
f92363d1
SR		 728 if ((ioc_status & MPI2_IOCSTATUS_MASK) &&
729 (ioc->logging_level & MPT_DEBUG_REPLY)) {
730 _base_sas_ioc_info(ioc , mpi_reply,
731 mpt3sas_base_get_msg_frame(ioc, smid));
732 }
af009411 733
f92363d1
SR		 734 if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
735 loginfo = le32_to_cpu(mpi_reply->IOCLogInfo);
736 _base_sas_log_info(ioc, loginfo);
737 }
738
739 if (ioc_status || loginfo) {
740 ioc_status &= MPI2_IOCSTATUS_MASK;
741 mpt3sas_trigger_mpi(ioc, ioc_status, loginfo);
742 }
743}
744
745/**
746 * mpt3sas_base_done - base internal command completion routine
747 * @ioc: per adapter object
748 * @smid: system request message index
749 * @msix_index: MSIX table index supplied by the OS
750 * @reply: reply message frame(lower 32bit addr)
751 *
752 * Return 1 meaning mf should be freed from _base_interrupt
753 * 0 means the mf is freed from this function.
754 */
755u8
756mpt3sas_base_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
757 u32 reply)
758{
759 MPI2DefaultReply_t *mpi_reply;
760
761 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
762 if (mpi_reply && mpi_reply->Function == MPI2_FUNCTION_EVENT_ACK)
763 return 1;
764
765 if (ioc->base_cmds.status == MPT3_CMD_NOT_USED)
766 return 1;
767
768 ioc->base_cmds.status |= MPT3_CMD_COMPLETE;
769 if (mpi_reply) {
770 ioc->base_cmds.status |= MPT3_CMD_REPLY_VALID;
771 memcpy(ioc->base_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
772 }
773 ioc->base_cmds.status &= ~MPT3_CMD_PENDING;
774
775 complete(&ioc->base_cmds.done);
776 return 1;
777}
778
779/**
780 * _base_async_event - main callback handler for firmware asyn events
781 * @ioc: per adapter object
782 * @msix_index: MSIX table index supplied by the OS
783 * @reply: reply message frame(lower 32bit addr)
784 *
785 * Return 1 meaning mf should be freed from _base_interrupt
786 * 0 means the mf is freed from this function.
787 */
788static u8
789_base_async_event(struct MPT3SAS_ADAPTER *ioc, u8 msix_index, u32 reply)
790{
791 Mpi2EventNotificationReply_t *mpi_reply;
792 Mpi2EventAckRequest_t *ack_request;
793 u16 smid;
794
795 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
796 if (!mpi_reply)
797 return 1;
798 if (mpi_reply->Function != MPI2_FUNCTION_EVENT_NOTIFICATION)
799 return 1;
af009411 800
f92363d1 801 _base_display_event_data(ioc, mpi_reply);
af009411 802
f92363d1
SR		 803 if (!(mpi_reply->AckRequired & MPI2_EVENT_NOTIFICATION_ACK_REQUIRED))
804 goto out;
805 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
806 if (!smid) {
807 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
808 ioc->name, __func__);
809 goto out;
810 }
811
812 ack_request = mpt3sas_base_get_msg_frame(ioc, smid);
813 memset(ack_request, 0, sizeof(Mpi2EventAckRequest_t));
814 ack_request->Function = MPI2_FUNCTION_EVENT_ACK;
815 ack_request->Event = mpi_reply->Event;
816 ack_request->EventContext = mpi_reply->EventContext;
817 ack_request->VF_ID = 0; /* TODO */
818 ack_request->VP_ID = 0;
819 mpt3sas_base_put_smid_default(ioc, smid);
820
821 out:
822
823 /* scsih callback handler */
824 mpt3sas_scsih_event_callback(ioc, msix_index, reply);
825
826 /* ctl callback handler */
827 mpt3sas_ctl_event_callback(ioc, msix_index, reply);
828
829 return 1;
830}
831
832/**
833 * _base_get_cb_idx - obtain the callback index
834 * @ioc: per adapter object
835 * @smid: system request message index
836 *
837 * Return callback index.
838 */
839static u8
840_base_get_cb_idx(struct MPT3SAS_ADAPTER *ioc, u16 smid)
841{
842 int i;
843 u8 cb_idx;
844
845 if (smid < ioc->hi_priority_smid) {
846 i = smid - 1;
847 cb_idx = ioc->scsi_lookup[i].cb_idx;
848 } else if (smid < ioc->internal_smid) {
849 i = smid - ioc->hi_priority_smid;
850 cb_idx = ioc->hpr_lookup[i].cb_idx;
851 } else if (smid <= ioc->hba_queue_depth) {
852 i = smid - ioc->internal_smid;
853 cb_idx = ioc->internal_lookup[i].cb_idx;
854 } else
855 cb_idx = 0xFF;
856 return cb_idx;
857}
858
859/**
860 * _base_mask_interrupts - disable interrupts
861 * @ioc: per adapter object
862 *
863 * Disabling ResetIRQ, Reply and Doorbell Interrupts
864 *
865 * Return nothing.
866 */
867static void
868_base_mask_interrupts(struct MPT3SAS_ADAPTER *ioc)
869{
870 u32 him_register;
871
872 ioc->mask_interrupts = 1;
873 him_register = readl(&ioc->chip->HostInterruptMask);
874 him_register |= MPI2_HIM_DIM + MPI2_HIM_RIM + MPI2_HIM_RESET_IRQ_MASK;
875 writel(him_register, &ioc->chip->HostInterruptMask);
876 readl(&ioc->chip->HostInterruptMask);
877}
878
879/**
880 * _base_unmask_interrupts - enable interrupts
881 * @ioc: per adapter object
882 *
883 * Enabling only Reply Interrupts
884 *
885 * Return nothing.
886 */
887static void
888_base_unmask_interrupts(struct MPT3SAS_ADAPTER *ioc)
889{
890 u32 him_register;
891
892 him_register = readl(&ioc->chip->HostInterruptMask);
893 him_register &= ~MPI2_HIM_RIM;
894 writel(him_register, &ioc->chip->HostInterruptMask);
895 ioc->mask_interrupts = 0;
896}
897
898union reply_descriptor {
899 u64 word;
900 struct {
901 u32 low;
902 u32 high;
903 } u;
904};
905
906/**
907 * _base_interrupt - MPT adapter (IOC) specific interrupt handler.
908 * @irq: irq number (not used)
909 * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure
910 * @r: pt_regs pointer (not used)
911 *
912 * Return IRQ_HANDLE if processed, else IRQ_NONE.
913 */
914static irqreturn_t
915_base_interrupt(int irq, void *bus_id)
916{
917 struct adapter_reply_queue *reply_q = bus_id;
918 union reply_descriptor rd;
919 u32 completed_cmds;
920 u8 request_desript_type;
921 u16 smid;
922 u8 cb_idx;
923 u32 reply;
924 u8 msix_index = reply_q->msix_index;
925 struct MPT3SAS_ADAPTER *ioc = reply_q->ioc;
926 Mpi2ReplyDescriptorsUnion_t *rpf;
927 u8 rc;
928
929 if (ioc->mask_interrupts)
930 return IRQ_NONE;
931
932 if (!atomic_add_unless(&reply_q->busy, 1, 1))
933 return IRQ_NONE;
934
935 rpf = &reply_q->reply_post_free[reply_q->reply_post_host_index];
936 request_desript_type = rpf->Default.ReplyFlags
937 & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
938 if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) {
939 atomic_dec(&reply_q->busy);
940 return IRQ_NONE;
941 }
942
943 completed_cmds = 0;
944 cb_idx = 0xFF;
945 do {
946 rd.word = le64_to_cpu(rpf->Words);
947 if (rd.u.low == UINT_MAX || rd.u.high == UINT_MAX)
948 goto out;
949 reply = 0;
950 smid = le16_to_cpu(rpf->Default.DescriptorTypeDependent1);
951 if (request_desript_type ==
952 MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS ||
953 request_desript_type ==
954 MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS) {
955 cb_idx = _base_get_cb_idx(ioc, smid);
956 if ((likely(cb_idx < MPT_MAX_CALLBACKS)) &&
957 (likely(mpt_callbacks[cb_idx] != NULL))) {
958 rc = mpt_callbacks[cb_idx](ioc, smid,
959 msix_index, 0);
960 if (rc)
961 mpt3sas_base_free_smid(ioc, smid);
962 }
963 } else if (request_desript_type ==
964 MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) {
965 reply = le32_to_cpu(
966 rpf->AddressReply.ReplyFrameAddress);
967 if (reply > ioc->reply_dma_max_address ||
968 reply < ioc->reply_dma_min_address)
969 reply = 0;
970 if (smid) {
971 cb_idx = _base_get_cb_idx(ioc, smid);
972 if ((likely(cb_idx < MPT_MAX_CALLBACKS)) &&
973 (likely(mpt_callbacks[cb_idx] != NULL))) {
974 rc = mpt_callbacks[cb_idx](ioc, smid,
975 msix_index, reply);
976 if (reply)
977 _base_display_reply_info(ioc,
978 smid, msix_index, reply);
979 if (rc)
980 mpt3sas_base_free_smid(ioc,
981 smid);
982 }
983 } else {
984 _base_async_event(ioc, msix_index, reply);
985 }
986
987 /* reply free queue handling */
988 if (reply) {
989 ioc->reply_free_host_index =
990 (ioc->reply_free_host_index ==
991 (ioc->reply_free_queue_depth - 1)) ?
992 0 : ioc->reply_free_host_index + 1;
993 ioc->reply_free[ioc->reply_free_host_index] =
994 cpu_to_le32(reply);
995 wmb();
996 writel(ioc->reply_free_host_index,
997 &ioc->chip->ReplyFreeHostIndex);
998 }
999 }
1000
1001 rpf->Words = cpu_to_le64(ULLONG_MAX);
1002 reply_q->reply_post_host_index =
1003 (reply_q->reply_post_host_index ==
1004 (ioc->reply_post_queue_depth - 1)) ? 0 :
1005 reply_q->reply_post_host_index + 1;
1006 request_desript_type =
1007 reply_q->reply_post_free[reply_q->reply_post_host_index].
1008 Default.ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
1009 completed_cmds++;
1010 if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED)
1011 goto out;
1012 if (!reply_q->reply_post_host_index)
1013 rpf = reply_q->reply_post_free;
1014 else
1015 rpf++;
1016 } while (1);
1017
1018 out:
1019
1020 if (!completed_cmds) {
1021 atomic_dec(&reply_q->busy);
1022 return IRQ_NONE;
1023 }
1024
1025 wmb();
fb77bb53
SR		 1026
1027 /* Update Reply Post Host Index.
1028 * For those HBA's which support combined reply queue feature
1029 * 1. Get the correct Supplemental Reply Post Host Index Register.
1030 * i.e. (msix_index / 8)th entry from Supplemental Reply Post Host
1031 * Index Register address bank i.e replyPostRegisterIndex[],
1032 * 2. Then update this register with new reply host index value
1033 * in ReplyPostIndex field and the MSIxIndex field with
1034 * msix_index value reduced to a value between 0 and 7,
1035 * using a modulo 8 operation. Since each Supplemental Reply Post
1036 * Host Index Register supports 8 MSI-X vectors.
1037 *
1038 * For other HBA's just update the Reply Post Host Index register with
1039 * new reply host index value in ReplyPostIndex Field and msix_index
1040 * value in MSIxIndex field.
1041 */
1042 if (ioc->msix96_vector)
1043 writel(reply_q->reply_post_host_index | ((msix_index & 7) <<
1044 MPI2_RPHI_MSIX_INDEX_SHIFT),
1045 ioc->replyPostRegisterIndex[msix_index/8]);
1046 else
1047 writel(reply_q->reply_post_host_index | (msix_index <<
1048 MPI2_RPHI_MSIX_INDEX_SHIFT),
1049 &ioc->chip->ReplyPostHostIndex);
f92363d1
SR		 1050 atomic_dec(&reply_q->busy);
1051 return IRQ_HANDLED;
1052}
1053
1054/**
1055 * _base_is_controller_msix_enabled - is controller support muli-reply queues
1056 * @ioc: per adapter object
1057 *
1058 */
1059static inline int
1060_base_is_controller_msix_enabled(struct MPT3SAS_ADAPTER *ioc)
1061{
1062 return (ioc->facts.IOCCapabilities &
1063 MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX) && ioc->msix_enable;
1064}
1065
1066/**
1067 * mpt3sas_base_flush_reply_queues - flushing the MSIX reply queues
1068 * @ioc: per adapter object
1069 * Context: ISR conext
1070 *
1071 * Called when a Task Management request has completed. We want
1072 * to flush the other reply queues so all the outstanding IO has been
1073 * completed back to OS before we process the TM completetion.
1074 *
1075 * Return nothing.
1076 */
1077void
1078mpt3sas_base_flush_reply_queues(struct MPT3SAS_ADAPTER *ioc)
1079{
1080 struct adapter_reply_queue *reply_q;
1081
1082 /* If MSIX capability is turned off
1083 * then multi-queues are not enabled
1084 */
1085 if (!_base_is_controller_msix_enabled(ioc))
1086 return;
1087
1088 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
1089 if (ioc->shost_recovery)
1090 return;
1091 /* TMs are on msix_index == 0 */
1092 if (reply_q->msix_index == 0)
1093 continue;
1094 _base_interrupt(reply_q->vector, (void *)reply_q);
1095 }
1096}
1097
1098/**
1099 * mpt3sas_base_release_callback_handler - clear interrupt callback handler
1100 * @cb_idx: callback index
1101 *
1102 * Return nothing.
1103 */
1104void
1105mpt3sas_base_release_callback_handler(u8 cb_idx)
1106{
1107 mpt_callbacks[cb_idx] = NULL;
1108}
1109
1110/**
1111 * mpt3sas_base_register_callback_handler - obtain index for the interrupt callback handler
1112 * @cb_func: callback function
1113 *
1114 * Returns cb_func.
1115 */
1116u8
1117mpt3sas_base_register_callback_handler(MPT_CALLBACK cb_func)
1118{
1119 u8 cb_idx;
1120
1121 for (cb_idx = MPT_MAX_CALLBACKS-1; cb_idx; cb_idx--)
1122 if (mpt_callbacks[cb_idx] == NULL)
1123 break;
1124
1125 mpt_callbacks[cb_idx] = cb_func;
1126 return cb_idx;
1127}
1128
1129/**
1130 * mpt3sas_base_initialize_callback_handler - initialize the interrupt callback handler
1131 *
1132 * Return nothing.
1133 */
1134void
1135mpt3sas_base_initialize_callback_handler(void)
1136{
1137 u8 cb_idx;
1138
1139 for (cb_idx = 0; cb_idx < MPT_MAX_CALLBACKS; cb_idx++)
1140 mpt3sas_base_release_callback_handler(cb_idx);
1141}
1142
1143
1144/**
1145 * _base_build_zero_len_sge - build zero length sg entry
1146 * @ioc: per adapter object
1147 * @paddr: virtual address for SGE
1148 *
1149 * Create a zero length scatter gather entry to insure the IOCs hardware has
1150 * something to use if the target device goes brain dead and tries
1151 * to send data even when none is asked for.
1152 *
1153 * Return nothing.
1154 */
1155static void
1156_base_build_zero_len_sge(struct MPT3SAS_ADAPTER *ioc, void *paddr)
1157{
1158 u32 flags_length = (u32)((MPI2_SGE_FLAGS_LAST_ELEMENT |
1159 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST |
1160 MPI2_SGE_FLAGS_SIMPLE_ELEMENT) <<
1161 MPI2_SGE_FLAGS_SHIFT);
1162 ioc->base_add_sg_single(paddr, flags_length, -1);
1163}
1164
1165/**
1166 * _base_add_sg_single_32 - Place a simple 32 bit SGE at address pAddr.
1167 * @paddr: virtual address for SGE
1168 * @flags_length: SGE flags and data transfer length
1169 * @dma_addr: Physical address
1170 *
1171 * Return nothing.
1172 */
1173static void
1174_base_add_sg_single_32(void *paddr, u32 flags_length, dma_addr_t dma_addr)
1175{
1176 Mpi2SGESimple32_t *sgel = paddr;
1177
1178 flags_length |= (MPI2_SGE_FLAGS_32_BIT_ADDRESSING |
1179 MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
1180 sgel->FlagsLength = cpu_to_le32(flags_length);
1181 sgel->Address = cpu_to_le32(dma_addr);
1182}
1183
1184
1185/**
1186 * _base_add_sg_single_64 - Place a simple 64 bit SGE at address pAddr.
1187 * @paddr: virtual address for SGE
1188 * @flags_length: SGE flags and data transfer length
1189 * @dma_addr: Physical address
1190 *
1191 * Return nothing.
1192 */
1193static void
1194_base_add_sg_single_64(void *paddr, u32 flags_length, dma_addr_t dma_addr)
1195{
1196 Mpi2SGESimple64_t *sgel = paddr;
1197
1198 flags_length |= (MPI2_SGE_FLAGS_64_BIT_ADDRESSING |
1199 MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
1200 sgel->FlagsLength = cpu_to_le32(flags_length);
1201 sgel->Address = cpu_to_le64(dma_addr);
1202}
1203
1204/**
1205 * _base_get_chain_buffer_tracker - obtain chain tracker
1206 * @ioc: per adapter object
1207 * @smid: smid associated to an IO request
1208 *
1209 * Returns chain tracker(from ioc->free_chain_list)
1210 */
1211static struct chain_tracker *
1212_base_get_chain_buffer_tracker(struct MPT3SAS_ADAPTER *ioc, u16 smid)
1213{
1214 struct chain_tracker *chain_req;
1215 unsigned long flags;
1216
1217 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
1218 if (list_empty(&ioc->free_chain_list)) {
1219 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
1220 dfailprintk(ioc, pr_warn(MPT3SAS_FMT
1221 "chain buffers not available\n", ioc->name));
1222 return NULL;
1223 }
1224 chain_req = list_entry(ioc->free_chain_list.next,
1225 struct chain_tracker, tracker_list);
1226 list_del_init(&chain_req->tracker_list);
1227 list_add_tail(&chain_req->tracker_list,
1228 &ioc->scsi_lookup[smid - 1].chain_list);
1229 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
1230 return chain_req;
1231}
1232
1233
1234/**
1235 * _base_build_sg - build generic sg
1236 * @ioc: per adapter object
1237 * @psge: virtual address for SGE
1238 * @data_out_dma: physical address for WRITES
1239 * @data_out_sz: data xfer size for WRITES
1240 * @data_in_dma: physical address for READS
1241 * @data_in_sz: data xfer size for READS
1242 *
1243 * Return nothing.
1244 */
1245static void
1246_base_build_sg(struct MPT3SAS_ADAPTER *ioc, void *psge,
1247 dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
1248 size_t data_in_sz)
1249{
1250 u32 sgl_flags;
1251
1252 if (!data_out_sz && !data_in_sz) {
1253 _base_build_zero_len_sge(ioc, psge);
1254 return;
1255 }
1256
1257 if (data_out_sz && data_in_sz) {
1258 /* WRITE sgel first */
1259 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1260 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_HOST_TO_IOC);
1261 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1262 ioc->base_add_sg_single(psge, sgl_flags |
1263 data_out_sz, data_out_dma);
1264
1265 /* incr sgel */
1266 psge += ioc->sge_size;
1267
1268 /* READ sgel last */
1269 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1270 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
1271 MPI2_SGE_FLAGS_END_OF_LIST);
1272 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1273 ioc->base_add_sg_single(psge, sgl_flags |
1274 data_in_sz, data_in_dma);
1275 } else if (data_out_sz) /* WRITE */ {
1276 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1277 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
1278 MPI2_SGE_FLAGS_END_OF_LIST | MPI2_SGE_FLAGS_HOST_TO_IOC);
1279 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1280 ioc->base_add_sg_single(psge, sgl_flags |
1281 data_out_sz, data_out_dma);
1282 } else if (data_in_sz) /* READ */ {
1283 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1284 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
1285 MPI2_SGE_FLAGS_END_OF_LIST);
1286 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1287 ioc->base_add_sg_single(psge, sgl_flags |
1288 data_in_sz, data_in_dma);
1289 }
1290}
1291
1292/* IEEE format sgls */
1293
1294/**
1295 * _base_add_sg_single_ieee - add sg element for IEEE format
1296 * @paddr: virtual address for SGE
1297 * @flags: SGE flags
1298 * @chain_offset: number of 128 byte elements from start of segment
1299 * @length: data transfer length
1300 * @dma_addr: Physical address
1301 *
1302 * Return nothing.
1303 */
1304static void
1305_base_add_sg_single_ieee(void *paddr, u8 flags, u8 chain_offset, u32 length,
1306 dma_addr_t dma_addr)
1307{
1308 Mpi25IeeeSgeChain64_t *sgel = paddr;
1309
1310 sgel->Flags = flags;
1311 sgel->NextChainOffset = chain_offset;
1312 sgel->Length = cpu_to_le32(length);
1313 sgel->Address = cpu_to_le64(dma_addr);
1314}
1315
1316/**
1317 * _base_build_zero_len_sge_ieee - build zero length sg entry for IEEE format
1318 * @ioc: per adapter object
1319 * @paddr: virtual address for SGE
1320 *
1321 * Create a zero length scatter gather entry to insure the IOCs hardware has
1322 * something to use if the target device goes brain dead and tries
1323 * to send data even when none is asked for.
1324 *
1325 * Return nothing.
1326 */
1327static void
1328_base_build_zero_len_sge_ieee(struct MPT3SAS_ADAPTER *ioc, void *paddr)
1329{
1330 u8 sgl_flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1331 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR |
1332 MPI25_IEEE_SGE_FLAGS_END_OF_LIST);
1333 _base_add_sg_single_ieee(paddr, sgl_flags, 0, 0, -1);
1334}
1335
471ef9d4
SR		 1336/**
1337 * _base_build_sg_scmd - main sg creation routine
1338 * @ioc: per adapter object
1339 * @scmd: scsi command
1340 * @smid: system request message index
1341 * Context: none.
1342 *
1343 * The main routine that builds scatter gather table from a given
1344 * scsi request sent via the .queuecommand main handler.
1345 *
1346 * Returns 0 success, anything else error
1347 */
1348static int
1349_base_build_sg_scmd(struct MPT3SAS_ADAPTER *ioc,
1350 struct scsi_cmnd *scmd, u16 smid)
1351{
1352 Mpi2SCSIIORequest_t *mpi_request;
1353 dma_addr_t chain_dma;
1354 struct scatterlist *sg_scmd;
1355 void *sg_local, *chain;
1356 u32 chain_offset;
1357 u32 chain_length;
1358 u32 chain_flags;
1359 int sges_left;
1360 u32 sges_in_segment;
1361 u32 sgl_flags;
1362 u32 sgl_flags_last_element;
1363 u32 sgl_flags_end_buffer;
1364 struct chain_tracker *chain_req;
1365
1366 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
1367
1368 /* init scatter gather flags */
1369 sgl_flags = MPI2_SGE_FLAGS_SIMPLE_ELEMENT;
1370 if (scmd->sc_data_direction == DMA_TO_DEVICE)
1371 sgl_flags |= MPI2_SGE_FLAGS_HOST_TO_IOC;
1372 sgl_flags_last_element = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT)
1373 << MPI2_SGE_FLAGS_SHIFT;
1374 sgl_flags_end_buffer = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT |
1375 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST)
1376 << MPI2_SGE_FLAGS_SHIFT;
1377 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1378
1379 sg_scmd = scsi_sglist(scmd);
1380 sges_left = scsi_dma_map(scmd);
1381 if (sges_left < 0) {
1382 sdev_printk(KERN_ERR, scmd->device,
1383 "pci_map_sg failed: request for %d bytes!\n",
1384 scsi_bufflen(scmd));
1385 return -ENOMEM;
1386 }
1387
1388 sg_local = &mpi_request->SGL;
1389 sges_in_segment = ioc->max_sges_in_main_message;
1390 if (sges_left <= sges_in_segment)
1391 goto fill_in_last_segment;
1392
1393 mpi_request->ChainOffset = (offsetof(Mpi2SCSIIORequest_t, SGL) +
1394 (sges_in_segment * ioc->sge_size))/4;
1395
1396 /* fill in main message segment when there is a chain following */
1397 while (sges_in_segment) {
1398 if (sges_in_segment == 1)
1399 ioc->base_add_sg_single(sg_local,
1400 sgl_flags_last_element | sg_dma_len(sg_scmd),
1401 sg_dma_address(sg_scmd));
1402 else
1403 ioc->base_add_sg_single(sg_local, sgl_flags |
1404 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1405 sg_scmd = sg_next(sg_scmd);
1406 sg_local += ioc->sge_size;
1407 sges_left--;
1408 sges_in_segment--;
1409 }
1410
1411 /* initializing the chain flags and pointers */
1412 chain_flags = MPI2_SGE_FLAGS_CHAIN_ELEMENT << MPI2_SGE_FLAGS_SHIFT;
1413 chain_req = _base_get_chain_buffer_tracker(ioc, smid);
1414 if (!chain_req)
1415 return -1;
1416 chain = chain_req->chain_buffer;
1417 chain_dma = chain_req->chain_buffer_dma;
1418 do {
1419 sges_in_segment = (sges_left <=
1420 ioc->max_sges_in_chain_message) ? sges_left :
1421 ioc->max_sges_in_chain_message;
1422 chain_offset = (sges_left == sges_in_segment) ?
1423 0 : (sges_in_segment * ioc->sge_size)/4;
1424 chain_length = sges_in_segment * ioc->sge_size;
1425 if (chain_offset) {
1426 chain_offset = chain_offset <<
1427 MPI2_SGE_CHAIN_OFFSET_SHIFT;
1428 chain_length += ioc->sge_size;
1429 }
1430 ioc->base_add_sg_single(sg_local, chain_flags | chain_offset |
1431 chain_length, chain_dma);
1432 sg_local = chain;
1433 if (!chain_offset)
1434 goto fill_in_last_segment;
1435
1436 /* fill in chain segments */
1437 while (sges_in_segment) {
1438 if (sges_in_segment == 1)
1439 ioc->base_add_sg_single(sg_local,
1440 sgl_flags_last_element |
1441 sg_dma_len(sg_scmd),
1442 sg_dma_address(sg_scmd));
1443 else
1444 ioc->base_add_sg_single(sg_local, sgl_flags |
1445 sg_dma_len(sg_scmd),
1446 sg_dma_address(sg_scmd));
1447 sg_scmd = sg_next(sg_scmd);
1448 sg_local += ioc->sge_size;
1449 sges_left--;
1450 sges_in_segment--;
1451 }
1452
1453 chain_req = _base_get_chain_buffer_tracker(ioc, smid);
1454 if (!chain_req)
1455 return -1;
1456 chain = chain_req->chain_buffer;
1457 chain_dma = chain_req->chain_buffer_dma;
1458 } while (1);
1459
1460
1461 fill_in_last_segment:
1462
1463 /* fill the last segment */
1464 while (sges_left) {
1465 if (sges_left == 1)
1466 ioc->base_add_sg_single(sg_local, sgl_flags_end_buffer |
1467 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1468 else
1469 ioc->base_add_sg_single(sg_local, sgl_flags |
1470 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1471 sg_scmd = sg_next(sg_scmd);
1472 sg_local += ioc->sge_size;
1473 sges_left--;
1474 }
1475
1476 return 0;
1477}
1478
f92363d1
SR		 1479/**
1480 * _base_build_sg_scmd_ieee - main sg creation routine for IEEE format
1481 * @ioc: per adapter object
1482 * @scmd: scsi command
1483 * @smid: system request message index
1484 * Context: none.
1485 *
1486 * The main routine that builds scatter gather table from a given
1487 * scsi request sent via the .queuecommand main handler.
1488 *
1489 * Returns 0 success, anything else error
1490 */
1491static int
1492_base_build_sg_scmd_ieee(struct MPT3SAS_ADAPTER *ioc,
1493 struct scsi_cmnd *scmd, u16 smid)
1494{
1495 Mpi2SCSIIORequest_t *mpi_request;
1496 dma_addr_t chain_dma;
1497 struct scatterlist *sg_scmd;
1498 void *sg_local, *chain;
1499 u32 chain_offset;
1500 u32 chain_length;
f92363d1
SR		 1501 int sges_left;
1502 u32 sges_in_segment;
1503 u8 simple_sgl_flags;
1504 u8 simple_sgl_flags_last;
1505 u8 chain_sgl_flags;
1506 struct chain_tracker *chain_req;
1507
1508 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
1509
1510 /* init scatter gather flags */
1511 simple_sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1512 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1513 simple_sgl_flags_last = simple_sgl_flags |
1514 MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
1515 chain_sgl_flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
1516 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1517
1518 sg_scmd = scsi_sglist(scmd);
1519 sges_left = scsi_dma_map(scmd);
62f5c74c 1520 if (sges_left < 0) {
f92363d1
SR		 1521 sdev_printk(KERN_ERR, scmd->device,
1522 "pci_map_sg failed: request for %d bytes!\n",
1523 scsi_bufflen(scmd));
1524 return -ENOMEM;
1525 }
1526
1527 sg_local = &mpi_request->SGL;
1528 sges_in_segment = (ioc->request_sz -
1529 offsetof(Mpi2SCSIIORequest_t, SGL))/ioc->sge_size_ieee;
1530 if (sges_left <= sges_in_segment)
1531 goto fill_in_last_segment;
1532
1533 mpi_request->ChainOffset = (sges_in_segment - 1 /* chain element */) +
1534 (offsetof(Mpi2SCSIIORequest_t, SGL)/ioc->sge_size_ieee);
1535
1536 /* fill in main message segment when there is a chain following */
1537 while (sges_in_segment > 1) {
1538 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
1539 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1540 sg_scmd = sg_next(sg_scmd);
1541 sg_local += ioc->sge_size_ieee;
1542 sges_left--;
1543 sges_in_segment--;
1544 }
1545
25ef16d0 1546 /* initializing the pointers */
f92363d1
SR		 1547 chain_req = _base_get_chain_buffer_tracker(ioc, smid);
1548 if (!chain_req)
1549 return -1;
1550 chain = chain_req->chain_buffer;
1551 chain_dma = chain_req->chain_buffer_dma;
1552 do {
1553 sges_in_segment = (sges_left <=
1554 ioc->max_sges_in_chain_message) ? sges_left :
1555 ioc->max_sges_in_chain_message;
1556 chain_offset = (sges_left == sges_in_segment) ?
1557 0 : sges_in_segment;
1558 chain_length = sges_in_segment * ioc->sge_size_ieee;
1559 if (chain_offset)
1560 chain_length += ioc->sge_size_ieee;
1561 _base_add_sg_single_ieee(sg_local, chain_sgl_flags,
1562 chain_offset, chain_length, chain_dma);
1563
1564 sg_local = chain;
1565 if (!chain_offset)
1566 goto fill_in_last_segment;
1567
1568 /* fill in chain segments */
1569 while (sges_in_segment) {
1570 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
1571 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1572 sg_scmd = sg_next(sg_scmd);
1573 sg_local += ioc->sge_size_ieee;
1574 sges_left--;
1575 sges_in_segment--;
1576 }
1577
1578 chain_req = _base_get_chain_buffer_tracker(ioc, smid);
1579 if (!chain_req)
1580 return -1;
1581 chain = chain_req->chain_buffer;
1582 chain_dma = chain_req->chain_buffer_dma;
1583 } while (1);
1584
1585
1586 fill_in_last_segment:
1587
1588 /* fill the last segment */
62f5c74c 1589 while (sges_left > 0) {
f92363d1
SR		 1590 if (sges_left == 1)
1591 _base_add_sg_single_ieee(sg_local,
1592 simple_sgl_flags_last, 0, sg_dma_len(sg_scmd),
1593 sg_dma_address(sg_scmd));
1594 else
1595 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
1596 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1597 sg_scmd = sg_next(sg_scmd);
1598 sg_local += ioc->sge_size_ieee;
1599 sges_left--;
1600 }
1601
1602 return 0;
1603}
1604
1605/**
1606 * _base_build_sg_ieee - build generic sg for IEEE format
1607 * @ioc: per adapter object
1608 * @psge: virtual address for SGE
1609 * @data_out_dma: physical address for WRITES
1610 * @data_out_sz: data xfer size for WRITES
1611 * @data_in_dma: physical address for READS
1612 * @data_in_sz: data xfer size for READS
1613 *
1614 * Return nothing.
1615 */
1616static void
1617_base_build_sg_ieee(struct MPT3SAS_ADAPTER *ioc, void *psge,
1618 dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
1619 size_t data_in_sz)
1620{
1621 u8 sgl_flags;
1622
1623 if (!data_out_sz && !data_in_sz) {
1624 _base_build_zero_len_sge_ieee(ioc, psge);
1625 return;
1626 }
1627
1628 if (data_out_sz && data_in_sz) {
1629 /* WRITE sgel first */
1630 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1631 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1632 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz,
1633 data_out_dma);
1634
1635 /* incr sgel */
1636 psge += ioc->sge_size_ieee;
1637
1638 /* READ sgel last */
1639 sgl_flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
1640 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz,
1641 data_in_dma);
1642 } else if (data_out_sz) /* WRITE */ {
1643 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1644 MPI25_IEEE_SGE_FLAGS_END_OF_LIST |
1645 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1646 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz,
1647 data_out_dma);
1648 } else if (data_in_sz) /* READ */ {
1649 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1650 MPI25_IEEE_SGE_FLAGS_END_OF_LIST |
1651 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1652 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz,
1653 data_in_dma);
1654 }
1655}
1656
1657#define convert_to_kb(x) ((x) << (PAGE_SHIFT - 10))
1658
1659/**
1660 * _base_config_dma_addressing - set dma addressing
1661 * @ioc: per adapter object
1662 * @pdev: PCI device struct
1663 *
1664 * Returns 0 for success, non-zero for failure.
1665 */
1666static int
1667_base_config_dma_addressing(struct MPT3SAS_ADAPTER *ioc, struct pci_dev *pdev)
1668{
1669 struct sysinfo s;
9b05c91a
SR		 1670 u64 consistent_dma_mask;
1671
1672 if (ioc->dma_mask)
1673 consistent_dma_mask = DMA_BIT_MASK(64);
1674 else
1675 consistent_dma_mask = DMA_BIT_MASK(32);
f92363d1
SR		 1676
1677 if (sizeof(dma_addr_t) > 4) {
1678 const uint64_t required_mask =
1679 dma_get_required_mask(&pdev->dev);
1680 if ((required_mask > DMA_BIT_MASK(32)) &&
1681 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
9b05c91a 1682 !pci_set_consistent_dma_mask(pdev, consistent_dma_mask)) {
f92363d1
SR		 1683 ioc->base_add_sg_single = &_base_add_sg_single_64;
1684 ioc->sge_size = sizeof(Mpi2SGESimple64_t);
9b05c91a 1685 ioc->dma_mask = 64;
f92363d1
SR		 1686 goto out;
1687 }
1688 }
1689
1690 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))
1691 && !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
1692 ioc->base_add_sg_single = &_base_add_sg_single_32;
1693 ioc->sge_size = sizeof(Mpi2SGESimple32_t);
9b05c91a 1694 ioc->dma_mask = 32;
f92363d1
SR		 1695 } else
1696 return -ENODEV;
1697
1698 out:
1699 si_meminfo(&s);
1700 pr_info(MPT3SAS_FMT
9b05c91a
SR		 1701 "%d BIT PCI BUS DMA ADDRESSING SUPPORTED, total mem (%ld kB)\n",
1702 ioc->name, ioc->dma_mask, convert_to_kb(s.totalram));
1703
1704 return 0;
1705}
f92363d1 1706
9b05c91a
SR		 1707static int
1708_base_change_consistent_dma_mask(struct MPT3SAS_ADAPTER *ioc,
1709 struct pci_dev *pdev)
1710{
1711 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
1712 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
1713 return -ENODEV;
1714 }
f92363d1
SR		 1715 return 0;
1716}
1717
1718/**
1719 * _base_check_enable_msix - checks MSIX capabable.
1720 * @ioc: per adapter object
1721 *
1722 * Check to see if card is capable of MSIX, and set number
1723 * of available msix vectors
1724 */
1725static int
1726_base_check_enable_msix(struct MPT3SAS_ADAPTER *ioc)
1727{
1728 int base;
1729 u16 message_control;
1730
42081173
SR		 1731 /* Check whether controller SAS2008 B0 controller,
1732 * if it is SAS2008 B0 controller use IO-APIC instead of MSIX
1733 */
1734 if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 &&
1735 ioc->pdev->revision == SAS2_PCI_DEVICE_B0_REVISION) {
1736 return -EINVAL;
1737 }
1738
f92363d1
SR		 1739 base = pci_find_capability(ioc->pdev, PCI_CAP_ID_MSIX);
1740 if (!base) {
1741 dfailprintk(ioc, pr_info(MPT3SAS_FMT "msix not supported\n",
1742 ioc->name));
1743 return -EINVAL;
1744 }
1745
1746 /* get msix vector count */
42081173
SR		 1747 /* NUMA_IO not supported for older controllers */
1748 if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2004 ||
1749 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 ||
1750 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_1 ||
1751 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_2 ||
1752 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_3 ||
1753 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_1 ||
1754 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_2)
1755 ioc->msix_vector_count = 1;
1756 else {
1757 pci_read_config_word(ioc->pdev, base + 2, &message_control);
1758 ioc->msix_vector_count = (message_control & 0x3FF) + 1;
1759 }
f92363d1
SR		 1760 dinitprintk(ioc, pr_info(MPT3SAS_FMT
1761 "msix is supported, vector_count(%d)\n",
1762 ioc->name, ioc->msix_vector_count));
1763 return 0;
1764}
1765
1766/**
1767 * _base_free_irq - free irq
1768 * @ioc: per adapter object
1769 *
1770 * Freeing respective reply_queue from the list.
1771 */
1772static void
1773_base_free_irq(struct MPT3SAS_ADAPTER *ioc)
1774{
1775 struct adapter_reply_queue *reply_q, *next;
1776
1777 if (list_empty(&ioc->reply_queue_list))
1778 return;
1779
1780 list_for_each_entry_safe(reply_q, next, &ioc->reply_queue_list, list) {
1781 list_del(&reply_q->list);
14b3114d
SR		 1782 irq_set_affinity_hint(reply_q->vector, NULL);
1783 free_cpumask_var(reply_q->affinity_hint);
f92363d1
SR		 1784 synchronize_irq(reply_q->vector);
1785 free_irq(reply_q->vector, reply_q);
1786 kfree(reply_q);
1787 }
1788}
1789
1790/**
1791 * _base_request_irq - request irq
1792 * @ioc: per adapter object
1793 * @index: msix index into vector table
1794 * @vector: irq vector
1795 *
1796 * Inserting respective reply_queue into the list.
1797 */
1798static int
1799_base_request_irq(struct MPT3SAS_ADAPTER *ioc, u8 index, u32 vector)
1800{
1801 struct adapter_reply_queue *reply_q;
1802 int r;
1803
1804 reply_q = kzalloc(sizeof(struct adapter_reply_queue), GFP_KERNEL);
1805 if (!reply_q) {
1806 pr_err(MPT3SAS_FMT "unable to allocate memory %d!\n",
1807 ioc->name, (int)sizeof(struct adapter_reply_queue));
1808 return -ENOMEM;
1809 }
1810 reply_q->ioc = ioc;
1811 reply_q->msix_index = index;
1812 reply_q->vector = vector;
14b3114d
SR		 1813
1814 if (!alloc_cpumask_var(&reply_q->affinity_hint, GFP_KERNEL))
1815 return -ENOMEM;
1816 cpumask_clear(reply_q->affinity_hint);
1817
f92363d1
SR		 1818 atomic_set(&reply_q->busy, 0);
1819 if (ioc->msix_enable)
1820 snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d-msix%d",
d357e84d 1821 driver_name, ioc->id, index);
f92363d1
SR		 1822 else
1823 snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d",
d357e84d 1824 driver_name, ioc->id);
f92363d1
SR		 1825 r = request_irq(vector, _base_interrupt, IRQF_SHARED, reply_q->name,
1826 reply_q);
1827 if (r) {
1828 pr_err(MPT3SAS_FMT "unable to allocate interrupt %d!\n",
1829 reply_q->name, vector);
1830 kfree(reply_q);
1831 return -EBUSY;
1832 }
1833
1834 INIT_LIST_HEAD(&reply_q->list);
1835 list_add_tail(&reply_q->list, &ioc->reply_queue_list);
1836 return 0;
1837}
1838
1839/**
1840 * _base_assign_reply_queues - assigning msix index for each cpu
1841 * @ioc: per adapter object
1842 *
1843 * The enduser would need to set the affinity via /proc/irq/#/smp_affinity
1844 *
1845 * It would nice if we could call irq_set_affinity, however it is not
1846 * an exported symbol
1847 */
1848static void
1849_base_assign_reply_queues(struct MPT3SAS_ADAPTER *ioc)
1850{
91b265bf 1851 unsigned int cpu, nr_cpus, nr_msix, index = 0;
14b3114d 1852 struct adapter_reply_queue *reply_q;
f92363d1
SR		 1853
1854 if (!_base_is_controller_msix_enabled(ioc))
1855 return;
1856
1857 memset(ioc->cpu_msix_table, 0, ioc->cpu_msix_table_sz);
1858
91b265bf
MP		 1859 nr_cpus = num_online_cpus();
1860 nr_msix = ioc->reply_queue_count = min(ioc->reply_queue_count,
1861 ioc->facts.MaxMSIxVectors);
1862 if (!nr_msix)
1863 return;
f92363d1 1864
91b265bf
MP		 1865 cpu = cpumask_first(cpu_online_mask);
1866
14b3114d
SR		 1867 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
1868
91b265bf
MP		 1869 unsigned int i, group = nr_cpus / nr_msix;
1870
14b3114d
SR		 1871 if (cpu >= nr_cpus)
1872 break;
1873
91b265bf
MP		 1874 if (index < nr_cpus % nr_msix)
1875 group++;
1876
1877 for (i = 0 ; i < group ; i++) {
1878 ioc->cpu_msix_table[cpu] = index;
14b3114d
SR		 1879 cpumask_or(reply_q->affinity_hint,
1880 reply_q->affinity_hint, get_cpu_mask(cpu));
91b265bf 1881 cpu = cpumask_next(cpu, cpu_online_mask);
f92363d1 1882 }
91b265bf 1883
14b3114d
SR		 1884 if (irq_set_affinity_hint(reply_q->vector,
1885 reply_q->affinity_hint))
1886 dinitprintk(ioc, pr_info(MPT3SAS_FMT
1887 "error setting affinity hint for irq vector %d\n",
1888 ioc->name, reply_q->vector));
91b265bf 1889 index++;
14b3114d 1890 }
f92363d1
SR		 1891}
1892
1893/**
1894 * _base_disable_msix - disables msix
1895 * @ioc: per adapter object
1896 *
1897 */
1898static void
1899_base_disable_msix(struct MPT3SAS_ADAPTER *ioc)
1900{
1901 if (!ioc->msix_enable)
1902 return;
1903 pci_disable_msix(ioc->pdev);
1904 ioc->msix_enable = 0;
1905}
1906
1907/**
1908 * _base_enable_msix - enables msix, failback to io_apic
1909 * @ioc: per adapter object
1910 *
1911 */
1912static int
1913_base_enable_msix(struct MPT3SAS_ADAPTER *ioc)
1914{
1915 struct msix_entry *entries, *a;
1916 int r;
1917 int i;
1918 u8 try_msix = 0;
1919
f92363d1
SR		 1920 if (msix_disable == -1 || msix_disable == 0)
1921 try_msix = 1;
1922
1923 if (!try_msix)
1924 goto try_ioapic;
1925
1926 if (_base_check_enable_msix(ioc) != 0)
1927 goto try_ioapic;
1928
1929 ioc->reply_queue_count = min_t(int, ioc->cpu_count,
1930 ioc->msix_vector_count);
1931
9c500060
SR		 1932 printk(MPT3SAS_FMT "MSI-X vectors supported: %d, no of cores"
1933 ": %d, max_msix_vectors: %d\n", ioc->name, ioc->msix_vector_count,
1934 ioc->cpu_count, max_msix_vectors);
1935
9b05c91a
SR		 1936 if (!ioc->rdpq_array_enable && max_msix_vectors == -1)
1937 max_msix_vectors = 8;
1938
9c500060
SR		 1939 if (max_msix_vectors > 0) {
1940 ioc->reply_queue_count = min_t(int, max_msix_vectors,
1941 ioc->reply_queue_count);
1942 ioc->msix_vector_count = ioc->reply_queue_count;
9b05c91a
SR		 1943 } else if (max_msix_vectors == 0)
1944 goto try_ioapic;
9c500060 1945
f92363d1
SR		 1946 entries = kcalloc(ioc->reply_queue_count, sizeof(struct msix_entry),
1947 GFP_KERNEL);
1948 if (!entries) {
1949 dfailprintk(ioc, pr_info(MPT3SAS_FMT
1950 "kcalloc failed @ at %s:%d/%s() !!!\n",
1951 ioc->name, __FILE__, __LINE__, __func__));
1952 goto try_ioapic;
1953 }
1954
1955 for (i = 0, a = entries; i < ioc->reply_queue_count; i++, a++)
1956 a->entry = i;
1957
6bfa6907 1958 r = pci_enable_msix_exact(ioc->pdev, entries, ioc->reply_queue_count);
f92363d1
SR		 1959 if (r) {
1960 dfailprintk(ioc, pr_info(MPT3SAS_FMT
6bfa6907 1961 "pci_enable_msix_exact failed (r=%d) !!!\n",
f92363d1
SR		 1962 ioc->name, r));
1963 kfree(entries);
1964 goto try_ioapic;
1965 }
1966
1967 ioc->msix_enable = 1;
1968 for (i = 0, a = entries; i < ioc->reply_queue_count; i++, a++) {
1969 r = _base_request_irq(ioc, i, a->vector);
1970 if (r) {
1971 _base_free_irq(ioc);
1972 _base_disable_msix(ioc);
1973 kfree(entries);
1974 goto try_ioapic;
1975 }
1976 }
1977
1978 kfree(entries);
1979 return 0;
1980
1981/* failback to io_apic interrupt routing */
1982 try_ioapic:
1983
9b05c91a 1984 ioc->reply_queue_count = 1;
f92363d1
SR		 1985 r = _base_request_irq(ioc, 0, ioc->pdev->irq);
1986
1987 return r;
1988}
1989
580d4e31
SR		 1990/**
1991 * mpt3sas_base_unmap_resources - free controller resources
1992 * @ioc: per adapter object
1993 */
1994void
1995mpt3sas_base_unmap_resources(struct MPT3SAS_ADAPTER *ioc)
1996{
1997 struct pci_dev *pdev = ioc->pdev;
1998
1999 dexitprintk(ioc, printk(MPT3SAS_FMT "%s\n",
2000 ioc->name, __func__));
2001
2002 _base_free_irq(ioc);
2003 _base_disable_msix(ioc);
2004
2005 if (ioc->msix96_vector)
2006 kfree(ioc->replyPostRegisterIndex);
2007
2008 if (ioc->chip_phys) {
2009 iounmap(ioc->chip);
2010 ioc->chip_phys = 0;
2011 }
2012
2013 if (pci_is_enabled(pdev)) {
2014 pci_release_selected_regions(ioc->pdev, ioc->bars);
2015 pci_disable_pcie_error_reporting(pdev);
2016 pci_disable_device(pdev);
2017 }
2018}
2019
f92363d1
SR		 2020/**
2021 * mpt3sas_base_map_resources - map in controller resources (io/irq/memap)
2022 * @ioc: per adapter object
2023 *
2024 * Returns 0 for success, non-zero for failure.
2025 */
2026int
2027mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc)
2028{
2029 struct pci_dev *pdev = ioc->pdev;
2030 u32 memap_sz;
2031 u32 pio_sz;
2032 int i, r = 0;
2033 u64 pio_chip = 0;
2034 u64 chip_phys = 0;
2035 struct adapter_reply_queue *reply_q;
2036
2037 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n",
2038 ioc->name, __func__));
2039
2040 ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
2041 if (pci_enable_device_mem(pdev)) {
2042 pr_warn(MPT3SAS_FMT "pci_enable_device_mem: failed\n",
2043 ioc->name);
cf9bd21a 2044 ioc->bars = 0;
f92363d1
SR		 2045 return -ENODEV;
2046 }
2047
2048
2049 if (pci_request_selected_regions(pdev, ioc->bars,
d357e84d 2050 driver_name)) {
f92363d1
SR		 2051 pr_warn(MPT3SAS_FMT "pci_request_selected_regions: failed\n",
2052 ioc->name);
cf9bd21a 2053 ioc->bars = 0;
f92363d1
SR		 2054 r = -ENODEV;
2055 goto out_fail;
2056 }
2057
2058/* AER (Advanced Error Reporting) hooks */
2059 pci_enable_pcie_error_reporting(pdev);
2060
2061 pci_set_master(pdev);
2062
2063
2064 if (_base_config_dma_addressing(ioc, pdev) != 0) {
2065 pr_warn(MPT3SAS_FMT "no suitable DMA mask for %s\n",
2066 ioc->name, pci_name(pdev));
2067 r = -ENODEV;
2068 goto out_fail;
2069 }
2070
5aeeb78a
SR		 2071 for (i = 0, memap_sz = 0, pio_sz = 0; (i < DEVICE_COUNT_RESOURCE) &&
2072 (!memap_sz || !pio_sz); i++) {
f92363d1
SR		 2073 if (pci_resource_flags(pdev, i) & IORESOURCE_IO) {
2074 if (pio_sz)
2075 continue;
2076 pio_chip = (u64)pci_resource_start(pdev, i);
2077 pio_sz = pci_resource_len(pdev, i);
2078 } else if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
2079 if (memap_sz)
2080 continue;
2081 ioc->chip_phys = pci_resource_start(pdev, i);
2082 chip_phys = (u64)ioc->chip_phys;
2083 memap_sz = pci_resource_len(pdev, i);
2084 ioc->chip = ioremap(ioc->chip_phys, memap_sz);
f92363d1
SR		 2085 }
2086 }
2087
5aeeb78a
SR		 2088 if (ioc->chip == NULL) {
2089 pr_err(MPT3SAS_FMT "unable to map adapter memory! "
2090 " or resource not found\n", ioc->name);
2091 r = -EINVAL;
2092 goto out_fail;
2093 }
2094
f92363d1 2095 _base_mask_interrupts(ioc);
9b05c91a
SR		 2096
2097 r = _base_get_ioc_facts(ioc, CAN_SLEEP);
2098 if (r)
2099 goto out_fail;
2100
2101 if (!ioc->rdpq_array_enable_assigned) {
2102 ioc->rdpq_array_enable = ioc->rdpq_array_capable;
2103 ioc->rdpq_array_enable_assigned = 1;
2104 }
2105
f92363d1
SR		 2106 r = _base_enable_msix(ioc);
2107 if (r)
2108 goto out_fail;
2109
fb77bb53
SR		 2110 /* Use the Combined reply queue feature only for SAS3 C0 & higher
2111 * revision HBAs and also only when reply queue count is greater than 8
2112 */
2113 if (ioc->msix96_vector && ioc->reply_queue_count > 8) {
2114 /* Determine the Supplemental Reply Post Host Index Registers
2115 * Addresse. Supplemental Reply Post Host Index Registers
2116 * starts at offset MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET and
2117 * each register is at offset bytes of
2118 * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET from previous one.
2119 */
2120 ioc->replyPostRegisterIndex = kcalloc(
2121 MPT3_SUP_REPLY_POST_HOST_INDEX_REG_COUNT,
2122 sizeof(resource_size_t *), GFP_KERNEL);
2123 if (!ioc->replyPostRegisterIndex) {
2124 dfailprintk(ioc, printk(MPT3SAS_FMT
2125 "allocation for reply Post Register Index failed!!!\n",
2126 ioc->name));
2127 r = -ENOMEM;
2128 goto out_fail;
2129 }
2130
2131 for (i = 0; i < MPT3_SUP_REPLY_POST_HOST_INDEX_REG_COUNT; i++) {
2132 ioc->replyPostRegisterIndex[i] = (resource_size_t *)
2133 ((u8 *)&ioc->chip->Doorbell +
2134 MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET +
2135 (i * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET));
2136 }
2137 } else
2138 ioc->msix96_vector = 0;
2139
f92363d1
SR		 2140 list_for_each_entry(reply_q, &ioc->reply_queue_list, list)
2141 pr_info(MPT3SAS_FMT "%s: IRQ %d\n",
2142 reply_q->name, ((ioc->msix_enable) ? "PCI-MSI-X enabled" :
2143 "IO-APIC enabled"), reply_q->vector);
2144
2145 pr_info(MPT3SAS_FMT "iomem(0x%016llx), mapped(0x%p), size(%d)\n",
2146 ioc->name, (unsigned long long)chip_phys, ioc->chip, memap_sz);
2147 pr_info(MPT3SAS_FMT "ioport(0x%016llx), size(%d)\n",
2148 ioc->name, (unsigned long long)pio_chip, pio_sz);
2149
2150 /* Save PCI configuration state for recovery from PCI AER/EEH errors */
2151 pci_save_state(pdev);
2152 return 0;
2153
2154 out_fail:
580d4e31 2155 mpt3sas_base_unmap_resources(ioc);
f92363d1
SR		 2156 return r;
2157}
2158
2159/**
2160 * mpt3sas_base_get_msg_frame - obtain request mf pointer
2161 * @ioc: per adapter object
2162 * @smid: system request message index(smid zero is invalid)
2163 *
2164 * Returns virt pointer to message frame.
2165 */
2166void *
2167mpt3sas_base_get_msg_frame(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2168{
2169 return (void *)(ioc->request + (smid * ioc->request_sz));
2170}
2171
2172/**
2173 * mpt3sas_base_get_sense_buffer - obtain a sense buffer virt addr
2174 * @ioc: per adapter object
2175 * @smid: system request message index
2176 *
2177 * Returns virt pointer to sense buffer.
2178 */
2179void *
2180mpt3sas_base_get_sense_buffer(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2181{
2182 return (void *)(ioc->sense + ((smid - 1) * SCSI_SENSE_BUFFERSIZE));
2183}
2184
2185/**
2186 * mpt3sas_base_get_sense_buffer_dma - obtain a sense buffer dma addr
2187 * @ioc: per adapter object
2188 * @smid: system request message index
2189 *
2190 * Returns phys pointer to the low 32bit address of the sense buffer.
2191 */
2192__le32
2193mpt3sas_base_get_sense_buffer_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2194{
2195 return cpu_to_le32(ioc->sense_dma + ((smid - 1) *
2196 SCSI_SENSE_BUFFERSIZE));
2197}
2198
2199/**
2200 * mpt3sas_base_get_reply_virt_addr - obtain reply frames virt address
2201 * @ioc: per adapter object
2202 * @phys_addr: lower 32 physical addr of the reply
2203 *
2204 * Converts 32bit lower physical addr into a virt address.
2205 */
2206void *
2207mpt3sas_base_get_reply_virt_addr(struct MPT3SAS_ADAPTER *ioc, u32 phys_addr)
2208{
2209 if (!phys_addr)
2210 return NULL;
2211 return ioc->reply + (phys_addr - (u32)ioc->reply_dma);
2212}
2213
2214/**
2215 * mpt3sas_base_get_smid - obtain a free smid from internal queue
2216 * @ioc: per adapter object
2217 * @cb_idx: callback index
2218 *
2219 * Returns smid (zero is invalid)
2220 */
2221u16
2222mpt3sas_base_get_smid(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx)
2223{
2224 unsigned long flags;
2225 struct request_tracker *request;
2226 u16 smid;
2227
2228 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2229 if (list_empty(&ioc->internal_free_list)) {
2230 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2231 pr_err(MPT3SAS_FMT "%s: smid not available\n",
2232 ioc->name, __func__);
2233 return 0;
2234 }
2235
2236 request = list_entry(ioc->internal_free_list.next,
2237 struct request_tracker, tracker_list);
2238 request->cb_idx = cb_idx;
2239 smid = request->smid;
2240 list_del(&request->tracker_list);
2241 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2242 return smid;
2243}
2244
2245/**
2246 * mpt3sas_base_get_smid_scsiio - obtain a free smid from scsiio queue
2247 * @ioc: per adapter object
2248 * @cb_idx: callback index
2249 * @scmd: pointer to scsi command object
2250 *
2251 * Returns smid (zero is invalid)
2252 */
2253u16
2254mpt3sas_base_get_smid_scsiio(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx,
2255 struct scsi_cmnd *scmd)
2256{
2257 unsigned long flags;
2258 struct scsiio_tracker *request;
2259 u16 smid;
2260
2261 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2262 if (list_empty(&ioc->free_list)) {
2263 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2264 pr_err(MPT3SAS_FMT "%s: smid not available\n",
2265 ioc->name, __func__);
2266 return 0;
2267 }
2268
2269 request = list_entry(ioc->free_list.next,
2270 struct scsiio_tracker, tracker_list);
2271 request->scmd = scmd;
2272 request->cb_idx = cb_idx;
2273 smid = request->smid;
2274 list_del(&request->tracker_list);
2275 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2276 return smid;
2277}
2278
2279/**
2280 * mpt3sas_base_get_smid_hpr - obtain a free smid from hi-priority queue
2281 * @ioc: per adapter object
2282 * @cb_idx: callback index
2283 *
2284 * Returns smid (zero is invalid)
2285 */
2286u16
2287mpt3sas_base_get_smid_hpr(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx)
2288{
2289 unsigned long flags;
2290 struct request_tracker *request;
2291 u16 smid;
2292
2293 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2294 if (list_empty(&ioc->hpr_free_list)) {
2295 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2296 return 0;
2297 }
2298
2299 request = list_entry(ioc->hpr_free_list.next,
2300 struct request_tracker, tracker_list);
2301 request->cb_idx = cb_idx;
2302 smid = request->smid;
2303 list_del(&request->tracker_list);
2304 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2305 return smid;
2306}
2307
2308/**
2309 * mpt3sas_base_free_smid - put smid back on free_list
2310 * @ioc: per adapter object
2311 * @smid: system request message index
2312 *
2313 * Return nothing.
2314 */
2315void
2316mpt3sas_base_free_smid(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2317{
2318 unsigned long flags;
2319 int i;
2320 struct chain_tracker *chain_req, *next;
2321
2322 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2323 if (smid < ioc->hi_priority_smid) {
2324 /* scsiio queue */
2325 i = smid - 1;
2326 if (!list_empty(&ioc->scsi_lookup[i].chain_list)) {
2327 list_for_each_entry_safe(chain_req, next,
2328 &ioc->scsi_lookup[i].chain_list, tracker_list) {
2329 list_del_init(&chain_req->tracker_list);
2330 list_add(&chain_req->tracker_list,
2331 &ioc->free_chain_list);
2332 }
2333 }
2334 ioc->scsi_lookup[i].cb_idx = 0xFF;
2335 ioc->scsi_lookup[i].scmd = NULL;
2336 list_add(&ioc->scsi_lookup[i].tracker_list, &ioc->free_list);
2337 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2338
2339 /*
2340 * See _wait_for_commands_to_complete() call with regards
2341 * to this code.
2342 */
2343 if (ioc->shost_recovery && ioc->pending_io_count) {
2344 if (ioc->pending_io_count == 1)
2345 wake_up(&ioc->reset_wq);
2346 ioc->pending_io_count--;
2347 }
2348 return;
2349 } else if (smid < ioc->internal_smid) {
2350 /* hi-priority */
2351 i = smid - ioc->hi_priority_smid;
2352 ioc->hpr_lookup[i].cb_idx = 0xFF;
2353 list_add(&ioc->hpr_lookup[i].tracker_list, &ioc->hpr_free_list);
2354 } else if (smid <= ioc->hba_queue_depth) {
2355 /* internal queue */
2356 i = smid - ioc->internal_smid;
2357 ioc->internal_lookup[i].cb_idx = 0xFF;
2358 list_add(&ioc->internal_lookup[i].tracker_list,
2359 &ioc->internal_free_list);
2360 }
2361 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2362}
2363
2364/**
2365 * _base_writeq - 64 bit write to MMIO
2366 * @ioc: per adapter object
2367 * @b: data payload
2368 * @addr: address in MMIO space
2369 * @writeq_lock: spin lock
2370 *
2371 * Glue for handling an atomic 64 bit word to MMIO. This special handling takes
2372 * care of 32 bit environment where its not quarenteed to send the entire word
2373 * in one transfer.
2374 */
2375#if defined(writeq) && defined(CONFIG_64BIT)
2376static inline void
2377_base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock)
2378{
2379 writeq(cpu_to_le64(b), addr);
2380}
2381#else
2382static inline void
2383_base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock)
2384{
2385 unsigned long flags;
2386 __u64 data_out = cpu_to_le64(b);
2387
2388 spin_lock_irqsave(writeq_lock, flags);
2389 writel((u32)(data_out), addr);
2390 writel((u32)(data_out >> 32), (addr + 4));
2391 spin_unlock_irqrestore(writeq_lock, flags);
2392}
2393#endif
2394
2395static inline u8
2396_base_get_msix_index(struct MPT3SAS_ADAPTER *ioc)
2397{
2398 return ioc->cpu_msix_table[raw_smp_processor_id()];
2399}
2400
2401/**
2402 * mpt3sas_base_put_smid_scsi_io - send SCSI_IO request to firmware
2403 * @ioc: per adapter object
2404 * @smid: system request message index
2405 * @handle: device handle
2406 *
2407 * Return nothing.
2408 */
2409void
2410mpt3sas_base_put_smid_scsi_io(struct MPT3SAS_ADAPTER *ioc, u16 smid, u16 handle)
2411{
2412 Mpi2RequestDescriptorUnion_t descriptor;
2413 u64 *request = (u64 *)&descriptor;
2414
2415
2416 descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
2417 descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc);
2418 descriptor.SCSIIO.SMID = cpu_to_le16(smid);
2419 descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
2420 descriptor.SCSIIO.LMID = 0;
2421 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2422 &ioc->scsi_lookup_lock);
2423}
2424
2425/**
2426 * mpt3sas_base_put_smid_fast_path - send fast path request to firmware
2427 * @ioc: per adapter object
2428 * @smid: system request message index
2429 * @handle: device handle
2430 *
2431 * Return nothing.
2432 */
2433void
2434mpt3sas_base_put_smid_fast_path(struct MPT3SAS_ADAPTER *ioc, u16 smid,
2435 u16 handle)
2436{
2437 Mpi2RequestDescriptorUnion_t descriptor;
2438 u64 *request = (u64 *)&descriptor;
2439
2440 descriptor.SCSIIO.RequestFlags =
2441 MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO;
2442 descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc);
2443 descriptor.SCSIIO.SMID = cpu_to_le16(smid);
2444 descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
2445 descriptor.SCSIIO.LMID = 0;
2446 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2447 &ioc->scsi_lookup_lock);
2448}
2449
2450/**
2451 * mpt3sas_base_put_smid_hi_priority - send Task Managment request to firmware
2452 * @ioc: per adapter object
2453 * @smid: system request message index
2454 *
2455 * Return nothing.
2456 */
2457void
2458mpt3sas_base_put_smid_hi_priority(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2459{
2460 Mpi2RequestDescriptorUnion_t descriptor;
2461 u64 *request = (u64 *)&descriptor;
2462
2463 descriptor.HighPriority.RequestFlags =
2464 MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY;
2465 descriptor.HighPriority.MSIxIndex = 0;
2466 descriptor.HighPriority.SMID = cpu_to_le16(smid);
2467 descriptor.HighPriority.LMID = 0;
2468 descriptor.HighPriority.Reserved1 = 0;
2469 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2470 &ioc->scsi_lookup_lock);
2471}
2472
2473/**
2474 * mpt3sas_base_put_smid_default - Default, primarily used for config pages
2475 * @ioc: per adapter object
2476 * @smid: system request message index
2477 *
2478 * Return nothing.
2479 */
2480void
2481mpt3sas_base_put_smid_default(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2482{
2483 Mpi2RequestDescriptorUnion_t descriptor;
2484 u64 *request = (u64 *)&descriptor;
2485
2486 descriptor.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
2487 descriptor.Default.MSIxIndex = _base_get_msix_index(ioc);
2488 descriptor.Default.SMID = cpu_to_le16(smid);
2489 descriptor.Default.LMID = 0;
2490 descriptor.Default.DescriptorTypeDependent = 0;
2491 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2492 &ioc->scsi_lookup_lock);
2493}
2494
1117b31a
SR		 2495/**
2496 * _base_display_intel_branding - Display branding string
2497 * @ioc: per adapter object
2498 *
2499 * Return nothing.
2500 */
2501static void
2502_base_display_intel_branding(struct MPT3SAS_ADAPTER *ioc)
2503{
2504 if (ioc->pdev->subsystem_vendor != PCI_VENDOR_ID_INTEL)
2505 return;
2506
2507 switch (ioc->pdev->device) {
2508 case MPI25_MFGPAGE_DEVID_SAS3008:
2509 switch (ioc->pdev->subsystem_device) {
2510 case MPT3SAS_INTEL_RMS3JC080_SSDID:
2511 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2512 MPT3SAS_INTEL_RMS3JC080_BRANDING);
2513 break;
2514
2515 case MPT3SAS_INTEL_RS3GC008_SSDID:
2516 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2517 MPT3SAS_INTEL_RS3GC008_BRANDING);
2518 break;
2519 case MPT3SAS_INTEL_RS3FC044_SSDID:
2520 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2521 MPT3SAS_INTEL_RS3FC044_BRANDING);
2522 break;
2523 case MPT3SAS_INTEL_RS3UC080_SSDID:
2524 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2525 MPT3SAS_INTEL_RS3UC080_BRANDING);
2526 break;
2527 default:
2528 pr_info(MPT3SAS_FMT
2529 "Intel(R) Controller: Subsystem ID: 0x%X\n",
2530 ioc->name, ioc->pdev->subsystem_device);
2531 break;
2532 }
2533 break;
2534 default:
2535 pr_info(MPT3SAS_FMT
2536 "Intel(R) Controller: Subsystem ID: 0x%X\n",
2537 ioc->name, ioc->pdev->subsystem_device);
2538 break;
2539 }
2540}
2541
f92363d1
SR		 2542
2543
fb84dfc4
SR		 2544/**
2545 * _base_display_dell_branding - Display branding string
2546 * @ioc: per adapter object
2547 *
2548 * Return nothing.
2549 */
2550static void
2551_base_display_dell_branding(struct MPT3SAS_ADAPTER *ioc)
2552{
2553 if (ioc->pdev->subsystem_vendor != PCI_VENDOR_ID_DELL)
2554 return;
2555
2556 switch (ioc->pdev->device) {
2557 case MPI25_MFGPAGE_DEVID_SAS3008:
2558 switch (ioc->pdev->subsystem_device) {
2559 case MPT3SAS_DELL_12G_HBA_SSDID:
2560 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2561 MPT3SAS_DELL_12G_HBA_BRANDING);
2562 break;
2563 default:
2564 pr_info(MPT3SAS_FMT
2565 "Dell 12Gbps HBA: Subsystem ID: 0x%X\n", ioc->name,
2566 ioc->pdev->subsystem_device);
2567 break;
2568 }
2569 break;
2570 default:
2571 pr_info(MPT3SAS_FMT
2572 "Dell 12Gbps HBA: Subsystem ID: 0x%X\n", ioc->name,
2573 ioc->pdev->subsystem_device);
2574 break;
2575 }
2576}
2577
38e4141e
SR		 2578/**
2579 * _base_display_cisco_branding - Display branding string
2580 * @ioc: per adapter object
2581 *
2582 * Return nothing.
2583 */
2584static void
2585_base_display_cisco_branding(struct MPT3SAS_ADAPTER *ioc)
2586{
2587 if (ioc->pdev->subsystem_vendor != PCI_VENDOR_ID_CISCO)
2588 return;
2589
2590 switch (ioc->pdev->device) {
2591 case MPI25_MFGPAGE_DEVID_SAS3008:
2592 switch (ioc->pdev->subsystem_device) {
d8eb4a47 2593 case MPT3SAS_CISCO_12G_8E_HBA_SSDID:
38e4141e 2594 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
d8eb4a47
SR		 2595 MPT3SAS_CISCO_12G_8E_HBA_BRANDING);
2596 break;
2597 case MPT3SAS_CISCO_12G_8I_HBA_SSDID:
2598 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2599 MPT3SAS_CISCO_12G_8I_HBA_BRANDING);
2600 break;
2601 case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID:
2602 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2603 MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING);
38e4141e
SR		 2604 break;
2605 default:
2606 pr_info(MPT3SAS_FMT
2607 "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n",
2608 ioc->name, ioc->pdev->subsystem_device);
2609 break;
2610 }
2611 break;
d8eb4a47
SR		 2612 case MPI25_MFGPAGE_DEVID_SAS3108_1:
2613 switch (ioc->pdev->subsystem_device) {
2614 case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID:
2615 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2616 MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING);
2617 break;
2618 case MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_SSDID:
2619 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2620 MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_BRANDING);
2621 break;
2622 default:
2623 pr_info(MPT3SAS_FMT
2624 "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n",
2625 ioc->name, ioc->pdev->subsystem_device);
2626 break;
2627 }
2628 break;
38e4141e
SR		 2629 default:
2630 pr_info(MPT3SAS_FMT
2631 "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n",
2632 ioc->name, ioc->pdev->subsystem_device);
2633 break;
2634 }
2635}
fb84dfc4 2636
f92363d1
SR		 2637/**
2638 * _base_display_ioc_capabilities - Disply IOC's capabilities.
2639 * @ioc: per adapter object
2640 *
2641 * Return nothing.
2642 */
2643static void
2644_base_display_ioc_capabilities(struct MPT3SAS_ADAPTER *ioc)
2645{
2646 int i = 0;
2647 char desc[16];
2648 u32 iounit_pg1_flags;
2649 u32 bios_version;
2650
2651 bios_version = le32_to_cpu(ioc->bios_pg3.BiosVersion);
2652 strncpy(desc, ioc->manu_pg0.ChipName, 16);
2653 pr_info(MPT3SAS_FMT "%s: FWVersion(%02d.%02d.%02d.%02d), "\
2654 "ChipRevision(0x%02x), BiosVersion(%02d.%02d.%02d.%02d)\n",
2655 ioc->name, desc,
2656 (ioc->facts.FWVersion.Word & 0xFF000000) >> 24,
2657 (ioc->facts.FWVersion.Word & 0x00FF0000) >> 16,
2658 (ioc->facts.FWVersion.Word & 0x0000FF00) >> 8,
2659 ioc->facts.FWVersion.Word & 0x000000FF,
2660 ioc->pdev->revision,
2661 (bios_version & 0xFF000000) >> 24,
2662 (bios_version & 0x00FF0000) >> 16,
2663 (bios_version & 0x0000FF00) >> 8,
2664 bios_version & 0x000000FF);
2665
1117b31a 2666 _base_display_intel_branding(ioc);
fb84dfc4 2667 _base_display_dell_branding(ioc);
38e4141e 2668 _base_display_cisco_branding(ioc);
1117b31a 2669
f92363d1
SR		 2670 pr_info(MPT3SAS_FMT "Protocol=(", ioc->name);
2671
2672 if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR) {
2673 pr_info("Initiator");
2674 i++;
2675 }
2676
2677 if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET) {
2678 pr_info("%sTarget", i ? "," : "");
2679 i++;
2680 }
2681
2682 i = 0;
2683 pr_info("), ");
2684 pr_info("Capabilities=(");
2685
2686 if (ioc->facts.IOCCapabilities &
2687 MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID) {
2688 pr_info("Raid");
2689 i++;
2690 }
2691
2692 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_TLR) {
2693 pr_info("%sTLR", i ? "," : "");
2694 i++;
2695 }
2696
2697 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_MULTICAST) {
2698 pr_info("%sMulticast", i ? "," : "");
2699 i++;
2700 }
2701
2702 if (ioc->facts.IOCCapabilities &
2703 MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET) {
2704 pr_info("%sBIDI Target", i ? "," : "");
2705 i++;
2706 }
2707
2708 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_EEDP) {
2709 pr_info("%sEEDP", i ? "," : "");
2710 i++;
2711 }
2712
2713 if (ioc->facts.IOCCapabilities &
2714 MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER) {
2715 pr_info("%sSnapshot Buffer", i ? "," : "");
2716 i++;
2717 }
2718
2719 if (ioc->facts.IOCCapabilities &
2720 MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER) {
2721 pr_info("%sDiag Trace Buffer", i ? "," : "");
2722 i++;
2723 }
2724
2725 if (ioc->facts.IOCCapabilities &
2726 MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER) {
2727 pr_info("%sDiag Extended Buffer", i ? "," : "");
2728 i++;
2729 }
2730
2731 if (ioc->facts.IOCCapabilities &
2732 MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING) {
2733 pr_info("%sTask Set Full", i ? "," : "");
2734 i++;
2735 }
2736
2737 iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
2738 if (!(iounit_pg1_flags & MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE)) {
2739 pr_info("%sNCQ", i ? "," : "");
2740 i++;
2741 }
2742
2743 pr_info(")\n");
2744}
2745
2746/**
2747 * mpt3sas_base_update_missing_delay - change the missing delay timers
2748 * @ioc: per adapter object
2749 * @device_missing_delay: amount of time till device is reported missing
2750 * @io_missing_delay: interval IO is returned when there is a missing device
2751 *
2752 * Return nothing.
2753 *
2754 * Passed on the command line, this function will modify the device missing
2755 * delay, as well as the io missing delay. This should be called at driver
2756 * load time.
2757 */
2758void
2759mpt3sas_base_update_missing_delay(struct MPT3SAS_ADAPTER *ioc,
2760 u16 device_missing_delay, u8 io_missing_delay)
2761{
2762 u16 dmd, dmd_new, dmd_orignal;
2763 u8 io_missing_delay_original;
2764 u16 sz;
2765 Mpi2SasIOUnitPage1_t *sas_iounit_pg1 = NULL;
2766 Mpi2ConfigReply_t mpi_reply;
2767 u8 num_phys = 0;
2768 u16 ioc_status;
2769
2770 mpt3sas_config_get_number_hba_phys(ioc, &num_phys);
2771 if (!num_phys)
2772 return;
2773
2774 sz = offsetof(Mpi2SasIOUnitPage1_t, PhyData) + (num_phys *
2775 sizeof(Mpi2SasIOUnit1PhyData_t));
2776 sas_iounit_pg1 = kzalloc(sz, GFP_KERNEL);
2777 if (!sas_iounit_pg1) {
2778 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
2779 ioc->name, __FILE__, __LINE__, __func__);
2780 goto out;
2781 }
2782 if ((mpt3sas_config_get_sas_iounit_pg1(ioc, &mpi_reply,
2783 sas_iounit_pg1, sz))) {
2784 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
2785 ioc->name, __FILE__, __LINE__, __func__);
2786 goto out;
2787 }
2788 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
2789 MPI2_IOCSTATUS_MASK;
2790 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
2791 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
2792 ioc->name, __FILE__, __LINE__, __func__);
2793 goto out;
2794 }
2795
2796 /* device missing delay */
2797 dmd = sas_iounit_pg1->ReportDeviceMissingDelay;
2798 if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16)
2799 dmd = (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16;
2800 else
2801 dmd = dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
2802 dmd_orignal = dmd;
2803 if (device_missing_delay > 0x7F) {
2804 dmd = (device_missing_delay > 0x7F0) ? 0x7F0 :
2805 device_missing_delay;
2806 dmd = dmd / 16;
2807 dmd |= MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16;
2808 } else
2809 dmd = device_missing_delay;
2810 sas_iounit_pg1->ReportDeviceMissingDelay = dmd;
2811
2812 /* io missing delay */
2813 io_missing_delay_original = sas_iounit_pg1->IODeviceMissingDelay;
2814 sas_iounit_pg1->IODeviceMissingDelay = io_missing_delay;
2815
2816 if (!mpt3sas_config_set_sas_iounit_pg1(ioc, &mpi_reply, sas_iounit_pg1,
2817 sz)) {
2818 if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16)
2819 dmd_new = (dmd &
2820 MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16;
2821 else
2822 dmd_new =
2823 dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
2824 pr_info(MPT3SAS_FMT "device_missing_delay: old(%d), new(%d)\n",
2825 ioc->name, dmd_orignal, dmd_new);
2826 pr_info(MPT3SAS_FMT "ioc_missing_delay: old(%d), new(%d)\n",
2827 ioc->name, io_missing_delay_original,
2828 io_missing_delay);
2829 ioc->device_missing_delay = dmd_new;
2830 ioc->io_missing_delay = io_missing_delay;
2831 }
2832
2833out:
2834 kfree(sas_iounit_pg1);
2835}
2836/**
2837 * _base_static_config_pages - static start of day config pages
2838 * @ioc: per adapter object
2839 *
2840 * Return nothing.
2841 */
2842static void
2843_base_static_config_pages(struct MPT3SAS_ADAPTER *ioc)
2844{
2845 Mpi2ConfigReply_t mpi_reply;
2846 u32 iounit_pg1_flags;
2847
2848 mpt3sas_config_get_manufacturing_pg0(ioc, &mpi_reply, &ioc->manu_pg0);
2849 if (ioc->ir_firmware)
2850 mpt3sas_config_get_manufacturing_pg10(ioc, &mpi_reply,
2851 &ioc->manu_pg10);
2852
2853 /*
2854 * Ensure correct T10 PI operation if vendor left EEDPTagMode
2855 * flag unset in NVDATA.
2856 */
2857 mpt3sas_config_get_manufacturing_pg11(ioc, &mpi_reply, &ioc->manu_pg11);
2858 if (ioc->manu_pg11.EEDPTagMode == 0) {
2859 pr_err("%s: overriding NVDATA EEDPTagMode setting\n",
2860 ioc->name);
2861 ioc->manu_pg11.EEDPTagMode &= ~0x3;
2862 ioc->manu_pg11.EEDPTagMode |= 0x1;
2863 mpt3sas_config_set_manufacturing_pg11(ioc, &mpi_reply,
2864 &ioc->manu_pg11);
2865 }
2866
2867 mpt3sas_config_get_bios_pg2(ioc, &mpi_reply, &ioc->bios_pg2);
2868 mpt3sas_config_get_bios_pg3(ioc, &mpi_reply, &ioc->bios_pg3);
2869 mpt3sas_config_get_ioc_pg8(ioc, &mpi_reply, &ioc->ioc_pg8);
2870 mpt3sas_config_get_iounit_pg0(ioc, &mpi_reply, &ioc->iounit_pg0);
2871 mpt3sas_config_get_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
2d8ce8c9 2872 mpt3sas_config_get_iounit_pg8(ioc, &mpi_reply, &ioc->iounit_pg8);
f92363d1
SR		 2873 _base_display_ioc_capabilities(ioc);
2874
2875 /*
2876 * Enable task_set_full handling in iounit_pg1 when the
2877 * facts capabilities indicate that its supported.
2878 */
2879 iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
2880 if ((ioc->facts.IOCCapabilities &
2881 MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING))
2882 iounit_pg1_flags &=
2883 ~MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
2884 else
2885 iounit_pg1_flags |=
2886 MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
2887 ioc->iounit_pg1.Flags = cpu_to_le32(iounit_pg1_flags);
2888 mpt3sas_config_set_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
2d8ce8c9
SR		 2889
2890 if (ioc->iounit_pg8.NumSensors)
2891 ioc->temp_sensors_count = ioc->iounit_pg8.NumSensors;
f92363d1
SR		 2892}
2893
2894/**
2895 * _base_release_memory_pools - release memory
2896 * @ioc: per adapter object
2897 *
2898 * Free memory allocated from _base_allocate_memory_pools.
2899 *
2900 * Return nothing.
2901 */
2902static void
2903_base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc)
2904{
9b05c91a
SR		 2905 int i = 0;
2906 struct reply_post_struct *rps;
f92363d1
SR		 2907
2908 dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2909 __func__));
2910
2911 if (ioc->request) {
2912 pci_free_consistent(ioc->pdev, ioc->request_dma_sz,
2913 ioc->request, ioc->request_dma);
2914 dexitprintk(ioc, pr_info(MPT3SAS_FMT
2915 "request_pool(0x%p): free\n",
2916 ioc->name, ioc->request));
2917 ioc->request = NULL;
2918 }
2919
2920 if (ioc->sense) {
2921 pci_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma);
2922 if (ioc->sense_dma_pool)
2923 pci_pool_destroy(ioc->sense_dma_pool);
2924 dexitprintk(ioc, pr_info(MPT3SAS_FMT
2925 "sense_pool(0x%p): free\n",
2926 ioc->name, ioc->sense));
2927 ioc->sense = NULL;
2928 }
2929
2930 if (ioc->reply) {
2931 pci_pool_free(ioc->reply_dma_pool, ioc->reply, ioc->reply_dma);
2932 if (ioc->reply_dma_pool)
2933 pci_pool_destroy(ioc->reply_dma_pool);
2934 dexitprintk(ioc, pr_info(MPT3SAS_FMT
2935 "reply_pool(0x%p): free\n",
2936 ioc->name, ioc->reply));
2937 ioc->reply = NULL;
2938 }
2939
2940 if (ioc->reply_free) {
2941 pci_pool_free(ioc->reply_free_dma_pool, ioc->reply_free,
2942 ioc->reply_free_dma);
2943 if (ioc->reply_free_dma_pool)
2944 pci_pool_destroy(ioc->reply_free_dma_pool);
2945 dexitprintk(ioc, pr_info(MPT3SAS_FMT
2946 "reply_free_pool(0x%p): free\n",
2947 ioc->name, ioc->reply_free));
2948 ioc->reply_free = NULL;
2949 }
2950
9b05c91a
SR		 2951 if (ioc->reply_post) {
2952 do {
2953 rps = &ioc->reply_post[i];
2954 if (rps->reply_post_free) {
2955 pci_pool_free(
2956 ioc->reply_post_free_dma_pool,
2957 rps->reply_post_free,
2958 rps->reply_post_free_dma);
2959 dexitprintk(ioc, pr_info(MPT3SAS_FMT
2960 "reply_post_free_pool(0x%p): free\n",
2961 ioc->name, rps->reply_post_free));
2962 rps->reply_post_free = NULL;
2963 }
2964 } while (ioc->rdpq_array_enable &&
2965 (++i < ioc->reply_queue_count));
2966
f92363d1
SR		 2967 if (ioc->reply_post_free_dma_pool)
2968 pci_pool_destroy(ioc->reply_post_free_dma_pool);
9b05c91a 2969 kfree(ioc->reply_post);
f92363d1
SR		 2970 }
2971
2972 if (ioc->config_page) {
2973 dexitprintk(ioc, pr_info(MPT3SAS_FMT
2974 "config_page(0x%p): free\n", ioc->name,
2975 ioc->config_page));
2976 pci_free_consistent(ioc->pdev, ioc->config_page_sz,
2977 ioc->config_page, ioc->config_page_dma);
2978 }
2979
2980 if (ioc->scsi_lookup) {
2981 free_pages((ulong)ioc->scsi_lookup, ioc->scsi_lookup_pages);
2982 ioc->scsi_lookup = NULL;
2983 }
2984 kfree(ioc->hpr_lookup);
2985 kfree(ioc->internal_lookup);
2986 if (ioc->chain_lookup) {
2987 for (i = 0; i < ioc->chain_depth; i++) {
2988 if (ioc->chain_lookup[i].chain_buffer)
2989 pci_pool_free(ioc->chain_dma_pool,
2990 ioc->chain_lookup[i].chain_buffer,
2991 ioc->chain_lookup[i].chain_buffer_dma);
2992 }
2993 if (ioc->chain_dma_pool)
2994 pci_pool_destroy(ioc->chain_dma_pool);
2995 free_pages((ulong)ioc->chain_lookup, ioc->chain_pages);
2996 ioc->chain_lookup = NULL;
2997 }
2998}
2999
3000/**
3001 * _base_allocate_memory_pools - allocate start of day memory pools
3002 * @ioc: per adapter object
3003 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3004 *
3005 * Returns 0 success, anything else error
3006 */
3007static int
3008_base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
3009{
3010 struct mpt3sas_facts *facts;
3011 u16 max_sge_elements;
3012 u16 chains_needed_per_io;
3013 u32 sz, total_sz, reply_post_free_sz;
3014 u32 retry_sz;
3015 u16 max_request_credit;
3016 unsigned short sg_tablesize;
3017 u16 sge_size;
3018 int i;
3019
3020 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3021 __func__));
3022
3023
3024 retry_sz = 0;
3025 facts = &ioc->facts;
3026
3027 /* command line tunables for max sgl entries */
3028 if (max_sgl_entries != -1)
3029 sg_tablesize = max_sgl_entries;
471ef9d4
SR		 3030 else {
3031 if (ioc->hba_mpi_version_belonged == MPI2_VERSION)
3032 sg_tablesize = MPT2SAS_SG_DEPTH;
3033 else
3034 sg_tablesize = MPT3SAS_SG_DEPTH;
3035 }
f92363d1 3036
8a7e4c24
SR		 3037 if (sg_tablesize < MPT_MIN_PHYS_SEGMENTS)
3038 sg_tablesize = MPT_MIN_PHYS_SEGMENTS;
3039 else if (sg_tablesize > MPT_MAX_PHYS_SEGMENTS) {
ad666a0f
SR		 3040 sg_tablesize = min_t(unsigned short, sg_tablesize,
3041 SCSI_MAX_SG_CHAIN_SEGMENTS);
3042 pr_warn(MPT3SAS_FMT
3043 "sg_tablesize(%u) is bigger than kernel"
3044 " defined SCSI_MAX_SG_SEGMENTS(%u)\n", ioc->name,
8a7e4c24 3045 sg_tablesize, MPT_MAX_PHYS_SEGMENTS);
ad666a0f 3046 }
f92363d1
SR		 3047 ioc->shost->sg_tablesize = sg_tablesize;
3048
3049 ioc->hi_priority_depth = facts->HighPriorityCredit;
3050 ioc->internal_depth = ioc->hi_priority_depth + (5);
3051 /* command line tunables for max controller queue depth */
3052 if (max_queue_depth != -1 && max_queue_depth != 0) {
3053 max_request_credit = min_t(u16, max_queue_depth +
3054 ioc->hi_priority_depth + ioc->internal_depth,
3055 facts->RequestCredit);
3056 if (max_request_credit > MAX_HBA_QUEUE_DEPTH)
3057 max_request_credit = MAX_HBA_QUEUE_DEPTH;
3058 } else
3059 max_request_credit = min_t(u16, facts->RequestCredit,
3060 MAX_HBA_QUEUE_DEPTH);
3061
3062 ioc->hba_queue_depth = max_request_credit;
3063
3064 /* request frame size */
3065 ioc->request_sz = facts->IOCRequestFrameSize * 4;
3066
3067 /* reply frame size */
3068 ioc->reply_sz = facts->ReplyFrameSize * 4;
3069
3070 /* calculate the max scatter element size */
3071 sge_size = max_t(u16, ioc->sge_size, ioc->sge_size_ieee);
3072
3073 retry_allocation:
3074 total_sz = 0;
3075 /* calculate number of sg elements left over in the 1st frame */
3076 max_sge_elements = ioc->request_sz - ((sizeof(Mpi2SCSIIORequest_t) -
3077 sizeof(Mpi2SGEIOUnion_t)) + sge_size);
3078 ioc->max_sges_in_main_message = max_sge_elements/sge_size;
3079
3080 /* now do the same for a chain buffer */
3081 max_sge_elements = ioc->request_sz - sge_size;
3082 ioc->max_sges_in_chain_message = max_sge_elements/sge_size;
3083
3084 /*
3085 * MPT3SAS_SG_DEPTH = CONFIG_FUSION_MAX_SGE
3086 */
3087 chains_needed_per_io = ((ioc->shost->sg_tablesize -
3088 ioc->max_sges_in_main_message)/ioc->max_sges_in_chain_message)
3089 + 1;
3090 if (chains_needed_per_io > facts->MaxChainDepth) {
3091 chains_needed_per_io = facts->MaxChainDepth;
3092 ioc->shost->sg_tablesize = min_t(u16,
3093 ioc->max_sges_in_main_message + (ioc->max_sges_in_chain_message
3094 * chains_needed_per_io), ioc->shost->sg_tablesize);
3095 }
3096 ioc->chains_needed_per_io = chains_needed_per_io;
3097
3098 /* reply free queue sizing - taking into account for 64 FW events */
3099 ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64;
3100
3101 /* calculate reply descriptor post queue depth */
3102 ioc->reply_post_queue_depth = ioc->hba_queue_depth +
3103 ioc->reply_free_queue_depth + 1 ;
3104 /* align the reply post queue on the next 16 count boundary */
3105 if (ioc->reply_post_queue_depth % 16)
3106 ioc->reply_post_queue_depth += 16 -
3107 (ioc->reply_post_queue_depth % 16);
3108
3109
3110 if (ioc->reply_post_queue_depth >
3111 facts->MaxReplyDescriptorPostQueueDepth) {
3112 ioc->reply_post_queue_depth =
3113 facts->MaxReplyDescriptorPostQueueDepth -
3114 (facts->MaxReplyDescriptorPostQueueDepth % 16);
3115 ioc->hba_queue_depth =
3116 ((ioc->reply_post_queue_depth - 64) / 2) - 1;
3117 ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64;
3118 }
3119
3120 dinitprintk(ioc, pr_info(MPT3SAS_FMT "scatter gather: " \
3121 "sge_in_main_msg(%d), sge_per_chain(%d), sge_per_io(%d), "
3122 "chains_per_io(%d)\n", ioc->name, ioc->max_sges_in_main_message,
3123 ioc->max_sges_in_chain_message, ioc->shost->sg_tablesize,
3124 ioc->chains_needed_per_io));
3125
9b05c91a
SR		 3126 /* reply post queue, 16 byte align */
3127 reply_post_free_sz = ioc->reply_post_queue_depth *
3128 sizeof(Mpi2DefaultReplyDescriptor_t);
3129
3130 sz = reply_post_free_sz;
3131 if (_base_is_controller_msix_enabled(ioc) && !ioc->rdpq_array_enable)
3132 sz *= ioc->reply_queue_count;
3133
3134 ioc->reply_post = kcalloc((ioc->rdpq_array_enable) ?
3135 (ioc->reply_queue_count):1,
3136 sizeof(struct reply_post_struct), GFP_KERNEL);
3137
3138 if (!ioc->reply_post) {
3139 pr_err(MPT3SAS_FMT "reply_post_free pool: kcalloc failed\n",
3140 ioc->name);
3141 goto out;
3142 }
3143 ioc->reply_post_free_dma_pool = pci_pool_create("reply_post_free pool",
3144 ioc->pdev, sz, 16, 0);
3145 if (!ioc->reply_post_free_dma_pool) {
3146 pr_err(MPT3SAS_FMT
3147 "reply_post_free pool: pci_pool_create failed\n",
3148 ioc->name);
3149 goto out;
3150 }
3151 i = 0;
3152 do {
3153 ioc->reply_post[i].reply_post_free =
3154 pci_pool_alloc(ioc->reply_post_free_dma_pool,
3155 GFP_KERNEL,
3156 &ioc->reply_post[i].reply_post_free_dma);
3157 if (!ioc->reply_post[i].reply_post_free) {
3158 pr_err(MPT3SAS_FMT
3159 "reply_post_free pool: pci_pool_alloc failed\n",
3160 ioc->name);
3161 goto out;
3162 }
3163 memset(ioc->reply_post[i].reply_post_free, 0, sz);
3164 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3165 "reply post free pool (0x%p): depth(%d),"
3166 "element_size(%d), pool_size(%d kB)\n", ioc->name,
3167 ioc->reply_post[i].reply_post_free,
3168 ioc->reply_post_queue_depth, 8, sz/1024));
3169 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3170 "reply_post_free_dma = (0x%llx)\n", ioc->name,
3171 (unsigned long long)
3172 ioc->reply_post[i].reply_post_free_dma));
3173 total_sz += sz;
3174 } while (ioc->rdpq_array_enable && (++i < ioc->reply_queue_count));
3175
3176 if (ioc->dma_mask == 64) {
3177 if (_base_change_consistent_dma_mask(ioc, ioc->pdev) != 0) {
3178 pr_warn(MPT3SAS_FMT
3179 "no suitable consistent DMA mask for %s\n",
3180 ioc->name, pci_name(ioc->pdev));
3181 goto out;
3182 }
3183 }
3184
f92363d1
SR		 3185 ioc->scsiio_depth = ioc->hba_queue_depth -
3186 ioc->hi_priority_depth - ioc->internal_depth;
3187
3188 /* set the scsi host can_queue depth
3189 * with some internal commands that could be outstanding
3190 */
3191 ioc->shost->can_queue = ioc->scsiio_depth;
3192 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3193 "scsi host: can_queue depth (%d)\n",
3194 ioc->name, ioc->shost->can_queue));
3195
3196
3197 /* contiguous pool for request and chains, 16 byte align, one extra "
3198 * "frame for smid=0
3199 */
3200 ioc->chain_depth = ioc->chains_needed_per_io * ioc->scsiio_depth;
3201 sz = ((ioc->scsiio_depth + 1) * ioc->request_sz);
3202
3203 /* hi-priority queue */
3204 sz += (ioc->hi_priority_depth * ioc->request_sz);
3205
3206 /* internal queue */
3207 sz += (ioc->internal_depth * ioc->request_sz);
3208
3209 ioc->request_dma_sz = sz;
3210 ioc->request = pci_alloc_consistent(ioc->pdev, sz, &ioc->request_dma);
3211 if (!ioc->request) {
3212 pr_err(MPT3SAS_FMT "request pool: pci_alloc_consistent " \
3213 "failed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
3214 "total(%d kB)\n", ioc->name, ioc->hba_queue_depth,
3215 ioc->chains_needed_per_io, ioc->request_sz, sz/1024);
3216 if (ioc->scsiio_depth < MPT3SAS_SAS_QUEUE_DEPTH)
3217 goto out;
3218 retry_sz += 64;
3219 ioc->hba_queue_depth = max_request_credit - retry_sz;
3220 goto retry_allocation;
3221 }
3222
3223 if (retry_sz)
3224 pr_err(MPT3SAS_FMT "request pool: pci_alloc_consistent " \
3225 "succeed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
3226 "total(%d kb)\n", ioc->name, ioc->hba_queue_depth,
3227 ioc->chains_needed_per_io, ioc->request_sz, sz/1024);
3228
3229 /* hi-priority queue */
3230 ioc->hi_priority = ioc->request + ((ioc->scsiio_depth + 1) *
3231 ioc->request_sz);
3232 ioc->hi_priority_dma = ioc->request_dma + ((ioc->scsiio_depth + 1) *
3233 ioc->request_sz);
3234
3235 /* internal queue */
3236 ioc->internal = ioc->hi_priority + (ioc->hi_priority_depth *
3237 ioc->request_sz);
3238 ioc->internal_dma = ioc->hi_priority_dma + (ioc->hi_priority_depth *
3239 ioc->request_sz);
3240
3241 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3242 "request pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n",
3243 ioc->name, ioc->request, ioc->hba_queue_depth, ioc->request_sz,
3244 (ioc->hba_queue_depth * ioc->request_sz)/1024));
3245
3246 dinitprintk(ioc, pr_info(MPT3SAS_FMT "request pool: dma(0x%llx)\n",
3247 ioc->name, (unsigned long long) ioc->request_dma));
3248 total_sz += sz;
3249
3250 sz = ioc->scsiio_depth * sizeof(struct scsiio_tracker);
3251 ioc->scsi_lookup_pages = get_order(sz);
3252 ioc->scsi_lookup = (struct scsiio_tracker *)__get_free_pages(
3253 GFP_KERNEL, ioc->scsi_lookup_pages);
3254 if (!ioc->scsi_lookup) {
3255 pr_err(MPT3SAS_FMT "scsi_lookup: get_free_pages failed, sz(%d)\n",
3256 ioc->name, (int)sz);
3257 goto out;
3258 }
3259
3260 dinitprintk(ioc, pr_info(MPT3SAS_FMT "scsiio(0x%p): depth(%d)\n",
3261 ioc->name, ioc->request, ioc->scsiio_depth));
3262
3263 ioc->chain_depth = min_t(u32, ioc->chain_depth, MAX_CHAIN_DEPTH);
3264 sz = ioc->chain_depth * sizeof(struct chain_tracker);
3265 ioc->chain_pages = get_order(sz);
3266 ioc->chain_lookup = (struct chain_tracker *)__get_free_pages(
3267 GFP_KERNEL, ioc->chain_pages);
3268 if (!ioc->chain_lookup) {
3269 pr_err(MPT3SAS_FMT "chain_lookup: __get_free_pages failed\n",
3270 ioc->name);
3271 goto out;
3272 }
3273 ioc->chain_dma_pool = pci_pool_create("chain pool", ioc->pdev,
3274 ioc->request_sz, 16, 0);
3275 if (!ioc->chain_dma_pool) {
3276 pr_err(MPT3SAS_FMT "chain_dma_pool: pci_pool_create failed\n",
3277 ioc->name);
3278 goto out;
3279 }
3280 for (i = 0; i < ioc->chain_depth; i++) {
3281 ioc->chain_lookup[i].chain_buffer = pci_pool_alloc(
3282 ioc->chain_dma_pool , GFP_KERNEL,
3283 &ioc->chain_lookup[i].chain_buffer_dma);
3284 if (!ioc->chain_lookup[i].chain_buffer) {
3285 ioc->chain_depth = i;
3286 goto chain_done;
3287 }
3288 total_sz += ioc->request_sz;
3289 }
3290 chain_done:
3291 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3292 "chain pool depth(%d), frame_size(%d), pool_size(%d kB)\n",
3293 ioc->name, ioc->chain_depth, ioc->request_sz,
3294 ((ioc->chain_depth * ioc->request_sz))/1024));
3295
3296 /* initialize hi-priority queue smid's */
3297 ioc->hpr_lookup = kcalloc(ioc->hi_priority_depth,
3298 sizeof(struct request_tracker), GFP_KERNEL);
3299 if (!ioc->hpr_lookup) {
3300 pr_err(MPT3SAS_FMT "hpr_lookup: kcalloc failed\n",
3301 ioc->name);
3302 goto out;
3303 }
3304 ioc->hi_priority_smid = ioc->scsiio_depth + 1;
3305 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3306 "hi_priority(0x%p): depth(%d), start smid(%d)\n",
3307 ioc->name, ioc->hi_priority,
3308 ioc->hi_priority_depth, ioc->hi_priority_smid));
3309
3310 /* initialize internal queue smid's */
3311 ioc->internal_lookup = kcalloc(ioc->internal_depth,
3312 sizeof(struct request_tracker), GFP_KERNEL);
3313 if (!ioc->internal_lookup) {
3314 pr_err(MPT3SAS_FMT "internal_lookup: kcalloc failed\n",
3315 ioc->name);
3316 goto out;
3317 }
3318 ioc->internal_smid = ioc->hi_priority_smid + ioc->hi_priority_depth;
3319 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3320 "internal(0x%p): depth(%d), start smid(%d)\n",
3321 ioc->name, ioc->internal,
3322 ioc->internal_depth, ioc->internal_smid));
3323
3324 /* sense buffers, 4 byte align */
3325 sz = ioc->scsiio_depth * SCSI_SENSE_BUFFERSIZE;
3326 ioc->sense_dma_pool = pci_pool_create("sense pool", ioc->pdev, sz, 4,
3327 0);
3328 if (!ioc->sense_dma_pool) {
3329 pr_err(MPT3SAS_FMT "sense pool: pci_pool_create failed\n",
3330 ioc->name);
3331 goto out;
3332 }
3333 ioc->sense = pci_pool_alloc(ioc->sense_dma_pool , GFP_KERNEL,
3334 &ioc->sense_dma);
3335 if (!ioc->sense) {
3336 pr_err(MPT3SAS_FMT "sense pool: pci_pool_alloc failed\n",
3337 ioc->name);
3338 goto out;
3339 }
3340 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3341 "sense pool(0x%p): depth(%d), element_size(%d), pool_size"
3342 "(%d kB)\n", ioc->name, ioc->sense, ioc->scsiio_depth,
3343 SCSI_SENSE_BUFFERSIZE, sz/1024));
3344 dinitprintk(ioc, pr_info(MPT3SAS_FMT "sense_dma(0x%llx)\n",
3345 ioc->name, (unsigned long long)ioc->sense_dma));
3346 total_sz += sz;
3347
3348 /* reply pool, 4 byte align */
3349 sz = ioc->reply_free_queue_depth * ioc->reply_sz;
3350 ioc->reply_dma_pool = pci_pool_create("reply pool", ioc->pdev, sz, 4,
3351 0);
3352 if (!ioc->reply_dma_pool) {
3353 pr_err(MPT3SAS_FMT "reply pool: pci_pool_create failed\n",
3354 ioc->name);
3355 goto out;
3356 }
3357 ioc->reply = pci_pool_alloc(ioc->reply_dma_pool , GFP_KERNEL,
3358 &ioc->reply_dma);
3359 if (!ioc->reply) {
3360 pr_err(MPT3SAS_FMT "reply pool: pci_pool_alloc failed\n",
3361 ioc->name);
3362 goto out;
3363 }
3364 ioc->reply_dma_min_address = (u32)(ioc->reply_dma);
3365 ioc->reply_dma_max_address = (u32)(ioc->reply_dma) + sz;
3366 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3367 "reply pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n",
3368 ioc->name, ioc->reply,
3369 ioc->reply_free_queue_depth, ioc->reply_sz, sz/1024));
3370 dinitprintk(ioc, pr_info(MPT3SAS_FMT "reply_dma(0x%llx)\n",
3371 ioc->name, (unsigned long long)ioc->reply_dma));
3372 total_sz += sz;
3373
3374 /* reply free queue, 16 byte align */
3375 sz = ioc->reply_free_queue_depth * 4;
3376 ioc->reply_free_dma_pool = pci_pool_create("reply_free pool",
3377 ioc->pdev, sz, 16, 0);
3378 if (!ioc->reply_free_dma_pool) {
3379 pr_err(MPT3SAS_FMT "reply_free pool: pci_pool_create failed\n",
3380 ioc->name);
3381 goto out;
3382 }
3383 ioc->reply_free = pci_pool_alloc(ioc->reply_free_dma_pool , GFP_KERNEL,
3384 &ioc->reply_free_dma);
3385 if (!ioc->reply_free) {
3386 pr_err(MPT3SAS_FMT "reply_free pool: pci_pool_alloc failed\n",
3387 ioc->name);
3388 goto out;
3389 }
3390 memset(ioc->reply_free, 0, sz);
3391 dinitprintk(ioc, pr_info(MPT3SAS_FMT "reply_free pool(0x%p): " \
3392 "depth(%d), element_size(%d), pool_size(%d kB)\n", ioc->name,
3393 ioc->reply_free, ioc->reply_free_queue_depth, 4, sz/1024));
3394 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3395 "reply_free_dma (0x%llx)\n",
3396 ioc->name, (unsigned long long)ioc->reply_free_dma));
3397 total_sz += sz;
3398
f92363d1
SR		 3399 ioc->config_page_sz = 512;
3400 ioc->config_page = pci_alloc_consistent(ioc->pdev,
3401 ioc->config_page_sz, &ioc->config_page_dma);
3402 if (!ioc->config_page) {
3403 pr_err(MPT3SAS_FMT
3404 "config page: pci_pool_alloc failed\n",
3405 ioc->name);
3406 goto out;
3407 }
3408 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3409 "config page(0x%p): size(%d)\n",
3410 ioc->name, ioc->config_page, ioc->config_page_sz));
3411 dinitprintk(ioc, pr_info(MPT3SAS_FMT "config_page_dma(0x%llx)\n",
3412 ioc->name, (unsigned long long)ioc->config_page_dma));
3413 total_sz += ioc->config_page_sz;
3414
3415 pr_info(MPT3SAS_FMT "Allocated physical memory: size(%d kB)\n",
3416 ioc->name, total_sz/1024);
3417 pr_info(MPT3SAS_FMT
3418 "Current Controller Queue Depth(%d),Max Controller Queue Depth(%d)\n",
3419 ioc->name, ioc->shost->can_queue, facts->RequestCredit);
3420 pr_info(MPT3SAS_FMT "Scatter Gather Elements per IO(%d)\n",
3421 ioc->name, ioc->shost->sg_tablesize);
3422 return 0;
3423
3424 out:
3425 return -ENOMEM;
3426}
3427
3428/**
3429 * mpt3sas_base_get_iocstate - Get the current state of a MPT adapter.
3430 * @ioc: Pointer to MPT_ADAPTER structure
3431 * @cooked: Request raw or cooked IOC state
3432 *
3433 * Returns all IOC Doorbell register bits if cooked==0, else just the
3434 * Doorbell bits in MPI_IOC_STATE_MASK.
3435 */
3436u32
3437mpt3sas_base_get_iocstate(struct MPT3SAS_ADAPTER *ioc, int cooked)
3438{
3439 u32 s, sc;
3440
3441 s = readl(&ioc->chip->Doorbell);
3442 sc = s & MPI2_IOC_STATE_MASK;
3443 return cooked ? sc : s;
3444}
3445
3446/**
3447 * _base_wait_on_iocstate - waiting on a particular ioc state
3448 * @ioc_state: controller state { READY, OPERATIONAL, or RESET }
3449 * @timeout: timeout in second
3450 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3451 *
3452 * Returns 0 for success, non-zero for failure.
3453 */
3454static int
3455_base_wait_on_iocstate(struct MPT3SAS_ADAPTER *ioc, u32 ioc_state, int timeout,
3456 int sleep_flag)
3457{
3458 u32 count, cntdn;
3459 u32 current_state;
3460
3461 count = 0;
3462 cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
3463 do {
3464 current_state = mpt3sas_base_get_iocstate(ioc, 1);
3465 if (current_state == ioc_state)
3466 return 0;
3467 if (count && current_state == MPI2_IOC_STATE_FAULT)
3468 break;
3469 if (sleep_flag == CAN_SLEEP)
3470 usleep_range(1000, 1500);
3471 else
3472 udelay(500);
3473 count++;
3474 } while (--cntdn);
3475
3476 return current_state;
3477}
3478
3479/**
3480 * _base_wait_for_doorbell_int - waiting for controller interrupt(generated by
3481 * a write to the doorbell)
3482 * @ioc: per adapter object
3483 * @timeout: timeout in second
3484 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3485 *
3486 * Returns 0 for success, non-zero for failure.
3487 *
3488 * Notes: MPI2_HIS_IOC2SYS_DB_STATUS - set to one when IOC writes to doorbell.
3489 */
4dc8c808
SR		 3490static int
3491_base_diag_reset(struct MPT3SAS_ADAPTER *ioc, int sleep_flag);
3492
f92363d1
SR		 3493static int
3494_base_wait_for_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout,
3495 int sleep_flag)
3496{
3497 u32 cntdn, count;
3498 u32 int_status;
3499
3500 count = 0;
3501 cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
3502 do {
3503 int_status = readl(&ioc->chip->HostInterruptStatus);
3504 if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
3505 dhsprintk(ioc, pr_info(MPT3SAS_FMT
3506 "%s: successful count(%d), timeout(%d)\n",
3507 ioc->name, __func__, count, timeout));
3508 return 0;
3509 }
3510 if (sleep_flag == CAN_SLEEP)
3511 usleep_range(1000, 1500);
3512 else
3513 udelay(500);
3514 count++;
3515 } while (--cntdn);
3516
3517 pr_err(MPT3SAS_FMT
3518 "%s: failed due to timeout count(%d), int_status(%x)!\n",
3519 ioc->name, __func__, count, int_status);
3520 return -EFAULT;
3521}
3522
3523/**
3524 * _base_wait_for_doorbell_ack - waiting for controller to read the doorbell.
3525 * @ioc: per adapter object
3526 * @timeout: timeout in second
3527 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3528 *
3529 * Returns 0 for success, non-zero for failure.
3530 *
3531 * Notes: MPI2_HIS_SYS2IOC_DB_STATUS - set to one when host writes to
3532 * doorbell.
3533 */
3534static int
3535_base_wait_for_doorbell_ack(struct MPT3SAS_ADAPTER *ioc, int timeout,
3536 int sleep_flag)
3537{
3538 u32 cntdn, count;
3539 u32 int_status;
3540 u32 doorbell;
3541
3542 count = 0;
3543 cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
3544 do {
3545 int_status = readl(&ioc->chip->HostInterruptStatus);
3546 if (!(int_status & MPI2_HIS_SYS2IOC_DB_STATUS)) {
3547 dhsprintk(ioc, pr_info(MPT3SAS_FMT
3548 "%s: successful count(%d), timeout(%d)\n",
3549 ioc->name, __func__, count, timeout));
3550 return 0;
3551 } else if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
3552 doorbell = readl(&ioc->chip->Doorbell);
3553 if ((doorbell & MPI2_IOC_STATE_MASK) ==
3554 MPI2_IOC_STATE_FAULT) {
3555 mpt3sas_base_fault_info(ioc , doorbell);
3556 return -EFAULT;
3557 }
3558 } else if (int_status == 0xFFFFFFFF)
3559 goto out;
3560
3561 if (sleep_flag == CAN_SLEEP)
3562 usleep_range(1000, 1500);
3563 else
3564 udelay(500);
3565 count++;
3566 } while (--cntdn);
3567
3568 out:
3569 pr_err(MPT3SAS_FMT
3570 "%s: failed due to timeout count(%d), int_status(%x)!\n",
3571 ioc->name, __func__, count, int_status);
3572 return -EFAULT;
3573}
3574
3575/**
3576 * _base_wait_for_doorbell_not_used - waiting for doorbell to not be in use
3577 * @ioc: per adapter object
3578 * @timeout: timeout in second
3579 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3580 *
3581 * Returns 0 for success, non-zero for failure.
3582 *
3583 */
3584static int
3585_base_wait_for_doorbell_not_used(struct MPT3SAS_ADAPTER *ioc, int timeout,
3586 int sleep_flag)
3587{
3588 u32 cntdn, count;
3589 u32 doorbell_reg;
3590
3591 count = 0;
3592 cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
3593 do {
3594 doorbell_reg = readl(&ioc->chip->Doorbell);
3595 if (!(doorbell_reg & MPI2_DOORBELL_USED)) {
3596 dhsprintk(ioc, pr_info(MPT3SAS_FMT
3597 "%s: successful count(%d), timeout(%d)\n",
3598 ioc->name, __func__, count, timeout));
3599 return 0;
3600 }
3601 if (sleep_flag == CAN_SLEEP)
3602 usleep_range(1000, 1500);
3603 else
3604 udelay(500);
3605 count++;
3606 } while (--cntdn);
3607
3608 pr_err(MPT3SAS_FMT
3609 "%s: failed due to timeout count(%d), doorbell_reg(%x)!\n",
3610 ioc->name, __func__, count, doorbell_reg);
3611 return -EFAULT;
3612}
3613
3614/**
3615 * _base_send_ioc_reset - send doorbell reset
3616 * @ioc: per adapter object
3617 * @reset_type: currently only supports: MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET
3618 * @timeout: timeout in second
3619 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3620 *
3621 * Returns 0 for success, non-zero for failure.
3622 */
3623static int
3624_base_send_ioc_reset(struct MPT3SAS_ADAPTER *ioc, u8 reset_type, int timeout,
3625 int sleep_flag)
3626{
3627 u32 ioc_state;
3628 int r = 0;
3629
3630 if (reset_type != MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET) {
3631 pr_err(MPT3SAS_FMT "%s: unknown reset_type\n",
3632 ioc->name, __func__);
3633 return -EFAULT;
3634 }
3635
3636 if (!(ioc->facts.IOCCapabilities &
3637 MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY))
3638 return -EFAULT;
3639
3640 pr_info(MPT3SAS_FMT "sending message unit reset !!\n", ioc->name);
3641
3642 writel(reset_type << MPI2_DOORBELL_FUNCTION_SHIFT,
3643 &ioc->chip->Doorbell);
3644 if ((_base_wait_for_doorbell_ack(ioc, 15, sleep_flag))) {
3645 r = -EFAULT;
3646 goto out;
3647 }
3648 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY,
3649 timeout, sleep_flag);
3650 if (ioc_state) {
3651 pr_err(MPT3SAS_FMT
3652 "%s: failed going to ready state (ioc_state=0x%x)\n",
3653 ioc->name, __func__, ioc_state);
3654 r = -EFAULT;
3655 goto out;
3656 }
3657 out:
3658 pr_info(MPT3SAS_FMT "message unit reset: %s\n",
3659 ioc->name, ((r == 0) ? "SUCCESS" : "FAILED"));
3660 return r;
3661}
3662
3663/**
3664 * _base_handshake_req_reply_wait - send request thru doorbell interface
3665 * @ioc: per adapter object
3666 * @request_bytes: request length
3667 * @request: pointer having request payload
3668 * @reply_bytes: reply length
3669 * @reply: pointer to reply payload
3670 * @timeout: timeout in second
3671 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3672 *
3673 * Returns 0 for success, non-zero for failure.
3674 */
3675static int
3676_base_handshake_req_reply_wait(struct MPT3SAS_ADAPTER *ioc, int request_bytes,
3677 u32 *request, int reply_bytes, u16 *reply, int timeout, int sleep_flag)
3678{
3679 MPI2DefaultReply_t *default_reply = (MPI2DefaultReply_t *)reply;
3680 int i;
3681 u8 failed;
3682 u16 dummy;
3683 __le32 *mfp;
3684
3685 /* make sure doorbell is not in use */
3686 if ((readl(&ioc->chip->Doorbell) & MPI2_DOORBELL_USED)) {
3687 pr_err(MPT3SAS_FMT
3688 "doorbell is in use (line=%d)\n",
3689 ioc->name, __LINE__);
3690 return -EFAULT;
3691 }
3692
3693 /* clear pending doorbell interrupts from previous state changes */
3694 if (readl(&ioc->chip->HostInterruptStatus) &
3695 MPI2_HIS_IOC2SYS_DB_STATUS)
3696 writel(0, &ioc->chip->HostInterruptStatus);
3697
3698 /* send message to ioc */
3699 writel(((MPI2_FUNCTION_HANDSHAKE<<MPI2_DOORBELL_FUNCTION_SHIFT) |
3700 ((request_bytes/4)<<MPI2_DOORBELL_ADD_DWORDS_SHIFT)),
3701 &ioc->chip->Doorbell);
3702
3703 if ((_base_wait_for_doorbell_int(ioc, 5, NO_SLEEP))) {
3704 pr_err(MPT3SAS_FMT
3705 "doorbell handshake int failed (line=%d)\n",
3706 ioc->name, __LINE__);
3707 return -EFAULT;
3708 }
3709 writel(0, &ioc->chip->HostInterruptStatus);
3710
3711 if ((_base_wait_for_doorbell_ack(ioc, 5, sleep_flag))) {
3712 pr_err(MPT3SAS_FMT
3713 "doorbell handshake ack failed (line=%d)\n",
3714 ioc->name, __LINE__);
3715 return -EFAULT;
3716 }
3717
3718 /* send message 32-bits at a time */
3719 for (i = 0, failed = 0; i < request_bytes/4 && !failed; i++) {
3720 writel(cpu_to_le32(request[i]), &ioc->chip->Doorbell);
3721 if ((_base_wait_for_doorbell_ack(ioc, 5, sleep_flag)))
3722 failed = 1;
3723 }
3724
3725 if (failed) {
3726 pr_err(MPT3SAS_FMT
3727 "doorbell handshake sending request failed (line=%d)\n",
3728 ioc->name, __LINE__);
3729 return -EFAULT;
3730 }
3731
3732 /* now wait for the reply */
3733 if ((_base_wait_for_doorbell_int(ioc, timeout, sleep_flag))) {
3734 pr_err(MPT3SAS_FMT
3735 "doorbell handshake int failed (line=%d)\n",
3736 ioc->name, __LINE__);
3737 return -EFAULT;
3738 }
3739
3740 /* read the first two 16-bits, it gives the total length of the reply */
3741 reply[0] = le16_to_cpu(readl(&ioc->chip->Doorbell)
3742 & MPI2_DOORBELL_DATA_MASK);
3743 writel(0, &ioc->chip->HostInterruptStatus);
3744 if ((_base_wait_for_doorbell_int(ioc, 5, sleep_flag))) {
3745 pr_err(MPT3SAS_FMT
3746 "doorbell handshake int failed (line=%d)\n",
3747 ioc->name, __LINE__);
3748 return -EFAULT;
3749 }
3750 reply[1] = le16_to_cpu(readl(&ioc->chip->Doorbell)
3751 & MPI2_DOORBELL_DATA_MASK);
3752 writel(0, &ioc->chip->HostInterruptStatus);
3753
3754 for (i = 2; i < default_reply->MsgLength * 2; i++) {
3755 if ((_base_wait_for_doorbell_int(ioc, 5, sleep_flag))) {
3756 pr_err(MPT3SAS_FMT
3757 "doorbell handshake int failed (line=%d)\n",
3758 ioc->name, __LINE__);
3759 return -EFAULT;
3760 }
3761 if (i >= reply_bytes/2) /* overflow case */
3762 dummy = readl(&ioc->chip->Doorbell);
3763 else
3764 reply[i] = le16_to_cpu(readl(&ioc->chip->Doorbell)
3765 & MPI2_DOORBELL_DATA_MASK);
3766 writel(0, &ioc->chip->HostInterruptStatus);
3767 }
3768
3769 _base_wait_for_doorbell_int(ioc, 5, sleep_flag);
3770 if (_base_wait_for_doorbell_not_used(ioc, 5, sleep_flag) != 0) {
3771 dhsprintk(ioc, pr_info(MPT3SAS_FMT
3772 "doorbell is in use (line=%d)\n", ioc->name, __LINE__));
3773 }
3774 writel(0, &ioc->chip->HostInterruptStatus);
3775
3776 if (ioc->logging_level & MPT_DEBUG_INIT) {
3777 mfp = (__le32 *)reply;
3778 pr_info("\toffset:data\n");
3779 for (i = 0; i < reply_bytes/4; i++)
3780 pr_info("\t[0x%02x]:%08x\n", i*4,
3781 le32_to_cpu(mfp[i]));
3782 }
3783 return 0;
3784}
3785
3786/**
3787 * mpt3sas_base_sas_iounit_control - send sas iounit control to FW
3788 * @ioc: per adapter object
3789 * @mpi_reply: the reply payload from FW
3790 * @mpi_request: the request payload sent to FW
3791 *
3792 * The SAS IO Unit Control Request message allows the host to perform low-level
3793 * operations, such as resets on the PHYs of the IO Unit, also allows the host
3794 * to obtain the IOC assigned device handles for a device if it has other
3795 * identifying information about the device, in addition allows the host to
3796 * remove IOC resources associated with the device.
3797 *
3798 * Returns 0 for success, non-zero for failure.
3799 */
3800int
3801mpt3sas_base_sas_iounit_control(struct MPT3SAS_ADAPTER *ioc,
3802 Mpi2SasIoUnitControlReply_t *mpi_reply,
3803 Mpi2SasIoUnitControlRequest_t *mpi_request)
3804{
3805 u16 smid;
3806 u32 ioc_state;
3807 unsigned long timeleft;
eb44552b 3808 bool issue_reset = false;
f92363d1
SR		 3809 int rc;
3810 void *request;
3811 u16 wait_state_count;
3812
3813 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3814 __func__));
3815
3816 mutex_lock(&ioc->base_cmds.mutex);
3817
3818 if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) {
3819 pr_err(MPT3SAS_FMT "%s: base_cmd in use\n",
3820 ioc->name, __func__);
3821 rc = -EAGAIN;
3822 goto out;
3823 }
3824
3825 wait_state_count = 0;
3826 ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
3827 while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) {
3828 if (wait_state_count++ == 10) {
3829 pr_err(MPT3SAS_FMT
3830 "%s: failed due to ioc not operational\n",
3831 ioc->name, __func__);
3832 rc = -EFAULT;
3833 goto out;
3834 }
3835 ssleep(1);
3836 ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
3837 pr_info(MPT3SAS_FMT
3838 "%s: waiting for operational state(count=%d)\n",
3839 ioc->name, __func__, wait_state_count);
3840 }
3841
3842 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
3843 if (!smid) {
3844 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
3845 ioc->name, __func__);
3846 rc = -EAGAIN;
3847 goto out;
3848 }
3849
3850 rc = 0;
3851 ioc->base_cmds.status = MPT3_CMD_PENDING;
3852 request = mpt3sas_base_get_msg_frame(ioc, smid);
3853 ioc->base_cmds.smid = smid;
3854 memcpy(request, mpi_request, sizeof(Mpi2SasIoUnitControlRequest_t));
3855 if (mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
3856 mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET)
3857 ioc->ioc_link_reset_in_progress = 1;
3858 init_completion(&ioc->base_cmds.done);
3859 mpt3sas_base_put_smid_default(ioc, smid);
3860 timeleft = wait_for_completion_timeout(&ioc->base_cmds.done,
3861 msecs_to_jiffies(10000));
3862 if ((mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
3863 mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET) &&
3864 ioc->ioc_link_reset_in_progress)
3865 ioc->ioc_link_reset_in_progress = 0;
3866 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
3867 pr_err(MPT3SAS_FMT "%s: timeout\n",
3868 ioc->name, __func__);
3869 _debug_dump_mf(mpi_request,
3870 sizeof(Mpi2SasIoUnitControlRequest_t)/4);
3871 if (!(ioc->base_cmds.status & MPT3_CMD_RESET))
eb44552b 3872 issue_reset = true;
f92363d1
SR		 3873 goto issue_host_reset;
3874 }
3875 if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID)
3876 memcpy(mpi_reply, ioc->base_cmds.reply,
3877 sizeof(Mpi2SasIoUnitControlReply_t));
3878 else
3879 memset(mpi_reply, 0, sizeof(Mpi2SasIoUnitControlReply_t));
3880 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
3881 goto out;
3882
3883 issue_host_reset:
3884 if (issue_reset)
3885 mpt3sas_base_hard_reset_handler(ioc, CAN_SLEEP,
3886 FORCE_BIG_HAMMER);
3887 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
3888 rc = -EFAULT;
3889 out:
3890 mutex_unlock(&ioc->base_cmds.mutex);
3891 return rc;
3892}
3893
3894/**
3895 * mpt3sas_base_scsi_enclosure_processor - sending request to sep device
3896 * @ioc: per adapter object
3897 * @mpi_reply: the reply payload from FW
3898 * @mpi_request: the request payload sent to FW
3899 *
3900 * The SCSI Enclosure Processor request message causes the IOC to
3901 * communicate with SES devices to control LED status signals.
3902 *
3903 * Returns 0 for success, non-zero for failure.
3904 */
3905int
3906mpt3sas_base_scsi_enclosure_processor(struct MPT3SAS_ADAPTER *ioc,
3907 Mpi2SepReply_t *mpi_reply, Mpi2SepRequest_t *mpi_request)
3908{
3909 u16 smid;
3910 u32 ioc_state;
3911 unsigned long timeleft;
eb44552b 3912 bool issue_reset = false;
f92363d1
SR		 3913 int rc;
3914 void *request;
3915 u16 wait_state_count;
3916
3917 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3918 __func__));
3919
3920 mutex_lock(&ioc->base_cmds.mutex);
3921
3922 if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) {
3923 pr_err(MPT3SAS_FMT "%s: base_cmd in use\n",
3924 ioc->name, __func__);
3925 rc = -EAGAIN;
3926 goto out;
3927 }
3928
3929 wait_state_count = 0;
3930 ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
3931 while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) {
3932 if (wait_state_count++ == 10) {
3933 pr_err(MPT3SAS_FMT
3934 "%s: failed due to ioc not operational\n",
3935 ioc->name, __func__);
3936 rc = -EFAULT;
3937 goto out;
3938 }
3939 ssleep(1);
3940 ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
3941 pr_info(MPT3SAS_FMT
3942 "%s: waiting for operational state(count=%d)\n",
3943 ioc->name,
3944 __func__, wait_state_count);
3945 }
3946
3947 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
3948 if (!smid) {
3949 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
3950 ioc->name, __func__);
3951 rc = -EAGAIN;
3952 goto out;
3953 }
3954
3955 rc = 0;
3956 ioc->base_cmds.status = MPT3_CMD_PENDING;
3957 request = mpt3sas_base_get_msg_frame(ioc, smid);
3958 ioc->base_cmds.smid = smid;
3959 memcpy(request, mpi_request, sizeof(Mpi2SepReply_t));
3960 init_completion(&ioc->base_cmds.done);
3961 mpt3sas_base_put_smid_default(ioc, smid);
3962 timeleft = wait_for_completion_timeout(&ioc->base_cmds.done,
3963 msecs_to_jiffies(10000));
3964 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
3965 pr_err(MPT3SAS_FMT "%s: timeout\n",
3966 ioc->name, __func__);
3967 _debug_dump_mf(mpi_request,
3968 sizeof(Mpi2SepRequest_t)/4);
3969 if (!(ioc->base_cmds.status & MPT3_CMD_RESET))
eb44552b 3970 issue_reset = false;
f92363d1
SR		 3971 goto issue_host_reset;
3972 }
3973 if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID)
3974 memcpy(mpi_reply, ioc->base_cmds.reply,
3975 sizeof(Mpi2SepReply_t));
3976 else
3977 memset(mpi_reply, 0, sizeof(Mpi2SepReply_t));
3978 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
3979 goto out;
3980
3981 issue_host_reset:
3982 if (issue_reset)
3983 mpt3sas_base_hard_reset_handler(ioc, CAN_SLEEP,
3984 FORCE_BIG_HAMMER);
3985 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
3986 rc = -EFAULT;
3987 out:
3988 mutex_unlock(&ioc->base_cmds.mutex);
3989 return rc;
3990}
3991
3992/**
3993 * _base_get_port_facts - obtain port facts reply and save in ioc
3994 * @ioc: per adapter object
3995 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3996 *
3997 * Returns 0 for success, non-zero for failure.
3998 */
3999static int
4000_base_get_port_facts(struct MPT3SAS_ADAPTER *ioc, int port, int sleep_flag)
4001{
4002 Mpi2PortFactsRequest_t mpi_request;
4003 Mpi2PortFactsReply_t mpi_reply;
4004 struct mpt3sas_port_facts *pfacts;
4005 int mpi_reply_sz, mpi_request_sz, r;
4006
4007 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4008 __func__));
4009
4010 mpi_reply_sz = sizeof(Mpi2PortFactsReply_t);
4011 mpi_request_sz = sizeof(Mpi2PortFactsRequest_t);
4012 memset(&mpi_request, 0, mpi_request_sz);
4013 mpi_request.Function = MPI2_FUNCTION_PORT_FACTS;
4014 mpi_request.PortNumber = port;
4015 r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
4016 (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5, CAN_SLEEP);
4017
4018 if (r != 0) {
4019 pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
4020 ioc->name, __func__, r);
4021 return r;
4022 }
4023
4024 pfacts = &ioc->pfacts[port];
4025 memset(pfacts, 0, sizeof(struct mpt3sas_port_facts));
4026 pfacts->PortNumber = mpi_reply.PortNumber;
4027 pfacts->VP_ID = mpi_reply.VP_ID;
4028 pfacts->VF_ID = mpi_reply.VF_ID;
4029 pfacts->MaxPostedCmdBuffers =
4030 le16_to_cpu(mpi_reply.MaxPostedCmdBuffers);
4031
4032 return 0;
4033}
4034
4dc8c808
SR		 4035/**
4036 * _base_wait_for_iocstate - Wait until the card is in READY or OPERATIONAL
4037 * @ioc: per adapter object
4038 * @timeout:
4039 * @sleep_flag: CAN_SLEEP or NO_SLEEP
4040 *
4041 * Returns 0 for success, non-zero for failure.
4042 */
4043static int
4044_base_wait_for_iocstate(struct MPT3SAS_ADAPTER *ioc, int timeout,
4045 int sleep_flag)
4046{
4047 u32 ioc_state;
4048 int rc;
4049
4050 dinitprintk(ioc, printk(MPT3SAS_FMT "%s\n", ioc->name,
4051 __func__));
4052
4053 if (ioc->pci_error_recovery) {
4054 dfailprintk(ioc, printk(MPT3SAS_FMT
4055 "%s: host in pci error recovery\n", ioc->name, __func__));
4056 return -EFAULT;
4057 }
4058
4059 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
4060 dhsprintk(ioc, printk(MPT3SAS_FMT "%s: ioc_state(0x%08x)\n",
4061 ioc->name, __func__, ioc_state));
4062
4063 if (((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY) ||
4064 (ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL)
4065 return 0;
4066
4067 if (ioc_state & MPI2_DOORBELL_USED) {
4068 dhsprintk(ioc, printk(MPT3SAS_FMT
4069 "unexpected doorbell active!\n", ioc->name));
4070 goto issue_diag_reset;
4071 }
4072
4073 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
4074 mpt3sas_base_fault_info(ioc, ioc_state &
4075 MPI2_DOORBELL_DATA_MASK);
4076 goto issue_diag_reset;
4077 }
4078
4079 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY,
4080 timeout, sleep_flag);
4081 if (ioc_state) {
4082 dfailprintk(ioc, printk(MPT3SAS_FMT
4083 "%s: failed going to ready state (ioc_state=0x%x)\n",
4084 ioc->name, __func__, ioc_state));
4085 return -EFAULT;
4086 }
4087
4088 issue_diag_reset:
4089 rc = _base_diag_reset(ioc, sleep_flag);
4090 return rc;
4091}
4092
f92363d1
SR		 4093/**
4094 * _base_get_ioc_facts - obtain ioc facts reply and save in ioc
4095 * @ioc: per adapter object
4096 * @sleep_flag: CAN_SLEEP or NO_SLEEP
4097 *
4098 * Returns 0 for success, non-zero for failure.
4099 */
4100static int
4101_base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
4102{
4103 Mpi2IOCFactsRequest_t mpi_request;
4104 Mpi2IOCFactsReply_t mpi_reply;
4105 struct mpt3sas_facts *facts;
4106 int mpi_reply_sz, mpi_request_sz, r;
4107
4108 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4109 __func__));
4110
4dc8c808
SR		 4111 r = _base_wait_for_iocstate(ioc, 10, sleep_flag);
4112 if (r) {
4113 dfailprintk(ioc, printk(MPT3SAS_FMT
4114 "%s: failed getting to correct state\n",
4115 ioc->name, __func__));
4116 return r;
4117 }
f92363d1
SR		 4118 mpi_reply_sz = sizeof(Mpi2IOCFactsReply_t);
4119 mpi_request_sz = sizeof(Mpi2IOCFactsRequest_t);
4120 memset(&mpi_request, 0, mpi_request_sz);
4121 mpi_request.Function = MPI2_FUNCTION_IOC_FACTS;
4122 r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
4123 (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5, CAN_SLEEP);
4124
4125 if (r != 0) {
4126 pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
4127 ioc->name, __func__, r);
4128 return r;
4129 }
4130
4131 facts = &ioc->facts;
4132 memset(facts, 0, sizeof(struct mpt3sas_facts));
4133 facts->MsgVersion = le16_to_cpu(mpi_reply.MsgVersion);
4134 facts->HeaderVersion = le16_to_cpu(mpi_reply.HeaderVersion);
4135 facts->VP_ID = mpi_reply.VP_ID;
4136 facts->VF_ID = mpi_reply.VF_ID;
4137 facts->IOCExceptions = le16_to_cpu(mpi_reply.IOCExceptions);
4138 facts->MaxChainDepth = mpi_reply.MaxChainDepth;
4139 facts->WhoInit = mpi_reply.WhoInit;
4140 facts->NumberOfPorts = mpi_reply.NumberOfPorts;
4141 facts->MaxMSIxVectors = mpi_reply.MaxMSIxVectors;
4142 facts->RequestCredit = le16_to_cpu(mpi_reply.RequestCredit);
4143 facts->MaxReplyDescriptorPostQueueDepth =
4144 le16_to_cpu(mpi_reply.MaxReplyDescriptorPostQueueDepth);
4145 facts->ProductID = le16_to_cpu(mpi_reply.ProductID);
4146 facts->IOCCapabilities = le32_to_cpu(mpi_reply.IOCCapabilities);
4147 if ((facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID))
4148 ioc->ir_firmware = 1;
9b05c91a
SR		 4149 if ((facts->IOCCapabilities &
4150 MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE))
4151 ioc->rdpq_array_capable = 1;
f92363d1
SR		 4152 facts->FWVersion.Word = le32_to_cpu(mpi_reply.FWVersion.Word);
4153 facts->IOCRequestFrameSize =
4154 le16_to_cpu(mpi_reply.IOCRequestFrameSize);
4155 facts->MaxInitiators = le16_to_cpu(mpi_reply.MaxInitiators);
4156 facts->MaxTargets = le16_to_cpu(mpi_reply.MaxTargets);
4157 ioc->shost->max_id = -1;
4158 facts->MaxSasExpanders = le16_to_cpu(mpi_reply.MaxSasExpanders);
4159 facts->MaxEnclosures = le16_to_cpu(mpi_reply.MaxEnclosures);
4160 facts->ProtocolFlags = le16_to_cpu(mpi_reply.ProtocolFlags);
4161 facts->HighPriorityCredit =
4162 le16_to_cpu(mpi_reply.HighPriorityCredit);
4163 facts->ReplyFrameSize = mpi_reply.ReplyFrameSize;
4164 facts->MaxDevHandle = le16_to_cpu(mpi_reply.MaxDevHandle);
4165
4166 dinitprintk(ioc, pr_info(MPT3SAS_FMT
4167 "hba queue depth(%d), max chains per io(%d)\n",
4168 ioc->name, facts->RequestCredit,
4169 facts->MaxChainDepth));
4170 dinitprintk(ioc, pr_info(MPT3SAS_FMT
4171 "request frame size(%d), reply frame size(%d)\n", ioc->name,
4172 facts->IOCRequestFrameSize * 4, facts->ReplyFrameSize * 4));
4173 return 0;
4174}
4175
4176/**
4177 * _base_send_ioc_init - send ioc_init to firmware
4178 * @ioc: per adapter object
4179 * @sleep_flag: CAN_SLEEP or NO_SLEEP
4180 *
4181 * Returns 0 for success, non-zero for failure.
4182 */
4183static int
4184_base_send_ioc_init(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
4185{
4186 Mpi2IOCInitRequest_t mpi_request;
4187 Mpi2IOCInitReply_t mpi_reply;
9b05c91a 4188 int i, r = 0;
f92363d1
SR		 4189 struct timeval current_time;
4190 u16 ioc_status;
9b05c91a
SR		 4191 u32 reply_post_free_array_sz = 0;
4192 Mpi2IOCInitRDPQArrayEntry *reply_post_free_array = NULL;
4193 dma_addr_t reply_post_free_array_dma;
f92363d1
SR		 4194
4195 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4196 __func__));
4197
4198 memset(&mpi_request, 0, sizeof(Mpi2IOCInitRequest_t));
4199 mpi_request.Function = MPI2_FUNCTION_IOC_INIT;
4200 mpi_request.WhoInit = MPI2_WHOINIT_HOST_DRIVER;
4201 mpi_request.VF_ID = 0; /* TODO */
4202 mpi_request.VP_ID = 0;
d357e84d 4203 mpi_request.MsgVersion = cpu_to_le16(ioc->hba_mpi_version_belonged);
f92363d1
SR		 4204 mpi_request.HeaderVersion = cpu_to_le16(MPI2_HEADER_VERSION);
4205
4206 if (_base_is_controller_msix_enabled(ioc))
4207 mpi_request.HostMSIxVectors = ioc->reply_queue_count;
4208 mpi_request.SystemRequestFrameSize = cpu_to_le16(ioc->request_sz/4);
4209 mpi_request.ReplyDescriptorPostQueueDepth =
4210 cpu_to_le16(ioc->reply_post_queue_depth);
4211 mpi_request.ReplyFreeQueueDepth =
4212 cpu_to_le16(ioc->reply_free_queue_depth);
4213
4214 mpi_request.SenseBufferAddressHigh =
4215 cpu_to_le32((u64)ioc->sense_dma >> 32);
4216 mpi_request.SystemReplyAddressHigh =
4217 cpu_to_le32((u64)ioc->reply_dma >> 32);
4218 mpi_request.SystemRequestFrameBaseAddress =
4219 cpu_to_le64((u64)ioc->request_dma);
4220 mpi_request.ReplyFreeQueueAddress =
4221 cpu_to_le64((u64)ioc->reply_free_dma);
f92363d1 4222
9b05c91a
SR		 4223 if (ioc->rdpq_array_enable) {
4224 reply_post_free_array_sz = ioc->reply_queue_count *
4225 sizeof(Mpi2IOCInitRDPQArrayEntry);
4226 reply_post_free_array = pci_alloc_consistent(ioc->pdev,
4227 reply_post_free_array_sz, &reply_post_free_array_dma);
4228 if (!reply_post_free_array) {
4229 pr_err(MPT3SAS_FMT
4230 "reply_post_free_array: pci_alloc_consistent failed\n",
4231 ioc->name);
4232 r = -ENOMEM;
4233 goto out;
4234 }
4235 memset(reply_post_free_array, 0, reply_post_free_array_sz);
4236 for (i = 0; i < ioc->reply_queue_count; i++)
4237 reply_post_free_array[i].RDPQBaseAddress =
4238 cpu_to_le64(
4239 (u64)ioc->reply_post[i].reply_post_free_dma);
4240 mpi_request.MsgFlags = MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE;
4241 mpi_request.ReplyDescriptorPostQueueAddress =
4242 cpu_to_le64((u64)reply_post_free_array_dma);
4243 } else {
4244 mpi_request.ReplyDescriptorPostQueueAddress =
4245 cpu_to_le64((u64)ioc->reply_post[0].reply_post_free_dma);
4246 }
f92363d1
SR		 4247
4248 /* This time stamp specifies number of milliseconds
4249 * since epoch ~ midnight January 1, 1970.
4250 */
4251 do_gettimeofday(&current_time);
4252 mpi_request.TimeStamp = cpu_to_le64((u64)current_time.tv_sec * 1000 +
4253 (current_time.tv_usec / 1000));
4254
4255 if (ioc->logging_level & MPT_DEBUG_INIT) {
4256 __le32 *mfp;
4257 int i;
4258
4259 mfp = (__le32 *)&mpi_request;
4260 pr_info("\toffset:data\n");
4261 for (i = 0; i < sizeof(Mpi2IOCInitRequest_t)/4; i++)
4262 pr_info("\t[0x%02x]:%08x\n", i*4,
4263 le32_to_cpu(mfp[i]));
4264 }
4265
4266 r = _base_handshake_req_reply_wait(ioc,
4267 sizeof(Mpi2IOCInitRequest_t), (u32 *)&mpi_request,
4268 sizeof(Mpi2IOCInitReply_t), (u16 *)&mpi_reply, 10,
4269 sleep_flag);
4270
4271 if (r != 0) {
4272 pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
4273 ioc->name, __func__, r);
9b05c91a 4274 goto out;
f92363d1
SR		 4275 }
4276
4277 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & MPI2_IOCSTATUS_MASK;
4278 if (ioc_status != MPI2_IOCSTATUS_SUCCESS ||
4279 mpi_reply.IOCLogInfo) {
4280 pr_err(MPT3SAS_FMT "%s: failed\n", ioc->name, __func__);
4281 r = -EIO;
4282 }
4283
9b05c91a
SR		 4284out:
4285 if (reply_post_free_array)
4286 pci_free_consistent(ioc->pdev, reply_post_free_array_sz,
4287 reply_post_free_array,
4288 reply_post_free_array_dma);
4289 return r;
f92363d1
SR		 4290}
4291
4292/**
4293 * mpt3sas_port_enable_done - command completion routine for port enable
4294 * @ioc: per adapter object
4295 * @smid: system request message index
4296 * @msix_index: MSIX table index supplied by the OS
4297 * @reply: reply message frame(lower 32bit addr)
4298 *
4299 * Return 1 meaning mf should be freed from _base_interrupt
4300 * 0 means the mf is freed from this function.
4301 */
4302u8
4303mpt3sas_port_enable_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
4304 u32 reply)
4305{
4306 MPI2DefaultReply_t *mpi_reply;
4307 u16 ioc_status;
4308
4309 if (ioc->port_enable_cmds.status == MPT3_CMD_NOT_USED)
4310 return 1;
4311
4312 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
4313 if (!mpi_reply)
4314 return 1;
4315
4316 if (mpi_reply->Function != MPI2_FUNCTION_PORT_ENABLE)
4317 return 1;
4318
4319 ioc->port_enable_cmds.status &= ~MPT3_CMD_PENDING;
4320 ioc->port_enable_cmds.status |= MPT3_CMD_COMPLETE;
4321 ioc->port_enable_cmds.status |= MPT3_CMD_REPLY_VALID;
4322 memcpy(ioc->port_enable_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
4323 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK;
4324 if (ioc_status != MPI2_IOCSTATUS_SUCCESS)
4325 ioc->port_enable_failed = 1;
4326
4327 if (ioc->is_driver_loading) {
4328 if (ioc_status == MPI2_IOCSTATUS_SUCCESS) {
4329 mpt3sas_port_enable_complete(ioc);
4330 return 1;
4331 } else {
4332 ioc->start_scan_failed = ioc_status;
4333 ioc->start_scan = 0;
4334 return 1;
4335 }
4336 }
4337 complete(&ioc->port_enable_cmds.done);
4338 return 1;
4339}
4340
4341/**
4342 * _base_send_port_enable - send port_enable(discovery stuff) to firmware
4343 * @ioc: per adapter object
4344 * @sleep_flag: CAN_SLEEP or NO_SLEEP
4345 *
4346 * Returns 0 for success, non-zero for failure.
4347 */
4348static int
4349_base_send_port_enable(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
4350{
4351 Mpi2PortEnableRequest_t *mpi_request;
4352 Mpi2PortEnableReply_t *mpi_reply;
4353 unsigned long timeleft;
4354 int r = 0;
4355 u16 smid;
4356 u16 ioc_status;
4357
4358 pr_info(MPT3SAS_FMT "sending port enable !!\n", ioc->name);
4359
4360 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
4361 pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
4362 ioc->name, __func__);
4363 return -EAGAIN;
4364 }
4365
4366 smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
4367 if (!smid) {
4368 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4369 ioc->name, __func__);
4370 return -EAGAIN;
4371 }
4372
4373 ioc->port_enable_cmds.status = MPT3_CMD_PENDING;
4374 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
4375 ioc->port_enable_cmds.smid = smid;
4376 memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
4377 mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
4378
4379 init_completion(&ioc->port_enable_cmds.done);
4380 mpt3sas_base_put_smid_default(ioc, smid);
4381 timeleft = wait_for_completion_timeout(&ioc->port_enable_cmds.done,
4382 300*HZ);
4383 if (!(ioc->port_enable_cmds.status & MPT3_CMD_COMPLETE)) {
4384 pr_err(MPT3SAS_FMT "%s: timeout\n",
4385 ioc->name, __func__);
4386 _debug_dump_mf(mpi_request,
4387 sizeof(Mpi2PortEnableRequest_t)/4);
4388 if (ioc->port_enable_cmds.status & MPT3_CMD_RESET)
4389 r = -EFAULT;
4390 else
4391 r = -ETIME;
4392 goto out;
4393 }
4394
4395 mpi_reply = ioc->port_enable_cmds.reply;
4396 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK;
4397 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
4398 pr_err(MPT3SAS_FMT "%s: failed with (ioc_status=0x%08x)\n",
4399 ioc->name, __func__, ioc_status);
4400 r = -EFAULT;
4401 goto out;
4402 }
4403
4404 out:
4405 ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED;
4406 pr_info(MPT3SAS_FMT "port enable: %s\n", ioc->name, ((r == 0) ?
4407 "SUCCESS" : "FAILED"));
4408 return r;
4409}
4410
4411/**
4412 * mpt3sas_port_enable - initiate firmware discovery (don't wait for reply)
4413 * @ioc: per adapter object
4414 *
4415 * Returns 0 for success, non-zero for failure.
4416 */
4417int
4418mpt3sas_port_enable(struct MPT3SAS_ADAPTER *ioc)
4419{
4420 Mpi2PortEnableRequest_t *mpi_request;
4421 u16 smid;
4422
4423 pr_info(MPT3SAS_FMT "sending port enable !!\n", ioc->name);
4424
4425 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
4426 pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
4427 ioc->name, __func__);
4428 return -EAGAIN;
4429 }
4430
4431 smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
4432 if (!smid) {
4433 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4434 ioc->name, __func__);
4435 return -EAGAIN;
4436 }
4437
4438 ioc->port_enable_cmds.status = MPT3_CMD_PENDING;
4439 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
4440 ioc->port_enable_cmds.smid = smid;
4441 memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
4442 mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
4443
4444 mpt3sas_base_put_smid_default(ioc, smid);
4445 return 0;
4446}
4447
4448/**
4449 * _base_determine_wait_on_discovery - desposition
4450 * @ioc: per adapter object
4451 *
4452 * Decide whether to wait on discovery to complete. Used to either
4453 * locate boot device, or report volumes ahead of physical devices.
4454 *
4455 * Returns 1 for wait, 0 for don't wait
4456 */
4457static int
4458_base_determine_wait_on_discovery(struct MPT3SAS_ADAPTER *ioc)
4459{
4460 /* We wait for discovery to complete if IR firmware is loaded.
4461 * The sas topology events arrive before PD events, so we need time to
4462 * turn on the bit in ioc->pd_handles to indicate PD
4463 * Also, it maybe required to report Volumes ahead of physical
4464 * devices when MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING is set.
4465 */
4466 if (ioc->ir_firmware)
4467 return 1;
4468
4469 /* if no Bios, then we don't need to wait */
4470 if (!ioc->bios_pg3.BiosVersion)
4471 return 0;
4472
4473 /* Bios is present, then we drop down here.
4474 *
4475 * If there any entries in the Bios Page 2, then we wait
4476 * for discovery to complete.
4477 */
4478
4479 /* Current Boot Device */
4480 if ((ioc->bios_pg2.CurrentBootDeviceForm &
4481 MPI2_BIOSPAGE2_FORM_MASK) ==
4482 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED &&
4483 /* Request Boot Device */
4484 (ioc->bios_pg2.ReqBootDeviceForm &
4485 MPI2_BIOSPAGE2_FORM_MASK) ==
4486 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED &&
4487 /* Alternate Request Boot Device */
4488 (ioc->bios_pg2.ReqAltBootDeviceForm &
4489 MPI2_BIOSPAGE2_FORM_MASK) ==
4490 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED)
4491 return 0;
4492
4493 return 1;
4494}
4495
4496/**
4497 * _base_unmask_events - turn on notification for this event
4498 * @ioc: per adapter object
4499 * @event: firmware event
4500 *
4501 * The mask is stored in ioc->event_masks.
4502 */
4503static void
4504_base_unmask_events(struct MPT3SAS_ADAPTER *ioc, u16 event)
4505{
4506 u32 desired_event;
4507
4508 if (event >= 128)
4509 return;
4510
4511 desired_event = (1 << (event % 32));
4512
4513 if (event < 32)
4514 ioc->event_masks[0] &= ~desired_event;
4515 else if (event < 64)
4516 ioc->event_masks[1] &= ~desired_event;
4517 else if (event < 96)
4518 ioc->event_masks[2] &= ~desired_event;
4519 else if (event < 128)
4520 ioc->event_masks[3] &= ~desired_event;
4521}
4522
4523/**
4524 * _base_event_notification - send event notification
4525 * @ioc: per adapter object
4526 * @sleep_flag: CAN_SLEEP or NO_SLEEP
4527 *
4528 * Returns 0 for success, non-zero for failure.
4529 */
4530static int
4531_base_event_notification(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
4532{
4533 Mpi2EventNotificationRequest_t *mpi_request;
4534 unsigned long timeleft;
4535 u16 smid;
4536 int r = 0;
4537 int i;
4538
4539 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4540 __func__));
4541
4542 if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
4543 pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
4544 ioc->name, __func__);
4545 return -EAGAIN;
4546 }
4547
4548 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
4549 if (!smid) {
4550 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4551 ioc->name, __func__);
4552 return -EAGAIN;
4553 }
4554 ioc->base_cmds.status = MPT3_CMD_PENDING;
4555 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
4556 ioc->base_cmds.smid = smid;
4557 memset(mpi_request, 0, sizeof(Mpi2EventNotificationRequest_t));
4558 mpi_request->Function = MPI2_FUNCTION_EVENT_NOTIFICATION;
4559 mpi_request->VF_ID = 0; /* TODO */
4560 mpi_request->VP_ID = 0;
4561 for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
4562 mpi_request->EventMasks[i] =
4563 cpu_to_le32(ioc->event_masks[i]);
4564 init_completion(&ioc->base_cmds.done);
4565 mpt3sas_base_put_smid_default(ioc, smid);
4566 timeleft = wait_for_completion_timeout(&ioc->base_cmds.done, 30*HZ);
4567 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
4568 pr_err(MPT3SAS_FMT "%s: timeout\n",
4569 ioc->name, __func__);
4570 _debug_dump_mf(mpi_request,
4571 sizeof(Mpi2EventNotificationRequest_t)/4);
4572 if (ioc->base_cmds.status & MPT3_CMD_RESET)
4573 r = -EFAULT;
4574 else
4575 r = -ETIME;
4576 } else
4577 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s: complete\n",
4578 ioc->name, __func__));
4579 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4580 return r;
4581}
4582
4583/**
4584 * mpt3sas_base_validate_event_type - validating event types
4585 * @ioc: per adapter object
4586 * @event: firmware event
4587 *
4588 * This will turn on firmware event notification when application
4589 * ask for that event. We don't mask events that are already enabled.
4590 */
4591void
4592mpt3sas_base_validate_event_type(struct MPT3SAS_ADAPTER *ioc, u32 *event_type)
4593{
4594 int i, j;
4595 u32 event_mask, desired_event;
4596 u8 send_update_to_fw;
4597
4598 for (i = 0, send_update_to_fw = 0; i <
4599 MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) {
4600 event_mask = ~event_type[i];
4601 desired_event = 1;
4602 for (j = 0; j < 32; j++) {
4603 if (!(event_mask & desired_event) &&
4604 (ioc->event_masks[i] & desired_event)) {
4605 ioc->event_masks[i] &= ~desired_event;
4606 send_update_to_fw = 1;
4607 }
4608 desired_event = (desired_event << 1);
4609 }
4610 }
4611
4612 if (!send_update_to_fw)
4613 return;
4614
4615 mutex_lock(&ioc->base_cmds.mutex);
4616 _base_event_notification(ioc, CAN_SLEEP);
4617 mutex_unlock(&ioc->base_cmds.mutex);
4618}
4619
4620/**
4621 * _base_diag_reset - the "big hammer" start of day reset
4622 * @ioc: per adapter object
4623 * @sleep_flag: CAN_SLEEP or NO_SLEEP
4624 *
4625 * Returns 0 for success, non-zero for failure.
4626 */
4627static int
4628_base_diag_reset(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
4629{
4630 u32 host_diagnostic;
4631 u32 ioc_state;
4632 u32 count;
4633 u32 hcb_size;
4634
4635 pr_info(MPT3SAS_FMT "sending diag reset !!\n", ioc->name);
4636
4637 drsprintk(ioc, pr_info(MPT3SAS_FMT "clear interrupts\n",
4638 ioc->name));
4639
4640 count = 0;
4641 do {
4642 /* Write magic sequence to WriteSequence register
4643 * Loop until in diagnostic mode
4644 */
4645 drsprintk(ioc, pr_info(MPT3SAS_FMT
4646 "write magic sequence\n", ioc->name));
4647 writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
4648 writel(MPI2_WRSEQ_1ST_KEY_VALUE, &ioc->chip->WriteSequence);
4649 writel(MPI2_WRSEQ_2ND_KEY_VALUE, &ioc->chip->WriteSequence);
4650 writel(MPI2_WRSEQ_3RD_KEY_VALUE, &ioc->chip->WriteSequence);
4651 writel(MPI2_WRSEQ_4TH_KEY_VALUE, &ioc->chip->WriteSequence);
4652 writel(MPI2_WRSEQ_5TH_KEY_VALUE, &ioc->chip->WriteSequence);
4653 writel(MPI2_WRSEQ_6TH_KEY_VALUE, &ioc->chip->WriteSequence);
4654
4655 /* wait 100 msec */
4656 if (sleep_flag == CAN_SLEEP)
4657 msleep(100);
4658 else
4659 mdelay(100);
4660
4661 if (count++ > 20)
4662 goto out;
4663
4664 host_diagnostic = readl(&ioc->chip->HostDiagnostic);
4665 drsprintk(ioc, pr_info(MPT3SAS_FMT
4666 "wrote magic sequence: count(%d), host_diagnostic(0x%08x)\n",
4667 ioc->name, count, host_diagnostic));
4668
4669 } while ((host_diagnostic & MPI2_DIAG_DIAG_WRITE_ENABLE) == 0);
4670
4671 hcb_size = readl(&ioc->chip->HCBSize);
4672
4673 drsprintk(ioc, pr_info(MPT3SAS_FMT "diag reset: issued\n",
4674 ioc->name));
4675 writel(host_diagnostic | MPI2_DIAG_RESET_ADAPTER,
4676 &ioc->chip->HostDiagnostic);
4677
b453ff84
SR		 4678 /*This delay allows the chip PCIe hardware time to finish reset tasks*/
4679 if (sleep_flag == CAN_SLEEP)
4680 msleep(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000);
4681 else
4682 mdelay(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000);
f92363d1 4683
b453ff84
SR		 4684 /* Approximately 300 second max wait */
4685 for (count = 0; count < (300000000 /
4686 MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC); count++) {
f92363d1
SR		 4687
4688 host_diagnostic = readl(&ioc->chip->HostDiagnostic);
4689
4690 if (host_diagnostic == 0xFFFFFFFF)
4691 goto out;
4692 if (!(host_diagnostic & MPI2_DIAG_RESET_ADAPTER))
4693 break;
4694
b453ff84 4695 /* Wait to pass the second read delay window */
f92363d1 4696 if (sleep_flag == CAN_SLEEP)
b453ff84
SR		 4697 msleep(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC
4698 / 1000);
f92363d1 4699 else
b453ff84
SR		 4700 mdelay(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC
4701 / 1000);
f92363d1
SR		 4702 }
4703
4704 if (host_diagnostic & MPI2_DIAG_HCB_MODE) {
4705
4706 drsprintk(ioc, pr_info(MPT3SAS_FMT
4707 "restart the adapter assuming the HCB Address points to good F/W\n",
4708 ioc->name));
4709 host_diagnostic &= ~MPI2_DIAG_BOOT_DEVICE_SELECT_MASK;
4710 host_diagnostic |= MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW;
4711 writel(host_diagnostic, &ioc->chip->HostDiagnostic);
4712
4713 drsprintk(ioc, pr_info(MPT3SAS_FMT
4714 "re-enable the HCDW\n", ioc->name));
4715 writel(hcb_size | MPI2_HCB_SIZE_HCB_ENABLE,
4716 &ioc->chip->HCBSize);
4717 }
4718
4719 drsprintk(ioc, pr_info(MPT3SAS_FMT "restart the adapter\n",
4720 ioc->name));
4721 writel(host_diagnostic & ~MPI2_DIAG_HOLD_IOC_RESET,
4722 &ioc->chip->HostDiagnostic);
4723
4724 drsprintk(ioc, pr_info(MPT3SAS_FMT
4725 "disable writes to the diagnostic register\n", ioc->name));
4726 writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
4727
4728 drsprintk(ioc, pr_info(MPT3SAS_FMT
4729 "Wait for FW to go to the READY state\n", ioc->name));
4730 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, 20,
4731 sleep_flag);
4732 if (ioc_state) {
4733 pr_err(MPT3SAS_FMT
4734 "%s: failed going to ready state (ioc_state=0x%x)\n",
4735 ioc->name, __func__, ioc_state);
4736 goto out;
4737 }
4738
4739 pr_info(MPT3SAS_FMT "diag reset: SUCCESS\n", ioc->name);
4740 return 0;
4741
4742 out:
4743 pr_err(MPT3SAS_FMT "diag reset: FAILED\n", ioc->name);
4744 return -EFAULT;
4745}
4746
4747/**
4748 * _base_make_ioc_ready - put controller in READY state
4749 * @ioc: per adapter object
4750 * @sleep_flag: CAN_SLEEP or NO_SLEEP
4751 * @type: FORCE_BIG_HAMMER or SOFT_RESET
4752 *
4753 * Returns 0 for success, non-zero for failure.
4754 */
4755static int
4756_base_make_ioc_ready(struct MPT3SAS_ADAPTER *ioc, int sleep_flag,
4757 enum reset_type type)
4758{
4759 u32 ioc_state;
4760 int rc;
4761 int count;
4762
4763 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4764 __func__));
4765
4766 if (ioc->pci_error_recovery)
4767 return 0;
4768
4769 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
4770 dhsprintk(ioc, pr_info(MPT3SAS_FMT "%s: ioc_state(0x%08x)\n",
4771 ioc->name, __func__, ioc_state));
4772
4773 /* if in RESET state, it should move to READY state shortly */
4774 count = 0;
4775 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_RESET) {
4776 while ((ioc_state & MPI2_IOC_STATE_MASK) !=
4777 MPI2_IOC_STATE_READY) {
4778 if (count++ == 10) {
4779 pr_err(MPT3SAS_FMT
4780 "%s: failed going to ready state (ioc_state=0x%x)\n",
4781 ioc->name, __func__, ioc_state);
4782 return -EFAULT;
4783 }
4784 if (sleep_flag == CAN_SLEEP)
4785 ssleep(1);
4786 else
4787 mdelay(1000);
4788 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
4789 }
4790 }
4791
4792 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY)
4793 return 0;
4794
4795 if (ioc_state & MPI2_DOORBELL_USED) {
4796 dhsprintk(ioc, pr_info(MPT3SAS_FMT
4797 "unexpected doorbell active!\n",
4798 ioc->name));
4799 goto issue_diag_reset;
4800 }
4801
4802 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
4803 mpt3sas_base_fault_info(ioc, ioc_state &
4804 MPI2_DOORBELL_DATA_MASK);
4805 goto issue_diag_reset;
4806 }
4807
4808 if (type == FORCE_BIG_HAMMER)
4809 goto issue_diag_reset;
4810
4811 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL)
4812 if (!(_base_send_ioc_reset(ioc,
4813 MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET, 15, CAN_SLEEP))) {
4814 return 0;
4815 }
4816
4817 issue_diag_reset:
4818 rc = _base_diag_reset(ioc, CAN_SLEEP);
4819 return rc;
4820}
4821
4822/**
4823 * _base_make_ioc_operational - put controller in OPERATIONAL state
4824 * @ioc: per adapter object
4825 * @sleep_flag: CAN_SLEEP or NO_SLEEP
4826 *
4827 * Returns 0 for success, non-zero for failure.
4828 */
4829static int
4830_base_make_ioc_operational(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
4831{
4832 int r, i;
4833 unsigned long flags;
4834 u32 reply_address;
4835 u16 smid;
4836 struct _tr_list *delayed_tr, *delayed_tr_next;
4837 struct adapter_reply_queue *reply_q;
4838 long reply_post_free;
9b05c91a 4839 u32 reply_post_free_sz, index = 0;
f92363d1
SR		 4840
4841 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4842 __func__));
4843
4844 /* clean the delayed target reset list */
4845 list_for_each_entry_safe(delayed_tr, delayed_tr_next,
4846 &ioc->delayed_tr_list, list) {
4847 list_del(&delayed_tr->list);
4848 kfree(delayed_tr);
4849 }
4850
4851
4852 list_for_each_entry_safe(delayed_tr, delayed_tr_next,
4853 &ioc->delayed_tr_volume_list, list) {
4854 list_del(&delayed_tr->list);
4855 kfree(delayed_tr);
4856 }
4857
4858 /* initialize the scsi lookup free list */
4859 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
4860 INIT_LIST_HEAD(&ioc->free_list);
4861 smid = 1;
4862 for (i = 0; i < ioc->scsiio_depth; i++, smid++) {
4863 INIT_LIST_HEAD(&ioc->scsi_lookup[i].chain_list);
4864 ioc->scsi_lookup[i].cb_idx = 0xFF;
4865 ioc->scsi_lookup[i].smid = smid;
4866 ioc->scsi_lookup[i].scmd = NULL;
4867 list_add_tail(&ioc->scsi_lookup[i].tracker_list,
4868 &ioc->free_list);
4869 }
4870
4871 /* hi-priority queue */
4872 INIT_LIST_HEAD(&ioc->hpr_free_list);
4873 smid = ioc->hi_priority_smid;
4874 for (i = 0; i < ioc->hi_priority_depth; i++, smid++) {
4875 ioc->hpr_lookup[i].cb_idx = 0xFF;
4876 ioc->hpr_lookup[i].smid = smid;
4877 list_add_tail(&ioc->hpr_lookup[i].tracker_list,
4878 &ioc->hpr_free_list);
4879 }
4880
4881 /* internal queue */
4882 INIT_LIST_HEAD(&ioc->internal_free_list);
4883 smid = ioc->internal_smid;
4884 for (i = 0; i < ioc->internal_depth; i++, smid++) {
4885 ioc->internal_lookup[i].cb_idx = 0xFF;
4886 ioc->internal_lookup[i].smid = smid;
4887 list_add_tail(&ioc->internal_lookup[i].tracker_list,
4888 &ioc->internal_free_list);
4889 }
4890
4891 /* chain pool */
4892 INIT_LIST_HEAD(&ioc->free_chain_list);
4893 for (i = 0; i < ioc->chain_depth; i++)
4894 list_add_tail(&ioc->chain_lookup[i].tracker_list,
4895 &ioc->free_chain_list);
4896
4897 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
4898
4899 /* initialize Reply Free Queue */
4900 for (i = 0, reply_address = (u32)ioc->reply_dma ;
4901 i < ioc->reply_free_queue_depth ; i++, reply_address +=
4902 ioc->reply_sz)
4903 ioc->reply_free[i] = cpu_to_le32(reply_address);
4904
4905 /* initialize reply queues */
4906 if (ioc->is_driver_loading)
4907 _base_assign_reply_queues(ioc);
4908
4909 /* initialize Reply Post Free Queue */
f92363d1
SR		 4910 reply_post_free_sz = ioc->reply_post_queue_depth *
4911 sizeof(Mpi2DefaultReplyDescriptor_t);
9b05c91a 4912 reply_post_free = (long)ioc->reply_post[index].reply_post_free;
f92363d1
SR		 4913 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
4914 reply_q->reply_post_host_index = 0;
4915 reply_q->reply_post_free = (Mpi2ReplyDescriptorsUnion_t *)
4916 reply_post_free;
4917 for (i = 0; i < ioc->reply_post_queue_depth; i++)
4918 reply_q->reply_post_free[i].Words =
4919 cpu_to_le64(ULLONG_MAX);
4920 if (!_base_is_controller_msix_enabled(ioc))
4921 goto skip_init_reply_post_free_queue;
9b05c91a
SR		 4922 /*
4923 * If RDPQ is enabled, switch to the next allocation.
4924 * Otherwise advance within the contiguous region.
4925 */
4926 if (ioc->rdpq_array_enable)
4927 reply_post_free = (long)
4928 ioc->reply_post[++index].reply_post_free;
4929 else
4930 reply_post_free += reply_post_free_sz;
f92363d1
SR		 4931 }
4932 skip_init_reply_post_free_queue:
4933
4934 r = _base_send_ioc_init(ioc, sleep_flag);
4935 if (r)
4936 return r;
4937
4938 /* initialize reply free host index */
4939 ioc->reply_free_host_index = ioc->reply_free_queue_depth - 1;
4940 writel(ioc->reply_free_host_index, &ioc->chip->ReplyFreeHostIndex);
4941
4942 /* initialize reply post host index */
4943 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
fb77bb53
SR		 4944 if (ioc->msix96_vector)
4945 writel((reply_q->msix_index & 7)<<
4946 MPI2_RPHI_MSIX_INDEX_SHIFT,
4947 ioc->replyPostRegisterIndex[reply_q->msix_index/8]);
4948 else
4949 writel(reply_q->msix_index <<
4950 MPI2_RPHI_MSIX_INDEX_SHIFT,
4951 &ioc->chip->ReplyPostHostIndex);
4952
f92363d1
SR		 4953 if (!_base_is_controller_msix_enabled(ioc))
4954 goto skip_init_reply_post_host_index;
4955 }
4956
4957 skip_init_reply_post_host_index:
4958
4959 _base_unmask_interrupts(ioc);
4960 r = _base_event_notification(ioc, sleep_flag);
4961 if (r)
4962 return r;
4963
4964 if (sleep_flag == CAN_SLEEP)
4965 _base_static_config_pages(ioc);
4966
4967
4968 if (ioc->is_driver_loading) {
4969 ioc->wait_for_discovery_to_complete =
4970 _base_determine_wait_on_discovery(ioc);
4971
4972 return r; /* scan_start and scan_finished support */
4973 }
4974
4975 r = _base_send_port_enable(ioc, sleep_flag);
4976 if (r)
4977 return r;
4978
4979 return r;
4980}
4981
4982/**
4983 * mpt3sas_base_free_resources - free resources controller resources
4984 * @ioc: per adapter object
4985 *
4986 * Return nothing.
4987 */
4988void
4989mpt3sas_base_free_resources(struct MPT3SAS_ADAPTER *ioc)
4990{
f92363d1
SR		 4991 dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4992 __func__));
4993
cf9bd21a
JL		 4994 if (ioc->chip_phys && ioc->chip) {
4995 _base_mask_interrupts(ioc);
4996 ioc->shost_recovery = 1;
4997 _base_make_ioc_ready(ioc, CAN_SLEEP, SOFT_RESET);
4998 ioc->shost_recovery = 0;
4999 }
5000
580d4e31 5001 mpt3sas_base_unmap_resources(ioc);
f92363d1
SR		 5002 return;
5003}
5004
5005/**
5006 * mpt3sas_base_attach - attach controller instance
5007 * @ioc: per adapter object
5008 *
5009 * Returns 0 for success, non-zero for failure.
5010 */
5011int
5012mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc)
5013{
5014 int r, i;
5015 int cpu_id, last_cpu_id = 0;
5016
5017 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
5018 __func__));
5019
5020 /* setup cpu_msix_table */
5021 ioc->cpu_count = num_online_cpus();
5022 for_each_online_cpu(cpu_id)
5023 last_cpu_id = cpu_id;
5024 ioc->cpu_msix_table_sz = last_cpu_id + 1;
5025 ioc->cpu_msix_table = kzalloc(ioc->cpu_msix_table_sz, GFP_KERNEL);
5026 ioc->reply_queue_count = 1;
5027 if (!ioc->cpu_msix_table) {
5028 dfailprintk(ioc, pr_info(MPT3SAS_FMT
5029 "allocation for cpu_msix_table failed!!!\n",
5030 ioc->name));
5031 r = -ENOMEM;
5032 goto out_free_resources;
5033 }
5034
9b05c91a
SR		 5035 ioc->rdpq_array_enable_assigned = 0;
5036 ioc->dma_mask = 0;
f92363d1
SR		 5037 r = mpt3sas_base_map_resources(ioc);
5038 if (r)
5039 goto out_free_resources;
5040
5041
5042 pci_set_drvdata(ioc->pdev, ioc->shost);
5043 r = _base_get_ioc_facts(ioc, CAN_SLEEP);
5044 if (r)
5045 goto out_free_resources;
5046
471ef9d4
SR		 5047 switch (ioc->hba_mpi_version_belonged) {
5048 case MPI2_VERSION:
5049 ioc->build_sg_scmd = &_base_build_sg_scmd;
5050 ioc->build_sg = &_base_build_sg;
5051 ioc->build_zero_len_sge = &_base_build_zero_len_sge;
5052 break;
5053 case MPI25_VERSION:
5054 /*
5055 * In SAS3.0,
5056 * SCSI_IO, SMP_PASSTHRU, SATA_PASSTHRU, Target Assist, and
5057 * Target Status - all require the IEEE formated scatter gather
5058 * elements.
5059 */
5060 ioc->build_sg_scmd = &_base_build_sg_scmd_ieee;
5061 ioc->build_sg = &_base_build_sg_ieee;
5062 ioc->build_zero_len_sge = &_base_build_zero_len_sge_ieee;
5063 ioc->sge_size_ieee = sizeof(Mpi2IeeeSgeSimple64_t);
5064 break;
5065 }
f92363d1
SR		 5066
5067 /*
5068 * These function pointers for other requests that don't
5069 * the require IEEE scatter gather elements.
5070 *
5071 * For example Configuration Pages and SAS IOUNIT Control don't.
5072 */
5073 ioc->build_sg_mpi = &_base_build_sg;
5074 ioc->build_zero_len_sge_mpi = &_base_build_zero_len_sge;
5075
5076 r = _base_make_ioc_ready(ioc, CAN_SLEEP, SOFT_RESET);
5077 if (r)
5078 goto out_free_resources;
5079
5080 ioc->pfacts = kcalloc(ioc->facts.NumberOfPorts,
5081 sizeof(struct mpt3sas_port_facts), GFP_KERNEL);
5082 if (!ioc->pfacts) {
5083 r = -ENOMEM;
5084 goto out_free_resources;
5085 }
5086
5087 for (i = 0 ; i < ioc->facts.NumberOfPorts; i++) {
5088 r = _base_get_port_facts(ioc, i, CAN_SLEEP);
5089 if (r)
5090 goto out_free_resources;
5091 }
5092
5093 r = _base_allocate_memory_pools(ioc, CAN_SLEEP);
5094 if (r)
5095 goto out_free_resources;
5096
5097 init_waitqueue_head(&ioc->reset_wq);
5098
5099 /* allocate memory pd handle bitmask list */
5100 ioc->pd_handles_sz = (ioc->facts.MaxDevHandle / 8);
5101 if (ioc->facts.MaxDevHandle % 8)
5102 ioc->pd_handles_sz++;
5103 ioc->pd_handles = kzalloc(ioc->pd_handles_sz,
5104 GFP_KERNEL);
5105 if (!ioc->pd_handles) {
5106 r = -ENOMEM;
5107 goto out_free_resources;
5108 }
5109 ioc->blocking_handles = kzalloc(ioc->pd_handles_sz,
5110 GFP_KERNEL);
5111 if (!ioc->blocking_handles) {
5112 r = -ENOMEM;
5113 goto out_free_resources;
5114 }
5115
5116 ioc->fwfault_debug = mpt3sas_fwfault_debug;
5117
5118 /* base internal command bits */
5119 mutex_init(&ioc->base_cmds.mutex);
5120 ioc->base_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5121 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
5122
5123 /* port_enable command bits */
5124 ioc->port_enable_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5125 ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED;
5126
5127 /* transport internal command bits */
5128 ioc->transport_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5129 ioc->transport_cmds.status = MPT3_CMD_NOT_USED;
5130 mutex_init(&ioc->transport_cmds.mutex);
5131
5132 /* scsih internal command bits */
5133 ioc->scsih_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5134 ioc->scsih_cmds.status = MPT3_CMD_NOT_USED;
5135 mutex_init(&ioc->scsih_cmds.mutex);
5136
5137 /* task management internal command bits */
5138 ioc->tm_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5139 ioc->tm_cmds.status = MPT3_CMD_NOT_USED;
5140 mutex_init(&ioc->tm_cmds.mutex);
5141
5142 /* config page internal command bits */
5143 ioc->config_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5144 ioc->config_cmds.status = MPT3_CMD_NOT_USED;
5145 mutex_init(&ioc->config_cmds.mutex);
5146
5147 /* ctl module internal command bits */
5148 ioc->ctl_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5149 ioc->ctl_cmds.sense = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL);
5150 ioc->ctl_cmds.status = MPT3_CMD_NOT_USED;
5151 mutex_init(&ioc->ctl_cmds.mutex);
5152
5153 if (!ioc->base_cmds.reply || !ioc->transport_cmds.reply ||
5154 !ioc->scsih_cmds.reply || !ioc->tm_cmds.reply ||
5155 !ioc->config_cmds.reply || !ioc->ctl_cmds.reply ||
5156 !ioc->ctl_cmds.sense) {
5157 r = -ENOMEM;
5158 goto out_free_resources;
5159 }
5160
5161 for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
5162 ioc->event_masks[i] = -1;
5163
5164 /* here we enable the events we care about */
5165 _base_unmask_events(ioc, MPI2_EVENT_SAS_DISCOVERY);
5166 _base_unmask_events(ioc, MPI2_EVENT_SAS_BROADCAST_PRIMITIVE);
5167 _base_unmask_events(ioc, MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST);
5168 _base_unmask_events(ioc, MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE);
5169 _base_unmask_events(ioc, MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE);
5170 _base_unmask_events(ioc, MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST);
5171 _base_unmask_events(ioc, MPI2_EVENT_IR_VOLUME);
5172 _base_unmask_events(ioc, MPI2_EVENT_IR_PHYSICAL_DISK);
5173 _base_unmask_events(ioc, MPI2_EVENT_IR_OPERATION_STATUS);
5174 _base_unmask_events(ioc, MPI2_EVENT_LOG_ENTRY_ADDED);
2d8ce8c9 5175 _base_unmask_events(ioc, MPI2_EVENT_TEMP_THRESHOLD);
f92363d1
SR		 5176
5177 r = _base_make_ioc_operational(ioc, CAN_SLEEP);
5178 if (r)
5179 goto out_free_resources;
5180
16e179bd 5181 ioc->non_operational_loop = 0;
f92363d1
SR		 5182 return 0;
5183
5184 out_free_resources:
5185
5186 ioc->remove_host = 1;
5187
5188 mpt3sas_base_free_resources(ioc);
5189 _base_release_memory_pools(ioc);
5190 pci_set_drvdata(ioc->pdev, NULL);
5191 kfree(ioc->cpu_msix_table);
5192 kfree(ioc->pd_handles);
5193 kfree(ioc->blocking_handles);
5194 kfree(ioc->tm_cmds.reply);
5195 kfree(ioc->transport_cmds.reply);
5196 kfree(ioc->scsih_cmds.reply);
5197 kfree(ioc->config_cmds.reply);
5198 kfree(ioc->base_cmds.reply);
5199 kfree(ioc->port_enable_cmds.reply);
5200 kfree(ioc->ctl_cmds.reply);
5201 kfree(ioc->ctl_cmds.sense);
5202 kfree(ioc->pfacts);
5203 ioc->ctl_cmds.reply = NULL;
5204 ioc->base_cmds.reply = NULL;
5205 ioc->tm_cmds.reply = NULL;
5206 ioc->scsih_cmds.reply = NULL;
5207 ioc->transport_cmds.reply = NULL;
5208 ioc->config_cmds.reply = NULL;
5209 ioc->pfacts = NULL;
5210 return r;
5211}
5212
5213
5214/**
5215 * mpt3sas_base_detach - remove controller instance
5216 * @ioc: per adapter object
5217 *
5218 * Return nothing.
5219 */
5220void
5221mpt3sas_base_detach(struct MPT3SAS_ADAPTER *ioc)
5222{
5223 dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
5224 __func__));
5225
5226 mpt3sas_base_stop_watchdog(ioc);
5227 mpt3sas_base_free_resources(ioc);
5228 _base_release_memory_pools(ioc);
5229 pci_set_drvdata(ioc->pdev, NULL);
5230 kfree(ioc->cpu_msix_table);
5231 kfree(ioc->pd_handles);
5232 kfree(ioc->blocking_handles);
5233 kfree(ioc->pfacts);
5234 kfree(ioc->ctl_cmds.reply);
5235 kfree(ioc->ctl_cmds.sense);
5236 kfree(ioc->base_cmds.reply);
5237 kfree(ioc->port_enable_cmds.reply);
5238 kfree(ioc->tm_cmds.reply);
5239 kfree(ioc->transport_cmds.reply);
5240 kfree(ioc->scsih_cmds.reply);
5241 kfree(ioc->config_cmds.reply);
5242}
5243
5244/**
5245 * _base_reset_handler - reset callback handler (for base)
5246 * @ioc: per adapter object
5247 * @reset_phase: phase
5248 *
5249 * The handler for doing any required cleanup or initialization.
5250 *
5251 * The reset phase can be MPT3_IOC_PRE_RESET, MPT3_IOC_AFTER_RESET,
5252 * MPT3_IOC_DONE_RESET
5253 *
5254 * Return nothing.
5255 */
5256static void
5257_base_reset_handler(struct MPT3SAS_ADAPTER *ioc, int reset_phase)
5258{
5259 mpt3sas_scsih_reset_handler(ioc, reset_phase);
5260 mpt3sas_ctl_reset_handler(ioc, reset_phase);
5261 switch (reset_phase) {
5262 case MPT3_IOC_PRE_RESET:
5263 dtmprintk(ioc, pr_info(MPT3SAS_FMT
5264 "%s: MPT3_IOC_PRE_RESET\n", ioc->name, __func__));
5265 break;
5266 case MPT3_IOC_AFTER_RESET:
5267 dtmprintk(ioc, pr_info(MPT3SAS_FMT
5268 "%s: MPT3_IOC_AFTER_RESET\n", ioc->name, __func__));
5269 if (ioc->transport_cmds.status & MPT3_CMD_PENDING) {
5270 ioc->transport_cmds.status |= MPT3_CMD_RESET;
5271 mpt3sas_base_free_smid(ioc, ioc->transport_cmds.smid);
5272 complete(&ioc->transport_cmds.done);
5273 }
5274 if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
5275 ioc->base_cmds.status |= MPT3_CMD_RESET;
5276 mpt3sas_base_free_smid(ioc, ioc->base_cmds.smid);
5277 complete(&ioc->base_cmds.done);
5278 }
5279 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
5280 ioc->port_enable_failed = 1;
5281 ioc->port_enable_cmds.status |= MPT3_CMD_RESET;
5282 mpt3sas_base_free_smid(ioc, ioc->port_enable_cmds.smid);
5283 if (ioc->is_driver_loading) {
5284 ioc->start_scan_failed =
5285 MPI2_IOCSTATUS_INTERNAL_ERROR;
5286 ioc->start_scan = 0;
5287 ioc->port_enable_cmds.status =
5288 MPT3_CMD_NOT_USED;
5289 } else
5290 complete(&ioc->port_enable_cmds.done);
5291 }
5292 if (ioc->config_cmds.status & MPT3_CMD_PENDING) {
5293 ioc->config_cmds.status |= MPT3_CMD_RESET;
5294 mpt3sas_base_free_smid(ioc, ioc->config_cmds.smid);
5295 ioc->config_cmds.smid = USHRT_MAX;
5296 complete(&ioc->config_cmds.done);
5297 }
5298 break;
5299 case MPT3_IOC_DONE_RESET:
5300 dtmprintk(ioc, pr_info(MPT3SAS_FMT
5301 "%s: MPT3_IOC_DONE_RESET\n", ioc->name, __func__));
5302 break;
5303 }
5304}
5305
5306/**
5307 * _wait_for_commands_to_complete - reset controller
5308 * @ioc: Pointer to MPT_ADAPTER structure
5309 * @sleep_flag: CAN_SLEEP or NO_SLEEP
5310 *
5311 * This function waiting(3s) for all pending commands to complete
5312 * prior to putting controller in reset.
5313 */
5314static void
5315_wait_for_commands_to_complete(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
5316{
5317 u32 ioc_state;
5318 unsigned long flags;
5319 u16 i;
5320
5321 ioc->pending_io_count = 0;
5322 if (sleep_flag != CAN_SLEEP)
5323 return;
5324
5325 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
5326 if ((ioc_state & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL)
5327 return;
5328
5329 /* pending command count */
5330 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
5331 for (i = 0; i < ioc->scsiio_depth; i++)
5332 if (ioc->scsi_lookup[i].cb_idx != 0xFF)
5333 ioc->pending_io_count++;
5334 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
5335
5336 if (!ioc->pending_io_count)
5337 return;
5338
5339 /* wait for pending commands to complete */
5340 wait_event_timeout(ioc->reset_wq, ioc->pending_io_count == 0, 10 * HZ);
5341}
5342
5343/**
5344 * mpt3sas_base_hard_reset_handler - reset controller
5345 * @ioc: Pointer to MPT_ADAPTER structure
5346 * @sleep_flag: CAN_SLEEP or NO_SLEEP
5347 * @type: FORCE_BIG_HAMMER or SOFT_RESET
5348 *
5349 * Returns 0 for success, non-zero for failure.
5350 */
5351int
5352mpt3sas_base_hard_reset_handler(struct MPT3SAS_ADAPTER *ioc, int sleep_flag,
5353 enum reset_type type)
5354{
5355 int r;
5356 unsigned long flags;
5357 u32 ioc_state;
5358 u8 is_fault = 0, is_trigger = 0;
5359
5360 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: enter\n", ioc->name,
5361 __func__));
5362
5363 if (ioc->pci_error_recovery) {
5364 pr_err(MPT3SAS_FMT "%s: pci error recovery reset\n",
5365 ioc->name, __func__);
5366 r = 0;
5367 goto out_unlocked;
5368 }
5369
5370 if (mpt3sas_fwfault_debug)
5371 mpt3sas_halt_firmware(ioc);
5372
5373 /* TODO - What we really should be doing is pulling
5374 * out all the code associated with NO_SLEEP; its never used.
5375 * That is legacy code from mpt fusion driver, ported over.
5376 * I will leave this BUG_ON here for now till its been resolved.
5377 */
5378 BUG_ON(sleep_flag == NO_SLEEP);
5379
5380 /* wait for an active reset in progress to complete */
5381 if (!mutex_trylock(&ioc->reset_in_progress_mutex)) {
5382 do {
5383 ssleep(1);
5384 } while (ioc->shost_recovery == 1);
5385 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: exit\n", ioc->name,
5386 __func__));
5387 return ioc->ioc_reset_in_progress_status;
5388 }
5389
5390 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
5391 ioc->shost_recovery = 1;
5392 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
5393
5394 if ((ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] &
5395 MPT3_DIAG_BUFFER_IS_REGISTERED) &&
5396 (!(ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] &
5397 MPT3_DIAG_BUFFER_IS_RELEASED))) {
5398 is_trigger = 1;
5399 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
5400 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
5401 is_fault = 1;
5402 }
5403 _base_reset_handler(ioc, MPT3_IOC_PRE_RESET);
5404 _wait_for_commands_to_complete(ioc, sleep_flag);
5405 _base_mask_interrupts(ioc);
5406 r = _base_make_ioc_ready(ioc, sleep_flag, type);
5407 if (r)
5408 goto out;
5409 _base_reset_handler(ioc, MPT3_IOC_AFTER_RESET);
5410
5411 /* If this hard reset is called while port enable is active, then
5412 * there is no reason to call make_ioc_operational
5413 */
5414 if (ioc->is_driver_loading && ioc->port_enable_failed) {
5415 ioc->remove_host = 1;
5416 r = -EFAULT;
5417 goto out;
5418 }
5419 r = _base_get_ioc_facts(ioc, CAN_SLEEP);
5420 if (r)
5421 goto out;
9b05c91a
SR		 5422
5423 if (ioc->rdpq_array_enable && !ioc->rdpq_array_capable)
5424 panic("%s: Issue occurred with flashing controller firmware."
5425 "Please reboot the system and ensure that the correct"
5426 " firmware version is running\n", ioc->name);
5427
f92363d1
SR		 5428 r = _base_make_ioc_operational(ioc, sleep_flag);
5429 if (!r)
5430 _base_reset_handler(ioc, MPT3_IOC_DONE_RESET);
5431
5432 out:
5433 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: %s\n",
5434 ioc->name, __func__, ((r == 0) ? "SUCCESS" : "FAILED")));
5435
5436 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
5437 ioc->ioc_reset_in_progress_status = r;
5438 ioc->shost_recovery = 0;
5439 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
5440 ioc->ioc_reset_count++;
5441 mutex_unlock(&ioc->reset_in_progress_mutex);
5442
5443 out_unlocked:
5444 if ((r == 0) && is_trigger) {
5445 if (is_fault)
5446 mpt3sas_trigger_master(ioc, MASTER_TRIGGER_FW_FAULT);
5447 else
5448 mpt3sas_trigger_master(ioc,
5449 MASTER_TRIGGER_ADAPTER_RESET);
5450 }
5451 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: exit\n", ioc->name,
5452 __func__));
5453 return r;
5454}
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