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scsi: mpt3sas: set EEDP-escape-flags for SAS35 devices.
[mirror_ubuntu-artful-kernel.git] / drivers / scsi / mpt3sas / mpt3sas_base.c
CommitLineData
f92363d1
SR		 1/*
2 * This is the Fusion MPT base driver providing common API layer interface
3 * for access to MPT (Message Passing Technology) firmware.
4 *
5 * This code is based on drivers/scsi/mpt3sas/mpt3sas_base.c
a4ffce0d 6 * Copyright (C) 2012-2014 LSI Corporation
a03bd153
SR		 7 * Copyright (C) 2013-2014 Avago Technologies
8 * (mailto: MPT-FusionLinux.pdl@avagotech.com)
f92363d1
SR		 9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version 2
13 * of the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * NO WARRANTY
21 * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
22 * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
23 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
24 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
25 * solely responsible for determining the appropriateness of using and
26 * distributing the Program and assumes all risks associated with its
27 * exercise of rights under this Agreement, including but not limited to
28 * the risks and costs of program errors, damage to or loss of data,
29 * programs or equipment, and unavailability or interruption of operations.
30
31 * DISCLAIMER OF LIABILITY
32 * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
33 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34 * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
35 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
36 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
37 * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
38 * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
39
40 * You should have received a copy of the GNU General Public License
41 * along with this program; if not, write to the Free Software
42 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
43 * USA.
44 */
45
f92363d1
SR		 46#include <linux/kernel.h>
47#include <linux/module.h>
48#include <linux/errno.h>
49#include <linux/init.h>
50#include <linux/slab.h>
51#include <linux/types.h>
52#include <linux/pci.h>
53#include <linux/kdev_t.h>
54#include <linux/blkdev.h>
55#include <linux/delay.h>
56#include <linux/interrupt.h>
57#include <linux/dma-mapping.h>
58#include <linux/io.h>
59#include <linux/time.h>
23409bd4 60#include <linux/ktime.h>
f92363d1
SR		 61#include <linux/kthread.h>
62#include <linux/aer.h>
63
64
65#include "mpt3sas_base.h"
66
67static MPT_CALLBACK mpt_callbacks[MPT_MAX_CALLBACKS];
68
69
70#define FAULT_POLLING_INTERVAL 1000 /* in milliseconds */
71
72 /* maximum controller queue depth */
73#define MAX_HBA_QUEUE_DEPTH 30000
74#define MAX_CHAIN_DEPTH 100000
75static int max_queue_depth = -1;
76module_param(max_queue_depth, int, 0);
77MODULE_PARM_DESC(max_queue_depth, " max controller queue depth ");
78
79static int max_sgl_entries = -1;
80module_param(max_sgl_entries, int, 0);
81MODULE_PARM_DESC(max_sgl_entries, " max sg entries ");
82
83static int msix_disable = -1;
84module_param(msix_disable, int, 0);
85MODULE_PARM_DESC(msix_disable, " disable msix routed interrupts (default=0)");
86
64038301
SPS		 87static int smp_affinity_enable = 1;
88module_param(smp_affinity_enable, int, S_IRUGO);
89MODULE_PARM_DESC(smp_affinity_enable, "SMP affinity feature enable/disbale Default: enable(1)");
90
fb77bb53 91static int max_msix_vectors = -1;
9c500060
SR		 92module_param(max_msix_vectors, int, 0);
93MODULE_PARM_DESC(max_msix_vectors,
fb77bb53 94 " max msix vectors");
f92363d1
SR		 95
96static int mpt3sas_fwfault_debug;
97MODULE_PARM_DESC(mpt3sas_fwfault_debug,
98 " enable detection of firmware fault and halt firmware - (default=0)");
99
9b05c91a 100static int
98c56ad3 101_base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc);
f92363d1
SR		 102
103/**
104 * _scsih_set_fwfault_debug - global setting of ioc->fwfault_debug.
105 *
106 */
107static int
108_scsih_set_fwfault_debug(const char *val, struct kernel_param *kp)
109{
110 int ret = param_set_int(val, kp);
111 struct MPT3SAS_ADAPTER *ioc;
112
113 if (ret)
114 return ret;
115
08c4d550 116 /* global ioc spinlock to protect controller list on list operations */
f92363d1 117 pr_info("setting fwfault_debug(%d)\n", mpt3sas_fwfault_debug);
08c4d550 118 spin_lock(&gioc_lock);
f92363d1
SR		 119 list_for_each_entry(ioc, &mpt3sas_ioc_list, list)
120 ioc->fwfault_debug = mpt3sas_fwfault_debug;
08c4d550 121 spin_unlock(&gioc_lock);
f92363d1
SR		 122 return 0;
123}
124module_param_call(mpt3sas_fwfault_debug, _scsih_set_fwfault_debug,
125 param_get_int, &mpt3sas_fwfault_debug, 0644);
126
127/**
128 * mpt3sas_remove_dead_ioc_func - kthread context to remove dead ioc
129 * @arg: input argument, used to derive ioc
130 *
131 * Return 0 if controller is removed from pci subsystem.
132 * Return -1 for other case.
133 */
134static int mpt3sas_remove_dead_ioc_func(void *arg)
135{
136 struct MPT3SAS_ADAPTER *ioc = (struct MPT3SAS_ADAPTER *)arg;
137 struct pci_dev *pdev;
138
139 if ((ioc == NULL))
140 return -1;
141
142 pdev = ioc->pdev;
143 if ((pdev == NULL))
144 return -1;
64cdb418 145 pci_stop_and_remove_bus_device_locked(pdev);
f92363d1
SR		 146 return 0;
147}
148
149/**
150 * _base_fault_reset_work - workq handling ioc fault conditions
151 * @work: input argument, used to derive ioc
152 * Context: sleep.
153 *
154 * Return nothing.
155 */
156static void
157_base_fault_reset_work(struct work_struct *work)
158{
159 struct MPT3SAS_ADAPTER *ioc =
160 container_of(work, struct MPT3SAS_ADAPTER, fault_reset_work.work);
161 unsigned long flags;
162 u32 doorbell;
163 int rc;
164 struct task_struct *p;
165
166
167 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
16e179bd 168 if (ioc->shost_recovery || ioc->pci_error_recovery)
f92363d1
SR		 169 goto rearm_timer;
170 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
171
172 doorbell = mpt3sas_base_get_iocstate(ioc, 0);
173 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_MASK) {
174 pr_err(MPT3SAS_FMT "SAS host is non-operational !!!!\n",
175 ioc->name);
176
16e179bd
SR		 177 /* It may be possible that EEH recovery can resolve some of
178 * pci bus failure issues rather removing the dead ioc function
179 * by considering controller is in a non-operational state. So
180 * here priority is given to the EEH recovery. If it doesn't
181 * not resolve this issue, mpt3sas driver will consider this
182 * controller to non-operational state and remove the dead ioc
183 * function.
184 */
185 if (ioc->non_operational_loop++ < 5) {
186 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock,
187 flags);
188 goto rearm_timer;
189 }
190
f92363d1
SR		 191 /*
192 * Call _scsih_flush_pending_cmds callback so that we flush all
193 * pending commands back to OS. This call is required to aovid
194 * deadlock at block layer. Dead IOC will fail to do diag reset,
195 * and this call is safe since dead ioc will never return any
196 * command back from HW.
197 */
198 ioc->schedule_dead_ioc_flush_running_cmds(ioc);
199 /*
200 * Set remove_host flag early since kernel thread will
201 * take some time to execute.
202 */
203 ioc->remove_host = 1;
204 /*Remove the Dead Host */
205 p = kthread_run(mpt3sas_remove_dead_ioc_func, ioc,
c84b06a4 206 "%s_dead_ioc_%d", ioc->driver_name, ioc->id);
f92363d1
SR		 207 if (IS_ERR(p))
208 pr_err(MPT3SAS_FMT
209 "%s: Running mpt3sas_dead_ioc thread failed !!!!\n",
210 ioc->name, __func__);
211 else
212 pr_err(MPT3SAS_FMT
213 "%s: Running mpt3sas_dead_ioc thread success !!!!\n",
214 ioc->name, __func__);
215 return; /* don't rearm timer */
216 }
217
16e179bd
SR		 218 ioc->non_operational_loop = 0;
219
f92363d1 220 if ((doorbell & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL) {
98c56ad3 221 rc = mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER);
f92363d1
SR		 222 pr_warn(MPT3SAS_FMT "%s: hard reset: %s\n", ioc->name,
223 __func__, (rc == 0) ? "success" : "failed");
224 doorbell = mpt3sas_base_get_iocstate(ioc, 0);
225 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
226 mpt3sas_base_fault_info(ioc, doorbell &
227 MPI2_DOORBELL_DATA_MASK);
228 if (rc && (doorbell & MPI2_IOC_STATE_MASK) !=
229 MPI2_IOC_STATE_OPERATIONAL)
230 return; /* don't rearm timer */
231 }
232
233 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
234 rearm_timer:
235 if (ioc->fault_reset_work_q)
236 queue_delayed_work(ioc->fault_reset_work_q,
237 &ioc->fault_reset_work,
238 msecs_to_jiffies(FAULT_POLLING_INTERVAL));
239 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
240}
241
242/**
243 * mpt3sas_base_start_watchdog - start the fault_reset_work_q
244 * @ioc: per adapter object
245 * Context: sleep.
246 *
247 * Return nothing.
248 */
249void
250mpt3sas_base_start_watchdog(struct MPT3SAS_ADAPTER *ioc)
251{
252 unsigned long flags;
253
254 if (ioc->fault_reset_work_q)
255 return;
256
257 /* initialize fault polling */
258
259 INIT_DELAYED_WORK(&ioc->fault_reset_work, _base_fault_reset_work);
260 snprintf(ioc->fault_reset_work_q_name,
c84b06a4
SR		 261 sizeof(ioc->fault_reset_work_q_name), "poll_%s%d_status",
262 ioc->driver_name, ioc->id);
f92363d1
SR		 263 ioc->fault_reset_work_q =
264 create_singlethread_workqueue(ioc->fault_reset_work_q_name);
265 if (!ioc->fault_reset_work_q) {
266 pr_err(MPT3SAS_FMT "%s: failed (line=%d)\n",
267 ioc->name, __func__, __LINE__);
268 return;
269 }
270 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
271 if (ioc->fault_reset_work_q)
272 queue_delayed_work(ioc->fault_reset_work_q,
273 &ioc->fault_reset_work,
274 msecs_to_jiffies(FAULT_POLLING_INTERVAL));
275 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
276}
277
278/**
279 * mpt3sas_base_stop_watchdog - stop the fault_reset_work_q
280 * @ioc: per adapter object
281 * Context: sleep.
282 *
283 * Return nothing.
284 */
285void
286mpt3sas_base_stop_watchdog(struct MPT3SAS_ADAPTER *ioc)
287{
288 unsigned long flags;
289 struct workqueue_struct *wq;
290
291 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
292 wq = ioc->fault_reset_work_q;
293 ioc->fault_reset_work_q = NULL;
294 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
295 if (wq) {
4dc06fd8 296 if (!cancel_delayed_work_sync(&ioc->fault_reset_work))
f92363d1
SR		 297 flush_workqueue(wq);
298 destroy_workqueue(wq);
299 }
300}
301
302/**
303 * mpt3sas_base_fault_info - verbose translation of firmware FAULT code
304 * @ioc: per adapter object
305 * @fault_code: fault code
306 *
307 * Return nothing.
308 */
309void
310mpt3sas_base_fault_info(struct MPT3SAS_ADAPTER *ioc , u16 fault_code)
311{
312 pr_err(MPT3SAS_FMT "fault_state(0x%04x)!\n",
313 ioc->name, fault_code);
314}
315
316/**
317 * mpt3sas_halt_firmware - halt's mpt controller firmware
318 * @ioc: per adapter object
319 *
320 * For debugging timeout related issues. Writing 0xCOFFEE00
321 * to the doorbell register will halt controller firmware. With
322 * the purpose to stop both driver and firmware, the enduser can
323 * obtain a ring buffer from controller UART.
324 */
325void
326mpt3sas_halt_firmware(struct MPT3SAS_ADAPTER *ioc)
327{
328 u32 doorbell;
329
330 if (!ioc->fwfault_debug)
331 return;
332
333 dump_stack();
334
335 doorbell = readl(&ioc->chip->Doorbell);
336 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
337 mpt3sas_base_fault_info(ioc , doorbell);
338 else {
339 writel(0xC0FFEE00, &ioc->chip->Doorbell);
340 pr_err(MPT3SAS_FMT "Firmware is halted due to command timeout\n",
341 ioc->name);
342 }
343
344 if (ioc->fwfault_debug == 2)
345 for (;;)
346 ;
347 else
348 panic("panic in %s\n", __func__);
349}
350
f92363d1
SR		 351/**
352 * _base_sas_ioc_info - verbose translation of the ioc status
353 * @ioc: per adapter object
354 * @mpi_reply: reply mf payload returned from firmware
355 * @request_hdr: request mf
356 *
357 * Return nothing.
358 */
359static void
360_base_sas_ioc_info(struct MPT3SAS_ADAPTER *ioc, MPI2DefaultReply_t *mpi_reply,
361 MPI2RequestHeader_t *request_hdr)
362{
363 u16 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) &
364 MPI2_IOCSTATUS_MASK;
365 char *desc = NULL;
366 u16 frame_sz;
367 char *func_str = NULL;
368
369 /* SCSI_IO, RAID_PASS are handled from _scsih_scsi_ioc_info */
370 if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST ||
371 request_hdr->Function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH ||
372 request_hdr->Function == MPI2_FUNCTION_EVENT_NOTIFICATION)
373 return;
374
375 if (ioc_status == MPI2_IOCSTATUS_CONFIG_INVALID_PAGE)
376 return;
377
378 switch (ioc_status) {
379
380/****************************************************************************
381* Common IOCStatus values for all replies
382****************************************************************************/
383
384 case MPI2_IOCSTATUS_INVALID_FUNCTION:
385 desc = "invalid function";
386 break;
387 case MPI2_IOCSTATUS_BUSY:
388 desc = "busy";
389 break;
390 case MPI2_IOCSTATUS_INVALID_SGL:
391 desc = "invalid sgl";
392 break;
393 case MPI2_IOCSTATUS_INTERNAL_ERROR:
394 desc = "internal error";
395 break;
396 case MPI2_IOCSTATUS_INVALID_VPID:
397 desc = "invalid vpid";
398 break;
399 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES:
400 desc = "insufficient resources";
401 break;
b130b0d5
SS		 402 case MPI2_IOCSTATUS_INSUFFICIENT_POWER:
403 desc = "insufficient power";
404 break;
f92363d1
SR		 405 case MPI2_IOCSTATUS_INVALID_FIELD:
406 desc = "invalid field";
407 break;
408 case MPI2_IOCSTATUS_INVALID_STATE:
409 desc = "invalid state";
410 break;
411 case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED:
412 desc = "op state not supported";
413 break;
414
415/****************************************************************************
416* Config IOCStatus values
417****************************************************************************/
418
419 case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION:
420 desc = "config invalid action";
421 break;
422 case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE:
423 desc = "config invalid type";
424 break;
425 case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE:
426 desc = "config invalid page";
427 break;
428 case MPI2_IOCSTATUS_CONFIG_INVALID_DATA:
429 desc = "config invalid data";
430 break;
431 case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS:
432 desc = "config no defaults";
433 break;
434 case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT:
435 desc = "config cant commit";
436 break;
437
438/****************************************************************************
439* SCSI IO Reply
440****************************************************************************/
441
442 case MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR:
443 case MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE:
444 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
445 case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN:
446 case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN:
447 case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR:
448 case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR:
449 case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED:
450 case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH:
451 case MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED:
452 case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED:
453 case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED:
454 break;
455
456/****************************************************************************
457* For use by SCSI Initiator and SCSI Target end-to-end data protection
458****************************************************************************/
459
460 case MPI2_IOCSTATUS_EEDP_GUARD_ERROR:
461 desc = "eedp guard error";
462 break;
463 case MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR:
464 desc = "eedp ref tag error";
465 break;
466 case MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR:
467 desc = "eedp app tag error";
468 break;
469
470/****************************************************************************
471* SCSI Target values
472****************************************************************************/
473
474 case MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX:
475 desc = "target invalid io index";
476 break;
477 case MPI2_IOCSTATUS_TARGET_ABORTED:
478 desc = "target aborted";
479 break;
480 case MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE:
481 desc = "target no conn retryable";
482 break;
483 case MPI2_IOCSTATUS_TARGET_NO_CONNECTION:
484 desc = "target no connection";
485 break;
486 case MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH:
487 desc = "target xfer count mismatch";
488 break;
489 case MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR:
490 desc = "target data offset error";
491 break;
492 case MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA:
493 desc = "target too much write data";
494 break;
495 case MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT:
496 desc = "target iu too short";
497 break;
498 case MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT:
499 desc = "target ack nak timeout";
500 break;
501 case MPI2_IOCSTATUS_TARGET_NAK_RECEIVED:
502 desc = "target nak received";
503 break;
504
505/****************************************************************************
506* Serial Attached SCSI values
507****************************************************************************/
508
509 case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED:
510 desc = "smp request failed";
511 break;
512 case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN:
513 desc = "smp data overrun";
514 break;
515
516/****************************************************************************
517* Diagnostic Buffer Post / Diagnostic Release values
518****************************************************************************/
519
520 case MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED:
521 desc = "diagnostic released";
522 break;
523 default:
524 break;
525 }
526
527 if (!desc)
528 return;
529
530 switch (request_hdr->Function) {
531 case MPI2_FUNCTION_CONFIG:
532 frame_sz = sizeof(Mpi2ConfigRequest_t) + ioc->sge_size;
533 func_str = "config_page";
534 break;
535 case MPI2_FUNCTION_SCSI_TASK_MGMT:
536 frame_sz = sizeof(Mpi2SCSITaskManagementRequest_t);
537 func_str = "task_mgmt";
538 break;
539 case MPI2_FUNCTION_SAS_IO_UNIT_CONTROL:
540 frame_sz = sizeof(Mpi2SasIoUnitControlRequest_t);
541 func_str = "sas_iounit_ctl";
542 break;
543 case MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR:
544 frame_sz = sizeof(Mpi2SepRequest_t);
545 func_str = "enclosure";
546 break;
547 case MPI2_FUNCTION_IOC_INIT:
548 frame_sz = sizeof(Mpi2IOCInitRequest_t);
549 func_str = "ioc_init";
550 break;
551 case MPI2_FUNCTION_PORT_ENABLE:
552 frame_sz = sizeof(Mpi2PortEnableRequest_t);
553 func_str = "port_enable";
554 break;
555 case MPI2_FUNCTION_SMP_PASSTHROUGH:
556 frame_sz = sizeof(Mpi2SmpPassthroughRequest_t) + ioc->sge_size;
557 func_str = "smp_passthru";
558 break;
559 default:
560 frame_sz = 32;
561 func_str = "unknown";
562 break;
563 }
564
565 pr_warn(MPT3SAS_FMT "ioc_status: %s(0x%04x), request(0x%p),(%s)\n",
566 ioc->name, desc, ioc_status, request_hdr, func_str);
567
568 _debug_dump_mf(request_hdr, frame_sz/4);
569}
570
571/**
572 * _base_display_event_data - verbose translation of firmware asyn events
573 * @ioc: per adapter object
574 * @mpi_reply: reply mf payload returned from firmware
575 *
576 * Return nothing.
577 */
578static void
579_base_display_event_data(struct MPT3SAS_ADAPTER *ioc,
580 Mpi2EventNotificationReply_t *mpi_reply)
581{
582 char *desc = NULL;
583 u16 event;
584
585 if (!(ioc->logging_level & MPT_DEBUG_EVENTS))
586 return;
587
588 event = le16_to_cpu(mpi_reply->Event);
589
590 switch (event) {
591 case MPI2_EVENT_LOG_DATA:
592 desc = "Log Data";
593 break;
594 case MPI2_EVENT_STATE_CHANGE:
595 desc = "Status Change";
596 break;
597 case MPI2_EVENT_HARD_RESET_RECEIVED:
598 desc = "Hard Reset Received";
599 break;
600 case MPI2_EVENT_EVENT_CHANGE:
601 desc = "Event Change";
602 break;
603 case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE:
604 desc = "Device Status Change";
605 break;
606 case MPI2_EVENT_IR_OPERATION_STATUS:
7786ab6a
SR		 607 if (!ioc->hide_ir_msg)
608 desc = "IR Operation Status";
f92363d1
SR		 609 break;
610 case MPI2_EVENT_SAS_DISCOVERY:
611 {
612 Mpi2EventDataSasDiscovery_t *event_data =
613 (Mpi2EventDataSasDiscovery_t *)mpi_reply->EventData;
614 pr_info(MPT3SAS_FMT "Discovery: (%s)", ioc->name,
615 (event_data->ReasonCode == MPI2_EVENT_SAS_DISC_RC_STARTED) ?
616 "start" : "stop");
617 if (event_data->DiscoveryStatus)
618 pr_info("discovery_status(0x%08x)",
619 le32_to_cpu(event_data->DiscoveryStatus));
620 pr_info("\n");
621 return;
622 }
623 case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE:
624 desc = "SAS Broadcast Primitive";
625 break;
626 case MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
627 desc = "SAS Init Device Status Change";
628 break;
629 case MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW:
630 desc = "SAS Init Table Overflow";
631 break;
632 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
633 desc = "SAS Topology Change List";
634 break;
635 case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE:
636 desc = "SAS Enclosure Device Status Change";
637 break;
638 case MPI2_EVENT_IR_VOLUME:
7786ab6a
SR		 639 if (!ioc->hide_ir_msg)
640 desc = "IR Volume";
f92363d1
SR		 641 break;
642 case MPI2_EVENT_IR_PHYSICAL_DISK:
7786ab6a
SR		 643 if (!ioc->hide_ir_msg)
644 desc = "IR Physical Disk";
f92363d1
SR		 645 break;
646 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
7786ab6a
SR		 647 if (!ioc->hide_ir_msg)
648 desc = "IR Configuration Change List";
f92363d1
SR		 649 break;
650 case MPI2_EVENT_LOG_ENTRY_ADDED:
7786ab6a
SR		 651 if (!ioc->hide_ir_msg)
652 desc = "Log Entry Added";
f92363d1 653 break;
2d8ce8c9
SR		 654 case MPI2_EVENT_TEMP_THRESHOLD:
655 desc = "Temperature Threshold";
656 break;
a470a51c
C		 657 case MPI2_EVENT_ACTIVE_CABLE_EXCEPTION:
658 desc = "Active cable exception";
659 break;
f92363d1
SR		 660 }
661
662 if (!desc)
663 return;
664
665 pr_info(MPT3SAS_FMT "%s\n", ioc->name, desc);
666}
f92363d1
SR		 667
668/**
669 * _base_sas_log_info - verbose translation of firmware log info
670 * @ioc: per adapter object
671 * @log_info: log info
672 *
673 * Return nothing.
674 */
675static void
676_base_sas_log_info(struct MPT3SAS_ADAPTER *ioc , u32 log_info)
677{
678 union loginfo_type {
679 u32 loginfo;
680 struct {
681 u32 subcode:16;
682 u32 code:8;
683 u32 originator:4;
684 u32 bus_type:4;
685 } dw;
686 };
687 union loginfo_type sas_loginfo;
688 char *originator_str = NULL;
689
690 sas_loginfo.loginfo = log_info;
691 if (sas_loginfo.dw.bus_type != 3 /*SAS*/)
692 return;
693
694 /* each nexus loss loginfo */
695 if (log_info == 0x31170000)
696 return;
697
698 /* eat the loginfos associated with task aborts */
699 if (ioc->ignore_loginfos && (log_info == 0x30050000 || log_info ==
700 0x31140000 || log_info == 0x31130000))
701 return;
702
703 switch (sas_loginfo.dw.originator) {
704 case 0:
705 originator_str = "IOP";
706 break;
707 case 1:
708 originator_str = "PL";
709 break;
710 case 2:
7786ab6a
SR		 711 if (!ioc->hide_ir_msg)
712 originator_str = "IR";
713 else
714 originator_str = "WarpDrive";
f92363d1
SR		 715 break;
716 }
717
718 pr_warn(MPT3SAS_FMT
719 "log_info(0x%08x): originator(%s), code(0x%02x), sub_code(0x%04x)\n",
720 ioc->name, log_info,
721 originator_str, sas_loginfo.dw.code,
722 sas_loginfo.dw.subcode);
723}
724
725/**
726 * _base_display_reply_info -
727 * @ioc: per adapter object
728 * @smid: system request message index
729 * @msix_index: MSIX table index supplied by the OS
730 * @reply: reply message frame(lower 32bit addr)
731 *
732 * Return nothing.
733 */
734static void
735_base_display_reply_info(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
736 u32 reply)
737{
738 MPI2DefaultReply_t *mpi_reply;
739 u16 ioc_status;
740 u32 loginfo = 0;
741
742 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
743 if (unlikely(!mpi_reply)) {
744 pr_err(MPT3SAS_FMT "mpi_reply not valid at %s:%d/%s()!\n",
745 ioc->name, __FILE__, __LINE__, __func__);
746 return;
747 }
748 ioc_status = le16_to_cpu(mpi_reply->IOCStatus);
af009411 749
f92363d1
SR		 750 if ((ioc_status & MPI2_IOCSTATUS_MASK) &&
751 (ioc->logging_level & MPT_DEBUG_REPLY)) {
752 _base_sas_ioc_info(ioc , mpi_reply,
753 mpt3sas_base_get_msg_frame(ioc, smid));
754 }
af009411 755
f92363d1
SR		 756 if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
757 loginfo = le32_to_cpu(mpi_reply->IOCLogInfo);
758 _base_sas_log_info(ioc, loginfo);
759 }
760
761 if (ioc_status || loginfo) {
762 ioc_status &= MPI2_IOCSTATUS_MASK;
763 mpt3sas_trigger_mpi(ioc, ioc_status, loginfo);
764 }
765}
766
767/**
768 * mpt3sas_base_done - base internal command completion routine
769 * @ioc: per adapter object
770 * @smid: system request message index
771 * @msix_index: MSIX table index supplied by the OS
772 * @reply: reply message frame(lower 32bit addr)
773 *
774 * Return 1 meaning mf should be freed from _base_interrupt
775 * 0 means the mf is freed from this function.
776 */
777u8
778mpt3sas_base_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
779 u32 reply)
780{
781 MPI2DefaultReply_t *mpi_reply;
782
783 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
784 if (mpi_reply && mpi_reply->Function == MPI2_FUNCTION_EVENT_ACK)
fd0331b3 785 return mpt3sas_check_for_pending_internal_cmds(ioc, smid);
f92363d1
SR		 786
787 if (ioc->base_cmds.status == MPT3_CMD_NOT_USED)
788 return 1;
789
790 ioc->base_cmds.status |= MPT3_CMD_COMPLETE;
791 if (mpi_reply) {
792 ioc->base_cmds.status |= MPT3_CMD_REPLY_VALID;
793 memcpy(ioc->base_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
794 }
795 ioc->base_cmds.status &= ~MPT3_CMD_PENDING;
796
797 complete(&ioc->base_cmds.done);
798 return 1;
799}
800
801/**
802 * _base_async_event - main callback handler for firmware asyn events
803 * @ioc: per adapter object
804 * @msix_index: MSIX table index supplied by the OS
805 * @reply: reply message frame(lower 32bit addr)
806 *
807 * Return 1 meaning mf should be freed from _base_interrupt
808 * 0 means the mf is freed from this function.
809 */
810static u8
811_base_async_event(struct MPT3SAS_ADAPTER *ioc, u8 msix_index, u32 reply)
812{
813 Mpi2EventNotificationReply_t *mpi_reply;
814 Mpi2EventAckRequest_t *ack_request;
815 u16 smid;
fd0331b3 816 struct _event_ack_list *delayed_event_ack;
f92363d1
SR		 817
818 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
819 if (!mpi_reply)
820 return 1;
821 if (mpi_reply->Function != MPI2_FUNCTION_EVENT_NOTIFICATION)
822 return 1;
af009411 823
f92363d1 824 _base_display_event_data(ioc, mpi_reply);
af009411 825
f92363d1
SR		 826 if (!(mpi_reply->AckRequired & MPI2_EVENT_NOTIFICATION_ACK_REQUIRED))
827 goto out;
828 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
829 if (!smid) {
fd0331b3
SS		 830 delayed_event_ack = kzalloc(sizeof(*delayed_event_ack),
831 GFP_ATOMIC);
832 if (!delayed_event_ack)
833 goto out;
834 INIT_LIST_HEAD(&delayed_event_ack->list);
835 delayed_event_ack->Event = mpi_reply->Event;
836 delayed_event_ack->EventContext = mpi_reply->EventContext;
837 list_add_tail(&delayed_event_ack->list,
838 &ioc->delayed_event_ack_list);
839 dewtprintk(ioc, pr_info(MPT3SAS_FMT
840 "DELAYED: EVENT ACK: event (0x%04x)\n",
841 ioc->name, le16_to_cpu(mpi_reply->Event)));
f92363d1
SR		 842 goto out;
843 }
844
845 ack_request = mpt3sas_base_get_msg_frame(ioc, smid);
846 memset(ack_request, 0, sizeof(Mpi2EventAckRequest_t));
847 ack_request->Function = MPI2_FUNCTION_EVENT_ACK;
848 ack_request->Event = mpi_reply->Event;
849 ack_request->EventContext = mpi_reply->EventContext;
850 ack_request->VF_ID = 0; /* TODO */
851 ack_request->VP_ID = 0;
852 mpt3sas_base_put_smid_default(ioc, smid);
853
854 out:
855
856 /* scsih callback handler */
857 mpt3sas_scsih_event_callback(ioc, msix_index, reply);
858
859 /* ctl callback handler */
860 mpt3sas_ctl_event_callback(ioc, msix_index, reply);
861
862 return 1;
863}
864
865/**
866 * _base_get_cb_idx - obtain the callback index
867 * @ioc: per adapter object
868 * @smid: system request message index
869 *
870 * Return callback index.
871 */
872static u8
873_base_get_cb_idx(struct MPT3SAS_ADAPTER *ioc, u16 smid)
874{
875 int i;
876 u8 cb_idx;
877
878 if (smid < ioc->hi_priority_smid) {
879 i = smid - 1;
880 cb_idx = ioc->scsi_lookup[i].cb_idx;
881 } else if (smid < ioc->internal_smid) {
882 i = smid - ioc->hi_priority_smid;
883 cb_idx = ioc->hpr_lookup[i].cb_idx;
884 } else if (smid <= ioc->hba_queue_depth) {
885 i = smid - ioc->internal_smid;
886 cb_idx = ioc->internal_lookup[i].cb_idx;
887 } else
888 cb_idx = 0xFF;
889 return cb_idx;
890}
891
892/**
893 * _base_mask_interrupts - disable interrupts
894 * @ioc: per adapter object
895 *
896 * Disabling ResetIRQ, Reply and Doorbell Interrupts
897 *
898 * Return nothing.
899 */
900static void
901_base_mask_interrupts(struct MPT3SAS_ADAPTER *ioc)
902{
903 u32 him_register;
904
905 ioc->mask_interrupts = 1;
906 him_register = readl(&ioc->chip->HostInterruptMask);
907 him_register |= MPI2_HIM_DIM + MPI2_HIM_RIM + MPI2_HIM_RESET_IRQ_MASK;
908 writel(him_register, &ioc->chip->HostInterruptMask);
909 readl(&ioc->chip->HostInterruptMask);
910}
911
912/**
913 * _base_unmask_interrupts - enable interrupts
914 * @ioc: per adapter object
915 *
916 * Enabling only Reply Interrupts
917 *
918 * Return nothing.
919 */
920static void
921_base_unmask_interrupts(struct MPT3SAS_ADAPTER *ioc)
922{
923 u32 him_register;
924
925 him_register = readl(&ioc->chip->HostInterruptMask);
926 him_register &= ~MPI2_HIM_RIM;
927 writel(him_register, &ioc->chip->HostInterruptMask);
928 ioc->mask_interrupts = 0;
929}
930
931union reply_descriptor {
932 u64 word;
933 struct {
934 u32 low;
935 u32 high;
936 } u;
937};
938
939/**
940 * _base_interrupt - MPT adapter (IOC) specific interrupt handler.
941 * @irq: irq number (not used)
942 * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure
943 * @r: pt_regs pointer (not used)
944 *
945 * Return IRQ_HANDLE if processed, else IRQ_NONE.
946 */
947static irqreturn_t
948_base_interrupt(int irq, void *bus_id)
949{
950 struct adapter_reply_queue *reply_q = bus_id;
951 union reply_descriptor rd;
952 u32 completed_cmds;
953 u8 request_desript_type;
954 u16 smid;
955 u8 cb_idx;
956 u32 reply;
957 u8 msix_index = reply_q->msix_index;
958 struct MPT3SAS_ADAPTER *ioc = reply_q->ioc;
959 Mpi2ReplyDescriptorsUnion_t *rpf;
960 u8 rc;
961
962 if (ioc->mask_interrupts)
963 return IRQ_NONE;
964
965 if (!atomic_add_unless(&reply_q->busy, 1, 1))
966 return IRQ_NONE;
967
968 rpf = &reply_q->reply_post_free[reply_q->reply_post_host_index];
969 request_desript_type = rpf->Default.ReplyFlags
970 & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
971 if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) {
972 atomic_dec(&reply_q->busy);
973 return IRQ_NONE;
974 }
975
976 completed_cmds = 0;
977 cb_idx = 0xFF;
978 do {
979 rd.word = le64_to_cpu(rpf->Words);
980 if (rd.u.low == UINT_MAX || rd.u.high == UINT_MAX)
981 goto out;
982 reply = 0;
983 smid = le16_to_cpu(rpf->Default.DescriptorTypeDependent1);
984 if (request_desript_type ==
985 MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS ||
986 request_desript_type ==
987 MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS) {
988 cb_idx = _base_get_cb_idx(ioc, smid);
989 if ((likely(cb_idx < MPT_MAX_CALLBACKS)) &&
990 (likely(mpt_callbacks[cb_idx] != NULL))) {
991 rc = mpt_callbacks[cb_idx](ioc, smid,
992 msix_index, 0);
993 if (rc)
994 mpt3sas_base_free_smid(ioc, smid);
995 }
996 } else if (request_desript_type ==
997 MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) {
998 reply = le32_to_cpu(
999 rpf->AddressReply.ReplyFrameAddress);
1000 if (reply > ioc->reply_dma_max_address ||
1001 reply < ioc->reply_dma_min_address)
1002 reply = 0;
1003 if (smid) {
1004 cb_idx = _base_get_cb_idx(ioc, smid);
1005 if ((likely(cb_idx < MPT_MAX_CALLBACKS)) &&
1006 (likely(mpt_callbacks[cb_idx] != NULL))) {
1007 rc = mpt_callbacks[cb_idx](ioc, smid,
1008 msix_index, reply);
1009 if (reply)
1010 _base_display_reply_info(ioc,
1011 smid, msix_index, reply);
1012 if (rc)
1013 mpt3sas_base_free_smid(ioc,
1014 smid);
1015 }
1016 } else {
1017 _base_async_event(ioc, msix_index, reply);
1018 }
1019
1020 /* reply free queue handling */
1021 if (reply) {
1022 ioc->reply_free_host_index =
1023 (ioc->reply_free_host_index ==
1024 (ioc->reply_free_queue_depth - 1)) ?
1025 0 : ioc->reply_free_host_index + 1;
1026 ioc->reply_free[ioc->reply_free_host_index] =
1027 cpu_to_le32(reply);
1028 wmb();
1029 writel(ioc->reply_free_host_index,
1030 &ioc->chip->ReplyFreeHostIndex);
1031 }
1032 }
1033
1034 rpf->Words = cpu_to_le64(ULLONG_MAX);
1035 reply_q->reply_post_host_index =
1036 (reply_q->reply_post_host_index ==
1037 (ioc->reply_post_queue_depth - 1)) ? 0 :
1038 reply_q->reply_post_host_index + 1;
1039 request_desript_type =
1040 reply_q->reply_post_free[reply_q->reply_post_host_index].
1041 Default.ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
1042 completed_cmds++;
1043 if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED)
1044 goto out;
1045 if (!reply_q->reply_post_host_index)
1046 rpf = reply_q->reply_post_free;
1047 else
1048 rpf++;
1049 } while (1);
1050
1051 out:
1052
1053 if (!completed_cmds) {
1054 atomic_dec(&reply_q->busy);
1055 return IRQ_NONE;
1056 }
1057
1058 wmb();
7786ab6a
SR		 1059 if (ioc->is_warpdrive) {
1060 writel(reply_q->reply_post_host_index,
1061 ioc->reply_post_host_index[msix_index]);
1062 atomic_dec(&reply_q->busy);
1063 return IRQ_HANDLED;
1064 }
fb77bb53
SR		 1065
1066 /* Update Reply Post Host Index.
1067 * For those HBA's which support combined reply queue feature
1068 * 1. Get the correct Supplemental Reply Post Host Index Register.
1069 * i.e. (msix_index / 8)th entry from Supplemental Reply Post Host
1070 * Index Register address bank i.e replyPostRegisterIndex[],
1071 * 2. Then update this register with new reply host index value
1072 * in ReplyPostIndex field and the MSIxIndex field with
1073 * msix_index value reduced to a value between 0 and 7,
1074 * using a modulo 8 operation. Since each Supplemental Reply Post
1075 * Host Index Register supports 8 MSI-X vectors.
1076 *
1077 * For other HBA's just update the Reply Post Host Index register with
1078 * new reply host index value in ReplyPostIndex Field and msix_index
1079 * value in MSIxIndex field.
1080 */
0bb337c9 1081 if (ioc->combined_reply_queue)
fb77bb53
SR		 1082 writel(reply_q->reply_post_host_index | ((msix_index & 7) <<
1083 MPI2_RPHI_MSIX_INDEX_SHIFT),
1084 ioc->replyPostRegisterIndex[msix_index/8]);
1085 else
1086 writel(reply_q->reply_post_host_index | (msix_index <<
1087 MPI2_RPHI_MSIX_INDEX_SHIFT),
1088 &ioc->chip->ReplyPostHostIndex);
f92363d1
SR		 1089 atomic_dec(&reply_q->busy);
1090 return IRQ_HANDLED;
1091}
1092
1093/**
1094 * _base_is_controller_msix_enabled - is controller support muli-reply queues
1095 * @ioc: per adapter object
1096 *
1097 */
1098static inline int
1099_base_is_controller_msix_enabled(struct MPT3SAS_ADAPTER *ioc)
1100{
1101 return (ioc->facts.IOCCapabilities &
1102 MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX) && ioc->msix_enable;
1103}
1104
1105/**
5f0dfb7a 1106 * mpt3sas_base_sync_reply_irqs - flush pending MSIX interrupts
f92363d1 1107 * @ioc: per adapter object
5f0dfb7a 1108 * Context: non ISR conext
f92363d1 1109 *
5f0dfb7a 1110 * Called when a Task Management request has completed.
f92363d1
SR		 1111 *
1112 * Return nothing.
1113 */
1114void
5f0dfb7a 1115mpt3sas_base_sync_reply_irqs(struct MPT3SAS_ADAPTER *ioc)
f92363d1
SR		 1116{
1117 struct adapter_reply_queue *reply_q;
1118
1119 /* If MSIX capability is turned off
1120 * then multi-queues are not enabled
1121 */
1122 if (!_base_is_controller_msix_enabled(ioc))
1123 return;
1124
1125 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
5f0dfb7a
C		 1126 if (ioc->shost_recovery || ioc->remove_host ||
1127 ioc->pci_error_recovery)
f92363d1
SR		 1128 return;
1129 /* TMs are on msix_index == 0 */
1130 if (reply_q->msix_index == 0)
1131 continue;
5f0dfb7a 1132 synchronize_irq(reply_q->vector);
f92363d1
SR		 1133 }
1134}
1135
1136/**
1137 * mpt3sas_base_release_callback_handler - clear interrupt callback handler
1138 * @cb_idx: callback index
1139 *
1140 * Return nothing.
1141 */
1142void
1143mpt3sas_base_release_callback_handler(u8 cb_idx)
1144{
1145 mpt_callbacks[cb_idx] = NULL;
1146}
1147
1148/**
1149 * mpt3sas_base_register_callback_handler - obtain index for the interrupt callback handler
1150 * @cb_func: callback function
1151 *
1152 * Returns cb_func.
1153 */
1154u8
1155mpt3sas_base_register_callback_handler(MPT_CALLBACK cb_func)
1156{
1157 u8 cb_idx;
1158
1159 for (cb_idx = MPT_MAX_CALLBACKS-1; cb_idx; cb_idx--)
1160 if (mpt_callbacks[cb_idx] == NULL)
1161 break;
1162
1163 mpt_callbacks[cb_idx] = cb_func;
1164 return cb_idx;
1165}
1166
1167/**
1168 * mpt3sas_base_initialize_callback_handler - initialize the interrupt callback handler
1169 *
1170 * Return nothing.
1171 */
1172void
1173mpt3sas_base_initialize_callback_handler(void)
1174{
1175 u8 cb_idx;
1176
1177 for (cb_idx = 0; cb_idx < MPT_MAX_CALLBACKS; cb_idx++)
1178 mpt3sas_base_release_callback_handler(cb_idx);
1179}
1180
1181
1182/**
1183 * _base_build_zero_len_sge - build zero length sg entry
1184 * @ioc: per adapter object
1185 * @paddr: virtual address for SGE
1186 *
1187 * Create a zero length scatter gather entry to insure the IOCs hardware has
1188 * something to use if the target device goes brain dead and tries
1189 * to send data even when none is asked for.
1190 *
1191 * Return nothing.
1192 */
1193static void
1194_base_build_zero_len_sge(struct MPT3SAS_ADAPTER *ioc, void *paddr)
1195{
1196 u32 flags_length = (u32)((MPI2_SGE_FLAGS_LAST_ELEMENT |
1197 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST |
1198 MPI2_SGE_FLAGS_SIMPLE_ELEMENT) <<
1199 MPI2_SGE_FLAGS_SHIFT);
1200 ioc->base_add_sg_single(paddr, flags_length, -1);
1201}
1202
1203/**
1204 * _base_add_sg_single_32 - Place a simple 32 bit SGE at address pAddr.
1205 * @paddr: virtual address for SGE
1206 * @flags_length: SGE flags and data transfer length
1207 * @dma_addr: Physical address
1208 *
1209 * Return nothing.
1210 */
1211static void
1212_base_add_sg_single_32(void *paddr, u32 flags_length, dma_addr_t dma_addr)
1213{
1214 Mpi2SGESimple32_t *sgel = paddr;
1215
1216 flags_length |= (MPI2_SGE_FLAGS_32_BIT_ADDRESSING |
1217 MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
1218 sgel->FlagsLength = cpu_to_le32(flags_length);
1219 sgel->Address = cpu_to_le32(dma_addr);
1220}
1221
1222
1223/**
1224 * _base_add_sg_single_64 - Place a simple 64 bit SGE at address pAddr.
1225 * @paddr: virtual address for SGE
1226 * @flags_length: SGE flags and data transfer length
1227 * @dma_addr: Physical address
1228 *
1229 * Return nothing.
1230 */
1231static void
1232_base_add_sg_single_64(void *paddr, u32 flags_length, dma_addr_t dma_addr)
1233{
1234 Mpi2SGESimple64_t *sgel = paddr;
1235
1236 flags_length |= (MPI2_SGE_FLAGS_64_BIT_ADDRESSING |
1237 MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
1238 sgel->FlagsLength = cpu_to_le32(flags_length);
1239 sgel->Address = cpu_to_le64(dma_addr);
1240}
1241
1242/**
1243 * _base_get_chain_buffer_tracker - obtain chain tracker
1244 * @ioc: per adapter object
1245 * @smid: smid associated to an IO request
1246 *
1247 * Returns chain tracker(from ioc->free_chain_list)
1248 */
1249static struct chain_tracker *
1250_base_get_chain_buffer_tracker(struct MPT3SAS_ADAPTER *ioc, u16 smid)
1251{
1252 struct chain_tracker *chain_req;
1253 unsigned long flags;
1254
1255 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
1256 if (list_empty(&ioc->free_chain_list)) {
1257 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
1258 dfailprintk(ioc, pr_warn(MPT3SAS_FMT
1259 "chain buffers not available\n", ioc->name));
1260 return NULL;
1261 }
1262 chain_req = list_entry(ioc->free_chain_list.next,
1263 struct chain_tracker, tracker_list);
1264 list_del_init(&chain_req->tracker_list);
1265 list_add_tail(&chain_req->tracker_list,
1266 &ioc->scsi_lookup[smid - 1].chain_list);
1267 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
1268 return chain_req;
1269}
1270
1271
1272/**
1273 * _base_build_sg - build generic sg
1274 * @ioc: per adapter object
1275 * @psge: virtual address for SGE
1276 * @data_out_dma: physical address for WRITES
1277 * @data_out_sz: data xfer size for WRITES
1278 * @data_in_dma: physical address for READS
1279 * @data_in_sz: data xfer size for READS
1280 *
1281 * Return nothing.
1282 */
1283static void
1284_base_build_sg(struct MPT3SAS_ADAPTER *ioc, void *psge,
1285 dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
1286 size_t data_in_sz)
1287{
1288 u32 sgl_flags;
1289
1290 if (!data_out_sz && !data_in_sz) {
1291 _base_build_zero_len_sge(ioc, psge);
1292 return;
1293 }
1294
1295 if (data_out_sz && data_in_sz) {
1296 /* WRITE sgel first */
1297 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1298 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_HOST_TO_IOC);
1299 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1300 ioc->base_add_sg_single(psge, sgl_flags |
1301 data_out_sz, data_out_dma);
1302
1303 /* incr sgel */
1304 psge += ioc->sge_size;
1305
1306 /* READ sgel last */
1307 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1308 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
1309 MPI2_SGE_FLAGS_END_OF_LIST);
1310 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1311 ioc->base_add_sg_single(psge, sgl_flags |
1312 data_in_sz, data_in_dma);
1313 } else if (data_out_sz) /* WRITE */ {
1314 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1315 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
1316 MPI2_SGE_FLAGS_END_OF_LIST | MPI2_SGE_FLAGS_HOST_TO_IOC);
1317 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1318 ioc->base_add_sg_single(psge, sgl_flags |
1319 data_out_sz, data_out_dma);
1320 } else if (data_in_sz) /* READ */ {
1321 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1322 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
1323 MPI2_SGE_FLAGS_END_OF_LIST);
1324 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1325 ioc->base_add_sg_single(psge, sgl_flags |
1326 data_in_sz, data_in_dma);
1327 }
1328}
1329
1330/* IEEE format sgls */
1331
1332/**
1333 * _base_add_sg_single_ieee - add sg element for IEEE format
1334 * @paddr: virtual address for SGE
1335 * @flags: SGE flags
1336 * @chain_offset: number of 128 byte elements from start of segment
1337 * @length: data transfer length
1338 * @dma_addr: Physical address
1339 *
1340 * Return nothing.
1341 */
1342static void
1343_base_add_sg_single_ieee(void *paddr, u8 flags, u8 chain_offset, u32 length,
1344 dma_addr_t dma_addr)
1345{
1346 Mpi25IeeeSgeChain64_t *sgel = paddr;
1347
1348 sgel->Flags = flags;
1349 sgel->NextChainOffset = chain_offset;
1350 sgel->Length = cpu_to_le32(length);
1351 sgel->Address = cpu_to_le64(dma_addr);
1352}
1353
1354/**
1355 * _base_build_zero_len_sge_ieee - build zero length sg entry for IEEE format
1356 * @ioc: per adapter object
1357 * @paddr: virtual address for SGE
1358 *
1359 * Create a zero length scatter gather entry to insure the IOCs hardware has
1360 * something to use if the target device goes brain dead and tries
1361 * to send data even when none is asked for.
1362 *
1363 * Return nothing.
1364 */
1365static void
1366_base_build_zero_len_sge_ieee(struct MPT3SAS_ADAPTER *ioc, void *paddr)
1367{
1368 u8 sgl_flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1369 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR |
1370 MPI25_IEEE_SGE_FLAGS_END_OF_LIST);
b130b0d5 1371
f92363d1
SR		 1372 _base_add_sg_single_ieee(paddr, sgl_flags, 0, 0, -1);
1373}
1374
471ef9d4
SR		 1375/**
1376 * _base_build_sg_scmd - main sg creation routine
1377 * @ioc: per adapter object
1378 * @scmd: scsi command
1379 * @smid: system request message index
1380 * Context: none.
1381 *
1382 * The main routine that builds scatter gather table from a given
1383 * scsi request sent via the .queuecommand main handler.
1384 *
1385 * Returns 0 success, anything else error
1386 */
1387static int
1388_base_build_sg_scmd(struct MPT3SAS_ADAPTER *ioc,
1389 struct scsi_cmnd *scmd, u16 smid)
1390{
1391 Mpi2SCSIIORequest_t *mpi_request;
1392 dma_addr_t chain_dma;
1393 struct scatterlist *sg_scmd;
1394 void *sg_local, *chain;
1395 u32 chain_offset;
1396 u32 chain_length;
1397 u32 chain_flags;
1398 int sges_left;
1399 u32 sges_in_segment;
1400 u32 sgl_flags;
1401 u32 sgl_flags_last_element;
1402 u32 sgl_flags_end_buffer;
1403 struct chain_tracker *chain_req;
1404
1405 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
1406
1407 /* init scatter gather flags */
1408 sgl_flags = MPI2_SGE_FLAGS_SIMPLE_ELEMENT;
1409 if (scmd->sc_data_direction == DMA_TO_DEVICE)
1410 sgl_flags |= MPI2_SGE_FLAGS_HOST_TO_IOC;
1411 sgl_flags_last_element = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT)
1412 << MPI2_SGE_FLAGS_SHIFT;
1413 sgl_flags_end_buffer = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT |
1414 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST)
1415 << MPI2_SGE_FLAGS_SHIFT;
1416 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1417
1418 sg_scmd = scsi_sglist(scmd);
1419 sges_left = scsi_dma_map(scmd);
1420 if (sges_left < 0) {
1421 sdev_printk(KERN_ERR, scmd->device,
1422 "pci_map_sg failed: request for %d bytes!\n",
1423 scsi_bufflen(scmd));
1424 return -ENOMEM;
1425 }
1426
1427 sg_local = &mpi_request->SGL;
1428 sges_in_segment = ioc->max_sges_in_main_message;
1429 if (sges_left <= sges_in_segment)
1430 goto fill_in_last_segment;
1431
1432 mpi_request->ChainOffset = (offsetof(Mpi2SCSIIORequest_t, SGL) +
1433 (sges_in_segment * ioc->sge_size))/4;
1434
1435 /* fill in main message segment when there is a chain following */
1436 while (sges_in_segment) {
1437 if (sges_in_segment == 1)
1438 ioc->base_add_sg_single(sg_local,
1439 sgl_flags_last_element | sg_dma_len(sg_scmd),
1440 sg_dma_address(sg_scmd));
1441 else
1442 ioc->base_add_sg_single(sg_local, sgl_flags |
1443 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1444 sg_scmd = sg_next(sg_scmd);
1445 sg_local += ioc->sge_size;
1446 sges_left--;
1447 sges_in_segment--;
1448 }
1449
1450 /* initializing the chain flags and pointers */
1451 chain_flags = MPI2_SGE_FLAGS_CHAIN_ELEMENT << MPI2_SGE_FLAGS_SHIFT;
1452 chain_req = _base_get_chain_buffer_tracker(ioc, smid);
1453 if (!chain_req)
1454 return -1;
1455 chain = chain_req->chain_buffer;
1456 chain_dma = chain_req->chain_buffer_dma;
1457 do {
1458 sges_in_segment = (sges_left <=
1459 ioc->max_sges_in_chain_message) ? sges_left :
1460 ioc->max_sges_in_chain_message;
1461 chain_offset = (sges_left == sges_in_segment) ?
1462 0 : (sges_in_segment * ioc->sge_size)/4;
1463 chain_length = sges_in_segment * ioc->sge_size;
1464 if (chain_offset) {
1465 chain_offset = chain_offset <<
1466 MPI2_SGE_CHAIN_OFFSET_SHIFT;
1467 chain_length += ioc->sge_size;
1468 }
1469 ioc->base_add_sg_single(sg_local, chain_flags | chain_offset |
1470 chain_length, chain_dma);
1471 sg_local = chain;
1472 if (!chain_offset)
1473 goto fill_in_last_segment;
1474
1475 /* fill in chain segments */
1476 while (sges_in_segment) {
1477 if (sges_in_segment == 1)
1478 ioc->base_add_sg_single(sg_local,
1479 sgl_flags_last_element |
1480 sg_dma_len(sg_scmd),
1481 sg_dma_address(sg_scmd));
1482 else
1483 ioc->base_add_sg_single(sg_local, sgl_flags |
1484 sg_dma_len(sg_scmd),
1485 sg_dma_address(sg_scmd));
1486 sg_scmd = sg_next(sg_scmd);
1487 sg_local += ioc->sge_size;
1488 sges_left--;
1489 sges_in_segment--;
1490 }
1491
1492 chain_req = _base_get_chain_buffer_tracker(ioc, smid);
1493 if (!chain_req)
1494 return -1;
1495 chain = chain_req->chain_buffer;
1496 chain_dma = chain_req->chain_buffer_dma;
1497 } while (1);
1498
1499
1500 fill_in_last_segment:
1501
1502 /* fill the last segment */
1503 while (sges_left) {
1504 if (sges_left == 1)
1505 ioc->base_add_sg_single(sg_local, sgl_flags_end_buffer |
1506 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1507 else
1508 ioc->base_add_sg_single(sg_local, sgl_flags |
1509 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1510 sg_scmd = sg_next(sg_scmd);
1511 sg_local += ioc->sge_size;
1512 sges_left--;
1513 }
1514
1515 return 0;
1516}
1517
f92363d1
SR		 1518/**
1519 * _base_build_sg_scmd_ieee - main sg creation routine for IEEE format
1520 * @ioc: per adapter object
1521 * @scmd: scsi command
1522 * @smid: system request message index
1523 * Context: none.
1524 *
1525 * The main routine that builds scatter gather table from a given
1526 * scsi request sent via the .queuecommand main handler.
1527 *
1528 * Returns 0 success, anything else error
1529 */
1530static int
1531_base_build_sg_scmd_ieee(struct MPT3SAS_ADAPTER *ioc,
1532 struct scsi_cmnd *scmd, u16 smid)
1533{
1534 Mpi2SCSIIORequest_t *mpi_request;
1535 dma_addr_t chain_dma;
1536 struct scatterlist *sg_scmd;
1537 void *sg_local, *chain;
1538 u32 chain_offset;
1539 u32 chain_length;
f92363d1
SR		 1540 int sges_left;
1541 u32 sges_in_segment;
1542 u8 simple_sgl_flags;
1543 u8 simple_sgl_flags_last;
1544 u8 chain_sgl_flags;
1545 struct chain_tracker *chain_req;
1546
1547 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
1548
1549 /* init scatter gather flags */
1550 simple_sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1551 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1552 simple_sgl_flags_last = simple_sgl_flags |
1553 MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
1554 chain_sgl_flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
1555 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1556
1557 sg_scmd = scsi_sglist(scmd);
1558 sges_left = scsi_dma_map(scmd);
62f5c74c 1559 if (sges_left < 0) {
f92363d1
SR		 1560 sdev_printk(KERN_ERR, scmd->device,
1561 "pci_map_sg failed: request for %d bytes!\n",
1562 scsi_bufflen(scmd));
1563 return -ENOMEM;
1564 }
1565
1566 sg_local = &mpi_request->SGL;
1567 sges_in_segment = (ioc->request_sz -
1568 offsetof(Mpi2SCSIIORequest_t, SGL))/ioc->sge_size_ieee;
1569 if (sges_left <= sges_in_segment)
1570 goto fill_in_last_segment;
1571
1572 mpi_request->ChainOffset = (sges_in_segment - 1 /* chain element */) +
1573 (offsetof(Mpi2SCSIIORequest_t, SGL)/ioc->sge_size_ieee);
1574
1575 /* fill in main message segment when there is a chain following */
1576 while (sges_in_segment > 1) {
1577 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
1578 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1579 sg_scmd = sg_next(sg_scmd);
1580 sg_local += ioc->sge_size_ieee;
1581 sges_left--;
1582 sges_in_segment--;
1583 }
1584
25ef16d0 1585 /* initializing the pointers */
f92363d1
SR		 1586 chain_req = _base_get_chain_buffer_tracker(ioc, smid);
1587 if (!chain_req)
1588 return -1;
1589 chain = chain_req->chain_buffer;
1590 chain_dma = chain_req->chain_buffer_dma;
1591 do {
1592 sges_in_segment = (sges_left <=
1593 ioc->max_sges_in_chain_message) ? sges_left :
1594 ioc->max_sges_in_chain_message;
1595 chain_offset = (sges_left == sges_in_segment) ?
1596 0 : sges_in_segment;
1597 chain_length = sges_in_segment * ioc->sge_size_ieee;
1598 if (chain_offset)
1599 chain_length += ioc->sge_size_ieee;
1600 _base_add_sg_single_ieee(sg_local, chain_sgl_flags,
1601 chain_offset, chain_length, chain_dma);
1602
1603 sg_local = chain;
1604 if (!chain_offset)
1605 goto fill_in_last_segment;
1606
1607 /* fill in chain segments */
1608 while (sges_in_segment) {
1609 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
1610 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1611 sg_scmd = sg_next(sg_scmd);
1612 sg_local += ioc->sge_size_ieee;
1613 sges_left--;
1614 sges_in_segment--;
1615 }
1616
1617 chain_req = _base_get_chain_buffer_tracker(ioc, smid);
1618 if (!chain_req)
1619 return -1;
1620 chain = chain_req->chain_buffer;
1621 chain_dma = chain_req->chain_buffer_dma;
1622 } while (1);
1623
1624
1625 fill_in_last_segment:
1626
1627 /* fill the last segment */
62f5c74c 1628 while (sges_left > 0) {
f92363d1
SR		 1629 if (sges_left == 1)
1630 _base_add_sg_single_ieee(sg_local,
1631 simple_sgl_flags_last, 0, sg_dma_len(sg_scmd),
1632 sg_dma_address(sg_scmd));
1633 else
1634 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
1635 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1636 sg_scmd = sg_next(sg_scmd);
1637 sg_local += ioc->sge_size_ieee;
1638 sges_left--;
1639 }
1640
1641 return 0;
1642}
1643
1644/**
1645 * _base_build_sg_ieee - build generic sg for IEEE format
1646 * @ioc: per adapter object
1647 * @psge: virtual address for SGE
1648 * @data_out_dma: physical address for WRITES
1649 * @data_out_sz: data xfer size for WRITES
1650 * @data_in_dma: physical address for READS
1651 * @data_in_sz: data xfer size for READS
1652 *
1653 * Return nothing.
1654 */
1655static void
1656_base_build_sg_ieee(struct MPT3SAS_ADAPTER *ioc, void *psge,
1657 dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
1658 size_t data_in_sz)
1659{
1660 u8 sgl_flags;
1661
1662 if (!data_out_sz && !data_in_sz) {
1663 _base_build_zero_len_sge_ieee(ioc, psge);
1664 return;
1665 }
1666
1667 if (data_out_sz && data_in_sz) {
1668 /* WRITE sgel first */
1669 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1670 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1671 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz,
1672 data_out_dma);
1673
1674 /* incr sgel */
1675 psge += ioc->sge_size_ieee;
1676
1677 /* READ sgel last */
1678 sgl_flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
1679 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz,
1680 data_in_dma);
1681 } else if (data_out_sz) /* WRITE */ {
1682 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1683 MPI25_IEEE_SGE_FLAGS_END_OF_LIST |
1684 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1685 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz,
1686 data_out_dma);
1687 } else if (data_in_sz) /* READ */ {
1688 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1689 MPI25_IEEE_SGE_FLAGS_END_OF_LIST |
1690 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1691 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz,
1692 data_in_dma);
1693 }
1694}
1695
1696#define convert_to_kb(x) ((x) << (PAGE_SHIFT - 10))
1697
1698/**
1699 * _base_config_dma_addressing - set dma addressing
1700 * @ioc: per adapter object
1701 * @pdev: PCI device struct
1702 *
1703 * Returns 0 for success, non-zero for failure.
1704 */
1705static int
1706_base_config_dma_addressing(struct MPT3SAS_ADAPTER *ioc, struct pci_dev *pdev)
1707{
1708 struct sysinfo s;
9b05c91a
SR		 1709 u64 consistent_dma_mask;
1710
1711 if (ioc->dma_mask)
1712 consistent_dma_mask = DMA_BIT_MASK(64);
1713 else
1714 consistent_dma_mask = DMA_BIT_MASK(32);
f92363d1
SR		 1715
1716 if (sizeof(dma_addr_t) > 4) {
1717 const uint64_t required_mask =
1718 dma_get_required_mask(&pdev->dev);
1719 if ((required_mask > DMA_BIT_MASK(32)) &&
1720 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
9b05c91a 1721 !pci_set_consistent_dma_mask(pdev, consistent_dma_mask)) {
f92363d1
SR		 1722 ioc->base_add_sg_single = &_base_add_sg_single_64;
1723 ioc->sge_size = sizeof(Mpi2SGESimple64_t);
9b05c91a 1724 ioc->dma_mask = 64;
f92363d1
SR		 1725 goto out;
1726 }
1727 }
1728
1729 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))
1730 && !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
1731 ioc->base_add_sg_single = &_base_add_sg_single_32;
1732 ioc->sge_size = sizeof(Mpi2SGESimple32_t);
9b05c91a 1733 ioc->dma_mask = 32;
f92363d1
SR		 1734 } else
1735 return -ENODEV;
1736
1737 out:
1738 si_meminfo(&s);
1739 pr_info(MPT3SAS_FMT
9b05c91a
SR		 1740 "%d BIT PCI BUS DMA ADDRESSING SUPPORTED, total mem (%ld kB)\n",
1741 ioc->name, ioc->dma_mask, convert_to_kb(s.totalram));
1742
1743 return 0;
1744}
f92363d1 1745
9b05c91a
SR		 1746static int
1747_base_change_consistent_dma_mask(struct MPT3SAS_ADAPTER *ioc,
1748 struct pci_dev *pdev)
1749{
1750 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
1751 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
1752 return -ENODEV;
1753 }
f92363d1
SR		 1754 return 0;
1755}
1756
1757/**
1758 * _base_check_enable_msix - checks MSIX capabable.
1759 * @ioc: per adapter object
1760 *
1761 * Check to see if card is capable of MSIX, and set number
1762 * of available msix vectors
1763 */
1764static int
1765_base_check_enable_msix(struct MPT3SAS_ADAPTER *ioc)
1766{
1767 int base;
1768 u16 message_control;
1769
42081173
SR		 1770 /* Check whether controller SAS2008 B0 controller,
1771 * if it is SAS2008 B0 controller use IO-APIC instead of MSIX
1772 */
1773 if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 &&
1774 ioc->pdev->revision == SAS2_PCI_DEVICE_B0_REVISION) {
1775 return -EINVAL;
1776 }
1777
f92363d1
SR		 1778 base = pci_find_capability(ioc->pdev, PCI_CAP_ID_MSIX);
1779 if (!base) {
1780 dfailprintk(ioc, pr_info(MPT3SAS_FMT "msix not supported\n",
1781 ioc->name));
1782 return -EINVAL;
1783 }
1784
1785 /* get msix vector count */
42081173
SR		 1786 /* NUMA_IO not supported for older controllers */
1787 if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2004 ||
1788 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 ||
1789 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_1 ||
1790 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_2 ||
1791 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_3 ||
1792 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_1 ||
1793 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_2)
1794 ioc->msix_vector_count = 1;
1795 else {
1796 pci_read_config_word(ioc->pdev, base + 2, &message_control);
1797 ioc->msix_vector_count = (message_control & 0x3FF) + 1;
1798 }
f92363d1
SR		 1799 dinitprintk(ioc, pr_info(MPT3SAS_FMT
1800 "msix is supported, vector_count(%d)\n",
1801 ioc->name, ioc->msix_vector_count));
1802 return 0;
1803}
1804
1805/**
1806 * _base_free_irq - free irq
1807 * @ioc: per adapter object
1808 *
1809 * Freeing respective reply_queue from the list.
1810 */
1811static void
1812_base_free_irq(struct MPT3SAS_ADAPTER *ioc)
1813{
1814 struct adapter_reply_queue *reply_q, *next;
1815
1816 if (list_empty(&ioc->reply_queue_list))
1817 return;
1818
1819 list_for_each_entry_safe(reply_q, next, &ioc->reply_queue_list, list) {
1820 list_del(&reply_q->list);
64038301
SPS		 1821 if (smp_affinity_enable) {
1822 irq_set_affinity_hint(reply_q->vector, NULL);
1823 free_cpumask_var(reply_q->affinity_hint);
1824 }
f92363d1
SR		 1825 free_irq(reply_q->vector, reply_q);
1826 kfree(reply_q);
1827 }
1828}
1829
1830/**
1831 * _base_request_irq - request irq
1832 * @ioc: per adapter object
1833 * @index: msix index into vector table
1834 * @vector: irq vector
1835 *
1836 * Inserting respective reply_queue into the list.
1837 */
1838static int
1839_base_request_irq(struct MPT3SAS_ADAPTER *ioc, u8 index, u32 vector)
1840{
1841 struct adapter_reply_queue *reply_q;
1842 int r;
1843
1844 reply_q = kzalloc(sizeof(struct adapter_reply_queue), GFP_KERNEL);
1845 if (!reply_q) {
1846 pr_err(MPT3SAS_FMT "unable to allocate memory %d!\n",
1847 ioc->name, (int)sizeof(struct adapter_reply_queue));
1848 return -ENOMEM;
1849 }
1850 reply_q->ioc = ioc;
1851 reply_q->msix_index = index;
1852 reply_q->vector = vector;
14b3114d 1853
64038301
SPS		 1854 if (smp_affinity_enable) {
1855 if (!zalloc_cpumask_var(&reply_q->affinity_hint, GFP_KERNEL)) {
1856 kfree(reply_q);
1857 return -ENOMEM;
1858 }
64038301 1859 }
14b3114d 1860
f92363d1
SR		 1861 atomic_set(&reply_q->busy, 0);
1862 if (ioc->msix_enable)
1863 snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d-msix%d",
c84b06a4 1864 ioc->driver_name, ioc->id, index);
f92363d1
SR		 1865 else
1866 snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d",
c84b06a4 1867 ioc->driver_name, ioc->id);
f92363d1
SR		 1868 r = request_irq(vector, _base_interrupt, IRQF_SHARED, reply_q->name,
1869 reply_q);
1870 if (r) {
1871 pr_err(MPT3SAS_FMT "unable to allocate interrupt %d!\n",
1872 reply_q->name, vector);
64038301 1873 free_cpumask_var(reply_q->affinity_hint);
da3cec25 1874 kfree(reply_q);
f92363d1
SR		 1875 return -EBUSY;
1876 }
1877
1878 INIT_LIST_HEAD(&reply_q->list);
1879 list_add_tail(&reply_q->list, &ioc->reply_queue_list);
1880 return 0;
1881}
1882
1883/**
1884 * _base_assign_reply_queues - assigning msix index for each cpu
1885 * @ioc: per adapter object
1886 *
1887 * The enduser would need to set the affinity via /proc/irq/#/smp_affinity
1888 *
1889 * It would nice if we could call irq_set_affinity, however it is not
1890 * an exported symbol
1891 */
1892static void
1893_base_assign_reply_queues(struct MPT3SAS_ADAPTER *ioc)
1894{
91b265bf 1895 unsigned int cpu, nr_cpus, nr_msix, index = 0;
14b3114d 1896 struct adapter_reply_queue *reply_q;
f92363d1
SR		 1897
1898 if (!_base_is_controller_msix_enabled(ioc))
1899 return;
1900
1901 memset(ioc->cpu_msix_table, 0, ioc->cpu_msix_table_sz);
1902
91b265bf
MP		 1903 nr_cpus = num_online_cpus();
1904 nr_msix = ioc->reply_queue_count = min(ioc->reply_queue_count,
1905 ioc->facts.MaxMSIxVectors);
1906 if (!nr_msix)
1907 return;
f92363d1 1908
91b265bf
MP		 1909 cpu = cpumask_first(cpu_online_mask);
1910
14b3114d
SR		 1911 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
1912
91b265bf
MP		 1913 unsigned int i, group = nr_cpus / nr_msix;
1914
14b3114d
SR		 1915 if (cpu >= nr_cpus)
1916 break;
1917
91b265bf
MP		 1918 if (index < nr_cpus % nr_msix)
1919 group++;
1920
1921 for (i = 0 ; i < group ; i++) {
1922 ioc->cpu_msix_table[cpu] = index;
64038301
SPS		 1923 if (smp_affinity_enable)
1924 cpumask_or(reply_q->affinity_hint,
14b3114d 1925 reply_q->affinity_hint, get_cpu_mask(cpu));
91b265bf 1926 cpu = cpumask_next(cpu, cpu_online_mask);
f92363d1 1927 }
64038301
SPS		 1928 if (smp_affinity_enable)
1929 if (irq_set_affinity_hint(reply_q->vector,
14b3114d 1930 reply_q->affinity_hint))
64038301
SPS		 1931 dinitprintk(ioc, pr_info(MPT3SAS_FMT
1932 "Err setting affinity hint to irq vector %d\n",
1933 ioc->name, reply_q->vector));
91b265bf 1934 index++;
14b3114d 1935 }
f92363d1
SR		 1936}
1937
1938/**
1939 * _base_disable_msix - disables msix
1940 * @ioc: per adapter object
1941 *
1942 */
1943static void
1944_base_disable_msix(struct MPT3SAS_ADAPTER *ioc)
1945{
1946 if (!ioc->msix_enable)
1947 return;
1948 pci_disable_msix(ioc->pdev);
1949 ioc->msix_enable = 0;
1950}
1951
1952/**
1953 * _base_enable_msix - enables msix, failback to io_apic
1954 * @ioc: per adapter object
1955 *
1956 */
1957static int
1958_base_enable_msix(struct MPT3SAS_ADAPTER *ioc)
1959{
1960 struct msix_entry *entries, *a;
1961 int r;
bb350661 1962 int i, local_max_msix_vectors;
f92363d1
SR		 1963 u8 try_msix = 0;
1964
f92363d1
SR		 1965 if (msix_disable == -1 || msix_disable == 0)
1966 try_msix = 1;
1967
1968 if (!try_msix)
1969 goto try_ioapic;
1970
1971 if (_base_check_enable_msix(ioc) != 0)
1972 goto try_ioapic;
1973
1974 ioc->reply_queue_count = min_t(int, ioc->cpu_count,
1975 ioc->msix_vector_count);
1976
9c500060
SR		 1977 printk(MPT3SAS_FMT "MSI-X vectors supported: %d, no of cores"
1978 ": %d, max_msix_vectors: %d\n", ioc->name, ioc->msix_vector_count,
1979 ioc->cpu_count, max_msix_vectors);
1980
9b05c91a 1981 if (!ioc->rdpq_array_enable && max_msix_vectors == -1)
bb350661
SPS		 1982 local_max_msix_vectors = 8;
1983 else
1984 local_max_msix_vectors = max_msix_vectors;
9b05c91a 1985
bb350661
SPS		 1986 if (local_max_msix_vectors > 0) {
1987 ioc->reply_queue_count = min_t(int, local_max_msix_vectors,
9c500060
SR		 1988 ioc->reply_queue_count);
1989 ioc->msix_vector_count = ioc->reply_queue_count;
bb350661 1990 } else if (local_max_msix_vectors == 0)
9b05c91a 1991 goto try_ioapic;
9c500060 1992
64038301
SPS		 1993 if (ioc->msix_vector_count < ioc->cpu_count)
1994 smp_affinity_enable = 0;
1995
f92363d1
SR		 1996 entries = kcalloc(ioc->reply_queue_count, sizeof(struct msix_entry),
1997 GFP_KERNEL);
1998 if (!entries) {
1999 dfailprintk(ioc, pr_info(MPT3SAS_FMT
2000 "kcalloc failed @ at %s:%d/%s() !!!\n",
2001 ioc->name, __FILE__, __LINE__, __func__));
2002 goto try_ioapic;
2003 }
2004
2005 for (i = 0, a = entries; i < ioc->reply_queue_count; i++, a++)
2006 a->entry = i;
2007
6bfa6907 2008 r = pci_enable_msix_exact(ioc->pdev, entries, ioc->reply_queue_count);
f92363d1
SR		 2009 if (r) {
2010 dfailprintk(ioc, pr_info(MPT3SAS_FMT
6bfa6907 2011 "pci_enable_msix_exact failed (r=%d) !!!\n",
f92363d1
SR		 2012 ioc->name, r));
2013 kfree(entries);
2014 goto try_ioapic;
2015 }
2016
2017 ioc->msix_enable = 1;
2018 for (i = 0, a = entries; i < ioc->reply_queue_count; i++, a++) {
2019 r = _base_request_irq(ioc, i, a->vector);
2020 if (r) {
2021 _base_free_irq(ioc);
2022 _base_disable_msix(ioc);
2023 kfree(entries);
2024 goto try_ioapic;
2025 }
2026 }
2027
2028 kfree(entries);
2029 return 0;
2030
2031/* failback to io_apic interrupt routing */
2032 try_ioapic:
2033
9b05c91a 2034 ioc->reply_queue_count = 1;
f92363d1
SR		 2035 r = _base_request_irq(ioc, 0, ioc->pdev->irq);
2036
2037 return r;
2038}
2039
580d4e31
SR		 2040/**
2041 * mpt3sas_base_unmap_resources - free controller resources
2042 * @ioc: per adapter object
2043 */
8bbb1cf6 2044static void
580d4e31
SR		 2045mpt3sas_base_unmap_resources(struct MPT3SAS_ADAPTER *ioc)
2046{
2047 struct pci_dev *pdev = ioc->pdev;
2048
2049 dexitprintk(ioc, printk(MPT3SAS_FMT "%s\n",
2050 ioc->name, __func__));
2051
2052 _base_free_irq(ioc);
2053 _base_disable_msix(ioc);
2054
0bb337c9 2055 if (ioc->combined_reply_queue) {
580d4e31 2056 kfree(ioc->replyPostRegisterIndex);
5f985d88
TH		 2057 ioc->replyPostRegisterIndex = NULL;
2058 }
580d4e31
SR		 2059
2060 if (ioc->chip_phys) {
2061 iounmap(ioc->chip);
2062 ioc->chip_phys = 0;
2063 }
2064
2065 if (pci_is_enabled(pdev)) {
2066 pci_release_selected_regions(ioc->pdev, ioc->bars);
2067 pci_disable_pcie_error_reporting(pdev);
2068 pci_disable_device(pdev);
2069 }
2070}
2071
f92363d1
SR		 2072/**
2073 * mpt3sas_base_map_resources - map in controller resources (io/irq/memap)
2074 * @ioc: per adapter object
2075 *
2076 * Returns 0 for success, non-zero for failure.
2077 */
2078int
2079mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc)
2080{
2081 struct pci_dev *pdev = ioc->pdev;
2082 u32 memap_sz;
2083 u32 pio_sz;
2084 int i, r = 0;
2085 u64 pio_chip = 0;
2086 u64 chip_phys = 0;
2087 struct adapter_reply_queue *reply_q;
2088
2089 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n",
2090 ioc->name, __func__));
2091
2092 ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
2093 if (pci_enable_device_mem(pdev)) {
2094 pr_warn(MPT3SAS_FMT "pci_enable_device_mem: failed\n",
2095 ioc->name);
cf9bd21a 2096 ioc->bars = 0;
f92363d1
SR		 2097 return -ENODEV;
2098 }
2099
2100
2101 if (pci_request_selected_regions(pdev, ioc->bars,
c84b06a4 2102 ioc->driver_name)) {
f92363d1
SR		 2103 pr_warn(MPT3SAS_FMT "pci_request_selected_regions: failed\n",
2104 ioc->name);
cf9bd21a 2105 ioc->bars = 0;
f92363d1
SR		 2106 r = -ENODEV;
2107 goto out_fail;
2108 }
2109
2110/* AER (Advanced Error Reporting) hooks */
2111 pci_enable_pcie_error_reporting(pdev);
2112
2113 pci_set_master(pdev);
2114
2115
2116 if (_base_config_dma_addressing(ioc, pdev) != 0) {
2117 pr_warn(MPT3SAS_FMT "no suitable DMA mask for %s\n",
2118 ioc->name, pci_name(pdev));
2119 r = -ENODEV;
2120 goto out_fail;
2121 }
2122
5aeeb78a
SR		 2123 for (i = 0, memap_sz = 0, pio_sz = 0; (i < DEVICE_COUNT_RESOURCE) &&
2124 (!memap_sz || !pio_sz); i++) {
f92363d1
SR		 2125 if (pci_resource_flags(pdev, i) & IORESOURCE_IO) {
2126 if (pio_sz)
2127 continue;
2128 pio_chip = (u64)pci_resource_start(pdev, i);
2129 pio_sz = pci_resource_len(pdev, i);
2130 } else if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
2131 if (memap_sz)
2132 continue;
2133 ioc->chip_phys = pci_resource_start(pdev, i);
2134 chip_phys = (u64)ioc->chip_phys;
2135 memap_sz = pci_resource_len(pdev, i);
2136 ioc->chip = ioremap(ioc->chip_phys, memap_sz);
f92363d1
SR		 2137 }
2138 }
2139
5aeeb78a
SR		 2140 if (ioc->chip == NULL) {
2141 pr_err(MPT3SAS_FMT "unable to map adapter memory! "
2142 " or resource not found\n", ioc->name);
2143 r = -EINVAL;
2144 goto out_fail;
2145 }
2146
f92363d1 2147 _base_mask_interrupts(ioc);
9b05c91a 2148
98c56ad3 2149 r = _base_get_ioc_facts(ioc);
9b05c91a
SR		 2150 if (r)
2151 goto out_fail;
2152
2153 if (!ioc->rdpq_array_enable_assigned) {
2154 ioc->rdpq_array_enable = ioc->rdpq_array_capable;
2155 ioc->rdpq_array_enable_assigned = 1;
2156 }
2157
f92363d1
SR		 2158 r = _base_enable_msix(ioc);
2159 if (r)
2160 goto out_fail;
2161
fb77bb53
SR		 2162 /* Use the Combined reply queue feature only for SAS3 C0 & higher
2163 * revision HBAs and also only when reply queue count is greater than 8
2164 */
0bb337c9 2165 if (ioc->combined_reply_queue && ioc->reply_queue_count > 8) {
fb77bb53
SR		 2166 /* Determine the Supplemental Reply Post Host Index Registers
2167 * Addresse. Supplemental Reply Post Host Index Registers
2168 * starts at offset MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET and
2169 * each register is at offset bytes of
2170 * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET from previous one.
2171 */
2172 ioc->replyPostRegisterIndex = kcalloc(
0bb337c9 2173 ioc->combined_reply_index_count,
fb77bb53
SR		 2174 sizeof(resource_size_t *), GFP_KERNEL);
2175 if (!ioc->replyPostRegisterIndex) {
2176 dfailprintk(ioc, printk(MPT3SAS_FMT
2177 "allocation for reply Post Register Index failed!!!\n",
2178 ioc->name));
2179 r = -ENOMEM;
2180 goto out_fail;
2181 }
2182
0bb337c9 2183 for (i = 0; i < ioc->combined_reply_index_count; i++) {
fb77bb53
SR		 2184 ioc->replyPostRegisterIndex[i] = (resource_size_t *)
2185 ((u8 *)&ioc->chip->Doorbell +
2186 MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET +
2187 (i * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET));
2188 }
2189 } else
0bb337c9 2190 ioc->combined_reply_queue = 0;
fb77bb53 2191
ce7c6c9e
GE		 2192 if (ioc->is_warpdrive) {
2193 ioc->reply_post_host_index[0] = (resource_size_t __iomem *)
2194 &ioc->chip->ReplyPostHostIndex;
2195
2196 for (i = 1; i < ioc->cpu_msix_table_sz; i++)
2197 ioc->reply_post_host_index[i] =
2198 (resource_size_t __iomem *)
2199 ((u8 __iomem *)&ioc->chip->Doorbell + (0x4000 + ((i - 1)
2200 * 4)));
2201 }
2202
f92363d1
SR		 2203 list_for_each_entry(reply_q, &ioc->reply_queue_list, list)
2204 pr_info(MPT3SAS_FMT "%s: IRQ %d\n",
2205 reply_q->name, ((ioc->msix_enable) ? "PCI-MSI-X enabled" :
2206 "IO-APIC enabled"), reply_q->vector);
2207
2208 pr_info(MPT3SAS_FMT "iomem(0x%016llx), mapped(0x%p), size(%d)\n",
2209 ioc->name, (unsigned long long)chip_phys, ioc->chip, memap_sz);
2210 pr_info(MPT3SAS_FMT "ioport(0x%016llx), size(%d)\n",
2211 ioc->name, (unsigned long long)pio_chip, pio_sz);
2212
2213 /* Save PCI configuration state for recovery from PCI AER/EEH errors */
2214 pci_save_state(pdev);
2215 return 0;
2216
2217 out_fail:
580d4e31 2218 mpt3sas_base_unmap_resources(ioc);
f92363d1
SR		 2219 return r;
2220}
2221
2222/**
2223 * mpt3sas_base_get_msg_frame - obtain request mf pointer
2224 * @ioc: per adapter object
2225 * @smid: system request message index(smid zero is invalid)
2226 *
2227 * Returns virt pointer to message frame.
2228 */
2229void *
2230mpt3sas_base_get_msg_frame(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2231{
2232 return (void *)(ioc->request + (smid * ioc->request_sz));
2233}
2234
2235/**
2236 * mpt3sas_base_get_sense_buffer - obtain a sense buffer virt addr
2237 * @ioc: per adapter object
2238 * @smid: system request message index
2239 *
2240 * Returns virt pointer to sense buffer.
2241 */
2242void *
2243mpt3sas_base_get_sense_buffer(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2244{
2245 return (void *)(ioc->sense + ((smid - 1) * SCSI_SENSE_BUFFERSIZE));
2246}
2247
2248/**
2249 * mpt3sas_base_get_sense_buffer_dma - obtain a sense buffer dma addr
2250 * @ioc: per adapter object
2251 * @smid: system request message index
2252 *
2253 * Returns phys pointer to the low 32bit address of the sense buffer.
2254 */
2255__le32
2256mpt3sas_base_get_sense_buffer_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2257{
2258 return cpu_to_le32(ioc->sense_dma + ((smid - 1) *
2259 SCSI_SENSE_BUFFERSIZE));
2260}
2261
2262/**
2263 * mpt3sas_base_get_reply_virt_addr - obtain reply frames virt address
2264 * @ioc: per adapter object
2265 * @phys_addr: lower 32 physical addr of the reply
2266 *
2267 * Converts 32bit lower physical addr into a virt address.
2268 */
2269void *
2270mpt3sas_base_get_reply_virt_addr(struct MPT3SAS_ADAPTER *ioc, u32 phys_addr)
2271{
2272 if (!phys_addr)
2273 return NULL;
2274 return ioc->reply + (phys_addr - (u32)ioc->reply_dma);
2275}
2276
03d1fb3a
SS		 2277static inline u8
2278_base_get_msix_index(struct MPT3SAS_ADAPTER *ioc)
2279{
2280 return ioc->cpu_msix_table[raw_smp_processor_id()];
2281}
2282
f92363d1
SR		 2283/**
2284 * mpt3sas_base_get_smid - obtain a free smid from internal queue
2285 * @ioc: per adapter object
2286 * @cb_idx: callback index
2287 *
2288 * Returns smid (zero is invalid)
2289 */
2290u16
2291mpt3sas_base_get_smid(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx)
2292{
2293 unsigned long flags;
2294 struct request_tracker *request;
2295 u16 smid;
2296
2297 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2298 if (list_empty(&ioc->internal_free_list)) {
2299 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2300 pr_err(MPT3SAS_FMT "%s: smid not available\n",
2301 ioc->name, __func__);
2302 return 0;
2303 }
2304
2305 request = list_entry(ioc->internal_free_list.next,
2306 struct request_tracker, tracker_list);
2307 request->cb_idx = cb_idx;
2308 smid = request->smid;
2309 list_del(&request->tracker_list);
2310 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2311 return smid;
2312}
2313
2314/**
2315 * mpt3sas_base_get_smid_scsiio - obtain a free smid from scsiio queue
2316 * @ioc: per adapter object
2317 * @cb_idx: callback index
2318 * @scmd: pointer to scsi command object
2319 *
2320 * Returns smid (zero is invalid)
2321 */
2322u16
2323mpt3sas_base_get_smid_scsiio(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx,
2324 struct scsi_cmnd *scmd)
2325{
2326 unsigned long flags;
2327 struct scsiio_tracker *request;
2328 u16 smid;
2329
2330 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2331 if (list_empty(&ioc->free_list)) {
2332 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2333 pr_err(MPT3SAS_FMT "%s: smid not available\n",
2334 ioc->name, __func__);
2335 return 0;
2336 }
2337
2338 request = list_entry(ioc->free_list.next,
2339 struct scsiio_tracker, tracker_list);
2340 request->scmd = scmd;
2341 request->cb_idx = cb_idx;
2342 smid = request->smid;
03d1fb3a 2343 request->msix_io = _base_get_msix_index(ioc);
f92363d1
SR		 2344 list_del(&request->tracker_list);
2345 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2346 return smid;
2347}
2348
2349/**
2350 * mpt3sas_base_get_smid_hpr - obtain a free smid from hi-priority queue
2351 * @ioc: per adapter object
2352 * @cb_idx: callback index
2353 *
2354 * Returns smid (zero is invalid)
2355 */
2356u16
2357mpt3sas_base_get_smid_hpr(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx)
2358{
2359 unsigned long flags;
2360 struct request_tracker *request;
2361 u16 smid;
2362
2363 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2364 if (list_empty(&ioc->hpr_free_list)) {
2365 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2366 return 0;
2367 }
2368
2369 request = list_entry(ioc->hpr_free_list.next,
2370 struct request_tracker, tracker_list);
2371 request->cb_idx = cb_idx;
2372 smid = request->smid;
2373 list_del(&request->tracker_list);
2374 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2375 return smid;
2376}
2377
2378/**
2379 * mpt3sas_base_free_smid - put smid back on free_list
2380 * @ioc: per adapter object
2381 * @smid: system request message index
2382 *
2383 * Return nothing.
2384 */
2385void
2386mpt3sas_base_free_smid(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2387{
2388 unsigned long flags;
2389 int i;
2390 struct chain_tracker *chain_req, *next;
2391
2392 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2393 if (smid < ioc->hi_priority_smid) {
2394 /* scsiio queue */
2395 i = smid - 1;
2396 if (!list_empty(&ioc->scsi_lookup[i].chain_list)) {
2397 list_for_each_entry_safe(chain_req, next,
2398 &ioc->scsi_lookup[i].chain_list, tracker_list) {
2399 list_del_init(&chain_req->tracker_list);
2400 list_add(&chain_req->tracker_list,
2401 &ioc->free_chain_list);
2402 }
2403 }
2404 ioc->scsi_lookup[i].cb_idx = 0xFF;
2405 ioc->scsi_lookup[i].scmd = NULL;
7786ab6a 2406 ioc->scsi_lookup[i].direct_io = 0;
f92363d1
SR		 2407 list_add(&ioc->scsi_lookup[i].tracker_list, &ioc->free_list);
2408 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2409
2410 /*
2411 * See _wait_for_commands_to_complete() call with regards
2412 * to this code.
2413 */
2414 if (ioc->shost_recovery && ioc->pending_io_count) {
2415 if (ioc->pending_io_count == 1)
2416 wake_up(&ioc->reset_wq);
2417 ioc->pending_io_count--;
2418 }
2419 return;
2420 } else if (smid < ioc->internal_smid) {
2421 /* hi-priority */
2422 i = smid - ioc->hi_priority_smid;
2423 ioc->hpr_lookup[i].cb_idx = 0xFF;
2424 list_add(&ioc->hpr_lookup[i].tracker_list, &ioc->hpr_free_list);
2425 } else if (smid <= ioc->hba_queue_depth) {
2426 /* internal queue */
2427 i = smid - ioc->internal_smid;
2428 ioc->internal_lookup[i].cb_idx = 0xFF;
2429 list_add(&ioc->internal_lookup[i].tracker_list,
2430 &ioc->internal_free_list);
2431 }
2432 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2433}
2434
2435/**
2436 * _base_writeq - 64 bit write to MMIO
2437 * @ioc: per adapter object
2438 * @b: data payload
2439 * @addr: address in MMIO space
2440 * @writeq_lock: spin lock
2441 *
2442 * Glue for handling an atomic 64 bit word to MMIO. This special handling takes
2443 * care of 32 bit environment where its not quarenteed to send the entire word
2444 * in one transfer.
2445 */
2446#if defined(writeq) && defined(CONFIG_64BIT)
2447static inline void
2448_base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock)
2449{
2450 writeq(cpu_to_le64(b), addr);
2451}
2452#else
2453static inline void
2454_base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock)
2455{
2456 unsigned long flags;
2457 __u64 data_out = cpu_to_le64(b);
2458
2459 spin_lock_irqsave(writeq_lock, flags);
2460 writel((u32)(data_out), addr);
2461 writel((u32)(data_out >> 32), (addr + 4));
2462 spin_unlock_irqrestore(writeq_lock, flags);
2463}
2464#endif
2465
f92363d1
SR		 2466/**
2467 * mpt3sas_base_put_smid_scsi_io - send SCSI_IO request to firmware
2468 * @ioc: per adapter object
2469 * @smid: system request message index
2470 * @handle: device handle
2471 *
2472 * Return nothing.
2473 */
2474void
2475mpt3sas_base_put_smid_scsi_io(struct MPT3SAS_ADAPTER *ioc, u16 smid, u16 handle)
2476{
2477 Mpi2RequestDescriptorUnion_t descriptor;
2478 u64 *request = (u64 *)&descriptor;
2479
2480
2481 descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
2482 descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc);
2483 descriptor.SCSIIO.SMID = cpu_to_le16(smid);
2484 descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
2485 descriptor.SCSIIO.LMID = 0;
2486 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2487 &ioc->scsi_lookup_lock);
2488}
2489
2490/**
2491 * mpt3sas_base_put_smid_fast_path - send fast path request to firmware
2492 * @ioc: per adapter object
2493 * @smid: system request message index
2494 * @handle: device handle
2495 *
2496 * Return nothing.
2497 */
2498void
2499mpt3sas_base_put_smid_fast_path(struct MPT3SAS_ADAPTER *ioc, u16 smid,
2500 u16 handle)
2501{
2502 Mpi2RequestDescriptorUnion_t descriptor;
2503 u64 *request = (u64 *)&descriptor;
2504
2505 descriptor.SCSIIO.RequestFlags =
2506 MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO;
2507 descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc);
2508 descriptor.SCSIIO.SMID = cpu_to_le16(smid);
2509 descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
2510 descriptor.SCSIIO.LMID = 0;
2511 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2512 &ioc->scsi_lookup_lock);
2513}
2514
2515/**
2516 * mpt3sas_base_put_smid_hi_priority - send Task Managment request to firmware
2517 * @ioc: per adapter object
2518 * @smid: system request message index
03d1fb3a 2519 * @msix_task: msix_task will be same as msix of IO incase of task abort else 0.
f92363d1
SR		 2520 * Return nothing.
2521 */
2522void
03d1fb3a
SS		 2523mpt3sas_base_put_smid_hi_priority(struct MPT3SAS_ADAPTER *ioc, u16 smid,
2524 u16 msix_task)
f92363d1
SR		 2525{
2526 Mpi2RequestDescriptorUnion_t descriptor;
2527 u64 *request = (u64 *)&descriptor;
2528
2529 descriptor.HighPriority.RequestFlags =
2530 MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY;
03d1fb3a 2531 descriptor.HighPriority.MSIxIndex = msix_task;
f92363d1
SR		 2532 descriptor.HighPriority.SMID = cpu_to_le16(smid);
2533 descriptor.HighPriority.LMID = 0;
2534 descriptor.HighPriority.Reserved1 = 0;
2535 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2536 &ioc->scsi_lookup_lock);
2537}
2538
2539/**
2540 * mpt3sas_base_put_smid_default - Default, primarily used for config pages
2541 * @ioc: per adapter object
2542 * @smid: system request message index
2543 *
2544 * Return nothing.
2545 */
2546void
2547mpt3sas_base_put_smid_default(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2548{
2549 Mpi2RequestDescriptorUnion_t descriptor;
2550 u64 *request = (u64 *)&descriptor;
2551
2552 descriptor.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
2553 descriptor.Default.MSIxIndex = _base_get_msix_index(ioc);
2554 descriptor.Default.SMID = cpu_to_le16(smid);
2555 descriptor.Default.LMID = 0;
2556 descriptor.Default.DescriptorTypeDependent = 0;
2557 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2558 &ioc->scsi_lookup_lock);
2559}
2560
1117b31a 2561/**
989e43c7 2562 * _base_display_OEMs_branding - Display branding string
1117b31a
SR		 2563 * @ioc: per adapter object
2564 *
2565 * Return nothing.
2566 */
2567static void
989e43c7 2568_base_display_OEMs_branding(struct MPT3SAS_ADAPTER *ioc)
1117b31a
SR		 2569{
2570 if (ioc->pdev->subsystem_vendor != PCI_VENDOR_ID_INTEL)
2571 return;
2572
989e43c7
SR		 2573 switch (ioc->pdev->subsystem_vendor) {
2574 case PCI_VENDOR_ID_INTEL:
2575 switch (ioc->pdev->device) {
2576 case MPI2_MFGPAGE_DEVID_SAS2008:
2577 switch (ioc->pdev->subsystem_device) {
2578 case MPT2SAS_INTEL_RMS2LL080_SSDID:
2579 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2580 MPT2SAS_INTEL_RMS2LL080_BRANDING);
2581 break;
2582 case MPT2SAS_INTEL_RMS2LL040_SSDID:
2583 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2584 MPT2SAS_INTEL_RMS2LL040_BRANDING);
2585 break;
2586 case MPT2SAS_INTEL_SSD910_SSDID:
2587 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2588 MPT2SAS_INTEL_SSD910_BRANDING);
2589 break;
2590 default:
2591 pr_info(MPT3SAS_FMT
2592 "Intel(R) Controller: Subsystem ID: 0x%X\n",
2593 ioc->name, ioc->pdev->subsystem_device);
2594 break;
2595 }
2596 case MPI2_MFGPAGE_DEVID_SAS2308_2:
2597 switch (ioc->pdev->subsystem_device) {
2598 case MPT2SAS_INTEL_RS25GB008_SSDID:
2599 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2600 MPT2SAS_INTEL_RS25GB008_BRANDING);
2601 break;
2602 case MPT2SAS_INTEL_RMS25JB080_SSDID:
2603 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2604 MPT2SAS_INTEL_RMS25JB080_BRANDING);
2605 break;
2606 case MPT2SAS_INTEL_RMS25JB040_SSDID:
2607 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2608 MPT2SAS_INTEL_RMS25JB040_BRANDING);
2609 break;
2610 case MPT2SAS_INTEL_RMS25KB080_SSDID:
2611 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2612 MPT2SAS_INTEL_RMS25KB080_BRANDING);
2613 break;
2614 case MPT2SAS_INTEL_RMS25KB040_SSDID:
2615 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2616 MPT2SAS_INTEL_RMS25KB040_BRANDING);
2617 break;
2618 case MPT2SAS_INTEL_RMS25LB040_SSDID:
2619 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2620 MPT2SAS_INTEL_RMS25LB040_BRANDING);
2621 break;
2622 case MPT2SAS_INTEL_RMS25LB080_SSDID:
2623 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2624 MPT2SAS_INTEL_RMS25LB080_BRANDING);
2625 break;
2626 default:
2627 pr_info(MPT3SAS_FMT
2628 "Intel(R) Controller: Subsystem ID: 0x%X\n",
2629 ioc->name, ioc->pdev->subsystem_device);
2630 break;
2631 }
2632 case MPI25_MFGPAGE_DEVID_SAS3008:
2633 switch (ioc->pdev->subsystem_device) {
2634 case MPT3SAS_INTEL_RMS3JC080_SSDID:
2635 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2636 MPT3SAS_INTEL_RMS3JC080_BRANDING);
2637 break;
2638
2639 case MPT3SAS_INTEL_RS3GC008_SSDID:
2640 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2641 MPT3SAS_INTEL_RS3GC008_BRANDING);
2642 break;
2643 case MPT3SAS_INTEL_RS3FC044_SSDID:
2644 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2645 MPT3SAS_INTEL_RS3FC044_BRANDING);
2646 break;
2647 case MPT3SAS_INTEL_RS3UC080_SSDID:
2648 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2649 MPT3SAS_INTEL_RS3UC080_BRANDING);
2650 break;
2651 default:
2652 pr_info(MPT3SAS_FMT
2653 "Intel(R) Controller: Subsystem ID: 0x%X\n",
2654 ioc->name, ioc->pdev->subsystem_device);
2655 break;
2656 }
1117b31a
SR		 2657 break;
2658 default:
2659 pr_info(MPT3SAS_FMT
989e43c7
SR		 2660 "Intel(R) Controller: Subsystem ID: 0x%X\n",
2661 ioc->name, ioc->pdev->subsystem_device);
1117b31a
SR		 2662 break;
2663 }
2664 break;
989e43c7
SR		 2665 case PCI_VENDOR_ID_DELL:
2666 switch (ioc->pdev->device) {
2667 case MPI2_MFGPAGE_DEVID_SAS2008:
2668 switch (ioc->pdev->subsystem_device) {
2669 case MPT2SAS_DELL_6GBPS_SAS_HBA_SSDID:
2670 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2671 MPT2SAS_DELL_6GBPS_SAS_HBA_BRANDING);
2672 break;
2673 case MPT2SAS_DELL_PERC_H200_ADAPTER_SSDID:
2674 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2675 MPT2SAS_DELL_PERC_H200_ADAPTER_BRANDING);
2676 break;
2677 case MPT2SAS_DELL_PERC_H200_INTEGRATED_SSDID:
2678 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2679 MPT2SAS_DELL_PERC_H200_INTEGRATED_BRANDING);
2680 break;
2681 case MPT2SAS_DELL_PERC_H200_MODULAR_SSDID:
2682 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2683 MPT2SAS_DELL_PERC_H200_MODULAR_BRANDING);
2684 break;
2685 case MPT2SAS_DELL_PERC_H200_EMBEDDED_SSDID:
2686 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2687 MPT2SAS_DELL_PERC_H200_EMBEDDED_BRANDING);
2688 break;
2689 case MPT2SAS_DELL_PERC_H200_SSDID:
2690 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2691 MPT2SAS_DELL_PERC_H200_BRANDING);
2692 break;
2693 case MPT2SAS_DELL_6GBPS_SAS_SSDID:
2694 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2695 MPT2SAS_DELL_6GBPS_SAS_BRANDING);
2696 break;
2697 default:
2698 pr_info(MPT3SAS_FMT
2699 "Dell 6Gbps HBA: Subsystem ID: 0x%X\n",
2700 ioc->name, ioc->pdev->subsystem_device);
2701 break;
2702 }
2703 break;
2704 case MPI25_MFGPAGE_DEVID_SAS3008:
2705 switch (ioc->pdev->subsystem_device) {
2706 case MPT3SAS_DELL_12G_HBA_SSDID:
2707 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2708 MPT3SAS_DELL_12G_HBA_BRANDING);
2709 break;
2710 default:
2711 pr_info(MPT3SAS_FMT
2712 "Dell 12Gbps HBA: Subsystem ID: 0x%X\n",
2713 ioc->name, ioc->pdev->subsystem_device);
2714 break;
2715 }
fb84dfc4
SR		 2716 break;
2717 default:
2718 pr_info(MPT3SAS_FMT
989e43c7 2719 "Dell HBA: Subsystem ID: 0x%X\n", ioc->name,
fb84dfc4
SR		 2720 ioc->pdev->subsystem_device);
2721 break;
2722 }
2723 break;
989e43c7
SR		 2724 case PCI_VENDOR_ID_CISCO:
2725 switch (ioc->pdev->device) {
2726 case MPI25_MFGPAGE_DEVID_SAS3008:
2727 switch (ioc->pdev->subsystem_device) {
2728 case MPT3SAS_CISCO_12G_8E_HBA_SSDID:
2729 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2730 MPT3SAS_CISCO_12G_8E_HBA_BRANDING);
2731 break;
2732 case MPT3SAS_CISCO_12G_8I_HBA_SSDID:
2733 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2734 MPT3SAS_CISCO_12G_8I_HBA_BRANDING);
2735 break;
2736 case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID:
2737 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2738 MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING);
2739 break;
2740 default:
2741 pr_info(MPT3SAS_FMT
2742 "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n",
2743 ioc->name, ioc->pdev->subsystem_device);
2744 break;
2745 }
d8eb4a47 2746 break;
989e43c7
SR		 2747 case MPI25_MFGPAGE_DEVID_SAS3108_1:
2748 switch (ioc->pdev->subsystem_device) {
2749 case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID:
2750 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
d8eb4a47 2751 MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING);
989e43c7
SR		 2752 break;
2753 case MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_SSDID:
2754 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2755 MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_BRANDING
2756 );
2757 break;
2758 default:
2759 pr_info(MPT3SAS_FMT
2760 "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n",
2761 ioc->name, ioc->pdev->subsystem_device);
2762 break;
2763 }
38e4141e
SR		 2764 break;
2765 default:
2766 pr_info(MPT3SAS_FMT
989e43c7
SR		 2767 "Cisco SAS HBA: Subsystem ID: 0x%X\n",
2768 ioc->name, ioc->pdev->subsystem_device);
38e4141e
SR		 2769 break;
2770 }
2771 break;
989e43c7
SR		 2772 case MPT2SAS_HP_3PAR_SSVID:
2773 switch (ioc->pdev->device) {
2774 case MPI2_MFGPAGE_DEVID_SAS2004:
2775 switch (ioc->pdev->subsystem_device) {
2776 case MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_SSDID:
2777 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2778 MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_BRANDING);
2779 break;
2780 default:
2781 pr_info(MPT3SAS_FMT
2782 "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n",
2783 ioc->name, ioc->pdev->subsystem_device);
2784 break;
2785 }
2786 case MPI2_MFGPAGE_DEVID_SAS2308_2:
2787 switch (ioc->pdev->subsystem_device) {
2788 case MPT2SAS_HP_2_4_INTERNAL_SSDID:
2789 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2790 MPT2SAS_HP_2_4_INTERNAL_BRANDING);
2791 break;
2792 case MPT2SAS_HP_2_4_EXTERNAL_SSDID:
2793 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2794 MPT2SAS_HP_2_4_EXTERNAL_BRANDING);
2795 break;
2796 case MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_SSDID:
2797 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2798 MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_BRANDING);
2799 break;
2800 case MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_SSDID:
2801 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2802 MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_BRANDING);
2803 break;
2804 default:
2805 pr_info(MPT3SAS_FMT
2806 "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n",
2807 ioc->name, ioc->pdev->subsystem_device);
2808 break;
2809 }
d8eb4a47
SR		 2810 default:
2811 pr_info(MPT3SAS_FMT
989e43c7
SR		 2812 "HP SAS HBA: Subsystem ID: 0x%X\n",
2813 ioc->name, ioc->pdev->subsystem_device);
d8eb4a47
SR		 2814 break;
2815 }
38e4141e 2816 default:
38e4141e
SR		 2817 break;
2818 }
2819}
fb84dfc4 2820
f92363d1
SR		 2821/**
2822 * _base_display_ioc_capabilities - Disply IOC's capabilities.
2823 * @ioc: per adapter object
2824 *
2825 * Return nothing.
2826 */
2827static void
2828_base_display_ioc_capabilities(struct MPT3SAS_ADAPTER *ioc)
2829{
2830 int i = 0;
2831 char desc[16];
2832 u32 iounit_pg1_flags;
2833 u32 bios_version;
2834
2835 bios_version = le32_to_cpu(ioc->bios_pg3.BiosVersion);
2836 strncpy(desc, ioc->manu_pg0.ChipName, 16);
2837 pr_info(MPT3SAS_FMT "%s: FWVersion(%02d.%02d.%02d.%02d), "\
2838 "ChipRevision(0x%02x), BiosVersion(%02d.%02d.%02d.%02d)\n",
2839 ioc->name, desc,
2840 (ioc->facts.FWVersion.Word & 0xFF000000) >> 24,
2841 (ioc->facts.FWVersion.Word & 0x00FF0000) >> 16,
2842 (ioc->facts.FWVersion.Word & 0x0000FF00) >> 8,
2843 ioc->facts.FWVersion.Word & 0x000000FF,
2844 ioc->pdev->revision,
2845 (bios_version & 0xFF000000) >> 24,
2846 (bios_version & 0x00FF0000) >> 16,
2847 (bios_version & 0x0000FF00) >> 8,
2848 bios_version & 0x000000FF);
2849
989e43c7 2850 _base_display_OEMs_branding(ioc);
1117b31a 2851
f92363d1
SR		 2852 pr_info(MPT3SAS_FMT "Protocol=(", ioc->name);
2853
2854 if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR) {
2855 pr_info("Initiator");
2856 i++;
2857 }
2858
2859 if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET) {
2860 pr_info("%sTarget", i ? "," : "");
2861 i++;
2862 }
2863
2864 i = 0;
2865 pr_info("), ");
2866 pr_info("Capabilities=(");
2867
7786ab6a
SR		 2868 if (!ioc->hide_ir_msg) {
2869 if (ioc->facts.IOCCapabilities &
f92363d1
SR		 2870 MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID) {
2871 pr_info("Raid");
2872 i++;
7786ab6a 2873 }
f92363d1
SR		 2874 }
2875
2876 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_TLR) {
2877 pr_info("%sTLR", i ? "," : "");
2878 i++;
2879 }
2880
2881 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_MULTICAST) {
2882 pr_info("%sMulticast", i ? "," : "");
2883 i++;
2884 }
2885
2886 if (ioc->facts.IOCCapabilities &
2887 MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET) {
2888 pr_info("%sBIDI Target", i ? "," : "");
2889 i++;
2890 }
2891
2892 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_EEDP) {
2893 pr_info("%sEEDP", i ? "," : "");
2894 i++;
2895 }
2896
2897 if (ioc->facts.IOCCapabilities &
2898 MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER) {
2899 pr_info("%sSnapshot Buffer", i ? "," : "");
2900 i++;
2901 }
2902
2903 if (ioc->facts.IOCCapabilities &
2904 MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER) {
2905 pr_info("%sDiag Trace Buffer", i ? "," : "");
2906 i++;
2907 }
2908
2909 if (ioc->facts.IOCCapabilities &
2910 MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER) {
2911 pr_info("%sDiag Extended Buffer", i ? "," : "");
2912 i++;
2913 }
2914
2915 if (ioc->facts.IOCCapabilities &
2916 MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING) {
2917 pr_info("%sTask Set Full", i ? "," : "");
2918 i++;
2919 }
2920
2921 iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
2922 if (!(iounit_pg1_flags & MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE)) {
2923 pr_info("%sNCQ", i ? "," : "");
2924 i++;
2925 }
2926
2927 pr_info(")\n");
2928}
2929
2930/**
2931 * mpt3sas_base_update_missing_delay - change the missing delay timers
2932 * @ioc: per adapter object
2933 * @device_missing_delay: amount of time till device is reported missing
2934 * @io_missing_delay: interval IO is returned when there is a missing device
2935 *
2936 * Return nothing.
2937 *
2938 * Passed on the command line, this function will modify the device missing
2939 * delay, as well as the io missing delay. This should be called at driver
2940 * load time.
2941 */
2942void
2943mpt3sas_base_update_missing_delay(struct MPT3SAS_ADAPTER *ioc,
2944 u16 device_missing_delay, u8 io_missing_delay)
2945{
2946 u16 dmd, dmd_new, dmd_orignal;
2947 u8 io_missing_delay_original;
2948 u16 sz;
2949 Mpi2SasIOUnitPage1_t *sas_iounit_pg1 = NULL;
2950 Mpi2ConfigReply_t mpi_reply;
2951 u8 num_phys = 0;
2952 u16 ioc_status;
2953
2954 mpt3sas_config_get_number_hba_phys(ioc, &num_phys);
2955 if (!num_phys)
2956 return;
2957
2958 sz = offsetof(Mpi2SasIOUnitPage1_t, PhyData) + (num_phys *
2959 sizeof(Mpi2SasIOUnit1PhyData_t));
2960 sas_iounit_pg1 = kzalloc(sz, GFP_KERNEL);
2961 if (!sas_iounit_pg1) {
2962 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
2963 ioc->name, __FILE__, __LINE__, __func__);
2964 goto out;
2965 }
2966 if ((mpt3sas_config_get_sas_iounit_pg1(ioc, &mpi_reply,
2967 sas_iounit_pg1, sz))) {
2968 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
2969 ioc->name, __FILE__, __LINE__, __func__);
2970 goto out;
2971 }
2972 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
2973 MPI2_IOCSTATUS_MASK;
2974 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
2975 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
2976 ioc->name, __FILE__, __LINE__, __func__);
2977 goto out;
2978 }
2979
2980 /* device missing delay */
2981 dmd = sas_iounit_pg1->ReportDeviceMissingDelay;
2982 if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16)
2983 dmd = (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16;
2984 else
2985 dmd = dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
2986 dmd_orignal = dmd;
2987 if (device_missing_delay > 0x7F) {
2988 dmd = (device_missing_delay > 0x7F0) ? 0x7F0 :
2989 device_missing_delay;
2990 dmd = dmd / 16;
2991 dmd |= MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16;
2992 } else
2993 dmd = device_missing_delay;
2994 sas_iounit_pg1->ReportDeviceMissingDelay = dmd;
2995
2996 /* io missing delay */
2997 io_missing_delay_original = sas_iounit_pg1->IODeviceMissingDelay;
2998 sas_iounit_pg1->IODeviceMissingDelay = io_missing_delay;
2999
3000 if (!mpt3sas_config_set_sas_iounit_pg1(ioc, &mpi_reply, sas_iounit_pg1,
3001 sz)) {
3002 if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16)
3003 dmd_new = (dmd &
3004 MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16;
3005 else
3006 dmd_new =
3007 dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
3008 pr_info(MPT3SAS_FMT "device_missing_delay: old(%d), new(%d)\n",
3009 ioc->name, dmd_orignal, dmd_new);
3010 pr_info(MPT3SAS_FMT "ioc_missing_delay: old(%d), new(%d)\n",
3011 ioc->name, io_missing_delay_original,
3012 io_missing_delay);
3013 ioc->device_missing_delay = dmd_new;
3014 ioc->io_missing_delay = io_missing_delay;
3015 }
3016
3017out:
3018 kfree(sas_iounit_pg1);
3019}
3020/**
3021 * _base_static_config_pages - static start of day config pages
3022 * @ioc: per adapter object
3023 *
3024 * Return nothing.
3025 */
3026static void
3027_base_static_config_pages(struct MPT3SAS_ADAPTER *ioc)
3028{
3029 Mpi2ConfigReply_t mpi_reply;
3030 u32 iounit_pg1_flags;
3031
3032 mpt3sas_config_get_manufacturing_pg0(ioc, &mpi_reply, &ioc->manu_pg0);
3033 if (ioc->ir_firmware)
3034 mpt3sas_config_get_manufacturing_pg10(ioc, &mpi_reply,
3035 &ioc->manu_pg10);
3036
3037 /*
3038 * Ensure correct T10 PI operation if vendor left EEDPTagMode
3039 * flag unset in NVDATA.
3040 */
3041 mpt3sas_config_get_manufacturing_pg11(ioc, &mpi_reply, &ioc->manu_pg11);
3042 if (ioc->manu_pg11.EEDPTagMode == 0) {
3043 pr_err("%s: overriding NVDATA EEDPTagMode setting\n",
3044 ioc->name);
3045 ioc->manu_pg11.EEDPTagMode &= ~0x3;
3046 ioc->manu_pg11.EEDPTagMode |= 0x1;
3047 mpt3sas_config_set_manufacturing_pg11(ioc, &mpi_reply,
3048 &ioc->manu_pg11);
3049 }
3050
3051 mpt3sas_config_get_bios_pg2(ioc, &mpi_reply, &ioc->bios_pg2);
3052 mpt3sas_config_get_bios_pg3(ioc, &mpi_reply, &ioc->bios_pg3);
3053 mpt3sas_config_get_ioc_pg8(ioc, &mpi_reply, &ioc->ioc_pg8);
3054 mpt3sas_config_get_iounit_pg0(ioc, &mpi_reply, &ioc->iounit_pg0);
3055 mpt3sas_config_get_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
2d8ce8c9 3056 mpt3sas_config_get_iounit_pg8(ioc, &mpi_reply, &ioc->iounit_pg8);
f92363d1
SR		 3057 _base_display_ioc_capabilities(ioc);
3058
3059 /*
3060 * Enable task_set_full handling in iounit_pg1 when the
3061 * facts capabilities indicate that its supported.
3062 */
3063 iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
3064 if ((ioc->facts.IOCCapabilities &
3065 MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING))
3066 iounit_pg1_flags &=
3067 ~MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
3068 else
3069 iounit_pg1_flags |=
3070 MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
3071 ioc->iounit_pg1.Flags = cpu_to_le32(iounit_pg1_flags);
3072 mpt3sas_config_set_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
2d8ce8c9
SR		 3073
3074 if (ioc->iounit_pg8.NumSensors)
3075 ioc->temp_sensors_count = ioc->iounit_pg8.NumSensors;
f92363d1
SR		 3076}
3077
3078/**
3079 * _base_release_memory_pools - release memory
3080 * @ioc: per adapter object
3081 *
3082 * Free memory allocated from _base_allocate_memory_pools.
3083 *
3084 * Return nothing.
3085 */
3086static void
3087_base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc)
3088{
9b05c91a
SR		 3089 int i = 0;
3090 struct reply_post_struct *rps;
f92363d1
SR		 3091
3092 dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3093 __func__));
3094
3095 if (ioc->request) {
3096 pci_free_consistent(ioc->pdev, ioc->request_dma_sz,
3097 ioc->request, ioc->request_dma);
3098 dexitprintk(ioc, pr_info(MPT3SAS_FMT
3099 "request_pool(0x%p): free\n",
3100 ioc->name, ioc->request));
3101 ioc->request = NULL;
3102 }
3103
3104 if (ioc->sense) {
3105 pci_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma);
3106 if (ioc->sense_dma_pool)
3107 pci_pool_destroy(ioc->sense_dma_pool);
3108 dexitprintk(ioc, pr_info(MPT3SAS_FMT
3109 "sense_pool(0x%p): free\n",
3110 ioc->name, ioc->sense));
3111 ioc->sense = NULL;
3112 }
3113
3114 if (ioc->reply) {
3115 pci_pool_free(ioc->reply_dma_pool, ioc->reply, ioc->reply_dma);
3116 if (ioc->reply_dma_pool)
3117 pci_pool_destroy(ioc->reply_dma_pool);
3118 dexitprintk(ioc, pr_info(MPT3SAS_FMT
3119 "reply_pool(0x%p): free\n",
3120 ioc->name, ioc->reply));
3121 ioc->reply = NULL;
3122 }
3123
3124 if (ioc->reply_free) {
3125 pci_pool_free(ioc->reply_free_dma_pool, ioc->reply_free,
3126 ioc->reply_free_dma);
3127 if (ioc->reply_free_dma_pool)
3128 pci_pool_destroy(ioc->reply_free_dma_pool);
3129 dexitprintk(ioc, pr_info(MPT3SAS_FMT
3130 "reply_free_pool(0x%p): free\n",
3131 ioc->name, ioc->reply_free));
3132 ioc->reply_free = NULL;
3133 }
3134
9b05c91a
SR		 3135 if (ioc->reply_post) {
3136 do {
3137 rps = &ioc->reply_post[i];
3138 if (rps->reply_post_free) {
3139 pci_pool_free(
3140 ioc->reply_post_free_dma_pool,
3141 rps->reply_post_free,
3142 rps->reply_post_free_dma);
3143 dexitprintk(ioc, pr_info(MPT3SAS_FMT
3144 "reply_post_free_pool(0x%p): free\n",
3145 ioc->name, rps->reply_post_free));
3146 rps->reply_post_free = NULL;
3147 }
3148 } while (ioc->rdpq_array_enable &&
3149 (++i < ioc->reply_queue_count));
3150
f92363d1
SR		 3151 if (ioc->reply_post_free_dma_pool)
3152 pci_pool_destroy(ioc->reply_post_free_dma_pool);
9b05c91a 3153 kfree(ioc->reply_post);
f92363d1
SR		 3154 }
3155
3156 if (ioc->config_page) {
3157 dexitprintk(ioc, pr_info(MPT3SAS_FMT
3158 "config_page(0x%p): free\n", ioc->name,
3159 ioc->config_page));
3160 pci_free_consistent(ioc->pdev, ioc->config_page_sz,
3161 ioc->config_page, ioc->config_page_dma);
3162 }
3163
3164 if (ioc->scsi_lookup) {
3165 free_pages((ulong)ioc->scsi_lookup, ioc->scsi_lookup_pages);
3166 ioc->scsi_lookup = NULL;
3167 }
3168 kfree(ioc->hpr_lookup);
3169 kfree(ioc->internal_lookup);
3170 if (ioc->chain_lookup) {
3171 for (i = 0; i < ioc->chain_depth; i++) {
3172 if (ioc->chain_lookup[i].chain_buffer)
3173 pci_pool_free(ioc->chain_dma_pool,
3174 ioc->chain_lookup[i].chain_buffer,
3175 ioc->chain_lookup[i].chain_buffer_dma);
3176 }
3177 if (ioc->chain_dma_pool)
3178 pci_pool_destroy(ioc->chain_dma_pool);
3179 free_pages((ulong)ioc->chain_lookup, ioc->chain_pages);
3180 ioc->chain_lookup = NULL;
3181 }
3182}
3183
3184/**
3185 * _base_allocate_memory_pools - allocate start of day memory pools
3186 * @ioc: per adapter object
f92363d1
SR		 3187 *
3188 * Returns 0 success, anything else error
3189 */
3190static int
98c56ad3 3191_base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc)
f92363d1
SR		 3192{
3193 struct mpt3sas_facts *facts;
3194 u16 max_sge_elements;
3195 u16 chains_needed_per_io;
3196 u32 sz, total_sz, reply_post_free_sz;
3197 u32 retry_sz;
3198 u16 max_request_credit;
3199 unsigned short sg_tablesize;
3200 u16 sge_size;
3201 int i;
3202
3203 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3204 __func__));
3205
3206
3207 retry_sz = 0;
3208 facts = &ioc->facts;
3209
3210 /* command line tunables for max sgl entries */
3211 if (max_sgl_entries != -1)
3212 sg_tablesize = max_sgl_entries;
471ef9d4
SR		 3213 else {
3214 if (ioc->hba_mpi_version_belonged == MPI2_VERSION)
3215 sg_tablesize = MPT2SAS_SG_DEPTH;
3216 else
3217 sg_tablesize = MPT3SAS_SG_DEPTH;
3218 }
f92363d1 3219
8a7e4c24
SR		 3220 if (sg_tablesize < MPT_MIN_PHYS_SEGMENTS)
3221 sg_tablesize = MPT_MIN_PHYS_SEGMENTS;
3222 else if (sg_tablesize > MPT_MAX_PHYS_SEGMENTS) {
ad666a0f 3223 sg_tablesize = min_t(unsigned short, sg_tablesize,
65e8617f 3224 SG_MAX_SEGMENTS);
ad666a0f
SR		 3225 pr_warn(MPT3SAS_FMT
3226 "sg_tablesize(%u) is bigger than kernel"
65e8617f 3227 " defined SG_CHUNK_SIZE(%u)\n", ioc->name,
8a7e4c24 3228 sg_tablesize, MPT_MAX_PHYS_SEGMENTS);
ad666a0f 3229 }
f92363d1
SR		 3230 ioc->shost->sg_tablesize = sg_tablesize;
3231
fd0331b3
SS		 3232 ioc->internal_depth = min_t(int, (facts->HighPriorityCredit + (5)),
3233 (facts->RequestCredit / 4));
3234 if (ioc->internal_depth < INTERNAL_CMDS_COUNT) {
3235 if (facts->RequestCredit <= (INTERNAL_CMDS_COUNT +
3236 INTERNAL_SCSIIO_CMDS_COUNT)) {
3237 pr_err(MPT3SAS_FMT "IOC doesn't have enough Request \
3238 Credits, it has just %d number of credits\n",
3239 ioc->name, facts->RequestCredit);
3240 return -ENOMEM;
3241 }
3242 ioc->internal_depth = 10;
3243 }
3244
3245 ioc->hi_priority_depth = ioc->internal_depth - (5);
f92363d1
SR		 3246 /* command line tunables for max controller queue depth */
3247 if (max_queue_depth != -1 && max_queue_depth != 0) {
3248 max_request_credit = min_t(u16, max_queue_depth +
fd0331b3 3249 ioc->internal_depth, facts->RequestCredit);
f92363d1
SR		 3250 if (max_request_credit > MAX_HBA_QUEUE_DEPTH)
3251 max_request_credit = MAX_HBA_QUEUE_DEPTH;
3252 } else
3253 max_request_credit = min_t(u16, facts->RequestCredit,
3254 MAX_HBA_QUEUE_DEPTH);
3255
fd0331b3
SS		 3256 /* Firmware maintains additional facts->HighPriorityCredit number of
3257 * credits for HiPriprity Request messages, so hba queue depth will be
3258 * sum of max_request_credit and high priority queue depth.
3259 */
3260 ioc->hba_queue_depth = max_request_credit + ioc->hi_priority_depth;
f92363d1
SR		 3261
3262 /* request frame size */
3263 ioc->request_sz = facts->IOCRequestFrameSize * 4;
3264
3265 /* reply frame size */
3266 ioc->reply_sz = facts->ReplyFrameSize * 4;
3267
ebb3024e
SS		 3268 /* chain segment size */
3269 if (ioc->hba_mpi_version_belonged != MPI2_VERSION) {
3270 if (facts->IOCMaxChainSegmentSize)
3271 ioc->chain_segment_sz =
3272 facts->IOCMaxChainSegmentSize *
3273 MAX_CHAIN_ELEMT_SZ;
3274 else
3275 /* set to 128 bytes size if IOCMaxChainSegmentSize is zero */
3276 ioc->chain_segment_sz = DEFAULT_NUM_FWCHAIN_ELEMTS *
3277 MAX_CHAIN_ELEMT_SZ;
3278 } else
3279 ioc->chain_segment_sz = ioc->request_sz;
3280
f92363d1
SR		 3281 /* calculate the max scatter element size */
3282 sge_size = max_t(u16, ioc->sge_size, ioc->sge_size_ieee);
3283
3284 retry_allocation:
3285 total_sz = 0;
3286 /* calculate number of sg elements left over in the 1st frame */
3287 max_sge_elements = ioc->request_sz - ((sizeof(Mpi2SCSIIORequest_t) -
3288 sizeof(Mpi2SGEIOUnion_t)) + sge_size);
3289 ioc->max_sges_in_main_message = max_sge_elements/sge_size;
3290
3291 /* now do the same for a chain buffer */
ebb3024e 3292 max_sge_elements = ioc->chain_segment_sz - sge_size;
f92363d1
SR		 3293 ioc->max_sges_in_chain_message = max_sge_elements/sge_size;
3294
3295 /*
3296 * MPT3SAS_SG_DEPTH = CONFIG_FUSION_MAX_SGE
3297 */
3298 chains_needed_per_io = ((ioc->shost->sg_tablesize -
3299 ioc->max_sges_in_main_message)/ioc->max_sges_in_chain_message)
3300 + 1;
3301 if (chains_needed_per_io > facts->MaxChainDepth) {
3302 chains_needed_per_io = facts->MaxChainDepth;
3303 ioc->shost->sg_tablesize = min_t(u16,
3304 ioc->max_sges_in_main_message + (ioc->max_sges_in_chain_message
3305 * chains_needed_per_io), ioc->shost->sg_tablesize);
3306 }
3307 ioc->chains_needed_per_io = chains_needed_per_io;
3308
3309 /* reply free queue sizing - taking into account for 64 FW events */
3310 ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64;
3311
3312 /* calculate reply descriptor post queue depth */
3313 ioc->reply_post_queue_depth = ioc->hba_queue_depth +
3314 ioc->reply_free_queue_depth + 1 ;
3315 /* align the reply post queue on the next 16 count boundary */
3316 if (ioc->reply_post_queue_depth % 16)
3317 ioc->reply_post_queue_depth += 16 -
3318 (ioc->reply_post_queue_depth % 16);
3319
f92363d1
SR		 3320 if (ioc->reply_post_queue_depth >
3321 facts->MaxReplyDescriptorPostQueueDepth) {
3322 ioc->reply_post_queue_depth =
3323 facts->MaxReplyDescriptorPostQueueDepth -
3324 (facts->MaxReplyDescriptorPostQueueDepth % 16);
3325 ioc->hba_queue_depth =
3326 ((ioc->reply_post_queue_depth - 64) / 2) - 1;
3327 ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64;
3328 }
3329
3330 dinitprintk(ioc, pr_info(MPT3SAS_FMT "scatter gather: " \
3331 "sge_in_main_msg(%d), sge_per_chain(%d), sge_per_io(%d), "
3332 "chains_per_io(%d)\n", ioc->name, ioc->max_sges_in_main_message,
3333 ioc->max_sges_in_chain_message, ioc->shost->sg_tablesize,
3334 ioc->chains_needed_per_io));
3335
9b05c91a
SR		 3336 /* reply post queue, 16 byte align */
3337 reply_post_free_sz = ioc->reply_post_queue_depth *
3338 sizeof(Mpi2DefaultReplyDescriptor_t);
3339
3340 sz = reply_post_free_sz;
3341 if (_base_is_controller_msix_enabled(ioc) && !ioc->rdpq_array_enable)
3342 sz *= ioc->reply_queue_count;
3343
3344 ioc->reply_post = kcalloc((ioc->rdpq_array_enable) ?
3345 (ioc->reply_queue_count):1,
3346 sizeof(struct reply_post_struct), GFP_KERNEL);
3347
3348 if (!ioc->reply_post) {
3349 pr_err(MPT3SAS_FMT "reply_post_free pool: kcalloc failed\n",
3350 ioc->name);
3351 goto out;
3352 }
3353 ioc->reply_post_free_dma_pool = pci_pool_create("reply_post_free pool",
3354 ioc->pdev, sz, 16, 0);
3355 if (!ioc->reply_post_free_dma_pool) {
3356 pr_err(MPT3SAS_FMT
3357 "reply_post_free pool: pci_pool_create failed\n",
3358 ioc->name);
3359 goto out;
3360 }
3361 i = 0;
3362 do {
3363 ioc->reply_post[i].reply_post_free =
3364 pci_pool_alloc(ioc->reply_post_free_dma_pool,
3365 GFP_KERNEL,
3366 &ioc->reply_post[i].reply_post_free_dma);
3367 if (!ioc->reply_post[i].reply_post_free) {
3368 pr_err(MPT3SAS_FMT
3369 "reply_post_free pool: pci_pool_alloc failed\n",
3370 ioc->name);
3371 goto out;
3372 }
3373 memset(ioc->reply_post[i].reply_post_free, 0, sz);
3374 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3375 "reply post free pool (0x%p): depth(%d),"
3376 "element_size(%d), pool_size(%d kB)\n", ioc->name,
3377 ioc->reply_post[i].reply_post_free,
3378 ioc->reply_post_queue_depth, 8, sz/1024));
3379 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3380 "reply_post_free_dma = (0x%llx)\n", ioc->name,
3381 (unsigned long long)
3382 ioc->reply_post[i].reply_post_free_dma));
3383 total_sz += sz;
3384 } while (ioc->rdpq_array_enable && (++i < ioc->reply_queue_count));
3385
3386 if (ioc->dma_mask == 64) {
3387 if (_base_change_consistent_dma_mask(ioc, ioc->pdev) != 0) {
3388 pr_warn(MPT3SAS_FMT
3389 "no suitable consistent DMA mask for %s\n",
3390 ioc->name, pci_name(ioc->pdev));
3391 goto out;
3392 }
3393 }
3394
f92363d1
SR		 3395 ioc->scsiio_depth = ioc->hba_queue_depth -
3396 ioc->hi_priority_depth - ioc->internal_depth;
3397
3398 /* set the scsi host can_queue depth
3399 * with some internal commands that could be outstanding
3400 */
fd0331b3 3401 ioc->shost->can_queue = ioc->scsiio_depth - INTERNAL_SCSIIO_CMDS_COUNT;
f92363d1
SR		 3402 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3403 "scsi host: can_queue depth (%d)\n",
3404 ioc->name, ioc->shost->can_queue));
3405
3406
3407 /* contiguous pool for request and chains, 16 byte align, one extra "
3408 * "frame for smid=0
3409 */
3410 ioc->chain_depth = ioc->chains_needed_per_io * ioc->scsiio_depth;
3411 sz = ((ioc->scsiio_depth + 1) * ioc->request_sz);
3412
3413 /* hi-priority queue */
3414 sz += (ioc->hi_priority_depth * ioc->request_sz);
3415
3416 /* internal queue */
3417 sz += (ioc->internal_depth * ioc->request_sz);
3418
3419 ioc->request_dma_sz = sz;
3420 ioc->request = pci_alloc_consistent(ioc->pdev, sz, &ioc->request_dma);
3421 if (!ioc->request) {
3422 pr_err(MPT3SAS_FMT "request pool: pci_alloc_consistent " \
3423 "failed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
3424 "total(%d kB)\n", ioc->name, ioc->hba_queue_depth,
3425 ioc->chains_needed_per_io, ioc->request_sz, sz/1024);
3426 if (ioc->scsiio_depth < MPT3SAS_SAS_QUEUE_DEPTH)
3427 goto out;
fd0331b3
SS		 3428 retry_sz = 64;
3429 ioc->hba_queue_depth -= retry_sz;
8ff045c9 3430 _base_release_memory_pools(ioc);
f92363d1
SR		 3431 goto retry_allocation;
3432 }
3433
3434 if (retry_sz)
3435 pr_err(MPT3SAS_FMT "request pool: pci_alloc_consistent " \
3436 "succeed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
3437 "total(%d kb)\n", ioc->name, ioc->hba_queue_depth,
3438 ioc->chains_needed_per_io, ioc->request_sz, sz/1024);
3439
3440 /* hi-priority queue */
3441 ioc->hi_priority = ioc->request + ((ioc->scsiio_depth + 1) *
3442 ioc->request_sz);
3443 ioc->hi_priority_dma = ioc->request_dma + ((ioc->scsiio_depth + 1) *
3444 ioc->request_sz);
3445
3446 /* internal queue */
3447 ioc->internal = ioc->hi_priority + (ioc->hi_priority_depth *
3448 ioc->request_sz);
3449 ioc->internal_dma = ioc->hi_priority_dma + (ioc->hi_priority_depth *
3450 ioc->request_sz);
3451
3452 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3453 "request pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n",
3454 ioc->name, ioc->request, ioc->hba_queue_depth, ioc->request_sz,
3455 (ioc->hba_queue_depth * ioc->request_sz)/1024));
3456
3457 dinitprintk(ioc, pr_info(MPT3SAS_FMT "request pool: dma(0x%llx)\n",
3458 ioc->name, (unsigned long long) ioc->request_dma));
3459 total_sz += sz;
3460
3461 sz = ioc->scsiio_depth * sizeof(struct scsiio_tracker);
3462 ioc->scsi_lookup_pages = get_order(sz);
3463 ioc->scsi_lookup = (struct scsiio_tracker *)__get_free_pages(
3464 GFP_KERNEL, ioc->scsi_lookup_pages);
3465 if (!ioc->scsi_lookup) {
3466 pr_err(MPT3SAS_FMT "scsi_lookup: get_free_pages failed, sz(%d)\n",
3467 ioc->name, (int)sz);
3468 goto out;
3469 }
3470
3471 dinitprintk(ioc, pr_info(MPT3SAS_FMT "scsiio(0x%p): depth(%d)\n",
3472 ioc->name, ioc->request, ioc->scsiio_depth));
3473
3474 ioc->chain_depth = min_t(u32, ioc->chain_depth, MAX_CHAIN_DEPTH);
3475 sz = ioc->chain_depth * sizeof(struct chain_tracker);
3476 ioc->chain_pages = get_order(sz);
3477 ioc->chain_lookup = (struct chain_tracker *)__get_free_pages(
3478 GFP_KERNEL, ioc->chain_pages);
3479 if (!ioc->chain_lookup) {
3480 pr_err(MPT3SAS_FMT "chain_lookup: __get_free_pages failed\n",
3481 ioc->name);
3482 goto out;
3483 }
3484 ioc->chain_dma_pool = pci_pool_create("chain pool", ioc->pdev,
ebb3024e 3485 ioc->chain_segment_sz, 16, 0);
f92363d1
SR		 3486 if (!ioc->chain_dma_pool) {
3487 pr_err(MPT3SAS_FMT "chain_dma_pool: pci_pool_create failed\n",
3488 ioc->name);
3489 goto out;
3490 }
3491 for (i = 0; i < ioc->chain_depth; i++) {
3492 ioc->chain_lookup[i].chain_buffer = pci_pool_alloc(
3493 ioc->chain_dma_pool , GFP_KERNEL,
3494 &ioc->chain_lookup[i].chain_buffer_dma);
3495 if (!ioc->chain_lookup[i].chain_buffer) {
3496 ioc->chain_depth = i;
3497 goto chain_done;
3498 }
ebb3024e 3499 total_sz += ioc->chain_segment_sz;
f92363d1
SR		 3500 }
3501 chain_done:
3502 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3503 "chain pool depth(%d), frame_size(%d), pool_size(%d kB)\n",
ebb3024e
SS		 3504 ioc->name, ioc->chain_depth, ioc->chain_segment_sz,
3505 ((ioc->chain_depth * ioc->chain_segment_sz))/1024));
f92363d1
SR		 3506
3507 /* initialize hi-priority queue smid's */
3508 ioc->hpr_lookup = kcalloc(ioc->hi_priority_depth,
3509 sizeof(struct request_tracker), GFP_KERNEL);
3510 if (!ioc->hpr_lookup) {
3511 pr_err(MPT3SAS_FMT "hpr_lookup: kcalloc failed\n",
3512 ioc->name);
3513 goto out;
3514 }
3515 ioc->hi_priority_smid = ioc->scsiio_depth + 1;
3516 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3517 "hi_priority(0x%p): depth(%d), start smid(%d)\n",
3518 ioc->name, ioc->hi_priority,
3519 ioc->hi_priority_depth, ioc->hi_priority_smid));
3520
3521 /* initialize internal queue smid's */
3522 ioc->internal_lookup = kcalloc(ioc->internal_depth,
3523 sizeof(struct request_tracker), GFP_KERNEL);
3524 if (!ioc->internal_lookup) {
3525 pr_err(MPT3SAS_FMT "internal_lookup: kcalloc failed\n",
3526 ioc->name);
3527 goto out;
3528 }
3529 ioc->internal_smid = ioc->hi_priority_smid + ioc->hi_priority_depth;
3530 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3531 "internal(0x%p): depth(%d), start smid(%d)\n",
3532 ioc->name, ioc->internal,
3533 ioc->internal_depth, ioc->internal_smid));
3534
3535 /* sense buffers, 4 byte align */
3536 sz = ioc->scsiio_depth * SCSI_SENSE_BUFFERSIZE;
3537 ioc->sense_dma_pool = pci_pool_create("sense pool", ioc->pdev, sz, 4,
3538 0);
3539 if (!ioc->sense_dma_pool) {
3540 pr_err(MPT3SAS_FMT "sense pool: pci_pool_create failed\n",
3541 ioc->name);
3542 goto out;
3543 }
3544 ioc->sense = pci_pool_alloc(ioc->sense_dma_pool , GFP_KERNEL,
3545 &ioc->sense_dma);
3546 if (!ioc->sense) {
3547 pr_err(MPT3SAS_FMT "sense pool: pci_pool_alloc failed\n",
3548 ioc->name);
3549 goto out;
3550 }
3551 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3552 "sense pool(0x%p): depth(%d), element_size(%d), pool_size"
3553 "(%d kB)\n", ioc->name, ioc->sense, ioc->scsiio_depth,
3554 SCSI_SENSE_BUFFERSIZE, sz/1024));
3555 dinitprintk(ioc, pr_info(MPT3SAS_FMT "sense_dma(0x%llx)\n",
3556 ioc->name, (unsigned long long)ioc->sense_dma));
3557 total_sz += sz;
3558
3559 /* reply pool, 4 byte align */
3560 sz = ioc->reply_free_queue_depth * ioc->reply_sz;
3561 ioc->reply_dma_pool = pci_pool_create("reply pool", ioc->pdev, sz, 4,
3562 0);
3563 if (!ioc->reply_dma_pool) {
3564 pr_err(MPT3SAS_FMT "reply pool: pci_pool_create failed\n",
3565 ioc->name);
3566 goto out;
3567 }
3568 ioc->reply = pci_pool_alloc(ioc->reply_dma_pool , GFP_KERNEL,
3569 &ioc->reply_dma);
3570 if (!ioc->reply) {
3571 pr_err(MPT3SAS_FMT "reply pool: pci_pool_alloc failed\n",
3572 ioc->name);
3573 goto out;
3574 }
3575 ioc->reply_dma_min_address = (u32)(ioc->reply_dma);
3576 ioc->reply_dma_max_address = (u32)(ioc->reply_dma) + sz;
3577 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3578 "reply pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n",
3579 ioc->name, ioc->reply,
3580 ioc->reply_free_queue_depth, ioc->reply_sz, sz/1024));
3581 dinitprintk(ioc, pr_info(MPT3SAS_FMT "reply_dma(0x%llx)\n",
3582 ioc->name, (unsigned long long)ioc->reply_dma));
3583 total_sz += sz;
3584
3585 /* reply free queue, 16 byte align */
3586 sz = ioc->reply_free_queue_depth * 4;
3587 ioc->reply_free_dma_pool = pci_pool_create("reply_free pool",
3588 ioc->pdev, sz, 16, 0);
3589 if (!ioc->reply_free_dma_pool) {
3590 pr_err(MPT3SAS_FMT "reply_free pool: pci_pool_create failed\n",
3591 ioc->name);
3592 goto out;
3593 }
3594 ioc->reply_free = pci_pool_alloc(ioc->reply_free_dma_pool , GFP_KERNEL,
3595 &ioc->reply_free_dma);
3596 if (!ioc->reply_free) {
3597 pr_err(MPT3SAS_FMT "reply_free pool: pci_pool_alloc failed\n",
3598 ioc->name);
3599 goto out;
3600 }
3601 memset(ioc->reply_free, 0, sz);
3602 dinitprintk(ioc, pr_info(MPT3SAS_FMT "reply_free pool(0x%p): " \
3603 "depth(%d), element_size(%d), pool_size(%d kB)\n", ioc->name,
3604 ioc->reply_free, ioc->reply_free_queue_depth, 4, sz/1024));
3605 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3606 "reply_free_dma (0x%llx)\n",
3607 ioc->name, (unsigned long long)ioc->reply_free_dma));
3608 total_sz += sz;
3609
f92363d1
SR		 3610 ioc->config_page_sz = 512;
3611 ioc->config_page = pci_alloc_consistent(ioc->pdev,
3612 ioc->config_page_sz, &ioc->config_page_dma);
3613 if (!ioc->config_page) {
3614 pr_err(MPT3SAS_FMT
3615 "config page: pci_pool_alloc failed\n",
3616 ioc->name);
3617 goto out;
3618 }
3619 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3620 "config page(0x%p): size(%d)\n",
3621 ioc->name, ioc->config_page, ioc->config_page_sz));
3622 dinitprintk(ioc, pr_info(MPT3SAS_FMT "config_page_dma(0x%llx)\n",
3623 ioc->name, (unsigned long long)ioc->config_page_dma));
3624 total_sz += ioc->config_page_sz;
3625
3626 pr_info(MPT3SAS_FMT "Allocated physical memory: size(%d kB)\n",
3627 ioc->name, total_sz/1024);
3628 pr_info(MPT3SAS_FMT
3629 "Current Controller Queue Depth(%d),Max Controller Queue Depth(%d)\n",
3630 ioc->name, ioc->shost->can_queue, facts->RequestCredit);
3631 pr_info(MPT3SAS_FMT "Scatter Gather Elements per IO(%d)\n",
3632 ioc->name, ioc->shost->sg_tablesize);
3633 return 0;
3634
3635 out:
3636 return -ENOMEM;
3637}
3638
3639/**
3640 * mpt3sas_base_get_iocstate - Get the current state of a MPT adapter.
3641 * @ioc: Pointer to MPT_ADAPTER structure
3642 * @cooked: Request raw or cooked IOC state
3643 *
3644 * Returns all IOC Doorbell register bits if cooked==0, else just the
3645 * Doorbell bits in MPI_IOC_STATE_MASK.
3646 */
3647u32
3648mpt3sas_base_get_iocstate(struct MPT3SAS_ADAPTER *ioc, int cooked)
3649{
3650 u32 s, sc;
3651
3652 s = readl(&ioc->chip->Doorbell);
3653 sc = s & MPI2_IOC_STATE_MASK;
3654 return cooked ? sc : s;
3655}
3656
3657/**
3658 * _base_wait_on_iocstate - waiting on a particular ioc state
3659 * @ioc_state: controller state { READY, OPERATIONAL, or RESET }
3660 * @timeout: timeout in second
f92363d1
SR		 3661 *
3662 * Returns 0 for success, non-zero for failure.
3663 */
3664static int
98c56ad3 3665_base_wait_on_iocstate(struct MPT3SAS_ADAPTER *ioc, u32 ioc_state, int timeout)
f92363d1
SR		 3666{
3667 u32 count, cntdn;
3668 u32 current_state;
3669
3670 count = 0;
98c56ad3 3671 cntdn = 1000 * timeout;
f92363d1
SR		 3672 do {
3673 current_state = mpt3sas_base_get_iocstate(ioc, 1);
3674 if (current_state == ioc_state)
3675 return 0;
3676 if (count && current_state == MPI2_IOC_STATE_FAULT)
3677 break;
98c56ad3
CO		 3678
3679 usleep_range(1000, 1500);
f92363d1
SR		 3680 count++;
3681 } while (--cntdn);
3682
3683 return current_state;
3684}
3685
3686/**
3687 * _base_wait_for_doorbell_int - waiting for controller interrupt(generated by
3688 * a write to the doorbell)
3689 * @ioc: per adapter object
3690 * @timeout: timeout in second
f92363d1
SR		 3691 *
3692 * Returns 0 for success, non-zero for failure.
3693 *
3694 * Notes: MPI2_HIS_IOC2SYS_DB_STATUS - set to one when IOC writes to doorbell.
3695 */
4dc8c808 3696static int
98c56ad3 3697_base_diag_reset(struct MPT3SAS_ADAPTER *ioc);
4dc8c808 3698
f92363d1 3699static int
98c56ad3 3700_base_wait_for_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout)
f92363d1
SR		 3701{
3702 u32 cntdn, count;
3703 u32 int_status;
3704
3705 count = 0;
98c56ad3 3706 cntdn = 1000 * timeout;
f92363d1
SR		 3707 do {
3708 int_status = readl(&ioc->chip->HostInterruptStatus);
3709 if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
3710 dhsprintk(ioc, pr_info(MPT3SAS_FMT
3711 "%s: successful count(%d), timeout(%d)\n",
3712 ioc->name, __func__, count, timeout));
3713 return 0;
3714 }
98c56ad3
CO		 3715
3716 usleep_range(1000, 1500);
3717 count++;
3718 } while (--cntdn);
3719
3720 pr_err(MPT3SAS_FMT
3721 "%s: failed due to timeout count(%d), int_status(%x)!\n",
3722 ioc->name, __func__, count, int_status);
3723 return -EFAULT;
3724}
3725
3726static int
3727_base_spin_on_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout)
3728{
3729 u32 cntdn, count;
3730 u32 int_status;
3731
3732 count = 0;
3733 cntdn = 2000 * timeout;
3734 do {
3735 int_status = readl(&ioc->chip->HostInterruptStatus);
3736 if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
3737 dhsprintk(ioc, pr_info(MPT3SAS_FMT
3738 "%s: successful count(%d), timeout(%d)\n",
3739 ioc->name, __func__, count, timeout));
3740 return 0;
3741 }
3742
3743 udelay(500);
f92363d1
SR		 3744 count++;
3745 } while (--cntdn);
3746
3747 pr_err(MPT3SAS_FMT
3748 "%s: failed due to timeout count(%d), int_status(%x)!\n",
3749 ioc->name, __func__, count, int_status);
3750 return -EFAULT;
98c56ad3 3751
f92363d1
SR		 3752}
3753
3754/**
3755 * _base_wait_for_doorbell_ack - waiting for controller to read the doorbell.
3756 * @ioc: per adapter object
3757 * @timeout: timeout in second
f92363d1
SR		 3758 *
3759 * Returns 0 for success, non-zero for failure.
3760 *
3761 * Notes: MPI2_HIS_SYS2IOC_DB_STATUS - set to one when host writes to
3762 * doorbell.
3763 */
3764static int
98c56ad3 3765_base_wait_for_doorbell_ack(struct MPT3SAS_ADAPTER *ioc, int timeout)
f92363d1
SR		 3766{
3767 u32 cntdn, count;
3768 u32 int_status;
3769 u32 doorbell;
3770
3771 count = 0;
98c56ad3 3772 cntdn = 1000 * timeout;
f92363d1
SR		 3773 do {
3774 int_status = readl(&ioc->chip->HostInterruptStatus);
3775 if (!(int_status & MPI2_HIS_SYS2IOC_DB_STATUS)) {
3776 dhsprintk(ioc, pr_info(MPT3SAS_FMT
3777 "%s: successful count(%d), timeout(%d)\n",
3778 ioc->name, __func__, count, timeout));
3779 return 0;
3780 } else if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
3781 doorbell = readl(&ioc->chip->Doorbell);
3782 if ((doorbell & MPI2_IOC_STATE_MASK) ==
3783 MPI2_IOC_STATE_FAULT) {
3784 mpt3sas_base_fault_info(ioc , doorbell);
3785 return -EFAULT;
3786 }
3787 } else if (int_status == 0xFFFFFFFF)
3788 goto out;
3789
98c56ad3 3790 usleep_range(1000, 1500);
f92363d1
SR		 3791 count++;
3792 } while (--cntdn);
3793
3794 out:
3795 pr_err(MPT3SAS_FMT
3796 "%s: failed due to timeout count(%d), int_status(%x)!\n",
3797 ioc->name, __func__, count, int_status);
3798 return -EFAULT;
3799}
3800
3801/**
3802 * _base_wait_for_doorbell_not_used - waiting for doorbell to not be in use
3803 * @ioc: per adapter object
3804 * @timeout: timeout in second
f92363d1
SR		 3805 *
3806 * Returns 0 for success, non-zero for failure.
3807 *
3808 */
3809static int
98c56ad3 3810_base_wait_for_doorbell_not_used(struct MPT3SAS_ADAPTER *ioc, int timeout)
f92363d1
SR		 3811{
3812 u32 cntdn, count;
3813 u32 doorbell_reg;
3814
3815 count = 0;
98c56ad3 3816 cntdn = 1000 * timeout;
f92363d1
SR		 3817 do {
3818 doorbell_reg = readl(&ioc->chip->Doorbell);
3819 if (!(doorbell_reg & MPI2_DOORBELL_USED)) {
3820 dhsprintk(ioc, pr_info(MPT3SAS_FMT
3821 "%s: successful count(%d), timeout(%d)\n",
3822 ioc->name, __func__, count, timeout));
3823 return 0;
3824 }
98c56ad3
CO		 3825
3826 usleep_range(1000, 1500);
f92363d1
SR		 3827 count++;
3828 } while (--cntdn);
3829
3830 pr_err(MPT3SAS_FMT
3831 "%s: failed due to timeout count(%d), doorbell_reg(%x)!\n",
3832 ioc->name, __func__, count, doorbell_reg);
3833 return -EFAULT;
3834}
3835
3836/**
3837 * _base_send_ioc_reset - send doorbell reset
3838 * @ioc: per adapter object
3839 * @reset_type: currently only supports: MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET
3840 * @timeout: timeout in second
f92363d1
SR		 3841 *
3842 * Returns 0 for success, non-zero for failure.
3843 */
3844static int
98c56ad3 3845_base_send_ioc_reset(struct MPT3SAS_ADAPTER *ioc, u8 reset_type, int timeout)
f92363d1
SR		 3846{
3847 u32 ioc_state;
3848 int r = 0;
3849
3850 if (reset_type != MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET) {
3851 pr_err(MPT3SAS_FMT "%s: unknown reset_type\n",
3852 ioc->name, __func__);
3853 return -EFAULT;
3854 }
3855
3856 if (!(ioc->facts.IOCCapabilities &
3857 MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY))
3858 return -EFAULT;
3859
3860 pr_info(MPT3SAS_FMT "sending message unit reset !!\n", ioc->name);
3861
3862 writel(reset_type << MPI2_DOORBELL_FUNCTION_SHIFT,
3863 &ioc->chip->Doorbell);
98c56ad3 3864 if ((_base_wait_for_doorbell_ack(ioc, 15))) {
f92363d1
SR		 3865 r = -EFAULT;
3866 goto out;
3867 }
98c56ad3 3868 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, timeout);
f92363d1
SR		 3869 if (ioc_state) {
3870 pr_err(MPT3SAS_FMT
3871 "%s: failed going to ready state (ioc_state=0x%x)\n",
3872 ioc->name, __func__, ioc_state);
3873 r = -EFAULT;
3874 goto out;
3875 }
3876 out:
3877 pr_info(MPT3SAS_FMT "message unit reset: %s\n",
3878 ioc->name, ((r == 0) ? "SUCCESS" : "FAILED"));
3879 return r;
3880}
3881
3882/**
3883 * _base_handshake_req_reply_wait - send request thru doorbell interface
3884 * @ioc: per adapter object
3885 * @request_bytes: request length
3886 * @request: pointer having request payload
3887 * @reply_bytes: reply length
3888 * @reply: pointer to reply payload
3889 * @timeout: timeout in second
f92363d1
SR		 3890 *
3891 * Returns 0 for success, non-zero for failure.
3892 */
3893static int
3894_base_handshake_req_reply_wait(struct MPT3SAS_ADAPTER *ioc, int request_bytes,
98c56ad3 3895 u32 *request, int reply_bytes, u16 *reply, int timeout)
f92363d1
SR		 3896{
3897 MPI2DefaultReply_t *default_reply = (MPI2DefaultReply_t *)reply;
3898 int i;
3899 u8 failed;
f92363d1
SR		 3900 __le32 *mfp;
3901
3902 /* make sure doorbell is not in use */
3903 if ((readl(&ioc->chip->Doorbell) & MPI2_DOORBELL_USED)) {
3904 pr_err(MPT3SAS_FMT
3905 "doorbell is in use (line=%d)\n",
3906 ioc->name, __LINE__);
3907 return -EFAULT;
3908 }
3909
3910 /* clear pending doorbell interrupts from previous state changes */
3911 if (readl(&ioc->chip->HostInterruptStatus) &
3912 MPI2_HIS_IOC2SYS_DB_STATUS)
3913 writel(0, &ioc->chip->HostInterruptStatus);
3914
3915 /* send message to ioc */
3916 writel(((MPI2_FUNCTION_HANDSHAKE<<MPI2_DOORBELL_FUNCTION_SHIFT) |
3917 ((request_bytes/4)<<MPI2_DOORBELL_ADD_DWORDS_SHIFT)),
3918 &ioc->chip->Doorbell);
3919
98c56ad3 3920 if ((_base_spin_on_doorbell_int(ioc, 5))) {
f92363d1
SR		 3921 pr_err(MPT3SAS_FMT
3922 "doorbell handshake int failed (line=%d)\n",
3923 ioc->name, __LINE__);
3924 return -EFAULT;
3925 }
3926 writel(0, &ioc->chip->HostInterruptStatus);
3927
98c56ad3 3928 if ((_base_wait_for_doorbell_ack(ioc, 5))) {
f92363d1
SR		 3929 pr_err(MPT3SAS_FMT
3930 "doorbell handshake ack failed (line=%d)\n",
3931 ioc->name, __LINE__);
3932 return -EFAULT;
3933 }
3934
3935 /* send message 32-bits at a time */
3936 for (i = 0, failed = 0; i < request_bytes/4 && !failed; i++) {
3937 writel(cpu_to_le32(request[i]), &ioc->chip->Doorbell);
98c56ad3 3938 if ((_base_wait_for_doorbell_ack(ioc, 5)))
f92363d1
SR		 3939 failed = 1;
3940 }
3941
3942 if (failed) {
3943 pr_err(MPT3SAS_FMT
3944 "doorbell handshake sending request failed (line=%d)\n",
3945 ioc->name, __LINE__);
3946 return -EFAULT;
3947 }
3948
3949 /* now wait for the reply */
98c56ad3 3950 if ((_base_wait_for_doorbell_int(ioc, timeout))) {
f92363d1
SR		 3951 pr_err(MPT3SAS_FMT
3952 "doorbell handshake int failed (line=%d)\n",
3953 ioc->name, __LINE__);
3954 return -EFAULT;
3955 }
3956
3957 /* read the first two 16-bits, it gives the total length of the reply */
3958 reply[0] = le16_to_cpu(readl(&ioc->chip->Doorbell)
3959 & MPI2_DOORBELL_DATA_MASK);
3960 writel(0, &ioc->chip->HostInterruptStatus);
98c56ad3 3961 if ((_base_wait_for_doorbell_int(ioc, 5))) {
f92363d1
SR		 3962 pr_err(MPT3SAS_FMT
3963 "doorbell handshake int failed (line=%d)\n",
3964 ioc->name, __LINE__);
3965 return -EFAULT;
3966 }
3967 reply[1] = le16_to_cpu(readl(&ioc->chip->Doorbell)
3968 & MPI2_DOORBELL_DATA_MASK);
3969 writel(0, &ioc->chip->HostInterruptStatus);
3970
3971 for (i = 2; i < default_reply->MsgLength * 2; i++) {
98c56ad3 3972 if ((_base_wait_for_doorbell_int(ioc, 5))) {
f92363d1
SR		 3973 pr_err(MPT3SAS_FMT
3974 "doorbell handshake int failed (line=%d)\n",
3975 ioc->name, __LINE__);
3976 return -EFAULT;
3977 }
3978 if (i >= reply_bytes/2) /* overflow case */
8bbb1cf6 3979 readl(&ioc->chip->Doorbell);
f92363d1
SR		 3980 else
3981 reply[i] = le16_to_cpu(readl(&ioc->chip->Doorbell)
3982 & MPI2_DOORBELL_DATA_MASK);
3983 writel(0, &ioc->chip->HostInterruptStatus);
3984 }
3985
98c56ad3
CO		 3986 _base_wait_for_doorbell_int(ioc, 5);
3987 if (_base_wait_for_doorbell_not_used(ioc, 5) != 0) {
f92363d1
SR		 3988 dhsprintk(ioc, pr_info(MPT3SAS_FMT
3989 "doorbell is in use (line=%d)\n", ioc->name, __LINE__));
3990 }
3991 writel(0, &ioc->chip->HostInterruptStatus);
3992
3993 if (ioc->logging_level & MPT_DEBUG_INIT) {
3994 mfp = (__le32 *)reply;
3995 pr_info("\toffset:data\n");
3996 for (i = 0; i < reply_bytes/4; i++)
3997 pr_info("\t[0x%02x]:%08x\n", i*4,
3998 le32_to_cpu(mfp[i]));
3999 }
4000 return 0;
4001}
4002
4003/**
4004 * mpt3sas_base_sas_iounit_control - send sas iounit control to FW
4005 * @ioc: per adapter object
4006 * @mpi_reply: the reply payload from FW
4007 * @mpi_request: the request payload sent to FW
4008 *
4009 * The SAS IO Unit Control Request message allows the host to perform low-level
4010 * operations, such as resets on the PHYs of the IO Unit, also allows the host
4011 * to obtain the IOC assigned device handles for a device if it has other
4012 * identifying information about the device, in addition allows the host to
4013 * remove IOC resources associated with the device.
4014 *
4015 * Returns 0 for success, non-zero for failure.
4016 */
4017int
4018mpt3sas_base_sas_iounit_control(struct MPT3SAS_ADAPTER *ioc,
4019 Mpi2SasIoUnitControlReply_t *mpi_reply,
4020 Mpi2SasIoUnitControlRequest_t *mpi_request)
4021{
4022 u16 smid;
4023 u32 ioc_state;
eb44552b 4024 bool issue_reset = false;
f92363d1
SR		 4025 int rc;
4026 void *request;
4027 u16 wait_state_count;
4028
4029 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4030 __func__));
4031
4032 mutex_lock(&ioc->base_cmds.mutex);
4033
4034 if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) {
4035 pr_err(MPT3SAS_FMT "%s: base_cmd in use\n",
4036 ioc->name, __func__);
4037 rc = -EAGAIN;
4038 goto out;
4039 }
4040
4041 wait_state_count = 0;
4042 ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
4043 while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) {
4044 if (wait_state_count++ == 10) {
4045 pr_err(MPT3SAS_FMT
4046 "%s: failed due to ioc not operational\n",
4047 ioc->name, __func__);
4048 rc = -EFAULT;
4049 goto out;
4050 }
4051 ssleep(1);
4052 ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
4053 pr_info(MPT3SAS_FMT
4054 "%s: waiting for operational state(count=%d)\n",
4055 ioc->name, __func__, wait_state_count);
4056 }
4057
4058 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
4059 if (!smid) {
4060 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4061 ioc->name, __func__);
4062 rc = -EAGAIN;
4063 goto out;
4064 }
4065
4066 rc = 0;
4067 ioc->base_cmds.status = MPT3_CMD_PENDING;
4068 request = mpt3sas_base_get_msg_frame(ioc, smid);
4069 ioc->base_cmds.smid = smid;
4070 memcpy(request, mpi_request, sizeof(Mpi2SasIoUnitControlRequest_t));
4071 if (mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
4072 mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET)
4073 ioc->ioc_link_reset_in_progress = 1;
4074 init_completion(&ioc->base_cmds.done);
4075 mpt3sas_base_put_smid_default(ioc, smid);
8bbb1cf6 4076 wait_for_completion_timeout(&ioc->base_cmds.done,
f92363d1
SR		 4077 msecs_to_jiffies(10000));
4078 if ((mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
4079 mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET) &&
4080 ioc->ioc_link_reset_in_progress)
4081 ioc->ioc_link_reset_in_progress = 0;
4082 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
4083 pr_err(MPT3SAS_FMT "%s: timeout\n",
4084 ioc->name, __func__);
4085 _debug_dump_mf(mpi_request,
4086 sizeof(Mpi2SasIoUnitControlRequest_t)/4);
4087 if (!(ioc->base_cmds.status & MPT3_CMD_RESET))
eb44552b 4088 issue_reset = true;
f92363d1
SR		 4089 goto issue_host_reset;
4090 }
4091 if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID)
4092 memcpy(mpi_reply, ioc->base_cmds.reply,
4093 sizeof(Mpi2SasIoUnitControlReply_t));
4094 else
4095 memset(mpi_reply, 0, sizeof(Mpi2SasIoUnitControlReply_t));
4096 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4097 goto out;
4098
4099 issue_host_reset:
4100 if (issue_reset)
98c56ad3 4101 mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER);
f92363d1
SR		 4102 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4103 rc = -EFAULT;
4104 out:
4105 mutex_unlock(&ioc->base_cmds.mutex);
4106 return rc;
4107}
4108
4109/**
4110 * mpt3sas_base_scsi_enclosure_processor - sending request to sep device
4111 * @ioc: per adapter object
4112 * @mpi_reply: the reply payload from FW
4113 * @mpi_request: the request payload sent to FW
4114 *
4115 * The SCSI Enclosure Processor request message causes the IOC to
4116 * communicate with SES devices to control LED status signals.
4117 *
4118 * Returns 0 for success, non-zero for failure.
4119 */
4120int
4121mpt3sas_base_scsi_enclosure_processor(struct MPT3SAS_ADAPTER *ioc,
4122 Mpi2SepReply_t *mpi_reply, Mpi2SepRequest_t *mpi_request)
4123{
4124 u16 smid;
4125 u32 ioc_state;
eb44552b 4126 bool issue_reset = false;
f92363d1
SR		 4127 int rc;
4128 void *request;
4129 u16 wait_state_count;
4130
4131 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4132 __func__));
4133
4134 mutex_lock(&ioc->base_cmds.mutex);
4135
4136 if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) {
4137 pr_err(MPT3SAS_FMT "%s: base_cmd in use\n",
4138 ioc->name, __func__);
4139 rc = -EAGAIN;
4140 goto out;
4141 }
4142
4143 wait_state_count = 0;
4144 ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
4145 while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) {
4146 if (wait_state_count++ == 10) {
4147 pr_err(MPT3SAS_FMT
4148 "%s: failed due to ioc not operational\n",
4149 ioc->name, __func__);
4150 rc = -EFAULT;
4151 goto out;
4152 }
4153 ssleep(1);
4154 ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
4155 pr_info(MPT3SAS_FMT
4156 "%s: waiting for operational state(count=%d)\n",
4157 ioc->name,
4158 __func__, wait_state_count);
4159 }
4160
4161 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
4162 if (!smid) {
4163 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4164 ioc->name, __func__);
4165 rc = -EAGAIN;
4166 goto out;
4167 }
4168
4169 rc = 0;
4170 ioc->base_cmds.status = MPT3_CMD_PENDING;
4171 request = mpt3sas_base_get_msg_frame(ioc, smid);
4172 ioc->base_cmds.smid = smid;
4173 memcpy(request, mpi_request, sizeof(Mpi2SepReply_t));
4174 init_completion(&ioc->base_cmds.done);
4175 mpt3sas_base_put_smid_default(ioc, smid);
8bbb1cf6 4176 wait_for_completion_timeout(&ioc->base_cmds.done,
f92363d1
SR		 4177 msecs_to_jiffies(10000));
4178 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
4179 pr_err(MPT3SAS_FMT "%s: timeout\n",
4180 ioc->name, __func__);
4181 _debug_dump_mf(mpi_request,
4182 sizeof(Mpi2SepRequest_t)/4);
4183 if (!(ioc->base_cmds.status & MPT3_CMD_RESET))
eb44552b 4184 issue_reset = false;
f92363d1
SR		 4185 goto issue_host_reset;
4186 }
4187 if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID)
4188 memcpy(mpi_reply, ioc->base_cmds.reply,
4189 sizeof(Mpi2SepReply_t));
4190 else
4191 memset(mpi_reply, 0, sizeof(Mpi2SepReply_t));
4192 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4193 goto out;
4194
4195 issue_host_reset:
4196 if (issue_reset)
98c56ad3 4197 mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER);
f92363d1
SR		 4198 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4199 rc = -EFAULT;
4200 out:
4201 mutex_unlock(&ioc->base_cmds.mutex);
4202 return rc;
4203}
4204
4205/**
4206 * _base_get_port_facts - obtain port facts reply and save in ioc
4207 * @ioc: per adapter object
f92363d1
SR		 4208 *
4209 * Returns 0 for success, non-zero for failure.
4210 */
4211static int
98c56ad3 4212_base_get_port_facts(struct MPT3SAS_ADAPTER *ioc, int port)
f92363d1
SR		 4213{
4214 Mpi2PortFactsRequest_t mpi_request;
4215 Mpi2PortFactsReply_t mpi_reply;
4216 struct mpt3sas_port_facts *pfacts;
4217 int mpi_reply_sz, mpi_request_sz, r;
4218
4219 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4220 __func__));
4221
4222 mpi_reply_sz = sizeof(Mpi2PortFactsReply_t);
4223 mpi_request_sz = sizeof(Mpi2PortFactsRequest_t);
4224 memset(&mpi_request, 0, mpi_request_sz);
4225 mpi_request.Function = MPI2_FUNCTION_PORT_FACTS;
4226 mpi_request.PortNumber = port;
4227 r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
98c56ad3 4228 (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5);
f92363d1
SR		 4229
4230 if (r != 0) {
4231 pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
4232 ioc->name, __func__, r);
4233 return r;
4234 }
4235
4236 pfacts = &ioc->pfacts[port];
4237 memset(pfacts, 0, sizeof(struct mpt3sas_port_facts));
4238 pfacts->PortNumber = mpi_reply.PortNumber;
4239 pfacts->VP_ID = mpi_reply.VP_ID;
4240 pfacts->VF_ID = mpi_reply.VF_ID;
4241 pfacts->MaxPostedCmdBuffers =
4242 le16_to_cpu(mpi_reply.MaxPostedCmdBuffers);
4243
4244 return 0;
4245}
4246
4dc8c808
SR		 4247/**
4248 * _base_wait_for_iocstate - Wait until the card is in READY or OPERATIONAL
4249 * @ioc: per adapter object
4250 * @timeout:
4dc8c808
SR		 4251 *
4252 * Returns 0 for success, non-zero for failure.
4253 */
4254static int
98c56ad3 4255_base_wait_for_iocstate(struct MPT3SAS_ADAPTER *ioc, int timeout)
4dc8c808
SR		 4256{
4257 u32 ioc_state;
4258 int rc;
4259
4260 dinitprintk(ioc, printk(MPT3SAS_FMT "%s\n", ioc->name,
4261 __func__));
4262
4263 if (ioc->pci_error_recovery) {
4264 dfailprintk(ioc, printk(MPT3SAS_FMT
4265 "%s: host in pci error recovery\n", ioc->name, __func__));
4266 return -EFAULT;
4267 }
4268
4269 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
4270 dhsprintk(ioc, printk(MPT3SAS_FMT "%s: ioc_state(0x%08x)\n",
4271 ioc->name, __func__, ioc_state));
4272
4273 if (((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY) ||
4274 (ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL)
4275 return 0;
4276
4277 if (ioc_state & MPI2_DOORBELL_USED) {
4278 dhsprintk(ioc, printk(MPT3SAS_FMT
4279 "unexpected doorbell active!\n", ioc->name));
4280 goto issue_diag_reset;
4281 }
4282
4283 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
4284 mpt3sas_base_fault_info(ioc, ioc_state &
4285 MPI2_DOORBELL_DATA_MASK);
4286 goto issue_diag_reset;
4287 }
4288
98c56ad3 4289 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, timeout);
4dc8c808
SR		 4290 if (ioc_state) {
4291 dfailprintk(ioc, printk(MPT3SAS_FMT
4292 "%s: failed going to ready state (ioc_state=0x%x)\n",
4293 ioc->name, __func__, ioc_state));
4294 return -EFAULT;
4295 }
4296
4297 issue_diag_reset:
98c56ad3 4298 rc = _base_diag_reset(ioc);
4dc8c808
SR		 4299 return rc;
4300}
4301
f92363d1
SR		 4302/**
4303 * _base_get_ioc_facts - obtain ioc facts reply and save in ioc
4304 * @ioc: per adapter object
f92363d1
SR		 4305 *
4306 * Returns 0 for success, non-zero for failure.
4307 */
4308static int
98c56ad3 4309_base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc)
f92363d1
SR		 4310{
4311 Mpi2IOCFactsRequest_t mpi_request;
4312 Mpi2IOCFactsReply_t mpi_reply;
4313 struct mpt3sas_facts *facts;
4314 int mpi_reply_sz, mpi_request_sz, r;
4315
4316 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4317 __func__));
4318
98c56ad3 4319 r = _base_wait_for_iocstate(ioc, 10);
4dc8c808
SR		 4320 if (r) {
4321 dfailprintk(ioc, printk(MPT3SAS_FMT
4322 "%s: failed getting to correct state\n",
4323 ioc->name, __func__));
4324 return r;
4325 }
f92363d1
SR		 4326 mpi_reply_sz = sizeof(Mpi2IOCFactsReply_t);
4327 mpi_request_sz = sizeof(Mpi2IOCFactsRequest_t);
4328 memset(&mpi_request, 0, mpi_request_sz);
4329 mpi_request.Function = MPI2_FUNCTION_IOC_FACTS;
4330 r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
98c56ad3 4331 (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5);
f92363d1
SR		 4332
4333 if (r != 0) {
4334 pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
4335 ioc->name, __func__, r);
4336 return r;
4337 }
4338
4339 facts = &ioc->facts;
4340 memset(facts, 0, sizeof(struct mpt3sas_facts));
4341 facts->MsgVersion = le16_to_cpu(mpi_reply.MsgVersion);
4342 facts->HeaderVersion = le16_to_cpu(mpi_reply.HeaderVersion);
4343 facts->VP_ID = mpi_reply.VP_ID;
4344 facts->VF_ID = mpi_reply.VF_ID;
4345 facts->IOCExceptions = le16_to_cpu(mpi_reply.IOCExceptions);
4346 facts->MaxChainDepth = mpi_reply.MaxChainDepth;
4347 facts->WhoInit = mpi_reply.WhoInit;
4348 facts->NumberOfPorts = mpi_reply.NumberOfPorts;
4349 facts->MaxMSIxVectors = mpi_reply.MaxMSIxVectors;
4350 facts->RequestCredit = le16_to_cpu(mpi_reply.RequestCredit);
4351 facts->MaxReplyDescriptorPostQueueDepth =
4352 le16_to_cpu(mpi_reply.MaxReplyDescriptorPostQueueDepth);
4353 facts->ProductID = le16_to_cpu(mpi_reply.ProductID);
4354 facts->IOCCapabilities = le32_to_cpu(mpi_reply.IOCCapabilities);
4355 if ((facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID))
4356 ioc->ir_firmware = 1;
9b05c91a
SR		 4357 if ((facts->IOCCapabilities &
4358 MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE))
4359 ioc->rdpq_array_capable = 1;
f92363d1
SR		 4360 facts->FWVersion.Word = le32_to_cpu(mpi_reply.FWVersion.Word);
4361 facts->IOCRequestFrameSize =
4362 le16_to_cpu(mpi_reply.IOCRequestFrameSize);
ebb3024e
SS		 4363 if (ioc->hba_mpi_version_belonged != MPI2_VERSION) {
4364 facts->IOCMaxChainSegmentSize =
4365 le16_to_cpu(mpi_reply.IOCMaxChainSegmentSize);
4366 }
f92363d1
SR		 4367 facts->MaxInitiators = le16_to_cpu(mpi_reply.MaxInitiators);
4368 facts->MaxTargets = le16_to_cpu(mpi_reply.MaxTargets);
4369 ioc->shost->max_id = -1;
4370 facts->MaxSasExpanders = le16_to_cpu(mpi_reply.MaxSasExpanders);
4371 facts->MaxEnclosures = le16_to_cpu(mpi_reply.MaxEnclosures);
4372 facts->ProtocolFlags = le16_to_cpu(mpi_reply.ProtocolFlags);
4373 facts->HighPriorityCredit =
4374 le16_to_cpu(mpi_reply.HighPriorityCredit);
4375 facts->ReplyFrameSize = mpi_reply.ReplyFrameSize;
4376 facts->MaxDevHandle = le16_to_cpu(mpi_reply.MaxDevHandle);
4377
4378 dinitprintk(ioc, pr_info(MPT3SAS_FMT
4379 "hba queue depth(%d), max chains per io(%d)\n",
4380 ioc->name, facts->RequestCredit,
4381 facts->MaxChainDepth));
4382 dinitprintk(ioc, pr_info(MPT3SAS_FMT
4383 "request frame size(%d), reply frame size(%d)\n", ioc->name,
4384 facts->IOCRequestFrameSize * 4, facts->ReplyFrameSize * 4));
4385 return 0;
4386}
4387
4388/**
4389 * _base_send_ioc_init - send ioc_init to firmware
4390 * @ioc: per adapter object
f92363d1
SR		 4391 *
4392 * Returns 0 for success, non-zero for failure.
4393 */
4394static int
98c56ad3 4395_base_send_ioc_init(struct MPT3SAS_ADAPTER *ioc)
f92363d1
SR		 4396{
4397 Mpi2IOCInitRequest_t mpi_request;
4398 Mpi2IOCInitReply_t mpi_reply;
9b05c91a 4399 int i, r = 0;
23409bd4 4400 ktime_t current_time;
f92363d1 4401 u16 ioc_status;
9b05c91a
SR		 4402 u32 reply_post_free_array_sz = 0;
4403 Mpi2IOCInitRDPQArrayEntry *reply_post_free_array = NULL;
4404 dma_addr_t reply_post_free_array_dma;
f92363d1
SR		 4405
4406 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4407 __func__));
4408
4409 memset(&mpi_request, 0, sizeof(Mpi2IOCInitRequest_t));
4410 mpi_request.Function = MPI2_FUNCTION_IOC_INIT;
4411 mpi_request.WhoInit = MPI2_WHOINIT_HOST_DRIVER;
4412 mpi_request.VF_ID = 0; /* TODO */
4413 mpi_request.VP_ID = 0;
d357e84d 4414 mpi_request.MsgVersion = cpu_to_le16(ioc->hba_mpi_version_belonged);
f92363d1
SR		 4415 mpi_request.HeaderVersion = cpu_to_le16(MPI2_HEADER_VERSION);
4416
4417 if (_base_is_controller_msix_enabled(ioc))
4418 mpi_request.HostMSIxVectors = ioc->reply_queue_count;
4419 mpi_request.SystemRequestFrameSize = cpu_to_le16(ioc->request_sz/4);
4420 mpi_request.ReplyDescriptorPostQueueDepth =
4421 cpu_to_le16(ioc->reply_post_queue_depth);
4422 mpi_request.ReplyFreeQueueDepth =
4423 cpu_to_le16(ioc->reply_free_queue_depth);
4424
4425 mpi_request.SenseBufferAddressHigh =
4426 cpu_to_le32((u64)ioc->sense_dma >> 32);
4427 mpi_request.SystemReplyAddressHigh =
4428 cpu_to_le32((u64)ioc->reply_dma >> 32);
4429 mpi_request.SystemRequestFrameBaseAddress =
4430 cpu_to_le64((u64)ioc->request_dma);
4431 mpi_request.ReplyFreeQueueAddress =
4432 cpu_to_le64((u64)ioc->reply_free_dma);
f92363d1 4433
9b05c91a
SR		 4434 if (ioc->rdpq_array_enable) {
4435 reply_post_free_array_sz = ioc->reply_queue_count *
4436 sizeof(Mpi2IOCInitRDPQArrayEntry);
4437 reply_post_free_array = pci_alloc_consistent(ioc->pdev,
4438 reply_post_free_array_sz, &reply_post_free_array_dma);
4439 if (!reply_post_free_array) {
4440 pr_err(MPT3SAS_FMT
4441 "reply_post_free_array: pci_alloc_consistent failed\n",
4442 ioc->name);
4443 r = -ENOMEM;
4444 goto out;
4445 }
4446 memset(reply_post_free_array, 0, reply_post_free_array_sz);
4447 for (i = 0; i < ioc->reply_queue_count; i++)
4448 reply_post_free_array[i].RDPQBaseAddress =
4449 cpu_to_le64(
4450 (u64)ioc->reply_post[i].reply_post_free_dma);
4451 mpi_request.MsgFlags = MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE;
4452 mpi_request.ReplyDescriptorPostQueueAddress =
4453 cpu_to_le64((u64)reply_post_free_array_dma);
4454 } else {
4455 mpi_request.ReplyDescriptorPostQueueAddress =
4456 cpu_to_le64((u64)ioc->reply_post[0].reply_post_free_dma);
4457 }
f92363d1
SR		 4458
4459 /* This time stamp specifies number of milliseconds
4460 * since epoch ~ midnight January 1, 1970.
4461 */
23409bd4
TR		 4462 current_time = ktime_get_real();
4463 mpi_request.TimeStamp = cpu_to_le64(ktime_to_ms(current_time));
f92363d1
SR		 4464
4465 if (ioc->logging_level & MPT_DEBUG_INIT) {
4466 __le32 *mfp;
4467 int i;
4468
4469 mfp = (__le32 *)&mpi_request;
4470 pr_info("\toffset:data\n");
4471 for (i = 0; i < sizeof(Mpi2IOCInitRequest_t)/4; i++)
4472 pr_info("\t[0x%02x]:%08x\n", i*4,
4473 le32_to_cpu(mfp[i]));
4474 }
4475
4476 r = _base_handshake_req_reply_wait(ioc,
4477 sizeof(Mpi2IOCInitRequest_t), (u32 *)&mpi_request,
98c56ad3 4478 sizeof(Mpi2IOCInitReply_t), (u16 *)&mpi_reply, 10);
f92363d1
SR		 4479
4480 if (r != 0) {
4481 pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
4482 ioc->name, __func__, r);
9b05c91a 4483 goto out;
f92363d1
SR		 4484 }
4485
4486 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & MPI2_IOCSTATUS_MASK;
4487 if (ioc_status != MPI2_IOCSTATUS_SUCCESS ||
4488 mpi_reply.IOCLogInfo) {
4489 pr_err(MPT3SAS_FMT "%s: failed\n", ioc->name, __func__);
4490 r = -EIO;
4491 }
4492
9b05c91a
SR		 4493out:
4494 if (reply_post_free_array)
4495 pci_free_consistent(ioc->pdev, reply_post_free_array_sz,
4496 reply_post_free_array,
4497 reply_post_free_array_dma);
4498 return r;
f92363d1
SR		 4499}
4500
4501/**
4502 * mpt3sas_port_enable_done - command completion routine for port enable
4503 * @ioc: per adapter object
4504 * @smid: system request message index
4505 * @msix_index: MSIX table index supplied by the OS
4506 * @reply: reply message frame(lower 32bit addr)
4507 *
4508 * Return 1 meaning mf should be freed from _base_interrupt
4509 * 0 means the mf is freed from this function.
4510 */
4511u8
4512mpt3sas_port_enable_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
4513 u32 reply)
4514{
4515 MPI2DefaultReply_t *mpi_reply;
4516 u16 ioc_status;
4517
4518 if (ioc->port_enable_cmds.status == MPT3_CMD_NOT_USED)
4519 return 1;
4520
4521 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
4522 if (!mpi_reply)
4523 return 1;
4524
4525 if (mpi_reply->Function != MPI2_FUNCTION_PORT_ENABLE)
4526 return 1;
4527
4528 ioc->port_enable_cmds.status &= ~MPT3_CMD_PENDING;
4529 ioc->port_enable_cmds.status |= MPT3_CMD_COMPLETE;
4530 ioc->port_enable_cmds.status |= MPT3_CMD_REPLY_VALID;
4531 memcpy(ioc->port_enable_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
4532 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK;
4533 if (ioc_status != MPI2_IOCSTATUS_SUCCESS)
4534 ioc->port_enable_failed = 1;
4535
4536 if (ioc->is_driver_loading) {
4537 if (ioc_status == MPI2_IOCSTATUS_SUCCESS) {
4538 mpt3sas_port_enable_complete(ioc);
4539 return 1;
4540 } else {
4541 ioc->start_scan_failed = ioc_status;
4542 ioc->start_scan = 0;
4543 return 1;
4544 }
4545 }
4546 complete(&ioc->port_enable_cmds.done);
4547 return 1;
4548}
4549
4550/**
4551 * _base_send_port_enable - send port_enable(discovery stuff) to firmware
4552 * @ioc: per adapter object
f92363d1
SR		 4553 *
4554 * Returns 0 for success, non-zero for failure.
4555 */
4556static int
98c56ad3 4557_base_send_port_enable(struct MPT3SAS_ADAPTER *ioc)
f92363d1
SR		 4558{
4559 Mpi2PortEnableRequest_t *mpi_request;
4560 Mpi2PortEnableReply_t *mpi_reply;
f92363d1
SR		 4561 int r = 0;
4562 u16 smid;
4563 u16 ioc_status;
4564
4565 pr_info(MPT3SAS_FMT "sending port enable !!\n", ioc->name);
4566
4567 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
4568 pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
4569 ioc->name, __func__);
4570 return -EAGAIN;
4571 }
4572
4573 smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
4574 if (!smid) {
4575 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4576 ioc->name, __func__);
4577 return -EAGAIN;
4578 }
4579
4580 ioc->port_enable_cmds.status = MPT3_CMD_PENDING;
4581 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
4582 ioc->port_enable_cmds.smid = smid;
4583 memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
4584 mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
4585
4586 init_completion(&ioc->port_enable_cmds.done);
4587 mpt3sas_base_put_smid_default(ioc, smid);
8bbb1cf6 4588 wait_for_completion_timeout(&ioc->port_enable_cmds.done, 300*HZ);
f92363d1
SR		 4589 if (!(ioc->port_enable_cmds.status & MPT3_CMD_COMPLETE)) {
4590 pr_err(MPT3SAS_FMT "%s: timeout\n",
4591 ioc->name, __func__);
4592 _debug_dump_mf(mpi_request,
4593 sizeof(Mpi2PortEnableRequest_t)/4);
4594 if (ioc->port_enable_cmds.status & MPT3_CMD_RESET)
4595 r = -EFAULT;
4596 else
4597 r = -ETIME;
4598 goto out;
4599 }
4600
4601 mpi_reply = ioc->port_enable_cmds.reply;
4602 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK;
4603 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
4604 pr_err(MPT3SAS_FMT "%s: failed with (ioc_status=0x%08x)\n",
4605 ioc->name, __func__, ioc_status);
4606 r = -EFAULT;
4607 goto out;
4608 }
4609
4610 out:
4611 ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED;
4612 pr_info(MPT3SAS_FMT "port enable: %s\n", ioc->name, ((r == 0) ?
4613 "SUCCESS" : "FAILED"));
4614 return r;
4615}
4616
4617/**
4618 * mpt3sas_port_enable - initiate firmware discovery (don't wait for reply)
4619 * @ioc: per adapter object
4620 *
4621 * Returns 0 for success, non-zero for failure.
4622 */
4623int
4624mpt3sas_port_enable(struct MPT3SAS_ADAPTER *ioc)
4625{
4626 Mpi2PortEnableRequest_t *mpi_request;
4627 u16 smid;
4628
4629 pr_info(MPT3SAS_FMT "sending port enable !!\n", ioc->name);
4630
4631 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
4632 pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
4633 ioc->name, __func__);
4634 return -EAGAIN;
4635 }
4636
4637 smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
4638 if (!smid) {
4639 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4640 ioc->name, __func__);
4641 return -EAGAIN;
4642 }
4643
4644 ioc->port_enable_cmds.status = MPT3_CMD_PENDING;
4645 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
4646 ioc->port_enable_cmds.smid = smid;
4647 memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
4648 mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
4649
4650 mpt3sas_base_put_smid_default(ioc, smid);
4651 return 0;
4652}
4653
4654/**
4655 * _base_determine_wait_on_discovery - desposition
4656 * @ioc: per adapter object
4657 *
4658 * Decide whether to wait on discovery to complete. Used to either
4659 * locate boot device, or report volumes ahead of physical devices.
4660 *
4661 * Returns 1 for wait, 0 for don't wait
4662 */
4663static int
4664_base_determine_wait_on_discovery(struct MPT3SAS_ADAPTER *ioc)
4665{
4666 /* We wait for discovery to complete if IR firmware is loaded.
4667 * The sas topology events arrive before PD events, so we need time to
4668 * turn on the bit in ioc->pd_handles to indicate PD
4669 * Also, it maybe required to report Volumes ahead of physical
4670 * devices when MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING is set.
4671 */
4672 if (ioc->ir_firmware)
4673 return 1;
4674
4675 /* if no Bios, then we don't need to wait */
4676 if (!ioc->bios_pg3.BiosVersion)
4677 return 0;
4678
4679 /* Bios is present, then we drop down here.
4680 *
4681 * If there any entries in the Bios Page 2, then we wait
4682 * for discovery to complete.
4683 */
4684
4685 /* Current Boot Device */
4686 if ((ioc->bios_pg2.CurrentBootDeviceForm &
4687 MPI2_BIOSPAGE2_FORM_MASK) ==
4688 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED &&
4689 /* Request Boot Device */
4690 (ioc->bios_pg2.ReqBootDeviceForm &
4691 MPI2_BIOSPAGE2_FORM_MASK) ==
4692 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED &&
4693 /* Alternate Request Boot Device */
4694 (ioc->bios_pg2.ReqAltBootDeviceForm &
4695 MPI2_BIOSPAGE2_FORM_MASK) ==
4696 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED)
4697 return 0;
4698
4699 return 1;
4700}
4701
4702/**
4703 * _base_unmask_events - turn on notification for this event
4704 * @ioc: per adapter object
4705 * @event: firmware event
4706 *
4707 * The mask is stored in ioc->event_masks.
4708 */
4709static void
4710_base_unmask_events(struct MPT3SAS_ADAPTER *ioc, u16 event)
4711{
4712 u32 desired_event;
4713
4714 if (event >= 128)
4715 return;
4716
4717 desired_event = (1 << (event % 32));
4718
4719 if (event < 32)
4720 ioc->event_masks[0] &= ~desired_event;
4721 else if (event < 64)
4722 ioc->event_masks[1] &= ~desired_event;
4723 else if (event < 96)
4724 ioc->event_masks[2] &= ~desired_event;
4725 else if (event < 128)
4726 ioc->event_masks[3] &= ~desired_event;
4727}
4728
4729/**
4730 * _base_event_notification - send event notification
4731 * @ioc: per adapter object
f92363d1
SR		 4732 *
4733 * Returns 0 for success, non-zero for failure.
4734 */
4735static int
98c56ad3 4736_base_event_notification(struct MPT3SAS_ADAPTER *ioc)
f92363d1
SR		 4737{
4738 Mpi2EventNotificationRequest_t *mpi_request;
f92363d1
SR		 4739 u16 smid;
4740 int r = 0;
4741 int i;
4742
4743 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4744 __func__));
4745
4746 if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
4747 pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
4748 ioc->name, __func__);
4749 return -EAGAIN;
4750 }
4751
4752 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
4753 if (!smid) {
4754 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4755 ioc->name, __func__);
4756 return -EAGAIN;
4757 }
4758 ioc->base_cmds.status = MPT3_CMD_PENDING;
4759 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
4760 ioc->base_cmds.smid = smid;
4761 memset(mpi_request, 0, sizeof(Mpi2EventNotificationRequest_t));
4762 mpi_request->Function = MPI2_FUNCTION_EVENT_NOTIFICATION;
4763 mpi_request->VF_ID = 0; /* TODO */
4764 mpi_request->VP_ID = 0;
4765 for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
4766 mpi_request->EventMasks[i] =
4767 cpu_to_le32(ioc->event_masks[i]);
4768 init_completion(&ioc->base_cmds.done);
4769 mpt3sas_base_put_smid_default(ioc, smid);
8bbb1cf6 4770 wait_for_completion_timeout(&ioc->base_cmds.done, 30*HZ);
f92363d1
SR		 4771 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
4772 pr_err(MPT3SAS_FMT "%s: timeout\n",
4773 ioc->name, __func__);
4774 _debug_dump_mf(mpi_request,
4775 sizeof(Mpi2EventNotificationRequest_t)/4);
4776 if (ioc->base_cmds.status & MPT3_CMD_RESET)
4777 r = -EFAULT;
4778 else
4779 r = -ETIME;
4780 } else
4781 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s: complete\n",
4782 ioc->name, __func__));
4783 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4784 return r;
4785}
4786
4787/**
4788 * mpt3sas_base_validate_event_type - validating event types
4789 * @ioc: per adapter object
4790 * @event: firmware event
4791 *
4792 * This will turn on firmware event notification when application
4793 * ask for that event. We don't mask events that are already enabled.
4794 */
4795void
4796mpt3sas_base_validate_event_type(struct MPT3SAS_ADAPTER *ioc, u32 *event_type)
4797{
4798 int i, j;
4799 u32 event_mask, desired_event;
4800 u8 send_update_to_fw;
4801
4802 for (i = 0, send_update_to_fw = 0; i <
4803 MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) {
4804 event_mask = ~event_type[i];
4805 desired_event = 1;
4806 for (j = 0; j < 32; j++) {
4807 if (!(event_mask & desired_event) &&
4808 (ioc->event_masks[i] & desired_event)) {
4809 ioc->event_masks[i] &= ~desired_event;
4810 send_update_to_fw = 1;
4811 }
4812 desired_event = (desired_event << 1);
4813 }
4814 }
4815
4816 if (!send_update_to_fw)
4817 return;
4818
4819 mutex_lock(&ioc->base_cmds.mutex);
98c56ad3 4820 _base_event_notification(ioc);
f92363d1
SR		 4821 mutex_unlock(&ioc->base_cmds.mutex);
4822}
4823
4824/**
4825 * _base_diag_reset - the "big hammer" start of day reset
4826 * @ioc: per adapter object
f92363d1
SR		 4827 *
4828 * Returns 0 for success, non-zero for failure.
4829 */
4830static int
98c56ad3 4831_base_diag_reset(struct MPT3SAS_ADAPTER *ioc)
f92363d1
SR		 4832{
4833 u32 host_diagnostic;
4834 u32 ioc_state;
4835 u32 count;
4836 u32 hcb_size;
4837
4838 pr_info(MPT3SAS_FMT "sending diag reset !!\n", ioc->name);
4839
4840 drsprintk(ioc, pr_info(MPT3SAS_FMT "clear interrupts\n",
4841 ioc->name));
4842
4843 count = 0;
4844 do {
4845 /* Write magic sequence to WriteSequence register
4846 * Loop until in diagnostic mode
4847 */
4848 drsprintk(ioc, pr_info(MPT3SAS_FMT
4849 "write magic sequence\n", ioc->name));
4850 writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
4851 writel(MPI2_WRSEQ_1ST_KEY_VALUE, &ioc->chip->WriteSequence);
4852 writel(MPI2_WRSEQ_2ND_KEY_VALUE, &ioc->chip->WriteSequence);
4853 writel(MPI2_WRSEQ_3RD_KEY_VALUE, &ioc->chip->WriteSequence);
4854 writel(MPI2_WRSEQ_4TH_KEY_VALUE, &ioc->chip->WriteSequence);
4855 writel(MPI2_WRSEQ_5TH_KEY_VALUE, &ioc->chip->WriteSequence);
4856 writel(MPI2_WRSEQ_6TH_KEY_VALUE, &ioc->chip->WriteSequence);
4857
4858 /* wait 100 msec */
98c56ad3 4859 msleep(100);
f92363d1
SR		 4860
4861 if (count++ > 20)
4862 goto out;
4863
4864 host_diagnostic = readl(&ioc->chip->HostDiagnostic);
4865 drsprintk(ioc, pr_info(MPT3SAS_FMT
4866 "wrote magic sequence: count(%d), host_diagnostic(0x%08x)\n",
4867 ioc->name, count, host_diagnostic));
4868
4869 } while ((host_diagnostic & MPI2_DIAG_DIAG_WRITE_ENABLE) == 0);
4870
4871 hcb_size = readl(&ioc->chip->HCBSize);
4872
4873 drsprintk(ioc, pr_info(MPT3SAS_FMT "diag reset: issued\n",
4874 ioc->name));
4875 writel(host_diagnostic | MPI2_DIAG_RESET_ADAPTER,
4876 &ioc->chip->HostDiagnostic);
4877
b453ff84 4878 /*This delay allows the chip PCIe hardware time to finish reset tasks*/
98c56ad3 4879 msleep(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000);
f92363d1 4880
b453ff84
SR		 4881 /* Approximately 300 second max wait */
4882 for (count = 0; count < (300000000 /
4883 MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC); count++) {
f92363d1
SR		 4884
4885 host_diagnostic = readl(&ioc->chip->HostDiagnostic);
4886
4887 if (host_diagnostic == 0xFFFFFFFF)
4888 goto out;
4889 if (!(host_diagnostic & MPI2_DIAG_RESET_ADAPTER))
4890 break;
4891
98c56ad3 4892 msleep(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC / 1000);
f92363d1
SR		 4893 }
4894
4895 if (host_diagnostic & MPI2_DIAG_HCB_MODE) {
4896
4897 drsprintk(ioc, pr_info(MPT3SAS_FMT
4898 "restart the adapter assuming the HCB Address points to good F/W\n",
4899 ioc->name));
4900 host_diagnostic &= ~MPI2_DIAG_BOOT_DEVICE_SELECT_MASK;
4901 host_diagnostic |= MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW;
4902 writel(host_diagnostic, &ioc->chip->HostDiagnostic);
4903
4904 drsprintk(ioc, pr_info(MPT3SAS_FMT
4905 "re-enable the HCDW\n", ioc->name));
4906 writel(hcb_size | MPI2_HCB_SIZE_HCB_ENABLE,
4907 &ioc->chip->HCBSize);
4908 }
4909
4910 drsprintk(ioc, pr_info(MPT3SAS_FMT "restart the adapter\n",
4911 ioc->name));
4912 writel(host_diagnostic & ~MPI2_DIAG_HOLD_IOC_RESET,
4913 &ioc->chip->HostDiagnostic);
4914
4915 drsprintk(ioc, pr_info(MPT3SAS_FMT
4916 "disable writes to the diagnostic register\n", ioc->name));
4917 writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
4918
4919 drsprintk(ioc, pr_info(MPT3SAS_FMT
4920 "Wait for FW to go to the READY state\n", ioc->name));
98c56ad3 4921 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, 20);
f92363d1
SR		 4922 if (ioc_state) {
4923 pr_err(MPT3SAS_FMT
4924 "%s: failed going to ready state (ioc_state=0x%x)\n",
4925 ioc->name, __func__, ioc_state);
4926 goto out;
4927 }
4928
4929 pr_info(MPT3SAS_FMT "diag reset: SUCCESS\n", ioc->name);
4930 return 0;
4931
4932 out:
4933 pr_err(MPT3SAS_FMT "diag reset: FAILED\n", ioc->name);
4934 return -EFAULT;
4935}
4936
4937/**
4938 * _base_make_ioc_ready - put controller in READY state
4939 * @ioc: per adapter object
f92363d1
SR		 4940 * @type: FORCE_BIG_HAMMER or SOFT_RESET
4941 *
4942 * Returns 0 for success, non-zero for failure.
4943 */
4944static int
98c56ad3 4945_base_make_ioc_ready(struct MPT3SAS_ADAPTER *ioc, enum reset_type type)
f92363d1
SR		 4946{
4947 u32 ioc_state;
4948 int rc;
4949 int count;
4950
4951 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4952 __func__));
4953
4954 if (ioc->pci_error_recovery)
4955 return 0;
4956
4957 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
4958 dhsprintk(ioc, pr_info(MPT3SAS_FMT "%s: ioc_state(0x%08x)\n",
4959 ioc->name, __func__, ioc_state));
4960
4961 /* if in RESET state, it should move to READY state shortly */
4962 count = 0;
4963 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_RESET) {
4964 while ((ioc_state & MPI2_IOC_STATE_MASK) !=
4965 MPI2_IOC_STATE_READY) {
4966 if (count++ == 10) {
4967 pr_err(MPT3SAS_FMT
4968 "%s: failed going to ready state (ioc_state=0x%x)\n",
4969 ioc->name, __func__, ioc_state);
4970 return -EFAULT;
4971 }
98c56ad3 4972 ssleep(1);
f92363d1
SR		 4973 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
4974 }
4975 }
4976
4977 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY)
4978 return 0;
4979
4980 if (ioc_state & MPI2_DOORBELL_USED) {
4981 dhsprintk(ioc, pr_info(MPT3SAS_FMT
4982 "unexpected doorbell active!\n",
4983 ioc->name));
4984 goto issue_diag_reset;
4985 }
4986
4987 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
4988 mpt3sas_base_fault_info(ioc, ioc_state &
4989 MPI2_DOORBELL_DATA_MASK);
4990 goto issue_diag_reset;
4991 }
4992
4993 if (type == FORCE_BIG_HAMMER)
4994 goto issue_diag_reset;
4995
4996 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL)
4997 if (!(_base_send_ioc_reset(ioc,
98c56ad3 4998 MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET, 15))) {
f92363d1
SR		 4999 return 0;
5000 }
5001
5002 issue_diag_reset:
98c56ad3 5003 rc = _base_diag_reset(ioc);
f92363d1
SR		 5004 return rc;
5005}
5006
5007/**
5008 * _base_make_ioc_operational - put controller in OPERATIONAL state
5009 * @ioc: per adapter object
f92363d1
SR		 5010 *
5011 * Returns 0 for success, non-zero for failure.
5012 */
5013static int
98c56ad3 5014_base_make_ioc_operational(struct MPT3SAS_ADAPTER *ioc)
f92363d1 5015{
5ec8a175 5016 int r, i, index;
f92363d1
SR		 5017 unsigned long flags;
5018 u32 reply_address;
5019 u16 smid;
5020 struct _tr_list *delayed_tr, *delayed_tr_next;
fd0331b3
SS		 5021 struct _sc_list *delayed_sc, *delayed_sc_next;
5022 struct _event_ack_list *delayed_event_ack, *delayed_event_ack_next;
7786ab6a 5023 u8 hide_flag;
f92363d1 5024 struct adapter_reply_queue *reply_q;
5ec8a175 5025 Mpi2ReplyDescriptorsUnion_t *reply_post_free_contig;
f92363d1
SR		 5026
5027 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
5028 __func__));
5029
5030 /* clean the delayed target reset list */
5031 list_for_each_entry_safe(delayed_tr, delayed_tr_next,
5032 &ioc->delayed_tr_list, list) {
5033 list_del(&delayed_tr->list);
5034 kfree(delayed_tr);
5035 }
5036
5037
5038 list_for_each_entry_safe(delayed_tr, delayed_tr_next,
5039 &ioc->delayed_tr_volume_list, list) {
5040 list_del(&delayed_tr->list);
5041 kfree(delayed_tr);
5042 }
5043
fd0331b3
SS		 5044 list_for_each_entry_safe(delayed_sc, delayed_sc_next,
5045 &ioc->delayed_sc_list, list) {
5046 list_del(&delayed_sc->list);
5047 kfree(delayed_sc);
5048 }
5049
5050 list_for_each_entry_safe(delayed_event_ack, delayed_event_ack_next,
5051 &ioc->delayed_event_ack_list, list) {
5052 list_del(&delayed_event_ack->list);
5053 kfree(delayed_event_ack);
5054 }
5055
f92363d1
SR		 5056 /* initialize the scsi lookup free list */
5057 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
5058 INIT_LIST_HEAD(&ioc->free_list);
5059 smid = 1;
5060 for (i = 0; i < ioc->scsiio_depth; i++, smid++) {
5061 INIT_LIST_HEAD(&ioc->scsi_lookup[i].chain_list);
5062 ioc->scsi_lookup[i].cb_idx = 0xFF;
5063 ioc->scsi_lookup[i].smid = smid;
5064 ioc->scsi_lookup[i].scmd = NULL;
7786ab6a 5065 ioc->scsi_lookup[i].direct_io = 0;
f92363d1
SR		 5066 list_add_tail(&ioc->scsi_lookup[i].tracker_list,
5067 &ioc->free_list);
5068 }
5069
5070 /* hi-priority queue */
5071 INIT_LIST_HEAD(&ioc->hpr_free_list);
5072 smid = ioc->hi_priority_smid;
5073 for (i = 0; i < ioc->hi_priority_depth; i++, smid++) {
5074 ioc->hpr_lookup[i].cb_idx = 0xFF;
5075 ioc->hpr_lookup[i].smid = smid;
5076 list_add_tail(&ioc->hpr_lookup[i].tracker_list,
5077 &ioc->hpr_free_list);
5078 }
5079
5080 /* internal queue */
5081 INIT_LIST_HEAD(&ioc->internal_free_list);
5082 smid = ioc->internal_smid;
5083 for (i = 0; i < ioc->internal_depth; i++, smid++) {
5084 ioc->internal_lookup[i].cb_idx = 0xFF;
5085 ioc->internal_lookup[i].smid = smid;
5086 list_add_tail(&ioc->internal_lookup[i].tracker_list,
5087 &ioc->internal_free_list);
5088 }
5089
5090 /* chain pool */
5091 INIT_LIST_HEAD(&ioc->free_chain_list);
5092 for (i = 0; i < ioc->chain_depth; i++)
5093 list_add_tail(&ioc->chain_lookup[i].tracker_list,
5094 &ioc->free_chain_list);
5095
5096 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
5097
5098 /* initialize Reply Free Queue */
5099 for (i = 0, reply_address = (u32)ioc->reply_dma ;
5100 i < ioc->reply_free_queue_depth ; i++, reply_address +=
5101 ioc->reply_sz)
5102 ioc->reply_free[i] = cpu_to_le32(reply_address);
5103
5104 /* initialize reply queues */
5105 if (ioc->is_driver_loading)
5106 _base_assign_reply_queues(ioc);
5107
5108 /* initialize Reply Post Free Queue */
5ec8a175
CO		 5109 index = 0;
5110 reply_post_free_contig = ioc->reply_post[0].reply_post_free;
f92363d1 5111 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
5ec8a175
CO		 5112 /*
5113 * If RDPQ is enabled, switch to the next allocation.
5114 * Otherwise advance within the contiguous region.
5115 */
5116 if (ioc->rdpq_array_enable) {
5117 reply_q->reply_post_free =
5118 ioc->reply_post[index++].reply_post_free;
5119 } else {
5120 reply_q->reply_post_free = reply_post_free_contig;
5121 reply_post_free_contig += ioc->reply_post_queue_depth;
5122 }
5123
f92363d1 5124 reply_q->reply_post_host_index = 0;
f92363d1
SR		 5125 for (i = 0; i < ioc->reply_post_queue_depth; i++)
5126 reply_q->reply_post_free[i].Words =
5127 cpu_to_le64(ULLONG_MAX);
5128 if (!_base_is_controller_msix_enabled(ioc))
5129 goto skip_init_reply_post_free_queue;
f92363d1
SR		 5130 }
5131 skip_init_reply_post_free_queue:
5132
98c56ad3 5133 r = _base_send_ioc_init(ioc);
f92363d1
SR		 5134 if (r)
5135 return r;
5136
5137 /* initialize reply free host index */
5138 ioc->reply_free_host_index = ioc->reply_free_queue_depth - 1;
5139 writel(ioc->reply_free_host_index, &ioc->chip->ReplyFreeHostIndex);
5140
5141 /* initialize reply post host index */
5142 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
0bb337c9 5143 if (ioc->combined_reply_queue)
fb77bb53
SR		 5144 writel((reply_q->msix_index & 7)<<
5145 MPI2_RPHI_MSIX_INDEX_SHIFT,
5146 ioc->replyPostRegisterIndex[reply_q->msix_index/8]);
5147 else
5148 writel(reply_q->msix_index <<
5149 MPI2_RPHI_MSIX_INDEX_SHIFT,
5150 &ioc->chip->ReplyPostHostIndex);
5151
f92363d1
SR		 5152 if (!_base_is_controller_msix_enabled(ioc))
5153 goto skip_init_reply_post_host_index;
5154 }
5155
5156 skip_init_reply_post_host_index:
5157
5158 _base_unmask_interrupts(ioc);
98c56ad3 5159 r = _base_event_notification(ioc);
f92363d1
SR		 5160 if (r)
5161 return r;
5162
98c56ad3 5163 _base_static_config_pages(ioc);
f92363d1
SR		 5164
5165 if (ioc->is_driver_loading) {
7786ab6a
SR		 5166
5167 if (ioc->is_warpdrive && ioc->manu_pg10.OEMIdentifier
5168 == 0x80) {
5169 hide_flag = (u8) (
5170 le32_to_cpu(ioc->manu_pg10.OEMSpecificFlags0) &
5171 MFG_PAGE10_HIDE_SSDS_MASK);
5172 if (hide_flag != MFG_PAGE10_HIDE_SSDS_MASK)
5173 ioc->mfg_pg10_hide_flag = hide_flag;
5174 }
5175
f92363d1
SR		 5176 ioc->wait_for_discovery_to_complete =
5177 _base_determine_wait_on_discovery(ioc);
5178
5179 return r; /* scan_start and scan_finished support */
5180 }
5181
98c56ad3 5182 r = _base_send_port_enable(ioc);
f92363d1
SR		 5183 if (r)
5184 return r;
5185
5186 return r;
5187}
5188
5189/**
5190 * mpt3sas_base_free_resources - free resources controller resources
5191 * @ioc: per adapter object
5192 *
5193 * Return nothing.
5194 */
5195void
5196mpt3sas_base_free_resources(struct MPT3SAS_ADAPTER *ioc)
5197{
f92363d1
SR		 5198 dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
5199 __func__));
5200
08c4d550
SR		 5201 /* synchronizing freeing resource with pci_access_mutex lock */
5202 mutex_lock(&ioc->pci_access_mutex);
cf9bd21a
JL		 5203 if (ioc->chip_phys && ioc->chip) {
5204 _base_mask_interrupts(ioc);
5205 ioc->shost_recovery = 1;
98c56ad3 5206 _base_make_ioc_ready(ioc, SOFT_RESET);
cf9bd21a
JL		 5207 ioc->shost_recovery = 0;
5208 }
5209
580d4e31 5210 mpt3sas_base_unmap_resources(ioc);
08c4d550 5211 mutex_unlock(&ioc->pci_access_mutex);
f92363d1
SR		 5212 return;
5213}
5214
5215/**
5216 * mpt3sas_base_attach - attach controller instance
5217 * @ioc: per adapter object
5218 *
5219 * Returns 0 for success, non-zero for failure.
5220 */
5221int
5222mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc)
5223{
5224 int r, i;
5225 int cpu_id, last_cpu_id = 0;
5226
5227 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
5228 __func__));
5229
5230 /* setup cpu_msix_table */
5231 ioc->cpu_count = num_online_cpus();
5232 for_each_online_cpu(cpu_id)
5233 last_cpu_id = cpu_id;
5234 ioc->cpu_msix_table_sz = last_cpu_id + 1;
5235 ioc->cpu_msix_table = kzalloc(ioc->cpu_msix_table_sz, GFP_KERNEL);
5236 ioc->reply_queue_count = 1;
5237 if (!ioc->cpu_msix_table) {
5238 dfailprintk(ioc, pr_info(MPT3SAS_FMT
5239 "allocation for cpu_msix_table failed!!!\n",
5240 ioc->name));
5241 r = -ENOMEM;
5242 goto out_free_resources;
5243 }
5244
7786ab6a
SR		 5245 if (ioc->is_warpdrive) {
5246 ioc->reply_post_host_index = kcalloc(ioc->cpu_msix_table_sz,
5247 sizeof(resource_size_t *), GFP_KERNEL);
5248 if (!ioc->reply_post_host_index) {
5249 dfailprintk(ioc, pr_info(MPT3SAS_FMT "allocation "
5250 "for cpu_msix_table failed!!!\n", ioc->name));
5251 r = -ENOMEM;
5252 goto out_free_resources;
5253 }
5254 }
5255
9b05c91a
SR		 5256 ioc->rdpq_array_enable_assigned = 0;
5257 ioc->dma_mask = 0;
f92363d1
SR		 5258 r = mpt3sas_base_map_resources(ioc);
5259 if (r)
5260 goto out_free_resources;
5261
f92363d1 5262 pci_set_drvdata(ioc->pdev, ioc->shost);
98c56ad3 5263 r = _base_get_ioc_facts(ioc);
f92363d1
SR		 5264 if (r)
5265 goto out_free_resources;
5266
471ef9d4
SR		 5267 switch (ioc->hba_mpi_version_belonged) {
5268 case MPI2_VERSION:
5269 ioc->build_sg_scmd = &_base_build_sg_scmd;
5270 ioc->build_sg = &_base_build_sg;
5271 ioc->build_zero_len_sge = &_base_build_zero_len_sge;
5272 break;
5273 case MPI25_VERSION:
b130b0d5 5274 case MPI26_VERSION:
471ef9d4
SR		 5275 /*
5276 * In SAS3.0,
5277 * SCSI_IO, SMP_PASSTHRU, SATA_PASSTHRU, Target Assist, and
5278 * Target Status - all require the IEEE formated scatter gather
5279 * elements.
5280 */
5281 ioc->build_sg_scmd = &_base_build_sg_scmd_ieee;
5282 ioc->build_sg = &_base_build_sg_ieee;
5283 ioc->build_zero_len_sge = &_base_build_zero_len_sge_ieee;
5284 ioc->sge_size_ieee = sizeof(Mpi2IeeeSgeSimple64_t);
5285 break;
5286 }
f92363d1
SR		 5287
5288 /*
5289 * These function pointers for other requests that don't
5290 * the require IEEE scatter gather elements.
5291 *
5292 * For example Configuration Pages and SAS IOUNIT Control don't.
5293 */
5294 ioc->build_sg_mpi = &_base_build_sg;
5295 ioc->build_zero_len_sge_mpi = &_base_build_zero_len_sge;
5296
98c56ad3 5297 r = _base_make_ioc_ready(ioc, SOFT_RESET);
f92363d1
SR		 5298 if (r)
5299 goto out_free_resources;
5300
5301 ioc->pfacts = kcalloc(ioc->facts.NumberOfPorts,
5302 sizeof(struct mpt3sas_port_facts), GFP_KERNEL);
5303 if (!ioc->pfacts) {
5304 r = -ENOMEM;
5305 goto out_free_resources;
5306 }
5307
5308 for (i = 0 ; i < ioc->facts.NumberOfPorts; i++) {
98c56ad3 5309 r = _base_get_port_facts(ioc, i);
f92363d1
SR		 5310 if (r)
5311 goto out_free_resources;
5312 }
5313
98c56ad3 5314 r = _base_allocate_memory_pools(ioc);
f92363d1
SR		 5315 if (r)
5316 goto out_free_resources;
5317
5318 init_waitqueue_head(&ioc->reset_wq);
5319
5320 /* allocate memory pd handle bitmask list */
5321 ioc->pd_handles_sz = (ioc->facts.MaxDevHandle / 8);
5322 if (ioc->facts.MaxDevHandle % 8)
5323 ioc->pd_handles_sz++;
5324 ioc->pd_handles = kzalloc(ioc->pd_handles_sz,
5325 GFP_KERNEL);
5326 if (!ioc->pd_handles) {
5327 r = -ENOMEM;
5328 goto out_free_resources;
5329 }
5330 ioc->blocking_handles = kzalloc(ioc->pd_handles_sz,
5331 GFP_KERNEL);
5332 if (!ioc->blocking_handles) {
5333 r = -ENOMEM;
5334 goto out_free_resources;
5335 }
5336
c696f7b8
SPS		 5337 /* allocate memory for pending OS device add list */
5338 ioc->pend_os_device_add_sz = (ioc->facts.MaxDevHandle / 8);
5339 if (ioc->facts.MaxDevHandle % 8)
5340 ioc->pend_os_device_add_sz++;
5341 ioc->pend_os_device_add = kzalloc(ioc->pend_os_device_add_sz,
5342 GFP_KERNEL);
5343 if (!ioc->pend_os_device_add)
5344 goto out_free_resources;
5345
5346 ioc->device_remove_in_progress_sz = ioc->pend_os_device_add_sz;
5347 ioc->device_remove_in_progress =
5348 kzalloc(ioc->device_remove_in_progress_sz, GFP_KERNEL);
5349 if (!ioc->device_remove_in_progress)
5350 goto out_free_resources;
5351
f92363d1
SR		 5352 ioc->fwfault_debug = mpt3sas_fwfault_debug;
5353
5354 /* base internal command bits */
5355 mutex_init(&ioc->base_cmds.mutex);
5356 ioc->base_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5357 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
5358
5359 /* port_enable command bits */
5360 ioc->port_enable_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5361 ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED;
5362
5363 /* transport internal command bits */
5364 ioc->transport_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5365 ioc->transport_cmds.status = MPT3_CMD_NOT_USED;
5366 mutex_init(&ioc->transport_cmds.mutex);
5367
5368 /* scsih internal command bits */
5369 ioc->scsih_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5370 ioc->scsih_cmds.status = MPT3_CMD_NOT_USED;
5371 mutex_init(&ioc->scsih_cmds.mutex);
5372
5373 /* task management internal command bits */
5374 ioc->tm_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5375 ioc->tm_cmds.status = MPT3_CMD_NOT_USED;
5376 mutex_init(&ioc->tm_cmds.mutex);
5377
5378 /* config page internal command bits */
5379 ioc->config_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5380 ioc->config_cmds.status = MPT3_CMD_NOT_USED;
5381 mutex_init(&ioc->config_cmds.mutex);
5382
5383 /* ctl module internal command bits */
5384 ioc->ctl_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5385 ioc->ctl_cmds.sense = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL);
5386 ioc->ctl_cmds.status = MPT3_CMD_NOT_USED;
5387 mutex_init(&ioc->ctl_cmds.mutex);
5388
5389 if (!ioc->base_cmds.reply || !ioc->transport_cmds.reply ||
5390 !ioc->scsih_cmds.reply || !ioc->tm_cmds.reply ||
5391 !ioc->config_cmds.reply || !ioc->ctl_cmds.reply ||
5392 !ioc->ctl_cmds.sense) {
5393 r = -ENOMEM;
5394 goto out_free_resources;
5395 }
5396
5397 for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
5398 ioc->event_masks[i] = -1;
5399
5400 /* here we enable the events we care about */
5401 _base_unmask_events(ioc, MPI2_EVENT_SAS_DISCOVERY);
5402 _base_unmask_events(ioc, MPI2_EVENT_SAS_BROADCAST_PRIMITIVE);
5403 _base_unmask_events(ioc, MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST);
5404 _base_unmask_events(ioc, MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE);
5405 _base_unmask_events(ioc, MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE);
5406 _base_unmask_events(ioc, MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST);
5407 _base_unmask_events(ioc, MPI2_EVENT_IR_VOLUME);
5408 _base_unmask_events(ioc, MPI2_EVENT_IR_PHYSICAL_DISK);
5409 _base_unmask_events(ioc, MPI2_EVENT_IR_OPERATION_STATUS);
5410 _base_unmask_events(ioc, MPI2_EVENT_LOG_ENTRY_ADDED);
2d8ce8c9 5411 _base_unmask_events(ioc, MPI2_EVENT_TEMP_THRESHOLD);
a470a51c
C		 5412 if (ioc->hba_mpi_version_belonged == MPI26_VERSION)
5413 _base_unmask_events(ioc, MPI2_EVENT_ACTIVE_CABLE_EXCEPTION);
f92363d1 5414
98c56ad3 5415 r = _base_make_ioc_operational(ioc);
f92363d1
SR		 5416 if (r)
5417 goto out_free_resources;
5418
16e179bd 5419 ioc->non_operational_loop = 0;
f92363d1
SR		 5420 return 0;
5421
5422 out_free_resources:
5423
5424 ioc->remove_host = 1;
5425
5426 mpt3sas_base_free_resources(ioc);
5427 _base_release_memory_pools(ioc);
5428 pci_set_drvdata(ioc->pdev, NULL);
5429 kfree(ioc->cpu_msix_table);
7786ab6a
SR		 5430 if (ioc->is_warpdrive)
5431 kfree(ioc->reply_post_host_index);
f92363d1
SR		 5432 kfree(ioc->pd_handles);
5433 kfree(ioc->blocking_handles);
c696f7b8
SPS		 5434 kfree(ioc->device_remove_in_progress);
5435 kfree(ioc->pend_os_device_add);
f92363d1
SR		 5436 kfree(ioc->tm_cmds.reply);
5437 kfree(ioc->transport_cmds.reply);
5438 kfree(ioc->scsih_cmds.reply);
5439 kfree(ioc->config_cmds.reply);
5440 kfree(ioc->base_cmds.reply);
5441 kfree(ioc->port_enable_cmds.reply);
5442 kfree(ioc->ctl_cmds.reply);
5443 kfree(ioc->ctl_cmds.sense);
5444 kfree(ioc->pfacts);
5445 ioc->ctl_cmds.reply = NULL;
5446 ioc->base_cmds.reply = NULL;
5447 ioc->tm_cmds.reply = NULL;
5448 ioc->scsih_cmds.reply = NULL;
5449 ioc->transport_cmds.reply = NULL;
5450 ioc->config_cmds.reply = NULL;
5451 ioc->pfacts = NULL;
5452 return r;
5453}
5454
5455
5456/**
5457 * mpt3sas_base_detach - remove controller instance
5458 * @ioc: per adapter object
5459 *
5460 * Return nothing.
5461 */
5462void
5463mpt3sas_base_detach(struct MPT3SAS_ADAPTER *ioc)
5464{
5465 dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
5466 __func__));
5467
5468 mpt3sas_base_stop_watchdog(ioc);
5469 mpt3sas_base_free_resources(ioc);
5470 _base_release_memory_pools(ioc);
5471 pci_set_drvdata(ioc->pdev, NULL);
5472 kfree(ioc->cpu_msix_table);
7786ab6a
SR		 5473 if (ioc->is_warpdrive)
5474 kfree(ioc->reply_post_host_index);
f92363d1
SR		 5475 kfree(ioc->pd_handles);
5476 kfree(ioc->blocking_handles);
c696f7b8
SPS		 5477 kfree(ioc->device_remove_in_progress);
5478 kfree(ioc->pend_os_device_add);
f92363d1
SR		 5479 kfree(ioc->pfacts);
5480 kfree(ioc->ctl_cmds.reply);
5481 kfree(ioc->ctl_cmds.sense);
5482 kfree(ioc->base_cmds.reply);
5483 kfree(ioc->port_enable_cmds.reply);
5484 kfree(ioc->tm_cmds.reply);
5485 kfree(ioc->transport_cmds.reply);
5486 kfree(ioc->scsih_cmds.reply);
5487 kfree(ioc->config_cmds.reply);
5488}
5489
5490/**
5491 * _base_reset_handler - reset callback handler (for base)
5492 * @ioc: per adapter object
5493 * @reset_phase: phase
5494 *
5495 * The handler for doing any required cleanup or initialization.
5496 *
5497 * The reset phase can be MPT3_IOC_PRE_RESET, MPT3_IOC_AFTER_RESET,
5498 * MPT3_IOC_DONE_RESET
5499 *
5500 * Return nothing.
5501 */
5502static void
5503_base_reset_handler(struct MPT3SAS_ADAPTER *ioc, int reset_phase)
5504{
5505 mpt3sas_scsih_reset_handler(ioc, reset_phase);
5506 mpt3sas_ctl_reset_handler(ioc, reset_phase);
5507 switch (reset_phase) {
5508 case MPT3_IOC_PRE_RESET:
5509 dtmprintk(ioc, pr_info(MPT3SAS_FMT
5510 "%s: MPT3_IOC_PRE_RESET\n", ioc->name, __func__));
5511 break;
5512 case MPT3_IOC_AFTER_RESET:
5513 dtmprintk(ioc, pr_info(MPT3SAS_FMT
5514 "%s: MPT3_IOC_AFTER_RESET\n", ioc->name, __func__));
5515 if (ioc->transport_cmds.status & MPT3_CMD_PENDING) {
5516 ioc->transport_cmds.status |= MPT3_CMD_RESET;
5517 mpt3sas_base_free_smid(ioc, ioc->transport_cmds.smid);
5518 complete(&ioc->transport_cmds.done);
5519 }
5520 if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
5521 ioc->base_cmds.status |= MPT3_CMD_RESET;
5522 mpt3sas_base_free_smid(ioc, ioc->base_cmds.smid);
5523 complete(&ioc->base_cmds.done);
5524 }
5525 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
5526 ioc->port_enable_failed = 1;
5527 ioc->port_enable_cmds.status |= MPT3_CMD_RESET;
5528 mpt3sas_base_free_smid(ioc, ioc->port_enable_cmds.smid);
5529 if (ioc->is_driver_loading) {
5530 ioc->start_scan_failed =
5531 MPI2_IOCSTATUS_INTERNAL_ERROR;
5532 ioc->start_scan = 0;
5533 ioc->port_enable_cmds.status =
5534 MPT3_CMD_NOT_USED;
5535 } else
5536 complete(&ioc->port_enable_cmds.done);
5537 }
5538 if (ioc->config_cmds.status & MPT3_CMD_PENDING) {
5539 ioc->config_cmds.status |= MPT3_CMD_RESET;
5540 mpt3sas_base_free_smid(ioc, ioc->config_cmds.smid);
5541 ioc->config_cmds.smid = USHRT_MAX;
5542 complete(&ioc->config_cmds.done);
5543 }
5544 break;
5545 case MPT3_IOC_DONE_RESET:
5546 dtmprintk(ioc, pr_info(MPT3SAS_FMT
5547 "%s: MPT3_IOC_DONE_RESET\n", ioc->name, __func__));
5548 break;
5549 }
5550}
5551
5552/**
5553 * _wait_for_commands_to_complete - reset controller
5554 * @ioc: Pointer to MPT_ADAPTER structure
f92363d1
SR		 5555 *
5556 * This function waiting(3s) for all pending commands to complete
5557 * prior to putting controller in reset.
5558 */
5559static void
98c56ad3 5560_wait_for_commands_to_complete(struct MPT3SAS_ADAPTER *ioc)
f92363d1
SR		 5561{
5562 u32 ioc_state;
5563 unsigned long flags;
5564 u16 i;
5565
5566 ioc->pending_io_count = 0;
f92363d1
SR		 5567
5568 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
5569 if ((ioc_state & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL)
5570 return;
5571
5572 /* pending command count */
5573 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
5574 for (i = 0; i < ioc->scsiio_depth; i++)
5575 if (ioc->scsi_lookup[i].cb_idx != 0xFF)
5576 ioc->pending_io_count++;
5577 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
5578
5579 if (!ioc->pending_io_count)
5580 return;
5581
5582 /* wait for pending commands to complete */
5583 wait_event_timeout(ioc->reset_wq, ioc->pending_io_count == 0, 10 * HZ);
5584}
5585
5586/**
5587 * mpt3sas_base_hard_reset_handler - reset controller
5588 * @ioc: Pointer to MPT_ADAPTER structure
f92363d1
SR		 5589 * @type: FORCE_BIG_HAMMER or SOFT_RESET
5590 *
5591 * Returns 0 for success, non-zero for failure.
5592 */
5593int
98c56ad3 5594mpt3sas_base_hard_reset_handler(struct MPT3SAS_ADAPTER *ioc,
f92363d1
SR		 5595 enum reset_type type)
5596{
5597 int r;
5598 unsigned long flags;
5599 u32 ioc_state;
5600 u8 is_fault = 0, is_trigger = 0;
5601
5602 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: enter\n", ioc->name,
5603 __func__));
5604
5605 if (ioc->pci_error_recovery) {
5606 pr_err(MPT3SAS_FMT "%s: pci error recovery reset\n",
5607 ioc->name, __func__);
5608 r = 0;
5609 goto out_unlocked;
5610 }
5611
5612 if (mpt3sas_fwfault_debug)
5613 mpt3sas_halt_firmware(ioc);
5614
f92363d1
SR		 5615 /* wait for an active reset in progress to complete */
5616 if (!mutex_trylock(&ioc->reset_in_progress_mutex)) {
5617 do {
5618 ssleep(1);
5619 } while (ioc->shost_recovery == 1);
5620 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: exit\n", ioc->name,
5621 __func__));
5622 return ioc->ioc_reset_in_progress_status;
5623 }
5624
5625 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
5626 ioc->shost_recovery = 1;
5627 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
5628
5629 if ((ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] &
5630 MPT3_DIAG_BUFFER_IS_REGISTERED) &&
5631 (!(ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] &
5632 MPT3_DIAG_BUFFER_IS_RELEASED))) {
5633 is_trigger = 1;
5634 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
5635 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
5636 is_fault = 1;
5637 }
5638 _base_reset_handler(ioc, MPT3_IOC_PRE_RESET);
98c56ad3 5639 _wait_for_commands_to_complete(ioc);
f92363d1 5640 _base_mask_interrupts(ioc);
98c56ad3 5641 r = _base_make_ioc_ready(ioc, type);
f92363d1
SR		 5642 if (r)
5643 goto out;
5644 _base_reset_handler(ioc, MPT3_IOC_AFTER_RESET);
5645
5646 /* If this hard reset is called while port enable is active, then
5647 * there is no reason to call make_ioc_operational
5648 */
5649 if (ioc->is_driver_loading && ioc->port_enable_failed) {
5650 ioc->remove_host = 1;
5651 r = -EFAULT;
5652 goto out;
5653 }
98c56ad3 5654 r = _base_get_ioc_facts(ioc);
f92363d1
SR		 5655 if (r)
5656 goto out;
9b05c91a
SR		 5657
5658 if (ioc->rdpq_array_enable && !ioc->rdpq_array_capable)
5659 panic("%s: Issue occurred with flashing controller firmware."
5660 "Please reboot the system and ensure that the correct"
5661 " firmware version is running\n", ioc->name);
5662
98c56ad3 5663 r = _base_make_ioc_operational(ioc);
f92363d1
SR		 5664 if (!r)
5665 _base_reset_handler(ioc, MPT3_IOC_DONE_RESET);
5666
5667 out:
5668 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: %s\n",
5669 ioc->name, __func__, ((r == 0) ? "SUCCESS" : "FAILED")));
5670
5671 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
5672 ioc->ioc_reset_in_progress_status = r;
5673 ioc->shost_recovery = 0;
5674 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
5675 ioc->ioc_reset_count++;
5676 mutex_unlock(&ioc->reset_in_progress_mutex);
5677
5678 out_unlocked:
5679 if ((r == 0) && is_trigger) {
5680 if (is_fault)
5681 mpt3sas_trigger_master(ioc, MASTER_TRIGGER_FW_FAULT);
5682 else
5683 mpt3sas_trigger_master(ioc,
5684 MASTER_TRIGGER_ADAPTER_RESET);
5685 }
5686 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: exit\n", ioc->name,
5687 __func__));
5688 return r;
5689}
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