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mpt3sas: Eliminate dead sleep_flag code
[mirror_ubuntu-artful-kernel.git] / drivers / scsi / mpt3sas / mpt3sas_base.c
CommitLineData
f92363d1
SR		 1/*
2 * This is the Fusion MPT base driver providing common API layer interface
3 * for access to MPT (Message Passing Technology) firmware.
4 *
5 * This code is based on drivers/scsi/mpt3sas/mpt3sas_base.c
a4ffce0d 6 * Copyright (C) 2012-2014 LSI Corporation
a03bd153
SR		 7 * Copyright (C) 2013-2014 Avago Technologies
8 * (mailto: MPT-FusionLinux.pdl@avagotech.com)
f92363d1
SR		 9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version 2
13 * of the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * NO WARRANTY
21 * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
22 * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
23 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
24 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
25 * solely responsible for determining the appropriateness of using and
26 * distributing the Program and assumes all risks associated with its
27 * exercise of rights under this Agreement, including but not limited to
28 * the risks and costs of program errors, damage to or loss of data,
29 * programs or equipment, and unavailability or interruption of operations.
30
31 * DISCLAIMER OF LIABILITY
32 * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
33 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34 * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
35 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
36 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
37 * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
38 * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
39
40 * You should have received a copy of the GNU General Public License
41 * along with this program; if not, write to the Free Software
42 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
43 * USA.
44 */
45
f92363d1
SR		 46#include <linux/kernel.h>
47#include <linux/module.h>
48#include <linux/errno.h>
49#include <linux/init.h>
50#include <linux/slab.h>
51#include <linux/types.h>
52#include <linux/pci.h>
53#include <linux/kdev_t.h>
54#include <linux/blkdev.h>
55#include <linux/delay.h>
56#include <linux/interrupt.h>
57#include <linux/dma-mapping.h>
58#include <linux/io.h>
59#include <linux/time.h>
23409bd4 60#include <linux/ktime.h>
f92363d1
SR		 61#include <linux/kthread.h>
62#include <linux/aer.h>
63
64
65#include "mpt3sas_base.h"
66
67static MPT_CALLBACK mpt_callbacks[MPT_MAX_CALLBACKS];
68
69
70#define FAULT_POLLING_INTERVAL 1000 /* in milliseconds */
71
72 /* maximum controller queue depth */
73#define MAX_HBA_QUEUE_DEPTH 30000
74#define MAX_CHAIN_DEPTH 100000
75static int max_queue_depth = -1;
76module_param(max_queue_depth, int, 0);
77MODULE_PARM_DESC(max_queue_depth, " max controller queue depth ");
78
79static int max_sgl_entries = -1;
80module_param(max_sgl_entries, int, 0);
81MODULE_PARM_DESC(max_sgl_entries, " max sg entries ");
82
83static int msix_disable = -1;
84module_param(msix_disable, int, 0);
85MODULE_PARM_DESC(msix_disable, " disable msix routed interrupts (default=0)");
86
64038301
SPS		 87static int smp_affinity_enable = 1;
88module_param(smp_affinity_enable, int, S_IRUGO);
89MODULE_PARM_DESC(smp_affinity_enable, "SMP affinity feature enable/disbale Default: enable(1)");
90
fb77bb53 91static int max_msix_vectors = -1;
9c500060
SR		 92module_param(max_msix_vectors, int, 0);
93MODULE_PARM_DESC(max_msix_vectors,
fb77bb53 94 " max msix vectors");
f92363d1
SR		 95
96static int mpt3sas_fwfault_debug;
97MODULE_PARM_DESC(mpt3sas_fwfault_debug,
98 " enable detection of firmware fault and halt firmware - (default=0)");
99
9b05c91a 100static int
98c56ad3 101_base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc);
f92363d1
SR		 102
103/**
104 * _scsih_set_fwfault_debug - global setting of ioc->fwfault_debug.
105 *
106 */
107static int
108_scsih_set_fwfault_debug(const char *val, struct kernel_param *kp)
109{
110 int ret = param_set_int(val, kp);
111 struct MPT3SAS_ADAPTER *ioc;
112
113 if (ret)
114 return ret;
115
08c4d550 116 /* global ioc spinlock to protect controller list on list operations */
f92363d1 117 pr_info("setting fwfault_debug(%d)\n", mpt3sas_fwfault_debug);
08c4d550 118 spin_lock(&gioc_lock);
f92363d1
SR		 119 list_for_each_entry(ioc, &mpt3sas_ioc_list, list)
120 ioc->fwfault_debug = mpt3sas_fwfault_debug;
08c4d550 121 spin_unlock(&gioc_lock);
f92363d1
SR		 122 return 0;
123}
124module_param_call(mpt3sas_fwfault_debug, _scsih_set_fwfault_debug,
125 param_get_int, &mpt3sas_fwfault_debug, 0644);
126
127/**
128 * mpt3sas_remove_dead_ioc_func - kthread context to remove dead ioc
129 * @arg: input argument, used to derive ioc
130 *
131 * Return 0 if controller is removed from pci subsystem.
132 * Return -1 for other case.
133 */
134static int mpt3sas_remove_dead_ioc_func(void *arg)
135{
136 struct MPT3SAS_ADAPTER *ioc = (struct MPT3SAS_ADAPTER *)arg;
137 struct pci_dev *pdev;
138
139 if ((ioc == NULL))
140 return -1;
141
142 pdev = ioc->pdev;
143 if ((pdev == NULL))
144 return -1;
64cdb418 145 pci_stop_and_remove_bus_device_locked(pdev);
f92363d1
SR		 146 return 0;
147}
148
149/**
150 * _base_fault_reset_work - workq handling ioc fault conditions
151 * @work: input argument, used to derive ioc
152 * Context: sleep.
153 *
154 * Return nothing.
155 */
156static void
157_base_fault_reset_work(struct work_struct *work)
158{
159 struct MPT3SAS_ADAPTER *ioc =
160 container_of(work, struct MPT3SAS_ADAPTER, fault_reset_work.work);
161 unsigned long flags;
162 u32 doorbell;
163 int rc;
164 struct task_struct *p;
165
166
167 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
16e179bd 168 if (ioc->shost_recovery || ioc->pci_error_recovery)
f92363d1
SR		 169 goto rearm_timer;
170 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
171
172 doorbell = mpt3sas_base_get_iocstate(ioc, 0);
173 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_MASK) {
174 pr_err(MPT3SAS_FMT "SAS host is non-operational !!!!\n",
175 ioc->name);
176
16e179bd
SR		 177 /* It may be possible that EEH recovery can resolve some of
178 * pci bus failure issues rather removing the dead ioc function
179 * by considering controller is in a non-operational state. So
180 * here priority is given to the EEH recovery. If it doesn't
181 * not resolve this issue, mpt3sas driver will consider this
182 * controller to non-operational state and remove the dead ioc
183 * function.
184 */
185 if (ioc->non_operational_loop++ < 5) {
186 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock,
187 flags);
188 goto rearm_timer;
189 }
190
f92363d1
SR		 191 /*
192 * Call _scsih_flush_pending_cmds callback so that we flush all
193 * pending commands back to OS. This call is required to aovid
194 * deadlock at block layer. Dead IOC will fail to do diag reset,
195 * and this call is safe since dead ioc will never return any
196 * command back from HW.
197 */
198 ioc->schedule_dead_ioc_flush_running_cmds(ioc);
199 /*
200 * Set remove_host flag early since kernel thread will
201 * take some time to execute.
202 */
203 ioc->remove_host = 1;
204 /*Remove the Dead Host */
205 p = kthread_run(mpt3sas_remove_dead_ioc_func, ioc,
c84b06a4 206 "%s_dead_ioc_%d", ioc->driver_name, ioc->id);
f92363d1
SR		 207 if (IS_ERR(p))
208 pr_err(MPT3SAS_FMT
209 "%s: Running mpt3sas_dead_ioc thread failed !!!!\n",
210 ioc->name, __func__);
211 else
212 pr_err(MPT3SAS_FMT
213 "%s: Running mpt3sas_dead_ioc thread success !!!!\n",
214 ioc->name, __func__);
215 return; /* don't rearm timer */
216 }
217
16e179bd
SR		 218 ioc->non_operational_loop = 0;
219
f92363d1 220 if ((doorbell & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL) {
98c56ad3 221 rc = mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER);
f92363d1
SR		 222 pr_warn(MPT3SAS_FMT "%s: hard reset: %s\n", ioc->name,
223 __func__, (rc == 0) ? "success" : "failed");
224 doorbell = mpt3sas_base_get_iocstate(ioc, 0);
225 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
226 mpt3sas_base_fault_info(ioc, doorbell &
227 MPI2_DOORBELL_DATA_MASK);
228 if (rc && (doorbell & MPI2_IOC_STATE_MASK) !=
229 MPI2_IOC_STATE_OPERATIONAL)
230 return; /* don't rearm timer */
231 }
232
233 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
234 rearm_timer:
235 if (ioc->fault_reset_work_q)
236 queue_delayed_work(ioc->fault_reset_work_q,
237 &ioc->fault_reset_work,
238 msecs_to_jiffies(FAULT_POLLING_INTERVAL));
239 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
240}
241
242/**
243 * mpt3sas_base_start_watchdog - start the fault_reset_work_q
244 * @ioc: per adapter object
245 * Context: sleep.
246 *
247 * Return nothing.
248 */
249void
250mpt3sas_base_start_watchdog(struct MPT3SAS_ADAPTER *ioc)
251{
252 unsigned long flags;
253
254 if (ioc->fault_reset_work_q)
255 return;
256
257 /* initialize fault polling */
258
259 INIT_DELAYED_WORK(&ioc->fault_reset_work, _base_fault_reset_work);
260 snprintf(ioc->fault_reset_work_q_name,
c84b06a4
SR		 261 sizeof(ioc->fault_reset_work_q_name), "poll_%s%d_status",
262 ioc->driver_name, ioc->id);
f92363d1
SR		 263 ioc->fault_reset_work_q =
264 create_singlethread_workqueue(ioc->fault_reset_work_q_name);
265 if (!ioc->fault_reset_work_q) {
266 pr_err(MPT3SAS_FMT "%s: failed (line=%d)\n",
267 ioc->name, __func__, __LINE__);
268 return;
269 }
270 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
271 if (ioc->fault_reset_work_q)
272 queue_delayed_work(ioc->fault_reset_work_q,
273 &ioc->fault_reset_work,
274 msecs_to_jiffies(FAULT_POLLING_INTERVAL));
275 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
276}
277
278/**
279 * mpt3sas_base_stop_watchdog - stop the fault_reset_work_q
280 * @ioc: per adapter object
281 * Context: sleep.
282 *
283 * Return nothing.
284 */
285void
286mpt3sas_base_stop_watchdog(struct MPT3SAS_ADAPTER *ioc)
287{
288 unsigned long flags;
289 struct workqueue_struct *wq;
290
291 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
292 wq = ioc->fault_reset_work_q;
293 ioc->fault_reset_work_q = NULL;
294 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
295 if (wq) {
4dc06fd8 296 if (!cancel_delayed_work_sync(&ioc->fault_reset_work))
f92363d1
SR		 297 flush_workqueue(wq);
298 destroy_workqueue(wq);
299 }
300}
301
302/**
303 * mpt3sas_base_fault_info - verbose translation of firmware FAULT code
304 * @ioc: per adapter object
305 * @fault_code: fault code
306 *
307 * Return nothing.
308 */
309void
310mpt3sas_base_fault_info(struct MPT3SAS_ADAPTER *ioc , u16 fault_code)
311{
312 pr_err(MPT3SAS_FMT "fault_state(0x%04x)!\n",
313 ioc->name, fault_code);
314}
315
316/**
317 * mpt3sas_halt_firmware - halt's mpt controller firmware
318 * @ioc: per adapter object
319 *
320 * For debugging timeout related issues. Writing 0xCOFFEE00
321 * to the doorbell register will halt controller firmware. With
322 * the purpose to stop both driver and firmware, the enduser can
323 * obtain a ring buffer from controller UART.
324 */
325void
326mpt3sas_halt_firmware(struct MPT3SAS_ADAPTER *ioc)
327{
328 u32 doorbell;
329
330 if (!ioc->fwfault_debug)
331 return;
332
333 dump_stack();
334
335 doorbell = readl(&ioc->chip->Doorbell);
336 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
337 mpt3sas_base_fault_info(ioc , doorbell);
338 else {
339 writel(0xC0FFEE00, &ioc->chip->Doorbell);
340 pr_err(MPT3SAS_FMT "Firmware is halted due to command timeout\n",
341 ioc->name);
342 }
343
344 if (ioc->fwfault_debug == 2)
345 for (;;)
346 ;
347 else
348 panic("panic in %s\n", __func__);
349}
350
f92363d1
SR		 351/**
352 * _base_sas_ioc_info - verbose translation of the ioc status
353 * @ioc: per adapter object
354 * @mpi_reply: reply mf payload returned from firmware
355 * @request_hdr: request mf
356 *
357 * Return nothing.
358 */
359static void
360_base_sas_ioc_info(struct MPT3SAS_ADAPTER *ioc, MPI2DefaultReply_t *mpi_reply,
361 MPI2RequestHeader_t *request_hdr)
362{
363 u16 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) &
364 MPI2_IOCSTATUS_MASK;
365 char *desc = NULL;
366 u16 frame_sz;
367 char *func_str = NULL;
368
369 /* SCSI_IO, RAID_PASS are handled from _scsih_scsi_ioc_info */
370 if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST ||
371 request_hdr->Function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH ||
372 request_hdr->Function == MPI2_FUNCTION_EVENT_NOTIFICATION)
373 return;
374
375 if (ioc_status == MPI2_IOCSTATUS_CONFIG_INVALID_PAGE)
376 return;
377
378 switch (ioc_status) {
379
380/****************************************************************************
381* Common IOCStatus values for all replies
382****************************************************************************/
383
384 case MPI2_IOCSTATUS_INVALID_FUNCTION:
385 desc = "invalid function";
386 break;
387 case MPI2_IOCSTATUS_BUSY:
388 desc = "busy";
389 break;
390 case MPI2_IOCSTATUS_INVALID_SGL:
391 desc = "invalid sgl";
392 break;
393 case MPI2_IOCSTATUS_INTERNAL_ERROR:
394 desc = "internal error";
395 break;
396 case MPI2_IOCSTATUS_INVALID_VPID:
397 desc = "invalid vpid";
398 break;
399 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES:
400 desc = "insufficient resources";
401 break;
b130b0d5
SS		 402 case MPI2_IOCSTATUS_INSUFFICIENT_POWER:
403 desc = "insufficient power";
404 break;
f92363d1
SR		 405 case MPI2_IOCSTATUS_INVALID_FIELD:
406 desc = "invalid field";
407 break;
408 case MPI2_IOCSTATUS_INVALID_STATE:
409 desc = "invalid state";
410 break;
411 case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED:
412 desc = "op state not supported";
413 break;
414
415/****************************************************************************
416* Config IOCStatus values
417****************************************************************************/
418
419 case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION:
420 desc = "config invalid action";
421 break;
422 case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE:
423 desc = "config invalid type";
424 break;
425 case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE:
426 desc = "config invalid page";
427 break;
428 case MPI2_IOCSTATUS_CONFIG_INVALID_DATA:
429 desc = "config invalid data";
430 break;
431 case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS:
432 desc = "config no defaults";
433 break;
434 case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT:
435 desc = "config cant commit";
436 break;
437
438/****************************************************************************
439* SCSI IO Reply
440****************************************************************************/
441
442 case MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR:
443 case MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE:
444 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
445 case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN:
446 case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN:
447 case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR:
448 case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR:
449 case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED:
450 case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH:
451 case MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED:
452 case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED:
453 case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED:
454 break;
455
456/****************************************************************************
457* For use by SCSI Initiator and SCSI Target end-to-end data protection
458****************************************************************************/
459
460 case MPI2_IOCSTATUS_EEDP_GUARD_ERROR:
461 desc = "eedp guard error";
462 break;
463 case MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR:
464 desc = "eedp ref tag error";
465 break;
466 case MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR:
467 desc = "eedp app tag error";
468 break;
469
470/****************************************************************************
471* SCSI Target values
472****************************************************************************/
473
474 case MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX:
475 desc = "target invalid io index";
476 break;
477 case MPI2_IOCSTATUS_TARGET_ABORTED:
478 desc = "target aborted";
479 break;
480 case MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE:
481 desc = "target no conn retryable";
482 break;
483 case MPI2_IOCSTATUS_TARGET_NO_CONNECTION:
484 desc = "target no connection";
485 break;
486 case MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH:
487 desc = "target xfer count mismatch";
488 break;
489 case MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR:
490 desc = "target data offset error";
491 break;
492 case MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA:
493 desc = "target too much write data";
494 break;
495 case MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT:
496 desc = "target iu too short";
497 break;
498 case MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT:
499 desc = "target ack nak timeout";
500 break;
501 case MPI2_IOCSTATUS_TARGET_NAK_RECEIVED:
502 desc = "target nak received";
503 break;
504
505/****************************************************************************
506* Serial Attached SCSI values
507****************************************************************************/
508
509 case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED:
510 desc = "smp request failed";
511 break;
512 case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN:
513 desc = "smp data overrun";
514 break;
515
516/****************************************************************************
517* Diagnostic Buffer Post / Diagnostic Release values
518****************************************************************************/
519
520 case MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED:
521 desc = "diagnostic released";
522 break;
523 default:
524 break;
525 }
526
527 if (!desc)
528 return;
529
530 switch (request_hdr->Function) {
531 case MPI2_FUNCTION_CONFIG:
532 frame_sz = sizeof(Mpi2ConfigRequest_t) + ioc->sge_size;
533 func_str = "config_page";
534 break;
535 case MPI2_FUNCTION_SCSI_TASK_MGMT:
536 frame_sz = sizeof(Mpi2SCSITaskManagementRequest_t);
537 func_str = "task_mgmt";
538 break;
539 case MPI2_FUNCTION_SAS_IO_UNIT_CONTROL:
540 frame_sz = sizeof(Mpi2SasIoUnitControlRequest_t);
541 func_str = "sas_iounit_ctl";
542 break;
543 case MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR:
544 frame_sz = sizeof(Mpi2SepRequest_t);
545 func_str = "enclosure";
546 break;
547 case MPI2_FUNCTION_IOC_INIT:
548 frame_sz = sizeof(Mpi2IOCInitRequest_t);
549 func_str = "ioc_init";
550 break;
551 case MPI2_FUNCTION_PORT_ENABLE:
552 frame_sz = sizeof(Mpi2PortEnableRequest_t);
553 func_str = "port_enable";
554 break;
555 case MPI2_FUNCTION_SMP_PASSTHROUGH:
556 frame_sz = sizeof(Mpi2SmpPassthroughRequest_t) + ioc->sge_size;
557 func_str = "smp_passthru";
558 break;
559 default:
560 frame_sz = 32;
561 func_str = "unknown";
562 break;
563 }
564
565 pr_warn(MPT3SAS_FMT "ioc_status: %s(0x%04x), request(0x%p),(%s)\n",
566 ioc->name, desc, ioc_status, request_hdr, func_str);
567
568 _debug_dump_mf(request_hdr, frame_sz/4);
569}
570
571/**
572 * _base_display_event_data - verbose translation of firmware asyn events
573 * @ioc: per adapter object
574 * @mpi_reply: reply mf payload returned from firmware
575 *
576 * Return nothing.
577 */
578static void
579_base_display_event_data(struct MPT3SAS_ADAPTER *ioc,
580 Mpi2EventNotificationReply_t *mpi_reply)
581{
582 char *desc = NULL;
583 u16 event;
584
585 if (!(ioc->logging_level & MPT_DEBUG_EVENTS))
586 return;
587
588 event = le16_to_cpu(mpi_reply->Event);
589
590 switch (event) {
591 case MPI2_EVENT_LOG_DATA:
592 desc = "Log Data";
593 break;
594 case MPI2_EVENT_STATE_CHANGE:
595 desc = "Status Change";
596 break;
597 case MPI2_EVENT_HARD_RESET_RECEIVED:
598 desc = "Hard Reset Received";
599 break;
600 case MPI2_EVENT_EVENT_CHANGE:
601 desc = "Event Change";
602 break;
603 case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE:
604 desc = "Device Status Change";
605 break;
606 case MPI2_EVENT_IR_OPERATION_STATUS:
7786ab6a
SR		 607 if (!ioc->hide_ir_msg)
608 desc = "IR Operation Status";
f92363d1
SR		 609 break;
610 case MPI2_EVENT_SAS_DISCOVERY:
611 {
612 Mpi2EventDataSasDiscovery_t *event_data =
613 (Mpi2EventDataSasDiscovery_t *)mpi_reply->EventData;
614 pr_info(MPT3SAS_FMT "Discovery: (%s)", ioc->name,
615 (event_data->ReasonCode == MPI2_EVENT_SAS_DISC_RC_STARTED) ?
616 "start" : "stop");
617 if (event_data->DiscoveryStatus)
618 pr_info("discovery_status(0x%08x)",
619 le32_to_cpu(event_data->DiscoveryStatus));
620 pr_info("\n");
621 return;
622 }
623 case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE:
624 desc = "SAS Broadcast Primitive";
625 break;
626 case MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
627 desc = "SAS Init Device Status Change";
628 break;
629 case MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW:
630 desc = "SAS Init Table Overflow";
631 break;
632 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
633 desc = "SAS Topology Change List";
634 break;
635 case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE:
636 desc = "SAS Enclosure Device Status Change";
637 break;
638 case MPI2_EVENT_IR_VOLUME:
7786ab6a
SR		 639 if (!ioc->hide_ir_msg)
640 desc = "IR Volume";
f92363d1
SR		 641 break;
642 case MPI2_EVENT_IR_PHYSICAL_DISK:
7786ab6a
SR		 643 if (!ioc->hide_ir_msg)
644 desc = "IR Physical Disk";
f92363d1
SR		 645 break;
646 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
7786ab6a
SR		 647 if (!ioc->hide_ir_msg)
648 desc = "IR Configuration Change List";
f92363d1
SR		 649 break;
650 case MPI2_EVENT_LOG_ENTRY_ADDED:
7786ab6a
SR		 651 if (!ioc->hide_ir_msg)
652 desc = "Log Entry Added";
f92363d1 653 break;
2d8ce8c9
SR		 654 case MPI2_EVENT_TEMP_THRESHOLD:
655 desc = "Temperature Threshold";
656 break;
a470a51c
C		 657 case MPI2_EVENT_ACTIVE_CABLE_EXCEPTION:
658 desc = "Active cable exception";
659 break;
f92363d1
SR		 660 }
661
662 if (!desc)
663 return;
664
665 pr_info(MPT3SAS_FMT "%s\n", ioc->name, desc);
666}
f92363d1
SR		 667
668/**
669 * _base_sas_log_info - verbose translation of firmware log info
670 * @ioc: per adapter object
671 * @log_info: log info
672 *
673 * Return nothing.
674 */
675static void
676_base_sas_log_info(struct MPT3SAS_ADAPTER *ioc , u32 log_info)
677{
678 union loginfo_type {
679 u32 loginfo;
680 struct {
681 u32 subcode:16;
682 u32 code:8;
683 u32 originator:4;
684 u32 bus_type:4;
685 } dw;
686 };
687 union loginfo_type sas_loginfo;
688 char *originator_str = NULL;
689
690 sas_loginfo.loginfo = log_info;
691 if (sas_loginfo.dw.bus_type != 3 /*SAS*/)
692 return;
693
694 /* each nexus loss loginfo */
695 if (log_info == 0x31170000)
696 return;
697
698 /* eat the loginfos associated with task aborts */
699 if (ioc->ignore_loginfos && (log_info == 0x30050000 || log_info ==
700 0x31140000 || log_info == 0x31130000))
701 return;
702
703 switch (sas_loginfo.dw.originator) {
704 case 0:
705 originator_str = "IOP";
706 break;
707 case 1:
708 originator_str = "PL";
709 break;
710 case 2:
7786ab6a
SR		 711 if (!ioc->hide_ir_msg)
712 originator_str = "IR";
713 else
714 originator_str = "WarpDrive";
f92363d1
SR		 715 break;
716 }
717
718 pr_warn(MPT3SAS_FMT
719 "log_info(0x%08x): originator(%s), code(0x%02x), sub_code(0x%04x)\n",
720 ioc->name, log_info,
721 originator_str, sas_loginfo.dw.code,
722 sas_loginfo.dw.subcode);
723}
724
725/**
726 * _base_display_reply_info -
727 * @ioc: per adapter object
728 * @smid: system request message index
729 * @msix_index: MSIX table index supplied by the OS
730 * @reply: reply message frame(lower 32bit addr)
731 *
732 * Return nothing.
733 */
734static void
735_base_display_reply_info(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
736 u32 reply)
737{
738 MPI2DefaultReply_t *mpi_reply;
739 u16 ioc_status;
740 u32 loginfo = 0;
741
742 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
743 if (unlikely(!mpi_reply)) {
744 pr_err(MPT3SAS_FMT "mpi_reply not valid at %s:%d/%s()!\n",
745 ioc->name, __FILE__, __LINE__, __func__);
746 return;
747 }
748 ioc_status = le16_to_cpu(mpi_reply->IOCStatus);
af009411 749
f92363d1
SR		 750 if ((ioc_status & MPI2_IOCSTATUS_MASK) &&
751 (ioc->logging_level & MPT_DEBUG_REPLY)) {
752 _base_sas_ioc_info(ioc , mpi_reply,
753 mpt3sas_base_get_msg_frame(ioc, smid));
754 }
af009411 755
f92363d1
SR		 756 if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
757 loginfo = le32_to_cpu(mpi_reply->IOCLogInfo);
758 _base_sas_log_info(ioc, loginfo);
759 }
760
761 if (ioc_status || loginfo) {
762 ioc_status &= MPI2_IOCSTATUS_MASK;
763 mpt3sas_trigger_mpi(ioc, ioc_status, loginfo);
764 }
765}
766
767/**
768 * mpt3sas_base_done - base internal command completion routine
769 * @ioc: per adapter object
770 * @smid: system request message index
771 * @msix_index: MSIX table index supplied by the OS
772 * @reply: reply message frame(lower 32bit addr)
773 *
774 * Return 1 meaning mf should be freed from _base_interrupt
775 * 0 means the mf is freed from this function.
776 */
777u8
778mpt3sas_base_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
779 u32 reply)
780{
781 MPI2DefaultReply_t *mpi_reply;
782
783 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
784 if (mpi_reply && mpi_reply->Function == MPI2_FUNCTION_EVENT_ACK)
fd0331b3 785 return mpt3sas_check_for_pending_internal_cmds(ioc, smid);
f92363d1
SR		 786
787 if (ioc->base_cmds.status == MPT3_CMD_NOT_USED)
788 return 1;
789
790 ioc->base_cmds.status |= MPT3_CMD_COMPLETE;
791 if (mpi_reply) {
792 ioc->base_cmds.status |= MPT3_CMD_REPLY_VALID;
793 memcpy(ioc->base_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
794 }
795 ioc->base_cmds.status &= ~MPT3_CMD_PENDING;
796
797 complete(&ioc->base_cmds.done);
798 return 1;
799}
800
801/**
802 * _base_async_event - main callback handler for firmware asyn events
803 * @ioc: per adapter object
804 * @msix_index: MSIX table index supplied by the OS
805 * @reply: reply message frame(lower 32bit addr)
806 *
807 * Return 1 meaning mf should be freed from _base_interrupt
808 * 0 means the mf is freed from this function.
809 */
810static u8
811_base_async_event(struct MPT3SAS_ADAPTER *ioc, u8 msix_index, u32 reply)
812{
813 Mpi2EventNotificationReply_t *mpi_reply;
814 Mpi2EventAckRequest_t *ack_request;
815 u16 smid;
fd0331b3 816 struct _event_ack_list *delayed_event_ack;
f92363d1
SR		 817
818 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
819 if (!mpi_reply)
820 return 1;
821 if (mpi_reply->Function != MPI2_FUNCTION_EVENT_NOTIFICATION)
822 return 1;
af009411 823
f92363d1 824 _base_display_event_data(ioc, mpi_reply);
af009411 825
f92363d1
SR		 826 if (!(mpi_reply->AckRequired & MPI2_EVENT_NOTIFICATION_ACK_REQUIRED))
827 goto out;
828 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
829 if (!smid) {
fd0331b3
SS		 830 delayed_event_ack = kzalloc(sizeof(*delayed_event_ack),
831 GFP_ATOMIC);
832 if (!delayed_event_ack)
833 goto out;
834 INIT_LIST_HEAD(&delayed_event_ack->list);
835 delayed_event_ack->Event = mpi_reply->Event;
836 delayed_event_ack->EventContext = mpi_reply->EventContext;
837 list_add_tail(&delayed_event_ack->list,
838 &ioc->delayed_event_ack_list);
839 dewtprintk(ioc, pr_info(MPT3SAS_FMT
840 "DELAYED: EVENT ACK: event (0x%04x)\n",
841 ioc->name, le16_to_cpu(mpi_reply->Event)));
f92363d1
SR		 842 goto out;
843 }
844
845 ack_request = mpt3sas_base_get_msg_frame(ioc, smid);
846 memset(ack_request, 0, sizeof(Mpi2EventAckRequest_t));
847 ack_request->Function = MPI2_FUNCTION_EVENT_ACK;
848 ack_request->Event = mpi_reply->Event;
849 ack_request->EventContext = mpi_reply->EventContext;
850 ack_request->VF_ID = 0; /* TODO */
851 ack_request->VP_ID = 0;
852 mpt3sas_base_put_smid_default(ioc, smid);
853
854 out:
855
856 /* scsih callback handler */
857 mpt3sas_scsih_event_callback(ioc, msix_index, reply);
858
859 /* ctl callback handler */
860 mpt3sas_ctl_event_callback(ioc, msix_index, reply);
861
862 return 1;
863}
864
865/**
866 * _base_get_cb_idx - obtain the callback index
867 * @ioc: per adapter object
868 * @smid: system request message index
869 *
870 * Return callback index.
871 */
872static u8
873_base_get_cb_idx(struct MPT3SAS_ADAPTER *ioc, u16 smid)
874{
875 int i;
876 u8 cb_idx;
877
878 if (smid < ioc->hi_priority_smid) {
879 i = smid - 1;
880 cb_idx = ioc->scsi_lookup[i].cb_idx;
881 } else if (smid < ioc->internal_smid) {
882 i = smid - ioc->hi_priority_smid;
883 cb_idx = ioc->hpr_lookup[i].cb_idx;
884 } else if (smid <= ioc->hba_queue_depth) {
885 i = smid - ioc->internal_smid;
886 cb_idx = ioc->internal_lookup[i].cb_idx;
887 } else
888 cb_idx = 0xFF;
889 return cb_idx;
890}
891
892/**
893 * _base_mask_interrupts - disable interrupts
894 * @ioc: per adapter object
895 *
896 * Disabling ResetIRQ, Reply and Doorbell Interrupts
897 *
898 * Return nothing.
899 */
900static void
901_base_mask_interrupts(struct MPT3SAS_ADAPTER *ioc)
902{
903 u32 him_register;
904
905 ioc->mask_interrupts = 1;
906 him_register = readl(&ioc->chip->HostInterruptMask);
907 him_register |= MPI2_HIM_DIM + MPI2_HIM_RIM + MPI2_HIM_RESET_IRQ_MASK;
908 writel(him_register, &ioc->chip->HostInterruptMask);
909 readl(&ioc->chip->HostInterruptMask);
910}
911
912/**
913 * _base_unmask_interrupts - enable interrupts
914 * @ioc: per adapter object
915 *
916 * Enabling only Reply Interrupts
917 *
918 * Return nothing.
919 */
920static void
921_base_unmask_interrupts(struct MPT3SAS_ADAPTER *ioc)
922{
923 u32 him_register;
924
925 him_register = readl(&ioc->chip->HostInterruptMask);
926 him_register &= ~MPI2_HIM_RIM;
927 writel(him_register, &ioc->chip->HostInterruptMask);
928 ioc->mask_interrupts = 0;
929}
930
931union reply_descriptor {
932 u64 word;
933 struct {
934 u32 low;
935 u32 high;
936 } u;
937};
938
939/**
940 * _base_interrupt - MPT adapter (IOC) specific interrupt handler.
941 * @irq: irq number (not used)
942 * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure
943 * @r: pt_regs pointer (not used)
944 *
945 * Return IRQ_HANDLE if processed, else IRQ_NONE.
946 */
947static irqreturn_t
948_base_interrupt(int irq, void *bus_id)
949{
950 struct adapter_reply_queue *reply_q = bus_id;
951 union reply_descriptor rd;
952 u32 completed_cmds;
953 u8 request_desript_type;
954 u16 smid;
955 u8 cb_idx;
956 u32 reply;
957 u8 msix_index = reply_q->msix_index;
958 struct MPT3SAS_ADAPTER *ioc = reply_q->ioc;
959 Mpi2ReplyDescriptorsUnion_t *rpf;
960 u8 rc;
961
962 if (ioc->mask_interrupts)
963 return IRQ_NONE;
964
965 if (!atomic_add_unless(&reply_q->busy, 1, 1))
966 return IRQ_NONE;
967
968 rpf = &reply_q->reply_post_free[reply_q->reply_post_host_index];
969 request_desript_type = rpf->Default.ReplyFlags
970 & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
971 if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) {
972 atomic_dec(&reply_q->busy);
973 return IRQ_NONE;
974 }
975
976 completed_cmds = 0;
977 cb_idx = 0xFF;
978 do {
979 rd.word = le64_to_cpu(rpf->Words);
980 if (rd.u.low == UINT_MAX || rd.u.high == UINT_MAX)
981 goto out;
982 reply = 0;
983 smid = le16_to_cpu(rpf->Default.DescriptorTypeDependent1);
984 if (request_desript_type ==
985 MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS ||
986 request_desript_type ==
987 MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS) {
988 cb_idx = _base_get_cb_idx(ioc, smid);
989 if ((likely(cb_idx < MPT_MAX_CALLBACKS)) &&
990 (likely(mpt_callbacks[cb_idx] != NULL))) {
991 rc = mpt_callbacks[cb_idx](ioc, smid,
992 msix_index, 0);
993 if (rc)
994 mpt3sas_base_free_smid(ioc, smid);
995 }
996 } else if (request_desript_type ==
997 MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) {
998 reply = le32_to_cpu(
999 rpf->AddressReply.ReplyFrameAddress);
1000 if (reply > ioc->reply_dma_max_address ||
1001 reply < ioc->reply_dma_min_address)
1002 reply = 0;
1003 if (smid) {
1004 cb_idx = _base_get_cb_idx(ioc, smid);
1005 if ((likely(cb_idx < MPT_MAX_CALLBACKS)) &&
1006 (likely(mpt_callbacks[cb_idx] != NULL))) {
1007 rc = mpt_callbacks[cb_idx](ioc, smid,
1008 msix_index, reply);
1009 if (reply)
1010 _base_display_reply_info(ioc,
1011 smid, msix_index, reply);
1012 if (rc)
1013 mpt3sas_base_free_smid(ioc,
1014 smid);
1015 }
1016 } else {
1017 _base_async_event(ioc, msix_index, reply);
1018 }
1019
1020 /* reply free queue handling */
1021 if (reply) {
1022 ioc->reply_free_host_index =
1023 (ioc->reply_free_host_index ==
1024 (ioc->reply_free_queue_depth - 1)) ?
1025 0 : ioc->reply_free_host_index + 1;
1026 ioc->reply_free[ioc->reply_free_host_index] =
1027 cpu_to_le32(reply);
1028 wmb();
1029 writel(ioc->reply_free_host_index,
1030 &ioc->chip->ReplyFreeHostIndex);
1031 }
1032 }
1033
1034 rpf->Words = cpu_to_le64(ULLONG_MAX);
1035 reply_q->reply_post_host_index =
1036 (reply_q->reply_post_host_index ==
1037 (ioc->reply_post_queue_depth - 1)) ? 0 :
1038 reply_q->reply_post_host_index + 1;
1039 request_desript_type =
1040 reply_q->reply_post_free[reply_q->reply_post_host_index].
1041 Default.ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
1042 completed_cmds++;
1043 if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED)
1044 goto out;
1045 if (!reply_q->reply_post_host_index)
1046 rpf = reply_q->reply_post_free;
1047 else
1048 rpf++;
1049 } while (1);
1050
1051 out:
1052
1053 if (!completed_cmds) {
1054 atomic_dec(&reply_q->busy);
1055 return IRQ_NONE;
1056 }
1057
1058 wmb();
7786ab6a
SR		 1059 if (ioc->is_warpdrive) {
1060 writel(reply_q->reply_post_host_index,
1061 ioc->reply_post_host_index[msix_index]);
1062 atomic_dec(&reply_q->busy);
1063 return IRQ_HANDLED;
1064 }
fb77bb53
SR		 1065
1066 /* Update Reply Post Host Index.
1067 * For those HBA's which support combined reply queue feature
1068 * 1. Get the correct Supplemental Reply Post Host Index Register.
1069 * i.e. (msix_index / 8)th entry from Supplemental Reply Post Host
1070 * Index Register address bank i.e replyPostRegisterIndex[],
1071 * 2. Then update this register with new reply host index value
1072 * in ReplyPostIndex field and the MSIxIndex field with
1073 * msix_index value reduced to a value between 0 and 7,
1074 * using a modulo 8 operation. Since each Supplemental Reply Post
1075 * Host Index Register supports 8 MSI-X vectors.
1076 *
1077 * For other HBA's just update the Reply Post Host Index register with
1078 * new reply host index value in ReplyPostIndex Field and msix_index
1079 * value in MSIxIndex field.
1080 */
1081 if (ioc->msix96_vector)
1082 writel(reply_q->reply_post_host_index | ((msix_index & 7) <<
1083 MPI2_RPHI_MSIX_INDEX_SHIFT),
1084 ioc->replyPostRegisterIndex[msix_index/8]);
1085 else
1086 writel(reply_q->reply_post_host_index | (msix_index <<
1087 MPI2_RPHI_MSIX_INDEX_SHIFT),
1088 &ioc->chip->ReplyPostHostIndex);
f92363d1
SR		 1089 atomic_dec(&reply_q->busy);
1090 return IRQ_HANDLED;
1091}
1092
1093/**
1094 * _base_is_controller_msix_enabled - is controller support muli-reply queues
1095 * @ioc: per adapter object
1096 *
1097 */
1098static inline int
1099_base_is_controller_msix_enabled(struct MPT3SAS_ADAPTER *ioc)
1100{
1101 return (ioc->facts.IOCCapabilities &
1102 MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX) && ioc->msix_enable;
1103}
1104
1105/**
5f0dfb7a 1106 * mpt3sas_base_sync_reply_irqs - flush pending MSIX interrupts
f92363d1 1107 * @ioc: per adapter object
5f0dfb7a 1108 * Context: non ISR conext
f92363d1 1109 *
5f0dfb7a 1110 * Called when a Task Management request has completed.
f92363d1
SR		 1111 *
1112 * Return nothing.
1113 */
1114void
5f0dfb7a 1115mpt3sas_base_sync_reply_irqs(struct MPT3SAS_ADAPTER *ioc)
f92363d1
SR		 1116{
1117 struct adapter_reply_queue *reply_q;
1118
1119 /* If MSIX capability is turned off
1120 * then multi-queues are not enabled
1121 */
1122 if (!_base_is_controller_msix_enabled(ioc))
1123 return;
1124
1125 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
5f0dfb7a
C		 1126 if (ioc->shost_recovery || ioc->remove_host ||
1127 ioc->pci_error_recovery)
f92363d1
SR		 1128 return;
1129 /* TMs are on msix_index == 0 */
1130 if (reply_q->msix_index == 0)
1131 continue;
5f0dfb7a 1132 synchronize_irq(reply_q->vector);
f92363d1
SR		 1133 }
1134}
1135
1136/**
1137 * mpt3sas_base_release_callback_handler - clear interrupt callback handler
1138 * @cb_idx: callback index
1139 *
1140 * Return nothing.
1141 */
1142void
1143mpt3sas_base_release_callback_handler(u8 cb_idx)
1144{
1145 mpt_callbacks[cb_idx] = NULL;
1146}
1147
1148/**
1149 * mpt3sas_base_register_callback_handler - obtain index for the interrupt callback handler
1150 * @cb_func: callback function
1151 *
1152 * Returns cb_func.
1153 */
1154u8
1155mpt3sas_base_register_callback_handler(MPT_CALLBACK cb_func)
1156{
1157 u8 cb_idx;
1158
1159 for (cb_idx = MPT_MAX_CALLBACKS-1; cb_idx; cb_idx--)
1160 if (mpt_callbacks[cb_idx] == NULL)
1161 break;
1162
1163 mpt_callbacks[cb_idx] = cb_func;
1164 return cb_idx;
1165}
1166
1167/**
1168 * mpt3sas_base_initialize_callback_handler - initialize the interrupt callback handler
1169 *
1170 * Return nothing.
1171 */
1172void
1173mpt3sas_base_initialize_callback_handler(void)
1174{
1175 u8 cb_idx;
1176
1177 for (cb_idx = 0; cb_idx < MPT_MAX_CALLBACKS; cb_idx++)
1178 mpt3sas_base_release_callback_handler(cb_idx);
1179}
1180
1181
1182/**
1183 * _base_build_zero_len_sge - build zero length sg entry
1184 * @ioc: per adapter object
1185 * @paddr: virtual address for SGE
1186 *
1187 * Create a zero length scatter gather entry to insure the IOCs hardware has
1188 * something to use if the target device goes brain dead and tries
1189 * to send data even when none is asked for.
1190 *
1191 * Return nothing.
1192 */
1193static void
1194_base_build_zero_len_sge(struct MPT3SAS_ADAPTER *ioc, void *paddr)
1195{
1196 u32 flags_length = (u32)((MPI2_SGE_FLAGS_LAST_ELEMENT |
1197 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST |
1198 MPI2_SGE_FLAGS_SIMPLE_ELEMENT) <<
1199 MPI2_SGE_FLAGS_SHIFT);
1200 ioc->base_add_sg_single(paddr, flags_length, -1);
1201}
1202
1203/**
1204 * _base_add_sg_single_32 - Place a simple 32 bit SGE at address pAddr.
1205 * @paddr: virtual address for SGE
1206 * @flags_length: SGE flags and data transfer length
1207 * @dma_addr: Physical address
1208 *
1209 * Return nothing.
1210 */
1211static void
1212_base_add_sg_single_32(void *paddr, u32 flags_length, dma_addr_t dma_addr)
1213{
1214 Mpi2SGESimple32_t *sgel = paddr;
1215
1216 flags_length |= (MPI2_SGE_FLAGS_32_BIT_ADDRESSING |
1217 MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
1218 sgel->FlagsLength = cpu_to_le32(flags_length);
1219 sgel->Address = cpu_to_le32(dma_addr);
1220}
1221
1222
1223/**
1224 * _base_add_sg_single_64 - Place a simple 64 bit SGE at address pAddr.
1225 * @paddr: virtual address for SGE
1226 * @flags_length: SGE flags and data transfer length
1227 * @dma_addr: Physical address
1228 *
1229 * Return nothing.
1230 */
1231static void
1232_base_add_sg_single_64(void *paddr, u32 flags_length, dma_addr_t dma_addr)
1233{
1234 Mpi2SGESimple64_t *sgel = paddr;
1235
1236 flags_length |= (MPI2_SGE_FLAGS_64_BIT_ADDRESSING |
1237 MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
1238 sgel->FlagsLength = cpu_to_le32(flags_length);
1239 sgel->Address = cpu_to_le64(dma_addr);
1240}
1241
1242/**
1243 * _base_get_chain_buffer_tracker - obtain chain tracker
1244 * @ioc: per adapter object
1245 * @smid: smid associated to an IO request
1246 *
1247 * Returns chain tracker(from ioc->free_chain_list)
1248 */
1249static struct chain_tracker *
1250_base_get_chain_buffer_tracker(struct MPT3SAS_ADAPTER *ioc, u16 smid)
1251{
1252 struct chain_tracker *chain_req;
1253 unsigned long flags;
1254
1255 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
1256 if (list_empty(&ioc->free_chain_list)) {
1257 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
1258 dfailprintk(ioc, pr_warn(MPT3SAS_FMT
1259 "chain buffers not available\n", ioc->name));
1260 return NULL;
1261 }
1262 chain_req = list_entry(ioc->free_chain_list.next,
1263 struct chain_tracker, tracker_list);
1264 list_del_init(&chain_req->tracker_list);
1265 list_add_tail(&chain_req->tracker_list,
1266 &ioc->scsi_lookup[smid - 1].chain_list);
1267 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
1268 return chain_req;
1269}
1270
1271
1272/**
1273 * _base_build_sg - build generic sg
1274 * @ioc: per adapter object
1275 * @psge: virtual address for SGE
1276 * @data_out_dma: physical address for WRITES
1277 * @data_out_sz: data xfer size for WRITES
1278 * @data_in_dma: physical address for READS
1279 * @data_in_sz: data xfer size for READS
1280 *
1281 * Return nothing.
1282 */
1283static void
1284_base_build_sg(struct MPT3SAS_ADAPTER *ioc, void *psge,
1285 dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
1286 size_t data_in_sz)
1287{
1288 u32 sgl_flags;
1289
1290 if (!data_out_sz && !data_in_sz) {
1291 _base_build_zero_len_sge(ioc, psge);
1292 return;
1293 }
1294
1295 if (data_out_sz && data_in_sz) {
1296 /* WRITE sgel first */
1297 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1298 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_HOST_TO_IOC);
1299 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1300 ioc->base_add_sg_single(psge, sgl_flags |
1301 data_out_sz, data_out_dma);
1302
1303 /* incr sgel */
1304 psge += ioc->sge_size;
1305
1306 /* READ sgel last */
1307 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1308 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
1309 MPI2_SGE_FLAGS_END_OF_LIST);
1310 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1311 ioc->base_add_sg_single(psge, sgl_flags |
1312 data_in_sz, data_in_dma);
1313 } else if (data_out_sz) /* WRITE */ {
1314 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1315 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
1316 MPI2_SGE_FLAGS_END_OF_LIST | MPI2_SGE_FLAGS_HOST_TO_IOC);
1317 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1318 ioc->base_add_sg_single(psge, sgl_flags |
1319 data_out_sz, data_out_dma);
1320 } else if (data_in_sz) /* READ */ {
1321 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1322 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
1323 MPI2_SGE_FLAGS_END_OF_LIST);
1324 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1325 ioc->base_add_sg_single(psge, sgl_flags |
1326 data_in_sz, data_in_dma);
1327 }
1328}
1329
1330/* IEEE format sgls */
1331
1332/**
1333 * _base_add_sg_single_ieee - add sg element for IEEE format
1334 * @paddr: virtual address for SGE
1335 * @flags: SGE flags
1336 * @chain_offset: number of 128 byte elements from start of segment
1337 * @length: data transfer length
1338 * @dma_addr: Physical address
1339 *
1340 * Return nothing.
1341 */
1342static void
1343_base_add_sg_single_ieee(void *paddr, u8 flags, u8 chain_offset, u32 length,
1344 dma_addr_t dma_addr)
1345{
1346 Mpi25IeeeSgeChain64_t *sgel = paddr;
1347
1348 sgel->Flags = flags;
1349 sgel->NextChainOffset = chain_offset;
1350 sgel->Length = cpu_to_le32(length);
1351 sgel->Address = cpu_to_le64(dma_addr);
1352}
1353
1354/**
1355 * _base_build_zero_len_sge_ieee - build zero length sg entry for IEEE format
1356 * @ioc: per adapter object
1357 * @paddr: virtual address for SGE
1358 *
1359 * Create a zero length scatter gather entry to insure the IOCs hardware has
1360 * something to use if the target device goes brain dead and tries
1361 * to send data even when none is asked for.
1362 *
1363 * Return nothing.
1364 */
1365static void
1366_base_build_zero_len_sge_ieee(struct MPT3SAS_ADAPTER *ioc, void *paddr)
1367{
1368 u8 sgl_flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1369 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR |
1370 MPI25_IEEE_SGE_FLAGS_END_OF_LIST);
b130b0d5 1371
f92363d1
SR		 1372 _base_add_sg_single_ieee(paddr, sgl_flags, 0, 0, -1);
1373}
1374
471ef9d4
SR		 1375/**
1376 * _base_build_sg_scmd - main sg creation routine
1377 * @ioc: per adapter object
1378 * @scmd: scsi command
1379 * @smid: system request message index
1380 * Context: none.
1381 *
1382 * The main routine that builds scatter gather table from a given
1383 * scsi request sent via the .queuecommand main handler.
1384 *
1385 * Returns 0 success, anything else error
1386 */
1387static int
1388_base_build_sg_scmd(struct MPT3SAS_ADAPTER *ioc,
1389 struct scsi_cmnd *scmd, u16 smid)
1390{
1391 Mpi2SCSIIORequest_t *mpi_request;
1392 dma_addr_t chain_dma;
1393 struct scatterlist *sg_scmd;
1394 void *sg_local, *chain;
1395 u32 chain_offset;
1396 u32 chain_length;
1397 u32 chain_flags;
1398 int sges_left;
1399 u32 sges_in_segment;
1400 u32 sgl_flags;
1401 u32 sgl_flags_last_element;
1402 u32 sgl_flags_end_buffer;
1403 struct chain_tracker *chain_req;
1404
1405 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
1406
1407 /* init scatter gather flags */
1408 sgl_flags = MPI2_SGE_FLAGS_SIMPLE_ELEMENT;
1409 if (scmd->sc_data_direction == DMA_TO_DEVICE)
1410 sgl_flags |= MPI2_SGE_FLAGS_HOST_TO_IOC;
1411 sgl_flags_last_element = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT)
1412 << MPI2_SGE_FLAGS_SHIFT;
1413 sgl_flags_end_buffer = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT |
1414 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST)
1415 << MPI2_SGE_FLAGS_SHIFT;
1416 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1417
1418 sg_scmd = scsi_sglist(scmd);
1419 sges_left = scsi_dma_map(scmd);
1420 if (sges_left < 0) {
1421 sdev_printk(KERN_ERR, scmd->device,
1422 "pci_map_sg failed: request for %d bytes!\n",
1423 scsi_bufflen(scmd));
1424 return -ENOMEM;
1425 }
1426
1427 sg_local = &mpi_request->SGL;
1428 sges_in_segment = ioc->max_sges_in_main_message;
1429 if (sges_left <= sges_in_segment)
1430 goto fill_in_last_segment;
1431
1432 mpi_request->ChainOffset = (offsetof(Mpi2SCSIIORequest_t, SGL) +
1433 (sges_in_segment * ioc->sge_size))/4;
1434
1435 /* fill in main message segment when there is a chain following */
1436 while (sges_in_segment) {
1437 if (sges_in_segment == 1)
1438 ioc->base_add_sg_single(sg_local,
1439 sgl_flags_last_element | sg_dma_len(sg_scmd),
1440 sg_dma_address(sg_scmd));
1441 else
1442 ioc->base_add_sg_single(sg_local, sgl_flags |
1443 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1444 sg_scmd = sg_next(sg_scmd);
1445 sg_local += ioc->sge_size;
1446 sges_left--;
1447 sges_in_segment--;
1448 }
1449
1450 /* initializing the chain flags and pointers */
1451 chain_flags = MPI2_SGE_FLAGS_CHAIN_ELEMENT << MPI2_SGE_FLAGS_SHIFT;
1452 chain_req = _base_get_chain_buffer_tracker(ioc, smid);
1453 if (!chain_req)
1454 return -1;
1455 chain = chain_req->chain_buffer;
1456 chain_dma = chain_req->chain_buffer_dma;
1457 do {
1458 sges_in_segment = (sges_left <=
1459 ioc->max_sges_in_chain_message) ? sges_left :
1460 ioc->max_sges_in_chain_message;
1461 chain_offset = (sges_left == sges_in_segment) ?
1462 0 : (sges_in_segment * ioc->sge_size)/4;
1463 chain_length = sges_in_segment * ioc->sge_size;
1464 if (chain_offset) {
1465 chain_offset = chain_offset <<
1466 MPI2_SGE_CHAIN_OFFSET_SHIFT;
1467 chain_length += ioc->sge_size;
1468 }
1469 ioc->base_add_sg_single(sg_local, chain_flags | chain_offset |
1470 chain_length, chain_dma);
1471 sg_local = chain;
1472 if (!chain_offset)
1473 goto fill_in_last_segment;
1474
1475 /* fill in chain segments */
1476 while (sges_in_segment) {
1477 if (sges_in_segment == 1)
1478 ioc->base_add_sg_single(sg_local,
1479 sgl_flags_last_element |
1480 sg_dma_len(sg_scmd),
1481 sg_dma_address(sg_scmd));
1482 else
1483 ioc->base_add_sg_single(sg_local, sgl_flags |
1484 sg_dma_len(sg_scmd),
1485 sg_dma_address(sg_scmd));
1486 sg_scmd = sg_next(sg_scmd);
1487 sg_local += ioc->sge_size;
1488 sges_left--;
1489 sges_in_segment--;
1490 }
1491
1492 chain_req = _base_get_chain_buffer_tracker(ioc, smid);
1493 if (!chain_req)
1494 return -1;
1495 chain = chain_req->chain_buffer;
1496 chain_dma = chain_req->chain_buffer_dma;
1497 } while (1);
1498
1499
1500 fill_in_last_segment:
1501
1502 /* fill the last segment */
1503 while (sges_left) {
1504 if (sges_left == 1)
1505 ioc->base_add_sg_single(sg_local, sgl_flags_end_buffer |
1506 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1507 else
1508 ioc->base_add_sg_single(sg_local, sgl_flags |
1509 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1510 sg_scmd = sg_next(sg_scmd);
1511 sg_local += ioc->sge_size;
1512 sges_left--;
1513 }
1514
1515 return 0;
1516}
1517
f92363d1
SR		 1518/**
1519 * _base_build_sg_scmd_ieee - main sg creation routine for IEEE format
1520 * @ioc: per adapter object
1521 * @scmd: scsi command
1522 * @smid: system request message index
1523 * Context: none.
1524 *
1525 * The main routine that builds scatter gather table from a given
1526 * scsi request sent via the .queuecommand main handler.
1527 *
1528 * Returns 0 success, anything else error
1529 */
1530static int
1531_base_build_sg_scmd_ieee(struct MPT3SAS_ADAPTER *ioc,
1532 struct scsi_cmnd *scmd, u16 smid)
1533{
1534 Mpi2SCSIIORequest_t *mpi_request;
1535 dma_addr_t chain_dma;
1536 struct scatterlist *sg_scmd;
1537 void *sg_local, *chain;
1538 u32 chain_offset;
1539 u32 chain_length;
f92363d1
SR		 1540 int sges_left;
1541 u32 sges_in_segment;
1542 u8 simple_sgl_flags;
1543 u8 simple_sgl_flags_last;
1544 u8 chain_sgl_flags;
1545 struct chain_tracker *chain_req;
1546
1547 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
1548
1549 /* init scatter gather flags */
1550 simple_sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1551 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1552 simple_sgl_flags_last = simple_sgl_flags |
1553 MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
1554 chain_sgl_flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
1555 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1556
1557 sg_scmd = scsi_sglist(scmd);
1558 sges_left = scsi_dma_map(scmd);
62f5c74c 1559 if (sges_left < 0) {
f92363d1
SR		 1560 sdev_printk(KERN_ERR, scmd->device,
1561 "pci_map_sg failed: request for %d bytes!\n",
1562 scsi_bufflen(scmd));
1563 return -ENOMEM;
1564 }
1565
1566 sg_local = &mpi_request->SGL;
1567 sges_in_segment = (ioc->request_sz -
1568 offsetof(Mpi2SCSIIORequest_t, SGL))/ioc->sge_size_ieee;
1569 if (sges_left <= sges_in_segment)
1570 goto fill_in_last_segment;
1571
1572 mpi_request->ChainOffset = (sges_in_segment - 1 /* chain element */) +
1573 (offsetof(Mpi2SCSIIORequest_t, SGL)/ioc->sge_size_ieee);
1574
1575 /* fill in main message segment when there is a chain following */
1576 while (sges_in_segment > 1) {
1577 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
1578 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1579 sg_scmd = sg_next(sg_scmd);
1580 sg_local += ioc->sge_size_ieee;
1581 sges_left--;
1582 sges_in_segment--;
1583 }
1584
25ef16d0 1585 /* initializing the pointers */
f92363d1
SR		 1586 chain_req = _base_get_chain_buffer_tracker(ioc, smid);
1587 if (!chain_req)
1588 return -1;
1589 chain = chain_req->chain_buffer;
1590 chain_dma = chain_req->chain_buffer_dma;
1591 do {
1592 sges_in_segment = (sges_left <=
1593 ioc->max_sges_in_chain_message) ? sges_left :
1594 ioc->max_sges_in_chain_message;
1595 chain_offset = (sges_left == sges_in_segment) ?
1596 0 : sges_in_segment;
1597 chain_length = sges_in_segment * ioc->sge_size_ieee;
1598 if (chain_offset)
1599 chain_length += ioc->sge_size_ieee;
1600 _base_add_sg_single_ieee(sg_local, chain_sgl_flags,
1601 chain_offset, chain_length, chain_dma);
1602
1603 sg_local = chain;
1604 if (!chain_offset)
1605 goto fill_in_last_segment;
1606
1607 /* fill in chain segments */
1608 while (sges_in_segment) {
1609 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
1610 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1611 sg_scmd = sg_next(sg_scmd);
1612 sg_local += ioc->sge_size_ieee;
1613 sges_left--;
1614 sges_in_segment--;
1615 }
1616
1617 chain_req = _base_get_chain_buffer_tracker(ioc, smid);
1618 if (!chain_req)
1619 return -1;
1620 chain = chain_req->chain_buffer;
1621 chain_dma = chain_req->chain_buffer_dma;
1622 } while (1);
1623
1624
1625 fill_in_last_segment:
1626
1627 /* fill the last segment */
62f5c74c 1628 while (sges_left > 0) {
f92363d1
SR		 1629 if (sges_left == 1)
1630 _base_add_sg_single_ieee(sg_local,
1631 simple_sgl_flags_last, 0, sg_dma_len(sg_scmd),
1632 sg_dma_address(sg_scmd));
1633 else
1634 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
1635 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1636 sg_scmd = sg_next(sg_scmd);
1637 sg_local += ioc->sge_size_ieee;
1638 sges_left--;
1639 }
1640
1641 return 0;
1642}
1643
1644/**
1645 * _base_build_sg_ieee - build generic sg for IEEE format
1646 * @ioc: per adapter object
1647 * @psge: virtual address for SGE
1648 * @data_out_dma: physical address for WRITES
1649 * @data_out_sz: data xfer size for WRITES
1650 * @data_in_dma: physical address for READS
1651 * @data_in_sz: data xfer size for READS
1652 *
1653 * Return nothing.
1654 */
1655static void
1656_base_build_sg_ieee(struct MPT3SAS_ADAPTER *ioc, void *psge,
1657 dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
1658 size_t data_in_sz)
1659{
1660 u8 sgl_flags;
1661
1662 if (!data_out_sz && !data_in_sz) {
1663 _base_build_zero_len_sge_ieee(ioc, psge);
1664 return;
1665 }
1666
1667 if (data_out_sz && data_in_sz) {
1668 /* WRITE sgel first */
1669 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1670 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1671 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz,
1672 data_out_dma);
1673
1674 /* incr sgel */
1675 psge += ioc->sge_size_ieee;
1676
1677 /* READ sgel last */
1678 sgl_flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
1679 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz,
1680 data_in_dma);
1681 } else if (data_out_sz) /* WRITE */ {
1682 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1683 MPI25_IEEE_SGE_FLAGS_END_OF_LIST |
1684 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1685 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz,
1686 data_out_dma);
1687 } else if (data_in_sz) /* READ */ {
1688 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1689 MPI25_IEEE_SGE_FLAGS_END_OF_LIST |
1690 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1691 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz,
1692 data_in_dma);
1693 }
1694}
1695
1696#define convert_to_kb(x) ((x) << (PAGE_SHIFT - 10))
1697
1698/**
1699 * _base_config_dma_addressing - set dma addressing
1700 * @ioc: per adapter object
1701 * @pdev: PCI device struct
1702 *
1703 * Returns 0 for success, non-zero for failure.
1704 */
1705static int
1706_base_config_dma_addressing(struct MPT3SAS_ADAPTER *ioc, struct pci_dev *pdev)
1707{
1708 struct sysinfo s;
9b05c91a
SR		 1709 u64 consistent_dma_mask;
1710
1711 if (ioc->dma_mask)
1712 consistent_dma_mask = DMA_BIT_MASK(64);
1713 else
1714 consistent_dma_mask = DMA_BIT_MASK(32);
f92363d1
SR		 1715
1716 if (sizeof(dma_addr_t) > 4) {
1717 const uint64_t required_mask =
1718 dma_get_required_mask(&pdev->dev);
1719 if ((required_mask > DMA_BIT_MASK(32)) &&
1720 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
9b05c91a 1721 !pci_set_consistent_dma_mask(pdev, consistent_dma_mask)) {
f92363d1
SR		 1722 ioc->base_add_sg_single = &_base_add_sg_single_64;
1723 ioc->sge_size = sizeof(Mpi2SGESimple64_t);
9b05c91a 1724 ioc->dma_mask = 64;
f92363d1
SR		 1725 goto out;
1726 }
1727 }
1728
1729 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))
1730 && !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
1731 ioc->base_add_sg_single = &_base_add_sg_single_32;
1732 ioc->sge_size = sizeof(Mpi2SGESimple32_t);
9b05c91a 1733 ioc->dma_mask = 32;
f92363d1
SR		 1734 } else
1735 return -ENODEV;
1736
1737 out:
1738 si_meminfo(&s);
1739 pr_info(MPT3SAS_FMT
9b05c91a
SR		 1740 "%d BIT PCI BUS DMA ADDRESSING SUPPORTED, total mem (%ld kB)\n",
1741 ioc->name, ioc->dma_mask, convert_to_kb(s.totalram));
1742
1743 return 0;
1744}
f92363d1 1745
9b05c91a
SR		 1746static int
1747_base_change_consistent_dma_mask(struct MPT3SAS_ADAPTER *ioc,
1748 struct pci_dev *pdev)
1749{
1750 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
1751 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
1752 return -ENODEV;
1753 }
f92363d1
SR		 1754 return 0;
1755}
1756
1757/**
1758 * _base_check_enable_msix - checks MSIX capabable.
1759 * @ioc: per adapter object
1760 *
1761 * Check to see if card is capable of MSIX, and set number
1762 * of available msix vectors
1763 */
1764static int
1765_base_check_enable_msix(struct MPT3SAS_ADAPTER *ioc)
1766{
1767 int base;
1768 u16 message_control;
1769
42081173
SR		 1770 /* Check whether controller SAS2008 B0 controller,
1771 * if it is SAS2008 B0 controller use IO-APIC instead of MSIX
1772 */
1773 if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 &&
1774 ioc->pdev->revision == SAS2_PCI_DEVICE_B0_REVISION) {
1775 return -EINVAL;
1776 }
1777
f92363d1
SR		 1778 base = pci_find_capability(ioc->pdev, PCI_CAP_ID_MSIX);
1779 if (!base) {
1780 dfailprintk(ioc, pr_info(MPT3SAS_FMT "msix not supported\n",
1781 ioc->name));
1782 return -EINVAL;
1783 }
1784
1785 /* get msix vector count */
42081173
SR		 1786 /* NUMA_IO not supported for older controllers */
1787 if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2004 ||
1788 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 ||
1789 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_1 ||
1790 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_2 ||
1791 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_3 ||
1792 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_1 ||
1793 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_2)
1794 ioc->msix_vector_count = 1;
1795 else {
1796 pci_read_config_word(ioc->pdev, base + 2, &message_control);
1797 ioc->msix_vector_count = (message_control & 0x3FF) + 1;
1798 }
f92363d1
SR		 1799 dinitprintk(ioc, pr_info(MPT3SAS_FMT
1800 "msix is supported, vector_count(%d)\n",
1801 ioc->name, ioc->msix_vector_count));
1802 return 0;
1803}
1804
1805/**
1806 * _base_free_irq - free irq
1807 * @ioc: per adapter object
1808 *
1809 * Freeing respective reply_queue from the list.
1810 */
1811static void
1812_base_free_irq(struct MPT3SAS_ADAPTER *ioc)
1813{
1814 struct adapter_reply_queue *reply_q, *next;
1815
1816 if (list_empty(&ioc->reply_queue_list))
1817 return;
1818
1819 list_for_each_entry_safe(reply_q, next, &ioc->reply_queue_list, list) {
1820 list_del(&reply_q->list);
64038301
SPS		 1821 if (smp_affinity_enable) {
1822 irq_set_affinity_hint(reply_q->vector, NULL);
1823 free_cpumask_var(reply_q->affinity_hint);
1824 }
f92363d1
SR		 1825 free_irq(reply_q->vector, reply_q);
1826 kfree(reply_q);
1827 }
1828}
1829
1830/**
1831 * _base_request_irq - request irq
1832 * @ioc: per adapter object
1833 * @index: msix index into vector table
1834 * @vector: irq vector
1835 *
1836 * Inserting respective reply_queue into the list.
1837 */
1838static int
1839_base_request_irq(struct MPT3SAS_ADAPTER *ioc, u8 index, u32 vector)
1840{
1841 struct adapter_reply_queue *reply_q;
1842 int r;
1843
1844 reply_q = kzalloc(sizeof(struct adapter_reply_queue), GFP_KERNEL);
1845 if (!reply_q) {
1846 pr_err(MPT3SAS_FMT "unable to allocate memory %d!\n",
1847 ioc->name, (int)sizeof(struct adapter_reply_queue));
1848 return -ENOMEM;
1849 }
1850 reply_q->ioc = ioc;
1851 reply_q->msix_index = index;
1852 reply_q->vector = vector;
14b3114d 1853
64038301
SPS		 1854 if (smp_affinity_enable) {
1855 if (!zalloc_cpumask_var(&reply_q->affinity_hint, GFP_KERNEL)) {
1856 kfree(reply_q);
1857 return -ENOMEM;
1858 }
64038301 1859 }
14b3114d 1860
f92363d1
SR		 1861 atomic_set(&reply_q->busy, 0);
1862 if (ioc->msix_enable)
1863 snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d-msix%d",
c84b06a4 1864 ioc->driver_name, ioc->id, index);
f92363d1
SR		 1865 else
1866 snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d",
c84b06a4 1867 ioc->driver_name, ioc->id);
f92363d1
SR		 1868 r = request_irq(vector, _base_interrupt, IRQF_SHARED, reply_q->name,
1869 reply_q);
1870 if (r) {
1871 pr_err(MPT3SAS_FMT "unable to allocate interrupt %d!\n",
1872 reply_q->name, vector);
64038301 1873 free_cpumask_var(reply_q->affinity_hint);
da3cec25 1874 kfree(reply_q);
f92363d1
SR		 1875 return -EBUSY;
1876 }
1877
1878 INIT_LIST_HEAD(&reply_q->list);
1879 list_add_tail(&reply_q->list, &ioc->reply_queue_list);
1880 return 0;
1881}
1882
1883/**
1884 * _base_assign_reply_queues - assigning msix index for each cpu
1885 * @ioc: per adapter object
1886 *
1887 * The enduser would need to set the affinity via /proc/irq/#/smp_affinity
1888 *
1889 * It would nice if we could call irq_set_affinity, however it is not
1890 * an exported symbol
1891 */
1892static void
1893_base_assign_reply_queues(struct MPT3SAS_ADAPTER *ioc)
1894{
91b265bf 1895 unsigned int cpu, nr_cpus, nr_msix, index = 0;
14b3114d 1896 struct adapter_reply_queue *reply_q;
f92363d1
SR		 1897
1898 if (!_base_is_controller_msix_enabled(ioc))
1899 return;
1900
1901 memset(ioc->cpu_msix_table, 0, ioc->cpu_msix_table_sz);
1902
91b265bf
MP		 1903 nr_cpus = num_online_cpus();
1904 nr_msix = ioc->reply_queue_count = min(ioc->reply_queue_count,
1905 ioc->facts.MaxMSIxVectors);
1906 if (!nr_msix)
1907 return;
f92363d1 1908
91b265bf
MP		 1909 cpu = cpumask_first(cpu_online_mask);
1910
14b3114d
SR		 1911 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
1912
91b265bf
MP		 1913 unsigned int i, group = nr_cpus / nr_msix;
1914
14b3114d
SR		 1915 if (cpu >= nr_cpus)
1916 break;
1917
91b265bf
MP		 1918 if (index < nr_cpus % nr_msix)
1919 group++;
1920
1921 for (i = 0 ; i < group ; i++) {
1922 ioc->cpu_msix_table[cpu] = index;
64038301
SPS		 1923 if (smp_affinity_enable)
1924 cpumask_or(reply_q->affinity_hint,
14b3114d 1925 reply_q->affinity_hint, get_cpu_mask(cpu));
91b265bf 1926 cpu = cpumask_next(cpu, cpu_online_mask);
f92363d1 1927 }
64038301
SPS		 1928 if (smp_affinity_enable)
1929 if (irq_set_affinity_hint(reply_q->vector,
14b3114d 1930 reply_q->affinity_hint))
64038301
SPS		 1931 dinitprintk(ioc, pr_info(MPT3SAS_FMT
1932 "Err setting affinity hint to irq vector %d\n",
1933 ioc->name, reply_q->vector));
91b265bf 1934 index++;
14b3114d 1935 }
f92363d1
SR		 1936}
1937
1938/**
1939 * _base_disable_msix - disables msix
1940 * @ioc: per adapter object
1941 *
1942 */
1943static void
1944_base_disable_msix(struct MPT3SAS_ADAPTER *ioc)
1945{
1946 if (!ioc->msix_enable)
1947 return;
1948 pci_disable_msix(ioc->pdev);
1949 ioc->msix_enable = 0;
1950}
1951
1952/**
1953 * _base_enable_msix - enables msix, failback to io_apic
1954 * @ioc: per adapter object
1955 *
1956 */
1957static int
1958_base_enable_msix(struct MPT3SAS_ADAPTER *ioc)
1959{
1960 struct msix_entry *entries, *a;
1961 int r;
1962 int i;
1963 u8 try_msix = 0;
1964
f92363d1
SR		 1965 if (msix_disable == -1 || msix_disable == 0)
1966 try_msix = 1;
1967
1968 if (!try_msix)
1969 goto try_ioapic;
1970
1971 if (_base_check_enable_msix(ioc) != 0)
1972 goto try_ioapic;
1973
1974 ioc->reply_queue_count = min_t(int, ioc->cpu_count,
1975 ioc->msix_vector_count);
1976
9c500060
SR		 1977 printk(MPT3SAS_FMT "MSI-X vectors supported: %d, no of cores"
1978 ": %d, max_msix_vectors: %d\n", ioc->name, ioc->msix_vector_count,
1979 ioc->cpu_count, max_msix_vectors);
1980
9b05c91a
SR		 1981 if (!ioc->rdpq_array_enable && max_msix_vectors == -1)
1982 max_msix_vectors = 8;
1983
9c500060
SR		 1984 if (max_msix_vectors > 0) {
1985 ioc->reply_queue_count = min_t(int, max_msix_vectors,
1986 ioc->reply_queue_count);
1987 ioc->msix_vector_count = ioc->reply_queue_count;
9b05c91a
SR		 1988 } else if (max_msix_vectors == 0)
1989 goto try_ioapic;
9c500060 1990
64038301
SPS		 1991 if (ioc->msix_vector_count < ioc->cpu_count)
1992 smp_affinity_enable = 0;
1993
f92363d1
SR		 1994 entries = kcalloc(ioc->reply_queue_count, sizeof(struct msix_entry),
1995 GFP_KERNEL);
1996 if (!entries) {
1997 dfailprintk(ioc, pr_info(MPT3SAS_FMT
1998 "kcalloc failed @ at %s:%d/%s() !!!\n",
1999 ioc->name, __FILE__, __LINE__, __func__));
2000 goto try_ioapic;
2001 }
2002
2003 for (i = 0, a = entries; i < ioc->reply_queue_count; i++, a++)
2004 a->entry = i;
2005
6bfa6907 2006 r = pci_enable_msix_exact(ioc->pdev, entries, ioc->reply_queue_count);
f92363d1
SR		 2007 if (r) {
2008 dfailprintk(ioc, pr_info(MPT3SAS_FMT
6bfa6907 2009 "pci_enable_msix_exact failed (r=%d) !!!\n",
f92363d1
SR		 2010 ioc->name, r));
2011 kfree(entries);
2012 goto try_ioapic;
2013 }
2014
2015 ioc->msix_enable = 1;
2016 for (i = 0, a = entries; i < ioc->reply_queue_count; i++, a++) {
2017 r = _base_request_irq(ioc, i, a->vector);
2018 if (r) {
2019 _base_free_irq(ioc);
2020 _base_disable_msix(ioc);
2021 kfree(entries);
2022 goto try_ioapic;
2023 }
2024 }
2025
2026 kfree(entries);
2027 return 0;
2028
2029/* failback to io_apic interrupt routing */
2030 try_ioapic:
2031
9b05c91a 2032 ioc->reply_queue_count = 1;
f92363d1
SR		 2033 r = _base_request_irq(ioc, 0, ioc->pdev->irq);
2034
2035 return r;
2036}
2037
580d4e31
SR		 2038/**
2039 * mpt3sas_base_unmap_resources - free controller resources
2040 * @ioc: per adapter object
2041 */
2042void
2043mpt3sas_base_unmap_resources(struct MPT3SAS_ADAPTER *ioc)
2044{
2045 struct pci_dev *pdev = ioc->pdev;
2046
2047 dexitprintk(ioc, printk(MPT3SAS_FMT "%s\n",
2048 ioc->name, __func__));
2049
2050 _base_free_irq(ioc);
2051 _base_disable_msix(ioc);
2052
5f985d88 2053 if (ioc->msix96_vector) {
580d4e31 2054 kfree(ioc->replyPostRegisterIndex);
5f985d88
TH		 2055 ioc->replyPostRegisterIndex = NULL;
2056 }
580d4e31
SR		 2057
2058 if (ioc->chip_phys) {
2059 iounmap(ioc->chip);
2060 ioc->chip_phys = 0;
2061 }
2062
2063 if (pci_is_enabled(pdev)) {
2064 pci_release_selected_regions(ioc->pdev, ioc->bars);
2065 pci_disable_pcie_error_reporting(pdev);
2066 pci_disable_device(pdev);
2067 }
2068}
2069
f92363d1
SR		 2070/**
2071 * mpt3sas_base_map_resources - map in controller resources (io/irq/memap)
2072 * @ioc: per adapter object
2073 *
2074 * Returns 0 for success, non-zero for failure.
2075 */
2076int
2077mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc)
2078{
2079 struct pci_dev *pdev = ioc->pdev;
2080 u32 memap_sz;
2081 u32 pio_sz;
2082 int i, r = 0;
2083 u64 pio_chip = 0;
2084 u64 chip_phys = 0;
2085 struct adapter_reply_queue *reply_q;
2086
2087 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n",
2088 ioc->name, __func__));
2089
2090 ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
2091 if (pci_enable_device_mem(pdev)) {
2092 pr_warn(MPT3SAS_FMT "pci_enable_device_mem: failed\n",
2093 ioc->name);
cf9bd21a 2094 ioc->bars = 0;
f92363d1
SR		 2095 return -ENODEV;
2096 }
2097
2098
2099 if (pci_request_selected_regions(pdev, ioc->bars,
c84b06a4 2100 ioc->driver_name)) {
f92363d1
SR		 2101 pr_warn(MPT3SAS_FMT "pci_request_selected_regions: failed\n",
2102 ioc->name);
cf9bd21a 2103 ioc->bars = 0;
f92363d1
SR		 2104 r = -ENODEV;
2105 goto out_fail;
2106 }
2107
2108/* AER (Advanced Error Reporting) hooks */
2109 pci_enable_pcie_error_reporting(pdev);
2110
2111 pci_set_master(pdev);
2112
2113
2114 if (_base_config_dma_addressing(ioc, pdev) != 0) {
2115 pr_warn(MPT3SAS_FMT "no suitable DMA mask for %s\n",
2116 ioc->name, pci_name(pdev));
2117 r = -ENODEV;
2118 goto out_fail;
2119 }
2120
5aeeb78a
SR		 2121 for (i = 0, memap_sz = 0, pio_sz = 0; (i < DEVICE_COUNT_RESOURCE) &&
2122 (!memap_sz || !pio_sz); i++) {
f92363d1
SR		 2123 if (pci_resource_flags(pdev, i) & IORESOURCE_IO) {
2124 if (pio_sz)
2125 continue;
2126 pio_chip = (u64)pci_resource_start(pdev, i);
2127 pio_sz = pci_resource_len(pdev, i);
2128 } else if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
2129 if (memap_sz)
2130 continue;
2131 ioc->chip_phys = pci_resource_start(pdev, i);
2132 chip_phys = (u64)ioc->chip_phys;
2133 memap_sz = pci_resource_len(pdev, i);
2134 ioc->chip = ioremap(ioc->chip_phys, memap_sz);
f92363d1
SR		 2135 }
2136 }
2137
5aeeb78a
SR		 2138 if (ioc->chip == NULL) {
2139 pr_err(MPT3SAS_FMT "unable to map adapter memory! "
2140 " or resource not found\n", ioc->name);
2141 r = -EINVAL;
2142 goto out_fail;
2143 }
2144
f92363d1 2145 _base_mask_interrupts(ioc);
9b05c91a 2146
98c56ad3 2147 r = _base_get_ioc_facts(ioc);
9b05c91a
SR		 2148 if (r)
2149 goto out_fail;
2150
2151 if (!ioc->rdpq_array_enable_assigned) {
2152 ioc->rdpq_array_enable = ioc->rdpq_array_capable;
2153 ioc->rdpq_array_enable_assigned = 1;
2154 }
2155
f92363d1
SR		 2156 r = _base_enable_msix(ioc);
2157 if (r)
2158 goto out_fail;
2159
fb77bb53
SR		 2160 /* Use the Combined reply queue feature only for SAS3 C0 & higher
2161 * revision HBAs and also only when reply queue count is greater than 8
2162 */
2163 if (ioc->msix96_vector && ioc->reply_queue_count > 8) {
2164 /* Determine the Supplemental Reply Post Host Index Registers
2165 * Addresse. Supplemental Reply Post Host Index Registers
2166 * starts at offset MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET and
2167 * each register is at offset bytes of
2168 * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET from previous one.
2169 */
2170 ioc->replyPostRegisterIndex = kcalloc(
2171 MPT3_SUP_REPLY_POST_HOST_INDEX_REG_COUNT,
2172 sizeof(resource_size_t *), GFP_KERNEL);
2173 if (!ioc->replyPostRegisterIndex) {
2174 dfailprintk(ioc, printk(MPT3SAS_FMT
2175 "allocation for reply Post Register Index failed!!!\n",
2176 ioc->name));
2177 r = -ENOMEM;
2178 goto out_fail;
2179 }
2180
2181 for (i = 0; i < MPT3_SUP_REPLY_POST_HOST_INDEX_REG_COUNT; i++) {
2182 ioc->replyPostRegisterIndex[i] = (resource_size_t *)
2183 ((u8 *)&ioc->chip->Doorbell +
2184 MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET +
2185 (i * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET));
2186 }
2187 } else
2188 ioc->msix96_vector = 0;
2189
f92363d1
SR		 2190 list_for_each_entry(reply_q, &ioc->reply_queue_list, list)
2191 pr_info(MPT3SAS_FMT "%s: IRQ %d\n",
2192 reply_q->name, ((ioc->msix_enable) ? "PCI-MSI-X enabled" :
2193 "IO-APIC enabled"), reply_q->vector);
2194
2195 pr_info(MPT3SAS_FMT "iomem(0x%016llx), mapped(0x%p), size(%d)\n",
2196 ioc->name, (unsigned long long)chip_phys, ioc->chip, memap_sz);
2197 pr_info(MPT3SAS_FMT "ioport(0x%016llx), size(%d)\n",
2198 ioc->name, (unsigned long long)pio_chip, pio_sz);
2199
2200 /* Save PCI configuration state for recovery from PCI AER/EEH errors */
2201 pci_save_state(pdev);
2202 return 0;
2203
2204 out_fail:
580d4e31 2205 mpt3sas_base_unmap_resources(ioc);
f92363d1
SR		 2206 return r;
2207}
2208
2209/**
2210 * mpt3sas_base_get_msg_frame - obtain request mf pointer
2211 * @ioc: per adapter object
2212 * @smid: system request message index(smid zero is invalid)
2213 *
2214 * Returns virt pointer to message frame.
2215 */
2216void *
2217mpt3sas_base_get_msg_frame(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2218{
2219 return (void *)(ioc->request + (smid * ioc->request_sz));
2220}
2221
2222/**
2223 * mpt3sas_base_get_sense_buffer - obtain a sense buffer virt addr
2224 * @ioc: per adapter object
2225 * @smid: system request message index
2226 *
2227 * Returns virt pointer to sense buffer.
2228 */
2229void *
2230mpt3sas_base_get_sense_buffer(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2231{
2232 return (void *)(ioc->sense + ((smid - 1) * SCSI_SENSE_BUFFERSIZE));
2233}
2234
2235/**
2236 * mpt3sas_base_get_sense_buffer_dma - obtain a sense buffer dma addr
2237 * @ioc: per adapter object
2238 * @smid: system request message index
2239 *
2240 * Returns phys pointer to the low 32bit address of the sense buffer.
2241 */
2242__le32
2243mpt3sas_base_get_sense_buffer_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2244{
2245 return cpu_to_le32(ioc->sense_dma + ((smid - 1) *
2246 SCSI_SENSE_BUFFERSIZE));
2247}
2248
2249/**
2250 * mpt3sas_base_get_reply_virt_addr - obtain reply frames virt address
2251 * @ioc: per adapter object
2252 * @phys_addr: lower 32 physical addr of the reply
2253 *
2254 * Converts 32bit lower physical addr into a virt address.
2255 */
2256void *
2257mpt3sas_base_get_reply_virt_addr(struct MPT3SAS_ADAPTER *ioc, u32 phys_addr)
2258{
2259 if (!phys_addr)
2260 return NULL;
2261 return ioc->reply + (phys_addr - (u32)ioc->reply_dma);
2262}
2263
03d1fb3a
SS		 2264static inline u8
2265_base_get_msix_index(struct MPT3SAS_ADAPTER *ioc)
2266{
2267 return ioc->cpu_msix_table[raw_smp_processor_id()];
2268}
2269
f92363d1
SR		 2270/**
2271 * mpt3sas_base_get_smid - obtain a free smid from internal queue
2272 * @ioc: per adapter object
2273 * @cb_idx: callback index
2274 *
2275 * Returns smid (zero is invalid)
2276 */
2277u16
2278mpt3sas_base_get_smid(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx)
2279{
2280 unsigned long flags;
2281 struct request_tracker *request;
2282 u16 smid;
2283
2284 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2285 if (list_empty(&ioc->internal_free_list)) {
2286 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2287 pr_err(MPT3SAS_FMT "%s: smid not available\n",
2288 ioc->name, __func__);
2289 return 0;
2290 }
2291
2292 request = list_entry(ioc->internal_free_list.next,
2293 struct request_tracker, tracker_list);
2294 request->cb_idx = cb_idx;
2295 smid = request->smid;
2296 list_del(&request->tracker_list);
2297 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2298 return smid;
2299}
2300
2301/**
2302 * mpt3sas_base_get_smid_scsiio - obtain a free smid from scsiio queue
2303 * @ioc: per adapter object
2304 * @cb_idx: callback index
2305 * @scmd: pointer to scsi command object
2306 *
2307 * Returns smid (zero is invalid)
2308 */
2309u16
2310mpt3sas_base_get_smid_scsiio(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx,
2311 struct scsi_cmnd *scmd)
2312{
2313 unsigned long flags;
2314 struct scsiio_tracker *request;
2315 u16 smid;
2316
2317 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2318 if (list_empty(&ioc->free_list)) {
2319 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2320 pr_err(MPT3SAS_FMT "%s: smid not available\n",
2321 ioc->name, __func__);
2322 return 0;
2323 }
2324
2325 request = list_entry(ioc->free_list.next,
2326 struct scsiio_tracker, tracker_list);
2327 request->scmd = scmd;
2328 request->cb_idx = cb_idx;
2329 smid = request->smid;
03d1fb3a 2330 request->msix_io = _base_get_msix_index(ioc);
f92363d1
SR		 2331 list_del(&request->tracker_list);
2332 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2333 return smid;
2334}
2335
2336/**
2337 * mpt3sas_base_get_smid_hpr - obtain a free smid from hi-priority queue
2338 * @ioc: per adapter object
2339 * @cb_idx: callback index
2340 *
2341 * Returns smid (zero is invalid)
2342 */
2343u16
2344mpt3sas_base_get_smid_hpr(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx)
2345{
2346 unsigned long flags;
2347 struct request_tracker *request;
2348 u16 smid;
2349
2350 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2351 if (list_empty(&ioc->hpr_free_list)) {
2352 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2353 return 0;
2354 }
2355
2356 request = list_entry(ioc->hpr_free_list.next,
2357 struct request_tracker, tracker_list);
2358 request->cb_idx = cb_idx;
2359 smid = request->smid;
2360 list_del(&request->tracker_list);
2361 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2362 return smid;
2363}
2364
2365/**
2366 * mpt3sas_base_free_smid - put smid back on free_list
2367 * @ioc: per adapter object
2368 * @smid: system request message index
2369 *
2370 * Return nothing.
2371 */
2372void
2373mpt3sas_base_free_smid(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2374{
2375 unsigned long flags;
2376 int i;
2377 struct chain_tracker *chain_req, *next;
2378
2379 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2380 if (smid < ioc->hi_priority_smid) {
2381 /* scsiio queue */
2382 i = smid - 1;
2383 if (!list_empty(&ioc->scsi_lookup[i].chain_list)) {
2384 list_for_each_entry_safe(chain_req, next,
2385 &ioc->scsi_lookup[i].chain_list, tracker_list) {
2386 list_del_init(&chain_req->tracker_list);
2387 list_add(&chain_req->tracker_list,
2388 &ioc->free_chain_list);
2389 }
2390 }
2391 ioc->scsi_lookup[i].cb_idx = 0xFF;
2392 ioc->scsi_lookup[i].scmd = NULL;
7786ab6a 2393 ioc->scsi_lookup[i].direct_io = 0;
f92363d1
SR		 2394 list_add(&ioc->scsi_lookup[i].tracker_list, &ioc->free_list);
2395 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2396
2397 /*
2398 * See _wait_for_commands_to_complete() call with regards
2399 * to this code.
2400 */
2401 if (ioc->shost_recovery && ioc->pending_io_count) {
2402 if (ioc->pending_io_count == 1)
2403 wake_up(&ioc->reset_wq);
2404 ioc->pending_io_count--;
2405 }
2406 return;
2407 } else if (smid < ioc->internal_smid) {
2408 /* hi-priority */
2409 i = smid - ioc->hi_priority_smid;
2410 ioc->hpr_lookup[i].cb_idx = 0xFF;
2411 list_add(&ioc->hpr_lookup[i].tracker_list, &ioc->hpr_free_list);
2412 } else if (smid <= ioc->hba_queue_depth) {
2413 /* internal queue */
2414 i = smid - ioc->internal_smid;
2415 ioc->internal_lookup[i].cb_idx = 0xFF;
2416 list_add(&ioc->internal_lookup[i].tracker_list,
2417 &ioc->internal_free_list);
2418 }
2419 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2420}
2421
2422/**
2423 * _base_writeq - 64 bit write to MMIO
2424 * @ioc: per adapter object
2425 * @b: data payload
2426 * @addr: address in MMIO space
2427 * @writeq_lock: spin lock
2428 *
2429 * Glue for handling an atomic 64 bit word to MMIO. This special handling takes
2430 * care of 32 bit environment where its not quarenteed to send the entire word
2431 * in one transfer.
2432 */
2433#if defined(writeq) && defined(CONFIG_64BIT)
2434static inline void
2435_base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock)
2436{
2437 writeq(cpu_to_le64(b), addr);
2438}
2439#else
2440static inline void
2441_base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock)
2442{
2443 unsigned long flags;
2444 __u64 data_out = cpu_to_le64(b);
2445
2446 spin_lock_irqsave(writeq_lock, flags);
2447 writel((u32)(data_out), addr);
2448 writel((u32)(data_out >> 32), (addr + 4));
2449 spin_unlock_irqrestore(writeq_lock, flags);
2450}
2451#endif
2452
f92363d1
SR		 2453/**
2454 * mpt3sas_base_put_smid_scsi_io - send SCSI_IO request to firmware
2455 * @ioc: per adapter object
2456 * @smid: system request message index
2457 * @handle: device handle
2458 *
2459 * Return nothing.
2460 */
2461void
2462mpt3sas_base_put_smid_scsi_io(struct MPT3SAS_ADAPTER *ioc, u16 smid, u16 handle)
2463{
2464 Mpi2RequestDescriptorUnion_t descriptor;
2465 u64 *request = (u64 *)&descriptor;
2466
2467
2468 descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
2469 descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc);
2470 descriptor.SCSIIO.SMID = cpu_to_le16(smid);
2471 descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
2472 descriptor.SCSIIO.LMID = 0;
2473 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2474 &ioc->scsi_lookup_lock);
2475}
2476
2477/**
2478 * mpt3sas_base_put_smid_fast_path - send fast path request to firmware
2479 * @ioc: per adapter object
2480 * @smid: system request message index
2481 * @handle: device handle
2482 *
2483 * Return nothing.
2484 */
2485void
2486mpt3sas_base_put_smid_fast_path(struct MPT3SAS_ADAPTER *ioc, u16 smid,
2487 u16 handle)
2488{
2489 Mpi2RequestDescriptorUnion_t descriptor;
2490 u64 *request = (u64 *)&descriptor;
2491
2492 descriptor.SCSIIO.RequestFlags =
2493 MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO;
2494 descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc);
2495 descriptor.SCSIIO.SMID = cpu_to_le16(smid);
2496 descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
2497 descriptor.SCSIIO.LMID = 0;
2498 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2499 &ioc->scsi_lookup_lock);
2500}
2501
2502/**
2503 * mpt3sas_base_put_smid_hi_priority - send Task Managment request to firmware
2504 * @ioc: per adapter object
2505 * @smid: system request message index
03d1fb3a 2506 * @msix_task: msix_task will be same as msix of IO incase of task abort else 0.
f92363d1
SR		 2507 * Return nothing.
2508 */
2509void
03d1fb3a
SS		 2510mpt3sas_base_put_smid_hi_priority(struct MPT3SAS_ADAPTER *ioc, u16 smid,
2511 u16 msix_task)
f92363d1
SR		 2512{
2513 Mpi2RequestDescriptorUnion_t descriptor;
2514 u64 *request = (u64 *)&descriptor;
2515
2516 descriptor.HighPriority.RequestFlags =
2517 MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY;
03d1fb3a 2518 descriptor.HighPriority.MSIxIndex = msix_task;
f92363d1
SR		 2519 descriptor.HighPriority.SMID = cpu_to_le16(smid);
2520 descriptor.HighPriority.LMID = 0;
2521 descriptor.HighPriority.Reserved1 = 0;
2522 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2523 &ioc->scsi_lookup_lock);
2524}
2525
2526/**
2527 * mpt3sas_base_put_smid_default - Default, primarily used for config pages
2528 * @ioc: per adapter object
2529 * @smid: system request message index
2530 *
2531 * Return nothing.
2532 */
2533void
2534mpt3sas_base_put_smid_default(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2535{
2536 Mpi2RequestDescriptorUnion_t descriptor;
2537 u64 *request = (u64 *)&descriptor;
2538
2539 descriptor.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
2540 descriptor.Default.MSIxIndex = _base_get_msix_index(ioc);
2541 descriptor.Default.SMID = cpu_to_le16(smid);
2542 descriptor.Default.LMID = 0;
2543 descriptor.Default.DescriptorTypeDependent = 0;
2544 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2545 &ioc->scsi_lookup_lock);
2546}
2547
1117b31a 2548/**
989e43c7 2549 * _base_display_OEMs_branding - Display branding string
1117b31a
SR		 2550 * @ioc: per adapter object
2551 *
2552 * Return nothing.
2553 */
2554static void
989e43c7 2555_base_display_OEMs_branding(struct MPT3SAS_ADAPTER *ioc)
1117b31a
SR		 2556{
2557 if (ioc->pdev->subsystem_vendor != PCI_VENDOR_ID_INTEL)
2558 return;
2559
989e43c7
SR		 2560 switch (ioc->pdev->subsystem_vendor) {
2561 case PCI_VENDOR_ID_INTEL:
2562 switch (ioc->pdev->device) {
2563 case MPI2_MFGPAGE_DEVID_SAS2008:
2564 switch (ioc->pdev->subsystem_device) {
2565 case MPT2SAS_INTEL_RMS2LL080_SSDID:
2566 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2567 MPT2SAS_INTEL_RMS2LL080_BRANDING);
2568 break;
2569 case MPT2SAS_INTEL_RMS2LL040_SSDID:
2570 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2571 MPT2SAS_INTEL_RMS2LL040_BRANDING);
2572 break;
2573 case MPT2SAS_INTEL_SSD910_SSDID:
2574 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2575 MPT2SAS_INTEL_SSD910_BRANDING);
2576 break;
2577 default:
2578 pr_info(MPT3SAS_FMT
2579 "Intel(R) Controller: Subsystem ID: 0x%X\n",
2580 ioc->name, ioc->pdev->subsystem_device);
2581 break;
2582 }
2583 case MPI2_MFGPAGE_DEVID_SAS2308_2:
2584 switch (ioc->pdev->subsystem_device) {
2585 case MPT2SAS_INTEL_RS25GB008_SSDID:
2586 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2587 MPT2SAS_INTEL_RS25GB008_BRANDING);
2588 break;
2589 case MPT2SAS_INTEL_RMS25JB080_SSDID:
2590 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2591 MPT2SAS_INTEL_RMS25JB080_BRANDING);
2592 break;
2593 case MPT2SAS_INTEL_RMS25JB040_SSDID:
2594 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2595 MPT2SAS_INTEL_RMS25JB040_BRANDING);
2596 break;
2597 case MPT2SAS_INTEL_RMS25KB080_SSDID:
2598 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2599 MPT2SAS_INTEL_RMS25KB080_BRANDING);
2600 break;
2601 case MPT2SAS_INTEL_RMS25KB040_SSDID:
2602 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2603 MPT2SAS_INTEL_RMS25KB040_BRANDING);
2604 break;
2605 case MPT2SAS_INTEL_RMS25LB040_SSDID:
2606 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2607 MPT2SAS_INTEL_RMS25LB040_BRANDING);
2608 break;
2609 case MPT2SAS_INTEL_RMS25LB080_SSDID:
2610 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2611 MPT2SAS_INTEL_RMS25LB080_BRANDING);
2612 break;
2613 default:
2614 pr_info(MPT3SAS_FMT
2615 "Intel(R) Controller: Subsystem ID: 0x%X\n",
2616 ioc->name, ioc->pdev->subsystem_device);
2617 break;
2618 }
2619 case MPI25_MFGPAGE_DEVID_SAS3008:
2620 switch (ioc->pdev->subsystem_device) {
2621 case MPT3SAS_INTEL_RMS3JC080_SSDID:
2622 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2623 MPT3SAS_INTEL_RMS3JC080_BRANDING);
2624 break;
2625
2626 case MPT3SAS_INTEL_RS3GC008_SSDID:
2627 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2628 MPT3SAS_INTEL_RS3GC008_BRANDING);
2629 break;
2630 case MPT3SAS_INTEL_RS3FC044_SSDID:
2631 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2632 MPT3SAS_INTEL_RS3FC044_BRANDING);
2633 break;
2634 case MPT3SAS_INTEL_RS3UC080_SSDID:
2635 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2636 MPT3SAS_INTEL_RS3UC080_BRANDING);
2637 break;
2638 default:
2639 pr_info(MPT3SAS_FMT
2640 "Intel(R) Controller: Subsystem ID: 0x%X\n",
2641 ioc->name, ioc->pdev->subsystem_device);
2642 break;
2643 }
1117b31a
SR		 2644 break;
2645 default:
2646 pr_info(MPT3SAS_FMT
989e43c7
SR		 2647 "Intel(R) Controller: Subsystem ID: 0x%X\n",
2648 ioc->name, ioc->pdev->subsystem_device);
1117b31a
SR		 2649 break;
2650 }
2651 break;
989e43c7
SR		 2652 case PCI_VENDOR_ID_DELL:
2653 switch (ioc->pdev->device) {
2654 case MPI2_MFGPAGE_DEVID_SAS2008:
2655 switch (ioc->pdev->subsystem_device) {
2656 case MPT2SAS_DELL_6GBPS_SAS_HBA_SSDID:
2657 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2658 MPT2SAS_DELL_6GBPS_SAS_HBA_BRANDING);
2659 break;
2660 case MPT2SAS_DELL_PERC_H200_ADAPTER_SSDID:
2661 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2662 MPT2SAS_DELL_PERC_H200_ADAPTER_BRANDING);
2663 break;
2664 case MPT2SAS_DELL_PERC_H200_INTEGRATED_SSDID:
2665 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2666 MPT2SAS_DELL_PERC_H200_INTEGRATED_BRANDING);
2667 break;
2668 case MPT2SAS_DELL_PERC_H200_MODULAR_SSDID:
2669 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2670 MPT2SAS_DELL_PERC_H200_MODULAR_BRANDING);
2671 break;
2672 case MPT2SAS_DELL_PERC_H200_EMBEDDED_SSDID:
2673 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2674 MPT2SAS_DELL_PERC_H200_EMBEDDED_BRANDING);
2675 break;
2676 case MPT2SAS_DELL_PERC_H200_SSDID:
2677 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2678 MPT2SAS_DELL_PERC_H200_BRANDING);
2679 break;
2680 case MPT2SAS_DELL_6GBPS_SAS_SSDID:
2681 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2682 MPT2SAS_DELL_6GBPS_SAS_BRANDING);
2683 break;
2684 default:
2685 pr_info(MPT3SAS_FMT
2686 "Dell 6Gbps HBA: Subsystem ID: 0x%X\n",
2687 ioc->name, ioc->pdev->subsystem_device);
2688 break;
2689 }
2690 break;
2691 case MPI25_MFGPAGE_DEVID_SAS3008:
2692 switch (ioc->pdev->subsystem_device) {
2693 case MPT3SAS_DELL_12G_HBA_SSDID:
2694 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2695 MPT3SAS_DELL_12G_HBA_BRANDING);
2696 break;
2697 default:
2698 pr_info(MPT3SAS_FMT
2699 "Dell 12Gbps HBA: Subsystem ID: 0x%X\n",
2700 ioc->name, ioc->pdev->subsystem_device);
2701 break;
2702 }
fb84dfc4
SR		 2703 break;
2704 default:
2705 pr_info(MPT3SAS_FMT
989e43c7 2706 "Dell HBA: Subsystem ID: 0x%X\n", ioc->name,
fb84dfc4
SR		 2707 ioc->pdev->subsystem_device);
2708 break;
2709 }
2710 break;
989e43c7
SR		 2711 case PCI_VENDOR_ID_CISCO:
2712 switch (ioc->pdev->device) {
2713 case MPI25_MFGPAGE_DEVID_SAS3008:
2714 switch (ioc->pdev->subsystem_device) {
2715 case MPT3SAS_CISCO_12G_8E_HBA_SSDID:
2716 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2717 MPT3SAS_CISCO_12G_8E_HBA_BRANDING);
2718 break;
2719 case MPT3SAS_CISCO_12G_8I_HBA_SSDID:
2720 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2721 MPT3SAS_CISCO_12G_8I_HBA_BRANDING);
2722 break;
2723 case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID:
2724 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2725 MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING);
2726 break;
2727 default:
2728 pr_info(MPT3SAS_FMT
2729 "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n",
2730 ioc->name, ioc->pdev->subsystem_device);
2731 break;
2732 }
d8eb4a47 2733 break;
989e43c7
SR		 2734 case MPI25_MFGPAGE_DEVID_SAS3108_1:
2735 switch (ioc->pdev->subsystem_device) {
2736 case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID:
2737 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
d8eb4a47 2738 MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING);
989e43c7
SR		 2739 break;
2740 case MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_SSDID:
2741 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2742 MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_BRANDING
2743 );
2744 break;
2745 default:
2746 pr_info(MPT3SAS_FMT
2747 "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n",
2748 ioc->name, ioc->pdev->subsystem_device);
2749 break;
2750 }
38e4141e
SR		 2751 break;
2752 default:
2753 pr_info(MPT3SAS_FMT
989e43c7
SR		 2754 "Cisco SAS HBA: Subsystem ID: 0x%X\n",
2755 ioc->name, ioc->pdev->subsystem_device);
38e4141e
SR		 2756 break;
2757 }
2758 break;
989e43c7
SR		 2759 case MPT2SAS_HP_3PAR_SSVID:
2760 switch (ioc->pdev->device) {
2761 case MPI2_MFGPAGE_DEVID_SAS2004:
2762 switch (ioc->pdev->subsystem_device) {
2763 case MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_SSDID:
2764 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2765 MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_BRANDING);
2766 break;
2767 default:
2768 pr_info(MPT3SAS_FMT
2769 "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n",
2770 ioc->name, ioc->pdev->subsystem_device);
2771 break;
2772 }
2773 case MPI2_MFGPAGE_DEVID_SAS2308_2:
2774 switch (ioc->pdev->subsystem_device) {
2775 case MPT2SAS_HP_2_4_INTERNAL_SSDID:
2776 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2777 MPT2SAS_HP_2_4_INTERNAL_BRANDING);
2778 break;
2779 case MPT2SAS_HP_2_4_EXTERNAL_SSDID:
2780 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2781 MPT2SAS_HP_2_4_EXTERNAL_BRANDING);
2782 break;
2783 case MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_SSDID:
2784 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2785 MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_BRANDING);
2786 break;
2787 case MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_SSDID:
2788 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2789 MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_BRANDING);
2790 break;
2791 default:
2792 pr_info(MPT3SAS_FMT
2793 "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n",
2794 ioc->name, ioc->pdev->subsystem_device);
2795 break;
2796 }
d8eb4a47
SR		 2797 default:
2798 pr_info(MPT3SAS_FMT
989e43c7
SR		 2799 "HP SAS HBA: Subsystem ID: 0x%X\n",
2800 ioc->name, ioc->pdev->subsystem_device);
d8eb4a47
SR		 2801 break;
2802 }
38e4141e 2803 default:
38e4141e
SR		 2804 break;
2805 }
2806}
fb84dfc4 2807
f92363d1
SR		 2808/**
2809 * _base_display_ioc_capabilities - Disply IOC's capabilities.
2810 * @ioc: per adapter object
2811 *
2812 * Return nothing.
2813 */
2814static void
2815_base_display_ioc_capabilities(struct MPT3SAS_ADAPTER *ioc)
2816{
2817 int i = 0;
2818 char desc[16];
2819 u32 iounit_pg1_flags;
2820 u32 bios_version;
2821
2822 bios_version = le32_to_cpu(ioc->bios_pg3.BiosVersion);
2823 strncpy(desc, ioc->manu_pg0.ChipName, 16);
2824 pr_info(MPT3SAS_FMT "%s: FWVersion(%02d.%02d.%02d.%02d), "\
2825 "ChipRevision(0x%02x), BiosVersion(%02d.%02d.%02d.%02d)\n",
2826 ioc->name, desc,
2827 (ioc->facts.FWVersion.Word & 0xFF000000) >> 24,
2828 (ioc->facts.FWVersion.Word & 0x00FF0000) >> 16,
2829 (ioc->facts.FWVersion.Word & 0x0000FF00) >> 8,
2830 ioc->facts.FWVersion.Word & 0x000000FF,
2831 ioc->pdev->revision,
2832 (bios_version & 0xFF000000) >> 24,
2833 (bios_version & 0x00FF0000) >> 16,
2834 (bios_version & 0x0000FF00) >> 8,
2835 bios_version & 0x000000FF);
2836
989e43c7 2837 _base_display_OEMs_branding(ioc);
1117b31a 2838
f92363d1
SR		 2839 pr_info(MPT3SAS_FMT "Protocol=(", ioc->name);
2840
2841 if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR) {
2842 pr_info("Initiator");
2843 i++;
2844 }
2845
2846 if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET) {
2847 pr_info("%sTarget", i ? "," : "");
2848 i++;
2849 }
2850
2851 i = 0;
2852 pr_info("), ");
2853 pr_info("Capabilities=(");
2854
7786ab6a
SR		 2855 if (!ioc->hide_ir_msg) {
2856 if (ioc->facts.IOCCapabilities &
f92363d1
SR		 2857 MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID) {
2858 pr_info("Raid");
2859 i++;
7786ab6a 2860 }
f92363d1
SR		 2861 }
2862
2863 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_TLR) {
2864 pr_info("%sTLR", i ? "," : "");
2865 i++;
2866 }
2867
2868 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_MULTICAST) {
2869 pr_info("%sMulticast", i ? "," : "");
2870 i++;
2871 }
2872
2873 if (ioc->facts.IOCCapabilities &
2874 MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET) {
2875 pr_info("%sBIDI Target", i ? "," : "");
2876 i++;
2877 }
2878
2879 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_EEDP) {
2880 pr_info("%sEEDP", i ? "," : "");
2881 i++;
2882 }
2883
2884 if (ioc->facts.IOCCapabilities &
2885 MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER) {
2886 pr_info("%sSnapshot Buffer", i ? "," : "");
2887 i++;
2888 }
2889
2890 if (ioc->facts.IOCCapabilities &
2891 MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER) {
2892 pr_info("%sDiag Trace Buffer", i ? "," : "");
2893 i++;
2894 }
2895
2896 if (ioc->facts.IOCCapabilities &
2897 MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER) {
2898 pr_info("%sDiag Extended Buffer", i ? "," : "");
2899 i++;
2900 }
2901
2902 if (ioc->facts.IOCCapabilities &
2903 MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING) {
2904 pr_info("%sTask Set Full", i ? "," : "");
2905 i++;
2906 }
2907
2908 iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
2909 if (!(iounit_pg1_flags & MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE)) {
2910 pr_info("%sNCQ", i ? "," : "");
2911 i++;
2912 }
2913
2914 pr_info(")\n");
2915}
2916
2917/**
2918 * mpt3sas_base_update_missing_delay - change the missing delay timers
2919 * @ioc: per adapter object
2920 * @device_missing_delay: amount of time till device is reported missing
2921 * @io_missing_delay: interval IO is returned when there is a missing device
2922 *
2923 * Return nothing.
2924 *
2925 * Passed on the command line, this function will modify the device missing
2926 * delay, as well as the io missing delay. This should be called at driver
2927 * load time.
2928 */
2929void
2930mpt3sas_base_update_missing_delay(struct MPT3SAS_ADAPTER *ioc,
2931 u16 device_missing_delay, u8 io_missing_delay)
2932{
2933 u16 dmd, dmd_new, dmd_orignal;
2934 u8 io_missing_delay_original;
2935 u16 sz;
2936 Mpi2SasIOUnitPage1_t *sas_iounit_pg1 = NULL;
2937 Mpi2ConfigReply_t mpi_reply;
2938 u8 num_phys = 0;
2939 u16 ioc_status;
2940
2941 mpt3sas_config_get_number_hba_phys(ioc, &num_phys);
2942 if (!num_phys)
2943 return;
2944
2945 sz = offsetof(Mpi2SasIOUnitPage1_t, PhyData) + (num_phys *
2946 sizeof(Mpi2SasIOUnit1PhyData_t));
2947 sas_iounit_pg1 = kzalloc(sz, GFP_KERNEL);
2948 if (!sas_iounit_pg1) {
2949 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
2950 ioc->name, __FILE__, __LINE__, __func__);
2951 goto out;
2952 }
2953 if ((mpt3sas_config_get_sas_iounit_pg1(ioc, &mpi_reply,
2954 sas_iounit_pg1, sz))) {
2955 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
2956 ioc->name, __FILE__, __LINE__, __func__);
2957 goto out;
2958 }
2959 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
2960 MPI2_IOCSTATUS_MASK;
2961 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
2962 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
2963 ioc->name, __FILE__, __LINE__, __func__);
2964 goto out;
2965 }
2966
2967 /* device missing delay */
2968 dmd = sas_iounit_pg1->ReportDeviceMissingDelay;
2969 if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16)
2970 dmd = (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16;
2971 else
2972 dmd = dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
2973 dmd_orignal = dmd;
2974 if (device_missing_delay > 0x7F) {
2975 dmd = (device_missing_delay > 0x7F0) ? 0x7F0 :
2976 device_missing_delay;
2977 dmd = dmd / 16;
2978 dmd |= MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16;
2979 } else
2980 dmd = device_missing_delay;
2981 sas_iounit_pg1->ReportDeviceMissingDelay = dmd;
2982
2983 /* io missing delay */
2984 io_missing_delay_original = sas_iounit_pg1->IODeviceMissingDelay;
2985 sas_iounit_pg1->IODeviceMissingDelay = io_missing_delay;
2986
2987 if (!mpt3sas_config_set_sas_iounit_pg1(ioc, &mpi_reply, sas_iounit_pg1,
2988 sz)) {
2989 if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16)
2990 dmd_new = (dmd &
2991 MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16;
2992 else
2993 dmd_new =
2994 dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
2995 pr_info(MPT3SAS_FMT "device_missing_delay: old(%d), new(%d)\n",
2996 ioc->name, dmd_orignal, dmd_new);
2997 pr_info(MPT3SAS_FMT "ioc_missing_delay: old(%d), new(%d)\n",
2998 ioc->name, io_missing_delay_original,
2999 io_missing_delay);
3000 ioc->device_missing_delay = dmd_new;
3001 ioc->io_missing_delay = io_missing_delay;
3002 }
3003
3004out:
3005 kfree(sas_iounit_pg1);
3006}
3007/**
3008 * _base_static_config_pages - static start of day config pages
3009 * @ioc: per adapter object
3010 *
3011 * Return nothing.
3012 */
3013static void
3014_base_static_config_pages(struct MPT3SAS_ADAPTER *ioc)
3015{
3016 Mpi2ConfigReply_t mpi_reply;
3017 u32 iounit_pg1_flags;
3018
3019 mpt3sas_config_get_manufacturing_pg0(ioc, &mpi_reply, &ioc->manu_pg0);
3020 if (ioc->ir_firmware)
3021 mpt3sas_config_get_manufacturing_pg10(ioc, &mpi_reply,
3022 &ioc->manu_pg10);
3023
3024 /*
3025 * Ensure correct T10 PI operation if vendor left EEDPTagMode
3026 * flag unset in NVDATA.
3027 */
3028 mpt3sas_config_get_manufacturing_pg11(ioc, &mpi_reply, &ioc->manu_pg11);
3029 if (ioc->manu_pg11.EEDPTagMode == 0) {
3030 pr_err("%s: overriding NVDATA EEDPTagMode setting\n",
3031 ioc->name);
3032 ioc->manu_pg11.EEDPTagMode &= ~0x3;
3033 ioc->manu_pg11.EEDPTagMode |= 0x1;
3034 mpt3sas_config_set_manufacturing_pg11(ioc, &mpi_reply,
3035 &ioc->manu_pg11);
3036 }
3037
3038 mpt3sas_config_get_bios_pg2(ioc, &mpi_reply, &ioc->bios_pg2);
3039 mpt3sas_config_get_bios_pg3(ioc, &mpi_reply, &ioc->bios_pg3);
3040 mpt3sas_config_get_ioc_pg8(ioc, &mpi_reply, &ioc->ioc_pg8);
3041 mpt3sas_config_get_iounit_pg0(ioc, &mpi_reply, &ioc->iounit_pg0);
3042 mpt3sas_config_get_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
2d8ce8c9 3043 mpt3sas_config_get_iounit_pg8(ioc, &mpi_reply, &ioc->iounit_pg8);
f92363d1
SR		 3044 _base_display_ioc_capabilities(ioc);
3045
3046 /*
3047 * Enable task_set_full handling in iounit_pg1 when the
3048 * facts capabilities indicate that its supported.
3049 */
3050 iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
3051 if ((ioc->facts.IOCCapabilities &
3052 MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING))
3053 iounit_pg1_flags &=
3054 ~MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
3055 else
3056 iounit_pg1_flags |=
3057 MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
3058 ioc->iounit_pg1.Flags = cpu_to_le32(iounit_pg1_flags);
3059 mpt3sas_config_set_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
2d8ce8c9
SR		 3060
3061 if (ioc->iounit_pg8.NumSensors)
3062 ioc->temp_sensors_count = ioc->iounit_pg8.NumSensors;
f92363d1
SR		 3063}
3064
3065/**
3066 * _base_release_memory_pools - release memory
3067 * @ioc: per adapter object
3068 *
3069 * Free memory allocated from _base_allocate_memory_pools.
3070 *
3071 * Return nothing.
3072 */
3073static void
3074_base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc)
3075{
9b05c91a
SR		 3076 int i = 0;
3077 struct reply_post_struct *rps;
f92363d1
SR		 3078
3079 dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3080 __func__));
3081
3082 if (ioc->request) {
3083 pci_free_consistent(ioc->pdev, ioc->request_dma_sz,
3084 ioc->request, ioc->request_dma);
3085 dexitprintk(ioc, pr_info(MPT3SAS_FMT
3086 "request_pool(0x%p): free\n",
3087 ioc->name, ioc->request));
3088 ioc->request = NULL;
3089 }
3090
3091 if (ioc->sense) {
3092 pci_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma);
3093 if (ioc->sense_dma_pool)
3094 pci_pool_destroy(ioc->sense_dma_pool);
3095 dexitprintk(ioc, pr_info(MPT3SAS_FMT
3096 "sense_pool(0x%p): free\n",
3097 ioc->name, ioc->sense));
3098 ioc->sense = NULL;
3099 }
3100
3101 if (ioc->reply) {
3102 pci_pool_free(ioc->reply_dma_pool, ioc->reply, ioc->reply_dma);
3103 if (ioc->reply_dma_pool)
3104 pci_pool_destroy(ioc->reply_dma_pool);
3105 dexitprintk(ioc, pr_info(MPT3SAS_FMT
3106 "reply_pool(0x%p): free\n",
3107 ioc->name, ioc->reply));
3108 ioc->reply = NULL;
3109 }
3110
3111 if (ioc->reply_free) {
3112 pci_pool_free(ioc->reply_free_dma_pool, ioc->reply_free,
3113 ioc->reply_free_dma);
3114 if (ioc->reply_free_dma_pool)
3115 pci_pool_destroy(ioc->reply_free_dma_pool);
3116 dexitprintk(ioc, pr_info(MPT3SAS_FMT
3117 "reply_free_pool(0x%p): free\n",
3118 ioc->name, ioc->reply_free));
3119 ioc->reply_free = NULL;
3120 }
3121
9b05c91a
SR		 3122 if (ioc->reply_post) {
3123 do {
3124 rps = &ioc->reply_post[i];
3125 if (rps->reply_post_free) {
3126 pci_pool_free(
3127 ioc->reply_post_free_dma_pool,
3128 rps->reply_post_free,
3129 rps->reply_post_free_dma);
3130 dexitprintk(ioc, pr_info(MPT3SAS_FMT
3131 "reply_post_free_pool(0x%p): free\n",
3132 ioc->name, rps->reply_post_free));
3133 rps->reply_post_free = NULL;
3134 }
3135 } while (ioc->rdpq_array_enable &&
3136 (++i < ioc->reply_queue_count));
3137
f92363d1
SR		 3138 if (ioc->reply_post_free_dma_pool)
3139 pci_pool_destroy(ioc->reply_post_free_dma_pool);
9b05c91a 3140 kfree(ioc->reply_post);
f92363d1
SR		 3141 }
3142
3143 if (ioc->config_page) {
3144 dexitprintk(ioc, pr_info(MPT3SAS_FMT
3145 "config_page(0x%p): free\n", ioc->name,
3146 ioc->config_page));
3147 pci_free_consistent(ioc->pdev, ioc->config_page_sz,
3148 ioc->config_page, ioc->config_page_dma);
3149 }
3150
3151 if (ioc->scsi_lookup) {
3152 free_pages((ulong)ioc->scsi_lookup, ioc->scsi_lookup_pages);
3153 ioc->scsi_lookup = NULL;
3154 }
3155 kfree(ioc->hpr_lookup);
3156 kfree(ioc->internal_lookup);
3157 if (ioc->chain_lookup) {
3158 for (i = 0; i < ioc->chain_depth; i++) {
3159 if (ioc->chain_lookup[i].chain_buffer)
3160 pci_pool_free(ioc->chain_dma_pool,
3161 ioc->chain_lookup[i].chain_buffer,
3162 ioc->chain_lookup[i].chain_buffer_dma);
3163 }
3164 if (ioc->chain_dma_pool)
3165 pci_pool_destroy(ioc->chain_dma_pool);
3166 free_pages((ulong)ioc->chain_lookup, ioc->chain_pages);
3167 ioc->chain_lookup = NULL;
3168 }
3169}
3170
3171/**
3172 * _base_allocate_memory_pools - allocate start of day memory pools
3173 * @ioc: per adapter object
f92363d1
SR		 3174 *
3175 * Returns 0 success, anything else error
3176 */
3177static int
98c56ad3 3178_base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc)
f92363d1
SR		 3179{
3180 struct mpt3sas_facts *facts;
3181 u16 max_sge_elements;
3182 u16 chains_needed_per_io;
3183 u32 sz, total_sz, reply_post_free_sz;
3184 u32 retry_sz;
3185 u16 max_request_credit;
3186 unsigned short sg_tablesize;
3187 u16 sge_size;
3188 int i;
3189
3190 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3191 __func__));
3192
3193
3194 retry_sz = 0;
3195 facts = &ioc->facts;
3196
3197 /* command line tunables for max sgl entries */
3198 if (max_sgl_entries != -1)
3199 sg_tablesize = max_sgl_entries;
471ef9d4
SR		 3200 else {
3201 if (ioc->hba_mpi_version_belonged == MPI2_VERSION)
3202 sg_tablesize = MPT2SAS_SG_DEPTH;
3203 else
3204 sg_tablesize = MPT3SAS_SG_DEPTH;
3205 }
f92363d1 3206
8a7e4c24
SR		 3207 if (sg_tablesize < MPT_MIN_PHYS_SEGMENTS)
3208 sg_tablesize = MPT_MIN_PHYS_SEGMENTS;
3209 else if (sg_tablesize > MPT_MAX_PHYS_SEGMENTS) {
ad666a0f 3210 sg_tablesize = min_t(unsigned short, sg_tablesize,
65e8617f 3211 SG_MAX_SEGMENTS);
ad666a0f
SR		 3212 pr_warn(MPT3SAS_FMT
3213 "sg_tablesize(%u) is bigger than kernel"
65e8617f 3214 " defined SG_CHUNK_SIZE(%u)\n", ioc->name,
8a7e4c24 3215 sg_tablesize, MPT_MAX_PHYS_SEGMENTS);
ad666a0f 3216 }
f92363d1
SR		 3217 ioc->shost->sg_tablesize = sg_tablesize;
3218
fd0331b3
SS		 3219 ioc->internal_depth = min_t(int, (facts->HighPriorityCredit + (5)),
3220 (facts->RequestCredit / 4));
3221 if (ioc->internal_depth < INTERNAL_CMDS_COUNT) {
3222 if (facts->RequestCredit <= (INTERNAL_CMDS_COUNT +
3223 INTERNAL_SCSIIO_CMDS_COUNT)) {
3224 pr_err(MPT3SAS_FMT "IOC doesn't have enough Request \
3225 Credits, it has just %d number of credits\n",
3226 ioc->name, facts->RequestCredit);
3227 return -ENOMEM;
3228 }
3229 ioc->internal_depth = 10;
3230 }
3231
3232 ioc->hi_priority_depth = ioc->internal_depth - (5);
f92363d1
SR		 3233 /* command line tunables for max controller queue depth */
3234 if (max_queue_depth != -1 && max_queue_depth != 0) {
3235 max_request_credit = min_t(u16, max_queue_depth +
fd0331b3 3236 ioc->internal_depth, facts->RequestCredit);
f92363d1
SR		 3237 if (max_request_credit > MAX_HBA_QUEUE_DEPTH)
3238 max_request_credit = MAX_HBA_QUEUE_DEPTH;
3239 } else
3240 max_request_credit = min_t(u16, facts->RequestCredit,
3241 MAX_HBA_QUEUE_DEPTH);
3242
fd0331b3
SS		 3243 /* Firmware maintains additional facts->HighPriorityCredit number of
3244 * credits for HiPriprity Request messages, so hba queue depth will be
3245 * sum of max_request_credit and high priority queue depth.
3246 */
3247 ioc->hba_queue_depth = max_request_credit + ioc->hi_priority_depth;
f92363d1
SR		 3248
3249 /* request frame size */
3250 ioc->request_sz = facts->IOCRequestFrameSize * 4;
3251
3252 /* reply frame size */
3253 ioc->reply_sz = facts->ReplyFrameSize * 4;
3254
ebb3024e
SS		 3255 /* chain segment size */
3256 if (ioc->hba_mpi_version_belonged != MPI2_VERSION) {
3257 if (facts->IOCMaxChainSegmentSize)
3258 ioc->chain_segment_sz =
3259 facts->IOCMaxChainSegmentSize *
3260 MAX_CHAIN_ELEMT_SZ;
3261 else
3262 /* set to 128 bytes size if IOCMaxChainSegmentSize is zero */
3263 ioc->chain_segment_sz = DEFAULT_NUM_FWCHAIN_ELEMTS *
3264 MAX_CHAIN_ELEMT_SZ;
3265 } else
3266 ioc->chain_segment_sz = ioc->request_sz;
3267
f92363d1
SR		 3268 /* calculate the max scatter element size */
3269 sge_size = max_t(u16, ioc->sge_size, ioc->sge_size_ieee);
3270
3271 retry_allocation:
3272 total_sz = 0;
3273 /* calculate number of sg elements left over in the 1st frame */
3274 max_sge_elements = ioc->request_sz - ((sizeof(Mpi2SCSIIORequest_t) -
3275 sizeof(Mpi2SGEIOUnion_t)) + sge_size);
3276 ioc->max_sges_in_main_message = max_sge_elements/sge_size;
3277
3278 /* now do the same for a chain buffer */
ebb3024e 3279 max_sge_elements = ioc->chain_segment_sz - sge_size;
f92363d1
SR		 3280 ioc->max_sges_in_chain_message = max_sge_elements/sge_size;
3281
3282 /*
3283 * MPT3SAS_SG_DEPTH = CONFIG_FUSION_MAX_SGE
3284 */
3285 chains_needed_per_io = ((ioc->shost->sg_tablesize -
3286 ioc->max_sges_in_main_message)/ioc->max_sges_in_chain_message)
3287 + 1;
3288 if (chains_needed_per_io > facts->MaxChainDepth) {
3289 chains_needed_per_io = facts->MaxChainDepth;
3290 ioc->shost->sg_tablesize = min_t(u16,
3291 ioc->max_sges_in_main_message + (ioc->max_sges_in_chain_message
3292 * chains_needed_per_io), ioc->shost->sg_tablesize);
3293 }
3294 ioc->chains_needed_per_io = chains_needed_per_io;
3295
3296 /* reply free queue sizing - taking into account for 64 FW events */
3297 ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64;
3298
3299 /* calculate reply descriptor post queue depth */
3300 ioc->reply_post_queue_depth = ioc->hba_queue_depth +
3301 ioc->reply_free_queue_depth + 1 ;
3302 /* align the reply post queue on the next 16 count boundary */
3303 if (ioc->reply_post_queue_depth % 16)
3304 ioc->reply_post_queue_depth += 16 -
3305 (ioc->reply_post_queue_depth % 16);
3306
f92363d1
SR		 3307 if (ioc->reply_post_queue_depth >
3308 facts->MaxReplyDescriptorPostQueueDepth) {
3309 ioc->reply_post_queue_depth =
3310 facts->MaxReplyDescriptorPostQueueDepth -
3311 (facts->MaxReplyDescriptorPostQueueDepth % 16);
3312 ioc->hba_queue_depth =
3313 ((ioc->reply_post_queue_depth - 64) / 2) - 1;
3314 ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64;
3315 }
3316
3317 dinitprintk(ioc, pr_info(MPT3SAS_FMT "scatter gather: " \
3318 "sge_in_main_msg(%d), sge_per_chain(%d), sge_per_io(%d), "
3319 "chains_per_io(%d)\n", ioc->name, ioc->max_sges_in_main_message,
3320 ioc->max_sges_in_chain_message, ioc->shost->sg_tablesize,
3321 ioc->chains_needed_per_io));
3322
9b05c91a
SR		 3323 /* reply post queue, 16 byte align */
3324 reply_post_free_sz = ioc->reply_post_queue_depth *
3325 sizeof(Mpi2DefaultReplyDescriptor_t);
3326
3327 sz = reply_post_free_sz;
3328 if (_base_is_controller_msix_enabled(ioc) && !ioc->rdpq_array_enable)
3329 sz *= ioc->reply_queue_count;
3330
3331 ioc->reply_post = kcalloc((ioc->rdpq_array_enable) ?
3332 (ioc->reply_queue_count):1,
3333 sizeof(struct reply_post_struct), GFP_KERNEL);
3334
3335 if (!ioc->reply_post) {
3336 pr_err(MPT3SAS_FMT "reply_post_free pool: kcalloc failed\n",
3337 ioc->name);
3338 goto out;
3339 }
3340 ioc->reply_post_free_dma_pool = pci_pool_create("reply_post_free pool",
3341 ioc->pdev, sz, 16, 0);
3342 if (!ioc->reply_post_free_dma_pool) {
3343 pr_err(MPT3SAS_FMT
3344 "reply_post_free pool: pci_pool_create failed\n",
3345 ioc->name);
3346 goto out;
3347 }
3348 i = 0;
3349 do {
3350 ioc->reply_post[i].reply_post_free =
3351 pci_pool_alloc(ioc->reply_post_free_dma_pool,
3352 GFP_KERNEL,
3353 &ioc->reply_post[i].reply_post_free_dma);
3354 if (!ioc->reply_post[i].reply_post_free) {
3355 pr_err(MPT3SAS_FMT
3356 "reply_post_free pool: pci_pool_alloc failed\n",
3357 ioc->name);
3358 goto out;
3359 }
3360 memset(ioc->reply_post[i].reply_post_free, 0, sz);
3361 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3362 "reply post free pool (0x%p): depth(%d),"
3363 "element_size(%d), pool_size(%d kB)\n", ioc->name,
3364 ioc->reply_post[i].reply_post_free,
3365 ioc->reply_post_queue_depth, 8, sz/1024));
3366 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3367 "reply_post_free_dma = (0x%llx)\n", ioc->name,
3368 (unsigned long long)
3369 ioc->reply_post[i].reply_post_free_dma));
3370 total_sz += sz;
3371 } while (ioc->rdpq_array_enable && (++i < ioc->reply_queue_count));
3372
3373 if (ioc->dma_mask == 64) {
3374 if (_base_change_consistent_dma_mask(ioc, ioc->pdev) != 0) {
3375 pr_warn(MPT3SAS_FMT
3376 "no suitable consistent DMA mask for %s\n",
3377 ioc->name, pci_name(ioc->pdev));
3378 goto out;
3379 }
3380 }
3381
f92363d1
SR		 3382 ioc->scsiio_depth = ioc->hba_queue_depth -
3383 ioc->hi_priority_depth - ioc->internal_depth;
3384
3385 /* set the scsi host can_queue depth
3386 * with some internal commands that could be outstanding
3387 */
fd0331b3 3388 ioc->shost->can_queue = ioc->scsiio_depth - INTERNAL_SCSIIO_CMDS_COUNT;
f92363d1
SR		 3389 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3390 "scsi host: can_queue depth (%d)\n",
3391 ioc->name, ioc->shost->can_queue));
3392
3393
3394 /* contiguous pool for request and chains, 16 byte align, one extra "
3395 * "frame for smid=0
3396 */
3397 ioc->chain_depth = ioc->chains_needed_per_io * ioc->scsiio_depth;
3398 sz = ((ioc->scsiio_depth + 1) * ioc->request_sz);
3399
3400 /* hi-priority queue */
3401 sz += (ioc->hi_priority_depth * ioc->request_sz);
3402
3403 /* internal queue */
3404 sz += (ioc->internal_depth * ioc->request_sz);
3405
3406 ioc->request_dma_sz = sz;
3407 ioc->request = pci_alloc_consistent(ioc->pdev, sz, &ioc->request_dma);
3408 if (!ioc->request) {
3409 pr_err(MPT3SAS_FMT "request pool: pci_alloc_consistent " \
3410 "failed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
3411 "total(%d kB)\n", ioc->name, ioc->hba_queue_depth,
3412 ioc->chains_needed_per_io, ioc->request_sz, sz/1024);
3413 if (ioc->scsiio_depth < MPT3SAS_SAS_QUEUE_DEPTH)
3414 goto out;
fd0331b3
SS		 3415 retry_sz = 64;
3416 ioc->hba_queue_depth -= retry_sz;
8ff045c9 3417 _base_release_memory_pools(ioc);
f92363d1
SR		 3418 goto retry_allocation;
3419 }
3420
3421 if (retry_sz)
3422 pr_err(MPT3SAS_FMT "request pool: pci_alloc_consistent " \
3423 "succeed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
3424 "total(%d kb)\n", ioc->name, ioc->hba_queue_depth,
3425 ioc->chains_needed_per_io, ioc->request_sz, sz/1024);
3426
3427 /* hi-priority queue */
3428 ioc->hi_priority = ioc->request + ((ioc->scsiio_depth + 1) *
3429 ioc->request_sz);
3430 ioc->hi_priority_dma = ioc->request_dma + ((ioc->scsiio_depth + 1) *
3431 ioc->request_sz);
3432
3433 /* internal queue */
3434 ioc->internal = ioc->hi_priority + (ioc->hi_priority_depth *
3435 ioc->request_sz);
3436 ioc->internal_dma = ioc->hi_priority_dma + (ioc->hi_priority_depth *
3437 ioc->request_sz);
3438
3439 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3440 "request pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n",
3441 ioc->name, ioc->request, ioc->hba_queue_depth, ioc->request_sz,
3442 (ioc->hba_queue_depth * ioc->request_sz)/1024));
3443
3444 dinitprintk(ioc, pr_info(MPT3SAS_FMT "request pool: dma(0x%llx)\n",
3445 ioc->name, (unsigned long long) ioc->request_dma));
3446 total_sz += sz;
3447
3448 sz = ioc->scsiio_depth * sizeof(struct scsiio_tracker);
3449 ioc->scsi_lookup_pages = get_order(sz);
3450 ioc->scsi_lookup = (struct scsiio_tracker *)__get_free_pages(
3451 GFP_KERNEL, ioc->scsi_lookup_pages);
3452 if (!ioc->scsi_lookup) {
3453 pr_err(MPT3SAS_FMT "scsi_lookup: get_free_pages failed, sz(%d)\n",
3454 ioc->name, (int)sz);
3455 goto out;
3456 }
3457
3458 dinitprintk(ioc, pr_info(MPT3SAS_FMT "scsiio(0x%p): depth(%d)\n",
3459 ioc->name, ioc->request, ioc->scsiio_depth));
3460
3461 ioc->chain_depth = min_t(u32, ioc->chain_depth, MAX_CHAIN_DEPTH);
3462 sz = ioc->chain_depth * sizeof(struct chain_tracker);
3463 ioc->chain_pages = get_order(sz);
3464 ioc->chain_lookup = (struct chain_tracker *)__get_free_pages(
3465 GFP_KERNEL, ioc->chain_pages);
3466 if (!ioc->chain_lookup) {
3467 pr_err(MPT3SAS_FMT "chain_lookup: __get_free_pages failed\n",
3468 ioc->name);
3469 goto out;
3470 }
3471 ioc->chain_dma_pool = pci_pool_create("chain pool", ioc->pdev,
ebb3024e 3472 ioc->chain_segment_sz, 16, 0);
f92363d1
SR		 3473 if (!ioc->chain_dma_pool) {
3474 pr_err(MPT3SAS_FMT "chain_dma_pool: pci_pool_create failed\n",
3475 ioc->name);
3476 goto out;
3477 }
3478 for (i = 0; i < ioc->chain_depth; i++) {
3479 ioc->chain_lookup[i].chain_buffer = pci_pool_alloc(
3480 ioc->chain_dma_pool , GFP_KERNEL,
3481 &ioc->chain_lookup[i].chain_buffer_dma);
3482 if (!ioc->chain_lookup[i].chain_buffer) {
3483 ioc->chain_depth = i;
3484 goto chain_done;
3485 }
ebb3024e 3486 total_sz += ioc->chain_segment_sz;
f92363d1
SR		 3487 }
3488 chain_done:
3489 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3490 "chain pool depth(%d), frame_size(%d), pool_size(%d kB)\n",
ebb3024e
SS		 3491 ioc->name, ioc->chain_depth, ioc->chain_segment_sz,
3492 ((ioc->chain_depth * ioc->chain_segment_sz))/1024));
f92363d1
SR		 3493
3494 /* initialize hi-priority queue smid's */
3495 ioc->hpr_lookup = kcalloc(ioc->hi_priority_depth,
3496 sizeof(struct request_tracker), GFP_KERNEL);
3497 if (!ioc->hpr_lookup) {
3498 pr_err(MPT3SAS_FMT "hpr_lookup: kcalloc failed\n",
3499 ioc->name);
3500 goto out;
3501 }
3502 ioc->hi_priority_smid = ioc->scsiio_depth + 1;
3503 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3504 "hi_priority(0x%p): depth(%d), start smid(%d)\n",
3505 ioc->name, ioc->hi_priority,
3506 ioc->hi_priority_depth, ioc->hi_priority_smid));
3507
3508 /* initialize internal queue smid's */
3509 ioc->internal_lookup = kcalloc(ioc->internal_depth,
3510 sizeof(struct request_tracker), GFP_KERNEL);
3511 if (!ioc->internal_lookup) {
3512 pr_err(MPT3SAS_FMT "internal_lookup: kcalloc failed\n",
3513 ioc->name);
3514 goto out;
3515 }
3516 ioc->internal_smid = ioc->hi_priority_smid + ioc->hi_priority_depth;
3517 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3518 "internal(0x%p): depth(%d), start smid(%d)\n",
3519 ioc->name, ioc->internal,
3520 ioc->internal_depth, ioc->internal_smid));
3521
3522 /* sense buffers, 4 byte align */
3523 sz = ioc->scsiio_depth * SCSI_SENSE_BUFFERSIZE;
3524 ioc->sense_dma_pool = pci_pool_create("sense pool", ioc->pdev, sz, 4,
3525 0);
3526 if (!ioc->sense_dma_pool) {
3527 pr_err(MPT3SAS_FMT "sense pool: pci_pool_create failed\n",
3528 ioc->name);
3529 goto out;
3530 }
3531 ioc->sense = pci_pool_alloc(ioc->sense_dma_pool , GFP_KERNEL,
3532 &ioc->sense_dma);
3533 if (!ioc->sense) {
3534 pr_err(MPT3SAS_FMT "sense pool: pci_pool_alloc failed\n",
3535 ioc->name);
3536 goto out;
3537 }
3538 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3539 "sense pool(0x%p): depth(%d), element_size(%d), pool_size"
3540 "(%d kB)\n", ioc->name, ioc->sense, ioc->scsiio_depth,
3541 SCSI_SENSE_BUFFERSIZE, sz/1024));
3542 dinitprintk(ioc, pr_info(MPT3SAS_FMT "sense_dma(0x%llx)\n",
3543 ioc->name, (unsigned long long)ioc->sense_dma));
3544 total_sz += sz;
3545
3546 /* reply pool, 4 byte align */
3547 sz = ioc->reply_free_queue_depth * ioc->reply_sz;
3548 ioc->reply_dma_pool = pci_pool_create("reply pool", ioc->pdev, sz, 4,
3549 0);
3550 if (!ioc->reply_dma_pool) {
3551 pr_err(MPT3SAS_FMT "reply pool: pci_pool_create failed\n",
3552 ioc->name);
3553 goto out;
3554 }
3555 ioc->reply = pci_pool_alloc(ioc->reply_dma_pool , GFP_KERNEL,
3556 &ioc->reply_dma);
3557 if (!ioc->reply) {
3558 pr_err(MPT3SAS_FMT "reply pool: pci_pool_alloc failed\n",
3559 ioc->name);
3560 goto out;
3561 }
3562 ioc->reply_dma_min_address = (u32)(ioc->reply_dma);
3563 ioc->reply_dma_max_address = (u32)(ioc->reply_dma) + sz;
3564 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3565 "reply pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n",
3566 ioc->name, ioc->reply,
3567 ioc->reply_free_queue_depth, ioc->reply_sz, sz/1024));
3568 dinitprintk(ioc, pr_info(MPT3SAS_FMT "reply_dma(0x%llx)\n",
3569 ioc->name, (unsigned long long)ioc->reply_dma));
3570 total_sz += sz;
3571
3572 /* reply free queue, 16 byte align */
3573 sz = ioc->reply_free_queue_depth * 4;
3574 ioc->reply_free_dma_pool = pci_pool_create("reply_free pool",
3575 ioc->pdev, sz, 16, 0);
3576 if (!ioc->reply_free_dma_pool) {
3577 pr_err(MPT3SAS_FMT "reply_free pool: pci_pool_create failed\n",
3578 ioc->name);
3579 goto out;
3580 }
3581 ioc->reply_free = pci_pool_alloc(ioc->reply_free_dma_pool , GFP_KERNEL,
3582 &ioc->reply_free_dma);
3583 if (!ioc->reply_free) {
3584 pr_err(MPT3SAS_FMT "reply_free pool: pci_pool_alloc failed\n",
3585 ioc->name);
3586 goto out;
3587 }
3588 memset(ioc->reply_free, 0, sz);
3589 dinitprintk(ioc, pr_info(MPT3SAS_FMT "reply_free pool(0x%p): " \
3590 "depth(%d), element_size(%d), pool_size(%d kB)\n", ioc->name,
3591 ioc->reply_free, ioc->reply_free_queue_depth, 4, sz/1024));
3592 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3593 "reply_free_dma (0x%llx)\n",
3594 ioc->name, (unsigned long long)ioc->reply_free_dma));
3595 total_sz += sz;
3596
f92363d1
SR		 3597 ioc->config_page_sz = 512;
3598 ioc->config_page = pci_alloc_consistent(ioc->pdev,
3599 ioc->config_page_sz, &ioc->config_page_dma);
3600 if (!ioc->config_page) {
3601 pr_err(MPT3SAS_FMT
3602 "config page: pci_pool_alloc failed\n",
3603 ioc->name);
3604 goto out;
3605 }
3606 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3607 "config page(0x%p): size(%d)\n",
3608 ioc->name, ioc->config_page, ioc->config_page_sz));
3609 dinitprintk(ioc, pr_info(MPT3SAS_FMT "config_page_dma(0x%llx)\n",
3610 ioc->name, (unsigned long long)ioc->config_page_dma));
3611 total_sz += ioc->config_page_sz;
3612
3613 pr_info(MPT3SAS_FMT "Allocated physical memory: size(%d kB)\n",
3614 ioc->name, total_sz/1024);
3615 pr_info(MPT3SAS_FMT
3616 "Current Controller Queue Depth(%d),Max Controller Queue Depth(%d)\n",
3617 ioc->name, ioc->shost->can_queue, facts->RequestCredit);
3618 pr_info(MPT3SAS_FMT "Scatter Gather Elements per IO(%d)\n",
3619 ioc->name, ioc->shost->sg_tablesize);
3620 return 0;
3621
3622 out:
3623 return -ENOMEM;
3624}
3625
3626/**
3627 * mpt3sas_base_get_iocstate - Get the current state of a MPT adapter.
3628 * @ioc: Pointer to MPT_ADAPTER structure
3629 * @cooked: Request raw or cooked IOC state
3630 *
3631 * Returns all IOC Doorbell register bits if cooked==0, else just the
3632 * Doorbell bits in MPI_IOC_STATE_MASK.
3633 */
3634u32
3635mpt3sas_base_get_iocstate(struct MPT3SAS_ADAPTER *ioc, int cooked)
3636{
3637 u32 s, sc;
3638
3639 s = readl(&ioc->chip->Doorbell);
3640 sc = s & MPI2_IOC_STATE_MASK;
3641 return cooked ? sc : s;
3642}
3643
3644/**
3645 * _base_wait_on_iocstate - waiting on a particular ioc state
3646 * @ioc_state: controller state { READY, OPERATIONAL, or RESET }
3647 * @timeout: timeout in second
f92363d1
SR		 3648 *
3649 * Returns 0 for success, non-zero for failure.
3650 */
3651static int
98c56ad3 3652_base_wait_on_iocstate(struct MPT3SAS_ADAPTER *ioc, u32 ioc_state, int timeout)
f92363d1
SR		 3653{
3654 u32 count, cntdn;
3655 u32 current_state;
3656
3657 count = 0;
98c56ad3 3658 cntdn = 1000 * timeout;
f92363d1
SR		 3659 do {
3660 current_state = mpt3sas_base_get_iocstate(ioc, 1);
3661 if (current_state == ioc_state)
3662 return 0;
3663 if (count && current_state == MPI2_IOC_STATE_FAULT)
3664 break;
98c56ad3
CO		 3665
3666 usleep_range(1000, 1500);
f92363d1
SR		 3667 count++;
3668 } while (--cntdn);
3669
3670 return current_state;
3671}
3672
3673/**
3674 * _base_wait_for_doorbell_int - waiting for controller interrupt(generated by
3675 * a write to the doorbell)
3676 * @ioc: per adapter object
3677 * @timeout: timeout in second
f92363d1
SR		 3678 *
3679 * Returns 0 for success, non-zero for failure.
3680 *
3681 * Notes: MPI2_HIS_IOC2SYS_DB_STATUS - set to one when IOC writes to doorbell.
3682 */
4dc8c808 3683static int
98c56ad3 3684_base_diag_reset(struct MPT3SAS_ADAPTER *ioc);
4dc8c808 3685
f92363d1 3686static int
98c56ad3 3687_base_wait_for_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout)
f92363d1
SR		 3688{
3689 u32 cntdn, count;
3690 u32 int_status;
3691
3692 count = 0;
98c56ad3 3693 cntdn = 1000 * timeout;
f92363d1
SR		 3694 do {
3695 int_status = readl(&ioc->chip->HostInterruptStatus);
3696 if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
3697 dhsprintk(ioc, pr_info(MPT3SAS_FMT
3698 "%s: successful count(%d), timeout(%d)\n",
3699 ioc->name, __func__, count, timeout));
3700 return 0;
3701 }
98c56ad3
CO		 3702
3703 usleep_range(1000, 1500);
3704 count++;
3705 } while (--cntdn);
3706
3707 pr_err(MPT3SAS_FMT
3708 "%s: failed due to timeout count(%d), int_status(%x)!\n",
3709 ioc->name, __func__, count, int_status);
3710 return -EFAULT;
3711}
3712
3713static int
3714_base_spin_on_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout)
3715{
3716 u32 cntdn, count;
3717 u32 int_status;
3718
3719 count = 0;
3720 cntdn = 2000 * timeout;
3721 do {
3722 int_status = readl(&ioc->chip->HostInterruptStatus);
3723 if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
3724 dhsprintk(ioc, pr_info(MPT3SAS_FMT
3725 "%s: successful count(%d), timeout(%d)\n",
3726 ioc->name, __func__, count, timeout));
3727 return 0;
3728 }
3729
3730 udelay(500);
f92363d1
SR		 3731 count++;
3732 } while (--cntdn);
3733
3734 pr_err(MPT3SAS_FMT
3735 "%s: failed due to timeout count(%d), int_status(%x)!\n",
3736 ioc->name, __func__, count, int_status);
3737 return -EFAULT;
98c56ad3 3738
f92363d1
SR		 3739}
3740
3741/**
3742 * _base_wait_for_doorbell_ack - waiting for controller to read the doorbell.
3743 * @ioc: per adapter object
3744 * @timeout: timeout in second
f92363d1
SR		 3745 *
3746 * Returns 0 for success, non-zero for failure.
3747 *
3748 * Notes: MPI2_HIS_SYS2IOC_DB_STATUS - set to one when host writes to
3749 * doorbell.
3750 */
3751static int
98c56ad3 3752_base_wait_for_doorbell_ack(struct MPT3SAS_ADAPTER *ioc, int timeout)
f92363d1
SR		 3753{
3754 u32 cntdn, count;
3755 u32 int_status;
3756 u32 doorbell;
3757
3758 count = 0;
98c56ad3 3759 cntdn = 1000 * timeout;
f92363d1
SR		 3760 do {
3761 int_status = readl(&ioc->chip->HostInterruptStatus);
3762 if (!(int_status & MPI2_HIS_SYS2IOC_DB_STATUS)) {
3763 dhsprintk(ioc, pr_info(MPT3SAS_FMT
3764 "%s: successful count(%d), timeout(%d)\n",
3765 ioc->name, __func__, count, timeout));
3766 return 0;
3767 } else if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
3768 doorbell = readl(&ioc->chip->Doorbell);
3769 if ((doorbell & MPI2_IOC_STATE_MASK) ==
3770 MPI2_IOC_STATE_FAULT) {
3771 mpt3sas_base_fault_info(ioc , doorbell);
3772 return -EFAULT;
3773 }
3774 } else if (int_status == 0xFFFFFFFF)
3775 goto out;
3776
98c56ad3 3777 usleep_range(1000, 1500);
f92363d1
SR		 3778 count++;
3779 } while (--cntdn);
3780
3781 out:
3782 pr_err(MPT3SAS_FMT
3783 "%s: failed due to timeout count(%d), int_status(%x)!\n",
3784 ioc->name, __func__, count, int_status);
3785 return -EFAULT;
3786}
3787
3788/**
3789 * _base_wait_for_doorbell_not_used - waiting for doorbell to not be in use
3790 * @ioc: per adapter object
3791 * @timeout: timeout in second
f92363d1
SR		 3792 *
3793 * Returns 0 for success, non-zero for failure.
3794 *
3795 */
3796static int
98c56ad3 3797_base_wait_for_doorbell_not_used(struct MPT3SAS_ADAPTER *ioc, int timeout)
f92363d1
SR		 3798{
3799 u32 cntdn, count;
3800 u32 doorbell_reg;
3801
3802 count = 0;
98c56ad3 3803 cntdn = 1000 * timeout;
f92363d1
SR		 3804 do {
3805 doorbell_reg = readl(&ioc->chip->Doorbell);
3806 if (!(doorbell_reg & MPI2_DOORBELL_USED)) {
3807 dhsprintk(ioc, pr_info(MPT3SAS_FMT
3808 "%s: successful count(%d), timeout(%d)\n",
3809 ioc->name, __func__, count, timeout));
3810 return 0;
3811 }
98c56ad3
CO		 3812
3813 usleep_range(1000, 1500);
f92363d1
SR		 3814 count++;
3815 } while (--cntdn);
3816
3817 pr_err(MPT3SAS_FMT
3818 "%s: failed due to timeout count(%d), doorbell_reg(%x)!\n",
3819 ioc->name, __func__, count, doorbell_reg);
3820 return -EFAULT;
3821}
3822
3823/**
3824 * _base_send_ioc_reset - send doorbell reset
3825 * @ioc: per adapter object
3826 * @reset_type: currently only supports: MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET
3827 * @timeout: timeout in second
f92363d1
SR		 3828 *
3829 * Returns 0 for success, non-zero for failure.
3830 */
3831static int
98c56ad3 3832_base_send_ioc_reset(struct MPT3SAS_ADAPTER *ioc, u8 reset_type, int timeout)
f92363d1
SR		 3833{
3834 u32 ioc_state;
3835 int r = 0;
3836
3837 if (reset_type != MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET) {
3838 pr_err(MPT3SAS_FMT "%s: unknown reset_type\n",
3839 ioc->name, __func__);
3840 return -EFAULT;
3841 }
3842
3843 if (!(ioc->facts.IOCCapabilities &
3844 MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY))
3845 return -EFAULT;
3846
3847 pr_info(MPT3SAS_FMT "sending message unit reset !!\n", ioc->name);
3848
3849 writel(reset_type << MPI2_DOORBELL_FUNCTION_SHIFT,
3850 &ioc->chip->Doorbell);
98c56ad3 3851 if ((_base_wait_for_doorbell_ack(ioc, 15))) {
f92363d1
SR		 3852 r = -EFAULT;
3853 goto out;
3854 }
98c56ad3 3855 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, timeout);
f92363d1
SR		 3856 if (ioc_state) {
3857 pr_err(MPT3SAS_FMT
3858 "%s: failed going to ready state (ioc_state=0x%x)\n",
3859 ioc->name, __func__, ioc_state);
3860 r = -EFAULT;
3861 goto out;
3862 }
3863 out:
3864 pr_info(MPT3SAS_FMT "message unit reset: %s\n",
3865 ioc->name, ((r == 0) ? "SUCCESS" : "FAILED"));
3866 return r;
3867}
3868
3869/**
3870 * _base_handshake_req_reply_wait - send request thru doorbell interface
3871 * @ioc: per adapter object
3872 * @request_bytes: request length
3873 * @request: pointer having request payload
3874 * @reply_bytes: reply length
3875 * @reply: pointer to reply payload
3876 * @timeout: timeout in second
f92363d1
SR		 3877 *
3878 * Returns 0 for success, non-zero for failure.
3879 */
3880static int
3881_base_handshake_req_reply_wait(struct MPT3SAS_ADAPTER *ioc, int request_bytes,
98c56ad3 3882 u32 *request, int reply_bytes, u16 *reply, int timeout)
f92363d1
SR		 3883{
3884 MPI2DefaultReply_t *default_reply = (MPI2DefaultReply_t *)reply;
3885 int i;
3886 u8 failed;
3887 u16 dummy;
3888 __le32 *mfp;
3889
3890 /* make sure doorbell is not in use */
3891 if ((readl(&ioc->chip->Doorbell) & MPI2_DOORBELL_USED)) {
3892 pr_err(MPT3SAS_FMT
3893 "doorbell is in use (line=%d)\n",
3894 ioc->name, __LINE__);
3895 return -EFAULT;
3896 }
3897
3898 /* clear pending doorbell interrupts from previous state changes */
3899 if (readl(&ioc->chip->HostInterruptStatus) &
3900 MPI2_HIS_IOC2SYS_DB_STATUS)
3901 writel(0, &ioc->chip->HostInterruptStatus);
3902
3903 /* send message to ioc */
3904 writel(((MPI2_FUNCTION_HANDSHAKE<<MPI2_DOORBELL_FUNCTION_SHIFT) |
3905 ((request_bytes/4)<<MPI2_DOORBELL_ADD_DWORDS_SHIFT)),
3906 &ioc->chip->Doorbell);
3907
98c56ad3 3908 if ((_base_spin_on_doorbell_int(ioc, 5))) {
f92363d1
SR		 3909 pr_err(MPT3SAS_FMT
3910 "doorbell handshake int failed (line=%d)\n",
3911 ioc->name, __LINE__);
3912 return -EFAULT;
3913 }
3914 writel(0, &ioc->chip->HostInterruptStatus);
3915
98c56ad3 3916 if ((_base_wait_for_doorbell_ack(ioc, 5))) {
f92363d1
SR		 3917 pr_err(MPT3SAS_FMT
3918 "doorbell handshake ack failed (line=%d)\n",
3919 ioc->name, __LINE__);
3920 return -EFAULT;
3921 }
3922
3923 /* send message 32-bits at a time */
3924 for (i = 0, failed = 0; i < request_bytes/4 && !failed; i++) {
3925 writel(cpu_to_le32(request[i]), &ioc->chip->Doorbell);
98c56ad3 3926 if ((_base_wait_for_doorbell_ack(ioc, 5)))
f92363d1
SR		 3927 failed = 1;
3928 }
3929
3930 if (failed) {
3931 pr_err(MPT3SAS_FMT
3932 "doorbell handshake sending request failed (line=%d)\n",
3933 ioc->name, __LINE__);
3934 return -EFAULT;
3935 }
3936
3937 /* now wait for the reply */
98c56ad3 3938 if ((_base_wait_for_doorbell_int(ioc, timeout))) {
f92363d1
SR		 3939 pr_err(MPT3SAS_FMT
3940 "doorbell handshake int failed (line=%d)\n",
3941 ioc->name, __LINE__);
3942 return -EFAULT;
3943 }
3944
3945 /* read the first two 16-bits, it gives the total length of the reply */
3946 reply[0] = le16_to_cpu(readl(&ioc->chip->Doorbell)
3947 & MPI2_DOORBELL_DATA_MASK);
3948 writel(0, &ioc->chip->HostInterruptStatus);
98c56ad3 3949 if ((_base_wait_for_doorbell_int(ioc, 5))) {
f92363d1
SR		 3950 pr_err(MPT3SAS_FMT
3951 "doorbell handshake int failed (line=%d)\n",
3952 ioc->name, __LINE__);
3953 return -EFAULT;
3954 }
3955 reply[1] = le16_to_cpu(readl(&ioc->chip->Doorbell)
3956 & MPI2_DOORBELL_DATA_MASK);
3957 writel(0, &ioc->chip->HostInterruptStatus);
3958
3959 for (i = 2; i < default_reply->MsgLength * 2; i++) {
98c56ad3 3960 if ((_base_wait_for_doorbell_int(ioc, 5))) {
f92363d1
SR		 3961 pr_err(MPT3SAS_FMT
3962 "doorbell handshake int failed (line=%d)\n",
3963 ioc->name, __LINE__);
3964 return -EFAULT;
3965 }
3966 if (i >= reply_bytes/2) /* overflow case */
3967 dummy = readl(&ioc->chip->Doorbell);
3968 else
3969 reply[i] = le16_to_cpu(readl(&ioc->chip->Doorbell)
3970 & MPI2_DOORBELL_DATA_MASK);
3971 writel(0, &ioc->chip->HostInterruptStatus);
3972 }
3973
98c56ad3
CO		 3974 _base_wait_for_doorbell_int(ioc, 5);
3975 if (_base_wait_for_doorbell_not_used(ioc, 5) != 0) {
f92363d1
SR		 3976 dhsprintk(ioc, pr_info(MPT3SAS_FMT
3977 "doorbell is in use (line=%d)\n", ioc->name, __LINE__));
3978 }
3979 writel(0, &ioc->chip->HostInterruptStatus);
3980
3981 if (ioc->logging_level & MPT_DEBUG_INIT) {
3982 mfp = (__le32 *)reply;
3983 pr_info("\toffset:data\n");
3984 for (i = 0; i < reply_bytes/4; i++)
3985 pr_info("\t[0x%02x]:%08x\n", i*4,
3986 le32_to_cpu(mfp[i]));
3987 }
3988 return 0;
3989}
3990
3991/**
3992 * mpt3sas_base_sas_iounit_control - send sas iounit control to FW
3993 * @ioc: per adapter object
3994 * @mpi_reply: the reply payload from FW
3995 * @mpi_request: the request payload sent to FW
3996 *
3997 * The SAS IO Unit Control Request message allows the host to perform low-level
3998 * operations, such as resets on the PHYs of the IO Unit, also allows the host
3999 * to obtain the IOC assigned device handles for a device if it has other
4000 * identifying information about the device, in addition allows the host to
4001 * remove IOC resources associated with the device.
4002 *
4003 * Returns 0 for success, non-zero for failure.
4004 */
4005int
4006mpt3sas_base_sas_iounit_control(struct MPT3SAS_ADAPTER *ioc,
4007 Mpi2SasIoUnitControlReply_t *mpi_reply,
4008 Mpi2SasIoUnitControlRequest_t *mpi_request)
4009{
4010 u16 smid;
4011 u32 ioc_state;
4012 unsigned long timeleft;
eb44552b 4013 bool issue_reset = false;
f92363d1
SR		 4014 int rc;
4015 void *request;
4016 u16 wait_state_count;
4017
4018 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4019 __func__));
4020
4021 mutex_lock(&ioc->base_cmds.mutex);
4022
4023 if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) {
4024 pr_err(MPT3SAS_FMT "%s: base_cmd in use\n",
4025 ioc->name, __func__);
4026 rc = -EAGAIN;
4027 goto out;
4028 }
4029
4030 wait_state_count = 0;
4031 ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
4032 while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) {
4033 if (wait_state_count++ == 10) {
4034 pr_err(MPT3SAS_FMT
4035 "%s: failed due to ioc not operational\n",
4036 ioc->name, __func__);
4037 rc = -EFAULT;
4038 goto out;
4039 }
4040 ssleep(1);
4041 ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
4042 pr_info(MPT3SAS_FMT
4043 "%s: waiting for operational state(count=%d)\n",
4044 ioc->name, __func__, wait_state_count);
4045 }
4046
4047 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
4048 if (!smid) {
4049 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4050 ioc->name, __func__);
4051 rc = -EAGAIN;
4052 goto out;
4053 }
4054
4055 rc = 0;
4056 ioc->base_cmds.status = MPT3_CMD_PENDING;
4057 request = mpt3sas_base_get_msg_frame(ioc, smid);
4058 ioc->base_cmds.smid = smid;
4059 memcpy(request, mpi_request, sizeof(Mpi2SasIoUnitControlRequest_t));
4060 if (mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
4061 mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET)
4062 ioc->ioc_link_reset_in_progress = 1;
4063 init_completion(&ioc->base_cmds.done);
4064 mpt3sas_base_put_smid_default(ioc, smid);
4065 timeleft = wait_for_completion_timeout(&ioc->base_cmds.done,
4066 msecs_to_jiffies(10000));
4067 if ((mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
4068 mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET) &&
4069 ioc->ioc_link_reset_in_progress)
4070 ioc->ioc_link_reset_in_progress = 0;
4071 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
4072 pr_err(MPT3SAS_FMT "%s: timeout\n",
4073 ioc->name, __func__);
4074 _debug_dump_mf(mpi_request,
4075 sizeof(Mpi2SasIoUnitControlRequest_t)/4);
4076 if (!(ioc->base_cmds.status & MPT3_CMD_RESET))
eb44552b 4077 issue_reset = true;
f92363d1
SR		 4078 goto issue_host_reset;
4079 }
4080 if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID)
4081 memcpy(mpi_reply, ioc->base_cmds.reply,
4082 sizeof(Mpi2SasIoUnitControlReply_t));
4083 else
4084 memset(mpi_reply, 0, sizeof(Mpi2SasIoUnitControlReply_t));
4085 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4086 goto out;
4087
4088 issue_host_reset:
4089 if (issue_reset)
98c56ad3 4090 mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER);
f92363d1
SR		 4091 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4092 rc = -EFAULT;
4093 out:
4094 mutex_unlock(&ioc->base_cmds.mutex);
4095 return rc;
4096}
4097
4098/**
4099 * mpt3sas_base_scsi_enclosure_processor - sending request to sep device
4100 * @ioc: per adapter object
4101 * @mpi_reply: the reply payload from FW
4102 * @mpi_request: the request payload sent to FW
4103 *
4104 * The SCSI Enclosure Processor request message causes the IOC to
4105 * communicate with SES devices to control LED status signals.
4106 *
4107 * Returns 0 for success, non-zero for failure.
4108 */
4109int
4110mpt3sas_base_scsi_enclosure_processor(struct MPT3SAS_ADAPTER *ioc,
4111 Mpi2SepReply_t *mpi_reply, Mpi2SepRequest_t *mpi_request)
4112{
4113 u16 smid;
4114 u32 ioc_state;
4115 unsigned long timeleft;
eb44552b 4116 bool issue_reset = false;
f92363d1
SR		 4117 int rc;
4118 void *request;
4119 u16 wait_state_count;
4120
4121 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4122 __func__));
4123
4124 mutex_lock(&ioc->base_cmds.mutex);
4125
4126 if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) {
4127 pr_err(MPT3SAS_FMT "%s: base_cmd in use\n",
4128 ioc->name, __func__);
4129 rc = -EAGAIN;
4130 goto out;
4131 }
4132
4133 wait_state_count = 0;
4134 ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
4135 while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) {
4136 if (wait_state_count++ == 10) {
4137 pr_err(MPT3SAS_FMT
4138 "%s: failed due to ioc not operational\n",
4139 ioc->name, __func__);
4140 rc = -EFAULT;
4141 goto out;
4142 }
4143 ssleep(1);
4144 ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
4145 pr_info(MPT3SAS_FMT
4146 "%s: waiting for operational state(count=%d)\n",
4147 ioc->name,
4148 __func__, wait_state_count);
4149 }
4150
4151 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
4152 if (!smid) {
4153 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4154 ioc->name, __func__);
4155 rc = -EAGAIN;
4156 goto out;
4157 }
4158
4159 rc = 0;
4160 ioc->base_cmds.status = MPT3_CMD_PENDING;
4161 request = mpt3sas_base_get_msg_frame(ioc, smid);
4162 ioc->base_cmds.smid = smid;
4163 memcpy(request, mpi_request, sizeof(Mpi2SepReply_t));
4164 init_completion(&ioc->base_cmds.done);
4165 mpt3sas_base_put_smid_default(ioc, smid);
4166 timeleft = wait_for_completion_timeout(&ioc->base_cmds.done,
4167 msecs_to_jiffies(10000));
4168 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
4169 pr_err(MPT3SAS_FMT "%s: timeout\n",
4170 ioc->name, __func__);
4171 _debug_dump_mf(mpi_request,
4172 sizeof(Mpi2SepRequest_t)/4);
4173 if (!(ioc->base_cmds.status & MPT3_CMD_RESET))
eb44552b 4174 issue_reset = false;
f92363d1
SR		 4175 goto issue_host_reset;
4176 }
4177 if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID)
4178 memcpy(mpi_reply, ioc->base_cmds.reply,
4179 sizeof(Mpi2SepReply_t));
4180 else
4181 memset(mpi_reply, 0, sizeof(Mpi2SepReply_t));
4182 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4183 goto out;
4184
4185 issue_host_reset:
4186 if (issue_reset)
98c56ad3 4187 mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER);
f92363d1
SR		 4188 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4189 rc = -EFAULT;
4190 out:
4191 mutex_unlock(&ioc->base_cmds.mutex);
4192 return rc;
4193}
4194
4195/**
4196 * _base_get_port_facts - obtain port facts reply and save in ioc
4197 * @ioc: per adapter object
f92363d1
SR		 4198 *
4199 * Returns 0 for success, non-zero for failure.
4200 */
4201static int
98c56ad3 4202_base_get_port_facts(struct MPT3SAS_ADAPTER *ioc, int port)
f92363d1
SR		 4203{
4204 Mpi2PortFactsRequest_t mpi_request;
4205 Mpi2PortFactsReply_t mpi_reply;
4206 struct mpt3sas_port_facts *pfacts;
4207 int mpi_reply_sz, mpi_request_sz, r;
4208
4209 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4210 __func__));
4211
4212 mpi_reply_sz = sizeof(Mpi2PortFactsReply_t);
4213 mpi_request_sz = sizeof(Mpi2PortFactsRequest_t);
4214 memset(&mpi_request, 0, mpi_request_sz);
4215 mpi_request.Function = MPI2_FUNCTION_PORT_FACTS;
4216 mpi_request.PortNumber = port;
4217 r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
98c56ad3 4218 (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5);
f92363d1
SR		 4219
4220 if (r != 0) {
4221 pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
4222 ioc->name, __func__, r);
4223 return r;
4224 }
4225
4226 pfacts = &ioc->pfacts[port];
4227 memset(pfacts, 0, sizeof(struct mpt3sas_port_facts));
4228 pfacts->PortNumber = mpi_reply.PortNumber;
4229 pfacts->VP_ID = mpi_reply.VP_ID;
4230 pfacts->VF_ID = mpi_reply.VF_ID;
4231 pfacts->MaxPostedCmdBuffers =
4232 le16_to_cpu(mpi_reply.MaxPostedCmdBuffers);
4233
4234 return 0;
4235}
4236
4dc8c808
SR		 4237/**
4238 * _base_wait_for_iocstate - Wait until the card is in READY or OPERATIONAL
4239 * @ioc: per adapter object
4240 * @timeout:
4dc8c808
SR		 4241 *
4242 * Returns 0 for success, non-zero for failure.
4243 */
4244static int
98c56ad3 4245_base_wait_for_iocstate(struct MPT3SAS_ADAPTER *ioc, int timeout)
4dc8c808
SR		 4246{
4247 u32 ioc_state;
4248 int rc;
4249
4250 dinitprintk(ioc, printk(MPT3SAS_FMT "%s\n", ioc->name,
4251 __func__));
4252
4253 if (ioc->pci_error_recovery) {
4254 dfailprintk(ioc, printk(MPT3SAS_FMT
4255 "%s: host in pci error recovery\n", ioc->name, __func__));
4256 return -EFAULT;
4257 }
4258
4259 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
4260 dhsprintk(ioc, printk(MPT3SAS_FMT "%s: ioc_state(0x%08x)\n",
4261 ioc->name, __func__, ioc_state));
4262
4263 if (((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY) ||
4264 (ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL)
4265 return 0;
4266
4267 if (ioc_state & MPI2_DOORBELL_USED) {
4268 dhsprintk(ioc, printk(MPT3SAS_FMT
4269 "unexpected doorbell active!\n", ioc->name));
4270 goto issue_diag_reset;
4271 }
4272
4273 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
4274 mpt3sas_base_fault_info(ioc, ioc_state &
4275 MPI2_DOORBELL_DATA_MASK);
4276 goto issue_diag_reset;
4277 }
4278
98c56ad3 4279 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, timeout);
4dc8c808
SR		 4280 if (ioc_state) {
4281 dfailprintk(ioc, printk(MPT3SAS_FMT
4282 "%s: failed going to ready state (ioc_state=0x%x)\n",
4283 ioc->name, __func__, ioc_state));
4284 return -EFAULT;
4285 }
4286
4287 issue_diag_reset:
98c56ad3 4288 rc = _base_diag_reset(ioc);
4dc8c808
SR		 4289 return rc;
4290}
4291
f92363d1
SR		 4292/**
4293 * _base_get_ioc_facts - obtain ioc facts reply and save in ioc
4294 * @ioc: per adapter object
f92363d1
SR		 4295 *
4296 * Returns 0 for success, non-zero for failure.
4297 */
4298static int
98c56ad3 4299_base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc)
f92363d1
SR		 4300{
4301 Mpi2IOCFactsRequest_t mpi_request;
4302 Mpi2IOCFactsReply_t mpi_reply;
4303 struct mpt3sas_facts *facts;
4304 int mpi_reply_sz, mpi_request_sz, r;
4305
4306 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4307 __func__));
4308
98c56ad3 4309 r = _base_wait_for_iocstate(ioc, 10);
4dc8c808
SR		 4310 if (r) {
4311 dfailprintk(ioc, printk(MPT3SAS_FMT
4312 "%s: failed getting to correct state\n",
4313 ioc->name, __func__));
4314 return r;
4315 }
f92363d1
SR		 4316 mpi_reply_sz = sizeof(Mpi2IOCFactsReply_t);
4317 mpi_request_sz = sizeof(Mpi2IOCFactsRequest_t);
4318 memset(&mpi_request, 0, mpi_request_sz);
4319 mpi_request.Function = MPI2_FUNCTION_IOC_FACTS;
4320 r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
98c56ad3 4321 (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5);
f92363d1
SR		 4322
4323 if (r != 0) {
4324 pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
4325 ioc->name, __func__, r);
4326 return r;
4327 }
4328
4329 facts = &ioc->facts;
4330 memset(facts, 0, sizeof(struct mpt3sas_facts));
4331 facts->MsgVersion = le16_to_cpu(mpi_reply.MsgVersion);
4332 facts->HeaderVersion = le16_to_cpu(mpi_reply.HeaderVersion);
4333 facts->VP_ID = mpi_reply.VP_ID;
4334 facts->VF_ID = mpi_reply.VF_ID;
4335 facts->IOCExceptions = le16_to_cpu(mpi_reply.IOCExceptions);
4336 facts->MaxChainDepth = mpi_reply.MaxChainDepth;
4337 facts->WhoInit = mpi_reply.WhoInit;
4338 facts->NumberOfPorts = mpi_reply.NumberOfPorts;
4339 facts->MaxMSIxVectors = mpi_reply.MaxMSIxVectors;
4340 facts->RequestCredit = le16_to_cpu(mpi_reply.RequestCredit);
4341 facts->MaxReplyDescriptorPostQueueDepth =
4342 le16_to_cpu(mpi_reply.MaxReplyDescriptorPostQueueDepth);
4343 facts->ProductID = le16_to_cpu(mpi_reply.ProductID);
4344 facts->IOCCapabilities = le32_to_cpu(mpi_reply.IOCCapabilities);
4345 if ((facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID))
4346 ioc->ir_firmware = 1;
9b05c91a
SR		 4347 if ((facts->IOCCapabilities &
4348 MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE))
4349 ioc->rdpq_array_capable = 1;
f92363d1
SR		 4350 facts->FWVersion.Word = le32_to_cpu(mpi_reply.FWVersion.Word);
4351 facts->IOCRequestFrameSize =
4352 le16_to_cpu(mpi_reply.IOCRequestFrameSize);
ebb3024e
SS		 4353 if (ioc->hba_mpi_version_belonged != MPI2_VERSION) {
4354 facts->IOCMaxChainSegmentSize =
4355 le16_to_cpu(mpi_reply.IOCMaxChainSegmentSize);
4356 }
f92363d1
SR		 4357 facts->MaxInitiators = le16_to_cpu(mpi_reply.MaxInitiators);
4358 facts->MaxTargets = le16_to_cpu(mpi_reply.MaxTargets);
4359 ioc->shost->max_id = -1;
4360 facts->MaxSasExpanders = le16_to_cpu(mpi_reply.MaxSasExpanders);
4361 facts->MaxEnclosures = le16_to_cpu(mpi_reply.MaxEnclosures);
4362 facts->ProtocolFlags = le16_to_cpu(mpi_reply.ProtocolFlags);
4363 facts->HighPriorityCredit =
4364 le16_to_cpu(mpi_reply.HighPriorityCredit);
4365 facts->ReplyFrameSize = mpi_reply.ReplyFrameSize;
4366 facts->MaxDevHandle = le16_to_cpu(mpi_reply.MaxDevHandle);
4367
4368 dinitprintk(ioc, pr_info(MPT3SAS_FMT
4369 "hba queue depth(%d), max chains per io(%d)\n",
4370 ioc->name, facts->RequestCredit,
4371 facts->MaxChainDepth));
4372 dinitprintk(ioc, pr_info(MPT3SAS_FMT
4373 "request frame size(%d), reply frame size(%d)\n", ioc->name,
4374 facts->IOCRequestFrameSize * 4, facts->ReplyFrameSize * 4));
4375 return 0;
4376}
4377
4378/**
4379 * _base_send_ioc_init - send ioc_init to firmware
4380 * @ioc: per adapter object
f92363d1
SR		 4381 *
4382 * Returns 0 for success, non-zero for failure.
4383 */
4384static int
98c56ad3 4385_base_send_ioc_init(struct MPT3SAS_ADAPTER *ioc)
f92363d1
SR		 4386{
4387 Mpi2IOCInitRequest_t mpi_request;
4388 Mpi2IOCInitReply_t mpi_reply;
9b05c91a 4389 int i, r = 0;
23409bd4 4390 ktime_t current_time;
f92363d1 4391 u16 ioc_status;
9b05c91a
SR		 4392 u32 reply_post_free_array_sz = 0;
4393 Mpi2IOCInitRDPQArrayEntry *reply_post_free_array = NULL;
4394 dma_addr_t reply_post_free_array_dma;
f92363d1
SR		 4395
4396 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4397 __func__));
4398
4399 memset(&mpi_request, 0, sizeof(Mpi2IOCInitRequest_t));
4400 mpi_request.Function = MPI2_FUNCTION_IOC_INIT;
4401 mpi_request.WhoInit = MPI2_WHOINIT_HOST_DRIVER;
4402 mpi_request.VF_ID = 0; /* TODO */
4403 mpi_request.VP_ID = 0;
d357e84d 4404 mpi_request.MsgVersion = cpu_to_le16(ioc->hba_mpi_version_belonged);
f92363d1
SR		 4405 mpi_request.HeaderVersion = cpu_to_le16(MPI2_HEADER_VERSION);
4406
4407 if (_base_is_controller_msix_enabled(ioc))
4408 mpi_request.HostMSIxVectors = ioc->reply_queue_count;
4409 mpi_request.SystemRequestFrameSize = cpu_to_le16(ioc->request_sz/4);
4410 mpi_request.ReplyDescriptorPostQueueDepth =
4411 cpu_to_le16(ioc->reply_post_queue_depth);
4412 mpi_request.ReplyFreeQueueDepth =
4413 cpu_to_le16(ioc->reply_free_queue_depth);
4414
4415 mpi_request.SenseBufferAddressHigh =
4416 cpu_to_le32((u64)ioc->sense_dma >> 32);
4417 mpi_request.SystemReplyAddressHigh =
4418 cpu_to_le32((u64)ioc->reply_dma >> 32);
4419 mpi_request.SystemRequestFrameBaseAddress =
4420 cpu_to_le64((u64)ioc->request_dma);
4421 mpi_request.ReplyFreeQueueAddress =
4422 cpu_to_le64((u64)ioc->reply_free_dma);
f92363d1 4423
9b05c91a
SR		 4424 if (ioc->rdpq_array_enable) {
4425 reply_post_free_array_sz = ioc->reply_queue_count *
4426 sizeof(Mpi2IOCInitRDPQArrayEntry);
4427 reply_post_free_array = pci_alloc_consistent(ioc->pdev,
4428 reply_post_free_array_sz, &reply_post_free_array_dma);
4429 if (!reply_post_free_array) {
4430 pr_err(MPT3SAS_FMT
4431 "reply_post_free_array: pci_alloc_consistent failed\n",
4432 ioc->name);
4433 r = -ENOMEM;
4434 goto out;
4435 }
4436 memset(reply_post_free_array, 0, reply_post_free_array_sz);
4437 for (i = 0; i < ioc->reply_queue_count; i++)
4438 reply_post_free_array[i].RDPQBaseAddress =
4439 cpu_to_le64(
4440 (u64)ioc->reply_post[i].reply_post_free_dma);
4441 mpi_request.MsgFlags = MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE;
4442 mpi_request.ReplyDescriptorPostQueueAddress =
4443 cpu_to_le64((u64)reply_post_free_array_dma);
4444 } else {
4445 mpi_request.ReplyDescriptorPostQueueAddress =
4446 cpu_to_le64((u64)ioc->reply_post[0].reply_post_free_dma);
4447 }
f92363d1
SR		 4448
4449 /* This time stamp specifies number of milliseconds
4450 * since epoch ~ midnight January 1, 1970.
4451 */
23409bd4
TR		 4452 current_time = ktime_get_real();
4453 mpi_request.TimeStamp = cpu_to_le64(ktime_to_ms(current_time));
f92363d1
SR		 4454
4455 if (ioc->logging_level & MPT_DEBUG_INIT) {
4456 __le32 *mfp;
4457 int i;
4458
4459 mfp = (__le32 *)&mpi_request;
4460 pr_info("\toffset:data\n");
4461 for (i = 0; i < sizeof(Mpi2IOCInitRequest_t)/4; i++)
4462 pr_info("\t[0x%02x]:%08x\n", i*4,
4463 le32_to_cpu(mfp[i]));
4464 }
4465
4466 r = _base_handshake_req_reply_wait(ioc,
4467 sizeof(Mpi2IOCInitRequest_t), (u32 *)&mpi_request,
98c56ad3 4468 sizeof(Mpi2IOCInitReply_t), (u16 *)&mpi_reply, 10);
f92363d1
SR		 4469
4470 if (r != 0) {
4471 pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
4472 ioc->name, __func__, r);
9b05c91a 4473 goto out;
f92363d1
SR		 4474 }
4475
4476 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & MPI2_IOCSTATUS_MASK;
4477 if (ioc_status != MPI2_IOCSTATUS_SUCCESS ||
4478 mpi_reply.IOCLogInfo) {
4479 pr_err(MPT3SAS_FMT "%s: failed\n", ioc->name, __func__);
4480 r = -EIO;
4481 }
4482
9b05c91a
SR		 4483out:
4484 if (reply_post_free_array)
4485 pci_free_consistent(ioc->pdev, reply_post_free_array_sz,
4486 reply_post_free_array,
4487 reply_post_free_array_dma);
4488 return r;
f92363d1
SR		 4489}
4490
4491/**
4492 * mpt3sas_port_enable_done - command completion routine for port enable
4493 * @ioc: per adapter object
4494 * @smid: system request message index
4495 * @msix_index: MSIX table index supplied by the OS
4496 * @reply: reply message frame(lower 32bit addr)
4497 *
4498 * Return 1 meaning mf should be freed from _base_interrupt
4499 * 0 means the mf is freed from this function.
4500 */
4501u8
4502mpt3sas_port_enable_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
4503 u32 reply)
4504{
4505 MPI2DefaultReply_t *mpi_reply;
4506 u16 ioc_status;
4507
4508 if (ioc->port_enable_cmds.status == MPT3_CMD_NOT_USED)
4509 return 1;
4510
4511 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
4512 if (!mpi_reply)
4513 return 1;
4514
4515 if (mpi_reply->Function != MPI2_FUNCTION_PORT_ENABLE)
4516 return 1;
4517
4518 ioc->port_enable_cmds.status &= ~MPT3_CMD_PENDING;
4519 ioc->port_enable_cmds.status |= MPT3_CMD_COMPLETE;
4520 ioc->port_enable_cmds.status |= MPT3_CMD_REPLY_VALID;
4521 memcpy(ioc->port_enable_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
4522 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK;
4523 if (ioc_status != MPI2_IOCSTATUS_SUCCESS)
4524 ioc->port_enable_failed = 1;
4525
4526 if (ioc->is_driver_loading) {
4527 if (ioc_status == MPI2_IOCSTATUS_SUCCESS) {
4528 mpt3sas_port_enable_complete(ioc);
4529 return 1;
4530 } else {
4531 ioc->start_scan_failed = ioc_status;
4532 ioc->start_scan = 0;
4533 return 1;
4534 }
4535 }
4536 complete(&ioc->port_enable_cmds.done);
4537 return 1;
4538}
4539
4540/**
4541 * _base_send_port_enable - send port_enable(discovery stuff) to firmware
4542 * @ioc: per adapter object
f92363d1
SR		 4543 *
4544 * Returns 0 for success, non-zero for failure.
4545 */
4546static int
98c56ad3 4547_base_send_port_enable(struct MPT3SAS_ADAPTER *ioc)
f92363d1
SR		 4548{
4549 Mpi2PortEnableRequest_t *mpi_request;
4550 Mpi2PortEnableReply_t *mpi_reply;
4551 unsigned long timeleft;
4552 int r = 0;
4553 u16 smid;
4554 u16 ioc_status;
4555
4556 pr_info(MPT3SAS_FMT "sending port enable !!\n", ioc->name);
4557
4558 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
4559 pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
4560 ioc->name, __func__);
4561 return -EAGAIN;
4562 }
4563
4564 smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
4565 if (!smid) {
4566 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4567 ioc->name, __func__);
4568 return -EAGAIN;
4569 }
4570
4571 ioc->port_enable_cmds.status = MPT3_CMD_PENDING;
4572 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
4573 ioc->port_enable_cmds.smid = smid;
4574 memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
4575 mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
4576
4577 init_completion(&ioc->port_enable_cmds.done);
4578 mpt3sas_base_put_smid_default(ioc, smid);
4579 timeleft = wait_for_completion_timeout(&ioc->port_enable_cmds.done,
4580 300*HZ);
4581 if (!(ioc->port_enable_cmds.status & MPT3_CMD_COMPLETE)) {
4582 pr_err(MPT3SAS_FMT "%s: timeout\n",
4583 ioc->name, __func__);
4584 _debug_dump_mf(mpi_request,
4585 sizeof(Mpi2PortEnableRequest_t)/4);
4586 if (ioc->port_enable_cmds.status & MPT3_CMD_RESET)
4587 r = -EFAULT;
4588 else
4589 r = -ETIME;
4590 goto out;
4591 }
4592
4593 mpi_reply = ioc->port_enable_cmds.reply;
4594 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK;
4595 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
4596 pr_err(MPT3SAS_FMT "%s: failed with (ioc_status=0x%08x)\n",
4597 ioc->name, __func__, ioc_status);
4598 r = -EFAULT;
4599 goto out;
4600 }
4601
4602 out:
4603 ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED;
4604 pr_info(MPT3SAS_FMT "port enable: %s\n", ioc->name, ((r == 0) ?
4605 "SUCCESS" : "FAILED"));
4606 return r;
4607}
4608
4609/**
4610 * mpt3sas_port_enable - initiate firmware discovery (don't wait for reply)
4611 * @ioc: per adapter object
4612 *
4613 * Returns 0 for success, non-zero for failure.
4614 */
4615int
4616mpt3sas_port_enable(struct MPT3SAS_ADAPTER *ioc)
4617{
4618 Mpi2PortEnableRequest_t *mpi_request;
4619 u16 smid;
4620
4621 pr_info(MPT3SAS_FMT "sending port enable !!\n", ioc->name);
4622
4623 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
4624 pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
4625 ioc->name, __func__);
4626 return -EAGAIN;
4627 }
4628
4629 smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
4630 if (!smid) {
4631 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4632 ioc->name, __func__);
4633 return -EAGAIN;
4634 }
4635
4636 ioc->port_enable_cmds.status = MPT3_CMD_PENDING;
4637 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
4638 ioc->port_enable_cmds.smid = smid;
4639 memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
4640 mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
4641
4642 mpt3sas_base_put_smid_default(ioc, smid);
4643 return 0;
4644}
4645
4646/**
4647 * _base_determine_wait_on_discovery - desposition
4648 * @ioc: per adapter object
4649 *
4650 * Decide whether to wait on discovery to complete. Used to either
4651 * locate boot device, or report volumes ahead of physical devices.
4652 *
4653 * Returns 1 for wait, 0 for don't wait
4654 */
4655static int
4656_base_determine_wait_on_discovery(struct MPT3SAS_ADAPTER *ioc)
4657{
4658 /* We wait for discovery to complete if IR firmware is loaded.
4659 * The sas topology events arrive before PD events, so we need time to
4660 * turn on the bit in ioc->pd_handles to indicate PD
4661 * Also, it maybe required to report Volumes ahead of physical
4662 * devices when MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING is set.
4663 */
4664 if (ioc->ir_firmware)
4665 return 1;
4666
4667 /* if no Bios, then we don't need to wait */
4668 if (!ioc->bios_pg3.BiosVersion)
4669 return 0;
4670
4671 /* Bios is present, then we drop down here.
4672 *
4673 * If there any entries in the Bios Page 2, then we wait
4674 * for discovery to complete.
4675 */
4676
4677 /* Current Boot Device */
4678 if ((ioc->bios_pg2.CurrentBootDeviceForm &
4679 MPI2_BIOSPAGE2_FORM_MASK) ==
4680 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED &&
4681 /* Request Boot Device */
4682 (ioc->bios_pg2.ReqBootDeviceForm &
4683 MPI2_BIOSPAGE2_FORM_MASK) ==
4684 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED &&
4685 /* Alternate Request Boot Device */
4686 (ioc->bios_pg2.ReqAltBootDeviceForm &
4687 MPI2_BIOSPAGE2_FORM_MASK) ==
4688 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED)
4689 return 0;
4690
4691 return 1;
4692}
4693
4694/**
4695 * _base_unmask_events - turn on notification for this event
4696 * @ioc: per adapter object
4697 * @event: firmware event
4698 *
4699 * The mask is stored in ioc->event_masks.
4700 */
4701static void
4702_base_unmask_events(struct MPT3SAS_ADAPTER *ioc, u16 event)
4703{
4704 u32 desired_event;
4705
4706 if (event >= 128)
4707 return;
4708
4709 desired_event = (1 << (event % 32));
4710
4711 if (event < 32)
4712 ioc->event_masks[0] &= ~desired_event;
4713 else if (event < 64)
4714 ioc->event_masks[1] &= ~desired_event;
4715 else if (event < 96)
4716 ioc->event_masks[2] &= ~desired_event;
4717 else if (event < 128)
4718 ioc->event_masks[3] &= ~desired_event;
4719}
4720
4721/**
4722 * _base_event_notification - send event notification
4723 * @ioc: per adapter object
f92363d1
SR		 4724 *
4725 * Returns 0 for success, non-zero for failure.
4726 */
4727static int
98c56ad3 4728_base_event_notification(struct MPT3SAS_ADAPTER *ioc)
f92363d1
SR		 4729{
4730 Mpi2EventNotificationRequest_t *mpi_request;
4731 unsigned long timeleft;
4732 u16 smid;
4733 int r = 0;
4734 int i;
4735
4736 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4737 __func__));
4738
4739 if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
4740 pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
4741 ioc->name, __func__);
4742 return -EAGAIN;
4743 }
4744
4745 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
4746 if (!smid) {
4747 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4748 ioc->name, __func__);
4749 return -EAGAIN;
4750 }
4751 ioc->base_cmds.status = MPT3_CMD_PENDING;
4752 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
4753 ioc->base_cmds.smid = smid;
4754 memset(mpi_request, 0, sizeof(Mpi2EventNotificationRequest_t));
4755 mpi_request->Function = MPI2_FUNCTION_EVENT_NOTIFICATION;
4756 mpi_request->VF_ID = 0; /* TODO */
4757 mpi_request->VP_ID = 0;
4758 for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
4759 mpi_request->EventMasks[i] =
4760 cpu_to_le32(ioc->event_masks[i]);
4761 init_completion(&ioc->base_cmds.done);
4762 mpt3sas_base_put_smid_default(ioc, smid);
4763 timeleft = wait_for_completion_timeout(&ioc->base_cmds.done, 30*HZ);
4764 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
4765 pr_err(MPT3SAS_FMT "%s: timeout\n",
4766 ioc->name, __func__);
4767 _debug_dump_mf(mpi_request,
4768 sizeof(Mpi2EventNotificationRequest_t)/4);
4769 if (ioc->base_cmds.status & MPT3_CMD_RESET)
4770 r = -EFAULT;
4771 else
4772 r = -ETIME;
4773 } else
4774 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s: complete\n",
4775 ioc->name, __func__));
4776 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4777 return r;
4778}
4779
4780/**
4781 * mpt3sas_base_validate_event_type - validating event types
4782 * @ioc: per adapter object
4783 * @event: firmware event
4784 *
4785 * This will turn on firmware event notification when application
4786 * ask for that event. We don't mask events that are already enabled.
4787 */
4788void
4789mpt3sas_base_validate_event_type(struct MPT3SAS_ADAPTER *ioc, u32 *event_type)
4790{
4791 int i, j;
4792 u32 event_mask, desired_event;
4793 u8 send_update_to_fw;
4794
4795 for (i = 0, send_update_to_fw = 0; i <
4796 MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) {
4797 event_mask = ~event_type[i];
4798 desired_event = 1;
4799 for (j = 0; j < 32; j++) {
4800 if (!(event_mask & desired_event) &&
4801 (ioc->event_masks[i] & desired_event)) {
4802 ioc->event_masks[i] &= ~desired_event;
4803 send_update_to_fw = 1;
4804 }
4805 desired_event = (desired_event << 1);
4806 }
4807 }
4808
4809 if (!send_update_to_fw)
4810 return;
4811
4812 mutex_lock(&ioc->base_cmds.mutex);
98c56ad3 4813 _base_event_notification(ioc);
f92363d1
SR		 4814 mutex_unlock(&ioc->base_cmds.mutex);
4815}
4816
4817/**
4818 * _base_diag_reset - the "big hammer" start of day reset
4819 * @ioc: per adapter object
f92363d1
SR		 4820 *
4821 * Returns 0 for success, non-zero for failure.
4822 */
4823static int
98c56ad3 4824_base_diag_reset(struct MPT3SAS_ADAPTER *ioc)
f92363d1
SR		 4825{
4826 u32 host_diagnostic;
4827 u32 ioc_state;
4828 u32 count;
4829 u32 hcb_size;
4830
4831 pr_info(MPT3SAS_FMT "sending diag reset !!\n", ioc->name);
4832
4833 drsprintk(ioc, pr_info(MPT3SAS_FMT "clear interrupts\n",
4834 ioc->name));
4835
4836 count = 0;
4837 do {
4838 /* Write magic sequence to WriteSequence register
4839 * Loop until in diagnostic mode
4840 */
4841 drsprintk(ioc, pr_info(MPT3SAS_FMT
4842 "write magic sequence\n", ioc->name));
4843 writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
4844 writel(MPI2_WRSEQ_1ST_KEY_VALUE, &ioc->chip->WriteSequence);
4845 writel(MPI2_WRSEQ_2ND_KEY_VALUE, &ioc->chip->WriteSequence);
4846 writel(MPI2_WRSEQ_3RD_KEY_VALUE, &ioc->chip->WriteSequence);
4847 writel(MPI2_WRSEQ_4TH_KEY_VALUE, &ioc->chip->WriteSequence);
4848 writel(MPI2_WRSEQ_5TH_KEY_VALUE, &ioc->chip->WriteSequence);
4849 writel(MPI2_WRSEQ_6TH_KEY_VALUE, &ioc->chip->WriteSequence);
4850
4851 /* wait 100 msec */
98c56ad3 4852 msleep(100);
f92363d1
SR		 4853
4854 if (count++ > 20)
4855 goto out;
4856
4857 host_diagnostic = readl(&ioc->chip->HostDiagnostic);
4858 drsprintk(ioc, pr_info(MPT3SAS_FMT
4859 "wrote magic sequence: count(%d), host_diagnostic(0x%08x)\n",
4860 ioc->name, count, host_diagnostic));
4861
4862 } while ((host_diagnostic & MPI2_DIAG_DIAG_WRITE_ENABLE) == 0);
4863
4864 hcb_size = readl(&ioc->chip->HCBSize);
4865
4866 drsprintk(ioc, pr_info(MPT3SAS_FMT "diag reset: issued\n",
4867 ioc->name));
4868 writel(host_diagnostic | MPI2_DIAG_RESET_ADAPTER,
4869 &ioc->chip->HostDiagnostic);
4870
b453ff84 4871 /*This delay allows the chip PCIe hardware time to finish reset tasks*/
98c56ad3 4872 msleep(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000);
f92363d1 4873
b453ff84
SR		 4874 /* Approximately 300 second max wait */
4875 for (count = 0; count < (300000000 /
4876 MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC); count++) {
f92363d1
SR		 4877
4878 host_diagnostic = readl(&ioc->chip->HostDiagnostic);
4879
4880 if (host_diagnostic == 0xFFFFFFFF)
4881 goto out;
4882 if (!(host_diagnostic & MPI2_DIAG_RESET_ADAPTER))
4883 break;
4884
98c56ad3 4885 msleep(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC / 1000);
f92363d1
SR		 4886 }
4887
4888 if (host_diagnostic & MPI2_DIAG_HCB_MODE) {
4889
4890 drsprintk(ioc, pr_info(MPT3SAS_FMT
4891 "restart the adapter assuming the HCB Address points to good F/W\n",
4892 ioc->name));
4893 host_diagnostic &= ~MPI2_DIAG_BOOT_DEVICE_SELECT_MASK;
4894 host_diagnostic |= MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW;
4895 writel(host_diagnostic, &ioc->chip->HostDiagnostic);
4896
4897 drsprintk(ioc, pr_info(MPT3SAS_FMT
4898 "re-enable the HCDW\n", ioc->name));
4899 writel(hcb_size | MPI2_HCB_SIZE_HCB_ENABLE,
4900 &ioc->chip->HCBSize);
4901 }
4902
4903 drsprintk(ioc, pr_info(MPT3SAS_FMT "restart the adapter\n",
4904 ioc->name));
4905 writel(host_diagnostic & ~MPI2_DIAG_HOLD_IOC_RESET,
4906 &ioc->chip->HostDiagnostic);
4907
4908 drsprintk(ioc, pr_info(MPT3SAS_FMT
4909 "disable writes to the diagnostic register\n", ioc->name));
4910 writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
4911
4912 drsprintk(ioc, pr_info(MPT3SAS_FMT
4913 "Wait for FW to go to the READY state\n", ioc->name));
98c56ad3 4914 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, 20);
f92363d1
SR		 4915 if (ioc_state) {
4916 pr_err(MPT3SAS_FMT
4917 "%s: failed going to ready state (ioc_state=0x%x)\n",
4918 ioc->name, __func__, ioc_state);
4919 goto out;
4920 }
4921
4922 pr_info(MPT3SAS_FMT "diag reset: SUCCESS\n", ioc->name);
4923 return 0;
4924
4925 out:
4926 pr_err(MPT3SAS_FMT "diag reset: FAILED\n", ioc->name);
4927 return -EFAULT;
4928}
4929
4930/**
4931 * _base_make_ioc_ready - put controller in READY state
4932 * @ioc: per adapter object
f92363d1
SR		 4933 * @type: FORCE_BIG_HAMMER or SOFT_RESET
4934 *
4935 * Returns 0 for success, non-zero for failure.
4936 */
4937static int
98c56ad3 4938_base_make_ioc_ready(struct MPT3SAS_ADAPTER *ioc, enum reset_type type)
f92363d1
SR		 4939{
4940 u32 ioc_state;
4941 int rc;
4942 int count;
4943
4944 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4945 __func__));
4946
4947 if (ioc->pci_error_recovery)
4948 return 0;
4949
4950 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
4951 dhsprintk(ioc, pr_info(MPT3SAS_FMT "%s: ioc_state(0x%08x)\n",
4952 ioc->name, __func__, ioc_state));
4953
4954 /* if in RESET state, it should move to READY state shortly */
4955 count = 0;
4956 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_RESET) {
4957 while ((ioc_state & MPI2_IOC_STATE_MASK) !=
4958 MPI2_IOC_STATE_READY) {
4959 if (count++ == 10) {
4960 pr_err(MPT3SAS_FMT
4961 "%s: failed going to ready state (ioc_state=0x%x)\n",
4962 ioc->name, __func__, ioc_state);
4963 return -EFAULT;
4964 }
98c56ad3 4965 ssleep(1);
f92363d1
SR		 4966 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
4967 }
4968 }
4969
4970 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY)
4971 return 0;
4972
4973 if (ioc_state & MPI2_DOORBELL_USED) {
4974 dhsprintk(ioc, pr_info(MPT3SAS_FMT
4975 "unexpected doorbell active!\n",
4976 ioc->name));
4977 goto issue_diag_reset;
4978 }
4979
4980 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
4981 mpt3sas_base_fault_info(ioc, ioc_state &
4982 MPI2_DOORBELL_DATA_MASK);
4983 goto issue_diag_reset;
4984 }
4985
4986 if (type == FORCE_BIG_HAMMER)
4987 goto issue_diag_reset;
4988
4989 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL)
4990 if (!(_base_send_ioc_reset(ioc,
98c56ad3 4991 MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET, 15))) {
f92363d1
SR		 4992 return 0;
4993 }
4994
4995 issue_diag_reset:
98c56ad3 4996 rc = _base_diag_reset(ioc);
f92363d1
SR		 4997 return rc;
4998}
4999
5000/**
5001 * _base_make_ioc_operational - put controller in OPERATIONAL state
5002 * @ioc: per adapter object
f92363d1
SR		 5003 *
5004 * Returns 0 for success, non-zero for failure.
5005 */
5006static int
98c56ad3 5007_base_make_ioc_operational(struct MPT3SAS_ADAPTER *ioc)
f92363d1 5008{
5ec8a175 5009 int r, i, index;
f92363d1
SR		 5010 unsigned long flags;
5011 u32 reply_address;
5012 u16 smid;
5013 struct _tr_list *delayed_tr, *delayed_tr_next;
fd0331b3
SS		 5014 struct _sc_list *delayed_sc, *delayed_sc_next;
5015 struct _event_ack_list *delayed_event_ack, *delayed_event_ack_next;
7786ab6a 5016 u8 hide_flag;
f92363d1 5017 struct adapter_reply_queue *reply_q;
5ec8a175 5018 Mpi2ReplyDescriptorsUnion_t *reply_post_free_contig;
f92363d1
SR		 5019
5020 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
5021 __func__));
5022
5023 /* clean the delayed target reset list */
5024 list_for_each_entry_safe(delayed_tr, delayed_tr_next,
5025 &ioc->delayed_tr_list, list) {
5026 list_del(&delayed_tr->list);
5027 kfree(delayed_tr);
5028 }
5029
5030
5031 list_for_each_entry_safe(delayed_tr, delayed_tr_next,
5032 &ioc->delayed_tr_volume_list, list) {
5033 list_del(&delayed_tr->list);
5034 kfree(delayed_tr);
5035 }
5036
fd0331b3
SS		 5037 list_for_each_entry_safe(delayed_sc, delayed_sc_next,
5038 &ioc->delayed_sc_list, list) {
5039 list_del(&delayed_sc->list);
5040 kfree(delayed_sc);
5041 }
5042
5043 list_for_each_entry_safe(delayed_event_ack, delayed_event_ack_next,
5044 &ioc->delayed_event_ack_list, list) {
5045 list_del(&delayed_event_ack->list);
5046 kfree(delayed_event_ack);
5047 }
5048
f92363d1
SR		 5049 /* initialize the scsi lookup free list */
5050 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
5051 INIT_LIST_HEAD(&ioc->free_list);
5052 smid = 1;
5053 for (i = 0; i < ioc->scsiio_depth; i++, smid++) {
5054 INIT_LIST_HEAD(&ioc->scsi_lookup[i].chain_list);
5055 ioc->scsi_lookup[i].cb_idx = 0xFF;
5056 ioc->scsi_lookup[i].smid = smid;
5057 ioc->scsi_lookup[i].scmd = NULL;
7786ab6a 5058 ioc->scsi_lookup[i].direct_io = 0;
f92363d1
SR		 5059 list_add_tail(&ioc->scsi_lookup[i].tracker_list,
5060 &ioc->free_list);
5061 }
5062
5063 /* hi-priority queue */
5064 INIT_LIST_HEAD(&ioc->hpr_free_list);
5065 smid = ioc->hi_priority_smid;
5066 for (i = 0; i < ioc->hi_priority_depth; i++, smid++) {
5067 ioc->hpr_lookup[i].cb_idx = 0xFF;
5068 ioc->hpr_lookup[i].smid = smid;
5069 list_add_tail(&ioc->hpr_lookup[i].tracker_list,
5070 &ioc->hpr_free_list);
5071 }
5072
5073 /* internal queue */
5074 INIT_LIST_HEAD(&ioc->internal_free_list);
5075 smid = ioc->internal_smid;
5076 for (i = 0; i < ioc->internal_depth; i++, smid++) {
5077 ioc->internal_lookup[i].cb_idx = 0xFF;
5078 ioc->internal_lookup[i].smid = smid;
5079 list_add_tail(&ioc->internal_lookup[i].tracker_list,
5080 &ioc->internal_free_list);
5081 }
5082
5083 /* chain pool */
5084 INIT_LIST_HEAD(&ioc->free_chain_list);
5085 for (i = 0; i < ioc->chain_depth; i++)
5086 list_add_tail(&ioc->chain_lookup[i].tracker_list,
5087 &ioc->free_chain_list);
5088
5089 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
5090
5091 /* initialize Reply Free Queue */
5092 for (i = 0, reply_address = (u32)ioc->reply_dma ;
5093 i < ioc->reply_free_queue_depth ; i++, reply_address +=
5094 ioc->reply_sz)
5095 ioc->reply_free[i] = cpu_to_le32(reply_address);
5096
5097 /* initialize reply queues */
5098 if (ioc->is_driver_loading)
5099 _base_assign_reply_queues(ioc);
5100
5101 /* initialize Reply Post Free Queue */
5ec8a175
CO		 5102 index = 0;
5103 reply_post_free_contig = ioc->reply_post[0].reply_post_free;
f92363d1 5104 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
5ec8a175
CO		 5105 /*
5106 * If RDPQ is enabled, switch to the next allocation.
5107 * Otherwise advance within the contiguous region.
5108 */
5109 if (ioc->rdpq_array_enable) {
5110 reply_q->reply_post_free =
5111 ioc->reply_post[index++].reply_post_free;
5112 } else {
5113 reply_q->reply_post_free = reply_post_free_contig;
5114 reply_post_free_contig += ioc->reply_post_queue_depth;
5115 }
5116
f92363d1 5117 reply_q->reply_post_host_index = 0;
f92363d1
SR		 5118 for (i = 0; i < ioc->reply_post_queue_depth; i++)
5119 reply_q->reply_post_free[i].Words =
5120 cpu_to_le64(ULLONG_MAX);
5121 if (!_base_is_controller_msix_enabled(ioc))
5122 goto skip_init_reply_post_free_queue;
f92363d1
SR		 5123 }
5124 skip_init_reply_post_free_queue:
5125
98c56ad3 5126 r = _base_send_ioc_init(ioc);
f92363d1
SR		 5127 if (r)
5128 return r;
5129
5130 /* initialize reply free host index */
5131 ioc->reply_free_host_index = ioc->reply_free_queue_depth - 1;
5132 writel(ioc->reply_free_host_index, &ioc->chip->ReplyFreeHostIndex);
5133
5134 /* initialize reply post host index */
5135 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
fb77bb53
SR		 5136 if (ioc->msix96_vector)
5137 writel((reply_q->msix_index & 7)<<
5138 MPI2_RPHI_MSIX_INDEX_SHIFT,
5139 ioc->replyPostRegisterIndex[reply_q->msix_index/8]);
5140 else
5141 writel(reply_q->msix_index <<
5142 MPI2_RPHI_MSIX_INDEX_SHIFT,
5143 &ioc->chip->ReplyPostHostIndex);
5144
f92363d1
SR		 5145 if (!_base_is_controller_msix_enabled(ioc))
5146 goto skip_init_reply_post_host_index;
5147 }
5148
5149 skip_init_reply_post_host_index:
5150
5151 _base_unmask_interrupts(ioc);
98c56ad3 5152 r = _base_event_notification(ioc);
f92363d1
SR		 5153 if (r)
5154 return r;
5155
98c56ad3 5156 _base_static_config_pages(ioc);
f92363d1
SR		 5157
5158 if (ioc->is_driver_loading) {
7786ab6a
SR		 5159
5160 if (ioc->is_warpdrive && ioc->manu_pg10.OEMIdentifier
5161 == 0x80) {
5162 hide_flag = (u8) (
5163 le32_to_cpu(ioc->manu_pg10.OEMSpecificFlags0) &
5164 MFG_PAGE10_HIDE_SSDS_MASK);
5165 if (hide_flag != MFG_PAGE10_HIDE_SSDS_MASK)
5166 ioc->mfg_pg10_hide_flag = hide_flag;
5167 }
5168
f92363d1
SR		 5169 ioc->wait_for_discovery_to_complete =
5170 _base_determine_wait_on_discovery(ioc);
5171
5172 return r; /* scan_start and scan_finished support */
5173 }
5174
98c56ad3 5175 r = _base_send_port_enable(ioc);
f92363d1
SR		 5176 if (r)
5177 return r;
5178
5179 return r;
5180}
5181
5182/**
5183 * mpt3sas_base_free_resources - free resources controller resources
5184 * @ioc: per adapter object
5185 *
5186 * Return nothing.
5187 */
5188void
5189mpt3sas_base_free_resources(struct MPT3SAS_ADAPTER *ioc)
5190{
f92363d1
SR		 5191 dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
5192 __func__));
5193
08c4d550
SR		 5194 /* synchronizing freeing resource with pci_access_mutex lock */
5195 mutex_lock(&ioc->pci_access_mutex);
cf9bd21a
JL		 5196 if (ioc->chip_phys && ioc->chip) {
5197 _base_mask_interrupts(ioc);
5198 ioc->shost_recovery = 1;
98c56ad3 5199 _base_make_ioc_ready(ioc, SOFT_RESET);
cf9bd21a
JL		 5200 ioc->shost_recovery = 0;
5201 }
5202
580d4e31 5203 mpt3sas_base_unmap_resources(ioc);
08c4d550 5204 mutex_unlock(&ioc->pci_access_mutex);
f92363d1
SR		 5205 return;
5206}
5207
5208/**
5209 * mpt3sas_base_attach - attach controller instance
5210 * @ioc: per adapter object
5211 *
5212 * Returns 0 for success, non-zero for failure.
5213 */
5214int
5215mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc)
5216{
5217 int r, i;
5218 int cpu_id, last_cpu_id = 0;
5219
5220 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
5221 __func__));
5222
5223 /* setup cpu_msix_table */
5224 ioc->cpu_count = num_online_cpus();
5225 for_each_online_cpu(cpu_id)
5226 last_cpu_id = cpu_id;
5227 ioc->cpu_msix_table_sz = last_cpu_id + 1;
5228 ioc->cpu_msix_table = kzalloc(ioc->cpu_msix_table_sz, GFP_KERNEL);
5229 ioc->reply_queue_count = 1;
5230 if (!ioc->cpu_msix_table) {
5231 dfailprintk(ioc, pr_info(MPT3SAS_FMT
5232 "allocation for cpu_msix_table failed!!!\n",
5233 ioc->name));
5234 r = -ENOMEM;
5235 goto out_free_resources;
5236 }
5237
7786ab6a
SR		 5238 if (ioc->is_warpdrive) {
5239 ioc->reply_post_host_index = kcalloc(ioc->cpu_msix_table_sz,
5240 sizeof(resource_size_t *), GFP_KERNEL);
5241 if (!ioc->reply_post_host_index) {
5242 dfailprintk(ioc, pr_info(MPT3SAS_FMT "allocation "
5243 "for cpu_msix_table failed!!!\n", ioc->name));
5244 r = -ENOMEM;
5245 goto out_free_resources;
5246 }
5247 }
5248
9b05c91a
SR		 5249 ioc->rdpq_array_enable_assigned = 0;
5250 ioc->dma_mask = 0;
f92363d1
SR		 5251 r = mpt3sas_base_map_resources(ioc);
5252 if (r)
5253 goto out_free_resources;
5254
7786ab6a
SR		 5255 if (ioc->is_warpdrive) {
5256 ioc->reply_post_host_index[0] = (resource_size_t __iomem *)
5257 &ioc->chip->ReplyPostHostIndex;
5258
5259 for (i = 1; i < ioc->cpu_msix_table_sz; i++)
5260 ioc->reply_post_host_index[i] =
5261 (resource_size_t __iomem *)
5262 ((u8 __iomem *)&ioc->chip->Doorbell + (0x4000 + ((i - 1)
5263 * 4)));
5264 }
f92363d1
SR		 5265
5266 pci_set_drvdata(ioc->pdev, ioc->shost);
98c56ad3 5267 r = _base_get_ioc_facts(ioc);
f92363d1
SR		 5268 if (r)
5269 goto out_free_resources;
5270
471ef9d4
SR		 5271 switch (ioc->hba_mpi_version_belonged) {
5272 case MPI2_VERSION:
5273 ioc->build_sg_scmd = &_base_build_sg_scmd;
5274 ioc->build_sg = &_base_build_sg;
5275 ioc->build_zero_len_sge = &_base_build_zero_len_sge;
5276 break;
5277 case MPI25_VERSION:
b130b0d5 5278 case MPI26_VERSION:
471ef9d4
SR		 5279 /*
5280 * In SAS3.0,
5281 * SCSI_IO, SMP_PASSTHRU, SATA_PASSTHRU, Target Assist, and
5282 * Target Status - all require the IEEE formated scatter gather
5283 * elements.
5284 */
5285 ioc->build_sg_scmd = &_base_build_sg_scmd_ieee;
5286 ioc->build_sg = &_base_build_sg_ieee;
5287 ioc->build_zero_len_sge = &_base_build_zero_len_sge_ieee;
5288 ioc->sge_size_ieee = sizeof(Mpi2IeeeSgeSimple64_t);
5289 break;
5290 }
f92363d1
SR		 5291
5292 /*
5293 * These function pointers for other requests that don't
5294 * the require IEEE scatter gather elements.
5295 *
5296 * For example Configuration Pages and SAS IOUNIT Control don't.
5297 */
5298 ioc->build_sg_mpi = &_base_build_sg;
5299 ioc->build_zero_len_sge_mpi = &_base_build_zero_len_sge;
5300
98c56ad3 5301 r = _base_make_ioc_ready(ioc, SOFT_RESET);
f92363d1
SR		 5302 if (r)
5303 goto out_free_resources;
5304
5305 ioc->pfacts = kcalloc(ioc->facts.NumberOfPorts,
5306 sizeof(struct mpt3sas_port_facts), GFP_KERNEL);
5307 if (!ioc->pfacts) {
5308 r = -ENOMEM;
5309 goto out_free_resources;
5310 }
5311
5312 for (i = 0 ; i < ioc->facts.NumberOfPorts; i++) {
98c56ad3 5313 r = _base_get_port_facts(ioc, i);
f92363d1
SR		 5314 if (r)
5315 goto out_free_resources;
5316 }
5317
98c56ad3 5318 r = _base_allocate_memory_pools(ioc);
f92363d1
SR		 5319 if (r)
5320 goto out_free_resources;
5321
5322 init_waitqueue_head(&ioc->reset_wq);
5323
5324 /* allocate memory pd handle bitmask list */
5325 ioc->pd_handles_sz = (ioc->facts.MaxDevHandle / 8);
5326 if (ioc->facts.MaxDevHandle % 8)
5327 ioc->pd_handles_sz++;
5328 ioc->pd_handles = kzalloc(ioc->pd_handles_sz,
5329 GFP_KERNEL);
5330 if (!ioc->pd_handles) {
5331 r = -ENOMEM;
5332 goto out_free_resources;
5333 }
5334 ioc->blocking_handles = kzalloc(ioc->pd_handles_sz,
5335 GFP_KERNEL);
5336 if (!ioc->blocking_handles) {
5337 r = -ENOMEM;
5338 goto out_free_resources;
5339 }
5340
5341 ioc->fwfault_debug = mpt3sas_fwfault_debug;
5342
5343 /* base internal command bits */
5344 mutex_init(&ioc->base_cmds.mutex);
5345 ioc->base_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5346 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
5347
5348 /* port_enable command bits */
5349 ioc->port_enable_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5350 ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED;
5351
5352 /* transport internal command bits */
5353 ioc->transport_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5354 ioc->transport_cmds.status = MPT3_CMD_NOT_USED;
5355 mutex_init(&ioc->transport_cmds.mutex);
5356
5357 /* scsih internal command bits */
5358 ioc->scsih_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5359 ioc->scsih_cmds.status = MPT3_CMD_NOT_USED;
5360 mutex_init(&ioc->scsih_cmds.mutex);
5361
5362 /* task management internal command bits */
5363 ioc->tm_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5364 ioc->tm_cmds.status = MPT3_CMD_NOT_USED;
5365 mutex_init(&ioc->tm_cmds.mutex);
5366
5367 /* config page internal command bits */
5368 ioc->config_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5369 ioc->config_cmds.status = MPT3_CMD_NOT_USED;
5370 mutex_init(&ioc->config_cmds.mutex);
5371
5372 /* ctl module internal command bits */
5373 ioc->ctl_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5374 ioc->ctl_cmds.sense = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL);
5375 ioc->ctl_cmds.status = MPT3_CMD_NOT_USED;
5376 mutex_init(&ioc->ctl_cmds.mutex);
5377
5378 if (!ioc->base_cmds.reply || !ioc->transport_cmds.reply ||
5379 !ioc->scsih_cmds.reply || !ioc->tm_cmds.reply ||
5380 !ioc->config_cmds.reply || !ioc->ctl_cmds.reply ||
5381 !ioc->ctl_cmds.sense) {
5382 r = -ENOMEM;
5383 goto out_free_resources;
5384 }
5385
5386 for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
5387 ioc->event_masks[i] = -1;
5388
5389 /* here we enable the events we care about */
5390 _base_unmask_events(ioc, MPI2_EVENT_SAS_DISCOVERY);
5391 _base_unmask_events(ioc, MPI2_EVENT_SAS_BROADCAST_PRIMITIVE);
5392 _base_unmask_events(ioc, MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST);
5393 _base_unmask_events(ioc, MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE);
5394 _base_unmask_events(ioc, MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE);
5395 _base_unmask_events(ioc, MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST);
5396 _base_unmask_events(ioc, MPI2_EVENT_IR_VOLUME);
5397 _base_unmask_events(ioc, MPI2_EVENT_IR_PHYSICAL_DISK);
5398 _base_unmask_events(ioc, MPI2_EVENT_IR_OPERATION_STATUS);
5399 _base_unmask_events(ioc, MPI2_EVENT_LOG_ENTRY_ADDED);
2d8ce8c9 5400 _base_unmask_events(ioc, MPI2_EVENT_TEMP_THRESHOLD);
a470a51c
C		 5401 if (ioc->hba_mpi_version_belonged == MPI26_VERSION)
5402 _base_unmask_events(ioc, MPI2_EVENT_ACTIVE_CABLE_EXCEPTION);
f92363d1 5403
98c56ad3 5404 r = _base_make_ioc_operational(ioc);
f92363d1
SR		 5405 if (r)
5406 goto out_free_resources;
5407
16e179bd 5408 ioc->non_operational_loop = 0;
f92363d1
SR		 5409 return 0;
5410
5411 out_free_resources:
5412
5413 ioc->remove_host = 1;
5414
5415 mpt3sas_base_free_resources(ioc);
5416 _base_release_memory_pools(ioc);
5417 pci_set_drvdata(ioc->pdev, NULL);
5418 kfree(ioc->cpu_msix_table);
7786ab6a
SR		 5419 if (ioc->is_warpdrive)
5420 kfree(ioc->reply_post_host_index);
f92363d1
SR		 5421 kfree(ioc->pd_handles);
5422 kfree(ioc->blocking_handles);
5423 kfree(ioc->tm_cmds.reply);
5424 kfree(ioc->transport_cmds.reply);
5425 kfree(ioc->scsih_cmds.reply);
5426 kfree(ioc->config_cmds.reply);
5427 kfree(ioc->base_cmds.reply);
5428 kfree(ioc->port_enable_cmds.reply);
5429 kfree(ioc->ctl_cmds.reply);
5430 kfree(ioc->ctl_cmds.sense);
5431 kfree(ioc->pfacts);
5432 ioc->ctl_cmds.reply = NULL;
5433 ioc->base_cmds.reply = NULL;
5434 ioc->tm_cmds.reply = NULL;
5435 ioc->scsih_cmds.reply = NULL;
5436 ioc->transport_cmds.reply = NULL;
5437 ioc->config_cmds.reply = NULL;
5438 ioc->pfacts = NULL;
5439 return r;
5440}
5441
5442
5443/**
5444 * mpt3sas_base_detach - remove controller instance
5445 * @ioc: per adapter object
5446 *
5447 * Return nothing.
5448 */
5449void
5450mpt3sas_base_detach(struct MPT3SAS_ADAPTER *ioc)
5451{
5452 dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
5453 __func__));
5454
5455 mpt3sas_base_stop_watchdog(ioc);
5456 mpt3sas_base_free_resources(ioc);
5457 _base_release_memory_pools(ioc);
5458 pci_set_drvdata(ioc->pdev, NULL);
5459 kfree(ioc->cpu_msix_table);
7786ab6a
SR		 5460 if (ioc->is_warpdrive)
5461 kfree(ioc->reply_post_host_index);
f92363d1
SR		 5462 kfree(ioc->pd_handles);
5463 kfree(ioc->blocking_handles);
5464 kfree(ioc->pfacts);
5465 kfree(ioc->ctl_cmds.reply);
5466 kfree(ioc->ctl_cmds.sense);
5467 kfree(ioc->base_cmds.reply);
5468 kfree(ioc->port_enable_cmds.reply);
5469 kfree(ioc->tm_cmds.reply);
5470 kfree(ioc->transport_cmds.reply);
5471 kfree(ioc->scsih_cmds.reply);
5472 kfree(ioc->config_cmds.reply);
5473}
5474
5475/**
5476 * _base_reset_handler - reset callback handler (for base)
5477 * @ioc: per adapter object
5478 * @reset_phase: phase
5479 *
5480 * The handler for doing any required cleanup or initialization.
5481 *
5482 * The reset phase can be MPT3_IOC_PRE_RESET, MPT3_IOC_AFTER_RESET,
5483 * MPT3_IOC_DONE_RESET
5484 *
5485 * Return nothing.
5486 */
5487static void
5488_base_reset_handler(struct MPT3SAS_ADAPTER *ioc, int reset_phase)
5489{
5490 mpt3sas_scsih_reset_handler(ioc, reset_phase);
5491 mpt3sas_ctl_reset_handler(ioc, reset_phase);
5492 switch (reset_phase) {
5493 case MPT3_IOC_PRE_RESET:
5494 dtmprintk(ioc, pr_info(MPT3SAS_FMT
5495 "%s: MPT3_IOC_PRE_RESET\n", ioc->name, __func__));
5496 break;
5497 case MPT3_IOC_AFTER_RESET:
5498 dtmprintk(ioc, pr_info(MPT3SAS_FMT
5499 "%s: MPT3_IOC_AFTER_RESET\n", ioc->name, __func__));
5500 if (ioc->transport_cmds.status & MPT3_CMD_PENDING) {
5501 ioc->transport_cmds.status |= MPT3_CMD_RESET;
5502 mpt3sas_base_free_smid(ioc, ioc->transport_cmds.smid);
5503 complete(&ioc->transport_cmds.done);
5504 }
5505 if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
5506 ioc->base_cmds.status |= MPT3_CMD_RESET;
5507 mpt3sas_base_free_smid(ioc, ioc->base_cmds.smid);
5508 complete(&ioc->base_cmds.done);
5509 }
5510 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
5511 ioc->port_enable_failed = 1;
5512 ioc->port_enable_cmds.status |= MPT3_CMD_RESET;
5513 mpt3sas_base_free_smid(ioc, ioc->port_enable_cmds.smid);
5514 if (ioc->is_driver_loading) {
5515 ioc->start_scan_failed =
5516 MPI2_IOCSTATUS_INTERNAL_ERROR;
5517 ioc->start_scan = 0;
5518 ioc->port_enable_cmds.status =
5519 MPT3_CMD_NOT_USED;
5520 } else
5521 complete(&ioc->port_enable_cmds.done);
5522 }
5523 if (ioc->config_cmds.status & MPT3_CMD_PENDING) {
5524 ioc->config_cmds.status |= MPT3_CMD_RESET;
5525 mpt3sas_base_free_smid(ioc, ioc->config_cmds.smid);
5526 ioc->config_cmds.smid = USHRT_MAX;
5527 complete(&ioc->config_cmds.done);
5528 }
5529 break;
5530 case MPT3_IOC_DONE_RESET:
5531 dtmprintk(ioc, pr_info(MPT3SAS_FMT
5532 "%s: MPT3_IOC_DONE_RESET\n", ioc->name, __func__));
5533 break;
5534 }
5535}
5536
5537/**
5538 * _wait_for_commands_to_complete - reset controller
5539 * @ioc: Pointer to MPT_ADAPTER structure
f92363d1
SR		 5540 *
5541 * This function waiting(3s) for all pending commands to complete
5542 * prior to putting controller in reset.
5543 */
5544static void
98c56ad3 5545_wait_for_commands_to_complete(struct MPT3SAS_ADAPTER *ioc)
f92363d1
SR		 5546{
5547 u32 ioc_state;
5548 unsigned long flags;
5549 u16 i;
5550
5551 ioc->pending_io_count = 0;
f92363d1
SR		 5552
5553 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
5554 if ((ioc_state & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL)
5555 return;
5556
5557 /* pending command count */
5558 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
5559 for (i = 0; i < ioc->scsiio_depth; i++)
5560 if (ioc->scsi_lookup[i].cb_idx != 0xFF)
5561 ioc->pending_io_count++;
5562 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
5563
5564 if (!ioc->pending_io_count)
5565 return;
5566
5567 /* wait for pending commands to complete */
5568 wait_event_timeout(ioc->reset_wq, ioc->pending_io_count == 0, 10 * HZ);
5569}
5570
5571/**
5572 * mpt3sas_base_hard_reset_handler - reset controller
5573 * @ioc: Pointer to MPT_ADAPTER structure
f92363d1
SR		 5574 * @type: FORCE_BIG_HAMMER or SOFT_RESET
5575 *
5576 * Returns 0 for success, non-zero for failure.
5577 */
5578int
98c56ad3 5579mpt3sas_base_hard_reset_handler(struct MPT3SAS_ADAPTER *ioc,
f92363d1
SR		 5580 enum reset_type type)
5581{
5582 int r;
5583 unsigned long flags;
5584 u32 ioc_state;
5585 u8 is_fault = 0, is_trigger = 0;
5586
5587 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: enter\n", ioc->name,
5588 __func__));
5589
5590 if (ioc->pci_error_recovery) {
5591 pr_err(MPT3SAS_FMT "%s: pci error recovery reset\n",
5592 ioc->name, __func__);
5593 r = 0;
5594 goto out_unlocked;
5595 }
5596
5597 if (mpt3sas_fwfault_debug)
5598 mpt3sas_halt_firmware(ioc);
5599
f92363d1
SR		 5600 /* wait for an active reset in progress to complete */
5601 if (!mutex_trylock(&ioc->reset_in_progress_mutex)) {
5602 do {
5603 ssleep(1);
5604 } while (ioc->shost_recovery == 1);
5605 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: exit\n", ioc->name,
5606 __func__));
5607 return ioc->ioc_reset_in_progress_status;
5608 }
5609
5610 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
5611 ioc->shost_recovery = 1;
5612 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
5613
5614 if ((ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] &
5615 MPT3_DIAG_BUFFER_IS_REGISTERED) &&
5616 (!(ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] &
5617 MPT3_DIAG_BUFFER_IS_RELEASED))) {
5618 is_trigger = 1;
5619 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
5620 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
5621 is_fault = 1;
5622 }
5623 _base_reset_handler(ioc, MPT3_IOC_PRE_RESET);
98c56ad3 5624 _wait_for_commands_to_complete(ioc);
f92363d1 5625 _base_mask_interrupts(ioc);
98c56ad3 5626 r = _base_make_ioc_ready(ioc, type);
f92363d1
SR		 5627 if (r)
5628 goto out;
5629 _base_reset_handler(ioc, MPT3_IOC_AFTER_RESET);
5630
5631 /* If this hard reset is called while port enable is active, then
5632 * there is no reason to call make_ioc_operational
5633 */
5634 if (ioc->is_driver_loading && ioc->port_enable_failed) {
5635 ioc->remove_host = 1;
5636 r = -EFAULT;
5637 goto out;
5638 }
98c56ad3 5639 r = _base_get_ioc_facts(ioc);
f92363d1
SR		 5640 if (r)
5641 goto out;
9b05c91a
SR		 5642
5643 if (ioc->rdpq_array_enable && !ioc->rdpq_array_capable)
5644 panic("%s: Issue occurred with flashing controller firmware."
5645 "Please reboot the system and ensure that the correct"
5646 " firmware version is running\n", ioc->name);
5647
98c56ad3 5648 r = _base_make_ioc_operational(ioc);
f92363d1
SR		 5649 if (!r)
5650 _base_reset_handler(ioc, MPT3_IOC_DONE_RESET);
5651
5652 out:
5653 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: %s\n",
5654 ioc->name, __func__, ((r == 0) ? "SUCCESS" : "FAILED")));
5655
5656 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
5657 ioc->ioc_reset_in_progress_status = r;
5658 ioc->shost_recovery = 0;
5659 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
5660 ioc->ioc_reset_count++;
5661 mutex_unlock(&ioc->reset_in_progress_mutex);
5662
5663 out_unlocked:
5664 if ((r == 0) && is_trigger) {
5665 if (is_fault)
5666 mpt3sas_trigger_master(ioc, MASTER_TRIGGER_FW_FAULT);
5667 else
5668 mpt3sas_trigger_master(ioc,
5669 MASTER_TRIGGER_ADAPTER_RESET);
5670 }
5671 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: exit\n", ioc->name,
5672 __func__));
5673 return r;
5674}
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