[mirror_ubuntu-artful-kernel.git] / drivers / scsi / mvsas / mv_94xx.h

/*
 * Marvell 88SE94xx hardware specific head file
 *
 * Copyright 2007 Red Hat, Inc.
 * Copyright 2008 Marvell. <kewei@marvell.com>
 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
 *
 * This file is licensed under GPLv2.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; version 2 of the
 * License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
 * USA
*/

#ifndef _MVS94XX_REG_H_
#define _MVS94XX_REG_H_

#include <linux/types.h>

#define MAX_LINK_RATE		SAS_LINK_RATE_6_0_GBPS

enum VANIR_REVISION_ID {
	VANIR_A0_REV		= 0xA0,
	VANIR_B0_REV		= 0x01,
	VANIR_C0_REV		= 0x02,
	VANIR_C1_REV		= 0x03,
	VANIR_C2_REV		= 0xC2,
};

enum hw_registers {
	MVS_GBL_CTL		= 0x04,  /* global control */
	MVS_GBL_INT_STAT	= 0x00,  /* global irq status */
	MVS_GBL_PI		= 0x0C,  /* ports implemented bitmask */

	MVS_PHY_CTL		= 0x40,  /* SOC PHY Control */
	MVS_PORTS_IMP		= 0x9C,  /* SOC Port Implemented */

	MVS_GBL_PORT_TYPE	= 0xa0,  /* port type */

	MVS_CTL			= 0x100, /* SAS/SATA port configuration */
	MVS_PCS			= 0x104, /* SAS/SATA port control/status */
	MVS_CMD_LIST_LO		= 0x108, /* cmd list addr */
	MVS_CMD_LIST_HI		= 0x10C,
	MVS_RX_FIS_LO		= 0x110, /* RX FIS list addr */
	MVS_RX_FIS_HI		= 0x114,
	MVS_STP_REG_SET_0	= 0x118, /* STP/SATA Register Set Enable */
	MVS_STP_REG_SET_1	= 0x11C,
	MVS_TX_CFG		= 0x120, /* TX configuration */
	MVS_TX_LO		= 0x124, /* TX (delivery) ring addr */
	MVS_TX_HI		= 0x128,

	MVS_TX_PROD_IDX		= 0x12C, /* TX producer pointer */
	MVS_TX_CONS_IDX		= 0x130, /* TX consumer pointer (RO) */
	MVS_RX_CFG		= 0x134, /* RX configuration */
	MVS_RX_LO		= 0x138, /* RX (completion) ring addr */
	MVS_RX_HI		= 0x13C,
	MVS_RX_CONS_IDX		= 0x140, /* RX consumer pointer (RO) */

	MVS_INT_COAL		= 0x148, /* Int coalescing config */
	MVS_INT_COAL_TMOUT	= 0x14C, /* Int coalescing timeout */
	MVS_INT_STAT		= 0x150, /* Central int status */
	MVS_INT_MASK		= 0x154, /* Central int enable */
	MVS_INT_STAT_SRS_0	= 0x158, /* SATA register set status */
	MVS_INT_MASK_SRS_0	= 0x15C,
	MVS_INT_STAT_SRS_1	= 0x160,
	MVS_INT_MASK_SRS_1	= 0x164,
	MVS_NON_NCQ_ERR_0	= 0x168, /* SRS Non-specific NCQ Error */
	MVS_NON_NCQ_ERR_1	= 0x16C,
	MVS_CMD_ADDR		= 0x170, /* Command register port (addr) */
	MVS_CMD_DATA		= 0x174, /* Command register port (data) */
	MVS_MEM_PARITY_ERR	= 0x178, /* Memory parity error */

					 /* ports 1-3 follow after this */
	MVS_P0_INT_STAT		= 0x180, /* port0 interrupt status */
	MVS_P0_INT_MASK		= 0x184, /* port0 interrupt mask */
					 /* ports 5-7 follow after this */
	MVS_P4_INT_STAT		= 0x1A0, /* Port4 interrupt status */
	MVS_P4_INT_MASK		= 0x1A4, /* Port4 interrupt enable mask */

					 /* ports 1-3 follow after this */
	MVS_P0_SER_CTLSTAT	= 0x1D0, /* port0 serial control/status */
					 /* ports 5-7 follow after this */
	MVS_P4_SER_CTLSTAT	= 0x1E0, /* port4 serial control/status */

					 /* ports 1-3 follow after this */
	MVS_P0_CFG_ADDR		= 0x200, /* port0 phy register address */
	MVS_P0_CFG_DATA		= 0x204, /* port0 phy register data */
					 /* ports 5-7 follow after this */
	MVS_P4_CFG_ADDR		= 0x220, /* Port4 config address */
	MVS_P4_CFG_DATA		= 0x224, /* Port4 config data */

					 /* phys 1-3 follow after this */
	MVS_P0_VSR_ADDR		= 0x250, /* phy0 VSR address */
	MVS_P0_VSR_DATA		= 0x254, /* phy0 VSR data */
					 /* phys 1-3 follow after this */
					 /* multiplexing */
	MVS_P4_VSR_ADDR 	= 0x250, /* phy4 VSR address */
	MVS_P4_VSR_DATA 	= 0x254, /* phy4 VSR data */
	MVS_PA_VSR_ADDR		= 0x290, /* All port VSR addr */
	MVS_PA_VSR_PORT		= 0x294, /* All port VSR data */
	MVS_COMMAND_ACTIVE	= 0x300,
};

enum pci_cfg_registers {
	PCR_PHY_CTL		= 0x40,
	PCR_PHY_CTL2		= 0x90,
	PCR_DEV_CTRL		= 0x78,
	PCR_LINK_STAT		= 0x82,
};

/*  SAS/SATA Vendor Specific Port Registers */
enum sas_sata_vsp_regs {
	VSR_PHY_STAT		= 0x00 * 4, /* Phy Interrupt Status */
	VSR_PHY_MODE1		= 0x01 * 4, /* phy Interrupt Enable */
	VSR_PHY_MODE2		= 0x02 * 4, /* Phy Configuration */
	VSR_PHY_MODE3		= 0x03 * 4, /* Phy Status */
	VSR_PHY_MODE4		= 0x04 * 4, /* Phy Counter 0 */
	VSR_PHY_MODE5		= 0x05 * 4, /* Phy Counter 1 */
	VSR_PHY_MODE6		= 0x06 * 4, /* Event Counter Control */
	VSR_PHY_MODE7		= 0x07 * 4, /* Event Counter Select */
	VSR_PHY_MODE8		= 0x08 * 4, /* Event Counter 0 */
	VSR_PHY_MODE9		= 0x09 * 4, /* Event Counter 1 */
	VSR_PHY_MODE10		= 0x0A * 4, /* Event Counter 2 */
	VSR_PHY_MODE11		= 0x0B * 4, /* Event Counter 3 */
	VSR_PHY_ACT_LED		= 0x0C * 4, /* Activity LED control */

	VSR_PHY_FFE_CONTROL	= 0x10C,
	VSR_PHY_DFE_UPDATE_CRTL	= 0x110,
	VSR_REF_CLOCK_CRTL	= 0x1A0,
};

enum chip_register_bits {
	PHY_MIN_SPP_PHYS_LINK_RATE_MASK = (0x7 << 8),
	PHY_MAX_SPP_PHYS_LINK_RATE_MASK = (0x7 << 12),
	PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET = (16),
	PHY_NEG_SPP_PHYS_LINK_RATE_MASK =
			(0x3 << PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET),
};

enum pci_interrupt_cause {
	/*  MAIN_IRQ_CAUSE (R10200) Bits*/
	MVS_IRQ_COM_IN_I2O_IOP0        = (1 << 0),
	MVS_IRQ_COM_IN_I2O_IOP1        = (1 << 1),
	MVS_IRQ_COM_IN_I2O_IOP2        = (1 << 2),
	MVS_IRQ_COM_IN_I2O_IOP3        = (1 << 3),
	MVS_IRQ_COM_OUT_I2O_HOS0       = (1 << 4),
	MVS_IRQ_COM_OUT_I2O_HOS1       = (1 << 5),
	MVS_IRQ_COM_OUT_I2O_HOS2       = (1 << 6),
	MVS_IRQ_COM_OUT_I2O_HOS3       = (1 << 7),
	MVS_IRQ_PCIF_TO_CPU_DRBL0      = (1 << 8),
	MVS_IRQ_PCIF_TO_CPU_DRBL1      = (1 << 9),
	MVS_IRQ_PCIF_TO_CPU_DRBL2      = (1 << 10),
	MVS_IRQ_PCIF_TO_CPU_DRBL3      = (1 << 11),
	MVS_IRQ_PCIF_DRBL0             = (1 << 12),
	MVS_IRQ_PCIF_DRBL1             = (1 << 13),
	MVS_IRQ_PCIF_DRBL2             = (1 << 14),
	MVS_IRQ_PCIF_DRBL3             = (1 << 15),
	MVS_IRQ_XOR_A                  = (1 << 16),
	MVS_IRQ_XOR_B                  = (1 << 17),
	MVS_IRQ_SAS_A                  = (1 << 18),
	MVS_IRQ_SAS_B                  = (1 << 19),
	MVS_IRQ_CPU_CNTRL              = (1 << 20),
	MVS_IRQ_GPIO                   = (1 << 21),
	MVS_IRQ_UART                   = (1 << 22),
	MVS_IRQ_SPI                    = (1 << 23),
	MVS_IRQ_I2C                    = (1 << 24),
	MVS_IRQ_SGPIO                  = (1 << 25),
	MVS_IRQ_COM_ERR                = (1 << 29),
	MVS_IRQ_I2O_ERR                = (1 << 30),
	MVS_IRQ_PCIE_ERR               = (1 << 31),
};

union reg_phy_cfg {
	u32 v;
	struct {
		u32 phy_reset:1;
		u32 sas_support:1;
		u32 sata_support:1;
		u32 sata_host_mode:1;
		/*
		 * bit 2: 6Gbps support
		 * bit 1: 3Gbps support
		 * bit 0: 1.5Gbps support
		 */
		u32 speed_support:3;
		u32 snw_3_support:1;
		u32 tx_lnk_parity:1;
		/*
		 * bit 5: G1 (1.5Gbps) Without SSC
		 * bit 4: G1 (1.5Gbps) with SSC
		 * bit 3: G2 (3.0Gbps) Without SSC
		 * bit 2: G2 (3.0Gbps) with SSC
		 * bit 1: G3 (6.0Gbps) without SSC
		 * bit 0: G3 (6.0Gbps) with SSC
		 */
		u32 tx_spt_phs_lnk_rate:6;
		/* 8h: 1.5Gbps 9h: 3Gbps Ah: 6Gbps */
		u32 tx_lgcl_lnk_rate:4;
		u32 tx_ssc_type:1;
		u32 sata_spin_up_spt:1;
		u32 sata_spin_up_en:1;
		u32 bypass_oob:1;
		u32 disable_phy:1;
		u32 rsvd:8;
	} u;
};

#define MAX_SG_ENTRY		255

struct mvs_prd_imt {
#ifndef __BIG_ENDIAN
	__le32			len:22;
	u8			_r_a:2;
	u8			misc_ctl:4;
	u8			inter_sel:4;
#else
	u32			inter_sel:4;
	u32			misc_ctl:4;
	u32			_r_a:2;
	u32			len:22;
#endif
};

struct mvs_prd {
	/* 64-bit buffer address */
	__le64			addr;
	/* 22-bit length */
	__le32			im_len;
} __attribute__ ((packed));

/*
 * these registers are accessed through port vendor
 * specific address/data registers
 */
enum sas_sata_phy_regs {
	GENERATION_1_SETTING		= 0x118,
	GENERATION_1_2_SETTING		= 0x11C,
	GENERATION_2_3_SETTING		= 0x120,
	GENERATION_3_4_SETTING		= 0x124,
};

#define SPI_CTRL_REG_94XX           	0xc800
#define SPI_ADDR_REG_94XX            	0xc804
#define SPI_WR_DATA_REG_94XX         0xc808
#define SPI_RD_DATA_REG_94XX         	0xc80c
#define SPI_CTRL_READ_94XX         	(1U << 2)
#define SPI_ADDR_VLD_94XX         	(1U << 1)
#define SPI_CTRL_SpiStart_94XX     	(1U << 0)

static inline int
mv_ffc64(u64 v)
{
	u64 x = ~v;
	return x ? __ffs64(x) : -1;
}

#define r_reg_set_enable(i) \
	(((i) > 31) ? mr32(MVS_STP_REG_SET_1) : \
	mr32(MVS_STP_REG_SET_0))

#define w_reg_set_enable(i, tmp) \
	(((i) > 31) ? mw32(MVS_STP_REG_SET_1, tmp) : \
	mw32(MVS_STP_REG_SET_0, tmp))

extern const struct mvs_dispatch mvs_94xx_dispatch;
#endif
Commit	Line	Data
20b09c29 AY	1	/*
	2	* Marvell 88SE94xx hardware specific head file
	3	*
	4	* Copyright 2007 Red Hat, Inc.
	5	* Copyright 2008 Marvell. <kewei@marvell.com>
0b15fb1f	6	* Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
20b09c29 AY	7	*
	8	* This file is licensed under GPLv2.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; version 2 of the
	13	* License.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	18	* General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
	23	* USA
	24	*/
	25
	26	#ifndef _MVS94XX_REG_H_
	27	#define _MVS94XX_REG_H_
	28
	29	#include <linux/types.h>
	30
	31	#define MAX_LINK_RATE SAS_LINK_RATE_6_0_GBPS
	32
f1f82a91 XY	33	enum VANIR_REVISION_ID {
	34	VANIR_A0_REV = 0xA0,
	35	VANIR_B0_REV = 0x01,
	36	VANIR_C0_REV = 0x02,
	37	VANIR_C1_REV = 0x03,
	38	VANIR_C2_REV = 0xC2,
	39	};
	40
20b09c29 AY	41	enum hw_registers {
	42	MVS_GBL_CTL = 0x04, /* global control */
	43	MVS_GBL_INT_STAT = 0x00, /* global irq status */
	44	MVS_GBL_PI = 0x0C, /* ports implemented bitmask */
	45
	46	MVS_PHY_CTL = 0x40, /* SOC PHY Control */
	47	MVS_PORTS_IMP = 0x9C, /* SOC Port Implemented */
	48
	49	MVS_GBL_PORT_TYPE = 0xa0, /* port type */
	50
	51	MVS_CTL = 0x100, /* SAS/SATA port configuration */
	52	MVS_PCS = 0x104, /* SAS/SATA port control/status */
	53	MVS_CMD_LIST_LO = 0x108, /* cmd list addr */
	54	MVS_CMD_LIST_HI = 0x10C,
	55	MVS_RX_FIS_LO = 0x110, /* RX FIS list addr */
	56	MVS_RX_FIS_HI = 0x114,
	57	MVS_STP_REG_SET_0 = 0x118, /* STP/SATA Register Set Enable */
	58	MVS_STP_REG_SET_1 = 0x11C,
	59	MVS_TX_CFG = 0x120, /* TX configuration */
	60	MVS_TX_LO = 0x124, /* TX (delivery) ring addr */
	61	MVS_TX_HI = 0x128,
	62
	63	MVS_TX_PROD_IDX = 0x12C, /* TX producer pointer */
	64	MVS_TX_CONS_IDX = 0x130, /* TX consumer pointer (RO) */
	65	MVS_RX_CFG = 0x134, /* RX configuration */
	66	MVS_RX_LO = 0x138, /* RX (completion) ring addr */
	67	MVS_RX_HI = 0x13C,
	68	MVS_RX_CONS_IDX = 0x140, /* RX consumer pointer (RO) */
	69
	70	MVS_INT_COAL = 0x148, /* Int coalescing config */
	71	MVS_INT_COAL_TMOUT = 0x14C, /* Int coalescing timeout */
	72	MVS_INT_STAT = 0x150, /* Central int status */
	73	MVS_INT_MASK = 0x154, /* Central int enable */
	74	MVS_INT_STAT_SRS_0 = 0x158, /* SATA register set status */
	75	MVS_INT_MASK_SRS_0 = 0x15C,
	76	MVS_INT_STAT_SRS_1 = 0x160,
	77	MVS_INT_MASK_SRS_1 = 0x164,
	78	MVS_NON_NCQ_ERR_0 = 0x168, /* SRS Non-specific NCQ Error */
	79	MVS_NON_NCQ_ERR_1 = 0x16C,
	80	MVS_CMD_ADDR = 0x170, /* Command register port (addr) */
	81	MVS_CMD_DATA = 0x174, /* Command register port (data) */
	82	MVS_MEM_PARITY_ERR = 0x178, /* Memory parity error */
	83
	84	/* ports 1-3 follow after this */
	85	MVS_P0_INT_STAT = 0x180, /* port0 interrupt status */
	86	MVS_P0_INT_MASK = 0x184, /* port0 interrupt mask */
	87	/* ports 5-7 follow after this */
	88	MVS_P4_INT_STAT = 0x1A0, /* Port4 interrupt status */
	89	MVS_P4_INT_MASK = 0x1A4, /* Port4 interrupt enable mask */
	90
	91	/* ports 1-3 follow after this */
	92	MVS_P0_SER_CTLSTAT = 0x1D0, /* port0 serial control/status */
	93	/* ports 5-7 follow after this */
	94	MVS_P4_SER_CTLSTAT = 0x1E0, /* port4 serial control/status */
	95
	96	/* ports 1-3 follow after this */
	97	MVS_P0_CFG_ADDR = 0x200, /* port0 phy register address */
	98	MVS_P0_CFG_DATA = 0x204, /* port0 phy register data */
	99	/* ports 5-7 follow after this */
	100	MVS_P4_CFG_ADDR = 0x220, /* Port4 config address */
	101	MVS_P4_CFG_DATA = 0x224, /* Port4 config data */
	102
	103	/* phys 1-3 follow after this */
	104	MVS_P0_VSR_ADDR = 0x250, /* phy0 VSR address */
105	MVS_P0_VSR_DATA = 0x254, /* phy0 VSR data */
106	/* phys 1-3 follow after this */
107	/* multiplexing */
108	MVS_P4_VSR_ADDR = 0x250, /* phy4 VSR address */
109	MVS_P4_VSR_DATA = 0x254, /* phy4 VSR data */
110	MVS_PA_VSR_ADDR = 0x290, /* All port VSR addr */
111	MVS_PA_VSR_PORT = 0x294, /* All port VSR data */
a4632aae	112	MVS_COMMAND_ACTIVE = 0x300,
20b09c29 AY	113	};
	114
	115	enum pci_cfg_registers {
	116	PCR_PHY_CTL = 0x40,
	117	PCR_PHY_CTL2 = 0x90,
	118	PCR_DEV_CTRL = 0x78,
	119	PCR_LINK_STAT = 0x82,
	120	};
	121
	122	/* SAS/SATA Vendor Specific Port Registers */
	123	enum sas_sata_vsp_regs {
e144f7ef XY	124	VSR_PHY_STAT = 0x00 * 4, /* Phy Interrupt Status */
	125	VSR_PHY_MODE1 = 0x01 * 4, /* phy Interrupt Enable */
	126	VSR_PHY_MODE2 = 0x02 * 4, /* Phy Configuration */
	127	VSR_PHY_MODE3 = 0x03 * 4, /* Phy Status */
	128	VSR_PHY_MODE4 = 0x04 * 4, /* Phy Counter 0 */
	129	VSR_PHY_MODE5 = 0x05 * 4, /* Phy Counter 1 */
	130	VSR_PHY_MODE6 = 0x06 * 4, /* Event Counter Control */
	131	VSR_PHY_MODE7 = 0x07 * 4, /* Event Counter Select */
	132	VSR_PHY_MODE8 = 0x08 * 4, /* Event Counter 0 */
	133	VSR_PHY_MODE9 = 0x09 * 4, /* Event Counter 1 */
	134	VSR_PHY_MODE10 = 0x0A * 4, /* Event Counter 2 */
	135	VSR_PHY_MODE11 = 0x0B * 4, /* Event Counter 3 */
a4632aae	136	VSR_PHY_ACT_LED = 0x0C * 4, /* Activity LED control */
f1f82a91 XY	137
	138	VSR_PHY_FFE_CONTROL = 0x10C,
	139	VSR_PHY_DFE_UPDATE_CRTL = 0x110,
	140	VSR_REF_CLOCK_CRTL = 0x1A0,
20b09c29 AY	141	};
	142
	143	enum chip_register_bits {
	144	PHY_MIN_SPP_PHYS_LINK_RATE_MASK = (0x7 << 8),
84fbd0ce XY	145	PHY_MAX_SPP_PHYS_LINK_RATE_MASK = (0x7 << 12),
84fbd0ce XY	146	PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET = (16),
20b09c29 AY	147	PHY_NEG_SPP_PHYS_LINK_RATE_MASK =
	148	(0x3 << PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET),
	149	};
	150
	151	enum pci_interrupt_cause {
	152	/* MAIN_IRQ_CAUSE (R10200) Bits*/
8902b107 CG	153	MVS_IRQ_COM_IN_I2O_IOP0 = (1 << 0),
	154	MVS_IRQ_COM_IN_I2O_IOP1 = (1 << 1),
	155	MVS_IRQ_COM_IN_I2O_IOP2 = (1 << 2),
	156	MVS_IRQ_COM_IN_I2O_IOP3 = (1 << 3),
	157	MVS_IRQ_COM_OUT_I2O_HOS0 = (1 << 4),
	158	MVS_IRQ_COM_OUT_I2O_HOS1 = (1 << 5),
	159	MVS_IRQ_COM_OUT_I2O_HOS2 = (1 << 6),
	160	MVS_IRQ_COM_OUT_I2O_HOS3 = (1 << 7),
	161	MVS_IRQ_PCIF_TO_CPU_DRBL0 = (1 << 8),
	162	MVS_IRQ_PCIF_TO_CPU_DRBL1 = (1 << 9),
	163	MVS_IRQ_PCIF_TO_CPU_DRBL2 = (1 << 10),
	164	MVS_IRQ_PCIF_TO_CPU_DRBL3 = (1 << 11),
	165	MVS_IRQ_PCIF_DRBL0 = (1 << 12),
	166	MVS_IRQ_PCIF_DRBL1 = (1 << 13),
	167	MVS_IRQ_PCIF_DRBL2 = (1 << 14),
	168	MVS_IRQ_PCIF_DRBL3 = (1 << 15),
	169	MVS_IRQ_XOR_A = (1 << 16),
	170	MVS_IRQ_XOR_B = (1 << 17),
	171	MVS_IRQ_SAS_A = (1 << 18),
	172	MVS_IRQ_SAS_B = (1 << 19),
	173	MVS_IRQ_CPU_CNTRL = (1 << 20),
	174	MVS_IRQ_GPIO = (1 << 21),
	175	MVS_IRQ_UART = (1 << 22),
	176	MVS_IRQ_SPI = (1 << 23),
	177	MVS_IRQ_I2C = (1 << 24),
	178	MVS_IRQ_SGPIO = (1 << 25),
	179	MVS_IRQ_COM_ERR = (1 << 29),
	180	MVS_IRQ_I2O_ERR = (1 << 30),
	181	MVS_IRQ_PCIE_ERR = (1 << 31),
20b09c29 AY	182	};
20b09c29 AY	183
f1f82a91 XY	184	union reg_phy_cfg {
	185	u32 v;
	186	struct {
	187	u32 phy_reset:1;
	188	u32 sas_support:1;
	189	u32 sata_support:1;
	190	u32 sata_host_mode:1;
	191	/*
	192	* bit 2: 6Gbps support
	193	* bit 1: 3Gbps support
	194	* bit 0: 1.5Gbps support
	195	*/
	196	u32 speed_support:3;
	197	u32 snw_3_support:1;
	198	u32 tx_lnk_parity:1;
	199	/*
	200	* bit 5: G1 (1.5Gbps) Without SSC
	201	* bit 4: G1 (1.5Gbps) with SSC
	202	* bit 3: G2 (3.0Gbps) Without SSC
	203	* bit 2: G2 (3.0Gbps) with SSC
	204	* bit 1: G3 (6.0Gbps) without SSC
	205	* bit 0: G3 (6.0Gbps) with SSC
	206	*/
	207	u32 tx_spt_phs_lnk_rate:6;
	208	/* 8h: 1.5Gbps 9h: 3Gbps Ah: 6Gbps */
	209	u32 tx_lgcl_lnk_rate:4;
	210	u32 tx_ssc_type:1;
	211	u32 sata_spin_up_spt:1;
	212	u32 sata_spin_up_en:1;
	213	u32 bypass_oob:1;
	214	u32 disable_phy:1;
	215	u32 rsvd:8;
	216	} u;
	217	};
	218
20b09c29 AY	219	#define MAX_SG_ENTRY 255
	220
	221	struct mvs_prd_imt {
84fbd0ce	222	#ifndef __BIG_ENDIAN
20b09c29 AY	223	__le32 len:22;
	224	u8 _r_a:2;
	225	u8 misc_ctl:4;
	226	u8 inter_sel:4;
84fbd0ce XY	227	#else
	228	u32 inter_sel:4;
	229	u32 misc_ctl:4;
	230	u32 _r_a:2;
	231	u32 len:22;
	232	#endif
20b09c29 AY	233	};
	234
	235	struct mvs_prd {
	236	/* 64-bit buffer address */
	237	__le64 addr;
	238	/* 22-bit length */
84fbd0ce	239	__le32 im_len;
20b09c29 AY	240	} __attribute__ ((packed));
20b09c29 AY	241
f1f82a91 XY	242	/*
	243	* these registers are accessed through port vendor
	244	* specific address/data registers
	245	*/
	246	enum sas_sata_phy_regs {
	247	GENERATION_1_SETTING = 0x118,
	248	GENERATION_1_2_SETTING = 0x11C,
	249	GENERATION_2_3_SETTING = 0x120,
	250	GENERATION_3_4_SETTING = 0x124,
	251	};
	252
20b09c29 AY	253	#define SPI_CTRL_REG_94XX 0xc800
	254	#define SPI_ADDR_REG_94XX 0xc804
	255	#define SPI_WR_DATA_REG_94XX 0xc808
	256	#define SPI_RD_DATA_REG_94XX 0xc80c
	257	#define SPI_CTRL_READ_94XX (1U << 2)
	258	#define SPI_ADDR_VLD_94XX (1U << 1)
	259	#define SPI_CTRL_SpiStart_94XX (1U << 0)
	260
20b09c29 AY	261	static inline int
	262	mv_ffc64(u64 v)
	263	{
beecadea XW	264	u64 x = ~v;
beecadea XW	265	return x ? __ffs64(x) : -1;
20b09c29 AY	266	}
	267
	268	#define r_reg_set_enable(i) \
	269	(((i) > 31) ? mr32(MVS_STP_REG_SET_1) : \
	270	mr32(MVS_STP_REG_SET_0))
	271
	272	#define w_reg_set_enable(i, tmp) \
	273	(((i) > 31) ? mw32(MVS_STP_REG_SET_1, tmp) : \
	274	mw32(MVS_STP_REG_SET_0, tmp))
	275
	276	extern const struct mvs_dispatch mvs_94xx_dispatch;
	277	#endif
	278