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Merge tag 'stable/for-linus-3.19-rc0-tag' of git://git.kernel.org/pub/scm/linux/kerne...
[mirror_ubuntu-artful-kernel.git] / drivers / scsi / mvsas / mv_sas.c
CommitLineData
b5762948 1/*
20b09c29
AY		 2 * Marvell 88SE64xx/88SE94xx main function
3 *
4 * Copyright 2007 Red Hat, Inc.
5 * Copyright 2008 Marvell. <kewei@marvell.com>
0b15fb1f 6 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
20b09c29
AY		 7 *
8 * This file is licensed under GPLv2.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; version 2 of the
13 * License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
23 * USA
24*/
b5762948 25
dd4969a8 26#include "mv_sas.h"
b5762948 27
dd4969a8
JG		 28static int mvs_find_tag(struct mvs_info *mvi, struct sas_task *task, u32 *tag)
29{
30 if (task->lldd_task) {
31 struct mvs_slot_info *slot;
f9da3be5 32 slot = task->lldd_task;
20b09c29 33 *tag = slot->slot_tag;
dd4969a8
JG		 34 return 1;
35 }
36 return 0;
37}
8f261aaf 38
20b09c29 39void mvs_tag_clear(struct mvs_info *mvi, u32 tag)
dd4969a8 40{
b89e8f53 41 void *bitmap = mvi->tags;
dd4969a8
JG		 42 clear_bit(tag, bitmap);
43}
8f261aaf 44
20b09c29 45void mvs_tag_free(struct mvs_info *mvi, u32 tag)
dd4969a8
JG		 46{
47 mvs_tag_clear(mvi, tag);
48}
8f261aaf 49
20b09c29 50void mvs_tag_set(struct mvs_info *mvi, unsigned int tag)
dd4969a8 51{
b89e8f53 52 void *bitmap = mvi->tags;
dd4969a8
JG		 53 set_bit(tag, bitmap);
54}
8f261aaf 55
20b09c29 56inline int mvs_tag_alloc(struct mvs_info *mvi, u32 *tag_out)
dd4969a8
JG		 57{
58 unsigned int index, tag;
b89e8f53 59 void *bitmap = mvi->tags;
b5762948 60
20b09c29 61 index = find_first_zero_bit(bitmap, mvi->tags_num);
dd4969a8 62 tag = index;
20b09c29 63 if (tag >= mvi->tags_num)
dd4969a8
JG		 64 return -SAS_QUEUE_FULL;
65 mvs_tag_set(mvi, tag);
66 *tag_out = tag;
67 return 0;
68}
b5762948 69
dd4969a8
JG		 70void mvs_tag_init(struct mvs_info *mvi)
71{
72 int i;
20b09c29 73 for (i = 0; i < mvi->tags_num; ++i)
dd4969a8
JG		 74 mvs_tag_clear(mvi, i);
75}
b5762948 76
20b09c29
AY		 77struct mvs_info *mvs_find_dev_mvi(struct domain_device *dev)
78{
79 unsigned long i = 0, j = 0, hi = 0;
80 struct sas_ha_struct *sha = dev->port->ha;
81 struct mvs_info *mvi = NULL;
82 struct asd_sas_phy *phy;
83
84 while (sha->sas_port[i]) {
85 if (sha->sas_port[i] == dev->port) {
86 phy = container_of(sha->sas_port[i]->phy_list.next,
87 struct asd_sas_phy, port_phy_el);
88 j = 0;
89 while (sha->sas_phy[j]) {
90 if (sha->sas_phy[j] == phy)
91 break;
92 j++;
93 }
94 break;
95 }
96 i++;
97 }
98 hi = j/((struct mvs_prv_info *)sha->lldd_ha)->n_phy;
99 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[hi];
8f261aaf 100
20b09c29 101 return mvi;
8f261aaf 102
20b09c29 103}
8f261aaf 104
20b09c29
AY		 105int mvs_find_dev_phyno(struct domain_device *dev, int *phyno)
106{
107 unsigned long i = 0, j = 0, n = 0, num = 0;
9870d9a2
AY		 108 struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
109 struct mvs_info *mvi = mvi_dev->mvi_info;
20b09c29
AY		 110 struct sas_ha_struct *sha = dev->port->ha;
111
112 while (sha->sas_port[i]) {
113 if (sha->sas_port[i] == dev->port) {
114 struct asd_sas_phy *phy;
115 list_for_each_entry(phy,
116 &sha->sas_port[i]->phy_list, port_phy_el) {
117 j = 0;
118 while (sha->sas_phy[j]) {
119 if (sha->sas_phy[j] == phy)
120 break;
121 j++;
122 }
123 phyno[n] = (j >= mvi->chip->n_phy) ?
124 (j - mvi->chip->n_phy) : j;
125 num++;
126 n++;
dd4969a8 127 }
dd4969a8
JG		 128 break;
129 }
20b09c29
AY		 130 i++;
131 }
132 return num;
133}
134
534ff101
XY		 135struct mvs_device *mvs_find_dev_by_reg_set(struct mvs_info *mvi,
136 u8 reg_set)
137{
138 u32 dev_no;
139 for (dev_no = 0; dev_no < MVS_MAX_DEVICES; dev_no++) {
140 if (mvi->devices[dev_no].taskfileset == MVS_ID_NOT_MAPPED)
141 continue;
142
143 if (mvi->devices[dev_no].taskfileset == reg_set)
144 return &mvi->devices[dev_no];
145 }
146 return NULL;
147}
148
20b09c29
AY		 149static inline void mvs_free_reg_set(struct mvs_info *mvi,
150 struct mvs_device *dev)
151{
152 if (!dev) {
153 mv_printk("device has been free.\n");
154 return;
155 }
20b09c29
AY		 156 if (dev->taskfileset == MVS_ID_NOT_MAPPED)
157 return;
158 MVS_CHIP_DISP->free_reg_set(mvi, &dev->taskfileset);
159}
160
161static inline u8 mvs_assign_reg_set(struct mvs_info *mvi,
162 struct mvs_device *dev)
163{
164 if (dev->taskfileset != MVS_ID_NOT_MAPPED)
165 return 0;
166 return MVS_CHIP_DISP->assign_reg_set(mvi, &dev->taskfileset);
167}
168
169void mvs_phys_reset(struct mvs_info *mvi, u32 phy_mask, int hard)
170{
171 u32 no;
172 for_each_phy(phy_mask, phy_mask, no) {
173 if (!(phy_mask & 1))
174 continue;
175 MVS_CHIP_DISP->phy_reset(mvi, no, hard);
176 }
177}
178
20b09c29
AY		 179int mvs_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
180 void *funcdata)
181{
182 int rc = 0, phy_id = sas_phy->id;
183 u32 tmp, i = 0, hi;
184 struct sas_ha_struct *sha = sas_phy->ha;
185 struct mvs_info *mvi = NULL;
186
187 while (sha->sas_phy[i]) {
188 if (sha->sas_phy[i] == sas_phy)
189 break;
190 i++;
191 }
192 hi = i/((struct mvs_prv_info *)sha->lldd_ha)->n_phy;
193 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[hi];
194
195 switch (func) {
196 case PHY_FUNC_SET_LINK_RATE:
197 MVS_CHIP_DISP->phy_set_link_rate(mvi, phy_id, funcdata);
198 break;
8f261aaf 199
dd4969a8 200 case PHY_FUNC_HARD_RESET:
20b09c29 201 tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, phy_id);
dd4969a8
JG		 202 if (tmp & PHY_RST_HARD)
203 break;
a4632aae 204 MVS_CHIP_DISP->phy_reset(mvi, phy_id, MVS_HARD_RESET);
dd4969a8 205 break;
b5762948 206
dd4969a8 207 case PHY_FUNC_LINK_RESET:
20b09c29 208 MVS_CHIP_DISP->phy_enable(mvi, phy_id);
a4632aae 209 MVS_CHIP_DISP->phy_reset(mvi, phy_id, MVS_SOFT_RESET);
dd4969a8 210 break;
b5762948 211
dd4969a8 212 case PHY_FUNC_DISABLE:
20b09c29
AY		 213 MVS_CHIP_DISP->phy_disable(mvi, phy_id);
214 break;
dd4969a8
JG		 215 case PHY_FUNC_RELEASE_SPINUP_HOLD:
216 default:
ac013ed1 217 rc = -ENOSYS;
b5762948 218 }
20b09c29 219 msleep(200);
b5762948
JG		 220 return rc;
221}
222
6f039790
GKH		 223void mvs_set_sas_addr(struct mvs_info *mvi, int port_id, u32 off_lo,
224 u32 off_hi, u64 sas_addr)
20b09c29
AY		 225{
226 u32 lo = (u32)sas_addr;
227 u32 hi = (u32)(sas_addr>>32);
228
229 MVS_CHIP_DISP->write_port_cfg_addr(mvi, port_id, off_lo);
230 MVS_CHIP_DISP->write_port_cfg_data(mvi, port_id, lo);
231 MVS_CHIP_DISP->write_port_cfg_addr(mvi, port_id, off_hi);
232 MVS_CHIP_DISP->write_port_cfg_data(mvi, port_id, hi);
233}
234
dd4969a8 235static void mvs_bytes_dmaed(struct mvs_info *mvi, int i)
ee1f1c2e 236{
dd4969a8 237 struct mvs_phy *phy = &mvi->phy[i];
20b09c29
AY		 238 struct asd_sas_phy *sas_phy = &phy->sas_phy;
239 struct sas_ha_struct *sas_ha;
dd4969a8
JG		 240 if (!phy->phy_attached)
241 return;
242
20b09c29
AY		 243 if (!(phy->att_dev_info & PORT_DEV_TRGT_MASK)
244 && phy->phy_type & PORT_TYPE_SAS) {
245 return;
246 }
247
248 sas_ha = mvi->sas;
249 sas_ha->notify_phy_event(sas_phy, PHYE_OOB_DONE);
250
dd4969a8
JG		 251 if (sas_phy->phy) {
252 struct sas_phy *sphy = sas_phy->phy;
253
254 sphy->negotiated_linkrate = sas_phy->linkrate;
255 sphy->minimum_linkrate = phy->minimum_linkrate;
256 sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
257 sphy->maximum_linkrate = phy->maximum_linkrate;
20b09c29 258 sphy->maximum_linkrate_hw = MVS_CHIP_DISP->phy_max_link_rate();
ee1f1c2e 259 }
ee1f1c2e 260
dd4969a8
JG		 261 if (phy->phy_type & PORT_TYPE_SAS) {
262 struct sas_identify_frame *id;
b5762948 263
dd4969a8
JG		 264 id = (struct sas_identify_frame *)phy->frame_rcvd;
265 id->dev_type = phy->identify.device_type;
266 id->initiator_bits = SAS_PROTOCOL_ALL;
267 id->target_bits = phy->identify.target_port_protocols;
477f6d19
XY		 268
269 /* direct attached SAS device */
270 if (phy->att_dev_info & PORT_SSP_TRGT_MASK) {
271 MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_PHY_STAT);
272 MVS_CHIP_DISP->write_port_cfg_data(mvi, i, 0x00);
273 }
dd4969a8 274 } else if (phy->phy_type & PORT_TYPE_SATA) {
20b09c29 275 /*Nothing*/
dd4969a8 276 }
20b09c29
AY		 277 mv_dprintk("phy %d byte dmaded.\n", i + mvi->id * mvi->chip->n_phy);
278
279 sas_phy->frame_rcvd_size = phy->frame_rcvd_size;
280
281 mvi->sas->notify_port_event(sas_phy,
dd4969a8 282 PORTE_BYTES_DMAED);
ee1f1c2e
KW		 283}
284
dd4969a8 285void mvs_scan_start(struct Scsi_Host *shost)
b5762948 286{
20b09c29
AY		 287 int i, j;
288 unsigned short core_nr;
289 struct mvs_info *mvi;
290 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
84fbd0ce 291 struct mvs_prv_info *mvs_prv = sha->lldd_ha;
20b09c29
AY		 292
293 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
dd4969a8 294
20b09c29
AY		 295 for (j = 0; j < core_nr; j++) {
296 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[j];
297 for (i = 0; i < mvi->chip->n_phy; ++i)
298 mvs_bytes_dmaed(mvi, i);
dd4969a8 299 }
84fbd0ce 300 mvs_prv->scan_finished = 1;
b5762948
JG		 301}
302
dd4969a8 303int mvs_scan_finished(struct Scsi_Host *shost, unsigned long time)
b5762948 304{
84fbd0ce
XY		 305 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
306 struct mvs_prv_info *mvs_prv = sha->lldd_ha;
307
308 if (mvs_prv->scan_finished == 0)
dd4969a8 309 return 0;
84fbd0ce 310
b1124cd3 311 sas_drain_work(sha);
dd4969a8 312 return 1;
b5762948
JG		 313}
314
dd4969a8
JG		 315static int mvs_task_prep_smp(struct mvs_info *mvi,
316 struct mvs_task_exec_info *tei)
b5762948 317{
dd4969a8 318 int elem, rc, i;
7c237c5f 319 struct sas_ha_struct *sha = mvi->sas;
dd4969a8
JG		 320 struct sas_task *task = tei->task;
321 struct mvs_cmd_hdr *hdr = tei->hdr;
20b09c29
AY		 322 struct domain_device *dev = task->dev;
323 struct asd_sas_port *sas_port = dev->port;
7c237c5f
XY		 324 struct sas_phy *sphy = dev->phy;
325 struct asd_sas_phy *sas_phy = sha->sas_phy[sphy->number];
dd4969a8
JG		 326 struct scatterlist *sg_req, *sg_resp;
327 u32 req_len, resp_len, tag = tei->tag;
328 void *buf_tmp;
329 u8 *buf_oaf;
330 dma_addr_t buf_tmp_dma;
20b09c29 331 void *buf_prd;
dd4969a8 332 struct mvs_slot_info *slot = &mvi->slot_info[tag];
dd4969a8 333 u32 flags = (tei->n_elem << MCH_PRD_LEN_SHIFT);
b89e8f53 334
dd4969a8
JG		 335 /*
336 * DMA-map SMP request, response buffers
337 */
338 sg_req = &task->smp_task.smp_req;
20b09c29 339 elem = dma_map_sg(mvi->dev, sg_req, 1, PCI_DMA_TODEVICE);
dd4969a8
JG		 340 if (!elem)
341 return -ENOMEM;
342 req_len = sg_dma_len(sg_req);
b5762948 343
dd4969a8 344 sg_resp = &task->smp_task.smp_resp;
20b09c29 345 elem = dma_map_sg(mvi->dev, sg_resp, 1, PCI_DMA_FROMDEVICE);
dd4969a8
JG		 346 if (!elem) {
347 rc = -ENOMEM;
348 goto err_out;
349 }
20b09c29 350 resp_len = SB_RFB_MAX;
b5762948 351
dd4969a8
JG		 352 /* must be in dwords */
353 if ((req_len & 0x3) || (resp_len & 0x3)) {
354 rc = -EINVAL;
355 goto err_out_2;
b5762948
JG		 356 }
357
dd4969a8
JG		 358 /*
359 * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
360 */
b5762948 361
20b09c29 362 /* region 1: command table area (MVS_SSP_CMD_SZ bytes) ***** */
dd4969a8
JG		 363 buf_tmp = slot->buf;
364 buf_tmp_dma = slot->buf_dma;
b5762948 365
dd4969a8 366 hdr->cmd_tbl = cpu_to_le64(sg_dma_address(sg_req));
b5762948 367
dd4969a8
JG		 368 /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
369 buf_oaf = buf_tmp;
370 hdr->open_frame = cpu_to_le64(buf_tmp_dma);
b5762948 371
dd4969a8
JG		 372 buf_tmp += MVS_OAF_SZ;
373 buf_tmp_dma += MVS_OAF_SZ;
b5762948 374
20b09c29 375 /* region 3: PRD table *********************************** */
dd4969a8
JG		 376 buf_prd = buf_tmp;
377 if (tei->n_elem)
378 hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
379 else
380 hdr->prd_tbl = 0;
b5762948 381
20b09c29 382 i = MVS_CHIP_DISP->prd_size() * tei->n_elem;
dd4969a8
JG		 383 buf_tmp += i;
384 buf_tmp_dma += i;
b5762948 385
dd4969a8
JG		 386 /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
387 slot->response = buf_tmp;
388 hdr->status_buf = cpu_to_le64(buf_tmp_dma);
20b09c29
AY		 389 if (mvi->flags & MVF_FLAG_SOC)
390 hdr->reserved[0] = 0;
b5762948 391
dd4969a8
JG		 392 /*
393 * Fill in TX ring and command slot header
394 */
395 slot->tx = mvi->tx_prod;
396 mvi->tx[mvi->tx_prod] = cpu_to_le32((TXQ_CMD_SMP << TXQ_CMD_SHIFT) |
397 TXQ_MODE_I | tag |
7c237c5f 398 (MVS_PHY_ID << TXQ_PHY_SHIFT));
b5762948 399
dd4969a8
JG		 400 hdr->flags |= flags;
401 hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | ((req_len - 4) / 4));
402 hdr->tags = cpu_to_le32(tag);
403 hdr->data_len = 0;
b5762948 404
dd4969a8 405 /* generate open address frame hdr (first 12 bytes) */
20b09c29
AY		 406 /* initiator, SMP, ftype 1h */
407 buf_oaf[0] = (1 << 7) | (PROTOCOL_SMP << 4) | 0x01;
6ceae7c6 408 buf_oaf[1] = min(sas_port->linkrate, dev->linkrate) & 0xf;
dd4969a8 409 *(u16 *)(buf_oaf + 2) = 0xFFFF; /* SAS SPEC */
20b09c29 410 memcpy(buf_oaf + 4, dev->sas_addr, SAS_ADDR_SIZE);
dd4969a8
JG		 411
412 /* fill in PRD (scatter/gather) table, if any */
20b09c29 413 MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);
b5762948
JG		 414
415 return 0;
416
dd4969a8 417err_out_2:
20b09c29 418 dma_unmap_sg(mvi->dev, &tei->task->smp_task.smp_resp, 1,
dd4969a8 419 PCI_DMA_FROMDEVICE);
b5762948 420err_out:
20b09c29 421 dma_unmap_sg(mvi->dev, &tei->task->smp_task.smp_req, 1,
dd4969a8 422 PCI_DMA_TODEVICE);
8f261aaf 423 return rc;
8f261aaf
KW		 424}
425
dd4969a8 426static u32 mvs_get_ncq_tag(struct sas_task *task, u32 *tag)
8f261aaf 427{
dd4969a8 428 struct ata_queued_cmd *qc = task->uldd_task;
8f261aaf 429
dd4969a8
JG		 430 if (qc) {
431 if (qc->tf.command == ATA_CMD_FPDMA_WRITE ||
432 qc->tf.command == ATA_CMD_FPDMA_READ) {
433 *tag = qc->tag;
434 return 1;
435 }
8f261aaf 436 }
8f261aaf 437
dd4969a8 438 return 0;
8f261aaf
KW		 439}
440
dd4969a8
JG		 441static int mvs_task_prep_ata(struct mvs_info *mvi,
442 struct mvs_task_exec_info *tei)
b5762948 443{
7c237c5f 444 struct sas_ha_struct *sha = mvi->sas;
b5762948
JG		 445 struct sas_task *task = tei->task;
446 struct domain_device *dev = task->dev;
f9da3be5 447 struct mvs_device *mvi_dev = dev->lldd_dev;
b5762948
JG		 448 struct mvs_cmd_hdr *hdr = tei->hdr;
449 struct asd_sas_port *sas_port = dev->port;
7c237c5f
XY		 450 struct sas_phy *sphy = dev->phy;
451 struct asd_sas_phy *sas_phy = sha->sas_phy[sphy->number];
8f261aaf 452 struct mvs_slot_info *slot;
20b09c29
AY		 453 void *buf_prd;
454 u32 tag = tei->tag, hdr_tag;
455 u32 flags, del_q;
b5762948
JG		 456 void *buf_tmp;
457 u8 *buf_cmd, *buf_oaf;
458 dma_addr_t buf_tmp_dma;
8f261aaf
KW		 459 u32 i, req_len, resp_len;
460 const u32 max_resp_len = SB_RFB_MAX;
461
20b09c29
AY		 462 if (mvs_assign_reg_set(mvi, mvi_dev) == MVS_ID_NOT_MAPPED) {
463 mv_dprintk("Have not enough regiset for dev %d.\n",
464 mvi_dev->device_id);
8f261aaf 465 return -EBUSY;
20b09c29 466 }
8f261aaf
KW		 467 slot = &mvi->slot_info[tag];
468 slot->tx = mvi->tx_prod;
20b09c29
AY		 469 del_q = TXQ_MODE_I | tag |
470 (TXQ_CMD_STP << TXQ_CMD_SHIFT) |
7c237c5f 471 (MVS_PHY_ID << TXQ_PHY_SHIFT) |
20b09c29
AY		 472 (mvi_dev->taskfileset << TXQ_SRS_SHIFT);
473 mvi->tx[mvi->tx_prod] = cpu_to_le32(del_q);
474
20b09c29
AY		 475 if (task->data_dir == DMA_FROM_DEVICE)
476 flags = (MVS_CHIP_DISP->prd_count() << MCH_PRD_LEN_SHIFT);
477 else
478 flags = (tei->n_elem << MCH_PRD_LEN_SHIFT);
8882f081 479
b5762948
JG		 480 if (task->ata_task.use_ncq)
481 flags |= MCH_FPDMA;
8f261aaf
KW		 482 if (dev->sata_dev.command_set == ATAPI_COMMAND_SET) {
483 if (task->ata_task.fis.command != ATA_CMD_ID_ATAPI)
484 flags |= MCH_ATAPI;
485 }
486
b5762948 487 hdr->flags = cpu_to_le32(flags);
8f261aaf 488
20b09c29
AY		 489 if (task->ata_task.use_ncq && mvs_get_ncq_tag(task, &hdr_tag))
490 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
4e52fc0a 491 else
20b09c29
AY		 492 hdr_tag = tag;
493
494 hdr->tags = cpu_to_le32(hdr_tag);
495
b5762948
JG		 496 hdr->data_len = cpu_to_le32(task->total_xfer_len);
497
498 /*
499 * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
500 */
b5762948 501
8f261aaf
KW		 502 /* region 1: command table area (MVS_ATA_CMD_SZ bytes) ************** */
503 buf_cmd = buf_tmp = slot->buf;
b5762948
JG		 504 buf_tmp_dma = slot->buf_dma;
505
506 hdr->cmd_tbl = cpu_to_le64(buf_tmp_dma);
507
508 buf_tmp += MVS_ATA_CMD_SZ;
509 buf_tmp_dma += MVS_ATA_CMD_SZ;
510
8f261aaf 511 /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
b5762948
JG		 512 /* used for STP. unused for SATA? */
513 buf_oaf = buf_tmp;
514 hdr->open_frame = cpu_to_le64(buf_tmp_dma);
515
516 buf_tmp += MVS_OAF_SZ;
517 buf_tmp_dma += MVS_OAF_SZ;
518
8f261aaf 519 /* region 3: PRD table ********************************************* */
b5762948 520 buf_prd = buf_tmp;
20b09c29 521
8f261aaf
KW		 522 if (tei->n_elem)
523 hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
524 else
525 hdr->prd_tbl = 0;
20b09c29 526 i = MVS_CHIP_DISP->prd_size() * MVS_CHIP_DISP->prd_count();
b5762948 527
b5762948
JG		 528 buf_tmp += i;
529 buf_tmp_dma += i;
530
8f261aaf 531 /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
b5762948
JG		 532 slot->response = buf_tmp;
533 hdr->status_buf = cpu_to_le64(buf_tmp_dma);
20b09c29
AY		 534 if (mvi->flags & MVF_FLAG_SOC)
535 hdr->reserved[0] = 0;
b5762948 536
8f261aaf 537 req_len = sizeof(struct host_to_dev_fis);
b5762948 538 resp_len = MVS_SLOT_BUF_SZ - MVS_ATA_CMD_SZ -
8f261aaf 539 sizeof(struct mvs_err_info) - i;
b5762948
JG		 540
541 /* request, response lengths */
8f261aaf 542 resp_len = min(resp_len, max_resp_len);
b5762948
JG		 543 hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | (req_len / 4));
544
20b09c29
AY		 545 if (likely(!task->ata_task.device_control_reg_update))
546 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
b5762948 547 /* fill in command FIS and ATAPI CDB */
8f261aaf
KW		 548 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
549 if (dev->sata_dev.command_set == ATAPI_COMMAND_SET)
550 memcpy(buf_cmd + STP_ATAPI_CMD,
551 task->ata_task.atapi_packet, 16);
552
553 /* generate open address frame hdr (first 12 bytes) */
20b09c29
AY		 554 /* initiator, STP, ftype 1h */
555 buf_oaf[0] = (1 << 7) | (PROTOCOL_STP << 4) | 0x1;
6ceae7c6 556 buf_oaf[1] = min(sas_port->linkrate, dev->linkrate) & 0xf;
20b09c29
AY		 557 *(u16 *)(buf_oaf + 2) = cpu_to_be16(mvi_dev->device_id + 1);
558 memcpy(buf_oaf + 4, dev->sas_addr, SAS_ADDR_SIZE);
b5762948
JG		 559
560 /* fill in PRD (scatter/gather) table, if any */
20b09c29 561 MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);
8882f081 562
20b09c29 563 if (task->data_dir == DMA_FROM_DEVICE)
8882f081 564 MVS_CHIP_DISP->dma_fix(mvi, sas_port->phy_mask,
20b09c29 565 TRASH_BUCKET_SIZE, tei->n_elem, buf_prd);
8882f081 566
b5762948
JG		 567 return 0;
568}
569
570static int mvs_task_prep_ssp(struct mvs_info *mvi,
20b09c29
AY		 571 struct mvs_task_exec_info *tei, int is_tmf,
572 struct mvs_tmf_task *tmf)
b5762948
JG		 573{
574 struct sas_task *task = tei->task;
b5762948 575 struct mvs_cmd_hdr *hdr = tei->hdr;
8f261aaf 576 struct mvs_port *port = tei->port;
20b09c29 577 struct domain_device *dev = task->dev;
f9da3be5 578 struct mvs_device *mvi_dev = dev->lldd_dev;
20b09c29 579 struct asd_sas_port *sas_port = dev->port;
b5762948 580 struct mvs_slot_info *slot;
20b09c29 581 void *buf_prd;
b5762948
JG		 582 struct ssp_frame_hdr *ssp_hdr;
583 void *buf_tmp;
584 u8 *buf_cmd, *buf_oaf, fburst = 0;
585 dma_addr_t buf_tmp_dma;
586 u32 flags;
8f261aaf
KW		 587 u32 resp_len, req_len, i, tag = tei->tag;
588 const u32 max_resp_len = SB_RFB_MAX;
20b09c29 589 u32 phy_mask;
b5762948
JG		 590
591 slot = &mvi->slot_info[tag];
592
20b09c29
AY		 593 phy_mask = ((port->wide_port_phymap) ? port->wide_port_phymap :
594 sas_port->phy_mask) & TXQ_PHY_MASK;
595
8f261aaf
KW		 596 slot->tx = mvi->tx_prod;
597 mvi->tx[mvi->tx_prod] = cpu_to_le32(TXQ_MODE_I | tag |
598 (TXQ_CMD_SSP << TXQ_CMD_SHIFT) |
4e52fc0a 599 (phy_mask << TXQ_PHY_SHIFT));
b5762948
JG		 600
601 flags = MCH_RETRY;
602 if (task->ssp_task.enable_first_burst) {
603 flags |= MCH_FBURST;
604 fburst = (1 << 7);
605 }
2b288133
AY		 606 if (is_tmf)
607 flags |= (MCH_SSP_FR_TASK << MCH_SSP_FR_TYPE_SHIFT);
84fbd0ce
XY		 608 else
609 flags |= (MCH_SSP_FR_CMD << MCH_SSP_FR_TYPE_SHIFT);
610
2b288133 611 hdr->flags = cpu_to_le32(flags | (tei->n_elem << MCH_PRD_LEN_SHIFT));
b5762948
JG		 612 hdr->tags = cpu_to_le32(tag);
613 hdr->data_len = cpu_to_le32(task->total_xfer_len);
614
615 /*
616 * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
617 */
b5762948 618
8f261aaf
KW		 619 /* region 1: command table area (MVS_SSP_CMD_SZ bytes) ************** */
620 buf_cmd = buf_tmp = slot->buf;
b5762948
JG		 621 buf_tmp_dma = slot->buf_dma;
622
623 hdr->cmd_tbl = cpu_to_le64(buf_tmp_dma);
624
625 buf_tmp += MVS_SSP_CMD_SZ;
626 buf_tmp_dma += MVS_SSP_CMD_SZ;
627
8f261aaf 628 /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
b5762948
JG		 629 buf_oaf = buf_tmp;
630 hdr->open_frame = cpu_to_le64(buf_tmp_dma);
631
632 buf_tmp += MVS_OAF_SZ;
633 buf_tmp_dma += MVS_OAF_SZ;
634
8f261aaf 635 /* region 3: PRD table ********************************************* */
b5762948 636 buf_prd = buf_tmp;
8f261aaf
KW		 637 if (tei->n_elem)
638 hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
639 else
640 hdr->prd_tbl = 0;
b5762948 641
20b09c29 642 i = MVS_CHIP_DISP->prd_size() * tei->n_elem;
b5762948
JG		 643 buf_tmp += i;
644 buf_tmp_dma += i;
645
8f261aaf 646 /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
b5762948
JG		 647 slot->response = buf_tmp;
648 hdr->status_buf = cpu_to_le64(buf_tmp_dma);
20b09c29
AY		 649 if (mvi->flags & MVF_FLAG_SOC)
650 hdr->reserved[0] = 0;
b5762948 651
b5762948 652 resp_len = MVS_SLOT_BUF_SZ - MVS_SSP_CMD_SZ - MVS_OAF_SZ -
8f261aaf
KW		 653 sizeof(struct mvs_err_info) - i;
654 resp_len = min(resp_len, max_resp_len);
655
656 req_len = sizeof(struct ssp_frame_hdr) + 28;
b5762948
JG		 657
658 /* request, response lengths */
659 hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | (req_len / 4));
660
661 /* generate open address frame hdr (first 12 bytes) */
20b09c29
AY		 662 /* initiator, SSP, ftype 1h */
663 buf_oaf[0] = (1 << 7) | (PROTOCOL_SSP << 4) | 0x1;
6ceae7c6 664 buf_oaf[1] = min(sas_port->linkrate, dev->linkrate) & 0xf;
20b09c29
AY		 665 *(u16 *)(buf_oaf + 2) = cpu_to_be16(mvi_dev->device_id + 1);
666 memcpy(buf_oaf + 4, dev->sas_addr, SAS_ADDR_SIZE);
b5762948 667
8f261aaf
KW		 668 /* fill in SSP frame header (Command Table.SSP frame header) */
669 ssp_hdr = (struct ssp_frame_hdr *)buf_cmd;
20b09c29
AY		 670
671 if (is_tmf)
672 ssp_hdr->frame_type = SSP_TASK;
673 else
674 ssp_hdr->frame_type = SSP_COMMAND;
675
676 memcpy(ssp_hdr->hashed_dest_addr, dev->hashed_sas_addr,
b5762948
JG		 677 HASHED_SAS_ADDR_SIZE);
678 memcpy(ssp_hdr->hashed_src_addr,
20b09c29 679 dev->hashed_sas_addr, HASHED_SAS_ADDR_SIZE);
b5762948
JG		 680 ssp_hdr->tag = cpu_to_be16(tag);
681
20b09c29 682 /* fill in IU for TASK and Command Frame */
b5762948
JG		 683 buf_cmd += sizeof(*ssp_hdr);
684 memcpy(buf_cmd, &task->ssp_task.LUN, 8);
b5762948 685
20b09c29
AY		 686 if (ssp_hdr->frame_type != SSP_TASK) {
687 buf_cmd[9] = fburst | task->ssp_task.task_attr |
688 (task->ssp_task.task_prio << 3);
e73823f7
JB		 689 memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd,
690 task->ssp_task.cmd->cmd_len);
20b09c29
AY		 691 } else{
692 buf_cmd[10] = tmf->tmf;
693 switch (tmf->tmf) {
694 case TMF_ABORT_TASK:
695 case TMF_QUERY_TASK:
696 buf_cmd[12] =
697 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
698 buf_cmd[13] =
699 tmf->tag_of_task_to_be_managed & 0xff;
700 break;
701 default:
702 break;
703 }
b5762948 704 }
20b09c29
AY		 705 /* fill in PRD (scatter/gather) table, if any */
706 MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);
b5762948
JG		 707 return 0;
708}
709
aa9f8328 710#define DEV_IS_GONE(mvi_dev) ((!mvi_dev || (mvi_dev->dev_type == SAS_PHY_UNUSED)))
0b15fb1f
XY		 711static int mvs_task_prep(struct sas_task *task, struct mvs_info *mvi, int is_tmf,
712 struct mvs_tmf_task *tmf, int *pass)
b5762948 713{
8f261aaf 714 struct domain_device *dev = task->dev;
0b15fb1f 715 struct mvs_device *mvi_dev = dev->lldd_dev;
b5762948 716 struct mvs_task_exec_info tei;
4e52fc0a 717 struct mvs_slot_info *slot;
0b15fb1f
XY		 718 u32 tag = 0xdeadbeef, n_elem = 0;
719 int rc = 0;
b5762948 720
20b09c29 721 if (!dev->port) {
0b15fb1f 722 struct task_status_struct *tsm = &task->task_status;
20b09c29
AY		 723
724 tsm->resp = SAS_TASK_UNDELIVERED;
725 tsm->stat = SAS_PHY_DOWN;
0b15fb1f
XY		 726 /*
727 * libsas will use dev->port, should
728 * not call task_done for sata
729 */
aa9f8328 730 if (dev->dev_type != SAS_SATA_DEV)
0b15fb1f
XY		 731 task->task_done(task);
732 return rc;
20b09c29
AY		 733 }
734
0b15fb1f
XY		 735 if (DEV_IS_GONE(mvi_dev)) {
736 if (mvi_dev)
737 mv_dprintk("device %d not ready.\n",
738 mvi_dev->device_id);
739 else
740 mv_dprintk("device %016llx not ready.\n",
741 SAS_ADDR(dev->sas_addr));
20b09c29
AY		 742
743 rc = SAS_PHY_DOWN;
0b15fb1f
XY		 744 return rc;
745 }
746 tei.port = dev->port->lldd_port;
747 if (tei.port && !tei.port->port_attached && !tmf) {
748 if (sas_protocol_ata(task->task_proto)) {
749 struct task_status_struct *ts = &task->task_status;
750 mv_dprintk("SATA/STP port %d does not attach"
751 "device.\n", dev->port->id);
752 ts->resp = SAS_TASK_COMPLETE;
753 ts->stat = SAS_PHY_DOWN;
20b09c29 754
0b15fb1f 755 task->task_done(task);
dd4969a8 756
dd4969a8 757 } else {
0b15fb1f
XY		 758 struct task_status_struct *ts = &task->task_status;
759 mv_dprintk("SAS port %d does not attach"
760 "device.\n", dev->port->id);
761 ts->resp = SAS_TASK_UNDELIVERED;
762 ts->stat = SAS_PHY_DOWN;
763 task->task_done(task);
dd4969a8 764 }
0b15fb1f
XY		 765 return rc;
766 }
dd4969a8 767
0b15fb1f
XY		 768 if (!sas_protocol_ata(task->task_proto)) {
769 if (task->num_scatter) {
770 n_elem = dma_map_sg(mvi->dev,
771 task->scatter,
772 task->num_scatter,
773 task->data_dir);
774 if (!n_elem) {
775 rc = -ENOMEM;
776 goto prep_out;
777 }
778 }
779 } else {
780 n_elem = task->num_scatter;
781 }
20b09c29 782
0b15fb1f
XY		 783 rc = mvs_tag_alloc(mvi, &tag);
784 if (rc)
785 goto err_out;
20b09c29 786
0b15fb1f 787 slot = &mvi->slot_info[tag];
20b09c29 788
0b15fb1f
XY		 789 task->lldd_task = NULL;
790 slot->n_elem = n_elem;
791 slot->slot_tag = tag;
792
793 slot->buf = pci_pool_alloc(mvi->dma_pool, GFP_ATOMIC, &slot->buf_dma);
794 if (!slot->buf)
795 goto err_out_tag;
796 memset(slot->buf, 0, MVS_SLOT_BUF_SZ);
797
798 tei.task = task;
799 tei.hdr = &mvi->slot[tag];
800 tei.tag = tag;
801 tei.n_elem = n_elem;
802 switch (task->task_proto) {
803 case SAS_PROTOCOL_SMP:
804 rc = mvs_task_prep_smp(mvi, &tei);
805 break;
806 case SAS_PROTOCOL_SSP:
807 rc = mvs_task_prep_ssp(mvi, &tei, is_tmf, tmf);
808 break;
809 case SAS_PROTOCOL_SATA:
810 case SAS_PROTOCOL_STP:
811 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
812 rc = mvs_task_prep_ata(mvi, &tei);
813 break;
814 default:
815 dev_printk(KERN_ERR, mvi->dev,
816 "unknown sas_task proto: 0x%x\n",
817 task->task_proto);
818 rc = -EINVAL;
819 break;
820 }
dd4969a8 821
0b15fb1f
XY		 822 if (rc) {
823 mv_dprintk("rc is %x\n", rc);
824 goto err_out_slot_buf;
825 }
826 slot->task = task;
827 slot->port = tei.port;
828 task->lldd_task = slot;
829 list_add_tail(&slot->entry, &tei.port->list);
830 spin_lock(&task->task_state_lock);
831 task->task_state_flags |= SAS_TASK_AT_INITIATOR;
832 spin_unlock(&task->task_state_lock);
833
0b15fb1f
XY		 834 mvi_dev->running_req++;
835 ++(*pass);
836 mvi->tx_prod = (mvi->tx_prod + 1) & (MVS_CHIP_SLOT_SZ - 1);
9dc9fd94 837
0b15fb1f 838 return rc;
dd4969a8 839
0b15fb1f
XY		 840err_out_slot_buf:
841 pci_pool_free(mvi->dma_pool, slot->buf, slot->buf_dma);
dd4969a8
JG		 842err_out_tag:
843 mvs_tag_free(mvi, tag);
844err_out:
20b09c29 845
0b15fb1f
XY		 846 dev_printk(KERN_ERR, mvi->dev, "mvsas prep failed[%d]!\n", rc);
847 if (!sas_protocol_ata(task->task_proto))
dd4969a8 848 if (n_elem)
0b15fb1f
XY		 849 dma_unmap_sg(mvi->dev, task->scatter, n_elem,
850 task->data_dir);
851prep_out:
852 return rc;
853}
854
79855d17 855static int mvs_task_exec(struct sas_task *task, gfp_t gfp_flags,
0b15fb1f
XY		 856 struct completion *completion, int is_tmf,
857 struct mvs_tmf_task *tmf)
858{
0b15fb1f
XY		 859 struct mvs_info *mvi = NULL;
860 u32 rc = 0;
861 u32 pass = 0;
862 unsigned long flags = 0;
863
864 mvi = ((struct mvs_device *)task->dev->lldd_dev)->mvi_info;
865
0b15fb1f
XY		 866 spin_lock_irqsave(&mvi->lock, flags);
867 rc = mvs_task_prep(task, mvi, is_tmf, tmf, &pass);
868 if (rc)
869 dev_printk(KERN_ERR, mvi->dev, "mvsas exec failed[%d]!\n", rc);
870
871 if (likely(pass))
872 MVS_CHIP_DISP->start_delivery(mvi, (mvi->tx_prod - 1) &
873 (MVS_CHIP_SLOT_SZ - 1));
0b84b709 874 spin_unlock_irqrestore(&mvi->lock, flags);
0b15fb1f 875
0b15fb1f
XY		 876 return rc;
877}
878
79855d17 879int mvs_queue_command(struct sas_task *task, gfp_t gfp_flags)
20b09c29 880{
79855d17 881 return mvs_task_exec(task, gfp_flags, NULL, 0, NULL);
20b09c29
AY		 882}
883
dd4969a8
JG		 884static void mvs_slot_free(struct mvs_info *mvi, u32 rx_desc)
885{
886 u32 slot_idx = rx_desc & RXQ_SLOT_MASK;
887 mvs_tag_clear(mvi, slot_idx);
888}
889
890static void mvs_slot_task_free(struct mvs_info *mvi, struct sas_task *task,
891 struct mvs_slot_info *slot, u32 slot_idx)
892{
20b09c29
AY		 893 if (!slot->task)
894 return;
dd4969a8
JG		 895 if (!sas_protocol_ata(task->task_proto))
896 if (slot->n_elem)
20b09c29 897 dma_unmap_sg(mvi->dev, task->scatter,
dd4969a8
JG		 898 slot->n_elem, task->data_dir);
899
900 switch (task->task_proto) {
901 case SAS_PROTOCOL_SMP:
20b09c29 902 dma_unmap_sg(mvi->dev, &task->smp_task.smp_resp, 1,
dd4969a8 903 PCI_DMA_FROMDEVICE);
20b09c29 904 dma_unmap_sg(mvi->dev, &task->smp_task.smp_req, 1,
dd4969a8
JG		 905 PCI_DMA_TODEVICE);
906 break;
907
908 case SAS_PROTOCOL_SATA:
909 case SAS_PROTOCOL_STP:
910 case SAS_PROTOCOL_SSP:
911 default:
912 /* do nothing */
913 break;
914 }
0b15fb1f
XY		 915
916 if (slot->buf) {
917 pci_pool_free(mvi->dma_pool, slot->buf, slot->buf_dma);
918 slot->buf = NULL;
919 }
20b09c29 920 list_del_init(&slot->entry);
dd4969a8
JG		 921 task->lldd_task = NULL;
922 slot->task = NULL;
923 slot->port = NULL;
20b09c29
AY		 924 slot->slot_tag = 0xFFFFFFFF;
925 mvs_slot_free(mvi, slot_idx);
dd4969a8
JG		 926}
927
84fbd0ce 928static void mvs_update_wideport(struct mvs_info *mvi, int phy_no)
dd4969a8 929{
84fbd0ce 930 struct mvs_phy *phy = &mvi->phy[phy_no];
dd4969a8
JG		 931 struct mvs_port *port = phy->port;
932 int j, no;
933
20b09c29
AY		 934 for_each_phy(port->wide_port_phymap, j, no) {
935 if (j & 1) {
936 MVS_CHIP_DISP->write_port_cfg_addr(mvi, no,
937 PHYR_WIDE_PORT);
938 MVS_CHIP_DISP->write_port_cfg_data(mvi, no,
dd4969a8
JG		 939 port->wide_port_phymap);
940 } else {
20b09c29
AY		 941 MVS_CHIP_DISP->write_port_cfg_addr(mvi, no,
942 PHYR_WIDE_PORT);
943 MVS_CHIP_DISP->write_port_cfg_data(mvi, no,
944 0);
dd4969a8 945 }
20b09c29 946 }
dd4969a8
JG		 947}
948
949static u32 mvs_is_phy_ready(struct mvs_info *mvi, int i)
950{
951 u32 tmp;
952 struct mvs_phy *phy = &mvi->phy[i];
20b09c29 953 struct mvs_port *port = phy->port;
dd4969a8 954
20b09c29 955 tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, i);
dd4969a8
JG		 956 if ((tmp & PHY_READY_MASK) && !(phy->irq_status & PHYEV_POOF)) {
957 if (!port)
958 phy->phy_attached = 1;
959 return tmp;
960 }
961
962 if (port) {
963 if (phy->phy_type & PORT_TYPE_SAS) {
964 port->wide_port_phymap &= ~(1U << i);
965 if (!port->wide_port_phymap)
966 port->port_attached = 0;
967 mvs_update_wideport(mvi, i);
968 } else if (phy->phy_type & PORT_TYPE_SATA)
969 port->port_attached = 0;
dd4969a8
JG		 970 phy->port = NULL;
971 phy->phy_attached = 0;
972 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
973 }
974 return 0;
975}
976
977static void *mvs_get_d2h_reg(struct mvs_info *mvi, int i, void *buf)
978{
979 u32 *s = (u32 *) buf;
980
981 if (!s)
982 return NULL;
983
20b09c29 984 MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG3);
84fbd0ce 985 s[3] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i));
dd4969a8 986
20b09c29 987 MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG2);
84fbd0ce 988 s[2] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i));
dd4969a8 989
20b09c29 990 MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG1);
84fbd0ce 991 s[1] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i));
dd4969a8 992
20b09c29 993 MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG0);
84fbd0ce 994 s[0] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i));
20b09c29 995
20b09c29
AY		 996 if (((s[1] & 0x00FFFFFF) == 0x00EB1401) && (*(u8 *)&s[3] == 0x01))
997 s[1] = 0x00EB1401 | (*((u8 *)&s[1] + 3) & 0x10);
dd4969a8 998
f9da3be5 999 return s;
dd4969a8
JG		 1000}
1001
1002static u32 mvs_is_sig_fis_received(u32 irq_status)
1003{
1004 return irq_status & PHYEV_SIG_FIS;
1005}
1006
8882f081
XY		 1007static void mvs_sig_remove_timer(struct mvs_phy *phy)
1008{
1009 if (phy->timer.function)
1010 del_timer(&phy->timer);
1011 phy->timer.function = NULL;
1012}
1013
20b09c29 1014void mvs_update_phyinfo(struct mvs_info *mvi, int i, int get_st)
dd4969a8
JG		 1015{
1016 struct mvs_phy *phy = &mvi->phy[i];
20b09c29 1017 struct sas_identify_frame *id;
b5762948 1018
20b09c29 1019 id = (struct sas_identify_frame *)phy->frame_rcvd;
b5762948 1020
dd4969a8 1021 if (get_st) {
20b09c29 1022 phy->irq_status = MVS_CHIP_DISP->read_port_irq_stat(mvi, i);
dd4969a8
JG		 1023 phy->phy_status = mvs_is_phy_ready(mvi, i);
1024 }
8f261aaf 1025
dd4969a8 1026 if (phy->phy_status) {
20b09c29
AY		 1027 int oob_done = 0;
1028 struct asd_sas_phy *sas_phy = &mvi->phy[i].sas_phy;
b5762948 1029
20b09c29
AY		 1030 oob_done = MVS_CHIP_DISP->oob_done(mvi, i);
1031
1032 MVS_CHIP_DISP->fix_phy_info(mvi, i, id);
1033 if (phy->phy_type & PORT_TYPE_SATA) {
1034 phy->identify.target_port_protocols = SAS_PROTOCOL_STP;
1035 if (mvs_is_sig_fis_received(phy->irq_status)) {
8882f081 1036 mvs_sig_remove_timer(phy);
20b09c29
AY		 1037 phy->phy_attached = 1;
1038 phy->att_dev_sas_addr =
1039 i + mvi->id * mvi->chip->n_phy;
1040 if (oob_done)
1041 sas_phy->oob_mode = SATA_OOB_MODE;
1042 phy->frame_rcvd_size =
1043 sizeof(struct dev_to_host_fis);
f9da3be5 1044 mvs_get_d2h_reg(mvi, i, id);
20b09c29
AY		 1045 } else {
1046 u32 tmp;
1047 dev_printk(KERN_DEBUG, mvi->dev,
1048 "Phy%d : No sig fis\n", i);
1049 tmp = MVS_CHIP_DISP->read_port_irq_mask(mvi, i);
1050 MVS_CHIP_DISP->write_port_irq_mask(mvi, i,
1051 tmp | PHYEV_SIG_FIS);
1052 phy->phy_attached = 0;
1053 phy->phy_type &= ~PORT_TYPE_SATA;
20b09c29
AY		 1054 goto out_done;
1055 }
9dc9fd94 1056 } else if (phy->phy_type & PORT_TYPE_SAS
20b09c29
AY		 1057 || phy->att_dev_info & PORT_SSP_INIT_MASK) {
1058 phy->phy_attached = 1;
dd4969a8 1059 phy->identify.device_type =
20b09c29 1060 phy->att_dev_info & PORT_DEV_TYPE_MASK;
b5762948 1061
aa9f8328 1062 if (phy->identify.device_type == SAS_END_DEVICE)
dd4969a8
JG		 1063 phy->identify.target_port_protocols =
1064 SAS_PROTOCOL_SSP;
aa9f8328 1065 else if (phy->identify.device_type != SAS_PHY_UNUSED)
dd4969a8
JG		 1066 phy->identify.target_port_protocols =
1067 SAS_PROTOCOL_SMP;
20b09c29 1068 if (oob_done)
dd4969a8
JG		 1069 sas_phy->oob_mode = SAS_OOB_MODE;
1070 phy->frame_rcvd_size =
1071 sizeof(struct sas_identify_frame);
dd4969a8 1072 }
20b09c29
AY		 1073 memcpy(sas_phy->attached_sas_addr,
1074 &phy->att_dev_sas_addr, SAS_ADDR_SIZE);
b5762948 1075
20b09c29
AY		 1076 if (MVS_CHIP_DISP->phy_work_around)
1077 MVS_CHIP_DISP->phy_work_around(mvi, i);
dd4969a8 1078 }
84fbd0ce 1079 mv_dprintk("phy %d attach dev info is %x\n",
20b09c29 1080 i + mvi->id * mvi->chip->n_phy, phy->att_dev_info);
84fbd0ce 1081 mv_dprintk("phy %d attach sas addr is %llx\n",
20b09c29 1082 i + mvi->id * mvi->chip->n_phy, phy->att_dev_sas_addr);
4e52fc0a 1083out_done:
dd4969a8 1084 if (get_st)
20b09c29 1085 MVS_CHIP_DISP->write_port_irq_stat(mvi, i, phy->irq_status);
b5762948
JG		 1086}
1087
20b09c29 1088static void mvs_port_notify_formed(struct asd_sas_phy *sas_phy, int lock)
8f261aaf 1089{
dd4969a8 1090 struct sas_ha_struct *sas_ha = sas_phy->ha;
20b09c29 1091 struct mvs_info *mvi = NULL; int i = 0, hi;
dd4969a8 1092 struct mvs_phy *phy = sas_phy->lldd_phy;
20b09c29
AY		 1093 struct asd_sas_port *sas_port = sas_phy->port;
1094 struct mvs_port *port;
1095 unsigned long flags = 0;
1096 if (!sas_port)
1097 return;
8f261aaf 1098
20b09c29
AY		 1099 while (sas_ha->sas_phy[i]) {
1100 if (sas_ha->sas_phy[i] == sas_phy)
1101 break;
1102 i++;
1103 }
1104 hi = i/((struct mvs_prv_info *)sas_ha->lldd_ha)->n_phy;
1105 mvi = ((struct mvs_prv_info *)sas_ha->lldd_ha)->mvi[hi];
84fbd0ce
XY		 1106 if (i >= mvi->chip->n_phy)
1107 port = &mvi->port[i - mvi->chip->n_phy];
20b09c29 1108 else
84fbd0ce 1109 port = &mvi->port[i];
20b09c29
AY		 1110 if (lock)
1111 spin_lock_irqsave(&mvi->lock, flags);
dd4969a8
JG		 1112 port->port_attached = 1;
1113 phy->port = port;
0b15fb1f 1114 sas_port->lldd_port = port;
dd4969a8
JG		 1115 if (phy->phy_type & PORT_TYPE_SAS) {
1116 port->wide_port_phymap = sas_port->phy_mask;
20b09c29 1117 mv_printk("set wide port phy map %x\n", sas_port->phy_mask);
dd4969a8 1118 mvs_update_wideport(mvi, sas_phy->id);
477f6d19
XY		 1119
1120 /* direct attached SAS device */
1121 if (phy->att_dev_info & PORT_SSP_TRGT_MASK) {
1122 MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_PHY_STAT);
1123 MVS_CHIP_DISP->write_port_cfg_data(mvi, i, 0x04);
1124 }
8f261aaf 1125 }
20b09c29
AY		 1126 if (lock)
1127 spin_unlock_irqrestore(&mvi->lock, flags);
dd4969a8
JG		 1128}
1129
20b09c29 1130static void mvs_port_notify_deformed(struct asd_sas_phy *sas_phy, int lock)
dd4969a8 1131{
9dc9fd94
S		 1132 struct domain_device *dev;
1133 struct mvs_phy *phy = sas_phy->lldd_phy;
1134 struct mvs_info *mvi = phy->mvi;
1135 struct asd_sas_port *port = sas_phy->port;
1136 int phy_no = 0;
1137
1138 while (phy != &mvi->phy[phy_no]) {
1139 phy_no++;
1140 if (phy_no >= MVS_MAX_PHYS)
1141 return;
1142 }
1143 list_for_each_entry(dev, &port->dev_list, dev_list_node)
84fbd0ce 1144 mvs_do_release_task(phy->mvi, phy_no, dev);
9dc9fd94 1145
dd4969a8
JG		 1146}
1147
dd4969a8 1148
20b09c29
AY		 1149void mvs_port_formed(struct asd_sas_phy *sas_phy)
1150{
1151 mvs_port_notify_formed(sas_phy, 1);
dd4969a8
JG		 1152}
1153
20b09c29 1154void mvs_port_deformed(struct asd_sas_phy *sas_phy)
dd4969a8 1155{
20b09c29
AY		 1156 mvs_port_notify_deformed(sas_phy, 1);
1157}
8f261aaf 1158
20b09c29
AY		 1159struct mvs_device *mvs_alloc_dev(struct mvs_info *mvi)
1160{
1161 u32 dev;
1162 for (dev = 0; dev < MVS_MAX_DEVICES; dev++) {
aa9f8328 1163 if (mvi->devices[dev].dev_type == SAS_PHY_UNUSED) {
20b09c29
AY		 1164 mvi->devices[dev].device_id = dev;
1165 return &mvi->devices[dev];
1166 }
8f261aaf 1167 }
8121ed42 1168
20b09c29
AY		 1169 if (dev == MVS_MAX_DEVICES)
1170 mv_printk("max support %d devices, ignore ..\n",
1171 MVS_MAX_DEVICES);
1172
1173 return NULL;
8f261aaf
KW		 1174}
1175
20b09c29 1176void mvs_free_dev(struct mvs_device *mvi_dev)
b5762948 1177{
20b09c29
AY		 1178 u32 id = mvi_dev->device_id;
1179 memset(mvi_dev, 0, sizeof(*mvi_dev));
1180 mvi_dev->device_id = id;
aa9f8328 1181 mvi_dev->dev_type = SAS_PHY_UNUSED;
20b09c29
AY		 1182 mvi_dev->dev_status = MVS_DEV_NORMAL;
1183 mvi_dev->taskfileset = MVS_ID_NOT_MAPPED;
1184}
b5762948 1185
20b09c29
AY		 1186int mvs_dev_found_notify(struct domain_device *dev, int lock)
1187{
1188 unsigned long flags = 0;
1189 int res = 0;
1190 struct mvs_info *mvi = NULL;
1191 struct domain_device *parent_dev = dev->parent;
1192 struct mvs_device *mvi_device;
b5762948 1193
20b09c29 1194 mvi = mvs_find_dev_mvi(dev);
b5762948 1195
20b09c29
AY		 1196 if (lock)
1197 spin_lock_irqsave(&mvi->lock, flags);
1198
1199 mvi_device = mvs_alloc_dev(mvi);
1200 if (!mvi_device) {
1201 res = -1;
1202 goto found_out;
b5762948 1203 }
f9da3be5 1204 dev->lldd_dev = mvi_device;
9dc9fd94 1205 mvi_device->dev_status = MVS_DEV_NORMAL;
20b09c29 1206 mvi_device->dev_type = dev->dev_type;
9870d9a2 1207 mvi_device->mvi_info = mvi;
84fbd0ce 1208 mvi_device->sas_device = dev;
20b09c29
AY		 1209 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) {
1210 int phy_id;
1211 u8 phy_num = parent_dev->ex_dev.num_phys;
1212 struct ex_phy *phy;
1213 for (phy_id = 0; phy_id < phy_num; phy_id++) {
1214 phy = &parent_dev->ex_dev.ex_phy[phy_id];
1215 if (SAS_ADDR(phy->attached_sas_addr) ==
1216 SAS_ADDR(dev->sas_addr)) {
1217 mvi_device->attached_phy = phy_id;
1218 break;
1219 }
1220 }
b5762948 1221
20b09c29
AY		 1222 if (phy_id == phy_num) {
1223 mv_printk("Error: no attached dev:%016llx"
1224 "at ex:%016llx.\n",
1225 SAS_ADDR(dev->sas_addr),
1226 SAS_ADDR(parent_dev->sas_addr));
1227 res = -1;
1228 }
dd4969a8 1229 }
b5762948 1230
20b09c29
AY		 1231found_out:
1232 if (lock)
1233 spin_unlock_irqrestore(&mvi->lock, flags);
1234 return res;
1235}
b5762948 1236
20b09c29
AY		 1237int mvs_dev_found(struct domain_device *dev)
1238{
1239 return mvs_dev_found_notify(dev, 1);
1240}
b5762948 1241
9dc9fd94 1242void mvs_dev_gone_notify(struct domain_device *dev)
20b09c29
AY		 1243{
1244 unsigned long flags = 0;
f9da3be5 1245 struct mvs_device *mvi_dev = dev->lldd_dev;
eaa015d2 1246 struct mvs_info *mvi;
b5762948 1247
eaa015d2 1248 if (!mvi_dev) {
20b09c29 1249 mv_dprintk("found dev has gone.\n");
eaa015d2 1250 return;
b5762948 1251 }
eaa015d2
RS		 1252
1253 mvi = mvi_dev->mvi_info;
1254
1255 spin_lock_irqsave(&mvi->lock, flags);
1256
1257 mv_dprintk("found dev[%d:%x] is gone.\n",
1258 mvi_dev->device_id, mvi_dev->dev_type);
1259 mvs_release_task(mvi, dev);
1260 mvs_free_reg_set(mvi, mvi_dev);
1261 mvs_free_dev(mvi_dev);
1262
20b09c29 1263 dev->lldd_dev = NULL;
84fbd0ce 1264 mvi_dev->sas_device = NULL;
b5762948 1265
9dc9fd94 1266 spin_unlock_irqrestore(&mvi->lock, flags);
b5762948
JG		 1267}
1268
b5762948 1269
20b09c29
AY		 1270void mvs_dev_gone(struct domain_device *dev)
1271{
9dc9fd94 1272 mvs_dev_gone_notify(dev);
20b09c29 1273}
b5762948 1274
20b09c29
AY		 1275static void mvs_task_done(struct sas_task *task)
1276{
f0bf750c 1277 if (!del_timer(&task->slow_task->timer))
20b09c29 1278 return;
f0bf750c 1279 complete(&task->slow_task->completion);
b5762948 1280}
b5762948 1281
20b09c29 1282static void mvs_tmf_timedout(unsigned long data)
b5762948 1283{
20b09c29 1284 struct sas_task *task = (struct sas_task *)data;
8f261aaf 1285
20b09c29 1286 task->task_state_flags |= SAS_TASK_STATE_ABORTED;
f0bf750c 1287 complete(&task->slow_task->completion);
20b09c29 1288}
8f261aaf 1289
20b09c29
AY		 1290#define MVS_TASK_TIMEOUT 20
1291static int mvs_exec_internal_tmf_task(struct domain_device *dev,
1292 void *parameter, u32 para_len, struct mvs_tmf_task *tmf)
1293{
1294 int res, retry;
1295 struct sas_task *task = NULL;
8f261aaf 1296
20b09c29 1297 for (retry = 0; retry < 3; retry++) {
f0bf750c 1298 task = sas_alloc_slow_task(GFP_KERNEL);
20b09c29
AY		 1299 if (!task)
1300 return -ENOMEM;
8f261aaf 1301
20b09c29
AY		 1302 task->dev = dev;
1303 task->task_proto = dev->tproto;
8f261aaf 1304
20b09c29
AY		 1305 memcpy(&task->ssp_task, parameter, para_len);
1306 task->task_done = mvs_task_done;
8f261aaf 1307
f0bf750c
DW		 1308 task->slow_task->timer.data = (unsigned long) task;
1309 task->slow_task->timer.function = mvs_tmf_timedout;
1310 task->slow_task->timer.expires = jiffies + MVS_TASK_TIMEOUT*HZ;
1311 add_timer(&task->slow_task->timer);
8f261aaf 1312
79855d17 1313 res = mvs_task_exec(task, GFP_KERNEL, NULL, 1, tmf);
8f261aaf 1314
20b09c29 1315 if (res) {
f0bf750c 1316 del_timer(&task->slow_task->timer);
6d3be300 1317 mv_printk("executing internal task failed:%d\n", res);
20b09c29
AY		 1318 goto ex_err;
1319 }
8f261aaf 1320
f0bf750c 1321 wait_for_completion(&task->slow_task->completion);
84fbd0ce 1322 res = TMF_RESP_FUNC_FAILED;
20b09c29
AY		 1323 /* Even TMF timed out, return direct. */
1324 if ((task->task_state_flags & SAS_TASK_STATE_ABORTED)) {
1325 if (!(task->task_state_flags & SAS_TASK_STATE_DONE)) {
1326 mv_printk("TMF task[%x] timeout.\n", tmf->tmf);
1327 goto ex_err;
1328 }
1329 }
8f261aaf 1330
20b09c29 1331 if (task->task_status.resp == SAS_TASK_COMPLETE &&
df64d3ca 1332 task->task_status.stat == SAM_STAT_GOOD) {
20b09c29
AY		 1333 res = TMF_RESP_FUNC_COMPLETE;
1334 break;
1335 }
b5762948 1336
20b09c29
AY		 1337 if (task->task_status.resp == SAS_TASK_COMPLETE &&
1338 task->task_status.stat == SAS_DATA_UNDERRUN) {
1339 /* no error, but return the number of bytes of
1340 * underrun */
1341 res = task->task_status.residual;
1342 break;
1343 }
b5762948 1344
20b09c29
AY		 1345 if (task->task_status.resp == SAS_TASK_COMPLETE &&
1346 task->task_status.stat == SAS_DATA_OVERRUN) {
1347 mv_dprintk("blocked task error.\n");
1348 res = -EMSGSIZE;
1349 break;
1350 } else {
1351 mv_dprintk(" task to dev %016llx response: 0x%x "
1352 "status 0x%x\n",
1353 SAS_ADDR(dev->sas_addr),
1354 task->task_status.resp,
1355 task->task_status.stat);
4fcf812c 1356 sas_free_task(task);
20b09c29 1357 task = NULL;
b5762948 1358
dd4969a8 1359 }
dd4969a8 1360 }
20b09c29
AY		 1361ex_err:
1362 BUG_ON(retry == 3 && task != NULL);
4fcf812c 1363 sas_free_task(task);
20b09c29 1364 return res;
dd4969a8 1365}
b5762948 1366
20b09c29
AY		 1367static int mvs_debug_issue_ssp_tmf(struct domain_device *dev,
1368 u8 *lun, struct mvs_tmf_task *tmf)
dd4969a8 1369{
20b09c29 1370 struct sas_ssp_task ssp_task;
20b09c29
AY		 1371 if (!(dev->tproto & SAS_PROTOCOL_SSP))
1372 return TMF_RESP_FUNC_ESUPP;
b5762948 1373
84fbd0ce 1374 memcpy(ssp_task.LUN, lun, 8);
b5762948 1375
20b09c29
AY		 1376 return mvs_exec_internal_tmf_task(dev, &ssp_task,
1377 sizeof(ssp_task), tmf);
1378}
8f261aaf 1379
8f261aaf 1380
20b09c29
AY		 1381/* Standard mandates link reset for ATA (type 0)
1382 and hard reset for SSP (type 1) , only for RECOVERY */
1383static int mvs_debug_I_T_nexus_reset(struct domain_device *dev)
1384{
1385 int rc;
f41a0c44 1386 struct sas_phy *phy = sas_get_local_phy(dev);
aa9f8328 1387 int reset_type = (dev->dev_type == SAS_SATA_DEV ||
20b09c29
AY		 1388 (dev->tproto & SAS_PROTOCOL_STP)) ? 0 : 1;
1389 rc = sas_phy_reset(phy, reset_type);
f41a0c44 1390 sas_put_local_phy(phy);
20b09c29
AY		 1391 msleep(2000);
1392 return rc;
1393}
8f261aaf 1394
20b09c29
AY		 1395/* mandatory SAM-3 */
1396int mvs_lu_reset(struct domain_device *dev, u8 *lun)
1397{
1398 unsigned long flags;
84fbd0ce 1399 int rc = TMF_RESP_FUNC_FAILED;
20b09c29 1400 struct mvs_tmf_task tmf_task;
f9da3be5 1401 struct mvs_device * mvi_dev = dev->lldd_dev;
9870d9a2 1402 struct mvs_info *mvi = mvi_dev->mvi_info;
20b09c29
AY		 1403
1404 tmf_task.tmf = TMF_LU_RESET;
1405 mvi_dev->dev_status = MVS_DEV_EH;
1406 rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
1407 if (rc == TMF_RESP_FUNC_COMPLETE) {
20b09c29 1408 spin_lock_irqsave(&mvi->lock, flags);
84fbd0ce 1409 mvs_release_task(mvi, dev);
20b09c29 1410 spin_unlock_irqrestore(&mvi->lock, flags);
dd4969a8 1411 }
20b09c29
AY		 1412 /* If failed, fall-through I_T_Nexus reset */
1413 mv_printk("%s for device[%x]:rc= %d\n", __func__,
1414 mvi_dev->device_id, rc);
1415 return rc;
1416}
8f261aaf 1417
20b09c29
AY		 1418int mvs_I_T_nexus_reset(struct domain_device *dev)
1419{
1420 unsigned long flags;
9dc9fd94
S		 1421 int rc = TMF_RESP_FUNC_FAILED;
1422 struct mvs_device * mvi_dev = (struct mvs_device *)dev->lldd_dev;
9870d9a2 1423 struct mvs_info *mvi = mvi_dev->mvi_info;
20b09c29
AY		 1424
1425 if (mvi_dev->dev_status != MVS_DEV_EH)
1426 return TMF_RESP_FUNC_COMPLETE;
84fbd0ce
XY		 1427 else
1428 mvi_dev->dev_status = MVS_DEV_NORMAL;
20b09c29
AY		 1429 rc = mvs_debug_I_T_nexus_reset(dev);
1430 mv_printk("%s for device[%x]:rc= %d\n",
1431 __func__, mvi_dev->device_id, rc);
1432
20b09c29 1433 spin_lock_irqsave(&mvi->lock, flags);
9dc9fd94 1434 mvs_release_task(mvi, dev);
20b09c29
AY		 1435 spin_unlock_irqrestore(&mvi->lock, flags);
1436
1437 return rc;
1438}
1439/* optional SAM-3 */
1440int mvs_query_task(struct sas_task *task)
1441{
1442 u32 tag;
1443 struct scsi_lun lun;
1444 struct mvs_tmf_task tmf_task;
1445 int rc = TMF_RESP_FUNC_FAILED;
1446
1447 if (task->lldd_task && task->task_proto & SAS_PROTOCOL_SSP) {
1448 struct scsi_cmnd * cmnd = (struct scsi_cmnd *)task->uldd_task;
1449 struct domain_device *dev = task->dev;
9870d9a2
AY		 1450 struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
1451 struct mvs_info *mvi = mvi_dev->mvi_info;
20b09c29
AY		 1452
1453 int_to_scsilun(cmnd->device->lun, &lun);
1454 rc = mvs_find_tag(mvi, task, &tag);
1455 if (rc == 0) {
1456 rc = TMF_RESP_FUNC_FAILED;
dd4969a8 1457 return rc;
20b09c29 1458 }
8f261aaf 1459
20b09c29
AY		 1460 tmf_task.tmf = TMF_QUERY_TASK;
1461 tmf_task.tag_of_task_to_be_managed = cpu_to_le16(tag);
8f261aaf 1462
20b09c29
AY		 1463 rc = mvs_debug_issue_ssp_tmf(dev, lun.scsi_lun, &tmf_task);
1464 switch (rc) {
1465 /* The task is still in Lun, release it then */
1466 case TMF_RESP_FUNC_SUCC:
1467 /* The task is not in Lun or failed, reset the phy */
1468 case TMF_RESP_FUNC_FAILED:
1469 case TMF_RESP_FUNC_COMPLETE:
1470 break;
1471 }
dd4969a8 1472 }
20b09c29
AY		 1473 mv_printk("%s:rc= %d\n", __func__, rc);
1474 return rc;
8f261aaf
KW		 1475}
1476
20b09c29
AY		 1477/* mandatory SAM-3, still need free task/slot info */
1478int mvs_abort_task(struct sas_task *task)
8f261aaf 1479{
20b09c29
AY		 1480 struct scsi_lun lun;
1481 struct mvs_tmf_task tmf_task;
1482 struct domain_device *dev = task->dev;
9870d9a2 1483 struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
24ae163e 1484 struct mvs_info *mvi;
20b09c29
AY		 1485 int rc = TMF_RESP_FUNC_FAILED;
1486 unsigned long flags;
1487 u32 tag;
9870d9a2 1488
9dc9fd94 1489 if (!mvi_dev) {
84fbd0ce
XY		 1490 mv_printk("Device has removed\n");
1491 return TMF_RESP_FUNC_FAILED;
9dc9fd94
S		 1492 }
1493
24ae163e
JS		 1494 mvi = mvi_dev->mvi_info;
1495
20b09c29
AY		 1496 spin_lock_irqsave(&task->task_state_lock, flags);
1497 if (task->task_state_flags & SAS_TASK_STATE_DONE) {
1498 spin_unlock_irqrestore(&task->task_state_lock, flags);
1499 rc = TMF_RESP_FUNC_COMPLETE;
1500 goto out;
dd4969a8 1501 }
20b09c29 1502 spin_unlock_irqrestore(&task->task_state_lock, flags);
9dc9fd94 1503 mvi_dev->dev_status = MVS_DEV_EH;
20b09c29
AY		 1504 if (task->lldd_task && task->task_proto & SAS_PROTOCOL_SSP) {
1505 struct scsi_cmnd * cmnd = (struct scsi_cmnd *)task->uldd_task;
1506
1507 int_to_scsilun(cmnd->device->lun, &lun);
1508 rc = mvs_find_tag(mvi, task, &tag);
1509 if (rc == 0) {
1510 mv_printk("No such tag in %s\n", __func__);
1511 rc = TMF_RESP_FUNC_FAILED;
1512 return rc;
1513 }
8f261aaf 1514
20b09c29
AY		 1515 tmf_task.tmf = TMF_ABORT_TASK;
1516 tmf_task.tag_of_task_to_be_managed = cpu_to_le16(tag);
8f261aaf 1517
20b09c29 1518 rc = mvs_debug_issue_ssp_tmf(dev, lun.scsi_lun, &tmf_task);
8f261aaf 1519
20b09c29
AY		 1520 /* if successful, clear the task and callback forwards.*/
1521 if (rc == TMF_RESP_FUNC_COMPLETE) {
1522 u32 slot_no;
1523 struct mvs_slot_info *slot;
8f261aaf 1524
20b09c29 1525 if (task->lldd_task) {
f9da3be5 1526 slot = task->lldd_task;
20b09c29 1527 slot_no = (u32) (slot - mvi->slot_info);
9dc9fd94 1528 spin_lock_irqsave(&mvi->lock, flags);
20b09c29 1529 mvs_slot_complete(mvi, slot_no, 1);
9dc9fd94 1530 spin_unlock_irqrestore(&mvi->lock, flags);
20b09c29
AY		 1531 }
1532 }
9dc9fd94 1533
20b09c29
AY		 1534 } else if (task->task_proto & SAS_PROTOCOL_SATA ||
1535 task->task_proto & SAS_PROTOCOL_STP) {
aa9f8328 1536 if (SAS_SATA_DEV == dev->dev_type) {
9dc9fd94 1537 struct mvs_slot_info *slot = task->lldd_task;
9dc9fd94 1538 u32 slot_idx = (u32)(slot - mvi->slot_info);
84fbd0ce 1539 mv_dprintk("mvs_abort_task() mvi=%p task=%p "
9dc9fd94
S		 1540 "slot=%p slot_idx=x%x\n",
1541 mvi, task, slot, slot_idx);
95ab0003 1542 task->task_state_flags |= SAS_TASK_STATE_ABORTED;
9dc9fd94 1543 mvs_slot_task_free(mvi, task, slot, slot_idx);
84fbd0ce
XY		 1544 rc = TMF_RESP_FUNC_COMPLETE;
1545 goto out;
9dc9fd94 1546 }
8f261aaf 1547
20b09c29
AY		 1548 }
1549out:
1550 if (rc != TMF_RESP_FUNC_COMPLETE)
1551 mv_printk("%s:rc= %d\n", __func__, rc);
dd4969a8 1552 return rc;
8f261aaf
KW		 1553}
1554
20b09c29 1555int mvs_abort_task_set(struct domain_device *dev, u8 *lun)
8f261aaf 1556{
20b09c29
AY		 1557 int rc = TMF_RESP_FUNC_FAILED;
1558 struct mvs_tmf_task tmf_task;
8f261aaf 1559
20b09c29
AY		 1560 tmf_task.tmf = TMF_ABORT_TASK_SET;
1561 rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
dd4969a8 1562
20b09c29 1563 return rc;
8f261aaf
KW		 1564}
1565
20b09c29 1566int mvs_clear_aca(struct domain_device *dev, u8 *lun)
8f261aaf 1567{
20b09c29
AY		 1568 int rc = TMF_RESP_FUNC_FAILED;
1569 struct mvs_tmf_task tmf_task;
8f261aaf 1570
20b09c29
AY		 1571 tmf_task.tmf = TMF_CLEAR_ACA;
1572 rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
8f261aaf 1573
20b09c29
AY		 1574 return rc;
1575}
8f261aaf 1576
20b09c29
AY		 1577int mvs_clear_task_set(struct domain_device *dev, u8 *lun)
1578{
1579 int rc = TMF_RESP_FUNC_FAILED;
1580 struct mvs_tmf_task tmf_task;
8f261aaf 1581
20b09c29
AY		 1582 tmf_task.tmf = TMF_CLEAR_TASK_SET;
1583 rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
8f261aaf 1584
20b09c29 1585 return rc;
dd4969a8 1586}
8f261aaf 1587
20b09c29
AY		 1588static int mvs_sata_done(struct mvs_info *mvi, struct sas_task *task,
1589 u32 slot_idx, int err)
dd4969a8 1590{
f9da3be5 1591 struct mvs_device *mvi_dev = task->dev->lldd_dev;
20b09c29
AY		 1592 struct task_status_struct *tstat = &task->task_status;
1593 struct ata_task_resp *resp = (struct ata_task_resp *)tstat->buf;
df64d3ca 1594 int stat = SAM_STAT_GOOD;
e9ff91b6 1595
8f261aaf 1596
20b09c29
AY		 1597 resp->frame_len = sizeof(struct dev_to_host_fis);
1598 memcpy(&resp->ending_fis[0],
1599 SATA_RECEIVED_D2H_FIS(mvi_dev->taskfileset),
1600 sizeof(struct dev_to_host_fis));
1601 tstat->buf_valid_size = sizeof(*resp);
9dc9fd94
S		 1602 if (unlikely(err)) {
1603 if (unlikely(err & CMD_ISS_STPD))
1604 stat = SAS_OPEN_REJECT;
1605 else
1606 stat = SAS_PROTO_RESPONSE;
1607 }
1608
20b09c29 1609 return stat;
8f261aaf
KW		 1610}
1611
a4632aae
XY		 1612void mvs_set_sense(u8 *buffer, int len, int d_sense,
1613 int key, int asc, int ascq)
1614{
1615 memset(buffer, 0, len);
1616
1617 if (d_sense) {
1618 /* Descriptor format */
1619 if (len < 4) {
1620 mv_printk("Length %d of sense buffer too small to "
1621 "fit sense %x:%x:%x", len, key, asc, ascq);
1622 }
1623
1624 buffer[0] = 0x72; /* Response Code */
1625 if (len > 1)
1626 buffer[1] = key; /* Sense Key */
1627 if (len > 2)
1628 buffer[2] = asc; /* ASC */
1629 if (len > 3)
1630 buffer[3] = ascq; /* ASCQ */
1631 } else {
1632 if (len < 14) {
1633 mv_printk("Length %d of sense buffer too small to "
1634 "fit sense %x:%x:%x", len, key, asc, ascq);
1635 }
1636
1637 buffer[0] = 0x70; /* Response Code */
1638 if (len > 2)
1639 buffer[2] = key; /* Sense Key */
1640 if (len > 7)
1641 buffer[7] = 0x0a; /* Additional Sense Length */
1642 if (len > 12)
1643 buffer[12] = asc; /* ASC */
1644 if (len > 13)
1645 buffer[13] = ascq; /* ASCQ */
1646 }
1647
1648 return;
1649}
1650
1651void mvs_fill_ssp_resp_iu(struct ssp_response_iu *iu,
1652 u8 key, u8 asc, u8 asc_q)
1653{
1654 iu->datapres = 2;
1655 iu->response_data_len = 0;
1656 iu->sense_data_len = 17;
1657 iu->status = 02;
1658 mvs_set_sense(iu->sense_data, 17, 0,
1659 key, asc, asc_q);
1660}
1661
20b09c29
AY		 1662static int mvs_slot_err(struct mvs_info *mvi, struct sas_task *task,
1663 u32 slot_idx)
8f261aaf 1664{
20b09c29
AY		 1665 struct mvs_slot_info *slot = &mvi->slot_info[slot_idx];
1666 int stat;
84fbd0ce 1667 u32 err_dw0 = le32_to_cpu(*(u32 *)slot->response);
a4632aae 1668 u32 err_dw1 = le32_to_cpu(*((u32 *)slot->response + 1));
20b09c29
AY		 1669 u32 tfs = 0;
1670 enum mvs_port_type type = PORT_TYPE_SAS;
8f261aaf 1671
20b09c29
AY		 1672 if (err_dw0 & CMD_ISS_STPD)
1673 MVS_CHIP_DISP->issue_stop(mvi, type, tfs);
1674
1675 MVS_CHIP_DISP->command_active(mvi, slot_idx);
b5762948 1676
df64d3ca 1677 stat = SAM_STAT_CHECK_CONDITION;
dd4969a8 1678 switch (task->task_proto) {
dd4969a8 1679 case SAS_PROTOCOL_SSP:
a4632aae 1680 {
20b09c29 1681 stat = SAS_ABORTED_TASK;
a4632aae
XY		 1682 if ((err_dw0 & NO_DEST) || err_dw1 & bit(31)) {
1683 struct ssp_response_iu *iu = slot->response +
1684 sizeof(struct mvs_err_info);
1685 mvs_fill_ssp_resp_iu(iu, NOT_READY, 0x04, 01);
1686 sas_ssp_task_response(mvi->dev, task, iu);
1687 stat = SAM_STAT_CHECK_CONDITION;
1688 }
1689 if (err_dw1 & bit(31))
1690 mv_printk("reuse same slot, retry command.\n");
20b09c29 1691 break;
a4632aae 1692 }
20b09c29 1693 case SAS_PROTOCOL_SMP:
df64d3ca 1694 stat = SAM_STAT_CHECK_CONDITION;
dd4969a8 1695 break;
20b09c29 1696
dd4969a8
JG		 1697 case SAS_PROTOCOL_SATA:
1698 case SAS_PROTOCOL_STP:
20b09c29
AY		 1699 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1700 {
20b09c29 1701 task->ata_task.use_ncq = 0;
84fbd0ce 1702 stat = SAS_PROTO_RESPONSE;
9dc9fd94 1703 mvs_sata_done(mvi, task, slot_idx, err_dw0);
dd4969a8 1704 }
20b09c29 1705 break;
dd4969a8
JG		 1706 default:
1707 break;
1708 }
1709
20b09c29 1710 return stat;
e9ff91b6
KW		 1711}
1712
20b09c29 1713int mvs_slot_complete(struct mvs_info *mvi, u32 rx_desc, u32 flags)
b5762948 1714{
20b09c29
AY		 1715 u32 slot_idx = rx_desc & RXQ_SLOT_MASK;
1716 struct mvs_slot_info *slot = &mvi->slot_info[slot_idx];
1717 struct sas_task *task = slot->task;
1718 struct mvs_device *mvi_dev = NULL;
1719 struct task_status_struct *tstat;
9dc9fd94
S		 1720 struct domain_device *dev;
1721 u32 aborted;
20b09c29 1722
20b09c29
AY		 1723 void *to;
1724 enum exec_status sts;
1725
9dc9fd94 1726 if (unlikely(!task || !task->lldd_task || !task->dev))
20b09c29
AY		 1727 return -1;
1728
1729 tstat = &task->task_status;
9dc9fd94
S		 1730 dev = task->dev;
1731 mvi_dev = dev->lldd_dev;
b5762948 1732
20b09c29
AY		 1733 spin_lock(&task->task_state_lock);
1734 task->task_state_flags &=
1735 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
1736 task->task_state_flags |= SAS_TASK_STATE_DONE;
1737 /* race condition*/
1738 aborted = task->task_state_flags & SAS_TASK_STATE_ABORTED;
1739 spin_unlock(&task->task_state_lock);
1740
1741 memset(tstat, 0, sizeof(*tstat));
1742 tstat->resp = SAS_TASK_COMPLETE;
1743
1744 if (unlikely(aborted)) {
1745 tstat->stat = SAS_ABORTED_TASK;
9dc9fd94
S		 1746 if (mvi_dev && mvi_dev->running_req)
1747 mvi_dev->running_req--;
20b09c29
AY		 1748 if (sas_protocol_ata(task->task_proto))
1749 mvs_free_reg_set(mvi, mvi_dev);
1750
1751 mvs_slot_task_free(mvi, task, slot, slot_idx);
1752 return -1;
b5762948
JG		 1753 }
1754
e144f7ef 1755 /* when no device attaching, go ahead and complete by error handling*/
9dc9fd94
S		 1756 if (unlikely(!mvi_dev || flags)) {
1757 if (!mvi_dev)
1758 mv_dprintk("port has not device.\n");
20b09c29
AY		 1759 tstat->stat = SAS_PHY_DOWN;
1760 goto out;
1761 }
b5762948 1762
53a983c4
JB		 1763 /*
1764 * error info record present; slot->response is 32 bit aligned but may
1765 * not be 64 bit aligned, so check for zero in two 32 bit reads
1766 */
1767 if (unlikely((rx_desc & RXQ_ERR)
1768 && (*((u32 *)slot->response)
1769 || *(((u32 *)slot->response) + 1)))) {
84fbd0ce
XY		 1770 mv_dprintk("port %d slot %d rx_desc %X has error info"
1771 "%016llX.\n", slot->port->sas_port.id, slot_idx,
53a983c4 1772 rx_desc, get_unaligned_le64(slot->response));
20b09c29 1773 tstat->stat = mvs_slot_err(mvi, task, slot_idx);
9dc9fd94 1774 tstat->resp = SAS_TASK_COMPLETE;
20b09c29 1775 goto out;
b5762948
JG		 1776 }
1777
20b09c29
AY		 1778 switch (task->task_proto) {
1779 case SAS_PROTOCOL_SSP:
1780 /* hw says status == 0, datapres == 0 */
1781 if (rx_desc & RXQ_GOOD) {
df64d3ca 1782 tstat->stat = SAM_STAT_GOOD;
20b09c29
AY		 1783 tstat->resp = SAS_TASK_COMPLETE;
1784 }
1785 /* response frame present */
1786 else if (rx_desc & RXQ_RSP) {
1787 struct ssp_response_iu *iu = slot->response +
1788 sizeof(struct mvs_err_info);
1789 sas_ssp_task_response(mvi->dev, task, iu);
1790 } else
df64d3ca 1791 tstat->stat = SAM_STAT_CHECK_CONDITION;
20b09c29 1792 break;
b5762948 1793
20b09c29
AY		 1794 case SAS_PROTOCOL_SMP: {
1795 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
df64d3ca 1796 tstat->stat = SAM_STAT_GOOD;
77dfce07 1797 to = kmap_atomic(sg_page(sg_resp));
20b09c29
AY		 1798 memcpy(to + sg_resp->offset,
1799 slot->response + sizeof(struct mvs_err_info),
1800 sg_dma_len(sg_resp));
77dfce07 1801 kunmap_atomic(to);
20b09c29
AY		 1802 break;
1803 }
8f261aaf 1804
20b09c29
AY		 1805 case SAS_PROTOCOL_SATA:
1806 case SAS_PROTOCOL_STP:
1807 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: {
1808 tstat->stat = mvs_sata_done(mvi, task, slot_idx, 0);
1809 break;
1810 }
b5762948 1811
20b09c29 1812 default:
df64d3ca 1813 tstat->stat = SAM_STAT_CHECK_CONDITION;
20b09c29
AY		 1814 break;
1815 }
9dc9fd94
S		 1816 if (!slot->port->port_attached) {
1817 mv_dprintk("port %d has removed.\n", slot->port->sas_port.id);
1818 tstat->stat = SAS_PHY_DOWN;
1819 }
1820
b5762948 1821
20b09c29 1822out:
9dc9fd94
S		 1823 if (mvi_dev && mvi_dev->running_req) {
1824 mvi_dev->running_req--;
1825 if (sas_protocol_ata(task->task_proto) && !mvi_dev->running_req)
0f980a87
AY		 1826 mvs_free_reg_set(mvi, mvi_dev);
1827 }
20b09c29
AY		 1828 mvs_slot_task_free(mvi, task, slot, slot_idx);
1829 sts = tstat->stat;
8f261aaf 1830
20b09c29
AY		 1831 spin_unlock(&mvi->lock);
1832 if (task->task_done)
1833 task->task_done(task);
84fbd0ce 1834
20b09c29 1835 spin_lock(&mvi->lock);
b5762948 1836
20b09c29
AY		 1837 return sts;
1838}
b5762948 1839
9dc9fd94 1840void mvs_do_release_task(struct mvs_info *mvi,
20b09c29
AY		 1841 int phy_no, struct domain_device *dev)
1842{
9dc9fd94 1843 u32 slot_idx;
20b09c29
AY		 1844 struct mvs_phy *phy;
1845 struct mvs_port *port;
1846 struct mvs_slot_info *slot, *slot2;
b5762948 1847
20b09c29
AY		 1848 phy = &mvi->phy[phy_no];
1849 port = phy->port;
1850 if (!port)
1851 return;
9dc9fd94
S		 1852 /* clean cmpl queue in case request is already finished */
1853 mvs_int_rx(mvi, false);
1854
1855
b5762948 1856
20b09c29
AY		 1857 list_for_each_entry_safe(slot, slot2, &port->list, entry) {
1858 struct sas_task *task;
1859 slot_idx = (u32) (slot - mvi->slot_info);
1860 task = slot->task;
b5762948 1861
20b09c29
AY		 1862 if (dev && task->dev != dev)
1863 continue;
8f261aaf 1864
20b09c29
AY		 1865 mv_printk("Release slot [%x] tag[%x], task [%p]:\n",
1866 slot_idx, slot->slot_tag, task);
9dc9fd94 1867 MVS_CHIP_DISP->command_active(mvi, slot_idx);
b5762948 1868
20b09c29 1869 mvs_slot_complete(mvi, slot_idx, 1);
b5762948 1870 }
20b09c29 1871}
b5762948 1872
9dc9fd94
S		 1873void mvs_release_task(struct mvs_info *mvi,
1874 struct domain_device *dev)
1875{
1876 int i, phyno[WIDE_PORT_MAX_PHY], num;
9dc9fd94
S		 1877 num = mvs_find_dev_phyno(dev, phyno);
1878 for (i = 0; i < num; i++)
1879 mvs_do_release_task(mvi, phyno[i], dev);
1880}
1881
20b09c29
AY		 1882static void mvs_phy_disconnected(struct mvs_phy *phy)
1883{
1884 phy->phy_attached = 0;
1885 phy->att_dev_info = 0;
1886 phy->att_dev_sas_addr = 0;
1887}
1888
1889static void mvs_work_queue(struct work_struct *work)
1890{
1891 struct delayed_work *dw = container_of(work, struct delayed_work, work);
1892 struct mvs_wq *mwq = container_of(dw, struct mvs_wq, work_q);
1893 struct mvs_info *mvi = mwq->mvi;
1894 unsigned long flags;
a4632aae
XY		 1895 u32 phy_no = (unsigned long) mwq->data;
1896 struct sas_ha_struct *sas_ha = mvi->sas;
1897 struct mvs_phy *phy = &mvi->phy[phy_no];
1898 struct asd_sas_phy *sas_phy = &phy->sas_phy;
b5762948 1899
20b09c29
AY		 1900 spin_lock_irqsave(&mvi->lock, flags);
1901 if (mwq->handler & PHY_PLUG_EVENT) {
20b09c29
AY		 1902
1903 if (phy->phy_event & PHY_PLUG_OUT) {
1904 u32 tmp;
1905 struct sas_identify_frame *id;
1906 id = (struct sas_identify_frame *)phy->frame_rcvd;
1907 tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, phy_no);
1908 phy->phy_event &= ~PHY_PLUG_OUT;
1909 if (!(tmp & PHY_READY_MASK)) {
1910 sas_phy_disconnected(sas_phy);
1911 mvs_phy_disconnected(phy);
1912 sas_ha->notify_phy_event(sas_phy,
1913 PHYE_LOSS_OF_SIGNAL);
1914 mv_dprintk("phy%d Removed Device\n", phy_no);
1915 } else {
1916 MVS_CHIP_DISP->detect_porttype(mvi, phy_no);
1917 mvs_update_phyinfo(mvi, phy_no, 1);
1918 mvs_bytes_dmaed(mvi, phy_no);
1919 mvs_port_notify_formed(sas_phy, 0);
1920 mv_dprintk("phy%d Attached Device\n", phy_no);
1921 }
1922 }
a4632aae
XY		 1923 } else if (mwq->handler & EXP_BRCT_CHG) {
1924 phy->phy_event &= ~EXP_BRCT_CHG;
1925 sas_ha->notify_port_event(sas_phy,
1926 PORTE_BROADCAST_RCVD);
1927 mv_dprintk("phy%d Got Broadcast Change\n", phy_no);
20b09c29
AY		 1928 }
1929 list_del(&mwq->entry);
1930 spin_unlock_irqrestore(&mvi->lock, flags);
1931 kfree(mwq);
1932}
8f261aaf 1933
20b09c29
AY		 1934static int mvs_handle_event(struct mvs_info *mvi, void *data, int handler)
1935{
1936 struct mvs_wq *mwq;
1937 int ret = 0;
1938
1939 mwq = kmalloc(sizeof(struct mvs_wq), GFP_ATOMIC);
1940 if (mwq) {
1941 mwq->mvi = mvi;
1942 mwq->data = data;
1943 mwq->handler = handler;
1944 MV_INIT_DELAYED_WORK(&mwq->work_q, mvs_work_queue, mwq);
1945 list_add_tail(&mwq->entry, &mvi->wq_list);
1946 schedule_delayed_work(&mwq->work_q, HZ * 2);
1947 } else
1948 ret = -ENOMEM;
1949
1950 return ret;
1951}
b5762948 1952
20b09c29
AY		 1953static void mvs_sig_time_out(unsigned long tphy)
1954{
1955 struct mvs_phy *phy = (struct mvs_phy *)tphy;
1956 struct mvs_info *mvi = phy->mvi;
1957 u8 phy_no;
1958
1959 for (phy_no = 0; phy_no < mvi->chip->n_phy; phy_no++) {
1960 if (&mvi->phy[phy_no] == phy) {
1961 mv_dprintk("Get signature time out, reset phy %d\n",
1962 phy_no+mvi->id*mvi->chip->n_phy);
a4632aae 1963 MVS_CHIP_DISP->phy_reset(mvi, phy_no, MVS_HARD_RESET);
20b09c29 1964 }
b5762948 1965 }
20b09c29 1966}
b5762948 1967
20b09c29
AY		 1968void mvs_int_port(struct mvs_info *mvi, int phy_no, u32 events)
1969{
1970 u32 tmp;
20b09c29 1971 struct mvs_phy *phy = &mvi->phy[phy_no];
8f261aaf 1972
20b09c29 1973 phy->irq_status = MVS_CHIP_DISP->read_port_irq_stat(mvi, phy_no);
84fbd0ce
XY		 1974 MVS_CHIP_DISP->write_port_irq_stat(mvi, phy_no, phy->irq_status);
1975 mv_dprintk("phy %d ctrl sts=0x%08X.\n", phy_no+mvi->id*mvi->chip->n_phy,
20b09c29 1976 MVS_CHIP_DISP->read_phy_ctl(mvi, phy_no));
84fbd0ce 1977 mv_dprintk("phy %d irq sts = 0x%08X\n", phy_no+mvi->id*mvi->chip->n_phy,
20b09c29 1978 phy->irq_status);
8f261aaf 1979
20b09c29
AY		 1980 /*
1981 * events is port event now ,
1982 * we need check the interrupt status which belongs to per port.
1983 */
b5762948 1984
9dc9fd94 1985 if (phy->irq_status & PHYEV_DCDR_ERR) {
84fbd0ce 1986 mv_dprintk("phy %d STP decoding error.\n",
9dc9fd94
S		 1987 phy_no + mvi->id*mvi->chip->n_phy);
1988 }
20b09c29
AY		 1989
1990 if (phy->irq_status & PHYEV_POOF) {
84fbd0ce 1991 mdelay(500);
20b09c29
AY		 1992 if (!(phy->phy_event & PHY_PLUG_OUT)) {
1993 int dev_sata = phy->phy_type & PORT_TYPE_SATA;
1994 int ready;
9dc9fd94 1995 mvs_do_release_task(mvi, phy_no, NULL);
20b09c29 1996 phy->phy_event |= PHY_PLUG_OUT;
9dc9fd94 1997 MVS_CHIP_DISP->clear_srs_irq(mvi, 0, 1);
20b09c29
AY		 1998 mvs_handle_event(mvi,
1999 (void *)(unsigned long)phy_no,
2000 PHY_PLUG_EVENT);
2001 ready = mvs_is_phy_ready(mvi, phy_no);
20b09c29
AY		 2002 if (ready || dev_sata) {
2003 if (MVS_CHIP_DISP->stp_reset)
2004 MVS_CHIP_DISP->stp_reset(mvi,
2005 phy_no);
2006 else
2007 MVS_CHIP_DISP->phy_reset(mvi,
a4632aae 2008 phy_no, MVS_SOFT_RESET);
20b09c29
AY		 2009 return;
2010 }
2011 }
2012 }
b5762948 2013
20b09c29
AY		 2014 if (phy->irq_status & PHYEV_COMWAKE) {
2015 tmp = MVS_CHIP_DISP->read_port_irq_mask(mvi, phy_no);
2016 MVS_CHIP_DISP->write_port_irq_mask(mvi, phy_no,
2017 tmp | PHYEV_SIG_FIS);
2018 if (phy->timer.function == NULL) {
2019 phy->timer.data = (unsigned long)phy;
2020 phy->timer.function = mvs_sig_time_out;
84fbd0ce 2021 phy->timer.expires = jiffies + 5*HZ;
20b09c29
AY		 2022 add_timer(&phy->timer);
2023 }
2024 }
2025 if (phy->irq_status & (PHYEV_SIG_FIS | PHYEV_ID_DONE)) {
2026 phy->phy_status = mvs_is_phy_ready(mvi, phy_no);
20b09c29
AY		 2027 mv_dprintk("notify plug in on phy[%d]\n", phy_no);
2028 if (phy->phy_status) {
2029 mdelay(10);
2030 MVS_CHIP_DISP->detect_porttype(mvi, phy_no);
2031 if (phy->phy_type & PORT_TYPE_SATA) {
2032 tmp = MVS_CHIP_DISP->read_port_irq_mask(
2033 mvi, phy_no);
2034 tmp &= ~PHYEV_SIG_FIS;
2035 MVS_CHIP_DISP->write_port_irq_mask(mvi,
2036 phy_no, tmp);
2037 }
2038 mvs_update_phyinfo(mvi, phy_no, 0);
9dc9fd94 2039 if (phy->phy_type & PORT_TYPE_SAS) {
a4632aae 2040 MVS_CHIP_DISP->phy_reset(mvi, phy_no, MVS_PHY_TUNE);
9dc9fd94
S		 2041 mdelay(10);
2042 }
2043
20b09c29
AY		 2044 mvs_bytes_dmaed(mvi, phy_no);
2045 /* whether driver is going to handle hot plug */
2046 if (phy->phy_event & PHY_PLUG_OUT) {
a4632aae 2047 mvs_port_notify_formed(&phy->sas_phy, 0);
20b09c29
AY		 2048 phy->phy_event &= ~PHY_PLUG_OUT;
2049 }
2050 } else {
2051 mv_dprintk("plugin interrupt but phy%d is gone\n",
2052 phy_no + mvi->id*mvi->chip->n_phy);
2053 }
2054 } else if (phy->irq_status & PHYEV_BROAD_CH) {
84fbd0ce 2055 mv_dprintk("phy %d broadcast change.\n",
20b09c29 2056 phy_no + mvi->id*mvi->chip->n_phy);
a4632aae
XY		 2057 mvs_handle_event(mvi, (void *)(unsigned long)phy_no,
2058 EXP_BRCT_CHG);
20b09c29 2059 }
b5762948
JG		 2060}
2061
20b09c29 2062int mvs_int_rx(struct mvs_info *mvi, bool self_clear)
b5762948 2063{
20b09c29
AY		 2064 u32 rx_prod_idx, rx_desc;
2065 bool attn = false;
b5762948 2066
20b09c29
AY		 2067 /* the first dword in the RX ring is special: it contains
2068 * a mirror of the hardware's RX producer index, so that
2069 * we don't have to stall the CPU reading that register.
2070 * The actual RX ring is offset by one dword, due to this.
2071 */
2072 rx_prod_idx = mvi->rx_cons;
2073 mvi->rx_cons = le32_to_cpu(mvi->rx[0]);
2074 if (mvi->rx_cons == 0xfff) /* h/w hasn't touched RX ring yet */
2075 return 0;
b5762948 2076
20b09c29
AY		 2077 /* The CMPL_Q may come late, read from register and try again
2078 * note: if coalescing is enabled,
2079 * it will need to read from register every time for sure
2080 */
2081 if (unlikely(mvi->rx_cons == rx_prod_idx))
2082 mvi->rx_cons = MVS_CHIP_DISP->rx_update(mvi) & RX_RING_SZ_MASK;
2083
2084 if (mvi->rx_cons == rx_prod_idx)
2085 return 0;
2086
2087 while (mvi->rx_cons != rx_prod_idx) {
2088 /* increment our internal RX consumer pointer */
2089 rx_prod_idx = (rx_prod_idx + 1) & (MVS_RX_RING_SZ - 1);
2090 rx_desc = le32_to_cpu(mvi->rx[rx_prod_idx + 1]);
2091
2092 if (likely(rx_desc & RXQ_DONE))
2093 mvs_slot_complete(mvi, rx_desc, 0);
2094 if (rx_desc & RXQ_ATTN) {
2095 attn = true;
2096 } else if (rx_desc & RXQ_ERR) {
2097 if (!(rx_desc & RXQ_DONE))
2098 mvs_slot_complete(mvi, rx_desc, 0);
2099 } else if (rx_desc & RXQ_SLOT_RESET) {
2100 mvs_slot_free(mvi, rx_desc);
2101 }
2102 }
2103
2104 if (attn && self_clear)
2105 MVS_CHIP_DISP->int_full(mvi);
2106 return 0;
b5762948
JG		 2107}
2108
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