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ncr5380: Remove NCR5380_STATS
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1/*
2 * This driver adapted from Drew Eckhardt's Trantor T128 driver
3 *
4 * Copyright 1993, Drew Eckhardt
5 * Visionary Computing
6 * (Unix and Linux consulting and custom programming)
7 * drew@colorado.edu
8 * +1 (303) 666-5836
9 *
10 * ( Based on T128 - DISTRIBUTION RELEASE 3. )
11 *
12 * Modified to work with the Pro Audio Spectrum/Studio 16
13 * by John Weidman.
14 *
15 *
16 * For more information, please consult
17 *
18 * Media Vision
19 * (510) 770-8600
20 * (800) 348-7116
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21 */
22
23
24#ifndef PAS16_H
25#define PAS16_H
26
27#define PAS16_PUBLIC_RELEASE 3
28
29#define PDEBUG_INIT 0x1
30#define PDEBUG_TRANSFER 0x2
31
32#define PAS16_DEFAULT_BASE_1 0x388
33#define PAS16_DEFAULT_BASE_2 0x384
34#define PAS16_DEFAULT_BASE_3 0x38c
35#define PAS16_DEFAULT_BASE_4 0x288
36
37#define PAS16_DEFAULT_BOARD_1_IRQ 10
38#define PAS16_DEFAULT_BOARD_2_IRQ 12
39#define PAS16_DEFAULT_BOARD_3_IRQ 14
40#define PAS16_DEFAULT_BOARD_4_IRQ 15
41
42
43/*
44 * The Pro Audio Spectrum boards are I/O mapped. They use a Zilog 5380
45 * SCSI controller, which is the equivalent of NCR's 5380. "Pseudo-DMA"
46 * architecture is used, where a PAL drives the DMA signals on the 5380
47 * allowing fast, blind transfers with proper handshaking.
48 */
49
50
51/* The Time-out Counter register is used to safe-guard against a stuck
52 * bus (in the case of RDY driven handshake) or a stuck byte (if 16-Bit
53 * DMA conversion is used). The counter uses a 28.224MHz clock
54 * divided by 14 as its clock source. In the case of a stuck byte in
55 * the holding register, an interrupt is generated (and mixed with the
56 * one with the drive) using the CD-ROM interrupt pointer.
57 */
58
59#define P_TIMEOUT_COUNTER_REG 0x4000
60#define P_TC_DISABLE 0x80 /* Set to 0 to enable timeout int. */
61 /* Bits D6-D0 contain timeout count */
62
63
64#define P_TIMEOUT_STATUS_REG_OFFSET 0x4001
65#define P_TS_TIM 0x80 /* check timeout status */
66 /* Bits D6-D4 N/U */
67#define P_TS_ARM_DRQ_INT 0x08 /* Arm DRQ Int. When set high,
68 * the next rising edge will
69 * cause a CD-ROM interrupt.
70 * When set low, the interrupt
71 * will be cleared. There is
72 * no status available for
73 * this interrupt.
74 */
75#define P_TS_ENABLE_TO_ERR_INTERRUPT /* Enable timeout error int. */
76#define P_TS_ENABLE_WAIT /* Enable Wait */
77
78#define P_TS_CT 0x01 /* clear timeout. Note: writing
79 * to this register clears the
80 * timeout error int. or status
81 */
82
83
84/*
85 * The data register reads/writes to/from the 5380 in pseudo-DMA mode
86 */
87
88#define P_DATA_REG_OFFSET 0x5c00 /* rw */
89
90#define P_STATUS_REG_OFFSET 0x5c01 /* ro */
91#define P_ST_RDY 0x80 /* 5380 DDRQ Status */
92
93#define P_IRQ_STATUS 0x5c03
94#define P_IS_IRQ 0x80 /* DIRQ status */
95
96#define PCB_CONFIG 0x803
97#define MASTER_ADDRESS_PTR 0x9a01 /* Fixed position - no relo */
98#define SYS_CONFIG_4 0x8003
99#define WAIT_STATE 0xbc00
100#define OPERATION_MODE_1 0xec03
101#define IO_CONFIG_3 0xf002
102
103
104#ifndef ASM
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105
106#ifndef CMD_PER_LUN
107#define CMD_PER_LUN 2
108#endif
109
110#ifndef CAN_QUEUE
111#define CAN_QUEUE 32
112#endif
113
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114#define NCR5380_implementation_fields \
115 volatile unsigned short io_port
116
117#define NCR5380_local_declare() \
118 volatile unsigned short io_port
119
120#define NCR5380_setup(instance) \
121 io_port = (instance)->io_port
122
123#define PAS16_io_port(reg) ( io_port + pas16_offset[(reg)] )
124
125#if !(PDEBUG & PDEBUG_TRANSFER)
126#define NCR5380_read(reg) ( inb(PAS16_io_port(reg)) )
127#define NCR5380_write(reg, value) ( outb((value),PAS16_io_port(reg)) )
128#else
129#define NCR5380_read(reg) \
130 (((unsigned char) printk("scsi%d : read register %d at io_port %04x\n"\
131 , instance->hostno, (reg), PAS16_io_port(reg))), inb( PAS16_io_port(reg)) )
132
133#define NCR5380_write(reg, value) \
134 (printk("scsi%d : write %02x to register %d at io_port %04x\n", \
135 instance->hostno, (value), (reg), PAS16_io_port(reg)), \
136 outb( (value),PAS16_io_port(reg) ) )
137
138#endif
139
140
141#define NCR5380_intr pas16_intr
142#define do_NCR5380_intr do_pas16_intr
143#define NCR5380_queue_command pas16_queue_command
144#define NCR5380_abort pas16_abort
1da177e4 145#define NCR5380_bus_reset pas16_bus_reset
dd7ab71b
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146#define NCR5380_show_info pas16_show_info
147#define NCR5380_write_info pas16_write_info
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148
149/* 15 14 12 10 7 5 3
150 1101 0100 1010 1000 */
151
152#define PAS16_IRQS 0xd4a8
153
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154#endif /* ndef ASM */
155#endif /* PAS16_H */