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lpfc: remove queue_depth events
[mirror_ubuntu-artful-kernel.git] / drivers / scsi / pm8001 / pm8001_init.c
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dbf9bfe6 1/*
e5742101 2 * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver
dbf9bfe6 3 *
4 * Copyright (c) 2008-2009 USI Co., Ltd.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
25 *
26 * NO WARRANTY
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
38 *
39 */
40
5a0e3ad6 41#include <linux/slab.h>
dbf9bfe6 42#include "pm8001_sas.h"
43#include "pm8001_chips.h"
44
45static struct scsi_transport_template *pm8001_stt;
46
e5742101
S		 47/**
48 * chip info structure to identify chip key functionality as
49 * encryption available/not, no of ports, hw specific function ref
50 */
dbf9bfe6 51static const struct pm8001_chip_info pm8001_chips[] = {
e5742101 52 [chip_8001] = {0, 8, &pm8001_8001_dispatch,},
f5860992
S		 53 [chip_8008] = {0, 8, &pm8001_80xx_dispatch,},
54 [chip_8009] = {1, 8, &pm8001_80xx_dispatch,},
55 [chip_8018] = {0, 16, &pm8001_80xx_dispatch,},
56 [chip_8019] = {1, 16, &pm8001_80xx_dispatch,},
a9a923e5
AKS		 57 [chip_8074] = {0, 8, &pm8001_80xx_dispatch,},
58 [chip_8076] = {0, 16, &pm8001_80xx_dispatch,},
59 [chip_8077] = {0, 16, &pm8001_80xx_dispatch,},
dbf9bfe6 60};
61static int pm8001_id;
62
63LIST_HEAD(hba_list);
64
429305e4
TH		 65struct workqueue_struct *pm8001_wq;
66
dbf9bfe6 67/**
68 * The main structure which LLDD must register for scsi core.
69 */
70static struct scsi_host_template pm8001_sht = {
71 .module = THIS_MODULE,
72 .name = DRV_NAME,
73 .queuecommand = sas_queuecommand,
74 .target_alloc = sas_target_alloc,
11e16364 75 .slave_configure = sas_slave_configure,
dbf9bfe6 76 .scan_finished = pm8001_scan_finished,
77 .scan_start = pm8001_scan_start,
78 .change_queue_depth = sas_change_queue_depth,
79 .change_queue_type = sas_change_queue_type,
80 .bios_param = sas_bios_param,
81 .can_queue = 1,
82 .cmd_per_lun = 1,
83 .this_id = -1,
84 .sg_tablesize = SG_ALL,
85 .max_sectors = SCSI_DEFAULT_MAX_SECTORS,
86 .use_clustering = ENABLE_CLUSTERING,
87 .eh_device_reset_handler = sas_eh_device_reset_handler,
88 .eh_bus_reset_handler = sas_eh_bus_reset_handler,
dbf9bfe6 89 .target_destroy = sas_target_destroy,
90 .ioctl = sas_ioctl,
91 .shost_attrs = pm8001_host_attrs,
2ecb204d 92 .use_blk_tags = 1,
dbf9bfe6 93};
94
95/**
96 * Sas layer call this function to execute specific task.
97 */
98static struct sas_domain_function_template pm8001_transport_ops = {
99 .lldd_dev_found = pm8001_dev_found,
100 .lldd_dev_gone = pm8001_dev_gone,
101
102 .lldd_execute_task = pm8001_queue_command,
103 .lldd_control_phy = pm8001_phy_control,
104
105 .lldd_abort_task = pm8001_abort_task,
106 .lldd_abort_task_set = pm8001_abort_task_set,
107 .lldd_clear_aca = pm8001_clear_aca,
108 .lldd_clear_task_set = pm8001_clear_task_set,
109 .lldd_I_T_nexus_reset = pm8001_I_T_nexus_reset,
110 .lldd_lu_reset = pm8001_lu_reset,
111 .lldd_query_task = pm8001_query_task,
112};
113
114/**
115 *pm8001_phy_init - initiate our adapter phys
116 *@pm8001_ha: our hba structure.
117 *@phy_id: phy id.
118 */
6f039790 119static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id)
dbf9bfe6 120{
121 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
122 struct asd_sas_phy *sas_phy = &phy->sas_phy;
123 phy->phy_state = 0;
124 phy->pm8001_ha = pm8001_ha;
125 sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0;
126 sas_phy->class = SAS;
127 sas_phy->iproto = SAS_PROTOCOL_ALL;
128 sas_phy->tproto = 0;
129 sas_phy->type = PHY_TYPE_PHYSICAL;
130 sas_phy->role = PHY_ROLE_INITIATOR;
131 sas_phy->oob_mode = OOB_NOT_CONNECTED;
132 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
133 sas_phy->id = phy_id;
134 sas_phy->sas_addr = &pm8001_ha->sas_addr[0];
135 sas_phy->frame_rcvd = &phy->frame_rcvd[0];
136 sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata;
137 sas_phy->lldd_phy = phy;
138}
139
140/**
141 *pm8001_free - free hba
142 *@pm8001_ha: our hba structure.
143 *
144 */
145static void pm8001_free(struct pm8001_hba_info *pm8001_ha)
146{
147 int i;
dbf9bfe6 148
149 if (!pm8001_ha)
150 return;
151
152 for (i = 0; i < USI_MAX_MEMCNT; i++) {
153 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
154 pci_free_consistent(pm8001_ha->pdev,
bfb4809f
S		 155 (pm8001_ha->memoryMap.region[i].total_len +
156 pm8001_ha->memoryMap.region[i].alignment),
dbf9bfe6 157 pm8001_ha->memoryMap.region[i].virt_ptr,
158 pm8001_ha->memoryMap.region[i].phys_addr);
159 }
160 }
161 PM8001_CHIP_DISP->chip_iounmap(pm8001_ha);
162 if (pm8001_ha->shost)
163 scsi_host_put(pm8001_ha->shost);
429305e4 164 flush_workqueue(pm8001_wq);
dbf9bfe6 165 kfree(pm8001_ha->tags);
166 kfree(pm8001_ha);
167}
168
169#ifdef PM8001_USE_TASKLET
1245ee59
S		 170
171/**
172 * tasklet for 64 msi-x interrupt handler
173 * @opaque: the passed general host adapter struct
174 * Note: pm8001_tasklet is common for pm8001 & pm80xx
175 */
dbf9bfe6 176static void pm8001_tasklet(unsigned long opaque)
177{
178 struct pm8001_hba_info *pm8001_ha;
6cd60b37
NG		 179 struct isr_param *irq_vector;
180
181 irq_vector = (struct isr_param *)opaque;
182 pm8001_ha = irq_vector->drv_inst;
dbf9bfe6 183 if (unlikely(!pm8001_ha))
184 BUG_ON(1);
6cd60b37 185 PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
1245ee59
S		 186}
187#endif
188
1245ee59
S		 189/**
190 * pm8001_interrupt_handler_msix - main MSIX interrupt handler.
191 * It obtains the vector number and calls the equivalent bottom
192 * half or services directly.
193 * @opaque: the passed outbound queue/vector. Host structure is
194 * retrieved from the same.
195 */
196static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque)
197{
6cd60b37
NG		 198 struct isr_param *irq_vector;
199 struct pm8001_hba_info *pm8001_ha;
1245ee59 200 irqreturn_t ret = IRQ_HANDLED;
6cd60b37
NG		 201 irq_vector = (struct isr_param *)opaque;
202 pm8001_ha = irq_vector->drv_inst;
203
1245ee59
S		 204 if (unlikely(!pm8001_ha))
205 return IRQ_NONE;
206 if (!PM8001_CHIP_DISP->is_our_interupt(pm8001_ha))
207 return IRQ_NONE;
1245ee59 208#ifdef PM8001_USE_TASKLET
6cd60b37 209 tasklet_schedule(&pm8001_ha->tasklet[irq_vector->irq_id]);
1245ee59 210#else
6cd60b37 211 ret = PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
dbf9bfe6 212#endif
1245ee59
S		 213 return ret;
214}
dbf9bfe6 215
1245ee59
S		 216/**
217 * pm8001_interrupt_handler_intx - main INTx interrupt handler.
218 * @dev_id: sas_ha structure. The HBA is retrieved from sas_has structure.
219 */
dbf9bfe6 220
1245ee59 221static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id)
dbf9bfe6 222{
223 struct pm8001_hba_info *pm8001_ha;
224 irqreturn_t ret = IRQ_HANDLED;
1245ee59 225 struct sas_ha_struct *sha = dev_id;
dbf9bfe6 226 pm8001_ha = sha->lldd_ha;
227 if (unlikely(!pm8001_ha))
228 return IRQ_NONE;
229 if (!PM8001_CHIP_DISP->is_our_interupt(pm8001_ha))
230 return IRQ_NONE;
1245ee59 231
dbf9bfe6 232#ifdef PM8001_USE_TASKLET
6cd60b37 233 tasklet_schedule(&pm8001_ha->tasklet[0]);
dbf9bfe6 234#else
f74cf271 235 ret = PM8001_CHIP_DISP->isr(pm8001_ha, 0);
dbf9bfe6 236#endif
237 return ret;
238}
239
240/**
241 * pm8001_alloc - initiate our hba structure and 6 DMAs area.
242 * @pm8001_ha:our hba structure.
243 *
244 */
e590adfd
S		 245static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha,
246 const struct pci_device_id *ent)
dbf9bfe6 247{
248 int i;
249 spin_lock_init(&pm8001_ha->lock);
646cdf00 250 spin_lock_init(&pm8001_ha->bitmap_lock);
e590adfd
S		 251 PM8001_INIT_DBG(pm8001_ha,
252 pm8001_printk("pm8001_alloc: PHY:%x\n",
253 pm8001_ha->chip->n_phy));
1cc943ae 254 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
dbf9bfe6 255 pm8001_phy_init(pm8001_ha, i);
1cc943ae 256 pm8001_ha->port[i].wide_port_phymap = 0;
257 pm8001_ha->port[i].port_attached = 0;
258 pm8001_ha->port[i].port_state = 0;
259 INIT_LIST_HEAD(&pm8001_ha->port[i].list);
260 }
dbf9bfe6 261
97ee2088 262 pm8001_ha->tags = kzalloc(PM8001_MAX_CCB, GFP_KERNEL);
263 if (!pm8001_ha->tags)
264 goto err_out;
dbf9bfe6 265 /* MPI Memory region 1 for AAP Event Log for fw */
266 pm8001_ha->memoryMap.region[AAP1].num_elements = 1;
267 pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE;
268 pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE;
269 pm8001_ha->memoryMap.region[AAP1].alignment = 32;
270
271 /* MPI Memory region 2 for IOP Event Log for fw */
272 pm8001_ha->memoryMap.region[IOP].num_elements = 1;
273 pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE;
274 pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE;
275 pm8001_ha->memoryMap.region[IOP].alignment = 32;
276
e590adfd
S		 277 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
278 /* MPI Memory region 3 for consumer Index of inbound queues */
279 pm8001_ha->memoryMap.region[CI+i].num_elements = 1;
280 pm8001_ha->memoryMap.region[CI+i].element_size = 4;
281 pm8001_ha->memoryMap.region[CI+i].total_len = 4;
282 pm8001_ha->memoryMap.region[CI+i].alignment = 4;
283
284 if ((ent->driver_data) != chip_8001) {
285 /* MPI Memory region 5 inbound queues */
286 pm8001_ha->memoryMap.region[IB+i].num_elements =
287 PM8001_MPI_QUEUE;
288 pm8001_ha->memoryMap.region[IB+i].element_size = 128;
289 pm8001_ha->memoryMap.region[IB+i].total_len =
290 PM8001_MPI_QUEUE * 128;
291 pm8001_ha->memoryMap.region[IB+i].alignment = 128;
292 } else {
293 pm8001_ha->memoryMap.region[IB+i].num_elements =
294 PM8001_MPI_QUEUE;
295 pm8001_ha->memoryMap.region[IB+i].element_size = 64;
296 pm8001_ha->memoryMap.region[IB+i].total_len =
297 PM8001_MPI_QUEUE * 64;
298 pm8001_ha->memoryMap.region[IB+i].alignment = 64;
299 }
300 }
301
302 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
303 /* MPI Memory region 4 for producer Index of outbound queues */
304 pm8001_ha->memoryMap.region[PI+i].num_elements = 1;
305 pm8001_ha->memoryMap.region[PI+i].element_size = 4;
306 pm8001_ha->memoryMap.region[PI+i].total_len = 4;
307 pm8001_ha->memoryMap.region[PI+i].alignment = 4;
308
309 if (ent->driver_data != chip_8001) {
310 /* MPI Memory region 6 Outbound queues */
311 pm8001_ha->memoryMap.region[OB+i].num_elements =
312 PM8001_MPI_QUEUE;
313 pm8001_ha->memoryMap.region[OB+i].element_size = 128;
314 pm8001_ha->memoryMap.region[OB+i].total_len =
315 PM8001_MPI_QUEUE * 128;
316 pm8001_ha->memoryMap.region[OB+i].alignment = 128;
317 } else {
318 /* MPI Memory region 6 Outbound queues */
319 pm8001_ha->memoryMap.region[OB+i].num_elements =
320 PM8001_MPI_QUEUE;
321 pm8001_ha->memoryMap.region[OB+i].element_size = 64;
322 pm8001_ha->memoryMap.region[OB+i].total_len =
323 PM8001_MPI_QUEUE * 64;
324 pm8001_ha->memoryMap.region[OB+i].alignment = 64;
325 }
dbf9bfe6 326
e590adfd 327 }
dbf9bfe6 328 /* Memory region write DMA*/
329 pm8001_ha->memoryMap.region[NVMD].num_elements = 1;
330 pm8001_ha->memoryMap.region[NVMD].element_size = 4096;
331 pm8001_ha->memoryMap.region[NVMD].total_len = 4096;
332 /* Memory region for devices*/
333 pm8001_ha->memoryMap.region[DEV_MEM].num_elements = 1;
334 pm8001_ha->memoryMap.region[DEV_MEM].element_size = PM8001_MAX_DEVICES *
335 sizeof(struct pm8001_device);
336 pm8001_ha->memoryMap.region[DEV_MEM].total_len = PM8001_MAX_DEVICES *
337 sizeof(struct pm8001_device);
338
339 /* Memory region for ccb_info*/
340 pm8001_ha->memoryMap.region[CCB_MEM].num_elements = 1;
341 pm8001_ha->memoryMap.region[CCB_MEM].element_size = PM8001_MAX_CCB *
342 sizeof(struct pm8001_ccb_info);
343 pm8001_ha->memoryMap.region[CCB_MEM].total_len = PM8001_MAX_CCB *
344 sizeof(struct pm8001_ccb_info);
345
1c75a679
S		 346 /* Memory region for fw flash */
347 pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096;
348
d078b511
AKS		 349 pm8001_ha->memoryMap.region[FORENSIC_MEM].num_elements = 1;
350 pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000;
351 pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000;
352 pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000;
dbf9bfe6 353 for (i = 0; i < USI_MAX_MEMCNT; i++) {
354 if (pm8001_mem_alloc(pm8001_ha->pdev,
355 &pm8001_ha->memoryMap.region[i].virt_ptr,
356 &pm8001_ha->memoryMap.region[i].phys_addr,
357 &pm8001_ha->memoryMap.region[i].phys_addr_hi,
358 &pm8001_ha->memoryMap.region[i].phys_addr_lo,
359 pm8001_ha->memoryMap.region[i].total_len,
360 pm8001_ha->memoryMap.region[i].alignment) != 0) {
361 PM8001_FAIL_DBG(pm8001_ha,
362 pm8001_printk("Mem%d alloc failed\n",
363 i));
364 goto err_out;
365 }
366 }
367
368 pm8001_ha->devices = pm8001_ha->memoryMap.region[DEV_MEM].virt_ptr;
369 for (i = 0; i < PM8001_MAX_DEVICES; i++) {
aa9f8328 370 pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED;
dbf9bfe6 371 pm8001_ha->devices[i].id = i;
372 pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES;
373 pm8001_ha->devices[i].running_req = 0;
374 }
375 pm8001_ha->ccb_info = pm8001_ha->memoryMap.region[CCB_MEM].virt_ptr;
376 for (i = 0; i < PM8001_MAX_CCB; i++) {
377 pm8001_ha->ccb_info[i].ccb_dma_handle =
378 pm8001_ha->memoryMap.region[CCB_MEM].phys_addr +
379 i * sizeof(struct pm8001_ccb_info);
97ee2088 380 pm8001_ha->ccb_info[i].task = NULL;
381 pm8001_ha->ccb_info[i].ccb_tag = 0xffffffff;
382 pm8001_ha->ccb_info[i].device = NULL;
dbf9bfe6 383 ++pm8001_ha->tags_num;
384 }
385 pm8001_ha->flags = PM8001F_INIT_TIME;
386 /* Initialize tags */
387 pm8001_tag_init(pm8001_ha);
388 return 0;
389err_out:
390 return 1;
391}
392
393/**
394 * pm8001_ioremap - remap the pci high physical address to kernal virtual
395 * address so that we can access them.
396 * @pm8001_ha:our hba structure.
397 */
398static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha)
399{
400 u32 bar;
401 u32 logicalBar = 0;
402 struct pci_dev *pdev;
403
404 pdev = pm8001_ha->pdev;
405 /* map pci mem (PMC pci base 0-3)*/
406 for (bar = 0; bar < 6; bar++) {
407 /*
408 ** logical BARs for SPC:
409 ** bar 0 and 1 - logical BAR0
410 ** bar 2 and 3 - logical BAR1
411 ** bar4 - logical BAR2
412 ** bar5 - logical BAR3
413 ** Skip the appropriate assignments:
414 */
415 if ((bar == 1) || (bar == 3))
416 continue;
417 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
418 pm8001_ha->io_mem[logicalBar].membase =
419 pci_resource_start(pdev, bar);
420 pm8001_ha->io_mem[logicalBar].membase &=
421 (u32)PCI_BASE_ADDRESS_MEM_MASK;
422 pm8001_ha->io_mem[logicalBar].memsize =
423 pci_resource_len(pdev, bar);
424 pm8001_ha->io_mem[logicalBar].memvirtaddr =
425 ioremap(pm8001_ha->io_mem[logicalBar].membase,
426 pm8001_ha->io_mem[logicalBar].memsize);
427 PM8001_INIT_DBG(pm8001_ha,
e590adfd
S		 428 pm8001_printk("PCI: bar %d, logicalBar %d ",
429 bar, logicalBar));
430 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
431 "base addr %llx virt_addr=%llx len=%d\n",
432 (u64)pm8001_ha->io_mem[logicalBar].membase,
da1dccce
AKS		 433 (u64)(unsigned long)
434 pm8001_ha->io_mem[logicalBar].memvirtaddr,
dbf9bfe6 435 pm8001_ha->io_mem[logicalBar].memsize));
436 } else {
437 pm8001_ha->io_mem[logicalBar].membase = 0;
438 pm8001_ha->io_mem[logicalBar].memsize = 0;
439 pm8001_ha->io_mem[logicalBar].memvirtaddr = 0;
440 }
441 logicalBar++;
442 }
443 return 0;
444}
445
446/**
447 * pm8001_pci_alloc - initialize our ha card structure
448 * @pdev: pci device.
449 * @ent: ent
450 * @shost: scsi host struct which has been initialized before.
451 */
6f039790 452static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev,
e590adfd
S		 453 const struct pci_device_id *ent,
454 struct Scsi_Host *shost)
455
dbf9bfe6 456{
457 struct pm8001_hba_info *pm8001_ha;
458 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
6cd60b37 459 int j;
dbf9bfe6 460
461 pm8001_ha = sha->lldd_ha;
462 if (!pm8001_ha)
463 return NULL;
464
465 pm8001_ha->pdev = pdev;
466 pm8001_ha->dev = &pdev->dev;
e590adfd 467 pm8001_ha->chip_id = ent->driver_data;
dbf9bfe6 468 pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id];
469 pm8001_ha->irq = pdev->irq;
470 pm8001_ha->sas = sha;
471 pm8001_ha->shost = shost;
472 pm8001_ha->id = pm8001_id++;
dbf9bfe6 473 pm8001_ha->logging_level = 0x01;
474 sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id);
f74cf271
S		 475 /* IOMB size is 128 for 8088/89 controllers */
476 if (pm8001_ha->chip_id != chip_8001)
477 pm8001_ha->iomb_size = IOMB_SIZE_SPCV;
478 else
479 pm8001_ha->iomb_size = IOMB_SIZE_SPC;
480
dbf9bfe6 481#ifdef PM8001_USE_TASKLET
6cd60b37
NG		 482 /* Tasklet for non msi-x interrupt handler */
483 if ((!pdev->msix_cap) || (pm8001_ha->chip_id == chip_8001))
484 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
485 (unsigned long)&(pm8001_ha->irq_vector[0]));
486 else
487 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
488 tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
489 (unsigned long)&(pm8001_ha->irq_vector[j]));
dbf9bfe6 490#endif
491 pm8001_ioremap(pm8001_ha);
e590adfd 492 if (!pm8001_alloc(pm8001_ha, ent))
dbf9bfe6 493 return pm8001_ha;
494 pm8001_free(pm8001_ha);
495 return NULL;
496}
497
498/**
499 * pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit
500 * @pdev: pci device.
501 */
502static int pci_go_44(struct pci_dev *pdev)
503{
504 int rc;
505
506 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(44))) {
507 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(44));
508 if (rc) {
509 rc = pci_set_consistent_dma_mask(pdev,
510 DMA_BIT_MASK(32));
511 if (rc) {
512 dev_printk(KERN_ERR, &pdev->dev,
513 "44-bit DMA enable failed\n");
514 return rc;
515 }
516 }
517 } else {
518 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
519 if (rc) {
520 dev_printk(KERN_ERR, &pdev->dev,
521 "32-bit DMA enable failed\n");
522 return rc;
523 }
524 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
525 if (rc) {
526 dev_printk(KERN_ERR, &pdev->dev,
527 "32-bit consistent DMA enable failed\n");
528 return rc;
529 }
530 }
531 return rc;
532}
533
534/**
535 * pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them.
536 * @shost: scsi host which has been allocated outside.
537 * @chip_info: our ha struct.
538 */
6f039790
GKH		 539static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost,
540 const struct pm8001_chip_info *chip_info)
dbf9bfe6 541{
542 int phy_nr, port_nr;
543 struct asd_sas_phy **arr_phy;
544 struct asd_sas_port **arr_port;
545 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
546
547 phy_nr = chip_info->n_phy;
548 port_nr = phy_nr;
549 memset(sha, 0x00, sizeof(*sha));
550 arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
551 if (!arr_phy)
552 goto exit;
553 arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
554 if (!arr_port)
555 goto exit_free2;
556
557 sha->sas_phy = arr_phy;
558 sha->sas_port = arr_port;
559 sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL);
560 if (!sha->lldd_ha)
561 goto exit_free1;
562
563 shost->transportt = pm8001_stt;
564 shost->max_id = PM8001_MAX_DEVICES;
565 shost->max_lun = 8;
566 shost->max_channel = 0;
567 shost->unique_id = pm8001_id;
568 shost->max_cmd_len = 16;
569 shost->can_queue = PM8001_CAN_QUEUE;
570 shost->cmd_per_lun = 32;
571 return 0;
572exit_free1:
573 kfree(arr_port);
574exit_free2:
575 kfree(arr_phy);
576exit:
577 return -1;
578}
579
580/**
581 * pm8001_post_sas_ha_init - initialize general hba struct defined in libsas
582 * @shost: scsi host which has been allocated outside
583 * @chip_info: our ha struct.
584 */
6f039790
GKH		 585static void pm8001_post_sas_ha_init(struct Scsi_Host *shost,
586 const struct pm8001_chip_info *chip_info)
dbf9bfe6 587{
588 int i = 0;
589 struct pm8001_hba_info *pm8001_ha;
590 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
591
592 pm8001_ha = sha->lldd_ha;
593 for (i = 0; i < chip_info->n_phy; i++) {
594 sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy;
595 sha->sas_port[i] = &pm8001_ha->port[i].sas_port;
596 }
597 sha->sas_ha_name = DRV_NAME;
598 sha->dev = pm8001_ha->dev;
599
600 sha->lldd_module = THIS_MODULE;
601 sha->sas_addr = &pm8001_ha->sas_addr[0];
602 sha->num_phys = chip_info->n_phy;
603 sha->lldd_max_execute_num = 1;
604 sha->lldd_queue_size = PM8001_CAN_QUEUE;
605 sha->core.shost = shost;
606}
607
608/**
609 * pm8001_init_sas_add - initialize sas address
610 * @chip_info: our ha struct.
611 *
612 * Currently we just set the fixed SAS address to our HBA,for manufacture,
613 * it should read from the EEPROM
614 */
615static void pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha)
616{
a33a0155 617 u8 i, j;
dbf9bfe6 618#ifdef PM8001_READ_VPD
a33a0155
S		 619 /* For new SPC controllers WWN is stored in flash vpd
620 * For SPC/SPCve controllers WWN is stored in EEPROM
621 * For Older SPC WWN is stored in NVMD
622 */
dbf9bfe6 623 DECLARE_COMPLETION_ONSTACK(completion);
7c8356d9 624 struct pm8001_ioctl_payload payload;
a33a0155 625 u16 deviceid;
5b4ce882
TH		 626 int rc;
627
a33a0155 628 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
dbf9bfe6 629 pm8001_ha->nvmd_completion = &completion;
a33a0155
S		 630
631 if (pm8001_ha->chip_id == chip_8001) {
f49d2132 632 if (deviceid == 0x8081 || deviceid == 0x0042) {
a33a0155
S		 633 payload.minor_function = 4;
634 payload.length = 4096;
635 } else {
636 payload.minor_function = 0;
637 payload.length = 128;
638 }
639 } else {
640 payload.minor_function = 1;
641 payload.length = 4096;
642 }
643 payload.offset = 0;
644 payload.func_specific = kzalloc(payload.length, GFP_KERNEL);
5b4ce882
TH		 645 if (!payload.func_specific) {
646 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("mem alloc fail\n"));
647 return;
648 }
649 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
650 if (rc) {
651 kfree(payload.func_specific);
652 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("nvmd failed\n"));
653 return;
654 }
dbf9bfe6 655 wait_for_completion(&completion);
a33a0155
S		 656
657 for (i = 0, j = 0; i <= 7; i++, j++) {
658 if (pm8001_ha->chip_id == chip_8001) {
659 if (deviceid == 0x8081)
660 pm8001_ha->sas_addr[j] =
661 payload.func_specific[0x704 + i];
f49d2132
BG		 662 else if (deviceid == 0x0042)
663 pm8001_ha->sas_addr[j] =
664 payload.func_specific[0x010 + i];
a33a0155
S		 665 } else
666 pm8001_ha->sas_addr[j] =
667 payload.func_specific[0x804 + i];
668 }
669
dbf9bfe6 670 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
a33a0155
S		 671 memcpy(&pm8001_ha->phy[i].dev_sas_addr,
672 pm8001_ha->sas_addr, SAS_ADDR_SIZE);
dbf9bfe6 673 PM8001_INIT_DBG(pm8001_ha,
a33a0155 674 pm8001_printk("phy %d sas_addr = %016llx\n", i,
7c8356d9 675 pm8001_ha->phy[i].dev_sas_addr));
dbf9bfe6 676 }
5b4ce882 677 kfree(payload.func_specific);
dbf9bfe6 678#else
679 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
7c8356d9 680 pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL;
dbf9bfe6 681 pm8001_ha->phy[i].dev_sas_addr =
682 cpu_to_be64((u64)
683 (*(u64 *)&pm8001_ha->phy[i].dev_sas_addr));
684 }
685 memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr,
686 SAS_ADDR_SIZE);
687#endif
688}
689
27909407
AKS		 690/*
691 * pm8001_get_phy_settings_info : Read phy setting values.
692 * @pm8001_ha : our hba.
693 */
f2c6f180 694static int pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha)
27909407
AKS		 695{
696
697#ifdef PM8001_READ_VPD
698 /*OPTION ROM FLASH read for the SPC cards */
699 DECLARE_COMPLETION_ONSTACK(completion);
700 struct pm8001_ioctl_payload payload;
5b4ce882 701 int rc;
27909407
AKS		 702
703 pm8001_ha->nvmd_completion = &completion;
704 /* SAS ADDRESS read from flash / EEPROM */
705 payload.minor_function = 6;
706 payload.offset = 0;
707 payload.length = 4096;
708 payload.func_specific = kzalloc(4096, GFP_KERNEL);
f2c6f180
ML		 709 if (!payload.func_specific)
710 return -ENOMEM;
27909407 711 /* Read phy setting values from flash */
5b4ce882
TH		 712 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
713 if (rc) {
714 kfree(payload.func_specific);
715 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("nvmd failed\n"));
716 return -ENOMEM;
717 }
27909407
AKS		 718 wait_for_completion(&completion);
719 pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific);
f2c6f180 720 kfree(payload.func_specific);
27909407 721#endif
f2c6f180 722 return 0;
27909407
AKS		 723}
724
dbf9bfe6 725#ifdef PM8001_USE_MSIX
726/**
727 * pm8001_setup_msix - enable MSI-X interrupt
728 * @chip_info: our ha struct.
729 * @irq_handler: irq_handler
730 */
1245ee59 731static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha)
dbf9bfe6 732{
733 u32 i = 0, j = 0;
1245ee59 734 u32 number_of_intr;
dbf9bfe6 735 int flag = 0;
736 u32 max_entry;
737 int rc;
1245ee59
S		 738 static char intr_drvname[PM8001_MAX_MSIX_VEC][sizeof(DRV_NAME)+3];
739
740 /* SPCv controllers supports 64 msi-x */
741 if (pm8001_ha->chip_id == chip_8001) {
742 number_of_intr = 1;
1245ee59
S		 743 } else {
744 number_of_intr = PM8001_MAX_MSIX_VEC;
745 flag &= ~IRQF_SHARED;
1245ee59
S		 746 }
747
dbf9bfe6 748 max_entry = sizeof(pm8001_ha->msix_entries) /
749 sizeof(pm8001_ha->msix_entries[0]);
dbf9bfe6 750 for (i = 0; i < max_entry ; i++)
751 pm8001_ha->msix_entries[i].entry = i;
b4d511e5 752 rc = pci_enable_msix_exact(pm8001_ha->pdev, pm8001_ha->msix_entries,
dbf9bfe6 753 number_of_intr);
754 pm8001_ha->number_of_intr = number_of_intr;
b4d511e5
AG		 755 if (rc)
756 return rc;
757
758 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
759 "pci_enable_msix_exact request ret:%d no of intr %d\n",
760 rc, pm8001_ha->number_of_intr));
761
762 for (i = 0; i < number_of_intr; i++) {
763 snprintf(intr_drvname[i], sizeof(intr_drvname[0]),
764 DRV_NAME"%d", i);
765 pm8001_ha->irq_vector[i].irq_id = i;
766 pm8001_ha->irq_vector[i].drv_inst = pm8001_ha;
767
768 rc = request_irq(pm8001_ha->msix_entries[i].vector,
769 pm8001_interrupt_handler_msix, flag,
770 intr_drvname[i], &(pm8001_ha->irq_vector[i]));
771 if (rc) {
772 for (j = 0; j < i; j++) {
773 free_irq(pm8001_ha->msix_entries[j].vector,
6cd60b37 774 &(pm8001_ha->irq_vector[i]));
dbf9bfe6 775 }
b4d511e5
AG		 776 pci_disable_msix(pm8001_ha->pdev);
777 break;
dbf9bfe6 778 }
779 }
b4d511e5 780
dbf9bfe6 781 return rc;
782}
783#endif
784
785/**
786 * pm8001_request_irq - register interrupt
787 * @chip_info: our ha struct.
788 */
789static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha)
790{
791 struct pci_dev *pdev;
97ee2088 792 int rc;
dbf9bfe6 793
794 pdev = pm8001_ha->pdev;
795
796#ifdef PM8001_USE_MSIX
e1e819cc 797 if (pdev->msix_cap)
1245ee59
S		 798 return pm8001_setup_msix(pm8001_ha);
799 else {
800 PM8001_INIT_DBG(pm8001_ha,
801 pm8001_printk("MSIX not supported!!!\n"));
dbf9bfe6 802 goto intx;
1245ee59 803 }
dbf9bfe6 804#endif
805
806intx:
b595076a 807 /* initialize the INT-X interrupt */
1245ee59
S		 808 rc = request_irq(pdev->irq, pm8001_interrupt_handler_intx, IRQF_SHARED,
809 DRV_NAME, SHOST_TO_SAS_HA(pm8001_ha->shost));
dbf9bfe6 810 return rc;
811}
812
813/**
814 * pm8001_pci_probe - probe supported device
815 * @pdev: pci device which kernel has been prepared for.
816 * @ent: pci device id
817 *
818 * This function is the main initialization function, when register a new
819 * pci driver it is invoked, all struct an hardware initilization should be done
820 * here, also, register interrupt
821 */
6f039790
GKH		 822static int pm8001_pci_probe(struct pci_dev *pdev,
823 const struct pci_device_id *ent)
dbf9bfe6 824{
825 unsigned int rc;
826 u32 pci_reg;
1245ee59 827 u8 i = 0;
dbf9bfe6 828 struct pm8001_hba_info *pm8001_ha;
829 struct Scsi_Host *shost = NULL;
830 const struct pm8001_chip_info *chip;
831
832 dev_printk(KERN_INFO, &pdev->dev,
a70b8fc3 833 "pm80xx: driver version %s\n", DRV_VERSION);
dbf9bfe6 834 rc = pci_enable_device(pdev);
835 if (rc)
836 goto err_out_enable;
837 pci_set_master(pdev);
838 /*
839 * Enable pci slot busmaster by setting pci command register.
840 * This is required by FW for Cyclone card.
841 */
842
843 pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg);
844 pci_reg |= 0x157;
845 pci_write_config_dword(pdev, PCI_COMMAND, pci_reg);
846 rc = pci_request_regions(pdev, DRV_NAME);
847 if (rc)
848 goto err_out_disable;
849 rc = pci_go_44(pdev);
850 if (rc)
851 goto err_out_regions;
852
853 shost = scsi_host_alloc(&pm8001_sht, sizeof(void *));
854 if (!shost) {
855 rc = -ENOMEM;
856 goto err_out_regions;
857 }
858 chip = &pm8001_chips[ent->driver_data];
859 SHOST_TO_SAS_HA(shost) =
3dbf6c00 860 kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL);
dbf9bfe6 861 if (!SHOST_TO_SAS_HA(shost)) {
862 rc = -ENOMEM;
863 goto err_out_free_host;
864 }
865
866 rc = pm8001_prep_sas_ha_init(shost, chip);
867 if (rc) {
868 rc = -ENOMEM;
869 goto err_out_free;
870 }
871 pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
e590adfd
S		 872 /* ent->driver variable is used to differentiate between controllers */
873 pm8001_ha = pm8001_pci_alloc(pdev, ent, shost);
dbf9bfe6 874 if (!pm8001_ha) {
875 rc = -ENOMEM;
876 goto err_out_free;
877 }
878 list_add_tail(&pm8001_ha->list, &hba_list);
f5860992 879 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
dbf9bfe6 880 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
a70b8fc3
S		 881 if (rc) {
882 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
883 "chip_init failed [ret: %d]\n", rc));
dbf9bfe6 884 goto err_out_ha_free;
a70b8fc3 885 }
dbf9bfe6 886
887 rc = scsi_add_host(shost, &pdev->dev);
888 if (rc)
889 goto err_out_ha_free;
890 rc = pm8001_request_irq(pm8001_ha);
a70b8fc3
S		 891 if (rc) {
892 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
893 "pm8001_request_irq failed [ret: %d]\n", rc));
dbf9bfe6 894 goto err_out_shost;
a70b8fc3 895 }
dbf9bfe6 896
f74cf271 897 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1245ee59
S		 898 if (pm8001_ha->chip_id != chip_8001) {
899 for (i = 1; i < pm8001_ha->number_of_intr; i++)
900 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
a6cb3d01
S		 901 /* setup thermal configuration. */
902 pm80xx_set_thermal_config(pm8001_ha);
1245ee59
S		 903 }
904
dbf9bfe6 905 pm8001_init_sas_add(pm8001_ha);
27909407
AKS		 906 /* phy setting support for motherboard controller */
907 if (pdev->subsystem_vendor != PCI_VENDOR_ID_ADAPTEC2 &&
f2c6f180
ML		 908 pdev->subsystem_vendor != 0) {
909 rc = pm8001_get_phy_settings_info(pm8001_ha);
910 if (rc)
911 goto err_out_shost;
912 }
dbf9bfe6 913 pm8001_post_sas_ha_init(shost, chip);
914 rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
915 if (rc)
916 goto err_out_shost;
917 scsi_scan_host(pm8001_ha->shost);
918 return 0;
919
920err_out_shost:
921 scsi_remove_host(pm8001_ha->shost);
922err_out_ha_free:
923 pm8001_free(pm8001_ha);
924err_out_free:
925 kfree(SHOST_TO_SAS_HA(shost));
926err_out_free_host:
927 kfree(shost);
928err_out_regions:
929 pci_release_regions(pdev);
930err_out_disable:
931 pci_disable_device(pdev);
932err_out_enable:
933 return rc;
934}
935
6f039790 936static void pm8001_pci_remove(struct pci_dev *pdev)
dbf9bfe6 937{
938 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
939 struct pm8001_hba_info *pm8001_ha;
6cd60b37 940 int i, j;
dbf9bfe6 941 pm8001_ha = sha->lldd_ha;
dbf9bfe6 942 sas_unregister_ha(sha);
943 sas_remove_host(pm8001_ha->shost);
944 list_del(&pm8001_ha->list);
945 scsi_remove_host(pm8001_ha->shost);
1245ee59 946 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
f5860992 947 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
dbf9bfe6 948
949#ifdef PM8001_USE_MSIX
950 for (i = 0; i < pm8001_ha->number_of_intr; i++)
951 synchronize_irq(pm8001_ha->msix_entries[i].vector);
952 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1245ee59 953 free_irq(pm8001_ha->msix_entries[i].vector,
6cd60b37 954 &(pm8001_ha->irq_vector[i]));
dbf9bfe6 955 pci_disable_msix(pdev);
956#else
957 free_irq(pm8001_ha->irq, sha);
958#endif
959#ifdef PM8001_USE_TASKLET
6cd60b37
NG		 960 /* For non-msix and msix interrupts */
961 if ((!pdev->msix_cap) || (pm8001_ha->chip_id == chip_8001))
962 tasklet_kill(&pm8001_ha->tasklet[0]);
963 else
964 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
965 tasklet_kill(&pm8001_ha->tasklet[j]);
dbf9bfe6 966#endif
967 pm8001_free(pm8001_ha);
968 kfree(sha->sas_phy);
969 kfree(sha->sas_port);
970 kfree(sha);
971 pci_release_regions(pdev);
972 pci_disable_device(pdev);
973}
974
975/**
976 * pm8001_pci_suspend - power management suspend main entry point
977 * @pdev: PCI device struct
978 * @state: PM state change to (usually PCI_D3)
979 *
980 * Returns 0 success, anything else error.
981 */
982static int pm8001_pci_suspend(struct pci_dev *pdev, pm_message_t state)
983{
984 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
985 struct pm8001_hba_info *pm8001_ha;
6cd60b37 986 int i, j;
dbf9bfe6 987 u32 device_state;
988 pm8001_ha = sha->lldd_ha;
9f176099 989 sas_suspend_ha(sha);
429305e4 990 flush_workqueue(pm8001_wq);
dbf9bfe6 991 scsi_block_requests(pm8001_ha->shost);
c8a2ba3f
YW		 992 if (!pdev->pm_cap) {
993 dev_err(&pdev->dev, " PCI PM not supported\n");
dbf9bfe6 994 return -ENODEV;
995 }
1245ee59 996 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
f5860992 997 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
dbf9bfe6 998#ifdef PM8001_USE_MSIX
999 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1000 synchronize_irq(pm8001_ha->msix_entries[i].vector);
1001 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1245ee59 1002 free_irq(pm8001_ha->msix_entries[i].vector,
6cd60b37 1003 &(pm8001_ha->irq_vector[i]));
dbf9bfe6 1004 pci_disable_msix(pdev);
1005#else
1006 free_irq(pm8001_ha->irq, sha);
1007#endif
1008#ifdef PM8001_USE_TASKLET
6cd60b37
NG		 1009 /* For non-msix and msix interrupts */
1010 if ((!pdev->msix_cap) || (pm8001_ha->chip_id == chip_8001))
1011 tasklet_kill(&pm8001_ha->tasklet[0]);
1012 else
1013 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1014 tasklet_kill(&pm8001_ha->tasklet[j]);
dbf9bfe6 1015#endif
1016 device_state = pci_choose_state(pdev, state);
1017 pm8001_printk("pdev=0x%p, slot=%s, entering "
1018 "operating state [D%d]\n", pdev,
1019 pm8001_ha->name, device_state);
1020 pci_save_state(pdev);
1021 pci_disable_device(pdev);
1022 pci_set_power_state(pdev, device_state);
1023 return 0;
1024}
1025
1026/**
1027 * pm8001_pci_resume - power management resume main entry point
1028 * @pdev: PCI device struct
1029 *
1030 * Returns 0 success, anything else error.
1031 */
1032static int pm8001_pci_resume(struct pci_dev *pdev)
1033{
1034 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1035 struct pm8001_hba_info *pm8001_ha;
1036 int rc;
6cd60b37 1037 u8 i = 0, j;
dbf9bfe6 1038 u32 device_state;
9f176099 1039 DECLARE_COMPLETION_ONSTACK(completion);
dbf9bfe6 1040 pm8001_ha = sha->lldd_ha;
1041 device_state = pdev->current_state;
1042
1043 pm8001_printk("pdev=0x%p, slot=%s, resuming from previous "
1044 "operating state [D%d]\n", pdev, pm8001_ha->name, device_state);
1045
1046 pci_set_power_state(pdev, PCI_D0);
1047 pci_enable_wake(pdev, PCI_D0, 0);
1048 pci_restore_state(pdev);
1049 rc = pci_enable_device(pdev);
1050 if (rc) {
1051 pm8001_printk("slot=%s Enable device failed during resume\n",
1052 pm8001_ha->name);
1053 goto err_out_enable;
1054 }
1055
1056 pci_set_master(pdev);
1057 rc = pci_go_44(pdev);
1058 if (rc)
1059 goto err_out_disable;
9f176099 1060 sas_prep_resume_ha(sha);
f5860992
S		 1061 /* chip soft rst only for spc */
1062 if (pm8001_ha->chip_id == chip_8001) {
1063 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1064 PM8001_INIT_DBG(pm8001_ha,
1065 pm8001_printk("chip soft reset successful\n"));
1066 }
dbf9bfe6 1067 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1068 if (rc)
1069 goto err_out_disable;
1245ee59
S		 1070
1071 /* disable all the interrupt bits */
1072 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1073
dbf9bfe6 1074 rc = pm8001_request_irq(pm8001_ha);
1075 if (rc)
1076 goto err_out_disable;
1245ee59 1077#ifdef PM8001_USE_TASKLET
6cd60b37
NG		 1078 /* Tasklet for non msi-x interrupt handler */
1079 if ((!pdev->msix_cap) || (pm8001_ha->chip_id == chip_8001))
1080 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
1081 (unsigned long)&(pm8001_ha->irq_vector[0]));
1082 else
1083 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1084 tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
1085 (unsigned long)&(pm8001_ha->irq_vector[j]));
1245ee59 1086#endif
f74cf271 1087 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1245ee59
S		 1088 if (pm8001_ha->chip_id != chip_8001) {
1089 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1090 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1091 }
9f176099
BG		 1092 pm8001_ha->flags = PM8001F_RUN_TIME;
1093 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
1094 pm8001_ha->phy[i].enable_completion = &completion;
1095 PM8001_CHIP_DISP->phy_start_req(pm8001_ha, i);
1096 wait_for_completion(&completion);
1097 }
1098 sas_resume_ha(sha);
dbf9bfe6 1099 return 0;
1100
1101err_out_disable:
1102 scsi_remove_host(pm8001_ha->shost);
1103 pci_disable_device(pdev);
1104err_out_enable:
1105 return rc;
1106}
1107
e5742101
S		 1108/* update of pci device, vendor id and driver data with
1109 * unique value for each of the controller
1110 */
6f039790 1111static struct pci_device_id pm8001_pci_table[] = {
e5742101 1112 { PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 },
f49d2132 1113 { PCI_VDEVICE(ATTO, 0x0042), chip_8001 },
e5742101
S		 1114 /* Support for SPC/SPCv/SPCve controllers */
1115 { PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 },
1116 { PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 },
1117 { PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 },
1118 { PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 },
1119 { PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 },
1120 { PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 },
1121 { PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 },
1122 { PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 },
1123 { PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 },
a9a923e5
AKS		 1124 { PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 },
1125 { PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 },
1126 { PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 },
1127 { PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 },
1128 { PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 },
1129 { PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 },
e5742101
S		 1130 { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1131 PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 },
1132 { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1133 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 },
1134 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1135 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 },
1136 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1137 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 },
1138 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1139 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 },
1140 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1141 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 },
1142 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1143 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 },
1144 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1145 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 },
1146 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1147 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 },
1148 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1149 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 },
a9a923e5
AKS		 1150 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1151 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 },
1152 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1153 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 },
1154 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1155 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 },
1156 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1157 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 },
1158 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1159 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 },
1160 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1161 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 },
1162 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1163 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 },
1164 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1165 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 },
1166 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1167 PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 },
dbf9bfe6 1168 {} /* terminate list */
1169};
1170
1171static struct pci_driver pm8001_pci_driver = {
1172 .name = DRV_NAME,
1173 .id_table = pm8001_pci_table,
1174 .probe = pm8001_pci_probe,
6f039790 1175 .remove = pm8001_pci_remove,
dbf9bfe6 1176 .suspend = pm8001_pci_suspend,
1177 .resume = pm8001_pci_resume,
1178};
1179
1180/**
1181 * pm8001_init - initialize scsi transport template
1182 */
1183static int __init pm8001_init(void)
1184{
429305e4
TH		 1185 int rc = -ENOMEM;
1186
a70b8fc3 1187 pm8001_wq = alloc_workqueue("pm80xx", 0, 0);
429305e4
TH		 1188 if (!pm8001_wq)
1189 goto err;
1190
dbf9bfe6 1191 pm8001_id = 0;
1192 pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops);
1193 if (!pm8001_stt)
429305e4 1194 goto err_wq;
dbf9bfe6 1195 rc = pci_register_driver(&pm8001_pci_driver);
1196 if (rc)
429305e4 1197 goto err_tp;
dbf9bfe6 1198 return 0;
429305e4
TH		 1199
1200err_tp:
dbf9bfe6 1201 sas_release_transport(pm8001_stt);
429305e4
TH		 1202err_wq:
1203 destroy_workqueue(pm8001_wq);
1204err:
dbf9bfe6 1205 return rc;
1206}
1207
1208static void __exit pm8001_exit(void)
1209{
1210 pci_unregister_driver(&pm8001_pci_driver);
1211 sas_release_transport(pm8001_stt);
429305e4 1212 destroy_workqueue(pm8001_wq);
dbf9bfe6 1213}
1214
1215module_init(pm8001_init);
1216module_exit(pm8001_exit);
1217
1218MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>");
a9a923e5
AKS		 1219MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>");
1220MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>");
94f33c16 1221MODULE_AUTHOR("Nikith Ganigarakoppal <Nikith.Ganigarakoppal@pmcs.com>");
e5742101 1222MODULE_DESCRIPTION(
a9a923e5
AKS		 1223 "PMC-Sierra PM8001/8081/8088/8089/8074/8076/8077 "
1224 "SAS/SATA controller driver");
dbf9bfe6 1225MODULE_VERSION(DRV_VERSION);
1226MODULE_LICENSE("GPL");
1227MODULE_DEVICE_TABLE(pci, pm8001_pci_table);
1228
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