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[SCSI] pm80xx: NCQ error handling changes
[mirror_ubuntu-artful-kernel.git] / drivers / scsi / pm8001 / pm8001_init.c
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dbf9bfe6 1/*
e5742101 2 * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver
dbf9bfe6 3 *
4 * Copyright (c) 2008-2009 USI Co., Ltd.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
25 *
26 * NO WARRANTY
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
38 *
39 */
40
5a0e3ad6 41#include <linux/slab.h>
dbf9bfe6 42#include "pm8001_sas.h"
43#include "pm8001_chips.h"
44
45static struct scsi_transport_template *pm8001_stt;
46
e5742101
S		 47/**
48 * chip info structure to identify chip key functionality as
49 * encryption available/not, no of ports, hw specific function ref
50 */
dbf9bfe6 51static const struct pm8001_chip_info pm8001_chips[] = {
e5742101 52 [chip_8001] = {0, 8, &pm8001_8001_dispatch,},
f5860992
S		 53 [chip_8008] = {0, 8, &pm8001_80xx_dispatch,},
54 [chip_8009] = {1, 8, &pm8001_80xx_dispatch,},
55 [chip_8018] = {0, 16, &pm8001_80xx_dispatch,},
56 [chip_8019] = {1, 16, &pm8001_80xx_dispatch,},
dbf9bfe6 57};
58static int pm8001_id;
59
60LIST_HEAD(hba_list);
61
429305e4
TH		 62struct workqueue_struct *pm8001_wq;
63
dbf9bfe6 64/**
65 * The main structure which LLDD must register for scsi core.
66 */
67static struct scsi_host_template pm8001_sht = {
68 .module = THIS_MODULE,
69 .name = DRV_NAME,
70 .queuecommand = sas_queuecommand,
71 .target_alloc = sas_target_alloc,
11e16364 72 .slave_configure = sas_slave_configure,
dbf9bfe6 73 .scan_finished = pm8001_scan_finished,
74 .scan_start = pm8001_scan_start,
75 .change_queue_depth = sas_change_queue_depth,
76 .change_queue_type = sas_change_queue_type,
77 .bios_param = sas_bios_param,
78 .can_queue = 1,
79 .cmd_per_lun = 1,
80 .this_id = -1,
81 .sg_tablesize = SG_ALL,
82 .max_sectors = SCSI_DEFAULT_MAX_SECTORS,
83 .use_clustering = ENABLE_CLUSTERING,
84 .eh_device_reset_handler = sas_eh_device_reset_handler,
85 .eh_bus_reset_handler = sas_eh_bus_reset_handler,
dbf9bfe6 86 .target_destroy = sas_target_destroy,
87 .ioctl = sas_ioctl,
88 .shost_attrs = pm8001_host_attrs,
89};
90
91/**
92 * Sas layer call this function to execute specific task.
93 */
94static struct sas_domain_function_template pm8001_transport_ops = {
95 .lldd_dev_found = pm8001_dev_found,
96 .lldd_dev_gone = pm8001_dev_gone,
97
98 .lldd_execute_task = pm8001_queue_command,
99 .lldd_control_phy = pm8001_phy_control,
100
101 .lldd_abort_task = pm8001_abort_task,
102 .lldd_abort_task_set = pm8001_abort_task_set,
103 .lldd_clear_aca = pm8001_clear_aca,
104 .lldd_clear_task_set = pm8001_clear_task_set,
105 .lldd_I_T_nexus_reset = pm8001_I_T_nexus_reset,
106 .lldd_lu_reset = pm8001_lu_reset,
107 .lldd_query_task = pm8001_query_task,
108};
109
110/**
111 *pm8001_phy_init - initiate our adapter phys
112 *@pm8001_ha: our hba structure.
113 *@phy_id: phy id.
114 */
6f039790 115static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id)
dbf9bfe6 116{
117 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
118 struct asd_sas_phy *sas_phy = &phy->sas_phy;
119 phy->phy_state = 0;
120 phy->pm8001_ha = pm8001_ha;
121 sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0;
122 sas_phy->class = SAS;
123 sas_phy->iproto = SAS_PROTOCOL_ALL;
124 sas_phy->tproto = 0;
125 sas_phy->type = PHY_TYPE_PHYSICAL;
126 sas_phy->role = PHY_ROLE_INITIATOR;
127 sas_phy->oob_mode = OOB_NOT_CONNECTED;
128 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
129 sas_phy->id = phy_id;
130 sas_phy->sas_addr = &pm8001_ha->sas_addr[0];
131 sas_phy->frame_rcvd = &phy->frame_rcvd[0];
132 sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata;
133 sas_phy->lldd_phy = phy;
134}
135
136/**
137 *pm8001_free - free hba
138 *@pm8001_ha: our hba structure.
139 *
140 */
141static void pm8001_free(struct pm8001_hba_info *pm8001_ha)
142{
143 int i;
dbf9bfe6 144
145 if (!pm8001_ha)
146 return;
147
148 for (i = 0; i < USI_MAX_MEMCNT; i++) {
149 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
150 pci_free_consistent(pm8001_ha->pdev,
bfb4809f
S		 151 (pm8001_ha->memoryMap.region[i].total_len +
152 pm8001_ha->memoryMap.region[i].alignment),
dbf9bfe6 153 pm8001_ha->memoryMap.region[i].virt_ptr,
154 pm8001_ha->memoryMap.region[i].phys_addr);
155 }
156 }
157 PM8001_CHIP_DISP->chip_iounmap(pm8001_ha);
158 if (pm8001_ha->shost)
159 scsi_host_put(pm8001_ha->shost);
429305e4 160 flush_workqueue(pm8001_wq);
dbf9bfe6 161 kfree(pm8001_ha->tags);
162 kfree(pm8001_ha);
163}
164
165#ifdef PM8001_USE_TASKLET
1245ee59
S		 166
167/**
168 * tasklet for 64 msi-x interrupt handler
169 * @opaque: the passed general host adapter struct
170 * Note: pm8001_tasklet is common for pm8001 & pm80xx
171 */
dbf9bfe6 172static void pm8001_tasklet(unsigned long opaque)
173{
174 struct pm8001_hba_info *pm8001_ha;
1245ee59 175 u32 vec;
6eab04a8 176 pm8001_ha = (struct pm8001_hba_info *)opaque;
dbf9bfe6 177 if (unlikely(!pm8001_ha))
178 BUG_ON(1);
1245ee59
S		 179 vec = pm8001_ha->int_vector;
180 PM8001_CHIP_DISP->isr(pm8001_ha, vec);
181}
182#endif
183
184static struct pm8001_hba_info *outq_to_hba(u8 *outq)
185{
186 return container_of((outq - *outq), struct pm8001_hba_info, outq[0]);
dbf9bfe6 187}
1245ee59
S		 188
189/**
190 * pm8001_interrupt_handler_msix - main MSIX interrupt handler.
191 * It obtains the vector number and calls the equivalent bottom
192 * half or services directly.
193 * @opaque: the passed outbound queue/vector. Host structure is
194 * retrieved from the same.
195 */
196static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque)
197{
198 struct pm8001_hba_info *pm8001_ha = outq_to_hba(opaque);
199 u8 outq = *(u8 *)opaque;
200 irqreturn_t ret = IRQ_HANDLED;
201 if (unlikely(!pm8001_ha))
202 return IRQ_NONE;
203 if (!PM8001_CHIP_DISP->is_our_interupt(pm8001_ha))
204 return IRQ_NONE;
205 pm8001_ha->int_vector = outq;
206#ifdef PM8001_USE_TASKLET
207 tasklet_schedule(&pm8001_ha->tasklet);
208#else
209 ret = PM8001_CHIP_DISP->isr(pm8001_ha, outq);
dbf9bfe6 210#endif
1245ee59
S		 211 return ret;
212}
dbf9bfe6 213
1245ee59
S		 214/**
215 * pm8001_interrupt_handler_intx - main INTx interrupt handler.
216 * @dev_id: sas_ha structure. The HBA is retrieved from sas_has structure.
217 */
dbf9bfe6 218
1245ee59 219static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id)
dbf9bfe6 220{
221 struct pm8001_hba_info *pm8001_ha;
222 irqreturn_t ret = IRQ_HANDLED;
1245ee59 223 struct sas_ha_struct *sha = dev_id;
dbf9bfe6 224 pm8001_ha = sha->lldd_ha;
225 if (unlikely(!pm8001_ha))
226 return IRQ_NONE;
227 if (!PM8001_CHIP_DISP->is_our_interupt(pm8001_ha))
228 return IRQ_NONE;
1245ee59
S		 229
230 pm8001_ha->int_vector = 0;
dbf9bfe6 231#ifdef PM8001_USE_TASKLET
232 tasklet_schedule(&pm8001_ha->tasklet);
233#else
f74cf271 234 ret = PM8001_CHIP_DISP->isr(pm8001_ha, 0);
dbf9bfe6 235#endif
236 return ret;
237}
238
239/**
240 * pm8001_alloc - initiate our hba structure and 6 DMAs area.
241 * @pm8001_ha:our hba structure.
242 *
243 */
e590adfd
S		 244static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha,
245 const struct pci_device_id *ent)
dbf9bfe6 246{
247 int i;
248 spin_lock_init(&pm8001_ha->lock);
e590adfd
S		 249 PM8001_INIT_DBG(pm8001_ha,
250 pm8001_printk("pm8001_alloc: PHY:%x\n",
251 pm8001_ha->chip->n_phy));
1cc943ae 252 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
dbf9bfe6 253 pm8001_phy_init(pm8001_ha, i);
1cc943ae 254 pm8001_ha->port[i].wide_port_phymap = 0;
255 pm8001_ha->port[i].port_attached = 0;
256 pm8001_ha->port[i].port_state = 0;
257 INIT_LIST_HEAD(&pm8001_ha->port[i].list);
258 }
dbf9bfe6 259
97ee2088 260 pm8001_ha->tags = kzalloc(PM8001_MAX_CCB, GFP_KERNEL);
261 if (!pm8001_ha->tags)
262 goto err_out;
dbf9bfe6 263 /* MPI Memory region 1 for AAP Event Log for fw */
264 pm8001_ha->memoryMap.region[AAP1].num_elements = 1;
265 pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE;
266 pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE;
267 pm8001_ha->memoryMap.region[AAP1].alignment = 32;
268
269 /* MPI Memory region 2 for IOP Event Log for fw */
270 pm8001_ha->memoryMap.region[IOP].num_elements = 1;
271 pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE;
272 pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE;
273 pm8001_ha->memoryMap.region[IOP].alignment = 32;
274
e590adfd
S		 275 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
276 /* MPI Memory region 3 for consumer Index of inbound queues */
277 pm8001_ha->memoryMap.region[CI+i].num_elements = 1;
278 pm8001_ha->memoryMap.region[CI+i].element_size = 4;
279 pm8001_ha->memoryMap.region[CI+i].total_len = 4;
280 pm8001_ha->memoryMap.region[CI+i].alignment = 4;
281
282 if ((ent->driver_data) != chip_8001) {
283 /* MPI Memory region 5 inbound queues */
284 pm8001_ha->memoryMap.region[IB+i].num_elements =
285 PM8001_MPI_QUEUE;
286 pm8001_ha->memoryMap.region[IB+i].element_size = 128;
287 pm8001_ha->memoryMap.region[IB+i].total_len =
288 PM8001_MPI_QUEUE * 128;
289 pm8001_ha->memoryMap.region[IB+i].alignment = 128;
290 } else {
291 pm8001_ha->memoryMap.region[IB+i].num_elements =
292 PM8001_MPI_QUEUE;
293 pm8001_ha->memoryMap.region[IB+i].element_size = 64;
294 pm8001_ha->memoryMap.region[IB+i].total_len =
295 PM8001_MPI_QUEUE * 64;
296 pm8001_ha->memoryMap.region[IB+i].alignment = 64;
297 }
298 }
299
300 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
301 /* MPI Memory region 4 for producer Index of outbound queues */
302 pm8001_ha->memoryMap.region[PI+i].num_elements = 1;
303 pm8001_ha->memoryMap.region[PI+i].element_size = 4;
304 pm8001_ha->memoryMap.region[PI+i].total_len = 4;
305 pm8001_ha->memoryMap.region[PI+i].alignment = 4;
306
307 if (ent->driver_data != chip_8001) {
308 /* MPI Memory region 6 Outbound queues */
309 pm8001_ha->memoryMap.region[OB+i].num_elements =
310 PM8001_MPI_QUEUE;
311 pm8001_ha->memoryMap.region[OB+i].element_size = 128;
312 pm8001_ha->memoryMap.region[OB+i].total_len =
313 PM8001_MPI_QUEUE * 128;
314 pm8001_ha->memoryMap.region[OB+i].alignment = 128;
315 } else {
316 /* MPI Memory region 6 Outbound queues */
317 pm8001_ha->memoryMap.region[OB+i].num_elements =
318 PM8001_MPI_QUEUE;
319 pm8001_ha->memoryMap.region[OB+i].element_size = 64;
320 pm8001_ha->memoryMap.region[OB+i].total_len =
321 PM8001_MPI_QUEUE * 64;
322 pm8001_ha->memoryMap.region[OB+i].alignment = 64;
323 }
dbf9bfe6 324
e590adfd 325 }
dbf9bfe6 326 /* Memory region write DMA*/
327 pm8001_ha->memoryMap.region[NVMD].num_elements = 1;
328 pm8001_ha->memoryMap.region[NVMD].element_size = 4096;
329 pm8001_ha->memoryMap.region[NVMD].total_len = 4096;
330 /* Memory region for devices*/
331 pm8001_ha->memoryMap.region[DEV_MEM].num_elements = 1;
332 pm8001_ha->memoryMap.region[DEV_MEM].element_size = PM8001_MAX_DEVICES *
333 sizeof(struct pm8001_device);
334 pm8001_ha->memoryMap.region[DEV_MEM].total_len = PM8001_MAX_DEVICES *
335 sizeof(struct pm8001_device);
336
337 /* Memory region for ccb_info*/
338 pm8001_ha->memoryMap.region[CCB_MEM].num_elements = 1;
339 pm8001_ha->memoryMap.region[CCB_MEM].element_size = PM8001_MAX_CCB *
340 sizeof(struct pm8001_ccb_info);
341 pm8001_ha->memoryMap.region[CCB_MEM].total_len = PM8001_MAX_CCB *
342 sizeof(struct pm8001_ccb_info);
343
1c75a679
S		 344 /* Memory region for fw flash */
345 pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096;
346
dbf9bfe6 347 for (i = 0; i < USI_MAX_MEMCNT; i++) {
348 if (pm8001_mem_alloc(pm8001_ha->pdev,
349 &pm8001_ha->memoryMap.region[i].virt_ptr,
350 &pm8001_ha->memoryMap.region[i].phys_addr,
351 &pm8001_ha->memoryMap.region[i].phys_addr_hi,
352 &pm8001_ha->memoryMap.region[i].phys_addr_lo,
353 pm8001_ha->memoryMap.region[i].total_len,
354 pm8001_ha->memoryMap.region[i].alignment) != 0) {
355 PM8001_FAIL_DBG(pm8001_ha,
356 pm8001_printk("Mem%d alloc failed\n",
357 i));
358 goto err_out;
359 }
360 }
361
362 pm8001_ha->devices = pm8001_ha->memoryMap.region[DEV_MEM].virt_ptr;
363 for (i = 0; i < PM8001_MAX_DEVICES; i++) {
364 pm8001_ha->devices[i].dev_type = NO_DEVICE;
365 pm8001_ha->devices[i].id = i;
366 pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES;
367 pm8001_ha->devices[i].running_req = 0;
368 }
369 pm8001_ha->ccb_info = pm8001_ha->memoryMap.region[CCB_MEM].virt_ptr;
370 for (i = 0; i < PM8001_MAX_CCB; i++) {
371 pm8001_ha->ccb_info[i].ccb_dma_handle =
372 pm8001_ha->memoryMap.region[CCB_MEM].phys_addr +
373 i * sizeof(struct pm8001_ccb_info);
97ee2088 374 pm8001_ha->ccb_info[i].task = NULL;
375 pm8001_ha->ccb_info[i].ccb_tag = 0xffffffff;
376 pm8001_ha->ccb_info[i].device = NULL;
dbf9bfe6 377 ++pm8001_ha->tags_num;
378 }
379 pm8001_ha->flags = PM8001F_INIT_TIME;
380 /* Initialize tags */
381 pm8001_tag_init(pm8001_ha);
382 return 0;
383err_out:
384 return 1;
385}
386
387/**
388 * pm8001_ioremap - remap the pci high physical address to kernal virtual
389 * address so that we can access them.
390 * @pm8001_ha:our hba structure.
391 */
392static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha)
393{
394 u32 bar;
395 u32 logicalBar = 0;
396 struct pci_dev *pdev;
397
398 pdev = pm8001_ha->pdev;
399 /* map pci mem (PMC pci base 0-3)*/
400 for (bar = 0; bar < 6; bar++) {
401 /*
402 ** logical BARs for SPC:
403 ** bar 0 and 1 - logical BAR0
404 ** bar 2 and 3 - logical BAR1
405 ** bar4 - logical BAR2
406 ** bar5 - logical BAR3
407 ** Skip the appropriate assignments:
408 */
409 if ((bar == 1) || (bar == 3))
410 continue;
411 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
412 pm8001_ha->io_mem[logicalBar].membase =
413 pci_resource_start(pdev, bar);
414 pm8001_ha->io_mem[logicalBar].membase &=
415 (u32)PCI_BASE_ADDRESS_MEM_MASK;
416 pm8001_ha->io_mem[logicalBar].memsize =
417 pci_resource_len(pdev, bar);
418 pm8001_ha->io_mem[logicalBar].memvirtaddr =
419 ioremap(pm8001_ha->io_mem[logicalBar].membase,
420 pm8001_ha->io_mem[logicalBar].memsize);
421 PM8001_INIT_DBG(pm8001_ha,
e590adfd
S		 422 pm8001_printk("PCI: bar %d, logicalBar %d ",
423 bar, logicalBar));
424 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
425 "base addr %llx virt_addr=%llx len=%d\n",
426 (u64)pm8001_ha->io_mem[logicalBar].membase,
427 (u64)pm8001_ha->io_mem[logicalBar].memvirtaddr,
dbf9bfe6 428 pm8001_ha->io_mem[logicalBar].memsize));
429 } else {
430 pm8001_ha->io_mem[logicalBar].membase = 0;
431 pm8001_ha->io_mem[logicalBar].memsize = 0;
432 pm8001_ha->io_mem[logicalBar].memvirtaddr = 0;
433 }
434 logicalBar++;
435 }
436 return 0;
437}
438
439/**
440 * pm8001_pci_alloc - initialize our ha card structure
441 * @pdev: pci device.
442 * @ent: ent
443 * @shost: scsi host struct which has been initialized before.
444 */
6f039790 445static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev,
e590adfd
S		 446 const struct pci_device_id *ent,
447 struct Scsi_Host *shost)
448
dbf9bfe6 449{
450 struct pm8001_hba_info *pm8001_ha;
451 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
452
453
454 pm8001_ha = sha->lldd_ha;
455 if (!pm8001_ha)
456 return NULL;
457
458 pm8001_ha->pdev = pdev;
459 pm8001_ha->dev = &pdev->dev;
e590adfd 460 pm8001_ha->chip_id = ent->driver_data;
dbf9bfe6 461 pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id];
462 pm8001_ha->irq = pdev->irq;
463 pm8001_ha->sas = sha;
464 pm8001_ha->shost = shost;
465 pm8001_ha->id = pm8001_id++;
dbf9bfe6 466 pm8001_ha->logging_level = 0x01;
467 sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id);
f74cf271
S		 468 /* IOMB size is 128 for 8088/89 controllers */
469 if (pm8001_ha->chip_id != chip_8001)
470 pm8001_ha->iomb_size = IOMB_SIZE_SPCV;
471 else
472 pm8001_ha->iomb_size = IOMB_SIZE_SPC;
473
dbf9bfe6 474#ifdef PM8001_USE_TASKLET
1245ee59
S		 475 /**
476 * default tasklet for non msi-x interrupt handler/first msi-x
477 * interrupt handler
478 **/
dbf9bfe6 479 tasklet_init(&pm8001_ha->tasklet, pm8001_tasklet,
1245ee59 480 (unsigned long)pm8001_ha);
dbf9bfe6 481#endif
482 pm8001_ioremap(pm8001_ha);
e590adfd 483 if (!pm8001_alloc(pm8001_ha, ent))
dbf9bfe6 484 return pm8001_ha;
485 pm8001_free(pm8001_ha);
486 return NULL;
487}
488
489/**
490 * pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit
491 * @pdev: pci device.
492 */
493static int pci_go_44(struct pci_dev *pdev)
494{
495 int rc;
496
497 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(44))) {
498 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(44));
499 if (rc) {
500 rc = pci_set_consistent_dma_mask(pdev,
501 DMA_BIT_MASK(32));
502 if (rc) {
503 dev_printk(KERN_ERR, &pdev->dev,
504 "44-bit DMA enable failed\n");
505 return rc;
506 }
507 }
508 } else {
509 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
510 if (rc) {
511 dev_printk(KERN_ERR, &pdev->dev,
512 "32-bit DMA enable failed\n");
513 return rc;
514 }
515 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
516 if (rc) {
517 dev_printk(KERN_ERR, &pdev->dev,
518 "32-bit consistent DMA enable failed\n");
519 return rc;
520 }
521 }
522 return rc;
523}
524
525/**
526 * pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them.
527 * @shost: scsi host which has been allocated outside.
528 * @chip_info: our ha struct.
529 */
6f039790
GKH		 530static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost,
531 const struct pm8001_chip_info *chip_info)
dbf9bfe6 532{
533 int phy_nr, port_nr;
534 struct asd_sas_phy **arr_phy;
535 struct asd_sas_port **arr_port;
536 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
537
538 phy_nr = chip_info->n_phy;
539 port_nr = phy_nr;
540 memset(sha, 0x00, sizeof(*sha));
541 arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
542 if (!arr_phy)
543 goto exit;
544 arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
545 if (!arr_port)
546 goto exit_free2;
547
548 sha->sas_phy = arr_phy;
549 sha->sas_port = arr_port;
550 sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL);
551 if (!sha->lldd_ha)
552 goto exit_free1;
553
554 shost->transportt = pm8001_stt;
555 shost->max_id = PM8001_MAX_DEVICES;
556 shost->max_lun = 8;
557 shost->max_channel = 0;
558 shost->unique_id = pm8001_id;
559 shost->max_cmd_len = 16;
560 shost->can_queue = PM8001_CAN_QUEUE;
561 shost->cmd_per_lun = 32;
562 return 0;
563exit_free1:
564 kfree(arr_port);
565exit_free2:
566 kfree(arr_phy);
567exit:
568 return -1;
569}
570
571/**
572 * pm8001_post_sas_ha_init - initialize general hba struct defined in libsas
573 * @shost: scsi host which has been allocated outside
574 * @chip_info: our ha struct.
575 */
6f039790
GKH		 576static void pm8001_post_sas_ha_init(struct Scsi_Host *shost,
577 const struct pm8001_chip_info *chip_info)
dbf9bfe6 578{
579 int i = 0;
580 struct pm8001_hba_info *pm8001_ha;
581 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
582
583 pm8001_ha = sha->lldd_ha;
584 for (i = 0; i < chip_info->n_phy; i++) {
585 sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy;
586 sha->sas_port[i] = &pm8001_ha->port[i].sas_port;
587 }
588 sha->sas_ha_name = DRV_NAME;
589 sha->dev = pm8001_ha->dev;
590
591 sha->lldd_module = THIS_MODULE;
592 sha->sas_addr = &pm8001_ha->sas_addr[0];
593 sha->num_phys = chip_info->n_phy;
594 sha->lldd_max_execute_num = 1;
595 sha->lldd_queue_size = PM8001_CAN_QUEUE;
596 sha->core.shost = shost;
597}
598
599/**
600 * pm8001_init_sas_add - initialize sas address
601 * @chip_info: our ha struct.
602 *
603 * Currently we just set the fixed SAS address to our HBA,for manufacture,
604 * it should read from the EEPROM
605 */
606static void pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha)
607{
a33a0155 608 u8 i, j;
dbf9bfe6 609#ifdef PM8001_READ_VPD
a33a0155
S		 610 /* For new SPC controllers WWN is stored in flash vpd
611 * For SPC/SPCve controllers WWN is stored in EEPROM
612 * For Older SPC WWN is stored in NVMD
613 */
dbf9bfe6 614 DECLARE_COMPLETION_ONSTACK(completion);
7c8356d9 615 struct pm8001_ioctl_payload payload;
a33a0155
S		 616 u16 deviceid;
617 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
dbf9bfe6 618 pm8001_ha->nvmd_completion = &completion;
a33a0155
S		 619
620 if (pm8001_ha->chip_id == chip_8001) {
621 if (deviceid == 0x8081) {
622 payload.minor_function = 4;
623 payload.length = 4096;
624 } else {
625 payload.minor_function = 0;
626 payload.length = 128;
627 }
628 } else {
629 payload.minor_function = 1;
630 payload.length = 4096;
631 }
632 payload.offset = 0;
633 payload.func_specific = kzalloc(payload.length, GFP_KERNEL);
7c8356d9 634 PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
dbf9bfe6 635 wait_for_completion(&completion);
a33a0155
S		 636
637 for (i = 0, j = 0; i <= 7; i++, j++) {
638 if (pm8001_ha->chip_id == chip_8001) {
639 if (deviceid == 0x8081)
640 pm8001_ha->sas_addr[j] =
641 payload.func_specific[0x704 + i];
642 } else
643 pm8001_ha->sas_addr[j] =
644 payload.func_specific[0x804 + i];
645 }
646
dbf9bfe6 647 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
a33a0155
S		 648 memcpy(&pm8001_ha->phy[i].dev_sas_addr,
649 pm8001_ha->sas_addr, SAS_ADDR_SIZE);
dbf9bfe6 650 PM8001_INIT_DBG(pm8001_ha,
a33a0155 651 pm8001_printk("phy %d sas_addr = %016llx\n", i,
7c8356d9 652 pm8001_ha->phy[i].dev_sas_addr));
dbf9bfe6 653 }
654#else
655 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
7c8356d9 656 pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL;
dbf9bfe6 657 pm8001_ha->phy[i].dev_sas_addr =
658 cpu_to_be64((u64)
659 (*(u64 *)&pm8001_ha->phy[i].dev_sas_addr));
660 }
661 memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr,
662 SAS_ADDR_SIZE);
663#endif
664}
665
666#ifdef PM8001_USE_MSIX
667/**
668 * pm8001_setup_msix - enable MSI-X interrupt
669 * @chip_info: our ha struct.
670 * @irq_handler: irq_handler
671 */
1245ee59 672static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha)
dbf9bfe6 673{
674 u32 i = 0, j = 0;
1245ee59 675 u32 number_of_intr;
dbf9bfe6 676 int flag = 0;
677 u32 max_entry;
678 int rc;
1245ee59
S		 679 static char intr_drvname[PM8001_MAX_MSIX_VEC][sizeof(DRV_NAME)+3];
680
681 /* SPCv controllers supports 64 msi-x */
682 if (pm8001_ha->chip_id == chip_8001) {
683 number_of_intr = 1;
684 flag |= IRQF_DISABLED;
685 } else {
686 number_of_intr = PM8001_MAX_MSIX_VEC;
687 flag &= ~IRQF_SHARED;
688 flag |= IRQF_DISABLED;
689 }
690
dbf9bfe6 691 max_entry = sizeof(pm8001_ha->msix_entries) /
692 sizeof(pm8001_ha->msix_entries[0]);
dbf9bfe6 693 for (i = 0; i < max_entry ; i++)
694 pm8001_ha->msix_entries[i].entry = i;
695 rc = pci_enable_msix(pm8001_ha->pdev, pm8001_ha->msix_entries,
696 number_of_intr);
697 pm8001_ha->number_of_intr = number_of_intr;
698 if (!rc) {
1245ee59
S		 699 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
700 "pci_enable_msix request ret:%d no of intr %d\n",
701 rc, pm8001_ha->number_of_intr));
702
703 for (i = 0; i < number_of_intr; i++)
704 pm8001_ha->outq[i] = i;
705
dbf9bfe6 706 for (i = 0; i < number_of_intr; i++) {
1245ee59
S		 707 snprintf(intr_drvname[i], sizeof(intr_drvname[0]),
708 DRV_NAME"%d", i);
dbf9bfe6 709 if (request_irq(pm8001_ha->msix_entries[i].vector,
1245ee59
S		 710 pm8001_interrupt_handler_msix, flag,
711 intr_drvname[i], &pm8001_ha->outq[i])) {
dbf9bfe6 712 for (j = 0; j < i; j++)
713 free_irq(
714 pm8001_ha->msix_entries[j].vector,
1245ee59 715 &pm8001_ha->outq[j]);
dbf9bfe6 716 pci_disable_msix(pm8001_ha->pdev);
717 break;
718 }
719 }
720 }
721 return rc;
722}
723#endif
724
725/**
726 * pm8001_request_irq - register interrupt
727 * @chip_info: our ha struct.
728 */
729static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha)
730{
731 struct pci_dev *pdev;
97ee2088 732 int rc;
dbf9bfe6 733
734 pdev = pm8001_ha->pdev;
735
736#ifdef PM8001_USE_MSIX
737 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
1245ee59
S		 738 return pm8001_setup_msix(pm8001_ha);
739 else {
740 PM8001_INIT_DBG(pm8001_ha,
741 pm8001_printk("MSIX not supported!!!\n"));
dbf9bfe6 742 goto intx;
1245ee59 743 }
dbf9bfe6 744#endif
745
746intx:
b595076a 747 /* initialize the INT-X interrupt */
1245ee59
S		 748 rc = request_irq(pdev->irq, pm8001_interrupt_handler_intx, IRQF_SHARED,
749 DRV_NAME, SHOST_TO_SAS_HA(pm8001_ha->shost));
dbf9bfe6 750 return rc;
751}
752
753/**
754 * pm8001_pci_probe - probe supported device
755 * @pdev: pci device which kernel has been prepared for.
756 * @ent: pci device id
757 *
758 * This function is the main initialization function, when register a new
759 * pci driver it is invoked, all struct an hardware initilization should be done
760 * here, also, register interrupt
761 */
6f039790
GKH		 762static int pm8001_pci_probe(struct pci_dev *pdev,
763 const struct pci_device_id *ent)
dbf9bfe6 764{
765 unsigned int rc;
766 u32 pci_reg;
1245ee59 767 u8 i = 0;
dbf9bfe6 768 struct pm8001_hba_info *pm8001_ha;
769 struct Scsi_Host *shost = NULL;
770 const struct pm8001_chip_info *chip;
771
772 dev_printk(KERN_INFO, &pdev->dev,
a70b8fc3 773 "pm80xx: driver version %s\n", DRV_VERSION);
dbf9bfe6 774 rc = pci_enable_device(pdev);
775 if (rc)
776 goto err_out_enable;
777 pci_set_master(pdev);
778 /*
779 * Enable pci slot busmaster by setting pci command register.
780 * This is required by FW for Cyclone card.
781 */
782
783 pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg);
784 pci_reg |= 0x157;
785 pci_write_config_dword(pdev, PCI_COMMAND, pci_reg);
786 rc = pci_request_regions(pdev, DRV_NAME);
787 if (rc)
788 goto err_out_disable;
789 rc = pci_go_44(pdev);
790 if (rc)
791 goto err_out_regions;
792
793 shost = scsi_host_alloc(&pm8001_sht, sizeof(void *));
794 if (!shost) {
795 rc = -ENOMEM;
796 goto err_out_regions;
797 }
798 chip = &pm8001_chips[ent->driver_data];
799 SHOST_TO_SAS_HA(shost) =
3dbf6c00 800 kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL);
dbf9bfe6 801 if (!SHOST_TO_SAS_HA(shost)) {
802 rc = -ENOMEM;
803 goto err_out_free_host;
804 }
805
806 rc = pm8001_prep_sas_ha_init(shost, chip);
807 if (rc) {
808 rc = -ENOMEM;
809 goto err_out_free;
810 }
811 pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
e590adfd
S		 812 /* ent->driver variable is used to differentiate between controllers */
813 pm8001_ha = pm8001_pci_alloc(pdev, ent, shost);
dbf9bfe6 814 if (!pm8001_ha) {
815 rc = -ENOMEM;
816 goto err_out_free;
817 }
818 list_add_tail(&pm8001_ha->list, &hba_list);
f5860992 819 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
dbf9bfe6 820 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
a70b8fc3
S		 821 if (rc) {
822 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
823 "chip_init failed [ret: %d]\n", rc));
dbf9bfe6 824 goto err_out_ha_free;
a70b8fc3 825 }
dbf9bfe6 826
827 rc = scsi_add_host(shost, &pdev->dev);
828 if (rc)
829 goto err_out_ha_free;
830 rc = pm8001_request_irq(pm8001_ha);
a70b8fc3
S		 831 if (rc) {
832 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
833 "pm8001_request_irq failed [ret: %d]\n", rc));
dbf9bfe6 834 goto err_out_shost;
a70b8fc3 835 }
dbf9bfe6 836
f74cf271 837 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1245ee59
S		 838 if (pm8001_ha->chip_id != chip_8001) {
839 for (i = 1; i < pm8001_ha->number_of_intr; i++)
840 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
841 }
842
dbf9bfe6 843 pm8001_init_sas_add(pm8001_ha);
844 pm8001_post_sas_ha_init(shost, chip);
845 rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
846 if (rc)
847 goto err_out_shost;
848 scsi_scan_host(pm8001_ha->shost);
849 return 0;
850
851err_out_shost:
852 scsi_remove_host(pm8001_ha->shost);
853err_out_ha_free:
854 pm8001_free(pm8001_ha);
855err_out_free:
856 kfree(SHOST_TO_SAS_HA(shost));
857err_out_free_host:
858 kfree(shost);
859err_out_regions:
860 pci_release_regions(pdev);
861err_out_disable:
862 pci_disable_device(pdev);
863err_out_enable:
864 return rc;
865}
866
6f039790 867static void pm8001_pci_remove(struct pci_dev *pdev)
dbf9bfe6 868{
869 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
870 struct pm8001_hba_info *pm8001_ha;
871 int i;
872 pm8001_ha = sha->lldd_ha;
873 pci_set_drvdata(pdev, NULL);
874 sas_unregister_ha(sha);
875 sas_remove_host(pm8001_ha->shost);
876 list_del(&pm8001_ha->list);
877 scsi_remove_host(pm8001_ha->shost);
1245ee59 878 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
f5860992 879 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
dbf9bfe6 880
881#ifdef PM8001_USE_MSIX
882 for (i = 0; i < pm8001_ha->number_of_intr; i++)
883 synchronize_irq(pm8001_ha->msix_entries[i].vector);
884 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1245ee59
S		 885 free_irq(pm8001_ha->msix_entries[i].vector,
886 &pm8001_ha->outq[i]);
dbf9bfe6 887 pci_disable_msix(pdev);
888#else
889 free_irq(pm8001_ha->irq, sha);
890#endif
891#ifdef PM8001_USE_TASKLET
892 tasklet_kill(&pm8001_ha->tasklet);
893#endif
894 pm8001_free(pm8001_ha);
895 kfree(sha->sas_phy);
896 kfree(sha->sas_port);
897 kfree(sha);
898 pci_release_regions(pdev);
899 pci_disable_device(pdev);
900}
901
902/**
903 * pm8001_pci_suspend - power management suspend main entry point
904 * @pdev: PCI device struct
905 * @state: PM state change to (usually PCI_D3)
906 *
907 * Returns 0 success, anything else error.
908 */
909static int pm8001_pci_suspend(struct pci_dev *pdev, pm_message_t state)
910{
911 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
912 struct pm8001_hba_info *pm8001_ha;
913 int i , pos;
914 u32 device_state;
915 pm8001_ha = sha->lldd_ha;
429305e4 916 flush_workqueue(pm8001_wq);
dbf9bfe6 917 scsi_block_requests(pm8001_ha->shost);
918 pos = pci_find_capability(pdev, PCI_CAP_ID_PM);
919 if (pos == 0) {
920 printk(KERN_ERR " PCI PM not supported\n");
921 return -ENODEV;
922 }
1245ee59 923 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
f5860992 924 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
dbf9bfe6 925#ifdef PM8001_USE_MSIX
926 for (i = 0; i < pm8001_ha->number_of_intr; i++)
927 synchronize_irq(pm8001_ha->msix_entries[i].vector);
928 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1245ee59
S		 929 free_irq(pm8001_ha->msix_entries[i].vector,
930 &pm8001_ha->outq[i]);
dbf9bfe6 931 pci_disable_msix(pdev);
932#else
933 free_irq(pm8001_ha->irq, sha);
934#endif
935#ifdef PM8001_USE_TASKLET
936 tasklet_kill(&pm8001_ha->tasklet);
937#endif
938 device_state = pci_choose_state(pdev, state);
939 pm8001_printk("pdev=0x%p, slot=%s, entering "
940 "operating state [D%d]\n", pdev,
941 pm8001_ha->name, device_state);
942 pci_save_state(pdev);
943 pci_disable_device(pdev);
944 pci_set_power_state(pdev, device_state);
945 return 0;
946}
947
948/**
949 * pm8001_pci_resume - power management resume main entry point
950 * @pdev: PCI device struct
951 *
952 * Returns 0 success, anything else error.
953 */
954static int pm8001_pci_resume(struct pci_dev *pdev)
955{
956 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
957 struct pm8001_hba_info *pm8001_ha;
958 int rc;
1245ee59 959 u8 i = 0;
dbf9bfe6 960 u32 device_state;
961 pm8001_ha = sha->lldd_ha;
962 device_state = pdev->current_state;
963
964 pm8001_printk("pdev=0x%p, slot=%s, resuming from previous "
965 "operating state [D%d]\n", pdev, pm8001_ha->name, device_state);
966
967 pci_set_power_state(pdev, PCI_D0);
968 pci_enable_wake(pdev, PCI_D0, 0);
969 pci_restore_state(pdev);
970 rc = pci_enable_device(pdev);
971 if (rc) {
972 pm8001_printk("slot=%s Enable device failed during resume\n",
973 pm8001_ha->name);
974 goto err_out_enable;
975 }
976
977 pci_set_master(pdev);
978 rc = pci_go_44(pdev);
979 if (rc)
980 goto err_out_disable;
981
f5860992
S		 982 /* chip soft rst only for spc */
983 if (pm8001_ha->chip_id == chip_8001) {
984 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
985 PM8001_INIT_DBG(pm8001_ha,
986 pm8001_printk("chip soft reset successful\n"));
987 }
dbf9bfe6 988 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
989 if (rc)
990 goto err_out_disable;
1245ee59
S		 991
992 /* disable all the interrupt bits */
993 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
994
dbf9bfe6 995 rc = pm8001_request_irq(pm8001_ha);
996 if (rc)
997 goto err_out_disable;
1245ee59
S		 998#ifdef PM8001_USE_TASKLET
999 /* default tasklet for non msi-x interrupt handler/first msi-x
1000 * interrupt handler */
dbf9bfe6 1001 tasklet_init(&pm8001_ha->tasklet, pm8001_tasklet,
1245ee59
S		 1002 (unsigned long)pm8001_ha);
1003#endif
f74cf271 1004 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1245ee59
S		 1005 if (pm8001_ha->chip_id != chip_8001) {
1006 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1007 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1008 }
dbf9bfe6 1009 scsi_unblock_requests(pm8001_ha->shost);
1010 return 0;
1011
1012err_out_disable:
1013 scsi_remove_host(pm8001_ha->shost);
1014 pci_disable_device(pdev);
1015err_out_enable:
1016 return rc;
1017}
1018
e5742101
S		 1019/* update of pci device, vendor id and driver data with
1020 * unique value for each of the controller
1021 */
6f039790 1022static struct pci_device_id pm8001_pci_table[] = {
e5742101 1023 { PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 },
dbf9bfe6 1024 {
1025 PCI_DEVICE(0x117c, 0x0042),
1026 .driver_data = chip_8001
1027 },
e5742101
S		 1028 /* Support for SPC/SPCv/SPCve controllers */
1029 { PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 },
1030 { PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 },
1031 { PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 },
1032 { PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 },
1033 { PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 },
1034 { PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 },
1035 { PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 },
1036 { PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 },
1037 { PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 },
1038 { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1039 PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 },
1040 { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1041 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 },
1042 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1043 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 },
1044 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1045 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 },
1046 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1047 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 },
1048 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1049 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 },
1050 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1051 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 },
1052 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1053 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 },
1054 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1055 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 },
1056 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1057 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 },
dbf9bfe6 1058 {} /* terminate list */
1059};
1060
1061static struct pci_driver pm8001_pci_driver = {
1062 .name = DRV_NAME,
1063 .id_table = pm8001_pci_table,
1064 .probe = pm8001_pci_probe,
6f039790 1065 .remove = pm8001_pci_remove,
dbf9bfe6 1066 .suspend = pm8001_pci_suspend,
1067 .resume = pm8001_pci_resume,
1068};
1069
1070/**
1071 * pm8001_init - initialize scsi transport template
1072 */
1073static int __init pm8001_init(void)
1074{
429305e4
TH		 1075 int rc = -ENOMEM;
1076
a70b8fc3 1077 pm8001_wq = alloc_workqueue("pm80xx", 0, 0);
429305e4
TH		 1078 if (!pm8001_wq)
1079 goto err;
1080
dbf9bfe6 1081 pm8001_id = 0;
1082 pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops);
1083 if (!pm8001_stt)
429305e4 1084 goto err_wq;
dbf9bfe6 1085 rc = pci_register_driver(&pm8001_pci_driver);
1086 if (rc)
429305e4 1087 goto err_tp;
dbf9bfe6 1088 return 0;
429305e4
TH		 1089
1090err_tp:
dbf9bfe6 1091 sas_release_transport(pm8001_stt);
429305e4
TH		 1092err_wq:
1093 destroy_workqueue(pm8001_wq);
1094err:
dbf9bfe6 1095 return rc;
1096}
1097
1098static void __exit pm8001_exit(void)
1099{
1100 pci_unregister_driver(&pm8001_pci_driver);
1101 sas_release_transport(pm8001_stt);
429305e4 1102 destroy_workqueue(pm8001_wq);
dbf9bfe6 1103}
1104
1105module_init(pm8001_init);
1106module_exit(pm8001_exit);
1107
1108MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>");
e5742101
S		 1109MODULE_DESCRIPTION(
1110 "PMC-Sierra PM8001/8081/8088/8089 SAS/SATA controller driver");
dbf9bfe6 1111MODULE_VERSION(DRV_VERSION);
1112MODULE_LICENSE("GPL");
1113MODULE_DEVICE_TABLE(pci, pm8001_pci_table);
1114
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