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scsi: pm80xx: Tie the interrupt name to the module instance
[mirror_ubuntu-jammy-kernel.git] / drivers / scsi / pm8001 / pm8001_sas.h
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dbf9bfe6 1/*
f5860992 2 * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver
dbf9bfe6 3 *
4 * Copyright (c) 2008-2009 USI Co., Ltd.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
25 *
26 * NO WARRANTY
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
38 *
39 */
40
41#ifndef _PM8001_SAS_H_
42#define _PM8001_SAS_H_
43
44#include <linux/kernel.h>
45#include <linux/module.h>
46#include <linux/spinlock.h>
47#include <linux/delay.h>
48#include <linux/types.h>
49#include <linux/ctype.h>
50#include <linux/dma-mapping.h>
51#include <linux/pci.h>
52#include <linux/interrupt.h>
429305e4 53#include <linux/workqueue.h>
dbf9bfe6 54#include <scsi/libsas.h>
55#include <scsi/scsi_tcq.h>
56#include <scsi/sas_ata.h>
60063497 57#include <linux/atomic.h>
dbf9bfe6 58#include "pm8001_defs.h"
59
a70b8fc3 60#define DRV_NAME "pm80xx"
b5dedc75 61#define DRV_VERSION "0.1.39"
83e73329 62#define PM8001_FAIL_LOGGING 0x01 /* Error message logging */
dbf9bfe6 63#define PM8001_INIT_LOGGING 0x02 /* driver init logging */
64#define PM8001_DISC_LOGGING 0x04 /* discovery layer logging */
65#define PM8001_IO_LOGGING 0x08 /* I/O path logging */
83e73329 66#define PM8001_EH_LOGGING 0x10 /* libsas EH function logging*/
dbf9bfe6 67#define PM8001_IOCTL_LOGGING 0x20 /* IOCTL message logging */
68#define PM8001_MSG_LOGGING 0x40 /* misc message logging */
7370672d 69#define PM8001_DEV_LOGGING 0x80 /* development message logging */
70#define PM8001_DEVIO_LOGGING 0x100 /* development io message logging */
71#define PM8001_IOERR_LOGGING 0x200 /* development io err message logging */
72#define pm8001_printk(format, arg...) pr_info("%s:: %s %d:" \
73 format, pm8001_ha->name, __func__, __LINE__, ## arg)
dbf9bfe6 74#define PM8001_CHECK_LOGGING(HBA, LEVEL, CMD) \
75do { \
76 if (unlikely(HBA->logging_level & LEVEL)) \
77 do { \
78 CMD; \
79 } while (0); \
80} while (0);
81
82#define PM8001_EH_DBG(HBA, CMD) \
83 PM8001_CHECK_LOGGING(HBA, PM8001_EH_LOGGING, CMD)
84
85#define PM8001_INIT_DBG(HBA, CMD) \
86 PM8001_CHECK_LOGGING(HBA, PM8001_INIT_LOGGING, CMD)
87
88#define PM8001_DISC_DBG(HBA, CMD) \
89 PM8001_CHECK_LOGGING(HBA, PM8001_DISC_LOGGING, CMD)
90
91#define PM8001_IO_DBG(HBA, CMD) \
92 PM8001_CHECK_LOGGING(HBA, PM8001_IO_LOGGING, CMD)
93
94#define PM8001_FAIL_DBG(HBA, CMD) \
95 PM8001_CHECK_LOGGING(HBA, PM8001_FAIL_LOGGING, CMD)
96
97#define PM8001_IOCTL_DBG(HBA, CMD) \
98 PM8001_CHECK_LOGGING(HBA, PM8001_IOCTL_LOGGING, CMD)
99
100#define PM8001_MSG_DBG(HBA, CMD) \
101 PM8001_CHECK_LOGGING(HBA, PM8001_MSG_LOGGING, CMD)
102
7370672d 103#define PM8001_DEV_DBG(HBA, CMD) \
104 PM8001_CHECK_LOGGING(HBA, PM8001_DEV_LOGGING, CMD)
105
106#define PM8001_DEVIO_DBG(HBA, CMD) \
107 PM8001_CHECK_LOGGING(HBA, PM8001_DEVIO_LOGGING, CMD)
108
109#define PM8001_IOERR_DBG(HBA, CMD) \
110 PM8001_CHECK_LOGGING(HBA, PM8001_IOERR_LOGGING, CMD)
dbf9bfe6 111
112#define PM8001_USE_TASKLET
113#define PM8001_USE_MSIX
7c8356d9 114#define PM8001_READ_VPD
dbf9bfe6 115
116
a9a923e5
AKS		 117#define IS_SPCV_12G(dev) ((dev->device == 0X8074) \
118 || (dev->device == 0X8076) \
db9d4034
BR		 119 || (dev->device == 0X8077) \
120 || (dev->device == 0X8070) \
121 || (dev->device == 0X8072))
dbf9bfe6 122
123#define PM8001_NAME_LENGTH 32/* generic length of strings */
124extern struct list_head hba_list;
125extern const struct pm8001_dispatch pm8001_8001_dispatch;
f5860992 126extern const struct pm8001_dispatch pm8001_80xx_dispatch;
dbf9bfe6 127
128struct pm8001_hba_info;
129struct pm8001_ccb_info;
130struct pm8001_device;
7c8356d9 131/* define task management IU */
132struct pm8001_tmf_task {
133 u8 tmf;
134 u32 tag_of_task_to_be_managed;
135};
136struct pm8001_ioctl_payload {
137 u32 signature;
138 u16 major_function;
139 u16 minor_function;
140 u16 length;
141 u16 status;
142 u16 offset;
143 u16 id;
144 u8 *func_specific;
145};
146
d078b511
AKS		 147#define MPI_FATAL_ERROR_TABLE_OFFSET_MASK 0xFFFFFF
148#define MPI_FATAL_ERROR_TABLE_SIZE(value) ((0xFF000000 & value) >> SHIFT24)
149#define MPI_FATAL_EDUMP_TABLE_LO_OFFSET 0x00 /* HNFBUFL */
150#define MPI_FATAL_EDUMP_TABLE_HI_OFFSET 0x04 /* HNFBUFH */
151#define MPI_FATAL_EDUMP_TABLE_LENGTH 0x08 /* HNFBLEN */
152#define MPI_FATAL_EDUMP_TABLE_HANDSHAKE 0x0C /* FDDHSHK */
153#define MPI_FATAL_EDUMP_TABLE_STATUS 0x10 /* FDDTSTAT */
154#define MPI_FATAL_EDUMP_TABLE_ACCUM_LEN 0x14 /* ACCDDLEN */
155#define MPI_FATAL_EDUMP_HANDSHAKE_RDY 0x1
156#define MPI_FATAL_EDUMP_HANDSHAKE_BUSY 0x0
157#define MPI_FATAL_EDUMP_TABLE_STAT_RSVD 0x0
158#define MPI_FATAL_EDUMP_TABLE_STAT_DMA_FAILED 0x1
159#define MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_MORE_DATA 0x2
160#define MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE 0x3
161#define TYPE_GSM_SPACE 1
162#define TYPE_QUEUE 2
163#define TYPE_FATAL 3
164#define TYPE_NON_FATAL 4
165#define TYPE_INBOUND 1
166#define TYPE_OUTBOUND 2
167struct forensic_data {
168 u32 data_type;
169 union {
170 struct {
171 u32 direct_len;
172 u32 direct_offset;
173 void *direct_data;
174 } gsm_buf;
175 struct {
176 u16 queue_type;
177 u16 queue_index;
178 u32 direct_len;
179 void *direct_data;
180 } queue_buf;
181 struct {
182 u32 direct_len;
183 u32 direct_offset;
184 u32 read_len;
185 void *direct_data;
186 } data_buf;
187 };
188};
189
190/* bit31-26 - mask bar */
191#define SCRATCH_PAD0_BAR_MASK 0xFC000000
192/* bit25-0 - offset mask */
193#define SCRATCH_PAD0_OFFSET_MASK 0x03FFFFFF
194/* if AAP error state */
195#define SCRATCH_PAD0_AAPERR_MASK 0xFFFFFFFF
196/* Inbound doorbell bit7 */
197#define SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP 0x80
198/* Inbound doorbell bit7 SPCV */
199#define SPCV_MSGU_CFG_TABLE_TRANSFER_DEBUG_INFO 0x80
200#define MAIN_MERRDCTO_MERRDCES 0xA0/* DWORD 0x28) */
201
dbf9bfe6 202struct pm8001_dispatch {
203 char *name;
204 int (*chip_init)(struct pm8001_hba_info *pm8001_ha);
f5860992 205 int (*chip_soft_rst)(struct pm8001_hba_info *pm8001_ha);
dbf9bfe6 206 void (*chip_rst)(struct pm8001_hba_info *pm8001_ha);
207 int (*chip_ioremap)(struct pm8001_hba_info *pm8001_ha);
208 void (*chip_iounmap)(struct pm8001_hba_info *pm8001_ha);
f74cf271 209 irqreturn_t (*isr)(struct pm8001_hba_info *pm8001_ha, u8 vec);
f310a4ea 210 u32 (*is_our_interrupt)(struct pm8001_hba_info *pm8001_ha);
f74cf271
S		 211 int (*isr_process_oq)(struct pm8001_hba_info *pm8001_ha, u8 vec);
212 void (*interrupt_enable)(struct pm8001_hba_info *pm8001_ha, u8 vec);
213 void (*interrupt_disable)(struct pm8001_hba_info *pm8001_ha, u8 vec);
dbf9bfe6 214 void (*make_prd)(struct scatterlist *scatter, int nr, void *prd);
215 int (*smp_req)(struct pm8001_hba_info *pm8001_ha,
216 struct pm8001_ccb_info *ccb);
217 int (*ssp_io_req)(struct pm8001_hba_info *pm8001_ha,
218 struct pm8001_ccb_info *ccb);
219 int (*sata_req)(struct pm8001_hba_info *pm8001_ha,
220 struct pm8001_ccb_info *ccb);
221 int (*phy_start_req)(struct pm8001_hba_info *pm8001_ha, u8 phy_id);
222 int (*phy_stop_req)(struct pm8001_hba_info *pm8001_ha, u8 phy_id);
223 int (*reg_dev_req)(struct pm8001_hba_info *pm8001_ha,
224 struct pm8001_device *pm8001_dev, u32 flag);
225 int (*dereg_dev_req)(struct pm8001_hba_info *pm8001_ha, u32 device_id);
226 int (*phy_ctl_req)(struct pm8001_hba_info *pm8001_ha,
227 u32 phy_id, u32 phy_op);
228 int (*task_abort)(struct pm8001_hba_info *pm8001_ha,
229 struct pm8001_device *pm8001_dev, u8 flag, u32 task_tag,
230 u32 cmd_tag);
231 int (*ssp_tm_req)(struct pm8001_hba_info *pm8001_ha,
232 struct pm8001_ccb_info *ccb, struct pm8001_tmf_task *tmf);
233 int (*get_nvmd_req)(struct pm8001_hba_info *pm8001_ha, void *payload);
234 int (*set_nvmd_req)(struct pm8001_hba_info *pm8001_ha, void *payload);
235 int (*fw_flash_update_req)(struct pm8001_hba_info *pm8001_ha,
236 void *payload);
237 int (*set_dev_state_req)(struct pm8001_hba_info *pm8001_ha,
238 struct pm8001_device *pm8001_dev, u32 state);
239 int (*sas_diag_start_end_req)(struct pm8001_hba_info *pm8001_ha,
240 u32 state);
241 int (*sas_diag_execute_req)(struct pm8001_hba_info *pm8001_ha,
242 u32 state);
d0b68041 243 int (*sas_re_init_req)(struct pm8001_hba_info *pm8001_ha);
dbf9bfe6 244};
245
246struct pm8001_chip_info {
e5742101 247 u32 encrypt;
dbf9bfe6 248 u32 n_phy;
249 const struct pm8001_dispatch *dispatch;
250};
251#define PM8001_CHIP_DISP (pm8001_ha->chip->dispatch)
252
253struct pm8001_port {
254 struct asd_sas_port sas_port;
1cc943ae 255 u8 port_attached;
8414cd80 256 u16 wide_port_phymap;
1cc943ae 257 u8 port_state;
258 struct list_head list;
dbf9bfe6 259};
260
261struct pm8001_phy {
262 struct pm8001_hba_info *pm8001_ha;
263 struct pm8001_port *port;
264 struct asd_sas_phy sas_phy;
265 struct sas_identify identify;
266 struct scsi_device *sdev;
267 u64 dev_sas_addr;
268 u32 phy_type;
269 struct completion *enable_completion;
270 u32 frame_rcvd_size;
271 u8 frame_rcvd[32];
272 u8 phy_attached;
273 u8 phy_state;
274 enum sas_linkrate minimum_linkrate;
275 enum sas_linkrate maximum_linkrate;
869ddbdc
V		 276 struct completion *reset_completion;
277 bool port_reset_status;
278 bool reset_success;
dbf9bfe6 279};
280
869ddbdc
V		 281/* port reset status */
282#define PORT_RESET_SUCCESS 0x00
283#define PORT_RESET_TMO 0x01
284
dbf9bfe6 285struct pm8001_device {
aa9f8328 286 enum sas_device_type dev_type;
dbf9bfe6 287 struct domain_device *sas_device;
288 u32 attached_phy;
289 u32 id;
290 struct completion *dcompletion;
291 struct completion *setds_completion;
292 u32 device_id;
293 u32 running_req;
294};
295
296struct pm8001_prd_imt {
297 __le32 len;
298 __le32 e;
299};
300
301struct pm8001_prd {
302 __le64 addr; /* 64-bit buffer address */
303 struct pm8001_prd_imt im_len; /* 64-bit length */
304} __attribute__ ((packed));
305/*
306 * CCB(Command Control Block)
307 */
308struct pm8001_ccb_info {
309 struct list_head entry;
310 struct sas_task *task;
311 u32 n_elem;
312 u32 ccb_tag;
313 dma_addr_t ccb_dma_handle;
314 struct pm8001_device *device;
315 struct pm8001_prd buf_prd[PM8001_MAX_DMA_SG];
316 struct fw_control_ex *fw_control_context;
5954d738 317 u8 open_retry;
dbf9bfe6 318};
319
320struct mpi_mem {
321 void *virt_ptr;
322 dma_addr_t phys_addr;
323 u32 phys_addr_hi;
324 u32 phys_addr_lo;
325 u32 total_len;
326 u32 num_elements;
327 u32 element_size;
328 u32 alignment;
329};
330
331struct mpi_mem_req {
332 /* The number of element in the mpiMemory array */
333 u32 count;
334 /* The array of structures that define memroy regions*/
335 struct mpi_mem region[USI_MAX_MEMCNT];
336};
337
e5742101
S		 338struct encrypt {
339 u32 cipher_mode;
340 u32 sec_mode;
341 u32 status;
342 u32 flag;
343};
344
345struct sas_phy_attribute_table {
346 u32 phystart1_16[16];
347 u32 outbound_hw_event_pid1_16[16];
348};
349
350union main_cfg_table {
351 struct {
dbf9bfe6 352 u32 signature;
353 u32 interface_rev;
354 u32 firmware_rev;
355 u32 max_out_io;
356 u32 max_sgl;
357 u32 ctrl_cap_flag;
358 u32 gst_offset;
359 u32 inbound_queue_offset;
360 u32 outbound_queue_offset;
361 u32 inbound_q_nppd_hppd;
362 u32 outbound_hw_event_pid0_3;
363 u32 outbound_hw_event_pid4_7;
364 u32 outbound_ncq_event_pid0_3;
365 u32 outbound_ncq_event_pid4_7;
366 u32 outbound_tgt_ITNexus_event_pid0_3;
367 u32 outbound_tgt_ITNexus_event_pid4_7;
368 u32 outbound_tgt_ssp_event_pid0_3;
369 u32 outbound_tgt_ssp_event_pid4_7;
370 u32 outbound_tgt_smp_event_pid0_3;
371 u32 outbound_tgt_smp_event_pid4_7;
372 u32 upper_event_log_addr;
373 u32 lower_event_log_addr;
374 u32 event_log_size;
375 u32 event_log_option;
376 u32 upper_iop_event_log_addr;
377 u32 lower_iop_event_log_addr;
378 u32 iop_event_log_size;
379 u32 iop_event_log_option;
380 u32 fatal_err_interrupt;
381 u32 fatal_err_dump_offset0;
382 u32 fatal_err_dump_length0;
383 u32 fatal_err_dump_offset1;
384 u32 fatal_err_dump_length1;
385 u32 hda_mode_flag;
386 u32 anolog_setup_table_offset;
e5742101
S		 387 u32 rsvd[4];
388 } pm8001_tbl;
389
390 struct {
391 u32 signature;
392 u32 interface_rev;
393 u32 firmware_rev;
394 u32 max_out_io;
395 u32 max_sgl;
396 u32 ctrl_cap_flag;
397 u32 gst_offset;
398 u32 inbound_queue_offset;
399 u32 outbound_queue_offset;
400 u32 inbound_q_nppd_hppd;
c6b9ef57
S		 401 u32 rsvd[8];
402 u32 crc_core_dump;
403 u32 rsvd1;
e5742101
S		 404 u32 upper_event_log_addr;
405 u32 lower_event_log_addr;
406 u32 event_log_size;
407 u32 event_log_severity;
408 u32 upper_pcs_event_log_addr;
409 u32 lower_pcs_event_log_addr;
410 u32 pcs_event_log_size;
411 u32 pcs_event_log_severity;
412 u32 fatal_err_interrupt;
413 u32 fatal_err_dump_offset0;
414 u32 fatal_err_dump_length0;
415 u32 fatal_err_dump_offset1;
416 u32 fatal_err_dump_length1;
417 u32 gpio_led_mapping;
418 u32 analog_setup_table_offset;
419 u32 int_vec_table_offset;
420 u32 phy_attr_table_offset;
421 u32 port_recovery_timer;
422 u32 interrupt_reassertion_delay;
d078b511 423 u32 fatal_n_non_fatal_dump; /* 0x28 */
24fff017
V		 424 u32 ila_version;
425 u32 inc_fw_version;
e5742101 426 } pm80xx_tbl;
dbf9bfe6 427};
e5742101
S		 428
429union general_status_table {
430 struct {
dbf9bfe6 431 u32 gst_len_mpistate;
432 u32 iq_freeze_state0;
433 u32 iq_freeze_state1;
434 u32 msgu_tcnt;
435 u32 iop_tcnt;
e5742101 436 u32 rsvd;
dbf9bfe6 437 u32 phy_state[8];
e5742101
S		 438 u32 gpio_input_val;
439 u32 rsvd1[2];
440 u32 recover_err_info[8];
441 } pm8001_tbl;
442 struct {
443 u32 gst_len_mpistate;
444 u32 iq_freeze_state0;
445 u32 iq_freeze_state1;
446 u32 msgu_tcnt;
447 u32 iop_tcnt;
448 u32 rsvd[9];
449 u32 gpio_input_val;
450 u32 rsvd1[2];
dbf9bfe6 451 u32 recover_err_info[8];
e5742101 452 } pm80xx_tbl;
dbf9bfe6 453};
454struct inbound_queue_table {
455 u32 element_pri_size_cnt;
456 u32 upper_base_addr;
457 u32 lower_base_addr;
458 u32 ci_upper_base_addr;
459 u32 ci_lower_base_addr;
460 u32 pi_pci_bar;
461 u32 pi_offset;
462 u32 total_length;
463 void *base_virt;
464 void *ci_virt;
465 u32 reserved;
466 __le32 consumer_index;
467 u32 producer_idx;
468};
469struct outbound_queue_table {
470 u32 element_size_cnt;
471 u32 upper_base_addr;
472 u32 lower_base_addr;
473 void *base_virt;
474 u32 pi_upper_base_addr;
475 u32 pi_lower_base_addr;
476 u32 ci_pci_bar;
477 u32 ci_offset;
478 u32 total_length;
479 void *pi_virt;
480 u32 interrup_vec_cnt_delay;
481 u32 dinterrup_to_pci_offset;
482 __le32 producer_index;
483 u32 consumer_idx;
484};
485struct pm8001_hba_memspace {
486 void __iomem *memvirtaddr;
487 u64 membase;
488 u32 memsize;
489};
6cd60b37
NG		 490struct isr_param {
491 struct pm8001_hba_info *drv_inst;
492 u32 irq_id;
493};
dbf9bfe6 494struct pm8001_hba_info {
495 char name[PM8001_NAME_LENGTH];
496 struct list_head list;
497 unsigned long flags;
498 spinlock_t lock;/* host-wide lock */
646cdf00 499 spinlock_t bitmap_lock;
dbf9bfe6 500 struct pci_dev *pdev;/* our device */
501 struct device *dev;
502 struct pm8001_hba_memspace io_mem[6];
503 struct mpi_mem_req memoryMap;
e5742101 504 struct encrypt encrypt_info; /* support encryption */
d078b511
AKS		 505 struct forensic_data forensic_info;
506 u32 fatal_bar_loc;
507 u32 forensic_last_offset;
508 u32 fatal_forensic_shift_offset;
509 u32 forensic_fatal_step;
510 u32 evtlog_ib_offset;
511 u32 evtlog_ob_offset;
dbf9bfe6 512 void __iomem *msg_unit_tbl_addr;/*Message Unit Table Addr*/
513 void __iomem *main_cfg_tbl_addr;/*Main Config Table Addr*/
514 void __iomem *general_stat_tbl_addr;/*General Status Table Addr*/
515 void __iomem *inbnd_q_tbl_addr;/*Inbound Queue Config Table Addr*/
516 void __iomem *outbnd_q_tbl_addr;/*Outbound Queue Config Table Addr*/
e5742101
S		 517 void __iomem *pspa_q_tbl_addr;
518 /*MPI SAS PHY attributes Queue Config Table Addr*/
519 void __iomem *ivt_tbl_addr; /*MPI IVT Table Addr */
d078b511 520 void __iomem *fatal_tbl_addr; /*MPI IVT Table Addr */
e5742101
S		 521 union main_cfg_table main_cfg_tbl;
522 union general_status_table gs_tbl;
523 struct inbound_queue_table inbnd_q_tbl[PM8001_MAX_SPCV_INB_NUM];
524 struct outbound_queue_table outbnd_q_tbl[PM8001_MAX_SPCV_OUTB_NUM];
525 struct sas_phy_attribute_table phy_attr_table;
526 /* MPI SAS PHY attributes */
dbf9bfe6 527 u8 sas_addr[SAS_ADDR_SIZE];
528 struct sas_ha_struct *sas;/* SCSI/SAS glue */
529 struct Scsi_Host *shost;
530 u32 chip_id;
531 const struct pm8001_chip_info *chip;
532 struct completion *nvmd_completion;
533 int tags_num;
534 unsigned long *tags;
535 struct pm8001_phy phy[PM8001_MAX_PHYS];
536 struct pm8001_port port[PM8001_MAX_PHYS];
537 u32 id;
538 u32 irq;
e5742101 539 u32 iomb_size; /* SPC and SPCV IOMB size */
dbf9bfe6 540 struct pm8001_device *devices;
541 struct pm8001_ccb_info *ccb_info;
542#ifdef PM8001_USE_MSIX
dbf9bfe6 543 int number_of_intr;/*will be used in remove()*/
72954936
VA		 544 char intr_drvname[PM8001_MAX_MSIX_VEC]
545 [PM8001_NAME_LENGTH+1+3+1];
dbf9bfe6 546#endif
547#ifdef PM8001_USE_TASKLET
6cd60b37 548 struct tasklet_struct tasklet[PM8001_MAX_MSIX_VEC];
dbf9bfe6 549#endif
dbf9bfe6 550 u32 logging_level;
3e253d96 551 u32 link_rate;
dbf9bfe6 552 u32 fw_status;
f5860992 553 u32 smp_exp_mode;
72349b62 554 bool controller_fatal_error;
dbf9bfe6 555 const struct firmware *fw_image;
6cd60b37 556 struct isr_param irq_vector[PM8001_MAX_MSIX_VEC];
869ddbdc 557 u32 reset_in_progress;
dbf9bfe6 558};
559
429305e4
TH		 560struct pm8001_work {
561 struct work_struct work;
dbf9bfe6 562 struct pm8001_hba_info *pm8001_ha;
563 void *data;
564 int handler;
dbf9bfe6 565};
566
567struct pm8001_fw_image_header {
568 u8 vender_id[8];
569 u8 product_id;
570 u8 hardware_rev;
571 u8 dest_partition;
572 u8 reserved;
573 u8 fw_rev[4];
574 __be32 image_length;
575 __be32 image_crc;
576 __be32 startup_entry;
577} __attribute__((packed, aligned(4)));
578
7c8356d9 579
dbf9bfe6 580/**
581 * FW Flash Update status values
582 */
583#define FLASH_UPDATE_COMPLETE_PENDING_REBOOT 0x00
584#define FLASH_UPDATE_IN_PROGRESS 0x01
585#define FLASH_UPDATE_HDR_ERR 0x02
586#define FLASH_UPDATE_OFFSET_ERR 0x03
587#define FLASH_UPDATE_CRC_ERR 0x04
588#define FLASH_UPDATE_LENGTH_ERR 0x05
589#define FLASH_UPDATE_HW_ERR 0x06
590#define FLASH_UPDATE_DNLD_NOT_SUPPORTED 0x10
591#define FLASH_UPDATE_DISABLED 0x11
592
c6b9ef57
S		 593#define NCQ_READ_LOG_FLAG 0x80000000
594#define NCQ_ABORT_ALL_FLAG 0x40000000
595#define NCQ_2ND_RLE_FLAG 0x20000000
3a1ae967
V		 596
597/* Device states */
598#define DS_OPERATIONAL 0x01
599#define DS_PORT_IN_RESET 0x02
600#define DS_IN_RECOVERY 0x03
601#define DS_IN_ERROR 0x04
602#define DS_NON_OPERATIONAL 0x07
603
dbf9bfe6 604/**
605 * brief param structure for firmware flash update.
606 */
607struct fw_flash_updata_info {
608 u32 cur_image_offset;
609 u32 cur_image_len;
610 u32 total_image_len;
611 struct pm8001_prd sgl;
612};
613
614struct fw_control_info {
615 u32 retcode;/*ret code (status)*/
616 u32 phase;/*ret code phase*/
617 u32 phaseCmplt;/*percent complete for the current
618 update phase */
619 u32 version;/*Hex encoded firmware version number*/
620 u32 offset;/*Used for downloading firmware */
621 u32 len; /*len of buffer*/
622 u32 size;/* Used in OS VPD and Trace get size
623 operations.*/
624 u32 reserved;/* padding required for 64 bit
625 alignment */
626 u8 buffer[1];/* Start of buffer */
627};
628struct fw_control_ex {
629 struct fw_control_info *fw_control;
630 void *buffer;/* keep buffer pointer to be
25985edc 631 freed when the response comes*/
dbf9bfe6 632 void *virtAddr;/* keep virtual address of the data */
633 void *usrAddr;/* keep virtual address of the
634 user data */
635 dma_addr_t phys_addr;
636 u32 len; /* len of buffer */
637 void *payload; /* pointer to IOCTL Payload */
638 u8 inProgress;/*if 1 - the IOCTL request is in
639 progress */
640 void *param1;
641 void *param2;
642 void *param3;
643};
644
429305e4
TH		 645/* pm8001 workqueue */
646extern struct workqueue_struct *pm8001_wq;
647
dbf9bfe6 648/******************** function prototype *********************/
649int pm8001_tag_alloc(struct pm8001_hba_info *pm8001_ha, u32 *tag_out);
650void pm8001_tag_init(struct pm8001_hba_info *pm8001_ha);
651u32 pm8001_get_ncq_tag(struct sas_task *task, u32 *tag);
dbf9bfe6 652void pm8001_ccb_task_free(struct pm8001_hba_info *pm8001_ha,
653 struct sas_task *task, struct pm8001_ccb_info *ccb, u32 ccb_idx);
654int pm8001_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
655 void *funcdata);
dbf9bfe6 656void pm8001_scan_start(struct Scsi_Host *shost);
657int pm8001_scan_finished(struct Scsi_Host *shost, unsigned long time);
79855d17 658int pm8001_queue_command(struct sas_task *task, gfp_t gfp_flags);
dbf9bfe6 659int pm8001_abort_task(struct sas_task *task);
660int pm8001_abort_task_set(struct domain_device *dev, u8 *lun);
661int pm8001_clear_aca(struct domain_device *dev, u8 *lun);
662int pm8001_clear_task_set(struct domain_device *dev, u8 *lun);
663int pm8001_dev_found(struct domain_device *dev);
664void pm8001_dev_gone(struct domain_device *dev);
665int pm8001_lu_reset(struct domain_device *dev, u8 *lun);
666int pm8001_I_T_nexus_reset(struct domain_device *dev);
a6cb3d01 667int pm8001_I_T_nexus_event_handler(struct domain_device *dev);
dbf9bfe6 668int pm8001_query_task(struct sas_task *task);
5954d738
MS		 669void pm8001_open_reject_retry(
670 struct pm8001_hba_info *pm8001_ha,
671 struct sas_task *task_to_close,
672 struct pm8001_device *device_to_close);
dbf9bfe6 673int pm8001_mem_alloc(struct pci_dev *pdev, void **virt_addr,
674 dma_addr_t *pphys_addr, u32 *pphys_addr_hi, u32 *pphys_addr_lo,
675 u32 mem_size, u32 align);
676
f74cf271
S		 677void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha);
678int pm8001_mpi_build_cmd(struct pm8001_hba_info *pm8001_ha,
679 struct inbound_queue_table *circularQ,
91a43fa6 680 u32 opCode, void *payload, size_t nb,
681 u32 responseQueue);
f74cf271
S		 682int pm8001_mpi_msg_free_get(struct inbound_queue_table *circularQ,
683 u16 messageSize, void **messagePtr);
684u32 pm8001_mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg,
685 struct outbound_queue_table *circularQ, u8 bc);
686u32 pm8001_mpi_msg_consume(struct pm8001_hba_info *pm8001_ha,
687 struct outbound_queue_table *circularQ,
688 void **messagePtr1, u8 *pBC);
689int pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha,
690 struct pm8001_device *pm8001_dev, u32 state);
691int pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha,
692 void *payload);
693int pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha,
694 void *fw_flash_updata_info, u32 tag);
695int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha, void *payload);
696int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha, void *payload);
697int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha,
698 struct pm8001_ccb_info *ccb,
699 struct pm8001_tmf_task *tmf);
700int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha,
701 struct pm8001_device *pm8001_dev,
702 u8 flag, u32 task_tag, u32 cmd_tag);
703int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha, u32 device_id);
704void pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd);
705void pm8001_work_fn(struct work_struct *work);
706int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha,
707 void *data, int handler);
708void pm8001_mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha,
709 void *piomb);
710void pm8001_mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha,
711 void *piomb);
712void pm8001_mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha,
713 void *piomb);
714int pm8001_mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha,
715 void *piomb);
716void pm8001_get_lrate_mode(struct pm8001_phy *phy, u8 link_rate);
717void pm8001_get_attached_sas_addr(struct pm8001_phy *phy, u8 *sas_addr);
718void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i);
719int pm8001_mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb);
720int pm8001_mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb);
721int pm8001_mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha,
722 void *piomb);
723int pm8001_mpi_general_event(struct pm8001_hba_info *pm8001_ha , void *piomb);
724int pm8001_mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb);
c6b9ef57
S		 725struct sas_task *pm8001_alloc_task(void);
726void pm8001_task_done(struct sas_task *task);
727void pm8001_free_task(struct sas_task *task);
728void pm8001_tag_free(struct pm8001_hba_info *pm8001_ha, u32 tag);
729struct pm8001_device *pm8001_find_dev(struct pm8001_hba_info *pm8001_ha,
730 u32 device_id);
a6cb3d01 731int pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha);
f74cf271 732
d95d0001 733int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue);
27909407
AKS		 734void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha,
735 u32 length, u8 *buf);
c5614df7
BR		 736void pm8001_set_phy_profile_single(struct pm8001_hba_info *pm8001_ha,
737 u32 phy, u32 length, u32 *buf);
d078b511
AKS		 738int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue);
739ssize_t pm80xx_get_fatal_dump(struct device *cdev,
740 struct device_attribute *attr, char *buf);
741ssize_t pm8001_get_gsm_dump(struct device *cdev, u32, char *buf);
dbf9bfe6 742/* ctl shared API */
743extern struct device_attribute *pm8001_host_attrs[];
744
2b01d816
ST		 745static inline void
746pm8001_ccb_task_free_done(struct pm8001_hba_info *pm8001_ha,
747 struct sas_task *task, struct pm8001_ccb_info *ccb,
748 u32 ccb_idx)
749{
750 pm8001_ccb_task_free(pm8001_ha, task, ccb, ccb_idx);
751 smp_mb(); /*in order to force CPU ordering*/
752 spin_unlock(&pm8001_ha->lock);
753 task->task_done(task);
754 spin_lock(&pm8001_ha->lock);
755}
756
dbf9bfe6 757#endif
758
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