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[SCSI] pm80xx: Resetting the phy state.
[mirror_ubuntu-artful-kernel.git] / drivers / scsi / pm8001 / pm8001_sas.h
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dbf9bfe6 1/*
f5860992 2 * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver
dbf9bfe6 3 *
4 * Copyright (c) 2008-2009 USI Co., Ltd.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
25 *
26 * NO WARRANTY
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
38 *
39 */
40
41#ifndef _PM8001_SAS_H_
42#define _PM8001_SAS_H_
43
44#include <linux/kernel.h>
45#include <linux/module.h>
46#include <linux/spinlock.h>
47#include <linux/delay.h>
48#include <linux/types.h>
49#include <linux/ctype.h>
50#include <linux/dma-mapping.h>
51#include <linux/pci.h>
52#include <linux/interrupt.h>
429305e4 53#include <linux/workqueue.h>
dbf9bfe6 54#include <scsi/libsas.h>
55#include <scsi/scsi_tcq.h>
56#include <scsi/sas_ata.h>
60063497 57#include <linux/atomic.h>
dbf9bfe6 58#include "pm8001_defs.h"
59
a70b8fc3
S		 60#define DRV_NAME "pm80xx"
61#define DRV_VERSION "0.1.37"
83e73329 62#define PM8001_FAIL_LOGGING 0x01 /* Error message logging */
dbf9bfe6 63#define PM8001_INIT_LOGGING 0x02 /* driver init logging */
64#define PM8001_DISC_LOGGING 0x04 /* discovery layer logging */
65#define PM8001_IO_LOGGING 0x08 /* I/O path logging */
83e73329 66#define PM8001_EH_LOGGING 0x10 /* libsas EH function logging*/
dbf9bfe6 67#define PM8001_IOCTL_LOGGING 0x20 /* IOCTL message logging */
68#define PM8001_MSG_LOGGING 0x40 /* misc message logging */
a70b8fc3
S		 69#define pm8001_printk(format, arg...) printk(KERN_INFO "pm80xx %s %d:" \
70 format, __func__, __LINE__, ## arg)
dbf9bfe6 71#define PM8001_CHECK_LOGGING(HBA, LEVEL, CMD) \
72do { \
73 if (unlikely(HBA->logging_level & LEVEL)) \
74 do { \
75 CMD; \
76 } while (0); \
77} while (0);
78
79#define PM8001_EH_DBG(HBA, CMD) \
80 PM8001_CHECK_LOGGING(HBA, PM8001_EH_LOGGING, CMD)
81
82#define PM8001_INIT_DBG(HBA, CMD) \
83 PM8001_CHECK_LOGGING(HBA, PM8001_INIT_LOGGING, CMD)
84
85#define PM8001_DISC_DBG(HBA, CMD) \
86 PM8001_CHECK_LOGGING(HBA, PM8001_DISC_LOGGING, CMD)
87
88#define PM8001_IO_DBG(HBA, CMD) \
89 PM8001_CHECK_LOGGING(HBA, PM8001_IO_LOGGING, CMD)
90
91#define PM8001_FAIL_DBG(HBA, CMD) \
92 PM8001_CHECK_LOGGING(HBA, PM8001_FAIL_LOGGING, CMD)
93
94#define PM8001_IOCTL_DBG(HBA, CMD) \
95 PM8001_CHECK_LOGGING(HBA, PM8001_IOCTL_LOGGING, CMD)
96
97#define PM8001_MSG_DBG(HBA, CMD) \
98 PM8001_CHECK_LOGGING(HBA, PM8001_MSG_LOGGING, CMD)
99
100
101#define PM8001_USE_TASKLET
102#define PM8001_USE_MSIX
7c8356d9 103#define PM8001_READ_VPD
dbf9bfe6 104
105
aa9f8328 106#define DEV_IS_EXPANDER(type) ((type == SAS_EDGE_EXPANDER_DEVICE) || (type == SAS_FANOUT_EXPANDER_DEVICE))
a9a923e5
AKS		 107#define IS_SPCV_12G(dev) ((dev->device == 0X8074) \
108 || (dev->device == 0X8076) \
109 || (dev->device == 0X8077))
dbf9bfe6 110
111#define PM8001_NAME_LENGTH 32/* generic length of strings */
112extern struct list_head hba_list;
113extern const struct pm8001_dispatch pm8001_8001_dispatch;
f5860992 114extern const struct pm8001_dispatch pm8001_80xx_dispatch;
dbf9bfe6 115
116struct pm8001_hba_info;
117struct pm8001_ccb_info;
118struct pm8001_device;
7c8356d9 119/* define task management IU */
120struct pm8001_tmf_task {
121 u8 tmf;
122 u32 tag_of_task_to_be_managed;
123};
124struct pm8001_ioctl_payload {
125 u32 signature;
126 u16 major_function;
127 u16 minor_function;
128 u16 length;
129 u16 status;
130 u16 offset;
131 u16 id;
132 u8 *func_specific;
133};
134
d078b511
AKS		 135#define MPI_FATAL_ERROR_TABLE_OFFSET_MASK 0xFFFFFF
136#define MPI_FATAL_ERROR_TABLE_SIZE(value) ((0xFF000000 & value) >> SHIFT24)
137#define MPI_FATAL_EDUMP_TABLE_LO_OFFSET 0x00 /* HNFBUFL */
138#define MPI_FATAL_EDUMP_TABLE_HI_OFFSET 0x04 /* HNFBUFH */
139#define MPI_FATAL_EDUMP_TABLE_LENGTH 0x08 /* HNFBLEN */
140#define MPI_FATAL_EDUMP_TABLE_HANDSHAKE 0x0C /* FDDHSHK */
141#define MPI_FATAL_EDUMP_TABLE_STATUS 0x10 /* FDDTSTAT */
142#define MPI_FATAL_EDUMP_TABLE_ACCUM_LEN 0x14 /* ACCDDLEN */
143#define MPI_FATAL_EDUMP_HANDSHAKE_RDY 0x1
144#define MPI_FATAL_EDUMP_HANDSHAKE_BUSY 0x0
145#define MPI_FATAL_EDUMP_TABLE_STAT_RSVD 0x0
146#define MPI_FATAL_EDUMP_TABLE_STAT_DMA_FAILED 0x1
147#define MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_MORE_DATA 0x2
148#define MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE 0x3
149#define TYPE_GSM_SPACE 1
150#define TYPE_QUEUE 2
151#define TYPE_FATAL 3
152#define TYPE_NON_FATAL 4
153#define TYPE_INBOUND 1
154#define TYPE_OUTBOUND 2
155struct forensic_data {
156 u32 data_type;
157 union {
158 struct {
159 u32 direct_len;
160 u32 direct_offset;
161 void *direct_data;
162 } gsm_buf;
163 struct {
164 u16 queue_type;
165 u16 queue_index;
166 u32 direct_len;
167 void *direct_data;
168 } queue_buf;
169 struct {
170 u32 direct_len;
171 u32 direct_offset;
172 u32 read_len;
173 void *direct_data;
174 } data_buf;
175 };
176};
177
178/* bit31-26 - mask bar */
179#define SCRATCH_PAD0_BAR_MASK 0xFC000000
180/* bit25-0 - offset mask */
181#define SCRATCH_PAD0_OFFSET_MASK 0x03FFFFFF
182/* if AAP error state */
183#define SCRATCH_PAD0_AAPERR_MASK 0xFFFFFFFF
184/* Inbound doorbell bit7 */
185#define SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP 0x80
186/* Inbound doorbell bit7 SPCV */
187#define SPCV_MSGU_CFG_TABLE_TRANSFER_DEBUG_INFO 0x80
188#define MAIN_MERRDCTO_MERRDCES 0xA0/* DWORD 0x28) */
189
dbf9bfe6 190struct pm8001_dispatch {
191 char *name;
192 int (*chip_init)(struct pm8001_hba_info *pm8001_ha);
f5860992 193 int (*chip_soft_rst)(struct pm8001_hba_info *pm8001_ha);
dbf9bfe6 194 void (*chip_rst)(struct pm8001_hba_info *pm8001_ha);
195 int (*chip_ioremap)(struct pm8001_hba_info *pm8001_ha);
196 void (*chip_iounmap)(struct pm8001_hba_info *pm8001_ha);
f74cf271 197 irqreturn_t (*isr)(struct pm8001_hba_info *pm8001_ha, u8 vec);
dbf9bfe6 198 u32 (*is_our_interupt)(struct pm8001_hba_info *pm8001_ha);
f74cf271
S		 199 int (*isr_process_oq)(struct pm8001_hba_info *pm8001_ha, u8 vec);
200 void (*interrupt_enable)(struct pm8001_hba_info *pm8001_ha, u8 vec);
201 void (*interrupt_disable)(struct pm8001_hba_info *pm8001_ha, u8 vec);
dbf9bfe6 202 void (*make_prd)(struct scatterlist *scatter, int nr, void *prd);
203 int (*smp_req)(struct pm8001_hba_info *pm8001_ha,
204 struct pm8001_ccb_info *ccb);
205 int (*ssp_io_req)(struct pm8001_hba_info *pm8001_ha,
206 struct pm8001_ccb_info *ccb);
207 int (*sata_req)(struct pm8001_hba_info *pm8001_ha,
208 struct pm8001_ccb_info *ccb);
209 int (*phy_start_req)(struct pm8001_hba_info *pm8001_ha, u8 phy_id);
210 int (*phy_stop_req)(struct pm8001_hba_info *pm8001_ha, u8 phy_id);
211 int (*reg_dev_req)(struct pm8001_hba_info *pm8001_ha,
212 struct pm8001_device *pm8001_dev, u32 flag);
213 int (*dereg_dev_req)(struct pm8001_hba_info *pm8001_ha, u32 device_id);
214 int (*phy_ctl_req)(struct pm8001_hba_info *pm8001_ha,
215 u32 phy_id, u32 phy_op);
216 int (*task_abort)(struct pm8001_hba_info *pm8001_ha,
217 struct pm8001_device *pm8001_dev, u8 flag, u32 task_tag,
218 u32 cmd_tag);
219 int (*ssp_tm_req)(struct pm8001_hba_info *pm8001_ha,
220 struct pm8001_ccb_info *ccb, struct pm8001_tmf_task *tmf);
221 int (*get_nvmd_req)(struct pm8001_hba_info *pm8001_ha, void *payload);
222 int (*set_nvmd_req)(struct pm8001_hba_info *pm8001_ha, void *payload);
223 int (*fw_flash_update_req)(struct pm8001_hba_info *pm8001_ha,
224 void *payload);
225 int (*set_dev_state_req)(struct pm8001_hba_info *pm8001_ha,
226 struct pm8001_device *pm8001_dev, u32 state);
227 int (*sas_diag_start_end_req)(struct pm8001_hba_info *pm8001_ha,
228 u32 state);
229 int (*sas_diag_execute_req)(struct pm8001_hba_info *pm8001_ha,
230 u32 state);
d0b68041 231 int (*sas_re_init_req)(struct pm8001_hba_info *pm8001_ha);
dbf9bfe6 232};
233
234struct pm8001_chip_info {
e5742101 235 u32 encrypt;
dbf9bfe6 236 u32 n_phy;
237 const struct pm8001_dispatch *dispatch;
238};
239#define PM8001_CHIP_DISP (pm8001_ha->chip->dispatch)
240
241struct pm8001_port {
242 struct asd_sas_port sas_port;
1cc943ae 243 u8 port_attached;
244 u8 wide_port_phymap;
245 u8 port_state;
246 struct list_head list;
dbf9bfe6 247};
248
249struct pm8001_phy {
250 struct pm8001_hba_info *pm8001_ha;
251 struct pm8001_port *port;
252 struct asd_sas_phy sas_phy;
253 struct sas_identify identify;
254 struct scsi_device *sdev;
255 u64 dev_sas_addr;
256 u32 phy_type;
257 struct completion *enable_completion;
258 u32 frame_rcvd_size;
259 u8 frame_rcvd[32];
260 u8 phy_attached;
261 u8 phy_state;
262 enum sas_linkrate minimum_linkrate;
263 enum sas_linkrate maximum_linkrate;
264};
265
266struct pm8001_device {
aa9f8328 267 enum sas_device_type dev_type;
dbf9bfe6 268 struct domain_device *sas_device;
269 u32 attached_phy;
270 u32 id;
271 struct completion *dcompletion;
272 struct completion *setds_completion;
273 u32 device_id;
274 u32 running_req;
275};
276
277struct pm8001_prd_imt {
278 __le32 len;
279 __le32 e;
280};
281
282struct pm8001_prd {
283 __le64 addr; /* 64-bit buffer address */
284 struct pm8001_prd_imt im_len; /* 64-bit length */
285} __attribute__ ((packed));
286/*
287 * CCB(Command Control Block)
288 */
289struct pm8001_ccb_info {
290 struct list_head entry;
291 struct sas_task *task;
292 u32 n_elem;
293 u32 ccb_tag;
294 dma_addr_t ccb_dma_handle;
295 struct pm8001_device *device;
296 struct pm8001_prd buf_prd[PM8001_MAX_DMA_SG];
297 struct fw_control_ex *fw_control_context;
5954d738 298 u8 open_retry;
dbf9bfe6 299};
300
301struct mpi_mem {
302 void *virt_ptr;
303 dma_addr_t phys_addr;
304 u32 phys_addr_hi;
305 u32 phys_addr_lo;
306 u32 total_len;
307 u32 num_elements;
308 u32 element_size;
309 u32 alignment;
310};
311
312struct mpi_mem_req {
313 /* The number of element in the mpiMemory array */
314 u32 count;
315 /* The array of structures that define memroy regions*/
316 struct mpi_mem region[USI_MAX_MEMCNT];
317};
318
e5742101
S		 319struct encrypt {
320 u32 cipher_mode;
321 u32 sec_mode;
322 u32 status;
323 u32 flag;
324};
325
326struct sas_phy_attribute_table {
327 u32 phystart1_16[16];
328 u32 outbound_hw_event_pid1_16[16];
329};
330
331union main_cfg_table {
332 struct {
dbf9bfe6 333 u32 signature;
334 u32 interface_rev;
335 u32 firmware_rev;
336 u32 max_out_io;
337 u32 max_sgl;
338 u32 ctrl_cap_flag;
339 u32 gst_offset;
340 u32 inbound_queue_offset;
341 u32 outbound_queue_offset;
342 u32 inbound_q_nppd_hppd;
343 u32 outbound_hw_event_pid0_3;
344 u32 outbound_hw_event_pid4_7;
345 u32 outbound_ncq_event_pid0_3;
346 u32 outbound_ncq_event_pid4_7;
347 u32 outbound_tgt_ITNexus_event_pid0_3;
348 u32 outbound_tgt_ITNexus_event_pid4_7;
349 u32 outbound_tgt_ssp_event_pid0_3;
350 u32 outbound_tgt_ssp_event_pid4_7;
351 u32 outbound_tgt_smp_event_pid0_3;
352 u32 outbound_tgt_smp_event_pid4_7;
353 u32 upper_event_log_addr;
354 u32 lower_event_log_addr;
355 u32 event_log_size;
356 u32 event_log_option;
357 u32 upper_iop_event_log_addr;
358 u32 lower_iop_event_log_addr;
359 u32 iop_event_log_size;
360 u32 iop_event_log_option;
361 u32 fatal_err_interrupt;
362 u32 fatal_err_dump_offset0;
363 u32 fatal_err_dump_length0;
364 u32 fatal_err_dump_offset1;
365 u32 fatal_err_dump_length1;
366 u32 hda_mode_flag;
367 u32 anolog_setup_table_offset;
e5742101
S		 368 u32 rsvd[4];
369 } pm8001_tbl;
370
371 struct {
372 u32 signature;
373 u32 interface_rev;
374 u32 firmware_rev;
375 u32 max_out_io;
376 u32 max_sgl;
377 u32 ctrl_cap_flag;
378 u32 gst_offset;
379 u32 inbound_queue_offset;
380 u32 outbound_queue_offset;
381 u32 inbound_q_nppd_hppd;
c6b9ef57
S		 382 u32 rsvd[8];
383 u32 crc_core_dump;
384 u32 rsvd1;
e5742101
S		 385 u32 upper_event_log_addr;
386 u32 lower_event_log_addr;
387 u32 event_log_size;
388 u32 event_log_severity;
389 u32 upper_pcs_event_log_addr;
390 u32 lower_pcs_event_log_addr;
391 u32 pcs_event_log_size;
392 u32 pcs_event_log_severity;
393 u32 fatal_err_interrupt;
394 u32 fatal_err_dump_offset0;
395 u32 fatal_err_dump_length0;
396 u32 fatal_err_dump_offset1;
397 u32 fatal_err_dump_length1;
398 u32 gpio_led_mapping;
399 u32 analog_setup_table_offset;
400 u32 int_vec_table_offset;
401 u32 phy_attr_table_offset;
402 u32 port_recovery_timer;
403 u32 interrupt_reassertion_delay;
d078b511 404 u32 fatal_n_non_fatal_dump; /* 0x28 */
e5742101 405 } pm80xx_tbl;
dbf9bfe6 406};
e5742101
S		 407
408union general_status_table {
409 struct {
dbf9bfe6 410 u32 gst_len_mpistate;
411 u32 iq_freeze_state0;
412 u32 iq_freeze_state1;
413 u32 msgu_tcnt;
414 u32 iop_tcnt;
e5742101 415 u32 rsvd;
dbf9bfe6 416 u32 phy_state[8];
e5742101
S		 417 u32 gpio_input_val;
418 u32 rsvd1[2];
419 u32 recover_err_info[8];
420 } pm8001_tbl;
421 struct {
422 u32 gst_len_mpistate;
423 u32 iq_freeze_state0;
424 u32 iq_freeze_state1;
425 u32 msgu_tcnt;
426 u32 iop_tcnt;
427 u32 rsvd[9];
428 u32 gpio_input_val;
429 u32 rsvd1[2];
dbf9bfe6 430 u32 recover_err_info[8];
e5742101 431 } pm80xx_tbl;
dbf9bfe6 432};
433struct inbound_queue_table {
434 u32 element_pri_size_cnt;
435 u32 upper_base_addr;
436 u32 lower_base_addr;
437 u32 ci_upper_base_addr;
438 u32 ci_lower_base_addr;
439 u32 pi_pci_bar;
440 u32 pi_offset;
441 u32 total_length;
442 void *base_virt;
443 void *ci_virt;
444 u32 reserved;
445 __le32 consumer_index;
446 u32 producer_idx;
447};
448struct outbound_queue_table {
449 u32 element_size_cnt;
450 u32 upper_base_addr;
451 u32 lower_base_addr;
452 void *base_virt;
453 u32 pi_upper_base_addr;
454 u32 pi_lower_base_addr;
455 u32 ci_pci_bar;
456 u32 ci_offset;
457 u32 total_length;
458 void *pi_virt;
459 u32 interrup_vec_cnt_delay;
460 u32 dinterrup_to_pci_offset;
461 __le32 producer_index;
462 u32 consumer_idx;
463};
464struct pm8001_hba_memspace {
465 void __iomem *memvirtaddr;
466 u64 membase;
467 u32 memsize;
468};
469struct pm8001_hba_info {
470 char name[PM8001_NAME_LENGTH];
471 struct list_head list;
472 unsigned long flags;
473 spinlock_t lock;/* host-wide lock */
474 struct pci_dev *pdev;/* our device */
475 struct device *dev;
476 struct pm8001_hba_memspace io_mem[6];
477 struct mpi_mem_req memoryMap;
e5742101 478 struct encrypt encrypt_info; /* support encryption */
d078b511
AKS		 479 struct forensic_data forensic_info;
480 u32 fatal_bar_loc;
481 u32 forensic_last_offset;
482 u32 fatal_forensic_shift_offset;
483 u32 forensic_fatal_step;
484 u32 evtlog_ib_offset;
485 u32 evtlog_ob_offset;
dbf9bfe6 486 void __iomem *msg_unit_tbl_addr;/*Message Unit Table Addr*/
487 void __iomem *main_cfg_tbl_addr;/*Main Config Table Addr*/
488 void __iomem *general_stat_tbl_addr;/*General Status Table Addr*/
489 void __iomem *inbnd_q_tbl_addr;/*Inbound Queue Config Table Addr*/
490 void __iomem *outbnd_q_tbl_addr;/*Outbound Queue Config Table Addr*/
e5742101
S		 491 void __iomem *pspa_q_tbl_addr;
492 /*MPI SAS PHY attributes Queue Config Table Addr*/
493 void __iomem *ivt_tbl_addr; /*MPI IVT Table Addr */
d078b511 494 void __iomem *fatal_tbl_addr; /*MPI IVT Table Addr */
e5742101
S		 495 union main_cfg_table main_cfg_tbl;
496 union general_status_table gs_tbl;
497 struct inbound_queue_table inbnd_q_tbl[PM8001_MAX_SPCV_INB_NUM];
498 struct outbound_queue_table outbnd_q_tbl[PM8001_MAX_SPCV_OUTB_NUM];
499 struct sas_phy_attribute_table phy_attr_table;
500 /* MPI SAS PHY attributes */
dbf9bfe6 501 u8 sas_addr[SAS_ADDR_SIZE];
502 struct sas_ha_struct *sas;/* SCSI/SAS glue */
503 struct Scsi_Host *shost;
504 u32 chip_id;
505 const struct pm8001_chip_info *chip;
506 struct completion *nvmd_completion;
507 int tags_num;
508 unsigned long *tags;
509 struct pm8001_phy phy[PM8001_MAX_PHYS];
510 struct pm8001_port port[PM8001_MAX_PHYS];
511 u32 id;
512 u32 irq;
e5742101 513 u32 iomb_size; /* SPC and SPCV IOMB size */
dbf9bfe6 514 struct pm8001_device *devices;
515 struct pm8001_ccb_info *ccb_info;
516#ifdef PM8001_USE_MSIX
e5742101
S		 517 struct msix_entry msix_entries[PM8001_MAX_MSIX_VEC];
518 /*for msi-x interrupt*/
dbf9bfe6 519 int number_of_intr;/*will be used in remove()*/
520#endif
521#ifdef PM8001_USE_TASKLET
522 struct tasklet_struct tasklet;
523#endif
dbf9bfe6 524 u32 logging_level;
525 u32 fw_status;
f5860992 526 u32 smp_exp_mode;
1245ee59 527 u32 int_vector;
dbf9bfe6 528 const struct firmware *fw_image;
1245ee59 529 u8 outq[PM8001_MAX_MSIX_VEC];
dbf9bfe6 530};
531
429305e4
TH		 532struct pm8001_work {
533 struct work_struct work;
dbf9bfe6 534 struct pm8001_hba_info *pm8001_ha;
535 void *data;
536 int handler;
dbf9bfe6 537};
538
539struct pm8001_fw_image_header {
540 u8 vender_id[8];
541 u8 product_id;
542 u8 hardware_rev;
543 u8 dest_partition;
544 u8 reserved;
545 u8 fw_rev[4];
546 __be32 image_length;
547 __be32 image_crc;
548 __be32 startup_entry;
549} __attribute__((packed, aligned(4)));
550
7c8356d9 551
dbf9bfe6 552/**
553 * FW Flash Update status values
554 */
555#define FLASH_UPDATE_COMPLETE_PENDING_REBOOT 0x00
556#define FLASH_UPDATE_IN_PROGRESS 0x01
557#define FLASH_UPDATE_HDR_ERR 0x02
558#define FLASH_UPDATE_OFFSET_ERR 0x03
559#define FLASH_UPDATE_CRC_ERR 0x04
560#define FLASH_UPDATE_LENGTH_ERR 0x05
561#define FLASH_UPDATE_HW_ERR 0x06
562#define FLASH_UPDATE_DNLD_NOT_SUPPORTED 0x10
563#define FLASH_UPDATE_DISABLED 0x11
564
c6b9ef57
S		 565#define NCQ_READ_LOG_FLAG 0x80000000
566#define NCQ_ABORT_ALL_FLAG 0x40000000
567#define NCQ_2ND_RLE_FLAG 0x20000000
dbf9bfe6 568/**
569 * brief param structure for firmware flash update.
570 */
571struct fw_flash_updata_info {
572 u32 cur_image_offset;
573 u32 cur_image_len;
574 u32 total_image_len;
575 struct pm8001_prd sgl;
576};
577
578struct fw_control_info {
579 u32 retcode;/*ret code (status)*/
580 u32 phase;/*ret code phase*/
581 u32 phaseCmplt;/*percent complete for the current
582 update phase */
583 u32 version;/*Hex encoded firmware version number*/
584 u32 offset;/*Used for downloading firmware */
585 u32 len; /*len of buffer*/
586 u32 size;/* Used in OS VPD and Trace get size
587 operations.*/
588 u32 reserved;/* padding required for 64 bit
589 alignment */
590 u8 buffer[1];/* Start of buffer */
591};
592struct fw_control_ex {
593 struct fw_control_info *fw_control;
594 void *buffer;/* keep buffer pointer to be
25985edc 595 freed when the response comes*/
dbf9bfe6 596 void *virtAddr;/* keep virtual address of the data */
597 void *usrAddr;/* keep virtual address of the
598 user data */
599 dma_addr_t phys_addr;
600 u32 len; /* len of buffer */
601 void *payload; /* pointer to IOCTL Payload */
602 u8 inProgress;/*if 1 - the IOCTL request is in
603 progress */
604 void *param1;
605 void *param2;
606 void *param3;
607};
608
429305e4
TH		 609/* pm8001 workqueue */
610extern struct workqueue_struct *pm8001_wq;
611
dbf9bfe6 612/******************** function prototype *********************/
613int pm8001_tag_alloc(struct pm8001_hba_info *pm8001_ha, u32 *tag_out);
614void pm8001_tag_init(struct pm8001_hba_info *pm8001_ha);
615u32 pm8001_get_ncq_tag(struct sas_task *task, u32 *tag);
616void pm8001_ccb_free(struct pm8001_hba_info *pm8001_ha, u32 ccb_idx);
617void pm8001_ccb_task_free(struct pm8001_hba_info *pm8001_ha,
618 struct sas_task *task, struct pm8001_ccb_info *ccb, u32 ccb_idx);
619int pm8001_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
620 void *funcdata);
dbf9bfe6 621void pm8001_scan_start(struct Scsi_Host *shost);
622int pm8001_scan_finished(struct Scsi_Host *shost, unsigned long time);
623int pm8001_queue_command(struct sas_task *task, const int num,
624 gfp_t gfp_flags);
625int pm8001_abort_task(struct sas_task *task);
626int pm8001_abort_task_set(struct domain_device *dev, u8 *lun);
627int pm8001_clear_aca(struct domain_device *dev, u8 *lun);
628int pm8001_clear_task_set(struct domain_device *dev, u8 *lun);
629int pm8001_dev_found(struct domain_device *dev);
630void pm8001_dev_gone(struct domain_device *dev);
631int pm8001_lu_reset(struct domain_device *dev, u8 *lun);
632int pm8001_I_T_nexus_reset(struct domain_device *dev);
a6cb3d01 633int pm8001_I_T_nexus_event_handler(struct domain_device *dev);
dbf9bfe6 634int pm8001_query_task(struct sas_task *task);
5954d738
MS		 635void pm8001_open_reject_retry(
636 struct pm8001_hba_info *pm8001_ha,
637 struct sas_task *task_to_close,
638 struct pm8001_device *device_to_close);
dbf9bfe6 639int pm8001_mem_alloc(struct pci_dev *pdev, void **virt_addr,
640 dma_addr_t *pphys_addr, u32 *pphys_addr_hi, u32 *pphys_addr_lo,
641 u32 mem_size, u32 align);
642
f74cf271
S		 643void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha);
644int pm8001_mpi_build_cmd(struct pm8001_hba_info *pm8001_ha,
645 struct inbound_queue_table *circularQ,
646 u32 opCode, void *payload, u32 responseQueue);
647int pm8001_mpi_msg_free_get(struct inbound_queue_table *circularQ,
648 u16 messageSize, void **messagePtr);
649u32 pm8001_mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg,
650 struct outbound_queue_table *circularQ, u8 bc);
651u32 pm8001_mpi_msg_consume(struct pm8001_hba_info *pm8001_ha,
652 struct outbound_queue_table *circularQ,
653 void **messagePtr1, u8 *pBC);
654int pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha,
655 struct pm8001_device *pm8001_dev, u32 state);
656int pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha,
657 void *payload);
658int pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha,
659 void *fw_flash_updata_info, u32 tag);
660int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha, void *payload);
661int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha, void *payload);
662int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha,
663 struct pm8001_ccb_info *ccb,
664 struct pm8001_tmf_task *tmf);
665int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha,
666 struct pm8001_device *pm8001_dev,
667 u8 flag, u32 task_tag, u32 cmd_tag);
668int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha, u32 device_id);
669void pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd);
670void pm8001_work_fn(struct work_struct *work);
671int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha,
672 void *data, int handler);
673void pm8001_mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha,
674 void *piomb);
675void pm8001_mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha,
676 void *piomb);
677void pm8001_mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha,
678 void *piomb);
679int pm8001_mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha,
680 void *piomb);
681void pm8001_get_lrate_mode(struct pm8001_phy *phy, u8 link_rate);
682void pm8001_get_attached_sas_addr(struct pm8001_phy *phy, u8 *sas_addr);
683void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i);
684int pm8001_mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb);
685int pm8001_mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb);
686int pm8001_mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha,
687 void *piomb);
688int pm8001_mpi_general_event(struct pm8001_hba_info *pm8001_ha , void *piomb);
689int pm8001_mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb);
c6b9ef57
S		 690struct sas_task *pm8001_alloc_task(void);
691void pm8001_task_done(struct sas_task *task);
692void pm8001_free_task(struct sas_task *task);
693void pm8001_tag_free(struct pm8001_hba_info *pm8001_ha, u32 tag);
694struct pm8001_device *pm8001_find_dev(struct pm8001_hba_info *pm8001_ha,
695 u32 device_id);
a6cb3d01 696int pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha);
f74cf271 697
d95d0001 698int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue);
27909407
AKS		 699void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha,
700 u32 length, u8 *buf);
d078b511
AKS		 701int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue);
702ssize_t pm80xx_get_fatal_dump(struct device *cdev,
703 struct device_attribute *attr, char *buf);
704ssize_t pm8001_get_gsm_dump(struct device *cdev, u32, char *buf);
dbf9bfe6 705/* ctl shared API */
706extern struct device_attribute *pm8001_host_attrs[];
707
708#endif
709
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