projects / mirror_ubuntu-bionic-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 | 1 | /* |
| fa90c54f | 2 | * QLogic Fibre Channel HBA Driver |
| 07e264b7 | 3 | * Copyright (c) 2003-2011 QLogic Corporation |
| 1da177e4 | 4 | * |
| fa90c54f | 5 | * See LICENSE.qla2xxx for copyright and licensing details. |
| 1da177e4 | 6 | */ |
| 3ce8866c SK |
7 | |
| 8 | /* | |
| 9 | * Table for showing the current message id in use for particular level | |
| 10 | * Change this table for addition of log/debug messages. | |
| e02587d7 AE |
11 | * ---------------------------------------------------------------------- |
| 12 | * | Level | Last Value Used | Holes | | |
| 13 | * ---------------------------------------------------------------------- | |
| 0b91d116 | 14 | * | Module Init and Probe | 0x0120 | 0x4b,0xba,0xfa | |
| 5f28d2d7 SK |
15 | * | Mailbox commands | 0x113e | 0x111a-0x111b | |
| 16 | * | | | 0x112c-0x112e | | |
| af11f64d | 17 | * | | | 0x113a | |
| 557cf785 | 18 | * | Device Discovery | 0x2086 | 0x2020-0x2022 | |
| 4aee5766 | 19 | * | Queue Command and IO tracing | 0x3030 | 0x3006,0x3008 | |
| 6246b8a1 | 20 | * | | | 0x302d-0x302e | |
| 5f28d2d7 | 21 | * | DPC Thread | 0x401c | 0x4002,0x4013 | |
| daae62a3 | 22 | * | Async Events | 0x505f | 0x502b-0x502f | |
| 9ba56b95 | 23 | * | | | 0x5047,0x5052 | |
| 5988aeb2 | 24 | * | Timer Routines | 0x6011 | | |
| 733a95bd JC |
25 | * | User Space Interactions | 0x709f | 0x7018,0x702e, | |
| 26 | * | | | 0x7039,0x7045, | | |
| 27 | * | | | 0x7073-0x7075, | | |
| 28 | * | | | 0x708c | | |
| cfb0919c CD |
29 | * | Task Management | 0x803c | 0x8025-0x8026 | |
| 30 | * | | | 0x800b,0x8039 | | |
| 5f28d2d7 | 31 | * | AER/EEH | 0x9011 | | |
| e02587d7 | 32 | * | Virtual Port | 0xa007 | | |
| 5f28d2d7 | 33 | * | ISP82XX Specific | 0xb054 | 0xb024 | |
| 6246b8a1 GM |
34 | * | MultiQ | 0xc00c | | |
| 35 | * | Misc | 0xd010 | | | |
| e02587d7 | 36 | * ---------------------------------------------------------------------- |
| 3ce8866c SK |
37 | */ |
| 38 | ||
| 1da177e4 LT |
39 | #include "qla_def.h" |
| 40 | ||
| 41 | #include <linux/delay.h> | |
| 42 | ||
| 3ce8866c SK |
43 | static uint32_t ql_dbg_offset = 0x800; |
| 44 | ||
| a7a167bf | 45 | static inline void |
| 7b867cf7 | 46 | qla2xxx_prep_dump(struct qla_hw_data *ha, struct qla2xxx_fw_dump *fw_dump) |
| a7a167bf AV |
47 | { |
| 48 | fw_dump->fw_major_version = htonl(ha->fw_major_version); | |
| 49 | fw_dump->fw_minor_version = htonl(ha->fw_minor_version); | |
| 50 | fw_dump->fw_subminor_version = htonl(ha->fw_subminor_version); | |
| 51 | fw_dump->fw_attributes = htonl(ha->fw_attributes); | |
| 52 | ||
| 53 | fw_dump->vendor = htonl(ha->pdev->vendor); | |
| 54 | fw_dump->device = htonl(ha->pdev->device); | |
| 55 | fw_dump->subsystem_vendor = htonl(ha->pdev->subsystem_vendor); | |
| 56 | fw_dump->subsystem_device = htonl(ha->pdev->subsystem_device); | |
| 57 | } | |
| 58 | ||
| 59 | static inline void * | |
| 73208dfd | 60 | qla2xxx_copy_queues(struct qla_hw_data *ha, void *ptr) |
| a7a167bf | 61 | { |
| 73208dfd AC |
62 | struct req_que *req = ha->req_q_map[0]; |
| 63 | struct rsp_que *rsp = ha->rsp_q_map[0]; | |
| a7a167bf | 64 | /* Request queue. */ |
| 7b867cf7 | 65 | memcpy(ptr, req->ring, req->length * |
| a7a167bf AV |
66 | sizeof(request_t)); |
| 67 | ||
| 68 | /* Response queue. */ | |
| 7b867cf7 AC |
69 | ptr += req->length * sizeof(request_t); |
| 70 | memcpy(ptr, rsp->ring, rsp->length * | |
| a7a167bf AV |
71 | sizeof(response_t)); |
| 72 | ||
| 7b867cf7 | 73 | return ptr + (rsp->length * sizeof(response_t)); |
| a7a167bf | 74 | } |
| 1da177e4 | 75 | |
| c3a2f0df | 76 | static int |
| 7b867cf7 | 77 | qla24xx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint32_t *ram, |
| c5722708 | 78 | uint32_t ram_dwords, void **nxt) |
| c3a2f0df AV |
79 | { |
| 80 | int rval; | |
| c5722708 AV |
81 | uint32_t cnt, stat, timer, dwords, idx; |
| 82 | uint16_t mb0; | |
| c3a2f0df | 83 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
| c5722708 AV |
84 | dma_addr_t dump_dma = ha->gid_list_dma; |
| 85 | uint32_t *dump = (uint32_t *)ha->gid_list; | |
| c3a2f0df AV |
86 | |
| 87 | rval = QLA_SUCCESS; | |
| c5722708 | 88 | mb0 = 0; |
| c3a2f0df | 89 | |
| c5722708 | 90 | WRT_REG_WORD(®->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED); |
| c3a2f0df AV |
91 | clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); |
| 92 | ||
| 642ef983 | 93 | dwords = qla2x00_gid_list_size(ha) / 4; |
| c5722708 AV |
94 | for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS; |
| 95 | cnt += dwords, addr += dwords) { | |
| 96 | if (cnt + dwords > ram_dwords) | |
| 97 | dwords = ram_dwords - cnt; | |
| c3a2f0df | 98 | |
| c5722708 AV |
99 | WRT_REG_WORD(®->mailbox1, LSW(addr)); |
| 100 | WRT_REG_WORD(®->mailbox8, MSW(addr)); | |
| c3a2f0df | 101 | |
| c5722708 AV |
102 | WRT_REG_WORD(®->mailbox2, MSW(dump_dma)); |
| 103 | WRT_REG_WORD(®->mailbox3, LSW(dump_dma)); | |
| 104 | WRT_REG_WORD(®->mailbox6, MSW(MSD(dump_dma))); | |
| 105 | WRT_REG_WORD(®->mailbox7, LSW(MSD(dump_dma))); | |
| c3a2f0df | 106 | |
| c5722708 AV |
107 | WRT_REG_WORD(®->mailbox4, MSW(dwords)); |
| 108 | WRT_REG_WORD(®->mailbox5, LSW(dwords)); | |
| c3a2f0df AV |
109 | WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT); |
| 110 | ||
| 111 | for (timer = 6000000; timer; timer--) { | |
| 112 | /* Check for pending interrupts. */ | |
| 113 | stat = RD_REG_DWORD(®->host_status); | |
| 114 | if (stat & HSRX_RISC_INT) { | |
| 115 | stat &= 0xff; | |
| 116 | ||
| 117 | if (stat == 0x1 || stat == 0x2 || | |
| 118 | stat == 0x10 || stat == 0x11) { | |
| 119 | set_bit(MBX_INTERRUPT, | |
| 120 | &ha->mbx_cmd_flags); | |
| 121 | ||
| c5722708 | 122 | mb0 = RD_REG_WORD(®->mailbox0); |
| c3a2f0df AV |
123 | |
| 124 | WRT_REG_DWORD(®->hccr, | |
| 125 | HCCRX_CLR_RISC_INT); | |
| 126 | RD_REG_DWORD(®->hccr); | |
| 127 | break; | |
| 128 | } | |
| 129 | ||
| 130 | /* Clear this intr; it wasn't a mailbox intr */ | |
| 131 | WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT); | |
| 132 | RD_REG_DWORD(®->hccr); | |
| 133 | } | |
| 134 | udelay(5); | |
| 135 | } | |
| 136 | ||
| 137 | if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { | |
| c5722708 AV |
138 | rval = mb0 & MBS_MASK; |
| 139 | for (idx = 0; idx < dwords; idx++) | |
| 140 | ram[cnt + idx] = swab32(dump[idx]); | |
| c3a2f0df AV |
141 | } else { |
| 142 | rval = QLA_FUNCTION_FAILED; | |
| 143 | } | |
| 144 | } | |
| 145 | ||
| c5722708 | 146 | *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL; |
| c3a2f0df AV |
147 | return rval; |
| 148 | } | |
| 149 | ||
| c5722708 | 150 | static int |
| 7b867cf7 | 151 | qla24xx_dump_memory(struct qla_hw_data *ha, uint32_t *code_ram, |
| c5722708 AV |
152 | uint32_t cram_size, void **nxt) |
| 153 | { | |
| 154 | int rval; | |
| 155 | ||
| 156 | /* Code RAM. */ | |
| 157 | rval = qla24xx_dump_ram(ha, 0x20000, code_ram, cram_size / 4, nxt); | |
| 158 | if (rval != QLA_SUCCESS) | |
| 159 | return rval; | |
| 160 | ||
| 161 | /* External Memory. */ | |
| 162 | return qla24xx_dump_ram(ha, 0x100000, *nxt, | |
| 163 | ha->fw_memory_size - 0x100000 + 1, nxt); | |
| 164 | } | |
| 165 | ||
| c81d04c9 AV |
166 | static uint32_t * |
| 167 | qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase, | |
| 168 | uint32_t count, uint32_t *buf) | |
| 169 | { | |
| 170 | uint32_t __iomem *dmp_reg; | |
| 171 | ||
| 172 | WRT_REG_DWORD(®->iobase_addr, iobase); | |
| 173 | dmp_reg = ®->iobase_window; | |
| 174 | while (count--) | |
| 175 | *buf++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
| 176 | ||
| 177 | return buf; | |
| 178 | } | |
| 179 | ||
| 180 | static inline int | |
| 181 | qla24xx_pause_risc(struct device_reg_24xx __iomem *reg) | |
| 182 | { | |
| 183 | int rval = QLA_SUCCESS; | |
| 184 | uint32_t cnt; | |
| 185 | ||
| c3b058af | 186 | WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_PAUSE); |
| aed10881 AV |
187 | for (cnt = 30000; |
| 188 | ((RD_REG_DWORD(®->host_status) & HSRX_RISC_PAUSED) == 0) && | |
| c3b058af AV |
189 | rval == QLA_SUCCESS; cnt--) { |
| 190 | if (cnt) | |
| 191 | udelay(100); | |
| 192 | else | |
| 193 | rval = QLA_FUNCTION_TIMEOUT; | |
| c81d04c9 AV |
194 | } |
| 195 | ||
| 196 | return rval; | |
| 197 | } | |
| 198 | ||
| 199 | static int | |
| 7b867cf7 | 200 | qla24xx_soft_reset(struct qla_hw_data *ha) |
| c81d04c9 AV |
201 | { |
| 202 | int rval = QLA_SUCCESS; | |
| 203 | uint32_t cnt; | |
| 204 | uint16_t mb0, wd; | |
| 205 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | |
| 206 | ||
| 207 | /* Reset RISC. */ | |
| 208 | WRT_REG_DWORD(®->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); | |
| 209 | for (cnt = 0; cnt < 30000; cnt++) { | |
| 210 | if ((RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0) | |
| 211 | break; | |
| 212 | ||
| 213 | udelay(10); | |
| 214 | } | |
| 215 | ||
| 216 | WRT_REG_DWORD(®->ctrl_status, | |
| 217 | CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); | |
| 218 | pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); | |
| 219 | ||
| 220 | udelay(100); | |
| 221 | /* Wait for firmware to complete NVRAM accesses. */ | |
| 222 | mb0 = (uint32_t) RD_REG_WORD(®->mailbox0); | |
| 223 | for (cnt = 10000 ; cnt && mb0; cnt--) { | |
| 224 | udelay(5); | |
| 225 | mb0 = (uint32_t) RD_REG_WORD(®->mailbox0); | |
| 226 | barrier(); | |
| 227 | } | |
| 228 | ||
| 229 | /* Wait for soft-reset to complete. */ | |
| 230 | for (cnt = 0; cnt < 30000; cnt++) { | |
| 231 | if ((RD_REG_DWORD(®->ctrl_status) & | |
| 232 | CSRX_ISP_SOFT_RESET) == 0) | |
| 233 | break; | |
| 234 | ||
| 235 | udelay(10); | |
| 236 | } | |
| 237 | WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET); | |
| 238 | RD_REG_DWORD(®->hccr); /* PCI Posting. */ | |
| 239 | ||
| 240 | for (cnt = 30000; RD_REG_WORD(®->mailbox0) != 0 && | |
| 241 | rval == QLA_SUCCESS; cnt--) { | |
| 242 | if (cnt) | |
| 243 | udelay(100); | |
| 244 | else | |
| 245 | rval = QLA_FUNCTION_TIMEOUT; | |
| 246 | } | |
| 247 | ||
| 248 | return rval; | |
| 249 | } | |
| 250 | ||
| c5722708 | 251 | static int |
| 7b867cf7 | 252 | qla2xxx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint16_t *ram, |
| e18e963b | 253 | uint32_t ram_words, void **nxt) |
| c5722708 AV |
254 | { |
| 255 | int rval; | |
| 256 | uint32_t cnt, stat, timer, words, idx; | |
| 257 | uint16_t mb0; | |
| 258 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
| 259 | dma_addr_t dump_dma = ha->gid_list_dma; | |
| 260 | uint16_t *dump = (uint16_t *)ha->gid_list; | |
| 261 | ||
| 262 | rval = QLA_SUCCESS; | |
| 263 | mb0 = 0; | |
| 264 | ||
| 265 | WRT_MAILBOX_REG(ha, reg, 0, MBC_DUMP_RISC_RAM_EXTENDED); | |
| 266 | clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); | |
| 267 | ||
| 642ef983 | 268 | words = qla2x00_gid_list_size(ha) / 2; |
| c5722708 AV |
269 | for (cnt = 0; cnt < ram_words && rval == QLA_SUCCESS; |
| 270 | cnt += words, addr += words) { | |
| 271 | if (cnt + words > ram_words) | |
| 272 | words = ram_words - cnt; | |
| 273 | ||
| 274 | WRT_MAILBOX_REG(ha, reg, 1, LSW(addr)); | |
| 275 | WRT_MAILBOX_REG(ha, reg, 8, MSW(addr)); | |
| 276 | ||
| 277 | WRT_MAILBOX_REG(ha, reg, 2, MSW(dump_dma)); | |
| 278 | WRT_MAILBOX_REG(ha, reg, 3, LSW(dump_dma)); | |
| 279 | WRT_MAILBOX_REG(ha, reg, 6, MSW(MSD(dump_dma))); | |
| 280 | WRT_MAILBOX_REG(ha, reg, 7, LSW(MSD(dump_dma))); | |
| 281 | ||
| 282 | WRT_MAILBOX_REG(ha, reg, 4, words); | |
| 283 | WRT_REG_WORD(®->hccr, HCCR_SET_HOST_INT); | |
| 284 | ||
| 285 | for (timer = 6000000; timer; timer--) { | |
| 286 | /* Check for pending interrupts. */ | |
| 287 | stat = RD_REG_DWORD(®->u.isp2300.host_status); | |
| 288 | if (stat & HSR_RISC_INT) { | |
| 289 | stat &= 0xff; | |
| 290 | ||
| 291 | if (stat == 0x1 || stat == 0x2) { | |
| 292 | set_bit(MBX_INTERRUPT, | |
| 293 | &ha->mbx_cmd_flags); | |
| 294 | ||
| 295 | mb0 = RD_MAILBOX_REG(ha, reg, 0); | |
| 296 | ||
| 297 | /* Release mailbox registers. */ | |
| 298 | WRT_REG_WORD(®->semaphore, 0); | |
| 299 | WRT_REG_WORD(®->hccr, | |
| 300 | HCCR_CLR_RISC_INT); | |
| 301 | RD_REG_WORD(®->hccr); | |
| 302 | break; | |
| 303 | } else if (stat == 0x10 || stat == 0x11) { | |
| 304 | set_bit(MBX_INTERRUPT, | |
| 305 | &ha->mbx_cmd_flags); | |
| 306 | ||
| 307 | mb0 = RD_MAILBOX_REG(ha, reg, 0); | |
| 308 | ||
| 309 | WRT_REG_WORD(®->hccr, | |
| 310 | HCCR_CLR_RISC_INT); | |
| 311 | RD_REG_WORD(®->hccr); | |
| 312 | break; | |
| 313 | } | |
| 314 | ||
| 315 | /* clear this intr; it wasn't a mailbox intr */ | |
| 316 | WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); | |
| 317 | RD_REG_WORD(®->hccr); | |
| 318 | } | |
| 319 | udelay(5); | |
| 320 | } | |
| 321 | ||
| 322 | if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { | |
| 323 | rval = mb0 & MBS_MASK; | |
| 324 | for (idx = 0; idx < words; idx++) | |
| 325 | ram[cnt + idx] = swab16(dump[idx]); | |
| 326 | } else { | |
| 327 | rval = QLA_FUNCTION_FAILED; | |
| 328 | } | |
| 329 | } | |
| 330 | ||
| 331 | *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL; | |
| 332 | return rval; | |
| 333 | } | |
| 334 | ||
| c81d04c9 AV |
335 | static inline void |
| 336 | qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count, | |
| 337 | uint16_t *buf) | |
| 338 | { | |
| 339 | uint16_t __iomem *dmp_reg = ®->u.isp2300.fb_cmd; | |
| 340 | ||
| 341 | while (count--) | |
| 342 | *buf++ = htons(RD_REG_WORD(dmp_reg++)); | |
| 343 | } | |
| 344 | ||
| bb99de67 AV |
345 | static inline void * |
| 346 | qla24xx_copy_eft(struct qla_hw_data *ha, void *ptr) | |
| 347 | { | |
| 348 | if (!ha->eft) | |
| 349 | return ptr; | |
| 350 | ||
| 351 | memcpy(ptr, ha->eft, ntohl(ha->fw_dump->eft_size)); | |
| 352 | return ptr + ntohl(ha->fw_dump->eft_size); | |
| 353 | } | |
| 354 | ||
| 355 | static inline void * | |
| 356 | qla25xx_copy_fce(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain) | |
| 357 | { | |
| 358 | uint32_t cnt; | |
| 359 | uint32_t *iter_reg; | |
| 360 | struct qla2xxx_fce_chain *fcec = ptr; | |
| 361 | ||
| 362 | if (!ha->fce) | |
| 363 | return ptr; | |
| 364 | ||
| 365 | *last_chain = &fcec->type; | |
| 366 | fcec->type = __constant_htonl(DUMP_CHAIN_FCE); | |
| 367 | fcec->chain_size = htonl(sizeof(struct qla2xxx_fce_chain) + | |
| 368 | fce_calc_size(ha->fce_bufs)); | |
| 369 | fcec->size = htonl(fce_calc_size(ha->fce_bufs)); | |
| 370 | fcec->addr_l = htonl(LSD(ha->fce_dma)); | |
| 371 | fcec->addr_h = htonl(MSD(ha->fce_dma)); | |
| 372 | ||
| 373 | iter_reg = fcec->eregs; | |
| 374 | for (cnt = 0; cnt < 8; cnt++) | |
| 375 | *iter_reg++ = htonl(ha->fce_mb[cnt]); | |
| 376 | ||
| 377 | memcpy(iter_reg, ha->fce, ntohl(fcec->size)); | |
| 378 | ||
| 3cb0a67d | 379 | return (char *)iter_reg + ntohl(fcec->size); |
| bb99de67 AV |
380 | } |
| 381 | ||
| 050c9bb1 GM |
382 | static inline void * |
| 383 | qla25xx_copy_mqueues(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain) | |
| 384 | { | |
| 385 | struct qla2xxx_mqueue_chain *q; | |
| 386 | struct qla2xxx_mqueue_header *qh; | |
| 387 | struct req_que *req; | |
| 388 | struct rsp_que *rsp; | |
| 389 | int que; | |
| 390 | ||
| 391 | if (!ha->mqenable) | |
| 392 | return ptr; | |
| 393 | ||
| 394 | /* Request queues */ | |
| 395 | for (que = 1; que < ha->max_req_queues; que++) { | |
| 396 | req = ha->req_q_map[que]; | |
| 397 | if (!req) | |
| 398 | break; | |
| 399 | ||
| 400 | /* Add chain. */ | |
| 401 | q = ptr; | |
| 402 | *last_chain = &q->type; | |
| 403 | q->type = __constant_htonl(DUMP_CHAIN_QUEUE); | |
| 404 | q->chain_size = htonl( | |
| 405 | sizeof(struct qla2xxx_mqueue_chain) + | |
| 406 | sizeof(struct qla2xxx_mqueue_header) + | |
| 407 | (req->length * sizeof(request_t))); | |
| 408 | ptr += sizeof(struct qla2xxx_mqueue_chain); | |
| 409 | ||
| 410 | /* Add header. */ | |
| 411 | qh = ptr; | |
| 412 | qh->queue = __constant_htonl(TYPE_REQUEST_QUEUE); | |
| 413 | qh->number = htonl(que); | |
| 414 | qh->size = htonl(req->length * sizeof(request_t)); | |
| 415 | ptr += sizeof(struct qla2xxx_mqueue_header); | |
| 416 | ||
| 417 | /* Add data. */ | |
| 418 | memcpy(ptr, req->ring, req->length * sizeof(request_t)); | |
| 419 | ptr += req->length * sizeof(request_t); | |
| 420 | } | |
| 421 | ||
| 422 | /* Response queues */ | |
| 423 | for (que = 1; que < ha->max_rsp_queues; que++) { | |
| 424 | rsp = ha->rsp_q_map[que]; | |
| 425 | if (!rsp) | |
| 426 | break; | |
| 427 | ||
| 428 | /* Add chain. */ | |
| 429 | q = ptr; | |
| 430 | *last_chain = &q->type; | |
| 431 | q->type = __constant_htonl(DUMP_CHAIN_QUEUE); | |
| 432 | q->chain_size = htonl( | |
| 433 | sizeof(struct qla2xxx_mqueue_chain) + | |
| 434 | sizeof(struct qla2xxx_mqueue_header) + | |
| 435 | (rsp->length * sizeof(response_t))); | |
| 436 | ptr += sizeof(struct qla2xxx_mqueue_chain); | |
| 437 | ||
| 438 | /* Add header. */ | |
| 439 | qh = ptr; | |
| 440 | qh->queue = __constant_htonl(TYPE_RESPONSE_QUEUE); | |
| 441 | qh->number = htonl(que); | |
| 442 | qh->size = htonl(rsp->length * sizeof(response_t)); | |
| 443 | ptr += sizeof(struct qla2xxx_mqueue_header); | |
| 444 | ||
| 445 | /* Add data. */ | |
| 446 | memcpy(ptr, rsp->ring, rsp->length * sizeof(response_t)); | |
| 447 | ptr += rsp->length * sizeof(response_t); | |
| 448 | } | |
| 449 | ||
| 450 | return ptr; | |
| 451 | } | |
| 452 | ||
| d63ab533 AV |
453 | static inline void * |
| 454 | qla25xx_copy_mq(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain) | |
| 455 | { | |
| 456 | uint32_t cnt, que_idx; | |
| 2afa19a9 | 457 | uint8_t que_cnt; |
| d63ab533 AV |
458 | struct qla2xxx_mq_chain *mq = ptr; |
| 459 | struct device_reg_25xxmq __iomem *reg; | |
| 460 | ||
| 6246b8a1 | 461 | if (!ha->mqenable || IS_QLA83XX(ha)) |
| d63ab533 AV |
462 | return ptr; |
| 463 | ||
| 464 | mq = ptr; | |
| 465 | *last_chain = &mq->type; | |
| 466 | mq->type = __constant_htonl(DUMP_CHAIN_MQ); | |
| 467 | mq->chain_size = __constant_htonl(sizeof(struct qla2xxx_mq_chain)); | |
| 468 | ||
| 2afa19a9 AC |
469 | que_cnt = ha->max_req_queues > ha->max_rsp_queues ? |
| 470 | ha->max_req_queues : ha->max_rsp_queues; | |
| d63ab533 AV |
471 | mq->count = htonl(que_cnt); |
| 472 | for (cnt = 0; cnt < que_cnt; cnt++) { | |
| 473 | reg = (struct device_reg_25xxmq *) ((void *) | |
| 474 | ha->mqiobase + cnt * QLA_QUE_PAGE); | |
| 475 | que_idx = cnt * 4; | |
| 476 | mq->qregs[que_idx] = htonl(RD_REG_DWORD(®->req_q_in)); | |
| 477 | mq->qregs[que_idx+1] = htonl(RD_REG_DWORD(®->req_q_out)); | |
| 478 | mq->qregs[que_idx+2] = htonl(RD_REG_DWORD(®->rsp_q_in)); | |
| 479 | mq->qregs[que_idx+3] = htonl(RD_REG_DWORD(®->rsp_q_out)); | |
| 480 | } | |
| 481 | ||
| 482 | return ptr + sizeof(struct qla2xxx_mq_chain); | |
| 483 | } | |
| 484 | ||
| 08de2844 | 485 | void |
| 3420d36c AV |
486 | qla2xxx_dump_post_process(scsi_qla_host_t *vha, int rval) |
| 487 | { | |
| 488 | struct qla_hw_data *ha = vha->hw; | |
| 489 | ||
| 490 | if (rval != QLA_SUCCESS) { | |
| 7c3df132 SK |
491 | ql_log(ql_log_warn, vha, 0xd000, |
| 492 | "Failed to dump firmware (%x).\n", rval); | |
| 3420d36c AV |
493 | ha->fw_dumped = 0; |
| 494 | } else { | |
| 7c3df132 | 495 | ql_log(ql_log_info, vha, 0xd001, |
| 3420d36c AV |
496 | "Firmware dump saved to temp buffer (%ld/%p).\n", |
| 497 | vha->host_no, ha->fw_dump); | |
| 498 | ha->fw_dumped = 1; | |
| 499 | qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP); | |
| 500 | } | |
| 501 | } | |
| 502 | ||
| 1da177e4 LT |
503 | /** |
| 504 | * qla2300_fw_dump() - Dumps binary data from the 2300 firmware. | |
| 505 | * @ha: HA context | |
| 506 | * @hardware_locked: Called with the hardware_lock | |
| 507 | */ | |
| 508 | void | |
| 7b867cf7 | 509 | qla2300_fw_dump(scsi_qla_host_t *vha, int hardware_locked) |
| 1da177e4 LT |
510 | { |
| 511 | int rval; | |
| c5722708 | 512 | uint32_t cnt; |
| 7b867cf7 | 513 | struct qla_hw_data *ha = vha->hw; |
| 3d71644c | 514 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
| 1da177e4 LT |
515 | uint16_t __iomem *dmp_reg; |
| 516 | unsigned long flags; | |
| 517 | struct qla2300_fw_dump *fw; | |
| c5722708 | 518 | void *nxt; |
| 73208dfd | 519 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); |
| 1da177e4 | 520 | |
| 1da177e4 LT |
521 | flags = 0; |
| 522 | ||
| 523 | if (!hardware_locked) | |
| 524 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
| 525 | ||
| d4e3e04d | 526 | if (!ha->fw_dump) { |
| 7c3df132 SK |
527 | ql_log(ql_log_warn, vha, 0xd002, |
| 528 | "No buffer available for dump.\n"); | |
| 1da177e4 LT |
529 | goto qla2300_fw_dump_failed; |
| 530 | } | |
| 531 | ||
| d4e3e04d | 532 | if (ha->fw_dumped) { |
| 7c3df132 SK |
533 | ql_log(ql_log_warn, vha, 0xd003, |
| 534 | "Firmware has been previously dumped (%p) " | |
| 535 | "-- ignoring request.\n", | |
| 536 | ha->fw_dump); | |
| 1da177e4 LT |
537 | goto qla2300_fw_dump_failed; |
| 538 | } | |
| a7a167bf AV |
539 | fw = &ha->fw_dump->isp.isp23; |
| 540 | qla2xxx_prep_dump(ha, ha->fw_dump); | |
| 1da177e4 LT |
541 | |
| 542 | rval = QLA_SUCCESS; | |
| a7a167bf | 543 | fw->hccr = htons(RD_REG_WORD(®->hccr)); |
| 1da177e4 LT |
544 | |
| 545 | /* Pause RISC. */ | |
| fa2a1ce5 | 546 | WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); |
| 1da177e4 LT |
547 | if (IS_QLA2300(ha)) { |
| 548 | for (cnt = 30000; | |
| 549 | (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && | |
| 550 | rval == QLA_SUCCESS; cnt--) { | |
| 551 | if (cnt) | |
| 552 | udelay(100); | |
| 553 | else | |
| 554 | rval = QLA_FUNCTION_TIMEOUT; | |
| 555 | } | |
| 556 | } else { | |
| 557 | RD_REG_WORD(®->hccr); /* PCI Posting. */ | |
| 558 | udelay(10); | |
| 559 | } | |
| 560 | ||
| 561 | if (rval == QLA_SUCCESS) { | |
| c81d04c9 | 562 | dmp_reg = ®->flash_address; |
| fa2a1ce5 | 563 | for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++) |
| a7a167bf | 564 | fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
| 1da177e4 | 565 | |
| c81d04c9 | 566 | dmp_reg = ®->u.isp2300.req_q_in; |
| fa2a1ce5 | 567 | for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++) |
| a7a167bf | 568 | fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
| 1da177e4 | 569 | |
| c81d04c9 | 570 | dmp_reg = ®->u.isp2300.mailbox0; |
| fa2a1ce5 | 571 | for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) |
| a7a167bf | 572 | fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
| 1da177e4 LT |
573 | |
| 574 | WRT_REG_WORD(®->ctrl_status, 0x40); | |
| c81d04c9 | 575 | qla2xxx_read_window(reg, 32, fw->resp_dma_reg); |
| 1da177e4 LT |
576 | |
| 577 | WRT_REG_WORD(®->ctrl_status, 0x50); | |
| c81d04c9 | 578 | qla2xxx_read_window(reg, 48, fw->dma_reg); |
| 1da177e4 LT |
579 | |
| 580 | WRT_REG_WORD(®->ctrl_status, 0x00); | |
| c81d04c9 | 581 | dmp_reg = ®->risc_hw; |
| fa2a1ce5 | 582 | for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++) |
| a7a167bf | 583 | fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
| 1da177e4 | 584 | |
| fa2a1ce5 | 585 | WRT_REG_WORD(®->pcr, 0x2000); |
| c81d04c9 | 586 | qla2xxx_read_window(reg, 16, fw->risc_gp0_reg); |
| 1da177e4 | 587 | |
| fa2a1ce5 | 588 | WRT_REG_WORD(®->pcr, 0x2200); |
| c81d04c9 | 589 | qla2xxx_read_window(reg, 16, fw->risc_gp1_reg); |
| 1da177e4 | 590 | |
| fa2a1ce5 | 591 | WRT_REG_WORD(®->pcr, 0x2400); |
| c81d04c9 | 592 | qla2xxx_read_window(reg, 16, fw->risc_gp2_reg); |
| 1da177e4 | 593 | |
| fa2a1ce5 | 594 | WRT_REG_WORD(®->pcr, 0x2600); |
| c81d04c9 | 595 | qla2xxx_read_window(reg, 16, fw->risc_gp3_reg); |
| 1da177e4 | 596 | |
| fa2a1ce5 | 597 | WRT_REG_WORD(®->pcr, 0x2800); |
| c81d04c9 | 598 | qla2xxx_read_window(reg, 16, fw->risc_gp4_reg); |
| 1da177e4 | 599 | |
| fa2a1ce5 | 600 | WRT_REG_WORD(®->pcr, 0x2A00); |
| c81d04c9 | 601 | qla2xxx_read_window(reg, 16, fw->risc_gp5_reg); |
| 1da177e4 | 602 | |
| fa2a1ce5 | 603 | WRT_REG_WORD(®->pcr, 0x2C00); |
| c81d04c9 | 604 | qla2xxx_read_window(reg, 16, fw->risc_gp6_reg); |
| 1da177e4 | 605 | |
| fa2a1ce5 | 606 | WRT_REG_WORD(®->pcr, 0x2E00); |
| c81d04c9 | 607 | qla2xxx_read_window(reg, 16, fw->risc_gp7_reg); |
| 1da177e4 | 608 | |
| fa2a1ce5 | 609 | WRT_REG_WORD(®->ctrl_status, 0x10); |
| c81d04c9 | 610 | qla2xxx_read_window(reg, 64, fw->frame_buf_hdw_reg); |
| 1da177e4 | 611 | |
| fa2a1ce5 | 612 | WRT_REG_WORD(®->ctrl_status, 0x20); |
| c81d04c9 | 613 | qla2xxx_read_window(reg, 64, fw->fpm_b0_reg); |
| 1da177e4 | 614 | |
| fa2a1ce5 | 615 | WRT_REG_WORD(®->ctrl_status, 0x30); |
| c81d04c9 | 616 | qla2xxx_read_window(reg, 64, fw->fpm_b1_reg); |
| 1da177e4 LT |
617 | |
| 618 | /* Reset RISC. */ | |
| 619 | WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); | |
| 620 | for (cnt = 0; cnt < 30000; cnt++) { | |
| 621 | if ((RD_REG_WORD(®->ctrl_status) & | |
| 622 | CSR_ISP_SOFT_RESET) == 0) | |
| 623 | break; | |
| 624 | ||
| 625 | udelay(10); | |
| 626 | } | |
| 627 | } | |
| 628 | ||
| 629 | if (!IS_QLA2300(ha)) { | |
| 630 | for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 && | |
| 631 | rval == QLA_SUCCESS; cnt--) { | |
| 632 | if (cnt) | |
| 633 | udelay(100); | |
| 634 | else | |
| 635 | rval = QLA_FUNCTION_TIMEOUT; | |
| 636 | } | |
| 637 | } | |
| 638 | ||
| c5722708 AV |
639 | /* Get RISC SRAM. */ |
| 640 | if (rval == QLA_SUCCESS) | |
| 641 | rval = qla2xxx_dump_ram(ha, 0x800, fw->risc_ram, | |
| 642 | sizeof(fw->risc_ram) / 2, &nxt); | |
| 1da177e4 | 643 | |
| c5722708 AV |
644 | /* Get stack SRAM. */ |
| 645 | if (rval == QLA_SUCCESS) | |
| 646 | rval = qla2xxx_dump_ram(ha, 0x10000, fw->stack_ram, | |
| 647 | sizeof(fw->stack_ram) / 2, &nxt); | |
| 1da177e4 | 648 | |
| c5722708 AV |
649 | /* Get data SRAM. */ |
| 650 | if (rval == QLA_SUCCESS) | |
| 651 | rval = qla2xxx_dump_ram(ha, 0x11000, fw->data_ram, | |
| 652 | ha->fw_memory_size - 0x11000 + 1, &nxt); | |
| 1da177e4 | 653 | |
| a7a167bf | 654 | if (rval == QLA_SUCCESS) |
| 73208dfd | 655 | qla2xxx_copy_queues(ha, nxt); |
| a7a167bf | 656 | |
| 3420d36c | 657 | qla2xxx_dump_post_process(base_vha, rval); |
| 1da177e4 LT |
658 | |
| 659 | qla2300_fw_dump_failed: | |
| 660 | if (!hardware_locked) | |
| 661 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
| 662 | } | |
| 663 | ||
| 1da177e4 LT |
664 | /** |
| 665 | * qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware. | |
| 666 | * @ha: HA context | |
| 667 | * @hardware_locked: Called with the hardware_lock | |
| 668 | */ | |
| 669 | void | |
| 7b867cf7 | 670 | qla2100_fw_dump(scsi_qla_host_t *vha, int hardware_locked) |
| 1da177e4 LT |
671 | { |
| 672 | int rval; | |
| 673 | uint32_t cnt, timer; | |
| 674 | uint16_t risc_address; | |
| 675 | uint16_t mb0, mb2; | |
| 7b867cf7 | 676 | struct qla_hw_data *ha = vha->hw; |
| 3d71644c | 677 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
| 1da177e4 LT |
678 | uint16_t __iomem *dmp_reg; |
| 679 | unsigned long flags; | |
| 680 | struct qla2100_fw_dump *fw; | |
| 73208dfd | 681 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); |
| 1da177e4 LT |
682 | |
| 683 | risc_address = 0; | |
| 684 | mb0 = mb2 = 0; | |
| 685 | flags = 0; | |
| 686 | ||
| 687 | if (!hardware_locked) | |
| 688 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
| 689 | ||
| d4e3e04d | 690 | if (!ha->fw_dump) { |
| 7c3df132 SK |
691 | ql_log(ql_log_warn, vha, 0xd004, |
| 692 | "No buffer available for dump.\n"); | |
| 1da177e4 LT |
693 | goto qla2100_fw_dump_failed; |
| 694 | } | |
| 695 | ||
| d4e3e04d | 696 | if (ha->fw_dumped) { |
| 7c3df132 SK |
697 | ql_log(ql_log_warn, vha, 0xd005, |
| 698 | "Firmware has been previously dumped (%p) " | |
| 699 | "-- ignoring request.\n", | |
| 700 | ha->fw_dump); | |
| 1da177e4 LT |
701 | goto qla2100_fw_dump_failed; |
| 702 | } | |
| a7a167bf AV |
703 | fw = &ha->fw_dump->isp.isp21; |
| 704 | qla2xxx_prep_dump(ha, ha->fw_dump); | |
| 1da177e4 LT |
705 | |
| 706 | rval = QLA_SUCCESS; | |
| a7a167bf | 707 | fw->hccr = htons(RD_REG_WORD(®->hccr)); |
| 1da177e4 LT |
708 | |
| 709 | /* Pause RISC. */ | |
| fa2a1ce5 | 710 | WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); |
| 1da177e4 LT |
711 | for (cnt = 30000; (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && |
| 712 | rval == QLA_SUCCESS; cnt--) { | |
| 713 | if (cnt) | |
| 714 | udelay(100); | |
| 715 | else | |
| 716 | rval = QLA_FUNCTION_TIMEOUT; | |
| 717 | } | |
| 718 | if (rval == QLA_SUCCESS) { | |
| c81d04c9 | 719 | dmp_reg = ®->flash_address; |
| fa2a1ce5 | 720 | for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++) |
| a7a167bf | 721 | fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
| 1da177e4 | 722 | |
| c81d04c9 | 723 | dmp_reg = ®->u.isp2100.mailbox0; |
| 1da177e4 | 724 | for (cnt = 0; cnt < ha->mbx_count; cnt++) { |
| c81d04c9 AV |
725 | if (cnt == 8) |
| 726 | dmp_reg = ®->u_end.isp2200.mailbox8; | |
| 727 | ||
| a7a167bf | 728 | fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
| 1da177e4 LT |
729 | } |
| 730 | ||
| c81d04c9 | 731 | dmp_reg = ®->u.isp2100.unused_2[0]; |
| fa2a1ce5 | 732 | for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++) |
| a7a167bf | 733 | fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
| 1da177e4 LT |
734 | |
| 735 | WRT_REG_WORD(®->ctrl_status, 0x00); | |
| c81d04c9 | 736 | dmp_reg = ®->risc_hw; |
| fa2a1ce5 | 737 | for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++) |
| a7a167bf | 738 | fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
| 1da177e4 | 739 | |
| fa2a1ce5 | 740 | WRT_REG_WORD(®->pcr, 0x2000); |
| c81d04c9 | 741 | qla2xxx_read_window(reg, 16, fw->risc_gp0_reg); |
| 1da177e4 | 742 | |
| fa2a1ce5 | 743 | WRT_REG_WORD(®->pcr, 0x2100); |
| c81d04c9 | 744 | qla2xxx_read_window(reg, 16, fw->risc_gp1_reg); |
| 1da177e4 | 745 | |
| fa2a1ce5 | 746 | WRT_REG_WORD(®->pcr, 0x2200); |
| c81d04c9 | 747 | qla2xxx_read_window(reg, 16, fw->risc_gp2_reg); |
| 1da177e4 | 748 | |
| fa2a1ce5 | 749 | WRT_REG_WORD(®->pcr, 0x2300); |
| c81d04c9 | 750 | qla2xxx_read_window(reg, 16, fw->risc_gp3_reg); |
| 1da177e4 | 751 | |
| fa2a1ce5 | 752 | WRT_REG_WORD(®->pcr, 0x2400); |
| c81d04c9 | 753 | qla2xxx_read_window(reg, 16, fw->risc_gp4_reg); |
| 1da177e4 | 754 | |
| fa2a1ce5 | 755 | WRT_REG_WORD(®->pcr, 0x2500); |
| c81d04c9 | 756 | qla2xxx_read_window(reg, 16, fw->risc_gp5_reg); |
| 1da177e4 | 757 | |
| fa2a1ce5 | 758 | WRT_REG_WORD(®->pcr, 0x2600); |
| c81d04c9 | 759 | qla2xxx_read_window(reg, 16, fw->risc_gp6_reg); |
| 1da177e4 | 760 | |
| fa2a1ce5 | 761 | WRT_REG_WORD(®->pcr, 0x2700); |
| c81d04c9 | 762 | qla2xxx_read_window(reg, 16, fw->risc_gp7_reg); |
| 1da177e4 | 763 | |
| fa2a1ce5 | 764 | WRT_REG_WORD(®->ctrl_status, 0x10); |
| c81d04c9 | 765 | qla2xxx_read_window(reg, 16, fw->frame_buf_hdw_reg); |
| 1da177e4 | 766 | |
| fa2a1ce5 | 767 | WRT_REG_WORD(®->ctrl_status, 0x20); |
| c81d04c9 | 768 | qla2xxx_read_window(reg, 64, fw->fpm_b0_reg); |
| 1da177e4 | 769 | |
| fa2a1ce5 | 770 | WRT_REG_WORD(®->ctrl_status, 0x30); |
| c81d04c9 | 771 | qla2xxx_read_window(reg, 64, fw->fpm_b1_reg); |
| 1da177e4 LT |
772 | |
| 773 | /* Reset the ISP. */ | |
| 774 | WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); | |
| 775 | } | |
| 776 | ||
| 777 | for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 && | |
| 778 | rval == QLA_SUCCESS; cnt--) { | |
| 779 | if (cnt) | |
| 780 | udelay(100); | |
| 781 | else | |
| 782 | rval = QLA_FUNCTION_TIMEOUT; | |
| 783 | } | |
| 784 | ||
| 785 | /* Pause RISC. */ | |
| 786 | if (rval == QLA_SUCCESS && (IS_QLA2200(ha) || (IS_QLA2100(ha) && | |
| 787 | (RD_REG_WORD(®->mctr) & (BIT_1 | BIT_0)) != 0))) { | |
| 788 | ||
| fa2a1ce5 | 789 | WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); |
| 1da177e4 LT |
790 | for (cnt = 30000; |
| 791 | (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && | |
| 792 | rval == QLA_SUCCESS; cnt--) { | |
| 793 | if (cnt) | |
| 794 | udelay(100); | |
| 795 | else | |
| 796 | rval = QLA_FUNCTION_TIMEOUT; | |
| 797 | } | |
| 798 | if (rval == QLA_SUCCESS) { | |
| 799 | /* Set memory configuration and timing. */ | |
| 800 | if (IS_QLA2100(ha)) | |
| 801 | WRT_REG_WORD(®->mctr, 0xf1); | |
| 802 | else | |
| 803 | WRT_REG_WORD(®->mctr, 0xf2); | |
| 804 | RD_REG_WORD(®->mctr); /* PCI Posting. */ | |
| 805 | ||
| 806 | /* Release RISC. */ | |
| 807 | WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); | |
| 808 | } | |
| 809 | } | |
| 810 | ||
| 811 | if (rval == QLA_SUCCESS) { | |
| 812 | /* Get RISC SRAM. */ | |
| 813 | risc_address = 0x1000; | |
| 814 | WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD); | |
| 815 | clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); | |
| 816 | } | |
| 817 | for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS; | |
| 818 | cnt++, risc_address++) { | |
| 819 | WRT_MAILBOX_REG(ha, reg, 1, risc_address); | |
| 820 | WRT_REG_WORD(®->hccr, HCCR_SET_HOST_INT); | |
| 821 | ||
| 822 | for (timer = 6000000; timer != 0; timer--) { | |
| 823 | /* Check for pending interrupts. */ | |
| 824 | if (RD_REG_WORD(®->istatus) & ISR_RISC_INT) { | |
| 825 | if (RD_REG_WORD(®->semaphore) & BIT_0) { | |
| 826 | set_bit(MBX_INTERRUPT, | |
| 827 | &ha->mbx_cmd_flags); | |
| 828 | ||
| 829 | mb0 = RD_MAILBOX_REG(ha, reg, 0); | |
| 830 | mb2 = RD_MAILBOX_REG(ha, reg, 2); | |
| 831 | ||
| 832 | WRT_REG_WORD(®->semaphore, 0); | |
| 833 | WRT_REG_WORD(®->hccr, | |
| 834 | HCCR_CLR_RISC_INT); | |
| 835 | RD_REG_WORD(®->hccr); | |
| 836 | break; | |
| 837 | } | |
| 838 | WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); | |
| 839 | RD_REG_WORD(®->hccr); | |
| 840 | } | |
| 841 | udelay(5); | |
| 842 | } | |
| 843 | ||
| 844 | if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { | |
| 845 | rval = mb0 & MBS_MASK; | |
| a7a167bf | 846 | fw->risc_ram[cnt] = htons(mb2); |
| 1da177e4 LT |
847 | } else { |
| 848 | rval = QLA_FUNCTION_FAILED; | |
| 849 | } | |
| 850 | } | |
| 851 | ||
| a7a167bf | 852 | if (rval == QLA_SUCCESS) |
| 73208dfd | 853 | qla2xxx_copy_queues(ha, &fw->risc_ram[cnt]); |
| a7a167bf | 854 | |
| 3420d36c | 855 | qla2xxx_dump_post_process(base_vha, rval); |
| 1da177e4 LT |
856 | |
| 857 | qla2100_fw_dump_failed: | |
| 858 | if (!hardware_locked) | |
| 859 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
| 860 | } | |
| 861 | ||
| 6d9b61ed | 862 | void |
| 7b867cf7 | 863 | qla24xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) |
| 6d9b61ed AV |
864 | { |
| 865 | int rval; | |
| c3a2f0df | 866 | uint32_t cnt; |
| 6d9b61ed | 867 | uint32_t risc_address; |
| 7b867cf7 | 868 | struct qla_hw_data *ha = vha->hw; |
| 6d9b61ed AV |
869 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
| 870 | uint32_t __iomem *dmp_reg; | |
| 871 | uint32_t *iter_reg; | |
| 872 | uint16_t __iomem *mbx_reg; | |
| 873 | unsigned long flags; | |
| 874 | struct qla24xx_fw_dump *fw; | |
| 875 | uint32_t ext_mem_cnt; | |
| c3a2f0df | 876 | void *nxt; |
| 73208dfd | 877 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); |
| 6d9b61ed | 878 | |
| a9083016 GM |
879 | if (IS_QLA82XX(ha)) |
| 880 | return; | |
| 881 | ||
| 6d9b61ed | 882 | risc_address = ext_mem_cnt = 0; |
| 6d9b61ed AV |
883 | flags = 0; |
| 884 | ||
| 885 | if (!hardware_locked) | |
| 886 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
| 887 | ||
| d4e3e04d | 888 | if (!ha->fw_dump) { |
| 7c3df132 SK |
889 | ql_log(ql_log_warn, vha, 0xd006, |
| 890 | "No buffer available for dump.\n"); | |
| 6d9b61ed AV |
891 | goto qla24xx_fw_dump_failed; |
| 892 | } | |
| 893 | ||
| 894 | if (ha->fw_dumped) { | |
| 7c3df132 SK |
895 | ql_log(ql_log_warn, vha, 0xd007, |
| 896 | "Firmware has been previously dumped (%p) " | |
| 897 | "-- ignoring request.\n", | |
| 898 | ha->fw_dump); | |
| 6d9b61ed AV |
899 | goto qla24xx_fw_dump_failed; |
| 900 | } | |
| a7a167bf AV |
901 | fw = &ha->fw_dump->isp.isp24; |
| 902 | qla2xxx_prep_dump(ha, ha->fw_dump); | |
| 6d9b61ed | 903 | |
| a7a167bf | 904 | fw->host_status = htonl(RD_REG_DWORD(®->host_status)); |
| 6d9b61ed AV |
905 | |
| 906 | /* Pause RISC. */ | |
| c81d04c9 AV |
907 | rval = qla24xx_pause_risc(reg); |
| 908 | if (rval != QLA_SUCCESS) | |
| 909 | goto qla24xx_fw_dump_failed_0; | |
| 910 | ||
| 911 | /* Host interface registers. */ | |
| 912 | dmp_reg = ®->flash_addr; | |
| 913 | for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) | |
| 914 | fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); | |
| 915 | ||
| 916 | /* Disable interrupts. */ | |
| 917 | WRT_REG_DWORD(®->ictrl, 0); | |
| 918 | RD_REG_DWORD(®->ictrl); | |
| 919 | ||
| 920 | /* Shadow registers. */ | |
| 921 | WRT_REG_DWORD(®->iobase_addr, 0x0F70); | |
| 922 | RD_REG_DWORD(®->iobase_addr); | |
| 923 | WRT_REG_DWORD(®->iobase_select, 0xB0000000); | |
| 924 | fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 925 | ||
| 926 | WRT_REG_DWORD(®->iobase_select, 0xB0100000); | |
| 927 | fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 928 | ||
| 929 | WRT_REG_DWORD(®->iobase_select, 0xB0200000); | |
| 930 | fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 931 | ||
| 932 | WRT_REG_DWORD(®->iobase_select, 0xB0300000); | |
| 933 | fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 934 | ||
| 935 | WRT_REG_DWORD(®->iobase_select, 0xB0400000); | |
| 936 | fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 937 | ||
| 938 | WRT_REG_DWORD(®->iobase_select, 0xB0500000); | |
| 939 | fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 940 | ||
| 941 | WRT_REG_DWORD(®->iobase_select, 0xB0600000); | |
| 942 | fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 943 | ||
| 944 | /* Mailbox registers. */ | |
| 945 | mbx_reg = ®->mailbox0; | |
| 946 | for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) | |
| 947 | fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); | |
| 948 | ||
| 949 | /* Transfer sequence registers. */ | |
| 950 | iter_reg = fw->xseq_gp_reg; | |
| 951 | iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); | |
| 952 | iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); | |
| 953 | iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); | |
| 954 | iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); | |
| 955 | iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); | |
| 956 | iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); | |
| 957 | iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); | |
| 958 | qla24xx_read_window(reg, 0xBF70, 16, iter_reg); | |
| 959 | ||
| 960 | qla24xx_read_window(reg, 0xBFE0, 16, fw->xseq_0_reg); | |
| 961 | qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); | |
| 962 | ||
| 963 | /* Receive sequence registers. */ | |
| 964 | iter_reg = fw->rseq_gp_reg; | |
| 965 | iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); | |
| 966 | iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); | |
| 967 | iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); | |
| 968 | iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); | |
| 969 | iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); | |
| 970 | iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); | |
| 971 | iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); | |
| 972 | qla24xx_read_window(reg, 0xFF70, 16, iter_reg); | |
| 973 | ||
| 974 | qla24xx_read_window(reg, 0xFFD0, 16, fw->rseq_0_reg); | |
| 975 | qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); | |
| 976 | qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); | |
| 977 | ||
| 978 | /* Command DMA registers. */ | |
| 979 | qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg); | |
| 980 | ||
| 981 | /* Queues. */ | |
| 982 | iter_reg = fw->req0_dma_reg; | |
| 983 | iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); | |
| 984 | dmp_reg = ®->iobase_q; | |
| 985 | for (cnt = 0; cnt < 7; cnt++) | |
| 986 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
| 987 | ||
| 988 | iter_reg = fw->resp0_dma_reg; | |
| 989 | iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); | |
| 990 | dmp_reg = ®->iobase_q; | |
| 991 | for (cnt = 0; cnt < 7; cnt++) | |
| 992 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
| 993 | ||
| 994 | iter_reg = fw->req1_dma_reg; | |
| 995 | iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); | |
| 996 | dmp_reg = ®->iobase_q; | |
| 997 | for (cnt = 0; cnt < 7; cnt++) | |
| 998 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
| 999 | ||
| 1000 | /* Transmit DMA registers. */ | |
| 1001 | iter_reg = fw->xmt0_dma_reg; | |
| 1002 | iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); | |
| 1003 | qla24xx_read_window(reg, 0x7610, 16, iter_reg); | |
| 1004 | ||
| 1005 | iter_reg = fw->xmt1_dma_reg; | |
| 1006 | iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); | |
| 1007 | qla24xx_read_window(reg, 0x7630, 16, iter_reg); | |
| 1008 | ||
| 1009 | iter_reg = fw->xmt2_dma_reg; | |
| 1010 | iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); | |
| 1011 | qla24xx_read_window(reg, 0x7650, 16, iter_reg); | |
| 1012 | ||
| 1013 | iter_reg = fw->xmt3_dma_reg; | |
| 1014 | iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); | |
| 1015 | qla24xx_read_window(reg, 0x7670, 16, iter_reg); | |
| 1016 | ||
| 1017 | iter_reg = fw->xmt4_dma_reg; | |
| 1018 | iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); | |
| 1019 | qla24xx_read_window(reg, 0x7690, 16, iter_reg); | |
| 1020 | ||
| 1021 | qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); | |
| 1022 | ||
| 1023 | /* Receive DMA registers. */ | |
| 1024 | iter_reg = fw->rcvt0_data_dma_reg; | |
| 1025 | iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); | |
| 1026 | qla24xx_read_window(reg, 0x7710, 16, iter_reg); | |
| 1027 | ||
| 1028 | iter_reg = fw->rcvt1_data_dma_reg; | |
| 1029 | iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); | |
| 1030 | qla24xx_read_window(reg, 0x7730, 16, iter_reg); | |
| 1031 | ||
| 1032 | /* RISC registers. */ | |
| 1033 | iter_reg = fw->risc_gp_reg; | |
| 1034 | iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); | |
| 1035 | iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); | |
| 1036 | iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); | |
| 1037 | iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); | |
| 1038 | iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); | |
| 1039 | iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); | |
| 1040 | iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); | |
| 1041 | qla24xx_read_window(reg, 0x0F70, 16, iter_reg); | |
| 1042 | ||
| 1043 | /* Local memory controller registers. */ | |
| 1044 | iter_reg = fw->lmc_reg; | |
| 1045 | iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); | |
| 1046 | iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); | |
| 1047 | iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); | |
| 1048 | iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); | |
| 1049 | iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); | |
| 1050 | iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); | |
| 1051 | qla24xx_read_window(reg, 0x3060, 16, iter_reg); | |
| 1052 | ||
| 1053 | /* Fibre Protocol Module registers. */ | |
| 1054 | iter_reg = fw->fpm_hdw_reg; | |
| 1055 | iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); | |
| 1056 | iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); | |
| 1057 | iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); | |
| 1058 | iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); | |
| 1059 | iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); | |
| 1060 | iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); | |
| 1061 | iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); | |
| 1062 | iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); | |
| 1063 | iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); | |
| 1064 | iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); | |
| 1065 | iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); | |
| 1066 | qla24xx_read_window(reg, 0x40B0, 16, iter_reg); | |
| 1067 | ||
| 1068 | /* Frame Buffer registers. */ | |
| 1069 | iter_reg = fw->fb_hdw_reg; | |
| 1070 | iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); | |
| 1071 | iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); | |
| 1072 | iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); | |
| 1073 | iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); | |
| 1074 | iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); | |
| 1075 | iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); | |
| 1076 | iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); | |
| 1077 | iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); | |
| 1078 | iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); | |
| 1079 | iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); | |
| 1080 | qla24xx_read_window(reg, 0x61B0, 16, iter_reg); | |
| 1081 | ||
| 1082 | rval = qla24xx_soft_reset(ha); | |
| 1083 | if (rval != QLA_SUCCESS) | |
| 1084 | goto qla24xx_fw_dump_failed_0; | |
| 1085 | ||
| 1086 | rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), | |
| c5722708 | 1087 | &nxt); |
| c81d04c9 AV |
1088 | if (rval != QLA_SUCCESS) |
| 1089 | goto qla24xx_fw_dump_failed_0; | |
| 1090 | ||
| 73208dfd | 1091 | nxt = qla2xxx_copy_queues(ha, nxt); |
| bb99de67 AV |
1092 | |
| 1093 | qla24xx_copy_eft(ha, nxt); | |
| c81d04c9 AV |
1094 | |
| 1095 | qla24xx_fw_dump_failed_0: | |
| 3420d36c | 1096 | qla2xxx_dump_post_process(base_vha, rval); |
| 6d9b61ed | 1097 | |
| c3a2f0df AV |
1098 | qla24xx_fw_dump_failed: |
| 1099 | if (!hardware_locked) | |
| 1100 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
| 1101 | } | |
| 6d9b61ed | 1102 | |
| c3a2f0df | 1103 | void |
| 7b867cf7 | 1104 | qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) |
| c3a2f0df AV |
1105 | { |
| 1106 | int rval; | |
| 1107 | uint32_t cnt; | |
| 1108 | uint32_t risc_address; | |
| 7b867cf7 | 1109 | struct qla_hw_data *ha = vha->hw; |
| c3a2f0df AV |
1110 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
| 1111 | uint32_t __iomem *dmp_reg; | |
| 1112 | uint32_t *iter_reg; | |
| 1113 | uint16_t __iomem *mbx_reg; | |
| 1114 | unsigned long flags; | |
| 1115 | struct qla25xx_fw_dump *fw; | |
| 1116 | uint32_t ext_mem_cnt; | |
| d63ab533 | 1117 | void *nxt, *nxt_chain; |
| bb99de67 | 1118 | uint32_t *last_chain = NULL; |
| 73208dfd | 1119 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); |
| 6d9b61ed | 1120 | |
| c3a2f0df AV |
1121 | risc_address = ext_mem_cnt = 0; |
| 1122 | flags = 0; | |
| 6d9b61ed | 1123 | |
| c3a2f0df AV |
1124 | if (!hardware_locked) |
| 1125 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
| 6d9b61ed | 1126 | |
| c3a2f0df | 1127 | if (!ha->fw_dump) { |
| 7c3df132 SK |
1128 | ql_log(ql_log_warn, vha, 0xd008, |
| 1129 | "No buffer available for dump.\n"); | |
| c3a2f0df AV |
1130 | goto qla25xx_fw_dump_failed; |
| 1131 | } | |
| 6d9b61ed | 1132 | |
| c3a2f0df | 1133 | if (ha->fw_dumped) { |
| 7c3df132 SK |
1134 | ql_log(ql_log_warn, vha, 0xd009, |
| 1135 | "Firmware has been previously dumped (%p) " | |
| 1136 | "-- ignoring request.\n", | |
| 1137 | ha->fw_dump); | |
| c3a2f0df AV |
1138 | goto qla25xx_fw_dump_failed; |
| 1139 | } | |
| 1140 | fw = &ha->fw_dump->isp.isp25; | |
| 1141 | qla2xxx_prep_dump(ha, ha->fw_dump); | |
| b5836927 | 1142 | ha->fw_dump->version = __constant_htonl(2); |
| 6d9b61ed | 1143 | |
| c3a2f0df | 1144 | fw->host_status = htonl(RD_REG_DWORD(®->host_status)); |
| 6d9b61ed | 1145 | |
| c3a2f0df | 1146 | /* Pause RISC. */ |
| c81d04c9 AV |
1147 | rval = qla24xx_pause_risc(reg); |
| 1148 | if (rval != QLA_SUCCESS) | |
| 1149 | goto qla25xx_fw_dump_failed_0; | |
| 1150 | ||
| b5836927 AV |
1151 | /* Host/Risc registers. */ |
| 1152 | iter_reg = fw->host_risc_reg; | |
| 1153 | iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg); | |
| 1154 | qla24xx_read_window(reg, 0x7010, 16, iter_reg); | |
| 1155 | ||
| 1156 | /* PCIe registers. */ | |
| 1157 | WRT_REG_DWORD(®->iobase_addr, 0x7C00); | |
| 1158 | RD_REG_DWORD(®->iobase_addr); | |
| 1159 | WRT_REG_DWORD(®->iobase_window, 0x01); | |
| 1160 | dmp_reg = ®->iobase_c4; | |
| 1161 | fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++)); | |
| 1162 | fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++)); | |
| 1163 | fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg)); | |
| 1164 | fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window)); | |
| 73208dfd | 1165 | |
| b5836927 AV |
1166 | WRT_REG_DWORD(®->iobase_window, 0x00); |
| 1167 | RD_REG_DWORD(®->iobase_window); | |
| 1168 | ||
| c81d04c9 AV |
1169 | /* Host interface registers. */ |
| 1170 | dmp_reg = ®->flash_addr; | |
| 1171 | for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) | |
| 1172 | fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); | |
| 1173 | ||
| 1174 | /* Disable interrupts. */ | |
| 1175 | WRT_REG_DWORD(®->ictrl, 0); | |
| 1176 | RD_REG_DWORD(®->ictrl); | |
| 1177 | ||
| 1178 | /* Shadow registers. */ | |
| 1179 | WRT_REG_DWORD(®->iobase_addr, 0x0F70); | |
| 1180 | RD_REG_DWORD(®->iobase_addr); | |
| 1181 | WRT_REG_DWORD(®->iobase_select, 0xB0000000); | |
| 1182 | fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1183 | ||
| 1184 | WRT_REG_DWORD(®->iobase_select, 0xB0100000); | |
| 1185 | fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1186 | ||
| 1187 | WRT_REG_DWORD(®->iobase_select, 0xB0200000); | |
| 1188 | fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1189 | ||
| 1190 | WRT_REG_DWORD(®->iobase_select, 0xB0300000); | |
| 1191 | fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1192 | ||
| 1193 | WRT_REG_DWORD(®->iobase_select, 0xB0400000); | |
| 1194 | fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1195 | ||
| 1196 | WRT_REG_DWORD(®->iobase_select, 0xB0500000); | |
| 1197 | fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1198 | ||
| 1199 | WRT_REG_DWORD(®->iobase_select, 0xB0600000); | |
| 1200 | fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1201 | ||
| 1202 | WRT_REG_DWORD(®->iobase_select, 0xB0700000); | |
| 1203 | fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1204 | ||
| 1205 | WRT_REG_DWORD(®->iobase_select, 0xB0800000); | |
| 1206 | fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1207 | ||
| 1208 | WRT_REG_DWORD(®->iobase_select, 0xB0900000); | |
| 1209 | fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1210 | ||
| 1211 | WRT_REG_DWORD(®->iobase_select, 0xB0A00000); | |
| 1212 | fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1213 | ||
| 1214 | /* RISC I/O register. */ | |
| 1215 | WRT_REG_DWORD(®->iobase_addr, 0x0010); | |
| 1216 | fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window)); | |
| 1217 | ||
| 1218 | /* Mailbox registers. */ | |
| 1219 | mbx_reg = ®->mailbox0; | |
| 1220 | for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) | |
| 1221 | fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); | |
| 1222 | ||
| 1223 | /* Transfer sequence registers. */ | |
| 1224 | iter_reg = fw->xseq_gp_reg; | |
| 1225 | iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); | |
| 1226 | iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); | |
| 1227 | iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); | |
| 1228 | iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); | |
| 1229 | iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); | |
| 1230 | iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); | |
| 1231 | iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); | |
| 1232 | qla24xx_read_window(reg, 0xBF70, 16, iter_reg); | |
| 1233 | ||
| 1234 | iter_reg = fw->xseq_0_reg; | |
| 1235 | iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg); | |
| 1236 | iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg); | |
| 1237 | qla24xx_read_window(reg, 0xBFE0, 16, iter_reg); | |
| 1238 | ||
| 1239 | qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); | |
| 1240 | ||
| 1241 | /* Receive sequence registers. */ | |
| 1242 | iter_reg = fw->rseq_gp_reg; | |
| 1243 | iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); | |
| 1244 | iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); | |
| 1245 | iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); | |
| 1246 | iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); | |
| 1247 | iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); | |
| 1248 | iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); | |
| 1249 | iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); | |
| 1250 | qla24xx_read_window(reg, 0xFF70, 16, iter_reg); | |
| 1251 | ||
| 1252 | iter_reg = fw->rseq_0_reg; | |
| 1253 | iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg); | |
| 1254 | qla24xx_read_window(reg, 0xFFD0, 16, iter_reg); | |
| 1255 | ||
| 1256 | qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); | |
| 1257 | qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); | |
| 1258 | ||
| 1259 | /* Auxiliary sequence registers. */ | |
| 1260 | iter_reg = fw->aseq_gp_reg; | |
| 1261 | iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg); | |
| 1262 | iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg); | |
| 1263 | iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg); | |
| 1264 | iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg); | |
| 1265 | iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg); | |
| 1266 | iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg); | |
| 1267 | iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg); | |
| 1268 | qla24xx_read_window(reg, 0xB070, 16, iter_reg); | |
| 1269 | ||
| 1270 | iter_reg = fw->aseq_0_reg; | |
| 1271 | iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg); | |
| 1272 | qla24xx_read_window(reg, 0xB0D0, 16, iter_reg); | |
| 1273 | ||
| 1274 | qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg); | |
| 1275 | qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg); | |
| 1276 | ||
| 1277 | /* Command DMA registers. */ | |
| 1278 | qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg); | |
| 1279 | ||
| 1280 | /* Queues. */ | |
| 1281 | iter_reg = fw->req0_dma_reg; | |
| 1282 | iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); | |
| 1283 | dmp_reg = ®->iobase_q; | |
| 1284 | for (cnt = 0; cnt < 7; cnt++) | |
| 1285 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
| 1286 | ||
| 1287 | iter_reg = fw->resp0_dma_reg; | |
| 1288 | iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); | |
| 1289 | dmp_reg = ®->iobase_q; | |
| 1290 | for (cnt = 0; cnt < 7; cnt++) | |
| 1291 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
| 1292 | ||
| 1293 | iter_reg = fw->req1_dma_reg; | |
| 1294 | iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); | |
| 1295 | dmp_reg = ®->iobase_q; | |
| 1296 | for (cnt = 0; cnt < 7; cnt++) | |
| 1297 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
| 1298 | ||
| 1299 | /* Transmit DMA registers. */ | |
| 1300 | iter_reg = fw->xmt0_dma_reg; | |
| 1301 | iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); | |
| 1302 | qla24xx_read_window(reg, 0x7610, 16, iter_reg); | |
| 1303 | ||
| 1304 | iter_reg = fw->xmt1_dma_reg; | |
| 1305 | iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); | |
| 1306 | qla24xx_read_window(reg, 0x7630, 16, iter_reg); | |
| 1307 | ||
| 1308 | iter_reg = fw->xmt2_dma_reg; | |
| 1309 | iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); | |
| 1310 | qla24xx_read_window(reg, 0x7650, 16, iter_reg); | |
| 1311 | ||
| 1312 | iter_reg = fw->xmt3_dma_reg; | |
| 1313 | iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); | |
| 1314 | qla24xx_read_window(reg, 0x7670, 16, iter_reg); | |
| 1315 | ||
| 1316 | iter_reg = fw->xmt4_dma_reg; | |
| 1317 | iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); | |
| 1318 | qla24xx_read_window(reg, 0x7690, 16, iter_reg); | |
| 1319 | ||
| 1320 | qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); | |
| 1321 | ||
| 1322 | /* Receive DMA registers. */ | |
| 1323 | iter_reg = fw->rcvt0_data_dma_reg; | |
| 1324 | iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); | |
| 1325 | qla24xx_read_window(reg, 0x7710, 16, iter_reg); | |
| 1326 | ||
| 1327 | iter_reg = fw->rcvt1_data_dma_reg; | |
| 1328 | iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); | |
| 1329 | qla24xx_read_window(reg, 0x7730, 16, iter_reg); | |
| 1330 | ||
| 1331 | /* RISC registers. */ | |
| 1332 | iter_reg = fw->risc_gp_reg; | |
| 1333 | iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); | |
| 1334 | iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); | |
| 1335 | iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); | |
| 1336 | iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); | |
| 1337 | iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); | |
| 1338 | iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); | |
| 1339 | iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); | |
| 1340 | qla24xx_read_window(reg, 0x0F70, 16, iter_reg); | |
| 1341 | ||
| 1342 | /* Local memory controller registers. */ | |
| 1343 | iter_reg = fw->lmc_reg; | |
| 1344 | iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); | |
| 1345 | iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); | |
| 1346 | iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); | |
| 1347 | iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); | |
| 1348 | iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); | |
| 1349 | iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); | |
| 1350 | iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg); | |
| 1351 | qla24xx_read_window(reg, 0x3070, 16, iter_reg); | |
| 1352 | ||
| 1353 | /* Fibre Protocol Module registers. */ | |
| 1354 | iter_reg = fw->fpm_hdw_reg; | |
| 1355 | iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); | |
| 1356 | iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); | |
| 1357 | iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); | |
| 1358 | iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); | |
| 1359 | iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); | |
| 1360 | iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); | |
| 1361 | iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); | |
| 1362 | iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); | |
| 1363 | iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); | |
| 1364 | iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); | |
| 1365 | iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); | |
| 1366 | qla24xx_read_window(reg, 0x40B0, 16, iter_reg); | |
| 1367 | ||
| 1368 | /* Frame Buffer registers. */ | |
| 1369 | iter_reg = fw->fb_hdw_reg; | |
| 1370 | iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); | |
| 1371 | iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); | |
| 1372 | iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); | |
| 1373 | iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); | |
| 1374 | iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); | |
| 1375 | iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); | |
| 1376 | iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); | |
| 1377 | iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); | |
| 1378 | iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); | |
| 1379 | iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); | |
| 1380 | iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg); | |
| 1381 | qla24xx_read_window(reg, 0x6F00, 16, iter_reg); | |
| 1382 | ||
| d63ab533 AV |
1383 | /* Multi queue registers */ |
| 1384 | nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset, | |
| 1385 | &last_chain); | |
| 1386 | ||
| c81d04c9 AV |
1387 | rval = qla24xx_soft_reset(ha); |
| 1388 | if (rval != QLA_SUCCESS) | |
| 1389 | goto qla25xx_fw_dump_failed_0; | |
| 1390 | ||
| 1391 | rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), | |
| c5722708 | 1392 | &nxt); |
| c81d04c9 AV |
1393 | if (rval != QLA_SUCCESS) |
| 1394 | goto qla25xx_fw_dump_failed_0; | |
| 1395 | ||
| 73208dfd | 1396 | nxt = qla2xxx_copy_queues(ha, nxt); |
| c81d04c9 | 1397 | |
| bb99de67 | 1398 | nxt = qla24xx_copy_eft(ha, nxt); |
| df613b96 | 1399 | |
| d63ab533 | 1400 | /* Chain entries -- started with MQ. */ |
| 050c9bb1 GM |
1401 | nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain); |
| 1402 | nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain); | |
| bb99de67 AV |
1403 | if (last_chain) { |
| 1404 | ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT); | |
| 1405 | *last_chain |= __constant_htonl(DUMP_CHAIN_LAST); | |
| 1406 | } | |
| df613b96 | 1407 | |
| 050c9bb1 GM |
1408 | /* Adjust valid length. */ |
| 1409 | ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump); | |
| 1410 | ||
| c81d04c9 | 1411 | qla25xx_fw_dump_failed_0: |
| 3420d36c | 1412 | qla2xxx_dump_post_process(base_vha, rval); |
| 6d9b61ed | 1413 | |
| c3a2f0df | 1414 | qla25xx_fw_dump_failed: |
| 6d9b61ed AV |
1415 | if (!hardware_locked) |
| 1416 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
| 1417 | } | |
| 3a03eb79 AV |
1418 | |
| 1419 | void | |
| 1420 | qla81xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) | |
| 1421 | { | |
| 1422 | int rval; | |
| 1423 | uint32_t cnt; | |
| 1424 | uint32_t risc_address; | |
| 1425 | struct qla_hw_data *ha = vha->hw; | |
| 1426 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | |
| 1427 | uint32_t __iomem *dmp_reg; | |
| 1428 | uint32_t *iter_reg; | |
| 1429 | uint16_t __iomem *mbx_reg; | |
| 1430 | unsigned long flags; | |
| 1431 | struct qla81xx_fw_dump *fw; | |
| 1432 | uint32_t ext_mem_cnt; | |
| 1433 | void *nxt, *nxt_chain; | |
| 1434 | uint32_t *last_chain = NULL; | |
| 1435 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); | |
| 1436 | ||
| 1437 | risc_address = ext_mem_cnt = 0; | |
| 1438 | flags = 0; | |
| 1439 | ||
| 1440 | if (!hardware_locked) | |
| 1441 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
| 1442 | ||
| 1443 | if (!ha->fw_dump) { | |
| 7c3df132 SK |
1444 | ql_log(ql_log_warn, vha, 0xd00a, |
| 1445 | "No buffer available for dump.\n"); | |
| 3a03eb79 AV |
1446 | goto qla81xx_fw_dump_failed; |
| 1447 | } | |
| 1448 | ||
| 1449 | if (ha->fw_dumped) { | |
| 7c3df132 SK |
1450 | ql_log(ql_log_warn, vha, 0xd00b, |
| 1451 | "Firmware has been previously dumped (%p) " | |
| 1452 | "-- ignoring request.\n", | |
| 1453 | ha->fw_dump); | |
| 3a03eb79 AV |
1454 | goto qla81xx_fw_dump_failed; |
| 1455 | } | |
| 1456 | fw = &ha->fw_dump->isp.isp81; | |
| 1457 | qla2xxx_prep_dump(ha, ha->fw_dump); | |
| 1458 | ||
| 1459 | fw->host_status = htonl(RD_REG_DWORD(®->host_status)); | |
| 1460 | ||
| 1461 | /* Pause RISC. */ | |
| 1462 | rval = qla24xx_pause_risc(reg); | |
| 1463 | if (rval != QLA_SUCCESS) | |
| 1464 | goto qla81xx_fw_dump_failed_0; | |
| 1465 | ||
| 1466 | /* Host/Risc registers. */ | |
| 1467 | iter_reg = fw->host_risc_reg; | |
| 1468 | iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg); | |
| 1469 | qla24xx_read_window(reg, 0x7010, 16, iter_reg); | |
| 1470 | ||
| 1471 | /* PCIe registers. */ | |
| 1472 | WRT_REG_DWORD(®->iobase_addr, 0x7C00); | |
| 1473 | RD_REG_DWORD(®->iobase_addr); | |
| 1474 | WRT_REG_DWORD(®->iobase_window, 0x01); | |
| 1475 | dmp_reg = ®->iobase_c4; | |
| 1476 | fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++)); | |
| 1477 | fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++)); | |
| 1478 | fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg)); | |
| 1479 | fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window)); | |
| 1480 | ||
| 1481 | WRT_REG_DWORD(®->iobase_window, 0x00); | |
| 1482 | RD_REG_DWORD(®->iobase_window); | |
| 1483 | ||
| 1484 | /* Host interface registers. */ | |
| 1485 | dmp_reg = ®->flash_addr; | |
| 1486 | for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) | |
| 1487 | fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); | |
| 1488 | ||
| 1489 | /* Disable interrupts. */ | |
| 1490 | WRT_REG_DWORD(®->ictrl, 0); | |
| 1491 | RD_REG_DWORD(®->ictrl); | |
| 1492 | ||
| 1493 | /* Shadow registers. */ | |
| 1494 | WRT_REG_DWORD(®->iobase_addr, 0x0F70); | |
| 1495 | RD_REG_DWORD(®->iobase_addr); | |
| 1496 | WRT_REG_DWORD(®->iobase_select, 0xB0000000); | |
| 1497 | fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1498 | ||
| 1499 | WRT_REG_DWORD(®->iobase_select, 0xB0100000); | |
| 1500 | fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1501 | ||
| 1502 | WRT_REG_DWORD(®->iobase_select, 0xB0200000); | |
| 1503 | fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1504 | ||
| 1505 | WRT_REG_DWORD(®->iobase_select, 0xB0300000); | |
| 1506 | fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1507 | ||
| 1508 | WRT_REG_DWORD(®->iobase_select, 0xB0400000); | |
| 1509 | fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1510 | ||
| 1511 | WRT_REG_DWORD(®->iobase_select, 0xB0500000); | |
| 1512 | fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1513 | ||
| 1514 | WRT_REG_DWORD(®->iobase_select, 0xB0600000); | |
| 1515 | fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1516 | ||
| 1517 | WRT_REG_DWORD(®->iobase_select, 0xB0700000); | |
| 1518 | fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1519 | ||
| 1520 | WRT_REG_DWORD(®->iobase_select, 0xB0800000); | |
| 1521 | fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1522 | ||
| 1523 | WRT_REG_DWORD(®->iobase_select, 0xB0900000); | |
| 1524 | fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1525 | ||
| 1526 | WRT_REG_DWORD(®->iobase_select, 0xB0A00000); | |
| 1527 | fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1528 | ||
| 1529 | /* RISC I/O register. */ | |
| 1530 | WRT_REG_DWORD(®->iobase_addr, 0x0010); | |
| 1531 | fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window)); | |
| 1532 | ||
| 1533 | /* Mailbox registers. */ | |
| 1534 | mbx_reg = ®->mailbox0; | |
| 1535 | for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) | |
| 1536 | fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); | |
| 1537 | ||
| 1538 | /* Transfer sequence registers. */ | |
| 1539 | iter_reg = fw->xseq_gp_reg; | |
| 1540 | iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); | |
| 1541 | iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); | |
| 1542 | iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); | |
| 1543 | iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); | |
| 1544 | iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); | |
| 1545 | iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); | |
| 1546 | iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); | |
| 1547 | qla24xx_read_window(reg, 0xBF70, 16, iter_reg); | |
| 1548 | ||
| 1549 | iter_reg = fw->xseq_0_reg; | |
| 1550 | iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg); | |
| 1551 | iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg); | |
| 1552 | qla24xx_read_window(reg, 0xBFE0, 16, iter_reg); | |
| 1553 | ||
| 1554 | qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); | |
| 1555 | ||
| 1556 | /* Receive sequence registers. */ | |
| 1557 | iter_reg = fw->rseq_gp_reg; | |
| 1558 | iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); | |
| 1559 | iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); | |
| 1560 | iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); | |
| 1561 | iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); | |
| 1562 | iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); | |
| 1563 | iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); | |
| 1564 | iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); | |
| 1565 | qla24xx_read_window(reg, 0xFF70, 16, iter_reg); | |
| 1566 | ||
| 1567 | iter_reg = fw->rseq_0_reg; | |
| 1568 | iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg); | |
| 1569 | qla24xx_read_window(reg, 0xFFD0, 16, iter_reg); | |
| 1570 | ||
| 1571 | qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); | |
| 1572 | qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); | |
| 1573 | ||
| 1574 | /* Auxiliary sequence registers. */ | |
| 1575 | iter_reg = fw->aseq_gp_reg; | |
| 1576 | iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg); | |
| 1577 | iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg); | |
| 1578 | iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg); | |
| 1579 | iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg); | |
| 1580 | iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg); | |
| 1581 | iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg); | |
| 1582 | iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg); | |
| 1583 | qla24xx_read_window(reg, 0xB070, 16, iter_reg); | |
| 1584 | ||
| 1585 | iter_reg = fw->aseq_0_reg; | |
| 1586 | iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg); | |
| 1587 | qla24xx_read_window(reg, 0xB0D0, 16, iter_reg); | |
| 1588 | ||
| 1589 | qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg); | |
| 1590 | qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg); | |
| 1591 | ||
| 1592 | /* Command DMA registers. */ | |
| 1593 | qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg); | |
| 1594 | ||
| 1595 | /* Queues. */ | |
| 1596 | iter_reg = fw->req0_dma_reg; | |
| 1597 | iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); | |
| 1598 | dmp_reg = ®->iobase_q; | |
| 1599 | for (cnt = 0; cnt < 7; cnt++) | |
| 1600 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
| 1601 | ||
| 1602 | iter_reg = fw->resp0_dma_reg; | |
| 1603 | iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); | |
| 1604 | dmp_reg = ®->iobase_q; | |
| 1605 | for (cnt = 0; cnt < 7; cnt++) | |
| 1606 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
| 1607 | ||
| 1608 | iter_reg = fw->req1_dma_reg; | |
| 1609 | iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); | |
| 1610 | dmp_reg = ®->iobase_q; | |
| 1611 | for (cnt = 0; cnt < 7; cnt++) | |
| 1612 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
| 1613 | ||
| 1614 | /* Transmit DMA registers. */ | |
| 1615 | iter_reg = fw->xmt0_dma_reg; | |
| 1616 | iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); | |
| 1617 | qla24xx_read_window(reg, 0x7610, 16, iter_reg); | |
| 1618 | ||
| 1619 | iter_reg = fw->xmt1_dma_reg; | |
| 1620 | iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); | |
| 1621 | qla24xx_read_window(reg, 0x7630, 16, iter_reg); | |
| 1622 | ||
| 1623 | iter_reg = fw->xmt2_dma_reg; | |
| 1624 | iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); | |
| 1625 | qla24xx_read_window(reg, 0x7650, 16, iter_reg); | |
| 1626 | ||
| 1627 | iter_reg = fw->xmt3_dma_reg; | |
| 1628 | iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); | |
| 1629 | qla24xx_read_window(reg, 0x7670, 16, iter_reg); | |
| 1630 | ||
| 1631 | iter_reg = fw->xmt4_dma_reg; | |
| 1632 | iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); | |
| 1633 | qla24xx_read_window(reg, 0x7690, 16, iter_reg); | |
| 1634 | ||
| 1635 | qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); | |
| 1636 | ||
| 1637 | /* Receive DMA registers. */ | |
| 1638 | iter_reg = fw->rcvt0_data_dma_reg; | |
| 1639 | iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); | |
| 1640 | qla24xx_read_window(reg, 0x7710, 16, iter_reg); | |
| 1641 | ||
| 1642 | iter_reg = fw->rcvt1_data_dma_reg; | |
| 1643 | iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); | |
| 1644 | qla24xx_read_window(reg, 0x7730, 16, iter_reg); | |
| 1645 | ||
| 1646 | /* RISC registers. */ | |
| 1647 | iter_reg = fw->risc_gp_reg; | |
| 1648 | iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); | |
| 1649 | iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); | |
| 1650 | iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); | |
| 1651 | iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); | |
| 1652 | iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); | |
| 1653 | iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); | |
| 1654 | iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); | |
| 1655 | qla24xx_read_window(reg, 0x0F70, 16, iter_reg); | |
| 1656 | ||
| 1657 | /* Local memory controller registers. */ | |
| 1658 | iter_reg = fw->lmc_reg; | |
| 1659 | iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); | |
| 1660 | iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); | |
| 1661 | iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); | |
| 1662 | iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); | |
| 1663 | iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); | |
| 1664 | iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); | |
| 1665 | iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg); | |
| 1666 | qla24xx_read_window(reg, 0x3070, 16, iter_reg); | |
| 1667 | ||
| 1668 | /* Fibre Protocol Module registers. */ | |
| 1669 | iter_reg = fw->fpm_hdw_reg; | |
| 1670 | iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); | |
| 1671 | iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); | |
| 1672 | iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); | |
| 1673 | iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); | |
| 1674 | iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); | |
| 1675 | iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); | |
| 1676 | iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); | |
| 1677 | iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); | |
| 1678 | iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); | |
| 1679 | iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); | |
| 1680 | iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); | |
| 1681 | iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg); | |
| 1682 | iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg); | |
| 1683 | qla24xx_read_window(reg, 0x40D0, 16, iter_reg); | |
| 1684 | ||
| 1685 | /* Frame Buffer registers. */ | |
| 1686 | iter_reg = fw->fb_hdw_reg; | |
| 1687 | iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); | |
| 1688 | iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); | |
| 1689 | iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); | |
| 1690 | iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); | |
| 1691 | iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); | |
| 1692 | iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); | |
| 1693 | iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); | |
| 1694 | iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); | |
| 1695 | iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); | |
| 1696 | iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); | |
| 1697 | iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg); | |
| 1698 | iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg); | |
| 1699 | qla24xx_read_window(reg, 0x6F00, 16, iter_reg); | |
| 1700 | ||
| 1701 | /* Multi queue registers */ | |
| 1702 | nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset, | |
| 1703 | &last_chain); | |
| 1704 | ||
| 1705 | rval = qla24xx_soft_reset(ha); | |
| 1706 | if (rval != QLA_SUCCESS) | |
| 1707 | goto qla81xx_fw_dump_failed_0; | |
| 1708 | ||
| 1709 | rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), | |
| 1710 | &nxt); | |
| 1711 | if (rval != QLA_SUCCESS) | |
| 1712 | goto qla81xx_fw_dump_failed_0; | |
| 1713 | ||
| 1714 | nxt = qla2xxx_copy_queues(ha, nxt); | |
| 1715 | ||
| 1716 | nxt = qla24xx_copy_eft(ha, nxt); | |
| 1717 | ||
| 1718 | /* Chain entries -- started with MQ. */ | |
| 050c9bb1 GM |
1719 | nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain); |
| 1720 | nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain); | |
| 3a03eb79 AV |
1721 | if (last_chain) { |
| 1722 | ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT); | |
| 1723 | *last_chain |= __constant_htonl(DUMP_CHAIN_LAST); | |
| 1724 | } | |
| 1725 | ||
| 050c9bb1 GM |
1726 | /* Adjust valid length. */ |
| 1727 | ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump); | |
| 1728 | ||
| 3a03eb79 | 1729 | qla81xx_fw_dump_failed_0: |
| 3420d36c | 1730 | qla2xxx_dump_post_process(base_vha, rval); |
| 3a03eb79 AV |
1731 | |
| 1732 | qla81xx_fw_dump_failed: | |
| 1733 | if (!hardware_locked) | |
| 1734 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
| 1735 | } | |
| 1736 | ||
| 6246b8a1 GM |
1737 | void |
| 1738 | qla83xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) | |
| 1739 | { | |
| 1740 | int rval; | |
| 1741 | uint32_t cnt, reg_data; | |
| 1742 | uint32_t risc_address; | |
| 1743 | struct qla_hw_data *ha = vha->hw; | |
| 1744 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | |
| 1745 | uint32_t __iomem *dmp_reg; | |
| 1746 | uint32_t *iter_reg; | |
| 1747 | uint16_t __iomem *mbx_reg; | |
| 1748 | unsigned long flags; | |
| 1749 | struct qla83xx_fw_dump *fw; | |
| 1750 | uint32_t ext_mem_cnt; | |
| 1751 | void *nxt, *nxt_chain; | |
| 1752 | uint32_t *last_chain = NULL; | |
| 1753 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); | |
| 1754 | ||
| 1755 | risc_address = ext_mem_cnt = 0; | |
| 1756 | flags = 0; | |
| 1757 | ||
| 1758 | if (!hardware_locked) | |
| 1759 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
| 1760 | ||
| 1761 | if (!ha->fw_dump) { | |
| 1762 | ql_log(ql_log_warn, vha, 0xd00c, | |
| 1763 | "No buffer available for dump!!!\n"); | |
| 1764 | goto qla83xx_fw_dump_failed; | |
| 1765 | } | |
| 1766 | ||
| 1767 | if (ha->fw_dumped) { | |
| 1768 | ql_log(ql_log_warn, vha, 0xd00d, | |
| 1769 | "Firmware has been previously dumped (%p) -- ignoring " | |
| 1770 | "request...\n", ha->fw_dump); | |
| 1771 | goto qla83xx_fw_dump_failed; | |
| 1772 | } | |
| 1773 | fw = &ha->fw_dump->isp.isp83; | |
| 1774 | qla2xxx_prep_dump(ha, ha->fw_dump); | |
| 1775 | ||
| 1776 | fw->host_status = htonl(RD_REG_DWORD(®->host_status)); | |
| 1777 | ||
| 1778 | /* Pause RISC. */ | |
| 1779 | rval = qla24xx_pause_risc(reg); | |
| 1780 | if (rval != QLA_SUCCESS) | |
| 1781 | goto qla83xx_fw_dump_failed_0; | |
| 1782 | ||
| 1783 | WRT_REG_DWORD(®->iobase_addr, 0x6000); | |
| 1784 | dmp_reg = ®->iobase_window; | |
| 1785 | reg_data = RD_REG_DWORD(dmp_reg); | |
| 1786 | WRT_REG_DWORD(dmp_reg, 0); | |
| 1787 | ||
| 1788 | dmp_reg = ®->unused_4_1[0]; | |
| 1789 | reg_data = RD_REG_DWORD(dmp_reg); | |
| 1790 | WRT_REG_DWORD(dmp_reg, 0); | |
| 1791 | ||
| 1792 | WRT_REG_DWORD(®->iobase_addr, 0x6010); | |
| 1793 | dmp_reg = ®->unused_4_1[2]; | |
| 1794 | reg_data = RD_REG_DWORD(dmp_reg); | |
| 1795 | WRT_REG_DWORD(dmp_reg, 0); | |
| 1796 | ||
| 1797 | /* select PCR and disable ecc checking and correction */ | |
| 1798 | WRT_REG_DWORD(®->iobase_addr, 0x0F70); | |
| 1799 | RD_REG_DWORD(®->iobase_addr); | |
| 1800 | WRT_REG_DWORD(®->iobase_select, 0x60000000); /* write to F0h = PCR */ | |
| 1801 | ||
| 1802 | /* Host/Risc registers. */ | |
| 1803 | iter_reg = fw->host_risc_reg; | |
| 1804 | iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg); | |
| 1805 | iter_reg = qla24xx_read_window(reg, 0x7010, 16, iter_reg); | |
| 1806 | qla24xx_read_window(reg, 0x7040, 16, iter_reg); | |
| 1807 | ||
| 1808 | /* PCIe registers. */ | |
| 1809 | WRT_REG_DWORD(®->iobase_addr, 0x7C00); | |
| 1810 | RD_REG_DWORD(®->iobase_addr); | |
| 1811 | WRT_REG_DWORD(®->iobase_window, 0x01); | |
| 1812 | dmp_reg = ®->iobase_c4; | |
| 1813 | fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++)); | |
| 1814 | fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++)); | |
| 1815 | fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg)); | |
| 1816 | fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window)); | |
| 1817 | ||
| 1818 | WRT_REG_DWORD(®->iobase_window, 0x00); | |
| 1819 | RD_REG_DWORD(®->iobase_window); | |
| 1820 | ||
| 1821 | /* Host interface registers. */ | |
| 1822 | dmp_reg = ®->flash_addr; | |
| 1823 | for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) | |
| 1824 | fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); | |
| 1825 | ||
| 1826 | /* Disable interrupts. */ | |
| 1827 | WRT_REG_DWORD(®->ictrl, 0); | |
| 1828 | RD_REG_DWORD(®->ictrl); | |
| 1829 | ||
| 1830 | /* Shadow registers. */ | |
| 1831 | WRT_REG_DWORD(®->iobase_addr, 0x0F70); | |
| 1832 | RD_REG_DWORD(®->iobase_addr); | |
| 1833 | WRT_REG_DWORD(®->iobase_select, 0xB0000000); | |
| 1834 | fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1835 | ||
| 1836 | WRT_REG_DWORD(®->iobase_select, 0xB0100000); | |
| 1837 | fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1838 | ||
| 1839 | WRT_REG_DWORD(®->iobase_select, 0xB0200000); | |
| 1840 | fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1841 | ||
| 1842 | WRT_REG_DWORD(®->iobase_select, 0xB0300000); | |
| 1843 | fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1844 | ||
| 1845 | WRT_REG_DWORD(®->iobase_select, 0xB0400000); | |
| 1846 | fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1847 | ||
| 1848 | WRT_REG_DWORD(®->iobase_select, 0xB0500000); | |
| 1849 | fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1850 | ||
| 1851 | WRT_REG_DWORD(®->iobase_select, 0xB0600000); | |
| 1852 | fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1853 | ||
| 1854 | WRT_REG_DWORD(®->iobase_select, 0xB0700000); | |
| 1855 | fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1856 | ||
| 1857 | WRT_REG_DWORD(®->iobase_select, 0xB0800000); | |
| 1858 | fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1859 | ||
| 1860 | WRT_REG_DWORD(®->iobase_select, 0xB0900000); | |
| 1861 | fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1862 | ||
| 1863 | WRT_REG_DWORD(®->iobase_select, 0xB0A00000); | |
| 1864 | fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1865 | ||
| 1866 | /* RISC I/O register. */ | |
| 1867 | WRT_REG_DWORD(®->iobase_addr, 0x0010); | |
| 1868 | fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window)); | |
| 1869 | ||
| 1870 | /* Mailbox registers. */ | |
| 1871 | mbx_reg = ®->mailbox0; | |
| 1872 | for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) | |
| 1873 | fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); | |
| 1874 | ||
| 1875 | /* Transfer sequence registers. */ | |
| 1876 | iter_reg = fw->xseq_gp_reg; | |
| 1877 | iter_reg = qla24xx_read_window(reg, 0xBE00, 16, iter_reg); | |
| 1878 | iter_reg = qla24xx_read_window(reg, 0xBE10, 16, iter_reg); | |
| 1879 | iter_reg = qla24xx_read_window(reg, 0xBE20, 16, iter_reg); | |
| 1880 | iter_reg = qla24xx_read_window(reg, 0xBE30, 16, iter_reg); | |
| 1881 | iter_reg = qla24xx_read_window(reg, 0xBE40, 16, iter_reg); | |
| 1882 | iter_reg = qla24xx_read_window(reg, 0xBE50, 16, iter_reg); | |
| 1883 | iter_reg = qla24xx_read_window(reg, 0xBE60, 16, iter_reg); | |
| 1884 | iter_reg = qla24xx_read_window(reg, 0xBE70, 16, iter_reg); | |
| 1885 | iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); | |
| 1886 | iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); | |
| 1887 | iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); | |
| 1888 | iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); | |
| 1889 | iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); | |
| 1890 | iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); | |
| 1891 | iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); | |
| 1892 | qla24xx_read_window(reg, 0xBF70, 16, iter_reg); | |
| 1893 | ||
| 1894 | iter_reg = fw->xseq_0_reg; | |
| 1895 | iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg); | |
| 1896 | iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg); | |
| 1897 | qla24xx_read_window(reg, 0xBFE0, 16, iter_reg); | |
| 1898 | ||
| 1899 | qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); | |
| 1900 | ||
| 1901 | qla24xx_read_window(reg, 0xBEF0, 16, fw->xseq_2_reg); | |
| 1902 | ||
| 1903 | /* Receive sequence registers. */ | |
| 1904 | iter_reg = fw->rseq_gp_reg; | |
| 1905 | iter_reg = qla24xx_read_window(reg, 0xFE00, 16, iter_reg); | |
| 1906 | iter_reg = qla24xx_read_window(reg, 0xFE10, 16, iter_reg); | |
| 1907 | iter_reg = qla24xx_read_window(reg, 0xFE20, 16, iter_reg); | |
| 1908 | iter_reg = qla24xx_read_window(reg, 0xFE30, 16, iter_reg); | |
| 1909 | iter_reg = qla24xx_read_window(reg, 0xFE40, 16, iter_reg); | |
| 1910 | iter_reg = qla24xx_read_window(reg, 0xFE50, 16, iter_reg); | |
| 1911 | iter_reg = qla24xx_read_window(reg, 0xFE60, 16, iter_reg); | |
| 1912 | iter_reg = qla24xx_read_window(reg, 0xFE70, 16, iter_reg); | |
| 1913 | iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); | |
| 1914 | iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); | |
| 1915 | iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); | |
| 1916 | iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); | |
| 1917 | iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); | |
| 1918 | iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); | |
| 1919 | iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); | |
| 1920 | qla24xx_read_window(reg, 0xFF70, 16, iter_reg); | |
| 1921 | ||
| 1922 | iter_reg = fw->rseq_0_reg; | |
| 1923 | iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg); | |
| 1924 | qla24xx_read_window(reg, 0xFFD0, 16, iter_reg); | |
| 1925 | ||
| 1926 | qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); | |
| 1927 | qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); | |
| 1928 | qla24xx_read_window(reg, 0xFEF0, 16, fw->rseq_3_reg); | |
| 1929 | ||
| 1930 | /* Auxiliary sequence registers. */ | |
| 1931 | iter_reg = fw->aseq_gp_reg; | |
| 1932 | iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg); | |
| 1933 | iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg); | |
| 1934 | iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg); | |
| 1935 | iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg); | |
| 1936 | iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg); | |
| 1937 | iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg); | |
| 1938 | iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg); | |
| 1939 | iter_reg = qla24xx_read_window(reg, 0xB070, 16, iter_reg); | |
| 1940 | iter_reg = qla24xx_read_window(reg, 0xB100, 16, iter_reg); | |
| 1941 | iter_reg = qla24xx_read_window(reg, 0xB110, 16, iter_reg); | |
| 1942 | iter_reg = qla24xx_read_window(reg, 0xB120, 16, iter_reg); | |
| 1943 | iter_reg = qla24xx_read_window(reg, 0xB130, 16, iter_reg); | |
| 1944 | iter_reg = qla24xx_read_window(reg, 0xB140, 16, iter_reg); | |
| 1945 | iter_reg = qla24xx_read_window(reg, 0xB150, 16, iter_reg); | |
| 1946 | iter_reg = qla24xx_read_window(reg, 0xB160, 16, iter_reg); | |
| 1947 | qla24xx_read_window(reg, 0xB170, 16, iter_reg); | |
| 1948 | ||
| 1949 | iter_reg = fw->aseq_0_reg; | |
| 1950 | iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg); | |
| 1951 | qla24xx_read_window(reg, 0xB0D0, 16, iter_reg); | |
| 1952 | ||
| 1953 | qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg); | |
| 1954 | qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg); | |
| 1955 | qla24xx_read_window(reg, 0xB1F0, 16, fw->aseq_3_reg); | |
| 1956 | ||
| 1957 | /* Command DMA registers. */ | |
| 1958 | iter_reg = fw->cmd_dma_reg; | |
| 1959 | iter_reg = qla24xx_read_window(reg, 0x7100, 16, iter_reg); | |
| 1960 | iter_reg = qla24xx_read_window(reg, 0x7120, 16, iter_reg); | |
| 1961 | iter_reg = qla24xx_read_window(reg, 0x7130, 16, iter_reg); | |
| 1962 | qla24xx_read_window(reg, 0x71F0, 16, iter_reg); | |
| 1963 | ||
| 1964 | /* Queues. */ | |
| 1965 | iter_reg = fw->req0_dma_reg; | |
| 1966 | iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); | |
| 1967 | dmp_reg = ®->iobase_q; | |
| 1968 | for (cnt = 0; cnt < 7; cnt++) | |
| 1969 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
| 1970 | ||
| 1971 | iter_reg = fw->resp0_dma_reg; | |
| 1972 | iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); | |
| 1973 | dmp_reg = ®->iobase_q; | |
| 1974 | for (cnt = 0; cnt < 7; cnt++) | |
| 1975 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
| 1976 | ||
| 1977 | iter_reg = fw->req1_dma_reg; | |
| 1978 | iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); | |
| 1979 | dmp_reg = ®->iobase_q; | |
| 1980 | for (cnt = 0; cnt < 7; cnt++) | |
| 1981 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
| 1982 | ||
| 1983 | /* Transmit DMA registers. */ | |
| 1984 | iter_reg = fw->xmt0_dma_reg; | |
| 1985 | iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); | |
| 1986 | qla24xx_read_window(reg, 0x7610, 16, iter_reg); | |
| 1987 | ||
| 1988 | iter_reg = fw->xmt1_dma_reg; | |
| 1989 | iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); | |
| 1990 | qla24xx_read_window(reg, 0x7630, 16, iter_reg); | |
| 1991 | ||
| 1992 | iter_reg = fw->xmt2_dma_reg; | |
| 1993 | iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); | |
| 1994 | qla24xx_read_window(reg, 0x7650, 16, iter_reg); | |
| 1995 | ||
| 1996 | iter_reg = fw->xmt3_dma_reg; | |
| 1997 | iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); | |
| 1998 | qla24xx_read_window(reg, 0x7670, 16, iter_reg); | |
| 1999 | ||
| 2000 | iter_reg = fw->xmt4_dma_reg; | |
| 2001 | iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); | |
| 2002 | qla24xx_read_window(reg, 0x7690, 16, iter_reg); | |
| 2003 | ||
| 2004 | qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); | |
| 2005 | ||
| 2006 | /* Receive DMA registers. */ | |
| 2007 | iter_reg = fw->rcvt0_data_dma_reg; | |
| 2008 | iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); | |
| 2009 | qla24xx_read_window(reg, 0x7710, 16, iter_reg); | |
| 2010 | ||
| 2011 | iter_reg = fw->rcvt1_data_dma_reg; | |
| 2012 | iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); | |
| 2013 | qla24xx_read_window(reg, 0x7730, 16, iter_reg); | |
| 2014 | ||
| 2015 | /* RISC registers. */ | |
| 2016 | iter_reg = fw->risc_gp_reg; | |
| 2017 | iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); | |
| 2018 | iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); | |
| 2019 | iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); | |
| 2020 | iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); | |
| 2021 | iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); | |
| 2022 | iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); | |
| 2023 | iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); | |
| 2024 | qla24xx_read_window(reg, 0x0F70, 16, iter_reg); | |
| 2025 | ||
| 2026 | /* Local memory controller registers. */ | |
| 2027 | iter_reg = fw->lmc_reg; | |
| 2028 | iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); | |
| 2029 | iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); | |
| 2030 | iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); | |
| 2031 | iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); | |
| 2032 | iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); | |
| 2033 | iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); | |
| 2034 | iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg); | |
| 2035 | qla24xx_read_window(reg, 0x3070, 16, iter_reg); | |
| 2036 | ||
| 2037 | /* Fibre Protocol Module registers. */ | |
| 2038 | iter_reg = fw->fpm_hdw_reg; | |
| 2039 | iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); | |
| 2040 | iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); | |
| 2041 | iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); | |
| 2042 | iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); | |
| 2043 | iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); | |
| 2044 | iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); | |
| 2045 | iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); | |
| 2046 | iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); | |
| 2047 | iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); | |
| 2048 | iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); | |
| 2049 | iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); | |
| 2050 | iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg); | |
| 2051 | iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg); | |
| 2052 | iter_reg = qla24xx_read_window(reg, 0x40D0, 16, iter_reg); | |
| 2053 | iter_reg = qla24xx_read_window(reg, 0x40E0, 16, iter_reg); | |
| 2054 | qla24xx_read_window(reg, 0x40F0, 16, iter_reg); | |
| 2055 | ||
| 2056 | /* RQ0 Array registers. */ | |
| 2057 | iter_reg = fw->rq0_array_reg; | |
| 2058 | iter_reg = qla24xx_read_window(reg, 0x5C00, 16, iter_reg); | |
| 2059 | iter_reg = qla24xx_read_window(reg, 0x5C10, 16, iter_reg); | |
| 2060 | iter_reg = qla24xx_read_window(reg, 0x5C20, 16, iter_reg); | |
| 2061 | iter_reg = qla24xx_read_window(reg, 0x5C30, 16, iter_reg); | |
| 2062 | iter_reg = qla24xx_read_window(reg, 0x5C40, 16, iter_reg); | |
| 2063 | iter_reg = qla24xx_read_window(reg, 0x5C50, 16, iter_reg); | |
| 2064 | iter_reg = qla24xx_read_window(reg, 0x5C60, 16, iter_reg); | |
| 2065 | iter_reg = qla24xx_read_window(reg, 0x5C70, 16, iter_reg); | |
| 2066 | iter_reg = qla24xx_read_window(reg, 0x5C80, 16, iter_reg); | |
| 2067 | iter_reg = qla24xx_read_window(reg, 0x5C90, 16, iter_reg); | |
| 2068 | iter_reg = qla24xx_read_window(reg, 0x5CA0, 16, iter_reg); | |
| 2069 | iter_reg = qla24xx_read_window(reg, 0x5CB0, 16, iter_reg); | |
| 2070 | iter_reg = qla24xx_read_window(reg, 0x5CC0, 16, iter_reg); | |
| 2071 | iter_reg = qla24xx_read_window(reg, 0x5CD0, 16, iter_reg); | |
| 2072 | iter_reg = qla24xx_read_window(reg, 0x5CE0, 16, iter_reg); | |
| 2073 | qla24xx_read_window(reg, 0x5CF0, 16, iter_reg); | |
| 2074 | ||
| 2075 | /* RQ1 Array registers. */ | |
| 2076 | iter_reg = fw->rq1_array_reg; | |
| 2077 | iter_reg = qla24xx_read_window(reg, 0x5D00, 16, iter_reg); | |
| 2078 | iter_reg = qla24xx_read_window(reg, 0x5D10, 16, iter_reg); | |
| 2079 | iter_reg = qla24xx_read_window(reg, 0x5D20, 16, iter_reg); | |
| 2080 | iter_reg = qla24xx_read_window(reg, 0x5D30, 16, iter_reg); | |
| 2081 | iter_reg = qla24xx_read_window(reg, 0x5D40, 16, iter_reg); | |
| 2082 | iter_reg = qla24xx_read_window(reg, 0x5D50, 16, iter_reg); | |
| 2083 | iter_reg = qla24xx_read_window(reg, 0x5D60, 16, iter_reg); | |
| 2084 | iter_reg = qla24xx_read_window(reg, 0x5D70, 16, iter_reg); | |
| 2085 | iter_reg = qla24xx_read_window(reg, 0x5D80, 16, iter_reg); | |
| 2086 | iter_reg = qla24xx_read_window(reg, 0x5D90, 16, iter_reg); | |
| 2087 | iter_reg = qla24xx_read_window(reg, 0x5DA0, 16, iter_reg); | |
| 2088 | iter_reg = qla24xx_read_window(reg, 0x5DB0, 16, iter_reg); | |
| 2089 | iter_reg = qla24xx_read_window(reg, 0x5DC0, 16, iter_reg); | |
| 2090 | iter_reg = qla24xx_read_window(reg, 0x5DD0, 16, iter_reg); | |
| 2091 | iter_reg = qla24xx_read_window(reg, 0x5DE0, 16, iter_reg); | |
| 2092 | qla24xx_read_window(reg, 0x5DF0, 16, iter_reg); | |
| 2093 | ||
| 2094 | /* RP0 Array registers. */ | |
| 2095 | iter_reg = fw->rp0_array_reg; | |
| 2096 | iter_reg = qla24xx_read_window(reg, 0x5E00, 16, iter_reg); | |
| 2097 | iter_reg = qla24xx_read_window(reg, 0x5E10, 16, iter_reg); | |
| 2098 | iter_reg = qla24xx_read_window(reg, 0x5E20, 16, iter_reg); | |
| 2099 | iter_reg = qla24xx_read_window(reg, 0x5E30, 16, iter_reg); | |
| 2100 | iter_reg = qla24xx_read_window(reg, 0x5E40, 16, iter_reg); | |
| 2101 | iter_reg = qla24xx_read_window(reg, 0x5E50, 16, iter_reg); | |
| 2102 | iter_reg = qla24xx_read_window(reg, 0x5E60, 16, iter_reg); | |
| 2103 | iter_reg = qla24xx_read_window(reg, 0x5E70, 16, iter_reg); | |
| 2104 | iter_reg = qla24xx_read_window(reg, 0x5E80, 16, iter_reg); | |
| 2105 | iter_reg = qla24xx_read_window(reg, 0x5E90, 16, iter_reg); | |
| 2106 | iter_reg = qla24xx_read_window(reg, 0x5EA0, 16, iter_reg); | |
| 2107 | iter_reg = qla24xx_read_window(reg, 0x5EB0, 16, iter_reg); | |
| 2108 | iter_reg = qla24xx_read_window(reg, 0x5EC0, 16, iter_reg); | |
| 2109 | iter_reg = qla24xx_read_window(reg, 0x5ED0, 16, iter_reg); | |
| 2110 | iter_reg = qla24xx_read_window(reg, 0x5EE0, 16, iter_reg); | |
| 2111 | qla24xx_read_window(reg, 0x5EF0, 16, iter_reg); | |
| 2112 | ||
| 2113 | /* RP1 Array registers. */ | |
| 2114 | iter_reg = fw->rp1_array_reg; | |
| 2115 | iter_reg = qla24xx_read_window(reg, 0x5F00, 16, iter_reg); | |
| 2116 | iter_reg = qla24xx_read_window(reg, 0x5F10, 16, iter_reg); | |
| 2117 | iter_reg = qla24xx_read_window(reg, 0x5F20, 16, iter_reg); | |
| 2118 | iter_reg = qla24xx_read_window(reg, 0x5F30, 16, iter_reg); | |
| 2119 | iter_reg = qla24xx_read_window(reg, 0x5F40, 16, iter_reg); | |
| 2120 | iter_reg = qla24xx_read_window(reg, 0x5F50, 16, iter_reg); | |
| 2121 | iter_reg = qla24xx_read_window(reg, 0x5F60, 16, iter_reg); | |
| 2122 | iter_reg = qla24xx_read_window(reg, 0x5F70, 16, iter_reg); | |
| 2123 | iter_reg = qla24xx_read_window(reg, 0x5F80, 16, iter_reg); | |
| 2124 | iter_reg = qla24xx_read_window(reg, 0x5F90, 16, iter_reg); | |
| 2125 | iter_reg = qla24xx_read_window(reg, 0x5FA0, 16, iter_reg); | |
| 2126 | iter_reg = qla24xx_read_window(reg, 0x5FB0, 16, iter_reg); | |
| 2127 | iter_reg = qla24xx_read_window(reg, 0x5FC0, 16, iter_reg); | |
| 2128 | iter_reg = qla24xx_read_window(reg, 0x5FD0, 16, iter_reg); | |
| 2129 | iter_reg = qla24xx_read_window(reg, 0x5FE0, 16, iter_reg); | |
| 2130 | qla24xx_read_window(reg, 0x5FF0, 16, iter_reg); | |
| 2131 | ||
| 2132 | iter_reg = fw->at0_array_reg; | |
| 2133 | iter_reg = qla24xx_read_window(reg, 0x7080, 16, iter_reg); | |
| 2134 | iter_reg = qla24xx_read_window(reg, 0x7090, 16, iter_reg); | |
| 2135 | iter_reg = qla24xx_read_window(reg, 0x70A0, 16, iter_reg); | |
| 2136 | iter_reg = qla24xx_read_window(reg, 0x70B0, 16, iter_reg); | |
| 2137 | iter_reg = qla24xx_read_window(reg, 0x70C0, 16, iter_reg); | |
| 2138 | iter_reg = qla24xx_read_window(reg, 0x70D0, 16, iter_reg); | |
| 2139 | iter_reg = qla24xx_read_window(reg, 0x70E0, 16, iter_reg); | |
| 2140 | qla24xx_read_window(reg, 0x70F0, 16, iter_reg); | |
| 2141 | ||
| 2142 | /* I/O Queue Control registers. */ | |
| 2143 | qla24xx_read_window(reg, 0x7800, 16, fw->queue_control_reg); | |
| 2144 | ||
| 2145 | /* Frame Buffer registers. */ | |
| 2146 | iter_reg = fw->fb_hdw_reg; | |
| 2147 | iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); | |
| 2148 | iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); | |
| 2149 | iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); | |
| 2150 | iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); | |
| 2151 | iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); | |
| 2152 | iter_reg = qla24xx_read_window(reg, 0x6060, 16, iter_reg); | |
| 2153 | iter_reg = qla24xx_read_window(reg, 0x6070, 16, iter_reg); | |
| 2154 | iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); | |
| 2155 | iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); | |
| 2156 | iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); | |
| 2157 | iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); | |
| 2158 | iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); | |
| 2159 | iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg); | |
| 2160 | iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg); | |
| 2161 | iter_reg = qla24xx_read_window(reg, 0x6530, 16, iter_reg); | |
| 2162 | iter_reg = qla24xx_read_window(reg, 0x6540, 16, iter_reg); | |
| 2163 | iter_reg = qla24xx_read_window(reg, 0x6550, 16, iter_reg); | |
| 2164 | iter_reg = qla24xx_read_window(reg, 0x6560, 16, iter_reg); | |
| 2165 | iter_reg = qla24xx_read_window(reg, 0x6570, 16, iter_reg); | |
| 2166 | iter_reg = qla24xx_read_window(reg, 0x6580, 16, iter_reg); | |
| 2167 | iter_reg = qla24xx_read_window(reg, 0x6590, 16, iter_reg); | |
| 2168 | iter_reg = qla24xx_read_window(reg, 0x65A0, 16, iter_reg); | |
| 2169 | iter_reg = qla24xx_read_window(reg, 0x65B0, 16, iter_reg); | |
| 2170 | iter_reg = qla24xx_read_window(reg, 0x65C0, 16, iter_reg); | |
| 2171 | iter_reg = qla24xx_read_window(reg, 0x65D0, 16, iter_reg); | |
| 2172 | iter_reg = qla24xx_read_window(reg, 0x65E0, 16, iter_reg); | |
| 2173 | qla24xx_read_window(reg, 0x6F00, 16, iter_reg); | |
| 2174 | ||
| 2175 | /* Multi queue registers */ | |
| 2176 | nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset, | |
| 2177 | &last_chain); | |
| 2178 | ||
| 2179 | rval = qla24xx_soft_reset(ha); | |
| 2180 | if (rval != QLA_SUCCESS) { | |
| 2181 | ql_log(ql_log_warn, vha, 0xd00e, | |
| 2182 | "SOFT RESET FAILED, forcing continuation of dump!!!\n"); | |
| 2183 | rval = QLA_SUCCESS; | |
| 2184 | ||
| 2185 | ql_log(ql_log_warn, vha, 0xd00f, "try a bigger hammer!!!\n"); | |
| 2186 | ||
| 2187 | WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_RESET); | |
| 2188 | RD_REG_DWORD(®->hccr); | |
| 2189 | ||
| 2190 | WRT_REG_DWORD(®->hccr, HCCRX_REL_RISC_PAUSE); | |
| 2191 | RD_REG_DWORD(®->hccr); | |
| 2192 | ||
| 2193 | WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET); | |
| 2194 | RD_REG_DWORD(®->hccr); | |
| 2195 | ||
| 2196 | for (cnt = 30000; cnt && (RD_REG_WORD(®->mailbox0)); cnt--) | |
| 2197 | udelay(5); | |
| 2198 | ||
| 2199 | if (!cnt) { | |
| 2200 | nxt = fw->code_ram; | |
| 2201 | nxt += sizeof(fw->code_ram), | |
| 2202 | nxt += (ha->fw_memory_size - 0x100000 + 1); | |
| 2203 | goto copy_queue; | |
| 2204 | } else | |
| 2205 | ql_log(ql_log_warn, vha, 0xd010, | |
| 2206 | "bigger hammer success?\n"); | |
| 2207 | } | |
| 2208 | ||
| 2209 | rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), | |
| 2210 | &nxt); | |
| 2211 | if (rval != QLA_SUCCESS) | |
| 2212 | goto qla83xx_fw_dump_failed_0; | |
| 2213 | ||
| 2214 | copy_queue: | |
| 2215 | nxt = qla2xxx_copy_queues(ha, nxt); | |
| 2216 | ||
| 2217 | nxt = qla24xx_copy_eft(ha, nxt); | |
| 2218 | ||
| 2219 | /* Chain entries -- started with MQ. */ | |
| 2220 | nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain); | |
| 2221 | nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain); | |
| 2222 | if (last_chain) { | |
| 2223 | ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT); | |
| 2224 | *last_chain |= __constant_htonl(DUMP_CHAIN_LAST); | |
| 2225 | } | |
| 2226 | ||
| 2227 | /* Adjust valid length. */ | |
| 2228 | ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump); | |
| 2229 | ||
| 2230 | qla83xx_fw_dump_failed_0: | |
| 2231 | qla2xxx_dump_post_process(base_vha, rval); | |
| 2232 | ||
| 2233 | qla83xx_fw_dump_failed: | |
| 2234 | if (!hardware_locked) | |
| 2235 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
| 2236 | } | |
| 2237 | ||
| 1da177e4 LT |
2238 | /****************************************************************************/ |
| 2239 | /* Driver Debug Functions. */ | |
| 2240 | /****************************************************************************/ | |
| cfb0919c CD |
2241 | |
| 2242 | static inline int | |
| 2243 | ql_mask_match(uint32_t level) | |
| 2244 | { | |
| 2245 | if (ql2xextended_error_logging == 1) | |
| 2246 | ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK; | |
| 2247 | return (level & ql2xextended_error_logging) == level; | |
| 2248 | } | |
| 2249 | ||
| 3ce8866c SK |
2250 | /* |
| 2251 | * This function is for formatting and logging debug information. | |
| 2252 | * It is to be used when vha is available. It formats the message | |
| 2253 | * and logs it to the messages file. | |
| 2254 | * parameters: | |
| 2255 | * level: The level of the debug messages to be printed. | |
| 2256 | * If ql2xextended_error_logging value is correctly set, | |
| 2257 | * this message will appear in the messages file. | |
| 2258 | * vha: Pointer to the scsi_qla_host_t. | |
| 2259 | * id: This is a unique identifier for the level. It identifies the | |
| 2260 | * part of the code from where the message originated. | |
| 2261 | * msg: The message to be displayed. | |
| 2262 | */ | |
| 2263 | void | |
| 086b3e8a JP |
2264 | ql_dbg(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...) |
| 2265 | { | |
| 2266 | va_list va; | |
| 2267 | struct va_format vaf; | |
| 3ce8866c | 2268 | |
| cfb0919c | 2269 | if (!ql_mask_match(level)) |
| 086b3e8a | 2270 | return; |
| 3ce8866c | 2271 | |
| 086b3e8a | 2272 | va_start(va, fmt); |
| 3ce8866c | 2273 | |
| 086b3e8a JP |
2274 | vaf.fmt = fmt; |
| 2275 | vaf.va = &va; | |
| 3ce8866c | 2276 | |
| 086b3e8a JP |
2277 | if (vha != NULL) { |
| 2278 | const struct pci_dev *pdev = vha->hw->pdev; | |
| 2279 | /* <module-name> <pci-name> <msg-id>:<host> Message */ | |
| 2280 | pr_warn("%s [%s]-%04x:%ld: %pV", | |
| 2281 | QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset, | |
| 2282 | vha->host_no, &vaf); | |
| 2283 | } else { | |
| 2284 | pr_warn("%s [%s]-%04x: : %pV", | |
| 2285 | QL_MSGHDR, "0000:00:00.0", id + ql_dbg_offset, &vaf); | |
| 3ce8866c SK |
2286 | } |
| 2287 | ||
| 086b3e8a | 2288 | va_end(va); |
| 3ce8866c SK |
2289 | |
| 2290 | } | |
| 2291 | ||
| 2292 | /* | |
| 2293 | * This function is for formatting and logging debug information. | |
| 2294 | * It is to be used when vha is not available and pci is availble, | |
| 2295 | * i.e., before host allocation. It formats the message and logs it | |
| 2296 | * to the messages file. | |
| 2297 | * parameters: | |
| 2298 | * level: The level of the debug messages to be printed. | |
| 2299 | * If ql2xextended_error_logging value is correctly set, | |
| 2300 | * this message will appear in the messages file. | |
| 2301 | * pdev: Pointer to the struct pci_dev. | |
| 2302 | * id: This is a unique id for the level. It identifies the part | |
| 2303 | * of the code from where the message originated. | |
| 2304 | * msg: The message to be displayed. | |
| 2305 | */ | |
| 2306 | void | |
| 086b3e8a JP |
2307 | ql_dbg_pci(uint32_t level, struct pci_dev *pdev, int32_t id, |
| 2308 | const char *fmt, ...) | |
| 2309 | { | |
| 2310 | va_list va; | |
| 2311 | struct va_format vaf; | |
| 3ce8866c SK |
2312 | |
| 2313 | if (pdev == NULL) | |
| 2314 | return; | |
| cfb0919c | 2315 | if (!ql_mask_match(level)) |
| 086b3e8a | 2316 | return; |
| 3ce8866c | 2317 | |
| 086b3e8a | 2318 | va_start(va, fmt); |
| 3ce8866c | 2319 | |
| 086b3e8a JP |
2320 | vaf.fmt = fmt; |
| 2321 | vaf.va = &va; | |
| 3ce8866c | 2322 | |
| 086b3e8a JP |
2323 | /* <module-name> <dev-name>:<msg-id> Message */ |
| 2324 | pr_warn("%s [%s]-%04x: : %pV", | |
| 2325 | QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset, &vaf); | |
| 3ce8866c | 2326 | |
| 086b3e8a | 2327 | va_end(va); |
| 3ce8866c SK |
2328 | } |
| 2329 | ||
| 2330 | /* | |
| 2331 | * This function is for formatting and logging log messages. | |
| 2332 | * It is to be used when vha is available. It formats the message | |
| 2333 | * and logs it to the messages file. All the messages will be logged | |
| 2334 | * irrespective of value of ql2xextended_error_logging. | |
| 2335 | * parameters: | |
| 2336 | * level: The level of the log messages to be printed in the | |
| 2337 | * messages file. | |
| 2338 | * vha: Pointer to the scsi_qla_host_t | |
| 2339 | * id: This is a unique id for the level. It identifies the | |
| 2340 | * part of the code from where the message originated. | |
| 2341 | * msg: The message to be displayed. | |
| 2342 | */ | |
| 2343 | void | |
| 086b3e8a JP |
2344 | ql_log(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...) |
| 2345 | { | |
| 2346 | va_list va; | |
| 2347 | struct va_format vaf; | |
| 2348 | char pbuf[128]; | |
| 3ce8866c | 2349 | |
| 086b3e8a JP |
2350 | if (level > ql_errlev) |
| 2351 | return; | |
| 3ce8866c | 2352 | |
| 086b3e8a JP |
2353 | if (vha != NULL) { |
| 2354 | const struct pci_dev *pdev = vha->hw->pdev; | |
| 2355 | /* <module-name> <msg-id>:<host> Message */ | |
| 2356 | snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x:%ld: ", | |
| 2357 | QL_MSGHDR, dev_name(&(pdev->dev)), id, vha->host_no); | |
| 2358 | } else { | |
| 2359 | snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ", | |
| 2360 | QL_MSGHDR, "0000:00:00.0", id); | |
| 2361 | } | |
| 2362 | pbuf[sizeof(pbuf) - 1] = 0; | |
| 2363 | ||
| 2364 | va_start(va, fmt); | |
| 2365 | ||
| 2366 | vaf.fmt = fmt; | |
| 2367 | vaf.va = &va; | |
| 2368 | ||
| 2369 | switch (level) { | |
| 70a3fc76 | 2370 | case ql_log_fatal: /* FATAL LOG */ |
| 086b3e8a JP |
2371 | pr_crit("%s%pV", pbuf, &vaf); |
| 2372 | break; | |
| 70a3fc76 | 2373 | case ql_log_warn: |
| 086b3e8a JP |
2374 | pr_err("%s%pV", pbuf, &vaf); |
| 2375 | break; | |
| 70a3fc76 | 2376 | case ql_log_info: |
| 086b3e8a JP |
2377 | pr_warn("%s%pV", pbuf, &vaf); |
| 2378 | break; | |
| 2379 | default: | |
| 2380 | pr_info("%s%pV", pbuf, &vaf); | |
| 2381 | break; | |
| 3ce8866c SK |
2382 | } |
| 2383 | ||
| 086b3e8a | 2384 | va_end(va); |
| 3ce8866c SK |
2385 | } |
| 2386 | ||
| 2387 | /* | |
| 2388 | * This function is for formatting and logging log messages. | |
| 2389 | * It is to be used when vha is not available and pci is availble, | |
| 2390 | * i.e., before host allocation. It formats the message and logs | |
| 2391 | * it to the messages file. All the messages are logged irrespective | |
| 2392 | * of the value of ql2xextended_error_logging. | |
| 2393 | * parameters: | |
| 2394 | * level: The level of the log messages to be printed in the | |
| 2395 | * messages file. | |
| 2396 | * pdev: Pointer to the struct pci_dev. | |
| 2397 | * id: This is a unique id for the level. It identifies the | |
| 2398 | * part of the code from where the message originated. | |
| 2399 | * msg: The message to be displayed. | |
| 2400 | */ | |
| 2401 | void | |
| 086b3e8a JP |
2402 | ql_log_pci(uint32_t level, struct pci_dev *pdev, int32_t id, |
| 2403 | const char *fmt, ...) | |
| 2404 | { | |
| 2405 | va_list va; | |
| 2406 | struct va_format vaf; | |
| 2407 | char pbuf[128]; | |
| 3ce8866c SK |
2408 | |
| 2409 | if (pdev == NULL) | |
| 2410 | return; | |
| 086b3e8a JP |
2411 | if (level > ql_errlev) |
| 2412 | return; | |
| 3ce8866c | 2413 | |
| 086b3e8a JP |
2414 | /* <module-name> <dev-name>:<msg-id> Message */ |
| 2415 | snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ", | |
| 2416 | QL_MSGHDR, dev_name(&(pdev->dev)), id); | |
| 2417 | pbuf[sizeof(pbuf) - 1] = 0; | |
| 2418 | ||
| 2419 | va_start(va, fmt); | |
| 2420 | ||
| 2421 | vaf.fmt = fmt; | |
| 2422 | vaf.va = &va; | |
| 2423 | ||
| 2424 | switch (level) { | |
| 70a3fc76 | 2425 | case ql_log_fatal: /* FATAL LOG */ |
| 086b3e8a JP |
2426 | pr_crit("%s%pV", pbuf, &vaf); |
| 2427 | break; | |
| 70a3fc76 | 2428 | case ql_log_warn: |
| 086b3e8a JP |
2429 | pr_err("%s%pV", pbuf, &vaf); |
| 2430 | break; | |
| 70a3fc76 | 2431 | case ql_log_info: |
| 086b3e8a JP |
2432 | pr_warn("%s%pV", pbuf, &vaf); |
| 2433 | break; | |
| 2434 | default: | |
| 2435 | pr_info("%s%pV", pbuf, &vaf); | |
| 2436 | break; | |
| 3ce8866c SK |
2437 | } |
| 2438 | ||
| 086b3e8a | 2439 | va_end(va); |
| 3ce8866c SK |
2440 | } |
| 2441 | ||
| 2442 | void | |
| 2443 | ql_dump_regs(uint32_t level, scsi_qla_host_t *vha, int32_t id) | |
| 2444 | { | |
| 2445 | int i; | |
| 2446 | struct qla_hw_data *ha = vha->hw; | |
| 2447 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
| 2448 | struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; | |
| 2449 | struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82; | |
| 2450 | uint16_t __iomem *mbx_reg; | |
| 2451 | ||
| cfb0919c CD |
2452 | if (!ql_mask_match(level)) |
| 2453 | return; | |
| 3ce8866c | 2454 | |
| cfb0919c CD |
2455 | if (IS_QLA82XX(ha)) |
| 2456 | mbx_reg = ®82->mailbox_in[0]; | |
| 2457 | else if (IS_FWI2_CAPABLE(ha)) | |
| 2458 | mbx_reg = ®24->mailbox0; | |
| 2459 | else | |
| 2460 | mbx_reg = MAILBOX_REG(ha, reg, 0); | |
| 2461 | ||
| 2462 | ql_dbg(level, vha, id, "Mailbox registers:\n"); | |
| 2463 | for (i = 0; i < 6; i++) | |
| 2464 | ql_dbg(level, vha, id, | |
| 2465 | "mbox[%d] 0x%04x\n", i, RD_REG_WORD(mbx_reg++)); | |
| 3ce8866c SK |
2466 | } |
| 2467 | ||
| 2468 | ||
| 2469 | void | |
| 2470 | ql_dump_buffer(uint32_t level, scsi_qla_host_t *vha, int32_t id, | |
| 2471 | uint8_t *b, uint32_t size) | |
| 2472 | { | |
| 2473 | uint32_t cnt; | |
| 2474 | uint8_t c; | |
| cfb0919c CD |
2475 | |
| 2476 | if (!ql_mask_match(level)) | |
| 2477 | return; | |
| 2478 | ||
| 2479 | ql_dbg(level, vha, id, " 0 1 2 3 4 5 6 7 8 " | |
| 2480 | "9 Ah Bh Ch Dh Eh Fh\n"); | |
| 2481 | ql_dbg(level, vha, id, "----------------------------------" | |
| 2482 | "----------------------------\n"); | |
| 2483 | ||
| 2484 | ql_dbg(level, vha, id, " "); | |
| 2485 | for (cnt = 0; cnt < size;) { | |
| 2486 | c = *b++; | |
| 2487 | printk("%02x", (uint32_t) c); | |
| 2488 | cnt++; | |
| 2489 | if (!(cnt % 16)) | |
| 2490 | printk("\n"); | |
| 2491 | else | |
| 2492 | printk(" "); | |
| 3ce8866c | 2493 | } |
| cfb0919c CD |
2494 | if (cnt % 16) |
| 2495 | ql_dbg(level, vha, id, "\n"); | |
| 3ce8866c | 2496 | } |