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Commit | Line | Data |
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1da177e4 | 1 | /* |
fa90c54f AV |
2 | * QLogic Fibre Channel HBA Driver |
3 | * Copyright (c) 2003-2005 QLogic Corporation | |
1da177e4 | 4 | * |
fa90c54f | 5 | * See LICENSE.qla2xxx for copyright and licensing details. |
1da177e4 LT |
6 | */ |
7 | #include "qla_def.h" | |
8 | ||
9 | #include <linux/delay.h> | |
10 | ||
a7a167bf AV |
11 | static inline void |
12 | qla2xxx_prep_dump(scsi_qla_host_t *ha, struct qla2xxx_fw_dump *fw_dump) | |
13 | { | |
14 | fw_dump->fw_major_version = htonl(ha->fw_major_version); | |
15 | fw_dump->fw_minor_version = htonl(ha->fw_minor_version); | |
16 | fw_dump->fw_subminor_version = htonl(ha->fw_subminor_version); | |
17 | fw_dump->fw_attributes = htonl(ha->fw_attributes); | |
18 | ||
19 | fw_dump->vendor = htonl(ha->pdev->vendor); | |
20 | fw_dump->device = htonl(ha->pdev->device); | |
21 | fw_dump->subsystem_vendor = htonl(ha->pdev->subsystem_vendor); | |
22 | fw_dump->subsystem_device = htonl(ha->pdev->subsystem_device); | |
23 | } | |
24 | ||
25 | static inline void * | |
26 | qla2xxx_copy_queues(scsi_qla_host_t *ha, void *ptr) | |
27 | { | |
28 | /* Request queue. */ | |
29 | memcpy(ptr, ha->request_ring, ha->request_q_length * | |
30 | sizeof(request_t)); | |
31 | ||
32 | /* Response queue. */ | |
33 | ptr += ha->request_q_length * sizeof(request_t); | |
34 | memcpy(ptr, ha->response_ring, ha->response_q_length * | |
35 | sizeof(response_t)); | |
36 | ||
37 | return ptr + (ha->response_q_length * sizeof(response_t)); | |
38 | } | |
1da177e4 | 39 | |
c3a2f0df AV |
40 | static int |
41 | qla2xxx_dump_memory(scsi_qla_host_t *ha, uint32_t *code_ram, | |
42 | uint32_t cram_size, uint32_t *ext_mem, void **nxt) | |
43 | { | |
44 | int rval; | |
45 | uint32_t cnt, stat, timer, risc_address, ext_mem_cnt; | |
46 | uint16_t mb[4]; | |
47 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | |
48 | ||
49 | rval = QLA_SUCCESS; | |
50 | risc_address = ext_mem_cnt = 0; | |
51 | memset(mb, 0, sizeof(mb)); | |
52 | ||
53 | /* Code RAM. */ | |
54 | risc_address = 0x20000; | |
55 | WRT_REG_WORD(®->mailbox0, MBC_READ_RAM_EXTENDED); | |
56 | clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); | |
57 | ||
58 | for (cnt = 0; cnt < cram_size / 4 && rval == QLA_SUCCESS; | |
59 | cnt++, risc_address++) { | |
60 | WRT_REG_WORD(®->mailbox1, LSW(risc_address)); | |
61 | WRT_REG_WORD(®->mailbox8, MSW(risc_address)); | |
62 | RD_REG_WORD(®->mailbox8); | |
63 | WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT); | |
64 | ||
65 | for (timer = 6000000; timer; timer--) { | |
66 | /* Check for pending interrupts. */ | |
67 | stat = RD_REG_DWORD(®->host_status); | |
68 | if (stat & HSRX_RISC_INT) { | |
69 | stat &= 0xff; | |
70 | ||
71 | if (stat == 0x1 || stat == 0x2 || | |
72 | stat == 0x10 || stat == 0x11) { | |
73 | set_bit(MBX_INTERRUPT, | |
74 | &ha->mbx_cmd_flags); | |
75 | ||
76 | mb[0] = RD_REG_WORD(®->mailbox0); | |
77 | mb[2] = RD_REG_WORD(®->mailbox2); | |
78 | mb[3] = RD_REG_WORD(®->mailbox3); | |
79 | ||
80 | WRT_REG_DWORD(®->hccr, | |
81 | HCCRX_CLR_RISC_INT); | |
82 | RD_REG_DWORD(®->hccr); | |
83 | break; | |
84 | } | |
85 | ||
86 | /* Clear this intr; it wasn't a mailbox intr */ | |
87 | WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT); | |
88 | RD_REG_DWORD(®->hccr); | |
89 | } | |
90 | udelay(5); | |
91 | } | |
92 | ||
93 | if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { | |
94 | rval = mb[0] & MBS_MASK; | |
95 | code_ram[cnt] = htonl((mb[3] << 16) | mb[2]); | |
96 | } else { | |
97 | rval = QLA_FUNCTION_FAILED; | |
98 | } | |
99 | } | |
100 | ||
101 | if (rval == QLA_SUCCESS) { | |
102 | /* External Memory. */ | |
103 | risc_address = 0x100000; | |
104 | ext_mem_cnt = ha->fw_memory_size - 0x100000 + 1; | |
105 | WRT_REG_WORD(®->mailbox0, MBC_READ_RAM_EXTENDED); | |
106 | clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); | |
107 | } | |
108 | for (cnt = 0; cnt < ext_mem_cnt && rval == QLA_SUCCESS; | |
109 | cnt++, risc_address++) { | |
110 | WRT_REG_WORD(®->mailbox1, LSW(risc_address)); | |
111 | WRT_REG_WORD(®->mailbox8, MSW(risc_address)); | |
112 | RD_REG_WORD(®->mailbox8); | |
113 | WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT); | |
114 | ||
115 | for (timer = 6000000; timer; timer--) { | |
116 | /* Check for pending interrupts. */ | |
117 | stat = RD_REG_DWORD(®->host_status); | |
118 | if (stat & HSRX_RISC_INT) { | |
119 | stat &= 0xff; | |
120 | ||
121 | if (stat == 0x1 || stat == 0x2 || | |
122 | stat == 0x10 || stat == 0x11) { | |
123 | set_bit(MBX_INTERRUPT, | |
124 | &ha->mbx_cmd_flags); | |
125 | ||
126 | mb[0] = RD_REG_WORD(®->mailbox0); | |
127 | mb[2] = RD_REG_WORD(®->mailbox2); | |
128 | mb[3] = RD_REG_WORD(®->mailbox3); | |
129 | ||
130 | WRT_REG_DWORD(®->hccr, | |
131 | HCCRX_CLR_RISC_INT); | |
132 | RD_REG_DWORD(®->hccr); | |
133 | break; | |
134 | } | |
135 | ||
136 | /* Clear this intr; it wasn't a mailbox intr */ | |
137 | WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT); | |
138 | RD_REG_DWORD(®->hccr); | |
139 | } | |
140 | udelay(5); | |
141 | } | |
142 | ||
143 | if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { | |
144 | rval = mb[0] & MBS_MASK; | |
145 | ext_mem[cnt] = htonl((mb[3] << 16) | mb[2]); | |
146 | } else { | |
147 | rval = QLA_FUNCTION_FAILED; | |
148 | } | |
149 | } | |
150 | ||
151 | *nxt = rval == QLA_SUCCESS ? &ext_mem[cnt]: NULL; | |
152 | return rval; | |
153 | } | |
154 | ||
1da177e4 LT |
155 | /** |
156 | * qla2300_fw_dump() - Dumps binary data from the 2300 firmware. | |
157 | * @ha: HA context | |
158 | * @hardware_locked: Called with the hardware_lock | |
159 | */ | |
160 | void | |
161 | qla2300_fw_dump(scsi_qla_host_t *ha, int hardware_locked) | |
162 | { | |
163 | int rval; | |
164 | uint32_t cnt, timer; | |
165 | uint32_t risc_address; | |
166 | uint16_t mb0, mb2; | |
167 | ||
168 | uint32_t stat; | |
3d71644c | 169 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
1da177e4 LT |
170 | uint16_t __iomem *dmp_reg; |
171 | unsigned long flags; | |
172 | struct qla2300_fw_dump *fw; | |
d4e3e04d | 173 | uint32_t data_ram_cnt; |
1da177e4 LT |
174 | |
175 | risc_address = data_ram_cnt = 0; | |
176 | mb0 = mb2 = 0; | |
177 | flags = 0; | |
178 | ||
179 | if (!hardware_locked) | |
180 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
181 | ||
d4e3e04d | 182 | if (!ha->fw_dump) { |
1da177e4 | 183 | qla_printk(KERN_WARNING, ha, |
d4e3e04d | 184 | "No buffer available for dump!!!\n"); |
1da177e4 LT |
185 | goto qla2300_fw_dump_failed; |
186 | } | |
187 | ||
d4e3e04d | 188 | if (ha->fw_dumped) { |
1da177e4 | 189 | qla_printk(KERN_WARNING, ha, |
d4e3e04d AV |
190 | "Firmware has been previously dumped (%p) -- ignoring " |
191 | "request...\n", ha->fw_dump); | |
1da177e4 LT |
192 | goto qla2300_fw_dump_failed; |
193 | } | |
a7a167bf AV |
194 | fw = &ha->fw_dump->isp.isp23; |
195 | qla2xxx_prep_dump(ha, ha->fw_dump); | |
1da177e4 LT |
196 | |
197 | rval = QLA_SUCCESS; | |
a7a167bf | 198 | fw->hccr = htons(RD_REG_WORD(®->hccr)); |
1da177e4 LT |
199 | |
200 | /* Pause RISC. */ | |
fa2a1ce5 | 201 | WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); |
1da177e4 LT |
202 | if (IS_QLA2300(ha)) { |
203 | for (cnt = 30000; | |
204 | (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && | |
205 | rval == QLA_SUCCESS; cnt--) { | |
206 | if (cnt) | |
207 | udelay(100); | |
208 | else | |
209 | rval = QLA_FUNCTION_TIMEOUT; | |
210 | } | |
211 | } else { | |
212 | RD_REG_WORD(®->hccr); /* PCI Posting. */ | |
213 | udelay(10); | |
214 | } | |
215 | ||
216 | if (rval == QLA_SUCCESS) { | |
217 | dmp_reg = (uint16_t __iomem *)(reg + 0); | |
fa2a1ce5 | 218 | for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++) |
a7a167bf | 219 | fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 LT |
220 | |
221 | dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x10); | |
fa2a1ce5 | 222 | for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++) |
a7a167bf | 223 | fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 LT |
224 | |
225 | dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x40); | |
fa2a1ce5 | 226 | for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) |
a7a167bf | 227 | fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 LT |
228 | |
229 | WRT_REG_WORD(®->ctrl_status, 0x40); | |
230 | dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); | |
fa2a1ce5 | 231 | for (cnt = 0; cnt < sizeof(fw->resp_dma_reg) / 2; cnt++) |
a7a167bf | 232 | fw->resp_dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 LT |
233 | |
234 | WRT_REG_WORD(®->ctrl_status, 0x50); | |
235 | dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); | |
fa2a1ce5 | 236 | for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++) |
a7a167bf | 237 | fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 LT |
238 | |
239 | WRT_REG_WORD(®->ctrl_status, 0x00); | |
240 | dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0xA0); | |
fa2a1ce5 | 241 | for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++) |
a7a167bf | 242 | fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 | 243 | |
fa2a1ce5 | 244 | WRT_REG_WORD(®->pcr, 0x2000); |
1da177e4 | 245 | dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); |
fa2a1ce5 | 246 | for (cnt = 0; cnt < sizeof(fw->risc_gp0_reg) / 2; cnt++) |
a7a167bf | 247 | fw->risc_gp0_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 | 248 | |
fa2a1ce5 | 249 | WRT_REG_WORD(®->pcr, 0x2200); |
1da177e4 | 250 | dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); |
fa2a1ce5 | 251 | for (cnt = 0; cnt < sizeof(fw->risc_gp1_reg) / 2; cnt++) |
a7a167bf | 252 | fw->risc_gp1_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 | 253 | |
fa2a1ce5 | 254 | WRT_REG_WORD(®->pcr, 0x2400); |
1da177e4 | 255 | dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); |
fa2a1ce5 | 256 | for (cnt = 0; cnt < sizeof(fw->risc_gp2_reg) / 2; cnt++) |
a7a167bf | 257 | fw->risc_gp2_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 | 258 | |
fa2a1ce5 | 259 | WRT_REG_WORD(®->pcr, 0x2600); |
1da177e4 | 260 | dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); |
fa2a1ce5 | 261 | for (cnt = 0; cnt < sizeof(fw->risc_gp3_reg) / 2; cnt++) |
a7a167bf | 262 | fw->risc_gp3_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 | 263 | |
fa2a1ce5 | 264 | WRT_REG_WORD(®->pcr, 0x2800); |
1da177e4 | 265 | dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); |
fa2a1ce5 | 266 | for (cnt = 0; cnt < sizeof(fw->risc_gp4_reg) / 2; cnt++) |
a7a167bf | 267 | fw->risc_gp4_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 | 268 | |
fa2a1ce5 | 269 | WRT_REG_WORD(®->pcr, 0x2A00); |
1da177e4 | 270 | dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); |
fa2a1ce5 | 271 | for (cnt = 0; cnt < sizeof(fw->risc_gp5_reg) / 2; cnt++) |
a7a167bf | 272 | fw->risc_gp5_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 | 273 | |
fa2a1ce5 | 274 | WRT_REG_WORD(®->pcr, 0x2C00); |
1da177e4 | 275 | dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); |
fa2a1ce5 | 276 | for (cnt = 0; cnt < sizeof(fw->risc_gp6_reg) / 2; cnt++) |
a7a167bf | 277 | fw->risc_gp6_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 | 278 | |
fa2a1ce5 | 279 | WRT_REG_WORD(®->pcr, 0x2E00); |
1da177e4 | 280 | dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); |
fa2a1ce5 | 281 | for (cnt = 0; cnt < sizeof(fw->risc_gp7_reg) / 2; cnt++) |
a7a167bf | 282 | fw->risc_gp7_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 | 283 | |
fa2a1ce5 | 284 | WRT_REG_WORD(®->ctrl_status, 0x10); |
1da177e4 | 285 | dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); |
fa2a1ce5 | 286 | for (cnt = 0; cnt < sizeof(fw->frame_buf_hdw_reg) / 2; cnt++) |
a7a167bf AV |
287 | fw->frame_buf_hdw_reg[cnt] = |
288 | htons(RD_REG_WORD(dmp_reg++)); | |
1da177e4 | 289 | |
fa2a1ce5 | 290 | WRT_REG_WORD(®->ctrl_status, 0x20); |
1da177e4 | 291 | dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); |
fa2a1ce5 | 292 | for (cnt = 0; cnt < sizeof(fw->fpm_b0_reg) / 2; cnt++) |
a7a167bf | 293 | fw->fpm_b0_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 | 294 | |
fa2a1ce5 | 295 | WRT_REG_WORD(®->ctrl_status, 0x30); |
1da177e4 | 296 | dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); |
fa2a1ce5 | 297 | for (cnt = 0; cnt < sizeof(fw->fpm_b1_reg) / 2; cnt++) |
a7a167bf | 298 | fw->fpm_b1_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 LT |
299 | |
300 | /* Reset RISC. */ | |
301 | WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); | |
302 | for (cnt = 0; cnt < 30000; cnt++) { | |
303 | if ((RD_REG_WORD(®->ctrl_status) & | |
304 | CSR_ISP_SOFT_RESET) == 0) | |
305 | break; | |
306 | ||
307 | udelay(10); | |
308 | } | |
309 | } | |
310 | ||
311 | if (!IS_QLA2300(ha)) { | |
312 | for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 && | |
313 | rval == QLA_SUCCESS; cnt--) { | |
314 | if (cnt) | |
315 | udelay(100); | |
316 | else | |
317 | rval = QLA_FUNCTION_TIMEOUT; | |
318 | } | |
319 | } | |
320 | ||
321 | if (rval == QLA_SUCCESS) { | |
322 | /* Get RISC SRAM. */ | |
323 | risc_address = 0x800; | |
324 | WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD); | |
325 | clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); | |
326 | } | |
327 | for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS; | |
328 | cnt++, risc_address++) { | |
329 | WRT_MAILBOX_REG(ha, reg, 1, (uint16_t)risc_address); | |
330 | WRT_REG_WORD(®->hccr, HCCR_SET_HOST_INT); | |
331 | ||
332 | for (timer = 6000000; timer; timer--) { | |
333 | /* Check for pending interrupts. */ | |
334 | stat = RD_REG_DWORD(®->u.isp2300.host_status); | |
335 | if (stat & HSR_RISC_INT) { | |
336 | stat &= 0xff; | |
337 | ||
338 | if (stat == 0x1 || stat == 0x2) { | |
339 | set_bit(MBX_INTERRUPT, | |
340 | &ha->mbx_cmd_flags); | |
341 | ||
342 | mb0 = RD_MAILBOX_REG(ha, reg, 0); | |
343 | mb2 = RD_MAILBOX_REG(ha, reg, 2); | |
344 | ||
345 | /* Release mailbox registers. */ | |
346 | WRT_REG_WORD(®->semaphore, 0); | |
347 | WRT_REG_WORD(®->hccr, | |
348 | HCCR_CLR_RISC_INT); | |
349 | RD_REG_WORD(®->hccr); | |
350 | break; | |
351 | } else if (stat == 0x10 || stat == 0x11) { | |
352 | set_bit(MBX_INTERRUPT, | |
353 | &ha->mbx_cmd_flags); | |
354 | ||
355 | mb0 = RD_MAILBOX_REG(ha, reg, 0); | |
356 | mb2 = RD_MAILBOX_REG(ha, reg, 2); | |
357 | ||
358 | WRT_REG_WORD(®->hccr, | |
359 | HCCR_CLR_RISC_INT); | |
360 | RD_REG_WORD(®->hccr); | |
361 | break; | |
362 | } | |
363 | ||
364 | /* clear this intr; it wasn't a mailbox intr */ | |
365 | WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); | |
366 | RD_REG_WORD(®->hccr); | |
367 | } | |
368 | udelay(5); | |
369 | } | |
370 | ||
371 | if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { | |
372 | rval = mb0 & MBS_MASK; | |
a7a167bf | 373 | fw->risc_ram[cnt] = htons(mb2); |
1da177e4 LT |
374 | } else { |
375 | rval = QLA_FUNCTION_FAILED; | |
376 | } | |
377 | } | |
378 | ||
379 | if (rval == QLA_SUCCESS) { | |
380 | /* Get stack SRAM. */ | |
381 | risc_address = 0x10000; | |
382 | WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_EXTENDED); | |
383 | clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); | |
384 | } | |
385 | for (cnt = 0; cnt < sizeof(fw->stack_ram) / 2 && rval == QLA_SUCCESS; | |
386 | cnt++, risc_address++) { | |
387 | WRT_MAILBOX_REG(ha, reg, 1, LSW(risc_address)); | |
388 | WRT_MAILBOX_REG(ha, reg, 8, MSW(risc_address)); | |
389 | WRT_REG_WORD(®->hccr, HCCR_SET_HOST_INT); | |
390 | ||
391 | for (timer = 6000000; timer; timer--) { | |
392 | /* Check for pending interrupts. */ | |
393 | stat = RD_REG_DWORD(®->u.isp2300.host_status); | |
394 | if (stat & HSR_RISC_INT) { | |
395 | stat &= 0xff; | |
396 | ||
397 | if (stat == 0x1 || stat == 0x2) { | |
398 | set_bit(MBX_INTERRUPT, | |
399 | &ha->mbx_cmd_flags); | |
400 | ||
401 | mb0 = RD_MAILBOX_REG(ha, reg, 0); | |
402 | mb2 = RD_MAILBOX_REG(ha, reg, 2); | |
403 | ||
404 | /* Release mailbox registers. */ | |
405 | WRT_REG_WORD(®->semaphore, 0); | |
406 | WRT_REG_WORD(®->hccr, | |
407 | HCCR_CLR_RISC_INT); | |
408 | RD_REG_WORD(®->hccr); | |
409 | break; | |
410 | } else if (stat == 0x10 || stat == 0x11) { | |
411 | set_bit(MBX_INTERRUPT, | |
412 | &ha->mbx_cmd_flags); | |
413 | ||
414 | mb0 = RD_MAILBOX_REG(ha, reg, 0); | |
415 | mb2 = RD_MAILBOX_REG(ha, reg, 2); | |
416 | ||
417 | WRT_REG_WORD(®->hccr, | |
418 | HCCR_CLR_RISC_INT); | |
419 | RD_REG_WORD(®->hccr); | |
420 | break; | |
421 | } | |
422 | ||
423 | /* clear this intr; it wasn't a mailbox intr */ | |
424 | WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); | |
425 | RD_REG_WORD(®->hccr); | |
426 | } | |
427 | udelay(5); | |
428 | } | |
429 | ||
430 | if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { | |
431 | rval = mb0 & MBS_MASK; | |
a7a167bf | 432 | fw->stack_ram[cnt] = htons(mb2); |
1da177e4 LT |
433 | } else { |
434 | rval = QLA_FUNCTION_FAILED; | |
435 | } | |
436 | } | |
437 | ||
438 | if (rval == QLA_SUCCESS) { | |
439 | /* Get data SRAM. */ | |
440 | risc_address = 0x11000; | |
441 | data_ram_cnt = ha->fw_memory_size - risc_address + 1; | |
442 | WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_EXTENDED); | |
443 | clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); | |
444 | } | |
445 | for (cnt = 0; cnt < data_ram_cnt && rval == QLA_SUCCESS; | |
446 | cnt++, risc_address++) { | |
447 | WRT_MAILBOX_REG(ha, reg, 1, LSW(risc_address)); | |
448 | WRT_MAILBOX_REG(ha, reg, 8, MSW(risc_address)); | |
449 | WRT_REG_WORD(®->hccr, HCCR_SET_HOST_INT); | |
450 | ||
451 | for (timer = 6000000; timer; timer--) { | |
452 | /* Check for pending interrupts. */ | |
453 | stat = RD_REG_DWORD(®->u.isp2300.host_status); | |
454 | if (stat & HSR_RISC_INT) { | |
455 | stat &= 0xff; | |
456 | ||
457 | if (stat == 0x1 || stat == 0x2) { | |
458 | set_bit(MBX_INTERRUPT, | |
459 | &ha->mbx_cmd_flags); | |
460 | ||
461 | mb0 = RD_MAILBOX_REG(ha, reg, 0); | |
462 | mb2 = RD_MAILBOX_REG(ha, reg, 2); | |
463 | ||
464 | /* Release mailbox registers. */ | |
465 | WRT_REG_WORD(®->semaphore, 0); | |
466 | WRT_REG_WORD(®->hccr, | |
467 | HCCR_CLR_RISC_INT); | |
468 | RD_REG_WORD(®->hccr); | |
469 | break; | |
470 | } else if (stat == 0x10 || stat == 0x11) { | |
471 | set_bit(MBX_INTERRUPT, | |
472 | &ha->mbx_cmd_flags); | |
473 | ||
474 | mb0 = RD_MAILBOX_REG(ha, reg, 0); | |
475 | mb2 = RD_MAILBOX_REG(ha, reg, 2); | |
476 | ||
477 | WRT_REG_WORD(®->hccr, | |
478 | HCCR_CLR_RISC_INT); | |
479 | RD_REG_WORD(®->hccr); | |
480 | break; | |
481 | } | |
482 | ||
483 | /* clear this intr; it wasn't a mailbox intr */ | |
484 | WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); | |
485 | RD_REG_WORD(®->hccr); | |
486 | } | |
487 | udelay(5); | |
488 | } | |
489 | ||
490 | if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { | |
491 | rval = mb0 & MBS_MASK; | |
a7a167bf | 492 | fw->data_ram[cnt] = htons(mb2); |
1da177e4 LT |
493 | } else { |
494 | rval = QLA_FUNCTION_FAILED; | |
495 | } | |
496 | } | |
497 | ||
a7a167bf AV |
498 | if (rval == QLA_SUCCESS) |
499 | qla2xxx_copy_queues(ha, &fw->data_ram[cnt]); | |
500 | ||
1da177e4 LT |
501 | if (rval != QLA_SUCCESS) { |
502 | qla_printk(KERN_WARNING, ha, | |
503 | "Failed to dump firmware (%x)!!!\n", rval); | |
d4e3e04d | 504 | ha->fw_dumped = 0; |
1da177e4 | 505 | |
1da177e4 LT |
506 | } else { |
507 | qla_printk(KERN_INFO, ha, | |
508 | "Firmware dump saved to temp buffer (%ld/%p).\n", | |
509 | ha->host_no, ha->fw_dump); | |
d4e3e04d | 510 | ha->fw_dumped = 1; |
1da177e4 LT |
511 | } |
512 | ||
513 | qla2300_fw_dump_failed: | |
514 | if (!hardware_locked) | |
515 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
516 | } | |
517 | ||
1da177e4 LT |
518 | /** |
519 | * qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware. | |
520 | * @ha: HA context | |
521 | * @hardware_locked: Called with the hardware_lock | |
522 | */ | |
523 | void | |
524 | qla2100_fw_dump(scsi_qla_host_t *ha, int hardware_locked) | |
525 | { | |
526 | int rval; | |
527 | uint32_t cnt, timer; | |
528 | uint16_t risc_address; | |
529 | uint16_t mb0, mb2; | |
3d71644c | 530 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
1da177e4 LT |
531 | uint16_t __iomem *dmp_reg; |
532 | unsigned long flags; | |
533 | struct qla2100_fw_dump *fw; | |
534 | ||
535 | risc_address = 0; | |
536 | mb0 = mb2 = 0; | |
537 | flags = 0; | |
538 | ||
539 | if (!hardware_locked) | |
540 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
541 | ||
d4e3e04d | 542 | if (!ha->fw_dump) { |
1da177e4 | 543 | qla_printk(KERN_WARNING, ha, |
d4e3e04d | 544 | "No buffer available for dump!!!\n"); |
1da177e4 LT |
545 | goto qla2100_fw_dump_failed; |
546 | } | |
547 | ||
d4e3e04d | 548 | if (ha->fw_dumped) { |
1da177e4 | 549 | qla_printk(KERN_WARNING, ha, |
d4e3e04d AV |
550 | "Firmware has been previously dumped (%p) -- ignoring " |
551 | "request...\n", ha->fw_dump); | |
1da177e4 LT |
552 | goto qla2100_fw_dump_failed; |
553 | } | |
a7a167bf AV |
554 | fw = &ha->fw_dump->isp.isp21; |
555 | qla2xxx_prep_dump(ha, ha->fw_dump); | |
1da177e4 LT |
556 | |
557 | rval = QLA_SUCCESS; | |
a7a167bf | 558 | fw->hccr = htons(RD_REG_WORD(®->hccr)); |
1da177e4 LT |
559 | |
560 | /* Pause RISC. */ | |
fa2a1ce5 | 561 | WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); |
1da177e4 LT |
562 | for (cnt = 30000; (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && |
563 | rval == QLA_SUCCESS; cnt--) { | |
564 | if (cnt) | |
565 | udelay(100); | |
566 | else | |
567 | rval = QLA_FUNCTION_TIMEOUT; | |
568 | } | |
569 | if (rval == QLA_SUCCESS) { | |
570 | dmp_reg = (uint16_t __iomem *)(reg + 0); | |
fa2a1ce5 | 571 | for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++) |
a7a167bf | 572 | fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 LT |
573 | |
574 | dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x10); | |
575 | for (cnt = 0; cnt < ha->mbx_count; cnt++) { | |
576 | if (cnt == 8) { | |
a7a167bf AV |
577 | dmp_reg = (uint16_t __iomem *) |
578 | ((uint8_t __iomem *)reg + 0xe0); | |
1da177e4 | 579 | } |
a7a167bf | 580 | fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 LT |
581 | } |
582 | ||
583 | dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x20); | |
fa2a1ce5 | 584 | for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++) |
a7a167bf | 585 | fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 LT |
586 | |
587 | WRT_REG_WORD(®->ctrl_status, 0x00); | |
588 | dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0xA0); | |
fa2a1ce5 | 589 | for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++) |
a7a167bf | 590 | fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 | 591 | |
fa2a1ce5 | 592 | WRT_REG_WORD(®->pcr, 0x2000); |
1da177e4 | 593 | dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); |
fa2a1ce5 | 594 | for (cnt = 0; cnt < sizeof(fw->risc_gp0_reg) / 2; cnt++) |
a7a167bf | 595 | fw->risc_gp0_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 | 596 | |
fa2a1ce5 | 597 | WRT_REG_WORD(®->pcr, 0x2100); |
1da177e4 | 598 | dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); |
fa2a1ce5 | 599 | for (cnt = 0; cnt < sizeof(fw->risc_gp1_reg) / 2; cnt++) |
a7a167bf | 600 | fw->risc_gp1_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 | 601 | |
fa2a1ce5 | 602 | WRT_REG_WORD(®->pcr, 0x2200); |
1da177e4 | 603 | dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); |
fa2a1ce5 | 604 | for (cnt = 0; cnt < sizeof(fw->risc_gp2_reg) / 2; cnt++) |
a7a167bf | 605 | fw->risc_gp2_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 | 606 | |
fa2a1ce5 | 607 | WRT_REG_WORD(®->pcr, 0x2300); |
1da177e4 | 608 | dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); |
fa2a1ce5 | 609 | for (cnt = 0; cnt < sizeof(fw->risc_gp3_reg) / 2; cnt++) |
a7a167bf | 610 | fw->risc_gp3_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 | 611 | |
fa2a1ce5 | 612 | WRT_REG_WORD(®->pcr, 0x2400); |
1da177e4 | 613 | dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); |
fa2a1ce5 | 614 | for (cnt = 0; cnt < sizeof(fw->risc_gp4_reg) / 2; cnt++) |
a7a167bf | 615 | fw->risc_gp4_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 | 616 | |
fa2a1ce5 | 617 | WRT_REG_WORD(®->pcr, 0x2500); |
1da177e4 | 618 | dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); |
fa2a1ce5 | 619 | for (cnt = 0; cnt < sizeof(fw->risc_gp5_reg) / 2; cnt++) |
a7a167bf | 620 | fw->risc_gp5_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 | 621 | |
fa2a1ce5 | 622 | WRT_REG_WORD(®->pcr, 0x2600); |
1da177e4 | 623 | dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); |
fa2a1ce5 | 624 | for (cnt = 0; cnt < sizeof(fw->risc_gp6_reg) / 2; cnt++) |
a7a167bf | 625 | fw->risc_gp6_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 | 626 | |
fa2a1ce5 | 627 | WRT_REG_WORD(®->pcr, 0x2700); |
1da177e4 | 628 | dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); |
fa2a1ce5 | 629 | for (cnt = 0; cnt < sizeof(fw->risc_gp7_reg) / 2; cnt++) |
a7a167bf | 630 | fw->risc_gp7_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 | 631 | |
fa2a1ce5 | 632 | WRT_REG_WORD(®->ctrl_status, 0x10); |
1da177e4 | 633 | dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); |
fa2a1ce5 | 634 | for (cnt = 0; cnt < sizeof(fw->frame_buf_hdw_reg) / 2; cnt++) |
a7a167bf AV |
635 | fw->frame_buf_hdw_reg[cnt] = |
636 | htons(RD_REG_WORD(dmp_reg++)); | |
1da177e4 | 637 | |
fa2a1ce5 | 638 | WRT_REG_WORD(®->ctrl_status, 0x20); |
1da177e4 | 639 | dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); |
fa2a1ce5 | 640 | for (cnt = 0; cnt < sizeof(fw->fpm_b0_reg) / 2; cnt++) |
a7a167bf | 641 | fw->fpm_b0_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 | 642 | |
fa2a1ce5 | 643 | WRT_REG_WORD(®->ctrl_status, 0x30); |
1da177e4 | 644 | dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); |
fa2a1ce5 | 645 | for (cnt = 0; cnt < sizeof(fw->fpm_b1_reg) / 2; cnt++) |
a7a167bf | 646 | fw->fpm_b1_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 LT |
647 | |
648 | /* Reset the ISP. */ | |
649 | WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); | |
650 | } | |
651 | ||
652 | for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 && | |
653 | rval == QLA_SUCCESS; cnt--) { | |
654 | if (cnt) | |
655 | udelay(100); | |
656 | else | |
657 | rval = QLA_FUNCTION_TIMEOUT; | |
658 | } | |
659 | ||
660 | /* Pause RISC. */ | |
661 | if (rval == QLA_SUCCESS && (IS_QLA2200(ha) || (IS_QLA2100(ha) && | |
662 | (RD_REG_WORD(®->mctr) & (BIT_1 | BIT_0)) != 0))) { | |
663 | ||
fa2a1ce5 | 664 | WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); |
1da177e4 LT |
665 | for (cnt = 30000; |
666 | (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && | |
667 | rval == QLA_SUCCESS; cnt--) { | |
668 | if (cnt) | |
669 | udelay(100); | |
670 | else | |
671 | rval = QLA_FUNCTION_TIMEOUT; | |
672 | } | |
673 | if (rval == QLA_SUCCESS) { | |
674 | /* Set memory configuration and timing. */ | |
675 | if (IS_QLA2100(ha)) | |
676 | WRT_REG_WORD(®->mctr, 0xf1); | |
677 | else | |
678 | WRT_REG_WORD(®->mctr, 0xf2); | |
679 | RD_REG_WORD(®->mctr); /* PCI Posting. */ | |
680 | ||
681 | /* Release RISC. */ | |
682 | WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); | |
683 | } | |
684 | } | |
685 | ||
686 | if (rval == QLA_SUCCESS) { | |
687 | /* Get RISC SRAM. */ | |
688 | risc_address = 0x1000; | |
689 | WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD); | |
690 | clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); | |
691 | } | |
692 | for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS; | |
693 | cnt++, risc_address++) { | |
694 | WRT_MAILBOX_REG(ha, reg, 1, risc_address); | |
695 | WRT_REG_WORD(®->hccr, HCCR_SET_HOST_INT); | |
696 | ||
697 | for (timer = 6000000; timer != 0; timer--) { | |
698 | /* Check for pending interrupts. */ | |
699 | if (RD_REG_WORD(®->istatus) & ISR_RISC_INT) { | |
700 | if (RD_REG_WORD(®->semaphore) & BIT_0) { | |
701 | set_bit(MBX_INTERRUPT, | |
702 | &ha->mbx_cmd_flags); | |
703 | ||
704 | mb0 = RD_MAILBOX_REG(ha, reg, 0); | |
705 | mb2 = RD_MAILBOX_REG(ha, reg, 2); | |
706 | ||
707 | WRT_REG_WORD(®->semaphore, 0); | |
708 | WRT_REG_WORD(®->hccr, | |
709 | HCCR_CLR_RISC_INT); | |
710 | RD_REG_WORD(®->hccr); | |
711 | break; | |
712 | } | |
713 | WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); | |
714 | RD_REG_WORD(®->hccr); | |
715 | } | |
716 | udelay(5); | |
717 | } | |
718 | ||
719 | if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { | |
720 | rval = mb0 & MBS_MASK; | |
a7a167bf | 721 | fw->risc_ram[cnt] = htons(mb2); |
1da177e4 LT |
722 | } else { |
723 | rval = QLA_FUNCTION_FAILED; | |
724 | } | |
725 | } | |
726 | ||
a7a167bf AV |
727 | if (rval == QLA_SUCCESS) |
728 | qla2xxx_copy_queues(ha, &fw->risc_ram[cnt]); | |
729 | ||
1da177e4 LT |
730 | if (rval != QLA_SUCCESS) { |
731 | qla_printk(KERN_WARNING, ha, | |
732 | "Failed to dump firmware (%x)!!!\n", rval); | |
d4e3e04d | 733 | ha->fw_dumped = 0; |
1da177e4 | 734 | |
1da177e4 LT |
735 | } else { |
736 | qla_printk(KERN_INFO, ha, | |
737 | "Firmware dump saved to temp buffer (%ld/%p).\n", | |
738 | ha->host_no, ha->fw_dump); | |
d4e3e04d | 739 | ha->fw_dumped = 1; |
1da177e4 LT |
740 | } |
741 | ||
742 | qla2100_fw_dump_failed: | |
743 | if (!hardware_locked) | |
744 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
745 | } | |
746 | ||
6d9b61ed AV |
747 | void |
748 | qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked) | |
749 | { | |
750 | int rval; | |
c3a2f0df | 751 | uint32_t cnt; |
6d9b61ed | 752 | uint32_t risc_address; |
c3a2f0df | 753 | uint16_t mb0, wd; |
6d9b61ed | 754 | |
6d9b61ed AV |
755 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
756 | uint32_t __iomem *dmp_reg; | |
757 | uint32_t *iter_reg; | |
758 | uint16_t __iomem *mbx_reg; | |
759 | unsigned long flags; | |
760 | struct qla24xx_fw_dump *fw; | |
761 | uint32_t ext_mem_cnt; | |
c3a2f0df | 762 | void *nxt; |
6d9b61ed AV |
763 | |
764 | risc_address = ext_mem_cnt = 0; | |
6d9b61ed AV |
765 | flags = 0; |
766 | ||
767 | if (!hardware_locked) | |
768 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
769 | ||
d4e3e04d | 770 | if (!ha->fw_dump) { |
6d9b61ed AV |
771 | qla_printk(KERN_WARNING, ha, |
772 | "No buffer available for dump!!!\n"); | |
773 | goto qla24xx_fw_dump_failed; | |
774 | } | |
775 | ||
776 | if (ha->fw_dumped) { | |
777 | qla_printk(KERN_WARNING, ha, | |
778 | "Firmware has been previously dumped (%p) -- ignoring " | |
d4e3e04d | 779 | "request...\n", ha->fw_dump); |
6d9b61ed AV |
780 | goto qla24xx_fw_dump_failed; |
781 | } | |
a7a167bf AV |
782 | fw = &ha->fw_dump->isp.isp24; |
783 | qla2xxx_prep_dump(ha, ha->fw_dump); | |
6d9b61ed AV |
784 | |
785 | rval = QLA_SUCCESS; | |
a7a167bf | 786 | fw->host_status = htonl(RD_REG_DWORD(®->host_status)); |
6d9b61ed AV |
787 | |
788 | /* Pause RISC. */ | |
210d5350 | 789 | if ((RD_REG_DWORD(®->hccr) & HCCRX_RISC_PAUSE) == 0) { |
6d9b61ed AV |
790 | WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_RESET | |
791 | HCCRX_CLR_HOST_INT); | |
792 | RD_REG_DWORD(®->hccr); /* PCI Posting. */ | |
793 | WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_PAUSE); | |
794 | for (cnt = 30000; | |
795 | (RD_REG_DWORD(®->hccr) & HCCRX_RISC_PAUSE) == 0 && | |
796 | rval == QLA_SUCCESS; cnt--) { | |
797 | if (cnt) | |
798 | udelay(100); | |
799 | else | |
800 | rval = QLA_FUNCTION_TIMEOUT; | |
801 | } | |
802 | } | |
803 | ||
6d9b61ed AV |
804 | if (rval == QLA_SUCCESS) { |
805 | /* Host interface registers. */ | |
806 | dmp_reg = (uint32_t __iomem *)(reg + 0); | |
807 | for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) | |
a7a167bf | 808 | fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed | 809 | |
210d5350 AV |
810 | /* Disable interrupts. */ |
811 | WRT_REG_DWORD(®->ictrl, 0); | |
812 | RD_REG_DWORD(®->ictrl); | |
813 | ||
814 | /* Shadow registers. */ | |
815 | WRT_REG_DWORD(®->iobase_addr, 0x0F70); | |
816 | RD_REG_DWORD(®->iobase_addr); | |
c3a2f0df AV |
817 | WRT_REG_DWORD(®->iobase_select, 0xB0000000); |
818 | fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
819 | ||
820 | WRT_REG_DWORD(®->iobase_select, 0xB0100000); | |
821 | fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
822 | ||
823 | WRT_REG_DWORD(®->iobase_select, 0xB0200000); | |
824 | fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
825 | ||
826 | WRT_REG_DWORD(®->iobase_select, 0xB0300000); | |
827 | fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
828 | ||
829 | WRT_REG_DWORD(®->iobase_select, 0xB0400000); | |
830 | fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
831 | ||
832 | WRT_REG_DWORD(®->iobase_select, 0xB0500000); | |
833 | fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
834 | ||
835 | WRT_REG_DWORD(®->iobase_select, 0xB0600000); | |
836 | fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
210d5350 | 837 | |
6d9b61ed | 838 | /* Mailbox registers. */ |
c3a2f0df | 839 | mbx_reg = ®->mailbox0; |
6d9b61ed | 840 | for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) |
a7a167bf | 841 | fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); |
6d9b61ed AV |
842 | |
843 | /* Transfer sequence registers. */ | |
844 | iter_reg = fw->xseq_gp_reg; | |
845 | WRT_REG_DWORD(®->iobase_addr, 0xBF00); | |
c3a2f0df | 846 | dmp_reg = ®->iobase_window; |
6d9b61ed | 847 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 848 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
849 | |
850 | WRT_REG_DWORD(®->iobase_addr, 0xBF10); | |
c3a2f0df | 851 | dmp_reg = ®->iobase_window; |
6d9b61ed | 852 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 853 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
854 | |
855 | WRT_REG_DWORD(®->iobase_addr, 0xBF20); | |
c3a2f0df | 856 | dmp_reg = ®->iobase_window; |
6d9b61ed | 857 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 858 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
859 | |
860 | WRT_REG_DWORD(®->iobase_addr, 0xBF30); | |
c3a2f0df | 861 | dmp_reg = ®->iobase_window; |
6d9b61ed | 862 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 863 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
864 | |
865 | WRT_REG_DWORD(®->iobase_addr, 0xBF40); | |
c3a2f0df | 866 | dmp_reg = ®->iobase_window; |
6d9b61ed | 867 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 868 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
869 | |
870 | WRT_REG_DWORD(®->iobase_addr, 0xBF50); | |
c3a2f0df | 871 | dmp_reg = ®->iobase_window; |
6d9b61ed | 872 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 873 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
874 | |
875 | WRT_REG_DWORD(®->iobase_addr, 0xBF60); | |
c3a2f0df | 876 | dmp_reg = ®->iobase_window; |
6d9b61ed | 877 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 878 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
879 | |
880 | WRT_REG_DWORD(®->iobase_addr, 0xBF70); | |
c3a2f0df | 881 | dmp_reg = ®->iobase_window; |
6d9b61ed | 882 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 883 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
884 | |
885 | WRT_REG_DWORD(®->iobase_addr, 0xBFE0); | |
c3a2f0df | 886 | dmp_reg = ®->iobase_window; |
6d9b61ed | 887 | for (cnt = 0; cnt < sizeof(fw->xseq_0_reg) / 4; cnt++) |
a7a167bf | 888 | fw->xseq_0_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
889 | |
890 | WRT_REG_DWORD(®->iobase_addr, 0xBFF0); | |
c3a2f0df | 891 | dmp_reg = ®->iobase_window; |
6d9b61ed | 892 | for (cnt = 0; cnt < sizeof(fw->xseq_1_reg) / 4; cnt++) |
a7a167bf | 893 | fw->xseq_1_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
894 | |
895 | /* Receive sequence registers. */ | |
896 | iter_reg = fw->rseq_gp_reg; | |
897 | WRT_REG_DWORD(®->iobase_addr, 0xFF00); | |
c3a2f0df | 898 | dmp_reg = ®->iobase_window; |
6d9b61ed | 899 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 900 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
901 | |
902 | WRT_REG_DWORD(®->iobase_addr, 0xFF10); | |
c3a2f0df | 903 | dmp_reg = ®->iobase_window; |
6d9b61ed | 904 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 905 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
906 | |
907 | WRT_REG_DWORD(®->iobase_addr, 0xFF20); | |
c3a2f0df | 908 | dmp_reg = ®->iobase_window; |
6d9b61ed | 909 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 910 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
911 | |
912 | WRT_REG_DWORD(®->iobase_addr, 0xFF30); | |
c3a2f0df | 913 | dmp_reg = ®->iobase_window; |
6d9b61ed | 914 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 915 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
916 | |
917 | WRT_REG_DWORD(®->iobase_addr, 0xFF40); | |
c3a2f0df | 918 | dmp_reg = ®->iobase_window; |
6d9b61ed | 919 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 920 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
921 | |
922 | WRT_REG_DWORD(®->iobase_addr, 0xFF50); | |
c3a2f0df | 923 | dmp_reg = ®->iobase_window; |
6d9b61ed | 924 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 925 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
926 | |
927 | WRT_REG_DWORD(®->iobase_addr, 0xFF60); | |
c3a2f0df | 928 | dmp_reg = ®->iobase_window; |
6d9b61ed | 929 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 930 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
931 | |
932 | WRT_REG_DWORD(®->iobase_addr, 0xFF70); | |
c3a2f0df | 933 | dmp_reg = ®->iobase_window; |
6d9b61ed | 934 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 935 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
936 | |
937 | WRT_REG_DWORD(®->iobase_addr, 0xFFD0); | |
c3a2f0df | 938 | dmp_reg = ®->iobase_window; |
6d9b61ed | 939 | for (cnt = 0; cnt < sizeof(fw->rseq_0_reg) / 4; cnt++) |
a7a167bf | 940 | fw->rseq_0_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
941 | |
942 | WRT_REG_DWORD(®->iobase_addr, 0xFFE0); | |
c3a2f0df | 943 | dmp_reg = ®->iobase_window; |
6d9b61ed | 944 | for (cnt = 0; cnt < sizeof(fw->rseq_1_reg) / 4; cnt++) |
a7a167bf | 945 | fw->rseq_1_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
946 | |
947 | WRT_REG_DWORD(®->iobase_addr, 0xFFF0); | |
c3a2f0df | 948 | dmp_reg = ®->iobase_window; |
6d9b61ed | 949 | for (cnt = 0; cnt < sizeof(fw->rseq_2_reg) / 4; cnt++) |
a7a167bf | 950 | fw->rseq_2_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
951 | |
952 | /* Command DMA registers. */ | |
953 | WRT_REG_DWORD(®->iobase_addr, 0x7100); | |
c3a2f0df | 954 | dmp_reg = ®->iobase_window; |
6d9b61ed | 955 | for (cnt = 0; cnt < sizeof(fw->cmd_dma_reg) / 4; cnt++) |
a7a167bf | 956 | fw->cmd_dma_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
957 | |
958 | /* Queues. */ | |
959 | iter_reg = fw->req0_dma_reg; | |
960 | WRT_REG_DWORD(®->iobase_addr, 0x7200); | |
c3a2f0df | 961 | dmp_reg = ®->iobase_window; |
6d9b61ed | 962 | for (cnt = 0; cnt < 8; cnt++) |
a7a167bf | 963 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed | 964 | |
c3a2f0df | 965 | dmp_reg = ®->iobase_q; |
6d9b61ed | 966 | for (cnt = 0; cnt < 7; cnt++) |
a7a167bf | 967 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
968 | |
969 | iter_reg = fw->resp0_dma_reg; | |
970 | WRT_REG_DWORD(®->iobase_addr, 0x7300); | |
c3a2f0df | 971 | dmp_reg = ®->iobase_window; |
6d9b61ed | 972 | for (cnt = 0; cnt < 8; cnt++) |
a7a167bf | 973 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed | 974 | |
c3a2f0df | 975 | dmp_reg = ®->iobase_q; |
6d9b61ed | 976 | for (cnt = 0; cnt < 7; cnt++) |
a7a167bf | 977 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
978 | |
979 | iter_reg = fw->req1_dma_reg; | |
980 | WRT_REG_DWORD(®->iobase_addr, 0x7400); | |
c3a2f0df | 981 | dmp_reg = ®->iobase_window; |
6d9b61ed | 982 | for (cnt = 0; cnt < 8; cnt++) |
a7a167bf | 983 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed | 984 | |
c3a2f0df | 985 | dmp_reg = ®->iobase_q; |
6d9b61ed | 986 | for (cnt = 0; cnt < 7; cnt++) |
a7a167bf | 987 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
988 | |
989 | /* Transmit DMA registers. */ | |
990 | iter_reg = fw->xmt0_dma_reg; | |
991 | WRT_REG_DWORD(®->iobase_addr, 0x7600); | |
c3a2f0df | 992 | dmp_reg = ®->iobase_window; |
6d9b61ed | 993 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 994 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
995 | |
996 | WRT_REG_DWORD(®->iobase_addr, 0x7610); | |
c3a2f0df | 997 | dmp_reg = ®->iobase_window; |
6d9b61ed | 998 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 999 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
1000 | |
1001 | iter_reg = fw->xmt1_dma_reg; | |
1002 | WRT_REG_DWORD(®->iobase_addr, 0x7620); | |
c3a2f0df | 1003 | dmp_reg = ®->iobase_window; |
6d9b61ed | 1004 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 1005 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
1006 | |
1007 | WRT_REG_DWORD(®->iobase_addr, 0x7630); | |
c3a2f0df | 1008 | dmp_reg = ®->iobase_window; |
6d9b61ed | 1009 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 1010 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
1011 | |
1012 | iter_reg = fw->xmt2_dma_reg; | |
1013 | WRT_REG_DWORD(®->iobase_addr, 0x7640); | |
c3a2f0df | 1014 | dmp_reg = ®->iobase_window; |
6d9b61ed | 1015 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 1016 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
1017 | |
1018 | WRT_REG_DWORD(®->iobase_addr, 0x7650); | |
c3a2f0df | 1019 | dmp_reg = ®->iobase_window; |
6d9b61ed | 1020 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 1021 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
1022 | |
1023 | iter_reg = fw->xmt3_dma_reg; | |
1024 | WRT_REG_DWORD(®->iobase_addr, 0x7660); | |
c3a2f0df | 1025 | dmp_reg = ®->iobase_window; |
6d9b61ed | 1026 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 1027 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
1028 | |
1029 | WRT_REG_DWORD(®->iobase_addr, 0x7670); | |
c3a2f0df | 1030 | dmp_reg = ®->iobase_window; |
6d9b61ed | 1031 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 1032 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
1033 | |
1034 | iter_reg = fw->xmt4_dma_reg; | |
1035 | WRT_REG_DWORD(®->iobase_addr, 0x7680); | |
c3a2f0df | 1036 | dmp_reg = ®->iobase_window; |
6d9b61ed | 1037 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 1038 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
1039 | |
1040 | WRT_REG_DWORD(®->iobase_addr, 0x7690); | |
c3a2f0df | 1041 | dmp_reg = ®->iobase_window; |
6d9b61ed | 1042 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 1043 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
1044 | |
1045 | WRT_REG_DWORD(®->iobase_addr, 0x76A0); | |
c3a2f0df | 1046 | dmp_reg = ®->iobase_window; |
6d9b61ed | 1047 | for (cnt = 0; cnt < sizeof(fw->xmt_data_dma_reg) / 4; cnt++) |
a7a167bf AV |
1048 | fw->xmt_data_dma_reg[cnt] = |
1049 | htonl(RD_REG_DWORD(dmp_reg++)); | |
6d9b61ed AV |
1050 | |
1051 | /* Receive DMA registers. */ | |
1052 | iter_reg = fw->rcvt0_data_dma_reg; | |
1053 | WRT_REG_DWORD(®->iobase_addr, 0x7700); | |
c3a2f0df | 1054 | dmp_reg = ®->iobase_window; |
6d9b61ed | 1055 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 1056 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
1057 | |
1058 | WRT_REG_DWORD(®->iobase_addr, 0x7710); | |
c3a2f0df | 1059 | dmp_reg = ®->iobase_window; |
6d9b61ed | 1060 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 1061 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
1062 | |
1063 | iter_reg = fw->rcvt1_data_dma_reg; | |
1064 | WRT_REG_DWORD(®->iobase_addr, 0x7720); | |
c3a2f0df | 1065 | dmp_reg = ®->iobase_window; |
6d9b61ed | 1066 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 1067 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
1068 | |
1069 | WRT_REG_DWORD(®->iobase_addr, 0x7730); | |
c3a2f0df | 1070 | dmp_reg = ®->iobase_window; |
6d9b61ed | 1071 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 1072 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
1073 | |
1074 | /* RISC registers. */ | |
1075 | iter_reg = fw->risc_gp_reg; | |
1076 | WRT_REG_DWORD(®->iobase_addr, 0x0F00); | |
c3a2f0df | 1077 | dmp_reg = ®->iobase_window; |
6d9b61ed | 1078 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 1079 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
1080 | |
1081 | WRT_REG_DWORD(®->iobase_addr, 0x0F10); | |
c3a2f0df | 1082 | dmp_reg = ®->iobase_window; |
6d9b61ed | 1083 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 1084 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
1085 | |
1086 | WRT_REG_DWORD(®->iobase_addr, 0x0F20); | |
c3a2f0df | 1087 | dmp_reg = ®->iobase_window; |
6d9b61ed | 1088 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 1089 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
1090 | |
1091 | WRT_REG_DWORD(®->iobase_addr, 0x0F30); | |
c3a2f0df | 1092 | dmp_reg = ®->iobase_window; |
6d9b61ed | 1093 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 1094 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
1095 | |
1096 | WRT_REG_DWORD(®->iobase_addr, 0x0F40); | |
c3a2f0df | 1097 | dmp_reg = ®->iobase_window; |
6d9b61ed | 1098 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 1099 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
1100 | |
1101 | WRT_REG_DWORD(®->iobase_addr, 0x0F50); | |
c3a2f0df | 1102 | dmp_reg = ®->iobase_window; |
6d9b61ed | 1103 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 1104 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
1105 | |
1106 | WRT_REG_DWORD(®->iobase_addr, 0x0F60); | |
c3a2f0df | 1107 | dmp_reg = ®->iobase_window; |
6d9b61ed | 1108 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 1109 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
1110 | |
1111 | WRT_REG_DWORD(®->iobase_addr, 0x0F70); | |
c3a2f0df | 1112 | dmp_reg = ®->iobase_window; |
6d9b61ed | 1113 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 1114 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed | 1115 | |
6d9b61ed AV |
1116 | /* Local memory controller registers. */ |
1117 | iter_reg = fw->lmc_reg; | |
1118 | WRT_REG_DWORD(®->iobase_addr, 0x3000); | |
c3a2f0df | 1119 | dmp_reg = ®->iobase_window; |
6d9b61ed | 1120 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 1121 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
1122 | |
1123 | WRT_REG_DWORD(®->iobase_addr, 0x3010); | |
c3a2f0df | 1124 | dmp_reg = ®->iobase_window; |
6d9b61ed | 1125 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 1126 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
1127 | |
1128 | WRT_REG_DWORD(®->iobase_addr, 0x3020); | |
c3a2f0df | 1129 | dmp_reg = ®->iobase_window; |
6d9b61ed | 1130 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 1131 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
1132 | |
1133 | WRT_REG_DWORD(®->iobase_addr, 0x3030); | |
c3a2f0df | 1134 | dmp_reg = ®->iobase_window; |
6d9b61ed | 1135 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 1136 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
1137 | |
1138 | WRT_REG_DWORD(®->iobase_addr, 0x3040); | |
c3a2f0df | 1139 | dmp_reg = ®->iobase_window; |
6d9b61ed | 1140 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 1141 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
1142 | |
1143 | WRT_REG_DWORD(®->iobase_addr, 0x3050); | |
c3a2f0df | 1144 | dmp_reg = ®->iobase_window; |
6d9b61ed | 1145 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 1146 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
1147 | |
1148 | WRT_REG_DWORD(®->iobase_addr, 0x3060); | |
c3a2f0df | 1149 | dmp_reg = ®->iobase_window; |
6d9b61ed | 1150 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 1151 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
1152 | |
1153 | /* Fibre Protocol Module registers. */ | |
1154 | iter_reg = fw->fpm_hdw_reg; | |
1155 | WRT_REG_DWORD(®->iobase_addr, 0x4000); | |
c3a2f0df | 1156 | dmp_reg = ®->iobase_window; |
6d9b61ed | 1157 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 1158 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
1159 | |
1160 | WRT_REG_DWORD(®->iobase_addr, 0x4010); | |
c3a2f0df | 1161 | dmp_reg = ®->iobase_window; |
6d9b61ed | 1162 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 1163 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
1164 | |
1165 | WRT_REG_DWORD(®->iobase_addr, 0x4020); | |
c3a2f0df | 1166 | dmp_reg = ®->iobase_window; |
6d9b61ed | 1167 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 1168 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
1169 | |
1170 | WRT_REG_DWORD(®->iobase_addr, 0x4030); | |
c3a2f0df | 1171 | dmp_reg = ®->iobase_window; |
6d9b61ed | 1172 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 1173 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
1174 | |
1175 | WRT_REG_DWORD(®->iobase_addr, 0x4040); | |
c3a2f0df | 1176 | dmp_reg = ®->iobase_window; |
6d9b61ed | 1177 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 1178 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
1179 | |
1180 | WRT_REG_DWORD(®->iobase_addr, 0x4050); | |
c3a2f0df | 1181 | dmp_reg = ®->iobase_window; |
6d9b61ed | 1182 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 1183 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
1184 | |
1185 | WRT_REG_DWORD(®->iobase_addr, 0x4060); | |
c3a2f0df | 1186 | dmp_reg = ®->iobase_window; |
6d9b61ed | 1187 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 1188 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
1189 | |
1190 | WRT_REG_DWORD(®->iobase_addr, 0x4070); | |
c3a2f0df | 1191 | dmp_reg = ®->iobase_window; |
6d9b61ed | 1192 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 1193 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
1194 | |
1195 | WRT_REG_DWORD(®->iobase_addr, 0x4080); | |
c3a2f0df | 1196 | dmp_reg = ®->iobase_window; |
6d9b61ed | 1197 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 1198 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
1199 | |
1200 | WRT_REG_DWORD(®->iobase_addr, 0x4090); | |
c3a2f0df | 1201 | dmp_reg = ®->iobase_window; |
6d9b61ed | 1202 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 1203 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
1204 | |
1205 | WRT_REG_DWORD(®->iobase_addr, 0x40A0); | |
c3a2f0df | 1206 | dmp_reg = ®->iobase_window; |
6d9b61ed | 1207 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 1208 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
1209 | |
1210 | WRT_REG_DWORD(®->iobase_addr, 0x40B0); | |
c3a2f0df | 1211 | dmp_reg = ®->iobase_window; |
6d9b61ed | 1212 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 1213 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
1214 | |
1215 | /* Frame Buffer registers. */ | |
1216 | iter_reg = fw->fb_hdw_reg; | |
1217 | WRT_REG_DWORD(®->iobase_addr, 0x6000); | |
c3a2f0df | 1218 | dmp_reg = ®->iobase_window; |
6d9b61ed | 1219 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 1220 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
1221 | |
1222 | WRT_REG_DWORD(®->iobase_addr, 0x6010); | |
c3a2f0df | 1223 | dmp_reg = ®->iobase_window; |
6d9b61ed | 1224 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 1225 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
1226 | |
1227 | WRT_REG_DWORD(®->iobase_addr, 0x6020); | |
c3a2f0df | 1228 | dmp_reg = ®->iobase_window; |
6d9b61ed | 1229 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 1230 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
1231 | |
1232 | WRT_REG_DWORD(®->iobase_addr, 0x6030); | |
c3a2f0df | 1233 | dmp_reg = ®->iobase_window; |
6d9b61ed | 1234 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 1235 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
1236 | |
1237 | WRT_REG_DWORD(®->iobase_addr, 0x6040); | |
c3a2f0df | 1238 | dmp_reg = ®->iobase_window; |
6d9b61ed | 1239 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 1240 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
1241 | |
1242 | WRT_REG_DWORD(®->iobase_addr, 0x6100); | |
c3a2f0df | 1243 | dmp_reg = ®->iobase_window; |
6d9b61ed | 1244 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 1245 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
1246 | |
1247 | WRT_REG_DWORD(®->iobase_addr, 0x6130); | |
c3a2f0df | 1248 | dmp_reg = ®->iobase_window; |
6d9b61ed | 1249 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 1250 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
1251 | |
1252 | WRT_REG_DWORD(®->iobase_addr, 0x6150); | |
c3a2f0df | 1253 | dmp_reg = ®->iobase_window; |
6d9b61ed | 1254 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 1255 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
1256 | |
1257 | WRT_REG_DWORD(®->iobase_addr, 0x6170); | |
c3a2f0df | 1258 | dmp_reg = ®->iobase_window; |
6d9b61ed | 1259 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 1260 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
1261 | |
1262 | WRT_REG_DWORD(®->iobase_addr, 0x6190); | |
c3a2f0df | 1263 | dmp_reg = ®->iobase_window; |
6d9b61ed | 1264 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 1265 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
1266 | |
1267 | WRT_REG_DWORD(®->iobase_addr, 0x61B0); | |
c3a2f0df | 1268 | dmp_reg = ®->iobase_window; |
6d9b61ed | 1269 | for (cnt = 0; cnt < 16; cnt++) |
a7a167bf | 1270 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); |
6d9b61ed AV |
1271 | |
1272 | /* Reset RISC. */ | |
1273 | WRT_REG_DWORD(®->ctrl_status, | |
1274 | CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); | |
1275 | for (cnt = 0; cnt < 30000; cnt++) { | |
1276 | if ((RD_REG_DWORD(®->ctrl_status) & | |
1277 | CSRX_DMA_ACTIVE) == 0) | |
1278 | break; | |
1279 | ||
1280 | udelay(10); | |
1281 | } | |
1282 | ||
1283 | WRT_REG_DWORD(®->ctrl_status, | |
1284 | CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); | |
335a1cc9 | 1285 | pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); |
88c26663 | 1286 | |
335a1cc9 | 1287 | udelay(100); |
88c26663 | 1288 | /* Wait for firmware to complete NVRAM accesses. */ |
c3a2f0df AV |
1289 | mb0 = (uint32_t) RD_REG_WORD(®->mailbox0); |
1290 | for (cnt = 10000 ; cnt && mb0; cnt--) { | |
88c26663 | 1291 | udelay(5); |
c3a2f0df | 1292 | mb0 = (uint32_t) RD_REG_WORD(®->mailbox0); |
88c26663 AV |
1293 | barrier(); |
1294 | } | |
1295 | ||
335a1cc9 | 1296 | /* Wait for soft-reset to complete. */ |
6d9b61ed AV |
1297 | for (cnt = 0; cnt < 30000; cnt++) { |
1298 | if ((RD_REG_DWORD(®->ctrl_status) & | |
1299 | CSRX_ISP_SOFT_RESET) == 0) | |
1300 | break; | |
1301 | ||
1302 | udelay(10); | |
1303 | } | |
1304 | WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET); | |
1305 | RD_REG_DWORD(®->hccr); /* PCI Posting. */ | |
1306 | } | |
1307 | ||
1308 | for (cnt = 30000; RD_REG_WORD(®->mailbox0) != 0 && | |
1309 | rval == QLA_SUCCESS; cnt--) { | |
1310 | if (cnt) | |
1311 | udelay(100); | |
1312 | else | |
1313 | rval = QLA_FUNCTION_TIMEOUT; | |
1314 | } | |
1315 | ||
c3a2f0df AV |
1316 | if (rval == QLA_SUCCESS) |
1317 | rval = qla2xxx_dump_memory(ha, fw->code_ram, | |
1318 | sizeof(fw->code_ram), fw->ext_mem, &nxt); | |
1319 | ||
6d9b61ed | 1320 | if (rval == QLA_SUCCESS) { |
c3a2f0df AV |
1321 | nxt = qla2xxx_copy_queues(ha, nxt); |
1322 | if (ha->eft) | |
1323 | memcpy(nxt, ha->eft, ntohl(ha->fw_dump->eft_size)); | |
6d9b61ed | 1324 | } |
6d9b61ed | 1325 | |
c3a2f0df AV |
1326 | if (rval != QLA_SUCCESS) { |
1327 | qla_printk(KERN_WARNING, ha, | |
1328 | "Failed to dump firmware (%x)!!!\n", rval); | |
1329 | ha->fw_dumped = 0; | |
6d9b61ed | 1330 | |
c3a2f0df AV |
1331 | } else { |
1332 | qla_printk(KERN_INFO, ha, | |
1333 | "Firmware dump saved to temp buffer (%ld/%p).\n", | |
1334 | ha->host_no, ha->fw_dump); | |
1335 | ha->fw_dumped = 1; | |
1336 | } | |
6d9b61ed | 1337 | |
c3a2f0df AV |
1338 | qla24xx_fw_dump_failed: |
1339 | if (!hardware_locked) | |
1340 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1341 | } | |
6d9b61ed | 1342 | |
c3a2f0df AV |
1343 | void |
1344 | qla25xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked) | |
1345 | { | |
1346 | int rval; | |
1347 | uint32_t cnt; | |
1348 | uint32_t risc_address; | |
1349 | uint16_t mb0, wd; | |
6d9b61ed | 1350 | |
c3a2f0df AV |
1351 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
1352 | uint32_t __iomem *dmp_reg; | |
1353 | uint32_t *iter_reg; | |
1354 | uint16_t __iomem *mbx_reg; | |
1355 | unsigned long flags; | |
1356 | struct qla25xx_fw_dump *fw; | |
1357 | uint32_t ext_mem_cnt; | |
1358 | void *nxt; | |
6d9b61ed | 1359 | |
c3a2f0df AV |
1360 | risc_address = ext_mem_cnt = 0; |
1361 | flags = 0; | |
6d9b61ed | 1362 | |
c3a2f0df AV |
1363 | if (!hardware_locked) |
1364 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
6d9b61ed | 1365 | |
c3a2f0df AV |
1366 | if (!ha->fw_dump) { |
1367 | qla_printk(KERN_WARNING, ha, | |
1368 | "No buffer available for dump!!!\n"); | |
1369 | goto qla25xx_fw_dump_failed; | |
1370 | } | |
6d9b61ed | 1371 | |
c3a2f0df AV |
1372 | if (ha->fw_dumped) { |
1373 | qla_printk(KERN_WARNING, ha, | |
1374 | "Firmware has been previously dumped (%p) -- ignoring " | |
1375 | "request...\n", ha->fw_dump); | |
1376 | goto qla25xx_fw_dump_failed; | |
1377 | } | |
1378 | fw = &ha->fw_dump->isp.isp25; | |
1379 | qla2xxx_prep_dump(ha, ha->fw_dump); | |
6d9b61ed | 1380 | |
c3a2f0df AV |
1381 | rval = QLA_SUCCESS; |
1382 | fw->host_status = htonl(RD_REG_DWORD(®->host_status)); | |
6d9b61ed | 1383 | |
c3a2f0df AV |
1384 | /* Pause RISC. */ |
1385 | if ((RD_REG_DWORD(®->hccr) & HCCRX_RISC_PAUSE) == 0) { | |
1386 | WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_RESET | | |
1387 | HCCRX_CLR_HOST_INT); | |
1388 | RD_REG_DWORD(®->hccr); /* PCI Posting. */ | |
1389 | WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_PAUSE); | |
1390 | for (cnt = 30000; | |
1391 | (RD_REG_DWORD(®->hccr) & HCCRX_RISC_PAUSE) == 0 && | |
1392 | rval == QLA_SUCCESS; cnt--) { | |
1393 | if (cnt) | |
1394 | udelay(100); | |
1395 | else | |
1396 | rval = QLA_FUNCTION_TIMEOUT; | |
6d9b61ed AV |
1397 | } |
1398 | } | |
1399 | ||
a7a167bf | 1400 | if (rval == QLA_SUCCESS) { |
c3a2f0df AV |
1401 | /* Host interface registers. */ |
1402 | dmp_reg = (uint32_t __iomem *)(reg + 0); | |
1403 | for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) | |
1404 | fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); | |
a7a167bf | 1405 | |
c3a2f0df AV |
1406 | /* Disable interrupts. */ |
1407 | WRT_REG_DWORD(®->ictrl, 0); | |
1408 | RD_REG_DWORD(®->ictrl); | |
1409 | ||
1410 | /* Shadow registers. */ | |
1411 | WRT_REG_DWORD(®->iobase_addr, 0x0F70); | |
1412 | RD_REG_DWORD(®->iobase_addr); | |
1413 | WRT_REG_DWORD(®->iobase_select, 0xB0000000); | |
1414 | fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1415 | ||
1416 | WRT_REG_DWORD(®->iobase_select, 0xB0100000); | |
1417 | fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1418 | ||
1419 | WRT_REG_DWORD(®->iobase_select, 0xB0200000); | |
1420 | fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1421 | ||
1422 | WRT_REG_DWORD(®->iobase_select, 0xB0300000); | |
1423 | fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1424 | ||
1425 | WRT_REG_DWORD(®->iobase_select, 0xB0400000); | |
1426 | fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1427 | ||
1428 | WRT_REG_DWORD(®->iobase_select, 0xB0500000); | |
1429 | fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1430 | ||
1431 | WRT_REG_DWORD(®->iobase_select, 0xB0600000); | |
1432 | fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1433 | ||
1434 | WRT_REG_DWORD(®->iobase_select, 0xB0700000); | |
1435 | fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1436 | ||
1437 | WRT_REG_DWORD(®->iobase_select, 0xB0800000); | |
1438 | fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1439 | ||
1440 | WRT_REG_DWORD(®->iobase_select, 0xB0900000); | |
1441 | fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1442 | ||
1443 | WRT_REG_DWORD(®->iobase_select, 0xB0A00000); | |
1444 | fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1445 | ||
1446 | /* RISC I/O register. */ | |
1447 | WRT_REG_DWORD(®->iobase_addr, 0x0010); | |
1448 | RD_REG_DWORD(®->iobase_addr); | |
1449 | fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window)); | |
1450 | ||
1451 | /* Mailbox registers. */ | |
1452 | mbx_reg = ®->mailbox0; | |
1453 | for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) | |
1454 | fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); | |
1455 | ||
1456 | /* Transfer sequence registers. */ | |
1457 | iter_reg = fw->xseq_gp_reg; | |
1458 | WRT_REG_DWORD(®->iobase_addr, 0xBF00); | |
1459 | dmp_reg = ®->iobase_window; | |
1460 | for (cnt = 0; cnt < 16; cnt++) | |
1461 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1462 | ||
1463 | WRT_REG_DWORD(®->iobase_addr, 0xBF10); | |
1464 | dmp_reg = ®->iobase_window; | |
1465 | for (cnt = 0; cnt < 16; cnt++) | |
1466 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1467 | ||
1468 | WRT_REG_DWORD(®->iobase_addr, 0xBF20); | |
1469 | dmp_reg = ®->iobase_window; | |
1470 | for (cnt = 0; cnt < 16; cnt++) | |
1471 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1472 | ||
1473 | WRT_REG_DWORD(®->iobase_addr, 0xBF30); | |
1474 | dmp_reg = ®->iobase_window; | |
1475 | for (cnt = 0; cnt < 16; cnt++) | |
1476 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1477 | ||
1478 | WRT_REG_DWORD(®->iobase_addr, 0xBF40); | |
1479 | dmp_reg = ®->iobase_window; | |
1480 | for (cnt = 0; cnt < 16; cnt++) | |
1481 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1482 | ||
1483 | WRT_REG_DWORD(®->iobase_addr, 0xBF50); | |
1484 | dmp_reg = ®->iobase_window; | |
1485 | for (cnt = 0; cnt < 16; cnt++) | |
1486 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1487 | ||
1488 | WRT_REG_DWORD(®->iobase_addr, 0xBF60); | |
1489 | dmp_reg = ®->iobase_window; | |
1490 | for (cnt = 0; cnt < 16; cnt++) | |
1491 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1492 | ||
1493 | WRT_REG_DWORD(®->iobase_addr, 0xBF70); | |
1494 | dmp_reg = ®->iobase_window; | |
1495 | for (cnt = 0; cnt < 16; cnt++) | |
1496 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1497 | ||
1498 | iter_reg = fw->xseq_0_reg; | |
1499 | WRT_REG_DWORD(®->iobase_addr, 0xBFC0); | |
1500 | dmp_reg = ®->iobase_window; | |
1501 | for (cnt = 0; cnt < 16; cnt++) | |
1502 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1503 | ||
1504 | WRT_REG_DWORD(®->iobase_addr, 0xBFD0); | |
1505 | dmp_reg = ®->iobase_window; | |
1506 | for (cnt = 0; cnt < 16; cnt++) | |
1507 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1508 | ||
1509 | WRT_REG_DWORD(®->iobase_addr, 0xBFE0); | |
1510 | dmp_reg = ®->iobase_window; | |
1511 | for (cnt = 0; cnt < 16; cnt++) | |
1512 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1513 | ||
1514 | WRT_REG_DWORD(®->iobase_addr, 0xBFF0); | |
1515 | dmp_reg = ®->iobase_window; | |
1516 | for (cnt = 0; cnt < sizeof(fw->xseq_1_reg) / 4; cnt++) | |
1517 | fw->xseq_1_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); | |
1518 | ||
1519 | /* Receive sequence registers. */ | |
1520 | iter_reg = fw->rseq_gp_reg; | |
1521 | WRT_REG_DWORD(®->iobase_addr, 0xFF00); | |
1522 | dmp_reg = ®->iobase_window; | |
1523 | for (cnt = 0; cnt < 16; cnt++) | |
1524 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1525 | ||
1526 | WRT_REG_DWORD(®->iobase_addr, 0xFF10); | |
1527 | dmp_reg = ®->iobase_window; | |
1528 | for (cnt = 0; cnt < 16; cnt++) | |
1529 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1530 | ||
1531 | WRT_REG_DWORD(®->iobase_addr, 0xFF20); | |
1532 | dmp_reg = ®->iobase_window; | |
1533 | for (cnt = 0; cnt < 16; cnt++) | |
1534 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1535 | ||
1536 | WRT_REG_DWORD(®->iobase_addr, 0xFF30); | |
1537 | dmp_reg = ®->iobase_window; | |
1538 | for (cnt = 0; cnt < 16; cnt++) | |
1539 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1540 | ||
1541 | WRT_REG_DWORD(®->iobase_addr, 0xFF40); | |
1542 | dmp_reg = ®->iobase_window; | |
1543 | for (cnt = 0; cnt < 16; cnt++) | |
1544 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1545 | ||
1546 | WRT_REG_DWORD(®->iobase_addr, 0xFF50); | |
1547 | dmp_reg = ®->iobase_window; | |
1548 | for (cnt = 0; cnt < 16; cnt++) | |
1549 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1550 | ||
1551 | WRT_REG_DWORD(®->iobase_addr, 0xFF60); | |
1552 | dmp_reg = ®->iobase_window; | |
1553 | for (cnt = 0; cnt < 16; cnt++) | |
1554 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1555 | ||
1556 | WRT_REG_DWORD(®->iobase_addr, 0xFF70); | |
1557 | dmp_reg = ®->iobase_window; | |
1558 | for (cnt = 0; cnt < 16; cnt++) | |
1559 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1560 | ||
1561 | iter_reg = fw->rseq_0_reg; | |
1562 | WRT_REG_DWORD(®->iobase_addr, 0xFFC0); | |
1563 | dmp_reg = ®->iobase_window; | |
1564 | for (cnt = 0; cnt < 16; cnt++) | |
1565 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1566 | ||
1567 | WRT_REG_DWORD(®->iobase_addr, 0xFFD0); | |
1568 | dmp_reg = ®->iobase_window; | |
1569 | for (cnt = 0; cnt < 16; cnt++) | |
1570 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1571 | ||
1572 | WRT_REG_DWORD(®->iobase_addr, 0xFFE0); | |
1573 | dmp_reg = ®->iobase_window; | |
1574 | for (cnt = 0; cnt < sizeof(fw->rseq_1_reg) / 4; cnt++) | |
1575 | fw->rseq_1_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); | |
1576 | ||
1577 | WRT_REG_DWORD(®->iobase_addr, 0xFFF0); | |
1578 | dmp_reg = ®->iobase_window; | |
1579 | for (cnt = 0; cnt < sizeof(fw->rseq_2_reg) / 4; cnt++) | |
1580 | fw->rseq_2_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); | |
1581 | ||
1582 | /* Auxiliary sequence registers. */ | |
1583 | iter_reg = fw->aseq_gp_reg; | |
1584 | WRT_REG_DWORD(®->iobase_addr, 0xB000); | |
1585 | dmp_reg = ®->iobase_window; | |
1586 | for (cnt = 0; cnt < 16; cnt++) | |
1587 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1588 | ||
1589 | WRT_REG_DWORD(®->iobase_addr, 0xB010); | |
1590 | dmp_reg = ®->iobase_window; | |
1591 | for (cnt = 0; cnt < 16; cnt++) | |
1592 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1593 | ||
1594 | WRT_REG_DWORD(®->iobase_addr, 0xB020); | |
1595 | dmp_reg = ®->iobase_window; | |
1596 | for (cnt = 0; cnt < 16; cnt++) | |
1597 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1598 | ||
1599 | WRT_REG_DWORD(®->iobase_addr, 0xB030); | |
1600 | dmp_reg = ®->iobase_window; | |
1601 | for (cnt = 0; cnt < 16; cnt++) | |
1602 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1603 | ||
1604 | WRT_REG_DWORD(®->iobase_addr, 0xB040); | |
1605 | dmp_reg = ®->iobase_window; | |
1606 | for (cnt = 0; cnt < 16; cnt++) | |
1607 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1608 | ||
1609 | WRT_REG_DWORD(®->iobase_addr, 0xB050); | |
1610 | dmp_reg = ®->iobase_window; | |
1611 | for (cnt = 0; cnt < 16; cnt++) | |
1612 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1613 | ||
1614 | WRT_REG_DWORD(®->iobase_addr, 0xB060); | |
1615 | dmp_reg = ®->iobase_window; | |
1616 | for (cnt = 0; cnt < 16; cnt++) | |
1617 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1618 | ||
1619 | WRT_REG_DWORD(®->iobase_addr, 0xB070); | |
1620 | dmp_reg = ®->iobase_window; | |
1621 | for (cnt = 0; cnt < 16; cnt++) | |
1622 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1623 | ||
1624 | iter_reg = fw->aseq_0_reg; | |
1625 | WRT_REG_DWORD(®->iobase_addr, 0xB0C0); | |
1626 | dmp_reg = ®->iobase_window; | |
1627 | for (cnt = 0; cnt < 16; cnt++) | |
1628 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1629 | ||
1630 | WRT_REG_DWORD(®->iobase_addr, 0xB0D0); | |
1631 | dmp_reg = ®->iobase_window; | |
1632 | for (cnt = 0; cnt < 16; cnt++) | |
1633 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1634 | ||
1635 | WRT_REG_DWORD(®->iobase_addr, 0xB0E0); | |
1636 | dmp_reg = ®->iobase_window; | |
1637 | for (cnt = 0; cnt < sizeof(fw->aseq_1_reg) / 4; cnt++) | |
1638 | fw->aseq_1_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); | |
1639 | ||
1640 | WRT_REG_DWORD(®->iobase_addr, 0xB0F0); | |
1641 | dmp_reg = ®->iobase_window; | |
1642 | for (cnt = 0; cnt < sizeof(fw->aseq_2_reg) / 4; cnt++) | |
1643 | fw->aseq_2_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); | |
1644 | ||
1645 | /* Command DMA registers. */ | |
1646 | WRT_REG_DWORD(®->iobase_addr, 0x7100); | |
1647 | dmp_reg = ®->iobase_window; | |
1648 | for (cnt = 0; cnt < sizeof(fw->cmd_dma_reg) / 4; cnt++) | |
1649 | fw->cmd_dma_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); | |
1650 | ||
1651 | /* Queues. */ | |
1652 | iter_reg = fw->req0_dma_reg; | |
1653 | WRT_REG_DWORD(®->iobase_addr, 0x7200); | |
1654 | dmp_reg = ®->iobase_window; | |
1655 | for (cnt = 0; cnt < 8; cnt++) | |
1656 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1657 | ||
1658 | dmp_reg = ®->iobase_q; | |
1659 | for (cnt = 0; cnt < 7; cnt++) | |
1660 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1661 | ||
1662 | iter_reg = fw->resp0_dma_reg; | |
1663 | WRT_REG_DWORD(®->iobase_addr, 0x7300); | |
1664 | dmp_reg = ®->iobase_window; | |
1665 | for (cnt = 0; cnt < 8; cnt++) | |
1666 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1667 | ||
1668 | dmp_reg = ®->iobase_q; | |
1669 | for (cnt = 0; cnt < 7; cnt++) | |
1670 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1671 | ||
1672 | iter_reg = fw->req1_dma_reg; | |
1673 | WRT_REG_DWORD(®->iobase_addr, 0x7400); | |
1674 | dmp_reg = ®->iobase_window; | |
1675 | for (cnt = 0; cnt < 8; cnt++) | |
1676 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1677 | ||
1678 | dmp_reg = ®->iobase_q; | |
1679 | for (cnt = 0; cnt < 7; cnt++) | |
1680 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1681 | ||
1682 | /* Transmit DMA registers. */ | |
1683 | iter_reg = fw->xmt0_dma_reg; | |
1684 | WRT_REG_DWORD(®->iobase_addr, 0x7600); | |
1685 | dmp_reg = ®->iobase_window; | |
1686 | for (cnt = 0; cnt < 16; cnt++) | |
1687 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1688 | ||
1689 | WRT_REG_DWORD(®->iobase_addr, 0x7610); | |
1690 | dmp_reg = ®->iobase_window; | |
1691 | for (cnt = 0; cnt < 16; cnt++) | |
1692 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1693 | ||
1694 | iter_reg = fw->xmt1_dma_reg; | |
1695 | WRT_REG_DWORD(®->iobase_addr, 0x7620); | |
1696 | dmp_reg = ®->iobase_window; | |
1697 | for (cnt = 0; cnt < 16; cnt++) | |
1698 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1699 | ||
1700 | WRT_REG_DWORD(®->iobase_addr, 0x7630); | |
1701 | dmp_reg = ®->iobase_window; | |
1702 | for (cnt = 0; cnt < 16; cnt++) | |
1703 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1704 | ||
1705 | iter_reg = fw->xmt2_dma_reg; | |
1706 | WRT_REG_DWORD(®->iobase_addr, 0x7640); | |
1707 | dmp_reg = ®->iobase_window; | |
1708 | for (cnt = 0; cnt < 16; cnt++) | |
1709 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1710 | ||
1711 | WRT_REG_DWORD(®->iobase_addr, 0x7650); | |
1712 | dmp_reg = ®->iobase_window; | |
1713 | for (cnt = 0; cnt < 16; cnt++) | |
1714 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1715 | ||
1716 | iter_reg = fw->xmt3_dma_reg; | |
1717 | WRT_REG_DWORD(®->iobase_addr, 0x7660); | |
1718 | dmp_reg = ®->iobase_window; | |
1719 | for (cnt = 0; cnt < 16; cnt++) | |
1720 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1721 | ||
1722 | WRT_REG_DWORD(®->iobase_addr, 0x7670); | |
1723 | dmp_reg = ®->iobase_window; | |
1724 | for (cnt = 0; cnt < 16; cnt++) | |
1725 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1726 | ||
1727 | iter_reg = fw->xmt4_dma_reg; | |
1728 | WRT_REG_DWORD(®->iobase_addr, 0x7680); | |
1729 | dmp_reg = ®->iobase_window; | |
1730 | for (cnt = 0; cnt < 16; cnt++) | |
1731 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1732 | ||
1733 | WRT_REG_DWORD(®->iobase_addr, 0x7690); | |
1734 | dmp_reg = ®->iobase_window; | |
1735 | for (cnt = 0; cnt < 16; cnt++) | |
1736 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1737 | ||
1738 | WRT_REG_DWORD(®->iobase_addr, 0x76A0); | |
1739 | dmp_reg = ®->iobase_window; | |
1740 | for (cnt = 0; cnt < sizeof(fw->xmt_data_dma_reg) / 4; cnt++) | |
1741 | fw->xmt_data_dma_reg[cnt] = | |
1742 | htonl(RD_REG_DWORD(dmp_reg++)); | |
1743 | ||
1744 | /* Receive DMA registers. */ | |
1745 | iter_reg = fw->rcvt0_data_dma_reg; | |
1746 | WRT_REG_DWORD(®->iobase_addr, 0x7700); | |
1747 | dmp_reg = ®->iobase_window; | |
1748 | for (cnt = 0; cnt < 16; cnt++) | |
1749 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1750 | ||
1751 | WRT_REG_DWORD(®->iobase_addr, 0x7710); | |
1752 | dmp_reg = ®->iobase_window; | |
1753 | for (cnt = 0; cnt < 16; cnt++) | |
1754 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1755 | ||
1756 | iter_reg = fw->rcvt1_data_dma_reg; | |
1757 | WRT_REG_DWORD(®->iobase_addr, 0x7720); | |
1758 | dmp_reg = ®->iobase_window; | |
1759 | for (cnt = 0; cnt < 16; cnt++) | |
1760 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1761 | ||
1762 | WRT_REG_DWORD(®->iobase_addr, 0x7730); | |
1763 | dmp_reg = ®->iobase_window; | |
1764 | for (cnt = 0; cnt < 16; cnt++) | |
1765 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1766 | ||
1767 | /* RISC registers. */ | |
1768 | iter_reg = fw->risc_gp_reg; | |
1769 | WRT_REG_DWORD(®->iobase_addr, 0x0F00); | |
1770 | dmp_reg = ®->iobase_window; | |
1771 | for (cnt = 0; cnt < 16; cnt++) | |
1772 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1773 | ||
1774 | WRT_REG_DWORD(®->iobase_addr, 0x0F10); | |
1775 | dmp_reg = ®->iobase_window; | |
1776 | for (cnt = 0; cnt < 16; cnt++) | |
1777 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1778 | ||
1779 | WRT_REG_DWORD(®->iobase_addr, 0x0F20); | |
1780 | dmp_reg = ®->iobase_window; | |
1781 | for (cnt = 0; cnt < 16; cnt++) | |
1782 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1783 | ||
1784 | WRT_REG_DWORD(®->iobase_addr, 0x0F30); | |
1785 | dmp_reg = ®->iobase_window; | |
1786 | for (cnt = 0; cnt < 16; cnt++) | |
1787 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1788 | ||
1789 | WRT_REG_DWORD(®->iobase_addr, 0x0F40); | |
1790 | dmp_reg = ®->iobase_window; | |
1791 | for (cnt = 0; cnt < 16; cnt++) | |
1792 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1793 | ||
1794 | WRT_REG_DWORD(®->iobase_addr, 0x0F50); | |
1795 | dmp_reg = ®->iobase_window; | |
1796 | for (cnt = 0; cnt < 16; cnt++) | |
1797 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1798 | ||
1799 | WRT_REG_DWORD(®->iobase_addr, 0x0F60); | |
1800 | dmp_reg = ®->iobase_window; | |
1801 | for (cnt = 0; cnt < 16; cnt++) | |
1802 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1803 | ||
1804 | WRT_REG_DWORD(®->iobase_addr, 0x0F70); | |
1805 | dmp_reg = ®->iobase_window; | |
1806 | for (cnt = 0; cnt < 16; cnt++) | |
1807 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1808 | ||
1809 | /* Local memory controller registers. */ | |
1810 | iter_reg = fw->lmc_reg; | |
1811 | WRT_REG_DWORD(®->iobase_addr, 0x3000); | |
1812 | dmp_reg = ®->iobase_window; | |
1813 | for (cnt = 0; cnt < 16; cnt++) | |
1814 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1815 | ||
1816 | WRT_REG_DWORD(®->iobase_addr, 0x3010); | |
1817 | dmp_reg = ®->iobase_window; | |
1818 | for (cnt = 0; cnt < 16; cnt++) | |
1819 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1820 | ||
1821 | WRT_REG_DWORD(®->iobase_addr, 0x3020); | |
1822 | dmp_reg = ®->iobase_window; | |
1823 | for (cnt = 0; cnt < 16; cnt++) | |
1824 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1825 | ||
1826 | WRT_REG_DWORD(®->iobase_addr, 0x3030); | |
1827 | dmp_reg = ®->iobase_window; | |
1828 | for (cnt = 0; cnt < 16; cnt++) | |
1829 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1830 | ||
1831 | WRT_REG_DWORD(®->iobase_addr, 0x3040); | |
1832 | dmp_reg = ®->iobase_window; | |
1833 | for (cnt = 0; cnt < 16; cnt++) | |
1834 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1835 | ||
1836 | WRT_REG_DWORD(®->iobase_addr, 0x3050); | |
1837 | dmp_reg = ®->iobase_window; | |
1838 | for (cnt = 0; cnt < 16; cnt++) | |
1839 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1840 | ||
1841 | WRT_REG_DWORD(®->iobase_addr, 0x3060); | |
1842 | dmp_reg = ®->iobase_window; | |
1843 | for (cnt = 0; cnt < 16; cnt++) | |
1844 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1845 | ||
1846 | WRT_REG_DWORD(®->iobase_addr, 0x3070); | |
1847 | dmp_reg = ®->iobase_window; | |
1848 | for (cnt = 0; cnt < 16; cnt++) | |
1849 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1850 | ||
1851 | /* Fibre Protocol Module registers. */ | |
1852 | iter_reg = fw->fpm_hdw_reg; | |
1853 | WRT_REG_DWORD(®->iobase_addr, 0x4000); | |
1854 | dmp_reg = ®->iobase_window; | |
1855 | for (cnt = 0; cnt < 16; cnt++) | |
1856 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1857 | ||
1858 | WRT_REG_DWORD(®->iobase_addr, 0x4010); | |
1859 | dmp_reg = ®->iobase_window; | |
1860 | for (cnt = 0; cnt < 16; cnt++) | |
1861 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1862 | ||
1863 | WRT_REG_DWORD(®->iobase_addr, 0x4020); | |
1864 | dmp_reg = ®->iobase_window; | |
1865 | for (cnt = 0; cnt < 16; cnt++) | |
1866 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1867 | ||
1868 | WRT_REG_DWORD(®->iobase_addr, 0x4030); | |
1869 | dmp_reg = ®->iobase_window; | |
1870 | for (cnt = 0; cnt < 16; cnt++) | |
1871 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1872 | ||
1873 | WRT_REG_DWORD(®->iobase_addr, 0x4040); | |
1874 | dmp_reg = ®->iobase_window; | |
1875 | for (cnt = 0; cnt < 16; cnt++) | |
1876 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1877 | ||
1878 | WRT_REG_DWORD(®->iobase_addr, 0x4050); | |
1879 | dmp_reg = ®->iobase_window; | |
1880 | for (cnt = 0; cnt < 16; cnt++) | |
1881 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1882 | ||
1883 | WRT_REG_DWORD(®->iobase_addr, 0x4060); | |
1884 | dmp_reg = ®->iobase_window; | |
1885 | for (cnt = 0; cnt < 16; cnt++) | |
1886 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1887 | ||
1888 | WRT_REG_DWORD(®->iobase_addr, 0x4070); | |
1889 | dmp_reg = ®->iobase_window; | |
1890 | for (cnt = 0; cnt < 16; cnt++) | |
1891 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1892 | ||
1893 | WRT_REG_DWORD(®->iobase_addr, 0x4080); | |
1894 | dmp_reg = ®->iobase_window; | |
1895 | for (cnt = 0; cnt < 16; cnt++) | |
1896 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1897 | ||
1898 | WRT_REG_DWORD(®->iobase_addr, 0x4090); | |
1899 | dmp_reg = ®->iobase_window; | |
1900 | for (cnt = 0; cnt < 16; cnt++) | |
1901 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1902 | ||
1903 | WRT_REG_DWORD(®->iobase_addr, 0x40A0); | |
1904 | dmp_reg = ®->iobase_window; | |
1905 | for (cnt = 0; cnt < 16; cnt++) | |
1906 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1907 | ||
1908 | WRT_REG_DWORD(®->iobase_addr, 0x40B0); | |
1909 | dmp_reg = ®->iobase_window; | |
1910 | for (cnt = 0; cnt < 16; cnt++) | |
1911 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1912 | ||
1913 | /* Frame Buffer registers. */ | |
1914 | iter_reg = fw->fb_hdw_reg; | |
1915 | WRT_REG_DWORD(®->iobase_addr, 0x6000); | |
1916 | dmp_reg = ®->iobase_window; | |
1917 | for (cnt = 0; cnt < 16; cnt++) | |
1918 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1919 | ||
1920 | WRT_REG_DWORD(®->iobase_addr, 0x6010); | |
1921 | dmp_reg = ®->iobase_window; | |
1922 | for (cnt = 0; cnt < 16; cnt++) | |
1923 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1924 | ||
1925 | WRT_REG_DWORD(®->iobase_addr, 0x6020); | |
1926 | dmp_reg = ®->iobase_window; | |
1927 | for (cnt = 0; cnt < 16; cnt++) | |
1928 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1929 | ||
1930 | WRT_REG_DWORD(®->iobase_addr, 0x6030); | |
1931 | dmp_reg = ®->iobase_window; | |
1932 | for (cnt = 0; cnt < 16; cnt++) | |
1933 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1934 | ||
1935 | WRT_REG_DWORD(®->iobase_addr, 0x6040); | |
1936 | dmp_reg = ®->iobase_window; | |
1937 | for (cnt = 0; cnt < 16; cnt++) | |
1938 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1939 | ||
1940 | WRT_REG_DWORD(®->iobase_addr, 0x6100); | |
1941 | dmp_reg = ®->iobase_window; | |
1942 | for (cnt = 0; cnt < 16; cnt++) | |
1943 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1944 | ||
1945 | WRT_REG_DWORD(®->iobase_addr, 0x6130); | |
1946 | dmp_reg = ®->iobase_window; | |
1947 | for (cnt = 0; cnt < 16; cnt++) | |
1948 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1949 | ||
1950 | WRT_REG_DWORD(®->iobase_addr, 0x6150); | |
1951 | dmp_reg = ®->iobase_window; | |
1952 | for (cnt = 0; cnt < 16; cnt++) | |
1953 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1954 | ||
1955 | WRT_REG_DWORD(®->iobase_addr, 0x6170); | |
1956 | dmp_reg = ®->iobase_window; | |
1957 | for (cnt = 0; cnt < 16; cnt++) | |
1958 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1959 | ||
1960 | WRT_REG_DWORD(®->iobase_addr, 0x6190); | |
1961 | dmp_reg = ®->iobase_window; | |
1962 | for (cnt = 0; cnt < 16; cnt++) | |
1963 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1964 | ||
1965 | WRT_REG_DWORD(®->iobase_addr, 0x61B0); | |
1966 | dmp_reg = ®->iobase_window; | |
1967 | for (cnt = 0; cnt < 16; cnt++) | |
1968 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1969 | ||
1970 | WRT_REG_DWORD(®->iobase_addr, 0x6F00); | |
1971 | dmp_reg = ®->iobase_window; | |
1972 | for (cnt = 0; cnt < 16; cnt++) | |
1973 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1974 | ||
1975 | /* Reset RISC. */ | |
1976 | WRT_REG_DWORD(®->ctrl_status, | |
1977 | CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); | |
1978 | for (cnt = 0; cnt < 30000; cnt++) { | |
1979 | if ((RD_REG_DWORD(®->ctrl_status) & | |
1980 | CSRX_DMA_ACTIVE) == 0) | |
1981 | break; | |
1982 | ||
1983 | udelay(10); | |
1984 | } | |
1985 | ||
1986 | WRT_REG_DWORD(®->ctrl_status, | |
1987 | CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); | |
1988 | pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); | |
1989 | ||
1990 | udelay(100); | |
1991 | /* Wait for firmware to complete NVRAM accesses. */ | |
1992 | mb0 = (uint32_t) RD_REG_WORD(®->mailbox0); | |
1993 | for (cnt = 10000 ; cnt && mb0; cnt--) { | |
1994 | udelay(5); | |
1995 | mb0 = (uint32_t) RD_REG_WORD(®->mailbox0); | |
1996 | barrier(); | |
1997 | } | |
1998 | ||
1999 | /* Wait for soft-reset to complete. */ | |
2000 | for (cnt = 0; cnt < 30000; cnt++) { | |
2001 | if ((RD_REG_DWORD(®->ctrl_status) & | |
2002 | CSRX_ISP_SOFT_RESET) == 0) | |
2003 | break; | |
2004 | ||
2005 | udelay(10); | |
2006 | } | |
2007 | WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET); | |
2008 | RD_REG_DWORD(®->hccr); /* PCI Posting. */ | |
2009 | } | |
2010 | ||
2011 | for (cnt = 30000; RD_REG_WORD(®->mailbox0) != 0 && | |
2012 | rval == QLA_SUCCESS; cnt--) { | |
2013 | if (cnt) | |
2014 | udelay(100); | |
2015 | else | |
2016 | rval = QLA_FUNCTION_TIMEOUT; | |
2017 | } | |
2018 | ||
2019 | if (rval == QLA_SUCCESS) | |
2020 | rval = qla2xxx_dump_memory(ha, fw->code_ram, | |
2021 | sizeof(fw->code_ram), fw->ext_mem, &nxt); | |
2022 | ||
2023 | if (rval == QLA_SUCCESS) { | |
2024 | nxt = qla2xxx_copy_queues(ha, nxt); | |
2025 | if (ha->eft) | |
2026 | memcpy(nxt, ha->eft, ntohl(ha->fw_dump->eft_size)); | |
2027 | } | |
2028 | ||
2029 | if (rval != QLA_SUCCESS) { | |
2030 | qla_printk(KERN_WARNING, ha, | |
2031 | "Failed to dump firmware (%x)!!!\n", rval); | |
2032 | ha->fw_dumped = 0; | |
6d9b61ed AV |
2033 | |
2034 | } else { | |
2035 | qla_printk(KERN_INFO, ha, | |
2036 | "Firmware dump saved to temp buffer (%ld/%p).\n", | |
d4e3e04d | 2037 | ha->host_no, ha->fw_dump); |
6d9b61ed AV |
2038 | ha->fw_dumped = 1; |
2039 | } | |
2040 | ||
c3a2f0df | 2041 | qla25xx_fw_dump_failed: |
6d9b61ed AV |
2042 | if (!hardware_locked) |
2043 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
2044 | } | |
2045 | ||
1da177e4 LT |
2046 | /****************************************************************************/ |
2047 | /* Driver Debug Functions. */ | |
2048 | /****************************************************************************/ | |
2049 | ||
fa2a1ce5 AV |
2050 | void |
2051 | qla2x00_dump_regs(scsi_qla_host_t *ha) | |
1da177e4 | 2052 | { |
6afd9763 | 2053 | int i; |
3d71644c | 2054 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
6afd9763 AV |
2055 | struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; |
2056 | uint16_t __iomem *mbx_reg; | |
2057 | ||
2058 | mbx_reg = IS_FWI2_CAPABLE(ha) ? ®24->mailbox0: | |
2059 | MAILBOX_REG(ha, reg, 0); | |
1da177e4 LT |
2060 | |
2061 | printk("Mailbox registers:\n"); | |
6afd9763 AV |
2062 | for (i = 0; i < 6; i++) |
2063 | printk("scsi(%ld): mbox %d 0x%04x \n", ha->host_no, i, | |
2064 | RD_REG_WORD(mbx_reg++)); | |
1da177e4 LT |
2065 | } |
2066 | ||
2067 | ||
2068 | void | |
fa2a1ce5 | 2069 | qla2x00_dump_buffer(uint8_t * b, uint32_t size) |
1da177e4 LT |
2070 | { |
2071 | uint32_t cnt; | |
2072 | uint8_t c; | |
2073 | ||
2074 | printk(" 0 1 2 3 4 5 6 7 8 9 " | |
2075 | "Ah Bh Ch Dh Eh Fh\n"); | |
2076 | printk("----------------------------------------" | |
2077 | "----------------------\n"); | |
2078 | ||
2079 | for (cnt = 0; cnt < size;) { | |
2080 | c = *b++; | |
2081 | printk("%02x",(uint32_t) c); | |
2082 | cnt++; | |
2083 | if (!(cnt % 16)) | |
2084 | printk("\n"); | |
2085 | else | |
2086 | printk(" "); | |
2087 | } | |
2088 | if (cnt % 16) | |
2089 | printk("\n"); | |
2090 | } | |
2091 | ||
2092 | /************************************************************************** | |
2093 | * qla2x00_print_scsi_cmd | |
2094 | * Dumps out info about the scsi cmd and srb. | |
fa2a1ce5 | 2095 | * Input |
1da177e4 LT |
2096 | * cmd : struct scsi_cmnd |
2097 | **************************************************************************/ | |
2098 | void | |
fa2a1ce5 | 2099 | qla2x00_print_scsi_cmd(struct scsi_cmnd * cmd) |
1da177e4 LT |
2100 | { |
2101 | int i; | |
2102 | struct scsi_qla_host *ha; | |
2103 | srb_t *sp; | |
2104 | ||
2105 | ha = (struct scsi_qla_host *)cmd->device->host->hostdata; | |
2106 | ||
2107 | sp = (srb_t *) cmd->SCp.ptr; | |
2108 | printk("SCSI Command @=0x%p, Handle=0x%p\n", cmd, cmd->host_scribble); | |
2109 | printk(" chan=0x%02x, target=0x%02x, lun=0x%02x, cmd_len=0x%02x\n", | |
2110 | cmd->device->channel, cmd->device->id, cmd->device->lun, | |
2111 | cmd->cmd_len); | |
2112 | printk(" CDB: "); | |
2113 | for (i = 0; i < cmd->cmd_len; i++) { | |
2114 | printk("0x%02x ", cmd->cmnd[i]); | |
2115 | } | |
c6295cdf | 2116 | printk("\n seg_cnt=%d, allowed=%d, retries=%d\n", |
385d70b4 | 2117 | scsi_sg_count(cmd), cmd->allowed, cmd->retries); |
1da177e4 | 2118 | printk(" request buffer=0x%p, request buffer len=0x%x\n", |
385d70b4 | 2119 | scsi_sglist(cmd), scsi_bufflen(cmd)); |
1da177e4 LT |
2120 | printk(" tag=%d, transfersize=0x%x\n", |
2121 | cmd->tag, cmd->transfersize); | |
fa2a1ce5 | 2122 | printk(" serial_number=%lx, SP=%p\n", cmd->serial_number, sp); |
1da177e4 LT |
2123 | printk(" data direction=%d\n", cmd->sc_data_direction); |
2124 | ||
2125 | if (!sp) | |
2126 | return; | |
2127 | ||
2128 | printk(" sp flags=0x%x\n", sp->flags); | |
1da177e4 LT |
2129 | } |
2130 | ||
6d9b61ed AV |
2131 | void |
2132 | qla2x00_dump_pkt(void *pkt) | |
2133 | { | |
2134 | uint32_t i; | |
2135 | uint8_t *data = (uint8_t *) pkt; | |
2136 | ||
2137 | for (i = 0; i < 64; i++) { | |
2138 | if (!(i % 4)) | |
2139 | printk("\n%02x: ", i); | |
2140 | ||
2141 | printk("%02x ", data[i]); | |
2142 | } | |
2143 | printk("\n"); | |
2144 | } | |
2145 | ||
1da177e4 LT |
2146 | #if defined(QL_DEBUG_ROUTINES) |
2147 | /* | |
2148 | * qla2x00_formatted_dump_buffer | |
2149 | * Prints string plus buffer. | |
2150 | * | |
2151 | * Input: | |
2152 | * string = Null terminated string (no newline at end). | |
2153 | * buffer = buffer address. | |
2154 | * wd_size = word size 8, 16, 32 or 64 bits | |
2155 | * count = number of words. | |
2156 | */ | |
2157 | void | |
fa2a1ce5 AV |
2158 | qla2x00_formatted_dump_buffer(char *string, uint8_t * buffer, |
2159 | uint8_t wd_size, uint32_t count) | |
1da177e4 LT |
2160 | { |
2161 | uint32_t cnt; | |
2162 | uint16_t *buf16; | |
2163 | uint32_t *buf32; | |
2164 | ||
2165 | if (strcmp(string, "") != 0) | |
2166 | printk("%s\n",string); | |
2167 | ||
2168 | switch (wd_size) { | |
2169 | case 8: | |
2170 | printk(" 0 1 2 3 4 5 6 7 " | |
2171 | "8 9 Ah Bh Ch Dh Eh Fh\n"); | |
2172 | printk("-----------------------------------------" | |
2173 | "-------------------------------------\n"); | |
2174 | ||
2175 | for (cnt = 1; cnt <= count; cnt++, buffer++) { | |
2176 | printk("%02x",*buffer); | |
2177 | if (cnt % 16 == 0) | |
2178 | printk("\n"); | |
2179 | else | |
2180 | printk(" "); | |
2181 | } | |
2182 | if (cnt % 16 != 0) | |
2183 | printk("\n"); | |
2184 | break; | |
2185 | case 16: | |
2186 | printk(" 0 2 4 6 8 Ah " | |
2187 | " Ch Eh\n"); | |
2188 | printk("-----------------------------------------" | |
2189 | "-------------\n"); | |
2190 | ||
2191 | buf16 = (uint16_t *) buffer; | |
2192 | for (cnt = 1; cnt <= count; cnt++, buf16++) { | |
2193 | printk("%4x",*buf16); | |
2194 | ||
2195 | if (cnt % 8 == 0) | |
2196 | printk("\n"); | |
2197 | else if (*buf16 < 10) | |
2198 | printk(" "); | |
2199 | else | |
2200 | printk(" "); | |
2201 | } | |
2202 | if (cnt % 8 != 0) | |
2203 | printk("\n"); | |
2204 | break; | |
2205 | case 32: | |
2206 | printk(" 0 4 8 Ch\n"); | |
2207 | printk("------------------------------------------\n"); | |
2208 | ||
2209 | buf32 = (uint32_t *) buffer; | |
2210 | for (cnt = 1; cnt <= count; cnt++, buf32++) { | |
2211 | printk("%8x", *buf32); | |
2212 | ||
2213 | if (cnt % 4 == 0) | |
2214 | printk("\n"); | |
2215 | else if (*buf32 < 10) | |
2216 | printk(" "); | |
2217 | else | |
2218 | printk(" "); | |
2219 | } | |
2220 | if (cnt % 4 != 0) | |
2221 | printk("\n"); | |
2222 | break; | |
2223 | default: | |
2224 | break; | |
2225 | } | |
2226 | } | |
2227 | #endif |