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[SCSI] qla2xxx: Add host-statistics FC transport attributes.
[mirror_ubuntu-focal-kernel.git] / drivers / scsi / qla2xxx / qla_def.h
CommitLineData
fa90c54f
AV		 1/*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2005 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
1da177e4
LT		 7#ifndef __QLA_DEF_H
8#define __QLA_DEF_H
9
10#include <linux/kernel.h>
11#include <linux/init.h>
12#include <linux/types.h>
13#include <linux/module.h>
14#include <linux/list.h>
15#include <linux/pci.h>
16#include <linux/dma-mapping.h>
17#include <linux/sched.h>
18#include <linux/slab.h>
19#include <linux/dmapool.h>
20#include <linux/mempool.h>
21#include <linux/spinlock.h>
22#include <linux/completion.h>
abbd8870 23#include <linux/interrupt.h>
19a7b4ae 24#include <linux/workqueue.h>
5433383e 25#include <linux/firmware.h>
1da177e4
LT		 26#include <asm/semaphore.h>
27
28#include <scsi/scsi.h>
29#include <scsi/scsi_host.h>
30#include <scsi/scsi_device.h>
31#include <scsi/scsi_cmnd.h>
392e2f65 32#include <scsi/scsi_transport_fc.h>
1da177e4 33
5433383e 34#if defined(CONFIG_SCSI_QLA2XXX_EMBEDDED_FIRMWARE)
1da177e4
LT		 35#if defined(CONFIG_SCSI_QLA21XX) || defined(CONFIG_SCSI_QLA21XX_MODULE)
36#define IS_QLA2100(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2100)
37#else
38#define IS_QLA2100(ha) 0
39#endif
40
41#if defined(CONFIG_SCSI_QLA22XX) || defined(CONFIG_SCSI_QLA22XX_MODULE)
42#define IS_QLA2200(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2200)
43#else
44#define IS_QLA2200(ha) 0
45#endif
46
47#if defined(CONFIG_SCSI_QLA2300) || defined(CONFIG_SCSI_QLA2300_MODULE)
48#define IS_QLA2300(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2300)
49#define IS_QLA2312(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2312)
50#else
51#define IS_QLA2300(ha) 0
52#define IS_QLA2312(ha) 0
53#endif
54
55#if defined(CONFIG_SCSI_QLA2322) || defined(CONFIG_SCSI_QLA2322_MODULE)
56#define IS_QLA2322(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2322)
57#else
58#define IS_QLA2322(ha) 0
59#endif
60
61#if defined(CONFIG_SCSI_QLA6312) || defined(CONFIG_SCSI_QLA6312_MODULE)
62#define IS_QLA6312(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP6312)
63#define IS_QLA6322(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP6322)
64#else
65#define IS_QLA6312(ha) 0
66#define IS_QLA6322(ha) 0
67#endif
68
3d71644c
AV		 69#if defined(CONFIG_SCSI_QLA24XX) || defined(CONFIG_SCSI_QLA24XX_MODULE)
70#define IS_QLA2422(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422)
71#define IS_QLA2432(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432)
72#else
73#define IS_QLA2422(ha) 0
74#define IS_QLA2432(ha) 0
75#endif
76
77#if defined(CONFIG_SCSI_QLA25XX) || defined(CONFIG_SCSI_QLA25XX_MODULE)
78#define IS_QLA2512(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2512)
79#define IS_QLA2522(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2522)
80#else
81#define IS_QLA2512(ha) 0
82#define IS_QLA2522(ha) 0
83#endif
84
5433383e
AV		 85#else /* !defined(CONFIG_SCSI_QLA2XXX_EMBEDDED_FIRMWARE) */
86
87#define IS_QLA2100(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2100)
88#define IS_QLA2200(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2200)
89#define IS_QLA2300(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2300)
90#define IS_QLA2312(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2312)
91#define IS_QLA2322(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2322)
92#define IS_QLA6312(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP6312)
93#define IS_QLA6322(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP6322)
94#define IS_QLA2422(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422)
95#define IS_QLA2432(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432)
96#define IS_QLA2512(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2512)
97#define IS_QLA2522(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2522)
98#endif
99
1da177e4
LT		 100#define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
101 IS_QLA6312(ha) || IS_QLA6322(ha))
3d71644c
AV		 102#define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
103#define IS_QLA25XX(ha) (IS_QLA2512(ha) || IS_QLA2522(ha))
104
1da177e4
LT		 105/*
106 * Only non-ISP2[12]00 have extended addressing support in the firmware.
107 */
108#define HAS_EXTENDED_IDS(ha) (!IS_QLA2100(ha) && !IS_QLA2200(ha))
109
110/*
111 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
112 * but that's fine as we don't look at the last 24 ones for
113 * ISP2100 HBAs.
114 */
115#define MAILBOX_REGISTER_COUNT_2100 8
116#define MAILBOX_REGISTER_COUNT 32
117
118#define QLA2200A_RISC_ROM_VER 4
119#define FPM_2300 6
120#define FPM_2310 7
121
122#include "qla_settings.h"
123
fa2a1ce5 124/*
1da177e4
LT		 125 * Data bit definitions
126 */
127#define BIT_0 0x1
128#define BIT_1 0x2
129#define BIT_2 0x4
130#define BIT_3 0x8
131#define BIT_4 0x10
132#define BIT_5 0x20
133#define BIT_6 0x40
134#define BIT_7 0x80
135#define BIT_8 0x100
136#define BIT_9 0x200
137#define BIT_10 0x400
138#define BIT_11 0x800
139#define BIT_12 0x1000
140#define BIT_13 0x2000
141#define BIT_14 0x4000
142#define BIT_15 0x8000
143#define BIT_16 0x10000
144#define BIT_17 0x20000
145#define BIT_18 0x40000
146#define BIT_19 0x80000
147#define BIT_20 0x100000
148#define BIT_21 0x200000
149#define BIT_22 0x400000
150#define BIT_23 0x800000
151#define BIT_24 0x1000000
152#define BIT_25 0x2000000
153#define BIT_26 0x4000000
154#define BIT_27 0x8000000
155#define BIT_28 0x10000000
156#define BIT_29 0x20000000
157#define BIT_30 0x40000000
158#define BIT_31 0x80000000
159
160#define LSB(x) ((uint8_t)(x))
161#define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
162
163#define LSW(x) ((uint16_t)(x))
164#define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
165
166#define LSD(x) ((uint32_t)((uint64_t)(x)))
167#define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
168
169
170/*
171 * I/O register
172*/
173
174#define RD_REG_BYTE(addr) readb(addr)
175#define RD_REG_WORD(addr) readw(addr)
176#define RD_REG_DWORD(addr) readl(addr)
177#define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
178#define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
179#define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
180#define WRT_REG_BYTE(addr, data) writeb(data,addr)
181#define WRT_REG_WORD(addr, data) writew(data,addr)
182#define WRT_REG_DWORD(addr, data) writel(data,addr)
183
184/*
185 * Fibre Channel device definitions.
186 */
187#define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
188#define MAX_FIBRE_DEVICES 512
cc4731f5 189#define MAX_FIBRE_LUNS 0xFFFF
1da177e4
LT		 190#define MAX_RSCN_COUNT 32
191#define MAX_HOST_COUNT 16
192
193/*
194 * Host adapter default definitions.
195 */
196#define MAX_BUSES 1 /* We only have one bus today */
197#define MAX_TARGETS_2100 MAX_FIBRE_DEVICES
198#define MAX_TARGETS_2200 MAX_FIBRE_DEVICES
1da177e4
LT		 199#define MIN_LUNS 8
200#define MAX_LUNS MAX_FIBRE_LUNS
fa2a1ce5
AV		 201#define MAX_CMDS_PER_LUN 255
202
1da177e4
LT		 203/*
204 * Fibre Channel device definitions.
205 */
206#define SNS_LAST_LOOP_ID_2100 0xfe
207#define SNS_LAST_LOOP_ID_2300 0x7ff
208
209#define LAST_LOCAL_LOOP_ID 0x7d
210#define SNS_FL_PORT 0x7e
211#define FABRIC_CONTROLLER 0x7f
212#define SIMPLE_NAME_SERVER 0x80
213#define SNS_FIRST_LOOP_ID 0x81
214#define MANAGEMENT_SERVER 0xfe
215#define BROADCAST 0xff
216
3d71644c
AV		 217/*
218 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the
219 * valid range of an N-PORT id is 0 through 0x7ef.
220 */
221#define NPH_LAST_HANDLE 0x7ef
cca5335c 222#define NPH_MGMT_SERVER 0x7fa /* FFFFFA */
3d71644c
AV		 223#define NPH_SNS 0x7fc /* FFFFFC */
224#define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */
225#define NPH_F_PORT 0x7fe /* FFFFFE */
226#define NPH_IP_BROADCAST 0x7ff /* FFFFFF */
227
228#define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
229#include "qla_fw.h"
1da177e4
LT		 230
231/*
232 * Timeout timer counts in seconds
233 */
8482e118 234#define PORT_RETRY_TIME 1
1da177e4
LT		 235#define LOOP_DOWN_TIMEOUT 60
236#define LOOP_DOWN_TIME 255 /* 240 */
237#define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
238
239/* Maximum outstanding commands in ISP queues (1-65535) */
240#define MAX_OUTSTANDING_COMMANDS 1024
241
242/* ISP request and response entry counts (37-65535) */
243#define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
244#define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
245#define REQUEST_ENTRY_CNT_2XXX_EXT_MEM 4096 /* Number of request entries. */
3d71644c 246#define REQUEST_ENTRY_CNT_24XX 4096 /* Number of request entries. */
1da177e4
LT		 247#define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
248#define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
249
250/*
fa2a1ce5 251 * SCSI Request Block
1da177e4
LT		 252 */
253typedef struct srb {
254 struct list_head list;
255
256 struct scsi_qla_host *ha; /* HA the SP is queued on */
bdf79621 257 struct fc_port *fcport;
1da177e4
LT		 258
259 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */
260
261 struct timer_list timer; /* Command timer */
fa2a1ce5 262 atomic_t ref_count; /* Reference count for this structure */
1da177e4
LT		 263 uint16_t flags;
264
265 /* Request state */
266 uint16_t state;
267
1da177e4
LT		 268 /* Single transfer DMA context */
269 dma_addr_t dma_handle;
270
271 uint32_t request_sense_length;
272 uint8_t *request_sense_ptr;
273
1da177e4
LT		 274 /* SRB magic number */
275 uint16_t magic;
276#define SRB_MAGIC 0x10CB
277} srb_t;
278
279/*
280 * SRB flag definitions
281 */
282#define SRB_TIMEOUT BIT_0 /* Command timed out */
283#define SRB_DMA_VALID BIT_1 /* Command sent to ISP */
284#define SRB_WATCHDOG BIT_2 /* Command on watchdog list */
285#define SRB_ABORT_PENDING BIT_3 /* Command abort sent to device */
286
287#define SRB_ABORTED BIT_4 /* Command aborted command already */
288#define SRB_RETRY BIT_5 /* Command needs retrying */
289#define SRB_GOT_SENSE BIT_6 /* Command has sense data */
290#define SRB_FAILOVER BIT_7 /* Command in failover state */
291
292#define SRB_BUSY BIT_8 /* Command is in busy retry state */
293#define SRB_FO_CANCEL BIT_9 /* Command don't need to do failover */
294#define SRB_IOCTL BIT_10 /* IOCTL command. */
295#define SRB_TAPE BIT_11 /* FCP2 (Tape) command. */
296
297/*
298 * SRB state definitions
299 */
300#define SRB_FREE_STATE 0 /* returned back */
301#define SRB_PENDING_STATE 1 /* queued in LUN Q */
302#define SRB_ACTIVE_STATE 2 /* in Active Array */
303#define SRB_DONE_STATE 3 /* queued in Done Queue */
304#define SRB_RETRY_STATE 4 /* in Retry Queue */
305#define SRB_SUSPENDED_STATE 5 /* in suspended state */
306#define SRB_NO_QUEUE_STATE 6 /* is in between states */
307#define SRB_ACTIVE_TIMEOUT_STATE 7 /* in Active Array but timed out */
308#define SRB_FAILOVER_STATE 8 /* in Failover Queue */
309#define SRB_SCSI_RETRY_STATE 9 /* in Scsi Retry Queue */
310
311
312/*
313 * ISP I/O Register Set structure definitions.
314 */
3d71644c
AV		 315struct device_reg_2xxx {
316 uint16_t flash_address; /* Flash BIOS address */
317 uint16_t flash_data; /* Flash BIOS data */
1da177e4 318 uint16_t unused_1[1]; /* Gap */
3d71644c 319 uint16_t ctrl_status; /* Control/Status */
fa2a1ce5 320#define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
1da177e4
LT		 321#define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
322#define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
323
3d71644c 324 uint16_t ictrl; /* Interrupt control */
1da177e4
LT		 325#define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
326#define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
327
3d71644c 328 uint16_t istatus; /* Interrupt status */
1da177e4
LT		 329#define ISR_RISC_INT BIT_3 /* RISC interrupt */
330
3d71644c
AV		 331 uint16_t semaphore; /* Semaphore */
332 uint16_t nvram; /* NVRAM register. */
1da177e4
LT		 333#define NVR_DESELECT 0
334#define NVR_BUSY BIT_15
335#define NVR_WRT_ENABLE BIT_14 /* Write enable */
336#define NVR_PR_ENABLE BIT_13 /* Protection register enable */
337#define NVR_DATA_IN BIT_3
338#define NVR_DATA_OUT BIT_2
339#define NVR_SELECT BIT_1
340#define NVR_CLOCK BIT_0
341
342 union {
343 struct {
3d71644c
AV		 344 uint16_t mailbox0;
345 uint16_t mailbox1;
346 uint16_t mailbox2;
347 uint16_t mailbox3;
348 uint16_t mailbox4;
349 uint16_t mailbox5;
350 uint16_t mailbox6;
351 uint16_t mailbox7;
352 uint16_t unused_2[59]; /* Gap */
1da177e4
LT		 353 } __attribute__((packed)) isp2100;
354 struct {
3d71644c
AV		 355 /* Request Queue */
356 uint16_t req_q_in; /* In-Pointer */
357 uint16_t req_q_out; /* Out-Pointer */
358 /* Response Queue */
359 uint16_t rsp_q_in; /* In-Pointer */
360 uint16_t rsp_q_out; /* Out-Pointer */
1da177e4
LT		 361
362 /* RISC to Host Status */
fa2a1ce5 363 uint32_t host_status;
1da177e4
LT		 364#define HSR_RISC_INT BIT_15 /* RISC interrupt */
365#define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
366
367 /* Host to Host Semaphore */
fa2a1ce5 368 uint16_t host_semaphore;
3d71644c
AV		 369 uint16_t unused_3[17]; /* Gap */
370 uint16_t mailbox0;
371 uint16_t mailbox1;
372 uint16_t mailbox2;
373 uint16_t mailbox3;
374 uint16_t mailbox4;
375 uint16_t mailbox5;
376 uint16_t mailbox6;
377 uint16_t mailbox7;
378 uint16_t mailbox8;
379 uint16_t mailbox9;
380 uint16_t mailbox10;
381 uint16_t mailbox11;
382 uint16_t mailbox12;
383 uint16_t mailbox13;
384 uint16_t mailbox14;
385 uint16_t mailbox15;
386 uint16_t mailbox16;
387 uint16_t mailbox17;
388 uint16_t mailbox18;
389 uint16_t mailbox19;
390 uint16_t mailbox20;
391 uint16_t mailbox21;
392 uint16_t mailbox22;
393 uint16_t mailbox23;
394 uint16_t mailbox24;
395 uint16_t mailbox25;
396 uint16_t mailbox26;
397 uint16_t mailbox27;
398 uint16_t mailbox28;
399 uint16_t mailbox29;
400 uint16_t mailbox30;
401 uint16_t mailbox31;
402 uint16_t fb_cmd;
403 uint16_t unused_4[10]; /* Gap */
1da177e4
LT		 404 } __attribute__((packed)) isp2300;
405 } u;
406
3d71644c 407 uint16_t fpm_diag_config;
1da177e4 408 uint16_t unused_5[0x6]; /* Gap */
3d71644c 409 uint16_t pcr; /* Processor Control Register. */
1da177e4 410 uint16_t unused_6[0x5]; /* Gap */
3d71644c 411 uint16_t mctr; /* Memory Configuration and Timing. */
1da177e4 412 uint16_t unused_7[0x3]; /* Gap */
3d71644c 413 uint16_t fb_cmd_2100; /* Unused on 23XX */
1da177e4 414 uint16_t unused_8[0x3]; /* Gap */
3d71644c 415 uint16_t hccr; /* Host command & control register. */
1da177e4
LT		 416#define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
417#define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
418 /* HCCR commands */
419#define HCCR_RESET_RISC 0x1000 /* Reset RISC */
420#define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
421#define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
422#define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
423#define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
424#define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
425#define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
426#define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
427
428 uint16_t unused_9[5]; /* Gap */
3d71644c
AV		 429 uint16_t gpiod; /* GPIO Data register. */
430 uint16_t gpioe; /* GPIO Enable register. */
1da177e4
LT		 431#define GPIO_LED_MASK 0x00C0
432#define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
433#define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
434#define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
435#define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
436
437 union {
438 struct {
3d71644c
AV		 439 uint16_t unused_10[8]; /* Gap */
440 uint16_t mailbox8;
441 uint16_t mailbox9;
442 uint16_t mailbox10;
443 uint16_t mailbox11;
444 uint16_t mailbox12;
445 uint16_t mailbox13;
446 uint16_t mailbox14;
447 uint16_t mailbox15;
448 uint16_t mailbox16;
449 uint16_t mailbox17;
450 uint16_t mailbox18;
451 uint16_t mailbox19;
452 uint16_t mailbox20;
453 uint16_t mailbox21;
454 uint16_t mailbox22;
455 uint16_t mailbox23; /* Also probe reg. */
1da177e4
LT		 456 } __attribute__((packed)) isp2200;
457 } u_end;
3d71644c
AV		 458};
459
9a168bdd 460typedef union {
3d71644c
AV		 461 struct device_reg_2xxx isp;
462 struct device_reg_24xx isp24;
1da177e4
LT		 463} device_reg_t;
464
465#define ISP_REQ_Q_IN(ha, reg) \
466 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
467 &(reg)->u.isp2100.mailbox4 : \
468 &(reg)->u.isp2300.req_q_in)
469#define ISP_REQ_Q_OUT(ha, reg) \
470 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
471 &(reg)->u.isp2100.mailbox4 : \
472 &(reg)->u.isp2300.req_q_out)
473#define ISP_RSP_Q_IN(ha, reg) \
474 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
475 &(reg)->u.isp2100.mailbox5 : \
476 &(reg)->u.isp2300.rsp_q_in)
477#define ISP_RSP_Q_OUT(ha, reg) \
478 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
479 &(reg)->u.isp2100.mailbox5 : \
480 &(reg)->u.isp2300.rsp_q_out)
481
482#define MAILBOX_REG(ha, reg, num) \
483 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
484 (num < 8 ? \
485 &(reg)->u.isp2100.mailbox0 + (num) : \
486 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
487 &(reg)->u.isp2300.mailbox0 + (num))
488#define RD_MAILBOX_REG(ha, reg, num) \
489 RD_REG_WORD(MAILBOX_REG(ha, reg, num))
490#define WRT_MAILBOX_REG(ha, reg, num, data) \
491 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
492
493#define FB_CMD_REG(ha, reg) \
494 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
495 &(reg)->fb_cmd_2100 : \
496 &(reg)->u.isp2300.fb_cmd)
497#define RD_FB_CMD_REG(ha, reg) \
498 RD_REG_WORD(FB_CMD_REG(ha, reg))
499#define WRT_FB_CMD_REG(ha, reg, data) \
500 WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
501
502typedef struct {
503 uint32_t out_mb; /* outbound from driver */
504 uint32_t in_mb; /* Incoming from RISC */
505 uint16_t mb[MAILBOX_REGISTER_COUNT];
506 long buf_size;
507 void *bufp;
508 uint32_t tov;
509 uint8_t flags;
510#define MBX_DMA_IN BIT_0
511#define MBX_DMA_OUT BIT_1
512#define IOCTL_CMD BIT_2
513} mbx_cmd_t;
514
515#define MBX_TOV_SECONDS 30
516
517/*
518 * ISP product identification definitions in mailboxes after reset.
519 */
520#define PROD_ID_1 0x4953
521#define PROD_ID_2 0x0000
522#define PROD_ID_2a 0x5020
523#define PROD_ID_3 0x2020
524
525/*
526 * ISP mailbox Self-Test status codes
527 */
528#define MBS_FRM_ALIVE 0 /* Firmware Alive. */
529#define MBS_CHKSUM_ERR 1 /* Checksum Error. */
530#define MBS_BUSY 4 /* Busy. */
531
532/*
533 * ISP mailbox command complete status codes
534 */
535#define MBS_COMMAND_COMPLETE 0x4000
536#define MBS_INVALID_COMMAND 0x4001
537#define MBS_HOST_INTERFACE_ERROR 0x4002
538#define MBS_TEST_FAILED 0x4003
539#define MBS_COMMAND_ERROR 0x4005
540#define MBS_COMMAND_PARAMETER_ERROR 0x4006
541#define MBS_PORT_ID_USED 0x4007
542#define MBS_LOOP_ID_USED 0x4008
543#define MBS_ALL_IDS_IN_USE 0x4009
544#define MBS_NOT_LOGGED_IN 0x400A
3d71644c
AV		 545#define MBS_LINK_DOWN_ERROR 0x400B
546#define MBS_DIAG_ECHO_TEST_ERROR 0x400C
1da177e4
LT		 547
548/*
549 * ISP mailbox asynchronous event status codes
550 */
551#define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
552#define MBA_RESET 0x8001 /* Reset Detected. */
553#define MBA_SYSTEM_ERR 0x8002 /* System Error. */
554#define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
555#define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
556#define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
557#define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
558 /* occurred. */
559#define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
560#define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
561#define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
562#define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
563#define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
564#define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
565#define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
566#define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
567#define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
568#define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
569#define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
570#define MBA_IP_RECEIVE 0x8023 /* IP Received. */
571#define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
572#define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
573#define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
574#define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
575 /* used. */
576#define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
577#define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
578#define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
579#define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
580#define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
581#define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
582#define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
583#define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
584#define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
585#define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
586#define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
587#define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
588#define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
589
590/*
591 * Firmware options 1, 2, 3.
592 */
593#define FO1_AE_ON_LIPF8 BIT_0
594#define FO1_AE_ALL_LIP_RESET BIT_1
595#define FO1_CTIO_RETRY BIT_3
596#define FO1_DISABLE_LIP_F7_SW BIT_4
597#define FO1_DISABLE_100MS_LOS_WAIT BIT_5
3d71644c 598#define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */
1da177e4
LT		 599#define FO1_AE_ON_LOOP_INIT_ERR BIT_7
600#define FO1_SET_EMPHASIS_SWING BIT_8
601#define FO1_AE_AUTO_BYPASS BIT_9
602#define FO1_ENABLE_PURE_IOCB BIT_10
603#define FO1_AE_PLOGI_RJT BIT_11
604#define FO1_ENABLE_ABORT_SEQUENCE BIT_12
605#define FO1_AE_QUEUE_FULL BIT_13
606
607#define FO2_ENABLE_ATIO_TYPE_3 BIT_0
608#define FO2_REV_LOOPBACK BIT_1
609
610#define FO3_ENABLE_EMERG_IOCB BIT_0
611#define FO3_AE_RND_ERROR BIT_1
612
3d71644c
AV		 613/* 24XX additional firmware options */
614#define ADD_FO_COUNT 3
615#define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */
616#define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
617
618#define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
619
620#define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
621
1da177e4
LT		 622/*
623 * ISP mailbox commands
624 */
625#define MBC_LOAD_RAM 1 /* Load RAM. */
626#define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
627#define MBC_WRITE_RAM_WORD 4 /* Write RAM word. */
628#define MBC_READ_RAM_WORD 5 /* Read RAM word. */
629#define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
630#define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
631#define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
632#define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
633#define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
634#define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
635#define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
636#define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
637#define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
638#define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
f6ef3b18 639#define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */
1da177e4
LT		 640#define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
641#define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
642#define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
643#define MBC_RESET 0x18 /* Reset. */
644#define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
645#define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
646#define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
647#define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
648#define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
649#define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
650#define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
651#define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
652#define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
653#define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
654#define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
655#define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
656#define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
657#define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
658#define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
659#define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
660#define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
661#define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
662#define MBC_GET_RNID_PARAMS 0x5a /* Data Rate */
663#define MBC_DATA_RATE 0x5d /* Get RNID parameters */
664#define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
665#define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
666 /* Initialization Procedure */
667#define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
668#define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
669#define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
670#define MBC_TARGET_RESET 0x66 /* Target Reset. */
671#define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
672#define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
673#define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
674#define MBC_GET_PORT_NAME 0x6a /* Get port name. */
675#define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
676#define MBC_LIP_RESET 0x6c /* LIP reset. */
677#define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
678 /* commandd. */
679#define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
680#define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
681#define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
682#define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
683#define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
684#define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
685#define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
686#define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
687#define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
688#define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
689#define MBC_LUN_RESET 0x7E /* Send LUN reset */
690
3d71644c
AV		 691/*
692 * ISP24xx mailbox commands
693 */
694#define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */
695#define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */
696#define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */
697#define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */
698#define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */
699#define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */
700#define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */
701#define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */
702#define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */
703#define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */
704#define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */
705#define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */
706
1da177e4
LT		 707/* Firmware return data sizes */
708#define FCAL_MAP_SIZE 128
709
710/* Mailbox bit definitions for out_mb and in_mb */
711#define MBX_31 BIT_31
712#define MBX_30 BIT_30
713#define MBX_29 BIT_29
714#define MBX_28 BIT_28
715#define MBX_27 BIT_27
716#define MBX_26 BIT_26
717#define MBX_25 BIT_25
718#define MBX_24 BIT_24
719#define MBX_23 BIT_23
720#define MBX_22 BIT_22
721#define MBX_21 BIT_21
722#define MBX_20 BIT_20
723#define MBX_19 BIT_19
724#define MBX_18 BIT_18
725#define MBX_17 BIT_17
726#define MBX_16 BIT_16
727#define MBX_15 BIT_15
728#define MBX_14 BIT_14
729#define MBX_13 BIT_13
730#define MBX_12 BIT_12
731#define MBX_11 BIT_11
732#define MBX_10 BIT_10
733#define MBX_9 BIT_9
734#define MBX_8 BIT_8
735#define MBX_7 BIT_7
736#define MBX_6 BIT_6
737#define MBX_5 BIT_5
738#define MBX_4 BIT_4
739#define MBX_3 BIT_3
740#define MBX_2 BIT_2
741#define MBX_1 BIT_1
742#define MBX_0 BIT_0
743
744/*
745 * Firmware state codes from get firmware state mailbox command
746 */
747#define FSTATE_CONFIG_WAIT 0
748#define FSTATE_WAIT_AL_PA 1
749#define FSTATE_WAIT_LOGIN 2
750#define FSTATE_READY 3
751#define FSTATE_LOSS_OF_SYNC 4
752#define FSTATE_ERROR 5
753#define FSTATE_REINIT 6
754#define FSTATE_NON_PART 7
755
756#define FSTATE_CONFIG_CORRECT 0
757#define FSTATE_P2P_RCV_LIP 1
758#define FSTATE_P2P_CHOOSE_LOOP 2
759#define FSTATE_P2P_RCV_UNIDEN_LIP 3
760#define FSTATE_FATAL_ERROR 4
761#define FSTATE_LOOP_BACK_CONN 5
762
763/*
764 * Port Database structure definition
765 * Little endian except where noted.
766 */
767#define PORT_DATABASE_SIZE 128 /* bytes */
768typedef struct {
769 uint8_t options;
770 uint8_t control;
771 uint8_t master_state;
772 uint8_t slave_state;
773 uint8_t reserved[2];
774 uint8_t hard_address;
775 uint8_t reserved_1;
776 uint8_t port_id[4];
777 uint8_t node_name[WWN_SIZE];
778 uint8_t port_name[WWN_SIZE];
779 uint16_t execution_throttle;
780 uint16_t execution_count;
781 uint8_t reset_count;
782 uint8_t reserved_2;
783 uint16_t resource_allocation;
784 uint16_t current_allocation;
785 uint16_t queue_head;
786 uint16_t queue_tail;
787 uint16_t transmit_execution_list_next;
788 uint16_t transmit_execution_list_previous;
789 uint16_t common_features;
790 uint16_t total_concurrent_sequences;
791 uint16_t RO_by_information_category;
792 uint8_t recipient;
793 uint8_t initiator;
794 uint16_t receive_data_size;
795 uint16_t concurrent_sequences;
796 uint16_t open_sequences_per_exchange;
797 uint16_t lun_abort_flags;
798 uint16_t lun_stop_flags;
799 uint16_t stop_queue_head;
800 uint16_t stop_queue_tail;
801 uint16_t port_retry_timer;
802 uint16_t next_sequence_id;
803 uint16_t frame_count;
804 uint16_t PRLI_payload_length;
805 uint8_t prli_svc_param_word_0[2]; /* Big endian */
806 /* Bits 15-0 of word 0 */
807 uint8_t prli_svc_param_word_3[2]; /* Big endian */
808 /* Bits 15-0 of word 3 */
809 uint16_t loop_id;
810 uint16_t extended_lun_info_list_pointer;
811 uint16_t extended_lun_stop_list_pointer;
812} port_database_t;
813
814/*
815 * Port database slave/master states
816 */
817#define PD_STATE_DISCOVERY 0
818#define PD_STATE_WAIT_DISCOVERY_ACK 1
819#define PD_STATE_PORT_LOGIN 2
820#define PD_STATE_WAIT_PORT_LOGIN_ACK 3
821#define PD_STATE_PROCESS_LOGIN 4
822#define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
823#define PD_STATE_PORT_LOGGED_IN 6
824#define PD_STATE_PORT_UNAVAILABLE 7
825#define PD_STATE_PROCESS_LOGOUT 8
826#define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
827#define PD_STATE_PORT_LOGOUT 10
828#define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
829
830
4fdfefe5
AV		 831#define QLA_ZIO_MODE_5 (BIT_2 | BIT_0)
832#define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
833#define QLA_ZIO_DISABLED 0
834#define QLA_ZIO_DEFAULT_TIMER 2
835
1da177e4
LT		 836/*
837 * ISP Initialization Control Block.
838 * Little endian except where noted.
839 */
840#define ICB_VERSION 1
841typedef struct {
842 uint8_t version;
843 uint8_t reserved_1;
844
845 /*
846 * LSB BIT 0 = Enable Hard Loop Id
847 * LSB BIT 1 = Enable Fairness
848 * LSB BIT 2 = Enable Full-Duplex
849 * LSB BIT 3 = Enable Fast Posting
850 * LSB BIT 4 = Enable Target Mode
851 * LSB BIT 5 = Disable Initiator Mode
852 * LSB BIT 6 = Enable ADISC
853 * LSB BIT 7 = Enable Target Inquiry Data
854 *
855 * MSB BIT 0 = Enable PDBC Notify
856 * MSB BIT 1 = Non Participating LIP
857 * MSB BIT 2 = Descending Loop ID Search
858 * MSB BIT 3 = Acquire Loop ID in LIPA
859 * MSB BIT 4 = Stop PortQ on Full Status
860 * MSB BIT 5 = Full Login after LIP
861 * MSB BIT 6 = Node Name Option
862 * MSB BIT 7 = Ext IFWCB enable bit
863 */
864 uint8_t firmware_options[2];
865
866 uint16_t frame_payload_size;
867 uint16_t max_iocb_allocation;
868 uint16_t execution_throttle;
869 uint8_t retry_count;
870 uint8_t retry_delay; /* unused */
871 uint8_t port_name[WWN_SIZE]; /* Big endian. */
872 uint16_t hard_address;
873 uint8_t inquiry_data;
874 uint8_t login_timeout;
875 uint8_t node_name[WWN_SIZE]; /* Big endian. */
876
877 uint16_t request_q_outpointer;
878 uint16_t response_q_inpointer;
879 uint16_t request_q_length;
880 uint16_t response_q_length;
881 uint32_t request_q_address[2];
882 uint32_t response_q_address[2];
883
884 uint16_t lun_enables;
885 uint8_t command_resource_count;
886 uint8_t immediate_notify_resource_count;
887 uint16_t timeout;
888 uint8_t reserved_2[2];
889
890 /*
891 * LSB BIT 0 = Timer Operation mode bit 0
892 * LSB BIT 1 = Timer Operation mode bit 1
893 * LSB BIT 2 = Timer Operation mode bit 2
894 * LSB BIT 3 = Timer Operation mode bit 3
895 * LSB BIT 4 = Init Config Mode bit 0
896 * LSB BIT 5 = Init Config Mode bit 1
897 * LSB BIT 6 = Init Config Mode bit 2
898 * LSB BIT 7 = Enable Non part on LIHA failure
899 *
900 * MSB BIT 0 = Enable class 2
901 * MSB BIT 1 = Enable ACK0
902 * MSB BIT 2 =
903 * MSB BIT 3 =
904 * MSB BIT 4 = FC Tape Enable
905 * MSB BIT 5 = Enable FC Confirm
906 * MSB BIT 6 = Enable command queuing in target mode
907 * MSB BIT 7 = No Logo On Link Down
908 */
909 uint8_t add_firmware_options[2];
910
911 uint8_t response_accumulation_timer;
912 uint8_t interrupt_delay_timer;
913
914 /*
915 * LSB BIT 0 = Enable Read xfr_rdy
916 * LSB BIT 1 = Soft ID only
917 * LSB BIT 2 =
918 * LSB BIT 3 =
919 * LSB BIT 4 = FCP RSP Payload [0]
920 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
921 * LSB BIT 6 = Enable Out-of-Order frame handling
922 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
923 *
924 * MSB BIT 0 = Sbus enable - 2300
925 * MSB BIT 1 =
926 * MSB BIT 2 =
927 * MSB BIT 3 =
06c22bd1 928 * MSB BIT 4 = LED mode
1da177e4
LT		 929 * MSB BIT 5 = enable 50 ohm termination
930 * MSB BIT 6 = Data Rate (2300 only)
931 * MSB BIT 7 = Data Rate (2300 only)
932 */
933 uint8_t special_options[2];
934
935 uint8_t reserved_3[26];
936} init_cb_t;
937
938/*
939 * Get Link Status mailbox command return buffer.
940 */
3d71644c
AV		 941#define GLSO_SEND_RPS BIT_0
942#define GLSO_USE_DID BIT_3
943
1da177e4
LT		 944typedef struct {
945 uint32_t link_fail_cnt;
946 uint32_t loss_sync_cnt;
947 uint32_t loss_sig_cnt;
948 uint32_t prim_seq_err_cnt;
949 uint32_t inval_xmit_word_cnt;
950 uint32_t inval_crc_cnt;
951} link_stat_t;
952
953/*
954 * NVRAM Command values.
955 */
956#define NV_START_BIT BIT_2
957#define NV_WRITE_OP (BIT_26+BIT_24)
958#define NV_READ_OP (BIT_26+BIT_25)
959#define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
960#define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
961#define NV_DELAY_COUNT 10
962
963/*
964 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
965 */
966typedef struct {
967 /*
968 * NVRAM header
969 */
970 uint8_t id[4];
971 uint8_t nvram_version;
972 uint8_t reserved_0;
973
974 /*
975 * NVRAM RISC parameter block
976 */
977 uint8_t parameter_block_version;
978 uint8_t reserved_1;
979
980 /*
981 * LSB BIT 0 = Enable Hard Loop Id
982 * LSB BIT 1 = Enable Fairness
983 * LSB BIT 2 = Enable Full-Duplex
984 * LSB BIT 3 = Enable Fast Posting
985 * LSB BIT 4 = Enable Target Mode
986 * LSB BIT 5 = Disable Initiator Mode
987 * LSB BIT 6 = Enable ADISC
988 * LSB BIT 7 = Enable Target Inquiry Data
989 *
990 * MSB BIT 0 = Enable PDBC Notify
991 * MSB BIT 1 = Non Participating LIP
992 * MSB BIT 2 = Descending Loop ID Search
993 * MSB BIT 3 = Acquire Loop ID in LIPA
994 * MSB BIT 4 = Stop PortQ on Full Status
995 * MSB BIT 5 = Full Login after LIP
996 * MSB BIT 6 = Node Name Option
997 * MSB BIT 7 = Ext IFWCB enable bit
998 */
999 uint8_t firmware_options[2];
1000
1001 uint16_t frame_payload_size;
1002 uint16_t max_iocb_allocation;
1003 uint16_t execution_throttle;
1004 uint8_t retry_count;
1005 uint8_t retry_delay; /* unused */
1006 uint8_t port_name[WWN_SIZE]; /* Big endian. */
1007 uint16_t hard_address;
1008 uint8_t inquiry_data;
1009 uint8_t login_timeout;
1010 uint8_t node_name[WWN_SIZE]; /* Big endian. */
1011
1012 /*
1013 * LSB BIT 0 = Timer Operation mode bit 0
1014 * LSB BIT 1 = Timer Operation mode bit 1
1015 * LSB BIT 2 = Timer Operation mode bit 2
1016 * LSB BIT 3 = Timer Operation mode bit 3
1017 * LSB BIT 4 = Init Config Mode bit 0
1018 * LSB BIT 5 = Init Config Mode bit 1
1019 * LSB BIT 6 = Init Config Mode bit 2
1020 * LSB BIT 7 = Enable Non part on LIHA failure
1021 *
1022 * MSB BIT 0 = Enable class 2
1023 * MSB BIT 1 = Enable ACK0
1024 * MSB BIT 2 =
1025 * MSB BIT 3 =
1026 * MSB BIT 4 = FC Tape Enable
1027 * MSB BIT 5 = Enable FC Confirm
1028 * MSB BIT 6 = Enable command queuing in target mode
1029 * MSB BIT 7 = No Logo On Link Down
1030 */
1031 uint8_t add_firmware_options[2];
1032
1033 uint8_t response_accumulation_timer;
1034 uint8_t interrupt_delay_timer;
1035
1036 /*
1037 * LSB BIT 0 = Enable Read xfr_rdy
1038 * LSB BIT 1 = Soft ID only
1039 * LSB BIT 2 =
1040 * LSB BIT 3 =
1041 * LSB BIT 4 = FCP RSP Payload [0]
1042 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1043 * LSB BIT 6 = Enable Out-of-Order frame handling
1044 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1045 *
1046 * MSB BIT 0 = Sbus enable - 2300
1047 * MSB BIT 1 =
1048 * MSB BIT 2 =
1049 * MSB BIT 3 =
06c22bd1 1050 * MSB BIT 4 = LED mode
1da177e4
LT		 1051 * MSB BIT 5 = enable 50 ohm termination
1052 * MSB BIT 6 = Data Rate (2300 only)
1053 * MSB BIT 7 = Data Rate (2300 only)
1054 */
1055 uint8_t special_options[2];
1056
1057 /* Reserved for expanded RISC parameter block */
1058 uint8_t reserved_2[22];
1059
1060 /*
1061 * LSB BIT 0 = Tx Sensitivity 1G bit 0
1062 * LSB BIT 1 = Tx Sensitivity 1G bit 1
1063 * LSB BIT 2 = Tx Sensitivity 1G bit 2
1064 * LSB BIT 3 = Tx Sensitivity 1G bit 3
1065 * LSB BIT 4 = Rx Sensitivity 1G bit 0
1066 * LSB BIT 5 = Rx Sensitivity 1G bit 1
1067 * LSB BIT 6 = Rx Sensitivity 1G bit 2
1068 * LSB BIT 7 = Rx Sensitivity 1G bit 3
fa2a1ce5 1069 *
1da177e4
LT		 1070 * MSB BIT 0 = Tx Sensitivity 2G bit 0
1071 * MSB BIT 1 = Tx Sensitivity 2G bit 1
1072 * MSB BIT 2 = Tx Sensitivity 2G bit 2
1073 * MSB BIT 3 = Tx Sensitivity 2G bit 3
1074 * MSB BIT 4 = Rx Sensitivity 2G bit 0
1075 * MSB BIT 5 = Rx Sensitivity 2G bit 1
1076 * MSB BIT 6 = Rx Sensitivity 2G bit 2
1077 * MSB BIT 7 = Rx Sensitivity 2G bit 3
1078 *
1079 * LSB BIT 0 = Output Swing 1G bit 0
1080 * LSB BIT 1 = Output Swing 1G bit 1
1081 * LSB BIT 2 = Output Swing 1G bit 2
1082 * LSB BIT 3 = Output Emphasis 1G bit 0
1083 * LSB BIT 4 = Output Emphasis 1G bit 1
1084 * LSB BIT 5 = Output Swing 2G bit 0
1085 * LSB BIT 6 = Output Swing 2G bit 1
1086 * LSB BIT 7 = Output Swing 2G bit 2
fa2a1ce5 1087 *
1da177e4
LT		 1088 * MSB BIT 0 = Output Emphasis 2G bit 0
1089 * MSB BIT 1 = Output Emphasis 2G bit 1
1090 * MSB BIT 2 = Output Enable
1091 * MSB BIT 3 =
1092 * MSB BIT 4 =
1093 * MSB BIT 5 =
1094 * MSB BIT 6 =
1095 * MSB BIT 7 =
1096 */
1097 uint8_t seriallink_options[4];
1098
1099 /*
1100 * NVRAM host parameter block
1101 *
1102 * LSB BIT 0 = Enable spinup delay
1103 * LSB BIT 1 = Disable BIOS
1104 * LSB BIT 2 = Enable Memory Map BIOS
1105 * LSB BIT 3 = Enable Selectable Boot
1106 * LSB BIT 4 = Disable RISC code load
1107 * LSB BIT 5 = Set cache line size 1
1108 * LSB BIT 6 = PCI Parity Disable
1109 * LSB BIT 7 = Enable extended logging
1110 *
1111 * MSB BIT 0 = Enable 64bit addressing
1112 * MSB BIT 1 = Enable lip reset
1113 * MSB BIT 2 = Enable lip full login
1114 * MSB BIT 3 = Enable target reset
1115 * MSB BIT 4 = Enable database storage
1116 * MSB BIT 5 = Enable cache flush read
1117 * MSB BIT 6 = Enable database load
1118 * MSB BIT 7 = Enable alternate WWN
1119 */
1120 uint8_t host_p[2];
1121
1122 uint8_t boot_node_name[WWN_SIZE];
1123 uint8_t boot_lun_number;
1124 uint8_t reset_delay;
1125 uint8_t port_down_retry_count;
1126 uint8_t boot_id_number;
1127 uint16_t max_luns_per_target;
1128 uint8_t fcode_boot_port_name[WWN_SIZE];
1129 uint8_t alternate_port_name[WWN_SIZE];
1130 uint8_t alternate_node_name[WWN_SIZE];
1131
1132 /*
1133 * BIT 0 = Selective Login
1134 * BIT 1 = Alt-Boot Enable
1135 * BIT 2 =
1136 * BIT 3 = Boot Order List
1137 * BIT 4 =
1138 * BIT 5 = Selective LUN
1139 * BIT 6 =
1140 * BIT 7 = unused
1141 */
1142 uint8_t efi_parameters;
1143
1144 uint8_t link_down_timeout;
1145
cca5335c 1146 uint8_t adapter_id[16];
1da177e4
LT		 1147
1148 uint8_t alt1_boot_node_name[WWN_SIZE];
1149 uint16_t alt1_boot_lun_number;
1150 uint8_t alt2_boot_node_name[WWN_SIZE];
1151 uint16_t alt2_boot_lun_number;
1152 uint8_t alt3_boot_node_name[WWN_SIZE];
1153 uint16_t alt3_boot_lun_number;
1154 uint8_t alt4_boot_node_name[WWN_SIZE];
1155 uint16_t alt4_boot_lun_number;
1156 uint8_t alt5_boot_node_name[WWN_SIZE];
1157 uint16_t alt5_boot_lun_number;
1158 uint8_t alt6_boot_node_name[WWN_SIZE];
1159 uint16_t alt6_boot_lun_number;
1160 uint8_t alt7_boot_node_name[WWN_SIZE];
1161 uint16_t alt7_boot_lun_number;
1162
1163 uint8_t reserved_3[2];
1164
1165 /* Offset 200-215 : Model Number */
1166 uint8_t model_number[16];
1167
1168 /* OEM related items */
1169 uint8_t oem_specific[16];
1170
1171 /*
1172 * NVRAM Adapter Features offset 232-239
1173 *
1174 * LSB BIT 0 = External GBIC
1175 * LSB BIT 1 = Risc RAM parity
1176 * LSB BIT 2 = Buffer Plus Module
1177 * LSB BIT 3 = Multi Chip Adapter
1178 * LSB BIT 4 = Internal connector
1179 * LSB BIT 5 =
1180 * LSB BIT 6 =
1181 * LSB BIT 7 =
1182 *
1183 * MSB BIT 0 =
1184 * MSB BIT 1 =
1185 * MSB BIT 2 =
1186 * MSB BIT 3 =
1187 * MSB BIT 4 =
1188 * MSB BIT 5 =
1189 * MSB BIT 6 =
1190 * MSB BIT 7 =
1191 */
1192 uint8_t adapter_features[2];
1193
1194 uint8_t reserved_4[16];
1195
1196 /* Subsystem vendor ID for ISP2200 */
1197 uint16_t subsystem_vendor_id_2200;
1198
1199 /* Subsystem device ID for ISP2200 */
1200 uint16_t subsystem_device_id_2200;
1201
1202 uint8_t reserved_5;
1203 uint8_t checksum;
1204} nvram_t;
1205
1206/*
1207 * ISP queue - response queue entry definition.
1208 */
1209typedef struct {
1210 uint8_t data[60];
1211 uint32_t signature;
1212#define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
1213} response_t;
1214
1215typedef union {
1216 uint16_t extended;
1217 struct {
1218 uint8_t reserved;
1219 uint8_t standard;
1220 } id;
1221} target_id_t;
1222
1223#define SET_TARGET_ID(ha, to, from) \
1224do { \
1225 if (HAS_EXTENDED_IDS(ha)) \
1226 to.extended = cpu_to_le16(from); \
1227 else \
1228 to.id.standard = (uint8_t)from; \
1229} while (0)
1230
1231/*
1232 * ISP queue - command entry structure definition.
1233 */
1234#define COMMAND_TYPE 0x11 /* Command entry */
1da177e4
LT		 1235typedef struct {
1236 uint8_t entry_type; /* Entry type. */
1237 uint8_t entry_count; /* Entry count. */
1238 uint8_t sys_define; /* System defined. */
1239 uint8_t entry_status; /* Entry Status. */
1240 uint32_t handle; /* System handle. */
1241 target_id_t target; /* SCSI ID */
1242 uint16_t lun; /* SCSI LUN */
1243 uint16_t control_flags; /* Control flags. */
1244#define CF_WRITE BIT_6
1245#define CF_READ BIT_5
1246#define CF_SIMPLE_TAG BIT_3
1247#define CF_ORDERED_TAG BIT_2
1248#define CF_HEAD_TAG BIT_1
1249 uint16_t reserved_1;
1250 uint16_t timeout; /* Command timeout. */
1251 uint16_t dseg_count; /* Data segment count. */
1252 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1253 uint32_t byte_count; /* Total byte count. */
1254 uint32_t dseg_0_address; /* Data segment 0 address. */
1255 uint32_t dseg_0_length; /* Data segment 0 length. */
1256 uint32_t dseg_1_address; /* Data segment 1 address. */
1257 uint32_t dseg_1_length; /* Data segment 1 length. */
1258 uint32_t dseg_2_address; /* Data segment 2 address. */
1259 uint32_t dseg_2_length; /* Data segment 2 length. */
1260} cmd_entry_t;
1261
1262/*
1263 * ISP queue - 64-Bit addressing, command entry structure definition.
1264 */
1265#define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
1266typedef struct {
1267 uint8_t entry_type; /* Entry type. */
1268 uint8_t entry_count; /* Entry count. */
1269 uint8_t sys_define; /* System defined. */
1270 uint8_t entry_status; /* Entry Status. */
1271 uint32_t handle; /* System handle. */
1272 target_id_t target; /* SCSI ID */
1273 uint16_t lun; /* SCSI LUN */
1274 uint16_t control_flags; /* Control flags. */
1275 uint16_t reserved_1;
1276 uint16_t timeout; /* Command timeout. */
1277 uint16_t dseg_count; /* Data segment count. */
1278 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1279 uint32_t byte_count; /* Total byte count. */
1280 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1281 uint32_t dseg_0_length; /* Data segment 0 length. */
1282 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1283 uint32_t dseg_1_length; /* Data segment 1 length. */
1284} cmd_a64_entry_t, request_t;
1285
1286/*
1287 * ISP queue - continuation entry structure definition.
1288 */
1289#define CONTINUE_TYPE 0x02 /* Continuation entry. */
1290typedef struct {
1291 uint8_t entry_type; /* Entry type. */
1292 uint8_t entry_count; /* Entry count. */
1293 uint8_t sys_define; /* System defined. */
1294 uint8_t entry_status; /* Entry Status. */
1295 uint32_t reserved;
1296 uint32_t dseg_0_address; /* Data segment 0 address. */
1297 uint32_t dseg_0_length; /* Data segment 0 length. */
1298 uint32_t dseg_1_address; /* Data segment 1 address. */
1299 uint32_t dseg_1_length; /* Data segment 1 length. */
1300 uint32_t dseg_2_address; /* Data segment 2 address. */
1301 uint32_t dseg_2_length; /* Data segment 2 length. */
1302 uint32_t dseg_3_address; /* Data segment 3 address. */
1303 uint32_t dseg_3_length; /* Data segment 3 length. */
1304 uint32_t dseg_4_address; /* Data segment 4 address. */
1305 uint32_t dseg_4_length; /* Data segment 4 length. */
1306 uint32_t dseg_5_address; /* Data segment 5 address. */
1307 uint32_t dseg_5_length; /* Data segment 5 length. */
1308 uint32_t dseg_6_address; /* Data segment 6 address. */
1309 uint32_t dseg_6_length; /* Data segment 6 length. */
1310} cont_entry_t;
1311
1312/*
1313 * ISP queue - 64-Bit addressing, continuation entry structure definition.
1314 */
1315#define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
1316typedef struct {
1317 uint8_t entry_type; /* Entry type. */
1318 uint8_t entry_count; /* Entry count. */
1319 uint8_t sys_define; /* System defined. */
1320 uint8_t entry_status; /* Entry Status. */
1321 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1322 uint32_t dseg_0_length; /* Data segment 0 length. */
1323 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1324 uint32_t dseg_1_length; /* Data segment 1 length. */
1325 uint32_t dseg_2_address [2]; /* Data segment 2 address. */
1326 uint32_t dseg_2_length; /* Data segment 2 length. */
1327 uint32_t dseg_3_address[2]; /* Data segment 3 address. */
1328 uint32_t dseg_3_length; /* Data segment 3 length. */
1329 uint32_t dseg_4_address[2]; /* Data segment 4 address. */
1330 uint32_t dseg_4_length; /* Data segment 4 length. */
1331} cont_a64_entry_t;
1332
1333/*
1334 * ISP queue - status entry structure definition.
1335 */
1336#define STATUS_TYPE 0x03 /* Status entry. */
1337typedef struct {
1338 uint8_t entry_type; /* Entry type. */
1339 uint8_t entry_count; /* Entry count. */
1340 uint8_t sys_define; /* System defined. */
1341 uint8_t entry_status; /* Entry Status. */
1342 uint32_t handle; /* System handle. */
1343 uint16_t scsi_status; /* SCSI status. */
1344 uint16_t comp_status; /* Completion status. */
1345 uint16_t state_flags; /* State flags. */
1346 uint16_t status_flags; /* Status flags. */
1347 uint16_t rsp_info_len; /* Response Info Length. */
1348 uint16_t req_sense_length; /* Request sense data length. */
1349 uint32_t residual_length; /* Residual transfer length. */
1350 uint8_t rsp_info[8]; /* FCP response information. */
1351 uint8_t req_sense_data[32]; /* Request sense data. */
1352} sts_entry_t;
1353
1354/*
1355 * Status entry entry status
1356 */
3d71644c 1357#define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */
1da177e4
LT		 1358#define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
1359#define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
1360#define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
1361#define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
1362#define RF_BUSY BIT_1 /* Busy */
3d71644c
AV		 1363#define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
1364 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
1365#define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
1366 RF_INV_E_TYPE)
1da177e4
LT		 1367
1368/*
1369 * Status entry SCSI status bit definitions.
1370 */
1371#define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
1372#define SS_RESIDUAL_UNDER BIT_11
1373#define SS_RESIDUAL_OVER BIT_10
1374#define SS_SENSE_LEN_VALID BIT_9
1375#define SS_RESPONSE_INFO_LEN_VALID BIT_8
1376
1377#define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
1378#define SS_BUSY_CONDITION BIT_3
1379#define SS_CONDITION_MET BIT_2
1380#define SS_CHECK_CONDITION BIT_1
1381
1382/*
1383 * Status entry completion status
1384 */
1385#define CS_COMPLETE 0x0 /* No errors */
1386#define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
1387#define CS_DMA 0x2 /* A DMA direction error. */
1388#define CS_TRANSPORT 0x3 /* Transport error. */
1389#define CS_RESET 0x4 /* SCSI bus reset occurred */
1390#define CS_ABORTED 0x5 /* System aborted command. */
1391#define CS_TIMEOUT 0x6 /* Timeout error. */
1392#define CS_DATA_OVERRUN 0x7 /* Data overrun. */
1393
1394#define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
1395#define CS_QUEUE_FULL 0x1C /* Queue Full. */
1396#define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
1397 /* (selection timeout) */
1398#define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
1399#define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
1400#define CS_PORT_BUSY 0x2B /* Port Busy */
1401#define CS_COMPLETE_CHKCOND 0x30 /* Error? */
1402#define CS_BAD_PAYLOAD 0x80 /* Driver defined */
1403#define CS_UNKNOWN 0x81 /* Driver defined */
1404#define CS_RETRY 0x82 /* Driver defined */
1405#define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
1406
1407/*
1408 * Status entry status flags
1409 */
1410#define SF_ABTS_TERMINATED BIT_10
1411#define SF_LOGOUT_SENT BIT_13
1412
1413/*
1414 * ISP queue - status continuation entry structure definition.
1415 */
1416#define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
1417typedef struct {
1418 uint8_t entry_type; /* Entry type. */
1419 uint8_t entry_count; /* Entry count. */
1420 uint8_t sys_define; /* System defined. */
1421 uint8_t entry_status; /* Entry Status. */
1422 uint8_t data[60]; /* data */
1423} sts_cont_entry_t;
1424
1425/*
1426 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
1427 * structure definition.
1428 */
1429#define STATUS_TYPE_21 0x21 /* Status entry. */
1430typedef struct {
1431 uint8_t entry_type; /* Entry type. */
1432 uint8_t entry_count; /* Entry count. */
1433 uint8_t handle_count; /* Handle count. */
1434 uint8_t entry_status; /* Entry Status. */
1435 uint32_t handle[15]; /* System handles. */
1436} sts21_entry_t;
1437
1438/*
1439 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
1440 * structure definition.
1441 */
1442#define STATUS_TYPE_22 0x22 /* Status entry. */
1443typedef struct {
1444 uint8_t entry_type; /* Entry type. */
1445 uint8_t entry_count; /* Entry count. */
1446 uint8_t handle_count; /* Handle count. */
1447 uint8_t entry_status; /* Entry Status. */
1448 uint16_t handle[30]; /* System handles. */
1449} sts22_entry_t;
1450
1451/*
1452 * ISP queue - marker entry structure definition.
1453 */
1454#define MARKER_TYPE 0x04 /* Marker entry. */
1455typedef struct {
1456 uint8_t entry_type; /* Entry type. */
1457 uint8_t entry_count; /* Entry count. */
1458 uint8_t handle_count; /* Handle count. */
1459 uint8_t entry_status; /* Entry Status. */
1460 uint32_t sys_define_2; /* System defined. */
1461 target_id_t target; /* SCSI ID */
1462 uint8_t modifier; /* Modifier (7-0). */
1463#define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
1464#define MK_SYNC_ID 1 /* Synchronize ID */
1465#define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
1466#define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
1467 /* clear port changed, */
1468 /* use sequence number. */
1469 uint8_t reserved_1;
1470 uint16_t sequence_number; /* Sequence number of event */
1471 uint16_t lun; /* SCSI LUN */
1472 uint8_t reserved_2[48];
1473} mrk_entry_t;
1474
1475/*
1476 * ISP queue - Management Server entry structure definition.
1477 */
1478#define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
1479typedef struct {
1480 uint8_t entry_type; /* Entry type. */
1481 uint8_t entry_count; /* Entry count. */
1482 uint8_t handle_count; /* Handle count. */
1483 uint8_t entry_status; /* Entry Status. */
1484 uint32_t handle1; /* System handle. */
1485 target_id_t loop_id;
1486 uint16_t status;
1487 uint16_t control_flags; /* Control flags. */
1488 uint16_t reserved2;
1489 uint16_t timeout;
1490 uint16_t cmd_dsd_count;
1491 uint16_t total_dsd_count;
1492 uint8_t type;
1493 uint8_t r_ctl;
1494 uint16_t rx_id;
1495 uint16_t reserved3;
1496 uint32_t handle2;
1497 uint32_t rsp_bytecount;
1498 uint32_t req_bytecount;
1499 uint32_t dseg_req_address[2]; /* Data segment 0 address. */
1500 uint32_t dseg_req_length; /* Data segment 0 length. */
1501 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */
1502 uint32_t dseg_rsp_length; /* Data segment 1 length. */
1503} ms_iocb_entry_t;
1504
1505
1506/*
1507 * ISP queue - Mailbox Command entry structure definition.
1508 */
1509#define MBX_IOCB_TYPE 0x39
1510struct mbx_entry {
1511 uint8_t entry_type;
1512 uint8_t entry_count;
1513 uint8_t sys_define1;
1514 /* Use sys_define1 for source type */
1515#define SOURCE_SCSI 0x00
1516#define SOURCE_IP 0x01
1517#define SOURCE_VI 0x02
1518#define SOURCE_SCTP 0x03
1519#define SOURCE_MP 0x04
1520#define SOURCE_MPIOCTL 0x05
1521#define SOURCE_ASYNC_IOCB 0x07
1522
1523 uint8_t entry_status;
1524
1525 uint32_t handle;
1526 target_id_t loop_id;
1527
1528 uint16_t status;
1529 uint16_t state_flags;
1530 uint16_t status_flags;
1531
1532 uint32_t sys_define2[2];
1533
1534 uint16_t mb0;
1535 uint16_t mb1;
1536 uint16_t mb2;
1537 uint16_t mb3;
1538 uint16_t mb6;
1539 uint16_t mb7;
1540 uint16_t mb9;
1541 uint16_t mb10;
1542 uint32_t reserved_2[2];
1543 uint8_t node_name[WWN_SIZE];
1544 uint8_t port_name[WWN_SIZE];
1545};
1546
1547/*
1548 * ISP request and response queue entry sizes
1549 */
1550#define RESPONSE_ENTRY_SIZE (sizeof(response_t))
1551#define REQUEST_ENTRY_SIZE (sizeof(request_t))
1552
1553
1554/*
1555 * 24 bit port ID type definition.
1556 */
1557typedef union {
1558 uint32_t b24 : 24;
1559
1560 struct {
1561 uint8_t d_id[3];
1562 uint8_t rsvd_1;
1563 } r;
1564
1565 struct {
1566 uint8_t al_pa;
1567 uint8_t area;
1568 uint8_t domain;
1569 uint8_t rsvd_1;
1570 } b;
1571} port_id_t;
1572#define INVALID_PORT_ID 0xFFFFFF
1573
1574/*
1575 * Switch info gathering structure.
1576 */
1577typedef struct {
1578 port_id_t d_id;
1579 uint8_t node_name[WWN_SIZE];
1580 uint8_t port_name[WWN_SIZE];
1da177e4
LT		 1581} sw_info_t;
1582
1583/*
1584 * Inquiry command structure.
1585 */
1586#define INQ_DATA_SIZE 36
1587
1588/*
1589 * Inquiry mailbox IOCB packet definition.
1590 */
1591typedef struct {
1592 union {
1593 cmd_a64_entry_t cmd;
1594 sts_entry_t rsp;
3d71644c
AV		 1595 struct cmd_type_7 cmd24;
1596 struct sts_entry_24xx rsp24;
1da177e4
LT		 1597 } p;
1598 uint8_t inq[INQ_DATA_SIZE];
1599} inq_cmd_rsp_t;
1600
1601/*
1602 * Report LUN command structure.
1603 */
1604#define CHAR_TO_SHORT(a, b) (uint16_t)((uint8_t)b << 8 | (uint8_t)a)
1605
1606typedef struct {
1607 uint32_t len;
1608 uint32_t rsrv;
1609} rpt_hdr_t;
1610
1611typedef struct {
1612 struct {
1613 uint8_t b : 6;
1614 uint8_t address_method : 2;
1615 } msb;
1616 uint8_t lsb;
1617 uint8_t unused[6];
1618} rpt_lun_t;
1619
1620typedef struct {
1621 rpt_hdr_t hdr;
1622 rpt_lun_t lst[MAX_LUNS];
1623} rpt_lun_lst_t;
1624
1625/*
1626 * Report Lun mailbox IOCB packet definition.
1627 */
1628typedef struct {
1629 union {
1630 cmd_a64_entry_t cmd;
1631 sts_entry_t rsp;
3d71644c
AV		 1632 struct cmd_type_7 cmd24;
1633 struct sts_entry_24xx rsp24;
1da177e4
LT		 1634 } p;
1635 rpt_lun_lst_t list;
1636} rpt_lun_cmd_rsp_t;
1637
3d71644c 1638
1da177e4
LT		 1639/*
1640 * Fibre channel port type.
1641 */
1642 typedef enum {
1643 FCT_UNKNOWN,
1644 FCT_RSCN,
1645 FCT_SWITCH,
1646 FCT_BROADCAST,
1647 FCT_INITIATOR,
1648 FCT_TARGET
1649} fc_port_type_t;
1650
1651/*
1652 * Fibre channel port structure.
1653 */
1654typedef struct fc_port {
1655 struct list_head list;
1da177e4
LT		 1656 struct scsi_qla_host *ha;
1657 struct scsi_qla_host *vis_ha; /* only used when suspending lun */
1658
1659 uint8_t node_name[WWN_SIZE];
1660 uint8_t port_name[WWN_SIZE];
1661 port_id_t d_id;
1662 uint16_t loop_id;
1663 uint16_t old_loop_id;
1664
1665 fc_port_type_t port_type;
1666
1667 atomic_t state;
1668 uint32_t flags;
1669
bdf79621 1670 unsigned int os_target_id;
1da177e4
LT		 1671
1672 uint16_t iodesc_idx_sent;
1673
1674 int port_login_retry_count;
1675 int login_retry;
1676 atomic_t port_down_timer;
1677
1678 uint8_t device_type;
1679 uint8_t unused;
1680
1681 uint8_t mp_byte; /* multi-path byte (not used) */
1682 uint8_t cur_path; /* current path id */
1683
d97994dc
AV		 1684 spinlock_t rport_lock;
1685 struct fc_rport *rport, *drport;
ad3e0eda 1686 u32 supported_classes;
19a7b4ae
JSEC		 1687 struct work_struct rport_add_work;
1688 struct work_struct rport_del_work;
1da177e4
LT		 1689} fc_port_t;
1690
1691/*
1692 * Fibre channel port/lun states.
1693 */
1694#define FCS_UNCONFIGURED 1
1695#define FCS_DEVICE_DEAD 2
1696#define FCS_DEVICE_LOST 3
1697#define FCS_ONLINE 4
1698#define FCS_NOT_SUPPORTED 5
1699#define FCS_FAILOVER 6
1700#define FCS_FAILOVER_FAILED 7
1701
1702/*
1703 * FC port flags.
1704 */
1705#define FCF_FABRIC_DEVICE BIT_0
1706#define FCF_LOGIN_NEEDED BIT_1
1707#define FCF_FO_MASKED BIT_2
1708#define FCF_FAILOVER_NEEDED BIT_3
1709#define FCF_RESET_NEEDED BIT_4
1710#define FCF_PERSISTENT_BOUND BIT_5
1711#define FCF_TAPE_PRESENT BIT_6
1712#define FCF_FARP_DONE BIT_7
1713#define FCF_FARP_FAILED BIT_8
1714#define FCF_FARP_REPLY_NEEDED BIT_9
1715#define FCF_AUTH_REQ BIT_10
1716#define FCF_SEND_AUTH_REQ BIT_11
1717#define FCF_RECEIVE_AUTH_REQ BIT_12
1718#define FCF_AUTH_SUCCESS BIT_13
1719#define FCF_RLC_SUPPORT BIT_14
1720#define FCF_CONFIG BIT_15 /* Needed? */
1721#define FCF_RESCAN_NEEDED BIT_16
1722#define FCF_XP_DEVICE BIT_17
1723#define FCF_MSA_DEVICE BIT_18
1724#define FCF_EVA_DEVICE BIT_19
1725#define FCF_MSA_PORT_ACTIVE BIT_20
1726#define FCF_FAILBACK_DISABLE BIT_21
1727#define FCF_FAILOVER_DISABLE BIT_22
1728#define FCF_DSXXX_DEVICE BIT_23
1729#define FCF_AA_EVA_DEVICE BIT_24
3d71644c 1730#define FCF_AA_MSA_DEVICE BIT_25
1da177e4
LT		 1731
1732/* No loop ID flag. */
1733#define FC_NO_LOOP_ID 0x1000
1734
1da177e4
LT		 1735/*
1736 * FC-CT interface
1737 *
1738 * NOTE: All structures are big-endian in form.
1739 */
1740
1741#define CT_REJECT_RESPONSE 0x8001
1742#define CT_ACCEPT_RESPONSE 0x8002
cca5335c
AV		 1743#define CT_REASON_CANNOT_PERFORM 0x09
1744#define CT_EXPL_ALREADY_REGISTERED 0x10
1da177e4
LT		 1745
1746#define NS_N_PORT_TYPE 0x01
1747#define NS_NL_PORT_TYPE 0x02
1748#define NS_NX_PORT_TYPE 0x7F
1749
1750#define GA_NXT_CMD 0x100
1751#define GA_NXT_REQ_SIZE (16 + 4)
1752#define GA_NXT_RSP_SIZE (16 + 620)
1753
1754#define GID_PT_CMD 0x1A1
1755#define GID_PT_REQ_SIZE (16 + 4)
1756#define GID_PT_RSP_SIZE (16 + (MAX_FIBRE_DEVICES * 4))
1757
1758#define GPN_ID_CMD 0x112
1759#define GPN_ID_REQ_SIZE (16 + 4)
1760#define GPN_ID_RSP_SIZE (16 + 8)
1761
1762#define GNN_ID_CMD 0x113
1763#define GNN_ID_REQ_SIZE (16 + 4)
1764#define GNN_ID_RSP_SIZE (16 + 8)
1765
1766#define GFT_ID_CMD 0x117
1767#define GFT_ID_REQ_SIZE (16 + 4)
1768#define GFT_ID_RSP_SIZE (16 + 32)
1769
1770#define RFT_ID_CMD 0x217
1771#define RFT_ID_REQ_SIZE (16 + 4 + 32)
1772#define RFT_ID_RSP_SIZE 16
1773
1774#define RFF_ID_CMD 0x21F
1775#define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
1776#define RFF_ID_RSP_SIZE 16
1777
1778#define RNN_ID_CMD 0x213
1779#define RNN_ID_REQ_SIZE (16 + 4 + 8)
1780#define RNN_ID_RSP_SIZE 16
1781
1782#define RSNN_NN_CMD 0x239
1783#define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
1784#define RSNN_NN_RSP_SIZE 16
1785
cca5335c
AV		 1786/*
1787 * HBA attribute types.
1788 */
1789#define FDMI_HBA_ATTR_COUNT 9
1790#define FDMI_HBA_NODE_NAME 1
1791#define FDMI_HBA_MANUFACTURER 2
1792#define FDMI_HBA_SERIAL_NUMBER 3
1793#define FDMI_HBA_MODEL 4
1794#define FDMI_HBA_MODEL_DESCRIPTION 5
1795#define FDMI_HBA_HARDWARE_VERSION 6
1796#define FDMI_HBA_DRIVER_VERSION 7
1797#define FDMI_HBA_OPTION_ROM_VERSION 8
1798#define FDMI_HBA_FIRMWARE_VERSION 9
1799#define FDMI_HBA_OS_NAME_AND_VERSION 0xa
1800#define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
1801
1802struct ct_fdmi_hba_attr {
1803 uint16_t type;
1804 uint16_t len;
1805 union {
1806 uint8_t node_name[WWN_SIZE];
1807 uint8_t manufacturer[32];
1808 uint8_t serial_num[8];
1809 uint8_t model[16];
1810 uint8_t model_desc[80];
1811 uint8_t hw_version[16];
1812 uint8_t driver_version[32];
1813 uint8_t orom_version[16];
1814 uint8_t fw_version[16];
1815 uint8_t os_version[128];
1816 uint8_t max_ct_len[4];
1817 } a;
1818};
1819
1820struct ct_fdmi_hba_attributes {
1821 uint32_t count;
1822 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT];
1823};
1824
1825/*
1826 * Port attribute types.
1827 */
1828#define FDMI_PORT_ATTR_COUNT 5
1829#define FDMI_PORT_FC4_TYPES 1
1830#define FDMI_PORT_SUPPORT_SPEED 2
1831#define FDMI_PORT_CURRENT_SPEED 3
1832#define FDMI_PORT_MAX_FRAME_SIZE 4
1833#define FDMI_PORT_OS_DEVICE_NAME 5
1834#define FDMI_PORT_HOST_NAME 6
1835
1836struct ct_fdmi_port_attr {
1837 uint16_t type;
1838 uint16_t len;
1839 union {
1840 uint8_t fc4_types[32];
1841 uint32_t sup_speed;
1842 uint32_t cur_speed;
1843 uint32_t max_frame_size;
1844 uint8_t os_dev_name[32];
1845 uint8_t host_name[32];
1846 } a;
1847};
1848
1849/*
1850 * Port Attribute Block.
1851 */
1852struct ct_fdmi_port_attributes {
1853 uint32_t count;
1854 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT];
1855};
1856
1857/* FDMI definitions. */
1858#define GRHL_CMD 0x100
1859#define GHAT_CMD 0x101
1860#define GRPL_CMD 0x102
1861#define GPAT_CMD 0x110
1862
1863#define RHBA_CMD 0x200
1864#define RHBA_RSP_SIZE 16
1865
1866#define RHAT_CMD 0x201
1867#define RPRT_CMD 0x210
1868
1869#define RPA_CMD 0x211
1870#define RPA_RSP_SIZE 16
1871
1872#define DHBA_CMD 0x300
1873#define DHBA_REQ_SIZE (16 + 8)
1874#define DHBA_RSP_SIZE 16
1875
1876#define DHAT_CMD 0x301
1877#define DPRT_CMD 0x310
1878#define DPA_CMD 0x311
1879
1da177e4
LT		 1880/* CT command header -- request/response common fields */
1881struct ct_cmd_hdr {
1882 uint8_t revision;
1883 uint8_t in_id[3];
1884 uint8_t gs_type;
1885 uint8_t gs_subtype;
1886 uint8_t options;
1887 uint8_t reserved;
1888};
1889
1890/* CT command request */
1891struct ct_sns_req {
1892 struct ct_cmd_hdr header;
1893 uint16_t command;
1894 uint16_t max_rsp_size;
1895 uint8_t fragment_id;
1896 uint8_t reserved[3];
1897
1898 union {
1899 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID */
1900 struct {
1901 uint8_t reserved;
1902 uint8_t port_id[3];
1903 } port_id;
1904
1905 struct {
1906 uint8_t port_type;
1907 uint8_t domain;
1908 uint8_t area;
1909 uint8_t reserved;
1910 } gid_pt;
1911
1912 struct {
1913 uint8_t reserved;
1914 uint8_t port_id[3];
1915 uint8_t fc4_types[32];
1916 } rft_id;
1917
1918 struct {
1919 uint8_t reserved;
1920 uint8_t port_id[3];
1921 uint16_t reserved2;
1922 uint8_t fc4_feature;
1923 uint8_t fc4_type;
1924 } rff_id;
1925
1926 struct {
1927 uint8_t reserved;
1928 uint8_t port_id[3];
1929 uint8_t node_name[8];
1930 } rnn_id;
1931
1932 struct {
1933 uint8_t node_name[8];
1934 uint8_t name_len;
1935 uint8_t sym_node_name[255];
1936 } rsnn_nn;
cca5335c
AV		 1937
1938 struct {
1939 uint8_t hba_indentifier[8];
1940 } ghat;
1941
1942 struct {
1943 uint8_t hba_identifier[8];
1944 uint32_t entry_count;
1945 uint8_t port_name[8];
1946 struct ct_fdmi_hba_attributes attrs;
1947 } rhba;
1948
1949 struct {
1950 uint8_t hba_identifier[8];
1951 struct ct_fdmi_hba_attributes attrs;
1952 } rhat;
1953
1954 struct {
1955 uint8_t port_name[8];
1956 struct ct_fdmi_port_attributes attrs;
1957 } rpa;
1958
1959 struct {
1960 uint8_t port_name[8];
1961 } dhba;
1962
1963 struct {
1964 uint8_t port_name[8];
1965 } dhat;
1966
1967 struct {
1968 uint8_t port_name[8];
1969 } dprt;
1970
1971 struct {
1972 uint8_t port_name[8];
1973 } dpa;
1da177e4
LT		 1974 } req;
1975};
1976
1977/* CT command response header */
1978struct ct_rsp_hdr {
1979 struct ct_cmd_hdr header;
1980 uint16_t response;
1981 uint16_t residual;
1982 uint8_t fragment_id;
1983 uint8_t reason_code;
1984 uint8_t explanation_code;
1985 uint8_t vendor_unique;
1986};
1987
1988struct ct_sns_gid_pt_data {
1989 uint8_t control_byte;
1990 uint8_t port_id[3];
1991};
1992
1993struct ct_sns_rsp {
1994 struct ct_rsp_hdr header;
1995
1996 union {
1997 struct {
1998 uint8_t port_type;
1999 uint8_t port_id[3];
2000 uint8_t port_name[8];
2001 uint8_t sym_port_name_len;
2002 uint8_t sym_port_name[255];
2003 uint8_t node_name[8];
2004 uint8_t sym_node_name_len;
2005 uint8_t sym_node_name[255];
2006 uint8_t init_proc_assoc[8];
2007 uint8_t node_ip_addr[16];
2008 uint8_t class_of_service[4];
2009 uint8_t fc4_types[32];
2010 uint8_t ip_address[16];
2011 uint8_t fabric_port_name[8];
2012 uint8_t reserved;
2013 uint8_t hard_address[3];
2014 } ga_nxt;
2015
2016 struct {
2017 struct ct_sns_gid_pt_data entries[MAX_FIBRE_DEVICES];
2018 } gid_pt;
2019
2020 struct {
2021 uint8_t port_name[8];
2022 } gpn_id;
2023
2024 struct {
2025 uint8_t node_name[8];
2026 } gnn_id;
2027
2028 struct {
2029 uint8_t fc4_types[32];
2030 } gft_id;
cca5335c
AV		 2031
2032 struct {
2033 uint32_t entry_count;
2034 uint8_t port_name[8];
2035 struct ct_fdmi_hba_attributes attrs;
2036 } ghat;
1da177e4
LT		 2037 } rsp;
2038};
2039
2040struct ct_sns_pkt {
2041 union {
2042 struct ct_sns_req req;
2043 struct ct_sns_rsp rsp;
2044 } p;
2045};
2046
2047/*
2048 * SNS command structures -- for 2200 compatability.
2049 */
2050#define RFT_ID_SNS_SCMD_LEN 22
2051#define RFT_ID_SNS_CMD_SIZE 60
2052#define RFT_ID_SNS_DATA_SIZE 16
2053
2054#define RNN_ID_SNS_SCMD_LEN 10
2055#define RNN_ID_SNS_CMD_SIZE 36
2056#define RNN_ID_SNS_DATA_SIZE 16
2057
2058#define GA_NXT_SNS_SCMD_LEN 6
2059#define GA_NXT_SNS_CMD_SIZE 28
2060#define GA_NXT_SNS_DATA_SIZE (620 + 16)
2061
2062#define GID_PT_SNS_SCMD_LEN 6
2063#define GID_PT_SNS_CMD_SIZE 28
2064#define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES * 4 + 16)
2065
2066#define GPN_ID_SNS_SCMD_LEN 6
2067#define GPN_ID_SNS_CMD_SIZE 28
2068#define GPN_ID_SNS_DATA_SIZE (8 + 16)
2069
2070#define GNN_ID_SNS_SCMD_LEN 6
2071#define GNN_ID_SNS_CMD_SIZE 28
2072#define GNN_ID_SNS_DATA_SIZE (8 + 16)
2073
2074struct sns_cmd_pkt {
2075 union {
2076 struct {
2077 uint16_t buffer_length;
2078 uint16_t reserved_1;
2079 uint32_t buffer_address[2];
2080 uint16_t subcommand_length;
2081 uint16_t reserved_2;
2082 uint16_t subcommand;
2083 uint16_t size;
2084 uint32_t reserved_3;
2085 uint8_t param[36];
2086 } cmd;
2087
2088 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
2089 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
2090 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
2091 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
2092 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
2093 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
2094 } p;
2095};
2096
2097/* IO descriptors */
2098#define MAX_IO_DESCRIPTORS 32
2099
2100#define ABORT_IOCB_CB 0
2101#define ADISC_PORT_IOCB_CB 1
2102#define LOGOUT_PORT_IOCB_CB 2
2103#define LOGIN_PORT_IOCB_CB 3
2104#define LAST_IOCB_CB 4
2105
2106#define IODESC_INVALID_INDEX 0xFFFF
2107#define IODESC_ADISC_NEEDED 0xFFFE
2108#define IODESC_LOGIN_NEEDED 0xFFFD
2109
2110struct io_descriptor {
2111 uint16_t used:1;
2112 uint16_t idx:11;
2113 uint16_t cb_idx:4;
2114
2115 struct timer_list timer;
2116
2117 struct scsi_qla_host *ha;
2118
2119 port_id_t d_id;
2120 fc_port_t *remote_fcport;
2121
2122 uint32_t signature;
2123};
2124
2125struct qla_fw_info {
2126 unsigned short addressing; /* addressing method used to load fw */
2127#define FW_INFO_ADDR_NORMAL 0
2128#define FW_INFO_ADDR_EXTENDED 1
2129#define FW_INFO_ADDR_NOMORE 0xffff
2130 unsigned short *fwcode; /* pointer to FW array */
2131 unsigned short *fwlen; /* number of words in array */
2132 unsigned short *fwstart; /* start address for F/W */
2133 unsigned long *lfwstart; /* start address (long) for F/W */
2134};
2135
2136struct qla_board_info {
2137 char *drv_name;
2138
2139 char isp_name[8];
2140 struct qla_fw_info *fw_info;
fca29703
AV		 2141 char *fw_fname;
2142 struct scsi_host_template *sht;
1da177e4
LT		 2143};
2144
5433383e
AV		 2145struct fw_blob {
2146 char *name;
2147 uint32_t segs[4];
2148 const struct firmware *fw;
2149};
2150
1da177e4
LT		 2151/* Return data from MBC_GET_ID_LIST call. */
2152struct gid_list_info {
2153 uint8_t al_pa;
2154 uint8_t area;
fa2a1ce5 2155 uint8_t domain;
1da177e4
LT		 2156 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
2157 uint16_t loop_id; /* ISP23XX -- 6 bytes. */
3d71644c 2158 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */
1da177e4
LT		 2159};
2160#define GID_LIST_SIZE (sizeof(struct gid_list_info) * MAX_FIBRE_DEVICES)
2161
abbd8870
AV		 2162/*
2163 * ISP operations
2164 */
2165struct isp_operations {
2166
2167 int (*pci_config) (struct scsi_qla_host *);
2168 void (*reset_chip) (struct scsi_qla_host *);
2169 int (*chip_diag) (struct scsi_qla_host *);
2170 void (*config_rings) (struct scsi_qla_host *);
2171 void (*reset_adapter) (struct scsi_qla_host *);
2172 int (*nvram_config) (struct scsi_qla_host *);
2173 void (*update_fw_options) (struct scsi_qla_host *);
2174 int (*load_risc) (struct scsi_qla_host *, uint32_t *);
2175
2176 char * (*pci_info_str) (struct scsi_qla_host *, char *);
2177 char * (*fw_version_str) (struct scsi_qla_host *, char *);
2178
2179 irqreturn_t (*intr_handler) (int, void *, struct pt_regs *);
2180 void (*enable_intrs) (struct scsi_qla_host *);
2181 void (*disable_intrs) (struct scsi_qla_host *);
2182
2183 int (*abort_command) (struct scsi_qla_host *, srb_t *);
2184 int (*abort_target) (struct fc_port *);
2185 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
2186 uint8_t, uint8_t, uint16_t *, uint8_t);
1c7c6357
AV		 2187 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
2188 uint8_t, uint8_t);
abbd8870
AV		 2189
2190 uint16_t (*calc_req_entries) (uint16_t);
2191 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
8c958a99 2192 void * (*prep_ms_iocb) (struct scsi_qla_host *, uint32_t, uint32_t);
cca5335c
AV		 2193 void * (*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
2194 uint32_t);
abbd8870
AV		 2195
2196 uint8_t * (*read_nvram) (struct scsi_qla_host *, uint8_t *,
2197 uint32_t, uint32_t);
2198 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t,
2199 uint32_t);
2200
2201 void (*fw_dump) (struct scsi_qla_host *, int);
2202 void (*ascii_fw_dump) (struct scsi_qla_host *);
2203};
2204
1da177e4
LT		 2205/*
2206 * Linux Host Adapter structure
2207 */
2208typedef struct scsi_qla_host {
2209 struct list_head list;
2210
2211 /* Commonly used flags and state information. */
2212 struct Scsi_Host *host;
2213 struct pci_dev *pdev;
2214
2215 unsigned long host_no;
2216 unsigned long instance;
2217
2218 volatile struct {
2219 uint32_t init_done :1;
2220 uint32_t online :1;
2221 uint32_t mbox_int :1;
2222 uint32_t mbox_busy :1;
2223 uint32_t rscn_queue_overflow :1;
2224 uint32_t reset_active :1;
2225
2226 uint32_t management_server_logged_in :1;
2227 uint32_t process_response_queue :1;
2228
2229 uint32_t disable_risc_code_load :1;
2230 uint32_t enable_64bit_addressing :1;
2231 uint32_t enable_lip_reset :1;
2232 uint32_t enable_lip_full_login :1;
2233 uint32_t enable_target_reset :1;
2234 uint32_t enable_led_scheme :1;
3d71644c
AV		 2235 uint32_t msi_enabled :1;
2236 uint32_t msix_enabled :1;
1da177e4
LT		 2237 } flags;
2238
2239 atomic_t loop_state;
2240#define LOOP_TIMEOUT 1
2241#define LOOP_DOWN 2
2242#define LOOP_UP 3
2243#define LOOP_UPDATE 4
2244#define LOOP_READY 5
2245#define LOOP_DEAD 6
2246
2247 unsigned long dpc_flags;
2248#define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
2249#define RESET_ACTIVE 1
2250#define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
2251#define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
2252#define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
2253#define LOOP_RESYNC_ACTIVE 5
2254#define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
2255#define RSCN_UPDATE 7 /* Perform an RSCN update. */
2256#define MAILBOX_RETRY 8
2257#define ISP_RESET_NEEDED 9 /* Initiate a ISP reset. */
2258#define FAILOVER_EVENT_NEEDED 10
2259#define FAILOVER_EVENT 11
2260#define FAILOVER_NEEDED 12
2261#define SCSI_RESTART_NEEDED 13 /* Processes SCSI retry queue. */
2262#define PORT_RESTART_NEEDED 14 /* Processes Retry queue. */
2263#define RESTART_QUEUES_NEEDED 15 /* Restarts the Lun queue. */
2264#define ABORT_QUEUES_NEEDED 16
2265#define RELOGIN_NEEDED 17
2266#define LOGIN_RETRY_NEEDED 18 /* Initiate required fabric logins. */
2267#define REGISTER_FC4_NEEDED 19 /* SNS FC4 registration required. */
2268#define ISP_ABORT_RETRY 20 /* ISP aborted. */
2269#define FCPORT_RESCAN_NEEDED 21 /* IO descriptor processing needed */
2270#define IODESC_PROCESS_NEEDED 22 /* IO descriptor processing needed */
fa2a1ce5 2271#define IOCTL_ERROR_RECOVERY 23
1da177e4 2272#define LOOP_RESET_NEEDED 24
3d71644c 2273#define BEACON_BLINK_NEEDED 25
cca5335c 2274#define REGISTER_FDMI_NEEDED 26
d97994dc 2275#define FCPORT_UPDATE_NEEDED 27
1da177e4
LT		 2276
2277 uint32_t device_flags;
2278#define DFLG_LOCAL_DEVICES BIT_0
2279#define DFLG_RETRY_LOCAL_DEVICES BIT_1
2280#define DFLG_FABRIC_DEVICES BIT_2
2281#define SWITCH_FOUND BIT_3
2282#define DFLG_NO_CABLE BIT_4
2283
2284 /* SRB cache. */
2285#define SRB_MIN_REQ 128
2286 mempool_t *srb_mempool;
2287
fa2a1ce5 2288 /* This spinlock is used to protect "io transactions", you must
1da177e4
LT		 2289 * aquire it before doing any IO to the card, eg with RD_REG*() and
2290 * WRT_REG*() for the duration of your entire commandtransaction.
2291 *
2292 * This spinlock is of lower priority than the io request lock.
2293 */
2294
2295 spinlock_t hardware_lock ____cacheline_aligned;
2296
2297 device_reg_t __iomem *iobase; /* Base I/O address */
2298 unsigned long pio_address;
2299 unsigned long pio_length;
2300#define MIN_IOBASE_LEN 0x100
2301
2302 /* ISP ring lock, rings, and indexes */
2303 dma_addr_t request_dma; /* Physical address. */
2304 request_t *request_ring; /* Base virtual address */
2305 request_t *request_ring_ptr; /* Current address. */
2306 uint16_t req_ring_index; /* Current index. */
2307 uint16_t req_q_cnt; /* Number of available entries. */
2308 uint16_t request_q_length;
2309
2310 dma_addr_t response_dma; /* Physical address. */
2311 response_t *response_ring; /* Base virtual address */
2312 response_t *response_ring_ptr; /* Current address. */
2313 uint16_t rsp_ring_index; /* Current index. */
2314 uint16_t response_q_length;
fa2a1ce5 2315
abbd8870 2316 struct isp_operations isp_ops;
1da177e4
LT		 2317
2318 /* Outstandings ISP commands. */
2319 srb_t *outstanding_cmds[MAX_OUTSTANDING_COMMANDS];
fa2a1ce5 2320 uint32_t current_outstanding_cmd;
1da177e4
LT		 2321 srb_t *status_srb; /* Status continuation entry. */
2322
1da177e4
LT		 2323 uint16_t revision;
2324 uint8_t ports;
1da177e4
LT		 2325
2326 /* ISP configuration data. */
2327 uint16_t loop_id; /* Host adapter loop id */
2328 uint16_t fb_rev;
2329
2330 port_id_t d_id; /* Host adapter port id */
2331 uint16_t max_public_loop_ids;
2332 uint16_t min_external_loopid; /* First external loop Id */
2333
2334 uint16_t link_data_rate; /* F/W operating speed */
04414013
AV		 2335#define LDR_1GB 0
2336#define LDR_2GB 1
2337#define LDR_4GB 3
2338#define LDR_UNKNOWN 0xFFFF
1da177e4
LT		 2339
2340 uint8_t current_topology;
2341 uint8_t prev_topology;
2342#define ISP_CFG_NL 1
2343#define ISP_CFG_N 2
2344#define ISP_CFG_FL 4
2345#define ISP_CFG_F 8
2346
2347 uint8_t operating_mode; /* F/W operating mode */
2348#define LOOP 0
2349#define P2P 1
2350#define LOOP_P2P 2
2351#define P2P_LOOP 3
2352
fa2a1ce5 2353 uint8_t marker_needed;
1da177e4
LT		 2354
2355 uint8_t interrupts_on;
2356
2357 /* HBA serial number */
2358 uint8_t serial0;
2359 uint8_t serial1;
2360 uint8_t serial2;
2361
2362 /* NVRAM configuration data */
3d71644c 2363 uint16_t nvram_size;
1da177e4
LT		 2364 uint16_t nvram_base;
2365
2366 uint16_t loop_reset_delay;
1da177e4
LT		 2367 uint8_t retry_count;
2368 uint8_t login_timeout;
2369 uint16_t r_a_tov;
2370 int port_down_retry_count;
1da177e4 2371 uint8_t mbx_count;
1da177e4 2372 uint16_t last_loop_id;
cca5335c 2373 uint16_t mgmt_svr_loop_id;
1da177e4 2374
fa2a1ce5 2375 uint32_t login_retry_count;
1da177e4
LT		 2376
2377 /* Fibre Channel Device List. */
2378 struct list_head fcports;
2379 struct list_head rscn_fcports;
2380
2381 struct io_descriptor io_descriptors[MAX_IO_DESCRIPTORS];
2382 uint16_t iodesc_signature;
2383
1da177e4
LT		 2384 /* RSCN queue. */
2385 uint32_t rscn_queue[MAX_RSCN_COUNT];
2386 uint8_t rscn_in_ptr;
2387 uint8_t rscn_out_ptr;
2388
2389 /* SNS command interfaces. */
2390 ms_iocb_entry_t *ms_iocb;
2391 dma_addr_t ms_iocb_dma;
2392 struct ct_sns_pkt *ct_sns;
2393 dma_addr_t ct_sns_dma;
2394 /* SNS command interfaces for 2200. */
2395 struct sns_cmd_pkt *sns_cmd;
2396 dma_addr_t sns_cmd_dma;
2397
2398 pid_t dpc_pid;
2399 int dpc_should_die;
2400 struct completion dpc_inited;
2401 struct completion dpc_exited;
2402 struct semaphore *dpc_wait;
2403 uint8_t dpc_active; /* DPC routine is active */
2404
2405 /* Timeout timers. */
1da177e4
LT		 2406 uint8_t loop_down_abort_time; /* port down timer */
2407 atomic_t loop_down_timer; /* loop down timer */
2408 uint8_t link_down_timeout; /* link down timeout */
2409
2410 uint32_t timer_active;
2411 struct timer_list timer;
2412
2413 dma_addr_t gid_list_dma;
2414 struct gid_list_info *gid_list;
abbd8870 2415 int gid_list_info_size;
1da177e4
LT		 2416
2417 dma_addr_t rlc_rsp_dma;
2418 rpt_lun_cmd_rsp_t *rlc_rsp;
2419
fa2a1ce5 2420 /* Small DMA pool allocations -- maximum 256 bytes in length. */
1da177e4
LT		 2421#define DMA_POOL_SIZE 256
2422 struct dma_pool *s_dma_pool;
2423
2424 dma_addr_t init_cb_dma;
3d71644c
AV		 2425 init_cb_t *init_cb;
2426 int init_cb_size;
1da177e4
LT		 2427
2428 dma_addr_t iodesc_pd_dma;
2429 port_database_t *iodesc_pd;
2430
2431 /* These are used by mailbox operations. */
2432 volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
2433
2434 mbx_cmd_t *mcp;
2435 unsigned long mbx_cmd_flags;
2436#define MBX_INTERRUPT 1
2437#define MBX_INTR_WAIT 2
2438#define MBX_UPDATE_FLASH_ACTIVE 3
2439
2440 spinlock_t mbx_reg_lock; /* Mbx Cmd Register Lock */
2441
2442 struct semaphore mbx_cmd_sem; /* Serialialize mbx access */
2443 struct semaphore mbx_intr_sem; /* Used for completion notification */
2444
2445 uint32_t mbx_flags;
2446#define MBX_IN_PROGRESS BIT_0
2447#define MBX_BUSY BIT_1 /* Got the Access */
fa2a1ce5 2448#define MBX_SLEEPING_ON_SEM BIT_2
1da177e4
LT		 2449#define MBX_POLLING_FOR_COMP BIT_3
2450#define MBX_COMPLETED BIT_4
fa2a1ce5 2451#define MBX_TIMEDOUT BIT_5
1da177e4
LT		 2452#define MBX_ACCESS_TIMEDOUT BIT_6
2453
2454 mbx_cmd_t mc;
2455
1da177e4
LT		 2456 /* Basic firmware related information. */
2457 struct qla_board_info *brd_info;
2458 uint16_t fw_major_version;
2459 uint16_t fw_minor_version;
2460 uint16_t fw_subminor_version;
2461 uint16_t fw_attributes;
2462 uint32_t fw_memory_size;
2463 uint32_t fw_transfer_size;
2464
2465 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
2466 uint8_t fw_seriallink_options[4];
3d71644c 2467 uint16_t fw_seriallink_options24[4];
1da177e4
LT		 2468
2469 /* Firmware dump information. */
2470 void *fw_dump;
2471 int fw_dump_order;
2472 int fw_dump_reading;
2473 char *fw_dump_buffer;
2474 int fw_dump_buffer_len;
2475
3d71644c
AV		 2476 int fw_dumped;
2477 void *fw_dump24;
2478 int fw_dump24_len;
2479
1da177e4 2480 uint8_t host_str[16];
3d71644c 2481 uint32_t pci_attr;
1da177e4
LT		 2482
2483 uint16_t product_id[4];
2484
2485 uint8_t model_number[16+1];
2486#define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
2487 char *model_desc;
cca5335c 2488 uint8_t adapter_id[16+1];
1da177e4 2489
3d71644c
AV		 2490 uint8_t *node_name;
2491 uint8_t *port_name;
1da177e4
LT		 2492 uint32_t isp_abort_cnt;
2493
1da177e4
LT		 2494 /* Needed for BEACON */
2495 uint16_t beacon_blink_led;
2496 uint16_t beacon_green_on;
4fdfefe5
AV		 2497
2498 uint16_t zio_mode;
2499 uint16_t zio_timer;
392e2f65 2500 struct fc_host_statistics fc_host_stat;
1da177e4
LT		 2501} scsi_qla_host_t;
2502
2503
2504/*
2505 * Macros to help code, maintain, etc.
2506 */
2507#define LOOP_TRANSITION(ha) \
2508 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
23443b1d 2509 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
1da177e4 2510 atomic_read(&ha->loop_state) == LOOP_DOWN)
fa2a1ce5 2511
1da177e4 2512#define TGT_Q(ha, t) (ha->otgt[t])
1da177e4
LT		 2513
2514#define to_qla_host(x) ((scsi_qla_host_t *) (x)->hostdata)
2515
2516#define qla_printk(level, ha, format, arg...) \
2517 dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
2518
2519/*
2520 * qla2x00 local function return status codes
2521 */
2522#define MBS_MASK 0x3fff
2523
2524#define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
2525#define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
2526#define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
2527#define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
2528#define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
2529#define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
2530#define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
2531#define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
2532#define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
2533#define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
2534
2535#define QLA_FUNCTION_TIMEOUT 0x100
2536#define QLA_FUNCTION_PARAMETER_ERROR 0x101
2537#define QLA_FUNCTION_FAILED 0x102
2538#define QLA_MEMORY_ALLOC_FAILED 0x103
2539#define QLA_LOCK_TIMEOUT 0x104
2540#define QLA_ABORTED 0x105
2541#define QLA_SUSPENDED 0x106
2542#define QLA_BUSY 0x107
2543#define QLA_RSCNS_HANDLED 0x108
cca5335c 2544#define QLA_ALREADY_REGISTERED 0x109
1da177e4
LT		 2545
2546/*
2547* Stat info for all adpaters
2548*/
2549struct _qla2x00stats {
2550 unsigned long mboxtout; /* mailbox timeouts */
2551 unsigned long mboxerr; /* mailbox errors */
2552 unsigned long ispAbort; /* ISP aborts */
2553 unsigned long debugNo;
2554 unsigned long loop_resync;
2555 unsigned long outarray_full;
2556 unsigned long retry_q_cnt;
2557};
2558
2559#define NVRAM_DELAY() udelay(10)
2560
2561#define INVALID_HANDLE (MAX_OUTSTANDING_COMMANDS+1)
2562
2563/*
2564 * Flash support definitions
2565 */
2566#define FLASH_IMAGE_SIZE 131072
2567
2568#include "qla_gbl.h"
2569#include "qla_dbg.h"
2570#include "qla_inline.h"
1da177e4
LT		 2571
2572/*
2573* String arrays
2574*/
2575#define LINESIZE 256
2576#define MAXARGS 26
2577
2578#define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
2579#define CMD_COMPL_STATUS(Cmnd) ((Cmnd)->SCp.this_residual)
2580#define CMD_RESID_LEN(Cmnd) ((Cmnd)->SCp.buffers_residual)
2581#define CMD_SCSI_STATUS(Cmnd) ((Cmnd)->SCp.Status)
2582#define CMD_ACTUAL_SNSLEN(Cmnd) ((Cmnd)->SCp.Message)
2583#define CMD_ENTRY_STATUS(Cmnd) ((Cmnd)->SCp.have_data_in)
2584
2585#endif
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