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[SCSI] use scmd_id(), scmd_channel() throughout code
[mirror_ubuntu-artful-kernel.git] / drivers / scsi / qla2xxx / qla_def.h
CommitLineData
fa90c54f
AV		 1/*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2005 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
1da177e4
LT		 7#ifndef __QLA_DEF_H
8#define __QLA_DEF_H
9
10#include <linux/kernel.h>
11#include <linux/init.h>
12#include <linux/types.h>
13#include <linux/module.h>
14#include <linux/list.h>
15#include <linux/pci.h>
16#include <linux/dma-mapping.h>
17#include <linux/sched.h>
18#include <linux/slab.h>
19#include <linux/dmapool.h>
20#include <linux/mempool.h>
21#include <linux/spinlock.h>
22#include <linux/completion.h>
abbd8870 23#include <linux/interrupt.h>
1da177e4
LT		 24#include <asm/semaphore.h>
25
26#include <scsi/scsi.h>
27#include <scsi/scsi_host.h>
28#include <scsi/scsi_device.h>
29#include <scsi/scsi_cmnd.h>
30
1da177e4
LT		 31#if defined(CONFIG_SCSI_QLA21XX) || defined(CONFIG_SCSI_QLA21XX_MODULE)
32#define IS_QLA2100(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2100)
33#else
34#define IS_QLA2100(ha) 0
35#endif
36
37#if defined(CONFIG_SCSI_QLA22XX) || defined(CONFIG_SCSI_QLA22XX_MODULE)
38#define IS_QLA2200(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2200)
39#else
40#define IS_QLA2200(ha) 0
41#endif
42
43#if defined(CONFIG_SCSI_QLA2300) || defined(CONFIG_SCSI_QLA2300_MODULE)
44#define IS_QLA2300(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2300)
45#define IS_QLA2312(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2312)
46#else
47#define IS_QLA2300(ha) 0
48#define IS_QLA2312(ha) 0
49#endif
50
51#if defined(CONFIG_SCSI_QLA2322) || defined(CONFIG_SCSI_QLA2322_MODULE)
52#define IS_QLA2322(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2322)
53#else
54#define IS_QLA2322(ha) 0
55#endif
56
57#if defined(CONFIG_SCSI_QLA6312) || defined(CONFIG_SCSI_QLA6312_MODULE)
58#define IS_QLA6312(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP6312)
59#define IS_QLA6322(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP6322)
60#else
61#define IS_QLA6312(ha) 0
62#define IS_QLA6322(ha) 0
63#endif
64
3d71644c
AV		 65#if defined(CONFIG_SCSI_QLA24XX) || defined(CONFIG_SCSI_QLA24XX_MODULE)
66#define IS_QLA2422(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422)
67#define IS_QLA2432(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432)
68#else
69#define IS_QLA2422(ha) 0
70#define IS_QLA2432(ha) 0
71#endif
72
73#if defined(CONFIG_SCSI_QLA25XX) || defined(CONFIG_SCSI_QLA25XX_MODULE)
74#define IS_QLA2512(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2512)
75#define IS_QLA2522(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2522)
76#else
77#define IS_QLA2512(ha) 0
78#define IS_QLA2522(ha) 0
79#endif
80
1da177e4
LT		 81#define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
82 IS_QLA6312(ha) || IS_QLA6322(ha))
83
3d71644c
AV		 84#define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
85#define IS_QLA25XX(ha) (IS_QLA2512(ha) || IS_QLA2522(ha))
86
1da177e4
LT		 87/*
88 * Only non-ISP2[12]00 have extended addressing support in the firmware.
89 */
90#define HAS_EXTENDED_IDS(ha) (!IS_QLA2100(ha) && !IS_QLA2200(ha))
91
92/*
93 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
94 * but that's fine as we don't look at the last 24 ones for
95 * ISP2100 HBAs.
96 */
97#define MAILBOX_REGISTER_COUNT_2100 8
98#define MAILBOX_REGISTER_COUNT 32
99
100#define QLA2200A_RISC_ROM_VER 4
101#define FPM_2300 6
102#define FPM_2310 7
103
104#include "qla_settings.h"
105
fa2a1ce5 106/*
1da177e4
LT		 107 * Data bit definitions
108 */
109#define BIT_0 0x1
110#define BIT_1 0x2
111#define BIT_2 0x4
112#define BIT_3 0x8
113#define BIT_4 0x10
114#define BIT_5 0x20
115#define BIT_6 0x40
116#define BIT_7 0x80
117#define BIT_8 0x100
118#define BIT_9 0x200
119#define BIT_10 0x400
120#define BIT_11 0x800
121#define BIT_12 0x1000
122#define BIT_13 0x2000
123#define BIT_14 0x4000
124#define BIT_15 0x8000
125#define BIT_16 0x10000
126#define BIT_17 0x20000
127#define BIT_18 0x40000
128#define BIT_19 0x80000
129#define BIT_20 0x100000
130#define BIT_21 0x200000
131#define BIT_22 0x400000
132#define BIT_23 0x800000
133#define BIT_24 0x1000000
134#define BIT_25 0x2000000
135#define BIT_26 0x4000000
136#define BIT_27 0x8000000
137#define BIT_28 0x10000000
138#define BIT_29 0x20000000
139#define BIT_30 0x40000000
140#define BIT_31 0x80000000
141
142#define LSB(x) ((uint8_t)(x))
143#define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
144
145#define LSW(x) ((uint16_t)(x))
146#define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
147
148#define LSD(x) ((uint32_t)((uint64_t)(x)))
149#define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
150
151
152/*
153 * I/O register
154*/
155
156#define RD_REG_BYTE(addr) readb(addr)
157#define RD_REG_WORD(addr) readw(addr)
158#define RD_REG_DWORD(addr) readl(addr)
159#define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
160#define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
161#define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
162#define WRT_REG_BYTE(addr, data) writeb(data,addr)
163#define WRT_REG_WORD(addr, data) writew(data,addr)
164#define WRT_REG_DWORD(addr, data) writel(data,addr)
165
166/*
167 * Fibre Channel device definitions.
168 */
169#define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
170#define MAX_FIBRE_DEVICES 512
cc4731f5 171#define MAX_FIBRE_LUNS 0xFFFF
1da177e4
LT		 172#define MAX_RSCN_COUNT 32
173#define MAX_HOST_COUNT 16
174
175/*
176 * Host adapter default definitions.
177 */
178#define MAX_BUSES 1 /* We only have one bus today */
179#define MAX_TARGETS_2100 MAX_FIBRE_DEVICES
180#define MAX_TARGETS_2200 MAX_FIBRE_DEVICES
1da177e4
LT		 181#define MIN_LUNS 8
182#define MAX_LUNS MAX_FIBRE_LUNS
fa2a1ce5
AV		 183#define MAX_CMDS_PER_LUN 255
184
1da177e4
LT		 185/*
186 * Fibre Channel device definitions.
187 */
188#define SNS_LAST_LOOP_ID_2100 0xfe
189#define SNS_LAST_LOOP_ID_2300 0x7ff
190
191#define LAST_LOCAL_LOOP_ID 0x7d
192#define SNS_FL_PORT 0x7e
193#define FABRIC_CONTROLLER 0x7f
194#define SIMPLE_NAME_SERVER 0x80
195#define SNS_FIRST_LOOP_ID 0x81
196#define MANAGEMENT_SERVER 0xfe
197#define BROADCAST 0xff
198
3d71644c
AV		 199/*
200 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the
201 * valid range of an N-PORT id is 0 through 0x7ef.
202 */
203#define NPH_LAST_HANDLE 0x7ef
cca5335c 204#define NPH_MGMT_SERVER 0x7fa /* FFFFFA */
3d71644c
AV		 205#define NPH_SNS 0x7fc /* FFFFFC */
206#define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */
207#define NPH_F_PORT 0x7fe /* FFFFFE */
208#define NPH_IP_BROADCAST 0x7ff /* FFFFFF */
209
210#define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
211#include "qla_fw.h"
1da177e4
LT		 212
213/*
214 * Timeout timer counts in seconds
215 */
8482e118 216#define PORT_RETRY_TIME 1
1da177e4
LT		 217#define LOOP_DOWN_TIMEOUT 60
218#define LOOP_DOWN_TIME 255 /* 240 */
219#define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
220
221/* Maximum outstanding commands in ISP queues (1-65535) */
222#define MAX_OUTSTANDING_COMMANDS 1024
223
224/* ISP request and response entry counts (37-65535) */
225#define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
226#define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
227#define REQUEST_ENTRY_CNT_2XXX_EXT_MEM 4096 /* Number of request entries. */
3d71644c 228#define REQUEST_ENTRY_CNT_24XX 4096 /* Number of request entries. */
1da177e4
LT		 229#define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
230#define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
231
232/*
fa2a1ce5 233 * SCSI Request Block
1da177e4
LT		 234 */
235typedef struct srb {
236 struct list_head list;
237
238 struct scsi_qla_host *ha; /* HA the SP is queued on */
bdf79621 239 struct fc_port *fcport;
1da177e4
LT		 240
241 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */
242
243 struct timer_list timer; /* Command timer */
fa2a1ce5 244 atomic_t ref_count; /* Reference count for this structure */
1da177e4
LT		 245 uint16_t flags;
246
247 /* Request state */
248 uint16_t state;
249
1da177e4
LT		 250 /* Single transfer DMA context */
251 dma_addr_t dma_handle;
252
253 uint32_t request_sense_length;
254 uint8_t *request_sense_ptr;
255
1da177e4
LT		 256 /* SRB magic number */
257 uint16_t magic;
258#define SRB_MAGIC 0x10CB
259} srb_t;
260
261/*
262 * SRB flag definitions
263 */
264#define SRB_TIMEOUT BIT_0 /* Command timed out */
265#define SRB_DMA_VALID BIT_1 /* Command sent to ISP */
266#define SRB_WATCHDOG BIT_2 /* Command on watchdog list */
267#define SRB_ABORT_PENDING BIT_3 /* Command abort sent to device */
268
269#define SRB_ABORTED BIT_4 /* Command aborted command already */
270#define SRB_RETRY BIT_5 /* Command needs retrying */
271#define SRB_GOT_SENSE BIT_6 /* Command has sense data */
272#define SRB_FAILOVER BIT_7 /* Command in failover state */
273
274#define SRB_BUSY BIT_8 /* Command is in busy retry state */
275#define SRB_FO_CANCEL BIT_9 /* Command don't need to do failover */
276#define SRB_IOCTL BIT_10 /* IOCTL command. */
277#define SRB_TAPE BIT_11 /* FCP2 (Tape) command. */
278
279/*
280 * SRB state definitions
281 */
282#define SRB_FREE_STATE 0 /* returned back */
283#define SRB_PENDING_STATE 1 /* queued in LUN Q */
284#define SRB_ACTIVE_STATE 2 /* in Active Array */
285#define SRB_DONE_STATE 3 /* queued in Done Queue */
286#define SRB_RETRY_STATE 4 /* in Retry Queue */
287#define SRB_SUSPENDED_STATE 5 /* in suspended state */
288#define SRB_NO_QUEUE_STATE 6 /* is in between states */
289#define SRB_ACTIVE_TIMEOUT_STATE 7 /* in Active Array but timed out */
290#define SRB_FAILOVER_STATE 8 /* in Failover Queue */
291#define SRB_SCSI_RETRY_STATE 9 /* in Scsi Retry Queue */
292
293
294/*
295 * ISP I/O Register Set structure definitions.
296 */
3d71644c
AV		 297struct device_reg_2xxx {
298 uint16_t flash_address; /* Flash BIOS address */
299 uint16_t flash_data; /* Flash BIOS data */
1da177e4 300 uint16_t unused_1[1]; /* Gap */
3d71644c 301 uint16_t ctrl_status; /* Control/Status */
fa2a1ce5 302#define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
1da177e4
LT		 303#define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
304#define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
305
3d71644c 306 uint16_t ictrl; /* Interrupt control */
1da177e4
LT		 307#define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
308#define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
309
3d71644c 310 uint16_t istatus; /* Interrupt status */
1da177e4
LT		 311#define ISR_RISC_INT BIT_3 /* RISC interrupt */
312
3d71644c
AV		 313 uint16_t semaphore; /* Semaphore */
314 uint16_t nvram; /* NVRAM register. */
1da177e4
LT		 315#define NVR_DESELECT 0
316#define NVR_BUSY BIT_15
317#define NVR_WRT_ENABLE BIT_14 /* Write enable */
318#define NVR_PR_ENABLE BIT_13 /* Protection register enable */
319#define NVR_DATA_IN BIT_3
320#define NVR_DATA_OUT BIT_2
321#define NVR_SELECT BIT_1
322#define NVR_CLOCK BIT_0
323
324 union {
325 struct {
3d71644c
AV		 326 uint16_t mailbox0;
327 uint16_t mailbox1;
328 uint16_t mailbox2;
329 uint16_t mailbox3;
330 uint16_t mailbox4;
331 uint16_t mailbox5;
332 uint16_t mailbox6;
333 uint16_t mailbox7;
334 uint16_t unused_2[59]; /* Gap */
1da177e4
LT		 335 } __attribute__((packed)) isp2100;
336 struct {
3d71644c
AV		 337 /* Request Queue */
338 uint16_t req_q_in; /* In-Pointer */
339 uint16_t req_q_out; /* Out-Pointer */
340 /* Response Queue */
341 uint16_t rsp_q_in; /* In-Pointer */
342 uint16_t rsp_q_out; /* Out-Pointer */
1da177e4
LT		 343
344 /* RISC to Host Status */
fa2a1ce5 345 uint32_t host_status;
1da177e4
LT		 346#define HSR_RISC_INT BIT_15 /* RISC interrupt */
347#define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
348
349 /* Host to Host Semaphore */
fa2a1ce5 350 uint16_t host_semaphore;
3d71644c
AV		 351 uint16_t unused_3[17]; /* Gap */
352 uint16_t mailbox0;
353 uint16_t mailbox1;
354 uint16_t mailbox2;
355 uint16_t mailbox3;
356 uint16_t mailbox4;
357 uint16_t mailbox5;
358 uint16_t mailbox6;
359 uint16_t mailbox7;
360 uint16_t mailbox8;
361 uint16_t mailbox9;
362 uint16_t mailbox10;
363 uint16_t mailbox11;
364 uint16_t mailbox12;
365 uint16_t mailbox13;
366 uint16_t mailbox14;
367 uint16_t mailbox15;
368 uint16_t mailbox16;
369 uint16_t mailbox17;
370 uint16_t mailbox18;
371 uint16_t mailbox19;
372 uint16_t mailbox20;
373 uint16_t mailbox21;
374 uint16_t mailbox22;
375 uint16_t mailbox23;
376 uint16_t mailbox24;
377 uint16_t mailbox25;
378 uint16_t mailbox26;
379 uint16_t mailbox27;
380 uint16_t mailbox28;
381 uint16_t mailbox29;
382 uint16_t mailbox30;
383 uint16_t mailbox31;
384 uint16_t fb_cmd;
385 uint16_t unused_4[10]; /* Gap */
1da177e4
LT		 386 } __attribute__((packed)) isp2300;
387 } u;
388
3d71644c 389 uint16_t fpm_diag_config;
1da177e4 390 uint16_t unused_5[0x6]; /* Gap */
3d71644c 391 uint16_t pcr; /* Processor Control Register. */
1da177e4 392 uint16_t unused_6[0x5]; /* Gap */
3d71644c 393 uint16_t mctr; /* Memory Configuration and Timing. */
1da177e4 394 uint16_t unused_7[0x3]; /* Gap */
3d71644c 395 uint16_t fb_cmd_2100; /* Unused on 23XX */
1da177e4 396 uint16_t unused_8[0x3]; /* Gap */
3d71644c 397 uint16_t hccr; /* Host command & control register. */
1da177e4
LT		 398#define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
399#define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
400 /* HCCR commands */
401#define HCCR_RESET_RISC 0x1000 /* Reset RISC */
402#define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
403#define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
404#define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
405#define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
406#define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
407#define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
408#define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
409
410 uint16_t unused_9[5]; /* Gap */
3d71644c
AV		 411 uint16_t gpiod; /* GPIO Data register. */
412 uint16_t gpioe; /* GPIO Enable register. */
1da177e4
LT		 413#define GPIO_LED_MASK 0x00C0
414#define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
415#define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
416#define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
417#define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
418
419 union {
420 struct {
3d71644c
AV		 421 uint16_t unused_10[8]; /* Gap */
422 uint16_t mailbox8;
423 uint16_t mailbox9;
424 uint16_t mailbox10;
425 uint16_t mailbox11;
426 uint16_t mailbox12;
427 uint16_t mailbox13;
428 uint16_t mailbox14;
429 uint16_t mailbox15;
430 uint16_t mailbox16;
431 uint16_t mailbox17;
432 uint16_t mailbox18;
433 uint16_t mailbox19;
434 uint16_t mailbox20;
435 uint16_t mailbox21;
436 uint16_t mailbox22;
437 uint16_t mailbox23; /* Also probe reg. */
1da177e4
LT		 438 } __attribute__((packed)) isp2200;
439 } u_end;
3d71644c
AV		 440};
441
9a168bdd 442typedef union {
3d71644c
AV		 443 struct device_reg_2xxx isp;
444 struct device_reg_24xx isp24;
1da177e4
LT		 445} device_reg_t;
446
447#define ISP_REQ_Q_IN(ha, reg) \
448 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
449 &(reg)->u.isp2100.mailbox4 : \
450 &(reg)->u.isp2300.req_q_in)
451#define ISP_REQ_Q_OUT(ha, reg) \
452 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
453 &(reg)->u.isp2100.mailbox4 : \
454 &(reg)->u.isp2300.req_q_out)
455#define ISP_RSP_Q_IN(ha, reg) \
456 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
457 &(reg)->u.isp2100.mailbox5 : \
458 &(reg)->u.isp2300.rsp_q_in)
459#define ISP_RSP_Q_OUT(ha, reg) \
460 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
461 &(reg)->u.isp2100.mailbox5 : \
462 &(reg)->u.isp2300.rsp_q_out)
463
464#define MAILBOX_REG(ha, reg, num) \
465 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
466 (num < 8 ? \
467 &(reg)->u.isp2100.mailbox0 + (num) : \
468 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
469 &(reg)->u.isp2300.mailbox0 + (num))
470#define RD_MAILBOX_REG(ha, reg, num) \
471 RD_REG_WORD(MAILBOX_REG(ha, reg, num))
472#define WRT_MAILBOX_REG(ha, reg, num, data) \
473 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
474
475#define FB_CMD_REG(ha, reg) \
476 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
477 &(reg)->fb_cmd_2100 : \
478 &(reg)->u.isp2300.fb_cmd)
479#define RD_FB_CMD_REG(ha, reg) \
480 RD_REG_WORD(FB_CMD_REG(ha, reg))
481#define WRT_FB_CMD_REG(ha, reg, data) \
482 WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
483
484typedef struct {
485 uint32_t out_mb; /* outbound from driver */
486 uint32_t in_mb; /* Incoming from RISC */
487 uint16_t mb[MAILBOX_REGISTER_COUNT];
488 long buf_size;
489 void *bufp;
490 uint32_t tov;
491 uint8_t flags;
492#define MBX_DMA_IN BIT_0
493#define MBX_DMA_OUT BIT_1
494#define IOCTL_CMD BIT_2
495} mbx_cmd_t;
496
497#define MBX_TOV_SECONDS 30
498
499/*
500 * ISP product identification definitions in mailboxes after reset.
501 */
502#define PROD_ID_1 0x4953
503#define PROD_ID_2 0x0000
504#define PROD_ID_2a 0x5020
505#define PROD_ID_3 0x2020
506
507/*
508 * ISP mailbox Self-Test status codes
509 */
510#define MBS_FRM_ALIVE 0 /* Firmware Alive. */
511#define MBS_CHKSUM_ERR 1 /* Checksum Error. */
512#define MBS_BUSY 4 /* Busy. */
513
514/*
515 * ISP mailbox command complete status codes
516 */
517#define MBS_COMMAND_COMPLETE 0x4000
518#define MBS_INVALID_COMMAND 0x4001
519#define MBS_HOST_INTERFACE_ERROR 0x4002
520#define MBS_TEST_FAILED 0x4003
521#define MBS_COMMAND_ERROR 0x4005
522#define MBS_COMMAND_PARAMETER_ERROR 0x4006
523#define MBS_PORT_ID_USED 0x4007
524#define MBS_LOOP_ID_USED 0x4008
525#define MBS_ALL_IDS_IN_USE 0x4009
526#define MBS_NOT_LOGGED_IN 0x400A
3d71644c
AV		 527#define MBS_LINK_DOWN_ERROR 0x400B
528#define MBS_DIAG_ECHO_TEST_ERROR 0x400C
1da177e4
LT		 529
530/*
531 * ISP mailbox asynchronous event status codes
532 */
533#define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
534#define MBA_RESET 0x8001 /* Reset Detected. */
535#define MBA_SYSTEM_ERR 0x8002 /* System Error. */
536#define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
537#define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
538#define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
539#define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
540 /* occurred. */
541#define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
542#define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
543#define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
544#define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
545#define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
546#define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
547#define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
548#define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
549#define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
550#define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
551#define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
552#define MBA_IP_RECEIVE 0x8023 /* IP Received. */
553#define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
554#define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
555#define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
556#define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
557 /* used. */
558#define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
559#define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
560#define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
561#define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
562#define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
563#define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
564#define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
565#define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
566#define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
567#define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
568#define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
569#define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
570#define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
571
572/*
573 * Firmware options 1, 2, 3.
574 */
575#define FO1_AE_ON_LIPF8 BIT_0
576#define FO1_AE_ALL_LIP_RESET BIT_1
577#define FO1_CTIO_RETRY BIT_3
578#define FO1_DISABLE_LIP_F7_SW BIT_4
579#define FO1_DISABLE_100MS_LOS_WAIT BIT_5
3d71644c 580#define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */
1da177e4
LT		 581#define FO1_AE_ON_LOOP_INIT_ERR BIT_7
582#define FO1_SET_EMPHASIS_SWING BIT_8
583#define FO1_AE_AUTO_BYPASS BIT_9
584#define FO1_ENABLE_PURE_IOCB BIT_10
585#define FO1_AE_PLOGI_RJT BIT_11
586#define FO1_ENABLE_ABORT_SEQUENCE BIT_12
587#define FO1_AE_QUEUE_FULL BIT_13
588
589#define FO2_ENABLE_ATIO_TYPE_3 BIT_0
590#define FO2_REV_LOOPBACK BIT_1
591
592#define FO3_ENABLE_EMERG_IOCB BIT_0
593#define FO3_AE_RND_ERROR BIT_1
594
3d71644c
AV		 595/* 24XX additional firmware options */
596#define ADD_FO_COUNT 3
597#define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */
598#define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
599
600#define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
601
602#define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
603
1da177e4
LT		 604/*
605 * ISP mailbox commands
606 */
607#define MBC_LOAD_RAM 1 /* Load RAM. */
608#define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
609#define MBC_WRITE_RAM_WORD 4 /* Write RAM word. */
610#define MBC_READ_RAM_WORD 5 /* Read RAM word. */
611#define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
612#define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
613#define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
614#define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
615#define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
616#define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
617#define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
618#define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
619#define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
620#define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
f6ef3b18 621#define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */
1da177e4
LT		 622#define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
623#define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
624#define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
625#define MBC_RESET 0x18 /* Reset. */
626#define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
627#define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
628#define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
629#define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
630#define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
631#define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
632#define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
633#define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
634#define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
635#define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
636#define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
637#define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
638#define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
639#define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
640#define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
641#define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
642#define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
643#define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
644#define MBC_GET_RNID_PARAMS 0x5a /* Data Rate */
645#define MBC_DATA_RATE 0x5d /* Get RNID parameters */
646#define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
647#define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
648 /* Initialization Procedure */
649#define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
650#define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
651#define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
652#define MBC_TARGET_RESET 0x66 /* Target Reset. */
653#define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
654#define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
655#define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
656#define MBC_GET_PORT_NAME 0x6a /* Get port name. */
657#define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
658#define MBC_LIP_RESET 0x6c /* LIP reset. */
659#define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
660 /* commandd. */
661#define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
662#define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
663#define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
664#define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
665#define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
666#define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
667#define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
668#define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
669#define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
670#define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
671#define MBC_LUN_RESET 0x7E /* Send LUN reset */
672
3d71644c
AV		 673/*
674 * ISP24xx mailbox commands
675 */
676#define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */
677#define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */
678#define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */
679#define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */
680#define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */
681#define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */
682#define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */
683#define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */
684#define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */
685#define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */
686#define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */
687#define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */
688
1da177e4
LT		 689/* Firmware return data sizes */
690#define FCAL_MAP_SIZE 128
691
692/* Mailbox bit definitions for out_mb and in_mb */
693#define MBX_31 BIT_31
694#define MBX_30 BIT_30
695#define MBX_29 BIT_29
696#define MBX_28 BIT_28
697#define MBX_27 BIT_27
698#define MBX_26 BIT_26
699#define MBX_25 BIT_25
700#define MBX_24 BIT_24
701#define MBX_23 BIT_23
702#define MBX_22 BIT_22
703#define MBX_21 BIT_21
704#define MBX_20 BIT_20
705#define MBX_19 BIT_19
706#define MBX_18 BIT_18
707#define MBX_17 BIT_17
708#define MBX_16 BIT_16
709#define MBX_15 BIT_15
710#define MBX_14 BIT_14
711#define MBX_13 BIT_13
712#define MBX_12 BIT_12
713#define MBX_11 BIT_11
714#define MBX_10 BIT_10
715#define MBX_9 BIT_9
716#define MBX_8 BIT_8
717#define MBX_7 BIT_7
718#define MBX_6 BIT_6
719#define MBX_5 BIT_5
720#define MBX_4 BIT_4
721#define MBX_3 BIT_3
722#define MBX_2 BIT_2
723#define MBX_1 BIT_1
724#define MBX_0 BIT_0
725
726/*
727 * Firmware state codes from get firmware state mailbox command
728 */
729#define FSTATE_CONFIG_WAIT 0
730#define FSTATE_WAIT_AL_PA 1
731#define FSTATE_WAIT_LOGIN 2
732#define FSTATE_READY 3
733#define FSTATE_LOSS_OF_SYNC 4
734#define FSTATE_ERROR 5
735#define FSTATE_REINIT 6
736#define FSTATE_NON_PART 7
737
738#define FSTATE_CONFIG_CORRECT 0
739#define FSTATE_P2P_RCV_LIP 1
740#define FSTATE_P2P_CHOOSE_LOOP 2
741#define FSTATE_P2P_RCV_UNIDEN_LIP 3
742#define FSTATE_FATAL_ERROR 4
743#define FSTATE_LOOP_BACK_CONN 5
744
745/*
746 * Port Database structure definition
747 * Little endian except where noted.
748 */
749#define PORT_DATABASE_SIZE 128 /* bytes */
750typedef struct {
751 uint8_t options;
752 uint8_t control;
753 uint8_t master_state;
754 uint8_t slave_state;
755 uint8_t reserved[2];
756 uint8_t hard_address;
757 uint8_t reserved_1;
758 uint8_t port_id[4];
759 uint8_t node_name[WWN_SIZE];
760 uint8_t port_name[WWN_SIZE];
761 uint16_t execution_throttle;
762 uint16_t execution_count;
763 uint8_t reset_count;
764 uint8_t reserved_2;
765 uint16_t resource_allocation;
766 uint16_t current_allocation;
767 uint16_t queue_head;
768 uint16_t queue_tail;
769 uint16_t transmit_execution_list_next;
770 uint16_t transmit_execution_list_previous;
771 uint16_t common_features;
772 uint16_t total_concurrent_sequences;
773 uint16_t RO_by_information_category;
774 uint8_t recipient;
775 uint8_t initiator;
776 uint16_t receive_data_size;
777 uint16_t concurrent_sequences;
778 uint16_t open_sequences_per_exchange;
779 uint16_t lun_abort_flags;
780 uint16_t lun_stop_flags;
781 uint16_t stop_queue_head;
782 uint16_t stop_queue_tail;
783 uint16_t port_retry_timer;
784 uint16_t next_sequence_id;
785 uint16_t frame_count;
786 uint16_t PRLI_payload_length;
787 uint8_t prli_svc_param_word_0[2]; /* Big endian */
788 /* Bits 15-0 of word 0 */
789 uint8_t prli_svc_param_word_3[2]; /* Big endian */
790 /* Bits 15-0 of word 3 */
791 uint16_t loop_id;
792 uint16_t extended_lun_info_list_pointer;
793 uint16_t extended_lun_stop_list_pointer;
794} port_database_t;
795
796/*
797 * Port database slave/master states
798 */
799#define PD_STATE_DISCOVERY 0
800#define PD_STATE_WAIT_DISCOVERY_ACK 1
801#define PD_STATE_PORT_LOGIN 2
802#define PD_STATE_WAIT_PORT_LOGIN_ACK 3
803#define PD_STATE_PROCESS_LOGIN 4
804#define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
805#define PD_STATE_PORT_LOGGED_IN 6
806#define PD_STATE_PORT_UNAVAILABLE 7
807#define PD_STATE_PROCESS_LOGOUT 8
808#define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
809#define PD_STATE_PORT_LOGOUT 10
810#define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
811
812
4fdfefe5
AV		 813#define QLA_ZIO_MODE_5 (BIT_2 | BIT_0)
814#define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
815#define QLA_ZIO_DISABLED 0
816#define QLA_ZIO_DEFAULT_TIMER 2
817
1da177e4
LT		 818/*
819 * ISP Initialization Control Block.
820 * Little endian except where noted.
821 */
822#define ICB_VERSION 1
823typedef struct {
824 uint8_t version;
825 uint8_t reserved_1;
826
827 /*
828 * LSB BIT 0 = Enable Hard Loop Id
829 * LSB BIT 1 = Enable Fairness
830 * LSB BIT 2 = Enable Full-Duplex
831 * LSB BIT 3 = Enable Fast Posting
832 * LSB BIT 4 = Enable Target Mode
833 * LSB BIT 5 = Disable Initiator Mode
834 * LSB BIT 6 = Enable ADISC
835 * LSB BIT 7 = Enable Target Inquiry Data
836 *
837 * MSB BIT 0 = Enable PDBC Notify
838 * MSB BIT 1 = Non Participating LIP
839 * MSB BIT 2 = Descending Loop ID Search
840 * MSB BIT 3 = Acquire Loop ID in LIPA
841 * MSB BIT 4 = Stop PortQ on Full Status
842 * MSB BIT 5 = Full Login after LIP
843 * MSB BIT 6 = Node Name Option
844 * MSB BIT 7 = Ext IFWCB enable bit
845 */
846 uint8_t firmware_options[2];
847
848 uint16_t frame_payload_size;
849 uint16_t max_iocb_allocation;
850 uint16_t execution_throttle;
851 uint8_t retry_count;
852 uint8_t retry_delay; /* unused */
853 uint8_t port_name[WWN_SIZE]; /* Big endian. */
854 uint16_t hard_address;
855 uint8_t inquiry_data;
856 uint8_t login_timeout;
857 uint8_t node_name[WWN_SIZE]; /* Big endian. */
858
859 uint16_t request_q_outpointer;
860 uint16_t response_q_inpointer;
861 uint16_t request_q_length;
862 uint16_t response_q_length;
863 uint32_t request_q_address[2];
864 uint32_t response_q_address[2];
865
866 uint16_t lun_enables;
867 uint8_t command_resource_count;
868 uint8_t immediate_notify_resource_count;
869 uint16_t timeout;
870 uint8_t reserved_2[2];
871
872 /*
873 * LSB BIT 0 = Timer Operation mode bit 0
874 * LSB BIT 1 = Timer Operation mode bit 1
875 * LSB BIT 2 = Timer Operation mode bit 2
876 * LSB BIT 3 = Timer Operation mode bit 3
877 * LSB BIT 4 = Init Config Mode bit 0
878 * LSB BIT 5 = Init Config Mode bit 1
879 * LSB BIT 6 = Init Config Mode bit 2
880 * LSB BIT 7 = Enable Non part on LIHA failure
881 *
882 * MSB BIT 0 = Enable class 2
883 * MSB BIT 1 = Enable ACK0
884 * MSB BIT 2 =
885 * MSB BIT 3 =
886 * MSB BIT 4 = FC Tape Enable
887 * MSB BIT 5 = Enable FC Confirm
888 * MSB BIT 6 = Enable command queuing in target mode
889 * MSB BIT 7 = No Logo On Link Down
890 */
891 uint8_t add_firmware_options[2];
892
893 uint8_t response_accumulation_timer;
894 uint8_t interrupt_delay_timer;
895
896 /*
897 * LSB BIT 0 = Enable Read xfr_rdy
898 * LSB BIT 1 = Soft ID only
899 * LSB BIT 2 =
900 * LSB BIT 3 =
901 * LSB BIT 4 = FCP RSP Payload [0]
902 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
903 * LSB BIT 6 = Enable Out-of-Order frame handling
904 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
905 *
906 * MSB BIT 0 = Sbus enable - 2300
907 * MSB BIT 1 =
908 * MSB BIT 2 =
909 * MSB BIT 3 =
06c22bd1 910 * MSB BIT 4 = LED mode
1da177e4
LT		 911 * MSB BIT 5 = enable 50 ohm termination
912 * MSB BIT 6 = Data Rate (2300 only)
913 * MSB BIT 7 = Data Rate (2300 only)
914 */
915 uint8_t special_options[2];
916
917 uint8_t reserved_3[26];
918} init_cb_t;
919
920/*
921 * Get Link Status mailbox command return buffer.
922 */
3d71644c
AV		 923#define GLSO_SEND_RPS BIT_0
924#define GLSO_USE_DID BIT_3
925
1da177e4
LT		 926typedef struct {
927 uint32_t link_fail_cnt;
928 uint32_t loss_sync_cnt;
929 uint32_t loss_sig_cnt;
930 uint32_t prim_seq_err_cnt;
931 uint32_t inval_xmit_word_cnt;
932 uint32_t inval_crc_cnt;
933} link_stat_t;
934
935/*
936 * NVRAM Command values.
937 */
938#define NV_START_BIT BIT_2
939#define NV_WRITE_OP (BIT_26+BIT_24)
940#define NV_READ_OP (BIT_26+BIT_25)
941#define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
942#define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
943#define NV_DELAY_COUNT 10
944
945/*
946 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
947 */
948typedef struct {
949 /*
950 * NVRAM header
951 */
952 uint8_t id[4];
953 uint8_t nvram_version;
954 uint8_t reserved_0;
955
956 /*
957 * NVRAM RISC parameter block
958 */
959 uint8_t parameter_block_version;
960 uint8_t reserved_1;
961
962 /*
963 * LSB BIT 0 = Enable Hard Loop Id
964 * LSB BIT 1 = Enable Fairness
965 * LSB BIT 2 = Enable Full-Duplex
966 * LSB BIT 3 = Enable Fast Posting
967 * LSB BIT 4 = Enable Target Mode
968 * LSB BIT 5 = Disable Initiator Mode
969 * LSB BIT 6 = Enable ADISC
970 * LSB BIT 7 = Enable Target Inquiry Data
971 *
972 * MSB BIT 0 = Enable PDBC Notify
973 * MSB BIT 1 = Non Participating LIP
974 * MSB BIT 2 = Descending Loop ID Search
975 * MSB BIT 3 = Acquire Loop ID in LIPA
976 * MSB BIT 4 = Stop PortQ on Full Status
977 * MSB BIT 5 = Full Login after LIP
978 * MSB BIT 6 = Node Name Option
979 * MSB BIT 7 = Ext IFWCB enable bit
980 */
981 uint8_t firmware_options[2];
982
983 uint16_t frame_payload_size;
984 uint16_t max_iocb_allocation;
985 uint16_t execution_throttle;
986 uint8_t retry_count;
987 uint8_t retry_delay; /* unused */
988 uint8_t port_name[WWN_SIZE]; /* Big endian. */
989 uint16_t hard_address;
990 uint8_t inquiry_data;
991 uint8_t login_timeout;
992 uint8_t node_name[WWN_SIZE]; /* Big endian. */
993
994 /*
995 * LSB BIT 0 = Timer Operation mode bit 0
996 * LSB BIT 1 = Timer Operation mode bit 1
997 * LSB BIT 2 = Timer Operation mode bit 2
998 * LSB BIT 3 = Timer Operation mode bit 3
999 * LSB BIT 4 = Init Config Mode bit 0
1000 * LSB BIT 5 = Init Config Mode bit 1
1001 * LSB BIT 6 = Init Config Mode bit 2
1002 * LSB BIT 7 = Enable Non part on LIHA failure
1003 *
1004 * MSB BIT 0 = Enable class 2
1005 * MSB BIT 1 = Enable ACK0
1006 * MSB BIT 2 =
1007 * MSB BIT 3 =
1008 * MSB BIT 4 = FC Tape Enable
1009 * MSB BIT 5 = Enable FC Confirm
1010 * MSB BIT 6 = Enable command queuing in target mode
1011 * MSB BIT 7 = No Logo On Link Down
1012 */
1013 uint8_t add_firmware_options[2];
1014
1015 uint8_t response_accumulation_timer;
1016 uint8_t interrupt_delay_timer;
1017
1018 /*
1019 * LSB BIT 0 = Enable Read xfr_rdy
1020 * LSB BIT 1 = Soft ID only
1021 * LSB BIT 2 =
1022 * LSB BIT 3 =
1023 * LSB BIT 4 = FCP RSP Payload [0]
1024 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1025 * LSB BIT 6 = Enable Out-of-Order frame handling
1026 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1027 *
1028 * MSB BIT 0 = Sbus enable - 2300
1029 * MSB BIT 1 =
1030 * MSB BIT 2 =
1031 * MSB BIT 3 =
06c22bd1 1032 * MSB BIT 4 = LED mode
1da177e4
LT		 1033 * MSB BIT 5 = enable 50 ohm termination
1034 * MSB BIT 6 = Data Rate (2300 only)
1035 * MSB BIT 7 = Data Rate (2300 only)
1036 */
1037 uint8_t special_options[2];
1038
1039 /* Reserved for expanded RISC parameter block */
1040 uint8_t reserved_2[22];
1041
1042 /*
1043 * LSB BIT 0 = Tx Sensitivity 1G bit 0
1044 * LSB BIT 1 = Tx Sensitivity 1G bit 1
1045 * LSB BIT 2 = Tx Sensitivity 1G bit 2
1046 * LSB BIT 3 = Tx Sensitivity 1G bit 3
1047 * LSB BIT 4 = Rx Sensitivity 1G bit 0
1048 * LSB BIT 5 = Rx Sensitivity 1G bit 1
1049 * LSB BIT 6 = Rx Sensitivity 1G bit 2
1050 * LSB BIT 7 = Rx Sensitivity 1G bit 3
fa2a1ce5 1051 *
1da177e4
LT		 1052 * MSB BIT 0 = Tx Sensitivity 2G bit 0
1053 * MSB BIT 1 = Tx Sensitivity 2G bit 1
1054 * MSB BIT 2 = Tx Sensitivity 2G bit 2
1055 * MSB BIT 3 = Tx Sensitivity 2G bit 3
1056 * MSB BIT 4 = Rx Sensitivity 2G bit 0
1057 * MSB BIT 5 = Rx Sensitivity 2G bit 1
1058 * MSB BIT 6 = Rx Sensitivity 2G bit 2
1059 * MSB BIT 7 = Rx Sensitivity 2G bit 3
1060 *
1061 * LSB BIT 0 = Output Swing 1G bit 0
1062 * LSB BIT 1 = Output Swing 1G bit 1
1063 * LSB BIT 2 = Output Swing 1G bit 2
1064 * LSB BIT 3 = Output Emphasis 1G bit 0
1065 * LSB BIT 4 = Output Emphasis 1G bit 1
1066 * LSB BIT 5 = Output Swing 2G bit 0
1067 * LSB BIT 6 = Output Swing 2G bit 1
1068 * LSB BIT 7 = Output Swing 2G bit 2
fa2a1ce5 1069 *
1da177e4
LT		 1070 * MSB BIT 0 = Output Emphasis 2G bit 0
1071 * MSB BIT 1 = Output Emphasis 2G bit 1
1072 * MSB BIT 2 = Output Enable
1073 * MSB BIT 3 =
1074 * MSB BIT 4 =
1075 * MSB BIT 5 =
1076 * MSB BIT 6 =
1077 * MSB BIT 7 =
1078 */
1079 uint8_t seriallink_options[4];
1080
1081 /*
1082 * NVRAM host parameter block
1083 *
1084 * LSB BIT 0 = Enable spinup delay
1085 * LSB BIT 1 = Disable BIOS
1086 * LSB BIT 2 = Enable Memory Map BIOS
1087 * LSB BIT 3 = Enable Selectable Boot
1088 * LSB BIT 4 = Disable RISC code load
1089 * LSB BIT 5 = Set cache line size 1
1090 * LSB BIT 6 = PCI Parity Disable
1091 * LSB BIT 7 = Enable extended logging
1092 *
1093 * MSB BIT 0 = Enable 64bit addressing
1094 * MSB BIT 1 = Enable lip reset
1095 * MSB BIT 2 = Enable lip full login
1096 * MSB BIT 3 = Enable target reset
1097 * MSB BIT 4 = Enable database storage
1098 * MSB BIT 5 = Enable cache flush read
1099 * MSB BIT 6 = Enable database load
1100 * MSB BIT 7 = Enable alternate WWN
1101 */
1102 uint8_t host_p[2];
1103
1104 uint8_t boot_node_name[WWN_SIZE];
1105 uint8_t boot_lun_number;
1106 uint8_t reset_delay;
1107 uint8_t port_down_retry_count;
1108 uint8_t boot_id_number;
1109 uint16_t max_luns_per_target;
1110 uint8_t fcode_boot_port_name[WWN_SIZE];
1111 uint8_t alternate_port_name[WWN_SIZE];
1112 uint8_t alternate_node_name[WWN_SIZE];
1113
1114 /*
1115 * BIT 0 = Selective Login
1116 * BIT 1 = Alt-Boot Enable
1117 * BIT 2 =
1118 * BIT 3 = Boot Order List
1119 * BIT 4 =
1120 * BIT 5 = Selective LUN
1121 * BIT 6 =
1122 * BIT 7 = unused
1123 */
1124 uint8_t efi_parameters;
1125
1126 uint8_t link_down_timeout;
1127
cca5335c 1128 uint8_t adapter_id[16];
1da177e4
LT		 1129
1130 uint8_t alt1_boot_node_name[WWN_SIZE];
1131 uint16_t alt1_boot_lun_number;
1132 uint8_t alt2_boot_node_name[WWN_SIZE];
1133 uint16_t alt2_boot_lun_number;
1134 uint8_t alt3_boot_node_name[WWN_SIZE];
1135 uint16_t alt3_boot_lun_number;
1136 uint8_t alt4_boot_node_name[WWN_SIZE];
1137 uint16_t alt4_boot_lun_number;
1138 uint8_t alt5_boot_node_name[WWN_SIZE];
1139 uint16_t alt5_boot_lun_number;
1140 uint8_t alt6_boot_node_name[WWN_SIZE];
1141 uint16_t alt6_boot_lun_number;
1142 uint8_t alt7_boot_node_name[WWN_SIZE];
1143 uint16_t alt7_boot_lun_number;
1144
1145 uint8_t reserved_3[2];
1146
1147 /* Offset 200-215 : Model Number */
1148 uint8_t model_number[16];
1149
1150 /* OEM related items */
1151 uint8_t oem_specific[16];
1152
1153 /*
1154 * NVRAM Adapter Features offset 232-239
1155 *
1156 * LSB BIT 0 = External GBIC
1157 * LSB BIT 1 = Risc RAM parity
1158 * LSB BIT 2 = Buffer Plus Module
1159 * LSB BIT 3 = Multi Chip Adapter
1160 * LSB BIT 4 = Internal connector
1161 * LSB BIT 5 =
1162 * LSB BIT 6 =
1163 * LSB BIT 7 =
1164 *
1165 * MSB BIT 0 =
1166 * MSB BIT 1 =
1167 * MSB BIT 2 =
1168 * MSB BIT 3 =
1169 * MSB BIT 4 =
1170 * MSB BIT 5 =
1171 * MSB BIT 6 =
1172 * MSB BIT 7 =
1173 */
1174 uint8_t adapter_features[2];
1175
1176 uint8_t reserved_4[16];
1177
1178 /* Subsystem vendor ID for ISP2200 */
1179 uint16_t subsystem_vendor_id_2200;
1180
1181 /* Subsystem device ID for ISP2200 */
1182 uint16_t subsystem_device_id_2200;
1183
1184 uint8_t reserved_5;
1185 uint8_t checksum;
1186} nvram_t;
1187
1188/*
1189 * ISP queue - response queue entry definition.
1190 */
1191typedef struct {
1192 uint8_t data[60];
1193 uint32_t signature;
1194#define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
1195} response_t;
1196
1197typedef union {
1198 uint16_t extended;
1199 struct {
1200 uint8_t reserved;
1201 uint8_t standard;
1202 } id;
1203} target_id_t;
1204
1205#define SET_TARGET_ID(ha, to, from) \
1206do { \
1207 if (HAS_EXTENDED_IDS(ha)) \
1208 to.extended = cpu_to_le16(from); \
1209 else \
1210 to.id.standard = (uint8_t)from; \
1211} while (0)
1212
1213/*
1214 * ISP queue - command entry structure definition.
1215 */
1216#define COMMAND_TYPE 0x11 /* Command entry */
1da177e4
LT		 1217typedef struct {
1218 uint8_t entry_type; /* Entry type. */
1219 uint8_t entry_count; /* Entry count. */
1220 uint8_t sys_define; /* System defined. */
1221 uint8_t entry_status; /* Entry Status. */
1222 uint32_t handle; /* System handle. */
1223 target_id_t target; /* SCSI ID */
1224 uint16_t lun; /* SCSI LUN */
1225 uint16_t control_flags; /* Control flags. */
1226#define CF_WRITE BIT_6
1227#define CF_READ BIT_5
1228#define CF_SIMPLE_TAG BIT_3
1229#define CF_ORDERED_TAG BIT_2
1230#define CF_HEAD_TAG BIT_1
1231 uint16_t reserved_1;
1232 uint16_t timeout; /* Command timeout. */
1233 uint16_t dseg_count; /* Data segment count. */
1234 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1235 uint32_t byte_count; /* Total byte count. */
1236 uint32_t dseg_0_address; /* Data segment 0 address. */
1237 uint32_t dseg_0_length; /* Data segment 0 length. */
1238 uint32_t dseg_1_address; /* Data segment 1 address. */
1239 uint32_t dseg_1_length; /* Data segment 1 length. */
1240 uint32_t dseg_2_address; /* Data segment 2 address. */
1241 uint32_t dseg_2_length; /* Data segment 2 length. */
1242} cmd_entry_t;
1243
1244/*
1245 * ISP queue - 64-Bit addressing, command entry structure definition.
1246 */
1247#define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
1248typedef struct {
1249 uint8_t entry_type; /* Entry type. */
1250 uint8_t entry_count; /* Entry count. */
1251 uint8_t sys_define; /* System defined. */
1252 uint8_t entry_status; /* Entry Status. */
1253 uint32_t handle; /* System handle. */
1254 target_id_t target; /* SCSI ID */
1255 uint16_t lun; /* SCSI LUN */
1256 uint16_t control_flags; /* Control flags. */
1257 uint16_t reserved_1;
1258 uint16_t timeout; /* Command timeout. */
1259 uint16_t dseg_count; /* Data segment count. */
1260 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1261 uint32_t byte_count; /* Total byte count. */
1262 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1263 uint32_t dseg_0_length; /* Data segment 0 length. */
1264 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1265 uint32_t dseg_1_length; /* Data segment 1 length. */
1266} cmd_a64_entry_t, request_t;
1267
1268/*
1269 * ISP queue - continuation entry structure definition.
1270 */
1271#define CONTINUE_TYPE 0x02 /* Continuation entry. */
1272typedef struct {
1273 uint8_t entry_type; /* Entry type. */
1274 uint8_t entry_count; /* Entry count. */
1275 uint8_t sys_define; /* System defined. */
1276 uint8_t entry_status; /* Entry Status. */
1277 uint32_t reserved;
1278 uint32_t dseg_0_address; /* Data segment 0 address. */
1279 uint32_t dseg_0_length; /* Data segment 0 length. */
1280 uint32_t dseg_1_address; /* Data segment 1 address. */
1281 uint32_t dseg_1_length; /* Data segment 1 length. */
1282 uint32_t dseg_2_address; /* Data segment 2 address. */
1283 uint32_t dseg_2_length; /* Data segment 2 length. */
1284 uint32_t dseg_3_address; /* Data segment 3 address. */
1285 uint32_t dseg_3_length; /* Data segment 3 length. */
1286 uint32_t dseg_4_address; /* Data segment 4 address. */
1287 uint32_t dseg_4_length; /* Data segment 4 length. */
1288 uint32_t dseg_5_address; /* Data segment 5 address. */
1289 uint32_t dseg_5_length; /* Data segment 5 length. */
1290 uint32_t dseg_6_address; /* Data segment 6 address. */
1291 uint32_t dseg_6_length; /* Data segment 6 length. */
1292} cont_entry_t;
1293
1294/*
1295 * ISP queue - 64-Bit addressing, continuation entry structure definition.
1296 */
1297#define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
1298typedef struct {
1299 uint8_t entry_type; /* Entry type. */
1300 uint8_t entry_count; /* Entry count. */
1301 uint8_t sys_define; /* System defined. */
1302 uint8_t entry_status; /* Entry Status. */
1303 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1304 uint32_t dseg_0_length; /* Data segment 0 length. */
1305 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1306 uint32_t dseg_1_length; /* Data segment 1 length. */
1307 uint32_t dseg_2_address [2]; /* Data segment 2 address. */
1308 uint32_t dseg_2_length; /* Data segment 2 length. */
1309 uint32_t dseg_3_address[2]; /* Data segment 3 address. */
1310 uint32_t dseg_3_length; /* Data segment 3 length. */
1311 uint32_t dseg_4_address[2]; /* Data segment 4 address. */
1312 uint32_t dseg_4_length; /* Data segment 4 length. */
1313} cont_a64_entry_t;
1314
1315/*
1316 * ISP queue - status entry structure definition.
1317 */
1318#define STATUS_TYPE 0x03 /* Status entry. */
1319typedef struct {
1320 uint8_t entry_type; /* Entry type. */
1321 uint8_t entry_count; /* Entry count. */
1322 uint8_t sys_define; /* System defined. */
1323 uint8_t entry_status; /* Entry Status. */
1324 uint32_t handle; /* System handle. */
1325 uint16_t scsi_status; /* SCSI status. */
1326 uint16_t comp_status; /* Completion status. */
1327 uint16_t state_flags; /* State flags. */
1328 uint16_t status_flags; /* Status flags. */
1329 uint16_t rsp_info_len; /* Response Info Length. */
1330 uint16_t req_sense_length; /* Request sense data length. */
1331 uint32_t residual_length; /* Residual transfer length. */
1332 uint8_t rsp_info[8]; /* FCP response information. */
1333 uint8_t req_sense_data[32]; /* Request sense data. */
1334} sts_entry_t;
1335
1336/*
1337 * Status entry entry status
1338 */
3d71644c 1339#define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */
1da177e4
LT		 1340#define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
1341#define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
1342#define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
1343#define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
1344#define RF_BUSY BIT_1 /* Busy */
3d71644c
AV		 1345#define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
1346 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
1347#define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
1348 RF_INV_E_TYPE)
1da177e4
LT		 1349
1350/*
1351 * Status entry SCSI status bit definitions.
1352 */
1353#define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
1354#define SS_RESIDUAL_UNDER BIT_11
1355#define SS_RESIDUAL_OVER BIT_10
1356#define SS_SENSE_LEN_VALID BIT_9
1357#define SS_RESPONSE_INFO_LEN_VALID BIT_8
1358
1359#define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
1360#define SS_BUSY_CONDITION BIT_3
1361#define SS_CONDITION_MET BIT_2
1362#define SS_CHECK_CONDITION BIT_1
1363
1364/*
1365 * Status entry completion status
1366 */
1367#define CS_COMPLETE 0x0 /* No errors */
1368#define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
1369#define CS_DMA 0x2 /* A DMA direction error. */
1370#define CS_TRANSPORT 0x3 /* Transport error. */
1371#define CS_RESET 0x4 /* SCSI bus reset occurred */
1372#define CS_ABORTED 0x5 /* System aborted command. */
1373#define CS_TIMEOUT 0x6 /* Timeout error. */
1374#define CS_DATA_OVERRUN 0x7 /* Data overrun. */
1375
1376#define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
1377#define CS_QUEUE_FULL 0x1C /* Queue Full. */
1378#define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
1379 /* (selection timeout) */
1380#define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
1381#define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
1382#define CS_PORT_BUSY 0x2B /* Port Busy */
1383#define CS_COMPLETE_CHKCOND 0x30 /* Error? */
1384#define CS_BAD_PAYLOAD 0x80 /* Driver defined */
1385#define CS_UNKNOWN 0x81 /* Driver defined */
1386#define CS_RETRY 0x82 /* Driver defined */
1387#define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
1388
1389/*
1390 * Status entry status flags
1391 */
1392#define SF_ABTS_TERMINATED BIT_10
1393#define SF_LOGOUT_SENT BIT_13
1394
1395/*
1396 * ISP queue - status continuation entry structure definition.
1397 */
1398#define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
1399typedef struct {
1400 uint8_t entry_type; /* Entry type. */
1401 uint8_t entry_count; /* Entry count. */
1402 uint8_t sys_define; /* System defined. */
1403 uint8_t entry_status; /* Entry Status. */
1404 uint8_t data[60]; /* data */
1405} sts_cont_entry_t;
1406
1407/*
1408 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
1409 * structure definition.
1410 */
1411#define STATUS_TYPE_21 0x21 /* Status entry. */
1412typedef struct {
1413 uint8_t entry_type; /* Entry type. */
1414 uint8_t entry_count; /* Entry count. */
1415 uint8_t handle_count; /* Handle count. */
1416 uint8_t entry_status; /* Entry Status. */
1417 uint32_t handle[15]; /* System handles. */
1418} sts21_entry_t;
1419
1420/*
1421 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
1422 * structure definition.
1423 */
1424#define STATUS_TYPE_22 0x22 /* Status entry. */
1425typedef struct {
1426 uint8_t entry_type; /* Entry type. */
1427 uint8_t entry_count; /* Entry count. */
1428 uint8_t handle_count; /* Handle count. */
1429 uint8_t entry_status; /* Entry Status. */
1430 uint16_t handle[30]; /* System handles. */
1431} sts22_entry_t;
1432
1433/*
1434 * ISP queue - marker entry structure definition.
1435 */
1436#define MARKER_TYPE 0x04 /* Marker entry. */
1437typedef struct {
1438 uint8_t entry_type; /* Entry type. */
1439 uint8_t entry_count; /* Entry count. */
1440 uint8_t handle_count; /* Handle count. */
1441 uint8_t entry_status; /* Entry Status. */
1442 uint32_t sys_define_2; /* System defined. */
1443 target_id_t target; /* SCSI ID */
1444 uint8_t modifier; /* Modifier (7-0). */
1445#define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
1446#define MK_SYNC_ID 1 /* Synchronize ID */
1447#define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
1448#define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
1449 /* clear port changed, */
1450 /* use sequence number. */
1451 uint8_t reserved_1;
1452 uint16_t sequence_number; /* Sequence number of event */
1453 uint16_t lun; /* SCSI LUN */
1454 uint8_t reserved_2[48];
1455} mrk_entry_t;
1456
1457/*
1458 * ISP queue - Management Server entry structure definition.
1459 */
1460#define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
1461typedef struct {
1462 uint8_t entry_type; /* Entry type. */
1463 uint8_t entry_count; /* Entry count. */
1464 uint8_t handle_count; /* Handle count. */
1465 uint8_t entry_status; /* Entry Status. */
1466 uint32_t handle1; /* System handle. */
1467 target_id_t loop_id;
1468 uint16_t status;
1469 uint16_t control_flags; /* Control flags. */
1470 uint16_t reserved2;
1471 uint16_t timeout;
1472 uint16_t cmd_dsd_count;
1473 uint16_t total_dsd_count;
1474 uint8_t type;
1475 uint8_t r_ctl;
1476 uint16_t rx_id;
1477 uint16_t reserved3;
1478 uint32_t handle2;
1479 uint32_t rsp_bytecount;
1480 uint32_t req_bytecount;
1481 uint32_t dseg_req_address[2]; /* Data segment 0 address. */
1482 uint32_t dseg_req_length; /* Data segment 0 length. */
1483 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */
1484 uint32_t dseg_rsp_length; /* Data segment 1 length. */
1485} ms_iocb_entry_t;
1486
1487
1488/*
1489 * ISP queue - Mailbox Command entry structure definition.
1490 */
1491#define MBX_IOCB_TYPE 0x39
1492struct mbx_entry {
1493 uint8_t entry_type;
1494 uint8_t entry_count;
1495 uint8_t sys_define1;
1496 /* Use sys_define1 for source type */
1497#define SOURCE_SCSI 0x00
1498#define SOURCE_IP 0x01
1499#define SOURCE_VI 0x02
1500#define SOURCE_SCTP 0x03
1501#define SOURCE_MP 0x04
1502#define SOURCE_MPIOCTL 0x05
1503#define SOURCE_ASYNC_IOCB 0x07
1504
1505 uint8_t entry_status;
1506
1507 uint32_t handle;
1508 target_id_t loop_id;
1509
1510 uint16_t status;
1511 uint16_t state_flags;
1512 uint16_t status_flags;
1513
1514 uint32_t sys_define2[2];
1515
1516 uint16_t mb0;
1517 uint16_t mb1;
1518 uint16_t mb2;
1519 uint16_t mb3;
1520 uint16_t mb6;
1521 uint16_t mb7;
1522 uint16_t mb9;
1523 uint16_t mb10;
1524 uint32_t reserved_2[2];
1525 uint8_t node_name[WWN_SIZE];
1526 uint8_t port_name[WWN_SIZE];
1527};
1528
1529/*
1530 * ISP request and response queue entry sizes
1531 */
1532#define RESPONSE_ENTRY_SIZE (sizeof(response_t))
1533#define REQUEST_ENTRY_SIZE (sizeof(request_t))
1534
1535
1536/*
1537 * 24 bit port ID type definition.
1538 */
1539typedef union {
1540 uint32_t b24 : 24;
1541
1542 struct {
1543 uint8_t d_id[3];
1544 uint8_t rsvd_1;
1545 } r;
1546
1547 struct {
1548 uint8_t al_pa;
1549 uint8_t area;
1550 uint8_t domain;
1551 uint8_t rsvd_1;
1552 } b;
1553} port_id_t;
1554#define INVALID_PORT_ID 0xFFFFFF
1555
1556/*
1557 * Switch info gathering structure.
1558 */
1559typedef struct {
1560 port_id_t d_id;
1561 uint8_t node_name[WWN_SIZE];
1562 uint8_t port_name[WWN_SIZE];
1da177e4
LT		 1563} sw_info_t;
1564
1565/*
1566 * Inquiry command structure.
1567 */
1568#define INQ_DATA_SIZE 36
1569
1570/*
1571 * Inquiry mailbox IOCB packet definition.
1572 */
1573typedef struct {
1574 union {
1575 cmd_a64_entry_t cmd;
1576 sts_entry_t rsp;
3d71644c
AV		 1577 struct cmd_type_7 cmd24;
1578 struct sts_entry_24xx rsp24;
1da177e4
LT		 1579 } p;
1580 uint8_t inq[INQ_DATA_SIZE];
1581} inq_cmd_rsp_t;
1582
1583/*
1584 * Report LUN command structure.
1585 */
1586#define CHAR_TO_SHORT(a, b) (uint16_t)((uint8_t)b << 8 | (uint8_t)a)
1587
1588typedef struct {
1589 uint32_t len;
1590 uint32_t rsrv;
1591} rpt_hdr_t;
1592
1593typedef struct {
1594 struct {
1595 uint8_t b : 6;
1596 uint8_t address_method : 2;
1597 } msb;
1598 uint8_t lsb;
1599 uint8_t unused[6];
1600} rpt_lun_t;
1601
1602typedef struct {
1603 rpt_hdr_t hdr;
1604 rpt_lun_t lst[MAX_LUNS];
1605} rpt_lun_lst_t;
1606
1607/*
1608 * Report Lun mailbox IOCB packet definition.
1609 */
1610typedef struct {
1611 union {
1612 cmd_a64_entry_t cmd;
1613 sts_entry_t rsp;
3d71644c
AV		 1614 struct cmd_type_7 cmd24;
1615 struct sts_entry_24xx rsp24;
1da177e4
LT		 1616 } p;
1617 rpt_lun_lst_t list;
1618} rpt_lun_cmd_rsp_t;
1619
3d71644c 1620
1da177e4
LT		 1621/*
1622 * Fibre channel port type.
1623 */
1624 typedef enum {
1625 FCT_UNKNOWN,
1626 FCT_RSCN,
1627 FCT_SWITCH,
1628 FCT_BROADCAST,
1629 FCT_INITIATOR,
1630 FCT_TARGET
1631} fc_port_type_t;
1632
1633/*
1634 * Fibre channel port structure.
1635 */
1636typedef struct fc_port {
1637 struct list_head list;
1da177e4
LT		 1638 struct scsi_qla_host *ha;
1639 struct scsi_qla_host *vis_ha; /* only used when suspending lun */
1640
1641 uint8_t node_name[WWN_SIZE];
1642 uint8_t port_name[WWN_SIZE];
1643 port_id_t d_id;
1644 uint16_t loop_id;
1645 uint16_t old_loop_id;
1646
1647 fc_port_type_t port_type;
1648
1649 atomic_t state;
1650 uint32_t flags;
1651
bdf79621 1652 unsigned int os_target_id;
1da177e4
LT		 1653
1654 uint16_t iodesc_idx_sent;
1655
1656 int port_login_retry_count;
1657 int login_retry;
1658 atomic_t port_down_timer;
1659
1660 uint8_t device_type;
1661 uint8_t unused;
1662
1663 uint8_t mp_byte; /* multi-path byte (not used) */
1664 uint8_t cur_path; /* current path id */
1665
8482e118 1666 struct fc_rport *rport;
ad3e0eda 1667 u32 supported_classes;
1da177e4
LT		 1668} fc_port_t;
1669
1670/*
1671 * Fibre channel port/lun states.
1672 */
1673#define FCS_UNCONFIGURED 1
1674#define FCS_DEVICE_DEAD 2
1675#define FCS_DEVICE_LOST 3
1676#define FCS_ONLINE 4
1677#define FCS_NOT_SUPPORTED 5
1678#define FCS_FAILOVER 6
1679#define FCS_FAILOVER_FAILED 7
1680
1681/*
1682 * FC port flags.
1683 */
1684#define FCF_FABRIC_DEVICE BIT_0
1685#define FCF_LOGIN_NEEDED BIT_1
1686#define FCF_FO_MASKED BIT_2
1687#define FCF_FAILOVER_NEEDED BIT_3
1688#define FCF_RESET_NEEDED BIT_4
1689#define FCF_PERSISTENT_BOUND BIT_5
1690#define FCF_TAPE_PRESENT BIT_6
1691#define FCF_FARP_DONE BIT_7
1692#define FCF_FARP_FAILED BIT_8
1693#define FCF_FARP_REPLY_NEEDED BIT_9
1694#define FCF_AUTH_REQ BIT_10
1695#define FCF_SEND_AUTH_REQ BIT_11
1696#define FCF_RECEIVE_AUTH_REQ BIT_12
1697#define FCF_AUTH_SUCCESS BIT_13
1698#define FCF_RLC_SUPPORT BIT_14
1699#define FCF_CONFIG BIT_15 /* Needed? */
1700#define FCF_RESCAN_NEEDED BIT_16
1701#define FCF_XP_DEVICE BIT_17
1702#define FCF_MSA_DEVICE BIT_18
1703#define FCF_EVA_DEVICE BIT_19
1704#define FCF_MSA_PORT_ACTIVE BIT_20
1705#define FCF_FAILBACK_DISABLE BIT_21
1706#define FCF_FAILOVER_DISABLE BIT_22
1707#define FCF_DSXXX_DEVICE BIT_23
1708#define FCF_AA_EVA_DEVICE BIT_24
3d71644c 1709#define FCF_AA_MSA_DEVICE BIT_25
1da177e4
LT		 1710
1711/* No loop ID flag. */
1712#define FC_NO_LOOP_ID 0x1000
1713
1da177e4
LT		 1714/*
1715 * FC-CT interface
1716 *
1717 * NOTE: All structures are big-endian in form.
1718 */
1719
1720#define CT_REJECT_RESPONSE 0x8001
1721#define CT_ACCEPT_RESPONSE 0x8002
cca5335c
AV		 1722#define CT_REASON_CANNOT_PERFORM 0x09
1723#define CT_EXPL_ALREADY_REGISTERED 0x10
1da177e4
LT		 1724
1725#define NS_N_PORT_TYPE 0x01
1726#define NS_NL_PORT_TYPE 0x02
1727#define NS_NX_PORT_TYPE 0x7F
1728
1729#define GA_NXT_CMD 0x100
1730#define GA_NXT_REQ_SIZE (16 + 4)
1731#define GA_NXT_RSP_SIZE (16 + 620)
1732
1733#define GID_PT_CMD 0x1A1
1734#define GID_PT_REQ_SIZE (16 + 4)
1735#define GID_PT_RSP_SIZE (16 + (MAX_FIBRE_DEVICES * 4))
1736
1737#define GPN_ID_CMD 0x112
1738#define GPN_ID_REQ_SIZE (16 + 4)
1739#define GPN_ID_RSP_SIZE (16 + 8)
1740
1741#define GNN_ID_CMD 0x113
1742#define GNN_ID_REQ_SIZE (16 + 4)
1743#define GNN_ID_RSP_SIZE (16 + 8)
1744
1745#define GFT_ID_CMD 0x117
1746#define GFT_ID_REQ_SIZE (16 + 4)
1747#define GFT_ID_RSP_SIZE (16 + 32)
1748
1749#define RFT_ID_CMD 0x217
1750#define RFT_ID_REQ_SIZE (16 + 4 + 32)
1751#define RFT_ID_RSP_SIZE 16
1752
1753#define RFF_ID_CMD 0x21F
1754#define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
1755#define RFF_ID_RSP_SIZE 16
1756
1757#define RNN_ID_CMD 0x213
1758#define RNN_ID_REQ_SIZE (16 + 4 + 8)
1759#define RNN_ID_RSP_SIZE 16
1760
1761#define RSNN_NN_CMD 0x239
1762#define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
1763#define RSNN_NN_RSP_SIZE 16
1764
cca5335c
AV		 1765/*
1766 * HBA attribute types.
1767 */
1768#define FDMI_HBA_ATTR_COUNT 9
1769#define FDMI_HBA_NODE_NAME 1
1770#define FDMI_HBA_MANUFACTURER 2
1771#define FDMI_HBA_SERIAL_NUMBER 3
1772#define FDMI_HBA_MODEL 4
1773#define FDMI_HBA_MODEL_DESCRIPTION 5
1774#define FDMI_HBA_HARDWARE_VERSION 6
1775#define FDMI_HBA_DRIVER_VERSION 7
1776#define FDMI_HBA_OPTION_ROM_VERSION 8
1777#define FDMI_HBA_FIRMWARE_VERSION 9
1778#define FDMI_HBA_OS_NAME_AND_VERSION 0xa
1779#define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
1780
1781struct ct_fdmi_hba_attr {
1782 uint16_t type;
1783 uint16_t len;
1784 union {
1785 uint8_t node_name[WWN_SIZE];
1786 uint8_t manufacturer[32];
1787 uint8_t serial_num[8];
1788 uint8_t model[16];
1789 uint8_t model_desc[80];
1790 uint8_t hw_version[16];
1791 uint8_t driver_version[32];
1792 uint8_t orom_version[16];
1793 uint8_t fw_version[16];
1794 uint8_t os_version[128];
1795 uint8_t max_ct_len[4];
1796 } a;
1797};
1798
1799struct ct_fdmi_hba_attributes {
1800 uint32_t count;
1801 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT];
1802};
1803
1804/*
1805 * Port attribute types.
1806 */
1807#define FDMI_PORT_ATTR_COUNT 5
1808#define FDMI_PORT_FC4_TYPES 1
1809#define FDMI_PORT_SUPPORT_SPEED 2
1810#define FDMI_PORT_CURRENT_SPEED 3
1811#define FDMI_PORT_MAX_FRAME_SIZE 4
1812#define FDMI_PORT_OS_DEVICE_NAME 5
1813#define FDMI_PORT_HOST_NAME 6
1814
1815struct ct_fdmi_port_attr {
1816 uint16_t type;
1817 uint16_t len;
1818 union {
1819 uint8_t fc4_types[32];
1820 uint32_t sup_speed;
1821 uint32_t cur_speed;
1822 uint32_t max_frame_size;
1823 uint8_t os_dev_name[32];
1824 uint8_t host_name[32];
1825 } a;
1826};
1827
1828/*
1829 * Port Attribute Block.
1830 */
1831struct ct_fdmi_port_attributes {
1832 uint32_t count;
1833 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT];
1834};
1835
1836/* FDMI definitions. */
1837#define GRHL_CMD 0x100
1838#define GHAT_CMD 0x101
1839#define GRPL_CMD 0x102
1840#define GPAT_CMD 0x110
1841
1842#define RHBA_CMD 0x200
1843#define RHBA_RSP_SIZE 16
1844
1845#define RHAT_CMD 0x201
1846#define RPRT_CMD 0x210
1847
1848#define RPA_CMD 0x211
1849#define RPA_RSP_SIZE 16
1850
1851#define DHBA_CMD 0x300
1852#define DHBA_REQ_SIZE (16 + 8)
1853#define DHBA_RSP_SIZE 16
1854
1855#define DHAT_CMD 0x301
1856#define DPRT_CMD 0x310
1857#define DPA_CMD 0x311
1858
1da177e4
LT		 1859/* CT command header -- request/response common fields */
1860struct ct_cmd_hdr {
1861 uint8_t revision;
1862 uint8_t in_id[3];
1863 uint8_t gs_type;
1864 uint8_t gs_subtype;
1865 uint8_t options;
1866 uint8_t reserved;
1867};
1868
1869/* CT command request */
1870struct ct_sns_req {
1871 struct ct_cmd_hdr header;
1872 uint16_t command;
1873 uint16_t max_rsp_size;
1874 uint8_t fragment_id;
1875 uint8_t reserved[3];
1876
1877 union {
1878 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID */
1879 struct {
1880 uint8_t reserved;
1881 uint8_t port_id[3];
1882 } port_id;
1883
1884 struct {
1885 uint8_t port_type;
1886 uint8_t domain;
1887 uint8_t area;
1888 uint8_t reserved;
1889 } gid_pt;
1890
1891 struct {
1892 uint8_t reserved;
1893 uint8_t port_id[3];
1894 uint8_t fc4_types[32];
1895 } rft_id;
1896
1897 struct {
1898 uint8_t reserved;
1899 uint8_t port_id[3];
1900 uint16_t reserved2;
1901 uint8_t fc4_feature;
1902 uint8_t fc4_type;
1903 } rff_id;
1904
1905 struct {
1906 uint8_t reserved;
1907 uint8_t port_id[3];
1908 uint8_t node_name[8];
1909 } rnn_id;
1910
1911 struct {
1912 uint8_t node_name[8];
1913 uint8_t name_len;
1914 uint8_t sym_node_name[255];
1915 } rsnn_nn;
cca5335c
AV		 1916
1917 struct {
1918 uint8_t hba_indentifier[8];
1919 } ghat;
1920
1921 struct {
1922 uint8_t hba_identifier[8];
1923 uint32_t entry_count;
1924 uint8_t port_name[8];
1925 struct ct_fdmi_hba_attributes attrs;
1926 } rhba;
1927
1928 struct {
1929 uint8_t hba_identifier[8];
1930 struct ct_fdmi_hba_attributes attrs;
1931 } rhat;
1932
1933 struct {
1934 uint8_t port_name[8];
1935 struct ct_fdmi_port_attributes attrs;
1936 } rpa;
1937
1938 struct {
1939 uint8_t port_name[8];
1940 } dhba;
1941
1942 struct {
1943 uint8_t port_name[8];
1944 } dhat;
1945
1946 struct {
1947 uint8_t port_name[8];
1948 } dprt;
1949
1950 struct {
1951 uint8_t port_name[8];
1952 } dpa;
1da177e4
LT		 1953 } req;
1954};
1955
1956/* CT command response header */
1957struct ct_rsp_hdr {
1958 struct ct_cmd_hdr header;
1959 uint16_t response;
1960 uint16_t residual;
1961 uint8_t fragment_id;
1962 uint8_t reason_code;
1963 uint8_t explanation_code;
1964 uint8_t vendor_unique;
1965};
1966
1967struct ct_sns_gid_pt_data {
1968 uint8_t control_byte;
1969 uint8_t port_id[3];
1970};
1971
1972struct ct_sns_rsp {
1973 struct ct_rsp_hdr header;
1974
1975 union {
1976 struct {
1977 uint8_t port_type;
1978 uint8_t port_id[3];
1979 uint8_t port_name[8];
1980 uint8_t sym_port_name_len;
1981 uint8_t sym_port_name[255];
1982 uint8_t node_name[8];
1983 uint8_t sym_node_name_len;
1984 uint8_t sym_node_name[255];
1985 uint8_t init_proc_assoc[8];
1986 uint8_t node_ip_addr[16];
1987 uint8_t class_of_service[4];
1988 uint8_t fc4_types[32];
1989 uint8_t ip_address[16];
1990 uint8_t fabric_port_name[8];
1991 uint8_t reserved;
1992 uint8_t hard_address[3];
1993 } ga_nxt;
1994
1995 struct {
1996 struct ct_sns_gid_pt_data entries[MAX_FIBRE_DEVICES];
1997 } gid_pt;
1998
1999 struct {
2000 uint8_t port_name[8];
2001 } gpn_id;
2002
2003 struct {
2004 uint8_t node_name[8];
2005 } gnn_id;
2006
2007 struct {
2008 uint8_t fc4_types[32];
2009 } gft_id;
cca5335c
AV		 2010
2011 struct {
2012 uint32_t entry_count;
2013 uint8_t port_name[8];
2014 struct ct_fdmi_hba_attributes attrs;
2015 } ghat;
1da177e4
LT		 2016 } rsp;
2017};
2018
2019struct ct_sns_pkt {
2020 union {
2021 struct ct_sns_req req;
2022 struct ct_sns_rsp rsp;
2023 } p;
2024};
2025
2026/*
2027 * SNS command structures -- for 2200 compatability.
2028 */
2029#define RFT_ID_SNS_SCMD_LEN 22
2030#define RFT_ID_SNS_CMD_SIZE 60
2031#define RFT_ID_SNS_DATA_SIZE 16
2032
2033#define RNN_ID_SNS_SCMD_LEN 10
2034#define RNN_ID_SNS_CMD_SIZE 36
2035#define RNN_ID_SNS_DATA_SIZE 16
2036
2037#define GA_NXT_SNS_SCMD_LEN 6
2038#define GA_NXT_SNS_CMD_SIZE 28
2039#define GA_NXT_SNS_DATA_SIZE (620 + 16)
2040
2041#define GID_PT_SNS_SCMD_LEN 6
2042#define GID_PT_SNS_CMD_SIZE 28
2043#define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES * 4 + 16)
2044
2045#define GPN_ID_SNS_SCMD_LEN 6
2046#define GPN_ID_SNS_CMD_SIZE 28
2047#define GPN_ID_SNS_DATA_SIZE (8 + 16)
2048
2049#define GNN_ID_SNS_SCMD_LEN 6
2050#define GNN_ID_SNS_CMD_SIZE 28
2051#define GNN_ID_SNS_DATA_SIZE (8 + 16)
2052
2053struct sns_cmd_pkt {
2054 union {
2055 struct {
2056 uint16_t buffer_length;
2057 uint16_t reserved_1;
2058 uint32_t buffer_address[2];
2059 uint16_t subcommand_length;
2060 uint16_t reserved_2;
2061 uint16_t subcommand;
2062 uint16_t size;
2063 uint32_t reserved_3;
2064 uint8_t param[36];
2065 } cmd;
2066
2067 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
2068 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
2069 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
2070 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
2071 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
2072 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
2073 } p;
2074};
2075
2076/* IO descriptors */
2077#define MAX_IO_DESCRIPTORS 32
2078
2079#define ABORT_IOCB_CB 0
2080#define ADISC_PORT_IOCB_CB 1
2081#define LOGOUT_PORT_IOCB_CB 2
2082#define LOGIN_PORT_IOCB_CB 3
2083#define LAST_IOCB_CB 4
2084
2085#define IODESC_INVALID_INDEX 0xFFFF
2086#define IODESC_ADISC_NEEDED 0xFFFE
2087#define IODESC_LOGIN_NEEDED 0xFFFD
2088
2089struct io_descriptor {
2090 uint16_t used:1;
2091 uint16_t idx:11;
2092 uint16_t cb_idx:4;
2093
2094 struct timer_list timer;
2095
2096 struct scsi_qla_host *ha;
2097
2098 port_id_t d_id;
2099 fc_port_t *remote_fcport;
2100
2101 uint32_t signature;
2102};
2103
2104struct qla_fw_info {
2105 unsigned short addressing; /* addressing method used to load fw */
2106#define FW_INFO_ADDR_NORMAL 0
2107#define FW_INFO_ADDR_EXTENDED 1
2108#define FW_INFO_ADDR_NOMORE 0xffff
2109 unsigned short *fwcode; /* pointer to FW array */
2110 unsigned short *fwlen; /* number of words in array */
2111 unsigned short *fwstart; /* start address for F/W */
2112 unsigned long *lfwstart; /* start address (long) for F/W */
2113};
2114
2115struct qla_board_info {
2116 char *drv_name;
2117
2118 char isp_name[8];
2119 struct qla_fw_info *fw_info;
fca29703
AV		 2120 char *fw_fname;
2121 struct scsi_host_template *sht;
1da177e4
LT		 2122};
2123
2124/* Return data from MBC_GET_ID_LIST call. */
2125struct gid_list_info {
2126 uint8_t al_pa;
2127 uint8_t area;
fa2a1ce5 2128 uint8_t domain;
1da177e4
LT		 2129 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
2130 uint16_t loop_id; /* ISP23XX -- 6 bytes. */
3d71644c 2131 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */
1da177e4
LT		 2132};
2133#define GID_LIST_SIZE (sizeof(struct gid_list_info) * MAX_FIBRE_DEVICES)
2134
abbd8870
AV		 2135/*
2136 * ISP operations
2137 */
2138struct isp_operations {
2139
2140 int (*pci_config) (struct scsi_qla_host *);
2141 void (*reset_chip) (struct scsi_qla_host *);
2142 int (*chip_diag) (struct scsi_qla_host *);
2143 void (*config_rings) (struct scsi_qla_host *);
2144 void (*reset_adapter) (struct scsi_qla_host *);
2145 int (*nvram_config) (struct scsi_qla_host *);
2146 void (*update_fw_options) (struct scsi_qla_host *);
2147 int (*load_risc) (struct scsi_qla_host *, uint32_t *);
2148
2149 char * (*pci_info_str) (struct scsi_qla_host *, char *);
2150 char * (*fw_version_str) (struct scsi_qla_host *, char *);
2151
2152 irqreturn_t (*intr_handler) (int, void *, struct pt_regs *);
2153 void (*enable_intrs) (struct scsi_qla_host *);
2154 void (*disable_intrs) (struct scsi_qla_host *);
2155
2156 int (*abort_command) (struct scsi_qla_host *, srb_t *);
2157 int (*abort_target) (struct fc_port *);
2158 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
2159 uint8_t, uint8_t, uint16_t *, uint8_t);
1c7c6357
AV		 2160 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
2161 uint8_t, uint8_t);
abbd8870
AV		 2162
2163 uint16_t (*calc_req_entries) (uint16_t);
2164 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
8c958a99 2165 void * (*prep_ms_iocb) (struct scsi_qla_host *, uint32_t, uint32_t);
cca5335c
AV		 2166 void * (*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
2167 uint32_t);
abbd8870
AV		 2168
2169 uint8_t * (*read_nvram) (struct scsi_qla_host *, uint8_t *,
2170 uint32_t, uint32_t);
2171 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t,
2172 uint32_t);
2173
2174 void (*fw_dump) (struct scsi_qla_host *, int);
2175 void (*ascii_fw_dump) (struct scsi_qla_host *);
2176};
2177
1da177e4
LT		 2178/*
2179 * Linux Host Adapter structure
2180 */
2181typedef struct scsi_qla_host {
2182 struct list_head list;
2183
2184 /* Commonly used flags and state information. */
2185 struct Scsi_Host *host;
2186 struct pci_dev *pdev;
2187
2188 unsigned long host_no;
2189 unsigned long instance;
2190
2191 volatile struct {
2192 uint32_t init_done :1;
2193 uint32_t online :1;
2194 uint32_t mbox_int :1;
2195 uint32_t mbox_busy :1;
2196 uint32_t rscn_queue_overflow :1;
2197 uint32_t reset_active :1;
2198
2199 uint32_t management_server_logged_in :1;
2200 uint32_t process_response_queue :1;
2201
2202 uint32_t disable_risc_code_load :1;
2203 uint32_t enable_64bit_addressing :1;
2204 uint32_t enable_lip_reset :1;
2205 uint32_t enable_lip_full_login :1;
2206 uint32_t enable_target_reset :1;
2207 uint32_t enable_led_scheme :1;
3d71644c
AV		 2208 uint32_t msi_enabled :1;
2209 uint32_t msix_enabled :1;
1da177e4
LT		 2210 } flags;
2211
2212 atomic_t loop_state;
2213#define LOOP_TIMEOUT 1
2214#define LOOP_DOWN 2
2215#define LOOP_UP 3
2216#define LOOP_UPDATE 4
2217#define LOOP_READY 5
2218#define LOOP_DEAD 6
2219
2220 unsigned long dpc_flags;
2221#define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
2222#define RESET_ACTIVE 1
2223#define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
2224#define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
2225#define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
2226#define LOOP_RESYNC_ACTIVE 5
2227#define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
2228#define RSCN_UPDATE 7 /* Perform an RSCN update. */
2229#define MAILBOX_RETRY 8
2230#define ISP_RESET_NEEDED 9 /* Initiate a ISP reset. */
2231#define FAILOVER_EVENT_NEEDED 10
2232#define FAILOVER_EVENT 11
2233#define FAILOVER_NEEDED 12
2234#define SCSI_RESTART_NEEDED 13 /* Processes SCSI retry queue. */
2235#define PORT_RESTART_NEEDED 14 /* Processes Retry queue. */
2236#define RESTART_QUEUES_NEEDED 15 /* Restarts the Lun queue. */
2237#define ABORT_QUEUES_NEEDED 16
2238#define RELOGIN_NEEDED 17
2239#define LOGIN_RETRY_NEEDED 18 /* Initiate required fabric logins. */
2240#define REGISTER_FC4_NEEDED 19 /* SNS FC4 registration required. */
2241#define ISP_ABORT_RETRY 20 /* ISP aborted. */
2242#define FCPORT_RESCAN_NEEDED 21 /* IO descriptor processing needed */
2243#define IODESC_PROCESS_NEEDED 22 /* IO descriptor processing needed */
fa2a1ce5 2244#define IOCTL_ERROR_RECOVERY 23
1da177e4 2245#define LOOP_RESET_NEEDED 24
3d71644c 2246#define BEACON_BLINK_NEEDED 25
cca5335c 2247#define REGISTER_FDMI_NEEDED 26
1da177e4
LT		 2248
2249 uint32_t device_flags;
2250#define DFLG_LOCAL_DEVICES BIT_0
2251#define DFLG_RETRY_LOCAL_DEVICES BIT_1
2252#define DFLG_FABRIC_DEVICES BIT_2
2253#define SWITCH_FOUND BIT_3
2254#define DFLG_NO_CABLE BIT_4
2255
2256 /* SRB cache. */
2257#define SRB_MIN_REQ 128
2258 mempool_t *srb_mempool;
2259
fa2a1ce5 2260 /* This spinlock is used to protect "io transactions", you must
1da177e4
LT		 2261 * aquire it before doing any IO to the card, eg with RD_REG*() and
2262 * WRT_REG*() for the duration of your entire commandtransaction.
2263 *
2264 * This spinlock is of lower priority than the io request lock.
2265 */
2266
2267 spinlock_t hardware_lock ____cacheline_aligned;
2268
2269 device_reg_t __iomem *iobase; /* Base I/O address */
2270 unsigned long pio_address;
2271 unsigned long pio_length;
2272#define MIN_IOBASE_LEN 0x100
2273
2274 /* ISP ring lock, rings, and indexes */
2275 dma_addr_t request_dma; /* Physical address. */
2276 request_t *request_ring; /* Base virtual address */
2277 request_t *request_ring_ptr; /* Current address. */
2278 uint16_t req_ring_index; /* Current index. */
2279 uint16_t req_q_cnt; /* Number of available entries. */
2280 uint16_t request_q_length;
2281
2282 dma_addr_t response_dma; /* Physical address. */
2283 response_t *response_ring; /* Base virtual address */
2284 response_t *response_ring_ptr; /* Current address. */
2285 uint16_t rsp_ring_index; /* Current index. */
2286 uint16_t response_q_length;
fa2a1ce5 2287
abbd8870 2288 struct isp_operations isp_ops;
1da177e4
LT		 2289
2290 /* Outstandings ISP commands. */
2291 srb_t *outstanding_cmds[MAX_OUTSTANDING_COMMANDS];
fa2a1ce5 2292 uint32_t current_outstanding_cmd;
1da177e4
LT		 2293 srb_t *status_srb; /* Status continuation entry. */
2294
1da177e4
LT		 2295 uint16_t revision;
2296 uint8_t ports;
1da177e4
LT		 2297
2298 /* ISP configuration data. */
2299 uint16_t loop_id; /* Host adapter loop id */
2300 uint16_t fb_rev;
2301
2302 port_id_t d_id; /* Host adapter port id */
2303 uint16_t max_public_loop_ids;
2304 uint16_t min_external_loopid; /* First external loop Id */
2305
2306 uint16_t link_data_rate; /* F/W operating speed */
2307
2308 uint8_t current_topology;
2309 uint8_t prev_topology;
2310#define ISP_CFG_NL 1
2311#define ISP_CFG_N 2
2312#define ISP_CFG_FL 4
2313#define ISP_CFG_F 8
2314
2315 uint8_t operating_mode; /* F/W operating mode */
2316#define LOOP 0
2317#define P2P 1
2318#define LOOP_P2P 2
2319#define P2P_LOOP 3
2320
fa2a1ce5 2321 uint8_t marker_needed;
1da177e4
LT		 2322
2323 uint8_t interrupts_on;
2324
2325 /* HBA serial number */
2326 uint8_t serial0;
2327 uint8_t serial1;
2328 uint8_t serial2;
2329
2330 /* NVRAM configuration data */
3d71644c 2331 uint16_t nvram_size;
1da177e4
LT		 2332 uint16_t nvram_base;
2333
2334 uint16_t loop_reset_delay;
1da177e4
LT		 2335 uint8_t retry_count;
2336 uint8_t login_timeout;
2337 uint16_t r_a_tov;
2338 int port_down_retry_count;
1da177e4 2339 uint8_t mbx_count;
1da177e4 2340 uint16_t last_loop_id;
cca5335c 2341 uint16_t mgmt_svr_loop_id;
1da177e4 2342
fa2a1ce5 2343 uint32_t login_retry_count;
1da177e4
LT		 2344
2345 /* Fibre Channel Device List. */
2346 struct list_head fcports;
2347 struct list_head rscn_fcports;
2348
2349 struct io_descriptor io_descriptors[MAX_IO_DESCRIPTORS];
2350 uint16_t iodesc_signature;
2351
1da177e4
LT		 2352 /* RSCN queue. */
2353 uint32_t rscn_queue[MAX_RSCN_COUNT];
2354 uint8_t rscn_in_ptr;
2355 uint8_t rscn_out_ptr;
2356
2357 /* SNS command interfaces. */
2358 ms_iocb_entry_t *ms_iocb;
2359 dma_addr_t ms_iocb_dma;
2360 struct ct_sns_pkt *ct_sns;
2361 dma_addr_t ct_sns_dma;
2362 /* SNS command interfaces for 2200. */
2363 struct sns_cmd_pkt *sns_cmd;
2364 dma_addr_t sns_cmd_dma;
2365
2366 pid_t dpc_pid;
2367 int dpc_should_die;
2368 struct completion dpc_inited;
2369 struct completion dpc_exited;
2370 struct semaphore *dpc_wait;
2371 uint8_t dpc_active; /* DPC routine is active */
2372
2373 /* Timeout timers. */
1da177e4
LT		 2374 uint8_t loop_down_abort_time; /* port down timer */
2375 atomic_t loop_down_timer; /* loop down timer */
2376 uint8_t link_down_timeout; /* link down timeout */
2377
2378 uint32_t timer_active;
2379 struct timer_list timer;
2380
2381 dma_addr_t gid_list_dma;
2382 struct gid_list_info *gid_list;
abbd8870 2383 int gid_list_info_size;
1da177e4
LT		 2384
2385 dma_addr_t rlc_rsp_dma;
2386 rpt_lun_cmd_rsp_t *rlc_rsp;
2387
fa2a1ce5 2388 /* Small DMA pool allocations -- maximum 256 bytes in length. */
1da177e4
LT		 2389#define DMA_POOL_SIZE 256
2390 struct dma_pool *s_dma_pool;
2391
2392 dma_addr_t init_cb_dma;
3d71644c
AV		 2393 init_cb_t *init_cb;
2394 int init_cb_size;
1da177e4
LT		 2395
2396 dma_addr_t iodesc_pd_dma;
2397 port_database_t *iodesc_pd;
2398
2399 /* These are used by mailbox operations. */
2400 volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
2401
2402 mbx_cmd_t *mcp;
2403 unsigned long mbx_cmd_flags;
2404#define MBX_INTERRUPT 1
2405#define MBX_INTR_WAIT 2
2406#define MBX_UPDATE_FLASH_ACTIVE 3
2407
2408 spinlock_t mbx_reg_lock; /* Mbx Cmd Register Lock */
2409
2410 struct semaphore mbx_cmd_sem; /* Serialialize mbx access */
2411 struct semaphore mbx_intr_sem; /* Used for completion notification */
2412
2413 uint32_t mbx_flags;
2414#define MBX_IN_PROGRESS BIT_0
2415#define MBX_BUSY BIT_1 /* Got the Access */
fa2a1ce5 2416#define MBX_SLEEPING_ON_SEM BIT_2
1da177e4
LT		 2417#define MBX_POLLING_FOR_COMP BIT_3
2418#define MBX_COMPLETED BIT_4
fa2a1ce5 2419#define MBX_TIMEDOUT BIT_5
1da177e4
LT		 2420#define MBX_ACCESS_TIMEDOUT BIT_6
2421
2422 mbx_cmd_t mc;
2423
1da177e4
LT		 2424 /* Basic firmware related information. */
2425 struct qla_board_info *brd_info;
2426 uint16_t fw_major_version;
2427 uint16_t fw_minor_version;
2428 uint16_t fw_subminor_version;
2429 uint16_t fw_attributes;
2430 uint32_t fw_memory_size;
2431 uint32_t fw_transfer_size;
2432
2433 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
2434 uint8_t fw_seriallink_options[4];
3d71644c 2435 uint16_t fw_seriallink_options24[4];
1da177e4
LT		 2436
2437 /* Firmware dump information. */
2438 void *fw_dump;
2439 int fw_dump_order;
2440 int fw_dump_reading;
2441 char *fw_dump_buffer;
2442 int fw_dump_buffer_len;
2443
3d71644c
AV		 2444 int fw_dumped;
2445 void *fw_dump24;
2446 int fw_dump24_len;
2447
1da177e4 2448 uint8_t host_str[16];
3d71644c 2449 uint32_t pci_attr;
1da177e4
LT		 2450
2451 uint16_t product_id[4];
2452
2453 uint8_t model_number[16+1];
2454#define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
2455 char *model_desc;
cca5335c 2456 uint8_t adapter_id[16+1];
1da177e4 2457
3d71644c
AV		 2458 uint8_t *node_name;
2459 uint8_t *port_name;
1da177e4
LT		 2460 uint32_t isp_abort_cnt;
2461
1da177e4
LT		 2462 /* Needed for BEACON */
2463 uint16_t beacon_blink_led;
2464 uint16_t beacon_green_on;
4fdfefe5
AV		 2465
2466 uint16_t zio_mode;
2467 uint16_t zio_timer;
1da177e4
LT		 2468} scsi_qla_host_t;
2469
2470
2471/*
2472 * Macros to help code, maintain, etc.
2473 */
2474#define LOOP_TRANSITION(ha) \
2475 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
2476 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags))
2477
2478#define LOOP_NOT_READY(ha) \
2479 ((test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
2480 test_bit(ABORT_ISP_ACTIVE, &ha->dpc_flags) || \
2481 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
2482 test_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) || \
2483 atomic_read(&ha->loop_state) == LOOP_DOWN)
fa2a1ce5 2484
1da177e4
LT		 2485#define LOOP_RDY(ha) (!LOOP_NOT_READY(ha))
2486
2487#define TGT_Q(ha, t) (ha->otgt[t])
1da177e4
LT		 2488
2489#define to_qla_host(x) ((scsi_qla_host_t *) (x)->hostdata)
2490
2491#define qla_printk(level, ha, format, arg...) \
2492 dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
2493
2494/*
2495 * qla2x00 local function return status codes
2496 */
2497#define MBS_MASK 0x3fff
2498
2499#define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
2500#define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
2501#define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
2502#define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
2503#define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
2504#define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
2505#define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
2506#define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
2507#define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
2508#define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
2509
2510#define QLA_FUNCTION_TIMEOUT 0x100
2511#define QLA_FUNCTION_PARAMETER_ERROR 0x101
2512#define QLA_FUNCTION_FAILED 0x102
2513#define QLA_MEMORY_ALLOC_FAILED 0x103
2514#define QLA_LOCK_TIMEOUT 0x104
2515#define QLA_ABORTED 0x105
2516#define QLA_SUSPENDED 0x106
2517#define QLA_BUSY 0x107
2518#define QLA_RSCNS_HANDLED 0x108
cca5335c 2519#define QLA_ALREADY_REGISTERED 0x109
1da177e4
LT		 2520
2521/*
2522* Stat info for all adpaters
2523*/
2524struct _qla2x00stats {
2525 unsigned long mboxtout; /* mailbox timeouts */
2526 unsigned long mboxerr; /* mailbox errors */
2527 unsigned long ispAbort; /* ISP aborts */
2528 unsigned long debugNo;
2529 unsigned long loop_resync;
2530 unsigned long outarray_full;
2531 unsigned long retry_q_cnt;
2532};
2533
2534#define NVRAM_DELAY() udelay(10)
2535
2536#define INVALID_HANDLE (MAX_OUTSTANDING_COMMANDS+1)
2537
2538/*
2539 * Flash support definitions
2540 */
2541#define FLASH_IMAGE_SIZE 131072
2542
2543#include "qla_gbl.h"
2544#include "qla_dbg.h"
2545#include "qla_inline.h"
1da177e4
LT		 2546
2547/*
2548* String arrays
2549*/
2550#define LINESIZE 256
2551#define MAXARGS 26
2552
2553#define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
2554#define CMD_COMPL_STATUS(Cmnd) ((Cmnd)->SCp.this_residual)
2555#define CMD_RESID_LEN(Cmnd) ((Cmnd)->SCp.buffers_residual)
2556#define CMD_SCSI_STATUS(Cmnd) ((Cmnd)->SCp.Status)
2557#define CMD_ACTUAL_SNSLEN(Cmnd) ((Cmnd)->SCp.Message)
2558#define CMD_ENTRY_STATUS(Cmnd) ((Cmnd)->SCp.have_data_in)
2559
2560#endif
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