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[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / qla2xxx / qla_def.h
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fa90c54f
AV
1/*
2 * QLogic Fibre Channel HBA Driver
01e58d8e 3 * Copyright (c) 2003-2008 QLogic Corporation
fa90c54f
AV
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
1da177e4
LT
7#ifndef __QLA_DEF_H
8#define __QLA_DEF_H
9
10#include <linux/kernel.h>
11#include <linux/init.h>
12#include <linux/types.h>
13#include <linux/module.h>
14#include <linux/list.h>
15#include <linux/pci.h>
16#include <linux/dma-mapping.h>
17#include <linux/sched.h>
18#include <linux/slab.h>
19#include <linux/dmapool.h>
20#include <linux/mempool.h>
21#include <linux/spinlock.h>
22#include <linux/completion.h>
abbd8870 23#include <linux/interrupt.h>
19a7b4ae 24#include <linux/workqueue.h>
5433383e 25#include <linux/firmware.h>
14e660e6 26#include <linux/aer.h>
4d4df193 27#include <linux/mutex.h>
1da177e4
LT
28
29#include <scsi/scsi.h>
30#include <scsi/scsi_host.h>
31#include <scsi/scsi_device.h>
32#include <scsi/scsi_cmnd.h>
392e2f65 33#include <scsi/scsi_transport_fc.h>
1da177e4 34
cb63067a
AV
35#define QLA2XXX_DRIVER_NAME "qla2xxx"
36
1da177e4
LT
37/*
38 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
39 * but that's fine as we don't look at the last 24 ones for
40 * ISP2100 HBAs.
41 */
42#define MAILBOX_REGISTER_COUNT_2100 8
43#define MAILBOX_REGISTER_COUNT 32
44
45#define QLA2200A_RISC_ROM_VER 4
46#define FPM_2300 6
47#define FPM_2310 7
48
49#include "qla_settings.h"
50
fa2a1ce5 51/*
1da177e4
LT
52 * Data bit definitions
53 */
54#define BIT_0 0x1
55#define BIT_1 0x2
56#define BIT_2 0x4
57#define BIT_3 0x8
58#define BIT_4 0x10
59#define BIT_5 0x20
60#define BIT_6 0x40
61#define BIT_7 0x80
62#define BIT_8 0x100
63#define BIT_9 0x200
64#define BIT_10 0x400
65#define BIT_11 0x800
66#define BIT_12 0x1000
67#define BIT_13 0x2000
68#define BIT_14 0x4000
69#define BIT_15 0x8000
70#define BIT_16 0x10000
71#define BIT_17 0x20000
72#define BIT_18 0x40000
73#define BIT_19 0x80000
74#define BIT_20 0x100000
75#define BIT_21 0x200000
76#define BIT_22 0x400000
77#define BIT_23 0x800000
78#define BIT_24 0x1000000
79#define BIT_25 0x2000000
80#define BIT_26 0x4000000
81#define BIT_27 0x8000000
82#define BIT_28 0x10000000
83#define BIT_29 0x20000000
84#define BIT_30 0x40000000
85#define BIT_31 0x80000000
86
87#define LSB(x) ((uint8_t)(x))
88#define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
89
90#define LSW(x) ((uint16_t)(x))
91#define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
92
93#define LSD(x) ((uint32_t)((uint64_t)(x)))
94#define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
95
96
97/*
98 * I/O register
99*/
100
101#define RD_REG_BYTE(addr) readb(addr)
102#define RD_REG_WORD(addr) readw(addr)
103#define RD_REG_DWORD(addr) readl(addr)
104#define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
105#define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
106#define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
107#define WRT_REG_BYTE(addr, data) writeb(data,addr)
108#define WRT_REG_WORD(addr, data) writew(data,addr)
109#define WRT_REG_DWORD(addr, data) writel(data,addr)
110
f6df144c
AV
111/*
112 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an
113 * 133Mhz slot.
114 */
115#define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr))
116#define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr))
117
1da177e4
LT
118/*
119 * Fibre Channel device definitions.
120 */
121#define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
122#define MAX_FIBRE_DEVICES 512
cc4731f5 123#define MAX_FIBRE_LUNS 0xFFFF
1da177e4
LT
124#define MAX_RSCN_COUNT 32
125#define MAX_HOST_COUNT 16
126
127/*
128 * Host adapter default definitions.
129 */
130#define MAX_BUSES 1 /* We only have one bus today */
131#define MAX_TARGETS_2100 MAX_FIBRE_DEVICES
132#define MAX_TARGETS_2200 MAX_FIBRE_DEVICES
1da177e4
LT
133#define MIN_LUNS 8
134#define MAX_LUNS MAX_FIBRE_LUNS
fa2a1ce5
AV
135#define MAX_CMDS_PER_LUN 255
136
1da177e4
LT
137/*
138 * Fibre Channel device definitions.
139 */
140#define SNS_LAST_LOOP_ID_2100 0xfe
141#define SNS_LAST_LOOP_ID_2300 0x7ff
142
143#define LAST_LOCAL_LOOP_ID 0x7d
144#define SNS_FL_PORT 0x7e
145#define FABRIC_CONTROLLER 0x7f
146#define SIMPLE_NAME_SERVER 0x80
147#define SNS_FIRST_LOOP_ID 0x81
148#define MANAGEMENT_SERVER 0xfe
149#define BROADCAST 0xff
150
3d71644c
AV
151/*
152 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the
153 * valid range of an N-PORT id is 0 through 0x7ef.
154 */
155#define NPH_LAST_HANDLE 0x7ef
cca5335c 156#define NPH_MGMT_SERVER 0x7fa /* FFFFFA */
3d71644c
AV
157#define NPH_SNS 0x7fc /* FFFFFC */
158#define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */
159#define NPH_F_PORT 0x7fe /* FFFFFE */
160#define NPH_IP_BROADCAST 0x7ff /* FFFFFF */
161
162#define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
163#include "qla_fw.h"
1da177e4
LT
164
165/*
166 * Timeout timer counts in seconds
167 */
8482e118 168#define PORT_RETRY_TIME 1
1da177e4
LT
169#define LOOP_DOWN_TIMEOUT 60
170#define LOOP_DOWN_TIME 255 /* 240 */
171#define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
172
173/* Maximum outstanding commands in ISP queues (1-65535) */
174#define MAX_OUTSTANDING_COMMANDS 1024
175
176/* ISP request and response entry counts (37-65535) */
177#define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
178#define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
179#define REQUEST_ENTRY_CNT_2XXX_EXT_MEM 4096 /* Number of request entries. */
3d71644c 180#define REQUEST_ENTRY_CNT_24XX 4096 /* Number of request entries. */
1da177e4
LT
181#define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
182#define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
183
184/*
fa2a1ce5 185 * SCSI Request Block
1da177e4
LT
186 */
187typedef struct srb {
1da177e4 188 struct scsi_qla_host *ha; /* HA the SP is queued on */
bdf79621 189 struct fc_port *fcport;
1da177e4
LT
190
191 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */
192
1da177e4
LT
193 uint16_t flags;
194
1da177e4
LT
195 uint32_t request_sense_length;
196 uint8_t *request_sense_ptr;
1da177e4
LT
197} srb_t;
198
199/*
200 * SRB flag definitions
201 */
202#define SRB_TIMEOUT BIT_0 /* Command timed out */
203#define SRB_DMA_VALID BIT_1 /* Command sent to ISP */
204#define SRB_WATCHDOG BIT_2 /* Command on watchdog list */
205#define SRB_ABORT_PENDING BIT_3 /* Command abort sent to device */
206
207#define SRB_ABORTED BIT_4 /* Command aborted command already */
208#define SRB_RETRY BIT_5 /* Command needs retrying */
209#define SRB_GOT_SENSE BIT_6 /* Command has sense data */
210#define SRB_FAILOVER BIT_7 /* Command in failover state */
211
212#define SRB_BUSY BIT_8 /* Command is in busy retry state */
213#define SRB_FO_CANCEL BIT_9 /* Command don't need to do failover */
214#define SRB_IOCTL BIT_10 /* IOCTL command. */
215#define SRB_TAPE BIT_11 /* FCP2 (Tape) command. */
216
1da177e4
LT
217/*
218 * ISP I/O Register Set structure definitions.
219 */
3d71644c
AV
220struct device_reg_2xxx {
221 uint16_t flash_address; /* Flash BIOS address */
222 uint16_t flash_data; /* Flash BIOS data */
1da177e4 223 uint16_t unused_1[1]; /* Gap */
3d71644c 224 uint16_t ctrl_status; /* Control/Status */
fa2a1ce5 225#define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
1da177e4
LT
226#define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
227#define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
228
3d71644c 229 uint16_t ictrl; /* Interrupt control */
1da177e4
LT
230#define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
231#define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
232
3d71644c 233 uint16_t istatus; /* Interrupt status */
1da177e4
LT
234#define ISR_RISC_INT BIT_3 /* RISC interrupt */
235
3d71644c
AV
236 uint16_t semaphore; /* Semaphore */
237 uint16_t nvram; /* NVRAM register. */
1da177e4
LT
238#define NVR_DESELECT 0
239#define NVR_BUSY BIT_15
240#define NVR_WRT_ENABLE BIT_14 /* Write enable */
241#define NVR_PR_ENABLE BIT_13 /* Protection register enable */
242#define NVR_DATA_IN BIT_3
243#define NVR_DATA_OUT BIT_2
244#define NVR_SELECT BIT_1
245#define NVR_CLOCK BIT_0
246
45aeaf1e
RA
247#define NVR_WAIT_CNT 20000
248
1da177e4
LT
249 union {
250 struct {
3d71644c
AV
251 uint16_t mailbox0;
252 uint16_t mailbox1;
253 uint16_t mailbox2;
254 uint16_t mailbox3;
255 uint16_t mailbox4;
256 uint16_t mailbox5;
257 uint16_t mailbox6;
258 uint16_t mailbox7;
259 uint16_t unused_2[59]; /* Gap */
1da177e4
LT
260 } __attribute__((packed)) isp2100;
261 struct {
3d71644c
AV
262 /* Request Queue */
263 uint16_t req_q_in; /* In-Pointer */
264 uint16_t req_q_out; /* Out-Pointer */
265 /* Response Queue */
266 uint16_t rsp_q_in; /* In-Pointer */
267 uint16_t rsp_q_out; /* Out-Pointer */
1da177e4
LT
268
269 /* RISC to Host Status */
fa2a1ce5 270 uint32_t host_status;
1da177e4
LT
271#define HSR_RISC_INT BIT_15 /* RISC interrupt */
272#define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
273
274 /* Host to Host Semaphore */
fa2a1ce5 275 uint16_t host_semaphore;
3d71644c
AV
276 uint16_t unused_3[17]; /* Gap */
277 uint16_t mailbox0;
278 uint16_t mailbox1;
279 uint16_t mailbox2;
280 uint16_t mailbox3;
281 uint16_t mailbox4;
282 uint16_t mailbox5;
283 uint16_t mailbox6;
284 uint16_t mailbox7;
285 uint16_t mailbox8;
286 uint16_t mailbox9;
287 uint16_t mailbox10;
288 uint16_t mailbox11;
289 uint16_t mailbox12;
290 uint16_t mailbox13;
291 uint16_t mailbox14;
292 uint16_t mailbox15;
293 uint16_t mailbox16;
294 uint16_t mailbox17;
295 uint16_t mailbox18;
296 uint16_t mailbox19;
297 uint16_t mailbox20;
298 uint16_t mailbox21;
299 uint16_t mailbox22;
300 uint16_t mailbox23;
301 uint16_t mailbox24;
302 uint16_t mailbox25;
303 uint16_t mailbox26;
304 uint16_t mailbox27;
305 uint16_t mailbox28;
306 uint16_t mailbox29;
307 uint16_t mailbox30;
308 uint16_t mailbox31;
309 uint16_t fb_cmd;
310 uint16_t unused_4[10]; /* Gap */
1da177e4
LT
311 } __attribute__((packed)) isp2300;
312 } u;
313
3d71644c 314 uint16_t fpm_diag_config;
c81d04c9
AV
315 uint16_t unused_5[0x4]; /* Gap */
316 uint16_t risc_hw;
317 uint16_t unused_5_1; /* Gap */
3d71644c 318 uint16_t pcr; /* Processor Control Register. */
1da177e4 319 uint16_t unused_6[0x5]; /* Gap */
3d71644c 320 uint16_t mctr; /* Memory Configuration and Timing. */
1da177e4 321 uint16_t unused_7[0x3]; /* Gap */
3d71644c 322 uint16_t fb_cmd_2100; /* Unused on 23XX */
1da177e4 323 uint16_t unused_8[0x3]; /* Gap */
3d71644c 324 uint16_t hccr; /* Host command & control register. */
1da177e4
LT
325#define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
326#define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
327 /* HCCR commands */
328#define HCCR_RESET_RISC 0x1000 /* Reset RISC */
329#define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
330#define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
331#define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
332#define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
333#define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
334#define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
335#define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
336
337 uint16_t unused_9[5]; /* Gap */
3d71644c
AV
338 uint16_t gpiod; /* GPIO Data register. */
339 uint16_t gpioe; /* GPIO Enable register. */
1da177e4
LT
340#define GPIO_LED_MASK 0x00C0
341#define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
342#define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
343#define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
344#define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
f6df144c
AV
345#define GPIO_LED_ALL_OFF 0x0000
346#define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */
347#define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */
1da177e4
LT
348
349 union {
350 struct {
3d71644c
AV
351 uint16_t unused_10[8]; /* Gap */
352 uint16_t mailbox8;
353 uint16_t mailbox9;
354 uint16_t mailbox10;
355 uint16_t mailbox11;
356 uint16_t mailbox12;
357 uint16_t mailbox13;
358 uint16_t mailbox14;
359 uint16_t mailbox15;
360 uint16_t mailbox16;
361 uint16_t mailbox17;
362 uint16_t mailbox18;
363 uint16_t mailbox19;
364 uint16_t mailbox20;
365 uint16_t mailbox21;
366 uint16_t mailbox22;
367 uint16_t mailbox23; /* Also probe reg. */
1da177e4
LT
368 } __attribute__((packed)) isp2200;
369 } u_end;
3d71644c
AV
370};
371
9a168bdd 372typedef union {
3d71644c
AV
373 struct device_reg_2xxx isp;
374 struct device_reg_24xx isp24;
1da177e4
LT
375} device_reg_t;
376
377#define ISP_REQ_Q_IN(ha, reg) \
378 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
379 &(reg)->u.isp2100.mailbox4 : \
380 &(reg)->u.isp2300.req_q_in)
381#define ISP_REQ_Q_OUT(ha, reg) \
382 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
383 &(reg)->u.isp2100.mailbox4 : \
384 &(reg)->u.isp2300.req_q_out)
385#define ISP_RSP_Q_IN(ha, reg) \
386 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
387 &(reg)->u.isp2100.mailbox5 : \
388 &(reg)->u.isp2300.rsp_q_in)
389#define ISP_RSP_Q_OUT(ha, reg) \
390 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
391 &(reg)->u.isp2100.mailbox5 : \
392 &(reg)->u.isp2300.rsp_q_out)
393
394#define MAILBOX_REG(ha, reg, num) \
395 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
396 (num < 8 ? \
397 &(reg)->u.isp2100.mailbox0 + (num) : \
398 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
399 &(reg)->u.isp2300.mailbox0 + (num))
400#define RD_MAILBOX_REG(ha, reg, num) \
401 RD_REG_WORD(MAILBOX_REG(ha, reg, num))
402#define WRT_MAILBOX_REG(ha, reg, num, data) \
403 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
404
405#define FB_CMD_REG(ha, reg) \
406 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
407 &(reg)->fb_cmd_2100 : \
408 &(reg)->u.isp2300.fb_cmd)
409#define RD_FB_CMD_REG(ha, reg) \
410 RD_REG_WORD(FB_CMD_REG(ha, reg))
411#define WRT_FB_CMD_REG(ha, reg, data) \
412 WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
413
414typedef struct {
415 uint32_t out_mb; /* outbound from driver */
416 uint32_t in_mb; /* Incoming from RISC */
417 uint16_t mb[MAILBOX_REGISTER_COUNT];
418 long buf_size;
419 void *bufp;
420 uint32_t tov;
421 uint8_t flags;
422#define MBX_DMA_IN BIT_0
423#define MBX_DMA_OUT BIT_1
424#define IOCTL_CMD BIT_2
425} mbx_cmd_t;
426
427#define MBX_TOV_SECONDS 30
428
429/*
430 * ISP product identification definitions in mailboxes after reset.
431 */
432#define PROD_ID_1 0x4953
433#define PROD_ID_2 0x0000
434#define PROD_ID_2a 0x5020
435#define PROD_ID_3 0x2020
436
437/*
438 * ISP mailbox Self-Test status codes
439 */
440#define MBS_FRM_ALIVE 0 /* Firmware Alive. */
441#define MBS_CHKSUM_ERR 1 /* Checksum Error. */
442#define MBS_BUSY 4 /* Busy. */
443
444/*
445 * ISP mailbox command complete status codes
446 */
447#define MBS_COMMAND_COMPLETE 0x4000
448#define MBS_INVALID_COMMAND 0x4001
449#define MBS_HOST_INTERFACE_ERROR 0x4002
450#define MBS_TEST_FAILED 0x4003
451#define MBS_COMMAND_ERROR 0x4005
452#define MBS_COMMAND_PARAMETER_ERROR 0x4006
453#define MBS_PORT_ID_USED 0x4007
454#define MBS_LOOP_ID_USED 0x4008
455#define MBS_ALL_IDS_IN_USE 0x4009
456#define MBS_NOT_LOGGED_IN 0x400A
3d71644c
AV
457#define MBS_LINK_DOWN_ERROR 0x400B
458#define MBS_DIAG_ECHO_TEST_ERROR 0x400C
1da177e4
LT
459
460/*
461 * ISP mailbox asynchronous event status codes
462 */
463#define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
464#define MBA_RESET 0x8001 /* Reset Detected. */
465#define MBA_SYSTEM_ERR 0x8002 /* System Error. */
466#define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
467#define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
468#define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
469#define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
470 /* occurred. */
471#define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
472#define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
473#define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
474#define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
475#define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
476#define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
477#define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
478#define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
479#define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
480#define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
481#define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
482#define MBA_IP_RECEIVE 0x8023 /* IP Received. */
483#define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
484#define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
485#define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
486#define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
487 /* used. */
45ebeb56 488#define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */
1da177e4
LT
489#define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
490#define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
491#define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
492#define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
493#define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
494#define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
495#define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
496#define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
497#define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
498#define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
499#define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
500#define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
501#define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
502
503/*
504 * Firmware options 1, 2, 3.
505 */
506#define FO1_AE_ON_LIPF8 BIT_0
507#define FO1_AE_ALL_LIP_RESET BIT_1
508#define FO1_CTIO_RETRY BIT_3
509#define FO1_DISABLE_LIP_F7_SW BIT_4
510#define FO1_DISABLE_100MS_LOS_WAIT BIT_5
3d71644c 511#define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */
1da177e4
LT
512#define FO1_AE_ON_LOOP_INIT_ERR BIT_7
513#define FO1_SET_EMPHASIS_SWING BIT_8
514#define FO1_AE_AUTO_BYPASS BIT_9
515#define FO1_ENABLE_PURE_IOCB BIT_10
516#define FO1_AE_PLOGI_RJT BIT_11
517#define FO1_ENABLE_ABORT_SEQUENCE BIT_12
518#define FO1_AE_QUEUE_FULL BIT_13
519
520#define FO2_ENABLE_ATIO_TYPE_3 BIT_0
521#define FO2_REV_LOOPBACK BIT_1
522
523#define FO3_ENABLE_EMERG_IOCB BIT_0
524#define FO3_AE_RND_ERROR BIT_1
525
3d71644c
AV
526/* 24XX additional firmware options */
527#define ADD_FO_COUNT 3
528#define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */
529#define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
530
531#define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
532
533#define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
534
1da177e4
LT
535/*
536 * ISP mailbox commands
537 */
538#define MBC_LOAD_RAM 1 /* Load RAM. */
539#define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
540#define MBC_WRITE_RAM_WORD 4 /* Write RAM word. */
541#define MBC_READ_RAM_WORD 5 /* Read RAM word. */
542#define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
543#define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
544#define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
545#define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
546#define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
547#define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
548#define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
549#define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
550#define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
551#define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
f6ef3b18 552#define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */
1da177e4
LT
553#define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
554#define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
555#define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
556#define MBC_RESET 0x18 /* Reset. */
557#define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
558#define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
559#define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
560#define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
561#define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
562#define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
563#define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
564#define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
565#define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
566#define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
567#define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
568#define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
569#define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
570#define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
571#define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
572#define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
573#define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
574#define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
575#define MBC_GET_RNID_PARAMS 0x5a /* Data Rate */
576#define MBC_DATA_RATE 0x5d /* Get RNID parameters */
577#define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
578#define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
579 /* Initialization Procedure */
580#define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
581#define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
582#define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
583#define MBC_TARGET_RESET 0x66 /* Target Reset. */
584#define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
585#define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
586#define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
587#define MBC_GET_PORT_NAME 0x6a /* Get port name. */
588#define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
589#define MBC_LIP_RESET 0x6c /* LIP reset. */
590#define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
591 /* commandd. */
592#define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
593#define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
594#define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
595#define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
596#define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
597#define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
598#define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
599#define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
600#define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
601#define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
602#define MBC_LUN_RESET 0x7E /* Send LUN reset */
603
3d71644c
AV
604/*
605 * ISP24xx mailbox commands
606 */
607#define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */
608#define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */
d8b45213 609#define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */
3d71644c 610#define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */
a7a167bf 611#define MBC_TRACE_CONTROL 0x27 /* Trace control command. */
3d71644c 612#define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */
88729e53 613#define MBC_READ_SFP 0x31 /* Read SFP Data. */
3d71644c
AV
614#define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */
615#define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */
616#define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */
617#define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */
618#define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */
619#define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */
620#define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */
621#define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */
622
1da177e4
LT
623/* Firmware return data sizes */
624#define FCAL_MAP_SIZE 128
625
626/* Mailbox bit definitions for out_mb and in_mb */
627#define MBX_31 BIT_31
628#define MBX_30 BIT_30
629#define MBX_29 BIT_29
630#define MBX_28 BIT_28
631#define MBX_27 BIT_27
632#define MBX_26 BIT_26
633#define MBX_25 BIT_25
634#define MBX_24 BIT_24
635#define MBX_23 BIT_23
636#define MBX_22 BIT_22
637#define MBX_21 BIT_21
638#define MBX_20 BIT_20
639#define MBX_19 BIT_19
640#define MBX_18 BIT_18
641#define MBX_17 BIT_17
642#define MBX_16 BIT_16
643#define MBX_15 BIT_15
644#define MBX_14 BIT_14
645#define MBX_13 BIT_13
646#define MBX_12 BIT_12
647#define MBX_11 BIT_11
648#define MBX_10 BIT_10
649#define MBX_9 BIT_9
650#define MBX_8 BIT_8
651#define MBX_7 BIT_7
652#define MBX_6 BIT_6
653#define MBX_5 BIT_5
654#define MBX_4 BIT_4
655#define MBX_3 BIT_3
656#define MBX_2 BIT_2
657#define MBX_1 BIT_1
658#define MBX_0 BIT_0
659
660/*
661 * Firmware state codes from get firmware state mailbox command
662 */
663#define FSTATE_CONFIG_WAIT 0
664#define FSTATE_WAIT_AL_PA 1
665#define FSTATE_WAIT_LOGIN 2
666#define FSTATE_READY 3
667#define FSTATE_LOSS_OF_SYNC 4
668#define FSTATE_ERROR 5
669#define FSTATE_REINIT 6
670#define FSTATE_NON_PART 7
671
672#define FSTATE_CONFIG_CORRECT 0
673#define FSTATE_P2P_RCV_LIP 1
674#define FSTATE_P2P_CHOOSE_LOOP 2
675#define FSTATE_P2P_RCV_UNIDEN_LIP 3
676#define FSTATE_FATAL_ERROR 4
677#define FSTATE_LOOP_BACK_CONN 5
678
679/*
680 * Port Database structure definition
681 * Little endian except where noted.
682 */
683#define PORT_DATABASE_SIZE 128 /* bytes */
684typedef struct {
685 uint8_t options;
686 uint8_t control;
687 uint8_t master_state;
688 uint8_t slave_state;
689 uint8_t reserved[2];
690 uint8_t hard_address;
691 uint8_t reserved_1;
692 uint8_t port_id[4];
693 uint8_t node_name[WWN_SIZE];
694 uint8_t port_name[WWN_SIZE];
695 uint16_t execution_throttle;
696 uint16_t execution_count;
697 uint8_t reset_count;
698 uint8_t reserved_2;
699 uint16_t resource_allocation;
700 uint16_t current_allocation;
701 uint16_t queue_head;
702 uint16_t queue_tail;
703 uint16_t transmit_execution_list_next;
704 uint16_t transmit_execution_list_previous;
705 uint16_t common_features;
706 uint16_t total_concurrent_sequences;
707 uint16_t RO_by_information_category;
708 uint8_t recipient;
709 uint8_t initiator;
710 uint16_t receive_data_size;
711 uint16_t concurrent_sequences;
712 uint16_t open_sequences_per_exchange;
713 uint16_t lun_abort_flags;
714 uint16_t lun_stop_flags;
715 uint16_t stop_queue_head;
716 uint16_t stop_queue_tail;
717 uint16_t port_retry_timer;
718 uint16_t next_sequence_id;
719 uint16_t frame_count;
720 uint16_t PRLI_payload_length;
721 uint8_t prli_svc_param_word_0[2]; /* Big endian */
722 /* Bits 15-0 of word 0 */
723 uint8_t prli_svc_param_word_3[2]; /* Big endian */
724 /* Bits 15-0 of word 3 */
725 uint16_t loop_id;
726 uint16_t extended_lun_info_list_pointer;
727 uint16_t extended_lun_stop_list_pointer;
728} port_database_t;
729
730/*
731 * Port database slave/master states
732 */
733#define PD_STATE_DISCOVERY 0
734#define PD_STATE_WAIT_DISCOVERY_ACK 1
735#define PD_STATE_PORT_LOGIN 2
736#define PD_STATE_WAIT_PORT_LOGIN_ACK 3
737#define PD_STATE_PROCESS_LOGIN 4
738#define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
739#define PD_STATE_PORT_LOGGED_IN 6
740#define PD_STATE_PORT_UNAVAILABLE 7
741#define PD_STATE_PROCESS_LOGOUT 8
742#define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
743#define PD_STATE_PORT_LOGOUT 10
744#define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
745
746
4fdfefe5
AV
747#define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
748#define QLA_ZIO_DISABLED 0
749#define QLA_ZIO_DEFAULT_TIMER 2
750
1da177e4
LT
751/*
752 * ISP Initialization Control Block.
753 * Little endian except where noted.
754 */
755#define ICB_VERSION 1
756typedef struct {
757 uint8_t version;
758 uint8_t reserved_1;
759
760 /*
761 * LSB BIT 0 = Enable Hard Loop Id
762 * LSB BIT 1 = Enable Fairness
763 * LSB BIT 2 = Enable Full-Duplex
764 * LSB BIT 3 = Enable Fast Posting
765 * LSB BIT 4 = Enable Target Mode
766 * LSB BIT 5 = Disable Initiator Mode
767 * LSB BIT 6 = Enable ADISC
768 * LSB BIT 7 = Enable Target Inquiry Data
769 *
770 * MSB BIT 0 = Enable PDBC Notify
771 * MSB BIT 1 = Non Participating LIP
772 * MSB BIT 2 = Descending Loop ID Search
773 * MSB BIT 3 = Acquire Loop ID in LIPA
774 * MSB BIT 4 = Stop PortQ on Full Status
775 * MSB BIT 5 = Full Login after LIP
776 * MSB BIT 6 = Node Name Option
777 * MSB BIT 7 = Ext IFWCB enable bit
778 */
779 uint8_t firmware_options[2];
780
781 uint16_t frame_payload_size;
782 uint16_t max_iocb_allocation;
783 uint16_t execution_throttle;
784 uint8_t retry_count;
785 uint8_t retry_delay; /* unused */
786 uint8_t port_name[WWN_SIZE]; /* Big endian. */
787 uint16_t hard_address;
788 uint8_t inquiry_data;
789 uint8_t login_timeout;
790 uint8_t node_name[WWN_SIZE]; /* Big endian. */
791
792 uint16_t request_q_outpointer;
793 uint16_t response_q_inpointer;
794 uint16_t request_q_length;
795 uint16_t response_q_length;
796 uint32_t request_q_address[2];
797 uint32_t response_q_address[2];
798
799 uint16_t lun_enables;
800 uint8_t command_resource_count;
801 uint8_t immediate_notify_resource_count;
802 uint16_t timeout;
803 uint8_t reserved_2[2];
804
805 /*
806 * LSB BIT 0 = Timer Operation mode bit 0
807 * LSB BIT 1 = Timer Operation mode bit 1
808 * LSB BIT 2 = Timer Operation mode bit 2
809 * LSB BIT 3 = Timer Operation mode bit 3
810 * LSB BIT 4 = Init Config Mode bit 0
811 * LSB BIT 5 = Init Config Mode bit 1
812 * LSB BIT 6 = Init Config Mode bit 2
813 * LSB BIT 7 = Enable Non part on LIHA failure
814 *
815 * MSB BIT 0 = Enable class 2
816 * MSB BIT 1 = Enable ACK0
817 * MSB BIT 2 =
818 * MSB BIT 3 =
819 * MSB BIT 4 = FC Tape Enable
820 * MSB BIT 5 = Enable FC Confirm
821 * MSB BIT 6 = Enable command queuing in target mode
822 * MSB BIT 7 = No Logo On Link Down
823 */
824 uint8_t add_firmware_options[2];
825
826 uint8_t response_accumulation_timer;
827 uint8_t interrupt_delay_timer;
828
829 /*
830 * LSB BIT 0 = Enable Read xfr_rdy
831 * LSB BIT 1 = Soft ID only
832 * LSB BIT 2 =
833 * LSB BIT 3 =
834 * LSB BIT 4 = FCP RSP Payload [0]
835 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
836 * LSB BIT 6 = Enable Out-of-Order frame handling
837 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
838 *
839 * MSB BIT 0 = Sbus enable - 2300
840 * MSB BIT 1 =
841 * MSB BIT 2 =
842 * MSB BIT 3 =
06c22bd1 843 * MSB BIT 4 = LED mode
1da177e4
LT
844 * MSB BIT 5 = enable 50 ohm termination
845 * MSB BIT 6 = Data Rate (2300 only)
846 * MSB BIT 7 = Data Rate (2300 only)
847 */
848 uint8_t special_options[2];
849
850 uint8_t reserved_3[26];
851} init_cb_t;
852
853/*
854 * Get Link Status mailbox command return buffer.
855 */
3d71644c
AV
856#define GLSO_SEND_RPS BIT_0
857#define GLSO_USE_DID BIT_3
858
43ef0580
AV
859struct link_statistics {
860 uint32_t link_fail_cnt;
861 uint32_t loss_sync_cnt;
862 uint32_t loss_sig_cnt;
863 uint32_t prim_seq_err_cnt;
864 uint32_t inval_xmit_word_cnt;
865 uint32_t inval_crc_cnt;
032d8dd7
HZ
866 uint32_t lip_cnt;
867 uint32_t unused1[0x1a];
43ef0580
AV
868 uint32_t tx_frames;
869 uint32_t rx_frames;
870 uint32_t dumped_frames;
871 uint32_t unused2[2];
872 uint32_t nos_rcvd;
873};
1da177e4
LT
874
875/*
876 * NVRAM Command values.
877 */
878#define NV_START_BIT BIT_2
879#define NV_WRITE_OP (BIT_26+BIT_24)
880#define NV_READ_OP (BIT_26+BIT_25)
881#define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
882#define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
883#define NV_DELAY_COUNT 10
884
885/*
886 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
887 */
888typedef struct {
889 /*
890 * NVRAM header
891 */
892 uint8_t id[4];
893 uint8_t nvram_version;
894 uint8_t reserved_0;
895
896 /*
897 * NVRAM RISC parameter block
898 */
899 uint8_t parameter_block_version;
900 uint8_t reserved_1;
901
902 /*
903 * LSB BIT 0 = Enable Hard Loop Id
904 * LSB BIT 1 = Enable Fairness
905 * LSB BIT 2 = Enable Full-Duplex
906 * LSB BIT 3 = Enable Fast Posting
907 * LSB BIT 4 = Enable Target Mode
908 * LSB BIT 5 = Disable Initiator Mode
909 * LSB BIT 6 = Enable ADISC
910 * LSB BIT 7 = Enable Target Inquiry Data
911 *
912 * MSB BIT 0 = Enable PDBC Notify
913 * MSB BIT 1 = Non Participating LIP
914 * MSB BIT 2 = Descending Loop ID Search
915 * MSB BIT 3 = Acquire Loop ID in LIPA
916 * MSB BIT 4 = Stop PortQ on Full Status
917 * MSB BIT 5 = Full Login after LIP
918 * MSB BIT 6 = Node Name Option
919 * MSB BIT 7 = Ext IFWCB enable bit
920 */
921 uint8_t firmware_options[2];
922
923 uint16_t frame_payload_size;
924 uint16_t max_iocb_allocation;
925 uint16_t execution_throttle;
926 uint8_t retry_count;
927 uint8_t retry_delay; /* unused */
928 uint8_t port_name[WWN_SIZE]; /* Big endian. */
929 uint16_t hard_address;
930 uint8_t inquiry_data;
931 uint8_t login_timeout;
932 uint8_t node_name[WWN_SIZE]; /* Big endian. */
933
934 /*
935 * LSB BIT 0 = Timer Operation mode bit 0
936 * LSB BIT 1 = Timer Operation mode bit 1
937 * LSB BIT 2 = Timer Operation mode bit 2
938 * LSB BIT 3 = Timer Operation mode bit 3
939 * LSB BIT 4 = Init Config Mode bit 0
940 * LSB BIT 5 = Init Config Mode bit 1
941 * LSB BIT 6 = Init Config Mode bit 2
942 * LSB BIT 7 = Enable Non part on LIHA failure
943 *
944 * MSB BIT 0 = Enable class 2
945 * MSB BIT 1 = Enable ACK0
946 * MSB BIT 2 =
947 * MSB BIT 3 =
948 * MSB BIT 4 = FC Tape Enable
949 * MSB BIT 5 = Enable FC Confirm
950 * MSB BIT 6 = Enable command queuing in target mode
951 * MSB BIT 7 = No Logo On Link Down
952 */
953 uint8_t add_firmware_options[2];
954
955 uint8_t response_accumulation_timer;
956 uint8_t interrupt_delay_timer;
957
958 /*
959 * LSB BIT 0 = Enable Read xfr_rdy
960 * LSB BIT 1 = Soft ID only
961 * LSB BIT 2 =
962 * LSB BIT 3 =
963 * LSB BIT 4 = FCP RSP Payload [0]
964 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
965 * LSB BIT 6 = Enable Out-of-Order frame handling
966 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
967 *
968 * MSB BIT 0 = Sbus enable - 2300
969 * MSB BIT 1 =
970 * MSB BIT 2 =
971 * MSB BIT 3 =
06c22bd1 972 * MSB BIT 4 = LED mode
1da177e4
LT
973 * MSB BIT 5 = enable 50 ohm termination
974 * MSB BIT 6 = Data Rate (2300 only)
975 * MSB BIT 7 = Data Rate (2300 only)
976 */
977 uint8_t special_options[2];
978
979 /* Reserved for expanded RISC parameter block */
980 uint8_t reserved_2[22];
981
982 /*
983 * LSB BIT 0 = Tx Sensitivity 1G bit 0
984 * LSB BIT 1 = Tx Sensitivity 1G bit 1
985 * LSB BIT 2 = Tx Sensitivity 1G bit 2
986 * LSB BIT 3 = Tx Sensitivity 1G bit 3
987 * LSB BIT 4 = Rx Sensitivity 1G bit 0
988 * LSB BIT 5 = Rx Sensitivity 1G bit 1
989 * LSB BIT 6 = Rx Sensitivity 1G bit 2
990 * LSB BIT 7 = Rx Sensitivity 1G bit 3
fa2a1ce5 991 *
1da177e4
LT
992 * MSB BIT 0 = Tx Sensitivity 2G bit 0
993 * MSB BIT 1 = Tx Sensitivity 2G bit 1
994 * MSB BIT 2 = Tx Sensitivity 2G bit 2
995 * MSB BIT 3 = Tx Sensitivity 2G bit 3
996 * MSB BIT 4 = Rx Sensitivity 2G bit 0
997 * MSB BIT 5 = Rx Sensitivity 2G bit 1
998 * MSB BIT 6 = Rx Sensitivity 2G bit 2
999 * MSB BIT 7 = Rx Sensitivity 2G bit 3
1000 *
1001 * LSB BIT 0 = Output Swing 1G bit 0
1002 * LSB BIT 1 = Output Swing 1G bit 1
1003 * LSB BIT 2 = Output Swing 1G bit 2
1004 * LSB BIT 3 = Output Emphasis 1G bit 0
1005 * LSB BIT 4 = Output Emphasis 1G bit 1
1006 * LSB BIT 5 = Output Swing 2G bit 0
1007 * LSB BIT 6 = Output Swing 2G bit 1
1008 * LSB BIT 7 = Output Swing 2G bit 2
fa2a1ce5 1009 *
1da177e4
LT
1010 * MSB BIT 0 = Output Emphasis 2G bit 0
1011 * MSB BIT 1 = Output Emphasis 2G bit 1
1012 * MSB BIT 2 = Output Enable
1013 * MSB BIT 3 =
1014 * MSB BIT 4 =
1015 * MSB BIT 5 =
1016 * MSB BIT 6 =
1017 * MSB BIT 7 =
1018 */
1019 uint8_t seriallink_options[4];
1020
1021 /*
1022 * NVRAM host parameter block
1023 *
1024 * LSB BIT 0 = Enable spinup delay
1025 * LSB BIT 1 = Disable BIOS
1026 * LSB BIT 2 = Enable Memory Map BIOS
1027 * LSB BIT 3 = Enable Selectable Boot
1028 * LSB BIT 4 = Disable RISC code load
1029 * LSB BIT 5 = Set cache line size 1
1030 * LSB BIT 6 = PCI Parity Disable
1031 * LSB BIT 7 = Enable extended logging
1032 *
1033 * MSB BIT 0 = Enable 64bit addressing
1034 * MSB BIT 1 = Enable lip reset
1035 * MSB BIT 2 = Enable lip full login
1036 * MSB BIT 3 = Enable target reset
1037 * MSB BIT 4 = Enable database storage
1038 * MSB BIT 5 = Enable cache flush read
1039 * MSB BIT 6 = Enable database load
1040 * MSB BIT 7 = Enable alternate WWN
1041 */
1042 uint8_t host_p[2];
1043
1044 uint8_t boot_node_name[WWN_SIZE];
1045 uint8_t boot_lun_number;
1046 uint8_t reset_delay;
1047 uint8_t port_down_retry_count;
1048 uint8_t boot_id_number;
1049 uint16_t max_luns_per_target;
1050 uint8_t fcode_boot_port_name[WWN_SIZE];
1051 uint8_t alternate_port_name[WWN_SIZE];
1052 uint8_t alternate_node_name[WWN_SIZE];
1053
1054 /*
1055 * BIT 0 = Selective Login
1056 * BIT 1 = Alt-Boot Enable
1057 * BIT 2 =
1058 * BIT 3 = Boot Order List
1059 * BIT 4 =
1060 * BIT 5 = Selective LUN
1061 * BIT 6 =
1062 * BIT 7 = unused
1063 */
1064 uint8_t efi_parameters;
1065
1066 uint8_t link_down_timeout;
1067
cca5335c 1068 uint8_t adapter_id[16];
1da177e4
LT
1069
1070 uint8_t alt1_boot_node_name[WWN_SIZE];
1071 uint16_t alt1_boot_lun_number;
1072 uint8_t alt2_boot_node_name[WWN_SIZE];
1073 uint16_t alt2_boot_lun_number;
1074 uint8_t alt3_boot_node_name[WWN_SIZE];
1075 uint16_t alt3_boot_lun_number;
1076 uint8_t alt4_boot_node_name[WWN_SIZE];
1077 uint16_t alt4_boot_lun_number;
1078 uint8_t alt5_boot_node_name[WWN_SIZE];
1079 uint16_t alt5_boot_lun_number;
1080 uint8_t alt6_boot_node_name[WWN_SIZE];
1081 uint16_t alt6_boot_lun_number;
1082 uint8_t alt7_boot_node_name[WWN_SIZE];
1083 uint16_t alt7_boot_lun_number;
1084
1085 uint8_t reserved_3[2];
1086
1087 /* Offset 200-215 : Model Number */
1088 uint8_t model_number[16];
1089
1090 /* OEM related items */
1091 uint8_t oem_specific[16];
1092
1093 /*
1094 * NVRAM Adapter Features offset 232-239
1095 *
1096 * LSB BIT 0 = External GBIC
1097 * LSB BIT 1 = Risc RAM parity
1098 * LSB BIT 2 = Buffer Plus Module
1099 * LSB BIT 3 = Multi Chip Adapter
1100 * LSB BIT 4 = Internal connector
1101 * LSB BIT 5 =
1102 * LSB BIT 6 =
1103 * LSB BIT 7 =
1104 *
1105 * MSB BIT 0 =
1106 * MSB BIT 1 =
1107 * MSB BIT 2 =
1108 * MSB BIT 3 =
1109 * MSB BIT 4 =
1110 * MSB BIT 5 =
1111 * MSB BIT 6 =
1112 * MSB BIT 7 =
1113 */
1114 uint8_t adapter_features[2];
1115
1116 uint8_t reserved_4[16];
1117
1118 /* Subsystem vendor ID for ISP2200 */
1119 uint16_t subsystem_vendor_id_2200;
1120
1121 /* Subsystem device ID for ISP2200 */
1122 uint16_t subsystem_device_id_2200;
1123
1124 uint8_t reserved_5;
1125 uint8_t checksum;
1126} nvram_t;
1127
1128/*
1129 * ISP queue - response queue entry definition.
1130 */
1131typedef struct {
1132 uint8_t data[60];
1133 uint32_t signature;
1134#define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
1135} response_t;
1136
1137typedef union {
1138 uint16_t extended;
1139 struct {
1140 uint8_t reserved;
1141 uint8_t standard;
1142 } id;
1143} target_id_t;
1144
1145#define SET_TARGET_ID(ha, to, from) \
1146do { \
1147 if (HAS_EXTENDED_IDS(ha)) \
1148 to.extended = cpu_to_le16(from); \
1149 else \
1150 to.id.standard = (uint8_t)from; \
1151} while (0)
1152
1153/*
1154 * ISP queue - command entry structure definition.
1155 */
1156#define COMMAND_TYPE 0x11 /* Command entry */
1da177e4
LT
1157typedef struct {
1158 uint8_t entry_type; /* Entry type. */
1159 uint8_t entry_count; /* Entry count. */
1160 uint8_t sys_define; /* System defined. */
1161 uint8_t entry_status; /* Entry Status. */
1162 uint32_t handle; /* System handle. */
1163 target_id_t target; /* SCSI ID */
1164 uint16_t lun; /* SCSI LUN */
1165 uint16_t control_flags; /* Control flags. */
1166#define CF_WRITE BIT_6
1167#define CF_READ BIT_5
1168#define CF_SIMPLE_TAG BIT_3
1169#define CF_ORDERED_TAG BIT_2
1170#define CF_HEAD_TAG BIT_1
1171 uint16_t reserved_1;
1172 uint16_t timeout; /* Command timeout. */
1173 uint16_t dseg_count; /* Data segment count. */
1174 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1175 uint32_t byte_count; /* Total byte count. */
1176 uint32_t dseg_0_address; /* Data segment 0 address. */
1177 uint32_t dseg_0_length; /* Data segment 0 length. */
1178 uint32_t dseg_1_address; /* Data segment 1 address. */
1179 uint32_t dseg_1_length; /* Data segment 1 length. */
1180 uint32_t dseg_2_address; /* Data segment 2 address. */
1181 uint32_t dseg_2_length; /* Data segment 2 length. */
1182} cmd_entry_t;
1183
1184/*
1185 * ISP queue - 64-Bit addressing, command entry structure definition.
1186 */
1187#define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
1188typedef struct {
1189 uint8_t entry_type; /* Entry type. */
1190 uint8_t entry_count; /* Entry count. */
1191 uint8_t sys_define; /* System defined. */
1192 uint8_t entry_status; /* Entry Status. */
1193 uint32_t handle; /* System handle. */
1194 target_id_t target; /* SCSI ID */
1195 uint16_t lun; /* SCSI LUN */
1196 uint16_t control_flags; /* Control flags. */
1197 uint16_t reserved_1;
1198 uint16_t timeout; /* Command timeout. */
1199 uint16_t dseg_count; /* Data segment count. */
1200 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1201 uint32_t byte_count; /* Total byte count. */
1202 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1203 uint32_t dseg_0_length; /* Data segment 0 length. */
1204 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1205 uint32_t dseg_1_length; /* Data segment 1 length. */
1206} cmd_a64_entry_t, request_t;
1207
1208/*
1209 * ISP queue - continuation entry structure definition.
1210 */
1211#define CONTINUE_TYPE 0x02 /* Continuation entry. */
1212typedef struct {
1213 uint8_t entry_type; /* Entry type. */
1214 uint8_t entry_count; /* Entry count. */
1215 uint8_t sys_define; /* System defined. */
1216 uint8_t entry_status; /* Entry Status. */
1217 uint32_t reserved;
1218 uint32_t dseg_0_address; /* Data segment 0 address. */
1219 uint32_t dseg_0_length; /* Data segment 0 length. */
1220 uint32_t dseg_1_address; /* Data segment 1 address. */
1221 uint32_t dseg_1_length; /* Data segment 1 length. */
1222 uint32_t dseg_2_address; /* Data segment 2 address. */
1223 uint32_t dseg_2_length; /* Data segment 2 length. */
1224 uint32_t dseg_3_address; /* Data segment 3 address. */
1225 uint32_t dseg_3_length; /* Data segment 3 length. */
1226 uint32_t dseg_4_address; /* Data segment 4 address. */
1227 uint32_t dseg_4_length; /* Data segment 4 length. */
1228 uint32_t dseg_5_address; /* Data segment 5 address. */
1229 uint32_t dseg_5_length; /* Data segment 5 length. */
1230 uint32_t dseg_6_address; /* Data segment 6 address. */
1231 uint32_t dseg_6_length; /* Data segment 6 length. */
1232} cont_entry_t;
1233
1234/*
1235 * ISP queue - 64-Bit addressing, continuation entry structure definition.
1236 */
1237#define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
1238typedef struct {
1239 uint8_t entry_type; /* Entry type. */
1240 uint8_t entry_count; /* Entry count. */
1241 uint8_t sys_define; /* System defined. */
1242 uint8_t entry_status; /* Entry Status. */
1243 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1244 uint32_t dseg_0_length; /* Data segment 0 length. */
1245 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1246 uint32_t dseg_1_length; /* Data segment 1 length. */
1247 uint32_t dseg_2_address [2]; /* Data segment 2 address. */
1248 uint32_t dseg_2_length; /* Data segment 2 length. */
1249 uint32_t dseg_3_address[2]; /* Data segment 3 address. */
1250 uint32_t dseg_3_length; /* Data segment 3 length. */
1251 uint32_t dseg_4_address[2]; /* Data segment 4 address. */
1252 uint32_t dseg_4_length; /* Data segment 4 length. */
1253} cont_a64_entry_t;
1254
1255/*
1256 * ISP queue - status entry structure definition.
1257 */
1258#define STATUS_TYPE 0x03 /* Status entry. */
1259typedef struct {
1260 uint8_t entry_type; /* Entry type. */
1261 uint8_t entry_count; /* Entry count. */
1262 uint8_t sys_define; /* System defined. */
1263 uint8_t entry_status; /* Entry Status. */
1264 uint32_t handle; /* System handle. */
1265 uint16_t scsi_status; /* SCSI status. */
1266 uint16_t comp_status; /* Completion status. */
1267 uint16_t state_flags; /* State flags. */
1268 uint16_t status_flags; /* Status flags. */
1269 uint16_t rsp_info_len; /* Response Info Length. */
1270 uint16_t req_sense_length; /* Request sense data length. */
1271 uint32_t residual_length; /* Residual transfer length. */
1272 uint8_t rsp_info[8]; /* FCP response information. */
1273 uint8_t req_sense_data[32]; /* Request sense data. */
1274} sts_entry_t;
1275
1276/*
1277 * Status entry entry status
1278 */
3d71644c 1279#define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */
1da177e4
LT
1280#define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
1281#define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
1282#define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
1283#define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
1284#define RF_BUSY BIT_1 /* Busy */
3d71644c
AV
1285#define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
1286 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
1287#define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
1288 RF_INV_E_TYPE)
1da177e4
LT
1289
1290/*
1291 * Status entry SCSI status bit definitions.
1292 */
1293#define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
1294#define SS_RESIDUAL_UNDER BIT_11
1295#define SS_RESIDUAL_OVER BIT_10
1296#define SS_SENSE_LEN_VALID BIT_9
1297#define SS_RESPONSE_INFO_LEN_VALID BIT_8
1298
1299#define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
1300#define SS_BUSY_CONDITION BIT_3
1301#define SS_CONDITION_MET BIT_2
1302#define SS_CHECK_CONDITION BIT_1
1303
1304/*
1305 * Status entry completion status
1306 */
1307#define CS_COMPLETE 0x0 /* No errors */
1308#define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
1309#define CS_DMA 0x2 /* A DMA direction error. */
1310#define CS_TRANSPORT 0x3 /* Transport error. */
1311#define CS_RESET 0x4 /* SCSI bus reset occurred */
1312#define CS_ABORTED 0x5 /* System aborted command. */
1313#define CS_TIMEOUT 0x6 /* Timeout error. */
1314#define CS_DATA_OVERRUN 0x7 /* Data overrun. */
1315
1316#define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
1317#define CS_QUEUE_FULL 0x1C /* Queue Full. */
1318#define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
1319 /* (selection timeout) */
1320#define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
1321#define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
1322#define CS_PORT_BUSY 0x2B /* Port Busy */
1323#define CS_COMPLETE_CHKCOND 0x30 /* Error? */
1324#define CS_BAD_PAYLOAD 0x80 /* Driver defined */
1325#define CS_UNKNOWN 0x81 /* Driver defined */
1326#define CS_RETRY 0x82 /* Driver defined */
1327#define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
1328
1329/*
1330 * Status entry status flags
1331 */
1332#define SF_ABTS_TERMINATED BIT_10
1333#define SF_LOGOUT_SENT BIT_13
1334
1335/*
1336 * ISP queue - status continuation entry structure definition.
1337 */
1338#define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
1339typedef struct {
1340 uint8_t entry_type; /* Entry type. */
1341 uint8_t entry_count; /* Entry count. */
1342 uint8_t sys_define; /* System defined. */
1343 uint8_t entry_status; /* Entry Status. */
1344 uint8_t data[60]; /* data */
1345} sts_cont_entry_t;
1346
1347/*
1348 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
1349 * structure definition.
1350 */
1351#define STATUS_TYPE_21 0x21 /* Status entry. */
1352typedef struct {
1353 uint8_t entry_type; /* Entry type. */
1354 uint8_t entry_count; /* Entry count. */
1355 uint8_t handle_count; /* Handle count. */
1356 uint8_t entry_status; /* Entry Status. */
1357 uint32_t handle[15]; /* System handles. */
1358} sts21_entry_t;
1359
1360/*
1361 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
1362 * structure definition.
1363 */
1364#define STATUS_TYPE_22 0x22 /* Status entry. */
1365typedef struct {
1366 uint8_t entry_type; /* Entry type. */
1367 uint8_t entry_count; /* Entry count. */
1368 uint8_t handle_count; /* Handle count. */
1369 uint8_t entry_status; /* Entry Status. */
1370 uint16_t handle[30]; /* System handles. */
1371} sts22_entry_t;
1372
1373/*
1374 * ISP queue - marker entry structure definition.
1375 */
1376#define MARKER_TYPE 0x04 /* Marker entry. */
1377typedef struct {
1378 uint8_t entry_type; /* Entry type. */
1379 uint8_t entry_count; /* Entry count. */
1380 uint8_t handle_count; /* Handle count. */
1381 uint8_t entry_status; /* Entry Status. */
1382 uint32_t sys_define_2; /* System defined. */
1383 target_id_t target; /* SCSI ID */
1384 uint8_t modifier; /* Modifier (7-0). */
1385#define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
1386#define MK_SYNC_ID 1 /* Synchronize ID */
1387#define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
1388#define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
1389 /* clear port changed, */
1390 /* use sequence number. */
1391 uint8_t reserved_1;
1392 uint16_t sequence_number; /* Sequence number of event */
1393 uint16_t lun; /* SCSI LUN */
1394 uint8_t reserved_2[48];
1395} mrk_entry_t;
1396
1397/*
1398 * ISP queue - Management Server entry structure definition.
1399 */
1400#define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
1401typedef struct {
1402 uint8_t entry_type; /* Entry type. */
1403 uint8_t entry_count; /* Entry count. */
1404 uint8_t handle_count; /* Handle count. */
1405 uint8_t entry_status; /* Entry Status. */
1406 uint32_t handle1; /* System handle. */
1407 target_id_t loop_id;
1408 uint16_t status;
1409 uint16_t control_flags; /* Control flags. */
1410 uint16_t reserved2;
1411 uint16_t timeout;
1412 uint16_t cmd_dsd_count;
1413 uint16_t total_dsd_count;
1414 uint8_t type;
1415 uint8_t r_ctl;
1416 uint16_t rx_id;
1417 uint16_t reserved3;
1418 uint32_t handle2;
1419 uint32_t rsp_bytecount;
1420 uint32_t req_bytecount;
1421 uint32_t dseg_req_address[2]; /* Data segment 0 address. */
1422 uint32_t dseg_req_length; /* Data segment 0 length. */
1423 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */
1424 uint32_t dseg_rsp_length; /* Data segment 1 length. */
1425} ms_iocb_entry_t;
1426
1427
1428/*
1429 * ISP queue - Mailbox Command entry structure definition.
1430 */
1431#define MBX_IOCB_TYPE 0x39
1432struct mbx_entry {
1433 uint8_t entry_type;
1434 uint8_t entry_count;
1435 uint8_t sys_define1;
1436 /* Use sys_define1 for source type */
1437#define SOURCE_SCSI 0x00
1438#define SOURCE_IP 0x01
1439#define SOURCE_VI 0x02
1440#define SOURCE_SCTP 0x03
1441#define SOURCE_MP 0x04
1442#define SOURCE_MPIOCTL 0x05
1443#define SOURCE_ASYNC_IOCB 0x07
1444
1445 uint8_t entry_status;
1446
1447 uint32_t handle;
1448 target_id_t loop_id;
1449
1450 uint16_t status;
1451 uint16_t state_flags;
1452 uint16_t status_flags;
1453
1454 uint32_t sys_define2[2];
1455
1456 uint16_t mb0;
1457 uint16_t mb1;
1458 uint16_t mb2;
1459 uint16_t mb3;
1460 uint16_t mb6;
1461 uint16_t mb7;
1462 uint16_t mb9;
1463 uint16_t mb10;
1464 uint32_t reserved_2[2];
1465 uint8_t node_name[WWN_SIZE];
1466 uint8_t port_name[WWN_SIZE];
1467};
1468
1469/*
1470 * ISP request and response queue entry sizes
1471 */
1472#define RESPONSE_ENTRY_SIZE (sizeof(response_t))
1473#define REQUEST_ENTRY_SIZE (sizeof(request_t))
1474
1475
1476/*
1477 * 24 bit port ID type definition.
1478 */
1479typedef union {
1480 uint32_t b24 : 24;
1481
1482 struct {
b889d531
MN
1483#ifdef __BIG_ENDIAN
1484 uint8_t domain;
1485 uint8_t area;
1486 uint8_t al_pa;
1487#elif __LITTLE_ENDIAN
1da177e4
LT
1488 uint8_t al_pa;
1489 uint8_t area;
1490 uint8_t domain;
b889d531
MN
1491#else
1492#error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!"
1493#endif
1da177e4
LT
1494 uint8_t rsvd_1;
1495 } b;
1496} port_id_t;
1497#define INVALID_PORT_ID 0xFFFFFF
1498
1499/*
1500 * Switch info gathering structure.
1501 */
1502typedef struct {
1503 port_id_t d_id;
1504 uint8_t node_name[WWN_SIZE];
1505 uint8_t port_name[WWN_SIZE];
d8b45213 1506 uint8_t fabric_port_name[WWN_SIZE];
d8b45213 1507 uint16_t fp_speed;
1da177e4
LT
1508} sw_info_t;
1509
1da177e4
LT
1510/*
1511 * Fibre channel port type.
1512 */
1513 typedef enum {
1514 FCT_UNKNOWN,
1515 FCT_RSCN,
1516 FCT_SWITCH,
1517 FCT_BROADCAST,
1518 FCT_INITIATOR,
1519 FCT_TARGET
1520} fc_port_type_t;
1521
1522/*
1523 * Fibre channel port structure.
1524 */
1525typedef struct fc_port {
1526 struct list_head list;
1da177e4 1527 struct scsi_qla_host *ha;
1da177e4
LT
1528
1529 uint8_t node_name[WWN_SIZE];
1530 uint8_t port_name[WWN_SIZE];
1531 port_id_t d_id;
1532 uint16_t loop_id;
1533 uint16_t old_loop_id;
1534
d8b45213
AV
1535 uint8_t fabric_port_name[WWN_SIZE];
1536 uint16_t fp_speed;
1537
1da177e4
LT
1538 fc_port_type_t port_type;
1539
1540 atomic_t state;
1541 uint32_t flags;
1542
1da177e4
LT
1543 int port_login_retry_count;
1544 int login_retry;
1545 atomic_t port_down_timer;
1546
d97994dc 1547 struct fc_rport *rport, *drport;
ad3e0eda 1548 u32 supported_classes;
df7baa50
AV
1549
1550 unsigned long last_queue_full;
1551 unsigned long last_ramp_up;
2c3dfe3f
SJ
1552
1553 struct list_head vp_fcport;
1554 uint16_t vp_idx;
1da177e4
LT
1555} fc_port_t;
1556
1557/*
1558 * Fibre channel port/lun states.
1559 */
1560#define FCS_UNCONFIGURED 1
1561#define FCS_DEVICE_DEAD 2
1562#define FCS_DEVICE_LOST 3
1563#define FCS_ONLINE 4
1564#define FCS_NOT_SUPPORTED 5
1565#define FCS_FAILOVER 6
1566#define FCS_FAILOVER_FAILED 7
1567
1568/*
1569 * FC port flags.
1570 */
1571#define FCF_FABRIC_DEVICE BIT_0
1572#define FCF_LOGIN_NEEDED BIT_1
1573#define FCF_FO_MASKED BIT_2
1574#define FCF_FAILOVER_NEEDED BIT_3
1575#define FCF_RESET_NEEDED BIT_4
1576#define FCF_PERSISTENT_BOUND BIT_5
1577#define FCF_TAPE_PRESENT BIT_6
1578#define FCF_FARP_DONE BIT_7
1579#define FCF_FARP_FAILED BIT_8
1580#define FCF_FARP_REPLY_NEEDED BIT_9
1581#define FCF_AUTH_REQ BIT_10
1582#define FCF_SEND_AUTH_REQ BIT_11
1583#define FCF_RECEIVE_AUTH_REQ BIT_12
1584#define FCF_AUTH_SUCCESS BIT_13
1585#define FCF_RLC_SUPPORT BIT_14
1586#define FCF_CONFIG BIT_15 /* Needed? */
1587#define FCF_RESCAN_NEEDED BIT_16
1588#define FCF_XP_DEVICE BIT_17
1589#define FCF_MSA_DEVICE BIT_18
1590#define FCF_EVA_DEVICE BIT_19
1591#define FCF_MSA_PORT_ACTIVE BIT_20
1592#define FCF_FAILBACK_DISABLE BIT_21
1593#define FCF_FAILOVER_DISABLE BIT_22
1594#define FCF_DSXXX_DEVICE BIT_23
1595#define FCF_AA_EVA_DEVICE BIT_24
3d71644c 1596#define FCF_AA_MSA_DEVICE BIT_25
1da177e4
LT
1597
1598/* No loop ID flag. */
1599#define FC_NO_LOOP_ID 0x1000
1600
1da177e4
LT
1601/*
1602 * FC-CT interface
1603 *
1604 * NOTE: All structures are big-endian in form.
1605 */
1606
1607#define CT_REJECT_RESPONSE 0x8001
1608#define CT_ACCEPT_RESPONSE 0x8002
4346b149 1609#define CT_REASON_INVALID_COMMAND_CODE 0x01
cca5335c 1610#define CT_REASON_CANNOT_PERFORM 0x09
3fe7cfb9 1611#define CT_REASON_COMMAND_UNSUPPORTED 0x0b
cca5335c 1612#define CT_EXPL_ALREADY_REGISTERED 0x10
1da177e4
LT
1613
1614#define NS_N_PORT_TYPE 0x01
1615#define NS_NL_PORT_TYPE 0x02
1616#define NS_NX_PORT_TYPE 0x7F
1617
1618#define GA_NXT_CMD 0x100
1619#define GA_NXT_REQ_SIZE (16 + 4)
1620#define GA_NXT_RSP_SIZE (16 + 620)
1621
1622#define GID_PT_CMD 0x1A1
1623#define GID_PT_REQ_SIZE (16 + 4)
1624#define GID_PT_RSP_SIZE (16 + (MAX_FIBRE_DEVICES * 4))
1625
1626#define GPN_ID_CMD 0x112
1627#define GPN_ID_REQ_SIZE (16 + 4)
1628#define GPN_ID_RSP_SIZE (16 + 8)
1629
1630#define GNN_ID_CMD 0x113
1631#define GNN_ID_REQ_SIZE (16 + 4)
1632#define GNN_ID_RSP_SIZE (16 + 8)
1633
1634#define GFT_ID_CMD 0x117
1635#define GFT_ID_REQ_SIZE (16 + 4)
1636#define GFT_ID_RSP_SIZE (16 + 32)
1637
1638#define RFT_ID_CMD 0x217
1639#define RFT_ID_REQ_SIZE (16 + 4 + 32)
1640#define RFT_ID_RSP_SIZE 16
1641
1642#define RFF_ID_CMD 0x21F
1643#define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
1644#define RFF_ID_RSP_SIZE 16
1645
1646#define RNN_ID_CMD 0x213
1647#define RNN_ID_REQ_SIZE (16 + 4 + 8)
1648#define RNN_ID_RSP_SIZE 16
1649
1650#define RSNN_NN_CMD 0x239
1651#define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
1652#define RSNN_NN_RSP_SIZE 16
1653
d8b45213
AV
1654#define GFPN_ID_CMD 0x11C
1655#define GFPN_ID_REQ_SIZE (16 + 4)
1656#define GFPN_ID_RSP_SIZE (16 + 8)
1657
1658#define GPSC_CMD 0x127
1659#define GPSC_REQ_SIZE (16 + 8)
1660#define GPSC_RSP_SIZE (16 + 2 + 2)
1661
1662
cca5335c
AV
1663/*
1664 * HBA attribute types.
1665 */
1666#define FDMI_HBA_ATTR_COUNT 9
1667#define FDMI_HBA_NODE_NAME 1
1668#define FDMI_HBA_MANUFACTURER 2
1669#define FDMI_HBA_SERIAL_NUMBER 3
1670#define FDMI_HBA_MODEL 4
1671#define FDMI_HBA_MODEL_DESCRIPTION 5
1672#define FDMI_HBA_HARDWARE_VERSION 6
1673#define FDMI_HBA_DRIVER_VERSION 7
1674#define FDMI_HBA_OPTION_ROM_VERSION 8
1675#define FDMI_HBA_FIRMWARE_VERSION 9
1676#define FDMI_HBA_OS_NAME_AND_VERSION 0xa
1677#define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
1678
1679struct ct_fdmi_hba_attr {
1680 uint16_t type;
1681 uint16_t len;
1682 union {
1683 uint8_t node_name[WWN_SIZE];
1684 uint8_t manufacturer[32];
1685 uint8_t serial_num[8];
1686 uint8_t model[16];
1687 uint8_t model_desc[80];
1688 uint8_t hw_version[16];
1689 uint8_t driver_version[32];
1690 uint8_t orom_version[16];
1691 uint8_t fw_version[16];
1692 uint8_t os_version[128];
1693 uint8_t max_ct_len[4];
1694 } a;
1695};
1696
1697struct ct_fdmi_hba_attributes {
1698 uint32_t count;
1699 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT];
1700};
1701
1702/*
1703 * Port attribute types.
1704 */
8a85e171 1705#define FDMI_PORT_ATTR_COUNT 6
cca5335c
AV
1706#define FDMI_PORT_FC4_TYPES 1
1707#define FDMI_PORT_SUPPORT_SPEED 2
1708#define FDMI_PORT_CURRENT_SPEED 3
1709#define FDMI_PORT_MAX_FRAME_SIZE 4
1710#define FDMI_PORT_OS_DEVICE_NAME 5
1711#define FDMI_PORT_HOST_NAME 6
1712
5881569b
AV
1713#define FDMI_PORT_SPEED_1GB 0x1
1714#define FDMI_PORT_SPEED_2GB 0x2
1715#define FDMI_PORT_SPEED_10GB 0x4
1716#define FDMI_PORT_SPEED_4GB 0x8
1717#define FDMI_PORT_SPEED_8GB 0x10
1718#define FDMI_PORT_SPEED_16GB 0x20
1719#define FDMI_PORT_SPEED_UNKNOWN 0x8000
1720
cca5335c
AV
1721struct ct_fdmi_port_attr {
1722 uint16_t type;
1723 uint16_t len;
1724 union {
1725 uint8_t fc4_types[32];
1726 uint32_t sup_speed;
1727 uint32_t cur_speed;
1728 uint32_t max_frame_size;
1729 uint8_t os_dev_name[32];
1730 uint8_t host_name[32];
1731 } a;
1732};
1733
1734/*
1735 * Port Attribute Block.
1736 */
1737struct ct_fdmi_port_attributes {
1738 uint32_t count;
1739 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT];
1740};
1741
1742/* FDMI definitions. */
1743#define GRHL_CMD 0x100
1744#define GHAT_CMD 0x101
1745#define GRPL_CMD 0x102
1746#define GPAT_CMD 0x110
1747
1748#define RHBA_CMD 0x200
1749#define RHBA_RSP_SIZE 16
1750
1751#define RHAT_CMD 0x201
1752#define RPRT_CMD 0x210
1753
1754#define RPA_CMD 0x211
1755#define RPA_RSP_SIZE 16
1756
1757#define DHBA_CMD 0x300
1758#define DHBA_REQ_SIZE (16 + 8)
1759#define DHBA_RSP_SIZE 16
1760
1761#define DHAT_CMD 0x301
1762#define DPRT_CMD 0x310
1763#define DPA_CMD 0x311
1764
1da177e4
LT
1765/* CT command header -- request/response common fields */
1766struct ct_cmd_hdr {
1767 uint8_t revision;
1768 uint8_t in_id[3];
1769 uint8_t gs_type;
1770 uint8_t gs_subtype;
1771 uint8_t options;
1772 uint8_t reserved;
1773};
1774
1775/* CT command request */
1776struct ct_sns_req {
1777 struct ct_cmd_hdr header;
1778 uint16_t command;
1779 uint16_t max_rsp_size;
1780 uint8_t fragment_id;
1781 uint8_t reserved[3];
1782
1783 union {
d8b45213 1784 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */
1da177e4
LT
1785 struct {
1786 uint8_t reserved;
1787 uint8_t port_id[3];
1788 } port_id;
1789
1790 struct {
1791 uint8_t port_type;
1792 uint8_t domain;
1793 uint8_t area;
1794 uint8_t reserved;
1795 } gid_pt;
1796
1797 struct {
1798 uint8_t reserved;
1799 uint8_t port_id[3];
1800 uint8_t fc4_types[32];
1801 } rft_id;
1802
1803 struct {
1804 uint8_t reserved;
1805 uint8_t port_id[3];
1806 uint16_t reserved2;
1807 uint8_t fc4_feature;
1808 uint8_t fc4_type;
1809 } rff_id;
1810
1811 struct {
1812 uint8_t reserved;
1813 uint8_t port_id[3];
1814 uint8_t node_name[8];
1815 } rnn_id;
1816
1817 struct {
1818 uint8_t node_name[8];
1819 uint8_t name_len;
1820 uint8_t sym_node_name[255];
1821 } rsnn_nn;
cca5335c
AV
1822
1823 struct {
1824 uint8_t hba_indentifier[8];
1825 } ghat;
1826
1827 struct {
1828 uint8_t hba_identifier[8];
1829 uint32_t entry_count;
1830 uint8_t port_name[8];
1831 struct ct_fdmi_hba_attributes attrs;
1832 } rhba;
1833
1834 struct {
1835 uint8_t hba_identifier[8];
1836 struct ct_fdmi_hba_attributes attrs;
1837 } rhat;
1838
1839 struct {
1840 uint8_t port_name[8];
1841 struct ct_fdmi_port_attributes attrs;
1842 } rpa;
1843
1844 struct {
1845 uint8_t port_name[8];
1846 } dhba;
1847
1848 struct {
1849 uint8_t port_name[8];
1850 } dhat;
1851
1852 struct {
1853 uint8_t port_name[8];
1854 } dprt;
1855
1856 struct {
1857 uint8_t port_name[8];
1858 } dpa;
d8b45213
AV
1859
1860 struct {
1861 uint8_t port_name[8];
1862 } gpsc;
1da177e4
LT
1863 } req;
1864};
1865
1866/* CT command response header */
1867struct ct_rsp_hdr {
1868 struct ct_cmd_hdr header;
1869 uint16_t response;
1870 uint16_t residual;
1871 uint8_t fragment_id;
1872 uint8_t reason_code;
1873 uint8_t explanation_code;
1874 uint8_t vendor_unique;
1875};
1876
1877struct ct_sns_gid_pt_data {
1878 uint8_t control_byte;
1879 uint8_t port_id[3];
1880};
1881
1882struct ct_sns_rsp {
1883 struct ct_rsp_hdr header;
1884
1885 union {
1886 struct {
1887 uint8_t port_type;
1888 uint8_t port_id[3];
1889 uint8_t port_name[8];
1890 uint8_t sym_port_name_len;
1891 uint8_t sym_port_name[255];
1892 uint8_t node_name[8];
1893 uint8_t sym_node_name_len;
1894 uint8_t sym_node_name[255];
1895 uint8_t init_proc_assoc[8];
1896 uint8_t node_ip_addr[16];
1897 uint8_t class_of_service[4];
1898 uint8_t fc4_types[32];
1899 uint8_t ip_address[16];
1900 uint8_t fabric_port_name[8];
1901 uint8_t reserved;
1902 uint8_t hard_address[3];
1903 } ga_nxt;
1904
1905 struct {
1906 struct ct_sns_gid_pt_data entries[MAX_FIBRE_DEVICES];
1907 } gid_pt;
1908
1909 struct {
1910 uint8_t port_name[8];
1911 } gpn_id;
1912
1913 struct {
1914 uint8_t node_name[8];
1915 } gnn_id;
1916
1917 struct {
1918 uint8_t fc4_types[32];
1919 } gft_id;
cca5335c
AV
1920
1921 struct {
1922 uint32_t entry_count;
1923 uint8_t port_name[8];
1924 struct ct_fdmi_hba_attributes attrs;
1925 } ghat;
d8b45213
AV
1926
1927 struct {
1928 uint8_t port_name[8];
1929 } gfpn_id;
1930
1931 struct {
1932 uint16_t speeds;
1933 uint16_t speed;
1934 } gpsc;
1da177e4
LT
1935 } rsp;
1936};
1937
1938struct ct_sns_pkt {
1939 union {
1940 struct ct_sns_req req;
1941 struct ct_sns_rsp rsp;
1942 } p;
1943};
1944
1945/*
1946 * SNS command structures -- for 2200 compatability.
1947 */
1948#define RFT_ID_SNS_SCMD_LEN 22
1949#define RFT_ID_SNS_CMD_SIZE 60
1950#define RFT_ID_SNS_DATA_SIZE 16
1951
1952#define RNN_ID_SNS_SCMD_LEN 10
1953#define RNN_ID_SNS_CMD_SIZE 36
1954#define RNN_ID_SNS_DATA_SIZE 16
1955
1956#define GA_NXT_SNS_SCMD_LEN 6
1957#define GA_NXT_SNS_CMD_SIZE 28
1958#define GA_NXT_SNS_DATA_SIZE (620 + 16)
1959
1960#define GID_PT_SNS_SCMD_LEN 6
1961#define GID_PT_SNS_CMD_SIZE 28
1962#define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES * 4 + 16)
1963
1964#define GPN_ID_SNS_SCMD_LEN 6
1965#define GPN_ID_SNS_CMD_SIZE 28
1966#define GPN_ID_SNS_DATA_SIZE (8 + 16)
1967
1968#define GNN_ID_SNS_SCMD_LEN 6
1969#define GNN_ID_SNS_CMD_SIZE 28
1970#define GNN_ID_SNS_DATA_SIZE (8 + 16)
1971
1972struct sns_cmd_pkt {
1973 union {
1974 struct {
1975 uint16_t buffer_length;
1976 uint16_t reserved_1;
1977 uint32_t buffer_address[2];
1978 uint16_t subcommand_length;
1979 uint16_t reserved_2;
1980 uint16_t subcommand;
1981 uint16_t size;
1982 uint32_t reserved_3;
1983 uint8_t param[36];
1984 } cmd;
1985
1986 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
1987 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
1988 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
1989 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
1990 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
1991 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
1992 } p;
1993};
1994
5433383e
AV
1995struct fw_blob {
1996 char *name;
1997 uint32_t segs[4];
1998 const struct firmware *fw;
1999};
2000
1da177e4
LT
2001/* Return data from MBC_GET_ID_LIST call. */
2002struct gid_list_info {
2003 uint8_t al_pa;
2004 uint8_t area;
fa2a1ce5 2005 uint8_t domain;
1da177e4
LT
2006 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
2007 uint16_t loop_id; /* ISP23XX -- 6 bytes. */
3d71644c 2008 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */
1da177e4
LT
2009};
2010#define GID_LIST_SIZE (sizeof(struct gid_list_info) * MAX_FIBRE_DEVICES)
2011
2c3dfe3f
SJ
2012/* NPIV */
2013typedef struct vport_info {
2014 uint8_t port_name[WWN_SIZE];
2015 uint8_t node_name[WWN_SIZE];
2016 int vp_id;
2017 uint16_t loop_id;
2018 unsigned long host_no;
2019 uint8_t port_id[3];
2020 int loop_state;
2021} vport_info_t;
2022
2023typedef struct vport_params {
2024 uint8_t port_name[WWN_SIZE];
2025 uint8_t node_name[WWN_SIZE];
2026 uint32_t options;
2027#define VP_OPTS_RETRY_ENABLE BIT_0
2028#define VP_OPTS_VP_DISABLE BIT_1
2029} vport_params_t;
2030
2031/* NPIV - return codes of VP create and modify */
2032#define VP_RET_CODE_OK 0
2033#define VP_RET_CODE_FATAL 1
2034#define VP_RET_CODE_WRONG_ID 2
2035#define VP_RET_CODE_WWPN 3
2036#define VP_RET_CODE_RESOURCES 4
2037#define VP_RET_CODE_NO_MEM 5
2038#define VP_RET_CODE_NOT_FOUND 6
2039
abbd8870
AV
2040/*
2041 * ISP operations
2042 */
2043struct isp_operations {
2044
2045 int (*pci_config) (struct scsi_qla_host *);
2046 void (*reset_chip) (struct scsi_qla_host *);
2047 int (*chip_diag) (struct scsi_qla_host *);
2048 void (*config_rings) (struct scsi_qla_host *);
2049 void (*reset_adapter) (struct scsi_qla_host *);
2050 int (*nvram_config) (struct scsi_qla_host *);
2051 void (*update_fw_options) (struct scsi_qla_host *);
2052 int (*load_risc) (struct scsi_qla_host *, uint32_t *);
2053
2054 char * (*pci_info_str) (struct scsi_qla_host *, char *);
2055 char * (*fw_version_str) (struct scsi_qla_host *, char *);
2056
7d12e780 2057 irq_handler_t intr_handler;
abbd8870
AV
2058 void (*enable_intrs) (struct scsi_qla_host *);
2059 void (*disable_intrs) (struct scsi_qla_host *);
2060
2061 int (*abort_command) (struct scsi_qla_host *, srb_t *);
523ec773
AV
2062 int (*target_reset) (struct fc_port *, unsigned int);
2063 int (*lun_reset) (struct fc_port *, unsigned int);
abbd8870
AV
2064 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
2065 uint8_t, uint8_t, uint16_t *, uint8_t);
1c7c6357
AV
2066 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
2067 uint8_t, uint8_t);
abbd8870
AV
2068
2069 uint16_t (*calc_req_entries) (uint16_t);
2070 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
8c958a99 2071 void * (*prep_ms_iocb) (struct scsi_qla_host *, uint32_t, uint32_t);
cca5335c
AV
2072 void * (*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
2073 uint32_t);
abbd8870
AV
2074
2075 uint8_t * (*read_nvram) (struct scsi_qla_host *, uint8_t *,
2076 uint32_t, uint32_t);
2077 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t,
2078 uint32_t);
2079
2080 void (*fw_dump) (struct scsi_qla_host *, int);
f6df144c
AV
2081
2082 int (*beacon_on) (struct scsi_qla_host *);
2083 int (*beacon_off) (struct scsi_qla_host *);
2084 void (*beacon_blink) (struct scsi_qla_host *);
854165f4
AV
2085
2086 uint8_t * (*read_optrom) (struct scsi_qla_host *, uint8_t *,
2087 uint32_t, uint32_t);
2088 int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t,
2089 uint32_t);
30c47662
AV
2090
2091 int (*get_flash_version) (struct scsi_qla_host *, void *);
abbd8870
AV
2092};
2093
a8488abe
AV
2094/* MSI-X Support *************************************************************/
2095
2096#define QLA_MSIX_CHIP_REV_24XX 3
2097#define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7)
2098#define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1)
2099
2100#define QLA_MSIX_DEFAULT 0x00
2101#define QLA_MSIX_RSP_Q 0x01
2102
2103#define QLA_MSIX_ENTRIES 2
2104#define QLA_MIDX_DEFAULT 0
2105#define QLA_MIDX_RSP_Q 1
2106
2107struct scsi_qla_host;
2108
2109struct qla_msix_entry {
2110 int have_irq;
42379b11 2111 uint32_t msix_vector;
a8488abe
AV
2112 uint16_t msix_entry;
2113};
2114
2c3dfe3f
SJ
2115#define WATCH_INTERVAL 1 /* number of seconds */
2116
0971de7f
AV
2117/* Work events. */
2118enum qla_work_type {
2119 QLA_EVT_AEN,
cb8dacbf 2120 QLA_EVT_HWE_LOG,
0971de7f
AV
2121};
2122
2123
2124struct qla_work_evt {
2125 struct list_head list;
2126 enum qla_work_type type;
2127 u32 flags;
2128#define QLA_EVT_FLAG_FREE 0x1
2129
2130 union {
2131 struct {
2132 enum fc_host_event_code code;
2133 u32 data;
2134 } aen;
cb8dacbf
AV
2135 struct {
2136 uint16_t code;
2137 uint16_t d1, d2, d3;
2138 } hwe;
0971de7f
AV
2139 } u;
2140};
2141
4d4df193
HK
2142struct qla_chip_state_84xx {
2143 struct list_head list;
2144 struct kref kref;
2145
2146 void *bus;
2147 spinlock_t access_lock;
2148 struct mutex fw_update_mutex;
2149 uint32_t fw_update;
2150 uint32_t op_fw_version;
2151 uint32_t op_fw_size;
2152 uint32_t op_fw_seq_size;
2153 uint32_t diag_fw_version;
2154 uint32_t gold_fw_version;
2155};
2156
e5f5f6f7
HZ
2157struct qla_statistics {
2158 uint32_t total_isp_aborts;
49fd462a
HZ
2159 uint64_t input_bytes;
2160 uint64_t output_bytes;
e5f5f6f7
HZ
2161};
2162
1da177e4
LT
2163/*
2164 * Linux Host Adapter structure
2165 */
2166typedef struct scsi_qla_host {
2167 struct list_head list;
2168
2169 /* Commonly used flags and state information. */
2170 struct Scsi_Host *host;
2171 struct pci_dev *pdev;
2172
2173 unsigned long host_no;
1da177e4
LT
2174
2175 volatile struct {
2176 uint32_t init_done :1;
2177 uint32_t online :1;
2178 uint32_t mbox_int :1;
2179 uint32_t mbox_busy :1;
2180 uint32_t rscn_queue_overflow :1;
2181 uint32_t reset_active :1;
2182
2183 uint32_t management_server_logged_in :1;
2184 uint32_t process_response_queue :1;
2185
2186 uint32_t disable_risc_code_load :1;
2187 uint32_t enable_64bit_addressing :1;
2188 uint32_t enable_lip_reset :1;
2189 uint32_t enable_lip_full_login :1;
2190 uint32_t enable_target_reset :1;
2191 uint32_t enable_led_scheme :1;
d88021a6 2192 uint32_t inta_enabled :1;
3d71644c
AV
2193 uint32_t msi_enabled :1;
2194 uint32_t msix_enabled :1;
d4c760c2 2195 uint32_t disable_serdes :1;
4346b149 2196 uint32_t gpsc_supported :1;
2c3dfe3f
SJ
2197 uint32_t vsan_enabled :1;
2198 uint32_t npiv_supported :1;
df613b96 2199 uint32_t fce_enabled :1;
cb8dacbf 2200 uint32_t hw_event_marker_found :1;
1da177e4
LT
2201 } flags;
2202
2203 atomic_t loop_state;
2204#define LOOP_TIMEOUT 1
2205#define LOOP_DOWN 2
2206#define LOOP_UP 3
2207#define LOOP_UPDATE 4
2208#define LOOP_READY 5
2209#define LOOP_DEAD 6
2210
2211 unsigned long dpc_flags;
2212#define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
2213#define RESET_ACTIVE 1
2214#define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
2215#define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
2216#define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
2217#define LOOP_RESYNC_ACTIVE 5
2218#define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
2219#define RSCN_UPDATE 7 /* Perform an RSCN update. */
2220#define MAILBOX_RETRY 8
2221#define ISP_RESET_NEEDED 9 /* Initiate a ISP reset. */
2222#define FAILOVER_EVENT_NEEDED 10
2223#define FAILOVER_EVENT 11
2224#define FAILOVER_NEEDED 12
2225#define SCSI_RESTART_NEEDED 13 /* Processes SCSI retry queue. */
2226#define PORT_RESTART_NEEDED 14 /* Processes Retry queue. */
2227#define RESTART_QUEUES_NEEDED 15 /* Restarts the Lun queue. */
2228#define ABORT_QUEUES_NEEDED 16
2229#define RELOGIN_NEEDED 17
2230#define LOGIN_RETRY_NEEDED 18 /* Initiate required fabric logins. */
2231#define REGISTER_FC4_NEEDED 19 /* SNS FC4 registration required. */
2232#define ISP_ABORT_RETRY 20 /* ISP aborted. */
2233#define FCPORT_RESCAN_NEEDED 21 /* IO descriptor processing needed */
2234#define IODESC_PROCESS_NEEDED 22 /* IO descriptor processing needed */
fa2a1ce5 2235#define IOCTL_ERROR_RECOVERY 23
1da177e4 2236#define LOOP_RESET_NEEDED 24
3d71644c 2237#define BEACON_BLINK_NEEDED 25
cca5335c 2238#define REGISTER_FDMI_NEEDED 26
d97994dc 2239#define FCPORT_UPDATE_NEEDED 27
2c3dfe3f 2240#define VP_DPC_NEEDED 28 /* wake up for VP dpc handling */
c795c1e4 2241#define UNLOADING 29
272976ca 2242#define NPIV_CONFIG_NEEDED 30
1da177e4
LT
2243
2244 uint32_t device_flags;
2245#define DFLG_LOCAL_DEVICES BIT_0
2246#define DFLG_RETRY_LOCAL_DEVICES BIT_1
2247#define DFLG_FABRIC_DEVICES BIT_2
2248#define SWITCH_FOUND BIT_3
2249#define DFLG_NO_CABLE BIT_4
2250
c3a2f0df 2251#define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532
4d4df193 2252#define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432
ea5b6382
AV
2253 uint32_t device_type;
2254#define DT_ISP2100 BIT_0
2255#define DT_ISP2200 BIT_1
2256#define DT_ISP2300 BIT_2
2257#define DT_ISP2312 BIT_3
2258#define DT_ISP2322 BIT_4
2259#define DT_ISP6312 BIT_5
2260#define DT_ISP6322 BIT_6
2261#define DT_ISP2422 BIT_7
2262#define DT_ISP2432 BIT_8
044cc6c8
AV
2263#define DT_ISP5422 BIT_9
2264#define DT_ISP5432 BIT_10
c3a2f0df 2265#define DT_ISP2532 BIT_11
4d4df193
HK
2266#define DT_ISP8432 BIT_12
2267#define DT_ISP_LAST (DT_ISP8432 << 1)
ea5b6382 2268
c76f2c01 2269#define DT_IIDMA BIT_26
e428924c 2270#define DT_FWI2 BIT_27
4a59f71d 2271#define DT_ZIO_SUPPORTED BIT_28
ea5b6382
AV
2272#define DT_OEM_001 BIT_29
2273#define DT_ISP2200A BIT_30
2274#define DT_EXTENDED_IDS BIT_31
2275
2276#define DT_MASK(ha) ((ha)->device_type & (DT_ISP_LAST - 1))
2277#define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100)
2278#define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200)
2279#define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300)
2280#define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312)
2281#define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322)
2282#define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312)
2283#define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322)
2284#define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422)
2285#define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432)
044cc6c8
AV
2286#define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422)
2287#define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432)
c3a2f0df 2288#define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532)
4d4df193 2289#define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432)
ea5b6382
AV
2290
2291#define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
2292 IS_QLA6312(ha) || IS_QLA6322(ha))
2293#define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
044cc6c8 2294#define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha))
c3a2f0df 2295#define IS_QLA25XX(ha) (IS_QLA2532(ha))
4d4df193
HK
2296#define IS_QLA84XX(ha) (IS_QLA8432(ha))
2297#define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \
2298 IS_QLA84XX(ha))
ea5b6382 2299
c76f2c01 2300#define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA)
e428924c 2301#define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2)
4a59f71d 2302#define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED)
ea5b6382
AV
2303#define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001)
2304#define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS)
2305
1da177e4
LT
2306 /* SRB cache. */
2307#define SRB_MIN_REQ 128
2308 mempool_t *srb_mempool;
2309
fa2a1ce5 2310 /* This spinlock is used to protect "io transactions", you must
0418726b 2311 * acquire it before doing any IO to the card, eg with RD_REG*() and
1da177e4
LT
2312 * WRT_REG*() for the duration of your entire commandtransaction.
2313 *
2314 * This spinlock is of lower priority than the io request lock.
2315 */
2316
2317 spinlock_t hardware_lock ____cacheline_aligned;
2318
285d0321 2319 int bars;
09483916 2320 int mem_only;
1da177e4 2321 device_reg_t __iomem *iobase; /* Base I/O address */
3776541d 2322 resource_size_t pio_address;
1da177e4
LT
2323#define MIN_IOBASE_LEN 0x100
2324
2325 /* ISP ring lock, rings, and indexes */
2326 dma_addr_t request_dma; /* Physical address. */
2327 request_t *request_ring; /* Base virtual address */
2328 request_t *request_ring_ptr; /* Current address. */
2329 uint16_t req_ring_index; /* Current index. */
2330 uint16_t req_q_cnt; /* Number of available entries. */
2331 uint16_t request_q_length;
2332
2333 dma_addr_t response_dma; /* Physical address. */
2334 response_t *response_ring; /* Base virtual address */
2335 response_t *response_ring_ptr; /* Current address. */
2336 uint16_t rsp_ring_index; /* Current index. */
2337 uint16_t response_q_length;
fa2a1ce5 2338
fd34f556 2339 struct isp_operations *isp_ops;
1da177e4
LT
2340
2341 /* Outstandings ISP commands. */
2342 srb_t *outstanding_cmds[MAX_OUTSTANDING_COMMANDS];
fa2a1ce5 2343 uint32_t current_outstanding_cmd;
1da177e4
LT
2344 srb_t *status_srb; /* Status continuation entry. */
2345
1da177e4
LT
2346 /* ISP configuration data. */
2347 uint16_t loop_id; /* Host adapter loop id */
2c3dfe3f
SJ
2348 uint16_t switch_cap;
2349#define FLOGI_SEQ_DEL BIT_8
2350#define FLOGI_MID_SUPPORT BIT_10
2351#define FLOGI_VSAN_SUPPORT BIT_12
2352#define FLOGI_SP_SUPPORT BIT_13
1da177e4
LT
2353 uint16_t fb_rev;
2354
2355 port_id_t d_id; /* Host adapter port id */
2356 uint16_t max_public_loop_ids;
2357 uint16_t min_external_loopid; /* First external loop Id */
2358
d8b45213
AV
2359#define PORT_SPEED_UNKNOWN 0xFFFF
2360#define PORT_SPEED_1GB 0x00
2361#define PORT_SPEED_2GB 0x01
2362#define PORT_SPEED_4GB 0x03
c3a2f0df 2363#define PORT_SPEED_8GB 0x04
1da177e4
LT
2364 uint16_t link_data_rate; /* F/W operating speed */
2365
2366 uint8_t current_topology;
2367 uint8_t prev_topology;
2368#define ISP_CFG_NL 1
2369#define ISP_CFG_N 2
2370#define ISP_CFG_FL 4
2371#define ISP_CFG_F 8
2372
2373 uint8_t operating_mode; /* F/W operating mode */
2374#define LOOP 0
2375#define P2P 1
2376#define LOOP_P2P 2
2377#define P2P_LOOP 3
2378
fa2a1ce5 2379 uint8_t marker_needed;
1da177e4
LT
2380
2381 uint8_t interrupts_on;
2382
2383 /* HBA serial number */
2384 uint8_t serial0;
2385 uint8_t serial1;
2386 uint8_t serial2;
2387
2388 /* NVRAM configuration data */
281afe19
SJ
2389#define MAX_NVRAM_SIZE 4096
2390#define VPD_OFFSET MAX_NVRAM_SIZE / 2
3d71644c 2391 uint16_t nvram_size;
1da177e4 2392 uint16_t nvram_base;
281afe19 2393 void *nvram;
6f641790
AV
2394 uint16_t vpd_size;
2395 uint16_t vpd_base;
281afe19 2396 void *vpd;
1da177e4
LT
2397
2398 uint16_t loop_reset_delay;
1da177e4
LT
2399 uint8_t retry_count;
2400 uint8_t login_timeout;
2401 uint16_t r_a_tov;
2402 int port_down_retry_count;
1da177e4 2403 uint8_t mbx_count;
1da177e4 2404 uint16_t last_loop_id;
cca5335c 2405 uint16_t mgmt_svr_loop_id;
1da177e4 2406
fa2a1ce5 2407 uint32_t login_retry_count;
df7baa50 2408 int max_q_depth;
1da177e4 2409
0971de7f
AV
2410 struct list_head work_list;
2411
1da177e4
LT
2412 /* Fibre Channel Device List. */
2413 struct list_head fcports;
1da177e4 2414
1da177e4
LT
2415 /* RSCN queue. */
2416 uint32_t rscn_queue[MAX_RSCN_COUNT];
2417 uint8_t rscn_in_ptr;
2418 uint8_t rscn_out_ptr;
2419
2420 /* SNS command interfaces. */
2421 ms_iocb_entry_t *ms_iocb;
2422 dma_addr_t ms_iocb_dma;
2423 struct ct_sns_pkt *ct_sns;
2424 dma_addr_t ct_sns_dma;
2425 /* SNS command interfaces for 2200. */
2426 struct sns_cmd_pkt *sns_cmd;
2427 dma_addr_t sns_cmd_dma;
2428
88729e53
AV
2429#define SFP_DEV_SIZE 256
2430#define SFP_BLOCK_SIZE 64
2431 void *sfp_data;
2432 dma_addr_t sfp_data_dma;
2433
39a11240 2434 struct task_struct *dpc_thread;
1da177e4
LT
2435 uint8_t dpc_active; /* DPC routine is active */
2436
2437 /* Timeout timers. */
1da177e4
LT
2438 uint8_t loop_down_abort_time; /* port down timer */
2439 atomic_t loop_down_timer; /* loop down timer */
2440 uint8_t link_down_timeout; /* link down timeout */
2441
2442 uint32_t timer_active;
2443 struct timer_list timer;
2444
2445 dma_addr_t gid_list_dma;
2446 struct gid_list_info *gid_list;
abbd8870 2447 int gid_list_info_size;
1da177e4 2448
fa2a1ce5 2449 /* Small DMA pool allocations -- maximum 256 bytes in length. */
1da177e4
LT
2450#define DMA_POOL_SIZE 256
2451 struct dma_pool *s_dma_pool;
2452
2453 dma_addr_t init_cb_dma;
3d71644c
AV
2454 init_cb_t *init_cb;
2455 int init_cb_size;
1da177e4 2456
1da177e4
LT
2457 /* These are used by mailbox operations. */
2458 volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
2459
2460 mbx_cmd_t *mcp;
2461 unsigned long mbx_cmd_flags;
2462#define MBX_INTERRUPT 1
2463#define MBX_INTR_WAIT 2
2464#define MBX_UPDATE_FLASH_ACTIVE 3
2465
6c2f527c 2466 struct mutex vport_lock; /* Virtual port synchronization */
0b05a1f0
MB
2467 struct completion mbx_cmd_comp; /* Serialize mbx access */
2468 struct completion mbx_intr_comp; /* Used for completion notification */
1da177e4
LT
2469
2470 uint32_t mbx_flags;
2471#define MBX_IN_PROGRESS BIT_0
2472#define MBX_BUSY BIT_1 /* Got the Access */
fa2a1ce5 2473#define MBX_SLEEPING_ON_SEM BIT_2
1da177e4
LT
2474#define MBX_POLLING_FOR_COMP BIT_3
2475#define MBX_COMPLETED BIT_4
fa2a1ce5 2476#define MBX_TIMEDOUT BIT_5
1da177e4
LT
2477#define MBX_ACCESS_TIMEDOUT BIT_6
2478
1da177e4 2479 /* Basic firmware related information. */
1da177e4
LT
2480 uint16_t fw_major_version;
2481 uint16_t fw_minor_version;
2482 uint16_t fw_subminor_version;
2483 uint16_t fw_attributes;
2484 uint32_t fw_memory_size;
2485 uint32_t fw_transfer_size;
441d1072
AV
2486 uint32_t fw_srisc_address;
2487#define RISC_START_ADDRESS_2100 0x1000
2488#define RISC_START_ADDRESS_2300 0x800
2489#define RISC_START_ADDRESS_2400 0x100000
1da177e4
LT
2490
2491 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
2492 uint8_t fw_seriallink_options[4];
3d71644c 2493 uint16_t fw_seriallink_options24[4];
1da177e4
LT
2494
2495 /* Firmware dump information. */
a7a167bf
AV
2496 struct qla2xxx_fw_dump *fw_dump;
2497 uint32_t fw_dump_len;
d4e3e04d 2498 int fw_dumped;
1da177e4 2499 int fw_dump_reading;
a7a167bf
AV
2500 dma_addr_t eft_dma;
2501 void *eft;
1da177e4 2502
df613b96
AV
2503 struct dentry *dfs_dir;
2504 struct dentry *dfs_fce;
2505 dma_addr_t fce_dma;
2506 void *fce;
2507 uint32_t fce_bufs;
2508 uint16_t fce_mb[8];
2509 uint64_t fce_wr, fce_rd;
2510 struct mutex fce_mutex;
2511
cb8dacbf
AV
2512 uint32_t hw_event_ptr;
2513 uint32_t hw_event_pause_errors;
2514
1da177e4 2515 uint8_t host_str[16];
3d71644c 2516 uint32_t pci_attr;
a8488abe 2517 uint16_t chip_revision;
1da177e4
LT
2518
2519 uint16_t product_id[4];
2520
2521 uint8_t model_number[16+1];
2522#define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
1ee27146 2523 char model_desc[80];
cca5335c 2524 uint8_t adapter_id[16+1];
1da177e4 2525
3d71644c
AV
2526 uint8_t *node_name;
2527 uint8_t *port_name;
90991c85 2528 uint8_t fabric_node_name[WWN_SIZE];
1da177e4
LT
2529 uint32_t isp_abort_cnt;
2530
854165f4
AV
2531 /* Option ROM information. */
2532 char *optrom_buffer;
2533 uint32_t optrom_size;
2534 int optrom_state;
2535#define QLA_SWAITING 0
2536#define QLA_SREADING 1
2537#define QLA_SWRITING 2
b7cc176c
JC
2538 uint32_t optrom_region_start;
2539 uint32_t optrom_region_size;
854165f4 2540
30c47662
AV
2541 /* PCI expansion ROM image information. */
2542#define ROM_CODE_TYPE_BIOS 0
2543#define ROM_CODE_TYPE_FCODE 1
2544#define ROM_CODE_TYPE_EFI 3
2545 uint8_t bios_revision[2];
2546 uint8_t efi_revision[2];
2547 uint8_t fcode_revision[16];
2548 uint32_t fw_revision[4];
2549
7d232c74
AV
2550 uint32_t fdt_wrt_disable;
2551 uint32_t fdt_erase_cmd;
2552 uint32_t fdt_block_size;
2553 uint32_t fdt_unprotect_sec_cmd;
2554 uint32_t fdt_protect_sec_cmd;
2555
c00d8994
AV
2556 uint32_t flt_region_flt;
2557 uint32_t flt_region_fdt;
2558 uint32_t flt_region_boot;
2559 uint32_t flt_region_fw;
2560 uint32_t flt_region_vpd_nvram;
2561 uint32_t flt_region_hw_event;
272976ca 2562 uint32_t flt_region_npiv_conf;
c00d8994 2563
1da177e4
LT
2564 /* Needed for BEACON */
2565 uint16_t beacon_blink_led;
f6df144c
AV
2566 uint8_t beacon_color_state;
2567#define QLA_LED_GRN_ON 0x01
2568#define QLA_LED_YLW_ON 0x02
2569#define QLA_LED_ABR_ON 0x04
2570#define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */
2571 /* ISP2322: red, green, amber. */
4fdfefe5
AV
2572
2573 uint16_t zio_mode;
2574 uint16_t zio_timer;
392e2f65 2575 struct fc_host_statistics fc_host_stat;
a8488abe
AV
2576
2577 struct qla_msix_entry msix_entries[QLA_MSIX_ENTRIES];
2c3dfe3f
SJ
2578
2579 struct list_head vp_list; /* list of VP */
2580 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */
eb66dc60 2581 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) / sizeof(unsigned long)];
2c3dfe3f
SJ
2582 uint16_t num_vhosts; /* number of vports created */
2583 uint16_t num_vsans; /* number of vsan created */
2584 uint16_t vp_idx; /* vport ID */
2585
2586 struct scsi_qla_host *parent; /* holds pport */
2587 unsigned long vp_flags;
2588 struct list_head vp_fcports; /* list of fcports */
2589#define VP_IDX_ACQUIRED 0 /* bit no 0 */
2590#define VP_CREATE_NEEDED 1
2591#define VP_BIND_NEEDED 2
2592#define VP_DELETE_NEEDED 3
2593#define VP_SCR_NEEDED 4 /* State Change Request registration */
2594 atomic_t vp_state;
2595#define VP_OFFLINE 0
2596#define VP_ACTIVE 1
2597#define VP_FAILED 2
2598// #define VP_DISABLE 3
2599 uint16_t vp_err_state;
2600 uint16_t vp_prev_err_state;
2601#define VP_ERR_UNKWN 0
2602#define VP_ERR_PORTDWN 1
2603#define VP_ERR_FAB_UNSUPPORTED 2
2604#define VP_ERR_FAB_NORESOURCES 3
2605#define VP_ERR_FAB_LOGOUT 4
2606#define VP_ERR_ADAP_NORESOURCES 5
4d0ea247 2607 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */
2c3dfe3f 2608 int cur_vport_count;
4d4df193
HK
2609
2610 struct qla_chip_state_84xx *cs84xx;
e5f5f6f7 2611 struct qla_statistics qla_stats;
1da177e4
LT
2612} scsi_qla_host_t;
2613
2614
2615/*
2616 * Macros to help code, maintain, etc.
2617 */
2618#define LOOP_TRANSITION(ha) \
2619 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
23443b1d 2620 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
1da177e4 2621 atomic_read(&ha->loop_state) == LOOP_DOWN)
fa2a1ce5 2622
1da177e4
LT
2623#define qla_printk(level, ha, format, arg...) \
2624 dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
2625
2626/*
2627 * qla2x00 local function return status codes
2628 */
2629#define MBS_MASK 0x3fff
2630
2631#define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
2632#define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
2633#define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
2634#define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
2635#define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
2636#define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
2637#define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
2638#define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
2639#define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
2640#define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
2641
2642#define QLA_FUNCTION_TIMEOUT 0x100
2643#define QLA_FUNCTION_PARAMETER_ERROR 0x101
2644#define QLA_FUNCTION_FAILED 0x102
2645#define QLA_MEMORY_ALLOC_FAILED 0x103
2646#define QLA_LOCK_TIMEOUT 0x104
2647#define QLA_ABORTED 0x105
2648#define QLA_SUSPENDED 0x106
2649#define QLA_BUSY 0x107
2650#define QLA_RSCNS_HANDLED 0x108
cca5335c 2651#define QLA_ALREADY_REGISTERED 0x109
1da177e4 2652
1da177e4
LT
2653#define NVRAM_DELAY() udelay(10)
2654
2655#define INVALID_HANDLE (MAX_OUTSTANDING_COMMANDS+1)
2656
2657/*
2658 * Flash support definitions
2659 */
854165f4
AV
2660#define OPTROM_SIZE_2300 0x20000
2661#define OPTROM_SIZE_2322 0x100000
2662#define OPTROM_SIZE_24XX 0x100000
c3a2f0df 2663#define OPTROM_SIZE_25XX 0x200000
1da177e4
LT
2664
2665#include "qla_gbl.h"
2666#include "qla_dbg.h"
2667#include "qla_inline.h"
1da177e4 2668
1da177e4
LT
2669#define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
2670#define CMD_COMPL_STATUS(Cmnd) ((Cmnd)->SCp.this_residual)
2671#define CMD_RESID_LEN(Cmnd) ((Cmnd)->SCp.buffers_residual)
2672#define CMD_SCSI_STATUS(Cmnd) ((Cmnd)->SCp.Status)
2673#define CMD_ACTUAL_SNSLEN(Cmnd) ((Cmnd)->SCp.Message)
2674#define CMD_ENTRY_STATUS(Cmnd) ((Cmnd)->SCp.have_data_in)
2675
2676#endif