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Commit | Line | Data |
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fa90c54f AV |
1 | /* |
2 | * QLogic Fibre Channel HBA Driver | |
bd21eaf9 | 3 | * Copyright (c) 2003-2014 QLogic Corporation |
fa90c54f AV |
4 | * |
5 | * See LICENSE.qla2xxx for copyright and licensing details. | |
6 | */ | |
1da177e4 LT |
7 | #ifndef __QLA_DEF_H |
8 | #define __QLA_DEF_H | |
9 | ||
10 | #include <linux/kernel.h> | |
11 | #include <linux/init.h> | |
12 | #include <linux/types.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/list.h> | |
15 | #include <linux/pci.h> | |
16 | #include <linux/dma-mapping.h> | |
17 | #include <linux/sched.h> | |
18 | #include <linux/slab.h> | |
19 | #include <linux/dmapool.h> | |
20 | #include <linux/mempool.h> | |
21 | #include <linux/spinlock.h> | |
22 | #include <linux/completion.h> | |
abbd8870 | 23 | #include <linux/interrupt.h> |
19a7b4ae | 24 | #include <linux/workqueue.h> |
5433383e | 25 | #include <linux/firmware.h> |
14e660e6 | 26 | #include <linux/aer.h> |
4d4df193 | 27 | #include <linux/mutex.h> |
482c9dc7 | 28 | #include <linux/btree.h> |
1da177e4 LT |
29 | |
30 | #include <scsi/scsi.h> | |
31 | #include <scsi/scsi_host.h> | |
32 | #include <scsi/scsi_device.h> | |
33 | #include <scsi/scsi_cmnd.h> | |
392e2f65 | 34 | #include <scsi/scsi_transport_fc.h> |
9a069e19 | 35 | #include <scsi/scsi_bsg_fc.h> |
1da177e4 | 36 | |
df95f39a BVA |
37 | /* Big endian Fibre Channel S_ID (source ID) or D_ID (destination ID). */ |
38 | typedef struct { | |
39 | uint8_t domain; | |
40 | uint8_t area; | |
41 | uint8_t al_pa; | |
42 | } be_id_t; | |
43 | ||
44 | /* Little endian Fibre Channel S_ID (source ID) or D_ID (destination ID). */ | |
45 | typedef struct { | |
46 | uint8_t al_pa; | |
47 | uint8_t area; | |
48 | uint8_t domain; | |
49 | } le_id_t; | |
50 | ||
6e98016c | 51 | #include "qla_bsg.h" |
15b7a68c | 52 | #include "qla_dsd.h" |
a9083016 | 53 | #include "qla_nx.h" |
7ec0effd | 54 | #include "qla_nx2.h" |
e84067d7 | 55 | #include "qla_nvme.h" |
6a03b4cd HZ |
56 | #define QLA2XXX_DRIVER_NAME "qla2xxx" |
57 | #define QLA2XXX_APIDEV "ql2xapidev" | |
f24b697b | 58 | #define QLA2XXX_MANUFACTURER "QLogic Corporation" |
cb63067a | 59 | |
1da177e4 LT |
60 | /* |
61 | * We have MAILBOX_REGISTER_COUNT sized arrays in a few places, | |
62 | * but that's fine as we don't look at the last 24 ones for | |
63 | * ISP2100 HBAs. | |
64 | */ | |
65 | #define MAILBOX_REGISTER_COUNT_2100 8 | |
67ddda35 | 66 | #define MAILBOX_REGISTER_COUNT_2200 24 |
1da177e4 LT |
67 | #define MAILBOX_REGISTER_COUNT 32 |
68 | ||
69 | #define QLA2200A_RISC_ROM_VER 4 | |
70 | #define FPM_2300 6 | |
71 | #define FPM_2310 7 | |
72 | ||
73 | #include "qla_settings.h" | |
74 | ||
726b8548 QT |
75 | #define MODE_DUAL (MODE_TARGET | MODE_INITIATOR) |
76 | ||
fa2a1ce5 | 77 | /* |
1da177e4 LT |
78 | * Data bit definitions |
79 | */ | |
80 | #define BIT_0 0x1 | |
81 | #define BIT_1 0x2 | |
82 | #define BIT_2 0x4 | |
83 | #define BIT_3 0x8 | |
84 | #define BIT_4 0x10 | |
85 | #define BIT_5 0x20 | |
86 | #define BIT_6 0x40 | |
87 | #define BIT_7 0x80 | |
88 | #define BIT_8 0x100 | |
89 | #define BIT_9 0x200 | |
90 | #define BIT_10 0x400 | |
91 | #define BIT_11 0x800 | |
92 | #define BIT_12 0x1000 | |
93 | #define BIT_13 0x2000 | |
94 | #define BIT_14 0x4000 | |
95 | #define BIT_15 0x8000 | |
96 | #define BIT_16 0x10000 | |
97 | #define BIT_17 0x20000 | |
98 | #define BIT_18 0x40000 | |
99 | #define BIT_19 0x80000 | |
100 | #define BIT_20 0x100000 | |
101 | #define BIT_21 0x200000 | |
102 | #define BIT_22 0x400000 | |
103 | #define BIT_23 0x800000 | |
104 | #define BIT_24 0x1000000 | |
105 | #define BIT_25 0x2000000 | |
106 | #define BIT_26 0x4000000 | |
107 | #define BIT_27 0x8000000 | |
108 | #define BIT_28 0x10000000 | |
109 | #define BIT_29 0x20000000 | |
110 | #define BIT_30 0x40000000 | |
111 | #define BIT_31 0x80000000 | |
112 | ||
113 | #define LSB(x) ((uint8_t)(x)) | |
114 | #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8)) | |
115 | ||
116 | #define LSW(x) ((uint16_t)(x)) | |
117 | #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16)) | |
118 | ||
119 | #define LSD(x) ((uint32_t)((uint64_t)(x))) | |
120 | #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16)) | |
121 | ||
2afa19a9 | 122 | #define MAKE_HANDLE(x, y) ((uint32_t)((((uint32_t)(x)) << 16) | (uint32_t)(y))) |
1da177e4 LT |
123 | |
124 | /* | |
125 | * I/O register | |
126 | */ | |
127 | ||
128 | #define RD_REG_BYTE(addr) readb(addr) | |
129 | #define RD_REG_WORD(addr) readw(addr) | |
130 | #define RD_REG_DWORD(addr) readl(addr) | |
131 | #define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr) | |
132 | #define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr) | |
133 | #define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr) | |
c1c7178c BVA |
134 | #define WRT_REG_BYTE(addr, data) writeb(data, addr) |
135 | #define WRT_REG_WORD(addr, data) writew(data, addr) | |
136 | #define WRT_REG_DWORD(addr, data) writel(data, addr) | |
1da177e4 | 137 | |
7d613ac6 SV |
138 | /* |
139 | * ISP83XX specific remote register addresses | |
140 | */ | |
141 | #define QLA83XX_LED_PORT0 0x00201320 | |
142 | #define QLA83XX_LED_PORT1 0x00201328 | |
143 | #define QLA83XX_IDC_DEV_STATE 0x22102384 | |
144 | #define QLA83XX_IDC_MAJOR_VERSION 0x22102380 | |
145 | #define QLA83XX_IDC_MINOR_VERSION 0x22102398 | |
146 | #define QLA83XX_IDC_DRV_PRESENCE 0x22102388 | |
147 | #define QLA83XX_IDC_DRIVER_ACK 0x2210238c | |
148 | #define QLA83XX_IDC_CONTROL 0x22102390 | |
149 | #define QLA83XX_IDC_AUDIT 0x22102394 | |
150 | #define QLA83XX_IDC_LOCK_RECOVERY 0x2210239c | |
151 | #define QLA83XX_DRIVER_LOCKID 0x22102104 | |
152 | #define QLA83XX_DRIVER_LOCK 0x8111c028 | |
153 | #define QLA83XX_DRIVER_UNLOCK 0x8111c02c | |
154 | #define QLA83XX_FLASH_LOCKID 0x22102100 | |
155 | #define QLA83XX_FLASH_LOCK 0x8111c010 | |
156 | #define QLA83XX_FLASH_UNLOCK 0x8111c014 | |
157 | #define QLA83XX_DEV_PARTINFO1 0x221023e0 | |
158 | #define QLA83XX_DEV_PARTINFO2 0x221023e4 | |
159 | #define QLA83XX_FW_HEARTBEAT 0x221020b0 | |
160 | #define QLA83XX_PEG_HALT_STATUS1 0x221020a8 | |
161 | #define QLA83XX_PEG_HALT_STATUS2 0x221020ac | |
162 | ||
163 | /* 83XX: Macros defining 8200 AEN Reason codes */ | |
164 | #define IDC_DEVICE_STATE_CHANGE BIT_0 | |
165 | #define IDC_PEG_HALT_STATUS_CHANGE BIT_1 | |
166 | #define IDC_NIC_FW_REPORTED_FAILURE BIT_2 | |
167 | #define IDC_HEARTBEAT_FAILURE BIT_3 | |
168 | ||
169 | /* 83XX: Macros defining 8200 AEN Error-levels */ | |
170 | #define ERR_LEVEL_NON_FATAL 0x1 | |
171 | #define ERR_LEVEL_RECOVERABLE_FATAL 0x2 | |
172 | #define ERR_LEVEL_UNRECOVERABLE_FATAL 0x4 | |
173 | ||
174 | /* 83XX: Macros for IDC Version */ | |
175 | #define QLA83XX_SUPP_IDC_MAJOR_VERSION 0x01 | |
176 | #define QLA83XX_SUPP_IDC_MINOR_VERSION 0x0 | |
177 | ||
178 | /* 83XX: Macros for scheduling dpc tasks */ | |
179 | #define QLA83XX_NIC_CORE_RESET 0x1 | |
180 | #define QLA83XX_IDC_STATE_HANDLER 0x2 | |
181 | #define QLA83XX_NIC_CORE_UNRECOVERABLE 0x3 | |
182 | ||
183 | /* 83XX: Macros for defining IDC-Control bits */ | |
184 | #define QLA83XX_IDC_RESET_DISABLED BIT_0 | |
185 | #define QLA83XX_IDC_GRACEFUL_RESET BIT_1 | |
186 | ||
187 | /* 83XX: Macros for different timeouts */ | |
188 | #define QLA83XX_IDC_INITIALIZATION_TIMEOUT 30 | |
189 | #define QLA83XX_IDC_RESET_ACK_TIMEOUT 10 | |
190 | #define QLA83XX_MAX_LOCK_RECOVERY_WAIT (2 * HZ) | |
191 | ||
192 | /* 83XX: Macros for defining class in DEV-Partition Info register */ | |
193 | #define QLA83XX_CLASS_TYPE_NONE 0x0 | |
194 | #define QLA83XX_CLASS_TYPE_NIC 0x1 | |
195 | #define QLA83XX_CLASS_TYPE_FCOE 0x2 | |
196 | #define QLA83XX_CLASS_TYPE_ISCSI 0x3 | |
197 | ||
198 | /* 83XX: Macros for IDC Lock-Recovery stages */ | |
199 | #define IDC_LOCK_RECOVERY_STAGE1 0x1 /* Stage1: Intent for | |
200 | * lock-recovery | |
201 | */ | |
202 | #define IDC_LOCK_RECOVERY_STAGE2 0x2 /* Stage2: Perform lock-recovery */ | |
203 | ||
204 | /* 83XX: Macros for IDC Audit type */ | |
205 | #define IDC_AUDIT_TIMESTAMP 0x0 /* IDC-AUDIT: Record timestamp of | |
206 | * dev-state change to NEED-RESET | |
207 | * or NEED-QUIESCENT | |
208 | */ | |
209 | #define IDC_AUDIT_COMPLETION 0x1 /* IDC-AUDIT: Record duration of | |
210 | * reset-recovery completion is | |
211 | * second | |
212 | */ | |
2d5a4c34 HM |
213 | /* ISP2031: Values for laser on/off */ |
214 | #define PORT_0_2031 0x00201340 | |
215 | #define PORT_1_2031 0x00201350 | |
216 | #define LASER_ON_2031 0x01800100 | |
217 | #define LASER_OFF_2031 0x01800180 | |
7d613ac6 | 218 | |
f6df144c AV |
219 | /* |
220 | * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an | |
221 | * 133Mhz slot. | |
222 | */ | |
223 | #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr)) | |
c1c7178c | 224 | #define WRT_REG_WORD_PIO(addr, data) (outw(data, (unsigned long)addr)) |
f6df144c | 225 | |
1da177e4 LT |
226 | /* |
227 | * Fibre Channel device definitions. | |
228 | */ | |
229 | #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */ | |
642ef983 CD |
230 | #define MAX_FIBRE_DEVICES_2100 512 |
231 | #define MAX_FIBRE_DEVICES_2400 2048 | |
232 | #define MAX_FIBRE_DEVICES_LOOP 128 | |
233 | #define MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400 | |
5f16b331 | 234 | #define LOOPID_MAP_SIZE (ha->max_fibre_devices) |
cc4731f5 | 235 | #define MAX_FIBRE_LUNS 0xFFFF |
1da177e4 LT |
236 | #define MAX_HOST_COUNT 16 |
237 | ||
238 | /* | |
239 | * Host adapter default definitions. | |
240 | */ | |
241 | #define MAX_BUSES 1 /* We only have one bus today */ | |
1da177e4 LT |
242 | #define MIN_LUNS 8 |
243 | #define MAX_LUNS MAX_FIBRE_LUNS | |
fa2a1ce5 AV |
244 | #define MAX_CMDS_PER_LUN 255 |
245 | ||
1da177e4 LT |
246 | /* |
247 | * Fibre Channel device definitions. | |
248 | */ | |
249 | #define SNS_LAST_LOOP_ID_2100 0xfe | |
250 | #define SNS_LAST_LOOP_ID_2300 0x7ff | |
251 | ||
252 | #define LAST_LOCAL_LOOP_ID 0x7d | |
253 | #define SNS_FL_PORT 0x7e | |
254 | #define FABRIC_CONTROLLER 0x7f | |
255 | #define SIMPLE_NAME_SERVER 0x80 | |
256 | #define SNS_FIRST_LOOP_ID 0x81 | |
257 | #define MANAGEMENT_SERVER 0xfe | |
258 | #define BROADCAST 0xff | |
259 | ||
3d71644c AV |
260 | /* |
261 | * There is no correspondence between an N-PORT id and an AL_PA. Therefore the | |
262 | * valid range of an N-PORT id is 0 through 0x7ef. | |
263 | */ | |
1429f044 | 264 | #define NPH_LAST_HANDLE 0x7ee |
265 | #define NPH_MGMT_SERVER 0x7ef /* FFFFEF */ | |
3d71644c AV |
266 | #define NPH_SNS 0x7fc /* FFFFFC */ |
267 | #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */ | |
268 | #define NPH_F_PORT 0x7fe /* FFFFFE */ | |
269 | #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */ | |
270 | ||
b98ae0d7 QT |
271 | #define NPH_SNS_LID(ha) (IS_FWI2_CAPABLE(ha) ? NPH_SNS : SIMPLE_NAME_SERVER) |
272 | ||
3d71644c AV |
273 | #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */ |
274 | #include "qla_fw.h" | |
726b8548 QT |
275 | |
276 | struct name_list_extended { | |
277 | struct get_name_list_extended *l; | |
278 | dma_addr_t ldma; | |
1c6cacf4 | 279 | struct list_head fcports; |
726b8548 | 280 | u32 size; |
0aca7784 | 281 | u8 sent; |
726b8548 | 282 | }; |
1da177e4 LT |
283 | /* |
284 | * Timeout timer counts in seconds | |
285 | */ | |
8482e118 | 286 | #define PORT_RETRY_TIME 1 |
1da177e4 LT |
287 | #define LOOP_DOWN_TIMEOUT 60 |
288 | #define LOOP_DOWN_TIME 255 /* 240 */ | |
289 | #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30) | |
290 | ||
e7b42e33 | 291 | #define DEFAULT_OUTSTANDING_COMMANDS 4096 |
8d93f550 | 292 | #define MIN_OUTSTANDING_COMMANDS 128 |
1da177e4 LT |
293 | |
294 | /* ISP request and response entry counts (37-65535) */ | |
295 | #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */ | |
296 | #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */ | |
d743de66 | 297 | #define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */ |
f2ea653f | 298 | #define REQUEST_ENTRY_CNT_83XX 8192 /* Number of request entries. */ |
e7b42e33 | 299 | #define RESPONSE_ENTRY_CNT_83XX 4096 /* Number of response entries.*/ |
1da177e4 LT |
300 | #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/ |
301 | #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/ | |
2afa19a9 | 302 | #define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/ |
2d70c103 | 303 | #define ATIO_ENTRY_CNT_24XX 4096 /* Number of ATIO entries. */ |
8ae6d9c7 | 304 | #define RESPONSE_ENTRY_CNT_FX00 256 /* Number of response entries.*/ |
99e1b683 | 305 | #define FW_DEF_EXCHANGES_CNT 2048 |
d1e3635a QT |
306 | #define FW_MAX_EXCHANGES_CNT (32 * 1024) |
307 | #define REDUCE_EXCHANGES_CNT (8 * 1024) | |
1da177e4 | 308 | |
17d98630 | 309 | struct req_que; |
a6ca8878 | 310 | struct qla_tgt_sess; |
17d98630 | 311 | |
1da177e4 | 312 | /* |
fa2a1ce5 | 313 | * SCSI Request Block |
1da177e4 | 314 | */ |
9ba56b95 | 315 | struct srb_cmd { |
1da177e4 | 316 | struct scsi_cmnd *cmd; /* Linux SCSI command pkt */ |
1da177e4 | 317 | uint32_t request_sense_length; |
8ae6d9c7 | 318 | uint32_t fw_sense_length; |
1da177e4 | 319 | uint8_t *request_sense_ptr; |
5ec9f904 BVA |
320 | struct ct6_dsd *ct6_ctx; |
321 | struct crc_context *crc_ctx; | |
9ba56b95 | 322 | }; |
1da177e4 LT |
323 | |
324 | /* | |
325 | * SRB flag definitions | |
326 | */ | |
bad75002 AE |
327 | #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */ |
328 | #define SRB_FCP_CMND_DMA_VALID BIT_12 /* DIF: DSD List valid */ | |
329 | #define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */ | |
330 | #define SRB_CRC_PROT_DMA_VALID BIT_4 /* DIF: prot DMA valid */ | |
331 | #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */ | |
f6145e86 | 332 | #define SRB_WAKEUP_ON_COMP BIT_6 |
50b81275 | 333 | #define SRB_DIF_BUNDL_DMA_VALID BIT_7 /* DIF: DMA list valid */ |
bad75002 AE |
334 | |
335 | /* To identify if a srb is of T10-CRC type. @sp => srb_t pointer */ | |
336 | #define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID) | |
1da177e4 | 337 | |
2d73ac61 QT |
338 | /* |
339 | * 24 bit port ID type definition. | |
340 | */ | |
341 | typedef union { | |
342 | uint32_t b24 : 24; | |
343 | ||
344 | struct { | |
345 | #ifdef __BIG_ENDIAN | |
346 | uint8_t domain; | |
347 | uint8_t area; | |
348 | uint8_t al_pa; | |
349 | #elif defined(__LITTLE_ENDIAN) | |
350 | uint8_t al_pa; | |
351 | uint8_t area; | |
352 | uint8_t domain; | |
353 | #else | |
354 | #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!" | |
355 | #endif | |
356 | uint8_t rsvd_1; | |
357 | } b; | |
358 | } port_id_t; | |
359 | #define INVALID_PORT_ID 0xFFFFFF | |
360 | ||
df95f39a BVA |
361 | static inline le_id_t be_id_to_le(be_id_t id) |
362 | { | |
363 | le_id_t res; | |
364 | ||
365 | res.domain = id.domain; | |
366 | res.area = id.area; | |
367 | res.al_pa = id.al_pa; | |
368 | ||
369 | return res; | |
370 | } | |
371 | ||
372 | static inline be_id_t le_id_to_be(le_id_t id) | |
373 | { | |
374 | be_id_t res; | |
375 | ||
376 | res.domain = id.domain; | |
377 | res.area = id.area; | |
378 | res.al_pa = id.al_pa; | |
379 | ||
380 | return res; | |
381 | } | |
382 | ||
383 | static inline port_id_t be_to_port_id(be_id_t id) | |
384 | { | |
385 | port_id_t res; | |
386 | ||
387 | res.b.domain = id.domain; | |
388 | res.b.area = id.area; | |
389 | res.b.al_pa = id.al_pa; | |
390 | res.b.rsvd_1 = 0; | |
391 | ||
392 | return res; | |
393 | } | |
394 | ||
395 | static inline be_id_t port_id_to_be_id(port_id_t port_id) | |
396 | { | |
397 | be_id_t res; | |
398 | ||
399 | res.domain = port_id.b.domain; | |
400 | res.area = port_id.b.area; | |
401 | res.al_pa = port_id.b.al_pa; | |
402 | ||
403 | return res; | |
404 | } | |
405 | ||
6eb54715 HM |
406 | struct els_logo_payload { |
407 | uint8_t opcode; | |
408 | uint8_t rsvd[3]; | |
409 | uint8_t s_id[3]; | |
410 | uint8_t rsvd1[1]; | |
411 | uint8_t wwpn[WWN_SIZE]; | |
412 | }; | |
413 | ||
edd05de1 DG |
414 | struct els_plogi_payload { |
415 | uint8_t opcode; | |
416 | uint8_t rsvd[3]; | |
417 | uint8_t data[112]; | |
418 | }; | |
419 | ||
726b8548 QT |
420 | struct ct_arg { |
421 | void *iocb; | |
422 | u16 nport_handle; | |
423 | dma_addr_t req_dma; | |
424 | dma_addr_t rsp_dma; | |
425 | u32 req_size; | |
426 | u32 rsp_size; | |
b5f3bc39 QT |
427 | u32 req_allocated_size; |
428 | u32 rsp_allocated_size; | |
726b8548 QT |
429 | void *req; |
430 | void *rsp; | |
2d73ac61 | 431 | port_id_t id; |
726b8548 QT |
432 | }; |
433 | ||
ac280b67 AV |
434 | /* |
435 | * SRB extensions. | |
436 | */ | |
4916392b MI |
437 | struct srb_iocb { |
438 | union { | |
439 | struct { | |
440 | uint16_t flags; | |
441 | #define SRB_LOGIN_RETRIED BIT_0 | |
442 | #define SRB_LOGIN_COND_PLOGI BIT_1 | |
443 | #define SRB_LOGIN_SKIP_PRLI BIT_2 | |
a5d42f4c | 444 | #define SRB_LOGIN_NVME_PRLI BIT_3 |
48acad09 | 445 | #define SRB_LOGIN_PRLI_ONLY BIT_4 |
4916392b | 446 | uint16_t data[2]; |
726b8548 | 447 | u32 iop[2]; |
4916392b | 448 | } logio; |
3822263e | 449 | struct { |
6eb54715 HM |
450 | #define ELS_DCMD_TIMEOUT 20 |
451 | #define ELS_DCMD_LOGO 0x5 | |
452 | uint32_t flags; | |
453 | uint32_t els_cmd; | |
454 | struct completion comp; | |
455 | struct els_logo_payload *els_logo_pyld; | |
456 | dma_addr_t els_logo_pyld_dma; | |
457 | } els_logo; | |
c6e58160 | 458 | struct els_plogi { |
edd05de1 DG |
459 | #define ELS_DCMD_PLOGI 0x3 |
460 | uint32_t flags; | |
461 | uint32_t els_cmd; | |
462 | struct completion comp; | |
463 | struct els_plogi_payload *els_plogi_pyld; | |
464 | struct els_plogi_payload *els_resp_pyld; | |
8777e431 QT |
465 | u32 tx_size; |
466 | u32 rx_size; | |
edd05de1 DG |
467 | dma_addr_t els_plogi_pyld_dma; |
468 | dma_addr_t els_resp_pyld_dma; | |
469 | uint32_t fw_status[3]; | |
470 | __le16 comp_status; | |
471 | __le16 len; | |
472 | } els_plogi; | |
473 | struct { | |
3822263e MI |
474 | /* |
475 | * Values for flags field below are as | |
476 | * defined in tsk_mgmt_entry struct | |
477 | * for control_flags field in qla_fw.h. | |
478 | */ | |
9cb78c16 | 479 | uint64_t lun; |
3822263e | 480 | uint32_t flags; |
3822263e | 481 | uint32_t data; |
8ae6d9c7 | 482 | struct completion comp; |
1f8deefe | 483 | __le16 comp_status; |
3822263e | 484 | } tmf; |
8ae6d9c7 GM |
485 | struct { |
486 | #define SRB_FXDISC_REQ_DMA_VALID BIT_0 | |
487 | #define SRB_FXDISC_RESP_DMA_VALID BIT_1 | |
488 | #define SRB_FXDISC_REQ_DWRD_VALID BIT_2 | |
489 | #define SRB_FXDISC_RSP_DWRD_VALID BIT_3 | |
490 | #define FXDISC_TIMEOUT 20 | |
491 | uint8_t flags; | |
492 | uint32_t req_len; | |
493 | uint32_t rsp_len; | |
494 | void *req_addr; | |
495 | void *rsp_addr; | |
496 | dma_addr_t req_dma_handle; | |
497 | dma_addr_t rsp_dma_handle; | |
1f8deefe SK |
498 | __le32 adapter_id; |
499 | __le32 adapter_id_hi; | |
500 | __le16 req_func_type; | |
501 | __le32 req_data; | |
502 | __le32 req_data_extra; | |
503 | __le32 result; | |
504 | __le32 seq_number; | |
505 | __le16 fw_flags; | |
8ae6d9c7 | 506 | struct completion fxiocb_comp; |
1f8deefe | 507 | __le32 reserved_0; |
8ae6d9c7 GM |
508 | uint8_t reserved_1; |
509 | } fxiocb; | |
510 | struct { | |
511 | uint32_t cmd_hndl; | |
1f8deefe | 512 | __le16 comp_status; |
b027a5ac | 513 | __le16 req_que_no; |
8ae6d9c7 GM |
514 | struct completion comp; |
515 | } abt; | |
726b8548 | 516 | struct ct_arg ctarg; |
15f30a57 QT |
517 | #define MAX_IOCB_MB_REG 28 |
518 | #define SIZEOF_IOCB_MB_REG (MAX_IOCB_MB_REG * sizeof(uint16_t)) | |
726b8548 | 519 | struct { |
15f30a57 QT |
520 | __le16 in_mb[MAX_IOCB_MB_REG]; /* from FW */ |
521 | __le16 out_mb[MAX_IOCB_MB_REG]; /* to FW */ | |
726b8548 QT |
522 | void *out, *in; |
523 | dma_addr_t out_dma, in_dma; | |
15f30a57 QT |
524 | struct completion comp; |
525 | int rc; | |
726b8548 QT |
526 | } mbx; |
527 | struct { | |
528 | struct imm_ntfy_from_isp *ntfy; | |
529 | } nack; | |
7401bc18 DG |
530 | struct { |
531 | __le16 comp_status; | |
532 | uint16_t rsp_pyld_len; | |
533 | uint8_t aen_op; | |
534 | void *desc; | |
535 | ||
536 | /* These are only used with ls4 requests */ | |
537 | int cmd_len; | |
538 | int rsp_len; | |
539 | dma_addr_t cmd_dma; | |
540 | dma_addr_t rsp_dma; | |
e84067d7 | 541 | enum nvmefc_fcp_datadir dir; |
7401bc18 DG |
542 | uint32_t dl; |
543 | uint32_t timeout_sec; | |
cf19c45d | 544 | struct list_head entry; |
7401bc18 | 545 | } nvme; |
2853192e QT |
546 | struct { |
547 | u16 cmd; | |
548 | u16 vp_index; | |
549 | } ctrlvp; | |
4916392b | 550 | } u; |
99b0bec7 | 551 | |
ac280b67 | 552 | struct timer_list timer; |
9ba56b95 | 553 | void (*timeout)(void *); |
ac280b67 AV |
554 | }; |
555 | ||
4916392b MI |
556 | /* Values for srb_ctx type */ |
557 | #define SRB_LOGIN_CMD 1 | |
558 | #define SRB_LOGOUT_CMD 2 | |
559 | #define SRB_ELS_CMD_RPT 3 | |
560 | #define SRB_ELS_CMD_HST 4 | |
561 | #define SRB_CT_CMD 5 | |
562 | #define SRB_ADISC_CMD 6 | |
3822263e | 563 | #define SRB_TM_CMD 7 |
9ba56b95 | 564 | #define SRB_SCSI_CMD 8 |
a9b6f722 | 565 | #define SRB_BIDI_CMD 9 |
8ae6d9c7 GM |
566 | #define SRB_FXIOCB_DCMD 10 |
567 | #define SRB_FXIOCB_BCMD 11 | |
568 | #define SRB_ABT_CMD 12 | |
6eb54715 | 569 | #define SRB_ELS_DCMD 13 |
726b8548 QT |
570 | #define SRB_MB_IOCB 14 |
571 | #define SRB_CT_PTHRU_CMD 15 | |
572 | #define SRB_NACK_PLOGI 16 | |
573 | #define SRB_NACK_PRLI 17 | |
574 | #define SRB_NACK_LOGO 18 | |
7401bc18 | 575 | #define SRB_NVME_CMD 19 |
e84067d7 | 576 | #define SRB_NVME_LS 20 |
a5d42f4c | 577 | #define SRB_PRLI_CMD 21 |
2853192e | 578 | #define SRB_CTRL_VP 22 |
11aea16a | 579 | #define SRB_PRLO_CMD 23 |
ac280b67 | 580 | |
c5419e26 QT |
581 | enum { |
582 | TYPE_SRB, | |
583 | TYPE_TGT_CMD, | |
6b0431d6 | 584 | TYPE_TGT_TMCMD, /* task management */ |
c5419e26 QT |
585 | }; |
586 | ||
9ba56b95 | 587 | typedef struct srb { |
c5419e26 QT |
588 | /* |
589 | * Do not move cmd_type field, it needs to | |
590 | * line up with qla_tgt_cmd->cmd_type | |
591 | */ | |
592 | uint8_t cmd_type; | |
593 | uint8_t pad[3]; | |
4c2a2d01 QT |
594 | struct kref cmd_kref; /* need to migrate ref_count over to this */ |
595 | void *priv; | |
6fcd98fd | 596 | wait_queue_head_t nvme_ls_waitq; |
9ba56b95 | 597 | struct fc_port *fcport; |
25ff6af1 | 598 | struct scsi_qla_host *vha; |
3a4b6cc7 | 599 | unsigned int start_timer:1; |
f45bca8c QT |
600 | unsigned int abort:1; |
601 | unsigned int aborted:1; | |
602 | unsigned int completed:1; | |
603 | ||
9ba56b95 GM |
604 | uint32_t handle; |
605 | uint16_t flags; | |
9a069e19 | 606 | uint16_t type; |
15f30a57 | 607 | const char *name; |
5780790e | 608 | int iocbs; |
d7459527 | 609 | struct qla_qpair *qpair; |
71c80b75 | 610 | struct srb *cmd_sp; |
2d73ac61 | 611 | struct list_head elem; |
726b8548 QT |
612 | u32 gen1; /* scratch */ |
613 | u32 gen2; /* scratch */ | |
2853192e | 614 | int rc; |
e374f9f5 | 615 | int retry_count; |
982cc4be | 616 | struct completion *comp; |
4916392b | 617 | union { |
9ba56b95 | 618 | struct srb_iocb iocb_cmd; |
75cc8cfc | 619 | struct bsg_job *bsg_job; |
9ba56b95 | 620 | struct srb_cmd scmd; |
4916392b | 621 | } u; |
6c18a43e BVA |
622 | /* |
623 | * Report completion status @res and call sp_put(@sp). @res is | |
624 | * an NVMe status code, a SCSI result (e.g. DID_OK << 16) or a | |
625 | * QLA_* status value. | |
626 | */ | |
627 | void (*done)(struct srb *sp, int res); | |
628 | /* Stop the timer and free @sp. Only used by the FCP code. */ | |
629 | void (*free)(struct srb *sp); | |
630 | /* | |
631 | * Call nvme_private->fd->done() and free @sp. Only used by the NVMe | |
632 | * code. | |
633 | */ | |
4c2a2d01 | 634 | void (*put_fn)(struct kref *kref); |
9ba56b95 GM |
635 | } srb_t; |
636 | ||
637 | #define GET_CMD_SP(sp) (sp->u.scmd.cmd) | |
9ba56b95 GM |
638 | |
639 | #define GET_CMD_SENSE_LEN(sp) \ | |
640 | (sp->u.scmd.request_sense_length) | |
641 | #define SET_CMD_SENSE_LEN(sp, len) \ | |
642 | (sp->u.scmd.request_sense_length = len) | |
643 | #define GET_CMD_SENSE_PTR(sp) \ | |
644 | (sp->u.scmd.request_sense_ptr) | |
645 | #define SET_CMD_SENSE_PTR(sp, ptr) \ | |
646 | (sp->u.scmd.request_sense_ptr = ptr) | |
8ae6d9c7 GM |
647 | #define GET_FW_SENSE_LEN(sp) \ |
648 | (sp->u.scmd.fw_sense_length) | |
649 | #define SET_FW_SENSE_LEN(sp, len) \ | |
650 | (sp->u.scmd.fw_sense_length = len) | |
9a069e19 GM |
651 | |
652 | struct msg_echo_lb { | |
653 | dma_addr_t send_dma; | |
654 | dma_addr_t rcv_dma; | |
655 | uint16_t req_sg_cnt; | |
656 | uint16_t rsp_sg_cnt; | |
657 | uint16_t options; | |
658 | uint32_t transfer_size; | |
1b98b421 | 659 | uint32_t iteration_count; |
9a069e19 GM |
660 | }; |
661 | ||
1da177e4 LT |
662 | /* |
663 | * ISP I/O Register Set structure definitions. | |
664 | */ | |
3d71644c AV |
665 | struct device_reg_2xxx { |
666 | uint16_t flash_address; /* Flash BIOS address */ | |
667 | uint16_t flash_data; /* Flash BIOS data */ | |
1da177e4 | 668 | uint16_t unused_1[1]; /* Gap */ |
3d71644c | 669 | uint16_t ctrl_status; /* Control/Status */ |
fa2a1ce5 | 670 | #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */ |
1da177e4 LT |
671 | #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */ |
672 | #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */ | |
673 | ||
3d71644c | 674 | uint16_t ictrl; /* Interrupt control */ |
1da177e4 LT |
675 | #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */ |
676 | #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */ | |
677 | ||
3d71644c | 678 | uint16_t istatus; /* Interrupt status */ |
1da177e4 LT |
679 | #define ISR_RISC_INT BIT_3 /* RISC interrupt */ |
680 | ||
3d71644c AV |
681 | uint16_t semaphore; /* Semaphore */ |
682 | uint16_t nvram; /* NVRAM register. */ | |
1da177e4 LT |
683 | #define NVR_DESELECT 0 |
684 | #define NVR_BUSY BIT_15 | |
685 | #define NVR_WRT_ENABLE BIT_14 /* Write enable */ | |
686 | #define NVR_PR_ENABLE BIT_13 /* Protection register enable */ | |
687 | #define NVR_DATA_IN BIT_3 | |
688 | #define NVR_DATA_OUT BIT_2 | |
689 | #define NVR_SELECT BIT_1 | |
690 | #define NVR_CLOCK BIT_0 | |
691 | ||
45aeaf1e RA |
692 | #define NVR_WAIT_CNT 20000 |
693 | ||
1da177e4 LT |
694 | union { |
695 | struct { | |
3d71644c AV |
696 | uint16_t mailbox0; |
697 | uint16_t mailbox1; | |
698 | uint16_t mailbox2; | |
699 | uint16_t mailbox3; | |
700 | uint16_t mailbox4; | |
701 | uint16_t mailbox5; | |
702 | uint16_t mailbox6; | |
703 | uint16_t mailbox7; | |
704 | uint16_t unused_2[59]; /* Gap */ | |
1da177e4 LT |
705 | } __attribute__((packed)) isp2100; |
706 | struct { | |
3d71644c AV |
707 | /* Request Queue */ |
708 | uint16_t req_q_in; /* In-Pointer */ | |
709 | uint16_t req_q_out; /* Out-Pointer */ | |
710 | /* Response Queue */ | |
711 | uint16_t rsp_q_in; /* In-Pointer */ | |
712 | uint16_t rsp_q_out; /* Out-Pointer */ | |
1da177e4 LT |
713 | |
714 | /* RISC to Host Status */ | |
fa2a1ce5 | 715 | uint32_t host_status; |
1da177e4 LT |
716 | #define HSR_RISC_INT BIT_15 /* RISC interrupt */ |
717 | #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */ | |
718 | ||
719 | /* Host to Host Semaphore */ | |
fa2a1ce5 | 720 | uint16_t host_semaphore; |
3d71644c AV |
721 | uint16_t unused_3[17]; /* Gap */ |
722 | uint16_t mailbox0; | |
723 | uint16_t mailbox1; | |
724 | uint16_t mailbox2; | |
725 | uint16_t mailbox3; | |
726 | uint16_t mailbox4; | |
727 | uint16_t mailbox5; | |
728 | uint16_t mailbox6; | |
729 | uint16_t mailbox7; | |
730 | uint16_t mailbox8; | |
731 | uint16_t mailbox9; | |
732 | uint16_t mailbox10; | |
733 | uint16_t mailbox11; | |
734 | uint16_t mailbox12; | |
735 | uint16_t mailbox13; | |
736 | uint16_t mailbox14; | |
737 | uint16_t mailbox15; | |
738 | uint16_t mailbox16; | |
739 | uint16_t mailbox17; | |
740 | uint16_t mailbox18; | |
741 | uint16_t mailbox19; | |
742 | uint16_t mailbox20; | |
743 | uint16_t mailbox21; | |
744 | uint16_t mailbox22; | |
745 | uint16_t mailbox23; | |
746 | uint16_t mailbox24; | |
747 | uint16_t mailbox25; | |
748 | uint16_t mailbox26; | |
749 | uint16_t mailbox27; | |
750 | uint16_t mailbox28; | |
751 | uint16_t mailbox29; | |
752 | uint16_t mailbox30; | |
753 | uint16_t mailbox31; | |
754 | uint16_t fb_cmd; | |
755 | uint16_t unused_4[10]; /* Gap */ | |
1da177e4 LT |
756 | } __attribute__((packed)) isp2300; |
757 | } u; | |
758 | ||
3d71644c | 759 | uint16_t fpm_diag_config; |
c81d04c9 AV |
760 | uint16_t unused_5[0x4]; /* Gap */ |
761 | uint16_t risc_hw; | |
762 | uint16_t unused_5_1; /* Gap */ | |
3d71644c | 763 | uint16_t pcr; /* Processor Control Register. */ |
1da177e4 | 764 | uint16_t unused_6[0x5]; /* Gap */ |
3d71644c | 765 | uint16_t mctr; /* Memory Configuration and Timing. */ |
1da177e4 | 766 | uint16_t unused_7[0x3]; /* Gap */ |
3d71644c | 767 | uint16_t fb_cmd_2100; /* Unused on 23XX */ |
1da177e4 | 768 | uint16_t unused_8[0x3]; /* Gap */ |
3d71644c | 769 | uint16_t hccr; /* Host command & control register. */ |
1da177e4 LT |
770 | #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */ |
771 | #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */ | |
772 | /* HCCR commands */ | |
773 | #define HCCR_RESET_RISC 0x1000 /* Reset RISC */ | |
774 | #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */ | |
775 | #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */ | |
776 | #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */ | |
777 | #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */ | |
778 | #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */ | |
779 | #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */ | |
780 | #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */ | |
781 | ||
782 | uint16_t unused_9[5]; /* Gap */ | |
3d71644c AV |
783 | uint16_t gpiod; /* GPIO Data register. */ |
784 | uint16_t gpioe; /* GPIO Enable register. */ | |
1da177e4 LT |
785 | #define GPIO_LED_MASK 0x00C0 |
786 | #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000 | |
787 | #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040 | |
788 | #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080 | |
789 | #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0 | |
f6df144c AV |
790 | #define GPIO_LED_ALL_OFF 0x0000 |
791 | #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */ | |
792 | #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */ | |
1da177e4 LT |
793 | |
794 | union { | |
795 | struct { | |
3d71644c AV |
796 | uint16_t unused_10[8]; /* Gap */ |
797 | uint16_t mailbox8; | |
798 | uint16_t mailbox9; | |
799 | uint16_t mailbox10; | |
800 | uint16_t mailbox11; | |
801 | uint16_t mailbox12; | |
802 | uint16_t mailbox13; | |
803 | uint16_t mailbox14; | |
804 | uint16_t mailbox15; | |
805 | uint16_t mailbox16; | |
806 | uint16_t mailbox17; | |
807 | uint16_t mailbox18; | |
808 | uint16_t mailbox19; | |
809 | uint16_t mailbox20; | |
810 | uint16_t mailbox21; | |
811 | uint16_t mailbox22; | |
812 | uint16_t mailbox23; /* Also probe reg. */ | |
1da177e4 LT |
813 | } __attribute__((packed)) isp2200; |
814 | } u_end; | |
3d71644c AV |
815 | }; |
816 | ||
73208dfd | 817 | struct device_reg_25xxmq { |
08029990 AV |
818 | uint32_t req_q_in; |
819 | uint32_t req_q_out; | |
820 | uint32_t rsp_q_in; | |
821 | uint32_t rsp_q_out; | |
aa230bc5 AE |
822 | uint32_t atio_q_in; |
823 | uint32_t atio_q_out; | |
73208dfd AC |
824 | }; |
825 | ||
8ae6d9c7 GM |
826 | |
827 | struct device_reg_fx00 { | |
828 | uint32_t mailbox0; /* 00 */ | |
829 | uint32_t mailbox1; /* 04 */ | |
830 | uint32_t mailbox2; /* 08 */ | |
831 | uint32_t mailbox3; /* 0C */ | |
832 | uint32_t mailbox4; /* 10 */ | |
833 | uint32_t mailbox5; /* 14 */ | |
834 | uint32_t mailbox6; /* 18 */ | |
835 | uint32_t mailbox7; /* 1C */ | |
836 | uint32_t mailbox8; /* 20 */ | |
837 | uint32_t mailbox9; /* 24 */ | |
838 | uint32_t mailbox10; /* 28 */ | |
839 | uint32_t mailbox11; | |
840 | uint32_t mailbox12; | |
841 | uint32_t mailbox13; | |
842 | uint32_t mailbox14; | |
843 | uint32_t mailbox15; | |
844 | uint32_t mailbox16; | |
845 | uint32_t mailbox17; | |
846 | uint32_t mailbox18; | |
847 | uint32_t mailbox19; | |
848 | uint32_t mailbox20; | |
849 | uint32_t mailbox21; | |
850 | uint32_t mailbox22; | |
851 | uint32_t mailbox23; | |
852 | uint32_t mailbox24; | |
853 | uint32_t mailbox25; | |
854 | uint32_t mailbox26; | |
855 | uint32_t mailbox27; | |
856 | uint32_t mailbox28; | |
857 | uint32_t mailbox29; | |
858 | uint32_t mailbox30; | |
859 | uint32_t mailbox31; | |
860 | uint32_t aenmailbox0; | |
861 | uint32_t aenmailbox1; | |
862 | uint32_t aenmailbox2; | |
863 | uint32_t aenmailbox3; | |
864 | uint32_t aenmailbox4; | |
865 | uint32_t aenmailbox5; | |
866 | uint32_t aenmailbox6; | |
867 | uint32_t aenmailbox7; | |
868 | /* Request Queue. */ | |
869 | uint32_t req_q_in; /* A0 - Request Queue In-Pointer */ | |
870 | uint32_t req_q_out; /* A4 - Request Queue Out-Pointer */ | |
871 | /* Response Queue. */ | |
872 | uint32_t rsp_q_in; /* A8 - Response Queue In-Pointer */ | |
873 | uint32_t rsp_q_out; /* AC - Response Queue Out-Pointer */ | |
874 | /* Init values shadowed on FW Up Event */ | |
875 | uint32_t initval0; /* B0 */ | |
876 | uint32_t initval1; /* B4 */ | |
877 | uint32_t initval2; /* B8 */ | |
878 | uint32_t initval3; /* BC */ | |
879 | uint32_t initval4; /* C0 */ | |
880 | uint32_t initval5; /* C4 */ | |
881 | uint32_t initval6; /* C8 */ | |
882 | uint32_t initval7; /* CC */ | |
883 | uint32_t fwheartbeat; /* D0 */ | |
f9a2a543 | 884 | uint32_t pseudoaen; /* D4 */ |
8ae6d9c7 GM |
885 | }; |
886 | ||
887 | ||
888 | ||
9a168bdd | 889 | typedef union { |
3d71644c AV |
890 | struct device_reg_2xxx isp; |
891 | struct device_reg_24xx isp24; | |
73208dfd | 892 | struct device_reg_25xxmq isp25mq; |
a9083016 | 893 | struct device_reg_82xx isp82; |
8ae6d9c7 | 894 | struct device_reg_fx00 ispfx00; |
f73cb695 | 895 | } __iomem device_reg_t; |
1da177e4 LT |
896 | |
897 | #define ISP_REQ_Q_IN(ha, reg) \ | |
898 | (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ | |
899 | &(reg)->u.isp2100.mailbox4 : \ | |
900 | &(reg)->u.isp2300.req_q_in) | |
901 | #define ISP_REQ_Q_OUT(ha, reg) \ | |
902 | (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ | |
903 | &(reg)->u.isp2100.mailbox4 : \ | |
904 | &(reg)->u.isp2300.req_q_out) | |
905 | #define ISP_RSP_Q_IN(ha, reg) \ | |
906 | (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ | |
907 | &(reg)->u.isp2100.mailbox5 : \ | |
908 | &(reg)->u.isp2300.rsp_q_in) | |
909 | #define ISP_RSP_Q_OUT(ha, reg) \ | |
910 | (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ | |
911 | &(reg)->u.isp2100.mailbox5 : \ | |
912 | &(reg)->u.isp2300.rsp_q_out) | |
913 | ||
aa230bc5 AE |
914 | #define ISP_ATIO_Q_IN(vha) (vha->hw->tgt.atio_q_in) |
915 | #define ISP_ATIO_Q_OUT(vha) (vha->hw->tgt.atio_q_out) | |
916 | ||
1da177e4 LT |
917 | #define MAILBOX_REG(ha, reg, num) \ |
918 | (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ | |
919 | (num < 8 ? \ | |
920 | &(reg)->u.isp2100.mailbox0 + (num) : \ | |
921 | &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \ | |
922 | &(reg)->u.isp2300.mailbox0 + (num)) | |
923 | #define RD_MAILBOX_REG(ha, reg, num) \ | |
924 | RD_REG_WORD(MAILBOX_REG(ha, reg, num)) | |
925 | #define WRT_MAILBOX_REG(ha, reg, num, data) \ | |
926 | WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data) | |
927 | ||
928 | #define FB_CMD_REG(ha, reg) \ | |
929 | (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ | |
930 | &(reg)->fb_cmd_2100 : \ | |
931 | &(reg)->u.isp2300.fb_cmd) | |
932 | #define RD_FB_CMD_REG(ha, reg) \ | |
933 | RD_REG_WORD(FB_CMD_REG(ha, reg)) | |
934 | #define WRT_FB_CMD_REG(ha, reg, data) \ | |
935 | WRT_REG_WORD(FB_CMD_REG(ha, reg), data) | |
936 | ||
937 | typedef struct { | |
938 | uint32_t out_mb; /* outbound from driver */ | |
939 | uint32_t in_mb; /* Incoming from RISC */ | |
940 | uint16_t mb[MAILBOX_REGISTER_COUNT]; | |
941 | long buf_size; | |
942 | void *bufp; | |
943 | uint32_t tov; | |
944 | uint8_t flags; | |
945 | #define MBX_DMA_IN BIT_0 | |
946 | #define MBX_DMA_OUT BIT_1 | |
947 | #define IOCTL_CMD BIT_2 | |
948 | } mbx_cmd_t; | |
949 | ||
8ae6d9c7 GM |
950 | struct mbx_cmd_32 { |
951 | uint32_t out_mb; /* outbound from driver */ | |
952 | uint32_t in_mb; /* Incoming from RISC */ | |
953 | uint32_t mb[MAILBOX_REGISTER_COUNT]; | |
954 | long buf_size; | |
955 | void *bufp; | |
956 | uint32_t tov; | |
957 | uint8_t flags; | |
958 | #define MBX_DMA_IN BIT_0 | |
959 | #define MBX_DMA_OUT BIT_1 | |
960 | #define IOCTL_CMD BIT_2 | |
961 | }; | |
962 | ||
963 | ||
1da177e4 LT |
964 | #define MBX_TOV_SECONDS 30 |
965 | ||
966 | /* | |
967 | * ISP product identification definitions in mailboxes after reset. | |
968 | */ | |
969 | #define PROD_ID_1 0x4953 | |
970 | #define PROD_ID_2 0x0000 | |
971 | #define PROD_ID_2a 0x5020 | |
972 | #define PROD_ID_3 0x2020 | |
973 | ||
974 | /* | |
975 | * ISP mailbox Self-Test status codes | |
976 | */ | |
977 | #define MBS_FRM_ALIVE 0 /* Firmware Alive. */ | |
978 | #define MBS_CHKSUM_ERR 1 /* Checksum Error. */ | |
979 | #define MBS_BUSY 4 /* Busy. */ | |
980 | ||
981 | /* | |
982 | * ISP mailbox command complete status codes | |
983 | */ | |
984 | #define MBS_COMMAND_COMPLETE 0x4000 | |
985 | #define MBS_INVALID_COMMAND 0x4001 | |
986 | #define MBS_HOST_INTERFACE_ERROR 0x4002 | |
987 | #define MBS_TEST_FAILED 0x4003 | |
988 | #define MBS_COMMAND_ERROR 0x4005 | |
989 | #define MBS_COMMAND_PARAMETER_ERROR 0x4006 | |
990 | #define MBS_PORT_ID_USED 0x4007 | |
991 | #define MBS_LOOP_ID_USED 0x4008 | |
992 | #define MBS_ALL_IDS_IN_USE 0x4009 | |
993 | #define MBS_NOT_LOGGED_IN 0x400A | |
3d71644c AV |
994 | #define MBS_LINK_DOWN_ERROR 0x400B |
995 | #define MBS_DIAG_ECHO_TEST_ERROR 0x400C | |
1da177e4 | 996 | |
72436192 BVA |
997 | static inline bool qla2xxx_is_valid_mbs(unsigned int mbs) |
998 | { | |
999 | return MBS_COMMAND_COMPLETE <= mbs && mbs <= MBS_DIAG_ECHO_TEST_ERROR; | |
1000 | } | |
1001 | ||
1da177e4 LT |
1002 | /* |
1003 | * ISP mailbox asynchronous event status codes | |
1004 | */ | |
1005 | #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */ | |
1006 | #define MBA_RESET 0x8001 /* Reset Detected. */ | |
1007 | #define MBA_SYSTEM_ERR 0x8002 /* System Error. */ | |
1008 | #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */ | |
1009 | #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */ | |
1010 | #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */ | |
1011 | #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */ | |
1012 | /* occurred. */ | |
1013 | #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */ | |
1014 | #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */ | |
1015 | #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */ | |
1016 | #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */ | |
1017 | #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */ | |
1018 | #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */ | |
1019 | #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */ | |
1020 | #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */ | |
1021 | #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */ | |
1022 | #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */ | |
1023 | #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */ | |
1024 | #define MBA_IP_RECEIVE 0x8023 /* IP Received. */ | |
1025 | #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */ | |
1026 | #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */ | |
1027 | #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */ | |
1028 | #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */ | |
1029 | /* used. */ | |
45ebeb56 | 1030 | #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */ |
1da177e4 LT |
1031 | #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */ |
1032 | #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */ | |
1033 | #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */ | |
1034 | #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */ | |
1035 | #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */ | |
1036 | #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */ | |
1037 | #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */ | |
1038 | #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */ | |
1039 | #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */ | |
1040 | #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */ | |
1041 | #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */ | |
1042 | #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */ | |
1043 | #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */ | |
8ae6d9c7 GM |
1044 | #define MBA_FW_NOT_STARTED 0x8050 /* Firmware not started */ |
1045 | #define MBA_FW_STARTING 0x8051 /* Firmware starting */ | |
1046 | #define MBA_FW_RESTART_CMPLT 0x8060 /* Firmware restart complete */ | |
1047 | #define MBA_INIT_REQUIRED 0x8061 /* Initialization required */ | |
1048 | #define MBA_SHUTDOWN_REQUESTED 0x8062 /* Shutdown Requested */ | |
a29b3dd7 | 1049 | #define MBA_TEMPERATURE_ALERT 0x8070 /* Temperature Alert */ |
b5a340dd | 1050 | #define MBA_DPORT_DIAGNOSTICS 0x8080 /* D-port Diagnostics */ |
92d4408e | 1051 | #define MBA_TRANS_INSERT 0x8130 /* Transceiver Insertion */ |
8ae6d9c7 GM |
1052 | #define MBA_FW_INIT_FAILURE 0x8401 /* Firmware initialization failure */ |
1053 | #define MBA_MIRROR_LUN_CHANGE 0x8402 /* Mirror LUN State Change | |
1054 | Notification */ | |
1055 | #define MBA_FW_POLL_STATE 0x8600 /* Firmware in poll diagnostic state */ | |
b6511d99 | 1056 | #define MBA_FW_RESET_FCT 0x8502 /* Firmware reset factory defaults */ |
0f8cdff5 | 1057 | #define MBA_FW_INIT_INPROGRESS 0x8500 /* Firmware boot in progress */ |
7d613ac6 SV |
1058 | /* 83XX FCoE specific */ |
1059 | #define MBA_IDC_AEN 0x8200 /* FCoE: NIC Core state change AEN */ | |
fafbda9f AE |
1060 | |
1061 | /* Interrupt type codes */ | |
1062 | #define INTR_ROM_MB_SUCCESS 0x1 | |
1063 | #define INTR_ROM_MB_FAILED 0x2 | |
1064 | #define INTR_MB_SUCCESS 0x10 | |
1065 | #define INTR_MB_FAILED 0x11 | |
1066 | #define INTR_ASYNC_EVENT 0x12 | |
1067 | #define INTR_RSP_QUE_UPDATE 0x13 | |
1068 | #define INTR_RSP_QUE_UPDATE_83XX 0x14 | |
1069 | #define INTR_ATIO_QUE_UPDATE 0x1C | |
1070 | #define INTR_ATIO_RSP_QUE_UPDATE 0x1D | |
c9558869 | 1071 | #define INTR_ATIO_QUE_UPDATE_27XX 0x1E |
7d613ac6 | 1072 | |
9a069e19 GM |
1073 | /* ISP mailbox loopback echo diagnostic error code */ |
1074 | #define MBS_LB_RESET 0x17 | |
1da177e4 LT |
1075 | /* |
1076 | * Firmware options 1, 2, 3. | |
1077 | */ | |
1078 | #define FO1_AE_ON_LIPF8 BIT_0 | |
1079 | #define FO1_AE_ALL_LIP_RESET BIT_1 | |
1080 | #define FO1_CTIO_RETRY BIT_3 | |
1081 | #define FO1_DISABLE_LIP_F7_SW BIT_4 | |
1082 | #define FO1_DISABLE_100MS_LOS_WAIT BIT_5 | |
3d71644c | 1083 | #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */ |
1da177e4 LT |
1084 | #define FO1_AE_ON_LOOP_INIT_ERR BIT_7 |
1085 | #define FO1_SET_EMPHASIS_SWING BIT_8 | |
1086 | #define FO1_AE_AUTO_BYPASS BIT_9 | |
1087 | #define FO1_ENABLE_PURE_IOCB BIT_10 | |
1088 | #define FO1_AE_PLOGI_RJT BIT_11 | |
1089 | #define FO1_ENABLE_ABORT_SEQUENCE BIT_12 | |
1090 | #define FO1_AE_QUEUE_FULL BIT_13 | |
1091 | ||
1092 | #define FO2_ENABLE_ATIO_TYPE_3 BIT_0 | |
1093 | #define FO2_REV_LOOPBACK BIT_1 | |
1094 | ||
1095 | #define FO3_ENABLE_EMERG_IOCB BIT_0 | |
1096 | #define FO3_AE_RND_ERROR BIT_1 | |
1097 | ||
3d71644c AV |
1098 | /* 24XX additional firmware options */ |
1099 | #define ADD_FO_COUNT 3 | |
1100 | #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */ | |
1101 | #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10 | |
1102 | ||
1103 | #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5 | |
1104 | ||
1105 | #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14 | |
1106 | ||
1da177e4 LT |
1107 | /* |
1108 | * ISP mailbox commands | |
1109 | */ | |
1110 | #define MBC_LOAD_RAM 1 /* Load RAM. */ | |
1111 | #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */ | |
1da177e4 LT |
1112 | #define MBC_READ_RAM_WORD 5 /* Read RAM word. */ |
1113 | #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */ | |
1114 | #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */ | |
1115 | #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */ | |
1116 | #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */ | |
1117 | #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */ | |
3f006ac3 | 1118 | #define MBC_SECURE_FLASH_UPDATE 0xa /* Secure Flash Update(28xx) */ |
1da177e4 LT |
1119 | #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */ |
1120 | #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */ | |
1121 | #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */ | |
1122 | #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */ | |
1123 | #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */ | |
f6ef3b18 | 1124 | #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */ |
1da177e4 LT |
1125 | #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */ |
1126 | #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */ | |
1127 | #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */ | |
1128 | #define MBC_RESET 0x18 /* Reset. */ | |
1129 | #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */ | |
deeae7a6 | 1130 | #define MBC_GET_SET_ZIO_THRESHOLD 0x21 /* Get/SET ZIO THRESHOLD. */ |
1da177e4 LT |
1131 | #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */ |
1132 | #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */ | |
1133 | #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */ | |
1134 | #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */ | |
b0d6cabd | 1135 | #define MBC_GET_MEM_OFFLOAD_CNTRL_STAT 0x34 /* Memory Offload ctrl/Stat*/ |
1da177e4 LT |
1136 | #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */ |
1137 | #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */ | |
1138 | #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */ | |
1139 | #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */ | |
1140 | #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */ | |
1141 | #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */ | |
1142 | #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */ | |
1143 | #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */ | |
1144 | #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */ | |
6246b8a1 | 1145 | #define MBC_CONFIGURE_VF 0x4b /* Configure VFs */ |
1da177e4 LT |
1146 | #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */ |
1147 | #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */ | |
af11f64d | 1148 | #define MBC_PORT_LOGOUT 0x56 /* Port Logout request */ |
1da177e4 LT |
1149 | #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */ |
1150 | #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */ | |
90687a1e JC |
1151 | #define MBC_GET_RNID_PARAMS 0x5a /* Get RNID parameters */ |
1152 | #define MBC_DATA_RATE 0x5d /* Data Rate */ | |
1da177e4 LT |
1153 | #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */ |
1154 | #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */ | |
1155 | /* Initialization Procedure */ | |
1156 | #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */ | |
1157 | #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */ | |
1158 | #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */ | |
1159 | #define MBC_TARGET_RESET 0x66 /* Target Reset. */ | |
1160 | #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */ | |
1161 | #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */ | |
1162 | #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */ | |
1163 | #define MBC_GET_PORT_NAME 0x6a /* Get port name. */ | |
1164 | #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */ | |
1165 | #define MBC_LIP_RESET 0x6c /* LIP reset. */ | |
1166 | #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */ | |
1167 | /* commandd. */ | |
1168 | #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */ | |
1169 | #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */ | |
1170 | #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */ | |
1171 | #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */ | |
1172 | #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */ | |
1173 | #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */ | |
1174 | #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */ | |
1175 | #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */ | |
1176 | #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */ | |
1177 | #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */ | |
1178 | #define MBC_LUN_RESET 0x7E /* Send LUN reset */ | |
1179 | ||
8ae6d9c7 GM |
1180 | /* |
1181 | * all the Mt. Rainier mailbox command codes that clash with FC/FCoE ones | |
1182 | * should be defined with MBC_MR_* | |
1183 | */ | |
1184 | #define MBC_MR_DRV_SHUTDOWN 0x6A | |
1185 | ||
3d71644c AV |
1186 | /* |
1187 | * ISP24xx mailbox commands | |
1188 | */ | |
db64e930 JC |
1189 | #define MBC_WRITE_SERDES 0x3 /* Write serdes word. */ |
1190 | #define MBC_READ_SERDES 0x4 /* Read serdes word. */ | |
f73cb695 | 1191 | #define MBC_LOAD_DUMP_MPI_RAM 0x5 /* Load/Dump MPI RAM. */ |
3d71644c AV |
1192 | #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */ |
1193 | #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */ | |
d8b45213 | 1194 | #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */ |
3d71644c | 1195 | #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */ |
a7a167bf | 1196 | #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */ |
3d71644c | 1197 | #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */ |
ad0ecd61 | 1198 | #define MBC_WRITE_SFP 0x30 /* Write SFP Data. */ |
88729e53 | 1199 | #define MBC_READ_SFP 0x31 /* Read SFP Data. */ |
3d71644c | 1200 | #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */ |
b5a340dd | 1201 | #define MBC_DPORT_DIAGNOSTICS 0x47 /* D-Port Diagnostics */ |
3d71644c AV |
1202 | #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */ |
1203 | #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */ | |
1204 | #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */ | |
1205 | #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */ | |
1206 | #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */ | |
1207 | #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */ | |
61e1b269 | 1208 | #define MBC_LINK_INITIALIZATION 0x72 /* Do link initialization. */ |
3d71644c | 1209 | #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */ |
8fcd6b8b | 1210 | #define MBC_PORT_RESET 0x120 /* Port Reset */ |
23f2ebd1 SR |
1211 | #define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */ |
1212 | #define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */ | |
3d71644c | 1213 | |
b1d46989 MI |
1214 | /* |
1215 | * ISP81xx mailbox commands | |
1216 | */ | |
1217 | #define MBC_WRITE_MPI_REGISTER 0x01 /* Write MPI Register. */ | |
1218 | ||
e8887c51 JC |
1219 | /* |
1220 | * ISP8044 mailbox commands | |
1221 | */ | |
1222 | #define MBC_SET_GET_ETH_SERDES_REG 0x150 | |
1223 | #define HCS_WRITE_SERDES 0x3 | |
1224 | #define HCS_READ_SERDES 0x4 | |
1225 | ||
1da177e4 LT |
1226 | /* Firmware return data sizes */ |
1227 | #define FCAL_MAP_SIZE 128 | |
1228 | ||
1229 | /* Mailbox bit definitions for out_mb and in_mb */ | |
1230 | #define MBX_31 BIT_31 | |
1231 | #define MBX_30 BIT_30 | |
1232 | #define MBX_29 BIT_29 | |
1233 | #define MBX_28 BIT_28 | |
1234 | #define MBX_27 BIT_27 | |
1235 | #define MBX_26 BIT_26 | |
1236 | #define MBX_25 BIT_25 | |
1237 | #define MBX_24 BIT_24 | |
1238 | #define MBX_23 BIT_23 | |
1239 | #define MBX_22 BIT_22 | |
1240 | #define MBX_21 BIT_21 | |
1241 | #define MBX_20 BIT_20 | |
1242 | #define MBX_19 BIT_19 | |
1243 | #define MBX_18 BIT_18 | |
1244 | #define MBX_17 BIT_17 | |
1245 | #define MBX_16 BIT_16 | |
1246 | #define MBX_15 BIT_15 | |
1247 | #define MBX_14 BIT_14 | |
1248 | #define MBX_13 BIT_13 | |
1249 | #define MBX_12 BIT_12 | |
1250 | #define MBX_11 BIT_11 | |
1251 | #define MBX_10 BIT_10 | |
1252 | #define MBX_9 BIT_9 | |
1253 | #define MBX_8 BIT_8 | |
1254 | #define MBX_7 BIT_7 | |
1255 | #define MBX_6 BIT_6 | |
1256 | #define MBX_5 BIT_5 | |
1257 | #define MBX_4 BIT_4 | |
1258 | #define MBX_3 BIT_3 | |
1259 | #define MBX_2 BIT_2 | |
1260 | #define MBX_1 BIT_1 | |
1261 | #define MBX_0 BIT_0 | |
1262 | ||
a5d42f4c | 1263 | #define RNID_TYPE_PORT_LOGIN 0x7 |
c46e65c7 | 1264 | #define RNID_TYPE_SET_VERSION 0x9 |
fe52f6e1 | 1265 | #define RNID_TYPE_ASIC_TEMP 0xC |
3a11711a | 1266 | |
1da177e4 LT |
1267 | /* |
1268 | * Firmware state codes from get firmware state mailbox command | |
1269 | */ | |
1270 | #define FSTATE_CONFIG_WAIT 0 | |
1271 | #define FSTATE_WAIT_AL_PA 1 | |
1272 | #define FSTATE_WAIT_LOGIN 2 | |
1273 | #define FSTATE_READY 3 | |
1274 | #define FSTATE_LOSS_OF_SYNC 4 | |
1275 | #define FSTATE_ERROR 5 | |
1276 | #define FSTATE_REINIT 6 | |
1277 | #define FSTATE_NON_PART 7 | |
1278 | ||
1279 | #define FSTATE_CONFIG_CORRECT 0 | |
1280 | #define FSTATE_P2P_RCV_LIP 1 | |
1281 | #define FSTATE_P2P_CHOOSE_LOOP 2 | |
1282 | #define FSTATE_P2P_RCV_UNIDEN_LIP 3 | |
1283 | #define FSTATE_FATAL_ERROR 4 | |
1284 | #define FSTATE_LOOP_BACK_CONN 5 | |
1285 | ||
4243c115 SC |
1286 | #define QLA27XX_IMG_STATUS_VER_MAJOR 0x01 |
1287 | #define QLA27XX_IMG_STATUS_VER_MINOR 0x00 | |
1288 | #define QLA27XX_IMG_STATUS_SIGN 0xFACEFADE | |
ecc89f25 | 1289 | #define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF |
5fa8774c JC |
1290 | #define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF |
1291 | #define QLA28XX_AUX_IMG_STATUS_SIGN 0xFACEFAED | |
1292 | #define QLA27XX_DEFAULT_IMAGE 0 | |
4243c115 SC |
1293 | #define QLA27XX_PRIMARY_IMAGE 1 |
1294 | #define QLA27XX_SECONDARY_IMAGE 2 | |
1295 | ||
1da177e4 LT |
1296 | /* |
1297 | * Port Database structure definition | |
1298 | * Little endian except where noted. | |
1299 | */ | |
1300 | #define PORT_DATABASE_SIZE 128 /* bytes */ | |
1301 | typedef struct { | |
1302 | uint8_t options; | |
1303 | uint8_t control; | |
1304 | uint8_t master_state; | |
1305 | uint8_t slave_state; | |
1306 | uint8_t reserved[2]; | |
1307 | uint8_t hard_address; | |
1308 | uint8_t reserved_1; | |
1309 | uint8_t port_id[4]; | |
1310 | uint8_t node_name[WWN_SIZE]; | |
1311 | uint8_t port_name[WWN_SIZE]; | |
1312 | uint16_t execution_throttle; | |
1313 | uint16_t execution_count; | |
1314 | uint8_t reset_count; | |
1315 | uint8_t reserved_2; | |
1316 | uint16_t resource_allocation; | |
1317 | uint16_t current_allocation; | |
1318 | uint16_t queue_head; | |
1319 | uint16_t queue_tail; | |
1320 | uint16_t transmit_execution_list_next; | |
1321 | uint16_t transmit_execution_list_previous; | |
1322 | uint16_t common_features; | |
1323 | uint16_t total_concurrent_sequences; | |
1324 | uint16_t RO_by_information_category; | |
1325 | uint8_t recipient; | |
1326 | uint8_t initiator; | |
1327 | uint16_t receive_data_size; | |
1328 | uint16_t concurrent_sequences; | |
1329 | uint16_t open_sequences_per_exchange; | |
1330 | uint16_t lun_abort_flags; | |
1331 | uint16_t lun_stop_flags; | |
1332 | uint16_t stop_queue_head; | |
1333 | uint16_t stop_queue_tail; | |
1334 | uint16_t port_retry_timer; | |
1335 | uint16_t next_sequence_id; | |
1336 | uint16_t frame_count; | |
1337 | uint16_t PRLI_payload_length; | |
1338 | uint8_t prli_svc_param_word_0[2]; /* Big endian */ | |
1339 | /* Bits 15-0 of word 0 */ | |
1340 | uint8_t prli_svc_param_word_3[2]; /* Big endian */ | |
1341 | /* Bits 15-0 of word 3 */ | |
1342 | uint16_t loop_id; | |
1343 | uint16_t extended_lun_info_list_pointer; | |
1344 | uint16_t extended_lun_stop_list_pointer; | |
1345 | } port_database_t; | |
1346 | ||
1347 | /* | |
1348 | * Port database slave/master states | |
1349 | */ | |
1350 | #define PD_STATE_DISCOVERY 0 | |
1351 | #define PD_STATE_WAIT_DISCOVERY_ACK 1 | |
1352 | #define PD_STATE_PORT_LOGIN 2 | |
1353 | #define PD_STATE_WAIT_PORT_LOGIN_ACK 3 | |
1354 | #define PD_STATE_PROCESS_LOGIN 4 | |
1355 | #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5 | |
1356 | #define PD_STATE_PORT_LOGGED_IN 6 | |
1357 | #define PD_STATE_PORT_UNAVAILABLE 7 | |
1358 | #define PD_STATE_PROCESS_LOGOUT 8 | |
1359 | #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9 | |
1360 | #define PD_STATE_PORT_LOGOUT 10 | |
1361 | #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11 | |
1362 | ||
1363 | ||
4fdfefe5 AV |
1364 | #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1) |
1365 | #define QLA_ZIO_DISABLED 0 | |
1366 | #define QLA_ZIO_DEFAULT_TIMER 2 | |
1367 | ||
1da177e4 LT |
1368 | /* |
1369 | * ISP Initialization Control Block. | |
1370 | * Little endian except where noted. | |
1371 | */ | |
1372 | #define ICB_VERSION 1 | |
1373 | typedef struct { | |
1374 | uint8_t version; | |
1375 | uint8_t reserved_1; | |
1376 | ||
1377 | /* | |
1378 | * LSB BIT 0 = Enable Hard Loop Id | |
1379 | * LSB BIT 1 = Enable Fairness | |
1380 | * LSB BIT 2 = Enable Full-Duplex | |
1381 | * LSB BIT 3 = Enable Fast Posting | |
1382 | * LSB BIT 4 = Enable Target Mode | |
1383 | * LSB BIT 5 = Disable Initiator Mode | |
1384 | * LSB BIT 6 = Enable ADISC | |
1385 | * LSB BIT 7 = Enable Target Inquiry Data | |
1386 | * | |
1387 | * MSB BIT 0 = Enable PDBC Notify | |
1388 | * MSB BIT 1 = Non Participating LIP | |
1389 | * MSB BIT 2 = Descending Loop ID Search | |
1390 | * MSB BIT 3 = Acquire Loop ID in LIPA | |
1391 | * MSB BIT 4 = Stop PortQ on Full Status | |
1392 | * MSB BIT 5 = Full Login after LIP | |
1393 | * MSB BIT 6 = Node Name Option | |
1394 | * MSB BIT 7 = Ext IFWCB enable bit | |
1395 | */ | |
1396 | uint8_t firmware_options[2]; | |
1397 | ||
1398 | uint16_t frame_payload_size; | |
1399 | uint16_t max_iocb_allocation; | |
1400 | uint16_t execution_throttle; | |
1401 | uint8_t retry_count; | |
1402 | uint8_t retry_delay; /* unused */ | |
1403 | uint8_t port_name[WWN_SIZE]; /* Big endian. */ | |
1404 | uint16_t hard_address; | |
1405 | uint8_t inquiry_data; | |
1406 | uint8_t login_timeout; | |
1407 | uint8_t node_name[WWN_SIZE]; /* Big endian. */ | |
1408 | ||
1409 | uint16_t request_q_outpointer; | |
1410 | uint16_t response_q_inpointer; | |
1411 | uint16_t request_q_length; | |
1412 | uint16_t response_q_length; | |
d4556a49 BVA |
1413 | __le64 request_q_address __packed; |
1414 | __le64 response_q_address __packed; | |
1da177e4 LT |
1415 | |
1416 | uint16_t lun_enables; | |
1417 | uint8_t command_resource_count; | |
1418 | uint8_t immediate_notify_resource_count; | |
1419 | uint16_t timeout; | |
1420 | uint8_t reserved_2[2]; | |
1421 | ||
1422 | /* | |
1423 | * LSB BIT 0 = Timer Operation mode bit 0 | |
1424 | * LSB BIT 1 = Timer Operation mode bit 1 | |
1425 | * LSB BIT 2 = Timer Operation mode bit 2 | |
1426 | * LSB BIT 3 = Timer Operation mode bit 3 | |
1427 | * LSB BIT 4 = Init Config Mode bit 0 | |
1428 | * LSB BIT 5 = Init Config Mode bit 1 | |
1429 | * LSB BIT 6 = Init Config Mode bit 2 | |
1430 | * LSB BIT 7 = Enable Non part on LIHA failure | |
1431 | * | |
1432 | * MSB BIT 0 = Enable class 2 | |
1433 | * MSB BIT 1 = Enable ACK0 | |
1434 | * MSB BIT 2 = | |
1435 | * MSB BIT 3 = | |
1436 | * MSB BIT 4 = FC Tape Enable | |
1437 | * MSB BIT 5 = Enable FC Confirm | |
1438 | * MSB BIT 6 = Enable command queuing in target mode | |
1439 | * MSB BIT 7 = No Logo On Link Down | |
1440 | */ | |
1441 | uint8_t add_firmware_options[2]; | |
1442 | ||
1443 | uint8_t response_accumulation_timer; | |
1444 | uint8_t interrupt_delay_timer; | |
1445 | ||
1446 | /* | |
1447 | * LSB BIT 0 = Enable Read xfr_rdy | |
1448 | * LSB BIT 1 = Soft ID only | |
1449 | * LSB BIT 2 = | |
1450 | * LSB BIT 3 = | |
1451 | * LSB BIT 4 = FCP RSP Payload [0] | |
1452 | * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 | |
1453 | * LSB BIT 6 = Enable Out-of-Order frame handling | |
1454 | * LSB BIT 7 = Disable Automatic PLOGI on Local Loop | |
1455 | * | |
1456 | * MSB BIT 0 = Sbus enable - 2300 | |
1457 | * MSB BIT 1 = | |
1458 | * MSB BIT 2 = | |
1459 | * MSB BIT 3 = | |
06c22bd1 | 1460 | * MSB BIT 4 = LED mode |
1da177e4 LT |
1461 | * MSB BIT 5 = enable 50 ohm termination |
1462 | * MSB BIT 6 = Data Rate (2300 only) | |
1463 | * MSB BIT 7 = Data Rate (2300 only) | |
1464 | */ | |
1465 | uint8_t special_options[2]; | |
1466 | ||
1467 | uint8_t reserved_3[26]; | |
1468 | } init_cb_t; | |
1469 | ||
1470 | /* | |
1471 | * Get Link Status mailbox command return buffer. | |
1472 | */ | |
3d71644c AV |
1473 | #define GLSO_SEND_RPS BIT_0 |
1474 | #define GLSO_USE_DID BIT_3 | |
1475 | ||
43ef0580 AV |
1476 | struct link_statistics { |
1477 | uint32_t link_fail_cnt; | |
1478 | uint32_t loss_sync_cnt; | |
1479 | uint32_t loss_sig_cnt; | |
1480 | uint32_t prim_seq_err_cnt; | |
1481 | uint32_t inval_xmit_word_cnt; | |
1482 | uint32_t inval_crc_cnt; | |
032d8dd7 | 1483 | uint32_t lip_cnt; |
243de676 HZ |
1484 | uint32_t link_up_cnt; |
1485 | uint32_t link_down_loop_init_tmo; | |
1486 | uint32_t link_down_los; | |
1487 | uint32_t link_down_loss_rcv_clk; | |
1488 | uint32_t reserved0[5]; | |
1489 | uint32_t port_cfg_chg; | |
1490 | uint32_t reserved1[11]; | |
1491 | uint32_t rsp_q_full; | |
1492 | uint32_t atio_q_full; | |
1493 | uint32_t drop_ae; | |
1494 | uint32_t els_proto_err; | |
1495 | uint32_t reserved2; | |
43ef0580 AV |
1496 | uint32_t tx_frames; |
1497 | uint32_t rx_frames; | |
fabbb8df JC |
1498 | uint32_t discarded_frames; |
1499 | uint32_t dropped_frames; | |
243de676 | 1500 | uint32_t reserved3; |
43ef0580 | 1501 | uint32_t nos_rcvd; |
243de676 HZ |
1502 | uint32_t reserved4[4]; |
1503 | uint32_t tx_prjt; | |
1504 | uint32_t rcv_exfail; | |
1505 | uint32_t rcv_abts; | |
1506 | uint32_t seq_frm_miss; | |
1507 | uint32_t corr_err; | |
1508 | uint32_t mb_rqst; | |
1509 | uint32_t nport_full; | |
1510 | uint32_t eofa; | |
1511 | uint32_t reserved5; | |
1512 | uint32_t fpm_recv_word_cnt_lo; | |
1513 | uint32_t fpm_recv_word_cnt_hi; | |
1514 | uint32_t fpm_disc_word_cnt_lo; | |
1515 | uint32_t fpm_disc_word_cnt_hi; | |
1516 | uint32_t fpm_xmit_word_cnt_lo; | |
1517 | uint32_t fpm_xmit_word_cnt_hi; | |
1518 | uint32_t reserved6[70]; | |
43ef0580 | 1519 | }; |
1da177e4 LT |
1520 | |
1521 | /* | |
1522 | * NVRAM Command values. | |
1523 | */ | |
1524 | #define NV_START_BIT BIT_2 | |
1525 | #define NV_WRITE_OP (BIT_26+BIT_24) | |
1526 | #define NV_READ_OP (BIT_26+BIT_25) | |
1527 | #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24) | |
1528 | #define NV_MASK_OP (BIT_26+BIT_25+BIT_24) | |
1529 | #define NV_DELAY_COUNT 10 | |
1530 | ||
1531 | /* | |
1532 | * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition. | |
1533 | */ | |
1534 | typedef struct { | |
1535 | /* | |
1536 | * NVRAM header | |
1537 | */ | |
1538 | uint8_t id[4]; | |
1539 | uint8_t nvram_version; | |
1540 | uint8_t reserved_0; | |
1541 | ||
1542 | /* | |
1543 | * NVRAM RISC parameter block | |
1544 | */ | |
1545 | uint8_t parameter_block_version; | |
1546 | uint8_t reserved_1; | |
1547 | ||
1548 | /* | |
1549 | * LSB BIT 0 = Enable Hard Loop Id | |
1550 | * LSB BIT 1 = Enable Fairness | |
1551 | * LSB BIT 2 = Enable Full-Duplex | |
1552 | * LSB BIT 3 = Enable Fast Posting | |
1553 | * LSB BIT 4 = Enable Target Mode | |
1554 | * LSB BIT 5 = Disable Initiator Mode | |
1555 | * LSB BIT 6 = Enable ADISC | |
1556 | * LSB BIT 7 = Enable Target Inquiry Data | |
1557 | * | |
1558 | * MSB BIT 0 = Enable PDBC Notify | |
1559 | * MSB BIT 1 = Non Participating LIP | |
1560 | * MSB BIT 2 = Descending Loop ID Search | |
1561 | * MSB BIT 3 = Acquire Loop ID in LIPA | |
1562 | * MSB BIT 4 = Stop PortQ on Full Status | |
1563 | * MSB BIT 5 = Full Login after LIP | |
1564 | * MSB BIT 6 = Node Name Option | |
1565 | * MSB BIT 7 = Ext IFWCB enable bit | |
1566 | */ | |
1567 | uint8_t firmware_options[2]; | |
1568 | ||
1569 | uint16_t frame_payload_size; | |
1570 | uint16_t max_iocb_allocation; | |
1571 | uint16_t execution_throttle; | |
1572 | uint8_t retry_count; | |
1573 | uint8_t retry_delay; /* unused */ | |
1574 | uint8_t port_name[WWN_SIZE]; /* Big endian. */ | |
1575 | uint16_t hard_address; | |
1576 | uint8_t inquiry_data; | |
1577 | uint8_t login_timeout; | |
1578 | uint8_t node_name[WWN_SIZE]; /* Big endian. */ | |
1579 | ||
1580 | /* | |
1581 | * LSB BIT 0 = Timer Operation mode bit 0 | |
1582 | * LSB BIT 1 = Timer Operation mode bit 1 | |
1583 | * LSB BIT 2 = Timer Operation mode bit 2 | |
1584 | * LSB BIT 3 = Timer Operation mode bit 3 | |
1585 | * LSB BIT 4 = Init Config Mode bit 0 | |
1586 | * LSB BIT 5 = Init Config Mode bit 1 | |
1587 | * LSB BIT 6 = Init Config Mode bit 2 | |
1588 | * LSB BIT 7 = Enable Non part on LIHA failure | |
1589 | * | |
1590 | * MSB BIT 0 = Enable class 2 | |
1591 | * MSB BIT 1 = Enable ACK0 | |
1592 | * MSB BIT 2 = | |
1593 | * MSB BIT 3 = | |
1594 | * MSB BIT 4 = FC Tape Enable | |
1595 | * MSB BIT 5 = Enable FC Confirm | |
1596 | * MSB BIT 6 = Enable command queuing in target mode | |
1597 | * MSB BIT 7 = No Logo On Link Down | |
1598 | */ | |
1599 | uint8_t add_firmware_options[2]; | |
1600 | ||
1601 | uint8_t response_accumulation_timer; | |
1602 | uint8_t interrupt_delay_timer; | |
1603 | ||
1604 | /* | |
1605 | * LSB BIT 0 = Enable Read xfr_rdy | |
1606 | * LSB BIT 1 = Soft ID only | |
1607 | * LSB BIT 2 = | |
1608 | * LSB BIT 3 = | |
1609 | * LSB BIT 4 = FCP RSP Payload [0] | |
1610 | * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 | |
1611 | * LSB BIT 6 = Enable Out-of-Order frame handling | |
1612 | * LSB BIT 7 = Disable Automatic PLOGI on Local Loop | |
1613 | * | |
1614 | * MSB BIT 0 = Sbus enable - 2300 | |
1615 | * MSB BIT 1 = | |
1616 | * MSB BIT 2 = | |
1617 | * MSB BIT 3 = | |
06c22bd1 | 1618 | * MSB BIT 4 = LED mode |
1da177e4 LT |
1619 | * MSB BIT 5 = enable 50 ohm termination |
1620 | * MSB BIT 6 = Data Rate (2300 only) | |
1621 | * MSB BIT 7 = Data Rate (2300 only) | |
1622 | */ | |
1623 | uint8_t special_options[2]; | |
1624 | ||
1625 | /* Reserved for expanded RISC parameter block */ | |
1626 | uint8_t reserved_2[22]; | |
1627 | ||
1628 | /* | |
1629 | * LSB BIT 0 = Tx Sensitivity 1G bit 0 | |
1630 | * LSB BIT 1 = Tx Sensitivity 1G bit 1 | |
1631 | * LSB BIT 2 = Tx Sensitivity 1G bit 2 | |
1632 | * LSB BIT 3 = Tx Sensitivity 1G bit 3 | |
1633 | * LSB BIT 4 = Rx Sensitivity 1G bit 0 | |
1634 | * LSB BIT 5 = Rx Sensitivity 1G bit 1 | |
1635 | * LSB BIT 6 = Rx Sensitivity 1G bit 2 | |
1636 | * LSB BIT 7 = Rx Sensitivity 1G bit 3 | |
fa2a1ce5 | 1637 | * |
1da177e4 LT |
1638 | * MSB BIT 0 = Tx Sensitivity 2G bit 0 |
1639 | * MSB BIT 1 = Tx Sensitivity 2G bit 1 | |
1640 | * MSB BIT 2 = Tx Sensitivity 2G bit 2 | |
1641 | * MSB BIT 3 = Tx Sensitivity 2G bit 3 | |
1642 | * MSB BIT 4 = Rx Sensitivity 2G bit 0 | |
1643 | * MSB BIT 5 = Rx Sensitivity 2G bit 1 | |
1644 | * MSB BIT 6 = Rx Sensitivity 2G bit 2 | |
1645 | * MSB BIT 7 = Rx Sensitivity 2G bit 3 | |
1646 | * | |
1647 | * LSB BIT 0 = Output Swing 1G bit 0 | |
1648 | * LSB BIT 1 = Output Swing 1G bit 1 | |
1649 | * LSB BIT 2 = Output Swing 1G bit 2 | |
1650 | * LSB BIT 3 = Output Emphasis 1G bit 0 | |
1651 | * LSB BIT 4 = Output Emphasis 1G bit 1 | |
1652 | * LSB BIT 5 = Output Swing 2G bit 0 | |
1653 | * LSB BIT 6 = Output Swing 2G bit 1 | |
1654 | * LSB BIT 7 = Output Swing 2G bit 2 | |
fa2a1ce5 | 1655 | * |
1da177e4 LT |
1656 | * MSB BIT 0 = Output Emphasis 2G bit 0 |
1657 | * MSB BIT 1 = Output Emphasis 2G bit 1 | |
1658 | * MSB BIT 2 = Output Enable | |
1659 | * MSB BIT 3 = | |
1660 | * MSB BIT 4 = | |
1661 | * MSB BIT 5 = | |
1662 | * MSB BIT 6 = | |
1663 | * MSB BIT 7 = | |
1664 | */ | |
1665 | uint8_t seriallink_options[4]; | |
1666 | ||
1667 | /* | |
1668 | * NVRAM host parameter block | |
1669 | * | |
1670 | * LSB BIT 0 = Enable spinup delay | |
1671 | * LSB BIT 1 = Disable BIOS | |
1672 | * LSB BIT 2 = Enable Memory Map BIOS | |
1673 | * LSB BIT 3 = Enable Selectable Boot | |
1674 | * LSB BIT 4 = Disable RISC code load | |
1675 | * LSB BIT 5 = Set cache line size 1 | |
1676 | * LSB BIT 6 = PCI Parity Disable | |
1677 | * LSB BIT 7 = Enable extended logging | |
1678 | * | |
1679 | * MSB BIT 0 = Enable 64bit addressing | |
1680 | * MSB BIT 1 = Enable lip reset | |
1681 | * MSB BIT 2 = Enable lip full login | |
1682 | * MSB BIT 3 = Enable target reset | |
1683 | * MSB BIT 4 = Enable database storage | |
1684 | * MSB BIT 5 = Enable cache flush read | |
1685 | * MSB BIT 6 = Enable database load | |
1686 | * MSB BIT 7 = Enable alternate WWN | |
1687 | */ | |
1688 | uint8_t host_p[2]; | |
1689 | ||
1690 | uint8_t boot_node_name[WWN_SIZE]; | |
1691 | uint8_t boot_lun_number; | |
1692 | uint8_t reset_delay; | |
1693 | uint8_t port_down_retry_count; | |
1694 | uint8_t boot_id_number; | |
1695 | uint16_t max_luns_per_target; | |
1696 | uint8_t fcode_boot_port_name[WWN_SIZE]; | |
1697 | uint8_t alternate_port_name[WWN_SIZE]; | |
1698 | uint8_t alternate_node_name[WWN_SIZE]; | |
1699 | ||
1700 | /* | |
1701 | * BIT 0 = Selective Login | |
1702 | * BIT 1 = Alt-Boot Enable | |
1703 | * BIT 2 = | |
1704 | * BIT 3 = Boot Order List | |
1705 | * BIT 4 = | |
1706 | * BIT 5 = Selective LUN | |
1707 | * BIT 6 = | |
1708 | * BIT 7 = unused | |
1709 | */ | |
1710 | uint8_t efi_parameters; | |
1711 | ||
1712 | uint8_t link_down_timeout; | |
1713 | ||
cca5335c | 1714 | uint8_t adapter_id[16]; |
1da177e4 LT |
1715 | |
1716 | uint8_t alt1_boot_node_name[WWN_SIZE]; | |
1717 | uint16_t alt1_boot_lun_number; | |
1718 | uint8_t alt2_boot_node_name[WWN_SIZE]; | |
1719 | uint16_t alt2_boot_lun_number; | |
1720 | uint8_t alt3_boot_node_name[WWN_SIZE]; | |
1721 | uint16_t alt3_boot_lun_number; | |
1722 | uint8_t alt4_boot_node_name[WWN_SIZE]; | |
1723 | uint16_t alt4_boot_lun_number; | |
1724 | uint8_t alt5_boot_node_name[WWN_SIZE]; | |
1725 | uint16_t alt5_boot_lun_number; | |
1726 | uint8_t alt6_boot_node_name[WWN_SIZE]; | |
1727 | uint16_t alt6_boot_lun_number; | |
1728 | uint8_t alt7_boot_node_name[WWN_SIZE]; | |
1729 | uint16_t alt7_boot_lun_number; | |
1730 | ||
1731 | uint8_t reserved_3[2]; | |
1732 | ||
1733 | /* Offset 200-215 : Model Number */ | |
1734 | uint8_t model_number[16]; | |
1735 | ||
1736 | /* OEM related items */ | |
1737 | uint8_t oem_specific[16]; | |
1738 | ||
1739 | /* | |
1740 | * NVRAM Adapter Features offset 232-239 | |
1741 | * | |
1742 | * LSB BIT 0 = External GBIC | |
1743 | * LSB BIT 1 = Risc RAM parity | |
1744 | * LSB BIT 2 = Buffer Plus Module | |
1745 | * LSB BIT 3 = Multi Chip Adapter | |
1746 | * LSB BIT 4 = Internal connector | |
1747 | * LSB BIT 5 = | |
1748 | * LSB BIT 6 = | |
1749 | * LSB BIT 7 = | |
1750 | * | |
1751 | * MSB BIT 0 = | |
1752 | * MSB BIT 1 = | |
1753 | * MSB BIT 2 = | |
1754 | * MSB BIT 3 = | |
1755 | * MSB BIT 4 = | |
1756 | * MSB BIT 5 = | |
1757 | * MSB BIT 6 = | |
1758 | * MSB BIT 7 = | |
1759 | */ | |
1760 | uint8_t adapter_features[2]; | |
1761 | ||
1762 | uint8_t reserved_4[16]; | |
1763 | ||
1764 | /* Subsystem vendor ID for ISP2200 */ | |
1765 | uint16_t subsystem_vendor_id_2200; | |
1766 | ||
1767 | /* Subsystem device ID for ISP2200 */ | |
1768 | uint16_t subsystem_device_id_2200; | |
1769 | ||
1770 | uint8_t reserved_5; | |
1771 | uint8_t checksum; | |
1772 | } nvram_t; | |
1773 | ||
1774 | /* | |
1775 | * ISP queue - response queue entry definition. | |
1776 | */ | |
1777 | typedef struct { | |
2d70c103 NB |
1778 | uint8_t entry_type; /* Entry type. */ |
1779 | uint8_t entry_count; /* Entry count. */ | |
1780 | uint8_t sys_define; /* System defined. */ | |
1781 | uint8_t entry_status; /* Entry Status. */ | |
1782 | uint32_t handle; /* System defined handle */ | |
1783 | uint8_t data[52]; | |
1da177e4 LT |
1784 | uint32_t signature; |
1785 | #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */ | |
1786 | } response_t; | |
1787 | ||
2d70c103 NB |
1788 | /* |
1789 | * ISP queue - ATIO queue entry definition. | |
1790 | */ | |
1791 | struct atio { | |
1792 | uint8_t entry_type; /* Entry type. */ | |
1793 | uint8_t entry_count; /* Entry count. */ | |
5f35509d QT |
1794 | __le16 attr_n_length; |
1795 | uint8_t data[56]; | |
2d70c103 NB |
1796 | uint32_t signature; |
1797 | #define ATIO_PROCESSED 0xDEADDEAD /* Signature */ | |
1798 | }; | |
1799 | ||
1da177e4 LT |
1800 | typedef union { |
1801 | uint16_t extended; | |
1802 | struct { | |
1803 | uint8_t reserved; | |
1804 | uint8_t standard; | |
1805 | } id; | |
1806 | } target_id_t; | |
1807 | ||
1808 | #define SET_TARGET_ID(ha, to, from) \ | |
1809 | do { \ | |
1810 | if (HAS_EXTENDED_IDS(ha)) \ | |
1811 | to.extended = cpu_to_le16(from); \ | |
1812 | else \ | |
1813 | to.id.standard = (uint8_t)from; \ | |
1814 | } while (0) | |
1815 | ||
1816 | /* | |
1817 | * ISP queue - command entry structure definition. | |
1818 | */ | |
1819 | #define COMMAND_TYPE 0x11 /* Command entry */ | |
1da177e4 LT |
1820 | typedef struct { |
1821 | uint8_t entry_type; /* Entry type. */ | |
1822 | uint8_t entry_count; /* Entry count. */ | |
1823 | uint8_t sys_define; /* System defined. */ | |
1824 | uint8_t entry_status; /* Entry Status. */ | |
1825 | uint32_t handle; /* System handle. */ | |
1826 | target_id_t target; /* SCSI ID */ | |
1827 | uint16_t lun; /* SCSI LUN */ | |
1828 | uint16_t control_flags; /* Control flags. */ | |
1829 | #define CF_WRITE BIT_6 | |
1830 | #define CF_READ BIT_5 | |
1831 | #define CF_SIMPLE_TAG BIT_3 | |
1832 | #define CF_ORDERED_TAG BIT_2 | |
1833 | #define CF_HEAD_TAG BIT_1 | |
1834 | uint16_t reserved_1; | |
1835 | uint16_t timeout; /* Command timeout. */ | |
1836 | uint16_t dseg_count; /* Data segment count. */ | |
1837 | uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ | |
1838 | uint32_t byte_count; /* Total byte count. */ | |
15b7a68c BVA |
1839 | union { |
1840 | struct dsd32 dsd32[3]; | |
1841 | struct dsd64 dsd64[2]; | |
1842 | }; | |
1da177e4 LT |
1843 | } cmd_entry_t; |
1844 | ||
1845 | /* | |
1846 | * ISP queue - 64-Bit addressing, command entry structure definition. | |
1847 | */ | |
1848 | #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */ | |
1849 | typedef struct { | |
1850 | uint8_t entry_type; /* Entry type. */ | |
1851 | uint8_t entry_count; /* Entry count. */ | |
1852 | uint8_t sys_define; /* System defined. */ | |
1853 | uint8_t entry_status; /* Entry Status. */ | |
1854 | uint32_t handle; /* System handle. */ | |
1855 | target_id_t target; /* SCSI ID */ | |
1856 | uint16_t lun; /* SCSI LUN */ | |
1857 | uint16_t control_flags; /* Control flags. */ | |
1858 | uint16_t reserved_1; | |
1859 | uint16_t timeout; /* Command timeout. */ | |
1860 | uint16_t dseg_count; /* Data segment count. */ | |
1861 | uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ | |
1862 | uint32_t byte_count; /* Total byte count. */ | |
15b7a68c | 1863 | struct dsd64 dsd[2]; |
1da177e4 LT |
1864 | } cmd_a64_entry_t, request_t; |
1865 | ||
1866 | /* | |
1867 | * ISP queue - continuation entry structure definition. | |
1868 | */ | |
1869 | #define CONTINUE_TYPE 0x02 /* Continuation entry. */ | |
1870 | typedef struct { | |
1871 | uint8_t entry_type; /* Entry type. */ | |
1872 | uint8_t entry_count; /* Entry count. */ | |
1873 | uint8_t sys_define; /* System defined. */ | |
1874 | uint8_t entry_status; /* Entry Status. */ | |
1875 | uint32_t reserved; | |
15b7a68c | 1876 | struct dsd32 dsd[7]; |
1da177e4 LT |
1877 | } cont_entry_t; |
1878 | ||
1879 | /* | |
1880 | * ISP queue - 64-Bit addressing, continuation entry structure definition. | |
1881 | */ | |
1882 | #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */ | |
1883 | typedef struct { | |
1884 | uint8_t entry_type; /* Entry type. */ | |
1885 | uint8_t entry_count; /* Entry count. */ | |
1886 | uint8_t sys_define; /* System defined. */ | |
1887 | uint8_t entry_status; /* Entry Status. */ | |
15b7a68c | 1888 | struct dsd64 dsd[5]; |
1da177e4 LT |
1889 | } cont_a64_entry_t; |
1890 | ||
bad75002 | 1891 | #define PO_MODE_DIF_INSERT 0 |
9e522cd8 AE |
1892 | #define PO_MODE_DIF_REMOVE 1 |
1893 | #define PO_MODE_DIF_PASS 2 | |
1894 | #define PO_MODE_DIF_REPLACE 3 | |
1895 | #define PO_MODE_DIF_TCP_CKSUM 6 | |
bad75002 | 1896 | #define PO_ENABLE_INCR_GUARD_SEED BIT_3 |
bad75002 | 1897 | #define PO_DISABLE_GUARD_CHECK BIT_4 |
f83adb61 QT |
1898 | #define PO_DISABLE_INCR_REF_TAG BIT_5 |
1899 | #define PO_DIS_HEADER_MODE BIT_7 | |
1900 | #define PO_ENABLE_DIF_BUNDLING BIT_8 | |
1901 | #define PO_DIS_FRAME_MODE BIT_9 | |
1902 | #define PO_DIS_VALD_APP_ESC BIT_10 /* Dis validation for escape tag/ffffh */ | |
1903 | #define PO_DIS_VALD_APP_REF_ESC BIT_11 | |
1904 | ||
1905 | #define PO_DIS_APP_TAG_REPL BIT_12 /* disable REG Tag replacement */ | |
1906 | #define PO_DIS_REF_TAG_REPL BIT_13 | |
1907 | #define PO_DIS_APP_TAG_VALD BIT_14 /* disable REF Tag validation */ | |
1908 | #define PO_DIS_REF_TAG_VALD BIT_15 | |
1909 | ||
bad75002 AE |
1910 | /* |
1911 | * ISP queue - 64-Bit addressing, continuation crc entry structure definition. | |
1912 | */ | |
1913 | struct crc_context { | |
1914 | uint32_t handle; /* System handle. */ | |
c7ee3bd4 QT |
1915 | __le32 ref_tag; |
1916 | __le16 app_tag; | |
bad75002 AE |
1917 | uint8_t ref_tag_mask[4]; /* Validation/Replacement Mask*/ |
1918 | uint8_t app_tag_mask[2]; /* Validation/Replacement Mask*/ | |
c7ee3bd4 QT |
1919 | __le16 guard_seed; /* Initial Guard Seed */ |
1920 | __le16 prot_opts; /* Requested Data Protection Mode */ | |
1921 | __le16 blk_size; /* Data size in bytes */ | |
bad75002 AE |
1922 | uint16_t runt_blk_guard; /* Guard value for runt block (tape |
1923 | * only) */ | |
c7ee3bd4 | 1924 | __le32 byte_count; /* Total byte count/ total data |
bad75002 AE |
1925 | * transfer count */ |
1926 | union { | |
1927 | struct { | |
1928 | uint32_t reserved_1; | |
1929 | uint16_t reserved_2; | |
1930 | uint16_t reserved_3; | |
1931 | uint32_t reserved_4; | |
9e75b5e2 | 1932 | struct dsd64 data_dsd[1]; |
bad75002 AE |
1933 | uint32_t reserved_5[2]; |
1934 | uint32_t reserved_6; | |
1935 | } nobundling; | |
1936 | struct { | |
c7ee3bd4 | 1937 | __le32 dif_byte_count; /* Total DIF byte |
bad75002 AE |
1938 | * count */ |
1939 | uint16_t reserved_1; | |
c7ee3bd4 | 1940 | __le16 dseg_count; /* Data segment count */ |
bad75002 | 1941 | uint32_t reserved_2; |
9e75b5e2 | 1942 | struct dsd64 data_dsd[1]; |
15b7a68c | 1943 | struct dsd64 dif_dsd; |
bad75002 AE |
1944 | } bundling; |
1945 | } u; | |
1946 | ||
1947 | struct fcp_cmnd fcp_cmnd; | |
1948 | dma_addr_t crc_ctx_dma; | |
1949 | /* List of DMA context transfers */ | |
1950 | struct list_head dsd_list; | |
1951 | ||
50b81275 GM |
1952 | /* List of DIF Bundling context DMA address */ |
1953 | struct list_head ldif_dsd_list; | |
1954 | u8 no_ldif_dsd; | |
1955 | ||
1956 | struct list_head ldif_dma_hndl_list; | |
1957 | u32 dif_bundl_len; | |
1958 | u8 no_dif_bundl; | |
bad75002 AE |
1959 | /* This structure should not exceed 512 bytes */ |
1960 | }; | |
1961 | ||
1962 | #define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun)) | |
1963 | #define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun)) | |
1964 | ||
1da177e4 LT |
1965 | /* |
1966 | * ISP queue - status entry structure definition. | |
1967 | */ | |
1968 | #define STATUS_TYPE 0x03 /* Status entry. */ | |
1969 | typedef struct { | |
1970 | uint8_t entry_type; /* Entry type. */ | |
1971 | uint8_t entry_count; /* Entry count. */ | |
1972 | uint8_t sys_define; /* System defined. */ | |
1973 | uint8_t entry_status; /* Entry Status. */ | |
1974 | uint32_t handle; /* System handle. */ | |
1975 | uint16_t scsi_status; /* SCSI status. */ | |
1976 | uint16_t comp_status; /* Completion status. */ | |
1977 | uint16_t state_flags; /* State flags. */ | |
1978 | uint16_t status_flags; /* Status flags. */ | |
1979 | uint16_t rsp_info_len; /* Response Info Length. */ | |
1980 | uint16_t req_sense_length; /* Request sense data length. */ | |
1981 | uint32_t residual_length; /* Residual transfer length. */ | |
1982 | uint8_t rsp_info[8]; /* FCP response information. */ | |
1983 | uint8_t req_sense_data[32]; /* Request sense data. */ | |
1984 | } sts_entry_t; | |
1985 | ||
1986 | /* | |
1987 | * Status entry entry status | |
1988 | */ | |
3d71644c | 1989 | #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */ |
1da177e4 LT |
1990 | #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */ |
1991 | #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */ | |
1992 | #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */ | |
1993 | #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */ | |
1994 | #define RF_BUSY BIT_1 /* Busy */ | |
3d71644c AV |
1995 | #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \ |
1996 | RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY) | |
1997 | #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \ | |
1998 | RF_INV_E_TYPE) | |
1da177e4 LT |
1999 | |
2000 | /* | |
2001 | * Status entry SCSI status bit definitions. | |
2002 | */ | |
2003 | #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/ | |
2004 | #define SS_RESIDUAL_UNDER BIT_11 | |
2005 | #define SS_RESIDUAL_OVER BIT_10 | |
2006 | #define SS_SENSE_LEN_VALID BIT_9 | |
2007 | #define SS_RESPONSE_INFO_LEN_VALID BIT_8 | |
df2e32c5 | 2008 | #define SS_SCSI_STATUS_BYTE 0xff |
1da177e4 LT |
2009 | |
2010 | #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3) | |
2011 | #define SS_BUSY_CONDITION BIT_3 | |
2012 | #define SS_CONDITION_MET BIT_2 | |
2013 | #define SS_CHECK_CONDITION BIT_1 | |
2014 | ||
2015 | /* | |
2016 | * Status entry completion status | |
2017 | */ | |
2018 | #define CS_COMPLETE 0x0 /* No errors */ | |
2019 | #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */ | |
2020 | #define CS_DMA 0x2 /* A DMA direction error. */ | |
2021 | #define CS_TRANSPORT 0x3 /* Transport error. */ | |
2022 | #define CS_RESET 0x4 /* SCSI bus reset occurred */ | |
2023 | #define CS_ABORTED 0x5 /* System aborted command. */ | |
2024 | #define CS_TIMEOUT 0x6 /* Timeout error. */ | |
2025 | #define CS_DATA_OVERRUN 0x7 /* Data overrun. */ | |
bad75002 | 2026 | #define CS_DIF_ERROR 0xC /* DIF error detected */ |
1da177e4 LT |
2027 | |
2028 | #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */ | |
2029 | #define CS_QUEUE_FULL 0x1C /* Queue Full. */ | |
2030 | #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */ | |
2031 | /* (selection timeout) */ | |
2032 | #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */ | |
2033 | #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */ | |
2034 | #define CS_PORT_BUSY 0x2B /* Port Busy */ | |
2035 | #define CS_COMPLETE_CHKCOND 0x30 /* Error? */ | |
f934c9d0 CD |
2036 | #define CS_IOCB_ERROR 0x31 /* Generic error for IOCB request |
2037 | failure */ | |
1da177e4 LT |
2038 | #define CS_BAD_PAYLOAD 0x80 /* Driver defined */ |
2039 | #define CS_UNKNOWN 0x81 /* Driver defined */ | |
2040 | #define CS_RETRY 0x82 /* Driver defined */ | |
2041 | #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */ | |
2042 | ||
a9b6f722 SK |
2043 | #define CS_BIDIR_RD_OVERRUN 0x700 |
2044 | #define CS_BIDIR_RD_WR_OVERRUN 0x707 | |
2045 | #define CS_BIDIR_RD_OVERRUN_WR_UNDERRUN 0x715 | |
2046 | #define CS_BIDIR_RD_UNDERRUN 0x1500 | |
2047 | #define CS_BIDIR_RD_UNDERRUN_WR_OVERRUN 0x1507 | |
2048 | #define CS_BIDIR_RD_WR_UNDERRUN 0x1515 | |
2049 | #define CS_BIDIR_DMA 0x200 | |
1da177e4 LT |
2050 | /* |
2051 | * Status entry status flags | |
2052 | */ | |
2053 | #define SF_ABTS_TERMINATED BIT_10 | |
2054 | #define SF_LOGOUT_SENT BIT_13 | |
2055 | ||
2056 | /* | |
2057 | * ISP queue - status continuation entry structure definition. | |
2058 | */ | |
2059 | #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */ | |
2060 | typedef struct { | |
2061 | uint8_t entry_type; /* Entry type. */ | |
2062 | uint8_t entry_count; /* Entry count. */ | |
2063 | uint8_t sys_define; /* System defined. */ | |
2064 | uint8_t entry_status; /* Entry Status. */ | |
2065 | uint8_t data[60]; /* data */ | |
2066 | } sts_cont_entry_t; | |
2067 | ||
2068 | /* | |
2069 | * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles) | |
2070 | * structure definition. | |
2071 | */ | |
2072 | #define STATUS_TYPE_21 0x21 /* Status entry. */ | |
2073 | typedef struct { | |
2074 | uint8_t entry_type; /* Entry type. */ | |
2075 | uint8_t entry_count; /* Entry count. */ | |
2076 | uint8_t handle_count; /* Handle count. */ | |
2077 | uint8_t entry_status; /* Entry Status. */ | |
2078 | uint32_t handle[15]; /* System handles. */ | |
2079 | } sts21_entry_t; | |
2080 | ||
2081 | /* | |
2082 | * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles) | |
2083 | * structure definition. | |
2084 | */ | |
2085 | #define STATUS_TYPE_22 0x22 /* Status entry. */ | |
2086 | typedef struct { | |
2087 | uint8_t entry_type; /* Entry type. */ | |
2088 | uint8_t entry_count; /* Entry count. */ | |
2089 | uint8_t handle_count; /* Handle count. */ | |
2090 | uint8_t entry_status; /* Entry Status. */ | |
2091 | uint16_t handle[30]; /* System handles. */ | |
2092 | } sts22_entry_t; | |
2093 | ||
2094 | /* | |
2095 | * ISP queue - marker entry structure definition. | |
2096 | */ | |
2097 | #define MARKER_TYPE 0x04 /* Marker entry. */ | |
2098 | typedef struct { | |
2099 | uint8_t entry_type; /* Entry type. */ | |
2100 | uint8_t entry_count; /* Entry count. */ | |
2101 | uint8_t handle_count; /* Handle count. */ | |
2102 | uint8_t entry_status; /* Entry Status. */ | |
2103 | uint32_t sys_define_2; /* System defined. */ | |
2104 | target_id_t target; /* SCSI ID */ | |
2105 | uint8_t modifier; /* Modifier (7-0). */ | |
2106 | #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */ | |
2107 | #define MK_SYNC_ID 1 /* Synchronize ID */ | |
2108 | #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */ | |
2109 | #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */ | |
2110 | /* clear port changed, */ | |
2111 | /* use sequence number. */ | |
2112 | uint8_t reserved_1; | |
2113 | uint16_t sequence_number; /* Sequence number of event */ | |
2114 | uint16_t lun; /* SCSI LUN */ | |
2115 | uint8_t reserved_2[48]; | |
2116 | } mrk_entry_t; | |
2117 | ||
2118 | /* | |
2119 | * ISP queue - Management Server entry structure definition. | |
2120 | */ | |
2121 | #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */ | |
2122 | typedef struct { | |
2123 | uint8_t entry_type; /* Entry type. */ | |
2124 | uint8_t entry_count; /* Entry count. */ | |
2125 | uint8_t handle_count; /* Handle count. */ | |
2126 | uint8_t entry_status; /* Entry Status. */ | |
2127 | uint32_t handle1; /* System handle. */ | |
2128 | target_id_t loop_id; | |
2129 | uint16_t status; | |
2130 | uint16_t control_flags; /* Control flags. */ | |
2131 | uint16_t reserved2; | |
2132 | uint16_t timeout; | |
2133 | uint16_t cmd_dsd_count; | |
2134 | uint16_t total_dsd_count; | |
2135 | uint8_t type; | |
2136 | uint8_t r_ctl; | |
2137 | uint16_t rx_id; | |
2138 | uint16_t reserved3; | |
2139 | uint32_t handle2; | |
2140 | uint32_t rsp_bytecount; | |
2141 | uint32_t req_bytecount; | |
15b7a68c BVA |
2142 | struct dsd64 req_dsd; |
2143 | struct dsd64 rsp_dsd; | |
1da177e4 LT |
2144 | } ms_iocb_entry_t; |
2145 | ||
2146 | ||
2147 | /* | |
2148 | * ISP queue - Mailbox Command entry structure definition. | |
2149 | */ | |
2150 | #define MBX_IOCB_TYPE 0x39 | |
2151 | struct mbx_entry { | |
2152 | uint8_t entry_type; | |
2153 | uint8_t entry_count; | |
2154 | uint8_t sys_define1; | |
2155 | /* Use sys_define1 for source type */ | |
2156 | #define SOURCE_SCSI 0x00 | |
2157 | #define SOURCE_IP 0x01 | |
2158 | #define SOURCE_VI 0x02 | |
2159 | #define SOURCE_SCTP 0x03 | |
2160 | #define SOURCE_MP 0x04 | |
2161 | #define SOURCE_MPIOCTL 0x05 | |
2162 | #define SOURCE_ASYNC_IOCB 0x07 | |
2163 | ||
2164 | uint8_t entry_status; | |
2165 | ||
2166 | uint32_t handle; | |
2167 | target_id_t loop_id; | |
2168 | ||
2169 | uint16_t status; | |
2170 | uint16_t state_flags; | |
2171 | uint16_t status_flags; | |
2172 | ||
2173 | uint32_t sys_define2[2]; | |
2174 | ||
2175 | uint16_t mb0; | |
2176 | uint16_t mb1; | |
2177 | uint16_t mb2; | |
2178 | uint16_t mb3; | |
2179 | uint16_t mb6; | |
2180 | uint16_t mb7; | |
2181 | uint16_t mb9; | |
2182 | uint16_t mb10; | |
2183 | uint32_t reserved_2[2]; | |
2184 | uint8_t node_name[WWN_SIZE]; | |
2185 | uint8_t port_name[WWN_SIZE]; | |
2186 | }; | |
2187 | ||
5d964837 QT |
2188 | #ifndef IMMED_NOTIFY_TYPE |
2189 | #define IMMED_NOTIFY_TYPE 0x0D /* Immediate notify entry. */ | |
2190 | /* | |
2191 | * ISP queue - immediate notify entry structure definition. | |
2192 | * This is sent by the ISP to the Target driver. | |
2193 | * This IOCB would have report of events sent by the | |
2194 | * initiator, that needs to be handled by the target | |
2195 | * driver immediately. | |
2196 | */ | |
2197 | struct imm_ntfy_from_isp { | |
2198 | uint8_t entry_type; /* Entry type. */ | |
2199 | uint8_t entry_count; /* Entry count. */ | |
2200 | uint8_t sys_define; /* System defined. */ | |
2201 | uint8_t entry_status; /* Entry Status. */ | |
2202 | union { | |
2203 | struct { | |
2204 | uint32_t sys_define_2; /* System defined. */ | |
2205 | target_id_t target; | |
2206 | uint16_t lun; | |
2207 | uint8_t target_id; | |
2208 | uint8_t reserved_1; | |
2209 | uint16_t status_modifier; | |
2210 | uint16_t status; | |
2211 | uint16_t task_flags; | |
2212 | uint16_t seq_id; | |
2213 | uint16_t srr_rx_id; | |
2214 | uint32_t srr_rel_offs; | |
2215 | uint16_t srr_ui; | |
2216 | #define SRR_IU_DATA_IN 0x1 | |
2217 | #define SRR_IU_DATA_OUT 0x5 | |
2218 | #define SRR_IU_STATUS 0x7 | |
2219 | uint16_t srr_ox_id; | |
2220 | uint8_t reserved_2[28]; | |
2221 | } isp2x; | |
2222 | struct { | |
2223 | uint32_t reserved; | |
2224 | uint16_t nport_handle; | |
2225 | uint16_t reserved_2; | |
2226 | uint16_t flags; | |
2227 | #define NOTIFY24XX_FLAGS_GLOBAL_TPRLO BIT_1 | |
2228 | #define NOTIFY24XX_FLAGS_PUREX_IOCB BIT_0 | |
2229 | uint16_t srr_rx_id; | |
2230 | uint16_t status; | |
2231 | uint8_t status_subcode; | |
2232 | uint8_t fw_handle; | |
2233 | uint32_t exchange_address; | |
2234 | uint32_t srr_rel_offs; | |
2235 | uint16_t srr_ui; | |
2236 | uint16_t srr_ox_id; | |
2237 | union { | |
2238 | struct { | |
2239 | uint8_t node_name[8]; | |
2240 | } plogi; /* PLOGI/ADISC/PDISC */ | |
2241 | struct { | |
2242 | /* PRLI word 3 bit 0-15 */ | |
2243 | uint16_t wd3_lo; | |
2244 | uint8_t resv0[6]; | |
2245 | } prli; | |
2246 | struct { | |
2247 | uint8_t port_id[3]; | |
2248 | uint8_t resv1; | |
2249 | uint16_t nport_handle; | |
2250 | uint16_t resv2; | |
2251 | } req_els; | |
2252 | } u; | |
2253 | uint8_t port_name[8]; | |
2254 | uint8_t resv3[3]; | |
2255 | uint8_t vp_index; | |
2256 | uint32_t reserved_5; | |
2257 | uint8_t port_id[3]; | |
2258 | uint8_t reserved_6; | |
2259 | } isp24; | |
2260 | } u; | |
2261 | uint16_t reserved_7; | |
2262 | uint16_t ox_id; | |
2263 | } __packed; | |
2264 | #endif | |
2265 | ||
1da177e4 LT |
2266 | /* |
2267 | * ISP request and response queue entry sizes | |
2268 | */ | |
2269 | #define RESPONSE_ENTRY_SIZE (sizeof(response_t)) | |
2270 | #define REQUEST_ENTRY_SIZE (sizeof(request_t)) | |
2271 | ||
2272 | ||
1da177e4 LT |
2273 | |
2274 | /* | |
2275 | * Switch info gathering structure. | |
2276 | */ | |
2277 | typedef struct { | |
2278 | port_id_t d_id; | |
2279 | uint8_t node_name[WWN_SIZE]; | |
2280 | uint8_t port_name[WWN_SIZE]; | |
d8b45213 | 2281 | uint8_t fabric_port_name[WWN_SIZE]; |
d8b45213 | 2282 | uint16_t fp_speed; |
e8c72ba5 | 2283 | uint8_t fc4_type; |
84ed362a | 2284 | uint8_t fc4_features; |
1da177e4 LT |
2285 | } sw_info_t; |
2286 | ||
e8c72ba5 CD |
2287 | /* FCP-4 types */ |
2288 | #define FC4_TYPE_FCP_SCSI 0x08 | |
33b28357 | 2289 | #define FC4_TYPE_NVME 0x28 |
e8c72ba5 CD |
2290 | #define FC4_TYPE_OTHER 0x0 |
2291 | #define FC4_TYPE_UNKNOWN 0xff | |
2292 | ||
726b8548 QT |
2293 | /* mailbox command 4G & above */ |
2294 | struct mbx_24xx_entry { | |
2295 | uint8_t entry_type; | |
2296 | uint8_t entry_count; | |
2297 | uint8_t sys_define1; | |
2298 | uint8_t entry_status; | |
2299 | uint32_t handle; | |
2300 | uint16_t mb[28]; | |
2301 | }; | |
2302 | ||
2303 | #define IOCB_SIZE 64 | |
2304 | ||
1da177e4 LT |
2305 | /* |
2306 | * Fibre channel port type. | |
2307 | */ | |
5d964837 | 2308 | typedef enum { |
1da177e4 LT |
2309 | FCT_UNKNOWN, |
2310 | FCT_RSCN, | |
2311 | FCT_SWITCH, | |
2312 | FCT_BROADCAST, | |
2313 | FCT_INITIATOR, | |
a5d42f4c | 2314 | FCT_TARGET, |
a6a6d058 HR |
2315 | FCT_NVME_INITIATOR = 0x10, |
2316 | FCT_NVME_TARGET = 0x20, | |
2317 | FCT_NVME_DISCOVERY = 0x40, | |
2318 | FCT_NVME = 0xf0, | |
1da177e4 LT |
2319 | } fc_port_type_t; |
2320 | ||
726b8548 QT |
2321 | enum qla_sess_deletion { |
2322 | QLA_SESS_DELETION_NONE = 0, | |
2323 | QLA_SESS_DELETION_IN_PROGRESS, | |
2324 | QLA_SESS_DELETED, | |
2325 | }; | |
2326 | ||
5d964837 QT |
2327 | enum qlt_plogi_link_t { |
2328 | QLT_PLOGI_LINK_SAME_WWN, | |
2329 | QLT_PLOGI_LINK_CONFLICT, | |
2330 | QLT_PLOGI_LINK_MAX | |
2331 | }; | |
2332 | ||
2333 | struct qlt_plogi_ack_t { | |
2334 | struct list_head list; | |
2335 | struct imm_ntfy_from_isp iocb; | |
2336 | port_id_t id; | |
2337 | int ref_count; | |
726b8548 QT |
2338 | void *fcport; |
2339 | }; | |
2340 | ||
2341 | struct ct_sns_desc { | |
2342 | struct ct_sns_pkt *ct_sns; | |
2343 | dma_addr_t ct_sns_dma; | |
2344 | }; | |
2345 | ||
2346 | enum discovery_state { | |
2347 | DSC_DELETED, | |
a4239945 | 2348 | DSC_GNN_ID, |
726b8548 QT |
2349 | DSC_GNL, |
2350 | DSC_LOGIN_PEND, | |
2351 | DSC_LOGIN_FAILED, | |
2352 | DSC_GPDB, | |
726b8548 QT |
2353 | DSC_UPD_FCPORT, |
2354 | DSC_LOGIN_COMPLETE, | |
f13515ac | 2355 | DSC_ADISC, |
726b8548 QT |
2356 | DSC_DELETE_PEND, |
2357 | }; | |
2358 | ||
2359 | enum login_state { /* FW control Target side */ | |
2360 | DSC_LS_LLIOCB_SENT = 2, | |
2361 | DSC_LS_PLOGI_PEND, | |
2362 | DSC_LS_PLOGI_COMP, | |
2363 | DSC_LS_PRLI_PEND, | |
2364 | DSC_LS_PRLI_COMP, | |
2365 | DSC_LS_PORT_UNAVAIL, | |
2366 | DSC_LS_PRLO_PEND = 9, | |
2367 | DSC_LS_LOGO_PEND, | |
2368 | }; | |
2369 | ||
41dc529a QT |
2370 | enum rscn_addr_format { |
2371 | RSCN_PORT_ADDR, | |
2372 | RSCN_AREA_ADDR, | |
2373 | RSCN_DOM_ADDR, | |
2374 | RSCN_FAB_ADDR, | |
2375 | }; | |
2376 | ||
1da177e4 LT |
2377 | /* |
2378 | * Fibre channel port structure. | |
2379 | */ | |
2380 | typedef struct fc_port { | |
2381 | struct list_head list; | |
7b867cf7 | 2382 | struct scsi_qla_host *vha; |
1da177e4 LT |
2383 | |
2384 | uint8_t node_name[WWN_SIZE]; | |
2385 | uint8_t port_name[WWN_SIZE]; | |
2386 | port_id_t d_id; | |
2387 | uint16_t loop_id; | |
2388 | uint16_t old_loop_id; | |
2389 | ||
5d964837 QT |
2390 | unsigned int conf_compl_supported:1; |
2391 | unsigned int deleted:2; | |
1ae634eb | 2392 | unsigned int free_pending:1; |
5d964837 QT |
2393 | unsigned int local:1; |
2394 | unsigned int logout_on_delete:1; | |
726b8548 | 2395 | unsigned int logo_ack_needed:1; |
5d964837 QT |
2396 | unsigned int keep_nport_handle:1; |
2397 | unsigned int send_els_logo:1; | |
726b8548 QT |
2398 | unsigned int login_pause:1; |
2399 | unsigned int login_succ:1; | |
c0c462c8 | 2400 | unsigned int query:1; |
a4239945 | 2401 | unsigned int id_changed:1; |
cb873ba4 | 2402 | unsigned int scan_needed:1; |
7f2a398d | 2403 | unsigned int n2n_flag:1; |
86196a8f | 2404 | unsigned int explicit_logout:1; |
8aaac2d7 | 2405 | unsigned int prli_pend_timer:1; |
5d964837 | 2406 | |
5621b0dd | 2407 | struct completion nvme_del_done; |
a5d42f4c DG |
2408 | uint32_t nvme_prli_service_param; |
2409 | #define NVME_PRLI_SP_CONF BIT_7 | |
2410 | #define NVME_PRLI_SP_INITIATOR BIT_5 | |
2411 | #define NVME_PRLI_SP_TARGET BIT_4 | |
2412 | #define NVME_PRLI_SP_DISCOVERY BIT_3 | |
03aaa89f | 2413 | #define NVME_PRLI_SP_FIRST_BURST BIT_0 |
a5d42f4c | 2414 | uint8_t nvme_flag; |
03aaa89f | 2415 | uint32_t nvme_first_burst_size; |
a5d42f4c | 2416 | #define NVME_FLAG_REGISTERED 4 |
9dd9686b | 2417 | #define NVME_FLAG_DELETING 2 |
870fe24f | 2418 | #define NVME_FLAG_RESETTING 1 |
a5d42f4c | 2419 | |
726b8548 | 2420 | struct fc_port *conflict; |
5d964837 QT |
2421 | unsigned char logout_completed; |
2422 | int generation; | |
2423 | ||
2424 | struct se_session *se_sess; | |
2425 | struct kref sess_kref; | |
2426 | struct qla_tgt *tgt; | |
2427 | unsigned long expires; | |
2428 | struct list_head del_list_entry; | |
2429 | struct work_struct free_work; | |
cd4ed6b4 QT |
2430 | struct work_struct reg_work; |
2431 | uint64_t jiffies_at_registration; | |
8aaac2d7 | 2432 | unsigned long prli_expired; |
5d964837 QT |
2433 | struct qlt_plogi_ack_t *plogi_link[QLT_PLOGI_LINK_MAX]; |
2434 | ||
8ae6d9c7 GM |
2435 | uint16_t tgt_id; |
2436 | uint16_t old_tgt_id; | |
cd4ed6b4 | 2437 | uint16_t sec_since_registration; |
8ae6d9c7 | 2438 | |
09ff701a SR |
2439 | uint8_t fcp_prio; |
2440 | ||
d8b45213 AV |
2441 | uint8_t fabric_port_name[WWN_SIZE]; |
2442 | uint16_t fp_speed; | |
2443 | ||
1da177e4 LT |
2444 | fc_port_type_t port_type; |
2445 | ||
2446 | atomic_t state; | |
2447 | uint32_t flags; | |
2448 | ||
1da177e4 | 2449 | int login_retry; |
1da177e4 | 2450 | |
d97994dc | 2451 | struct fc_rport *rport, *drport; |
ad3e0eda | 2452 | u32 supported_classes; |
df7baa50 | 2453 | |
e8c72ba5 | 2454 | uint8_t fc4_type; |
84ed362a | 2455 | uint8_t fc4_features; |
b3b02e6e | 2456 | uint8_t scan_state; |
8ae6d9c7 GM |
2457 | |
2458 | unsigned long last_queue_full; | |
2459 | unsigned long last_ramp_up; | |
2460 | ||
2461 | uint16_t port_id; | |
e05fe292 | 2462 | |
a5d42f4c DG |
2463 | struct nvme_fc_remote_port *nvme_remote_port; |
2464 | ||
e05fe292 | 2465 | unsigned long retry_delay_timestamp; |
a6ca8878 | 2466 | struct qla_tgt_sess *tgt_session; |
726b8548 QT |
2467 | struct ct_sns_desc ct_desc; |
2468 | enum discovery_state disc_state; | |
27258a57 | 2469 | atomic_t shadow_disc_state; |
cd4ed6b4 | 2470 | enum discovery_state next_disc_state; |
726b8548 | 2471 | enum login_state fw_login_state; |
8777e431 | 2472 | unsigned long dm_login_expire; |
5b33469a QT |
2473 | unsigned long plogi_nack_done_deadline; |
2474 | ||
726b8548 QT |
2475 | u32 login_gen, last_login_gen; |
2476 | u32 rscn_gen, last_rscn_gen; | |
2477 | u32 chip_reset; | |
2478 | struct list_head gnl_entry; | |
2479 | struct work_struct del_work; | |
2480 | u8 iocb[IOCB_SIZE]; | |
c0c462c8 DG |
2481 | u8 current_login_state; |
2482 | u8 last_login_state; | |
8777e431 QT |
2483 | u16 n2n_link_reset_cnt; |
2484 | u16 n2n_chip_reset; | |
1da177e4 LT |
2485 | } fc_port_t; |
2486 | ||
a10c8803 MW |
2487 | enum { |
2488 | FC4_PRIORITY_NVME = 1, | |
2489 | FC4_PRIORITY_FCP = 2, | |
2490 | }; | |
84ed362a | 2491 | |
726b8548 QT |
2492 | #define QLA_FCPORT_SCAN 1 |
2493 | #define QLA_FCPORT_FOUND 2 | |
2494 | ||
2495 | struct event_arg { | |
726b8548 QT |
2496 | fc_port_t *fcport; |
2497 | srb_t *sp; | |
2498 | port_id_t id; | |
2499 | u16 data[2], rc; | |
2500 | u8 port_name[WWN_SIZE]; | |
2501 | u32 iop[2]; | |
2502 | }; | |
2503 | ||
8ae6d9c7 GM |
2504 | #include "qla_mr.h" |
2505 | ||
1da177e4 LT |
2506 | /* |
2507 | * Fibre channel port/lun states. | |
2508 | */ | |
2509 | #define FCS_UNCONFIGURED 1 | |
2510 | #define FCS_DEVICE_DEAD 2 | |
2511 | #define FCS_DEVICE_LOST 3 | |
2512 | #define FCS_ONLINE 4 | |
1da177e4 | 2513 | |
c4dc7cd3 | 2514 | extern const char *const port_state_str[5]; |
ec426e10 | 2515 | |
27258a57 SS |
2516 | static const char * const port_dstate_str[] = { |
2517 | "DELETED", | |
2518 | "GNN_ID", | |
2519 | "GNL", | |
2520 | "LOGIN_PEND", | |
2521 | "LOGIN_FAILED", | |
2522 | "GPDB", | |
2523 | "UPD_FCPORT", | |
2524 | "LOGIN_COMPLETE", | |
2525 | "ADISC", | |
2526 | "DELETE_PEND" | |
2527 | }; | |
2528 | ||
1da177e4 LT |
2529 | /* |
2530 | * FC port flags. | |
2531 | */ | |
2532 | #define FCF_FABRIC_DEVICE BIT_0 | |
2533 | #define FCF_LOGIN_NEEDED BIT_1 | |
f08b7251 | 2534 | #define FCF_FCP2_DEVICE BIT_2 |
5ff1d584 | 2535 | #define FCF_ASYNC_SENT BIT_3 |
2d70c103 | 2536 | #define FCF_CONF_COMP_SUPPORTED BIT_4 |
6d674927 | 2537 | #define FCF_ASYNC_ACTIVE BIT_5 |
1da177e4 LT |
2538 | |
2539 | /* No loop ID flag. */ | |
2540 | #define FC_NO_LOOP_ID 0x1000 | |
2541 | ||
1da177e4 LT |
2542 | /* |
2543 | * FC-CT interface | |
2544 | * | |
2545 | * NOTE: All structures are big-endian in form. | |
2546 | */ | |
2547 | ||
2548 | #define CT_REJECT_RESPONSE 0x8001 | |
2549 | #define CT_ACCEPT_RESPONSE 0x8002 | |
df57caba HM |
2550 | #define CT_REASON_INVALID_COMMAND_CODE 0x01 |
2551 | #define CT_REASON_CANNOT_PERFORM 0x09 | |
2552 | #define CT_REASON_COMMAND_UNSUPPORTED 0x0b | |
2553 | #define CT_EXPL_ALREADY_REGISTERED 0x10 | |
2554 | #define CT_EXPL_HBA_ATTR_NOT_REGISTERED 0x11 | |
2555 | #define CT_EXPL_MULTIPLE_HBA_ATTR 0x12 | |
2556 | #define CT_EXPL_INVALID_HBA_BLOCK_LENGTH 0x13 | |
2557 | #define CT_EXPL_MISSING_REQ_HBA_ATTR 0x14 | |
2558 | #define CT_EXPL_PORT_NOT_REGISTERED_ 0x15 | |
2559 | #define CT_EXPL_MISSING_HBA_ID_PORT_LIST 0x16 | |
2560 | #define CT_EXPL_HBA_NOT_REGISTERED 0x17 | |
2561 | #define CT_EXPL_PORT_ATTR_NOT_REGISTERED 0x20 | |
2562 | #define CT_EXPL_PORT_NOT_REGISTERED 0x21 | |
2563 | #define CT_EXPL_MULTIPLE_PORT_ATTR 0x22 | |
2564 | #define CT_EXPL_INVALID_PORT_BLOCK_LENGTH 0x23 | |
1da177e4 LT |
2565 | |
2566 | #define NS_N_PORT_TYPE 0x01 | |
2567 | #define NS_NL_PORT_TYPE 0x02 | |
2568 | #define NS_NX_PORT_TYPE 0x7F | |
2569 | ||
2570 | #define GA_NXT_CMD 0x100 | |
2571 | #define GA_NXT_REQ_SIZE (16 + 4) | |
2572 | #define GA_NXT_RSP_SIZE (16 + 620) | |
2573 | ||
a4239945 QT |
2574 | #define GPN_FT_CMD 0x172 |
2575 | #define GPN_FT_REQ_SIZE (16 + 4) | |
2576 | #define GNN_FT_CMD 0x173 | |
2577 | #define GNN_FT_REQ_SIZE (16 + 4) | |
2578 | ||
1da177e4 LT |
2579 | #define GID_PT_CMD 0x1A1 |
2580 | #define GID_PT_REQ_SIZE (16 + 4) | |
1da177e4 LT |
2581 | |
2582 | #define GPN_ID_CMD 0x112 | |
2583 | #define GPN_ID_REQ_SIZE (16 + 4) | |
2584 | #define GPN_ID_RSP_SIZE (16 + 8) | |
2585 | ||
2586 | #define GNN_ID_CMD 0x113 | |
2587 | #define GNN_ID_REQ_SIZE (16 + 4) | |
2588 | #define GNN_ID_RSP_SIZE (16 + 8) | |
2589 | ||
2590 | #define GFT_ID_CMD 0x117 | |
2591 | #define GFT_ID_REQ_SIZE (16 + 4) | |
2592 | #define GFT_ID_RSP_SIZE (16 + 32) | |
2593 | ||
726b8548 QT |
2594 | #define GID_PN_CMD 0x121 |
2595 | #define GID_PN_REQ_SIZE (16 + 8) | |
2596 | #define GID_PN_RSP_SIZE (16 + 4) | |
2597 | ||
1da177e4 LT |
2598 | #define RFT_ID_CMD 0x217 |
2599 | #define RFT_ID_REQ_SIZE (16 + 4 + 32) | |
2600 | #define RFT_ID_RSP_SIZE 16 | |
2601 | ||
2602 | #define RFF_ID_CMD 0x21F | |
2603 | #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1) | |
2604 | #define RFF_ID_RSP_SIZE 16 | |
2605 | ||
2606 | #define RNN_ID_CMD 0x213 | |
2607 | #define RNN_ID_REQ_SIZE (16 + 4 + 8) | |
2608 | #define RNN_ID_RSP_SIZE 16 | |
2609 | ||
2610 | #define RSNN_NN_CMD 0x239 | |
2611 | #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255) | |
2612 | #define RSNN_NN_RSP_SIZE 16 | |
2613 | ||
d8b45213 AV |
2614 | #define GFPN_ID_CMD 0x11C |
2615 | #define GFPN_ID_REQ_SIZE (16 + 4) | |
2616 | #define GFPN_ID_RSP_SIZE (16 + 8) | |
2617 | ||
2618 | #define GPSC_CMD 0x127 | |
2619 | #define GPSC_REQ_SIZE (16 + 8) | |
2620 | #define GPSC_RSP_SIZE (16 + 2 + 2) | |
2621 | ||
e8c72ba5 CD |
2622 | #define GFF_ID_CMD 0x011F |
2623 | #define GFF_ID_REQ_SIZE (16 + 4) | |
2624 | #define GFF_ID_RSP_SIZE (16 + 128) | |
d8b45213 | 2625 | |
cca5335c AV |
2626 | /* |
2627 | * HBA attribute types. | |
2628 | */ | |
2629 | #define FDMI_HBA_ATTR_COUNT 9 | |
df57caba HM |
2630 | #define FDMIV2_HBA_ATTR_COUNT 17 |
2631 | #define FDMI_HBA_NODE_NAME 0x1 | |
2632 | #define FDMI_HBA_MANUFACTURER 0x2 | |
2633 | #define FDMI_HBA_SERIAL_NUMBER 0x3 | |
2634 | #define FDMI_HBA_MODEL 0x4 | |
2635 | #define FDMI_HBA_MODEL_DESCRIPTION 0x5 | |
2636 | #define FDMI_HBA_HARDWARE_VERSION 0x6 | |
2637 | #define FDMI_HBA_DRIVER_VERSION 0x7 | |
2638 | #define FDMI_HBA_OPTION_ROM_VERSION 0x8 | |
2639 | #define FDMI_HBA_FIRMWARE_VERSION 0x9 | |
cca5335c AV |
2640 | #define FDMI_HBA_OS_NAME_AND_VERSION 0xa |
2641 | #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb | |
df57caba HM |
2642 | #define FDMI_HBA_NODE_SYMBOLIC_NAME 0xc |
2643 | #define FDMI_HBA_VENDOR_ID 0xd | |
2644 | #define FDMI_HBA_NUM_PORTS 0xe | |
2645 | #define FDMI_HBA_FABRIC_NAME 0xf | |
2646 | #define FDMI_HBA_BOOT_BIOS_NAME 0x10 | |
2647 | #define FDMI_HBA_TYPE_VENDOR_IDENTIFIER 0xe0 | |
cca5335c AV |
2648 | |
2649 | struct ct_fdmi_hba_attr { | |
2650 | uint16_t type; | |
2651 | uint16_t len; | |
2652 | union { | |
2653 | uint8_t node_name[WWN_SIZE]; | |
df57caba HM |
2654 | uint8_t manufacturer[64]; |
2655 | uint8_t serial_num[32]; | |
dd83cb2c | 2656 | uint8_t model[16+1]; |
cca5335c | 2657 | uint8_t model_desc[80]; |
df57caba | 2658 | uint8_t hw_version[32]; |
cca5335c AV |
2659 | uint8_t driver_version[32]; |
2660 | uint8_t orom_version[16]; | |
df57caba | 2661 | uint8_t fw_version[32]; |
cca5335c | 2662 | uint8_t os_version[128]; |
df57caba | 2663 | uint32_t max_ct_len; |
cca5335c AV |
2664 | } a; |
2665 | }; | |
2666 | ||
2667 | struct ct_fdmi_hba_attributes { | |
2668 | uint32_t count; | |
2669 | struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT]; | |
2670 | }; | |
2671 | ||
df57caba HM |
2672 | struct ct_fdmiv2_hba_attr { |
2673 | uint16_t type; | |
2674 | uint16_t len; | |
2675 | union { | |
2676 | uint8_t node_name[WWN_SIZE]; | |
dd83cb2c | 2677 | uint8_t manufacturer[64]; |
df57caba | 2678 | uint8_t serial_num[32]; |
dd83cb2c | 2679 | uint8_t model[16+1]; |
df57caba HM |
2680 | uint8_t model_desc[80]; |
2681 | uint8_t hw_version[16]; | |
2682 | uint8_t driver_version[32]; | |
2683 | uint8_t orom_version[16]; | |
2684 | uint8_t fw_version[32]; | |
2685 | uint8_t os_version[128]; | |
2686 | uint32_t max_ct_len; | |
2687 | uint8_t sym_name[256]; | |
2688 | uint32_t vendor_id; | |
2689 | uint32_t num_ports; | |
2690 | uint8_t fabric_name[WWN_SIZE]; | |
2691 | uint8_t bios_name[32]; | |
577419f7 | 2692 | uint8_t vendor_identifier[8]; |
df57caba HM |
2693 | } a; |
2694 | }; | |
2695 | ||
2696 | struct ct_fdmiv2_hba_attributes { | |
2697 | uint32_t count; | |
2698 | struct ct_fdmiv2_hba_attr entry[FDMIV2_HBA_ATTR_COUNT]; | |
2699 | }; | |
2700 | ||
cca5335c AV |
2701 | /* |
2702 | * Port attribute types. | |
2703 | */ | |
8a85e171 | 2704 | #define FDMI_PORT_ATTR_COUNT 6 |
df57caba HM |
2705 | #define FDMIV2_PORT_ATTR_COUNT 16 |
2706 | #define FDMI_PORT_FC4_TYPES 0x1 | |
2707 | #define FDMI_PORT_SUPPORT_SPEED 0x2 | |
2708 | #define FDMI_PORT_CURRENT_SPEED 0x3 | |
2709 | #define FDMI_PORT_MAX_FRAME_SIZE 0x4 | |
2710 | #define FDMI_PORT_OS_DEVICE_NAME 0x5 | |
2711 | #define FDMI_PORT_HOST_NAME 0x6 | |
2712 | #define FDMI_PORT_NODE_NAME 0x7 | |
2713 | #define FDMI_PORT_NAME 0x8 | |
2714 | #define FDMI_PORT_SYM_NAME 0x9 | |
2715 | #define FDMI_PORT_TYPE 0xa | |
2716 | #define FDMI_PORT_SUPP_COS 0xb | |
2717 | #define FDMI_PORT_FABRIC_NAME 0xc | |
2718 | #define FDMI_PORT_FC4_TYPE 0xd | |
2719 | #define FDMI_PORT_STATE 0x101 | |
2720 | #define FDMI_PORT_COUNT 0x102 | |
2721 | #define FDMI_PORT_ID 0x103 | |
cca5335c | 2722 | |
5881569b AV |
2723 | #define FDMI_PORT_SPEED_1GB 0x1 |
2724 | #define FDMI_PORT_SPEED_2GB 0x2 | |
2725 | #define FDMI_PORT_SPEED_10GB 0x4 | |
2726 | #define FDMI_PORT_SPEED_4GB 0x8 | |
2727 | #define FDMI_PORT_SPEED_8GB 0x10 | |
2728 | #define FDMI_PORT_SPEED_16GB 0x20 | |
f73cb695 | 2729 | #define FDMI_PORT_SPEED_32GB 0x40 |
ecc89f25 | 2730 | #define FDMI_PORT_SPEED_64GB 0x80 |
5881569b AV |
2731 | #define FDMI_PORT_SPEED_UNKNOWN 0x8000 |
2732 | ||
df57caba HM |
2733 | #define FC_CLASS_2 0x04 |
2734 | #define FC_CLASS_3 0x08 | |
2735 | #define FC_CLASS_2_3 0x0C | |
2736 | ||
2737 | struct ct_fdmiv2_port_attr { | |
cca5335c AV |
2738 | uint16_t type; |
2739 | uint16_t len; | |
2740 | union { | |
2741 | uint8_t fc4_types[32]; | |
2742 | uint32_t sup_speed; | |
2743 | uint32_t cur_speed; | |
2744 | uint32_t max_frame_size; | |
2745 | uint8_t os_dev_name[32]; | |
dd83cb2c | 2746 | uint8_t host_name[256]; |
df57caba HM |
2747 | uint8_t node_name[WWN_SIZE]; |
2748 | uint8_t port_name[WWN_SIZE]; | |
2749 | uint8_t port_sym_name[128]; | |
2750 | uint32_t port_type; | |
2751 | uint32_t port_supported_cos; | |
2752 | uint8_t fabric_name[WWN_SIZE]; | |
2753 | uint8_t port_fc4_type[32]; | |
2754 | uint32_t port_state; | |
2755 | uint32_t num_ports; | |
2756 | uint32_t port_id; | |
cca5335c AV |
2757 | } a; |
2758 | }; | |
2759 | ||
2760 | /* | |
2761 | * Port Attribute Block. | |
2762 | */ | |
df57caba HM |
2763 | struct ct_fdmiv2_port_attributes { |
2764 | uint32_t count; | |
2765 | struct ct_fdmiv2_port_attr entry[FDMIV2_PORT_ATTR_COUNT]; | |
2766 | }; | |
2767 | ||
2768 | struct ct_fdmi_port_attr { | |
2769 | uint16_t type; | |
2770 | uint16_t len; | |
2771 | union { | |
2772 | uint8_t fc4_types[32]; | |
2773 | uint32_t sup_speed; | |
2774 | uint32_t cur_speed; | |
2775 | uint32_t max_frame_size; | |
2776 | uint8_t os_dev_name[32]; | |
dd83cb2c | 2777 | uint8_t host_name[256]; |
df57caba HM |
2778 | } a; |
2779 | }; | |
2780 | ||
cca5335c AV |
2781 | struct ct_fdmi_port_attributes { |
2782 | uint32_t count; | |
2783 | struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT]; | |
2784 | }; | |
2785 | ||
2786 | /* FDMI definitions. */ | |
2787 | #define GRHL_CMD 0x100 | |
2788 | #define GHAT_CMD 0x101 | |
2789 | #define GRPL_CMD 0x102 | |
2790 | #define GPAT_CMD 0x110 | |
2791 | ||
2792 | #define RHBA_CMD 0x200 | |
2793 | #define RHBA_RSP_SIZE 16 | |
2794 | ||
2795 | #define RHAT_CMD 0x201 | |
2796 | #define RPRT_CMD 0x210 | |
2797 | ||
2798 | #define RPA_CMD 0x211 | |
2799 | #define RPA_RSP_SIZE 16 | |
2800 | ||
2801 | #define DHBA_CMD 0x300 | |
2802 | #define DHBA_REQ_SIZE (16 + 8) | |
2803 | #define DHBA_RSP_SIZE 16 | |
2804 | ||
2805 | #define DHAT_CMD 0x301 | |
2806 | #define DPRT_CMD 0x310 | |
2807 | #define DPA_CMD 0x311 | |
2808 | ||
1da177e4 LT |
2809 | /* CT command header -- request/response common fields */ |
2810 | struct ct_cmd_hdr { | |
2811 | uint8_t revision; | |
2812 | uint8_t in_id[3]; | |
2813 | uint8_t gs_type; | |
2814 | uint8_t gs_subtype; | |
2815 | uint8_t options; | |
2816 | uint8_t reserved; | |
2817 | }; | |
2818 | ||
2819 | /* CT command request */ | |
2820 | struct ct_sns_req { | |
2821 | struct ct_cmd_hdr header; | |
2822 | uint16_t command; | |
2823 | uint16_t max_rsp_size; | |
2824 | uint8_t fragment_id; | |
2825 | uint8_t reserved[3]; | |
2826 | ||
2827 | union { | |
d8b45213 | 2828 | /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */ |
1da177e4 LT |
2829 | struct { |
2830 | uint8_t reserved; | |
df95f39a | 2831 | be_id_t port_id; |
1da177e4 LT |
2832 | } port_id; |
2833 | ||
a4239945 QT |
2834 | struct { |
2835 | uint8_t reserved; | |
2836 | uint8_t domain; | |
2837 | uint8_t area; | |
2838 | uint8_t port_type; | |
2839 | } gpn_ft; | |
2840 | ||
1da177e4 LT |
2841 | struct { |
2842 | uint8_t port_type; | |
2843 | uint8_t domain; | |
2844 | uint8_t area; | |
2845 | uint8_t reserved; | |
2846 | } gid_pt; | |
2847 | ||
2848 | struct { | |
2849 | uint8_t reserved; | |
df95f39a | 2850 | be_id_t port_id; |
1da177e4 LT |
2851 | uint8_t fc4_types[32]; |
2852 | } rft_id; | |
2853 | ||
2854 | struct { | |
2855 | uint8_t reserved; | |
df95f39a | 2856 | be_id_t port_id; |
1da177e4 LT |
2857 | uint16_t reserved2; |
2858 | uint8_t fc4_feature; | |
2859 | uint8_t fc4_type; | |
2860 | } rff_id; | |
2861 | ||
2862 | struct { | |
2863 | uint8_t reserved; | |
df95f39a | 2864 | be_id_t port_id; |
1da177e4 LT |
2865 | uint8_t node_name[8]; |
2866 | } rnn_id; | |
2867 | ||
2868 | struct { | |
2869 | uint8_t node_name[8]; | |
2870 | uint8_t name_len; | |
2871 | uint8_t sym_node_name[255]; | |
2872 | } rsnn_nn; | |
cca5335c AV |
2873 | |
2874 | struct { | |
577419f7 | 2875 | uint8_t hba_identifier[8]; |
cca5335c AV |
2876 | } ghat; |
2877 | ||
2878 | struct { | |
2879 | uint8_t hba_identifier[8]; | |
2880 | uint32_t entry_count; | |
2881 | uint8_t port_name[8]; | |
2882 | struct ct_fdmi_hba_attributes attrs; | |
2883 | } rhba; | |
2884 | ||
df57caba HM |
2885 | struct { |
2886 | uint8_t hba_identifier[8]; | |
2887 | uint32_t entry_count; | |
2888 | uint8_t port_name[8]; | |
2889 | struct ct_fdmiv2_hba_attributes attrs; | |
2890 | } rhba2; | |
2891 | ||
cca5335c AV |
2892 | struct { |
2893 | uint8_t hba_identifier[8]; | |
2894 | struct ct_fdmi_hba_attributes attrs; | |
2895 | } rhat; | |
2896 | ||
2897 | struct { | |
2898 | uint8_t port_name[8]; | |
2899 | struct ct_fdmi_port_attributes attrs; | |
2900 | } rpa; | |
2901 | ||
df57caba HM |
2902 | struct { |
2903 | uint8_t port_name[8]; | |
2904 | struct ct_fdmiv2_port_attributes attrs; | |
2905 | } rpa2; | |
2906 | ||
cca5335c AV |
2907 | struct { |
2908 | uint8_t port_name[8]; | |
2909 | } dhba; | |
2910 | ||
2911 | struct { | |
2912 | uint8_t port_name[8]; | |
2913 | } dhat; | |
2914 | ||
2915 | struct { | |
2916 | uint8_t port_name[8]; | |
2917 | } dprt; | |
2918 | ||
2919 | struct { | |
2920 | uint8_t port_name[8]; | |
2921 | } dpa; | |
d8b45213 AV |
2922 | |
2923 | struct { | |
2924 | uint8_t port_name[8]; | |
2925 | } gpsc; | |
e8c72ba5 CD |
2926 | |
2927 | struct { | |
2928 | uint8_t reserved; | |
a5d42f4c | 2929 | uint8_t port_id[3]; |
e8c72ba5 | 2930 | } gff_id; |
726b8548 QT |
2931 | |
2932 | struct { | |
2933 | uint8_t port_name[8]; | |
2934 | } gid_pn; | |
1da177e4 LT |
2935 | } req; |
2936 | }; | |
2937 | ||
2938 | /* CT command response header */ | |
2939 | struct ct_rsp_hdr { | |
2940 | struct ct_cmd_hdr header; | |
2941 | uint16_t response; | |
2942 | uint16_t residual; | |
2943 | uint8_t fragment_id; | |
2944 | uint8_t reason_code; | |
2945 | uint8_t explanation_code; | |
2946 | uint8_t vendor_unique; | |
2947 | }; | |
2948 | ||
2949 | struct ct_sns_gid_pt_data { | |
2950 | uint8_t control_byte; | |
df95f39a | 2951 | be_id_t port_id; |
1da177e4 LT |
2952 | }; |
2953 | ||
a4239945 QT |
2954 | /* It's the same for both GPN_FT and GNN_FT */ |
2955 | struct ct_sns_gpnft_rsp { | |
2956 | struct { | |
2957 | struct ct_cmd_hdr header; | |
2958 | uint16_t response; | |
2959 | uint16_t residual; | |
2960 | uint8_t fragment_id; | |
2961 | uint8_t reason_code; | |
2962 | uint8_t explanation_code; | |
2963 | uint8_t vendor_unique; | |
2964 | }; | |
2965 | /* Assume the largest number of targets for the union */ | |
2966 | struct ct_sns_gpn_ft_data { | |
2967 | u8 control_byte; | |
2968 | u8 port_id[3]; | |
2969 | u32 reserved; | |
2970 | u8 port_name[8]; | |
2971 | } entries[1]; | |
2972 | }; | |
2973 | ||
2974 | /* CT command response */ | |
1da177e4 LT |
2975 | struct ct_sns_rsp { |
2976 | struct ct_rsp_hdr header; | |
2977 | ||
2978 | union { | |
2979 | struct { | |
2980 | uint8_t port_type; | |
df95f39a | 2981 | be_id_t port_id; |
1da177e4 LT |
2982 | uint8_t port_name[8]; |
2983 | uint8_t sym_port_name_len; | |
2984 | uint8_t sym_port_name[255]; | |
2985 | uint8_t node_name[8]; | |
2986 | uint8_t sym_node_name_len; | |
2987 | uint8_t sym_node_name[255]; | |
2988 | uint8_t init_proc_assoc[8]; | |
2989 | uint8_t node_ip_addr[16]; | |
2990 | uint8_t class_of_service[4]; | |
2991 | uint8_t fc4_types[32]; | |
2992 | uint8_t ip_address[16]; | |
2993 | uint8_t fabric_port_name[8]; | |
2994 | uint8_t reserved; | |
2995 | uint8_t hard_address[3]; | |
2996 | } ga_nxt; | |
2997 | ||
2998 | struct { | |
642ef983 CD |
2999 | /* Assume the largest number of targets for the union */ |
3000 | struct ct_sns_gid_pt_data | |
3001 | entries[MAX_FIBRE_DEVICES_MAX]; | |
1da177e4 LT |
3002 | } gid_pt; |
3003 | ||
3004 | struct { | |
3005 | uint8_t port_name[8]; | |
3006 | } gpn_id; | |
3007 | ||
3008 | struct { | |
3009 | uint8_t node_name[8]; | |
3010 | } gnn_id; | |
3011 | ||
3012 | struct { | |
3013 | uint8_t fc4_types[32]; | |
3014 | } gft_id; | |
cca5335c AV |
3015 | |
3016 | struct { | |
3017 | uint32_t entry_count; | |
3018 | uint8_t port_name[8]; | |
3019 | struct ct_fdmi_hba_attributes attrs; | |
3020 | } ghat; | |
d8b45213 AV |
3021 | |
3022 | struct { | |
3023 | uint8_t port_name[8]; | |
3024 | } gfpn_id; | |
3025 | ||
3026 | struct { | |
3027 | uint16_t speeds; | |
3028 | uint16_t speed; | |
3029 | } gpsc; | |
e8c72ba5 CD |
3030 | |
3031 | #define GFF_FCP_SCSI_OFFSET 7 | |
d3bae931 | 3032 | #define GFF_NVME_OFFSET 23 /* type = 28h */ |
e8c72ba5 CD |
3033 | struct { |
3034 | uint8_t fc4_features[128]; | |
3035 | } gff_id; | |
726b8548 QT |
3036 | struct { |
3037 | uint8_t reserved; | |
3038 | uint8_t port_id[3]; | |
3039 | } gid_pn; | |
1da177e4 LT |
3040 | } rsp; |
3041 | }; | |
3042 | ||
3043 | struct ct_sns_pkt { | |
3044 | union { | |
3045 | struct ct_sns_req req; | |
3046 | struct ct_sns_rsp rsp; | |
3047 | } p; | |
3048 | }; | |
3049 | ||
a4239945 QT |
3050 | struct ct_sns_gpnft_pkt { |
3051 | union { | |
3052 | struct ct_sns_req req; | |
3053 | struct ct_sns_gpnft_rsp rsp; | |
3054 | } p; | |
3055 | }; | |
3056 | ||
f352eeb7 QT |
3057 | enum scan_flags_t { |
3058 | SF_SCANNING = BIT_0, | |
3059 | SF_QUEUED = BIT_1, | |
3060 | }; | |
3061 | ||
33b28357 QT |
3062 | enum fc4type_t { |
3063 | FS_FC4TYPE_FCP = BIT_0, | |
3064 | FS_FC4TYPE_NVME = BIT_1, | |
7f2a398d | 3065 | FS_FCP_IS_N2N = BIT_7, |
33b28357 QT |
3066 | }; |
3067 | ||
a4239945 QT |
3068 | struct fab_scan_rp { |
3069 | port_id_t id; | |
33b28357 | 3070 | enum fc4type_t fc4type; |
a4239945 QT |
3071 | u8 port_name[8]; |
3072 | u8 node_name[8]; | |
3073 | }; | |
3074 | ||
3075 | struct fab_scan { | |
3076 | struct fab_scan_rp *l; | |
3077 | u32 size; | |
6944dccb QT |
3078 | u16 scan_retry; |
3079 | #define MAX_SCAN_RETRIES 5 | |
f352eeb7 QT |
3080 | enum scan_flags_t scan_flags; |
3081 | struct delayed_work scan_work; | |
a4239945 QT |
3082 | }; |
3083 | ||
1da177e4 | 3084 | /* |
25985edc | 3085 | * SNS command structures -- for 2200 compatibility. |
1da177e4 LT |
3086 | */ |
3087 | #define RFT_ID_SNS_SCMD_LEN 22 | |
3088 | #define RFT_ID_SNS_CMD_SIZE 60 | |
3089 | #define RFT_ID_SNS_DATA_SIZE 16 | |
3090 | ||
3091 | #define RNN_ID_SNS_SCMD_LEN 10 | |
3092 | #define RNN_ID_SNS_CMD_SIZE 36 | |
3093 | #define RNN_ID_SNS_DATA_SIZE 16 | |
3094 | ||
3095 | #define GA_NXT_SNS_SCMD_LEN 6 | |
3096 | #define GA_NXT_SNS_CMD_SIZE 28 | |
3097 | #define GA_NXT_SNS_DATA_SIZE (620 + 16) | |
3098 | ||
3099 | #define GID_PT_SNS_SCMD_LEN 6 | |
3100 | #define GID_PT_SNS_CMD_SIZE 28 | |
642ef983 CD |
3101 | /* |
3102 | * Assume MAX_FIBRE_DEVICES_2100 as these defines are only used with older | |
3103 | * adapters. | |
3104 | */ | |
3105 | #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16) | |
1da177e4 LT |
3106 | |
3107 | #define GPN_ID_SNS_SCMD_LEN 6 | |
3108 | #define GPN_ID_SNS_CMD_SIZE 28 | |
3109 | #define GPN_ID_SNS_DATA_SIZE (8 + 16) | |
3110 | ||
3111 | #define GNN_ID_SNS_SCMD_LEN 6 | |
3112 | #define GNN_ID_SNS_CMD_SIZE 28 | |
3113 | #define GNN_ID_SNS_DATA_SIZE (8 + 16) | |
3114 | ||
3115 | struct sns_cmd_pkt { | |
3116 | union { | |
3117 | struct { | |
3118 | uint16_t buffer_length; | |
3119 | uint16_t reserved_1; | |
d4556a49 | 3120 | __le64 buffer_address __packed; |
1da177e4 LT |
3121 | uint16_t subcommand_length; |
3122 | uint16_t reserved_2; | |
3123 | uint16_t subcommand; | |
3124 | uint16_t size; | |
3125 | uint32_t reserved_3; | |
3126 | uint8_t param[36]; | |
3127 | } cmd; | |
3128 | ||
3129 | uint8_t rft_data[RFT_ID_SNS_DATA_SIZE]; | |
3130 | uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE]; | |
3131 | uint8_t gan_data[GA_NXT_SNS_DATA_SIZE]; | |
3132 | uint8_t gid_data[GID_PT_SNS_DATA_SIZE]; | |
3133 | uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE]; | |
3134 | uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE]; | |
3135 | } p; | |
3136 | }; | |
3137 | ||
5433383e AV |
3138 | struct fw_blob { |
3139 | char *name; | |
3140 | uint32_t segs[4]; | |
3141 | const struct firmware *fw; | |
3142 | }; | |
3143 | ||
1da177e4 LT |
3144 | /* Return data from MBC_GET_ID_LIST call. */ |
3145 | struct gid_list_info { | |
3146 | uint8_t al_pa; | |
3147 | uint8_t area; | |
fa2a1ce5 | 3148 | uint8_t domain; |
1da177e4 LT |
3149 | uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */ |
3150 | uint16_t loop_id; /* ISP23XX -- 6 bytes. */ | |
3d71644c | 3151 | uint16_t reserved_1; /* ISP24XX -- 8 bytes. */ |
1da177e4 | 3152 | }; |
1da177e4 | 3153 | |
2c3dfe3f SJ |
3154 | /* NPIV */ |
3155 | typedef struct vport_info { | |
3156 | uint8_t port_name[WWN_SIZE]; | |
3157 | uint8_t node_name[WWN_SIZE]; | |
3158 | int vp_id; | |
3159 | uint16_t loop_id; | |
3160 | unsigned long host_no; | |
3161 | uint8_t port_id[3]; | |
3162 | int loop_state; | |
3163 | } vport_info_t; | |
3164 | ||
3165 | typedef struct vport_params { | |
3166 | uint8_t port_name[WWN_SIZE]; | |
3167 | uint8_t node_name[WWN_SIZE]; | |
3168 | uint32_t options; | |
3169 | #define VP_OPTS_RETRY_ENABLE BIT_0 | |
3170 | #define VP_OPTS_VP_DISABLE BIT_1 | |
3171 | } vport_params_t; | |
3172 | ||
3173 | /* NPIV - return codes of VP create and modify */ | |
3174 | #define VP_RET_CODE_OK 0 | |
3175 | #define VP_RET_CODE_FATAL 1 | |
3176 | #define VP_RET_CODE_WRONG_ID 2 | |
3177 | #define VP_RET_CODE_WWPN 3 | |
3178 | #define VP_RET_CODE_RESOURCES 4 | |
3179 | #define VP_RET_CODE_NO_MEM 5 | |
3180 | #define VP_RET_CODE_NOT_FOUND 6 | |
3181 | ||
7b867cf7 | 3182 | struct qla_hw_data; |
2afa19a9 | 3183 | struct rsp_que; |
abbd8870 AV |
3184 | /* |
3185 | * ISP operations | |
3186 | */ | |
3187 | struct isp_operations { | |
3188 | ||
3189 | int (*pci_config) (struct scsi_qla_host *); | |
3f006ac3 | 3190 | int (*reset_chip)(struct scsi_qla_host *); |
abbd8870 AV |
3191 | int (*chip_diag) (struct scsi_qla_host *); |
3192 | void (*config_rings) (struct scsi_qla_host *); | |
3f006ac3 | 3193 | int (*reset_adapter)(struct scsi_qla_host *); |
abbd8870 AV |
3194 | int (*nvram_config) (struct scsi_qla_host *); |
3195 | void (*update_fw_options) (struct scsi_qla_host *); | |
3196 | int (*load_risc) (struct scsi_qla_host *, uint32_t *); | |
3197 | ||
dc6d6d34 | 3198 | char * (*pci_info_str)(struct scsi_qla_host *, char *, size_t); |
df57caba | 3199 | char * (*fw_version_str)(struct scsi_qla_host *, char *, size_t); |
abbd8870 | 3200 | |
7d12e780 | 3201 | irq_handler_t intr_handler; |
7b867cf7 AC |
3202 | void (*enable_intrs) (struct qla_hw_data *); |
3203 | void (*disable_intrs) (struct qla_hw_data *); | |
abbd8870 | 3204 | |
2afa19a9 | 3205 | int (*abort_command) (srb_t *); |
9cb78c16 HR |
3206 | int (*target_reset) (struct fc_port *, uint64_t, int); |
3207 | int (*lun_reset) (struct fc_port *, uint64_t, int); | |
abbd8870 AV |
3208 | int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t, |
3209 | uint8_t, uint8_t, uint16_t *, uint8_t); | |
1c7c6357 AV |
3210 | int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t, |
3211 | uint8_t, uint8_t); | |
abbd8870 AV |
3212 | |
3213 | uint16_t (*calc_req_entries) (uint16_t); | |
3214 | void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t); | |
726b8548 QT |
3215 | void *(*prep_ms_iocb) (struct scsi_qla_host *, struct ct_arg *); |
3216 | void *(*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t, | |
cca5335c | 3217 | uint32_t); |
abbd8870 | 3218 | |
3695310e | 3219 | uint8_t *(*read_nvram)(struct scsi_qla_host *, void *, |
abbd8870 | 3220 | uint32_t, uint32_t); |
3695310e | 3221 | int (*write_nvram)(struct scsi_qla_host *, void *, uint32_t, |
abbd8870 AV |
3222 | uint32_t); |
3223 | ||
3224 | void (*fw_dump) (struct scsi_qla_host *, int); | |
f6df144c AV |
3225 | |
3226 | int (*beacon_on) (struct scsi_qla_host *); | |
3227 | int (*beacon_off) (struct scsi_qla_host *); | |
3228 | void (*beacon_blink) (struct scsi_qla_host *); | |
854165f4 | 3229 | |
3695310e | 3230 | void *(*read_optrom)(struct scsi_qla_host *, void *, |
854165f4 | 3231 | uint32_t, uint32_t); |
3695310e | 3232 | int (*write_optrom)(struct scsi_qla_host *, void *, uint32_t, |
854165f4 | 3233 | uint32_t); |
30c47662 AV |
3234 | |
3235 | int (*get_flash_version) (struct scsi_qla_host *, void *); | |
7b867cf7 | 3236 | int (*start_scsi) (srb_t *); |
d7459527 | 3237 | int (*start_scsi_mq) (srb_t *); |
a9083016 | 3238 | int (*abort_isp) (struct scsi_qla_host *); |
845bbb09 | 3239 | int (*iospace_config)(struct qla_hw_data *); |
8ae6d9c7 | 3240 | int (*initialize_adapter)(struct scsi_qla_host *); |
abbd8870 AV |
3241 | }; |
3242 | ||
a8488abe AV |
3243 | /* MSI-X Support *************************************************************/ |
3244 | ||
3245 | #define QLA_MSIX_CHIP_REV_24XX 3 | |
3246 | #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7) | |
3247 | #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1) | |
3248 | ||
17e5fc58 | 3249 | #define QLA_BASE_VECTORS 2 /* default + RSP */ |
d7459527 | 3250 | #define QLA_MSIX_RSP_Q 0x01 |
093df737 QT |
3251 | #define QLA_ATIO_VECTOR 0x02 |
3252 | #define QLA_MSIX_QPAIR_MULTIQ_RSP_Q 0x03 | |
a8488abe | 3253 | |
a8488abe AV |
3254 | #define QLA_MIDX_DEFAULT 0 |
3255 | #define QLA_MIDX_RSP_Q 1 | |
73208dfd | 3256 | #define QLA_PCI_MSIX_CONTROL 0xa2 |
6246b8a1 | 3257 | #define QLA_83XX_PCI_MSIX_CONTROL 0x92 |
a8488abe AV |
3258 | |
3259 | struct scsi_qla_host; | |
3260 | ||
cdb898c5 QT |
3261 | |
3262 | #define QLA83XX_RSPQ_MSIX_ENTRY_NUMBER 1 /* refer to qla83xx_msix_entries */ | |
3263 | ||
a8488abe AV |
3264 | struct qla_msix_entry { |
3265 | int have_irq; | |
d7459527 | 3266 | int in_use; |
73208dfd AC |
3267 | uint32_t vector; |
3268 | uint16_t entry; | |
d7459527 | 3269 | char name[30]; |
4fa18345 | 3270 | void *handle; |
cdb898c5 | 3271 | int cpuid; |
a8488abe AV |
3272 | }; |
3273 | ||
2c3dfe3f SJ |
3274 | #define WATCH_INTERVAL 1 /* number of seconds */ |
3275 | ||
0971de7f AV |
3276 | /* Work events. */ |
3277 | enum qla_work_type { | |
3278 | QLA_EVT_AEN, | |
8a659571 | 3279 | QLA_EVT_IDC_ACK, |
ac280b67 | 3280 | QLA_EVT_ASYNC_LOGIN, |
ac280b67 | 3281 | QLA_EVT_ASYNC_LOGOUT, |
5ff1d584 | 3282 | QLA_EVT_ASYNC_ADISC, |
3420d36c | 3283 | QLA_EVT_UEVENT, |
8ae6d9c7 | 3284 | QLA_EVT_AENFX, |
726b8548 | 3285 | QLA_EVT_GPNID, |
e374f9f5 | 3286 | QLA_EVT_UNMAP, |
726b8548 QT |
3287 | QLA_EVT_NEW_SESS, |
3288 | QLA_EVT_GPDB, | |
a5d42f4c | 3289 | QLA_EVT_PRLI, |
726b8548 | 3290 | QLA_EVT_GPSC, |
726b8548 QT |
3291 | QLA_EVT_GNL, |
3292 | QLA_EVT_NACK, | |
9b3e0f4d | 3293 | QLA_EVT_RELOGIN, |
11aea16a QT |
3294 | QLA_EVT_ASYNC_PRLO, |
3295 | QLA_EVT_ASYNC_PRLO_DONE, | |
a4239945 QT |
3296 | QLA_EVT_GPNFT, |
3297 | QLA_EVT_GPNFT_DONE, | |
3298 | QLA_EVT_GNNFT_DONE, | |
3299 | QLA_EVT_GNNID, | |
3300 | QLA_EVT_GFPNID, | |
e374f9f5 | 3301 | QLA_EVT_SP_RETRY, |
cc28e0ac | 3302 | QLA_EVT_IIDMA, |
8777e431 | 3303 | QLA_EVT_ELS_PLOGI, |
0971de7f AV |
3304 | }; |
3305 | ||
3306 | ||
3307 | struct qla_work_evt { | |
3308 | struct list_head list; | |
3309 | enum qla_work_type type; | |
3310 | u32 flags; | |
3311 | #define QLA_EVT_FLAG_FREE 0x1 | |
3312 | ||
3313 | union { | |
3314 | struct { | |
3315 | enum fc_host_event_code code; | |
3316 | u32 data; | |
3317 | } aen; | |
8a659571 AV |
3318 | struct { |
3319 | #define QLA_IDC_ACK_REGS 7 | |
3320 | uint16_t mb[QLA_IDC_ACK_REGS]; | |
3321 | } idc_ack; | |
ac280b67 AV |
3322 | struct { |
3323 | struct fc_port *fcport; | |
3324 | #define QLA_LOGIO_LOGIN_RETRIED BIT_0 | |
3325 | u16 data[2]; | |
3326 | } logio; | |
3420d36c AV |
3327 | struct { |
3328 | u32 code; | |
3329 | #define QLA_UEVENT_CODE_FW_DUMP 0 | |
3330 | } uevent; | |
8ae6d9c7 GM |
3331 | struct { |
3332 | uint32_t evtcode; | |
3333 | uint32_t mbx[8]; | |
3334 | uint32_t count; | |
3335 | } aenfx; | |
3336 | struct { | |
3337 | srb_t *sp; | |
3338 | } iosb; | |
726b8548 QT |
3339 | struct { |
3340 | port_id_t id; | |
3341 | } gpnid; | |
3342 | struct { | |
3343 | port_id_t id; | |
3344 | u8 port_name[8]; | |
a4239945 | 3345 | u8 node_name[8]; |
726b8548 | 3346 | void *pla; |
a4239945 | 3347 | u8 fc4_type; |
726b8548 QT |
3348 | } new_sess; |
3349 | struct { /*Get PDB, Get Speed, update fcport, gnl, gidpn */ | |
3350 | fc_port_t *fcport; | |
3351 | u8 opt; | |
3352 | } fcport; | |
3353 | struct { | |
3354 | fc_port_t *fcport; | |
3355 | u8 iocb[IOCB_SIZE]; | |
3356 | int type; | |
3357 | } nack; | |
a4239945 QT |
3358 | struct { |
3359 | u8 fc4_type; | |
33b28357 | 3360 | srb_t *sp; |
a4239945 | 3361 | } gpnft; |
8ae6d9c7 | 3362 | } u; |
0971de7f AV |
3363 | }; |
3364 | ||
4d4df193 HK |
3365 | struct qla_chip_state_84xx { |
3366 | struct list_head list; | |
3367 | struct kref kref; | |
3368 | ||
3369 | void *bus; | |
3370 | spinlock_t access_lock; | |
3371 | struct mutex fw_update_mutex; | |
3372 | uint32_t fw_update; | |
3373 | uint32_t op_fw_version; | |
3374 | uint32_t op_fw_size; | |
3375 | uint32_t op_fw_seq_size; | |
3376 | uint32_t diag_fw_version; | |
3377 | uint32_t gold_fw_version; | |
3378 | }; | |
3379 | ||
54b9993c AG |
3380 | struct qla_dif_statistics { |
3381 | uint64_t dif_input_bytes; | |
3382 | uint64_t dif_output_bytes; | |
3383 | uint64_t dif_input_requests; | |
3384 | uint64_t dif_output_requests; | |
3385 | uint32_t dif_guard_err; | |
3386 | uint32_t dif_ref_tag_err; | |
3387 | uint32_t dif_app_tag_err; | |
3388 | }; | |
3389 | ||
e5f5f6f7 HZ |
3390 | struct qla_statistics { |
3391 | uint32_t total_isp_aborts; | |
49fd462a HZ |
3392 | uint64_t input_bytes; |
3393 | uint64_t output_bytes; | |
fabbb8df JC |
3394 | uint64_t input_requests; |
3395 | uint64_t output_requests; | |
3396 | uint32_t control_requests; | |
3397 | ||
3398 | uint64_t jiffies_at_last_reset; | |
33e79977 QT |
3399 | uint32_t stat_max_pend_cmds; |
3400 | uint32_t stat_max_qfull_cmds_alloc; | |
3401 | uint32_t stat_max_qfull_cmds_dropped; | |
54b9993c AG |
3402 | |
3403 | struct qla_dif_statistics qla_dif_stats; | |
e5f5f6f7 HZ |
3404 | }; |
3405 | ||
a9b6f722 SK |
3406 | struct bidi_statistics { |
3407 | unsigned long long io_count; | |
3408 | unsigned long long transfer_bytes; | |
3409 | }; | |
3410 | ||
be25152c QT |
3411 | struct qla_tc_param { |
3412 | struct scsi_qla_host *vha; | |
3413 | uint32_t blk_sz; | |
3414 | uint32_t bufflen; | |
3415 | struct scatterlist *sg; | |
3416 | struct scatterlist *prot_sg; | |
3417 | struct crc_context *ctx; | |
3418 | uint8_t *ctx_dsd_alloced; | |
3419 | }; | |
3420 | ||
73208dfd AC |
3421 | /* Multi queue support */ |
3422 | #define MBC_INITIALIZE_MULTIQ 0x1f | |
3423 | #define QLA_QUE_PAGE 0X1000 | |
3424 | #define QLA_MQ_SIZE 32 | |
73208dfd AC |
3425 | #define QLA_MAX_QUEUES 256 |
3426 | #define ISP_QUE_REG(ha, id) \ | |
ecc89f25 JC |
3427 | ((ha->mqenable || IS_QLA83XX(ha) || \ |
3428 | IS_QLA27XX(ha) || IS_QLA28XX(ha)) ? \ | |
da9b1d5c AV |
3429 | ((void __iomem *)ha->mqiobase + (QLA_QUE_PAGE * id)) :\ |
3430 | ((void __iomem *)ha->iobase)) | |
73208dfd AC |
3431 | #define QLA_REQ_QUE_ID(tag) \ |
3432 | ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0) | |
3433 | #define QLA_DEFAULT_QUE_QOS 5 | |
3434 | #define QLA_PRECONFIG_VPORTS 32 | |
3435 | #define QLA_MAX_VPORTS_QLA24XX 128 | |
3436 | #define QLA_MAX_VPORTS_QLA25XX 256 | |
82de802a | 3437 | |
60a9eadb QT |
3438 | struct qla_tgt_counters { |
3439 | uint64_t qla_core_sbt_cmd; | |
3440 | uint64_t core_qla_que_buf; | |
3441 | uint64_t qla_core_ret_ctio; | |
3442 | uint64_t core_qla_snd_status; | |
3443 | uint64_t qla_core_ret_sta_ctio; | |
3444 | uint64_t core_qla_free_cmd; | |
3445 | uint64_t num_q_full_sent; | |
3446 | uint64_t num_alloc_iocb_failed; | |
3447 | uint64_t num_term_xchg_sent; | |
3448 | }; | |
3449 | ||
82de802a QT |
3450 | struct qla_qpair; |
3451 | ||
7b867cf7 AC |
3452 | /* Response queue data structure */ |
3453 | struct rsp_que { | |
3454 | dma_addr_t dma; | |
3455 | response_t *ring; | |
3456 | response_t *ring_ptr; | |
08029990 AV |
3457 | uint32_t __iomem *rsp_q_in; /* FWI2-capable only. */ |
3458 | uint32_t __iomem *rsp_q_out; | |
7b867cf7 AC |
3459 | uint16_t ring_index; |
3460 | uint16_t out_ptr; | |
7c6300e3 | 3461 | uint16_t *in_ptr; /* queue shadow in index */ |
7b867cf7 AC |
3462 | uint16_t length; |
3463 | uint16_t options; | |
7b867cf7 | 3464 | uint16_t rid; |
73208dfd AC |
3465 | uint16_t id; |
3466 | uint16_t vp_idx; | |
7b867cf7 | 3467 | struct qla_hw_data *hw; |
73208dfd AC |
3468 | struct qla_msix_entry *msix; |
3469 | struct req_que *req; | |
2afa19a9 | 3470 | srb_t *status_srb; /* status continuation entry */ |
82de802a | 3471 | struct qla_qpair *qpair; |
8ae6d9c7 GM |
3472 | |
3473 | dma_addr_t dma_fx00; | |
3474 | response_t *ring_fx00; | |
3475 | uint16_t length_fx00; | |
3476 | uint8_t rsp_pkt[REQUEST_ENTRY_SIZE]; | |
7b867cf7 | 3477 | }; |
1da177e4 | 3478 | |
7b867cf7 AC |
3479 | /* Request queue data structure */ |
3480 | struct req_que { | |
3481 | dma_addr_t dma; | |
3482 | request_t *ring; | |
3483 | request_t *ring_ptr; | |
08029990 AV |
3484 | uint32_t __iomem *req_q_in; /* FWI2-capable only. */ |
3485 | uint32_t __iomem *req_q_out; | |
7b867cf7 AC |
3486 | uint16_t ring_index; |
3487 | uint16_t in_ptr; | |
7c6300e3 | 3488 | uint16_t *out_ptr; /* queue shadow out index */ |
7b867cf7 AC |
3489 | uint16_t cnt; |
3490 | uint16_t length; | |
3491 | uint16_t options; | |
3492 | uint16_t rid; | |
73208dfd | 3493 | uint16_t id; |
7b867cf7 AC |
3494 | uint16_t qos; |
3495 | uint16_t vp_idx; | |
73208dfd | 3496 | struct rsp_que *rsp; |
8d93f550 | 3497 | srb_t **outstanding_cmds; |
7b867cf7 | 3498 | uint32_t current_outstanding_cmd; |
8d93f550 | 3499 | uint16_t num_outstanding_cmds; |
7b867cf7 | 3500 | int max_q_depth; |
8ae6d9c7 GM |
3501 | |
3502 | dma_addr_t dma_fx00; | |
3503 | request_t *ring_fx00; | |
3504 | uint16_t length_fx00; | |
3505 | uint8_t req_pkt[REQUEST_ENTRY_SIZE]; | |
7b867cf7 | 3506 | }; |
1da177e4 | 3507 | |
d7459527 MH |
3508 | /*Queue pair data structure */ |
3509 | struct qla_qpair { | |
3510 | spinlock_t qp_lock; | |
3511 | atomic_t ref_count; | |
e326d22a | 3512 | uint32_t lun_cnt; |
82de802a QT |
3513 | /* |
3514 | * For qpair 0, qp_lock_ptr will point at hardware_lock due to | |
3515 | * legacy code. For other Qpair(s), it will point at qp_lock. | |
3516 | */ | |
3517 | spinlock_t *qp_lock_ptr; | |
3518 | struct scsi_qla_host *vha; | |
7c3f8fd1 | 3519 | u32 chip_reset; |
82de802a | 3520 | |
d7459527 MH |
3521 | /* distill these fields down to 'online=0/1' |
3522 | * ha->flags.eeh_busy | |
3523 | * ha->flags.pci_channel_io_perm_failure | |
3524 | * base_vha->loop_state | |
3525 | */ | |
3526 | uint32_t online:1; | |
3527 | /* move vha->flags.difdix_supported here */ | |
3528 | uint32_t difdix_supported:1; | |
3529 | uint32_t delete_in_progress:1; | |
4b60c827 | 3530 | uint32_t fw_started:1; |
7c3f8fd1 QT |
3531 | uint32_t enable_class_2:1; |
3532 | uint32_t enable_explicit_conf:1; | |
af7bb382 | 3533 | uint32_t use_shadow_reg:1; |
d7459527 MH |
3534 | |
3535 | uint16_t id; /* qp number used with FW */ | |
d7459527 | 3536 | uint16_t vp_idx; /* vport ID */ |
d7459527 MH |
3537 | mempool_t *srb_mempool; |
3538 | ||
8abfa9e2 QT |
3539 | struct pci_dev *pdev; |
3540 | void (*reqq_start_iocbs)(struct qla_qpair *); | |
3541 | ||
d7459527 MH |
3542 | /* to do: New driver: move queues to here instead of pointers */ |
3543 | struct req_que *req; | |
3544 | struct rsp_que *rsp; | |
3545 | struct atio_que *atio; | |
3546 | struct qla_msix_entry *msix; /* point to &ha->msix_entries[x] */ | |
3547 | struct qla_hw_data *hw; | |
3548 | struct work_struct q_work; | |
3549 | struct list_head qp_list_elem; /* vha->qp_list */ | |
e326d22a | 3550 | struct list_head hints_list; |
82de802a | 3551 | uint16_t cpuid; |
0691094f QT |
3552 | uint16_t retry_term_cnt; |
3553 | uint32_t retry_term_exchg_addr; | |
3554 | uint64_t retry_term_jiff; | |
60a9eadb | 3555 | struct qla_tgt_counters tgt_counters; |
d7459527 MH |
3556 | }; |
3557 | ||
9a069e19 GM |
3558 | /* Place holder for FW buffer parameters */ |
3559 | struct qlfc_fw { | |
3560 | void *fw_buf; | |
3561 | dma_addr_t fw_dma; | |
3562 | uint32_t len; | |
3563 | }; | |
3564 | ||
0e8cd71c SK |
3565 | struct scsi_qlt_host { |
3566 | void *target_lport_ptr; | |
3567 | struct mutex tgt_mutex; | |
3568 | struct mutex tgt_host_action_mutex; | |
3569 | struct qla_tgt *qla_tgt; | |
3570 | }; | |
3571 | ||
2d70c103 NB |
3572 | struct qlt_hw_data { |
3573 | /* Protected by hw lock */ | |
2d70c103 NB |
3574 | uint32_t node_name_set:1; |
3575 | ||
3576 | dma_addr_t atio_dma; /* Physical address. */ | |
3577 | struct atio *atio_ring; /* Base virtual address */ | |
3578 | struct atio *atio_ring_ptr; /* Current address. */ | |
3579 | uint16_t atio_ring_index; /* Current index. */ | |
3580 | uint16_t atio_q_length; | |
aa230bc5 AE |
3581 | uint32_t __iomem *atio_q_in; |
3582 | uint32_t __iomem *atio_q_out; | |
2d70c103 | 3583 | |
2d70c103 | 3584 | struct qla_tgt_func_tmpl *tgt_ops; |
2d70c103 | 3585 | struct qla_tgt_vp_map *tgt_vp_map; |
2d70c103 NB |
3586 | |
3587 | int saved_set; | |
3588 | uint16_t saved_exchange_count; | |
3589 | uint32_t saved_firmware_options_1; | |
3590 | uint32_t saved_firmware_options_2; | |
3591 | uint32_t saved_firmware_options_3; | |
3592 | uint8_t saved_firmware_options[2]; | |
3593 | uint8_t saved_add_firmware_options[2]; | |
3594 | ||
3595 | uint8_t tgt_node_name[WWN_SIZE]; | |
33e79977 | 3596 | |
36c78452 | 3597 | struct dentry *dfs_tgt_sess; |
c423437e | 3598 | struct dentry *dfs_tgt_port_database; |
09620eeb | 3599 | struct dentry *dfs_naqp; |
c423437e | 3600 | |
33e79977 QT |
3601 | struct list_head q_full_list; |
3602 | uint32_t num_pend_cmds; | |
3603 | uint32_t num_qfull_cmds_alloc; | |
3604 | uint32_t num_qfull_cmds_dropped; | |
3605 | spinlock_t q_full_lock; | |
3606 | uint32_t leak_exchg_thresh_hold; | |
7560151b | 3607 | spinlock_t sess_lock; |
09620eeb QT |
3608 | int num_act_qpairs; |
3609 | #define DEFAULT_NAQP 2 | |
2f424b9b | 3610 | spinlock_t atio_lock ____cacheline_aligned; |
482c9dc7 | 3611 | struct btree_head32 host_map; |
2d70c103 NB |
3612 | }; |
3613 | ||
33e79977 QT |
3614 | #define MAX_QFULL_CMDS_ALLOC 8192 |
3615 | #define Q_FULL_THRESH_HOLD_PERCENT 90 | |
3616 | #define Q_FULL_THRESH_HOLD(ha) \ | |
03e8c680 | 3617 | ((ha->cur_fw_xcb_count/100) * Q_FULL_THRESH_HOLD_PERCENT) |
33e79977 QT |
3618 | |
3619 | #define LEAK_EXCHG_THRESH_HOLD_PERCENT 75 /* 75 percent */ | |
3620 | ||
7b867cf7 AC |
3621 | /* |
3622 | * Qlogic host adapter specific data structure. | |
3623 | */ | |
3624 | struct qla_hw_data { | |
3625 | struct pci_dev *pdev; | |
3626 | /* SRB cache. */ | |
3627 | #define SRB_MIN_REQ 128 | |
3628 | mempool_t *srb_mempool; | |
1da177e4 LT |
3629 | |
3630 | volatile struct { | |
1da177e4 LT |
3631 | uint32_t mbox_int :1; |
3632 | uint32_t mbox_busy :1; | |
1da177e4 LT |
3633 | uint32_t disable_risc_code_load :1; |
3634 | uint32_t enable_64bit_addressing :1; | |
3635 | uint32_t enable_lip_reset :1; | |
1da177e4 | 3636 | uint32_t enable_target_reset :1; |
7b867cf7 | 3637 | uint32_t enable_lip_full_login :1; |
1da177e4 | 3638 | uint32_t enable_led_scheme :1; |
7190575f | 3639 | |
3d71644c AV |
3640 | uint32_t msi_enabled :1; |
3641 | uint32_t msix_enabled :1; | |
d4c760c2 | 3642 | uint32_t disable_serdes :1; |
4346b149 | 3643 | uint32_t gpsc_supported :1; |
2c3dfe3f | 3644 | uint32_t npiv_supported :1; |
85880801 | 3645 | uint32_t pci_channel_io_perm_failure :1; |
df613b96 | 3646 | uint32_t fce_enabled :1; |
1d2874de | 3647 | uint32_t fac_supported :1; |
7190575f | 3648 | |
2533cf67 | 3649 | uint32_t chip_reset_done :1; |
cbc8eb67 | 3650 | uint32_t running_gold_fw :1; |
85880801 | 3651 | uint32_t eeh_busy :1; |
3155754a | 3652 | uint32_t disable_msix_handshake :1; |
09ff701a | 3653 | uint32_t fcp_prio_enabled :1; |
7190575f | 3654 | uint32_t isp82xx_fw_hung:1; |
7d613ac6 | 3655 | uint32_t nic_core_hung:1; |
7190575f GM |
3656 | |
3657 | uint32_t quiesce_owner:1; | |
7d613ac6 SV |
3658 | uint32_t nic_core_reset_hdlr_active:1; |
3659 | uint32_t nic_core_reset_owner:1; | |
b6d0d9d5 | 3660 | uint32_t isp82xx_no_md_cap:1; |
2d70c103 | 3661 | uint32_t host_shutting_down:1; |
bf5b8ad7 | 3662 | uint32_t idc_compl_status:1; |
8ae6d9c7 GM |
3663 | uint32_t mr_reset_hdlr_active:1; |
3664 | uint32_t mr_intr_valid:1; | |
b0d6cabd | 3665 | |
40f3862b | 3666 | uint32_t dport_enabled:1; |
2486c627 | 3667 | uint32_t fawwpn_enabled:1; |
b0d6cabd | 3668 | uint32_t exlogins_enabled:1; |
2f56a7f1 | 3669 | uint32_t exchoffld_enabled:1; |
15f30a57 | 3670 | |
ec7193e2 QT |
3671 | uint32_t lip_ae:1; |
3672 | uint32_t n2n_ae:1; | |
15f30a57 | 3673 | uint32_t fw_started:1; |
ec7193e2 | 3674 | uint32_t fw_init_done:1; |
e4e3a2ce QT |
3675 | |
3676 | uint32_t detected_lr_sfp:1; | |
3677 | uint32_t using_lr_setting:1; | |
9cd883f0 | 3678 | uint32_t rida_fmt2:1; |
b2000805 | 3679 | uint32_t purge_mbox:1; |
8777e431 | 3680 | uint32_t n2n_bigger:1; |
3f006ac3 MH |
3681 | uint32_t secure_adapter:1; |
3682 | uint32_t secure_fw:1; | |
1da177e4 LT |
3683 | } flags; |
3684 | ||
d1e3635a | 3685 | uint16_t max_exchg; |
1f4c7c38 | 3686 | uint16_t long_range_distance; /* 32G & above */ |
e4e3a2ce QT |
3687 | #define LR_DISTANCE_5K 1 |
3688 | #define LR_DISTANCE_10K 0 | |
3689 | ||
fa2a1ce5 | 3690 | /* This spinlock is used to protect "io transactions", you must |
7b867cf7 AC |
3691 | * acquire it before doing any IO to the card, eg with RD_REG*() and |
3692 | * WRT_REG*() for the duration of your entire commandtransaction. | |
3693 | * | |
3694 | * This spinlock is of lower priority than the io request lock. | |
3695 | */ | |
1da177e4 | 3696 | |
7b867cf7 | 3697 | spinlock_t hardware_lock ____cacheline_aligned; |
285d0321 | 3698 | int bars; |
09483916 | 3699 | int mem_only; |
f73cb695 | 3700 | device_reg_t *iobase; /* Base I/O address */ |
3776541d | 3701 | resource_size_t pio_address; |
fa2a1ce5 | 3702 | |
7b867cf7 | 3703 | #define MIN_IOBASE_LEN 0x100 |
8ae6d9c7 GM |
3704 | dma_addr_t bar0_hdl; |
3705 | ||
3706 | void __iomem *cregbase; | |
3707 | dma_addr_t bar2_hdl; | |
3708 | #define BAR0_LEN_FX00 (1024 * 1024) | |
3709 | #define BAR2_LEN_FX00 (128 * 1024) | |
3710 | ||
3711 | uint32_t rqstq_intr_code; | |
3712 | uint32_t mbx_intr_code; | |
3713 | uint32_t req_que_len; | |
3714 | uint32_t rsp_que_len; | |
3715 | uint32_t req_que_off; | |
3716 | uint32_t rsp_que_off; | |
3717 | ||
3718 | /* Multi queue data structs */ | |
f73cb695 CD |
3719 | device_reg_t *mqiobase; |
3720 | device_reg_t *msixbase; | |
73208dfd AC |
3721 | uint16_t msix_count; |
3722 | uint8_t mqenable; | |
3723 | struct req_que **req_q_map; | |
3724 | struct rsp_que **rsp_q_map; | |
d7459527 | 3725 | struct qla_qpair **queue_pair_map; |
73208dfd AC |
3726 | unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; |
3727 | unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; | |
d7459527 MH |
3728 | unsigned long qpair_qid_map[(QLA_MAX_QUEUES / 8) |
3729 | / sizeof(unsigned long)]; | |
2afa19a9 AC |
3730 | uint8_t max_req_queues; |
3731 | uint8_t max_rsp_queues; | |
d7459527 | 3732 | uint8_t max_qpairs; |
b95b9452 | 3733 | uint8_t num_qpairs; |
d7459527 | 3734 | struct qla_qpair *base_qpair; |
73208dfd AC |
3735 | struct qla_npiv_entry *npiv_info; |
3736 | uint16_t nvram_npiv_size; | |
1da177e4 | 3737 | |
7b867cf7 AC |
3738 | uint16_t switch_cap; |
3739 | #define FLOGI_SEQ_DEL BIT_8 | |
3740 | #define FLOGI_MID_SUPPORT BIT_10 | |
3741 | #define FLOGI_VSAN_SUPPORT BIT_12 | |
3742 | #define FLOGI_SP_SUPPORT BIT_13 | |
e5b68a61 AC |
3743 | |
3744 | uint8_t port_no; /* Physical port of adapter */ | |
ead03855 | 3745 | uint8_t exch_starvation; |
e5b68a61 | 3746 | |
7b867cf7 AC |
3747 | /* Timeout timers. */ |
3748 | uint8_t loop_down_abort_time; /* port down timer */ | |
3749 | atomic_t loop_down_timer; /* loop down timer */ | |
3750 | uint8_t link_down_timeout; /* link down timeout */ | |
3751 | uint16_t max_loop_id; | |
642ef983 | 3752 | uint16_t max_fibre_devices; /* Maximum number of targets */ |
1da177e4 | 3753 | |
1da177e4 | 3754 | uint16_t fb_rev; |
7b867cf7 | 3755 | uint16_t min_external_loopid; /* First external loop Id */ |
1da177e4 | 3756 | |
d8b45213 | 3757 | #define PORT_SPEED_UNKNOWN 0xFFFF |
7b867cf7 AC |
3758 | #define PORT_SPEED_1GB 0x00 |
3759 | #define PORT_SPEED_2GB 0x01 | |
4910b524 | 3760 | #define PORT_SPEED_AUTO 0x02 |
7b867cf7 AC |
3761 | #define PORT_SPEED_4GB 0x03 |
3762 | #define PORT_SPEED_8GB 0x04 | |
6246b8a1 | 3763 | #define PORT_SPEED_16GB 0x05 |
f73cb695 | 3764 | #define PORT_SPEED_32GB 0x06 |
ecc89f25 | 3765 | #define PORT_SPEED_64GB 0x07 |
3a03eb79 | 3766 | #define PORT_SPEED_10GB 0x13 |
7b867cf7 | 3767 | uint16_t link_data_rate; /* F/W operating speed */ |
4910b524 | 3768 | uint16_t set_data_rate; /* Set by user */ |
1da177e4 LT |
3769 | |
3770 | uint8_t current_topology; | |
3771 | uint8_t prev_topology; | |
3772 | #define ISP_CFG_NL 1 | |
3773 | #define ISP_CFG_N 2 | |
3774 | #define ISP_CFG_FL 4 | |
3775 | #define ISP_CFG_F 8 | |
3776 | ||
7b867cf7 | 3777 | uint8_t operating_mode; /* F/W operating mode */ |
1da177e4 LT |
3778 | #define LOOP 0 |
3779 | #define P2P 1 | |
3780 | #define LOOP_P2P 2 | |
3781 | #define P2P_LOOP 3 | |
1da177e4 | 3782 | uint8_t interrupts_on; |
7b867cf7 | 3783 | uint32_t isp_abort_cnt; |
7b867cf7 AC |
3784 | #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532 |
3785 | #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432 | |
3a03eb79 | 3786 | #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001 |
6246b8a1 GM |
3787 | #define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031 |
3788 | #define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031 | |
f73cb695 | 3789 | #define PCI_DEVICE_ID_QLOGIC_ISP2071 0x2071 |
2c5bbbb2 | 3790 | #define PCI_DEVICE_ID_QLOGIC_ISP2271 0x2271 |
2b48992f | 3791 | #define PCI_DEVICE_ID_QLOGIC_ISP2261 0x2261 |
ecc89f25 JC |
3792 | #define PCI_DEVICE_ID_QLOGIC_ISP2061 0x2061 |
3793 | #define PCI_DEVICE_ID_QLOGIC_ISP2081 0x2081 | |
3794 | #define PCI_DEVICE_ID_QLOGIC_ISP2089 0x2089 | |
3795 | #define PCI_DEVICE_ID_QLOGIC_ISP2281 0x2281 | |
3796 | #define PCI_DEVICE_ID_QLOGIC_ISP2289 0x2289 | |
2c5bbbb2 | 3797 | |
9e052e2d | 3798 | uint32_t isp_type; |
7b867cf7 AC |
3799 | #define DT_ISP2100 BIT_0 |
3800 | #define DT_ISP2200 BIT_1 | |
3801 | #define DT_ISP2300 BIT_2 | |
3802 | #define DT_ISP2312 BIT_3 | |
3803 | #define DT_ISP2322 BIT_4 | |
3804 | #define DT_ISP6312 BIT_5 | |
3805 | #define DT_ISP6322 BIT_6 | |
3806 | #define DT_ISP2422 BIT_7 | |
3807 | #define DT_ISP2432 BIT_8 | |
3808 | #define DT_ISP5422 BIT_9 | |
3809 | #define DT_ISP5432 BIT_10 | |
3810 | #define DT_ISP2532 BIT_11 | |
3811 | #define DT_ISP8432 BIT_12 | |
3a03eb79 | 3812 | #define DT_ISP8001 BIT_13 |
a9083016 | 3813 | #define DT_ISP8021 BIT_14 |
6246b8a1 GM |
3814 | #define DT_ISP2031 BIT_15 |
3815 | #define DT_ISP8031 BIT_16 | |
8ae6d9c7 | 3816 | #define DT_ISPFX00 BIT_17 |
7ec0effd | 3817 | #define DT_ISP8044 BIT_18 |
f73cb695 | 3818 | #define DT_ISP2071 BIT_19 |
2c5bbbb2 | 3819 | #define DT_ISP2271 BIT_20 |
2b48992f | 3820 | #define DT_ISP2261 BIT_21 |
ecc89f25 JC |
3821 | #define DT_ISP2061 BIT_22 |
3822 | #define DT_ISP2081 BIT_23 | |
3823 | #define DT_ISP2089 BIT_24 | |
3824 | #define DT_ISP2281 BIT_25 | |
3825 | #define DT_ISP2289 BIT_26 | |
3826 | #define DT_ISP_LAST (DT_ISP2289 << 1) | |
7b867cf7 | 3827 | |
9e052e2d | 3828 | uint32_t device_type; |
e02587d7 | 3829 | #define DT_T10_PI BIT_25 |
7b867cf7 AC |
3830 | #define DT_IIDMA BIT_26 |
3831 | #define DT_FWI2 BIT_27 | |
3832 | #define DT_ZIO_SUPPORTED BIT_28 | |
3833 | #define DT_OEM_001 BIT_29 | |
3834 | #define DT_ISP2200A BIT_30 | |
3835 | #define DT_EXTENDED_IDS BIT_31 | |
9e052e2d JC |
3836 | |
3837 | #define DT_MASK(ha) ((ha)->isp_type & (DT_ISP_LAST - 1)) | |
7b867cf7 AC |
3838 | #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100) |
3839 | #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200) | |
3840 | #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300) | |
3841 | #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312) | |
3842 | #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322) | |
3843 | #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312) | |
3844 | #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322) | |
3845 | #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422) | |
3846 | #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432) | |
3847 | #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422) | |
3848 | #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432) | |
3849 | #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532) | |
3850 | #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432) | |
3a03eb79 | 3851 | #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001) |
6246b8a1 | 3852 | #define IS_QLA81XX(ha) (IS_QLA8001(ha)) |
a9083016 | 3853 | #define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021) |
7ec0effd | 3854 | #define IS_QLA8044(ha) (DT_MASK(ha) & DT_ISP8044) |
6246b8a1 GM |
3855 | #define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031) |
3856 | #define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031) | |
8ae6d9c7 | 3857 | #define IS_QLAFX00(ha) (DT_MASK(ha) & DT_ISPFX00) |
f73cb695 | 3858 | #define IS_QLA2071(ha) (DT_MASK(ha) & DT_ISP2071) |
2c5bbbb2 | 3859 | #define IS_QLA2271(ha) (DT_MASK(ha) & DT_ISP2271) |
2b48992f | 3860 | #define IS_QLA2261(ha) (DT_MASK(ha) & DT_ISP2261) |
ecc89f25 JC |
3861 | #define IS_QLA2081(ha) (DT_MASK(ha) & DT_ISP2081) |
3862 | #define IS_QLA2281(ha) (DT_MASK(ha) & DT_ISP2281) | |
7b867cf7 AC |
3863 | |
3864 | #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \ | |
3865 | IS_QLA6312(ha) || IS_QLA6322(ha)) | |
3866 | #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha)) | |
3867 | #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha)) | |
3868 | #define IS_QLA25XX(ha) (IS_QLA2532(ha)) | |
6246b8a1 | 3869 | #define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha)) |
7b867cf7 | 3870 | #define IS_QLA84XX(ha) (IS_QLA8432(ha)) |
2b48992f | 3871 | #define IS_QLA27XX(ha) (IS_QLA2071(ha) || IS_QLA2271(ha) || IS_QLA2261(ha)) |
ecc89f25 | 3872 | #define IS_QLA28XX(ha) (IS_QLA2081(ha) || IS_QLA2281(ha)) |
7b867cf7 AC |
3873 | #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \ |
3874 | IS_QLA84XX(ha)) | |
6246b8a1 | 3875 | #define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \ |
7ec0effd AD |
3876 | IS_QLA8031(ha) || IS_QLA8044(ha)) |
3877 | #define IS_P3P_TYPE(ha) (IS_QLA82XX(ha) || IS_QLA8044(ha)) | |
7b867cf7 | 3878 | #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \ |
a9083016 | 3879 | IS_QLA25XX(ha) || IS_QLA81XX(ha) || \ |
7ec0effd | 3880 | IS_QLA82XX(ha) || IS_QLA83XX(ha) || \ |
ecc89f25 JC |
3881 | IS_QLA8044(ha) || IS_QLA27XX(ha) || \ |
3882 | IS_QLA28XX(ha)) | |
fd564b5d | 3883 | #define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ |
ecc89f25 | 3884 | IS_QLA27XX(ha) || IS_QLA28XX(ha)) |
b77ed25c | 3885 | #define IS_NOPOLLING_TYPE(ha) (IS_QLA81XX(ha) && (ha)->flags.msix_enabled) |
f73cb695 | 3886 | #define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ |
ecc89f25 | 3887 | IS_QLA27XX(ha) || IS_QLA28XX(ha)) |
f73cb695 | 3888 | #define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ |
ecc89f25 | 3889 | IS_QLA27XX(ha) || IS_QLA28XX(ha)) |
ac280b67 | 3890 | #define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha)) |
7b867cf7 | 3891 | |
e02587d7 | 3892 | #define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI) |
7b867cf7 AC |
3893 | #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA) |
3894 | #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2) | |
3895 | #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED) | |
3896 | #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001) | |
3897 | #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS) | |
6246b8a1 | 3898 | #define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED) |
f73cb695 | 3899 | #define IS_MQUE_CAPABLE(ha) ((ha)->mqenable || IS_QLA83XX(ha) || \ |
ecc89f25 JC |
3900 | IS_QLA27XX(ha) || IS_QLA28XX(ha)) |
3901 | #define IS_BIDI_CAPABLE(ha) \ | |
3902 | (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) | |
81178772 SK |
3903 | /* Bit 21 of fw_attributes decides the MCTP capabilities */ |
3904 | #define IS_MCTP_CAPABLE(ha) (IS_QLA2031(ha) && \ | |
3905 | ((ha)->fw_attributes_ext[0] & BIT_0)) | |
b20f02e1 HM |
3906 | #define IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) |
3907 | #define IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) | |
9e522cd8 | 3908 | #define IS_PI_DIFB_DIX0_CAPABLE(ha) (0) |
ecc89f25 JC |
3909 | #define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ |
3910 | IS_QLA28XX(ha)) | |
9e522cd8 AE |
3911 | #define IS_PI_SPLIT_DET_CAPABLE(ha) (IS_PI_SPLIT_DET_CAPABLE_HBA(ha) && \ |
3912 | (((ha)->fw_attributes_h << 16 | (ha)->fw_attributes) & BIT_22)) | |
ecc89f25 JC |
3913 | #define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ |
3914 | IS_QLA28XX(ha)) | |
33c36c0a | 3915 | #define IS_TGT_MODE_CAPABLE(ha) (ha->tgt.atio_q_length) |
ecc89f25 JC |
3916 | #define IS_SHADOW_REG_CAPABLE(ha) (IS_QLA27XX(ha) || IS_QLA28XX(ha)) |
3917 | #define IS_DPORT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ | |
3918 | IS_QLA28XX(ha)) | |
3919 | #define IS_FAWWN_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ | |
3920 | IS_QLA28XX(ha)) | |
99e1b683 | 3921 | #define IS_EXCHG_OFFLD_CAPABLE(ha) \ |
ecc89f25 | 3922 | (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) |
99e1b683 | 3923 | #define IS_EXLOGIN_OFFLD_CAPABLE(ha) \ |
ecc89f25 JC |
3924 | (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ |
3925 | IS_QLA27XX(ha) || IS_QLA28XX(ha)) | |
a4239945 | 3926 | #define USE_ASYNC_SCAN(ha) (IS_QLA25XX(ha) || IS_QLA81XX(ha) ||\ |
ecc89f25 | 3927 | IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) |
1da177e4 LT |
3928 | |
3929 | /* HBA serial number */ | |
3930 | uint8_t serial0; | |
3931 | uint8_t serial1; | |
3932 | uint8_t serial2; | |
3933 | ||
3934 | /* NVRAM configuration data */ | |
7b867cf7 | 3935 | #define MAX_NVRAM_SIZE 4096 |
c1c7178c | 3936 | #define VPD_OFFSET (MAX_NVRAM_SIZE / 2) |
3d71644c | 3937 | uint16_t nvram_size; |
1da177e4 | 3938 | uint16_t nvram_base; |
281afe19 | 3939 | void *nvram; |
6f641790 AV |
3940 | uint16_t vpd_size; |
3941 | uint16_t vpd_base; | |
281afe19 | 3942 | void *vpd; |
1da177e4 LT |
3943 | |
3944 | uint16_t loop_reset_delay; | |
1da177e4 LT |
3945 | uint8_t retry_count; |
3946 | uint8_t login_timeout; | |
3947 | uint16_t r_a_tov; | |
3948 | int port_down_retry_count; | |
1da177e4 | 3949 | uint8_t mbx_count; |
8ae6d9c7 | 3950 | uint8_t aen_mbx_count; |
b2000805 QT |
3951 | atomic_t num_pend_mbx_stage1; |
3952 | atomic_t num_pend_mbx_stage2; | |
3953 | atomic_t num_pend_mbx_stage3; | |
0eaaca4c | 3954 | uint16_t frame_payload_size; |
1da177e4 | 3955 | |
7b867cf7 | 3956 | uint32_t login_retry_count; |
1da177e4 LT |
3957 | /* SNS command interfaces. */ |
3958 | ms_iocb_entry_t *ms_iocb; | |
3959 | dma_addr_t ms_iocb_dma; | |
3960 | struct ct_sns_pkt *ct_sns; | |
3961 | dma_addr_t ct_sns_dma; | |
3962 | /* SNS command interfaces for 2200. */ | |
3963 | struct sns_cmd_pkt *sns_cmd; | |
3964 | dma_addr_t sns_cmd_dma; | |
3965 | ||
e4e3a2ce | 3966 | #define SFP_DEV_SIZE 512 |
7b867cf7 AC |
3967 | #define SFP_BLOCK_SIZE 64 |
3968 | void *sfp_data; | |
3969 | dma_addr_t sfp_data_dma; | |
88729e53 | 3970 | |
a27747a2 | 3971 | struct qla_flt_header *flt; |
3f006ac3 MH |
3972 | dma_addr_t flt_dma; |
3973 | ||
b5d0329f | 3974 | #define XGMAC_DATA_SIZE 4096 |
ce0423f4 AV |
3975 | void *xgmac_data; |
3976 | dma_addr_t xgmac_data_dma; | |
3977 | ||
b5d0329f | 3978 | #define DCBX_TLV_DATA_SIZE 4096 |
11bbc1d8 AV |
3979 | void *dcbx_tlv; |
3980 | dma_addr_t dcbx_tlv_dma; | |
3981 | ||
39a11240 | 3982 | struct task_struct *dpc_thread; |
1da177e4 LT |
3983 | uint8_t dpc_active; /* DPC routine is active */ |
3984 | ||
1da177e4 LT |
3985 | dma_addr_t gid_list_dma; |
3986 | struct gid_list_info *gid_list; | |
abbd8870 | 3987 | int gid_list_info_size; |
1da177e4 | 3988 | |
fa2a1ce5 | 3989 | /* Small DMA pool allocations -- maximum 256 bytes in length. */ |
7b867cf7 | 3990 | #define DMA_POOL_SIZE 256 |
1da177e4 LT |
3991 | struct dma_pool *s_dma_pool; |
3992 | ||
3993 | dma_addr_t init_cb_dma; | |
3d71644c AV |
3994 | init_cb_t *init_cb; |
3995 | int init_cb_size; | |
b64b0e8f AV |
3996 | dma_addr_t ex_init_cb_dma; |
3997 | struct ex_init_cb_81xx *ex_init_cb; | |
1da177e4 | 3998 | |
5ff1d584 AV |
3999 | void *async_pd; |
4000 | dma_addr_t async_pd_dma; | |
4001 | ||
b0d6cabd HM |
4002 | #define ENABLE_EXTENDED_LOGIN BIT_7 |
4003 | ||
4004 | /* Extended Logins */ | |
4005 | void *exlogin_buf; | |
4006 | dma_addr_t exlogin_buf_dma; | |
4007 | int exlogin_size; | |
4008 | ||
2f56a7f1 HM |
4009 | #define ENABLE_EXCHANGE_OFFLD BIT_2 |
4010 | ||
4011 | /* Exchange Offload */ | |
4012 | void *exchoffld_buf; | |
4013 | dma_addr_t exchoffld_buf_dma; | |
4014 | int exchoffld_size; | |
4015 | int exchoffld_count; | |
4016 | ||
8777e431 QT |
4017 | /* n2n */ |
4018 | struct els_plogi_payload plogi_els_payld; | |
4019 | ||
a4239945 | 4020 | void *swl; |
7a67735b | 4021 | |
1da177e4 | 4022 | /* These are used by mailbox operations. */ |
8ae6d9c7 GM |
4023 | uint16_t mailbox_out[MAILBOX_REGISTER_COUNT]; |
4024 | uint32_t mailbox_out32[MAILBOX_REGISTER_COUNT]; | |
4025 | uint32_t aenmb[AEN_MAILBOX_REGISTER_COUNT_FX00]; | |
1da177e4 LT |
4026 | |
4027 | mbx_cmd_t *mcp; | |
8ae6d9c7 GM |
4028 | struct mbx_cmd_32 *mcp32; |
4029 | ||
1da177e4 | 4030 | unsigned long mbx_cmd_flags; |
7b867cf7 AC |
4031 | #define MBX_INTERRUPT 1 |
4032 | #define MBX_INTR_WAIT 2 | |
1da177e4 LT |
4033 | #define MBX_UPDATE_FLASH_ACTIVE 3 |
4034 | ||
7b867cf7 | 4035 | struct mutex vport_lock; /* Virtual port synchronization */ |
feafb7b1 | 4036 | spinlock_t vport_slock; /* order is hardware_lock, then vport_slock */ |
d7459527 | 4037 | struct mutex mq_lock; /* multi-queue synchronization */ |
7b867cf7 | 4038 | struct completion mbx_cmd_comp; /* Serialize mbx access */ |
0b05a1f0 | 4039 | struct completion mbx_intr_comp; /* Used for completion notification */ |
23f2ebd1 | 4040 | struct completion dcbx_comp; /* For set port config notification */ |
f356bef1 CD |
4041 | struct completion lb_portup_comp; /* Used to wait for link up during |
4042 | * loopback */ | |
4043 | #define DCBX_COMP_TIMEOUT 20 | |
4044 | #define LB_PORTUP_COMP_TIMEOUT 10 | |
4045 | ||
23f2ebd1 | 4046 | int notify_dcbx_comp; |
f356bef1 | 4047 | int notify_lb_portup_comp; |
a9b6f722 | 4048 | struct mutex selflogin_lock; |
1da177e4 | 4049 | |
1da177e4 | 4050 | /* Basic firmware related information. */ |
1da177e4 LT |
4051 | uint16_t fw_major_version; |
4052 | uint16_t fw_minor_version; | |
4053 | uint16_t fw_subminor_version; | |
4054 | uint16_t fw_attributes; | |
6246b8a1 | 4055 | uint16_t fw_attributes_h; |
03aaa89f | 4056 | #define FW_ATTR_H_NVME_FBURST BIT_1 |
171e4909 GM |
4057 | #define FW_ATTR_H_NVME BIT_10 |
4058 | #define FW_ATTR_H_NVME_UPDATED BIT_14 | |
4059 | ||
6246b8a1 | 4060 | uint16_t fw_attributes_ext[2]; |
1da177e4 LT |
4061 | uint32_t fw_memory_size; |
4062 | uint32_t fw_transfer_size; | |
441d1072 AV |
4063 | uint32_t fw_srisc_address; |
4064 | #define RISC_START_ADDRESS_2100 0x1000 | |
4065 | #define RISC_START_ADDRESS_2300 0x800 | |
4066 | #define RISC_START_ADDRESS_2400 0x100000 | |
03e8c680 QT |
4067 | |
4068 | uint16_t orig_fw_tgt_xcb_count; | |
4069 | uint16_t cur_fw_tgt_xcb_count; | |
4070 | uint16_t orig_fw_xcb_count; | |
4071 | uint16_t cur_fw_xcb_count; | |
4072 | uint16_t orig_fw_iocb_count; | |
4073 | uint16_t cur_fw_iocb_count; | |
4074 | uint16_t fw_max_fcf_count; | |
1da177e4 | 4075 | |
f73cb695 CD |
4076 | uint32_t fw_shared_ram_start; |
4077 | uint32_t fw_shared_ram_end; | |
ad1ef177 JC |
4078 | uint32_t fw_ddr_ram_start; |
4079 | uint32_t fw_ddr_ram_end; | |
f73cb695 | 4080 | |
7b867cf7 | 4081 | uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */ |
1da177e4 | 4082 | uint8_t fw_seriallink_options[4]; |
3d71644c | 4083 | uint16_t fw_seriallink_options24[4]; |
1da177e4 | 4084 | |
2a3192a3 | 4085 | uint8_t serdes_version[3]; |
55a96158 | 4086 | uint8_t mpi_version[3]; |
3a03eb79 | 4087 | uint32_t mpi_capabilities; |
55a96158 | 4088 | uint8_t phy_version[3]; |
03aa868c | 4089 | uint8_t pep_version[3]; |
3a03eb79 | 4090 | |
f73cb695 | 4091 | /* Firmware dump template */ |
a28d9e4e JC |
4092 | struct fwdt { |
4093 | void *template; | |
4094 | ulong length; | |
4095 | ulong dump_size; | |
4096 | } fwdt[2]; | |
a7a167bf AV |
4097 | struct qla2xxx_fw_dump *fw_dump; |
4098 | uint32_t fw_dump_len; | |
a4226ec3 | 4099 | u32 fw_dump_alloc_len; |
2a3192a3 JC |
4100 | bool fw_dumped; |
4101 | bool fw_dump_mpi; | |
61f098dd HP |
4102 | unsigned long fw_dump_cap_flags; |
4103 | #define RISC_PAUSE_CMPL 0 | |
4104 | #define DMA_SHUTDOWN_CMPL 1 | |
4105 | #define ISP_RESET_CMPL 2 | |
4106 | #define RISC_RDY_AFT_RESET 3 | |
4107 | #define RISC_SRAM_DUMP_CMPL 4 | |
4108 | #define RISC_EXT_MEM_DUMP_CMPL 5 | |
d14e72fb HM |
4109 | #define ISP_MBX_RDY 6 |
4110 | #define ISP_SOFT_RESET_CMPL 7 | |
1da177e4 | 4111 | int fw_dump_reading; |
edaa5c74 | 4112 | int prev_minidump_failed; |
a7a167bf AV |
4113 | dma_addr_t eft_dma; |
4114 | void *eft; | |
81178772 SK |
4115 | /* Current size of mctp dump is 0x086064 bytes */ |
4116 | #define MCTP_DUMP_SIZE 0x086064 | |
4117 | dma_addr_t mctp_dump_dma; | |
4118 | void *mctp_dump; | |
4119 | int mctp_dumped; | |
4120 | int mctp_dump_reading; | |
bb99de67 | 4121 | uint32_t chain_offset; |
df613b96 AV |
4122 | struct dentry *dfs_dir; |
4123 | struct dentry *dfs_fce; | |
ce1025cd | 4124 | struct dentry *dfs_tgt_counters; |
03e8c680 | 4125 | struct dentry *dfs_fw_resource_cnt; |
ce1025cd | 4126 | |
df613b96 AV |
4127 | dma_addr_t fce_dma; |
4128 | void *fce; | |
4129 | uint32_t fce_bufs; | |
4130 | uint16_t fce_mb[8]; | |
4131 | uint64_t fce_wr, fce_rd; | |
4132 | struct mutex fce_mutex; | |
4133 | ||
3d71644c | 4134 | uint32_t pci_attr; |
a8488abe | 4135 | uint16_t chip_revision; |
1da177e4 LT |
4136 | |
4137 | uint16_t product_id[4]; | |
4138 | ||
4139 | uint8_t model_number[16+1]; | |
1ee27146 | 4140 | char model_desc[80]; |
cca5335c | 4141 | uint8_t adapter_id[16+1]; |
1da177e4 | 4142 | |
854165f4 AV |
4143 | /* Option ROM information. */ |
4144 | char *optrom_buffer; | |
4145 | uint32_t optrom_size; | |
4146 | int optrom_state; | |
4147 | #define QLA_SWAITING 0 | |
4148 | #define QLA_SREADING 1 | |
4149 | #define QLA_SWRITING 2 | |
b7cc176c JC |
4150 | uint32_t optrom_region_start; |
4151 | uint32_t optrom_region_size; | |
7a8ab9c8 | 4152 | struct mutex optrom_mutex; |
854165f4 | 4153 | |
7b867cf7 | 4154 | /* PCI expansion ROM image information. */ |
30c47662 AV |
4155 | #define ROM_CODE_TYPE_BIOS 0 |
4156 | #define ROM_CODE_TYPE_FCODE 1 | |
4157 | #define ROM_CODE_TYPE_EFI 3 | |
7b867cf7 AC |
4158 | uint8_t bios_revision[2]; |
4159 | uint8_t efi_revision[2]; | |
4160 | uint8_t fcode_revision[16]; | |
30c47662 AV |
4161 | uint32_t fw_revision[4]; |
4162 | ||
0f2d962f MI |
4163 | uint32_t gold_fw_version[4]; |
4164 | ||
3a03eb79 AV |
4165 | /* Offsets for flash/nvram access (set to ~0 if not used). */ |
4166 | uint32_t flash_conf_off; | |
4167 | uint32_t flash_data_off; | |
4168 | uint32_t nvram_conf_off; | |
4169 | uint32_t nvram_data_off; | |
4170 | ||
7d232c74 | 4171 | uint32_t fdt_wrt_disable; |
7ec0effd | 4172 | uint32_t fdt_wrt_enable; |
7d232c74 AV |
4173 | uint32_t fdt_erase_cmd; |
4174 | uint32_t fdt_block_size; | |
4175 | uint32_t fdt_unprotect_sec_cmd; | |
4176 | uint32_t fdt_protect_sec_cmd; | |
7ec0effd | 4177 | uint32_t fdt_wrt_sts_reg_cmd; |
7d232c74 | 4178 | |
5fa8774c JC |
4179 | struct { |
4180 | uint32_t flt_region_flt; | |
4181 | uint32_t flt_region_fdt; | |
4182 | uint32_t flt_region_boot; | |
4183 | uint32_t flt_region_boot_sec; | |
4184 | uint32_t flt_region_fw; | |
4185 | uint32_t flt_region_fw_sec; | |
4186 | uint32_t flt_region_vpd_nvram; | |
4187 | uint32_t flt_region_vpd_nvram_sec; | |
4188 | uint32_t flt_region_vpd; | |
4189 | uint32_t flt_region_vpd_sec; | |
4190 | uint32_t flt_region_nvram; | |
4191 | uint32_t flt_region_nvram_sec; | |
4192 | uint32_t flt_region_npiv_conf; | |
4193 | uint32_t flt_region_gold_fw; | |
4194 | uint32_t flt_region_fcp_prio; | |
4195 | uint32_t flt_region_bootload; | |
4196 | uint32_t flt_region_img_status_pri; | |
4197 | uint32_t flt_region_img_status_sec; | |
4198 | uint32_t flt_region_aux_img_status_pri; | |
4199 | uint32_t flt_region_aux_img_status_sec; | |
4200 | }; | |
4243c115 | 4201 | uint8_t active_image; |
c00d8994 | 4202 | |
1da177e4 | 4203 | /* Needed for BEACON */ |
7b867cf7 AC |
4204 | uint16_t beacon_blink_led; |
4205 | uint8_t beacon_color_state; | |
f6df144c AV |
4206 | #define QLA_LED_GRN_ON 0x01 |
4207 | #define QLA_LED_YLW_ON 0x02 | |
4208 | #define QLA_LED_ABR_ON 0x04 | |
4209 | #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */ | |
4210 | /* ISP2322: red, green, amber. */ | |
7b867cf7 AC |
4211 | uint16_t zio_mode; |
4212 | uint16_t zio_timer; | |
a8488abe | 4213 | |
73208dfd | 4214 | struct qla_msix_entry *msix_entries; |
2c3dfe3f | 4215 | |
7b867cf7 AC |
4216 | struct list_head vp_list; /* list of VP */ |
4217 | unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) / | |
4218 | sizeof(unsigned long)]; | |
4219 | uint16_t num_vhosts; /* number of vports created */ | |
4220 | uint16_t num_vsans; /* number of vsan created */ | |
4221 | uint16_t max_npiv_vports; /* 63 or 125 per topoloty */ | |
4222 | int cur_vport_count; | |
4223 | ||
4224 | struct qla_chip_state_84xx *cs84xx; | |
7b867cf7 | 4225 | struct isp_operations *isp_ops; |
68ca949c | 4226 | struct workqueue_struct *wq; |
9a069e19 | 4227 | struct qlfc_fw fw_buf; |
09ff701a SR |
4228 | |
4229 | /* FCP_CMND priority support */ | |
4230 | struct qla_fcp_prio_cfg *fcp_prio_cfg; | |
a9083016 GM |
4231 | |
4232 | struct dma_pool *dl_dma_pool; | |
4233 | #define DSD_LIST_DMA_POOL_SIZE 512 | |
4234 | ||
4235 | struct dma_pool *fcp_cmnd_dma_pool; | |
4236 | mempool_t *ctx_mempool; | |
4237 | #define FCP_CMND_DMA_POOL_SIZE 512 | |
4238 | ||
8dfa4b5a BVA |
4239 | void __iomem *nx_pcibase; /* Base I/O address */ |
4240 | void __iomem *nxdb_rd_ptr; /* Doorbell read pointer */ | |
4241 | void __iomem *nxdb_wr_ptr; /* Door bell write pointer */ | |
a9083016 GM |
4242 | |
4243 | uint32_t crb_win; | |
4244 | uint32_t curr_window; | |
4245 | uint32_t ddr_mn_window; | |
4246 | unsigned long mn_win_crb; | |
4247 | unsigned long ms_win_crb; | |
4248 | int qdr_sn_window; | |
7d613ac6 SV |
4249 | uint32_t fcoe_dev_init_timeout; |
4250 | uint32_t fcoe_reset_timeout; | |
a9083016 GM |
4251 | rwlock_t hw_lock; |
4252 | uint16_t portnum; /* port number */ | |
4253 | int link_width; | |
4254 | struct fw_blob *hablob; | |
4255 | struct qla82xx_legacy_intr_set nx_legacy_intr; | |
4256 | ||
4257 | uint16_t gbl_dsd_inuse; | |
4258 | uint16_t gbl_dsd_avail; | |
4259 | struct list_head gbl_dsd_list; | |
4260 | #define NUM_DSD_CHAIN 4096 | |
9c2b2975 HZ |
4261 | |
4262 | uint8_t fw_type; | |
4263 | __le32 file_prd_off; /* File firmware product offset */ | |
08de2844 GM |
4264 | |
4265 | uint32_t md_template_size; | |
4266 | void *md_tmplt_hdr; | |
4267 | dma_addr_t md_tmplt_hdr_dma; | |
4268 | void *md_dump; | |
4269 | uint32_t md_dump_size; | |
2d70c103 | 4270 | |
5f16b331 | 4271 | void *loop_id_map; |
7d613ac6 SV |
4272 | |
4273 | /* QLA83XX IDC specific fields */ | |
4274 | uint32_t idc_audit_ts; | |
454073c9 | 4275 | uint32_t idc_extend_tmo; |
7d613ac6 SV |
4276 | |
4277 | /* DPC low-priority workqueue */ | |
4278 | struct workqueue_struct *dpc_lp_wq; | |
4279 | struct work_struct idc_aen; | |
4280 | /* DPC high-priority workqueue */ | |
4281 | struct workqueue_struct *dpc_hp_wq; | |
4282 | struct work_struct nic_core_reset; | |
4283 | struct work_struct idc_state_handler; | |
4284 | struct work_struct nic_core_unrecoverable; | |
f3ddac19 | 4285 | struct work_struct board_disable; |
7d613ac6 | 4286 | |
8ae6d9c7 | 4287 | struct mr_data_fx00 mr; |
b2000805 | 4288 | uint32_t chip_reset; |
8ae6d9c7 | 4289 | |
2d70c103 | 4290 | struct qlt_hw_data tgt; |
a1b23c5a | 4291 | int allow_cna_fw_dump; |
1f4c7c38 | 4292 | uint32_t fw_ability_mask; |
72a92df2 JC |
4293 | uint16_t min_supported_speed; |
4294 | uint16_t max_supported_speed; | |
deeae7a6 | 4295 | |
50b81275 GM |
4296 | /* DMA pool for the DIF bundling buffers */ |
4297 | struct dma_pool *dif_bundl_pool; | |
4298 | #define DIF_BUNDLING_DMA_POOL_SIZE 1024 | |
4299 | struct { | |
4300 | struct { | |
4301 | struct list_head head; | |
4302 | uint count; | |
4303 | } good; | |
4304 | struct { | |
4305 | struct list_head head; | |
4306 | uint count; | |
4307 | } unusable; | |
4308 | } pool; | |
4309 | ||
4310 | unsigned long long dif_bundle_crossed_pages; | |
4311 | unsigned long long dif_bundle_reads; | |
4312 | unsigned long long dif_bundle_writes; | |
4313 | unsigned long long dif_bundle_kallocs; | |
4314 | unsigned long long dif_bundle_dma_allocs; | |
4315 | ||
deeae7a6 DG |
4316 | atomic_t nvme_active_aen_cnt; |
4317 | uint16_t nvme_last_rptd_aen; /* Last recorded aen count */ | |
8b4673ba | 4318 | |
84ed362a MH |
4319 | uint8_t fc4_type_priority; |
4320 | ||
8b4673ba QT |
4321 | atomic_t zio_threshold; |
4322 | uint16_t last_zio_threshold; | |
5fa8774c | 4323 | |
4825034a | 4324 | #define DEFAULT_ZIO_THRESHOLD 5 |
7b867cf7 AC |
4325 | }; |
4326 | ||
5fa8774c JC |
4327 | struct active_regions { |
4328 | uint8_t global; | |
4329 | struct { | |
4330 | uint8_t board_config; | |
4331 | uint8_t vpd_nvram; | |
4332 | uint8_t npiv_config_0_1; | |
4333 | uint8_t npiv_config_2_3; | |
4334 | } aux; | |
4335 | }; | |
4336 | ||
1f4c7c38 JC |
4337 | #define FW_ABILITY_MAX_SPEED_MASK 0xFUL |
4338 | #define FW_ABILITY_MAX_SPEED_16G 0x0 | |
4339 | #define FW_ABILITY_MAX_SPEED_32G 0x1 | |
4340 | #define FW_ABILITY_MAX_SPEED(ha) \ | |
4341 | (ha->fw_ability_mask & FW_ABILITY_MAX_SPEED_MASK) | |
4342 | ||
4910b524 AG |
4343 | #define QLA_GET_DATA_RATE 0 |
4344 | #define QLA_SET_DATA_RATE_NOLR 1 | |
4345 | #define QLA_SET_DATA_RATE_LR 2 /* Set speed and initiate LR */ | |
4346 | ||
7b867cf7 AC |
4347 | /* |
4348 | * Qlogic scsi host structure | |
4349 | */ | |
4350 | typedef struct scsi_qla_host { | |
4351 | struct list_head list; | |
4352 | struct list_head vp_fcports; /* list of fcports */ | |
4353 | struct list_head work_list; | |
f999f4c1 | 4354 | spinlock_t work_lock; |
ec7193e2 | 4355 | struct work_struct iocb_work; |
f999f4c1 | 4356 | |
7b867cf7 AC |
4357 | /* Commonly used flags and state information. */ |
4358 | struct Scsi_Host *host; | |
4359 | unsigned long host_no; | |
4360 | uint8_t host_str[16]; | |
4361 | ||
4362 | volatile struct { | |
4363 | uint32_t init_done :1; | |
4364 | uint32_t online :1; | |
7b867cf7 AC |
4365 | uint32_t reset_active :1; |
4366 | ||
4367 | uint32_t management_server_logged_in :1; | |
4368 | uint32_t process_response_queue :1; | |
bad75002 | 4369 | uint32_t difdix_supported:1; |
feafb7b1 | 4370 | uint32_t delete_progress:1; |
8ae6d9c7 GM |
4371 | |
4372 | uint32_t fw_tgt_reported:1; | |
969a6199 | 4373 | uint32_t bbcr_enable:1; |
d7459527 | 4374 | uint32_t qpairs_available:1; |
d65237c7 SC |
4375 | uint32_t qpairs_req_created:1; |
4376 | uint32_t qpairs_rsp_created:1; | |
a5d42f4c | 4377 | uint32_t nvme_enabled:1; |
03aaa89f | 4378 | uint32_t nvme_first_burst:1; |
7b867cf7 AC |
4379 | } flags; |
4380 | ||
4381 | atomic_t loop_state; | |
4382 | #define LOOP_TIMEOUT 1 | |
4383 | #define LOOP_DOWN 2 | |
4384 | #define LOOP_UP 3 | |
4385 | #define LOOP_UPDATE 4 | |
4386 | #define LOOP_READY 5 | |
4387 | #define LOOP_DEAD 6 | |
4388 | ||
4005a995 | 4389 | unsigned long relogin_jif; |
7b867cf7 AC |
4390 | unsigned long dpc_flags; |
4391 | #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */ | |
4392 | #define RESET_ACTIVE 1 | |
4393 | #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */ | |
4394 | #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */ | |
4395 | #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */ | |
4396 | #define LOOP_RESYNC_ACTIVE 5 | |
4397 | #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */ | |
4398 | #define RSCN_UPDATE 7 /* Perform an RSCN update. */ | |
ddb9b126 SS |
4399 | #define RELOGIN_NEEDED 8 |
4400 | #define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */ | |
4401 | #define ISP_ABORT_RETRY 10 /* ISP aborted. */ | |
4402 | #define BEACON_BLINK_NEEDED 11 | |
4403 | #define REGISTER_FDMI_NEEDED 12 | |
4404 | #define FCPORT_UPDATE_NEEDED 13 | |
4405 | #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */ | |
4406 | #define UNLOADING 15 | |
4407 | #define NPIV_CONFIG_NEEDED 16 | |
a9083016 GM |
4408 | #define ISP_UNRECOVERABLE 17 |
4409 | #define FCOE_CTX_RESET_NEEDED 18 /* Initiate FCoE context reset */ | |
b1d46989 | 4410 | #define MPI_RESET_NEEDED 19 /* Initiate MPI FW reset */ |
579d12b5 | 4411 | #define ISP_QUIESCE_NEEDED 20 /* Driver need some quiescence */ |
48acad09 | 4412 | #define N2N_LINK_RESET 21 |
50280c01 CD |
4413 | #define PORT_UPDATE_NEEDED 22 |
4414 | #define FX00_RESET_RECOVERY 23 | |
4415 | #define FX00_TARGET_SCAN 24 | |
4416 | #define FX00_CRITEMP_RECOVERY 25 | |
e8f5e95d | 4417 | #define FX00_HOST_INFO_RESEND 26 |
d7459527 | 4418 | #define QPAIR_ONLINE_CHECK_NEEDED 27 |
8b4673ba | 4419 | #define SET_NVME_ZIO_THRESHOLD_NEEDED 28 |
e4e3a2ce | 4420 | #define DETECT_SFP_CHANGE 29 |
c0c462c8 | 4421 | #define N2N_LOGIN_NEEDED 30 |
9b3e0f4d | 4422 | #define IOCB_WORK_ACTIVE 31 |
8b4673ba | 4423 | #define SET_ZIO_THRESHOLD_NEEDED 32 |
3f006ac3 | 4424 | #define ISP_ABORT_TO_ROM 33 |
f5187b7d | 4425 | #define VPORT_DELETE 34 |
7b867cf7 | 4426 | |
232792b6 JL |
4427 | unsigned long pci_flags; |
4428 | #define PFLG_DISCONNECTED 0 /* PCI device removed */ | |
beb9e315 | 4429 | #define PFLG_DRIVER_REMOVING 1 /* PCI driver .remove */ |
6b383979 | 4430 | #define PFLG_DRIVER_PROBING 2 /* PCI driver .probe */ |
232792b6 | 4431 | |
7b867cf7 | 4432 | uint32_t device_flags; |
ddb9b126 SS |
4433 | #define SWITCH_FOUND BIT_0 |
4434 | #define DFLG_NO_CABLE BIT_1 | |
a9083016 | 4435 | #define DFLG_DEV_FAILED BIT_5 |
7b867cf7 | 4436 | |
7b867cf7 AC |
4437 | /* ISP configuration data. */ |
4438 | uint16_t loop_id; /* Host adapter loop id */ | |
a9b6f722 SK |
4439 | uint16_t self_login_loop_id; /* host adapter loop id |
4440 | * get it on self login | |
4441 | */ | |
4442 | fc_port_t bidir_fcport; /* fcport used for bidir cmnds | |
4443 | * no need of allocating it for | |
4444 | * each command | |
4445 | */ | |
7b867cf7 AC |
4446 | |
4447 | port_id_t d_id; /* Host adapter port id */ | |
4448 | uint8_t marker_needed; | |
4449 | uint16_t mgmt_svr_loop_id; | |
4450 | ||
4451 | ||
4452 | ||
7b867cf7 AC |
4453 | /* Timeout timers. */ |
4454 | uint8_t loop_down_abort_time; /* port down timer */ | |
4455 | atomic_t loop_down_timer; /* loop down timer */ | |
4456 | uint8_t link_down_timeout; /* link down timeout */ | |
4457 | ||
4458 | uint32_t timer_active; | |
4459 | struct timer_list timer; | |
4460 | ||
4461 | uint8_t node_name[WWN_SIZE]; | |
4462 | uint8_t port_name[WWN_SIZE]; | |
4463 | uint8_t fabric_node_name[WWN_SIZE]; | |
bad7001c | 4464 | |
a5d42f4c | 4465 | struct nvme_fc_local_port *nvme_local_port; |
5621b0dd | 4466 | struct completion nvme_del_done; |
a5d42f4c | 4467 | |
bad7001c AV |
4468 | uint16_t fcoe_vlan_id; |
4469 | uint16_t fcoe_fcf_idx; | |
4470 | uint8_t fcoe_vn_port_mac[6]; | |
4471 | ||
8b2f5ff3 SN |
4472 | /* list of commands waiting on workqueue */ |
4473 | struct list_head qla_cmd_list; | |
4474 | struct list_head qla_sess_op_cmd_list; | |
41dc529a | 4475 | struct list_head unknown_atio_list; |
8b2f5ff3 | 4476 | spinlock_t cmd_list_lock; |
41dc529a | 4477 | struct delayed_work unknown_atio_work; |
8b2f5ff3 | 4478 | |
df673274 AP |
4479 | /* Counter to detect races between ELS and RSCN events */ |
4480 | atomic_t generation_tick; | |
4481 | /* Time when global fcport update has been scheduled */ | |
4482 | int total_fcport_update_gen; | |
71cdc079 AP |
4483 | /* List of pending LOGOs, protected by tgt_mutex */ |
4484 | struct list_head logo_list; | |
b7bd104e AP |
4485 | /* List of pending PLOGI acks, protected by hw lock */ |
4486 | struct list_head plogi_ack_list; | |
df673274 | 4487 | |
d7459527 MH |
4488 | struct list_head qp_list; |
4489 | ||
7ec0effd | 4490 | uint32_t vp_abort_cnt; |
7b867cf7 | 4491 | |
2c3dfe3f | 4492 | struct fc_vport *fc_vport; /* holds fc_vport * for each vport */ |
2c3dfe3f | 4493 | uint16_t vp_idx; /* vport ID */ |
d7459527 | 4494 | struct qla_qpair *qpair; /* base qpair */ |
2c3dfe3f | 4495 | |
2c3dfe3f | 4496 | unsigned long vp_flags; |
2c3dfe3f SJ |
4497 | #define VP_IDX_ACQUIRED 0 /* bit no 0 */ |
4498 | #define VP_CREATE_NEEDED 1 | |
4499 | #define VP_BIND_NEEDED 2 | |
4500 | #define VP_DELETE_NEEDED 3 | |
4501 | #define VP_SCR_NEEDED 4 /* State Change Request registration */ | |
ded6411f | 4502 | #define VP_CONFIG_OK 5 /* Flag to cfg VP, if FW is ready */ |
2c3dfe3f SJ |
4503 | atomic_t vp_state; |
4504 | #define VP_OFFLINE 0 | |
4505 | #define VP_ACTIVE 1 | |
4506 | #define VP_FAILED 2 | |
4507 | // #define VP_DISABLE 3 | |
4508 | uint16_t vp_err_state; | |
4509 | uint16_t vp_prev_err_state; | |
4510 | #define VP_ERR_UNKWN 0 | |
4511 | #define VP_ERR_PORTDWN 1 | |
4512 | #define VP_ERR_FAB_UNSUPPORTED 2 | |
4513 | #define VP_ERR_FAB_NORESOURCES 3 | |
4514 | #define VP_ERR_FAB_LOGOUT 4 | |
4515 | #define VP_ERR_ADAP_NORESOURCES 5 | |
7b867cf7 | 4516 | struct qla_hw_data *hw; |
0e8cd71c | 4517 | struct scsi_qlt_host vha_tgt; |
2afa19a9 | 4518 | struct req_que *req; |
a9083016 GM |
4519 | int fw_heartbeat_counter; |
4520 | int seconds_since_last_heartbeat; | |
2be21fa2 SK |
4521 | struct fc_host_statistics fc_host_stat; |
4522 | struct qla_statistics qla_stats; | |
a9b6f722 | 4523 | struct bidi_statistics bidi_stats; |
feafb7b1 | 4524 | atomic_t vref_count; |
7ec0effd | 4525 | struct qla8044_reset_template reset_tmplt; |
969a6199 | 4526 | uint16_t bbcr; |
0645cb83 QT |
4527 | |
4528 | uint16_t u_ql2xexchoffld; | |
4529 | uint16_t u_ql2xiniexchg; | |
4530 | uint16_t qlini_mode; | |
4531 | uint16_t ql2xexchoffld; | |
4532 | uint16_t ql2xiniexchg; | |
4533 | ||
726b8548 QT |
4534 | struct name_list_extended gnl; |
4535 | /* Count of active session/fcport */ | |
4536 | int fcport_count; | |
4537 | wait_queue_head_t fcport_waitQ; | |
c4a9b538 | 4538 | wait_queue_head_t vref_waitq; |
72a92df2 | 4539 | uint8_t min_supported_speed; |
edd05de1 DG |
4540 | uint8_t n2n_node_name[WWN_SIZE]; |
4541 | uint8_t n2n_port_name[WWN_SIZE]; | |
4542 | uint16_t n2n_id; | |
2d73ac61 | 4543 | struct list_head gpnid_list; |
a4239945 | 4544 | struct fab_scan scan; |
f0783d43 ML |
4545 | |
4546 | unsigned int irq_offset; | |
1da177e4 LT |
4547 | } scsi_qla_host_t; |
4548 | ||
4243c115 SC |
4549 | struct qla27xx_image_status { |
4550 | uint8_t image_status_mask; | |
f8f97b0c | 4551 | uint16_t generation; |
4243c115 | 4552 | uint8_t ver_major; |
5fa8774c JC |
4553 | uint8_t ver_minor; |
4554 | uint8_t bitmap; /* 28xx only */ | |
4555 | uint8_t reserved[2]; | |
4243c115 SC |
4556 | uint32_t checksum; |
4557 | uint32_t signature; | |
4558 | } __packed; | |
4559 | ||
5fa8774c JC |
4560 | /* 28xx aux image status bimap values */ |
4561 | #define QLA28XX_AUX_IMG_BOARD_CONFIG BIT_0 | |
4562 | #define QLA28XX_AUX_IMG_VPD_NVRAM BIT_1 | |
4563 | #define QLA28XX_AUX_IMG_NPIV_CONFIG_0_1 BIT_2 | |
4564 | #define QLA28XX_AUX_IMG_NPIV_CONFIG_2_3 BIT_3 | |
4565 | ||
2d70c103 NB |
4566 | #define SET_VP_IDX 1 |
4567 | #define SET_AL_PA 2 | |
4568 | #define RESET_VP_IDX 3 | |
4569 | #define RESET_AL_PA 4 | |
4570 | struct qla_tgt_vp_map { | |
4571 | uint8_t idx; | |
4572 | scsi_qla_host_t *vha; | |
4573 | }; | |
4574 | ||
d7459527 MH |
4575 | struct qla2_sgx { |
4576 | dma_addr_t dma_addr; /* OUT */ | |
4577 | uint32_t dma_len; /* OUT */ | |
4578 | ||
4579 | uint32_t tot_bytes; /* IN */ | |
4580 | struct scatterlist *cur_sg; /* IN */ | |
4581 | ||
4582 | /* for book keeping, bzero on initial invocation */ | |
4583 | uint32_t bytes_consumed; | |
4584 | uint32_t num_bytes; | |
4585 | uint32_t tot_partial; | |
4586 | ||
4587 | /* for debugging */ | |
4588 | uint32_t num_sg; | |
4589 | srb_t *sp; | |
4590 | }; | |
4591 | ||
4b60c827 QT |
4592 | #define QLA_FW_STARTED(_ha) { \ |
4593 | int i; \ | |
4594 | _ha->flags.fw_started = 1; \ | |
4595 | _ha->base_qpair->fw_started = 1; \ | |
4596 | for (i = 0; i < _ha->max_qpairs; i++) { \ | |
4597 | if (_ha->queue_pair_map[i]) \ | |
4598 | _ha->queue_pair_map[i]->fw_started = 1; \ | |
4599 | } \ | |
4600 | } | |
4601 | ||
4602 | #define QLA_FW_STOPPED(_ha) { \ | |
4603 | int i; \ | |
4604 | _ha->flags.fw_started = 0; \ | |
4605 | _ha->base_qpair->fw_started = 0; \ | |
4606 | for (i = 0; i < _ha->max_qpairs; i++) { \ | |
4607 | if (_ha->queue_pair_map[i]) \ | |
4608 | _ha->queue_pair_map[i]->fw_started = 0; \ | |
4609 | } \ | |
4610 | } | |
4611 | ||
3f006ac3 MH |
4612 | |
4613 | #define SFUB_CHECKSUM_SIZE 4 | |
4614 | ||
4615 | struct secure_flash_update_block { | |
4616 | uint32_t block_info; | |
4617 | uint32_t signature_lo; | |
4618 | uint32_t signature_hi; | |
4619 | uint32_t signature_upper[0x3e]; | |
4620 | }; | |
4621 | ||
4622 | struct secure_flash_update_block_pk { | |
4623 | uint32_t block_info; | |
4624 | uint32_t signature_lo; | |
4625 | uint32_t signature_hi; | |
4626 | uint32_t signature_upper[0x3e]; | |
4627 | uint32_t public_key[0x41]; | |
4628 | }; | |
4629 | ||
1da177e4 LT |
4630 | /* |
4631 | * Macros to help code, maintain, etc. | |
4632 | */ | |
4633 | #define LOOP_TRANSITION(ha) \ | |
4634 | (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \ | |
23443b1d | 4635 | test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \ |
1da177e4 | 4636 | atomic_read(&ha->loop_state) == LOOP_DOWN) |
fa2a1ce5 | 4637 | |
8ae6d9c7 GM |
4638 | #define STATE_TRANSITION(ha) \ |
4639 | (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \ | |
4640 | test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags)) | |
4641 | ||
d7459527 MH |
4642 | #define QLA_VHA_MARK_BUSY(__vha, __bail) do { \ |
4643 | atomic_inc(&__vha->vref_count); \ | |
4644 | mb(); \ | |
4645 | if (__vha->flags.delete_progress) { \ | |
4646 | atomic_dec(&__vha->vref_count); \ | |
c4a9b538 | 4647 | wake_up(&__vha->vref_waitq); \ |
d7459527 MH |
4648 | __bail = 1; \ |
4649 | } else { \ | |
4650 | __bail = 0; \ | |
4651 | } \ | |
feafb7b1 AE |
4652 | } while (0) |
4653 | ||
c4a9b538 | 4654 | #define QLA_VHA_MARK_NOT_BUSY(__vha) do { \ |
d7459527 | 4655 | atomic_dec(&__vha->vref_count); \ |
c4a9b538 JC |
4656 | wake_up(&__vha->vref_waitq); \ |
4657 | } while (0) \ | |
d7459527 MH |
4658 | |
4659 | #define QLA_QPAIR_MARK_BUSY(__qpair, __bail) do { \ | |
4660 | atomic_inc(&__qpair->ref_count); \ | |
4661 | mb(); \ | |
4662 | if (__qpair->delete_in_progress) { \ | |
4663 | atomic_dec(&__qpair->ref_count); \ | |
4664 | __bail = 1; \ | |
4665 | } else { \ | |
4666 | __bail = 0; \ | |
4667 | } \ | |
feafb7b1 AE |
4668 | } while (0) |
4669 | ||
d7459527 MH |
4670 | #define QLA_QPAIR_MARK_NOT_BUSY(__qpair) \ |
4671 | atomic_dec(&__qpair->ref_count); \ | |
4672 | ||
7c3f8fd1 QT |
4673 | |
4674 | #define QLA_ENA_CONF(_ha) {\ | |
4675 | int i;\ | |
4676 | _ha->base_qpair->enable_explicit_conf = 1; \ | |
4677 | for (i = 0; i < _ha->max_qpairs; i++) { \ | |
4678 | if (_ha->queue_pair_map[i]) \ | |
4679 | _ha->queue_pair_map[i]->enable_explicit_conf = 1; \ | |
4680 | } \ | |
4681 | } | |
4682 | ||
4683 | #define QLA_DIS_CONF(_ha) {\ | |
4684 | int i;\ | |
4685 | _ha->base_qpair->enable_explicit_conf = 0; \ | |
4686 | for (i = 0; i < _ha->max_qpairs; i++) { \ | |
4687 | if (_ha->queue_pair_map[i]) \ | |
4688 | _ha->queue_pair_map[i]->enable_explicit_conf = 0; \ | |
4689 | } \ | |
4690 | } | |
4691 | ||
1da177e4 LT |
4692 | /* |
4693 | * qla2x00 local function return status codes | |
4694 | */ | |
4695 | #define MBS_MASK 0x3fff | |
4696 | ||
4697 | #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK) | |
4698 | #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK) | |
4699 | #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK) | |
4700 | #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK) | |
4701 | #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK) | |
4702 | #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK) | |
4703 | #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK) | |
4704 | #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK) | |
4705 | #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK) | |
4706 | #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK) | |
4707 | ||
4708 | #define QLA_FUNCTION_TIMEOUT 0x100 | |
4709 | #define QLA_FUNCTION_PARAMETER_ERROR 0x101 | |
4710 | #define QLA_FUNCTION_FAILED 0x102 | |
4711 | #define QLA_MEMORY_ALLOC_FAILED 0x103 | |
4712 | #define QLA_LOCK_TIMEOUT 0x104 | |
4713 | #define QLA_ABORTED 0x105 | |
4714 | #define QLA_SUSPENDED 0x106 | |
4715 | #define QLA_BUSY 0x107 | |
cca5335c | 4716 | #define QLA_ALREADY_REGISTERED 0x109 |
0c6df590 | 4717 | #define QLA_OS_TIMER_EXPIRED 0x10a |
1da177e4 | 4718 | |
1da177e4 LT |
4719 | #define NVRAM_DELAY() udelay(10) |
4720 | ||
1da177e4 LT |
4721 | /* |
4722 | * Flash support definitions | |
4723 | */ | |
854165f4 AV |
4724 | #define OPTROM_SIZE_2300 0x20000 |
4725 | #define OPTROM_SIZE_2322 0x100000 | |
4726 | #define OPTROM_SIZE_24XX 0x100000 | |
c3a2f0df | 4727 | #define OPTROM_SIZE_25XX 0x200000 |
3a03eb79 | 4728 | #define OPTROM_SIZE_81XX 0x400000 |
a9083016 | 4729 | #define OPTROM_SIZE_82XX 0x800000 |
6246b8a1 | 4730 | #define OPTROM_SIZE_83XX 0x1000000 |
ecc89f25 | 4731 | #define OPTROM_SIZE_28XX 0x2000000 |
a9083016 GM |
4732 | |
4733 | #define OPTROM_BURST_SIZE 0x1000 | |
4734 | #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4) | |
1da177e4 | 4735 | |
bad75002 AE |
4736 | #define QLA_DSDS_PER_IOCB 37 |
4737 | ||
4d78c973 GM |
4738 | #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr) |
4739 | ||
58548cb5 GM |
4740 | #define QLA_SG_ALL 1024 |
4741 | ||
4d78c973 GM |
4742 | enum nexus_wait_type { |
4743 | WAIT_HOST = 0, | |
4744 | WAIT_TARGET, | |
4745 | WAIT_LUN, | |
4746 | }; | |
4747 | ||
e4e3a2ce QT |
4748 | /* Refer to SNIA SFF 8247 */ |
4749 | struct sff_8247_a0 { | |
4750 | u8 txid; /* transceiver id */ | |
4751 | u8 ext_txid; | |
4752 | u8 connector; | |
4753 | /* compliance code */ | |
4754 | u8 eth_infi_cc3; /* ethernet, inifiband */ | |
4755 | u8 sonet_cc4[2]; | |
4756 | u8 eth_cc6; | |
4757 | /* link length */ | |
4758 | #define FC_LL_VL BIT_7 /* very long */ | |
4759 | #define FC_LL_S BIT_6 /* Short */ | |
4760 | #define FC_LL_I BIT_5 /* Intermidiate*/ | |
4761 | #define FC_LL_L BIT_4 /* Long */ | |
4762 | #define FC_LL_M BIT_3 /* Medium */ | |
4763 | #define FC_LL_SA BIT_2 /* ShortWave laser */ | |
4764 | #define FC_LL_LC BIT_1 /* LongWave laser */ | |
4765 | #define FC_LL_EL BIT_0 /* Electrical inter enclosure */ | |
4766 | u8 fc_ll_cc7; | |
4767 | /* FC technology */ | |
4768 | #define FC_TEC_EL BIT_7 /* Electrical inter enclosure */ | |
4769 | #define FC_TEC_SN BIT_6 /* short wave w/o OFC */ | |
4770 | #define FC_TEC_SL BIT_5 /* short wave with OFC */ | |
4771 | #define FC_TEC_LL BIT_4 /* Longwave Laser */ | |
4772 | #define FC_TEC_ACT BIT_3 /* Active cable */ | |
4773 | #define FC_TEC_PAS BIT_2 /* Passive cable */ | |
4774 | u8 fc_tec_cc8; | |
4775 | /* Transmission Media */ | |
4776 | #define FC_MED_TW BIT_7 /* Twin Ax */ | |
4777 | #define FC_MED_TP BIT_6 /* Twited Pair */ | |
4778 | #define FC_MED_MI BIT_5 /* Min Coax */ | |
4779 | #define FC_MED_TV BIT_4 /* Video Coax */ | |
4780 | #define FC_MED_M6 BIT_3 /* Multimode, 62.5um */ | |
4781 | #define FC_MED_M5 BIT_2 /* Multimode, 50um */ | |
4782 | #define FC_MED_SM BIT_0 /* Single Mode */ | |
4783 | u8 fc_med_cc9; | |
4784 | /* speed FC_SP_12: 12*100M = 1200 MB/s */ | |
4785 | #define FC_SP_12 BIT_7 | |
4786 | #define FC_SP_8 BIT_6 | |
4787 | #define FC_SP_16 BIT_5 | |
4788 | #define FC_SP_4 BIT_4 | |
4789 | #define FC_SP_32 BIT_3 | |
4790 | #define FC_SP_2 BIT_2 | |
4791 | #define FC_SP_1 BIT_0 | |
4792 | u8 fc_sp_cc10; | |
4793 | u8 encode; | |
4794 | u8 bitrate; | |
4795 | u8 rate_id; | |
4796 | u8 length_km; /* offset 14/eh */ | |
4797 | u8 length_100m; | |
4798 | u8 length_50um_10m; | |
4799 | u8 length_62um_10m; | |
4800 | u8 length_om4_10m; | |
4801 | u8 length_om3_10m; | |
4802 | #define SFF_VEN_NAME_LEN 16 | |
4803 | u8 vendor_name[SFF_VEN_NAME_LEN]; /* offset 20/14h */ | |
4804 | u8 tx_compat; | |
4805 | u8 vendor_oui[3]; | |
4806 | #define SFF_PART_NAME_LEN 16 | |
4807 | u8 vendor_pn[SFF_PART_NAME_LEN]; /* part number */ | |
4808 | u8 vendor_rev[4]; | |
4809 | u8 wavelength[2]; | |
4810 | u8 resv; | |
4811 | u8 cc_base; | |
4812 | u8 options[2]; /* offset 64 */ | |
4813 | u8 br_max; | |
4814 | u8 br_min; | |
4815 | u8 vendor_sn[16]; | |
4816 | u8 date_code[8]; | |
4817 | u8 diag; | |
4818 | u8 enh_options; | |
4819 | u8 sff_revision; | |
4820 | u8 cc_ext; | |
4821 | u8 vendor_specific[32]; | |
4822 | u8 resv2[128]; | |
4823 | }; | |
4824 | ||
4825 | #define AUTO_DETECT_SFP_SUPPORT(_vha)\ | |
4826 | (ql2xautodetectsfp && !_vha->vp_idx && \ | |
4827 | (IS_QLA25XX(_vha->hw) || IS_QLA81XX(_vha->hw) ||\ | |
ecc89f25 JC |
4828 | IS_QLA83XX(_vha->hw) || IS_QLA27XX(_vha->hw) || \ |
4829 | IS_QLA28XX(_vha->hw))) | |
e4e3a2ce | 4830 | |
3f006ac3 MH |
4831 | #define FLASH_SEMAPHORE_REGISTER_ADDR 0x00101016 |
4832 | ||
09620eeb | 4833 | #define USER_CTRL_IRQ(_ha) (ql2xuctrlirq && QLA_TGT_MODE_ENABLED() && \ |
ecc89f25 | 4834 | (IS_QLA27XX(_ha) || IS_QLA28XX(_ha) || IS_QLA83XX(_ha))) |
09620eeb | 4835 | |
9cd883f0 QT |
4836 | #define SAVE_TOPO(_ha) { \ |
4837 | if (_ha->current_topology) \ | |
4838 | _ha->prev_topology = _ha->current_topology; \ | |
4839 | } | |
4840 | ||
4841 | #define N2N_TOPO(ha) \ | |
4842 | ((ha->prev_topology == ISP_CFG_N && !ha->current_topology) || \ | |
4843 | ha->current_topology == ISP_CFG_N || \ | |
4844 | !ha->current_topology) | |
4845 | ||
84ed362a MH |
4846 | #define NVME_TYPE(fcport) \ |
4847 | (fcport->fc4_type & FS_FC4TYPE_NVME) \ | |
4848 | ||
4849 | #define FCP_TYPE(fcport) \ | |
4850 | (fcport->fc4_type & FS_FC4TYPE_FCP) \ | |
4851 | ||
4852 | #define NVME_ONLY_TARGET(fcport) \ | |
4853 | (NVME_TYPE(fcport) && !FCP_TYPE(fcport)) \ | |
4854 | ||
4855 | #define NVME_FCP_TARGET(fcport) \ | |
4856 | (FCP_TYPE(fcport) && NVME_TYPE(fcport)) \ | |
4857 | ||
4858 | #define NVME_TARGET(ha, fcport) \ | |
4859 | ((NVME_FCP_TARGET(fcport) && \ | |
4860 | (ha->fc4_type_priority == FC4_PRIORITY_NVME)) || \ | |
4861 | NVME_ONLY_TARGET(fcport)) \ | |
4862 | ||
8aaac2d7 QT |
4863 | #define PRLI_PHASE(_cls) \ |
4864 | ((_cls == DSC_LS_PRLI_PEND) || (_cls == DSC_LS_PRLI_COMP)) | |
4865 | ||
c5419e26 | 4866 | #include "qla_target.h" |
1da177e4 LT |
4867 | #include "qla_gbl.h" |
4868 | #include "qla_dbg.h" | |
4869 | #include "qla_inline.h" | |
1da177e4 | 4870 | #endif |