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[SCSI] qla2xxx: Add pci ids for new ISP types.
[mirror_ubuntu-zesty-kernel.git] / drivers / scsi / qla2xxx / qla_def.h
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1da177e4
LT		 1/********************************************************************************
2* QLOGIC LINUX SOFTWARE
3*
4* QLogic ISP2x00 device driver for Linux 2.6.x
5* Copyright (C) 2003-2004 QLogic Corporation
6* (www.qlogic.com)
7*
8* This program is free software; you can redistribute it and/or modify it
9* under the terms of the GNU General Public License as published by the
10* Free Software Foundation; either version 2, or (at your option) any
11* later version.
12*
13* This program is distributed in the hope that it will be useful, but
14* WITHOUT ANY WARRANTY; without even the implied warranty of
15* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16* General Public License for more details.
17**
18******************************************************************************/
19
20#ifndef __QLA_DEF_H
21#define __QLA_DEF_H
22
23#include <linux/kernel.h>
24#include <linux/init.h>
25#include <linux/types.h>
26#include <linux/module.h>
27#include <linux/list.h>
28#include <linux/pci.h>
29#include <linux/dma-mapping.h>
30#include <linux/sched.h>
31#include <linux/slab.h>
32#include <linux/dmapool.h>
33#include <linux/mempool.h>
34#include <linux/spinlock.h>
35#include <linux/completion.h>
abbd8870 36#include <linux/interrupt.h>
1da177e4
LT		 37#include <asm/semaphore.h>
38
39#include <scsi/scsi.h>
40#include <scsi/scsi_host.h>
41#include <scsi/scsi_device.h>
42#include <scsi/scsi_cmnd.h>
43
1da177e4
LT		 44#if defined(CONFIG_SCSI_QLA21XX) || defined(CONFIG_SCSI_QLA21XX_MODULE)
45#define IS_QLA2100(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2100)
46#else
47#define IS_QLA2100(ha) 0
48#endif
49
50#if defined(CONFIG_SCSI_QLA22XX) || defined(CONFIG_SCSI_QLA22XX_MODULE)
51#define IS_QLA2200(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2200)
52#else
53#define IS_QLA2200(ha) 0
54#endif
55
56#if defined(CONFIG_SCSI_QLA2300) || defined(CONFIG_SCSI_QLA2300_MODULE)
57#define IS_QLA2300(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2300)
58#define IS_QLA2312(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2312)
59#else
60#define IS_QLA2300(ha) 0
61#define IS_QLA2312(ha) 0
62#endif
63
64#if defined(CONFIG_SCSI_QLA2322) || defined(CONFIG_SCSI_QLA2322_MODULE)
65#define IS_QLA2322(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2322)
66#else
67#define IS_QLA2322(ha) 0
68#endif
69
70#if defined(CONFIG_SCSI_QLA6312) || defined(CONFIG_SCSI_QLA6312_MODULE)
71#define IS_QLA6312(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP6312)
72#define IS_QLA6322(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP6322)
73#else
74#define IS_QLA6312(ha) 0
75#define IS_QLA6322(ha) 0
76#endif
77
78#define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
79 IS_QLA6312(ha) || IS_QLA6322(ha))
80
81/*
82 * Only non-ISP2[12]00 have extended addressing support in the firmware.
83 */
84#define HAS_EXTENDED_IDS(ha) (!IS_QLA2100(ha) && !IS_QLA2200(ha))
85
86/*
87 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
88 * but that's fine as we don't look at the last 24 ones for
89 * ISP2100 HBAs.
90 */
91#define MAILBOX_REGISTER_COUNT_2100 8
92#define MAILBOX_REGISTER_COUNT 32
93
94#define QLA2200A_RISC_ROM_VER 4
95#define FPM_2300 6
96#define FPM_2310 7
97
98#include "qla_settings.h"
99
100/*
101 * Data bit definitions
102 */
103#define BIT_0 0x1
104#define BIT_1 0x2
105#define BIT_2 0x4
106#define BIT_3 0x8
107#define BIT_4 0x10
108#define BIT_5 0x20
109#define BIT_6 0x40
110#define BIT_7 0x80
111#define BIT_8 0x100
112#define BIT_9 0x200
113#define BIT_10 0x400
114#define BIT_11 0x800
115#define BIT_12 0x1000
116#define BIT_13 0x2000
117#define BIT_14 0x4000
118#define BIT_15 0x8000
119#define BIT_16 0x10000
120#define BIT_17 0x20000
121#define BIT_18 0x40000
122#define BIT_19 0x80000
123#define BIT_20 0x100000
124#define BIT_21 0x200000
125#define BIT_22 0x400000
126#define BIT_23 0x800000
127#define BIT_24 0x1000000
128#define BIT_25 0x2000000
129#define BIT_26 0x4000000
130#define BIT_27 0x8000000
131#define BIT_28 0x10000000
132#define BIT_29 0x20000000
133#define BIT_30 0x40000000
134#define BIT_31 0x80000000
135
136#define LSB(x) ((uint8_t)(x))
137#define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
138
139#define LSW(x) ((uint16_t)(x))
140#define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
141
142#define LSD(x) ((uint32_t)((uint64_t)(x)))
143#define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
144
145
146/*
147 * I/O register
148*/
149
150#define RD_REG_BYTE(addr) readb(addr)
151#define RD_REG_WORD(addr) readw(addr)
152#define RD_REG_DWORD(addr) readl(addr)
153#define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
154#define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
155#define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
156#define WRT_REG_BYTE(addr, data) writeb(data,addr)
157#define WRT_REG_WORD(addr, data) writew(data,addr)
158#define WRT_REG_DWORD(addr, data) writel(data,addr)
159
160/*
161 * Fibre Channel device definitions.
162 */
163#define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
164#define MAX_FIBRE_DEVICES 512
165#define MAX_FIBRE_LUNS 256
166#define MAX_RSCN_COUNT 32
167#define MAX_HOST_COUNT 16
168
169/*
170 * Host adapter default definitions.
171 */
172#define MAX_BUSES 1 /* We only have one bus today */
173#define MAX_TARGETS_2100 MAX_FIBRE_DEVICES
174#define MAX_TARGETS_2200 MAX_FIBRE_DEVICES
175#define MAX_TARGETS MAX_FIBRE_DEVICES
176#define MIN_LUNS 8
177#define MAX_LUNS MAX_FIBRE_LUNS
178#define MAX_CMDS_PER_LUN 255
179
180/*
181 * Fibre Channel device definitions.
182 */
183#define SNS_LAST_LOOP_ID_2100 0xfe
184#define SNS_LAST_LOOP_ID_2300 0x7ff
185
186#define LAST_LOCAL_LOOP_ID 0x7d
187#define SNS_FL_PORT 0x7e
188#define FABRIC_CONTROLLER 0x7f
189#define SIMPLE_NAME_SERVER 0x80
190#define SNS_FIRST_LOOP_ID 0x81
191#define MANAGEMENT_SERVER 0xfe
192#define BROADCAST 0xff
193
194#define RESERVED_LOOP_ID(x) ((x > LAST_LOCAL_LOOP_ID && \
195 x < SNS_FIRST_LOOP_ID) || \
196 x == MANAGEMENT_SERVER || \
197 x == BROADCAST)
198
199/*
200 * Timeout timer counts in seconds
201 */
8482e118 202#define PORT_RETRY_TIME 1
1da177e4
LT		 203#define LOOP_DOWN_TIMEOUT 60
204#define LOOP_DOWN_TIME 255 /* 240 */
205#define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
206
207/* Maximum outstanding commands in ISP queues (1-65535) */
208#define MAX_OUTSTANDING_COMMANDS 1024
209
210/* ISP request and response entry counts (37-65535) */
211#define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
212#define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
213#define REQUEST_ENTRY_CNT_2XXX_EXT_MEM 4096 /* Number of request entries. */
214#define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
215#define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
216
217/*
218 * SCSI Request Block
219 */
220typedef struct srb {
221 struct list_head list;
222
223 struct scsi_qla_host *ha; /* HA the SP is queued on */
bdf79621 224 struct fc_port *fcport;
1da177e4
LT		 225
226 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */
227
228 struct timer_list timer; /* Command timer */
229 atomic_t ref_count; /* Reference count for this structure */
230 uint16_t flags;
231
232 /* Request state */
233 uint16_t state;
234
1da177e4
LT		 235 /* Single transfer DMA context */
236 dma_addr_t dma_handle;
237
238 uint32_t request_sense_length;
239 uint8_t *request_sense_ptr;
240
1da177e4
LT		 241 /* SRB magic number */
242 uint16_t magic;
243#define SRB_MAGIC 0x10CB
244} srb_t;
245
246/*
247 * SRB flag definitions
248 */
249#define SRB_TIMEOUT BIT_0 /* Command timed out */
250#define SRB_DMA_VALID BIT_1 /* Command sent to ISP */
251#define SRB_WATCHDOG BIT_2 /* Command on watchdog list */
252#define SRB_ABORT_PENDING BIT_3 /* Command abort sent to device */
253
254#define SRB_ABORTED BIT_4 /* Command aborted command already */
255#define SRB_RETRY BIT_5 /* Command needs retrying */
256#define SRB_GOT_SENSE BIT_6 /* Command has sense data */
257#define SRB_FAILOVER BIT_7 /* Command in failover state */
258
259#define SRB_BUSY BIT_8 /* Command is in busy retry state */
260#define SRB_FO_CANCEL BIT_9 /* Command don't need to do failover */
261#define SRB_IOCTL BIT_10 /* IOCTL command. */
262#define SRB_TAPE BIT_11 /* FCP2 (Tape) command. */
263
264/*
265 * SRB state definitions
266 */
267#define SRB_FREE_STATE 0 /* returned back */
268#define SRB_PENDING_STATE 1 /* queued in LUN Q */
269#define SRB_ACTIVE_STATE 2 /* in Active Array */
270#define SRB_DONE_STATE 3 /* queued in Done Queue */
271#define SRB_RETRY_STATE 4 /* in Retry Queue */
272#define SRB_SUSPENDED_STATE 5 /* in suspended state */
273#define SRB_NO_QUEUE_STATE 6 /* is in between states */
274#define SRB_ACTIVE_TIMEOUT_STATE 7 /* in Active Array but timed out */
275#define SRB_FAILOVER_STATE 8 /* in Failover Queue */
276#define SRB_SCSI_RETRY_STATE 9 /* in Scsi Retry Queue */
277
278
279/*
280 * ISP I/O Register Set structure definitions.
281 */
282typedef volatile struct {
283 volatile uint16_t flash_address; /* Flash BIOS address */
284 volatile uint16_t flash_data; /* Flash BIOS data */
285 uint16_t unused_1[1]; /* Gap */
286 volatile uint16_t ctrl_status; /* Control/Status */
287#define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
288#define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
289#define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
290
291 volatile uint16_t ictrl; /* Interrupt control */
292#define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
293#define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
294
295 volatile uint16_t istatus; /* Interrupt status */
296#define ISR_RISC_INT BIT_3 /* RISC interrupt */
297
298 volatile uint16_t semaphore; /* Semaphore */
299 volatile uint16_t nvram; /* NVRAM register. */
300#define NVR_DESELECT 0
301#define NVR_BUSY BIT_15
302#define NVR_WRT_ENABLE BIT_14 /* Write enable */
303#define NVR_PR_ENABLE BIT_13 /* Protection register enable */
304#define NVR_DATA_IN BIT_3
305#define NVR_DATA_OUT BIT_2
306#define NVR_SELECT BIT_1
307#define NVR_CLOCK BIT_0
308
309 union {
310 struct {
311 volatile uint16_t mailbox0;
312 volatile uint16_t mailbox1;
313 volatile uint16_t mailbox2;
314 volatile uint16_t mailbox3;
315 volatile uint16_t mailbox4;
316 volatile uint16_t mailbox5;
317 volatile uint16_t mailbox6;
318 volatile uint16_t mailbox7;
319 uint16_t unused_2[59]; /* Gap */
320 } __attribute__((packed)) isp2100;
321 struct {
322 /* Request Queue */
323 volatile uint16_t req_q_in; /* In-Pointer */
324 volatile uint16_t req_q_out; /* Out-Pointer */
325 /* Response Queue */
326 volatile uint16_t rsp_q_in; /* In-Pointer */
327 volatile uint16_t rsp_q_out; /* Out-Pointer */
328
329 /* RISC to Host Status */
330 volatile uint32_t host_status;
331#define HSR_RISC_INT BIT_15 /* RISC interrupt */
332#define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
333
334 /* Host to Host Semaphore */
335 volatile uint16_t host_semaphore;
336 uint16_t unused_3[17]; /* Gap */
337 volatile uint16_t mailbox0;
338 volatile uint16_t mailbox1;
339 volatile uint16_t mailbox2;
340 volatile uint16_t mailbox3;
341 volatile uint16_t mailbox4;
342 volatile uint16_t mailbox5;
343 volatile uint16_t mailbox6;
344 volatile uint16_t mailbox7;
345 volatile uint16_t mailbox8;
346 volatile uint16_t mailbox9;
347 volatile uint16_t mailbox10;
348 volatile uint16_t mailbox11;
349 volatile uint16_t mailbox12;
350 volatile uint16_t mailbox13;
351 volatile uint16_t mailbox14;
352 volatile uint16_t mailbox15;
353 volatile uint16_t mailbox16;
354 volatile uint16_t mailbox17;
355 volatile uint16_t mailbox18;
356 volatile uint16_t mailbox19;
357 volatile uint16_t mailbox20;
358 volatile uint16_t mailbox21;
359 volatile uint16_t mailbox22;
360 volatile uint16_t mailbox23;
361 volatile uint16_t mailbox24;
362 volatile uint16_t mailbox25;
363 volatile uint16_t mailbox26;
364 volatile uint16_t mailbox27;
365 volatile uint16_t mailbox28;
366 volatile uint16_t mailbox29;
367 volatile uint16_t mailbox30;
368 volatile uint16_t mailbox31;
369 volatile uint16_t fb_cmd;
370 uint16_t unused_4[10]; /* Gap */
371 } __attribute__((packed)) isp2300;
372 } u;
373
374 volatile uint16_t fpm_diag_config;
375 uint16_t unused_5[0x6]; /* Gap */
376 volatile uint16_t pcr; /* Processor Control Register. */
377 uint16_t unused_6[0x5]; /* Gap */
378 volatile uint16_t mctr; /* Memory Configuration and Timing. */
379 uint16_t unused_7[0x3]; /* Gap */
380 volatile uint16_t fb_cmd_2100; /* Unused on 23XX */
381 uint16_t unused_8[0x3]; /* Gap */
382 volatile uint16_t hccr; /* Host command & control register. */
383#define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
384#define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
385 /* HCCR commands */
386#define HCCR_RESET_RISC 0x1000 /* Reset RISC */
387#define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
388#define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
389#define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
390#define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
391#define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
392#define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
393#define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
394
395 uint16_t unused_9[5]; /* Gap */
396 volatile uint16_t gpiod; /* GPIO Data register. */
397 volatile uint16_t gpioe; /* GPIO Enable register. */
398#define GPIO_LED_MASK 0x00C0
399#define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
400#define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
401#define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
402#define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
403
404 union {
405 struct {
406 uint16_t unused_10[8]; /* Gap */
407 volatile uint16_t mailbox8;
408 volatile uint16_t mailbox9;
409 volatile uint16_t mailbox10;
410 volatile uint16_t mailbox11;
411 volatile uint16_t mailbox12;
412 volatile uint16_t mailbox13;
413 volatile uint16_t mailbox14;
414 volatile uint16_t mailbox15;
415 volatile uint16_t mailbox16;
416 volatile uint16_t mailbox17;
417 volatile uint16_t mailbox18;
418 volatile uint16_t mailbox19;
419 volatile uint16_t mailbox20;
420 volatile uint16_t mailbox21;
421 volatile uint16_t mailbox22;
422 volatile uint16_t mailbox23; /* Also probe reg. */
423 } __attribute__((packed)) isp2200;
424 } u_end;
425} device_reg_t;
426
427#define ISP_REQ_Q_IN(ha, reg) \
428 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
429 &(reg)->u.isp2100.mailbox4 : \
430 &(reg)->u.isp2300.req_q_in)
431#define ISP_REQ_Q_OUT(ha, reg) \
432 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
433 &(reg)->u.isp2100.mailbox4 : \
434 &(reg)->u.isp2300.req_q_out)
435#define ISP_RSP_Q_IN(ha, reg) \
436 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
437 &(reg)->u.isp2100.mailbox5 : \
438 &(reg)->u.isp2300.rsp_q_in)
439#define ISP_RSP_Q_OUT(ha, reg) \
440 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
441 &(reg)->u.isp2100.mailbox5 : \
442 &(reg)->u.isp2300.rsp_q_out)
443
444#define MAILBOX_REG(ha, reg, num) \
445 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
446 (num < 8 ? \
447 &(reg)->u.isp2100.mailbox0 + (num) : \
448 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
449 &(reg)->u.isp2300.mailbox0 + (num))
450#define RD_MAILBOX_REG(ha, reg, num) \
451 RD_REG_WORD(MAILBOX_REG(ha, reg, num))
452#define WRT_MAILBOX_REG(ha, reg, num, data) \
453 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
454
455#define FB_CMD_REG(ha, reg) \
456 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
457 &(reg)->fb_cmd_2100 : \
458 &(reg)->u.isp2300.fb_cmd)
459#define RD_FB_CMD_REG(ha, reg) \
460 RD_REG_WORD(FB_CMD_REG(ha, reg))
461#define WRT_FB_CMD_REG(ha, reg, data) \
462 WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
463
464typedef struct {
465 uint32_t out_mb; /* outbound from driver */
466 uint32_t in_mb; /* Incoming from RISC */
467 uint16_t mb[MAILBOX_REGISTER_COUNT];
468 long buf_size;
469 void *bufp;
470 uint32_t tov;
471 uint8_t flags;
472#define MBX_DMA_IN BIT_0
473#define MBX_DMA_OUT BIT_1
474#define IOCTL_CMD BIT_2
475} mbx_cmd_t;
476
477#define MBX_TOV_SECONDS 30
478
479/*
480 * ISP product identification definitions in mailboxes after reset.
481 */
482#define PROD_ID_1 0x4953
483#define PROD_ID_2 0x0000
484#define PROD_ID_2a 0x5020
485#define PROD_ID_3 0x2020
486
487/*
488 * ISP mailbox Self-Test status codes
489 */
490#define MBS_FRM_ALIVE 0 /* Firmware Alive. */
491#define MBS_CHKSUM_ERR 1 /* Checksum Error. */
492#define MBS_BUSY 4 /* Busy. */
493
494/*
495 * ISP mailbox command complete status codes
496 */
497#define MBS_COMMAND_COMPLETE 0x4000
498#define MBS_INVALID_COMMAND 0x4001
499#define MBS_HOST_INTERFACE_ERROR 0x4002
500#define MBS_TEST_FAILED 0x4003
501#define MBS_COMMAND_ERROR 0x4005
502#define MBS_COMMAND_PARAMETER_ERROR 0x4006
503#define MBS_PORT_ID_USED 0x4007
504#define MBS_LOOP_ID_USED 0x4008
505#define MBS_ALL_IDS_IN_USE 0x4009
506#define MBS_NOT_LOGGED_IN 0x400A
507
508/*
509 * ISP mailbox asynchronous event status codes
510 */
511#define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
512#define MBA_RESET 0x8001 /* Reset Detected. */
513#define MBA_SYSTEM_ERR 0x8002 /* System Error. */
514#define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
515#define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
516#define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
517#define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
518 /* occurred. */
519#define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
520#define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
521#define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
522#define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
523#define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
524#define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
525#define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
526#define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
527#define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
528#define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
529#define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
530#define MBA_IP_RECEIVE 0x8023 /* IP Received. */
531#define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
532#define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
533#define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
534#define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
535 /* used. */
536#define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
537#define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
538#define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
539#define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
540#define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
541#define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
542#define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
543#define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
544#define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
545#define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
546#define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
547#define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
548#define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
549
550/*
551 * Firmware options 1, 2, 3.
552 */
553#define FO1_AE_ON_LIPF8 BIT_0
554#define FO1_AE_ALL_LIP_RESET BIT_1
555#define FO1_CTIO_RETRY BIT_3
556#define FO1_DISABLE_LIP_F7_SW BIT_4
557#define FO1_DISABLE_100MS_LOS_WAIT BIT_5
558#define FO1_DISABLE_GPIO6_7 BIT_6
559#define FO1_AE_ON_LOOP_INIT_ERR BIT_7
560#define FO1_SET_EMPHASIS_SWING BIT_8
561#define FO1_AE_AUTO_BYPASS BIT_9
562#define FO1_ENABLE_PURE_IOCB BIT_10
563#define FO1_AE_PLOGI_RJT BIT_11
564#define FO1_ENABLE_ABORT_SEQUENCE BIT_12
565#define FO1_AE_QUEUE_FULL BIT_13
566
567#define FO2_ENABLE_ATIO_TYPE_3 BIT_0
568#define FO2_REV_LOOPBACK BIT_1
569
570#define FO3_ENABLE_EMERG_IOCB BIT_0
571#define FO3_AE_RND_ERROR BIT_1
572
573/*
574 * ISP mailbox commands
575 */
576#define MBC_LOAD_RAM 1 /* Load RAM. */
577#define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
578#define MBC_WRITE_RAM_WORD 4 /* Write RAM word. */
579#define MBC_READ_RAM_WORD 5 /* Read RAM word. */
580#define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
581#define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
582#define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
583#define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
584#define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
585#define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
586#define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
587#define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
588#define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
589#define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
590#define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
591#define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
592#define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
593#define MBC_RESET 0x18 /* Reset. */
594#define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
595#define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
596#define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
597#define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
598#define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
599#define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
600#define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
601#define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
602#define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
603#define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
604#define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
605#define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
606#define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
607#define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
608#define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
609#define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
610#define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
611#define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
612#define MBC_GET_RNID_PARAMS 0x5a /* Data Rate */
613#define MBC_DATA_RATE 0x5d /* Get RNID parameters */
614#define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
615#define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
616 /* Initialization Procedure */
617#define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
618#define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
619#define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
620#define MBC_TARGET_RESET 0x66 /* Target Reset. */
621#define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
622#define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
623#define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
624#define MBC_GET_PORT_NAME 0x6a /* Get port name. */
625#define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
626#define MBC_LIP_RESET 0x6c /* LIP reset. */
627#define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
628 /* commandd. */
629#define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
630#define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
631#define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
632#define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
633#define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
634#define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
635#define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
636#define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
637#define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
638#define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
639#define MBC_LUN_RESET 0x7E /* Send LUN reset */
640
641/* Firmware return data sizes */
642#define FCAL_MAP_SIZE 128
643
644/* Mailbox bit definitions for out_mb and in_mb */
645#define MBX_31 BIT_31
646#define MBX_30 BIT_30
647#define MBX_29 BIT_29
648#define MBX_28 BIT_28
649#define MBX_27 BIT_27
650#define MBX_26 BIT_26
651#define MBX_25 BIT_25
652#define MBX_24 BIT_24
653#define MBX_23 BIT_23
654#define MBX_22 BIT_22
655#define MBX_21 BIT_21
656#define MBX_20 BIT_20
657#define MBX_19 BIT_19
658#define MBX_18 BIT_18
659#define MBX_17 BIT_17
660#define MBX_16 BIT_16
661#define MBX_15 BIT_15
662#define MBX_14 BIT_14
663#define MBX_13 BIT_13
664#define MBX_12 BIT_12
665#define MBX_11 BIT_11
666#define MBX_10 BIT_10
667#define MBX_9 BIT_9
668#define MBX_8 BIT_8
669#define MBX_7 BIT_7
670#define MBX_6 BIT_6
671#define MBX_5 BIT_5
672#define MBX_4 BIT_4
673#define MBX_3 BIT_3
674#define MBX_2 BIT_2
675#define MBX_1 BIT_1
676#define MBX_0 BIT_0
677
678/*
679 * Firmware state codes from get firmware state mailbox command
680 */
681#define FSTATE_CONFIG_WAIT 0
682#define FSTATE_WAIT_AL_PA 1
683#define FSTATE_WAIT_LOGIN 2
684#define FSTATE_READY 3
685#define FSTATE_LOSS_OF_SYNC 4
686#define FSTATE_ERROR 5
687#define FSTATE_REINIT 6
688#define FSTATE_NON_PART 7
689
690#define FSTATE_CONFIG_CORRECT 0
691#define FSTATE_P2P_RCV_LIP 1
692#define FSTATE_P2P_CHOOSE_LOOP 2
693#define FSTATE_P2P_RCV_UNIDEN_LIP 3
694#define FSTATE_FATAL_ERROR 4
695#define FSTATE_LOOP_BACK_CONN 5
696
697/*
698 * Port Database structure definition
699 * Little endian except where noted.
700 */
701#define PORT_DATABASE_SIZE 128 /* bytes */
702typedef struct {
703 uint8_t options;
704 uint8_t control;
705 uint8_t master_state;
706 uint8_t slave_state;
707 uint8_t reserved[2];
708 uint8_t hard_address;
709 uint8_t reserved_1;
710 uint8_t port_id[4];
711 uint8_t node_name[WWN_SIZE];
712 uint8_t port_name[WWN_SIZE];
713 uint16_t execution_throttle;
714 uint16_t execution_count;
715 uint8_t reset_count;
716 uint8_t reserved_2;
717 uint16_t resource_allocation;
718 uint16_t current_allocation;
719 uint16_t queue_head;
720 uint16_t queue_tail;
721 uint16_t transmit_execution_list_next;
722 uint16_t transmit_execution_list_previous;
723 uint16_t common_features;
724 uint16_t total_concurrent_sequences;
725 uint16_t RO_by_information_category;
726 uint8_t recipient;
727 uint8_t initiator;
728 uint16_t receive_data_size;
729 uint16_t concurrent_sequences;
730 uint16_t open_sequences_per_exchange;
731 uint16_t lun_abort_flags;
732 uint16_t lun_stop_flags;
733 uint16_t stop_queue_head;
734 uint16_t stop_queue_tail;
735 uint16_t port_retry_timer;
736 uint16_t next_sequence_id;
737 uint16_t frame_count;
738 uint16_t PRLI_payload_length;
739 uint8_t prli_svc_param_word_0[2]; /* Big endian */
740 /* Bits 15-0 of word 0 */
741 uint8_t prli_svc_param_word_3[2]; /* Big endian */
742 /* Bits 15-0 of word 3 */
743 uint16_t loop_id;
744 uint16_t extended_lun_info_list_pointer;
745 uint16_t extended_lun_stop_list_pointer;
746} port_database_t;
747
748/*
749 * Port database slave/master states
750 */
751#define PD_STATE_DISCOVERY 0
752#define PD_STATE_WAIT_DISCOVERY_ACK 1
753#define PD_STATE_PORT_LOGIN 2
754#define PD_STATE_WAIT_PORT_LOGIN_ACK 3
755#define PD_STATE_PROCESS_LOGIN 4
756#define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
757#define PD_STATE_PORT_LOGGED_IN 6
758#define PD_STATE_PORT_UNAVAILABLE 7
759#define PD_STATE_PROCESS_LOGOUT 8
760#define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
761#define PD_STATE_PORT_LOGOUT 10
762#define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
763
764
765/*
766 * ISP Initialization Control Block.
767 * Little endian except where noted.
768 */
769#define ICB_VERSION 1
770typedef struct {
771 uint8_t version;
772 uint8_t reserved_1;
773
774 /*
775 * LSB BIT 0 = Enable Hard Loop Id
776 * LSB BIT 1 = Enable Fairness
777 * LSB BIT 2 = Enable Full-Duplex
778 * LSB BIT 3 = Enable Fast Posting
779 * LSB BIT 4 = Enable Target Mode
780 * LSB BIT 5 = Disable Initiator Mode
781 * LSB BIT 6 = Enable ADISC
782 * LSB BIT 7 = Enable Target Inquiry Data
783 *
784 * MSB BIT 0 = Enable PDBC Notify
785 * MSB BIT 1 = Non Participating LIP
786 * MSB BIT 2 = Descending Loop ID Search
787 * MSB BIT 3 = Acquire Loop ID in LIPA
788 * MSB BIT 4 = Stop PortQ on Full Status
789 * MSB BIT 5 = Full Login after LIP
790 * MSB BIT 6 = Node Name Option
791 * MSB BIT 7 = Ext IFWCB enable bit
792 */
793 uint8_t firmware_options[2];
794
795 uint16_t frame_payload_size;
796 uint16_t max_iocb_allocation;
797 uint16_t execution_throttle;
798 uint8_t retry_count;
799 uint8_t retry_delay; /* unused */
800 uint8_t port_name[WWN_SIZE]; /* Big endian. */
801 uint16_t hard_address;
802 uint8_t inquiry_data;
803 uint8_t login_timeout;
804 uint8_t node_name[WWN_SIZE]; /* Big endian. */
805
806 uint16_t request_q_outpointer;
807 uint16_t response_q_inpointer;
808 uint16_t request_q_length;
809 uint16_t response_q_length;
810 uint32_t request_q_address[2];
811 uint32_t response_q_address[2];
812
813 uint16_t lun_enables;
814 uint8_t command_resource_count;
815 uint8_t immediate_notify_resource_count;
816 uint16_t timeout;
817 uint8_t reserved_2[2];
818
819 /*
820 * LSB BIT 0 = Timer Operation mode bit 0
821 * LSB BIT 1 = Timer Operation mode bit 1
822 * LSB BIT 2 = Timer Operation mode bit 2
823 * LSB BIT 3 = Timer Operation mode bit 3
824 * LSB BIT 4 = Init Config Mode bit 0
825 * LSB BIT 5 = Init Config Mode bit 1
826 * LSB BIT 6 = Init Config Mode bit 2
827 * LSB BIT 7 = Enable Non part on LIHA failure
828 *
829 * MSB BIT 0 = Enable class 2
830 * MSB BIT 1 = Enable ACK0
831 * MSB BIT 2 =
832 * MSB BIT 3 =
833 * MSB BIT 4 = FC Tape Enable
834 * MSB BIT 5 = Enable FC Confirm
835 * MSB BIT 6 = Enable command queuing in target mode
836 * MSB BIT 7 = No Logo On Link Down
837 */
838 uint8_t add_firmware_options[2];
839
840 uint8_t response_accumulation_timer;
841 uint8_t interrupt_delay_timer;
842
843 /*
844 * LSB BIT 0 = Enable Read xfr_rdy
845 * LSB BIT 1 = Soft ID only
846 * LSB BIT 2 =
847 * LSB BIT 3 =
848 * LSB BIT 4 = FCP RSP Payload [0]
849 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
850 * LSB BIT 6 = Enable Out-of-Order frame handling
851 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
852 *
853 * MSB BIT 0 = Sbus enable - 2300
854 * MSB BIT 1 =
855 * MSB BIT 2 =
856 * MSB BIT 3 =
857 * MSB BIT 4 =
858 * MSB BIT 5 = enable 50 ohm termination
859 * MSB BIT 6 = Data Rate (2300 only)
860 * MSB BIT 7 = Data Rate (2300 only)
861 */
862 uint8_t special_options[2];
863
864 uint8_t reserved_3[26];
865} init_cb_t;
866
867/*
868 * Get Link Status mailbox command return buffer.
869 */
870typedef struct {
871 uint32_t link_fail_cnt;
872 uint32_t loss_sync_cnt;
873 uint32_t loss_sig_cnt;
874 uint32_t prim_seq_err_cnt;
875 uint32_t inval_xmit_word_cnt;
876 uint32_t inval_crc_cnt;
877} link_stat_t;
878
879/*
880 * NVRAM Command values.
881 */
882#define NV_START_BIT BIT_2
883#define NV_WRITE_OP (BIT_26+BIT_24)
884#define NV_READ_OP (BIT_26+BIT_25)
885#define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
886#define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
887#define NV_DELAY_COUNT 10
888
889/*
890 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
891 */
892typedef struct {
893 /*
894 * NVRAM header
895 */
896 uint8_t id[4];
897 uint8_t nvram_version;
898 uint8_t reserved_0;
899
900 /*
901 * NVRAM RISC parameter block
902 */
903 uint8_t parameter_block_version;
904 uint8_t reserved_1;
905
906 /*
907 * LSB BIT 0 = Enable Hard Loop Id
908 * LSB BIT 1 = Enable Fairness
909 * LSB BIT 2 = Enable Full-Duplex
910 * LSB BIT 3 = Enable Fast Posting
911 * LSB BIT 4 = Enable Target Mode
912 * LSB BIT 5 = Disable Initiator Mode
913 * LSB BIT 6 = Enable ADISC
914 * LSB BIT 7 = Enable Target Inquiry Data
915 *
916 * MSB BIT 0 = Enable PDBC Notify
917 * MSB BIT 1 = Non Participating LIP
918 * MSB BIT 2 = Descending Loop ID Search
919 * MSB BIT 3 = Acquire Loop ID in LIPA
920 * MSB BIT 4 = Stop PortQ on Full Status
921 * MSB BIT 5 = Full Login after LIP
922 * MSB BIT 6 = Node Name Option
923 * MSB BIT 7 = Ext IFWCB enable bit
924 */
925 uint8_t firmware_options[2];
926
927 uint16_t frame_payload_size;
928 uint16_t max_iocb_allocation;
929 uint16_t execution_throttle;
930 uint8_t retry_count;
931 uint8_t retry_delay; /* unused */
932 uint8_t port_name[WWN_SIZE]; /* Big endian. */
933 uint16_t hard_address;
934 uint8_t inquiry_data;
935 uint8_t login_timeout;
936 uint8_t node_name[WWN_SIZE]; /* Big endian. */
937
938 /*
939 * LSB BIT 0 = Timer Operation mode bit 0
940 * LSB BIT 1 = Timer Operation mode bit 1
941 * LSB BIT 2 = Timer Operation mode bit 2
942 * LSB BIT 3 = Timer Operation mode bit 3
943 * LSB BIT 4 = Init Config Mode bit 0
944 * LSB BIT 5 = Init Config Mode bit 1
945 * LSB BIT 6 = Init Config Mode bit 2
946 * LSB BIT 7 = Enable Non part on LIHA failure
947 *
948 * MSB BIT 0 = Enable class 2
949 * MSB BIT 1 = Enable ACK0
950 * MSB BIT 2 =
951 * MSB BIT 3 =
952 * MSB BIT 4 = FC Tape Enable
953 * MSB BIT 5 = Enable FC Confirm
954 * MSB BIT 6 = Enable command queuing in target mode
955 * MSB BIT 7 = No Logo On Link Down
956 */
957 uint8_t add_firmware_options[2];
958
959 uint8_t response_accumulation_timer;
960 uint8_t interrupt_delay_timer;
961
962 /*
963 * LSB BIT 0 = Enable Read xfr_rdy
964 * LSB BIT 1 = Soft ID only
965 * LSB BIT 2 =
966 * LSB BIT 3 =
967 * LSB BIT 4 = FCP RSP Payload [0]
968 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
969 * LSB BIT 6 = Enable Out-of-Order frame handling
970 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
971 *
972 * MSB BIT 0 = Sbus enable - 2300
973 * MSB BIT 1 =
974 * MSB BIT 2 =
975 * MSB BIT 3 =
976 * MSB BIT 4 =
977 * MSB BIT 5 = enable 50 ohm termination
978 * MSB BIT 6 = Data Rate (2300 only)
979 * MSB BIT 7 = Data Rate (2300 only)
980 */
981 uint8_t special_options[2];
982
983 /* Reserved for expanded RISC parameter block */
984 uint8_t reserved_2[22];
985
986 /*
987 * LSB BIT 0 = Tx Sensitivity 1G bit 0
988 * LSB BIT 1 = Tx Sensitivity 1G bit 1
989 * LSB BIT 2 = Tx Sensitivity 1G bit 2
990 * LSB BIT 3 = Tx Sensitivity 1G bit 3
991 * LSB BIT 4 = Rx Sensitivity 1G bit 0
992 * LSB BIT 5 = Rx Sensitivity 1G bit 1
993 * LSB BIT 6 = Rx Sensitivity 1G bit 2
994 * LSB BIT 7 = Rx Sensitivity 1G bit 3
995 *
996 * MSB BIT 0 = Tx Sensitivity 2G bit 0
997 * MSB BIT 1 = Tx Sensitivity 2G bit 1
998 * MSB BIT 2 = Tx Sensitivity 2G bit 2
999 * MSB BIT 3 = Tx Sensitivity 2G bit 3
1000 * MSB BIT 4 = Rx Sensitivity 2G bit 0
1001 * MSB BIT 5 = Rx Sensitivity 2G bit 1
1002 * MSB BIT 6 = Rx Sensitivity 2G bit 2
1003 * MSB BIT 7 = Rx Sensitivity 2G bit 3
1004 *
1005 * LSB BIT 0 = Output Swing 1G bit 0
1006 * LSB BIT 1 = Output Swing 1G bit 1
1007 * LSB BIT 2 = Output Swing 1G bit 2
1008 * LSB BIT 3 = Output Emphasis 1G bit 0
1009 * LSB BIT 4 = Output Emphasis 1G bit 1
1010 * LSB BIT 5 = Output Swing 2G bit 0
1011 * LSB BIT 6 = Output Swing 2G bit 1
1012 * LSB BIT 7 = Output Swing 2G bit 2
1013 *
1014 * MSB BIT 0 = Output Emphasis 2G bit 0
1015 * MSB BIT 1 = Output Emphasis 2G bit 1
1016 * MSB BIT 2 = Output Enable
1017 * MSB BIT 3 =
1018 * MSB BIT 4 =
1019 * MSB BIT 5 =
1020 * MSB BIT 6 =
1021 * MSB BIT 7 =
1022 */
1023 uint8_t seriallink_options[4];
1024
1025 /*
1026 * NVRAM host parameter block
1027 *
1028 * LSB BIT 0 = Enable spinup delay
1029 * LSB BIT 1 = Disable BIOS
1030 * LSB BIT 2 = Enable Memory Map BIOS
1031 * LSB BIT 3 = Enable Selectable Boot
1032 * LSB BIT 4 = Disable RISC code load
1033 * LSB BIT 5 = Set cache line size 1
1034 * LSB BIT 6 = PCI Parity Disable
1035 * LSB BIT 7 = Enable extended logging
1036 *
1037 * MSB BIT 0 = Enable 64bit addressing
1038 * MSB BIT 1 = Enable lip reset
1039 * MSB BIT 2 = Enable lip full login
1040 * MSB BIT 3 = Enable target reset
1041 * MSB BIT 4 = Enable database storage
1042 * MSB BIT 5 = Enable cache flush read
1043 * MSB BIT 6 = Enable database load
1044 * MSB BIT 7 = Enable alternate WWN
1045 */
1046 uint8_t host_p[2];
1047
1048 uint8_t boot_node_name[WWN_SIZE];
1049 uint8_t boot_lun_number;
1050 uint8_t reset_delay;
1051 uint8_t port_down_retry_count;
1052 uint8_t boot_id_number;
1053 uint16_t max_luns_per_target;
1054 uint8_t fcode_boot_port_name[WWN_SIZE];
1055 uint8_t alternate_port_name[WWN_SIZE];
1056 uint8_t alternate_node_name[WWN_SIZE];
1057
1058 /*
1059 * BIT 0 = Selective Login
1060 * BIT 1 = Alt-Boot Enable
1061 * BIT 2 =
1062 * BIT 3 = Boot Order List
1063 * BIT 4 =
1064 * BIT 5 = Selective LUN
1065 * BIT 6 =
1066 * BIT 7 = unused
1067 */
1068 uint8_t efi_parameters;
1069
1070 uint8_t link_down_timeout;
1071
1072 uint8_t adapter_id_0[4];
1073 uint8_t adapter_id_1[4];
1074 uint8_t adapter_id_2[4];
1075 uint8_t adapter_id_3[4];
1076
1077 uint8_t alt1_boot_node_name[WWN_SIZE];
1078 uint16_t alt1_boot_lun_number;
1079 uint8_t alt2_boot_node_name[WWN_SIZE];
1080 uint16_t alt2_boot_lun_number;
1081 uint8_t alt3_boot_node_name[WWN_SIZE];
1082 uint16_t alt3_boot_lun_number;
1083 uint8_t alt4_boot_node_name[WWN_SIZE];
1084 uint16_t alt4_boot_lun_number;
1085 uint8_t alt5_boot_node_name[WWN_SIZE];
1086 uint16_t alt5_boot_lun_number;
1087 uint8_t alt6_boot_node_name[WWN_SIZE];
1088 uint16_t alt6_boot_lun_number;
1089 uint8_t alt7_boot_node_name[WWN_SIZE];
1090 uint16_t alt7_boot_lun_number;
1091
1092 uint8_t reserved_3[2];
1093
1094 /* Offset 200-215 : Model Number */
1095 uint8_t model_number[16];
1096
1097 /* OEM related items */
1098 uint8_t oem_specific[16];
1099
1100 /*
1101 * NVRAM Adapter Features offset 232-239
1102 *
1103 * LSB BIT 0 = External GBIC
1104 * LSB BIT 1 = Risc RAM parity
1105 * LSB BIT 2 = Buffer Plus Module
1106 * LSB BIT 3 = Multi Chip Adapter
1107 * LSB BIT 4 = Internal connector
1108 * LSB BIT 5 =
1109 * LSB BIT 6 =
1110 * LSB BIT 7 =
1111 *
1112 * MSB BIT 0 =
1113 * MSB BIT 1 =
1114 * MSB BIT 2 =
1115 * MSB BIT 3 =
1116 * MSB BIT 4 =
1117 * MSB BIT 5 =
1118 * MSB BIT 6 =
1119 * MSB BIT 7 =
1120 */
1121 uint8_t adapter_features[2];
1122
1123 uint8_t reserved_4[16];
1124
1125 /* Subsystem vendor ID for ISP2200 */
1126 uint16_t subsystem_vendor_id_2200;
1127
1128 /* Subsystem device ID for ISP2200 */
1129 uint16_t subsystem_device_id_2200;
1130
1131 uint8_t reserved_5;
1132 uint8_t checksum;
1133} nvram_t;
1134
1135/*
1136 * ISP queue - response queue entry definition.
1137 */
1138typedef struct {
1139 uint8_t data[60];
1140 uint32_t signature;
1141#define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
1142} response_t;
1143
1144typedef union {
1145 uint16_t extended;
1146 struct {
1147 uint8_t reserved;
1148 uint8_t standard;
1149 } id;
1150} target_id_t;
1151
1152#define SET_TARGET_ID(ha, to, from) \
1153do { \
1154 if (HAS_EXTENDED_IDS(ha)) \
1155 to.extended = cpu_to_le16(from); \
1156 else \
1157 to.id.standard = (uint8_t)from; \
1158} while (0)
1159
1160/*
1161 * ISP queue - command entry structure definition.
1162 */
1163#define COMMAND_TYPE 0x11 /* Command entry */
1164#define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
1165typedef struct {
1166 uint8_t entry_type; /* Entry type. */
1167 uint8_t entry_count; /* Entry count. */
1168 uint8_t sys_define; /* System defined. */
1169 uint8_t entry_status; /* Entry Status. */
1170 uint32_t handle; /* System handle. */
1171 target_id_t target; /* SCSI ID */
1172 uint16_t lun; /* SCSI LUN */
1173 uint16_t control_flags; /* Control flags. */
1174#define CF_WRITE BIT_6
1175#define CF_READ BIT_5
1176#define CF_SIMPLE_TAG BIT_3
1177#define CF_ORDERED_TAG BIT_2
1178#define CF_HEAD_TAG BIT_1
1179 uint16_t reserved_1;
1180 uint16_t timeout; /* Command timeout. */
1181 uint16_t dseg_count; /* Data segment count. */
1182 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1183 uint32_t byte_count; /* Total byte count. */
1184 uint32_t dseg_0_address; /* Data segment 0 address. */
1185 uint32_t dseg_0_length; /* Data segment 0 length. */
1186 uint32_t dseg_1_address; /* Data segment 1 address. */
1187 uint32_t dseg_1_length; /* Data segment 1 length. */
1188 uint32_t dseg_2_address; /* Data segment 2 address. */
1189 uint32_t dseg_2_length; /* Data segment 2 length. */
1190} cmd_entry_t;
1191
1192/*
1193 * ISP queue - 64-Bit addressing, command entry structure definition.
1194 */
1195#define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
1196typedef struct {
1197 uint8_t entry_type; /* Entry type. */
1198 uint8_t entry_count; /* Entry count. */
1199 uint8_t sys_define; /* System defined. */
1200 uint8_t entry_status; /* Entry Status. */
1201 uint32_t handle; /* System handle. */
1202 target_id_t target; /* SCSI ID */
1203 uint16_t lun; /* SCSI LUN */
1204 uint16_t control_flags; /* Control flags. */
1205 uint16_t reserved_1;
1206 uint16_t timeout; /* Command timeout. */
1207 uint16_t dseg_count; /* Data segment count. */
1208 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1209 uint32_t byte_count; /* Total byte count. */
1210 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1211 uint32_t dseg_0_length; /* Data segment 0 length. */
1212 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1213 uint32_t dseg_1_length; /* Data segment 1 length. */
1214} cmd_a64_entry_t, request_t;
1215
1216/*
1217 * ISP queue - continuation entry structure definition.
1218 */
1219#define CONTINUE_TYPE 0x02 /* Continuation entry. */
1220typedef struct {
1221 uint8_t entry_type; /* Entry type. */
1222 uint8_t entry_count; /* Entry count. */
1223 uint8_t sys_define; /* System defined. */
1224 uint8_t entry_status; /* Entry Status. */
1225 uint32_t reserved;
1226 uint32_t dseg_0_address; /* Data segment 0 address. */
1227 uint32_t dseg_0_length; /* Data segment 0 length. */
1228 uint32_t dseg_1_address; /* Data segment 1 address. */
1229 uint32_t dseg_1_length; /* Data segment 1 length. */
1230 uint32_t dseg_2_address; /* Data segment 2 address. */
1231 uint32_t dseg_2_length; /* Data segment 2 length. */
1232 uint32_t dseg_3_address; /* Data segment 3 address. */
1233 uint32_t dseg_3_length; /* Data segment 3 length. */
1234 uint32_t dseg_4_address; /* Data segment 4 address. */
1235 uint32_t dseg_4_length; /* Data segment 4 length. */
1236 uint32_t dseg_5_address; /* Data segment 5 address. */
1237 uint32_t dseg_5_length; /* Data segment 5 length. */
1238 uint32_t dseg_6_address; /* Data segment 6 address. */
1239 uint32_t dseg_6_length; /* Data segment 6 length. */
1240} cont_entry_t;
1241
1242/*
1243 * ISP queue - 64-Bit addressing, continuation entry structure definition.
1244 */
1245#define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
1246typedef struct {
1247 uint8_t entry_type; /* Entry type. */
1248 uint8_t entry_count; /* Entry count. */
1249 uint8_t sys_define; /* System defined. */
1250 uint8_t entry_status; /* Entry Status. */
1251 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1252 uint32_t dseg_0_length; /* Data segment 0 length. */
1253 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1254 uint32_t dseg_1_length; /* Data segment 1 length. */
1255 uint32_t dseg_2_address [2]; /* Data segment 2 address. */
1256 uint32_t dseg_2_length; /* Data segment 2 length. */
1257 uint32_t dseg_3_address[2]; /* Data segment 3 address. */
1258 uint32_t dseg_3_length; /* Data segment 3 length. */
1259 uint32_t dseg_4_address[2]; /* Data segment 4 address. */
1260 uint32_t dseg_4_length; /* Data segment 4 length. */
1261} cont_a64_entry_t;
1262
1263/*
1264 * ISP queue - status entry structure definition.
1265 */
1266#define STATUS_TYPE 0x03 /* Status entry. */
1267typedef struct {
1268 uint8_t entry_type; /* Entry type. */
1269 uint8_t entry_count; /* Entry count. */
1270 uint8_t sys_define; /* System defined. */
1271 uint8_t entry_status; /* Entry Status. */
1272 uint32_t handle; /* System handle. */
1273 uint16_t scsi_status; /* SCSI status. */
1274 uint16_t comp_status; /* Completion status. */
1275 uint16_t state_flags; /* State flags. */
1276 uint16_t status_flags; /* Status flags. */
1277 uint16_t rsp_info_len; /* Response Info Length. */
1278 uint16_t req_sense_length; /* Request sense data length. */
1279 uint32_t residual_length; /* Residual transfer length. */
1280 uint8_t rsp_info[8]; /* FCP response information. */
1281 uint8_t req_sense_data[32]; /* Request sense data. */
1282} sts_entry_t;
1283
1284/*
1285 * Status entry entry status
1286 */
1287#define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
1288#define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
1289#define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
1290#define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
1291#define RF_BUSY BIT_1 /* Busy */
1292
1293/*
1294 * Status entry SCSI status bit definitions.
1295 */
1296#define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
1297#define SS_RESIDUAL_UNDER BIT_11
1298#define SS_RESIDUAL_OVER BIT_10
1299#define SS_SENSE_LEN_VALID BIT_9
1300#define SS_RESPONSE_INFO_LEN_VALID BIT_8
1301
1302#define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
1303#define SS_BUSY_CONDITION BIT_3
1304#define SS_CONDITION_MET BIT_2
1305#define SS_CHECK_CONDITION BIT_1
1306
1307/*
1308 * Status entry completion status
1309 */
1310#define CS_COMPLETE 0x0 /* No errors */
1311#define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
1312#define CS_DMA 0x2 /* A DMA direction error. */
1313#define CS_TRANSPORT 0x3 /* Transport error. */
1314#define CS_RESET 0x4 /* SCSI bus reset occurred */
1315#define CS_ABORTED 0x5 /* System aborted command. */
1316#define CS_TIMEOUT 0x6 /* Timeout error. */
1317#define CS_DATA_OVERRUN 0x7 /* Data overrun. */
1318
1319#define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
1320#define CS_QUEUE_FULL 0x1C /* Queue Full. */
1321#define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
1322 /* (selection timeout) */
1323#define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
1324#define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
1325#define CS_PORT_BUSY 0x2B /* Port Busy */
1326#define CS_COMPLETE_CHKCOND 0x30 /* Error? */
1327#define CS_BAD_PAYLOAD 0x80 /* Driver defined */
1328#define CS_UNKNOWN 0x81 /* Driver defined */
1329#define CS_RETRY 0x82 /* Driver defined */
1330#define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
1331
1332/*
1333 * Status entry status flags
1334 */
1335#define SF_ABTS_TERMINATED BIT_10
1336#define SF_LOGOUT_SENT BIT_13
1337
1338/*
1339 * ISP queue - status continuation entry structure definition.
1340 */
1341#define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
1342typedef struct {
1343 uint8_t entry_type; /* Entry type. */
1344 uint8_t entry_count; /* Entry count. */
1345 uint8_t sys_define; /* System defined. */
1346 uint8_t entry_status; /* Entry Status. */
1347 uint8_t data[60]; /* data */
1348} sts_cont_entry_t;
1349
1350/*
1351 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
1352 * structure definition.
1353 */
1354#define STATUS_TYPE_21 0x21 /* Status entry. */
1355typedef struct {
1356 uint8_t entry_type; /* Entry type. */
1357 uint8_t entry_count; /* Entry count. */
1358 uint8_t handle_count; /* Handle count. */
1359 uint8_t entry_status; /* Entry Status. */
1360 uint32_t handle[15]; /* System handles. */
1361} sts21_entry_t;
1362
1363/*
1364 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
1365 * structure definition.
1366 */
1367#define STATUS_TYPE_22 0x22 /* Status entry. */
1368typedef struct {
1369 uint8_t entry_type; /* Entry type. */
1370 uint8_t entry_count; /* Entry count. */
1371 uint8_t handle_count; /* Handle count. */
1372 uint8_t entry_status; /* Entry Status. */
1373 uint16_t handle[30]; /* System handles. */
1374} sts22_entry_t;
1375
1376/*
1377 * ISP queue - marker entry structure definition.
1378 */
1379#define MARKER_TYPE 0x04 /* Marker entry. */
1380typedef struct {
1381 uint8_t entry_type; /* Entry type. */
1382 uint8_t entry_count; /* Entry count. */
1383 uint8_t handle_count; /* Handle count. */
1384 uint8_t entry_status; /* Entry Status. */
1385 uint32_t sys_define_2; /* System defined. */
1386 target_id_t target; /* SCSI ID */
1387 uint8_t modifier; /* Modifier (7-0). */
1388#define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
1389#define MK_SYNC_ID 1 /* Synchronize ID */
1390#define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
1391#define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
1392 /* clear port changed, */
1393 /* use sequence number. */
1394 uint8_t reserved_1;
1395 uint16_t sequence_number; /* Sequence number of event */
1396 uint16_t lun; /* SCSI LUN */
1397 uint8_t reserved_2[48];
1398} mrk_entry_t;
1399
1400/*
1401 * ISP queue - Management Server entry structure definition.
1402 */
1403#define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
1404typedef struct {
1405 uint8_t entry_type; /* Entry type. */
1406 uint8_t entry_count; /* Entry count. */
1407 uint8_t handle_count; /* Handle count. */
1408 uint8_t entry_status; /* Entry Status. */
1409 uint32_t handle1; /* System handle. */
1410 target_id_t loop_id;
1411 uint16_t status;
1412 uint16_t control_flags; /* Control flags. */
1413 uint16_t reserved2;
1414 uint16_t timeout;
1415 uint16_t cmd_dsd_count;
1416 uint16_t total_dsd_count;
1417 uint8_t type;
1418 uint8_t r_ctl;
1419 uint16_t rx_id;
1420 uint16_t reserved3;
1421 uint32_t handle2;
1422 uint32_t rsp_bytecount;
1423 uint32_t req_bytecount;
1424 uint32_t dseg_req_address[2]; /* Data segment 0 address. */
1425 uint32_t dseg_req_length; /* Data segment 0 length. */
1426 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */
1427 uint32_t dseg_rsp_length; /* Data segment 1 length. */
1428} ms_iocb_entry_t;
1429
1430
1431/*
1432 * ISP queue - Mailbox Command entry structure definition.
1433 */
1434#define MBX_IOCB_TYPE 0x39
1435struct mbx_entry {
1436 uint8_t entry_type;
1437 uint8_t entry_count;
1438 uint8_t sys_define1;
1439 /* Use sys_define1 for source type */
1440#define SOURCE_SCSI 0x00
1441#define SOURCE_IP 0x01
1442#define SOURCE_VI 0x02
1443#define SOURCE_SCTP 0x03
1444#define SOURCE_MP 0x04
1445#define SOURCE_MPIOCTL 0x05
1446#define SOURCE_ASYNC_IOCB 0x07
1447
1448 uint8_t entry_status;
1449
1450 uint32_t handle;
1451 target_id_t loop_id;
1452
1453 uint16_t status;
1454 uint16_t state_flags;
1455 uint16_t status_flags;
1456
1457 uint32_t sys_define2[2];
1458
1459 uint16_t mb0;
1460 uint16_t mb1;
1461 uint16_t mb2;
1462 uint16_t mb3;
1463 uint16_t mb6;
1464 uint16_t mb7;
1465 uint16_t mb9;
1466 uint16_t mb10;
1467 uint32_t reserved_2[2];
1468 uint8_t node_name[WWN_SIZE];
1469 uint8_t port_name[WWN_SIZE];
1470};
1471
1472/*
1473 * ISP request and response queue entry sizes
1474 */
1475#define RESPONSE_ENTRY_SIZE (sizeof(response_t))
1476#define REQUEST_ENTRY_SIZE (sizeof(request_t))
1477
1478
1479/*
1480 * 24 bit port ID type definition.
1481 */
1482typedef union {
1483 uint32_t b24 : 24;
1484
1485 struct {
1486 uint8_t d_id[3];
1487 uint8_t rsvd_1;
1488 } r;
1489
1490 struct {
1491 uint8_t al_pa;
1492 uint8_t area;
1493 uint8_t domain;
1494 uint8_t rsvd_1;
1495 } b;
1496} port_id_t;
1497#define INVALID_PORT_ID 0xFFFFFF
1498
1499/*
1500 * Switch info gathering structure.
1501 */
1502typedef struct {
1503 port_id_t d_id;
1504 uint8_t node_name[WWN_SIZE];
1505 uint8_t port_name[WWN_SIZE];
1506 uint32_t type;
1507#define SW_TYPE_IP BIT_1
1508#define SW_TYPE_SCSI BIT_0
1509} sw_info_t;
1510
1511/*
1512 * Inquiry command structure.
1513 */
1514#define INQ_DATA_SIZE 36
1515
1516/*
1517 * Inquiry mailbox IOCB packet definition.
1518 */
1519typedef struct {
1520 union {
1521 cmd_a64_entry_t cmd;
1522 sts_entry_t rsp;
1523 } p;
1524 uint8_t inq[INQ_DATA_SIZE];
1525} inq_cmd_rsp_t;
1526
1527/*
1528 * Report LUN command structure.
1529 */
1530#define CHAR_TO_SHORT(a, b) (uint16_t)((uint8_t)b << 8 | (uint8_t)a)
1531
1532typedef struct {
1533 uint32_t len;
1534 uint32_t rsrv;
1535} rpt_hdr_t;
1536
1537typedef struct {
1538 struct {
1539 uint8_t b : 6;
1540 uint8_t address_method : 2;
1541 } msb;
1542 uint8_t lsb;
1543 uint8_t unused[6];
1544} rpt_lun_t;
1545
1546typedef struct {
1547 rpt_hdr_t hdr;
1548 rpt_lun_t lst[MAX_LUNS];
1549} rpt_lun_lst_t;
1550
1551/*
1552 * Report Lun mailbox IOCB packet definition.
1553 */
1554typedef struct {
1555 union {
1556 cmd_a64_entry_t cmd;
1557 sts_entry_t rsp;
1558 } p;
1559 rpt_lun_lst_t list;
1560} rpt_lun_cmd_rsp_t;
1561
1da177e4
LT		 1562/*
1563 * Fibre channel port type.
1564 */
1565 typedef enum {
1566 FCT_UNKNOWN,
1567 FCT_RSCN,
1568 FCT_SWITCH,
1569 FCT_BROADCAST,
1570 FCT_INITIATOR,
1571 FCT_TARGET
1572} fc_port_type_t;
1573
1574/*
1575 * Fibre channel port structure.
1576 */
1577typedef struct fc_port {
1578 struct list_head list;
1da177e4
LT		 1579 struct scsi_qla_host *ha;
1580 struct scsi_qla_host *vis_ha; /* only used when suspending lun */
1581
1582 uint8_t node_name[WWN_SIZE];
1583 uint8_t port_name[WWN_SIZE];
1584 port_id_t d_id;
1585 uint16_t loop_id;
1586 uint16_t old_loop_id;
1587
1588 fc_port_type_t port_type;
1589
1590 atomic_t state;
1591 uint32_t flags;
1592
bdf79621 1593 unsigned int os_target_id;
1da177e4
LT		 1594
1595 uint16_t iodesc_idx_sent;
1596
1597 int port_login_retry_count;
1598 int login_retry;
1599 atomic_t port_down_timer;
1600
1601 uint8_t device_type;
1602 uint8_t unused;
1603
1604 uint8_t mp_byte; /* multi-path byte (not used) */
1605 uint8_t cur_path; /* current path id */
1606
8482e118 1607 struct fc_rport *rport;
1da177e4
LT		 1608} fc_port_t;
1609
1610/*
1611 * Fibre channel port/lun states.
1612 */
1613#define FCS_UNCONFIGURED 1
1614#define FCS_DEVICE_DEAD 2
1615#define FCS_DEVICE_LOST 3
1616#define FCS_ONLINE 4
1617#define FCS_NOT_SUPPORTED 5
1618#define FCS_FAILOVER 6
1619#define FCS_FAILOVER_FAILED 7
1620
1621/*
1622 * FC port flags.
1623 */
1624#define FCF_FABRIC_DEVICE BIT_0
1625#define FCF_LOGIN_NEEDED BIT_1
1626#define FCF_FO_MASKED BIT_2
1627#define FCF_FAILOVER_NEEDED BIT_3
1628#define FCF_RESET_NEEDED BIT_4
1629#define FCF_PERSISTENT_BOUND BIT_5
1630#define FCF_TAPE_PRESENT BIT_6
1631#define FCF_FARP_DONE BIT_7
1632#define FCF_FARP_FAILED BIT_8
1633#define FCF_FARP_REPLY_NEEDED BIT_9
1634#define FCF_AUTH_REQ BIT_10
1635#define FCF_SEND_AUTH_REQ BIT_11
1636#define FCF_RECEIVE_AUTH_REQ BIT_12
1637#define FCF_AUTH_SUCCESS BIT_13
1638#define FCF_RLC_SUPPORT BIT_14
1639#define FCF_CONFIG BIT_15 /* Needed? */
1640#define FCF_RESCAN_NEEDED BIT_16
1641#define FCF_XP_DEVICE BIT_17
1642#define FCF_MSA_DEVICE BIT_18
1643#define FCF_EVA_DEVICE BIT_19
1644#define FCF_MSA_PORT_ACTIVE BIT_20
1645#define FCF_FAILBACK_DISABLE BIT_21
1646#define FCF_FAILOVER_DISABLE BIT_22
1647#define FCF_DSXXX_DEVICE BIT_23
1648#define FCF_AA_EVA_DEVICE BIT_24
1649
1650/* No loop ID flag. */
1651#define FC_NO_LOOP_ID 0x1000
1652
1da177e4
LT		 1653/*
1654 * FC-CT interface
1655 *
1656 * NOTE: All structures are big-endian in form.
1657 */
1658
1659#define CT_REJECT_RESPONSE 0x8001
1660#define CT_ACCEPT_RESPONSE 0x8002
1661
1662#define NS_N_PORT_TYPE 0x01
1663#define NS_NL_PORT_TYPE 0x02
1664#define NS_NX_PORT_TYPE 0x7F
1665
1666#define GA_NXT_CMD 0x100
1667#define GA_NXT_REQ_SIZE (16 + 4)
1668#define GA_NXT_RSP_SIZE (16 + 620)
1669
1670#define GID_PT_CMD 0x1A1
1671#define GID_PT_REQ_SIZE (16 + 4)
1672#define GID_PT_RSP_SIZE (16 + (MAX_FIBRE_DEVICES * 4))
1673
1674#define GPN_ID_CMD 0x112
1675#define GPN_ID_REQ_SIZE (16 + 4)
1676#define GPN_ID_RSP_SIZE (16 + 8)
1677
1678#define GNN_ID_CMD 0x113
1679#define GNN_ID_REQ_SIZE (16 + 4)
1680#define GNN_ID_RSP_SIZE (16 + 8)
1681
1682#define GFT_ID_CMD 0x117
1683#define GFT_ID_REQ_SIZE (16 + 4)
1684#define GFT_ID_RSP_SIZE (16 + 32)
1685
1686#define RFT_ID_CMD 0x217
1687#define RFT_ID_REQ_SIZE (16 + 4 + 32)
1688#define RFT_ID_RSP_SIZE 16
1689
1690#define RFF_ID_CMD 0x21F
1691#define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
1692#define RFF_ID_RSP_SIZE 16
1693
1694#define RNN_ID_CMD 0x213
1695#define RNN_ID_REQ_SIZE (16 + 4 + 8)
1696#define RNN_ID_RSP_SIZE 16
1697
1698#define RSNN_NN_CMD 0x239
1699#define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
1700#define RSNN_NN_RSP_SIZE 16
1701
1702/* CT command header -- request/response common fields */
1703struct ct_cmd_hdr {
1704 uint8_t revision;
1705 uint8_t in_id[3];
1706 uint8_t gs_type;
1707 uint8_t gs_subtype;
1708 uint8_t options;
1709 uint8_t reserved;
1710};
1711
1712/* CT command request */
1713struct ct_sns_req {
1714 struct ct_cmd_hdr header;
1715 uint16_t command;
1716 uint16_t max_rsp_size;
1717 uint8_t fragment_id;
1718 uint8_t reserved[3];
1719
1720 union {
1721 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID */
1722 struct {
1723 uint8_t reserved;
1724 uint8_t port_id[3];
1725 } port_id;
1726
1727 struct {
1728 uint8_t port_type;
1729 uint8_t domain;
1730 uint8_t area;
1731 uint8_t reserved;
1732 } gid_pt;
1733
1734 struct {
1735 uint8_t reserved;
1736 uint8_t port_id[3];
1737 uint8_t fc4_types[32];
1738 } rft_id;
1739
1740 struct {
1741 uint8_t reserved;
1742 uint8_t port_id[3];
1743 uint16_t reserved2;
1744 uint8_t fc4_feature;
1745 uint8_t fc4_type;
1746 } rff_id;
1747
1748 struct {
1749 uint8_t reserved;
1750 uint8_t port_id[3];
1751 uint8_t node_name[8];
1752 } rnn_id;
1753
1754 struct {
1755 uint8_t node_name[8];
1756 uint8_t name_len;
1757 uint8_t sym_node_name[255];
1758 } rsnn_nn;
1759 } req;
1760};
1761
1762/* CT command response header */
1763struct ct_rsp_hdr {
1764 struct ct_cmd_hdr header;
1765 uint16_t response;
1766 uint16_t residual;
1767 uint8_t fragment_id;
1768 uint8_t reason_code;
1769 uint8_t explanation_code;
1770 uint8_t vendor_unique;
1771};
1772
1773struct ct_sns_gid_pt_data {
1774 uint8_t control_byte;
1775 uint8_t port_id[3];
1776};
1777
1778struct ct_sns_rsp {
1779 struct ct_rsp_hdr header;
1780
1781 union {
1782 struct {
1783 uint8_t port_type;
1784 uint8_t port_id[3];
1785 uint8_t port_name[8];
1786 uint8_t sym_port_name_len;
1787 uint8_t sym_port_name[255];
1788 uint8_t node_name[8];
1789 uint8_t sym_node_name_len;
1790 uint8_t sym_node_name[255];
1791 uint8_t init_proc_assoc[8];
1792 uint8_t node_ip_addr[16];
1793 uint8_t class_of_service[4];
1794 uint8_t fc4_types[32];
1795 uint8_t ip_address[16];
1796 uint8_t fabric_port_name[8];
1797 uint8_t reserved;
1798 uint8_t hard_address[3];
1799 } ga_nxt;
1800
1801 struct {
1802 struct ct_sns_gid_pt_data entries[MAX_FIBRE_DEVICES];
1803 } gid_pt;
1804
1805 struct {
1806 uint8_t port_name[8];
1807 } gpn_id;
1808
1809 struct {
1810 uint8_t node_name[8];
1811 } gnn_id;
1812
1813 struct {
1814 uint8_t fc4_types[32];
1815 } gft_id;
1816 } rsp;
1817};
1818
1819struct ct_sns_pkt {
1820 union {
1821 struct ct_sns_req req;
1822 struct ct_sns_rsp rsp;
1823 } p;
1824};
1825
1826/*
1827 * SNS command structures -- for 2200 compatability.
1828 */
1829#define RFT_ID_SNS_SCMD_LEN 22
1830#define RFT_ID_SNS_CMD_SIZE 60
1831#define RFT_ID_SNS_DATA_SIZE 16
1832
1833#define RNN_ID_SNS_SCMD_LEN 10
1834#define RNN_ID_SNS_CMD_SIZE 36
1835#define RNN_ID_SNS_DATA_SIZE 16
1836
1837#define GA_NXT_SNS_SCMD_LEN 6
1838#define GA_NXT_SNS_CMD_SIZE 28
1839#define GA_NXT_SNS_DATA_SIZE (620 + 16)
1840
1841#define GID_PT_SNS_SCMD_LEN 6
1842#define GID_PT_SNS_CMD_SIZE 28
1843#define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES * 4 + 16)
1844
1845#define GPN_ID_SNS_SCMD_LEN 6
1846#define GPN_ID_SNS_CMD_SIZE 28
1847#define GPN_ID_SNS_DATA_SIZE (8 + 16)
1848
1849#define GNN_ID_SNS_SCMD_LEN 6
1850#define GNN_ID_SNS_CMD_SIZE 28
1851#define GNN_ID_SNS_DATA_SIZE (8 + 16)
1852
1853struct sns_cmd_pkt {
1854 union {
1855 struct {
1856 uint16_t buffer_length;
1857 uint16_t reserved_1;
1858 uint32_t buffer_address[2];
1859 uint16_t subcommand_length;
1860 uint16_t reserved_2;
1861 uint16_t subcommand;
1862 uint16_t size;
1863 uint32_t reserved_3;
1864 uint8_t param[36];
1865 } cmd;
1866
1867 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
1868 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
1869 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
1870 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
1871 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
1872 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
1873 } p;
1874};
1875
1876/* IO descriptors */
1877#define MAX_IO_DESCRIPTORS 32
1878
1879#define ABORT_IOCB_CB 0
1880#define ADISC_PORT_IOCB_CB 1
1881#define LOGOUT_PORT_IOCB_CB 2
1882#define LOGIN_PORT_IOCB_CB 3
1883#define LAST_IOCB_CB 4
1884
1885#define IODESC_INVALID_INDEX 0xFFFF
1886#define IODESC_ADISC_NEEDED 0xFFFE
1887#define IODESC_LOGIN_NEEDED 0xFFFD
1888
1889struct io_descriptor {
1890 uint16_t used:1;
1891 uint16_t idx:11;
1892 uint16_t cb_idx:4;
1893
1894 struct timer_list timer;
1895
1896 struct scsi_qla_host *ha;
1897
1898 port_id_t d_id;
1899 fc_port_t *remote_fcport;
1900
1901 uint32_t signature;
1902};
1903
1904struct qla_fw_info {
1905 unsigned short addressing; /* addressing method used to load fw */
1906#define FW_INFO_ADDR_NORMAL 0
1907#define FW_INFO_ADDR_EXTENDED 1
1908#define FW_INFO_ADDR_NOMORE 0xffff
1909 unsigned short *fwcode; /* pointer to FW array */
1910 unsigned short *fwlen; /* number of words in array */
1911 unsigned short *fwstart; /* start address for F/W */
1912 unsigned long *lfwstart; /* start address (long) for F/W */
1913};
1914
1915struct qla_board_info {
1916 char *drv_name;
1917
1918 char isp_name[8];
1919 struct qla_fw_info *fw_info;
1920};
1921
1922/* Return data from MBC_GET_ID_LIST call. */
1923struct gid_list_info {
1924 uint8_t al_pa;
1925 uint8_t area;
1926 uint8_t domain;
1927 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
1928 uint16_t loop_id; /* ISP23XX -- 6 bytes. */
1929};
1930#define GID_LIST_SIZE (sizeof(struct gid_list_info) * MAX_FIBRE_DEVICES)
1931
abbd8870
AV		 1932/*
1933 * ISP operations
1934 */
1935struct isp_operations {
1936
1937 int (*pci_config) (struct scsi_qla_host *);
1938 void (*reset_chip) (struct scsi_qla_host *);
1939 int (*chip_diag) (struct scsi_qla_host *);
1940 void (*config_rings) (struct scsi_qla_host *);
1941 void (*reset_adapter) (struct scsi_qla_host *);
1942 int (*nvram_config) (struct scsi_qla_host *);
1943 void (*update_fw_options) (struct scsi_qla_host *);
1944 int (*load_risc) (struct scsi_qla_host *, uint32_t *);
1945
1946 char * (*pci_info_str) (struct scsi_qla_host *, char *);
1947 char * (*fw_version_str) (struct scsi_qla_host *, char *);
1948
1949 irqreturn_t (*intr_handler) (int, void *, struct pt_regs *);
1950 void (*enable_intrs) (struct scsi_qla_host *);
1951 void (*disable_intrs) (struct scsi_qla_host *);
1952
1953 int (*abort_command) (struct scsi_qla_host *, srb_t *);
1954 int (*abort_target) (struct fc_port *);
1955 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
1956 uint8_t, uint8_t, uint16_t *, uint8_t);
1957 int (*fabric_logout) (struct scsi_qla_host *, uint16_t);
1958
1959 uint16_t (*calc_req_entries) (uint16_t);
1960 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
1961 ms_iocb_entry_t * (*prep_ms_iocb) (struct scsi_qla_host *, uint32_t,
1962 uint32_t);
1963
1964 uint8_t * (*read_nvram) (struct scsi_qla_host *, uint8_t *,
1965 uint32_t, uint32_t);
1966 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t,
1967 uint32_t);
1968
1969 void (*fw_dump) (struct scsi_qla_host *, int);
1970 void (*ascii_fw_dump) (struct scsi_qla_host *);
1971};
1972
1da177e4
LT		 1973/*
1974 * Linux Host Adapter structure
1975 */
1976typedef struct scsi_qla_host {
1977 struct list_head list;
1978
1979 /* Commonly used flags and state information. */
1980 struct Scsi_Host *host;
1981 struct pci_dev *pdev;
1982
1983 unsigned long host_no;
1984 unsigned long instance;
1985
1986 volatile struct {
1987 uint32_t init_done :1;
1988 uint32_t online :1;
1989 uint32_t mbox_int :1;
1990 uint32_t mbox_busy :1;
1991 uint32_t rscn_queue_overflow :1;
1992 uint32_t reset_active :1;
1993
1994 uint32_t management_server_logged_in :1;
1995 uint32_t process_response_queue :1;
1996
1997 uint32_t disable_risc_code_load :1;
1998 uint32_t enable_64bit_addressing :1;
1999 uint32_t enable_lip_reset :1;
2000 uint32_t enable_lip_full_login :1;
2001 uint32_t enable_target_reset :1;
2002 uint32_t enable_led_scheme :1;
2003 } flags;
2004
2005 atomic_t loop_state;
2006#define LOOP_TIMEOUT 1
2007#define LOOP_DOWN 2
2008#define LOOP_UP 3
2009#define LOOP_UPDATE 4
2010#define LOOP_READY 5
2011#define LOOP_DEAD 6
2012
2013 unsigned long dpc_flags;
2014#define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
2015#define RESET_ACTIVE 1
2016#define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
2017#define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
2018#define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
2019#define LOOP_RESYNC_ACTIVE 5
2020#define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
2021#define RSCN_UPDATE 7 /* Perform an RSCN update. */
2022#define MAILBOX_RETRY 8
2023#define ISP_RESET_NEEDED 9 /* Initiate a ISP reset. */
2024#define FAILOVER_EVENT_NEEDED 10
2025#define FAILOVER_EVENT 11
2026#define FAILOVER_NEEDED 12
2027#define SCSI_RESTART_NEEDED 13 /* Processes SCSI retry queue. */
2028#define PORT_RESTART_NEEDED 14 /* Processes Retry queue. */
2029#define RESTART_QUEUES_NEEDED 15 /* Restarts the Lun queue. */
2030#define ABORT_QUEUES_NEEDED 16
2031#define RELOGIN_NEEDED 17
2032#define LOGIN_RETRY_NEEDED 18 /* Initiate required fabric logins. */
2033#define REGISTER_FC4_NEEDED 19 /* SNS FC4 registration required. */
2034#define ISP_ABORT_RETRY 20 /* ISP aborted. */
2035#define FCPORT_RESCAN_NEEDED 21 /* IO descriptor processing needed */
2036#define IODESC_PROCESS_NEEDED 22 /* IO descriptor processing needed */
2037#define IOCTL_ERROR_RECOVERY 23
2038#define LOOP_RESET_NEEDED 24
2039
2040 uint32_t device_flags;
2041#define DFLG_LOCAL_DEVICES BIT_0
2042#define DFLG_RETRY_LOCAL_DEVICES BIT_1
2043#define DFLG_FABRIC_DEVICES BIT_2
2044#define SWITCH_FOUND BIT_3
2045#define DFLG_NO_CABLE BIT_4
2046
2047 /* SRB cache. */
2048#define SRB_MIN_REQ 128
2049 mempool_t *srb_mempool;
2050
2051 /* This spinlock is used to protect "io transactions", you must
2052 * aquire it before doing any IO to the card, eg with RD_REG*() and
2053 * WRT_REG*() for the duration of your entire commandtransaction.
2054 *
2055 * This spinlock is of lower priority than the io request lock.
2056 */
2057
2058 spinlock_t hardware_lock ____cacheline_aligned;
2059
2060 device_reg_t __iomem *iobase; /* Base I/O address */
2061 unsigned long pio_address;
2062 unsigned long pio_length;
2063#define MIN_IOBASE_LEN 0x100
2064
2065 /* ISP ring lock, rings, and indexes */
2066 dma_addr_t request_dma; /* Physical address. */
2067 request_t *request_ring; /* Base virtual address */
2068 request_t *request_ring_ptr; /* Current address. */
2069 uint16_t req_ring_index; /* Current index. */
2070 uint16_t req_q_cnt; /* Number of available entries. */
2071 uint16_t request_q_length;
2072
2073 dma_addr_t response_dma; /* Physical address. */
2074 response_t *response_ring; /* Base virtual address */
2075 response_t *response_ring_ptr; /* Current address. */
2076 uint16_t rsp_ring_index; /* Current index. */
2077 uint16_t response_q_length;
2078
abbd8870 2079 struct isp_operations isp_ops;
1da177e4
LT		 2080
2081 /* Outstandings ISP commands. */
2082 srb_t *outstanding_cmds[MAX_OUTSTANDING_COMMANDS];
2083 uint32_t current_outstanding_cmd;
2084 srb_t *status_srb; /* Status continuation entry. */
2085
1da177e4
LT		 2086 uint16_t revision;
2087 uint8_t ports;
1da177e4
LT		 2088
2089 /* ISP configuration data. */
2090 uint16_t loop_id; /* Host adapter loop id */
2091 uint16_t fb_rev;
2092
2093 port_id_t d_id; /* Host adapter port id */
2094 uint16_t max_public_loop_ids;
2095 uint16_t min_external_loopid; /* First external loop Id */
2096
2097 uint16_t link_data_rate; /* F/W operating speed */
2098
2099 uint8_t current_topology;
2100 uint8_t prev_topology;
2101#define ISP_CFG_NL 1
2102#define ISP_CFG_N 2
2103#define ISP_CFG_FL 4
2104#define ISP_CFG_F 8
2105
2106 uint8_t operating_mode; /* F/W operating mode */
2107#define LOOP 0
2108#define P2P 1
2109#define LOOP_P2P 2
2110#define P2P_LOOP 3
2111
2112 uint8_t marker_needed;
1da177e4
LT		 2113
2114 uint8_t interrupts_on;
2115
2116 /* HBA serial number */
2117 uint8_t serial0;
2118 uint8_t serial1;
2119 uint8_t serial2;
2120
2121 /* NVRAM configuration data */
2122 uint16_t nvram_base;
2123
2124 uint16_t loop_reset_delay;
1da177e4
LT		 2125 uint8_t retry_count;
2126 uint8_t login_timeout;
2127 uint16_t r_a_tov;
2128 int port_down_retry_count;
1da177e4 2129 uint8_t mbx_count;
1da177e4
LT		 2130 uint16_t last_loop_id;
2131
2132 uint32_t login_retry_count;
2133
2134 /* Fibre Channel Device List. */
2135 struct list_head fcports;
2136 struct list_head rscn_fcports;
2137
2138 struct io_descriptor io_descriptors[MAX_IO_DESCRIPTORS];
2139 uint16_t iodesc_signature;
2140
1da177e4
LT		 2141 /* RSCN queue. */
2142 uint32_t rscn_queue[MAX_RSCN_COUNT];
2143 uint8_t rscn_in_ptr;
2144 uint8_t rscn_out_ptr;
2145
2146 /* SNS command interfaces. */
2147 ms_iocb_entry_t *ms_iocb;
2148 dma_addr_t ms_iocb_dma;
2149 struct ct_sns_pkt *ct_sns;
2150 dma_addr_t ct_sns_dma;
2151 /* SNS command interfaces for 2200. */
2152 struct sns_cmd_pkt *sns_cmd;
2153 dma_addr_t sns_cmd_dma;
2154
2155 pid_t dpc_pid;
2156 int dpc_should_die;
2157 struct completion dpc_inited;
2158 struct completion dpc_exited;
2159 struct semaphore *dpc_wait;
2160 uint8_t dpc_active; /* DPC routine is active */
2161
2162 /* Timeout timers. */
1da177e4
LT		 2163 uint8_t loop_down_abort_time; /* port down timer */
2164 atomic_t loop_down_timer; /* loop down timer */
2165 uint8_t link_down_timeout; /* link down timeout */
2166
2167 uint32_t timer_active;
2168 struct timer_list timer;
2169
2170 dma_addr_t gid_list_dma;
2171 struct gid_list_info *gid_list;
abbd8870 2172 int gid_list_info_size;
1da177e4
LT		 2173
2174 dma_addr_t rlc_rsp_dma;
2175 rpt_lun_cmd_rsp_t *rlc_rsp;
2176
2177 /* Small DMA pool allocations -- maximum 256 bytes in length. */
2178#define DMA_POOL_SIZE 256
2179 struct dma_pool *s_dma_pool;
2180
2181 dma_addr_t init_cb_dma;
2182 init_cb_t *init_cb;
2183
2184 dma_addr_t iodesc_pd_dma;
2185 port_database_t *iodesc_pd;
2186
2187 /* These are used by mailbox operations. */
2188 volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
2189
2190 mbx_cmd_t *mcp;
2191 unsigned long mbx_cmd_flags;
2192#define MBX_INTERRUPT 1
2193#define MBX_INTR_WAIT 2
2194#define MBX_UPDATE_FLASH_ACTIVE 3
2195
2196 spinlock_t mbx_reg_lock; /* Mbx Cmd Register Lock */
2197
2198 struct semaphore mbx_cmd_sem; /* Serialialize mbx access */
2199 struct semaphore mbx_intr_sem; /* Used for completion notification */
2200
2201 uint32_t mbx_flags;
2202#define MBX_IN_PROGRESS BIT_0
2203#define MBX_BUSY BIT_1 /* Got the Access */
2204#define MBX_SLEEPING_ON_SEM BIT_2
2205#define MBX_POLLING_FOR_COMP BIT_3
2206#define MBX_COMPLETED BIT_4
2207#define MBX_TIMEDOUT BIT_5
2208#define MBX_ACCESS_TIMEDOUT BIT_6
2209
2210 mbx_cmd_t mc;
2211
1da177e4
LT		 2212 /* Basic firmware related information. */
2213 struct qla_board_info *brd_info;
2214 uint16_t fw_major_version;
2215 uint16_t fw_minor_version;
2216 uint16_t fw_subminor_version;
2217 uint16_t fw_attributes;
2218 uint32_t fw_memory_size;
2219 uint32_t fw_transfer_size;
2220
2221 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
2222 uint8_t fw_seriallink_options[4];
2223
2224 /* Firmware dump information. */
2225 void *fw_dump;
2226 int fw_dump_order;
2227 int fw_dump_reading;
2228 char *fw_dump_buffer;
2229 int fw_dump_buffer_len;
2230
2231 uint8_t host_str[16];
2232 uint16_t pci_attr;
2233
2234 uint16_t product_id[4];
2235
2236 uint8_t model_number[16+1];
2237#define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
2238 char *model_desc;
2239
2240 uint8_t node_name[WWN_SIZE];
2241 uint8_t nvram_version;
2242 uint32_t isp_abort_cnt;
2243
1da177e4
LT		 2244 /* Needed for BEACON */
2245 uint16_t beacon_blink_led;
2246 uint16_t beacon_green_on;
2247} scsi_qla_host_t;
2248
2249
2250/*
2251 * Macros to help code, maintain, etc.
2252 */
2253#define LOOP_TRANSITION(ha) \
2254 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
2255 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags))
2256
2257#define LOOP_NOT_READY(ha) \
2258 ((test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
2259 test_bit(ABORT_ISP_ACTIVE, &ha->dpc_flags) || \
2260 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
2261 test_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) || \
2262 atomic_read(&ha->loop_state) == LOOP_DOWN)
2263
2264#define LOOP_RDY(ha) (!LOOP_NOT_READY(ha))
2265
2266#define TGT_Q(ha, t) (ha->otgt[t])
1da177e4
LT		 2267
2268#define to_qla_host(x) ((scsi_qla_host_t *) (x)->hostdata)
2269
2270#define qla_printk(level, ha, format, arg...) \
2271 dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
2272
2273/*
2274 * qla2x00 local function return status codes
2275 */
2276#define MBS_MASK 0x3fff
2277
2278#define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
2279#define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
2280#define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
2281#define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
2282#define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
2283#define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
2284#define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
2285#define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
2286#define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
2287#define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
2288
2289#define QLA_FUNCTION_TIMEOUT 0x100
2290#define QLA_FUNCTION_PARAMETER_ERROR 0x101
2291#define QLA_FUNCTION_FAILED 0x102
2292#define QLA_MEMORY_ALLOC_FAILED 0x103
2293#define QLA_LOCK_TIMEOUT 0x104
2294#define QLA_ABORTED 0x105
2295#define QLA_SUSPENDED 0x106
2296#define QLA_BUSY 0x107
2297#define QLA_RSCNS_HANDLED 0x108
2298
2299/*
2300* Stat info for all adpaters
2301*/
2302struct _qla2x00stats {
2303 unsigned long mboxtout; /* mailbox timeouts */
2304 unsigned long mboxerr; /* mailbox errors */
2305 unsigned long ispAbort; /* ISP aborts */
2306 unsigned long debugNo;
2307 unsigned long loop_resync;
2308 unsigned long outarray_full;
2309 unsigned long retry_q_cnt;
2310};
2311
2312#define NVRAM_DELAY() udelay(10)
2313
2314#define INVALID_HANDLE (MAX_OUTSTANDING_COMMANDS+1)
2315
2316/*
2317 * Flash support definitions
2318 */
2319#define FLASH_IMAGE_SIZE 131072
2320
2321#include "qla_gbl.h"
2322#include "qla_dbg.h"
2323#include "qla_inline.h"
1da177e4
LT		 2324
2325/*
2326* String arrays
2327*/
2328#define LINESIZE 256
2329#define MAXARGS 26
2330
2331#define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
2332#define CMD_COMPL_STATUS(Cmnd) ((Cmnd)->SCp.this_residual)
2333#define CMD_RESID_LEN(Cmnd) ((Cmnd)->SCp.buffers_residual)
2334#define CMD_SCSI_STATUS(Cmnd) ((Cmnd)->SCp.Status)
2335#define CMD_ACTUAL_SNSLEN(Cmnd) ((Cmnd)->SCp.Message)
2336#define CMD_ENTRY_STATUS(Cmnd) ((Cmnd)->SCp.have_data_in)
2337
2338#endif
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