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[SCSI] qla2xxx: Perform implicit logout during rport tear-down.
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / qla2xxx / qla_def.h
CommitLineData
fa90c54f
AV
1/*
2 * QLogic Fibre Channel HBA Driver
07e264b7 3 * Copyright (c) 2003-2011 QLogic Corporation
fa90c54f
AV
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
1da177e4
LT
7#ifndef __QLA_DEF_H
8#define __QLA_DEF_H
9
10#include <linux/kernel.h>
11#include <linux/init.h>
12#include <linux/types.h>
13#include <linux/module.h>
14#include <linux/list.h>
15#include <linux/pci.h>
16#include <linux/dma-mapping.h>
17#include <linux/sched.h>
18#include <linux/slab.h>
19#include <linux/dmapool.h>
20#include <linux/mempool.h>
21#include <linux/spinlock.h>
22#include <linux/completion.h>
abbd8870 23#include <linux/interrupt.h>
19a7b4ae 24#include <linux/workqueue.h>
5433383e 25#include <linux/firmware.h>
14e660e6 26#include <linux/aer.h>
4d4df193 27#include <linux/mutex.h>
1da177e4
LT
28
29#include <scsi/scsi.h>
30#include <scsi/scsi_host.h>
31#include <scsi/scsi_device.h>
32#include <scsi/scsi_cmnd.h>
392e2f65 33#include <scsi/scsi_transport_fc.h>
9a069e19 34#include <scsi/scsi_bsg_fc.h>
1da177e4 35
6e98016c 36#include "qla_bsg.h"
a9083016 37#include "qla_nx.h"
6a03b4cd
HZ
38#define QLA2XXX_DRIVER_NAME "qla2xxx"
39#define QLA2XXX_APIDEV "ql2xapidev"
cb63067a 40
1da177e4
LT
41/*
42 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
43 * but that's fine as we don't look at the last 24 ones for
44 * ISP2100 HBAs.
45 */
46#define MAILBOX_REGISTER_COUNT_2100 8
67ddda35 47#define MAILBOX_REGISTER_COUNT_2200 24
1da177e4
LT
48#define MAILBOX_REGISTER_COUNT 32
49
50#define QLA2200A_RISC_ROM_VER 4
51#define FPM_2300 6
52#define FPM_2310 7
53
54#include "qla_settings.h"
55
fa2a1ce5 56/*
1da177e4
LT
57 * Data bit definitions
58 */
59#define BIT_0 0x1
60#define BIT_1 0x2
61#define BIT_2 0x4
62#define BIT_3 0x8
63#define BIT_4 0x10
64#define BIT_5 0x20
65#define BIT_6 0x40
66#define BIT_7 0x80
67#define BIT_8 0x100
68#define BIT_9 0x200
69#define BIT_10 0x400
70#define BIT_11 0x800
71#define BIT_12 0x1000
72#define BIT_13 0x2000
73#define BIT_14 0x4000
74#define BIT_15 0x8000
75#define BIT_16 0x10000
76#define BIT_17 0x20000
77#define BIT_18 0x40000
78#define BIT_19 0x80000
79#define BIT_20 0x100000
80#define BIT_21 0x200000
81#define BIT_22 0x400000
82#define BIT_23 0x800000
83#define BIT_24 0x1000000
84#define BIT_25 0x2000000
85#define BIT_26 0x4000000
86#define BIT_27 0x8000000
87#define BIT_28 0x10000000
88#define BIT_29 0x20000000
89#define BIT_30 0x40000000
90#define BIT_31 0x80000000
91
92#define LSB(x) ((uint8_t)(x))
93#define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
94
95#define LSW(x) ((uint16_t)(x))
96#define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
97
98#define LSD(x) ((uint32_t)((uint64_t)(x)))
99#define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
100
2afa19a9 101#define MAKE_HANDLE(x, y) ((uint32_t)((((uint32_t)(x)) << 16) | (uint32_t)(y)))
1da177e4
LT
102
103/*
104 * I/O register
105*/
106
107#define RD_REG_BYTE(addr) readb(addr)
108#define RD_REG_WORD(addr) readw(addr)
109#define RD_REG_DWORD(addr) readl(addr)
110#define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
111#define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
112#define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
113#define WRT_REG_BYTE(addr, data) writeb(data,addr)
114#define WRT_REG_WORD(addr, data) writew(data,addr)
115#define WRT_REG_DWORD(addr, data) writel(data,addr)
116
f6df144c
AV
117/*
118 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an
119 * 133Mhz slot.
120 */
121#define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr))
122#define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr))
123
1da177e4
LT
124/*
125 * Fibre Channel device definitions.
126 */
127#define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
128#define MAX_FIBRE_DEVICES 512
cc4731f5 129#define MAX_FIBRE_LUNS 0xFFFF
1da177e4
LT
130#define MAX_HOST_COUNT 16
131
132/*
133 * Host adapter default definitions.
134 */
135#define MAX_BUSES 1 /* We only have one bus today */
136#define MAX_TARGETS_2100 MAX_FIBRE_DEVICES
137#define MAX_TARGETS_2200 MAX_FIBRE_DEVICES
1da177e4
LT
138#define MIN_LUNS 8
139#define MAX_LUNS MAX_FIBRE_LUNS
fa2a1ce5
AV
140#define MAX_CMDS_PER_LUN 255
141
1da177e4
LT
142/*
143 * Fibre Channel device definitions.
144 */
145#define SNS_LAST_LOOP_ID_2100 0xfe
146#define SNS_LAST_LOOP_ID_2300 0x7ff
147
148#define LAST_LOCAL_LOOP_ID 0x7d
149#define SNS_FL_PORT 0x7e
150#define FABRIC_CONTROLLER 0x7f
151#define SIMPLE_NAME_SERVER 0x80
152#define SNS_FIRST_LOOP_ID 0x81
153#define MANAGEMENT_SERVER 0xfe
154#define BROADCAST 0xff
155
3d71644c
AV
156/*
157 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the
158 * valid range of an N-PORT id is 0 through 0x7ef.
159 */
160#define NPH_LAST_HANDLE 0x7ef
cca5335c 161#define NPH_MGMT_SERVER 0x7fa /* FFFFFA */
3d71644c
AV
162#define NPH_SNS 0x7fc /* FFFFFC */
163#define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */
164#define NPH_F_PORT 0x7fe /* FFFFFE */
165#define NPH_IP_BROADCAST 0x7ff /* FFFFFF */
166
167#define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
168#include "qla_fw.h"
1da177e4
LT
169
170/*
171 * Timeout timer counts in seconds
172 */
8482e118 173#define PORT_RETRY_TIME 1
1da177e4
LT
174#define LOOP_DOWN_TIMEOUT 60
175#define LOOP_DOWN_TIME 255 /* 240 */
176#define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
177
178/* Maximum outstanding commands in ISP queues (1-65535) */
179#define MAX_OUTSTANDING_COMMANDS 1024
180
181/* ISP request and response entry counts (37-65535) */
182#define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
183#define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
d743de66 184#define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */
1da177e4
LT
185#define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
186#define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
2afa19a9 187#define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/
1da177e4 188
17d98630
AC
189struct req_que;
190
bad75002
AE
191/*
192 * (sd.h is not exported, hence local inclusion)
193 * Data Integrity Field tuple.
194 */
195struct sd_dif_tuple {
196 __be16 guard_tag; /* Checksum */
197 __be16 app_tag; /* Opaque storage */
198 __be32 ref_tag; /* Target LBA or indirect LBA */
199};
200
1da177e4 201/*
fa2a1ce5 202 * SCSI Request Block
1da177e4 203 */
9ba56b95 204struct srb_cmd {
1da177e4 205 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */
1da177e4
LT
206 uint32_t request_sense_length;
207 uint8_t *request_sense_ptr;
cf53b069 208 void *ctx;
9ba56b95 209};
1da177e4
LT
210
211/*
212 * SRB flag definitions
213 */
bad75002
AE
214#define SRB_DMA_VALID BIT_0 /* Command sent to ISP */
215#define SRB_FCP_CMND_DMA_VALID BIT_12 /* DIF: DSD List valid */
216#define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */
217#define SRB_CRC_PROT_DMA_VALID BIT_4 /* DIF: prot DMA valid */
218#define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */
219
220/* To identify if a srb is of T10-CRC type. @sp => srb_t pointer */
221#define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID)
1da177e4 222
ac280b67
AV
223/*
224 * SRB extensions.
225 */
4916392b
MI
226struct srb_iocb {
227 union {
228 struct {
229 uint16_t flags;
230#define SRB_LOGIN_RETRIED BIT_0
231#define SRB_LOGIN_COND_PLOGI BIT_1
232#define SRB_LOGIN_SKIP_PRLI BIT_2
233 uint16_t data[2];
234 } logio;
3822263e
MI
235 struct {
236 /*
237 * Values for flags field below are as
238 * defined in tsk_mgmt_entry struct
239 * for control_flags field in qla_fw.h.
240 */
241 uint32_t flags;
242 uint32_t lun;
243 uint32_t data;
244 } tmf;
4916392b 245 } u;
99b0bec7 246
ac280b67 247 struct timer_list timer;
9ba56b95 248 void (*timeout)(void *);
ac280b67
AV
249};
250
4916392b
MI
251/* Values for srb_ctx type */
252#define SRB_LOGIN_CMD 1
253#define SRB_LOGOUT_CMD 2
254#define SRB_ELS_CMD_RPT 3
255#define SRB_ELS_CMD_HST 4
256#define SRB_CT_CMD 5
257#define SRB_ADISC_CMD 6
3822263e 258#define SRB_TM_CMD 7
9ba56b95 259#define SRB_SCSI_CMD 8
ac280b67 260
9ba56b95
GM
261typedef struct srb {
262 atomic_t ref_count;
263 struct fc_port *fcport;
264 uint32_t handle;
265 uint16_t flags;
9a069e19 266 uint16_t type;
4916392b 267 char *name;
5780790e 268 int iocbs;
4916392b 269 union {
9ba56b95 270 struct srb_iocb iocb_cmd;
4916392b 271 struct fc_bsg_job *bsg_job;
9ba56b95 272 struct srb_cmd scmd;
4916392b 273 } u;
9ba56b95
GM
274 void (*done)(void *, void *, int);
275 void (*free)(void *, void *);
276} srb_t;
277
278#define GET_CMD_SP(sp) (sp->u.scmd.cmd)
279#define SET_CMD_SP(sp, cmd) (sp->u.scmd.cmd = cmd)
280#define GET_CMD_CTX_SP(sp) (sp->u.scmd.ctx)
281
282#define GET_CMD_SENSE_LEN(sp) \
283 (sp->u.scmd.request_sense_length)
284#define SET_CMD_SENSE_LEN(sp, len) \
285 (sp->u.scmd.request_sense_length = len)
286#define GET_CMD_SENSE_PTR(sp) \
287 (sp->u.scmd.request_sense_ptr)
288#define SET_CMD_SENSE_PTR(sp, ptr) \
289 (sp->u.scmd.request_sense_ptr = ptr)
9a069e19
GM
290
291struct msg_echo_lb {
292 dma_addr_t send_dma;
293 dma_addr_t rcv_dma;
294 uint16_t req_sg_cnt;
295 uint16_t rsp_sg_cnt;
296 uint16_t options;
297 uint32_t transfer_size;
298};
299
1da177e4
LT
300/*
301 * ISP I/O Register Set structure definitions.
302 */
3d71644c
AV
303struct device_reg_2xxx {
304 uint16_t flash_address; /* Flash BIOS address */
305 uint16_t flash_data; /* Flash BIOS data */
1da177e4 306 uint16_t unused_1[1]; /* Gap */
3d71644c 307 uint16_t ctrl_status; /* Control/Status */
fa2a1ce5 308#define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
1da177e4
LT
309#define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
310#define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
311
3d71644c 312 uint16_t ictrl; /* Interrupt control */
1da177e4
LT
313#define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
314#define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
315
3d71644c 316 uint16_t istatus; /* Interrupt status */
1da177e4
LT
317#define ISR_RISC_INT BIT_3 /* RISC interrupt */
318
3d71644c
AV
319 uint16_t semaphore; /* Semaphore */
320 uint16_t nvram; /* NVRAM register. */
1da177e4
LT
321#define NVR_DESELECT 0
322#define NVR_BUSY BIT_15
323#define NVR_WRT_ENABLE BIT_14 /* Write enable */
324#define NVR_PR_ENABLE BIT_13 /* Protection register enable */
325#define NVR_DATA_IN BIT_3
326#define NVR_DATA_OUT BIT_2
327#define NVR_SELECT BIT_1
328#define NVR_CLOCK BIT_0
329
45aeaf1e
RA
330#define NVR_WAIT_CNT 20000
331
1da177e4
LT
332 union {
333 struct {
3d71644c
AV
334 uint16_t mailbox0;
335 uint16_t mailbox1;
336 uint16_t mailbox2;
337 uint16_t mailbox3;
338 uint16_t mailbox4;
339 uint16_t mailbox5;
340 uint16_t mailbox6;
341 uint16_t mailbox7;
342 uint16_t unused_2[59]; /* Gap */
1da177e4
LT
343 } __attribute__((packed)) isp2100;
344 struct {
3d71644c
AV
345 /* Request Queue */
346 uint16_t req_q_in; /* In-Pointer */
347 uint16_t req_q_out; /* Out-Pointer */
348 /* Response Queue */
349 uint16_t rsp_q_in; /* In-Pointer */
350 uint16_t rsp_q_out; /* Out-Pointer */
1da177e4
LT
351
352 /* RISC to Host Status */
fa2a1ce5 353 uint32_t host_status;
1da177e4
LT
354#define HSR_RISC_INT BIT_15 /* RISC interrupt */
355#define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
356
357 /* Host to Host Semaphore */
fa2a1ce5 358 uint16_t host_semaphore;
3d71644c
AV
359 uint16_t unused_3[17]; /* Gap */
360 uint16_t mailbox0;
361 uint16_t mailbox1;
362 uint16_t mailbox2;
363 uint16_t mailbox3;
364 uint16_t mailbox4;
365 uint16_t mailbox5;
366 uint16_t mailbox6;
367 uint16_t mailbox7;
368 uint16_t mailbox8;
369 uint16_t mailbox9;
370 uint16_t mailbox10;
371 uint16_t mailbox11;
372 uint16_t mailbox12;
373 uint16_t mailbox13;
374 uint16_t mailbox14;
375 uint16_t mailbox15;
376 uint16_t mailbox16;
377 uint16_t mailbox17;
378 uint16_t mailbox18;
379 uint16_t mailbox19;
380 uint16_t mailbox20;
381 uint16_t mailbox21;
382 uint16_t mailbox22;
383 uint16_t mailbox23;
384 uint16_t mailbox24;
385 uint16_t mailbox25;
386 uint16_t mailbox26;
387 uint16_t mailbox27;
388 uint16_t mailbox28;
389 uint16_t mailbox29;
390 uint16_t mailbox30;
391 uint16_t mailbox31;
392 uint16_t fb_cmd;
393 uint16_t unused_4[10]; /* Gap */
1da177e4
LT
394 } __attribute__((packed)) isp2300;
395 } u;
396
3d71644c 397 uint16_t fpm_diag_config;
c81d04c9
AV
398 uint16_t unused_5[0x4]; /* Gap */
399 uint16_t risc_hw;
400 uint16_t unused_5_1; /* Gap */
3d71644c 401 uint16_t pcr; /* Processor Control Register. */
1da177e4 402 uint16_t unused_6[0x5]; /* Gap */
3d71644c 403 uint16_t mctr; /* Memory Configuration and Timing. */
1da177e4 404 uint16_t unused_7[0x3]; /* Gap */
3d71644c 405 uint16_t fb_cmd_2100; /* Unused on 23XX */
1da177e4 406 uint16_t unused_8[0x3]; /* Gap */
3d71644c 407 uint16_t hccr; /* Host command & control register. */
1da177e4
LT
408#define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
409#define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
410 /* HCCR commands */
411#define HCCR_RESET_RISC 0x1000 /* Reset RISC */
412#define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
413#define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
414#define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
415#define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
416#define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
417#define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
418#define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
419
420 uint16_t unused_9[5]; /* Gap */
3d71644c
AV
421 uint16_t gpiod; /* GPIO Data register. */
422 uint16_t gpioe; /* GPIO Enable register. */
1da177e4
LT
423#define GPIO_LED_MASK 0x00C0
424#define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
425#define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
426#define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
427#define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
f6df144c
AV
428#define GPIO_LED_ALL_OFF 0x0000
429#define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */
430#define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */
1da177e4
LT
431
432 union {
433 struct {
3d71644c
AV
434 uint16_t unused_10[8]; /* Gap */
435 uint16_t mailbox8;
436 uint16_t mailbox9;
437 uint16_t mailbox10;
438 uint16_t mailbox11;
439 uint16_t mailbox12;
440 uint16_t mailbox13;
441 uint16_t mailbox14;
442 uint16_t mailbox15;
443 uint16_t mailbox16;
444 uint16_t mailbox17;
445 uint16_t mailbox18;
446 uint16_t mailbox19;
447 uint16_t mailbox20;
448 uint16_t mailbox21;
449 uint16_t mailbox22;
450 uint16_t mailbox23; /* Also probe reg. */
1da177e4
LT
451 } __attribute__((packed)) isp2200;
452 } u_end;
3d71644c
AV
453};
454
73208dfd 455struct device_reg_25xxmq {
08029990
AV
456 uint32_t req_q_in;
457 uint32_t req_q_out;
458 uint32_t rsp_q_in;
459 uint32_t rsp_q_out;
73208dfd
AC
460};
461
9a168bdd 462typedef union {
3d71644c
AV
463 struct device_reg_2xxx isp;
464 struct device_reg_24xx isp24;
73208dfd 465 struct device_reg_25xxmq isp25mq;
a9083016 466 struct device_reg_82xx isp82;
1da177e4
LT
467} device_reg_t;
468
469#define ISP_REQ_Q_IN(ha, reg) \
470 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
471 &(reg)->u.isp2100.mailbox4 : \
472 &(reg)->u.isp2300.req_q_in)
473#define ISP_REQ_Q_OUT(ha, reg) \
474 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
475 &(reg)->u.isp2100.mailbox4 : \
476 &(reg)->u.isp2300.req_q_out)
477#define ISP_RSP_Q_IN(ha, reg) \
478 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
479 &(reg)->u.isp2100.mailbox5 : \
480 &(reg)->u.isp2300.rsp_q_in)
481#define ISP_RSP_Q_OUT(ha, reg) \
482 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
483 &(reg)->u.isp2100.mailbox5 : \
484 &(reg)->u.isp2300.rsp_q_out)
485
486#define MAILBOX_REG(ha, reg, num) \
487 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
488 (num < 8 ? \
489 &(reg)->u.isp2100.mailbox0 + (num) : \
490 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
491 &(reg)->u.isp2300.mailbox0 + (num))
492#define RD_MAILBOX_REG(ha, reg, num) \
493 RD_REG_WORD(MAILBOX_REG(ha, reg, num))
494#define WRT_MAILBOX_REG(ha, reg, num, data) \
495 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
496
497#define FB_CMD_REG(ha, reg) \
498 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
499 &(reg)->fb_cmd_2100 : \
500 &(reg)->u.isp2300.fb_cmd)
501#define RD_FB_CMD_REG(ha, reg) \
502 RD_REG_WORD(FB_CMD_REG(ha, reg))
503#define WRT_FB_CMD_REG(ha, reg, data) \
504 WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
505
506typedef struct {
507 uint32_t out_mb; /* outbound from driver */
508 uint32_t in_mb; /* Incoming from RISC */
509 uint16_t mb[MAILBOX_REGISTER_COUNT];
510 long buf_size;
511 void *bufp;
512 uint32_t tov;
513 uint8_t flags;
514#define MBX_DMA_IN BIT_0
515#define MBX_DMA_OUT BIT_1
516#define IOCTL_CMD BIT_2
517} mbx_cmd_t;
518
519#define MBX_TOV_SECONDS 30
520
521/*
522 * ISP product identification definitions in mailboxes after reset.
523 */
524#define PROD_ID_1 0x4953
525#define PROD_ID_2 0x0000
526#define PROD_ID_2a 0x5020
527#define PROD_ID_3 0x2020
528
529/*
530 * ISP mailbox Self-Test status codes
531 */
532#define MBS_FRM_ALIVE 0 /* Firmware Alive. */
533#define MBS_CHKSUM_ERR 1 /* Checksum Error. */
534#define MBS_BUSY 4 /* Busy. */
535
536/*
537 * ISP mailbox command complete status codes
538 */
539#define MBS_COMMAND_COMPLETE 0x4000
540#define MBS_INVALID_COMMAND 0x4001
541#define MBS_HOST_INTERFACE_ERROR 0x4002
542#define MBS_TEST_FAILED 0x4003
543#define MBS_COMMAND_ERROR 0x4005
544#define MBS_COMMAND_PARAMETER_ERROR 0x4006
545#define MBS_PORT_ID_USED 0x4007
546#define MBS_LOOP_ID_USED 0x4008
547#define MBS_ALL_IDS_IN_USE 0x4009
548#define MBS_NOT_LOGGED_IN 0x400A
3d71644c
AV
549#define MBS_LINK_DOWN_ERROR 0x400B
550#define MBS_DIAG_ECHO_TEST_ERROR 0x400C
1da177e4
LT
551
552/*
553 * ISP mailbox asynchronous event status codes
554 */
555#define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
556#define MBA_RESET 0x8001 /* Reset Detected. */
557#define MBA_SYSTEM_ERR 0x8002 /* System Error. */
558#define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
559#define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
560#define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
561#define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
562 /* occurred. */
563#define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
564#define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
565#define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
566#define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
567#define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
568#define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
569#define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
570#define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
571#define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
572#define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
573#define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
574#define MBA_IP_RECEIVE 0x8023 /* IP Received. */
575#define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
576#define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
577#define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
578#define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
579 /* used. */
45ebeb56 580#define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */
1da177e4
LT
581#define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
582#define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
583#define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
584#define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
585#define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
586#define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
587#define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
588#define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
589#define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
590#define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
591#define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
592#define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
593#define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
594
9a069e19
GM
595/* ISP mailbox loopback echo diagnostic error code */
596#define MBS_LB_RESET 0x17
1da177e4
LT
597/*
598 * Firmware options 1, 2, 3.
599 */
600#define FO1_AE_ON_LIPF8 BIT_0
601#define FO1_AE_ALL_LIP_RESET BIT_1
602#define FO1_CTIO_RETRY BIT_3
603#define FO1_DISABLE_LIP_F7_SW BIT_4
604#define FO1_DISABLE_100MS_LOS_WAIT BIT_5
3d71644c 605#define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */
1da177e4
LT
606#define FO1_AE_ON_LOOP_INIT_ERR BIT_7
607#define FO1_SET_EMPHASIS_SWING BIT_8
608#define FO1_AE_AUTO_BYPASS BIT_9
609#define FO1_ENABLE_PURE_IOCB BIT_10
610#define FO1_AE_PLOGI_RJT BIT_11
611#define FO1_ENABLE_ABORT_SEQUENCE BIT_12
612#define FO1_AE_QUEUE_FULL BIT_13
613
614#define FO2_ENABLE_ATIO_TYPE_3 BIT_0
615#define FO2_REV_LOOPBACK BIT_1
616
617#define FO3_ENABLE_EMERG_IOCB BIT_0
618#define FO3_AE_RND_ERROR BIT_1
619
3d71644c
AV
620/* 24XX additional firmware options */
621#define ADD_FO_COUNT 3
622#define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */
623#define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
624
625#define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
626
627#define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
628
1da177e4
LT
629/*
630 * ISP mailbox commands
631 */
632#define MBC_LOAD_RAM 1 /* Load RAM. */
633#define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
634#define MBC_WRITE_RAM_WORD 4 /* Write RAM word. */
635#define MBC_READ_RAM_WORD 5 /* Read RAM word. */
636#define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
637#define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
638#define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
639#define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
640#define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
641#define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
642#define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
643#define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
644#define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
645#define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
f6ef3b18 646#define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */
1da177e4
LT
647#define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
648#define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
649#define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
650#define MBC_RESET 0x18 /* Reset. */
651#define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
652#define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
653#define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
654#define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
655#define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
656#define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
657#define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
658#define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
659#define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
660#define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
661#define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
662#define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
663#define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
664#define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
6246b8a1 665#define MBC_CONFIGURE_VF 0x4b /* Configure VFs */
1da177e4
LT
666#define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
667#define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
af11f64d 668#define MBC_PORT_LOGOUT 0x56 /* Port Logout request */
1da177e4
LT
669#define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
670#define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
671#define MBC_GET_RNID_PARAMS 0x5a /* Data Rate */
672#define MBC_DATA_RATE 0x5d /* Get RNID parameters */
673#define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
674#define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
675 /* Initialization Procedure */
676#define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
677#define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
678#define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
679#define MBC_TARGET_RESET 0x66 /* Target Reset. */
680#define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
681#define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
682#define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
683#define MBC_GET_PORT_NAME 0x6a /* Get port name. */
684#define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
685#define MBC_LIP_RESET 0x6c /* LIP reset. */
686#define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
687 /* commandd. */
688#define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
689#define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
690#define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
691#define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
692#define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
693#define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
694#define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
695#define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
696#define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
697#define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
698#define MBC_LUN_RESET 0x7E /* Send LUN reset */
699
3d71644c
AV
700/*
701 * ISP24xx mailbox commands
702 */
703#define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */
704#define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */
d8b45213 705#define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */
3d71644c 706#define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */
a7a167bf 707#define MBC_TRACE_CONTROL 0x27 /* Trace control command. */
3d71644c 708#define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */
ad0ecd61 709#define MBC_WRITE_SFP 0x30 /* Write SFP Data. */
88729e53 710#define MBC_READ_SFP 0x31 /* Read SFP Data. */
3d71644c
AV
711#define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */
712#define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */
713#define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */
714#define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */
715#define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */
716#define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */
717#define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */
718#define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */
23f2ebd1
SR
719#define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */
720#define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */
3d71644c 721
b1d46989
MI
722/*
723 * ISP81xx mailbox commands
724 */
725#define MBC_WRITE_MPI_REGISTER 0x01 /* Write MPI Register. */
726
1da177e4
LT
727/* Firmware return data sizes */
728#define FCAL_MAP_SIZE 128
729
730/* Mailbox bit definitions for out_mb and in_mb */
731#define MBX_31 BIT_31
732#define MBX_30 BIT_30
733#define MBX_29 BIT_29
734#define MBX_28 BIT_28
735#define MBX_27 BIT_27
736#define MBX_26 BIT_26
737#define MBX_25 BIT_25
738#define MBX_24 BIT_24
739#define MBX_23 BIT_23
740#define MBX_22 BIT_22
741#define MBX_21 BIT_21
742#define MBX_20 BIT_20
743#define MBX_19 BIT_19
744#define MBX_18 BIT_18
745#define MBX_17 BIT_17
746#define MBX_16 BIT_16
747#define MBX_15 BIT_15
748#define MBX_14 BIT_14
749#define MBX_13 BIT_13
750#define MBX_12 BIT_12
751#define MBX_11 BIT_11
752#define MBX_10 BIT_10
753#define MBX_9 BIT_9
754#define MBX_8 BIT_8
755#define MBX_7 BIT_7
756#define MBX_6 BIT_6
757#define MBX_5 BIT_5
758#define MBX_4 BIT_4
759#define MBX_3 BIT_3
760#define MBX_2 BIT_2
761#define MBX_1 BIT_1
762#define MBX_0 BIT_0
763
764/*
765 * Firmware state codes from get firmware state mailbox command
766 */
767#define FSTATE_CONFIG_WAIT 0
768#define FSTATE_WAIT_AL_PA 1
769#define FSTATE_WAIT_LOGIN 2
770#define FSTATE_READY 3
771#define FSTATE_LOSS_OF_SYNC 4
772#define FSTATE_ERROR 5
773#define FSTATE_REINIT 6
774#define FSTATE_NON_PART 7
775
776#define FSTATE_CONFIG_CORRECT 0
777#define FSTATE_P2P_RCV_LIP 1
778#define FSTATE_P2P_CHOOSE_LOOP 2
779#define FSTATE_P2P_RCV_UNIDEN_LIP 3
780#define FSTATE_FATAL_ERROR 4
781#define FSTATE_LOOP_BACK_CONN 5
782
783/*
784 * Port Database structure definition
785 * Little endian except where noted.
786 */
787#define PORT_DATABASE_SIZE 128 /* bytes */
788typedef struct {
789 uint8_t options;
790 uint8_t control;
791 uint8_t master_state;
792 uint8_t slave_state;
793 uint8_t reserved[2];
794 uint8_t hard_address;
795 uint8_t reserved_1;
796 uint8_t port_id[4];
797 uint8_t node_name[WWN_SIZE];
798 uint8_t port_name[WWN_SIZE];
799 uint16_t execution_throttle;
800 uint16_t execution_count;
801 uint8_t reset_count;
802 uint8_t reserved_2;
803 uint16_t resource_allocation;
804 uint16_t current_allocation;
805 uint16_t queue_head;
806 uint16_t queue_tail;
807 uint16_t transmit_execution_list_next;
808 uint16_t transmit_execution_list_previous;
809 uint16_t common_features;
810 uint16_t total_concurrent_sequences;
811 uint16_t RO_by_information_category;
812 uint8_t recipient;
813 uint8_t initiator;
814 uint16_t receive_data_size;
815 uint16_t concurrent_sequences;
816 uint16_t open_sequences_per_exchange;
817 uint16_t lun_abort_flags;
818 uint16_t lun_stop_flags;
819 uint16_t stop_queue_head;
820 uint16_t stop_queue_tail;
821 uint16_t port_retry_timer;
822 uint16_t next_sequence_id;
823 uint16_t frame_count;
824 uint16_t PRLI_payload_length;
825 uint8_t prli_svc_param_word_0[2]; /* Big endian */
826 /* Bits 15-0 of word 0 */
827 uint8_t prli_svc_param_word_3[2]; /* Big endian */
828 /* Bits 15-0 of word 3 */
829 uint16_t loop_id;
830 uint16_t extended_lun_info_list_pointer;
831 uint16_t extended_lun_stop_list_pointer;
832} port_database_t;
833
834/*
835 * Port database slave/master states
836 */
837#define PD_STATE_DISCOVERY 0
838#define PD_STATE_WAIT_DISCOVERY_ACK 1
839#define PD_STATE_PORT_LOGIN 2
840#define PD_STATE_WAIT_PORT_LOGIN_ACK 3
841#define PD_STATE_PROCESS_LOGIN 4
842#define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
843#define PD_STATE_PORT_LOGGED_IN 6
844#define PD_STATE_PORT_UNAVAILABLE 7
845#define PD_STATE_PROCESS_LOGOUT 8
846#define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
847#define PD_STATE_PORT_LOGOUT 10
848#define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
849
850
4fdfefe5
AV
851#define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
852#define QLA_ZIO_DISABLED 0
853#define QLA_ZIO_DEFAULT_TIMER 2
854
1da177e4
LT
855/*
856 * ISP Initialization Control Block.
857 * Little endian except where noted.
858 */
859#define ICB_VERSION 1
860typedef struct {
861 uint8_t version;
862 uint8_t reserved_1;
863
864 /*
865 * LSB BIT 0 = Enable Hard Loop Id
866 * LSB BIT 1 = Enable Fairness
867 * LSB BIT 2 = Enable Full-Duplex
868 * LSB BIT 3 = Enable Fast Posting
869 * LSB BIT 4 = Enable Target Mode
870 * LSB BIT 5 = Disable Initiator Mode
871 * LSB BIT 6 = Enable ADISC
872 * LSB BIT 7 = Enable Target Inquiry Data
873 *
874 * MSB BIT 0 = Enable PDBC Notify
875 * MSB BIT 1 = Non Participating LIP
876 * MSB BIT 2 = Descending Loop ID Search
877 * MSB BIT 3 = Acquire Loop ID in LIPA
878 * MSB BIT 4 = Stop PortQ on Full Status
879 * MSB BIT 5 = Full Login after LIP
880 * MSB BIT 6 = Node Name Option
881 * MSB BIT 7 = Ext IFWCB enable bit
882 */
883 uint8_t firmware_options[2];
884
885 uint16_t frame_payload_size;
886 uint16_t max_iocb_allocation;
887 uint16_t execution_throttle;
888 uint8_t retry_count;
889 uint8_t retry_delay; /* unused */
890 uint8_t port_name[WWN_SIZE]; /* Big endian. */
891 uint16_t hard_address;
892 uint8_t inquiry_data;
893 uint8_t login_timeout;
894 uint8_t node_name[WWN_SIZE]; /* Big endian. */
895
896 uint16_t request_q_outpointer;
897 uint16_t response_q_inpointer;
898 uint16_t request_q_length;
899 uint16_t response_q_length;
900 uint32_t request_q_address[2];
901 uint32_t response_q_address[2];
902
903 uint16_t lun_enables;
904 uint8_t command_resource_count;
905 uint8_t immediate_notify_resource_count;
906 uint16_t timeout;
907 uint8_t reserved_2[2];
908
909 /*
910 * LSB BIT 0 = Timer Operation mode bit 0
911 * LSB BIT 1 = Timer Operation mode bit 1
912 * LSB BIT 2 = Timer Operation mode bit 2
913 * LSB BIT 3 = Timer Operation mode bit 3
914 * LSB BIT 4 = Init Config Mode bit 0
915 * LSB BIT 5 = Init Config Mode bit 1
916 * LSB BIT 6 = Init Config Mode bit 2
917 * LSB BIT 7 = Enable Non part on LIHA failure
918 *
919 * MSB BIT 0 = Enable class 2
920 * MSB BIT 1 = Enable ACK0
921 * MSB BIT 2 =
922 * MSB BIT 3 =
923 * MSB BIT 4 = FC Tape Enable
924 * MSB BIT 5 = Enable FC Confirm
925 * MSB BIT 6 = Enable command queuing in target mode
926 * MSB BIT 7 = No Logo On Link Down
927 */
928 uint8_t add_firmware_options[2];
929
930 uint8_t response_accumulation_timer;
931 uint8_t interrupt_delay_timer;
932
933 /*
934 * LSB BIT 0 = Enable Read xfr_rdy
935 * LSB BIT 1 = Soft ID only
936 * LSB BIT 2 =
937 * LSB BIT 3 =
938 * LSB BIT 4 = FCP RSP Payload [0]
939 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
940 * LSB BIT 6 = Enable Out-of-Order frame handling
941 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
942 *
943 * MSB BIT 0 = Sbus enable - 2300
944 * MSB BIT 1 =
945 * MSB BIT 2 =
946 * MSB BIT 3 =
06c22bd1 947 * MSB BIT 4 = LED mode
1da177e4
LT
948 * MSB BIT 5 = enable 50 ohm termination
949 * MSB BIT 6 = Data Rate (2300 only)
950 * MSB BIT 7 = Data Rate (2300 only)
951 */
952 uint8_t special_options[2];
953
954 uint8_t reserved_3[26];
955} init_cb_t;
956
957/*
958 * Get Link Status mailbox command return buffer.
959 */
3d71644c
AV
960#define GLSO_SEND_RPS BIT_0
961#define GLSO_USE_DID BIT_3
962
43ef0580
AV
963struct link_statistics {
964 uint32_t link_fail_cnt;
965 uint32_t loss_sync_cnt;
966 uint32_t loss_sig_cnt;
967 uint32_t prim_seq_err_cnt;
968 uint32_t inval_xmit_word_cnt;
969 uint32_t inval_crc_cnt;
032d8dd7
HZ
970 uint32_t lip_cnt;
971 uint32_t unused1[0x1a];
43ef0580
AV
972 uint32_t tx_frames;
973 uint32_t rx_frames;
974 uint32_t dumped_frames;
975 uint32_t unused2[2];
976 uint32_t nos_rcvd;
977};
1da177e4
LT
978
979/*
980 * NVRAM Command values.
981 */
982#define NV_START_BIT BIT_2
983#define NV_WRITE_OP (BIT_26+BIT_24)
984#define NV_READ_OP (BIT_26+BIT_25)
985#define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
986#define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
987#define NV_DELAY_COUNT 10
988
989/*
990 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
991 */
992typedef struct {
993 /*
994 * NVRAM header
995 */
996 uint8_t id[4];
997 uint8_t nvram_version;
998 uint8_t reserved_0;
999
1000 /*
1001 * NVRAM RISC parameter block
1002 */
1003 uint8_t parameter_block_version;
1004 uint8_t reserved_1;
1005
1006 /*
1007 * LSB BIT 0 = Enable Hard Loop Id
1008 * LSB BIT 1 = Enable Fairness
1009 * LSB BIT 2 = Enable Full-Duplex
1010 * LSB BIT 3 = Enable Fast Posting
1011 * LSB BIT 4 = Enable Target Mode
1012 * LSB BIT 5 = Disable Initiator Mode
1013 * LSB BIT 6 = Enable ADISC
1014 * LSB BIT 7 = Enable Target Inquiry Data
1015 *
1016 * MSB BIT 0 = Enable PDBC Notify
1017 * MSB BIT 1 = Non Participating LIP
1018 * MSB BIT 2 = Descending Loop ID Search
1019 * MSB BIT 3 = Acquire Loop ID in LIPA
1020 * MSB BIT 4 = Stop PortQ on Full Status
1021 * MSB BIT 5 = Full Login after LIP
1022 * MSB BIT 6 = Node Name Option
1023 * MSB BIT 7 = Ext IFWCB enable bit
1024 */
1025 uint8_t firmware_options[2];
1026
1027 uint16_t frame_payload_size;
1028 uint16_t max_iocb_allocation;
1029 uint16_t execution_throttle;
1030 uint8_t retry_count;
1031 uint8_t retry_delay; /* unused */
1032 uint8_t port_name[WWN_SIZE]; /* Big endian. */
1033 uint16_t hard_address;
1034 uint8_t inquiry_data;
1035 uint8_t login_timeout;
1036 uint8_t node_name[WWN_SIZE]; /* Big endian. */
1037
1038 /*
1039 * LSB BIT 0 = Timer Operation mode bit 0
1040 * LSB BIT 1 = Timer Operation mode bit 1
1041 * LSB BIT 2 = Timer Operation mode bit 2
1042 * LSB BIT 3 = Timer Operation mode bit 3
1043 * LSB BIT 4 = Init Config Mode bit 0
1044 * LSB BIT 5 = Init Config Mode bit 1
1045 * LSB BIT 6 = Init Config Mode bit 2
1046 * LSB BIT 7 = Enable Non part on LIHA failure
1047 *
1048 * MSB BIT 0 = Enable class 2
1049 * MSB BIT 1 = Enable ACK0
1050 * MSB BIT 2 =
1051 * MSB BIT 3 =
1052 * MSB BIT 4 = FC Tape Enable
1053 * MSB BIT 5 = Enable FC Confirm
1054 * MSB BIT 6 = Enable command queuing in target mode
1055 * MSB BIT 7 = No Logo On Link Down
1056 */
1057 uint8_t add_firmware_options[2];
1058
1059 uint8_t response_accumulation_timer;
1060 uint8_t interrupt_delay_timer;
1061
1062 /*
1063 * LSB BIT 0 = Enable Read xfr_rdy
1064 * LSB BIT 1 = Soft ID only
1065 * LSB BIT 2 =
1066 * LSB BIT 3 =
1067 * LSB BIT 4 = FCP RSP Payload [0]
1068 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1069 * LSB BIT 6 = Enable Out-of-Order frame handling
1070 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1071 *
1072 * MSB BIT 0 = Sbus enable - 2300
1073 * MSB BIT 1 =
1074 * MSB BIT 2 =
1075 * MSB BIT 3 =
06c22bd1 1076 * MSB BIT 4 = LED mode
1da177e4
LT
1077 * MSB BIT 5 = enable 50 ohm termination
1078 * MSB BIT 6 = Data Rate (2300 only)
1079 * MSB BIT 7 = Data Rate (2300 only)
1080 */
1081 uint8_t special_options[2];
1082
1083 /* Reserved for expanded RISC parameter block */
1084 uint8_t reserved_2[22];
1085
1086 /*
1087 * LSB BIT 0 = Tx Sensitivity 1G bit 0
1088 * LSB BIT 1 = Tx Sensitivity 1G bit 1
1089 * LSB BIT 2 = Tx Sensitivity 1G bit 2
1090 * LSB BIT 3 = Tx Sensitivity 1G bit 3
1091 * LSB BIT 4 = Rx Sensitivity 1G bit 0
1092 * LSB BIT 5 = Rx Sensitivity 1G bit 1
1093 * LSB BIT 6 = Rx Sensitivity 1G bit 2
1094 * LSB BIT 7 = Rx Sensitivity 1G bit 3
fa2a1ce5 1095 *
1da177e4
LT
1096 * MSB BIT 0 = Tx Sensitivity 2G bit 0
1097 * MSB BIT 1 = Tx Sensitivity 2G bit 1
1098 * MSB BIT 2 = Tx Sensitivity 2G bit 2
1099 * MSB BIT 3 = Tx Sensitivity 2G bit 3
1100 * MSB BIT 4 = Rx Sensitivity 2G bit 0
1101 * MSB BIT 5 = Rx Sensitivity 2G bit 1
1102 * MSB BIT 6 = Rx Sensitivity 2G bit 2
1103 * MSB BIT 7 = Rx Sensitivity 2G bit 3
1104 *
1105 * LSB BIT 0 = Output Swing 1G bit 0
1106 * LSB BIT 1 = Output Swing 1G bit 1
1107 * LSB BIT 2 = Output Swing 1G bit 2
1108 * LSB BIT 3 = Output Emphasis 1G bit 0
1109 * LSB BIT 4 = Output Emphasis 1G bit 1
1110 * LSB BIT 5 = Output Swing 2G bit 0
1111 * LSB BIT 6 = Output Swing 2G bit 1
1112 * LSB BIT 7 = Output Swing 2G bit 2
fa2a1ce5 1113 *
1da177e4
LT
1114 * MSB BIT 0 = Output Emphasis 2G bit 0
1115 * MSB BIT 1 = Output Emphasis 2G bit 1
1116 * MSB BIT 2 = Output Enable
1117 * MSB BIT 3 =
1118 * MSB BIT 4 =
1119 * MSB BIT 5 =
1120 * MSB BIT 6 =
1121 * MSB BIT 7 =
1122 */
1123 uint8_t seriallink_options[4];
1124
1125 /*
1126 * NVRAM host parameter block
1127 *
1128 * LSB BIT 0 = Enable spinup delay
1129 * LSB BIT 1 = Disable BIOS
1130 * LSB BIT 2 = Enable Memory Map BIOS
1131 * LSB BIT 3 = Enable Selectable Boot
1132 * LSB BIT 4 = Disable RISC code load
1133 * LSB BIT 5 = Set cache line size 1
1134 * LSB BIT 6 = PCI Parity Disable
1135 * LSB BIT 7 = Enable extended logging
1136 *
1137 * MSB BIT 0 = Enable 64bit addressing
1138 * MSB BIT 1 = Enable lip reset
1139 * MSB BIT 2 = Enable lip full login
1140 * MSB BIT 3 = Enable target reset
1141 * MSB BIT 4 = Enable database storage
1142 * MSB BIT 5 = Enable cache flush read
1143 * MSB BIT 6 = Enable database load
1144 * MSB BIT 7 = Enable alternate WWN
1145 */
1146 uint8_t host_p[2];
1147
1148 uint8_t boot_node_name[WWN_SIZE];
1149 uint8_t boot_lun_number;
1150 uint8_t reset_delay;
1151 uint8_t port_down_retry_count;
1152 uint8_t boot_id_number;
1153 uint16_t max_luns_per_target;
1154 uint8_t fcode_boot_port_name[WWN_SIZE];
1155 uint8_t alternate_port_name[WWN_SIZE];
1156 uint8_t alternate_node_name[WWN_SIZE];
1157
1158 /*
1159 * BIT 0 = Selective Login
1160 * BIT 1 = Alt-Boot Enable
1161 * BIT 2 =
1162 * BIT 3 = Boot Order List
1163 * BIT 4 =
1164 * BIT 5 = Selective LUN
1165 * BIT 6 =
1166 * BIT 7 = unused
1167 */
1168 uint8_t efi_parameters;
1169
1170 uint8_t link_down_timeout;
1171
cca5335c 1172 uint8_t adapter_id[16];
1da177e4
LT
1173
1174 uint8_t alt1_boot_node_name[WWN_SIZE];
1175 uint16_t alt1_boot_lun_number;
1176 uint8_t alt2_boot_node_name[WWN_SIZE];
1177 uint16_t alt2_boot_lun_number;
1178 uint8_t alt3_boot_node_name[WWN_SIZE];
1179 uint16_t alt3_boot_lun_number;
1180 uint8_t alt4_boot_node_name[WWN_SIZE];
1181 uint16_t alt4_boot_lun_number;
1182 uint8_t alt5_boot_node_name[WWN_SIZE];
1183 uint16_t alt5_boot_lun_number;
1184 uint8_t alt6_boot_node_name[WWN_SIZE];
1185 uint16_t alt6_boot_lun_number;
1186 uint8_t alt7_boot_node_name[WWN_SIZE];
1187 uint16_t alt7_boot_lun_number;
1188
1189 uint8_t reserved_3[2];
1190
1191 /* Offset 200-215 : Model Number */
1192 uint8_t model_number[16];
1193
1194 /* OEM related items */
1195 uint8_t oem_specific[16];
1196
1197 /*
1198 * NVRAM Adapter Features offset 232-239
1199 *
1200 * LSB BIT 0 = External GBIC
1201 * LSB BIT 1 = Risc RAM parity
1202 * LSB BIT 2 = Buffer Plus Module
1203 * LSB BIT 3 = Multi Chip Adapter
1204 * LSB BIT 4 = Internal connector
1205 * LSB BIT 5 =
1206 * LSB BIT 6 =
1207 * LSB BIT 7 =
1208 *
1209 * MSB BIT 0 =
1210 * MSB BIT 1 =
1211 * MSB BIT 2 =
1212 * MSB BIT 3 =
1213 * MSB BIT 4 =
1214 * MSB BIT 5 =
1215 * MSB BIT 6 =
1216 * MSB BIT 7 =
1217 */
1218 uint8_t adapter_features[2];
1219
1220 uint8_t reserved_4[16];
1221
1222 /* Subsystem vendor ID for ISP2200 */
1223 uint16_t subsystem_vendor_id_2200;
1224
1225 /* Subsystem device ID for ISP2200 */
1226 uint16_t subsystem_device_id_2200;
1227
1228 uint8_t reserved_5;
1229 uint8_t checksum;
1230} nvram_t;
1231
1232/*
1233 * ISP queue - response queue entry definition.
1234 */
1235typedef struct {
1236 uint8_t data[60];
1237 uint32_t signature;
1238#define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
1239} response_t;
1240
1241typedef union {
1242 uint16_t extended;
1243 struct {
1244 uint8_t reserved;
1245 uint8_t standard;
1246 } id;
1247} target_id_t;
1248
1249#define SET_TARGET_ID(ha, to, from) \
1250do { \
1251 if (HAS_EXTENDED_IDS(ha)) \
1252 to.extended = cpu_to_le16(from); \
1253 else \
1254 to.id.standard = (uint8_t)from; \
1255} while (0)
1256
1257/*
1258 * ISP queue - command entry structure definition.
1259 */
1260#define COMMAND_TYPE 0x11 /* Command entry */
1da177e4
LT
1261typedef struct {
1262 uint8_t entry_type; /* Entry type. */
1263 uint8_t entry_count; /* Entry count. */
1264 uint8_t sys_define; /* System defined. */
1265 uint8_t entry_status; /* Entry Status. */
1266 uint32_t handle; /* System handle. */
1267 target_id_t target; /* SCSI ID */
1268 uint16_t lun; /* SCSI LUN */
1269 uint16_t control_flags; /* Control flags. */
1270#define CF_WRITE BIT_6
1271#define CF_READ BIT_5
1272#define CF_SIMPLE_TAG BIT_3
1273#define CF_ORDERED_TAG BIT_2
1274#define CF_HEAD_TAG BIT_1
1275 uint16_t reserved_1;
1276 uint16_t timeout; /* Command timeout. */
1277 uint16_t dseg_count; /* Data segment count. */
1278 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1279 uint32_t byte_count; /* Total byte count. */
1280 uint32_t dseg_0_address; /* Data segment 0 address. */
1281 uint32_t dseg_0_length; /* Data segment 0 length. */
1282 uint32_t dseg_1_address; /* Data segment 1 address. */
1283 uint32_t dseg_1_length; /* Data segment 1 length. */
1284 uint32_t dseg_2_address; /* Data segment 2 address. */
1285 uint32_t dseg_2_length; /* Data segment 2 length. */
1286} cmd_entry_t;
1287
1288/*
1289 * ISP queue - 64-Bit addressing, command entry structure definition.
1290 */
1291#define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
1292typedef struct {
1293 uint8_t entry_type; /* Entry type. */
1294 uint8_t entry_count; /* Entry count. */
1295 uint8_t sys_define; /* System defined. */
1296 uint8_t entry_status; /* Entry Status. */
1297 uint32_t handle; /* System handle. */
1298 target_id_t target; /* SCSI ID */
1299 uint16_t lun; /* SCSI LUN */
1300 uint16_t control_flags; /* Control flags. */
1301 uint16_t reserved_1;
1302 uint16_t timeout; /* Command timeout. */
1303 uint16_t dseg_count; /* Data segment count. */
1304 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1305 uint32_t byte_count; /* Total byte count. */
1306 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1307 uint32_t dseg_0_length; /* Data segment 0 length. */
1308 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1309 uint32_t dseg_1_length; /* Data segment 1 length. */
1310} cmd_a64_entry_t, request_t;
1311
1312/*
1313 * ISP queue - continuation entry structure definition.
1314 */
1315#define CONTINUE_TYPE 0x02 /* Continuation entry. */
1316typedef struct {
1317 uint8_t entry_type; /* Entry type. */
1318 uint8_t entry_count; /* Entry count. */
1319 uint8_t sys_define; /* System defined. */
1320 uint8_t entry_status; /* Entry Status. */
1321 uint32_t reserved;
1322 uint32_t dseg_0_address; /* Data segment 0 address. */
1323 uint32_t dseg_0_length; /* Data segment 0 length. */
1324 uint32_t dseg_1_address; /* Data segment 1 address. */
1325 uint32_t dseg_1_length; /* Data segment 1 length. */
1326 uint32_t dseg_2_address; /* Data segment 2 address. */
1327 uint32_t dseg_2_length; /* Data segment 2 length. */
1328 uint32_t dseg_3_address; /* Data segment 3 address. */
1329 uint32_t dseg_3_length; /* Data segment 3 length. */
1330 uint32_t dseg_4_address; /* Data segment 4 address. */
1331 uint32_t dseg_4_length; /* Data segment 4 length. */
1332 uint32_t dseg_5_address; /* Data segment 5 address. */
1333 uint32_t dseg_5_length; /* Data segment 5 length. */
1334 uint32_t dseg_6_address; /* Data segment 6 address. */
1335 uint32_t dseg_6_length; /* Data segment 6 length. */
1336} cont_entry_t;
1337
1338/*
1339 * ISP queue - 64-Bit addressing, continuation entry structure definition.
1340 */
1341#define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
1342typedef struct {
1343 uint8_t entry_type; /* Entry type. */
1344 uint8_t entry_count; /* Entry count. */
1345 uint8_t sys_define; /* System defined. */
1346 uint8_t entry_status; /* Entry Status. */
1347 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1348 uint32_t dseg_0_length; /* Data segment 0 length. */
1349 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1350 uint32_t dseg_1_length; /* Data segment 1 length. */
1351 uint32_t dseg_2_address [2]; /* Data segment 2 address. */
1352 uint32_t dseg_2_length; /* Data segment 2 length. */
1353 uint32_t dseg_3_address[2]; /* Data segment 3 address. */
1354 uint32_t dseg_3_length; /* Data segment 3 length. */
1355 uint32_t dseg_4_address[2]; /* Data segment 4 address. */
1356 uint32_t dseg_4_length; /* Data segment 4 length. */
1357} cont_a64_entry_t;
1358
bad75002
AE
1359#define PO_MODE_DIF_INSERT 0
1360#define PO_MODE_DIF_REMOVE BIT_0
1361#define PO_MODE_DIF_PASS BIT_1
1362#define PO_MODE_DIF_REPLACE (BIT_0 + BIT_1)
1363#define PO_ENABLE_DIF_BUNDLING BIT_8
1364#define PO_ENABLE_INCR_GUARD_SEED BIT_3
1365#define PO_DISABLE_INCR_REF_TAG BIT_5
1366#define PO_DISABLE_GUARD_CHECK BIT_4
1367/*
1368 * ISP queue - 64-Bit addressing, continuation crc entry structure definition.
1369 */
1370struct crc_context {
1371 uint32_t handle; /* System handle. */
1372 uint32_t ref_tag;
1373 uint16_t app_tag;
1374 uint8_t ref_tag_mask[4]; /* Validation/Replacement Mask*/
1375 uint8_t app_tag_mask[2]; /* Validation/Replacement Mask*/
1376 uint16_t guard_seed; /* Initial Guard Seed */
1377 uint16_t prot_opts; /* Requested Data Protection Mode */
1378 uint16_t blk_size; /* Data size in bytes */
1379 uint16_t runt_blk_guard; /* Guard value for runt block (tape
1380 * only) */
1381 uint32_t byte_count; /* Total byte count/ total data
1382 * transfer count */
1383 union {
1384 struct {
1385 uint32_t reserved_1;
1386 uint16_t reserved_2;
1387 uint16_t reserved_3;
1388 uint32_t reserved_4;
1389 uint32_t data_address[2];
1390 uint32_t data_length;
1391 uint32_t reserved_5[2];
1392 uint32_t reserved_6;
1393 } nobundling;
1394 struct {
1395 uint32_t dif_byte_count; /* Total DIF byte
1396 * count */
1397 uint16_t reserved_1;
1398 uint16_t dseg_count; /* Data segment count */
1399 uint32_t reserved_2;
1400 uint32_t data_address[2];
1401 uint32_t data_length;
1402 uint32_t dif_address[2];
1403 uint32_t dif_length; /* Data segment 0
1404 * length */
1405 } bundling;
1406 } u;
1407
1408 struct fcp_cmnd fcp_cmnd;
1409 dma_addr_t crc_ctx_dma;
1410 /* List of DMA context transfers */
1411 struct list_head dsd_list;
1412
1413 /* This structure should not exceed 512 bytes */
1414};
1415
1416#define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun))
1417#define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun))
1418
1da177e4
LT
1419/*
1420 * ISP queue - status entry structure definition.
1421 */
1422#define STATUS_TYPE 0x03 /* Status entry. */
1423typedef struct {
1424 uint8_t entry_type; /* Entry type. */
1425 uint8_t entry_count; /* Entry count. */
1426 uint8_t sys_define; /* System defined. */
1427 uint8_t entry_status; /* Entry Status. */
1428 uint32_t handle; /* System handle. */
1429 uint16_t scsi_status; /* SCSI status. */
1430 uint16_t comp_status; /* Completion status. */
1431 uint16_t state_flags; /* State flags. */
1432 uint16_t status_flags; /* Status flags. */
1433 uint16_t rsp_info_len; /* Response Info Length. */
1434 uint16_t req_sense_length; /* Request sense data length. */
1435 uint32_t residual_length; /* Residual transfer length. */
1436 uint8_t rsp_info[8]; /* FCP response information. */
1437 uint8_t req_sense_data[32]; /* Request sense data. */
1438} sts_entry_t;
1439
1440/*
1441 * Status entry entry status
1442 */
3d71644c 1443#define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */
1da177e4
LT
1444#define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
1445#define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
1446#define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
1447#define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
1448#define RF_BUSY BIT_1 /* Busy */
3d71644c
AV
1449#define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
1450 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
1451#define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
1452 RF_INV_E_TYPE)
1da177e4
LT
1453
1454/*
1455 * Status entry SCSI status bit definitions.
1456 */
1457#define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
1458#define SS_RESIDUAL_UNDER BIT_11
1459#define SS_RESIDUAL_OVER BIT_10
1460#define SS_SENSE_LEN_VALID BIT_9
1461#define SS_RESPONSE_INFO_LEN_VALID BIT_8
1462
1463#define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
1464#define SS_BUSY_CONDITION BIT_3
1465#define SS_CONDITION_MET BIT_2
1466#define SS_CHECK_CONDITION BIT_1
1467
1468/*
1469 * Status entry completion status
1470 */
1471#define CS_COMPLETE 0x0 /* No errors */
1472#define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
1473#define CS_DMA 0x2 /* A DMA direction error. */
1474#define CS_TRANSPORT 0x3 /* Transport error. */
1475#define CS_RESET 0x4 /* SCSI bus reset occurred */
1476#define CS_ABORTED 0x5 /* System aborted command. */
1477#define CS_TIMEOUT 0x6 /* Timeout error. */
1478#define CS_DATA_OVERRUN 0x7 /* Data overrun. */
bad75002 1479#define CS_DIF_ERROR 0xC /* DIF error detected */
1da177e4
LT
1480
1481#define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
1482#define CS_QUEUE_FULL 0x1C /* Queue Full. */
1483#define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
1484 /* (selection timeout) */
1485#define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
1486#define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
1487#define CS_PORT_BUSY 0x2B /* Port Busy */
1488#define CS_COMPLETE_CHKCOND 0x30 /* Error? */
1489#define CS_BAD_PAYLOAD 0x80 /* Driver defined */
1490#define CS_UNKNOWN 0x81 /* Driver defined */
1491#define CS_RETRY 0x82 /* Driver defined */
1492#define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
1493
1494/*
1495 * Status entry status flags
1496 */
1497#define SF_ABTS_TERMINATED BIT_10
1498#define SF_LOGOUT_SENT BIT_13
1499
1500/*
1501 * ISP queue - status continuation entry structure definition.
1502 */
1503#define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
1504typedef struct {
1505 uint8_t entry_type; /* Entry type. */
1506 uint8_t entry_count; /* Entry count. */
1507 uint8_t sys_define; /* System defined. */
1508 uint8_t entry_status; /* Entry Status. */
1509 uint8_t data[60]; /* data */
1510} sts_cont_entry_t;
1511
1512/*
1513 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
1514 * structure definition.
1515 */
1516#define STATUS_TYPE_21 0x21 /* Status entry. */
1517typedef struct {
1518 uint8_t entry_type; /* Entry type. */
1519 uint8_t entry_count; /* Entry count. */
1520 uint8_t handle_count; /* Handle count. */
1521 uint8_t entry_status; /* Entry Status. */
1522 uint32_t handle[15]; /* System handles. */
1523} sts21_entry_t;
1524
1525/*
1526 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
1527 * structure definition.
1528 */
1529#define STATUS_TYPE_22 0x22 /* Status entry. */
1530typedef struct {
1531 uint8_t entry_type; /* Entry type. */
1532 uint8_t entry_count; /* Entry count. */
1533 uint8_t handle_count; /* Handle count. */
1534 uint8_t entry_status; /* Entry Status. */
1535 uint16_t handle[30]; /* System handles. */
1536} sts22_entry_t;
1537
1538/*
1539 * ISP queue - marker entry structure definition.
1540 */
1541#define MARKER_TYPE 0x04 /* Marker entry. */
1542typedef struct {
1543 uint8_t entry_type; /* Entry type. */
1544 uint8_t entry_count; /* Entry count. */
1545 uint8_t handle_count; /* Handle count. */
1546 uint8_t entry_status; /* Entry Status. */
1547 uint32_t sys_define_2; /* System defined. */
1548 target_id_t target; /* SCSI ID */
1549 uint8_t modifier; /* Modifier (7-0). */
1550#define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
1551#define MK_SYNC_ID 1 /* Synchronize ID */
1552#define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
1553#define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
1554 /* clear port changed, */
1555 /* use sequence number. */
1556 uint8_t reserved_1;
1557 uint16_t sequence_number; /* Sequence number of event */
1558 uint16_t lun; /* SCSI LUN */
1559 uint8_t reserved_2[48];
1560} mrk_entry_t;
1561
1562/*
1563 * ISP queue - Management Server entry structure definition.
1564 */
1565#define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
1566typedef struct {
1567 uint8_t entry_type; /* Entry type. */
1568 uint8_t entry_count; /* Entry count. */
1569 uint8_t handle_count; /* Handle count. */
1570 uint8_t entry_status; /* Entry Status. */
1571 uint32_t handle1; /* System handle. */
1572 target_id_t loop_id;
1573 uint16_t status;
1574 uint16_t control_flags; /* Control flags. */
1575 uint16_t reserved2;
1576 uint16_t timeout;
1577 uint16_t cmd_dsd_count;
1578 uint16_t total_dsd_count;
1579 uint8_t type;
1580 uint8_t r_ctl;
1581 uint16_t rx_id;
1582 uint16_t reserved3;
1583 uint32_t handle2;
1584 uint32_t rsp_bytecount;
1585 uint32_t req_bytecount;
1586 uint32_t dseg_req_address[2]; /* Data segment 0 address. */
1587 uint32_t dseg_req_length; /* Data segment 0 length. */
1588 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */
1589 uint32_t dseg_rsp_length; /* Data segment 1 length. */
1590} ms_iocb_entry_t;
1591
1592
1593/*
1594 * ISP queue - Mailbox Command entry structure definition.
1595 */
1596#define MBX_IOCB_TYPE 0x39
1597struct mbx_entry {
1598 uint8_t entry_type;
1599 uint8_t entry_count;
1600 uint8_t sys_define1;
1601 /* Use sys_define1 for source type */
1602#define SOURCE_SCSI 0x00
1603#define SOURCE_IP 0x01
1604#define SOURCE_VI 0x02
1605#define SOURCE_SCTP 0x03
1606#define SOURCE_MP 0x04
1607#define SOURCE_MPIOCTL 0x05
1608#define SOURCE_ASYNC_IOCB 0x07
1609
1610 uint8_t entry_status;
1611
1612 uint32_t handle;
1613 target_id_t loop_id;
1614
1615 uint16_t status;
1616 uint16_t state_flags;
1617 uint16_t status_flags;
1618
1619 uint32_t sys_define2[2];
1620
1621 uint16_t mb0;
1622 uint16_t mb1;
1623 uint16_t mb2;
1624 uint16_t mb3;
1625 uint16_t mb6;
1626 uint16_t mb7;
1627 uint16_t mb9;
1628 uint16_t mb10;
1629 uint32_t reserved_2[2];
1630 uint8_t node_name[WWN_SIZE];
1631 uint8_t port_name[WWN_SIZE];
1632};
1633
1634/*
1635 * ISP request and response queue entry sizes
1636 */
1637#define RESPONSE_ENTRY_SIZE (sizeof(response_t))
1638#define REQUEST_ENTRY_SIZE (sizeof(request_t))
1639
1640
1641/*
1642 * 24 bit port ID type definition.
1643 */
1644typedef union {
1645 uint32_t b24 : 24;
1646
1647 struct {
b889d531
MN
1648#ifdef __BIG_ENDIAN
1649 uint8_t domain;
1650 uint8_t area;
1651 uint8_t al_pa;
0fd30f77 1652#elif defined(__LITTLE_ENDIAN)
1da177e4
LT
1653 uint8_t al_pa;
1654 uint8_t area;
1655 uint8_t domain;
b889d531
MN
1656#else
1657#error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!"
1658#endif
1da177e4
LT
1659 uint8_t rsvd_1;
1660 } b;
1661} port_id_t;
1662#define INVALID_PORT_ID 0xFFFFFF
1663
1664/*
1665 * Switch info gathering structure.
1666 */
1667typedef struct {
1668 port_id_t d_id;
1669 uint8_t node_name[WWN_SIZE];
1670 uint8_t port_name[WWN_SIZE];
d8b45213 1671 uint8_t fabric_port_name[WWN_SIZE];
d8b45213 1672 uint16_t fp_speed;
e8c72ba5 1673 uint8_t fc4_type;
1da177e4
LT
1674} sw_info_t;
1675
e8c72ba5
CD
1676/* FCP-4 types */
1677#define FC4_TYPE_FCP_SCSI 0x08
1678#define FC4_TYPE_OTHER 0x0
1679#define FC4_TYPE_UNKNOWN 0xff
1680
1da177e4
LT
1681/*
1682 * Fibre channel port type.
1683 */
1684 typedef enum {
1685 FCT_UNKNOWN,
1686 FCT_RSCN,
1687 FCT_SWITCH,
1688 FCT_BROADCAST,
1689 FCT_INITIATOR,
1690 FCT_TARGET
1691} fc_port_type_t;
1692
1693/*
1694 * Fibre channel port structure.
1695 */
1696typedef struct fc_port {
1697 struct list_head list;
7b867cf7 1698 struct scsi_qla_host *vha;
1da177e4
LT
1699
1700 uint8_t node_name[WWN_SIZE];
1701 uint8_t port_name[WWN_SIZE];
1702 port_id_t d_id;
1703 uint16_t loop_id;
1704 uint16_t old_loop_id;
1705
09ff701a
SR
1706 uint8_t fcp_prio;
1707
d8b45213
AV
1708 uint8_t fabric_port_name[WWN_SIZE];
1709 uint16_t fp_speed;
1710
1da177e4
LT
1711 fc_port_type_t port_type;
1712
1713 atomic_t state;
1714 uint32_t flags;
1715
1da177e4 1716 int login_retry;
1da177e4 1717
d97994dc 1718 struct fc_rport *rport, *drport;
ad3e0eda 1719 u32 supported_classes;
df7baa50 1720
2c3dfe3f 1721 uint16_t vp_idx;
e8c72ba5 1722 uint8_t fc4_type;
b3b02e6e 1723 uint8_t scan_state;
1da177e4
LT
1724} fc_port_t;
1725
1726/*
1727 * Fibre channel port/lun states.
1728 */
1729#define FCS_UNCONFIGURED 1
1730#define FCS_DEVICE_DEAD 2
1731#define FCS_DEVICE_LOST 3
1732#define FCS_ONLINE 4
1da177e4 1733
ec426e10
CD
1734static const char * const port_state_str[] = {
1735 "Unknown",
1736 "UNCONFIGURED",
1737 "DEAD",
1738 "LOST",
1739 "ONLINE"
1740};
1741
1da177e4
LT
1742/*
1743 * FC port flags.
1744 */
1745#define FCF_FABRIC_DEVICE BIT_0
1746#define FCF_LOGIN_NEEDED BIT_1
f08b7251 1747#define FCF_FCP2_DEVICE BIT_2
5ff1d584 1748#define FCF_ASYNC_SENT BIT_3
1da177e4
LT
1749
1750/* No loop ID flag. */
1751#define FC_NO_LOOP_ID 0x1000
1752
1da177e4
LT
1753/*
1754 * FC-CT interface
1755 *
1756 * NOTE: All structures are big-endian in form.
1757 */
1758
1759#define CT_REJECT_RESPONSE 0x8001
1760#define CT_ACCEPT_RESPONSE 0x8002
4346b149 1761#define CT_REASON_INVALID_COMMAND_CODE 0x01
cca5335c 1762#define CT_REASON_CANNOT_PERFORM 0x09
3fe7cfb9 1763#define CT_REASON_COMMAND_UNSUPPORTED 0x0b
cca5335c 1764#define CT_EXPL_ALREADY_REGISTERED 0x10
1da177e4
LT
1765
1766#define NS_N_PORT_TYPE 0x01
1767#define NS_NL_PORT_TYPE 0x02
1768#define NS_NX_PORT_TYPE 0x7F
1769
1770#define GA_NXT_CMD 0x100
1771#define GA_NXT_REQ_SIZE (16 + 4)
1772#define GA_NXT_RSP_SIZE (16 + 620)
1773
1774#define GID_PT_CMD 0x1A1
1775#define GID_PT_REQ_SIZE (16 + 4)
1776#define GID_PT_RSP_SIZE (16 + (MAX_FIBRE_DEVICES * 4))
1777
1778#define GPN_ID_CMD 0x112
1779#define GPN_ID_REQ_SIZE (16 + 4)
1780#define GPN_ID_RSP_SIZE (16 + 8)
1781
1782#define GNN_ID_CMD 0x113
1783#define GNN_ID_REQ_SIZE (16 + 4)
1784#define GNN_ID_RSP_SIZE (16 + 8)
1785
1786#define GFT_ID_CMD 0x117
1787#define GFT_ID_REQ_SIZE (16 + 4)
1788#define GFT_ID_RSP_SIZE (16 + 32)
1789
1790#define RFT_ID_CMD 0x217
1791#define RFT_ID_REQ_SIZE (16 + 4 + 32)
1792#define RFT_ID_RSP_SIZE 16
1793
1794#define RFF_ID_CMD 0x21F
1795#define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
1796#define RFF_ID_RSP_SIZE 16
1797
1798#define RNN_ID_CMD 0x213
1799#define RNN_ID_REQ_SIZE (16 + 4 + 8)
1800#define RNN_ID_RSP_SIZE 16
1801
1802#define RSNN_NN_CMD 0x239
1803#define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
1804#define RSNN_NN_RSP_SIZE 16
1805
d8b45213
AV
1806#define GFPN_ID_CMD 0x11C
1807#define GFPN_ID_REQ_SIZE (16 + 4)
1808#define GFPN_ID_RSP_SIZE (16 + 8)
1809
1810#define GPSC_CMD 0x127
1811#define GPSC_REQ_SIZE (16 + 8)
1812#define GPSC_RSP_SIZE (16 + 2 + 2)
1813
e8c72ba5
CD
1814#define GFF_ID_CMD 0x011F
1815#define GFF_ID_REQ_SIZE (16 + 4)
1816#define GFF_ID_RSP_SIZE (16 + 128)
d8b45213 1817
cca5335c
AV
1818/*
1819 * HBA attribute types.
1820 */
1821#define FDMI_HBA_ATTR_COUNT 9
1822#define FDMI_HBA_NODE_NAME 1
1823#define FDMI_HBA_MANUFACTURER 2
1824#define FDMI_HBA_SERIAL_NUMBER 3
1825#define FDMI_HBA_MODEL 4
1826#define FDMI_HBA_MODEL_DESCRIPTION 5
1827#define FDMI_HBA_HARDWARE_VERSION 6
1828#define FDMI_HBA_DRIVER_VERSION 7
1829#define FDMI_HBA_OPTION_ROM_VERSION 8
1830#define FDMI_HBA_FIRMWARE_VERSION 9
1831#define FDMI_HBA_OS_NAME_AND_VERSION 0xa
1832#define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
1833
1834struct ct_fdmi_hba_attr {
1835 uint16_t type;
1836 uint16_t len;
1837 union {
1838 uint8_t node_name[WWN_SIZE];
1839 uint8_t manufacturer[32];
1840 uint8_t serial_num[8];
1841 uint8_t model[16];
1842 uint8_t model_desc[80];
1843 uint8_t hw_version[16];
1844 uint8_t driver_version[32];
1845 uint8_t orom_version[16];
1846 uint8_t fw_version[16];
1847 uint8_t os_version[128];
1848 uint8_t max_ct_len[4];
1849 } a;
1850};
1851
1852struct ct_fdmi_hba_attributes {
1853 uint32_t count;
1854 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT];
1855};
1856
1857/*
1858 * Port attribute types.
1859 */
8a85e171 1860#define FDMI_PORT_ATTR_COUNT 6
cca5335c
AV
1861#define FDMI_PORT_FC4_TYPES 1
1862#define FDMI_PORT_SUPPORT_SPEED 2
1863#define FDMI_PORT_CURRENT_SPEED 3
1864#define FDMI_PORT_MAX_FRAME_SIZE 4
1865#define FDMI_PORT_OS_DEVICE_NAME 5
1866#define FDMI_PORT_HOST_NAME 6
1867
5881569b
AV
1868#define FDMI_PORT_SPEED_1GB 0x1
1869#define FDMI_PORT_SPEED_2GB 0x2
1870#define FDMI_PORT_SPEED_10GB 0x4
1871#define FDMI_PORT_SPEED_4GB 0x8
1872#define FDMI_PORT_SPEED_8GB 0x10
1873#define FDMI_PORT_SPEED_16GB 0x20
1874#define FDMI_PORT_SPEED_UNKNOWN 0x8000
1875
cca5335c
AV
1876struct ct_fdmi_port_attr {
1877 uint16_t type;
1878 uint16_t len;
1879 union {
1880 uint8_t fc4_types[32];
1881 uint32_t sup_speed;
1882 uint32_t cur_speed;
1883 uint32_t max_frame_size;
1884 uint8_t os_dev_name[32];
1885 uint8_t host_name[32];
1886 } a;
1887};
1888
1889/*
1890 * Port Attribute Block.
1891 */
1892struct ct_fdmi_port_attributes {
1893 uint32_t count;
1894 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT];
1895};
1896
1897/* FDMI definitions. */
1898#define GRHL_CMD 0x100
1899#define GHAT_CMD 0x101
1900#define GRPL_CMD 0x102
1901#define GPAT_CMD 0x110
1902
1903#define RHBA_CMD 0x200
1904#define RHBA_RSP_SIZE 16
1905
1906#define RHAT_CMD 0x201
1907#define RPRT_CMD 0x210
1908
1909#define RPA_CMD 0x211
1910#define RPA_RSP_SIZE 16
1911
1912#define DHBA_CMD 0x300
1913#define DHBA_REQ_SIZE (16 + 8)
1914#define DHBA_RSP_SIZE 16
1915
1916#define DHAT_CMD 0x301
1917#define DPRT_CMD 0x310
1918#define DPA_CMD 0x311
1919
1da177e4
LT
1920/* CT command header -- request/response common fields */
1921struct ct_cmd_hdr {
1922 uint8_t revision;
1923 uint8_t in_id[3];
1924 uint8_t gs_type;
1925 uint8_t gs_subtype;
1926 uint8_t options;
1927 uint8_t reserved;
1928};
1929
1930/* CT command request */
1931struct ct_sns_req {
1932 struct ct_cmd_hdr header;
1933 uint16_t command;
1934 uint16_t max_rsp_size;
1935 uint8_t fragment_id;
1936 uint8_t reserved[3];
1937
1938 union {
d8b45213 1939 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */
1da177e4
LT
1940 struct {
1941 uint8_t reserved;
1942 uint8_t port_id[3];
1943 } port_id;
1944
1945 struct {
1946 uint8_t port_type;
1947 uint8_t domain;
1948 uint8_t area;
1949 uint8_t reserved;
1950 } gid_pt;
1951
1952 struct {
1953 uint8_t reserved;
1954 uint8_t port_id[3];
1955 uint8_t fc4_types[32];
1956 } rft_id;
1957
1958 struct {
1959 uint8_t reserved;
1960 uint8_t port_id[3];
1961 uint16_t reserved2;
1962 uint8_t fc4_feature;
1963 uint8_t fc4_type;
1964 } rff_id;
1965
1966 struct {
1967 uint8_t reserved;
1968 uint8_t port_id[3];
1969 uint8_t node_name[8];
1970 } rnn_id;
1971
1972 struct {
1973 uint8_t node_name[8];
1974 uint8_t name_len;
1975 uint8_t sym_node_name[255];
1976 } rsnn_nn;
cca5335c
AV
1977
1978 struct {
1979 uint8_t hba_indentifier[8];
1980 } ghat;
1981
1982 struct {
1983 uint8_t hba_identifier[8];
1984 uint32_t entry_count;
1985 uint8_t port_name[8];
1986 struct ct_fdmi_hba_attributes attrs;
1987 } rhba;
1988
1989 struct {
1990 uint8_t hba_identifier[8];
1991 struct ct_fdmi_hba_attributes attrs;
1992 } rhat;
1993
1994 struct {
1995 uint8_t port_name[8];
1996 struct ct_fdmi_port_attributes attrs;
1997 } rpa;
1998
1999 struct {
2000 uint8_t port_name[8];
2001 } dhba;
2002
2003 struct {
2004 uint8_t port_name[8];
2005 } dhat;
2006
2007 struct {
2008 uint8_t port_name[8];
2009 } dprt;
2010
2011 struct {
2012 uint8_t port_name[8];
2013 } dpa;
d8b45213
AV
2014
2015 struct {
2016 uint8_t port_name[8];
2017 } gpsc;
e8c72ba5
CD
2018
2019 struct {
2020 uint8_t reserved;
2021 uint8_t port_name[3];
2022 } gff_id;
1da177e4
LT
2023 } req;
2024};
2025
2026/* CT command response header */
2027struct ct_rsp_hdr {
2028 struct ct_cmd_hdr header;
2029 uint16_t response;
2030 uint16_t residual;
2031 uint8_t fragment_id;
2032 uint8_t reason_code;
2033 uint8_t explanation_code;
2034 uint8_t vendor_unique;
2035};
2036
2037struct ct_sns_gid_pt_data {
2038 uint8_t control_byte;
2039 uint8_t port_id[3];
2040};
2041
2042struct ct_sns_rsp {
2043 struct ct_rsp_hdr header;
2044
2045 union {
2046 struct {
2047 uint8_t port_type;
2048 uint8_t port_id[3];
2049 uint8_t port_name[8];
2050 uint8_t sym_port_name_len;
2051 uint8_t sym_port_name[255];
2052 uint8_t node_name[8];
2053 uint8_t sym_node_name_len;
2054 uint8_t sym_node_name[255];
2055 uint8_t init_proc_assoc[8];
2056 uint8_t node_ip_addr[16];
2057 uint8_t class_of_service[4];
2058 uint8_t fc4_types[32];
2059 uint8_t ip_address[16];
2060 uint8_t fabric_port_name[8];
2061 uint8_t reserved;
2062 uint8_t hard_address[3];
2063 } ga_nxt;
2064
2065 struct {
2066 struct ct_sns_gid_pt_data entries[MAX_FIBRE_DEVICES];
2067 } gid_pt;
2068
2069 struct {
2070 uint8_t port_name[8];
2071 } gpn_id;
2072
2073 struct {
2074 uint8_t node_name[8];
2075 } gnn_id;
2076
2077 struct {
2078 uint8_t fc4_types[32];
2079 } gft_id;
cca5335c
AV
2080
2081 struct {
2082 uint32_t entry_count;
2083 uint8_t port_name[8];
2084 struct ct_fdmi_hba_attributes attrs;
2085 } ghat;
d8b45213
AV
2086
2087 struct {
2088 uint8_t port_name[8];
2089 } gfpn_id;
2090
2091 struct {
2092 uint16_t speeds;
2093 uint16_t speed;
2094 } gpsc;
e8c72ba5
CD
2095
2096#define GFF_FCP_SCSI_OFFSET 7
2097 struct {
2098 uint8_t fc4_features[128];
2099 } gff_id;
1da177e4
LT
2100 } rsp;
2101};
2102
2103struct ct_sns_pkt {
2104 union {
2105 struct ct_sns_req req;
2106 struct ct_sns_rsp rsp;
2107 } p;
2108};
2109
2110/*
25985edc 2111 * SNS command structures -- for 2200 compatibility.
1da177e4
LT
2112 */
2113#define RFT_ID_SNS_SCMD_LEN 22
2114#define RFT_ID_SNS_CMD_SIZE 60
2115#define RFT_ID_SNS_DATA_SIZE 16
2116
2117#define RNN_ID_SNS_SCMD_LEN 10
2118#define RNN_ID_SNS_CMD_SIZE 36
2119#define RNN_ID_SNS_DATA_SIZE 16
2120
2121#define GA_NXT_SNS_SCMD_LEN 6
2122#define GA_NXT_SNS_CMD_SIZE 28
2123#define GA_NXT_SNS_DATA_SIZE (620 + 16)
2124
2125#define GID_PT_SNS_SCMD_LEN 6
2126#define GID_PT_SNS_CMD_SIZE 28
2127#define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES * 4 + 16)
2128
2129#define GPN_ID_SNS_SCMD_LEN 6
2130#define GPN_ID_SNS_CMD_SIZE 28
2131#define GPN_ID_SNS_DATA_SIZE (8 + 16)
2132
2133#define GNN_ID_SNS_SCMD_LEN 6
2134#define GNN_ID_SNS_CMD_SIZE 28
2135#define GNN_ID_SNS_DATA_SIZE (8 + 16)
2136
2137struct sns_cmd_pkt {
2138 union {
2139 struct {
2140 uint16_t buffer_length;
2141 uint16_t reserved_1;
2142 uint32_t buffer_address[2];
2143 uint16_t subcommand_length;
2144 uint16_t reserved_2;
2145 uint16_t subcommand;
2146 uint16_t size;
2147 uint32_t reserved_3;
2148 uint8_t param[36];
2149 } cmd;
2150
2151 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
2152 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
2153 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
2154 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
2155 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
2156 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
2157 } p;
2158};
2159
5433383e
AV
2160struct fw_blob {
2161 char *name;
2162 uint32_t segs[4];
2163 const struct firmware *fw;
2164};
2165
1da177e4
LT
2166/* Return data from MBC_GET_ID_LIST call. */
2167struct gid_list_info {
2168 uint8_t al_pa;
2169 uint8_t area;
fa2a1ce5 2170 uint8_t domain;
1da177e4
LT
2171 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
2172 uint16_t loop_id; /* ISP23XX -- 6 bytes. */
3d71644c 2173 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */
1da177e4
LT
2174};
2175#define GID_LIST_SIZE (sizeof(struct gid_list_info) * MAX_FIBRE_DEVICES)
2176
2c3dfe3f
SJ
2177/* NPIV */
2178typedef struct vport_info {
2179 uint8_t port_name[WWN_SIZE];
2180 uint8_t node_name[WWN_SIZE];
2181 int vp_id;
2182 uint16_t loop_id;
2183 unsigned long host_no;
2184 uint8_t port_id[3];
2185 int loop_state;
2186} vport_info_t;
2187
2188typedef struct vport_params {
2189 uint8_t port_name[WWN_SIZE];
2190 uint8_t node_name[WWN_SIZE];
2191 uint32_t options;
2192#define VP_OPTS_RETRY_ENABLE BIT_0
2193#define VP_OPTS_VP_DISABLE BIT_1
2194} vport_params_t;
2195
2196/* NPIV - return codes of VP create and modify */
2197#define VP_RET_CODE_OK 0
2198#define VP_RET_CODE_FATAL 1
2199#define VP_RET_CODE_WRONG_ID 2
2200#define VP_RET_CODE_WWPN 3
2201#define VP_RET_CODE_RESOURCES 4
2202#define VP_RET_CODE_NO_MEM 5
2203#define VP_RET_CODE_NOT_FOUND 6
2204
7b867cf7 2205struct qla_hw_data;
2afa19a9 2206struct rsp_que;
abbd8870
AV
2207/*
2208 * ISP operations
2209 */
2210struct isp_operations {
2211
2212 int (*pci_config) (struct scsi_qla_host *);
2213 void (*reset_chip) (struct scsi_qla_host *);
2214 int (*chip_diag) (struct scsi_qla_host *);
2215 void (*config_rings) (struct scsi_qla_host *);
2216 void (*reset_adapter) (struct scsi_qla_host *);
2217 int (*nvram_config) (struct scsi_qla_host *);
2218 void (*update_fw_options) (struct scsi_qla_host *);
2219 int (*load_risc) (struct scsi_qla_host *, uint32_t *);
2220
2221 char * (*pci_info_str) (struct scsi_qla_host *, char *);
2222 char * (*fw_version_str) (struct scsi_qla_host *, char *);
2223
7d12e780 2224 irq_handler_t intr_handler;
7b867cf7
AC
2225 void (*enable_intrs) (struct qla_hw_data *);
2226 void (*disable_intrs) (struct qla_hw_data *);
abbd8870 2227
2afa19a9
AC
2228 int (*abort_command) (srb_t *);
2229 int (*target_reset) (struct fc_port *, unsigned int, int);
2230 int (*lun_reset) (struct fc_port *, unsigned int, int);
abbd8870
AV
2231 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
2232 uint8_t, uint8_t, uint16_t *, uint8_t);
1c7c6357
AV
2233 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
2234 uint8_t, uint8_t);
abbd8870
AV
2235
2236 uint16_t (*calc_req_entries) (uint16_t);
2237 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
8c958a99 2238 void * (*prep_ms_iocb) (struct scsi_qla_host *, uint32_t, uint32_t);
cca5335c
AV
2239 void * (*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
2240 uint32_t);
abbd8870
AV
2241
2242 uint8_t * (*read_nvram) (struct scsi_qla_host *, uint8_t *,
2243 uint32_t, uint32_t);
2244 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t,
2245 uint32_t);
2246
2247 void (*fw_dump) (struct scsi_qla_host *, int);
f6df144c
AV
2248
2249 int (*beacon_on) (struct scsi_qla_host *);
2250 int (*beacon_off) (struct scsi_qla_host *);
2251 void (*beacon_blink) (struct scsi_qla_host *);
854165f4
AV
2252
2253 uint8_t * (*read_optrom) (struct scsi_qla_host *, uint8_t *,
2254 uint32_t, uint32_t);
2255 int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t,
2256 uint32_t);
30c47662
AV
2257
2258 int (*get_flash_version) (struct scsi_qla_host *, void *);
7b867cf7 2259 int (*start_scsi) (srb_t *);
a9083016 2260 int (*abort_isp) (struct scsi_qla_host *);
706f457d 2261 int (*iospace_config)(struct qla_hw_data*);
abbd8870
AV
2262};
2263
a8488abe
AV
2264/* MSI-X Support *************************************************************/
2265
2266#define QLA_MSIX_CHIP_REV_24XX 3
2267#define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7)
2268#define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1)
2269
2270#define QLA_MSIX_DEFAULT 0x00
2271#define QLA_MSIX_RSP_Q 0x01
2272
a8488abe
AV
2273#define QLA_MIDX_DEFAULT 0
2274#define QLA_MIDX_RSP_Q 1
73208dfd 2275#define QLA_PCI_MSIX_CONTROL 0xa2
6246b8a1 2276#define QLA_83XX_PCI_MSIX_CONTROL 0x92
a8488abe
AV
2277
2278struct scsi_qla_host;
2279
2280struct qla_msix_entry {
2281 int have_irq;
73208dfd
AC
2282 uint32_t vector;
2283 uint16_t entry;
2284 struct rsp_que *rsp;
a8488abe
AV
2285};
2286
2c3dfe3f
SJ
2287#define WATCH_INTERVAL 1 /* number of seconds */
2288
0971de7f
AV
2289/* Work events. */
2290enum qla_work_type {
2291 QLA_EVT_AEN,
8a659571 2292 QLA_EVT_IDC_ACK,
ac280b67
AV
2293 QLA_EVT_ASYNC_LOGIN,
2294 QLA_EVT_ASYNC_LOGIN_DONE,
2295 QLA_EVT_ASYNC_LOGOUT,
2296 QLA_EVT_ASYNC_LOGOUT_DONE,
5ff1d584
AV
2297 QLA_EVT_ASYNC_ADISC,
2298 QLA_EVT_ASYNC_ADISC_DONE,
3420d36c 2299 QLA_EVT_UEVENT,
0971de7f
AV
2300};
2301
2302
2303struct qla_work_evt {
2304 struct list_head list;
2305 enum qla_work_type type;
2306 u32 flags;
2307#define QLA_EVT_FLAG_FREE 0x1
2308
2309 union {
2310 struct {
2311 enum fc_host_event_code code;
2312 u32 data;
2313 } aen;
8a659571
AV
2314 struct {
2315#define QLA_IDC_ACK_REGS 7
2316 uint16_t mb[QLA_IDC_ACK_REGS];
2317 } idc_ack;
ac280b67
AV
2318 struct {
2319 struct fc_port *fcport;
2320#define QLA_LOGIO_LOGIN_RETRIED BIT_0
2321 u16 data[2];
2322 } logio;
3420d36c
AV
2323 struct {
2324 u32 code;
2325#define QLA_UEVENT_CODE_FW_DUMP 0
2326 } uevent;
0971de7f
AV
2327 } u;
2328};
2329
4d4df193
HK
2330struct qla_chip_state_84xx {
2331 struct list_head list;
2332 struct kref kref;
2333
2334 void *bus;
2335 spinlock_t access_lock;
2336 struct mutex fw_update_mutex;
2337 uint32_t fw_update;
2338 uint32_t op_fw_version;
2339 uint32_t op_fw_size;
2340 uint32_t op_fw_seq_size;
2341 uint32_t diag_fw_version;
2342 uint32_t gold_fw_version;
2343};
2344
e5f5f6f7
HZ
2345struct qla_statistics {
2346 uint32_t total_isp_aborts;
49fd462a
HZ
2347 uint64_t input_bytes;
2348 uint64_t output_bytes;
e5f5f6f7
HZ
2349};
2350
73208dfd
AC
2351/* Multi queue support */
2352#define MBC_INITIALIZE_MULTIQ 0x1f
2353#define QLA_QUE_PAGE 0X1000
2354#define QLA_MQ_SIZE 32
73208dfd
AC
2355#define QLA_MAX_QUEUES 256
2356#define ISP_QUE_REG(ha, id) \
6246b8a1 2357 ((ha->mqenable || IS_QLA83XX(ha)) ? \
73208dfd
AC
2358 ((void *)(ha->mqiobase) +\
2359 (QLA_QUE_PAGE * id)) :\
2360 ((void *)(ha->iobase)))
2361#define QLA_REQ_QUE_ID(tag) \
2362 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0)
2363#define QLA_DEFAULT_QUE_QOS 5
2364#define QLA_PRECONFIG_VPORTS 32
2365#define QLA_MAX_VPORTS_QLA24XX 128
2366#define QLA_MAX_VPORTS_QLA25XX 256
7b867cf7
AC
2367/* Response queue data structure */
2368struct rsp_que {
2369 dma_addr_t dma;
2370 response_t *ring;
2371 response_t *ring_ptr;
08029990
AV
2372 uint32_t __iomem *rsp_q_in; /* FWI2-capable only. */
2373 uint32_t __iomem *rsp_q_out;
7b867cf7
AC
2374 uint16_t ring_index;
2375 uint16_t out_ptr;
2376 uint16_t length;
2377 uint16_t options;
7b867cf7 2378 uint16_t rid;
73208dfd
AC
2379 uint16_t id;
2380 uint16_t vp_idx;
7b867cf7 2381 struct qla_hw_data *hw;
73208dfd
AC
2382 struct qla_msix_entry *msix;
2383 struct req_que *req;
2afa19a9 2384 srb_t *status_srb; /* status continuation entry */
68ca949c 2385 struct work_struct q_work;
7b867cf7 2386};
1da177e4 2387
7b867cf7
AC
2388/* Request queue data structure */
2389struct req_que {
2390 dma_addr_t dma;
2391 request_t *ring;
2392 request_t *ring_ptr;
08029990
AV
2393 uint32_t __iomem *req_q_in; /* FWI2-capable only. */
2394 uint32_t __iomem *req_q_out;
7b867cf7
AC
2395 uint16_t ring_index;
2396 uint16_t in_ptr;
2397 uint16_t cnt;
2398 uint16_t length;
2399 uint16_t options;
2400 uint16_t rid;
73208dfd 2401 uint16_t id;
7b867cf7
AC
2402 uint16_t qos;
2403 uint16_t vp_idx;
73208dfd 2404 struct rsp_que *rsp;
7b867cf7
AC
2405 srb_t *outstanding_cmds[MAX_OUTSTANDING_COMMANDS];
2406 uint32_t current_outstanding_cmd;
2407 int max_q_depth;
2408};
1da177e4 2409
9a069e19
GM
2410/* Place holder for FW buffer parameters */
2411struct qlfc_fw {
2412 void *fw_buf;
2413 dma_addr_t fw_dma;
2414 uint32_t len;
2415};
2416
7b867cf7
AC
2417/*
2418 * Qlogic host adapter specific data structure.
2419*/
2420struct qla_hw_data {
2421 struct pci_dev *pdev;
2422 /* SRB cache. */
2423#define SRB_MIN_REQ 128
2424 mempool_t *srb_mempool;
1da177e4
LT
2425
2426 volatile struct {
1da177e4
LT
2427 uint32_t mbox_int :1;
2428 uint32_t mbox_busy :1;
1da177e4
LT
2429 uint32_t disable_risc_code_load :1;
2430 uint32_t enable_64bit_addressing :1;
2431 uint32_t enable_lip_reset :1;
1da177e4 2432 uint32_t enable_target_reset :1;
7b867cf7 2433 uint32_t enable_lip_full_login :1;
1da177e4 2434 uint32_t enable_led_scheme :1;
7190575f 2435
3d71644c
AV
2436 uint32_t msi_enabled :1;
2437 uint32_t msix_enabled :1;
d4c760c2 2438 uint32_t disable_serdes :1;
4346b149 2439 uint32_t gpsc_supported :1;
2c3dfe3f 2440 uint32_t npiv_supported :1;
85880801 2441 uint32_t pci_channel_io_perm_failure :1;
df613b96 2442 uint32_t fce_enabled :1;
1d2874de 2443 uint32_t fac_supported :1;
7190575f 2444
2533cf67 2445 uint32_t chip_reset_done :1;
e5b68a61 2446 uint32_t port0 :1;
cbc8eb67 2447 uint32_t running_gold_fw :1;
85880801 2448 uint32_t eeh_busy :1;
7163ea81 2449 uint32_t cpu_affinity_enabled :1;
3155754a 2450 uint32_t disable_msix_handshake :1;
09ff701a 2451 uint32_t fcp_prio_enabled :1;
7190575f
GM
2452 uint32_t isp82xx_fw_hung:1;
2453
2454 uint32_t quiesce_owner:1;
794a5691 2455 uint32_t thermal_supported:1;
7190575f 2456 uint32_t isp82xx_reset_hdlr_active:1;
08de2844
GM
2457 uint32_t isp82xx_reset_owner:1;
2458 /* 28 bits */
1da177e4
LT
2459 } flags;
2460
fa2a1ce5 2461 /* This spinlock is used to protect "io transactions", you must
7b867cf7
AC
2462 * acquire it before doing any IO to the card, eg with RD_REG*() and
2463 * WRT_REG*() for the duration of your entire commandtransaction.
2464 *
2465 * This spinlock is of lower priority than the io request lock.
2466 */
1da177e4 2467
7b867cf7 2468 spinlock_t hardware_lock ____cacheline_aligned;
285d0321 2469 int bars;
09483916 2470 int mem_only;
7b867cf7 2471 device_reg_t __iomem *iobase; /* Base I/O address */
3776541d 2472 resource_size_t pio_address;
fa2a1ce5 2473
7b867cf7 2474#define MIN_IOBASE_LEN 0x100
73208dfd 2475/* Multi queue data structs */
08029990 2476 device_reg_t __iomem *mqiobase;
6246b8a1 2477 device_reg_t __iomem *msixbase;
73208dfd
AC
2478 uint16_t msix_count;
2479 uint8_t mqenable;
2480 struct req_que **req_q_map;
2481 struct rsp_que **rsp_q_map;
2482 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
2483 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
2afa19a9
AC
2484 uint8_t max_req_queues;
2485 uint8_t max_rsp_queues;
73208dfd
AC
2486 struct qla_npiv_entry *npiv_info;
2487 uint16_t nvram_npiv_size;
1da177e4 2488
7b867cf7
AC
2489 uint16_t switch_cap;
2490#define FLOGI_SEQ_DEL BIT_8
2491#define FLOGI_MID_SUPPORT BIT_10
2492#define FLOGI_VSAN_SUPPORT BIT_12
2493#define FLOGI_SP_SUPPORT BIT_13
e5b68a61
AC
2494
2495 uint8_t port_no; /* Physical port of adapter */
2496
7b867cf7
AC
2497 /* Timeout timers. */
2498 uint8_t loop_down_abort_time; /* port down timer */
2499 atomic_t loop_down_timer; /* loop down timer */
2500 uint8_t link_down_timeout; /* link down timeout */
2501 uint16_t max_loop_id;
1da177e4 2502
1da177e4 2503 uint16_t fb_rev;
7b867cf7 2504 uint16_t min_external_loopid; /* First external loop Id */
1da177e4 2505
d8b45213 2506#define PORT_SPEED_UNKNOWN 0xFFFF
7b867cf7
AC
2507#define PORT_SPEED_1GB 0x00
2508#define PORT_SPEED_2GB 0x01
2509#define PORT_SPEED_4GB 0x03
2510#define PORT_SPEED_8GB 0x04
6246b8a1 2511#define PORT_SPEED_16GB 0x05
3a03eb79 2512#define PORT_SPEED_10GB 0x13
7b867cf7 2513 uint16_t link_data_rate; /* F/W operating speed */
1da177e4
LT
2514
2515 uint8_t current_topology;
2516 uint8_t prev_topology;
2517#define ISP_CFG_NL 1
2518#define ISP_CFG_N 2
2519#define ISP_CFG_FL 4
2520#define ISP_CFG_F 8
2521
7b867cf7 2522 uint8_t operating_mode; /* F/W operating mode */
1da177e4
LT
2523#define LOOP 0
2524#define P2P 1
2525#define LOOP_P2P 2
2526#define P2P_LOOP 3
1da177e4 2527 uint8_t interrupts_on;
7b867cf7
AC
2528 uint32_t isp_abort_cnt;
2529
2530#define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532
2531#define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432
3a03eb79 2532#define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001
6246b8a1
GM
2533#define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031
2534#define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031
7b867cf7
AC
2535 uint32_t device_type;
2536#define DT_ISP2100 BIT_0
2537#define DT_ISP2200 BIT_1
2538#define DT_ISP2300 BIT_2
2539#define DT_ISP2312 BIT_3
2540#define DT_ISP2322 BIT_4
2541#define DT_ISP6312 BIT_5
2542#define DT_ISP6322 BIT_6
2543#define DT_ISP2422 BIT_7
2544#define DT_ISP2432 BIT_8
2545#define DT_ISP5422 BIT_9
2546#define DT_ISP5432 BIT_10
2547#define DT_ISP2532 BIT_11
2548#define DT_ISP8432 BIT_12
3a03eb79 2549#define DT_ISP8001 BIT_13
a9083016 2550#define DT_ISP8021 BIT_14
6246b8a1
GM
2551#define DT_ISP2031 BIT_15
2552#define DT_ISP8031 BIT_16
2553#define DT_ISP_LAST (DT_ISP8031 << 1)
7b867cf7 2554
e02587d7 2555#define DT_T10_PI BIT_25
7b867cf7
AC
2556#define DT_IIDMA BIT_26
2557#define DT_FWI2 BIT_27
2558#define DT_ZIO_SUPPORTED BIT_28
2559#define DT_OEM_001 BIT_29
2560#define DT_ISP2200A BIT_30
2561#define DT_EXTENDED_IDS BIT_31
2562#define DT_MASK(ha) ((ha)->device_type & (DT_ISP_LAST - 1))
2563#define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100)
2564#define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200)
2565#define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300)
2566#define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312)
2567#define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322)
2568#define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312)
2569#define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322)
2570#define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422)
2571#define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432)
2572#define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422)
2573#define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432)
2574#define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532)
2575#define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432)
3a03eb79 2576#define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001)
6246b8a1 2577#define IS_QLA81XX(ha) (IS_QLA8001(ha))
a9083016 2578#define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021)
6246b8a1
GM
2579#define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031)
2580#define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031)
7b867cf7
AC
2581
2582#define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
2583 IS_QLA6312(ha) || IS_QLA6322(ha))
2584#define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
2585#define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha))
2586#define IS_QLA25XX(ha) (IS_QLA2532(ha))
6246b8a1 2587#define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha))
7b867cf7
AC
2588#define IS_QLA84XX(ha) (IS_QLA8432(ha))
2589#define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \
2590 IS_QLA84XX(ha))
6246b8a1
GM
2591#define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \
2592 IS_QLA8031(ha))
7b867cf7 2593#define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \
a9083016 2594 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \
6246b8a1
GM
2595 IS_QLA82XX(ha) || IS_QLA83XX(ha))
2596#define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha))
2597#define IS_NOPOLLING_TYPE(ha) ((IS_QLA25XX(ha) || IS_QLA81XX(ha) || \
2598 IS_QLA83XX(ha)) && (ha)->flags.msix_enabled)
2599#define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha))
2600#define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha))
ac280b67 2601#define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha))
7b867cf7 2602
e02587d7 2603#define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI)
7b867cf7
AC
2604#define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA)
2605#define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2)
2606#define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED)
2607#define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001)
2608#define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS)
6246b8a1
GM
2609#define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED)
2610#define IS_MQUE_CAPABLE(ha) ((ha)->mqenable || IS_QLA83XX(ha))
1da177e4
LT
2611
2612 /* HBA serial number */
2613 uint8_t serial0;
2614 uint8_t serial1;
2615 uint8_t serial2;
2616
2617 /* NVRAM configuration data */
7b867cf7
AC
2618#define MAX_NVRAM_SIZE 4096
2619#define VPD_OFFSET MAX_NVRAM_SIZE / 2
3d71644c 2620 uint16_t nvram_size;
1da177e4 2621 uint16_t nvram_base;
281afe19 2622 void *nvram;
6f641790
AV
2623 uint16_t vpd_size;
2624 uint16_t vpd_base;
281afe19 2625 void *vpd;
1da177e4
LT
2626
2627 uint16_t loop_reset_delay;
1da177e4
LT
2628 uint8_t retry_count;
2629 uint8_t login_timeout;
2630 uint16_t r_a_tov;
2631 int port_down_retry_count;
1da177e4 2632 uint8_t mbx_count;
1da177e4 2633
7b867cf7 2634 uint32_t login_retry_count;
1da177e4
LT
2635 /* SNS command interfaces. */
2636 ms_iocb_entry_t *ms_iocb;
2637 dma_addr_t ms_iocb_dma;
2638 struct ct_sns_pkt *ct_sns;
2639 dma_addr_t ct_sns_dma;
2640 /* SNS command interfaces for 2200. */
2641 struct sns_cmd_pkt *sns_cmd;
2642 dma_addr_t sns_cmd_dma;
2643
7b867cf7
AC
2644#define SFP_DEV_SIZE 256
2645#define SFP_BLOCK_SIZE 64
2646 void *sfp_data;
2647 dma_addr_t sfp_data_dma;
88729e53 2648
ad0ecd61
JC
2649 uint8_t *edc_data;
2650 dma_addr_t edc_data_dma;
2651 uint16_t edc_data_len;
2652
b5d0329f 2653#define XGMAC_DATA_SIZE 4096
ce0423f4
AV
2654 void *xgmac_data;
2655 dma_addr_t xgmac_data_dma;
2656
b5d0329f 2657#define DCBX_TLV_DATA_SIZE 4096
11bbc1d8
AV
2658 void *dcbx_tlv;
2659 dma_addr_t dcbx_tlv_dma;
2660
39a11240 2661 struct task_struct *dpc_thread;
1da177e4
LT
2662 uint8_t dpc_active; /* DPC routine is active */
2663
1da177e4
LT
2664 dma_addr_t gid_list_dma;
2665 struct gid_list_info *gid_list;
abbd8870 2666 int gid_list_info_size;
1da177e4 2667
fa2a1ce5 2668 /* Small DMA pool allocations -- maximum 256 bytes in length. */
7b867cf7 2669#define DMA_POOL_SIZE 256
1da177e4
LT
2670 struct dma_pool *s_dma_pool;
2671
2672 dma_addr_t init_cb_dma;
3d71644c
AV
2673 init_cb_t *init_cb;
2674 int init_cb_size;
b64b0e8f
AV
2675 dma_addr_t ex_init_cb_dma;
2676 struct ex_init_cb_81xx *ex_init_cb;
1da177e4 2677
5ff1d584
AV
2678 void *async_pd;
2679 dma_addr_t async_pd_dma;
2680
1da177e4
LT
2681 /* These are used by mailbox operations. */
2682 volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
2683
2684 mbx_cmd_t *mcp;
2685 unsigned long mbx_cmd_flags;
7b867cf7
AC
2686#define MBX_INTERRUPT 1
2687#define MBX_INTR_WAIT 2
1da177e4
LT
2688#define MBX_UPDATE_FLASH_ACTIVE 3
2689
7b867cf7 2690 struct mutex vport_lock; /* Virtual port synchronization */
feafb7b1 2691 spinlock_t vport_slock; /* order is hardware_lock, then vport_slock */
7b867cf7 2692 struct completion mbx_cmd_comp; /* Serialize mbx access */
0b05a1f0 2693 struct completion mbx_intr_comp; /* Used for completion notification */
23f2ebd1
SR
2694 struct completion dcbx_comp; /* For set port config notification */
2695 int notify_dcbx_comp;
1da177e4 2696
1da177e4 2697 /* Basic firmware related information. */
1da177e4
LT
2698 uint16_t fw_major_version;
2699 uint16_t fw_minor_version;
2700 uint16_t fw_subminor_version;
2701 uint16_t fw_attributes;
6246b8a1
GM
2702 uint16_t fw_attributes_h;
2703 uint16_t fw_attributes_ext[2];
1da177e4
LT
2704 uint32_t fw_memory_size;
2705 uint32_t fw_transfer_size;
441d1072
AV
2706 uint32_t fw_srisc_address;
2707#define RISC_START_ADDRESS_2100 0x1000
2708#define RISC_START_ADDRESS_2300 0x800
2709#define RISC_START_ADDRESS_2400 0x100000
24a08138 2710 uint16_t fw_xcb_count;
1da177e4 2711
7b867cf7 2712 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
1da177e4 2713 uint8_t fw_seriallink_options[4];
3d71644c 2714 uint16_t fw_seriallink_options24[4];
1da177e4 2715
55a96158 2716 uint8_t mpi_version[3];
3a03eb79 2717 uint32_t mpi_capabilities;
55a96158 2718 uint8_t phy_version[3];
3a03eb79 2719
1da177e4 2720 /* Firmware dump information. */
a7a167bf
AV
2721 struct qla2xxx_fw_dump *fw_dump;
2722 uint32_t fw_dump_len;
d4e3e04d 2723 int fw_dumped;
1da177e4 2724 int fw_dump_reading;
a7a167bf
AV
2725 dma_addr_t eft_dma;
2726 void *eft;
1da177e4 2727
bb99de67 2728 uint32_t chain_offset;
df613b96
AV
2729 struct dentry *dfs_dir;
2730 struct dentry *dfs_fce;
2731 dma_addr_t fce_dma;
2732 void *fce;
2733 uint32_t fce_bufs;
2734 uint16_t fce_mb[8];
2735 uint64_t fce_wr, fce_rd;
2736 struct mutex fce_mutex;
2737
3d71644c 2738 uint32_t pci_attr;
a8488abe 2739 uint16_t chip_revision;
1da177e4
LT
2740
2741 uint16_t product_id[4];
2742
2743 uint8_t model_number[16+1];
2744#define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
1ee27146 2745 char model_desc[80];
cca5335c 2746 uint8_t adapter_id[16+1];
1da177e4 2747
854165f4
AV
2748 /* Option ROM information. */
2749 char *optrom_buffer;
2750 uint32_t optrom_size;
2751 int optrom_state;
2752#define QLA_SWAITING 0
2753#define QLA_SREADING 1
2754#define QLA_SWRITING 2
b7cc176c
JC
2755 uint32_t optrom_region_start;
2756 uint32_t optrom_region_size;
854165f4 2757
7b867cf7 2758/* PCI expansion ROM image information. */
30c47662
AV
2759#define ROM_CODE_TYPE_BIOS 0
2760#define ROM_CODE_TYPE_FCODE 1
2761#define ROM_CODE_TYPE_EFI 3
7b867cf7
AC
2762 uint8_t bios_revision[2];
2763 uint8_t efi_revision[2];
2764 uint8_t fcode_revision[16];
30c47662
AV
2765 uint32_t fw_revision[4];
2766
0f2d962f
MI
2767 uint32_t gold_fw_version[4];
2768
3a03eb79
AV
2769 /* Offsets for flash/nvram access (set to ~0 if not used). */
2770 uint32_t flash_conf_off;
2771 uint32_t flash_data_off;
2772 uint32_t nvram_conf_off;
2773 uint32_t nvram_data_off;
2774
7d232c74
AV
2775 uint32_t fdt_wrt_disable;
2776 uint32_t fdt_erase_cmd;
2777 uint32_t fdt_block_size;
2778 uint32_t fdt_unprotect_sec_cmd;
2779 uint32_t fdt_protect_sec_cmd;
2780
7b867cf7
AC
2781 uint32_t flt_region_flt;
2782 uint32_t flt_region_fdt;
2783 uint32_t flt_region_boot;
2784 uint32_t flt_region_fw;
2785 uint32_t flt_region_vpd_nvram;
3d79038f
AV
2786 uint32_t flt_region_vpd;
2787 uint32_t flt_region_nvram;
7b867cf7 2788 uint32_t flt_region_npiv_conf;
cbc8eb67 2789 uint32_t flt_region_gold_fw;
09ff701a 2790 uint32_t flt_region_fcp_prio;
a9083016 2791 uint32_t flt_region_bootload;
c00d8994 2792
1da177e4 2793 /* Needed for BEACON */
7b867cf7
AC
2794 uint16_t beacon_blink_led;
2795 uint8_t beacon_color_state;
f6df144c
AV
2796#define QLA_LED_GRN_ON 0x01
2797#define QLA_LED_YLW_ON 0x02
2798#define QLA_LED_ABR_ON 0x04
2799#define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */
2800 /* ISP2322: red, green, amber. */
7b867cf7
AC
2801 uint16_t zio_mode;
2802 uint16_t zio_timer;
392e2f65 2803 struct fc_host_statistics fc_host_stat;
a8488abe 2804
73208dfd 2805 struct qla_msix_entry *msix_entries;
2c3dfe3f 2806
7b867cf7
AC
2807 struct list_head vp_list; /* list of VP */
2808 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) /
2809 sizeof(unsigned long)];
2810 uint16_t num_vhosts; /* number of vports created */
2811 uint16_t num_vsans; /* number of vsan created */
2812 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */
2813 int cur_vport_count;
2814
2815 struct qla_chip_state_84xx *cs84xx;
2816 struct qla_statistics qla_stats;
2817 struct isp_operations *isp_ops;
68ca949c 2818 struct workqueue_struct *wq;
9a069e19 2819 struct qlfc_fw fw_buf;
09ff701a
SR
2820
2821 /* FCP_CMND priority support */
2822 struct qla_fcp_prio_cfg *fcp_prio_cfg;
a9083016
GM
2823
2824 struct dma_pool *dl_dma_pool;
2825#define DSD_LIST_DMA_POOL_SIZE 512
2826
2827 struct dma_pool *fcp_cmnd_dma_pool;
2828 mempool_t *ctx_mempool;
2829#define FCP_CMND_DMA_POOL_SIZE 512
2830
2831 unsigned long nx_pcibase; /* Base I/O address */
2832 uint8_t *nxdb_rd_ptr; /* Doorbell read pointer */
2833 unsigned long nxdb_wr_ptr; /* Door bell write pointer */
a9083016
GM
2834
2835 uint32_t crb_win;
2836 uint32_t curr_window;
2837 uint32_t ddr_mn_window;
2838 unsigned long mn_win_crb;
2839 unsigned long ms_win_crb;
2840 int qdr_sn_window;
2841 uint32_t nx_dev_init_timeout;
2842 uint32_t nx_reset_timeout;
2843 rwlock_t hw_lock;
2844 uint16_t portnum; /* port number */
2845 int link_width;
2846 struct fw_blob *hablob;
2847 struct qla82xx_legacy_intr_set nx_legacy_intr;
2848
2849 uint16_t gbl_dsd_inuse;
2850 uint16_t gbl_dsd_avail;
2851 struct list_head gbl_dsd_list;
2852#define NUM_DSD_CHAIN 4096
9c2b2975
HZ
2853
2854 uint8_t fw_type;
2855 __le32 file_prd_off; /* File firmware product offset */
08de2844
GM
2856
2857 uint32_t md_template_size;
2858 void *md_tmplt_hdr;
2859 dma_addr_t md_tmplt_hdr_dma;
2860 void *md_dump;
2861 uint32_t md_dump_size;
7b867cf7
AC
2862};
2863
2864/*
2865 * Qlogic scsi host structure
2866 */
2867typedef struct scsi_qla_host {
2868 struct list_head list;
2869 struct list_head vp_fcports; /* list of fcports */
2870 struct list_head work_list;
f999f4c1
AV
2871 spinlock_t work_lock;
2872
7b867cf7
AC
2873 /* Commonly used flags and state information. */
2874 struct Scsi_Host *host;
2875 unsigned long host_no;
2876 uint8_t host_str[16];
2877
2878 volatile struct {
2879 uint32_t init_done :1;
2880 uint32_t online :1;
7b867cf7
AC
2881 uint32_t reset_active :1;
2882
2883 uint32_t management_server_logged_in :1;
2884 uint32_t process_response_queue :1;
bad75002 2885 uint32_t difdix_supported:1;
feafb7b1 2886 uint32_t delete_progress:1;
7b867cf7
AC
2887 } flags;
2888
2889 atomic_t loop_state;
2890#define LOOP_TIMEOUT 1
2891#define LOOP_DOWN 2
2892#define LOOP_UP 3
2893#define LOOP_UPDATE 4
2894#define LOOP_READY 5
2895#define LOOP_DEAD 6
2896
2897 unsigned long dpc_flags;
2898#define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
2899#define RESET_ACTIVE 1
2900#define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
2901#define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
2902#define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
2903#define LOOP_RESYNC_ACTIVE 5
2904#define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
2905#define RSCN_UPDATE 7 /* Perform an RSCN update. */
ddb9b126
SS
2906#define RELOGIN_NEEDED 8
2907#define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */
2908#define ISP_ABORT_RETRY 10 /* ISP aborted. */
2909#define BEACON_BLINK_NEEDED 11
2910#define REGISTER_FDMI_NEEDED 12
2911#define FCPORT_UPDATE_NEEDED 13
2912#define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */
2913#define UNLOADING 15
2914#define NPIV_CONFIG_NEEDED 16
a9083016
GM
2915#define ISP_UNRECOVERABLE 17
2916#define FCOE_CTX_RESET_NEEDED 18 /* Initiate FCoE context reset */
b1d46989 2917#define MPI_RESET_NEEDED 19 /* Initiate MPI FW reset */
579d12b5 2918#define ISP_QUIESCE_NEEDED 20 /* Driver need some quiescence */
7b867cf7
AC
2919
2920 uint32_t device_flags;
ddb9b126
SS
2921#define SWITCH_FOUND BIT_0
2922#define DFLG_NO_CABLE BIT_1
a9083016 2923#define DFLG_DEV_FAILED BIT_5
7b867cf7 2924
7b867cf7
AC
2925 /* ISP configuration data. */
2926 uint16_t loop_id; /* Host adapter loop id */
2927
2928 port_id_t d_id; /* Host adapter port id */
2929 uint8_t marker_needed;
2930 uint16_t mgmt_svr_loop_id;
2931
2932
2933
7b867cf7
AC
2934 /* Timeout timers. */
2935 uint8_t loop_down_abort_time; /* port down timer */
2936 atomic_t loop_down_timer; /* loop down timer */
2937 uint8_t link_down_timeout; /* link down timeout */
2938
2939 uint32_t timer_active;
2940 struct timer_list timer;
2941
2942 uint8_t node_name[WWN_SIZE];
2943 uint8_t port_name[WWN_SIZE];
2944 uint8_t fabric_node_name[WWN_SIZE];
bad7001c
AV
2945
2946 uint16_t fcoe_vlan_id;
2947 uint16_t fcoe_fcf_idx;
2948 uint8_t fcoe_vn_port_mac[6];
2949
7b867cf7
AC
2950 uint32_t vp_abort_cnt;
2951
2c3dfe3f 2952 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */
2c3dfe3f
SJ
2953 uint16_t vp_idx; /* vport ID */
2954
2c3dfe3f 2955 unsigned long vp_flags;
2c3dfe3f
SJ
2956#define VP_IDX_ACQUIRED 0 /* bit no 0 */
2957#define VP_CREATE_NEEDED 1
2958#define VP_BIND_NEEDED 2
2959#define VP_DELETE_NEEDED 3
2960#define VP_SCR_NEEDED 4 /* State Change Request registration */
2961 atomic_t vp_state;
2962#define VP_OFFLINE 0
2963#define VP_ACTIVE 1
2964#define VP_FAILED 2
2965// #define VP_DISABLE 3
2966 uint16_t vp_err_state;
2967 uint16_t vp_prev_err_state;
2968#define VP_ERR_UNKWN 0
2969#define VP_ERR_PORTDWN 1
2970#define VP_ERR_FAB_UNSUPPORTED 2
2971#define VP_ERR_FAB_NORESOURCES 3
2972#define VP_ERR_FAB_LOGOUT 4
2973#define VP_ERR_ADAP_NORESOURCES 5
7b867cf7 2974 struct qla_hw_data *hw;
2afa19a9 2975 struct req_que *req;
a9083016
GM
2976 int fw_heartbeat_counter;
2977 int seconds_since_last_heartbeat;
feafb7b1
AE
2978
2979 atomic_t vref_count;
1da177e4
LT
2980} scsi_qla_host_t;
2981
1da177e4
LT
2982/*
2983 * Macros to help code, maintain, etc.
2984 */
2985#define LOOP_TRANSITION(ha) \
2986 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
23443b1d 2987 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
1da177e4 2988 atomic_read(&ha->loop_state) == LOOP_DOWN)
fa2a1ce5 2989
feafb7b1
AE
2990#define QLA_VHA_MARK_BUSY(__vha, __bail) do { \
2991 atomic_inc(&__vha->vref_count); \
2992 mb(); \
2993 if (__vha->flags.delete_progress) { \
2994 atomic_dec(&__vha->vref_count); \
2995 __bail = 1; \
2996 } else { \
2997 __bail = 0; \
2998 } \
2999} while (0)
3000
3001#define QLA_VHA_MARK_NOT_BUSY(__vha) do { \
3002 atomic_dec(&__vha->vref_count); \
3003} while (0)
3004
1da177e4
LT
3005/*
3006 * qla2x00 local function return status codes
3007 */
3008#define MBS_MASK 0x3fff
3009
3010#define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
3011#define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
3012#define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
3013#define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
3014#define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
3015#define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
3016#define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
3017#define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
3018#define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
3019#define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
3020
3021#define QLA_FUNCTION_TIMEOUT 0x100
3022#define QLA_FUNCTION_PARAMETER_ERROR 0x101
3023#define QLA_FUNCTION_FAILED 0x102
3024#define QLA_MEMORY_ALLOC_FAILED 0x103
3025#define QLA_LOCK_TIMEOUT 0x104
3026#define QLA_ABORTED 0x105
3027#define QLA_SUSPENDED 0x106
3028#define QLA_BUSY 0x107
cca5335c 3029#define QLA_ALREADY_REGISTERED 0x109
1da177e4 3030
1da177e4
LT
3031#define NVRAM_DELAY() udelay(10)
3032
3033#define INVALID_HANDLE (MAX_OUTSTANDING_COMMANDS+1)
3034
3035/*
3036 * Flash support definitions
3037 */
854165f4
AV
3038#define OPTROM_SIZE_2300 0x20000
3039#define OPTROM_SIZE_2322 0x100000
3040#define OPTROM_SIZE_24XX 0x100000
c3a2f0df 3041#define OPTROM_SIZE_25XX 0x200000
3a03eb79 3042#define OPTROM_SIZE_81XX 0x400000
a9083016 3043#define OPTROM_SIZE_82XX 0x800000
6246b8a1 3044#define OPTROM_SIZE_83XX 0x1000000
a9083016
GM
3045
3046#define OPTROM_BURST_SIZE 0x1000
3047#define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
1da177e4 3048
bad75002
AE
3049#define QLA_DSDS_PER_IOCB 37
3050
4d78c973
GM
3051#define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
3052
58548cb5
GM
3053#define QLA_SG_ALL 1024
3054
4d78c973
GM
3055enum nexus_wait_type {
3056 WAIT_HOST = 0,
3057 WAIT_TARGET,
3058 WAIT_LUN,
3059};
3060
1da177e4
LT
3061#include "qla_gbl.h"
3062#include "qla_dbg.h"
3063#include "qla_inline.h"
1da177e4 3064#endif