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fa90c54f AV |
1 | /* |
2 | * QLogic Fibre Channel HBA Driver | |
01e58d8e | 3 | * Copyright (c) 2003-2008 QLogic Corporation |
fa90c54f AV |
4 | * |
5 | * See LICENSE.qla2xxx for copyright and licensing details. | |
6 | */ | |
1da177e4 LT |
7 | #ifndef __QLA_DEF_H |
8 | #define __QLA_DEF_H | |
9 | ||
10 | #include <linux/kernel.h> | |
11 | #include <linux/init.h> | |
12 | #include <linux/types.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/list.h> | |
15 | #include <linux/pci.h> | |
16 | #include <linux/dma-mapping.h> | |
17 | #include <linux/sched.h> | |
18 | #include <linux/slab.h> | |
19 | #include <linux/dmapool.h> | |
20 | #include <linux/mempool.h> | |
21 | #include <linux/spinlock.h> | |
22 | #include <linux/completion.h> | |
abbd8870 | 23 | #include <linux/interrupt.h> |
19a7b4ae | 24 | #include <linux/workqueue.h> |
5433383e | 25 | #include <linux/firmware.h> |
14e660e6 | 26 | #include <linux/aer.h> |
4d4df193 | 27 | #include <linux/mutex.h> |
1da177e4 LT |
28 | |
29 | #include <scsi/scsi.h> | |
30 | #include <scsi/scsi_host.h> | |
31 | #include <scsi/scsi_device.h> | |
32 | #include <scsi/scsi_cmnd.h> | |
392e2f65 | 33 | #include <scsi/scsi_transport_fc.h> |
1da177e4 | 34 | |
cb63067a AV |
35 | #define QLA2XXX_DRIVER_NAME "qla2xxx" |
36 | ||
1da177e4 LT |
37 | /* |
38 | * We have MAILBOX_REGISTER_COUNT sized arrays in a few places, | |
39 | * but that's fine as we don't look at the last 24 ones for | |
40 | * ISP2100 HBAs. | |
41 | */ | |
42 | #define MAILBOX_REGISTER_COUNT_2100 8 | |
43 | #define MAILBOX_REGISTER_COUNT 32 | |
44 | ||
45 | #define QLA2200A_RISC_ROM_VER 4 | |
46 | #define FPM_2300 6 | |
47 | #define FPM_2310 7 | |
48 | ||
49 | #include "qla_settings.h" | |
50 | ||
fa2a1ce5 | 51 | /* |
1da177e4 LT |
52 | * Data bit definitions |
53 | */ | |
54 | #define BIT_0 0x1 | |
55 | #define BIT_1 0x2 | |
56 | #define BIT_2 0x4 | |
57 | #define BIT_3 0x8 | |
58 | #define BIT_4 0x10 | |
59 | #define BIT_5 0x20 | |
60 | #define BIT_6 0x40 | |
61 | #define BIT_7 0x80 | |
62 | #define BIT_8 0x100 | |
63 | #define BIT_9 0x200 | |
64 | #define BIT_10 0x400 | |
65 | #define BIT_11 0x800 | |
66 | #define BIT_12 0x1000 | |
67 | #define BIT_13 0x2000 | |
68 | #define BIT_14 0x4000 | |
69 | #define BIT_15 0x8000 | |
70 | #define BIT_16 0x10000 | |
71 | #define BIT_17 0x20000 | |
72 | #define BIT_18 0x40000 | |
73 | #define BIT_19 0x80000 | |
74 | #define BIT_20 0x100000 | |
75 | #define BIT_21 0x200000 | |
76 | #define BIT_22 0x400000 | |
77 | #define BIT_23 0x800000 | |
78 | #define BIT_24 0x1000000 | |
79 | #define BIT_25 0x2000000 | |
80 | #define BIT_26 0x4000000 | |
81 | #define BIT_27 0x8000000 | |
82 | #define BIT_28 0x10000000 | |
83 | #define BIT_29 0x20000000 | |
84 | #define BIT_30 0x40000000 | |
85 | #define BIT_31 0x80000000 | |
86 | ||
87 | #define LSB(x) ((uint8_t)(x)) | |
88 | #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8)) | |
89 | ||
90 | #define LSW(x) ((uint16_t)(x)) | |
91 | #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16)) | |
92 | ||
93 | #define LSD(x) ((uint32_t)((uint64_t)(x))) | |
94 | #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16)) | |
95 | ||
2afa19a9 | 96 | #define MAKE_HANDLE(x, y) ((uint32_t)((((uint32_t)(x)) << 16) | (uint32_t)(y))) |
1da177e4 LT |
97 | |
98 | /* | |
99 | * I/O register | |
100 | */ | |
101 | ||
102 | #define RD_REG_BYTE(addr) readb(addr) | |
103 | #define RD_REG_WORD(addr) readw(addr) | |
104 | #define RD_REG_DWORD(addr) readl(addr) | |
105 | #define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr) | |
106 | #define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr) | |
107 | #define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr) | |
108 | #define WRT_REG_BYTE(addr, data) writeb(data,addr) | |
109 | #define WRT_REG_WORD(addr, data) writew(data,addr) | |
110 | #define WRT_REG_DWORD(addr, data) writel(data,addr) | |
111 | ||
f6df144c AV |
112 | /* |
113 | * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an | |
114 | * 133Mhz slot. | |
115 | */ | |
116 | #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr)) | |
117 | #define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr)) | |
118 | ||
1da177e4 LT |
119 | /* |
120 | * Fibre Channel device definitions. | |
121 | */ | |
122 | #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */ | |
123 | #define MAX_FIBRE_DEVICES 512 | |
cc4731f5 | 124 | #define MAX_FIBRE_LUNS 0xFFFF |
1da177e4 LT |
125 | #define MAX_RSCN_COUNT 32 |
126 | #define MAX_HOST_COUNT 16 | |
127 | ||
128 | /* | |
129 | * Host adapter default definitions. | |
130 | */ | |
131 | #define MAX_BUSES 1 /* We only have one bus today */ | |
132 | #define MAX_TARGETS_2100 MAX_FIBRE_DEVICES | |
133 | #define MAX_TARGETS_2200 MAX_FIBRE_DEVICES | |
1da177e4 LT |
134 | #define MIN_LUNS 8 |
135 | #define MAX_LUNS MAX_FIBRE_LUNS | |
fa2a1ce5 AV |
136 | #define MAX_CMDS_PER_LUN 255 |
137 | ||
1da177e4 LT |
138 | /* |
139 | * Fibre Channel device definitions. | |
140 | */ | |
141 | #define SNS_LAST_LOOP_ID_2100 0xfe | |
142 | #define SNS_LAST_LOOP_ID_2300 0x7ff | |
143 | ||
144 | #define LAST_LOCAL_LOOP_ID 0x7d | |
145 | #define SNS_FL_PORT 0x7e | |
146 | #define FABRIC_CONTROLLER 0x7f | |
147 | #define SIMPLE_NAME_SERVER 0x80 | |
148 | #define SNS_FIRST_LOOP_ID 0x81 | |
149 | #define MANAGEMENT_SERVER 0xfe | |
150 | #define BROADCAST 0xff | |
151 | ||
3d71644c AV |
152 | /* |
153 | * There is no correspondence between an N-PORT id and an AL_PA. Therefore the | |
154 | * valid range of an N-PORT id is 0 through 0x7ef. | |
155 | */ | |
156 | #define NPH_LAST_HANDLE 0x7ef | |
cca5335c | 157 | #define NPH_MGMT_SERVER 0x7fa /* FFFFFA */ |
3d71644c AV |
158 | #define NPH_SNS 0x7fc /* FFFFFC */ |
159 | #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */ | |
160 | #define NPH_F_PORT 0x7fe /* FFFFFE */ | |
161 | #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */ | |
162 | ||
163 | #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */ | |
164 | #include "qla_fw.h" | |
1da177e4 LT |
165 | |
166 | /* | |
167 | * Timeout timer counts in seconds | |
168 | */ | |
8482e118 | 169 | #define PORT_RETRY_TIME 1 |
1da177e4 LT |
170 | #define LOOP_DOWN_TIMEOUT 60 |
171 | #define LOOP_DOWN_TIME 255 /* 240 */ | |
172 | #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30) | |
173 | ||
174 | /* Maximum outstanding commands in ISP queues (1-65535) */ | |
175 | #define MAX_OUTSTANDING_COMMANDS 1024 | |
176 | ||
177 | /* ISP request and response entry counts (37-65535) */ | |
178 | #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */ | |
179 | #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */ | |
d743de66 | 180 | #define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */ |
1da177e4 LT |
181 | #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/ |
182 | #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/ | |
2afa19a9 | 183 | #define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/ |
1da177e4 | 184 | |
17d98630 AC |
185 | struct req_que; |
186 | ||
1da177e4 | 187 | /* |
fa2a1ce5 | 188 | * SCSI Request Block |
1da177e4 LT |
189 | */ |
190 | typedef struct srb { | |
bdf79621 | 191 | struct fc_port *fcport; |
cf53b069 | 192 | uint32_t handle; |
1da177e4 LT |
193 | |
194 | struct scsi_cmnd *cmd; /* Linux SCSI command pkt */ | |
195 | ||
1da177e4 LT |
196 | uint16_t flags; |
197 | ||
1da177e4 LT |
198 | uint32_t request_sense_length; |
199 | uint8_t *request_sense_ptr; | |
cf53b069 AV |
200 | |
201 | void *ctx; | |
1da177e4 LT |
202 | } srb_t; |
203 | ||
204 | /* | |
205 | * SRB flag definitions | |
206 | */ | |
ddb9b126 | 207 | #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */ |
1da177e4 | 208 | |
1da177e4 LT |
209 | /* |
210 | * ISP I/O Register Set structure definitions. | |
211 | */ | |
3d71644c AV |
212 | struct device_reg_2xxx { |
213 | uint16_t flash_address; /* Flash BIOS address */ | |
214 | uint16_t flash_data; /* Flash BIOS data */ | |
1da177e4 | 215 | uint16_t unused_1[1]; /* Gap */ |
3d71644c | 216 | uint16_t ctrl_status; /* Control/Status */ |
fa2a1ce5 | 217 | #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */ |
1da177e4 LT |
218 | #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */ |
219 | #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */ | |
220 | ||
3d71644c | 221 | uint16_t ictrl; /* Interrupt control */ |
1da177e4 LT |
222 | #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */ |
223 | #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */ | |
224 | ||
3d71644c | 225 | uint16_t istatus; /* Interrupt status */ |
1da177e4 LT |
226 | #define ISR_RISC_INT BIT_3 /* RISC interrupt */ |
227 | ||
3d71644c AV |
228 | uint16_t semaphore; /* Semaphore */ |
229 | uint16_t nvram; /* NVRAM register. */ | |
1da177e4 LT |
230 | #define NVR_DESELECT 0 |
231 | #define NVR_BUSY BIT_15 | |
232 | #define NVR_WRT_ENABLE BIT_14 /* Write enable */ | |
233 | #define NVR_PR_ENABLE BIT_13 /* Protection register enable */ | |
234 | #define NVR_DATA_IN BIT_3 | |
235 | #define NVR_DATA_OUT BIT_2 | |
236 | #define NVR_SELECT BIT_1 | |
237 | #define NVR_CLOCK BIT_0 | |
238 | ||
45aeaf1e RA |
239 | #define NVR_WAIT_CNT 20000 |
240 | ||
1da177e4 LT |
241 | union { |
242 | struct { | |
3d71644c AV |
243 | uint16_t mailbox0; |
244 | uint16_t mailbox1; | |
245 | uint16_t mailbox2; | |
246 | uint16_t mailbox3; | |
247 | uint16_t mailbox4; | |
248 | uint16_t mailbox5; | |
249 | uint16_t mailbox6; | |
250 | uint16_t mailbox7; | |
251 | uint16_t unused_2[59]; /* Gap */ | |
1da177e4 LT |
252 | } __attribute__((packed)) isp2100; |
253 | struct { | |
3d71644c AV |
254 | /* Request Queue */ |
255 | uint16_t req_q_in; /* In-Pointer */ | |
256 | uint16_t req_q_out; /* Out-Pointer */ | |
257 | /* Response Queue */ | |
258 | uint16_t rsp_q_in; /* In-Pointer */ | |
259 | uint16_t rsp_q_out; /* Out-Pointer */ | |
1da177e4 LT |
260 | |
261 | /* RISC to Host Status */ | |
fa2a1ce5 | 262 | uint32_t host_status; |
1da177e4 LT |
263 | #define HSR_RISC_INT BIT_15 /* RISC interrupt */ |
264 | #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */ | |
265 | ||
266 | /* Host to Host Semaphore */ | |
fa2a1ce5 | 267 | uint16_t host_semaphore; |
3d71644c AV |
268 | uint16_t unused_3[17]; /* Gap */ |
269 | uint16_t mailbox0; | |
270 | uint16_t mailbox1; | |
271 | uint16_t mailbox2; | |
272 | uint16_t mailbox3; | |
273 | uint16_t mailbox4; | |
274 | uint16_t mailbox5; | |
275 | uint16_t mailbox6; | |
276 | uint16_t mailbox7; | |
277 | uint16_t mailbox8; | |
278 | uint16_t mailbox9; | |
279 | uint16_t mailbox10; | |
280 | uint16_t mailbox11; | |
281 | uint16_t mailbox12; | |
282 | uint16_t mailbox13; | |
283 | uint16_t mailbox14; | |
284 | uint16_t mailbox15; | |
285 | uint16_t mailbox16; | |
286 | uint16_t mailbox17; | |
287 | uint16_t mailbox18; | |
288 | uint16_t mailbox19; | |
289 | uint16_t mailbox20; | |
290 | uint16_t mailbox21; | |
291 | uint16_t mailbox22; | |
292 | uint16_t mailbox23; | |
293 | uint16_t mailbox24; | |
294 | uint16_t mailbox25; | |
295 | uint16_t mailbox26; | |
296 | uint16_t mailbox27; | |
297 | uint16_t mailbox28; | |
298 | uint16_t mailbox29; | |
299 | uint16_t mailbox30; | |
300 | uint16_t mailbox31; | |
301 | uint16_t fb_cmd; | |
302 | uint16_t unused_4[10]; /* Gap */ | |
1da177e4 LT |
303 | } __attribute__((packed)) isp2300; |
304 | } u; | |
305 | ||
3d71644c | 306 | uint16_t fpm_diag_config; |
c81d04c9 AV |
307 | uint16_t unused_5[0x4]; /* Gap */ |
308 | uint16_t risc_hw; | |
309 | uint16_t unused_5_1; /* Gap */ | |
3d71644c | 310 | uint16_t pcr; /* Processor Control Register. */ |
1da177e4 | 311 | uint16_t unused_6[0x5]; /* Gap */ |
3d71644c | 312 | uint16_t mctr; /* Memory Configuration and Timing. */ |
1da177e4 | 313 | uint16_t unused_7[0x3]; /* Gap */ |
3d71644c | 314 | uint16_t fb_cmd_2100; /* Unused on 23XX */ |
1da177e4 | 315 | uint16_t unused_8[0x3]; /* Gap */ |
3d71644c | 316 | uint16_t hccr; /* Host command & control register. */ |
1da177e4 LT |
317 | #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */ |
318 | #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */ | |
319 | /* HCCR commands */ | |
320 | #define HCCR_RESET_RISC 0x1000 /* Reset RISC */ | |
321 | #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */ | |
322 | #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */ | |
323 | #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */ | |
324 | #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */ | |
325 | #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */ | |
326 | #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */ | |
327 | #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */ | |
328 | ||
329 | uint16_t unused_9[5]; /* Gap */ | |
3d71644c AV |
330 | uint16_t gpiod; /* GPIO Data register. */ |
331 | uint16_t gpioe; /* GPIO Enable register. */ | |
1da177e4 LT |
332 | #define GPIO_LED_MASK 0x00C0 |
333 | #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000 | |
334 | #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040 | |
335 | #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080 | |
336 | #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0 | |
f6df144c AV |
337 | #define GPIO_LED_ALL_OFF 0x0000 |
338 | #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */ | |
339 | #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */ | |
1da177e4 LT |
340 | |
341 | union { | |
342 | struct { | |
3d71644c AV |
343 | uint16_t unused_10[8]; /* Gap */ |
344 | uint16_t mailbox8; | |
345 | uint16_t mailbox9; | |
346 | uint16_t mailbox10; | |
347 | uint16_t mailbox11; | |
348 | uint16_t mailbox12; | |
349 | uint16_t mailbox13; | |
350 | uint16_t mailbox14; | |
351 | uint16_t mailbox15; | |
352 | uint16_t mailbox16; | |
353 | uint16_t mailbox17; | |
354 | uint16_t mailbox18; | |
355 | uint16_t mailbox19; | |
356 | uint16_t mailbox20; | |
357 | uint16_t mailbox21; | |
358 | uint16_t mailbox22; | |
359 | uint16_t mailbox23; /* Also probe reg. */ | |
1da177e4 LT |
360 | } __attribute__((packed)) isp2200; |
361 | } u_end; | |
3d71644c AV |
362 | }; |
363 | ||
73208dfd | 364 | struct device_reg_25xxmq { |
08029990 AV |
365 | uint32_t req_q_in; |
366 | uint32_t req_q_out; | |
367 | uint32_t rsp_q_in; | |
368 | uint32_t rsp_q_out; | |
73208dfd AC |
369 | }; |
370 | ||
9a168bdd | 371 | typedef union { |
3d71644c AV |
372 | struct device_reg_2xxx isp; |
373 | struct device_reg_24xx isp24; | |
73208dfd | 374 | struct device_reg_25xxmq isp25mq; |
1da177e4 LT |
375 | } device_reg_t; |
376 | ||
377 | #define ISP_REQ_Q_IN(ha, reg) \ | |
378 | (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ | |
379 | &(reg)->u.isp2100.mailbox4 : \ | |
380 | &(reg)->u.isp2300.req_q_in) | |
381 | #define ISP_REQ_Q_OUT(ha, reg) \ | |
382 | (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ | |
383 | &(reg)->u.isp2100.mailbox4 : \ | |
384 | &(reg)->u.isp2300.req_q_out) | |
385 | #define ISP_RSP_Q_IN(ha, reg) \ | |
386 | (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ | |
387 | &(reg)->u.isp2100.mailbox5 : \ | |
388 | &(reg)->u.isp2300.rsp_q_in) | |
389 | #define ISP_RSP_Q_OUT(ha, reg) \ | |
390 | (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ | |
391 | &(reg)->u.isp2100.mailbox5 : \ | |
392 | &(reg)->u.isp2300.rsp_q_out) | |
393 | ||
394 | #define MAILBOX_REG(ha, reg, num) \ | |
395 | (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ | |
396 | (num < 8 ? \ | |
397 | &(reg)->u.isp2100.mailbox0 + (num) : \ | |
398 | &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \ | |
399 | &(reg)->u.isp2300.mailbox0 + (num)) | |
400 | #define RD_MAILBOX_REG(ha, reg, num) \ | |
401 | RD_REG_WORD(MAILBOX_REG(ha, reg, num)) | |
402 | #define WRT_MAILBOX_REG(ha, reg, num, data) \ | |
403 | WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data) | |
404 | ||
405 | #define FB_CMD_REG(ha, reg) \ | |
406 | (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ | |
407 | &(reg)->fb_cmd_2100 : \ | |
408 | &(reg)->u.isp2300.fb_cmd) | |
409 | #define RD_FB_CMD_REG(ha, reg) \ | |
410 | RD_REG_WORD(FB_CMD_REG(ha, reg)) | |
411 | #define WRT_FB_CMD_REG(ha, reg, data) \ | |
412 | WRT_REG_WORD(FB_CMD_REG(ha, reg), data) | |
413 | ||
414 | typedef struct { | |
415 | uint32_t out_mb; /* outbound from driver */ | |
416 | uint32_t in_mb; /* Incoming from RISC */ | |
417 | uint16_t mb[MAILBOX_REGISTER_COUNT]; | |
418 | long buf_size; | |
419 | void *bufp; | |
420 | uint32_t tov; | |
421 | uint8_t flags; | |
422 | #define MBX_DMA_IN BIT_0 | |
423 | #define MBX_DMA_OUT BIT_1 | |
424 | #define IOCTL_CMD BIT_2 | |
425 | } mbx_cmd_t; | |
426 | ||
427 | #define MBX_TOV_SECONDS 30 | |
428 | ||
429 | /* | |
430 | * ISP product identification definitions in mailboxes after reset. | |
431 | */ | |
432 | #define PROD_ID_1 0x4953 | |
433 | #define PROD_ID_2 0x0000 | |
434 | #define PROD_ID_2a 0x5020 | |
435 | #define PROD_ID_3 0x2020 | |
436 | ||
437 | /* | |
438 | * ISP mailbox Self-Test status codes | |
439 | */ | |
440 | #define MBS_FRM_ALIVE 0 /* Firmware Alive. */ | |
441 | #define MBS_CHKSUM_ERR 1 /* Checksum Error. */ | |
442 | #define MBS_BUSY 4 /* Busy. */ | |
443 | ||
444 | /* | |
445 | * ISP mailbox command complete status codes | |
446 | */ | |
447 | #define MBS_COMMAND_COMPLETE 0x4000 | |
448 | #define MBS_INVALID_COMMAND 0x4001 | |
449 | #define MBS_HOST_INTERFACE_ERROR 0x4002 | |
450 | #define MBS_TEST_FAILED 0x4003 | |
451 | #define MBS_COMMAND_ERROR 0x4005 | |
452 | #define MBS_COMMAND_PARAMETER_ERROR 0x4006 | |
453 | #define MBS_PORT_ID_USED 0x4007 | |
454 | #define MBS_LOOP_ID_USED 0x4008 | |
455 | #define MBS_ALL_IDS_IN_USE 0x4009 | |
456 | #define MBS_NOT_LOGGED_IN 0x400A | |
3d71644c AV |
457 | #define MBS_LINK_DOWN_ERROR 0x400B |
458 | #define MBS_DIAG_ECHO_TEST_ERROR 0x400C | |
1da177e4 LT |
459 | |
460 | /* | |
461 | * ISP mailbox asynchronous event status codes | |
462 | */ | |
463 | #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */ | |
464 | #define MBA_RESET 0x8001 /* Reset Detected. */ | |
465 | #define MBA_SYSTEM_ERR 0x8002 /* System Error. */ | |
466 | #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */ | |
467 | #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */ | |
468 | #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */ | |
469 | #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */ | |
470 | /* occurred. */ | |
471 | #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */ | |
472 | #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */ | |
473 | #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */ | |
474 | #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */ | |
475 | #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */ | |
476 | #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */ | |
477 | #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */ | |
478 | #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */ | |
479 | #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */ | |
480 | #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */ | |
481 | #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */ | |
482 | #define MBA_IP_RECEIVE 0x8023 /* IP Received. */ | |
483 | #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */ | |
484 | #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */ | |
485 | #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */ | |
486 | #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */ | |
487 | /* used. */ | |
45ebeb56 | 488 | #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */ |
1da177e4 LT |
489 | #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */ |
490 | #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */ | |
491 | #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */ | |
492 | #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */ | |
493 | #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */ | |
494 | #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */ | |
495 | #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */ | |
496 | #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */ | |
497 | #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */ | |
498 | #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */ | |
499 | #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */ | |
500 | #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */ | |
501 | #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */ | |
502 | ||
503 | /* | |
504 | * Firmware options 1, 2, 3. | |
505 | */ | |
506 | #define FO1_AE_ON_LIPF8 BIT_0 | |
507 | #define FO1_AE_ALL_LIP_RESET BIT_1 | |
508 | #define FO1_CTIO_RETRY BIT_3 | |
509 | #define FO1_DISABLE_LIP_F7_SW BIT_4 | |
510 | #define FO1_DISABLE_100MS_LOS_WAIT BIT_5 | |
3d71644c | 511 | #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */ |
1da177e4 LT |
512 | #define FO1_AE_ON_LOOP_INIT_ERR BIT_7 |
513 | #define FO1_SET_EMPHASIS_SWING BIT_8 | |
514 | #define FO1_AE_AUTO_BYPASS BIT_9 | |
515 | #define FO1_ENABLE_PURE_IOCB BIT_10 | |
516 | #define FO1_AE_PLOGI_RJT BIT_11 | |
517 | #define FO1_ENABLE_ABORT_SEQUENCE BIT_12 | |
518 | #define FO1_AE_QUEUE_FULL BIT_13 | |
519 | ||
520 | #define FO2_ENABLE_ATIO_TYPE_3 BIT_0 | |
521 | #define FO2_REV_LOOPBACK BIT_1 | |
522 | ||
523 | #define FO3_ENABLE_EMERG_IOCB BIT_0 | |
524 | #define FO3_AE_RND_ERROR BIT_1 | |
525 | ||
3d71644c AV |
526 | /* 24XX additional firmware options */ |
527 | #define ADD_FO_COUNT 3 | |
528 | #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */ | |
529 | #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10 | |
530 | ||
531 | #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5 | |
532 | ||
533 | #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14 | |
534 | ||
1da177e4 LT |
535 | /* |
536 | * ISP mailbox commands | |
537 | */ | |
538 | #define MBC_LOAD_RAM 1 /* Load RAM. */ | |
539 | #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */ | |
540 | #define MBC_WRITE_RAM_WORD 4 /* Write RAM word. */ | |
541 | #define MBC_READ_RAM_WORD 5 /* Read RAM word. */ | |
542 | #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */ | |
543 | #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */ | |
544 | #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */ | |
545 | #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */ | |
546 | #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */ | |
547 | #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */ | |
548 | #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */ | |
549 | #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */ | |
550 | #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */ | |
551 | #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */ | |
f6ef3b18 | 552 | #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */ |
1da177e4 LT |
553 | #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */ |
554 | #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */ | |
555 | #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */ | |
556 | #define MBC_RESET 0x18 /* Reset. */ | |
557 | #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */ | |
558 | #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */ | |
559 | #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */ | |
560 | #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */ | |
561 | #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */ | |
562 | #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */ | |
563 | #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */ | |
564 | #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */ | |
565 | #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */ | |
566 | #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */ | |
567 | #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */ | |
568 | #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */ | |
569 | #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */ | |
570 | #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */ | |
571 | #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */ | |
572 | #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */ | |
573 | #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */ | |
574 | #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */ | |
575 | #define MBC_GET_RNID_PARAMS 0x5a /* Data Rate */ | |
576 | #define MBC_DATA_RATE 0x5d /* Get RNID parameters */ | |
577 | #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */ | |
578 | #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */ | |
579 | /* Initialization Procedure */ | |
580 | #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */ | |
581 | #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */ | |
582 | #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */ | |
583 | #define MBC_TARGET_RESET 0x66 /* Target Reset. */ | |
584 | #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */ | |
585 | #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */ | |
586 | #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */ | |
587 | #define MBC_GET_PORT_NAME 0x6a /* Get port name. */ | |
588 | #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */ | |
589 | #define MBC_LIP_RESET 0x6c /* LIP reset. */ | |
590 | #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */ | |
591 | /* commandd. */ | |
592 | #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */ | |
593 | #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */ | |
594 | #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */ | |
595 | #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */ | |
596 | #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */ | |
597 | #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */ | |
598 | #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */ | |
599 | #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */ | |
600 | #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */ | |
601 | #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */ | |
602 | #define MBC_LUN_RESET 0x7E /* Send LUN reset */ | |
603 | ||
3d71644c AV |
604 | /* |
605 | * ISP24xx mailbox commands | |
606 | */ | |
607 | #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */ | |
608 | #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */ | |
d8b45213 | 609 | #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */ |
3d71644c | 610 | #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */ |
a7a167bf | 611 | #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */ |
3d71644c | 612 | #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */ |
ad0ecd61 | 613 | #define MBC_WRITE_SFP 0x30 /* Write SFP Data. */ |
88729e53 | 614 | #define MBC_READ_SFP 0x31 /* Read SFP Data. */ |
3d71644c AV |
615 | #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */ |
616 | #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */ | |
617 | #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */ | |
618 | #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */ | |
619 | #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */ | |
620 | #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */ | |
621 | #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */ | |
622 | #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */ | |
623 | ||
1da177e4 LT |
624 | /* Firmware return data sizes */ |
625 | #define FCAL_MAP_SIZE 128 | |
626 | ||
627 | /* Mailbox bit definitions for out_mb and in_mb */ | |
628 | #define MBX_31 BIT_31 | |
629 | #define MBX_30 BIT_30 | |
630 | #define MBX_29 BIT_29 | |
631 | #define MBX_28 BIT_28 | |
632 | #define MBX_27 BIT_27 | |
633 | #define MBX_26 BIT_26 | |
634 | #define MBX_25 BIT_25 | |
635 | #define MBX_24 BIT_24 | |
636 | #define MBX_23 BIT_23 | |
637 | #define MBX_22 BIT_22 | |
638 | #define MBX_21 BIT_21 | |
639 | #define MBX_20 BIT_20 | |
640 | #define MBX_19 BIT_19 | |
641 | #define MBX_18 BIT_18 | |
642 | #define MBX_17 BIT_17 | |
643 | #define MBX_16 BIT_16 | |
644 | #define MBX_15 BIT_15 | |
645 | #define MBX_14 BIT_14 | |
646 | #define MBX_13 BIT_13 | |
647 | #define MBX_12 BIT_12 | |
648 | #define MBX_11 BIT_11 | |
649 | #define MBX_10 BIT_10 | |
650 | #define MBX_9 BIT_9 | |
651 | #define MBX_8 BIT_8 | |
652 | #define MBX_7 BIT_7 | |
653 | #define MBX_6 BIT_6 | |
654 | #define MBX_5 BIT_5 | |
655 | #define MBX_4 BIT_4 | |
656 | #define MBX_3 BIT_3 | |
657 | #define MBX_2 BIT_2 | |
658 | #define MBX_1 BIT_1 | |
659 | #define MBX_0 BIT_0 | |
660 | ||
661 | /* | |
662 | * Firmware state codes from get firmware state mailbox command | |
663 | */ | |
664 | #define FSTATE_CONFIG_WAIT 0 | |
665 | #define FSTATE_WAIT_AL_PA 1 | |
666 | #define FSTATE_WAIT_LOGIN 2 | |
667 | #define FSTATE_READY 3 | |
668 | #define FSTATE_LOSS_OF_SYNC 4 | |
669 | #define FSTATE_ERROR 5 | |
670 | #define FSTATE_REINIT 6 | |
671 | #define FSTATE_NON_PART 7 | |
672 | ||
673 | #define FSTATE_CONFIG_CORRECT 0 | |
674 | #define FSTATE_P2P_RCV_LIP 1 | |
675 | #define FSTATE_P2P_CHOOSE_LOOP 2 | |
676 | #define FSTATE_P2P_RCV_UNIDEN_LIP 3 | |
677 | #define FSTATE_FATAL_ERROR 4 | |
678 | #define FSTATE_LOOP_BACK_CONN 5 | |
679 | ||
680 | /* | |
681 | * Port Database structure definition | |
682 | * Little endian except where noted. | |
683 | */ | |
684 | #define PORT_DATABASE_SIZE 128 /* bytes */ | |
685 | typedef struct { | |
686 | uint8_t options; | |
687 | uint8_t control; | |
688 | uint8_t master_state; | |
689 | uint8_t slave_state; | |
690 | uint8_t reserved[2]; | |
691 | uint8_t hard_address; | |
692 | uint8_t reserved_1; | |
693 | uint8_t port_id[4]; | |
694 | uint8_t node_name[WWN_SIZE]; | |
695 | uint8_t port_name[WWN_SIZE]; | |
696 | uint16_t execution_throttle; | |
697 | uint16_t execution_count; | |
698 | uint8_t reset_count; | |
699 | uint8_t reserved_2; | |
700 | uint16_t resource_allocation; | |
701 | uint16_t current_allocation; | |
702 | uint16_t queue_head; | |
703 | uint16_t queue_tail; | |
704 | uint16_t transmit_execution_list_next; | |
705 | uint16_t transmit_execution_list_previous; | |
706 | uint16_t common_features; | |
707 | uint16_t total_concurrent_sequences; | |
708 | uint16_t RO_by_information_category; | |
709 | uint8_t recipient; | |
710 | uint8_t initiator; | |
711 | uint16_t receive_data_size; | |
712 | uint16_t concurrent_sequences; | |
713 | uint16_t open_sequences_per_exchange; | |
714 | uint16_t lun_abort_flags; | |
715 | uint16_t lun_stop_flags; | |
716 | uint16_t stop_queue_head; | |
717 | uint16_t stop_queue_tail; | |
718 | uint16_t port_retry_timer; | |
719 | uint16_t next_sequence_id; | |
720 | uint16_t frame_count; | |
721 | uint16_t PRLI_payload_length; | |
722 | uint8_t prli_svc_param_word_0[2]; /* Big endian */ | |
723 | /* Bits 15-0 of word 0 */ | |
724 | uint8_t prli_svc_param_word_3[2]; /* Big endian */ | |
725 | /* Bits 15-0 of word 3 */ | |
726 | uint16_t loop_id; | |
727 | uint16_t extended_lun_info_list_pointer; | |
728 | uint16_t extended_lun_stop_list_pointer; | |
729 | } port_database_t; | |
730 | ||
731 | /* | |
732 | * Port database slave/master states | |
733 | */ | |
734 | #define PD_STATE_DISCOVERY 0 | |
735 | #define PD_STATE_WAIT_DISCOVERY_ACK 1 | |
736 | #define PD_STATE_PORT_LOGIN 2 | |
737 | #define PD_STATE_WAIT_PORT_LOGIN_ACK 3 | |
738 | #define PD_STATE_PROCESS_LOGIN 4 | |
739 | #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5 | |
740 | #define PD_STATE_PORT_LOGGED_IN 6 | |
741 | #define PD_STATE_PORT_UNAVAILABLE 7 | |
742 | #define PD_STATE_PROCESS_LOGOUT 8 | |
743 | #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9 | |
744 | #define PD_STATE_PORT_LOGOUT 10 | |
745 | #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11 | |
746 | ||
747 | ||
4fdfefe5 AV |
748 | #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1) |
749 | #define QLA_ZIO_DISABLED 0 | |
750 | #define QLA_ZIO_DEFAULT_TIMER 2 | |
751 | ||
1da177e4 LT |
752 | /* |
753 | * ISP Initialization Control Block. | |
754 | * Little endian except where noted. | |
755 | */ | |
756 | #define ICB_VERSION 1 | |
757 | typedef struct { | |
758 | uint8_t version; | |
759 | uint8_t reserved_1; | |
760 | ||
761 | /* | |
762 | * LSB BIT 0 = Enable Hard Loop Id | |
763 | * LSB BIT 1 = Enable Fairness | |
764 | * LSB BIT 2 = Enable Full-Duplex | |
765 | * LSB BIT 3 = Enable Fast Posting | |
766 | * LSB BIT 4 = Enable Target Mode | |
767 | * LSB BIT 5 = Disable Initiator Mode | |
768 | * LSB BIT 6 = Enable ADISC | |
769 | * LSB BIT 7 = Enable Target Inquiry Data | |
770 | * | |
771 | * MSB BIT 0 = Enable PDBC Notify | |
772 | * MSB BIT 1 = Non Participating LIP | |
773 | * MSB BIT 2 = Descending Loop ID Search | |
774 | * MSB BIT 3 = Acquire Loop ID in LIPA | |
775 | * MSB BIT 4 = Stop PortQ on Full Status | |
776 | * MSB BIT 5 = Full Login after LIP | |
777 | * MSB BIT 6 = Node Name Option | |
778 | * MSB BIT 7 = Ext IFWCB enable bit | |
779 | */ | |
780 | uint8_t firmware_options[2]; | |
781 | ||
782 | uint16_t frame_payload_size; | |
783 | uint16_t max_iocb_allocation; | |
784 | uint16_t execution_throttle; | |
785 | uint8_t retry_count; | |
786 | uint8_t retry_delay; /* unused */ | |
787 | uint8_t port_name[WWN_SIZE]; /* Big endian. */ | |
788 | uint16_t hard_address; | |
789 | uint8_t inquiry_data; | |
790 | uint8_t login_timeout; | |
791 | uint8_t node_name[WWN_SIZE]; /* Big endian. */ | |
792 | ||
793 | uint16_t request_q_outpointer; | |
794 | uint16_t response_q_inpointer; | |
795 | uint16_t request_q_length; | |
796 | uint16_t response_q_length; | |
797 | uint32_t request_q_address[2]; | |
798 | uint32_t response_q_address[2]; | |
799 | ||
800 | uint16_t lun_enables; | |
801 | uint8_t command_resource_count; | |
802 | uint8_t immediate_notify_resource_count; | |
803 | uint16_t timeout; | |
804 | uint8_t reserved_2[2]; | |
805 | ||
806 | /* | |
807 | * LSB BIT 0 = Timer Operation mode bit 0 | |
808 | * LSB BIT 1 = Timer Operation mode bit 1 | |
809 | * LSB BIT 2 = Timer Operation mode bit 2 | |
810 | * LSB BIT 3 = Timer Operation mode bit 3 | |
811 | * LSB BIT 4 = Init Config Mode bit 0 | |
812 | * LSB BIT 5 = Init Config Mode bit 1 | |
813 | * LSB BIT 6 = Init Config Mode bit 2 | |
814 | * LSB BIT 7 = Enable Non part on LIHA failure | |
815 | * | |
816 | * MSB BIT 0 = Enable class 2 | |
817 | * MSB BIT 1 = Enable ACK0 | |
818 | * MSB BIT 2 = | |
819 | * MSB BIT 3 = | |
820 | * MSB BIT 4 = FC Tape Enable | |
821 | * MSB BIT 5 = Enable FC Confirm | |
822 | * MSB BIT 6 = Enable command queuing in target mode | |
823 | * MSB BIT 7 = No Logo On Link Down | |
824 | */ | |
825 | uint8_t add_firmware_options[2]; | |
826 | ||
827 | uint8_t response_accumulation_timer; | |
828 | uint8_t interrupt_delay_timer; | |
829 | ||
830 | /* | |
831 | * LSB BIT 0 = Enable Read xfr_rdy | |
832 | * LSB BIT 1 = Soft ID only | |
833 | * LSB BIT 2 = | |
834 | * LSB BIT 3 = | |
835 | * LSB BIT 4 = FCP RSP Payload [0] | |
836 | * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 | |
837 | * LSB BIT 6 = Enable Out-of-Order frame handling | |
838 | * LSB BIT 7 = Disable Automatic PLOGI on Local Loop | |
839 | * | |
840 | * MSB BIT 0 = Sbus enable - 2300 | |
841 | * MSB BIT 1 = | |
842 | * MSB BIT 2 = | |
843 | * MSB BIT 3 = | |
06c22bd1 | 844 | * MSB BIT 4 = LED mode |
1da177e4 LT |
845 | * MSB BIT 5 = enable 50 ohm termination |
846 | * MSB BIT 6 = Data Rate (2300 only) | |
847 | * MSB BIT 7 = Data Rate (2300 only) | |
848 | */ | |
849 | uint8_t special_options[2]; | |
850 | ||
851 | uint8_t reserved_3[26]; | |
852 | } init_cb_t; | |
853 | ||
854 | /* | |
855 | * Get Link Status mailbox command return buffer. | |
856 | */ | |
3d71644c AV |
857 | #define GLSO_SEND_RPS BIT_0 |
858 | #define GLSO_USE_DID BIT_3 | |
859 | ||
43ef0580 AV |
860 | struct link_statistics { |
861 | uint32_t link_fail_cnt; | |
862 | uint32_t loss_sync_cnt; | |
863 | uint32_t loss_sig_cnt; | |
864 | uint32_t prim_seq_err_cnt; | |
865 | uint32_t inval_xmit_word_cnt; | |
866 | uint32_t inval_crc_cnt; | |
032d8dd7 HZ |
867 | uint32_t lip_cnt; |
868 | uint32_t unused1[0x1a]; | |
43ef0580 AV |
869 | uint32_t tx_frames; |
870 | uint32_t rx_frames; | |
871 | uint32_t dumped_frames; | |
872 | uint32_t unused2[2]; | |
873 | uint32_t nos_rcvd; | |
874 | }; | |
1da177e4 LT |
875 | |
876 | /* | |
877 | * NVRAM Command values. | |
878 | */ | |
879 | #define NV_START_BIT BIT_2 | |
880 | #define NV_WRITE_OP (BIT_26+BIT_24) | |
881 | #define NV_READ_OP (BIT_26+BIT_25) | |
882 | #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24) | |
883 | #define NV_MASK_OP (BIT_26+BIT_25+BIT_24) | |
884 | #define NV_DELAY_COUNT 10 | |
885 | ||
886 | /* | |
887 | * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition. | |
888 | */ | |
889 | typedef struct { | |
890 | /* | |
891 | * NVRAM header | |
892 | */ | |
893 | uint8_t id[4]; | |
894 | uint8_t nvram_version; | |
895 | uint8_t reserved_0; | |
896 | ||
897 | /* | |
898 | * NVRAM RISC parameter block | |
899 | */ | |
900 | uint8_t parameter_block_version; | |
901 | uint8_t reserved_1; | |
902 | ||
903 | /* | |
904 | * LSB BIT 0 = Enable Hard Loop Id | |
905 | * LSB BIT 1 = Enable Fairness | |
906 | * LSB BIT 2 = Enable Full-Duplex | |
907 | * LSB BIT 3 = Enable Fast Posting | |
908 | * LSB BIT 4 = Enable Target Mode | |
909 | * LSB BIT 5 = Disable Initiator Mode | |
910 | * LSB BIT 6 = Enable ADISC | |
911 | * LSB BIT 7 = Enable Target Inquiry Data | |
912 | * | |
913 | * MSB BIT 0 = Enable PDBC Notify | |
914 | * MSB BIT 1 = Non Participating LIP | |
915 | * MSB BIT 2 = Descending Loop ID Search | |
916 | * MSB BIT 3 = Acquire Loop ID in LIPA | |
917 | * MSB BIT 4 = Stop PortQ on Full Status | |
918 | * MSB BIT 5 = Full Login after LIP | |
919 | * MSB BIT 6 = Node Name Option | |
920 | * MSB BIT 7 = Ext IFWCB enable bit | |
921 | */ | |
922 | uint8_t firmware_options[2]; | |
923 | ||
924 | uint16_t frame_payload_size; | |
925 | uint16_t max_iocb_allocation; | |
926 | uint16_t execution_throttle; | |
927 | uint8_t retry_count; | |
928 | uint8_t retry_delay; /* unused */ | |
929 | uint8_t port_name[WWN_SIZE]; /* Big endian. */ | |
930 | uint16_t hard_address; | |
931 | uint8_t inquiry_data; | |
932 | uint8_t login_timeout; | |
933 | uint8_t node_name[WWN_SIZE]; /* Big endian. */ | |
934 | ||
935 | /* | |
936 | * LSB BIT 0 = Timer Operation mode bit 0 | |
937 | * LSB BIT 1 = Timer Operation mode bit 1 | |
938 | * LSB BIT 2 = Timer Operation mode bit 2 | |
939 | * LSB BIT 3 = Timer Operation mode bit 3 | |
940 | * LSB BIT 4 = Init Config Mode bit 0 | |
941 | * LSB BIT 5 = Init Config Mode bit 1 | |
942 | * LSB BIT 6 = Init Config Mode bit 2 | |
943 | * LSB BIT 7 = Enable Non part on LIHA failure | |
944 | * | |
945 | * MSB BIT 0 = Enable class 2 | |
946 | * MSB BIT 1 = Enable ACK0 | |
947 | * MSB BIT 2 = | |
948 | * MSB BIT 3 = | |
949 | * MSB BIT 4 = FC Tape Enable | |
950 | * MSB BIT 5 = Enable FC Confirm | |
951 | * MSB BIT 6 = Enable command queuing in target mode | |
952 | * MSB BIT 7 = No Logo On Link Down | |
953 | */ | |
954 | uint8_t add_firmware_options[2]; | |
955 | ||
956 | uint8_t response_accumulation_timer; | |
957 | uint8_t interrupt_delay_timer; | |
958 | ||
959 | /* | |
960 | * LSB BIT 0 = Enable Read xfr_rdy | |
961 | * LSB BIT 1 = Soft ID only | |
962 | * LSB BIT 2 = | |
963 | * LSB BIT 3 = | |
964 | * LSB BIT 4 = FCP RSP Payload [0] | |
965 | * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 | |
966 | * LSB BIT 6 = Enable Out-of-Order frame handling | |
967 | * LSB BIT 7 = Disable Automatic PLOGI on Local Loop | |
968 | * | |
969 | * MSB BIT 0 = Sbus enable - 2300 | |
970 | * MSB BIT 1 = | |
971 | * MSB BIT 2 = | |
972 | * MSB BIT 3 = | |
06c22bd1 | 973 | * MSB BIT 4 = LED mode |
1da177e4 LT |
974 | * MSB BIT 5 = enable 50 ohm termination |
975 | * MSB BIT 6 = Data Rate (2300 only) | |
976 | * MSB BIT 7 = Data Rate (2300 only) | |
977 | */ | |
978 | uint8_t special_options[2]; | |
979 | ||
980 | /* Reserved for expanded RISC parameter block */ | |
981 | uint8_t reserved_2[22]; | |
982 | ||
983 | /* | |
984 | * LSB BIT 0 = Tx Sensitivity 1G bit 0 | |
985 | * LSB BIT 1 = Tx Sensitivity 1G bit 1 | |
986 | * LSB BIT 2 = Tx Sensitivity 1G bit 2 | |
987 | * LSB BIT 3 = Tx Sensitivity 1G bit 3 | |
988 | * LSB BIT 4 = Rx Sensitivity 1G bit 0 | |
989 | * LSB BIT 5 = Rx Sensitivity 1G bit 1 | |
990 | * LSB BIT 6 = Rx Sensitivity 1G bit 2 | |
991 | * LSB BIT 7 = Rx Sensitivity 1G bit 3 | |
fa2a1ce5 | 992 | * |
1da177e4 LT |
993 | * MSB BIT 0 = Tx Sensitivity 2G bit 0 |
994 | * MSB BIT 1 = Tx Sensitivity 2G bit 1 | |
995 | * MSB BIT 2 = Tx Sensitivity 2G bit 2 | |
996 | * MSB BIT 3 = Tx Sensitivity 2G bit 3 | |
997 | * MSB BIT 4 = Rx Sensitivity 2G bit 0 | |
998 | * MSB BIT 5 = Rx Sensitivity 2G bit 1 | |
999 | * MSB BIT 6 = Rx Sensitivity 2G bit 2 | |
1000 | * MSB BIT 7 = Rx Sensitivity 2G bit 3 | |
1001 | * | |
1002 | * LSB BIT 0 = Output Swing 1G bit 0 | |
1003 | * LSB BIT 1 = Output Swing 1G bit 1 | |
1004 | * LSB BIT 2 = Output Swing 1G bit 2 | |
1005 | * LSB BIT 3 = Output Emphasis 1G bit 0 | |
1006 | * LSB BIT 4 = Output Emphasis 1G bit 1 | |
1007 | * LSB BIT 5 = Output Swing 2G bit 0 | |
1008 | * LSB BIT 6 = Output Swing 2G bit 1 | |
1009 | * LSB BIT 7 = Output Swing 2G bit 2 | |
fa2a1ce5 | 1010 | * |
1da177e4 LT |
1011 | * MSB BIT 0 = Output Emphasis 2G bit 0 |
1012 | * MSB BIT 1 = Output Emphasis 2G bit 1 | |
1013 | * MSB BIT 2 = Output Enable | |
1014 | * MSB BIT 3 = | |
1015 | * MSB BIT 4 = | |
1016 | * MSB BIT 5 = | |
1017 | * MSB BIT 6 = | |
1018 | * MSB BIT 7 = | |
1019 | */ | |
1020 | uint8_t seriallink_options[4]; | |
1021 | ||
1022 | /* | |
1023 | * NVRAM host parameter block | |
1024 | * | |
1025 | * LSB BIT 0 = Enable spinup delay | |
1026 | * LSB BIT 1 = Disable BIOS | |
1027 | * LSB BIT 2 = Enable Memory Map BIOS | |
1028 | * LSB BIT 3 = Enable Selectable Boot | |
1029 | * LSB BIT 4 = Disable RISC code load | |
1030 | * LSB BIT 5 = Set cache line size 1 | |
1031 | * LSB BIT 6 = PCI Parity Disable | |
1032 | * LSB BIT 7 = Enable extended logging | |
1033 | * | |
1034 | * MSB BIT 0 = Enable 64bit addressing | |
1035 | * MSB BIT 1 = Enable lip reset | |
1036 | * MSB BIT 2 = Enable lip full login | |
1037 | * MSB BIT 3 = Enable target reset | |
1038 | * MSB BIT 4 = Enable database storage | |
1039 | * MSB BIT 5 = Enable cache flush read | |
1040 | * MSB BIT 6 = Enable database load | |
1041 | * MSB BIT 7 = Enable alternate WWN | |
1042 | */ | |
1043 | uint8_t host_p[2]; | |
1044 | ||
1045 | uint8_t boot_node_name[WWN_SIZE]; | |
1046 | uint8_t boot_lun_number; | |
1047 | uint8_t reset_delay; | |
1048 | uint8_t port_down_retry_count; | |
1049 | uint8_t boot_id_number; | |
1050 | uint16_t max_luns_per_target; | |
1051 | uint8_t fcode_boot_port_name[WWN_SIZE]; | |
1052 | uint8_t alternate_port_name[WWN_SIZE]; | |
1053 | uint8_t alternate_node_name[WWN_SIZE]; | |
1054 | ||
1055 | /* | |
1056 | * BIT 0 = Selective Login | |
1057 | * BIT 1 = Alt-Boot Enable | |
1058 | * BIT 2 = | |
1059 | * BIT 3 = Boot Order List | |
1060 | * BIT 4 = | |
1061 | * BIT 5 = Selective LUN | |
1062 | * BIT 6 = | |
1063 | * BIT 7 = unused | |
1064 | */ | |
1065 | uint8_t efi_parameters; | |
1066 | ||
1067 | uint8_t link_down_timeout; | |
1068 | ||
cca5335c | 1069 | uint8_t adapter_id[16]; |
1da177e4 LT |
1070 | |
1071 | uint8_t alt1_boot_node_name[WWN_SIZE]; | |
1072 | uint16_t alt1_boot_lun_number; | |
1073 | uint8_t alt2_boot_node_name[WWN_SIZE]; | |
1074 | uint16_t alt2_boot_lun_number; | |
1075 | uint8_t alt3_boot_node_name[WWN_SIZE]; | |
1076 | uint16_t alt3_boot_lun_number; | |
1077 | uint8_t alt4_boot_node_name[WWN_SIZE]; | |
1078 | uint16_t alt4_boot_lun_number; | |
1079 | uint8_t alt5_boot_node_name[WWN_SIZE]; | |
1080 | uint16_t alt5_boot_lun_number; | |
1081 | uint8_t alt6_boot_node_name[WWN_SIZE]; | |
1082 | uint16_t alt6_boot_lun_number; | |
1083 | uint8_t alt7_boot_node_name[WWN_SIZE]; | |
1084 | uint16_t alt7_boot_lun_number; | |
1085 | ||
1086 | uint8_t reserved_3[2]; | |
1087 | ||
1088 | /* Offset 200-215 : Model Number */ | |
1089 | uint8_t model_number[16]; | |
1090 | ||
1091 | /* OEM related items */ | |
1092 | uint8_t oem_specific[16]; | |
1093 | ||
1094 | /* | |
1095 | * NVRAM Adapter Features offset 232-239 | |
1096 | * | |
1097 | * LSB BIT 0 = External GBIC | |
1098 | * LSB BIT 1 = Risc RAM parity | |
1099 | * LSB BIT 2 = Buffer Plus Module | |
1100 | * LSB BIT 3 = Multi Chip Adapter | |
1101 | * LSB BIT 4 = Internal connector | |
1102 | * LSB BIT 5 = | |
1103 | * LSB BIT 6 = | |
1104 | * LSB BIT 7 = | |
1105 | * | |
1106 | * MSB BIT 0 = | |
1107 | * MSB BIT 1 = | |
1108 | * MSB BIT 2 = | |
1109 | * MSB BIT 3 = | |
1110 | * MSB BIT 4 = | |
1111 | * MSB BIT 5 = | |
1112 | * MSB BIT 6 = | |
1113 | * MSB BIT 7 = | |
1114 | */ | |
1115 | uint8_t adapter_features[2]; | |
1116 | ||
1117 | uint8_t reserved_4[16]; | |
1118 | ||
1119 | /* Subsystem vendor ID for ISP2200 */ | |
1120 | uint16_t subsystem_vendor_id_2200; | |
1121 | ||
1122 | /* Subsystem device ID for ISP2200 */ | |
1123 | uint16_t subsystem_device_id_2200; | |
1124 | ||
1125 | uint8_t reserved_5; | |
1126 | uint8_t checksum; | |
1127 | } nvram_t; | |
1128 | ||
1129 | /* | |
1130 | * ISP queue - response queue entry definition. | |
1131 | */ | |
1132 | typedef struct { | |
1133 | uint8_t data[60]; | |
1134 | uint32_t signature; | |
1135 | #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */ | |
1136 | } response_t; | |
1137 | ||
1138 | typedef union { | |
1139 | uint16_t extended; | |
1140 | struct { | |
1141 | uint8_t reserved; | |
1142 | uint8_t standard; | |
1143 | } id; | |
1144 | } target_id_t; | |
1145 | ||
1146 | #define SET_TARGET_ID(ha, to, from) \ | |
1147 | do { \ | |
1148 | if (HAS_EXTENDED_IDS(ha)) \ | |
1149 | to.extended = cpu_to_le16(from); \ | |
1150 | else \ | |
1151 | to.id.standard = (uint8_t)from; \ | |
1152 | } while (0) | |
1153 | ||
1154 | /* | |
1155 | * ISP queue - command entry structure definition. | |
1156 | */ | |
1157 | #define COMMAND_TYPE 0x11 /* Command entry */ | |
1da177e4 LT |
1158 | typedef struct { |
1159 | uint8_t entry_type; /* Entry type. */ | |
1160 | uint8_t entry_count; /* Entry count. */ | |
1161 | uint8_t sys_define; /* System defined. */ | |
1162 | uint8_t entry_status; /* Entry Status. */ | |
1163 | uint32_t handle; /* System handle. */ | |
1164 | target_id_t target; /* SCSI ID */ | |
1165 | uint16_t lun; /* SCSI LUN */ | |
1166 | uint16_t control_flags; /* Control flags. */ | |
1167 | #define CF_WRITE BIT_6 | |
1168 | #define CF_READ BIT_5 | |
1169 | #define CF_SIMPLE_TAG BIT_3 | |
1170 | #define CF_ORDERED_TAG BIT_2 | |
1171 | #define CF_HEAD_TAG BIT_1 | |
1172 | uint16_t reserved_1; | |
1173 | uint16_t timeout; /* Command timeout. */ | |
1174 | uint16_t dseg_count; /* Data segment count. */ | |
1175 | uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ | |
1176 | uint32_t byte_count; /* Total byte count. */ | |
1177 | uint32_t dseg_0_address; /* Data segment 0 address. */ | |
1178 | uint32_t dseg_0_length; /* Data segment 0 length. */ | |
1179 | uint32_t dseg_1_address; /* Data segment 1 address. */ | |
1180 | uint32_t dseg_1_length; /* Data segment 1 length. */ | |
1181 | uint32_t dseg_2_address; /* Data segment 2 address. */ | |
1182 | uint32_t dseg_2_length; /* Data segment 2 length. */ | |
1183 | } cmd_entry_t; | |
1184 | ||
1185 | /* | |
1186 | * ISP queue - 64-Bit addressing, command entry structure definition. | |
1187 | */ | |
1188 | #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */ | |
1189 | typedef struct { | |
1190 | uint8_t entry_type; /* Entry type. */ | |
1191 | uint8_t entry_count; /* Entry count. */ | |
1192 | uint8_t sys_define; /* System defined. */ | |
1193 | uint8_t entry_status; /* Entry Status. */ | |
1194 | uint32_t handle; /* System handle. */ | |
1195 | target_id_t target; /* SCSI ID */ | |
1196 | uint16_t lun; /* SCSI LUN */ | |
1197 | uint16_t control_flags; /* Control flags. */ | |
1198 | uint16_t reserved_1; | |
1199 | uint16_t timeout; /* Command timeout. */ | |
1200 | uint16_t dseg_count; /* Data segment count. */ | |
1201 | uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ | |
1202 | uint32_t byte_count; /* Total byte count. */ | |
1203 | uint32_t dseg_0_address[2]; /* Data segment 0 address. */ | |
1204 | uint32_t dseg_0_length; /* Data segment 0 length. */ | |
1205 | uint32_t dseg_1_address[2]; /* Data segment 1 address. */ | |
1206 | uint32_t dseg_1_length; /* Data segment 1 length. */ | |
1207 | } cmd_a64_entry_t, request_t; | |
1208 | ||
1209 | /* | |
1210 | * ISP queue - continuation entry structure definition. | |
1211 | */ | |
1212 | #define CONTINUE_TYPE 0x02 /* Continuation entry. */ | |
1213 | typedef struct { | |
1214 | uint8_t entry_type; /* Entry type. */ | |
1215 | uint8_t entry_count; /* Entry count. */ | |
1216 | uint8_t sys_define; /* System defined. */ | |
1217 | uint8_t entry_status; /* Entry Status. */ | |
1218 | uint32_t reserved; | |
1219 | uint32_t dseg_0_address; /* Data segment 0 address. */ | |
1220 | uint32_t dseg_0_length; /* Data segment 0 length. */ | |
1221 | uint32_t dseg_1_address; /* Data segment 1 address. */ | |
1222 | uint32_t dseg_1_length; /* Data segment 1 length. */ | |
1223 | uint32_t dseg_2_address; /* Data segment 2 address. */ | |
1224 | uint32_t dseg_2_length; /* Data segment 2 length. */ | |
1225 | uint32_t dseg_3_address; /* Data segment 3 address. */ | |
1226 | uint32_t dseg_3_length; /* Data segment 3 length. */ | |
1227 | uint32_t dseg_4_address; /* Data segment 4 address. */ | |
1228 | uint32_t dseg_4_length; /* Data segment 4 length. */ | |
1229 | uint32_t dseg_5_address; /* Data segment 5 address. */ | |
1230 | uint32_t dseg_5_length; /* Data segment 5 length. */ | |
1231 | uint32_t dseg_6_address; /* Data segment 6 address. */ | |
1232 | uint32_t dseg_6_length; /* Data segment 6 length. */ | |
1233 | } cont_entry_t; | |
1234 | ||
1235 | /* | |
1236 | * ISP queue - 64-Bit addressing, continuation entry structure definition. | |
1237 | */ | |
1238 | #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */ | |
1239 | typedef struct { | |
1240 | uint8_t entry_type; /* Entry type. */ | |
1241 | uint8_t entry_count; /* Entry count. */ | |
1242 | uint8_t sys_define; /* System defined. */ | |
1243 | uint8_t entry_status; /* Entry Status. */ | |
1244 | uint32_t dseg_0_address[2]; /* Data segment 0 address. */ | |
1245 | uint32_t dseg_0_length; /* Data segment 0 length. */ | |
1246 | uint32_t dseg_1_address[2]; /* Data segment 1 address. */ | |
1247 | uint32_t dseg_1_length; /* Data segment 1 length. */ | |
1248 | uint32_t dseg_2_address [2]; /* Data segment 2 address. */ | |
1249 | uint32_t dseg_2_length; /* Data segment 2 length. */ | |
1250 | uint32_t dseg_3_address[2]; /* Data segment 3 address. */ | |
1251 | uint32_t dseg_3_length; /* Data segment 3 length. */ | |
1252 | uint32_t dseg_4_address[2]; /* Data segment 4 address. */ | |
1253 | uint32_t dseg_4_length; /* Data segment 4 length. */ | |
1254 | } cont_a64_entry_t; | |
1255 | ||
1256 | /* | |
1257 | * ISP queue - status entry structure definition. | |
1258 | */ | |
1259 | #define STATUS_TYPE 0x03 /* Status entry. */ | |
1260 | typedef struct { | |
1261 | uint8_t entry_type; /* Entry type. */ | |
1262 | uint8_t entry_count; /* Entry count. */ | |
1263 | uint8_t sys_define; /* System defined. */ | |
1264 | uint8_t entry_status; /* Entry Status. */ | |
1265 | uint32_t handle; /* System handle. */ | |
1266 | uint16_t scsi_status; /* SCSI status. */ | |
1267 | uint16_t comp_status; /* Completion status. */ | |
1268 | uint16_t state_flags; /* State flags. */ | |
1269 | uint16_t status_flags; /* Status flags. */ | |
1270 | uint16_t rsp_info_len; /* Response Info Length. */ | |
1271 | uint16_t req_sense_length; /* Request sense data length. */ | |
1272 | uint32_t residual_length; /* Residual transfer length. */ | |
1273 | uint8_t rsp_info[8]; /* FCP response information. */ | |
1274 | uint8_t req_sense_data[32]; /* Request sense data. */ | |
1275 | } sts_entry_t; | |
1276 | ||
1277 | /* | |
1278 | * Status entry entry status | |
1279 | */ | |
3d71644c | 1280 | #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */ |
1da177e4 LT |
1281 | #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */ |
1282 | #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */ | |
1283 | #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */ | |
1284 | #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */ | |
1285 | #define RF_BUSY BIT_1 /* Busy */ | |
3d71644c AV |
1286 | #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \ |
1287 | RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY) | |
1288 | #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \ | |
1289 | RF_INV_E_TYPE) | |
1da177e4 LT |
1290 | |
1291 | /* | |
1292 | * Status entry SCSI status bit definitions. | |
1293 | */ | |
1294 | #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/ | |
1295 | #define SS_RESIDUAL_UNDER BIT_11 | |
1296 | #define SS_RESIDUAL_OVER BIT_10 | |
1297 | #define SS_SENSE_LEN_VALID BIT_9 | |
1298 | #define SS_RESPONSE_INFO_LEN_VALID BIT_8 | |
1299 | ||
1300 | #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3) | |
1301 | #define SS_BUSY_CONDITION BIT_3 | |
1302 | #define SS_CONDITION_MET BIT_2 | |
1303 | #define SS_CHECK_CONDITION BIT_1 | |
1304 | ||
1305 | /* | |
1306 | * Status entry completion status | |
1307 | */ | |
1308 | #define CS_COMPLETE 0x0 /* No errors */ | |
1309 | #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */ | |
1310 | #define CS_DMA 0x2 /* A DMA direction error. */ | |
1311 | #define CS_TRANSPORT 0x3 /* Transport error. */ | |
1312 | #define CS_RESET 0x4 /* SCSI bus reset occurred */ | |
1313 | #define CS_ABORTED 0x5 /* System aborted command. */ | |
1314 | #define CS_TIMEOUT 0x6 /* Timeout error. */ | |
1315 | #define CS_DATA_OVERRUN 0x7 /* Data overrun. */ | |
1316 | ||
1317 | #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */ | |
1318 | #define CS_QUEUE_FULL 0x1C /* Queue Full. */ | |
1319 | #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */ | |
1320 | /* (selection timeout) */ | |
1321 | #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */ | |
1322 | #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */ | |
1323 | #define CS_PORT_BUSY 0x2B /* Port Busy */ | |
1324 | #define CS_COMPLETE_CHKCOND 0x30 /* Error? */ | |
1325 | #define CS_BAD_PAYLOAD 0x80 /* Driver defined */ | |
1326 | #define CS_UNKNOWN 0x81 /* Driver defined */ | |
1327 | #define CS_RETRY 0x82 /* Driver defined */ | |
1328 | #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */ | |
1329 | ||
1330 | /* | |
1331 | * Status entry status flags | |
1332 | */ | |
1333 | #define SF_ABTS_TERMINATED BIT_10 | |
1334 | #define SF_LOGOUT_SENT BIT_13 | |
1335 | ||
1336 | /* | |
1337 | * ISP queue - status continuation entry structure definition. | |
1338 | */ | |
1339 | #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */ | |
1340 | typedef struct { | |
1341 | uint8_t entry_type; /* Entry type. */ | |
1342 | uint8_t entry_count; /* Entry count. */ | |
1343 | uint8_t sys_define; /* System defined. */ | |
1344 | uint8_t entry_status; /* Entry Status. */ | |
1345 | uint8_t data[60]; /* data */ | |
1346 | } sts_cont_entry_t; | |
1347 | ||
1348 | /* | |
1349 | * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles) | |
1350 | * structure definition. | |
1351 | */ | |
1352 | #define STATUS_TYPE_21 0x21 /* Status entry. */ | |
1353 | typedef struct { | |
1354 | uint8_t entry_type; /* Entry type. */ | |
1355 | uint8_t entry_count; /* Entry count. */ | |
1356 | uint8_t handle_count; /* Handle count. */ | |
1357 | uint8_t entry_status; /* Entry Status. */ | |
1358 | uint32_t handle[15]; /* System handles. */ | |
1359 | } sts21_entry_t; | |
1360 | ||
1361 | /* | |
1362 | * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles) | |
1363 | * structure definition. | |
1364 | */ | |
1365 | #define STATUS_TYPE_22 0x22 /* Status entry. */ | |
1366 | typedef struct { | |
1367 | uint8_t entry_type; /* Entry type. */ | |
1368 | uint8_t entry_count; /* Entry count. */ | |
1369 | uint8_t handle_count; /* Handle count. */ | |
1370 | uint8_t entry_status; /* Entry Status. */ | |
1371 | uint16_t handle[30]; /* System handles. */ | |
1372 | } sts22_entry_t; | |
1373 | ||
1374 | /* | |
1375 | * ISP queue - marker entry structure definition. | |
1376 | */ | |
1377 | #define MARKER_TYPE 0x04 /* Marker entry. */ | |
1378 | typedef struct { | |
1379 | uint8_t entry_type; /* Entry type. */ | |
1380 | uint8_t entry_count; /* Entry count. */ | |
1381 | uint8_t handle_count; /* Handle count. */ | |
1382 | uint8_t entry_status; /* Entry Status. */ | |
1383 | uint32_t sys_define_2; /* System defined. */ | |
1384 | target_id_t target; /* SCSI ID */ | |
1385 | uint8_t modifier; /* Modifier (7-0). */ | |
1386 | #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */ | |
1387 | #define MK_SYNC_ID 1 /* Synchronize ID */ | |
1388 | #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */ | |
1389 | #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */ | |
1390 | /* clear port changed, */ | |
1391 | /* use sequence number. */ | |
1392 | uint8_t reserved_1; | |
1393 | uint16_t sequence_number; /* Sequence number of event */ | |
1394 | uint16_t lun; /* SCSI LUN */ | |
1395 | uint8_t reserved_2[48]; | |
1396 | } mrk_entry_t; | |
1397 | ||
1398 | /* | |
1399 | * ISP queue - Management Server entry structure definition. | |
1400 | */ | |
1401 | #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */ | |
1402 | typedef struct { | |
1403 | uint8_t entry_type; /* Entry type. */ | |
1404 | uint8_t entry_count; /* Entry count. */ | |
1405 | uint8_t handle_count; /* Handle count. */ | |
1406 | uint8_t entry_status; /* Entry Status. */ | |
1407 | uint32_t handle1; /* System handle. */ | |
1408 | target_id_t loop_id; | |
1409 | uint16_t status; | |
1410 | uint16_t control_flags; /* Control flags. */ | |
1411 | uint16_t reserved2; | |
1412 | uint16_t timeout; | |
1413 | uint16_t cmd_dsd_count; | |
1414 | uint16_t total_dsd_count; | |
1415 | uint8_t type; | |
1416 | uint8_t r_ctl; | |
1417 | uint16_t rx_id; | |
1418 | uint16_t reserved3; | |
1419 | uint32_t handle2; | |
1420 | uint32_t rsp_bytecount; | |
1421 | uint32_t req_bytecount; | |
1422 | uint32_t dseg_req_address[2]; /* Data segment 0 address. */ | |
1423 | uint32_t dseg_req_length; /* Data segment 0 length. */ | |
1424 | uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */ | |
1425 | uint32_t dseg_rsp_length; /* Data segment 1 length. */ | |
1426 | } ms_iocb_entry_t; | |
1427 | ||
1428 | ||
1429 | /* | |
1430 | * ISP queue - Mailbox Command entry structure definition. | |
1431 | */ | |
1432 | #define MBX_IOCB_TYPE 0x39 | |
1433 | struct mbx_entry { | |
1434 | uint8_t entry_type; | |
1435 | uint8_t entry_count; | |
1436 | uint8_t sys_define1; | |
1437 | /* Use sys_define1 for source type */ | |
1438 | #define SOURCE_SCSI 0x00 | |
1439 | #define SOURCE_IP 0x01 | |
1440 | #define SOURCE_VI 0x02 | |
1441 | #define SOURCE_SCTP 0x03 | |
1442 | #define SOURCE_MP 0x04 | |
1443 | #define SOURCE_MPIOCTL 0x05 | |
1444 | #define SOURCE_ASYNC_IOCB 0x07 | |
1445 | ||
1446 | uint8_t entry_status; | |
1447 | ||
1448 | uint32_t handle; | |
1449 | target_id_t loop_id; | |
1450 | ||
1451 | uint16_t status; | |
1452 | uint16_t state_flags; | |
1453 | uint16_t status_flags; | |
1454 | ||
1455 | uint32_t sys_define2[2]; | |
1456 | ||
1457 | uint16_t mb0; | |
1458 | uint16_t mb1; | |
1459 | uint16_t mb2; | |
1460 | uint16_t mb3; | |
1461 | uint16_t mb6; | |
1462 | uint16_t mb7; | |
1463 | uint16_t mb9; | |
1464 | uint16_t mb10; | |
1465 | uint32_t reserved_2[2]; | |
1466 | uint8_t node_name[WWN_SIZE]; | |
1467 | uint8_t port_name[WWN_SIZE]; | |
1468 | }; | |
1469 | ||
1470 | /* | |
1471 | * ISP request and response queue entry sizes | |
1472 | */ | |
1473 | #define RESPONSE_ENTRY_SIZE (sizeof(response_t)) | |
1474 | #define REQUEST_ENTRY_SIZE (sizeof(request_t)) | |
1475 | ||
1476 | ||
1477 | /* | |
1478 | * 24 bit port ID type definition. | |
1479 | */ | |
1480 | typedef union { | |
1481 | uint32_t b24 : 24; | |
1482 | ||
1483 | struct { | |
b889d531 MN |
1484 | #ifdef __BIG_ENDIAN |
1485 | uint8_t domain; | |
1486 | uint8_t area; | |
1487 | uint8_t al_pa; | |
0fd30f77 | 1488 | #elif defined(__LITTLE_ENDIAN) |
1da177e4 LT |
1489 | uint8_t al_pa; |
1490 | uint8_t area; | |
1491 | uint8_t domain; | |
b889d531 MN |
1492 | #else |
1493 | #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!" | |
1494 | #endif | |
1da177e4 LT |
1495 | uint8_t rsvd_1; |
1496 | } b; | |
1497 | } port_id_t; | |
1498 | #define INVALID_PORT_ID 0xFFFFFF | |
1499 | ||
1500 | /* | |
1501 | * Switch info gathering structure. | |
1502 | */ | |
1503 | typedef struct { | |
1504 | port_id_t d_id; | |
1505 | uint8_t node_name[WWN_SIZE]; | |
1506 | uint8_t port_name[WWN_SIZE]; | |
d8b45213 | 1507 | uint8_t fabric_port_name[WWN_SIZE]; |
d8b45213 | 1508 | uint16_t fp_speed; |
1da177e4 LT |
1509 | } sw_info_t; |
1510 | ||
1da177e4 LT |
1511 | /* |
1512 | * Fibre channel port type. | |
1513 | */ | |
1514 | typedef enum { | |
1515 | FCT_UNKNOWN, | |
1516 | FCT_RSCN, | |
1517 | FCT_SWITCH, | |
1518 | FCT_BROADCAST, | |
1519 | FCT_INITIATOR, | |
1520 | FCT_TARGET | |
1521 | } fc_port_type_t; | |
1522 | ||
1523 | /* | |
1524 | * Fibre channel port structure. | |
1525 | */ | |
1526 | typedef struct fc_port { | |
1527 | struct list_head list; | |
7b867cf7 | 1528 | struct scsi_qla_host *vha; |
1da177e4 LT |
1529 | |
1530 | uint8_t node_name[WWN_SIZE]; | |
1531 | uint8_t port_name[WWN_SIZE]; | |
1532 | port_id_t d_id; | |
1533 | uint16_t loop_id; | |
1534 | uint16_t old_loop_id; | |
1535 | ||
d8b45213 AV |
1536 | uint8_t fabric_port_name[WWN_SIZE]; |
1537 | uint16_t fp_speed; | |
1538 | ||
1da177e4 LT |
1539 | fc_port_type_t port_type; |
1540 | ||
1541 | atomic_t state; | |
1542 | uint32_t flags; | |
1543 | ||
1da177e4 LT |
1544 | int port_login_retry_count; |
1545 | int login_retry; | |
1546 | atomic_t port_down_timer; | |
1547 | ||
d97994dc | 1548 | struct fc_rport *rport, *drport; |
ad3e0eda | 1549 | u32 supported_classes; |
df7baa50 AV |
1550 | |
1551 | unsigned long last_queue_full; | |
1552 | unsigned long last_ramp_up; | |
2c3dfe3f | 1553 | |
2c3dfe3f | 1554 | uint16_t vp_idx; |
1da177e4 LT |
1555 | } fc_port_t; |
1556 | ||
1557 | /* | |
1558 | * Fibre channel port/lun states. | |
1559 | */ | |
1560 | #define FCS_UNCONFIGURED 1 | |
1561 | #define FCS_DEVICE_DEAD 2 | |
1562 | #define FCS_DEVICE_LOST 3 | |
1563 | #define FCS_ONLINE 4 | |
1da177e4 LT |
1564 | |
1565 | /* | |
1566 | * FC port flags. | |
1567 | */ | |
1568 | #define FCF_FABRIC_DEVICE BIT_0 | |
1569 | #define FCF_LOGIN_NEEDED BIT_1 | |
ddb9b126 | 1570 | #define FCF_TAPE_PRESENT BIT_2 |
1da177e4 LT |
1571 | |
1572 | /* No loop ID flag. */ | |
1573 | #define FC_NO_LOOP_ID 0x1000 | |
1574 | ||
1da177e4 LT |
1575 | /* |
1576 | * FC-CT interface | |
1577 | * | |
1578 | * NOTE: All structures are big-endian in form. | |
1579 | */ | |
1580 | ||
1581 | #define CT_REJECT_RESPONSE 0x8001 | |
1582 | #define CT_ACCEPT_RESPONSE 0x8002 | |
4346b149 | 1583 | #define CT_REASON_INVALID_COMMAND_CODE 0x01 |
cca5335c | 1584 | #define CT_REASON_CANNOT_PERFORM 0x09 |
3fe7cfb9 | 1585 | #define CT_REASON_COMMAND_UNSUPPORTED 0x0b |
cca5335c | 1586 | #define CT_EXPL_ALREADY_REGISTERED 0x10 |
1da177e4 LT |
1587 | |
1588 | #define NS_N_PORT_TYPE 0x01 | |
1589 | #define NS_NL_PORT_TYPE 0x02 | |
1590 | #define NS_NX_PORT_TYPE 0x7F | |
1591 | ||
1592 | #define GA_NXT_CMD 0x100 | |
1593 | #define GA_NXT_REQ_SIZE (16 + 4) | |
1594 | #define GA_NXT_RSP_SIZE (16 + 620) | |
1595 | ||
1596 | #define GID_PT_CMD 0x1A1 | |
1597 | #define GID_PT_REQ_SIZE (16 + 4) | |
1598 | #define GID_PT_RSP_SIZE (16 + (MAX_FIBRE_DEVICES * 4)) | |
1599 | ||
1600 | #define GPN_ID_CMD 0x112 | |
1601 | #define GPN_ID_REQ_SIZE (16 + 4) | |
1602 | #define GPN_ID_RSP_SIZE (16 + 8) | |
1603 | ||
1604 | #define GNN_ID_CMD 0x113 | |
1605 | #define GNN_ID_REQ_SIZE (16 + 4) | |
1606 | #define GNN_ID_RSP_SIZE (16 + 8) | |
1607 | ||
1608 | #define GFT_ID_CMD 0x117 | |
1609 | #define GFT_ID_REQ_SIZE (16 + 4) | |
1610 | #define GFT_ID_RSP_SIZE (16 + 32) | |
1611 | ||
1612 | #define RFT_ID_CMD 0x217 | |
1613 | #define RFT_ID_REQ_SIZE (16 + 4 + 32) | |
1614 | #define RFT_ID_RSP_SIZE 16 | |
1615 | ||
1616 | #define RFF_ID_CMD 0x21F | |
1617 | #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1) | |
1618 | #define RFF_ID_RSP_SIZE 16 | |
1619 | ||
1620 | #define RNN_ID_CMD 0x213 | |
1621 | #define RNN_ID_REQ_SIZE (16 + 4 + 8) | |
1622 | #define RNN_ID_RSP_SIZE 16 | |
1623 | ||
1624 | #define RSNN_NN_CMD 0x239 | |
1625 | #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255) | |
1626 | #define RSNN_NN_RSP_SIZE 16 | |
1627 | ||
d8b45213 AV |
1628 | #define GFPN_ID_CMD 0x11C |
1629 | #define GFPN_ID_REQ_SIZE (16 + 4) | |
1630 | #define GFPN_ID_RSP_SIZE (16 + 8) | |
1631 | ||
1632 | #define GPSC_CMD 0x127 | |
1633 | #define GPSC_REQ_SIZE (16 + 8) | |
1634 | #define GPSC_RSP_SIZE (16 + 2 + 2) | |
1635 | ||
1636 | ||
cca5335c AV |
1637 | /* |
1638 | * HBA attribute types. | |
1639 | */ | |
1640 | #define FDMI_HBA_ATTR_COUNT 9 | |
1641 | #define FDMI_HBA_NODE_NAME 1 | |
1642 | #define FDMI_HBA_MANUFACTURER 2 | |
1643 | #define FDMI_HBA_SERIAL_NUMBER 3 | |
1644 | #define FDMI_HBA_MODEL 4 | |
1645 | #define FDMI_HBA_MODEL_DESCRIPTION 5 | |
1646 | #define FDMI_HBA_HARDWARE_VERSION 6 | |
1647 | #define FDMI_HBA_DRIVER_VERSION 7 | |
1648 | #define FDMI_HBA_OPTION_ROM_VERSION 8 | |
1649 | #define FDMI_HBA_FIRMWARE_VERSION 9 | |
1650 | #define FDMI_HBA_OS_NAME_AND_VERSION 0xa | |
1651 | #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb | |
1652 | ||
1653 | struct ct_fdmi_hba_attr { | |
1654 | uint16_t type; | |
1655 | uint16_t len; | |
1656 | union { | |
1657 | uint8_t node_name[WWN_SIZE]; | |
1658 | uint8_t manufacturer[32]; | |
1659 | uint8_t serial_num[8]; | |
1660 | uint8_t model[16]; | |
1661 | uint8_t model_desc[80]; | |
1662 | uint8_t hw_version[16]; | |
1663 | uint8_t driver_version[32]; | |
1664 | uint8_t orom_version[16]; | |
1665 | uint8_t fw_version[16]; | |
1666 | uint8_t os_version[128]; | |
1667 | uint8_t max_ct_len[4]; | |
1668 | } a; | |
1669 | }; | |
1670 | ||
1671 | struct ct_fdmi_hba_attributes { | |
1672 | uint32_t count; | |
1673 | struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT]; | |
1674 | }; | |
1675 | ||
1676 | /* | |
1677 | * Port attribute types. | |
1678 | */ | |
8a85e171 | 1679 | #define FDMI_PORT_ATTR_COUNT 6 |
cca5335c AV |
1680 | #define FDMI_PORT_FC4_TYPES 1 |
1681 | #define FDMI_PORT_SUPPORT_SPEED 2 | |
1682 | #define FDMI_PORT_CURRENT_SPEED 3 | |
1683 | #define FDMI_PORT_MAX_FRAME_SIZE 4 | |
1684 | #define FDMI_PORT_OS_DEVICE_NAME 5 | |
1685 | #define FDMI_PORT_HOST_NAME 6 | |
1686 | ||
5881569b AV |
1687 | #define FDMI_PORT_SPEED_1GB 0x1 |
1688 | #define FDMI_PORT_SPEED_2GB 0x2 | |
1689 | #define FDMI_PORT_SPEED_10GB 0x4 | |
1690 | #define FDMI_PORT_SPEED_4GB 0x8 | |
1691 | #define FDMI_PORT_SPEED_8GB 0x10 | |
1692 | #define FDMI_PORT_SPEED_16GB 0x20 | |
1693 | #define FDMI_PORT_SPEED_UNKNOWN 0x8000 | |
1694 | ||
cca5335c AV |
1695 | struct ct_fdmi_port_attr { |
1696 | uint16_t type; | |
1697 | uint16_t len; | |
1698 | union { | |
1699 | uint8_t fc4_types[32]; | |
1700 | uint32_t sup_speed; | |
1701 | uint32_t cur_speed; | |
1702 | uint32_t max_frame_size; | |
1703 | uint8_t os_dev_name[32]; | |
1704 | uint8_t host_name[32]; | |
1705 | } a; | |
1706 | }; | |
1707 | ||
1708 | /* | |
1709 | * Port Attribute Block. | |
1710 | */ | |
1711 | struct ct_fdmi_port_attributes { | |
1712 | uint32_t count; | |
1713 | struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT]; | |
1714 | }; | |
1715 | ||
1716 | /* FDMI definitions. */ | |
1717 | #define GRHL_CMD 0x100 | |
1718 | #define GHAT_CMD 0x101 | |
1719 | #define GRPL_CMD 0x102 | |
1720 | #define GPAT_CMD 0x110 | |
1721 | ||
1722 | #define RHBA_CMD 0x200 | |
1723 | #define RHBA_RSP_SIZE 16 | |
1724 | ||
1725 | #define RHAT_CMD 0x201 | |
1726 | #define RPRT_CMD 0x210 | |
1727 | ||
1728 | #define RPA_CMD 0x211 | |
1729 | #define RPA_RSP_SIZE 16 | |
1730 | ||
1731 | #define DHBA_CMD 0x300 | |
1732 | #define DHBA_REQ_SIZE (16 + 8) | |
1733 | #define DHBA_RSP_SIZE 16 | |
1734 | ||
1735 | #define DHAT_CMD 0x301 | |
1736 | #define DPRT_CMD 0x310 | |
1737 | #define DPA_CMD 0x311 | |
1738 | ||
1da177e4 LT |
1739 | /* CT command header -- request/response common fields */ |
1740 | struct ct_cmd_hdr { | |
1741 | uint8_t revision; | |
1742 | uint8_t in_id[3]; | |
1743 | uint8_t gs_type; | |
1744 | uint8_t gs_subtype; | |
1745 | uint8_t options; | |
1746 | uint8_t reserved; | |
1747 | }; | |
1748 | ||
1749 | /* CT command request */ | |
1750 | struct ct_sns_req { | |
1751 | struct ct_cmd_hdr header; | |
1752 | uint16_t command; | |
1753 | uint16_t max_rsp_size; | |
1754 | uint8_t fragment_id; | |
1755 | uint8_t reserved[3]; | |
1756 | ||
1757 | union { | |
d8b45213 | 1758 | /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */ |
1da177e4 LT |
1759 | struct { |
1760 | uint8_t reserved; | |
1761 | uint8_t port_id[3]; | |
1762 | } port_id; | |
1763 | ||
1764 | struct { | |
1765 | uint8_t port_type; | |
1766 | uint8_t domain; | |
1767 | uint8_t area; | |
1768 | uint8_t reserved; | |
1769 | } gid_pt; | |
1770 | ||
1771 | struct { | |
1772 | uint8_t reserved; | |
1773 | uint8_t port_id[3]; | |
1774 | uint8_t fc4_types[32]; | |
1775 | } rft_id; | |
1776 | ||
1777 | struct { | |
1778 | uint8_t reserved; | |
1779 | uint8_t port_id[3]; | |
1780 | uint16_t reserved2; | |
1781 | uint8_t fc4_feature; | |
1782 | uint8_t fc4_type; | |
1783 | } rff_id; | |
1784 | ||
1785 | struct { | |
1786 | uint8_t reserved; | |
1787 | uint8_t port_id[3]; | |
1788 | uint8_t node_name[8]; | |
1789 | } rnn_id; | |
1790 | ||
1791 | struct { | |
1792 | uint8_t node_name[8]; | |
1793 | uint8_t name_len; | |
1794 | uint8_t sym_node_name[255]; | |
1795 | } rsnn_nn; | |
cca5335c AV |
1796 | |
1797 | struct { | |
1798 | uint8_t hba_indentifier[8]; | |
1799 | } ghat; | |
1800 | ||
1801 | struct { | |
1802 | uint8_t hba_identifier[8]; | |
1803 | uint32_t entry_count; | |
1804 | uint8_t port_name[8]; | |
1805 | struct ct_fdmi_hba_attributes attrs; | |
1806 | } rhba; | |
1807 | ||
1808 | struct { | |
1809 | uint8_t hba_identifier[8]; | |
1810 | struct ct_fdmi_hba_attributes attrs; | |
1811 | } rhat; | |
1812 | ||
1813 | struct { | |
1814 | uint8_t port_name[8]; | |
1815 | struct ct_fdmi_port_attributes attrs; | |
1816 | } rpa; | |
1817 | ||
1818 | struct { | |
1819 | uint8_t port_name[8]; | |
1820 | } dhba; | |
1821 | ||
1822 | struct { | |
1823 | uint8_t port_name[8]; | |
1824 | } dhat; | |
1825 | ||
1826 | struct { | |
1827 | uint8_t port_name[8]; | |
1828 | } dprt; | |
1829 | ||
1830 | struct { | |
1831 | uint8_t port_name[8]; | |
1832 | } dpa; | |
d8b45213 AV |
1833 | |
1834 | struct { | |
1835 | uint8_t port_name[8]; | |
1836 | } gpsc; | |
1da177e4 LT |
1837 | } req; |
1838 | }; | |
1839 | ||
1840 | /* CT command response header */ | |
1841 | struct ct_rsp_hdr { | |
1842 | struct ct_cmd_hdr header; | |
1843 | uint16_t response; | |
1844 | uint16_t residual; | |
1845 | uint8_t fragment_id; | |
1846 | uint8_t reason_code; | |
1847 | uint8_t explanation_code; | |
1848 | uint8_t vendor_unique; | |
1849 | }; | |
1850 | ||
1851 | struct ct_sns_gid_pt_data { | |
1852 | uint8_t control_byte; | |
1853 | uint8_t port_id[3]; | |
1854 | }; | |
1855 | ||
1856 | struct ct_sns_rsp { | |
1857 | struct ct_rsp_hdr header; | |
1858 | ||
1859 | union { | |
1860 | struct { | |
1861 | uint8_t port_type; | |
1862 | uint8_t port_id[3]; | |
1863 | uint8_t port_name[8]; | |
1864 | uint8_t sym_port_name_len; | |
1865 | uint8_t sym_port_name[255]; | |
1866 | uint8_t node_name[8]; | |
1867 | uint8_t sym_node_name_len; | |
1868 | uint8_t sym_node_name[255]; | |
1869 | uint8_t init_proc_assoc[8]; | |
1870 | uint8_t node_ip_addr[16]; | |
1871 | uint8_t class_of_service[4]; | |
1872 | uint8_t fc4_types[32]; | |
1873 | uint8_t ip_address[16]; | |
1874 | uint8_t fabric_port_name[8]; | |
1875 | uint8_t reserved; | |
1876 | uint8_t hard_address[3]; | |
1877 | } ga_nxt; | |
1878 | ||
1879 | struct { | |
1880 | struct ct_sns_gid_pt_data entries[MAX_FIBRE_DEVICES]; | |
1881 | } gid_pt; | |
1882 | ||
1883 | struct { | |
1884 | uint8_t port_name[8]; | |
1885 | } gpn_id; | |
1886 | ||
1887 | struct { | |
1888 | uint8_t node_name[8]; | |
1889 | } gnn_id; | |
1890 | ||
1891 | struct { | |
1892 | uint8_t fc4_types[32]; | |
1893 | } gft_id; | |
cca5335c AV |
1894 | |
1895 | struct { | |
1896 | uint32_t entry_count; | |
1897 | uint8_t port_name[8]; | |
1898 | struct ct_fdmi_hba_attributes attrs; | |
1899 | } ghat; | |
d8b45213 AV |
1900 | |
1901 | struct { | |
1902 | uint8_t port_name[8]; | |
1903 | } gfpn_id; | |
1904 | ||
1905 | struct { | |
1906 | uint16_t speeds; | |
1907 | uint16_t speed; | |
1908 | } gpsc; | |
1da177e4 LT |
1909 | } rsp; |
1910 | }; | |
1911 | ||
1912 | struct ct_sns_pkt { | |
1913 | union { | |
1914 | struct ct_sns_req req; | |
1915 | struct ct_sns_rsp rsp; | |
1916 | } p; | |
1917 | }; | |
1918 | ||
1919 | /* | |
1920 | * SNS command structures -- for 2200 compatability. | |
1921 | */ | |
1922 | #define RFT_ID_SNS_SCMD_LEN 22 | |
1923 | #define RFT_ID_SNS_CMD_SIZE 60 | |
1924 | #define RFT_ID_SNS_DATA_SIZE 16 | |
1925 | ||
1926 | #define RNN_ID_SNS_SCMD_LEN 10 | |
1927 | #define RNN_ID_SNS_CMD_SIZE 36 | |
1928 | #define RNN_ID_SNS_DATA_SIZE 16 | |
1929 | ||
1930 | #define GA_NXT_SNS_SCMD_LEN 6 | |
1931 | #define GA_NXT_SNS_CMD_SIZE 28 | |
1932 | #define GA_NXT_SNS_DATA_SIZE (620 + 16) | |
1933 | ||
1934 | #define GID_PT_SNS_SCMD_LEN 6 | |
1935 | #define GID_PT_SNS_CMD_SIZE 28 | |
1936 | #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES * 4 + 16) | |
1937 | ||
1938 | #define GPN_ID_SNS_SCMD_LEN 6 | |
1939 | #define GPN_ID_SNS_CMD_SIZE 28 | |
1940 | #define GPN_ID_SNS_DATA_SIZE (8 + 16) | |
1941 | ||
1942 | #define GNN_ID_SNS_SCMD_LEN 6 | |
1943 | #define GNN_ID_SNS_CMD_SIZE 28 | |
1944 | #define GNN_ID_SNS_DATA_SIZE (8 + 16) | |
1945 | ||
1946 | struct sns_cmd_pkt { | |
1947 | union { | |
1948 | struct { | |
1949 | uint16_t buffer_length; | |
1950 | uint16_t reserved_1; | |
1951 | uint32_t buffer_address[2]; | |
1952 | uint16_t subcommand_length; | |
1953 | uint16_t reserved_2; | |
1954 | uint16_t subcommand; | |
1955 | uint16_t size; | |
1956 | uint32_t reserved_3; | |
1957 | uint8_t param[36]; | |
1958 | } cmd; | |
1959 | ||
1960 | uint8_t rft_data[RFT_ID_SNS_DATA_SIZE]; | |
1961 | uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE]; | |
1962 | uint8_t gan_data[GA_NXT_SNS_DATA_SIZE]; | |
1963 | uint8_t gid_data[GID_PT_SNS_DATA_SIZE]; | |
1964 | uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE]; | |
1965 | uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE]; | |
1966 | } p; | |
1967 | }; | |
1968 | ||
5433383e AV |
1969 | struct fw_blob { |
1970 | char *name; | |
1971 | uint32_t segs[4]; | |
1972 | const struct firmware *fw; | |
1973 | }; | |
1974 | ||
1da177e4 LT |
1975 | /* Return data from MBC_GET_ID_LIST call. */ |
1976 | struct gid_list_info { | |
1977 | uint8_t al_pa; | |
1978 | uint8_t area; | |
fa2a1ce5 | 1979 | uint8_t domain; |
1da177e4 LT |
1980 | uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */ |
1981 | uint16_t loop_id; /* ISP23XX -- 6 bytes. */ | |
3d71644c | 1982 | uint16_t reserved_1; /* ISP24XX -- 8 bytes. */ |
1da177e4 LT |
1983 | }; |
1984 | #define GID_LIST_SIZE (sizeof(struct gid_list_info) * MAX_FIBRE_DEVICES) | |
1985 | ||
2c3dfe3f SJ |
1986 | /* NPIV */ |
1987 | typedef struct vport_info { | |
1988 | uint8_t port_name[WWN_SIZE]; | |
1989 | uint8_t node_name[WWN_SIZE]; | |
1990 | int vp_id; | |
1991 | uint16_t loop_id; | |
1992 | unsigned long host_no; | |
1993 | uint8_t port_id[3]; | |
1994 | int loop_state; | |
1995 | } vport_info_t; | |
1996 | ||
1997 | typedef struct vport_params { | |
1998 | uint8_t port_name[WWN_SIZE]; | |
1999 | uint8_t node_name[WWN_SIZE]; | |
2000 | uint32_t options; | |
2001 | #define VP_OPTS_RETRY_ENABLE BIT_0 | |
2002 | #define VP_OPTS_VP_DISABLE BIT_1 | |
2003 | } vport_params_t; | |
2004 | ||
2005 | /* NPIV - return codes of VP create and modify */ | |
2006 | #define VP_RET_CODE_OK 0 | |
2007 | #define VP_RET_CODE_FATAL 1 | |
2008 | #define VP_RET_CODE_WRONG_ID 2 | |
2009 | #define VP_RET_CODE_WWPN 3 | |
2010 | #define VP_RET_CODE_RESOURCES 4 | |
2011 | #define VP_RET_CODE_NO_MEM 5 | |
2012 | #define VP_RET_CODE_NOT_FOUND 6 | |
2013 | ||
7b867cf7 | 2014 | struct qla_hw_data; |
2afa19a9 | 2015 | struct rsp_que; |
abbd8870 AV |
2016 | /* |
2017 | * ISP operations | |
2018 | */ | |
2019 | struct isp_operations { | |
2020 | ||
2021 | int (*pci_config) (struct scsi_qla_host *); | |
2022 | void (*reset_chip) (struct scsi_qla_host *); | |
2023 | int (*chip_diag) (struct scsi_qla_host *); | |
2024 | void (*config_rings) (struct scsi_qla_host *); | |
2025 | void (*reset_adapter) (struct scsi_qla_host *); | |
2026 | int (*nvram_config) (struct scsi_qla_host *); | |
2027 | void (*update_fw_options) (struct scsi_qla_host *); | |
2028 | int (*load_risc) (struct scsi_qla_host *, uint32_t *); | |
2029 | ||
2030 | char * (*pci_info_str) (struct scsi_qla_host *, char *); | |
2031 | char * (*fw_version_str) (struct scsi_qla_host *, char *); | |
2032 | ||
7d12e780 | 2033 | irq_handler_t intr_handler; |
7b867cf7 AC |
2034 | void (*enable_intrs) (struct qla_hw_data *); |
2035 | void (*disable_intrs) (struct qla_hw_data *); | |
abbd8870 | 2036 | |
2afa19a9 AC |
2037 | int (*abort_command) (srb_t *); |
2038 | int (*target_reset) (struct fc_port *, unsigned int, int); | |
2039 | int (*lun_reset) (struct fc_port *, unsigned int, int); | |
abbd8870 AV |
2040 | int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t, |
2041 | uint8_t, uint8_t, uint16_t *, uint8_t); | |
1c7c6357 AV |
2042 | int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t, |
2043 | uint8_t, uint8_t); | |
abbd8870 AV |
2044 | |
2045 | uint16_t (*calc_req_entries) (uint16_t); | |
2046 | void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t); | |
8c958a99 | 2047 | void * (*prep_ms_iocb) (struct scsi_qla_host *, uint32_t, uint32_t); |
cca5335c AV |
2048 | void * (*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t, |
2049 | uint32_t); | |
abbd8870 AV |
2050 | |
2051 | uint8_t * (*read_nvram) (struct scsi_qla_host *, uint8_t *, | |
2052 | uint32_t, uint32_t); | |
2053 | int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t, | |
2054 | uint32_t); | |
2055 | ||
2056 | void (*fw_dump) (struct scsi_qla_host *, int); | |
f6df144c AV |
2057 | |
2058 | int (*beacon_on) (struct scsi_qla_host *); | |
2059 | int (*beacon_off) (struct scsi_qla_host *); | |
2060 | void (*beacon_blink) (struct scsi_qla_host *); | |
854165f4 AV |
2061 | |
2062 | uint8_t * (*read_optrom) (struct scsi_qla_host *, uint8_t *, | |
2063 | uint32_t, uint32_t); | |
2064 | int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t, | |
2065 | uint32_t); | |
30c47662 AV |
2066 | |
2067 | int (*get_flash_version) (struct scsi_qla_host *, void *); | |
7b867cf7 | 2068 | int (*start_scsi) (srb_t *); |
abbd8870 AV |
2069 | }; |
2070 | ||
a8488abe AV |
2071 | /* MSI-X Support *************************************************************/ |
2072 | ||
2073 | #define QLA_MSIX_CHIP_REV_24XX 3 | |
2074 | #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7) | |
2075 | #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1) | |
2076 | ||
2077 | #define QLA_MSIX_DEFAULT 0x00 | |
2078 | #define QLA_MSIX_RSP_Q 0x01 | |
2079 | ||
a8488abe AV |
2080 | #define QLA_MIDX_DEFAULT 0 |
2081 | #define QLA_MIDX_RSP_Q 1 | |
73208dfd | 2082 | #define QLA_PCI_MSIX_CONTROL 0xa2 |
a8488abe AV |
2083 | |
2084 | struct scsi_qla_host; | |
2085 | ||
2086 | struct qla_msix_entry { | |
2087 | int have_irq; | |
73208dfd AC |
2088 | uint32_t vector; |
2089 | uint16_t entry; | |
2090 | struct rsp_que *rsp; | |
a8488abe AV |
2091 | }; |
2092 | ||
2c3dfe3f SJ |
2093 | #define WATCH_INTERVAL 1 /* number of seconds */ |
2094 | ||
0971de7f AV |
2095 | /* Work events. */ |
2096 | enum qla_work_type { | |
2097 | QLA_EVT_AEN, | |
8a659571 | 2098 | QLA_EVT_IDC_ACK, |
0971de7f AV |
2099 | }; |
2100 | ||
2101 | ||
2102 | struct qla_work_evt { | |
2103 | struct list_head list; | |
2104 | enum qla_work_type type; | |
2105 | u32 flags; | |
2106 | #define QLA_EVT_FLAG_FREE 0x1 | |
2107 | ||
2108 | union { | |
2109 | struct { | |
2110 | enum fc_host_event_code code; | |
2111 | u32 data; | |
2112 | } aen; | |
8a659571 AV |
2113 | struct { |
2114 | #define QLA_IDC_ACK_REGS 7 | |
2115 | uint16_t mb[QLA_IDC_ACK_REGS]; | |
2116 | } idc_ack; | |
0971de7f AV |
2117 | } u; |
2118 | }; | |
2119 | ||
4d4df193 HK |
2120 | struct qla_chip_state_84xx { |
2121 | struct list_head list; | |
2122 | struct kref kref; | |
2123 | ||
2124 | void *bus; | |
2125 | spinlock_t access_lock; | |
2126 | struct mutex fw_update_mutex; | |
2127 | uint32_t fw_update; | |
2128 | uint32_t op_fw_version; | |
2129 | uint32_t op_fw_size; | |
2130 | uint32_t op_fw_seq_size; | |
2131 | uint32_t diag_fw_version; | |
2132 | uint32_t gold_fw_version; | |
2133 | }; | |
2134 | ||
e5f5f6f7 HZ |
2135 | struct qla_statistics { |
2136 | uint32_t total_isp_aborts; | |
49fd462a HZ |
2137 | uint64_t input_bytes; |
2138 | uint64_t output_bytes; | |
e5f5f6f7 HZ |
2139 | }; |
2140 | ||
73208dfd AC |
2141 | /* Multi queue support */ |
2142 | #define MBC_INITIALIZE_MULTIQ 0x1f | |
2143 | #define QLA_QUE_PAGE 0X1000 | |
2144 | #define QLA_MQ_SIZE 32 | |
73208dfd AC |
2145 | #define QLA_MAX_QUEUES 256 |
2146 | #define ISP_QUE_REG(ha, id) \ | |
2147 | ((ha->mqenable) ? \ | |
2148 | ((void *)(ha->mqiobase) +\ | |
2149 | (QLA_QUE_PAGE * id)) :\ | |
2150 | ((void *)(ha->iobase))) | |
2151 | #define QLA_REQ_QUE_ID(tag) \ | |
2152 | ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0) | |
2153 | #define QLA_DEFAULT_QUE_QOS 5 | |
2154 | #define QLA_PRECONFIG_VPORTS 32 | |
2155 | #define QLA_MAX_VPORTS_QLA24XX 128 | |
2156 | #define QLA_MAX_VPORTS_QLA25XX 256 | |
7b867cf7 AC |
2157 | /* Response queue data structure */ |
2158 | struct rsp_que { | |
2159 | dma_addr_t dma; | |
2160 | response_t *ring; | |
2161 | response_t *ring_ptr; | |
08029990 AV |
2162 | uint32_t __iomem *rsp_q_in; /* FWI2-capable only. */ |
2163 | uint32_t __iomem *rsp_q_out; | |
7b867cf7 AC |
2164 | uint16_t ring_index; |
2165 | uint16_t out_ptr; | |
2166 | uint16_t length; | |
2167 | uint16_t options; | |
7b867cf7 | 2168 | uint16_t rid; |
73208dfd AC |
2169 | uint16_t id; |
2170 | uint16_t vp_idx; | |
7b867cf7 | 2171 | struct qla_hw_data *hw; |
73208dfd AC |
2172 | struct qla_msix_entry *msix; |
2173 | struct req_que *req; | |
2afa19a9 | 2174 | srb_t *status_srb; /* status continuation entry */ |
68ca949c | 2175 | struct work_struct q_work; |
7b867cf7 | 2176 | }; |
1da177e4 | 2177 | |
7b867cf7 AC |
2178 | /* Request queue data structure */ |
2179 | struct req_que { | |
2180 | dma_addr_t dma; | |
2181 | request_t *ring; | |
2182 | request_t *ring_ptr; | |
08029990 AV |
2183 | uint32_t __iomem *req_q_in; /* FWI2-capable only. */ |
2184 | uint32_t __iomem *req_q_out; | |
7b867cf7 AC |
2185 | uint16_t ring_index; |
2186 | uint16_t in_ptr; | |
2187 | uint16_t cnt; | |
2188 | uint16_t length; | |
2189 | uint16_t options; | |
2190 | uint16_t rid; | |
73208dfd | 2191 | uint16_t id; |
7b867cf7 AC |
2192 | uint16_t qos; |
2193 | uint16_t vp_idx; | |
73208dfd | 2194 | struct rsp_que *rsp; |
7b867cf7 AC |
2195 | srb_t *outstanding_cmds[MAX_OUTSTANDING_COMMANDS]; |
2196 | uint32_t current_outstanding_cmd; | |
2197 | int max_q_depth; | |
2198 | }; | |
1da177e4 | 2199 | |
7b867cf7 AC |
2200 | /* |
2201 | * Qlogic host adapter specific data structure. | |
2202 | */ | |
2203 | struct qla_hw_data { | |
2204 | struct pci_dev *pdev; | |
2205 | /* SRB cache. */ | |
2206 | #define SRB_MIN_REQ 128 | |
2207 | mempool_t *srb_mempool; | |
1da177e4 LT |
2208 | |
2209 | volatile struct { | |
1da177e4 LT |
2210 | uint32_t mbox_int :1; |
2211 | uint32_t mbox_busy :1; | |
1da177e4 LT |
2212 | |
2213 | uint32_t disable_risc_code_load :1; | |
2214 | uint32_t enable_64bit_addressing :1; | |
2215 | uint32_t enable_lip_reset :1; | |
1da177e4 | 2216 | uint32_t enable_target_reset :1; |
7b867cf7 | 2217 | uint32_t enable_lip_full_login :1; |
1da177e4 | 2218 | uint32_t enable_led_scheme :1; |
d88021a6 | 2219 | uint32_t inta_enabled :1; |
3d71644c AV |
2220 | uint32_t msi_enabled :1; |
2221 | uint32_t msix_enabled :1; | |
d4c760c2 | 2222 | uint32_t disable_serdes :1; |
4346b149 | 2223 | uint32_t gpsc_supported :1; |
2c3dfe3f | 2224 | uint32_t npiv_supported :1; |
df613b96 | 2225 | uint32_t fce_enabled :1; |
1d2874de | 2226 | uint32_t fac_supported :1; |
2533cf67 | 2227 | uint32_t chip_reset_done :1; |
e5b68a61 | 2228 | uint32_t port0 :1; |
cbc8eb67 | 2229 | uint32_t running_gold_fw :1; |
7163ea81 | 2230 | uint32_t cpu_affinity_enabled :1; |
1da177e4 LT |
2231 | } flags; |
2232 | ||
fa2a1ce5 | 2233 | /* This spinlock is used to protect "io transactions", you must |
7b867cf7 AC |
2234 | * acquire it before doing any IO to the card, eg with RD_REG*() and |
2235 | * WRT_REG*() for the duration of your entire commandtransaction. | |
2236 | * | |
2237 | * This spinlock is of lower priority than the io request lock. | |
2238 | */ | |
1da177e4 | 2239 | |
7b867cf7 | 2240 | spinlock_t hardware_lock ____cacheline_aligned; |
285d0321 | 2241 | int bars; |
09483916 | 2242 | int mem_only; |
7b867cf7 | 2243 | device_reg_t __iomem *iobase; /* Base I/O address */ |
3776541d | 2244 | resource_size_t pio_address; |
fa2a1ce5 | 2245 | |
7b867cf7 | 2246 | #define MIN_IOBASE_LEN 0x100 |
73208dfd | 2247 | /* Multi queue data structs */ |
08029990 | 2248 | device_reg_t __iomem *mqiobase; |
73208dfd AC |
2249 | uint16_t msix_count; |
2250 | uint8_t mqenable; | |
2251 | struct req_que **req_q_map; | |
2252 | struct rsp_que **rsp_q_map; | |
2253 | unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; | |
2254 | unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; | |
2afa19a9 AC |
2255 | uint8_t max_req_queues; |
2256 | uint8_t max_rsp_queues; | |
73208dfd AC |
2257 | struct qla_npiv_entry *npiv_info; |
2258 | uint16_t nvram_npiv_size; | |
1da177e4 | 2259 | |
7b867cf7 AC |
2260 | uint16_t switch_cap; |
2261 | #define FLOGI_SEQ_DEL BIT_8 | |
2262 | #define FLOGI_MID_SUPPORT BIT_10 | |
2263 | #define FLOGI_VSAN_SUPPORT BIT_12 | |
2264 | #define FLOGI_SP_SUPPORT BIT_13 | |
e5b68a61 AC |
2265 | |
2266 | uint8_t port_no; /* Physical port of adapter */ | |
2267 | ||
7b867cf7 AC |
2268 | /* Timeout timers. */ |
2269 | uint8_t loop_down_abort_time; /* port down timer */ | |
2270 | atomic_t loop_down_timer; /* loop down timer */ | |
2271 | uint8_t link_down_timeout; /* link down timeout */ | |
2272 | uint16_t max_loop_id; | |
1da177e4 | 2273 | |
1da177e4 | 2274 | uint16_t fb_rev; |
7b867cf7 | 2275 | uint16_t min_external_loopid; /* First external loop Id */ |
1da177e4 | 2276 | |
d8b45213 | 2277 | #define PORT_SPEED_UNKNOWN 0xFFFF |
7b867cf7 AC |
2278 | #define PORT_SPEED_1GB 0x00 |
2279 | #define PORT_SPEED_2GB 0x01 | |
2280 | #define PORT_SPEED_4GB 0x03 | |
2281 | #define PORT_SPEED_8GB 0x04 | |
3a03eb79 | 2282 | #define PORT_SPEED_10GB 0x13 |
7b867cf7 | 2283 | uint16_t link_data_rate; /* F/W operating speed */ |
1da177e4 LT |
2284 | |
2285 | uint8_t current_topology; | |
2286 | uint8_t prev_topology; | |
2287 | #define ISP_CFG_NL 1 | |
2288 | #define ISP_CFG_N 2 | |
2289 | #define ISP_CFG_FL 4 | |
2290 | #define ISP_CFG_F 8 | |
2291 | ||
7b867cf7 | 2292 | uint8_t operating_mode; /* F/W operating mode */ |
1da177e4 LT |
2293 | #define LOOP 0 |
2294 | #define P2P 1 | |
2295 | #define LOOP_P2P 2 | |
2296 | #define P2P_LOOP 3 | |
1da177e4 | 2297 | uint8_t interrupts_on; |
7b867cf7 AC |
2298 | uint32_t isp_abort_cnt; |
2299 | ||
2300 | #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532 | |
2301 | #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432 | |
3a03eb79 | 2302 | #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001 |
7b867cf7 AC |
2303 | uint32_t device_type; |
2304 | #define DT_ISP2100 BIT_0 | |
2305 | #define DT_ISP2200 BIT_1 | |
2306 | #define DT_ISP2300 BIT_2 | |
2307 | #define DT_ISP2312 BIT_3 | |
2308 | #define DT_ISP2322 BIT_4 | |
2309 | #define DT_ISP6312 BIT_5 | |
2310 | #define DT_ISP6322 BIT_6 | |
2311 | #define DT_ISP2422 BIT_7 | |
2312 | #define DT_ISP2432 BIT_8 | |
2313 | #define DT_ISP5422 BIT_9 | |
2314 | #define DT_ISP5432 BIT_10 | |
2315 | #define DT_ISP2532 BIT_11 | |
2316 | #define DT_ISP8432 BIT_12 | |
3a03eb79 AV |
2317 | #define DT_ISP8001 BIT_13 |
2318 | #define DT_ISP_LAST (DT_ISP8001 << 1) | |
7b867cf7 AC |
2319 | |
2320 | #define DT_IIDMA BIT_26 | |
2321 | #define DT_FWI2 BIT_27 | |
2322 | #define DT_ZIO_SUPPORTED BIT_28 | |
2323 | #define DT_OEM_001 BIT_29 | |
2324 | #define DT_ISP2200A BIT_30 | |
2325 | #define DT_EXTENDED_IDS BIT_31 | |
2326 | #define DT_MASK(ha) ((ha)->device_type & (DT_ISP_LAST - 1)) | |
2327 | #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100) | |
2328 | #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200) | |
2329 | #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300) | |
2330 | #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312) | |
2331 | #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322) | |
2332 | #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312) | |
2333 | #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322) | |
2334 | #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422) | |
2335 | #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432) | |
2336 | #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422) | |
2337 | #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432) | |
2338 | #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532) | |
2339 | #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432) | |
3a03eb79 | 2340 | #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001) |
7b867cf7 AC |
2341 | |
2342 | #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \ | |
2343 | IS_QLA6312(ha) || IS_QLA6322(ha)) | |
2344 | #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha)) | |
2345 | #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha)) | |
2346 | #define IS_QLA25XX(ha) (IS_QLA2532(ha)) | |
2347 | #define IS_QLA84XX(ha) (IS_QLA8432(ha)) | |
2348 | #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \ | |
2349 | IS_QLA84XX(ha)) | |
3a03eb79 | 2350 | #define IS_QLA81XX(ha) (IS_QLA8001(ha)) |
7b867cf7 | 2351 | #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \ |
3a03eb79 AV |
2352 | IS_QLA25XX(ha) || IS_QLA81XX(ha)) |
2353 | #define IS_NOPOLLING_TYPE(ha) ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && \ | |
124f85e6 | 2354 | (ha)->flags.msix_enabled) |
1d2874de | 2355 | #define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha)) |
6749ce36 | 2356 | #define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha)) |
7b867cf7 AC |
2357 | |
2358 | #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA) | |
2359 | #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2) | |
2360 | #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED) | |
2361 | #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001) | |
2362 | #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS) | |
1da177e4 LT |
2363 | |
2364 | /* HBA serial number */ | |
2365 | uint8_t serial0; | |
2366 | uint8_t serial1; | |
2367 | uint8_t serial2; | |
2368 | ||
2369 | /* NVRAM configuration data */ | |
7b867cf7 AC |
2370 | #define MAX_NVRAM_SIZE 4096 |
2371 | #define VPD_OFFSET MAX_NVRAM_SIZE / 2 | |
3d71644c | 2372 | uint16_t nvram_size; |
1da177e4 | 2373 | uint16_t nvram_base; |
281afe19 | 2374 | void *nvram; |
6f641790 AV |
2375 | uint16_t vpd_size; |
2376 | uint16_t vpd_base; | |
281afe19 | 2377 | void *vpd; |
1da177e4 LT |
2378 | |
2379 | uint16_t loop_reset_delay; | |
1da177e4 LT |
2380 | uint8_t retry_count; |
2381 | uint8_t login_timeout; | |
2382 | uint16_t r_a_tov; | |
2383 | int port_down_retry_count; | |
1da177e4 | 2384 | uint8_t mbx_count; |
1da177e4 | 2385 | |
7b867cf7 | 2386 | uint32_t login_retry_count; |
1da177e4 LT |
2387 | /* SNS command interfaces. */ |
2388 | ms_iocb_entry_t *ms_iocb; | |
2389 | dma_addr_t ms_iocb_dma; | |
2390 | struct ct_sns_pkt *ct_sns; | |
2391 | dma_addr_t ct_sns_dma; | |
2392 | /* SNS command interfaces for 2200. */ | |
2393 | struct sns_cmd_pkt *sns_cmd; | |
2394 | dma_addr_t sns_cmd_dma; | |
2395 | ||
7b867cf7 AC |
2396 | #define SFP_DEV_SIZE 256 |
2397 | #define SFP_BLOCK_SIZE 64 | |
2398 | void *sfp_data; | |
2399 | dma_addr_t sfp_data_dma; | |
88729e53 | 2400 | |
ad0ecd61 JC |
2401 | uint8_t *edc_data; |
2402 | dma_addr_t edc_data_dma; | |
2403 | uint16_t edc_data_len; | |
2404 | ||
ce0423f4 AV |
2405 | #define XGMAC_DATA_SIZE PAGE_SIZE |
2406 | void *xgmac_data; | |
2407 | dma_addr_t xgmac_data_dma; | |
2408 | ||
11bbc1d8 AV |
2409 | #define DCBX_TLV_DATA_SIZE PAGE_SIZE |
2410 | void *dcbx_tlv; | |
2411 | dma_addr_t dcbx_tlv_dma; | |
2412 | ||
39a11240 | 2413 | struct task_struct *dpc_thread; |
1da177e4 LT |
2414 | uint8_t dpc_active; /* DPC routine is active */ |
2415 | ||
1da177e4 LT |
2416 | dma_addr_t gid_list_dma; |
2417 | struct gid_list_info *gid_list; | |
abbd8870 | 2418 | int gid_list_info_size; |
1da177e4 | 2419 | |
fa2a1ce5 | 2420 | /* Small DMA pool allocations -- maximum 256 bytes in length. */ |
7b867cf7 | 2421 | #define DMA_POOL_SIZE 256 |
1da177e4 LT |
2422 | struct dma_pool *s_dma_pool; |
2423 | ||
2424 | dma_addr_t init_cb_dma; | |
3d71644c AV |
2425 | init_cb_t *init_cb; |
2426 | int init_cb_size; | |
b64b0e8f AV |
2427 | dma_addr_t ex_init_cb_dma; |
2428 | struct ex_init_cb_81xx *ex_init_cb; | |
1da177e4 | 2429 | |
1da177e4 LT |
2430 | /* These are used by mailbox operations. */ |
2431 | volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT]; | |
2432 | ||
2433 | mbx_cmd_t *mcp; | |
2434 | unsigned long mbx_cmd_flags; | |
7b867cf7 AC |
2435 | #define MBX_INTERRUPT 1 |
2436 | #define MBX_INTR_WAIT 2 | |
1da177e4 LT |
2437 | #define MBX_UPDATE_FLASH_ACTIVE 3 |
2438 | ||
7b867cf7 AC |
2439 | struct mutex vport_lock; /* Virtual port synchronization */ |
2440 | struct completion mbx_cmd_comp; /* Serialize mbx access */ | |
0b05a1f0 | 2441 | struct completion mbx_intr_comp; /* Used for completion notification */ |
1da177e4 | 2442 | |
1da177e4 | 2443 | /* Basic firmware related information. */ |
1da177e4 LT |
2444 | uint16_t fw_major_version; |
2445 | uint16_t fw_minor_version; | |
2446 | uint16_t fw_subminor_version; | |
2447 | uint16_t fw_attributes; | |
2448 | uint32_t fw_memory_size; | |
2449 | uint32_t fw_transfer_size; | |
441d1072 AV |
2450 | uint32_t fw_srisc_address; |
2451 | #define RISC_START_ADDRESS_2100 0x1000 | |
2452 | #define RISC_START_ADDRESS_2300 0x800 | |
2453 | #define RISC_START_ADDRESS_2400 0x100000 | |
24a08138 | 2454 | uint16_t fw_xcb_count; |
1da177e4 | 2455 | |
7b867cf7 | 2456 | uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */ |
1da177e4 | 2457 | uint8_t fw_seriallink_options[4]; |
3d71644c | 2458 | uint16_t fw_seriallink_options24[4]; |
1da177e4 | 2459 | |
55a96158 | 2460 | uint8_t mpi_version[3]; |
3a03eb79 | 2461 | uint32_t mpi_capabilities; |
55a96158 | 2462 | uint8_t phy_version[3]; |
3a03eb79 | 2463 | |
1da177e4 | 2464 | /* Firmware dump information. */ |
a7a167bf AV |
2465 | struct qla2xxx_fw_dump *fw_dump; |
2466 | uint32_t fw_dump_len; | |
d4e3e04d | 2467 | int fw_dumped; |
1da177e4 | 2468 | int fw_dump_reading; |
a7a167bf AV |
2469 | dma_addr_t eft_dma; |
2470 | void *eft; | |
1da177e4 | 2471 | |
bb99de67 | 2472 | uint32_t chain_offset; |
df613b96 AV |
2473 | struct dentry *dfs_dir; |
2474 | struct dentry *dfs_fce; | |
2475 | dma_addr_t fce_dma; | |
2476 | void *fce; | |
2477 | uint32_t fce_bufs; | |
2478 | uint16_t fce_mb[8]; | |
2479 | uint64_t fce_wr, fce_rd; | |
2480 | struct mutex fce_mutex; | |
2481 | ||
3d71644c | 2482 | uint32_t pci_attr; |
a8488abe | 2483 | uint16_t chip_revision; |
1da177e4 LT |
2484 | |
2485 | uint16_t product_id[4]; | |
2486 | ||
2487 | uint8_t model_number[16+1]; | |
2488 | #define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0" | |
1ee27146 | 2489 | char model_desc[80]; |
cca5335c | 2490 | uint8_t adapter_id[16+1]; |
1da177e4 | 2491 | |
854165f4 AV |
2492 | /* Option ROM information. */ |
2493 | char *optrom_buffer; | |
2494 | uint32_t optrom_size; | |
2495 | int optrom_state; | |
2496 | #define QLA_SWAITING 0 | |
2497 | #define QLA_SREADING 1 | |
2498 | #define QLA_SWRITING 2 | |
b7cc176c JC |
2499 | uint32_t optrom_region_start; |
2500 | uint32_t optrom_region_size; | |
854165f4 | 2501 | |
7b867cf7 | 2502 | /* PCI expansion ROM image information. */ |
30c47662 AV |
2503 | #define ROM_CODE_TYPE_BIOS 0 |
2504 | #define ROM_CODE_TYPE_FCODE 1 | |
2505 | #define ROM_CODE_TYPE_EFI 3 | |
7b867cf7 AC |
2506 | uint8_t bios_revision[2]; |
2507 | uint8_t efi_revision[2]; | |
2508 | uint8_t fcode_revision[16]; | |
30c47662 AV |
2509 | uint32_t fw_revision[4]; |
2510 | ||
3a03eb79 AV |
2511 | /* Offsets for flash/nvram access (set to ~0 if not used). */ |
2512 | uint32_t flash_conf_off; | |
2513 | uint32_t flash_data_off; | |
2514 | uint32_t nvram_conf_off; | |
2515 | uint32_t nvram_data_off; | |
2516 | ||
7d232c74 AV |
2517 | uint32_t fdt_wrt_disable; |
2518 | uint32_t fdt_erase_cmd; | |
2519 | uint32_t fdt_block_size; | |
2520 | uint32_t fdt_unprotect_sec_cmd; | |
2521 | uint32_t fdt_protect_sec_cmd; | |
2522 | ||
7b867cf7 AC |
2523 | uint32_t flt_region_flt; |
2524 | uint32_t flt_region_fdt; | |
2525 | uint32_t flt_region_boot; | |
2526 | uint32_t flt_region_fw; | |
2527 | uint32_t flt_region_vpd_nvram; | |
3d79038f AV |
2528 | uint32_t flt_region_vpd; |
2529 | uint32_t flt_region_nvram; | |
7b867cf7 | 2530 | uint32_t flt_region_npiv_conf; |
cbc8eb67 | 2531 | uint32_t flt_region_gold_fw; |
c00d8994 | 2532 | |
1da177e4 | 2533 | /* Needed for BEACON */ |
7b867cf7 AC |
2534 | uint16_t beacon_blink_led; |
2535 | uint8_t beacon_color_state; | |
f6df144c AV |
2536 | #define QLA_LED_GRN_ON 0x01 |
2537 | #define QLA_LED_YLW_ON 0x02 | |
2538 | #define QLA_LED_ABR_ON 0x04 | |
2539 | #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */ | |
2540 | /* ISP2322: red, green, amber. */ | |
7b867cf7 AC |
2541 | uint16_t zio_mode; |
2542 | uint16_t zio_timer; | |
392e2f65 | 2543 | struct fc_host_statistics fc_host_stat; |
a8488abe | 2544 | |
73208dfd | 2545 | struct qla_msix_entry *msix_entries; |
2c3dfe3f | 2546 | |
7b867cf7 AC |
2547 | struct list_head vp_list; /* list of VP */ |
2548 | unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) / | |
2549 | sizeof(unsigned long)]; | |
2550 | uint16_t num_vhosts; /* number of vports created */ | |
2551 | uint16_t num_vsans; /* number of vsan created */ | |
2552 | uint16_t max_npiv_vports; /* 63 or 125 per topoloty */ | |
2553 | int cur_vport_count; | |
2554 | ||
2555 | struct qla_chip_state_84xx *cs84xx; | |
2556 | struct qla_statistics qla_stats; | |
2557 | struct isp_operations *isp_ops; | |
68ca949c | 2558 | struct workqueue_struct *wq; |
7b867cf7 AC |
2559 | }; |
2560 | ||
2561 | /* | |
2562 | * Qlogic scsi host structure | |
2563 | */ | |
2564 | typedef struct scsi_qla_host { | |
2565 | struct list_head list; | |
2566 | struct list_head vp_fcports; /* list of fcports */ | |
2567 | struct list_head work_list; | |
f999f4c1 AV |
2568 | spinlock_t work_lock; |
2569 | ||
7b867cf7 AC |
2570 | /* Commonly used flags and state information. */ |
2571 | struct Scsi_Host *host; | |
2572 | unsigned long host_no; | |
2573 | uint8_t host_str[16]; | |
2574 | ||
2575 | volatile struct { | |
2576 | uint32_t init_done :1; | |
2577 | uint32_t online :1; | |
2578 | uint32_t rscn_queue_overflow :1; | |
2579 | uint32_t reset_active :1; | |
2580 | ||
2581 | uint32_t management_server_logged_in :1; | |
2582 | uint32_t process_response_queue :1; | |
2583 | } flags; | |
2584 | ||
2585 | atomic_t loop_state; | |
2586 | #define LOOP_TIMEOUT 1 | |
2587 | #define LOOP_DOWN 2 | |
2588 | #define LOOP_UP 3 | |
2589 | #define LOOP_UPDATE 4 | |
2590 | #define LOOP_READY 5 | |
2591 | #define LOOP_DEAD 6 | |
2592 | ||
2593 | unsigned long dpc_flags; | |
2594 | #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */ | |
2595 | #define RESET_ACTIVE 1 | |
2596 | #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */ | |
2597 | #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */ | |
2598 | #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */ | |
2599 | #define LOOP_RESYNC_ACTIVE 5 | |
2600 | #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */ | |
2601 | #define RSCN_UPDATE 7 /* Perform an RSCN update. */ | |
ddb9b126 SS |
2602 | #define RELOGIN_NEEDED 8 |
2603 | #define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */ | |
2604 | #define ISP_ABORT_RETRY 10 /* ISP aborted. */ | |
2605 | #define BEACON_BLINK_NEEDED 11 | |
2606 | #define REGISTER_FDMI_NEEDED 12 | |
2607 | #define FCPORT_UPDATE_NEEDED 13 | |
2608 | #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */ | |
2609 | #define UNLOADING 15 | |
2610 | #define NPIV_CONFIG_NEEDED 16 | |
7b867cf7 AC |
2611 | |
2612 | uint32_t device_flags; | |
ddb9b126 SS |
2613 | #define SWITCH_FOUND BIT_0 |
2614 | #define DFLG_NO_CABLE BIT_1 | |
7b867cf7 | 2615 | |
7b867cf7 AC |
2616 | /* ISP configuration data. */ |
2617 | uint16_t loop_id; /* Host adapter loop id */ | |
2618 | ||
2619 | port_id_t d_id; /* Host adapter port id */ | |
2620 | uint8_t marker_needed; | |
2621 | uint16_t mgmt_svr_loop_id; | |
2622 | ||
2623 | ||
2624 | ||
2625 | /* RSCN queue. */ | |
2626 | uint32_t rscn_queue[MAX_RSCN_COUNT]; | |
2627 | uint8_t rscn_in_ptr; | |
2628 | uint8_t rscn_out_ptr; | |
2629 | ||
2630 | /* Timeout timers. */ | |
2631 | uint8_t loop_down_abort_time; /* port down timer */ | |
2632 | atomic_t loop_down_timer; /* loop down timer */ | |
2633 | uint8_t link_down_timeout; /* link down timeout */ | |
2634 | ||
2635 | uint32_t timer_active; | |
2636 | struct timer_list timer; | |
2637 | ||
2638 | uint8_t node_name[WWN_SIZE]; | |
2639 | uint8_t port_name[WWN_SIZE]; | |
2640 | uint8_t fabric_node_name[WWN_SIZE]; | |
bad7001c AV |
2641 | |
2642 | uint16_t fcoe_vlan_id; | |
2643 | uint16_t fcoe_fcf_idx; | |
2644 | uint8_t fcoe_vn_port_mac[6]; | |
2645 | ||
7b867cf7 AC |
2646 | uint32_t vp_abort_cnt; |
2647 | ||
2c3dfe3f | 2648 | struct fc_vport *fc_vport; /* holds fc_vport * for each vport */ |
2c3dfe3f SJ |
2649 | uint16_t vp_idx; /* vport ID */ |
2650 | ||
2c3dfe3f | 2651 | unsigned long vp_flags; |
2c3dfe3f SJ |
2652 | #define VP_IDX_ACQUIRED 0 /* bit no 0 */ |
2653 | #define VP_CREATE_NEEDED 1 | |
2654 | #define VP_BIND_NEEDED 2 | |
2655 | #define VP_DELETE_NEEDED 3 | |
2656 | #define VP_SCR_NEEDED 4 /* State Change Request registration */ | |
2657 | atomic_t vp_state; | |
2658 | #define VP_OFFLINE 0 | |
2659 | #define VP_ACTIVE 1 | |
2660 | #define VP_FAILED 2 | |
2661 | // #define VP_DISABLE 3 | |
2662 | uint16_t vp_err_state; | |
2663 | uint16_t vp_prev_err_state; | |
2664 | #define VP_ERR_UNKWN 0 | |
2665 | #define VP_ERR_PORTDWN 1 | |
2666 | #define VP_ERR_FAB_UNSUPPORTED 2 | |
2667 | #define VP_ERR_FAB_NORESOURCES 3 | |
2668 | #define VP_ERR_FAB_LOGOUT 4 | |
2669 | #define VP_ERR_ADAP_NORESOURCES 5 | |
7b867cf7 | 2670 | struct qla_hw_data *hw; |
2afa19a9 | 2671 | struct req_que *req; |
1da177e4 LT |
2672 | } scsi_qla_host_t; |
2673 | ||
1da177e4 LT |
2674 | /* |
2675 | * Macros to help code, maintain, etc. | |
2676 | */ | |
2677 | #define LOOP_TRANSITION(ha) \ | |
2678 | (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \ | |
23443b1d | 2679 | test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \ |
1da177e4 | 2680 | atomic_read(&ha->loop_state) == LOOP_DOWN) |
fa2a1ce5 | 2681 | |
1da177e4 LT |
2682 | #define qla_printk(level, ha, format, arg...) \ |
2683 | dev_printk(level , &((ha)->pdev->dev) , format , ## arg) | |
2684 | ||
2685 | /* | |
2686 | * qla2x00 local function return status codes | |
2687 | */ | |
2688 | #define MBS_MASK 0x3fff | |
2689 | ||
2690 | #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK) | |
2691 | #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK) | |
2692 | #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK) | |
2693 | #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK) | |
2694 | #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK) | |
2695 | #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK) | |
2696 | #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK) | |
2697 | #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK) | |
2698 | #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK) | |
2699 | #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK) | |
2700 | ||
2701 | #define QLA_FUNCTION_TIMEOUT 0x100 | |
2702 | #define QLA_FUNCTION_PARAMETER_ERROR 0x101 | |
2703 | #define QLA_FUNCTION_FAILED 0x102 | |
2704 | #define QLA_MEMORY_ALLOC_FAILED 0x103 | |
2705 | #define QLA_LOCK_TIMEOUT 0x104 | |
2706 | #define QLA_ABORTED 0x105 | |
2707 | #define QLA_SUSPENDED 0x106 | |
2708 | #define QLA_BUSY 0x107 | |
2709 | #define QLA_RSCNS_HANDLED 0x108 | |
cca5335c | 2710 | #define QLA_ALREADY_REGISTERED 0x109 |
1da177e4 | 2711 | |
1da177e4 LT |
2712 | #define NVRAM_DELAY() udelay(10) |
2713 | ||
2714 | #define INVALID_HANDLE (MAX_OUTSTANDING_COMMANDS+1) | |
2715 | ||
2716 | /* | |
2717 | * Flash support definitions | |
2718 | */ | |
854165f4 AV |
2719 | #define OPTROM_SIZE_2300 0x20000 |
2720 | #define OPTROM_SIZE_2322 0x100000 | |
2721 | #define OPTROM_SIZE_24XX 0x100000 | |
c3a2f0df | 2722 | #define OPTROM_SIZE_25XX 0x200000 |
3a03eb79 | 2723 | #define OPTROM_SIZE_81XX 0x400000 |
1da177e4 LT |
2724 | |
2725 | #include "qla_gbl.h" | |
2726 | #include "qla_dbg.h" | |
2727 | #include "qla_inline.h" | |
1da177e4 | 2728 | |
1da177e4 | 2729 | #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr) |
1da177e4 LT |
2730 | |
2731 | #endif |