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Commit | Line | Data |
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fa90c54f AV |
1 | /* |
2 | * QLogic Fibre Channel HBA Driver | |
1e63395c | 3 | * Copyright (c) 2003-2013 QLogic Corporation |
fa90c54f AV |
4 | * |
5 | * See LICENSE.qla2xxx for copyright and licensing details. | |
6 | */ | |
1da177e4 LT |
7 | #ifndef __QLA_DEF_H |
8 | #define __QLA_DEF_H | |
9 | ||
10 | #include <linux/kernel.h> | |
11 | #include <linux/init.h> | |
12 | #include <linux/types.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/list.h> | |
15 | #include <linux/pci.h> | |
16 | #include <linux/dma-mapping.h> | |
17 | #include <linux/sched.h> | |
18 | #include <linux/slab.h> | |
19 | #include <linux/dmapool.h> | |
20 | #include <linux/mempool.h> | |
21 | #include <linux/spinlock.h> | |
22 | #include <linux/completion.h> | |
abbd8870 | 23 | #include <linux/interrupt.h> |
19a7b4ae | 24 | #include <linux/workqueue.h> |
5433383e | 25 | #include <linux/firmware.h> |
14e660e6 | 26 | #include <linux/aer.h> |
4d4df193 | 27 | #include <linux/mutex.h> |
1da177e4 LT |
28 | |
29 | #include <scsi/scsi.h> | |
30 | #include <scsi/scsi_host.h> | |
31 | #include <scsi/scsi_device.h> | |
32 | #include <scsi/scsi_cmnd.h> | |
392e2f65 | 33 | #include <scsi/scsi_transport_fc.h> |
9a069e19 | 34 | #include <scsi/scsi_bsg_fc.h> |
1da177e4 | 35 | |
6e98016c | 36 | #include "qla_bsg.h" |
a9083016 | 37 | #include "qla_nx.h" |
6a03b4cd HZ |
38 | #define QLA2XXX_DRIVER_NAME "qla2xxx" |
39 | #define QLA2XXX_APIDEV "ql2xapidev" | |
f24b697b | 40 | #define QLA2XXX_MANUFACTURER "QLogic Corporation" |
cb63067a | 41 | |
1da177e4 LT |
42 | /* |
43 | * We have MAILBOX_REGISTER_COUNT sized arrays in a few places, | |
44 | * but that's fine as we don't look at the last 24 ones for | |
45 | * ISP2100 HBAs. | |
46 | */ | |
47 | #define MAILBOX_REGISTER_COUNT_2100 8 | |
67ddda35 | 48 | #define MAILBOX_REGISTER_COUNT_2200 24 |
1da177e4 LT |
49 | #define MAILBOX_REGISTER_COUNT 32 |
50 | ||
51 | #define QLA2200A_RISC_ROM_VER 4 | |
52 | #define FPM_2300 6 | |
53 | #define FPM_2310 7 | |
54 | ||
55 | #include "qla_settings.h" | |
56 | ||
fa2a1ce5 | 57 | /* |
1da177e4 LT |
58 | * Data bit definitions |
59 | */ | |
60 | #define BIT_0 0x1 | |
61 | #define BIT_1 0x2 | |
62 | #define BIT_2 0x4 | |
63 | #define BIT_3 0x8 | |
64 | #define BIT_4 0x10 | |
65 | #define BIT_5 0x20 | |
66 | #define BIT_6 0x40 | |
67 | #define BIT_7 0x80 | |
68 | #define BIT_8 0x100 | |
69 | #define BIT_9 0x200 | |
70 | #define BIT_10 0x400 | |
71 | #define BIT_11 0x800 | |
72 | #define BIT_12 0x1000 | |
73 | #define BIT_13 0x2000 | |
74 | #define BIT_14 0x4000 | |
75 | #define BIT_15 0x8000 | |
76 | #define BIT_16 0x10000 | |
77 | #define BIT_17 0x20000 | |
78 | #define BIT_18 0x40000 | |
79 | #define BIT_19 0x80000 | |
80 | #define BIT_20 0x100000 | |
81 | #define BIT_21 0x200000 | |
82 | #define BIT_22 0x400000 | |
83 | #define BIT_23 0x800000 | |
84 | #define BIT_24 0x1000000 | |
85 | #define BIT_25 0x2000000 | |
86 | #define BIT_26 0x4000000 | |
87 | #define BIT_27 0x8000000 | |
88 | #define BIT_28 0x10000000 | |
89 | #define BIT_29 0x20000000 | |
90 | #define BIT_30 0x40000000 | |
91 | #define BIT_31 0x80000000 | |
92 | ||
93 | #define LSB(x) ((uint8_t)(x)) | |
94 | #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8)) | |
95 | ||
96 | #define LSW(x) ((uint16_t)(x)) | |
97 | #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16)) | |
98 | ||
99 | #define LSD(x) ((uint32_t)((uint64_t)(x))) | |
100 | #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16)) | |
101 | ||
2afa19a9 | 102 | #define MAKE_HANDLE(x, y) ((uint32_t)((((uint32_t)(x)) << 16) | (uint32_t)(y))) |
1da177e4 LT |
103 | |
104 | /* | |
105 | * I/O register | |
106 | */ | |
107 | ||
108 | #define RD_REG_BYTE(addr) readb(addr) | |
109 | #define RD_REG_WORD(addr) readw(addr) | |
110 | #define RD_REG_DWORD(addr) readl(addr) | |
111 | #define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr) | |
112 | #define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr) | |
113 | #define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr) | |
114 | #define WRT_REG_BYTE(addr, data) writeb(data,addr) | |
115 | #define WRT_REG_WORD(addr, data) writew(data,addr) | |
116 | #define WRT_REG_DWORD(addr, data) writel(data,addr) | |
117 | ||
7d613ac6 SV |
118 | /* |
119 | * ISP83XX specific remote register addresses | |
120 | */ | |
121 | #define QLA83XX_LED_PORT0 0x00201320 | |
122 | #define QLA83XX_LED_PORT1 0x00201328 | |
123 | #define QLA83XX_IDC_DEV_STATE 0x22102384 | |
124 | #define QLA83XX_IDC_MAJOR_VERSION 0x22102380 | |
125 | #define QLA83XX_IDC_MINOR_VERSION 0x22102398 | |
126 | #define QLA83XX_IDC_DRV_PRESENCE 0x22102388 | |
127 | #define QLA83XX_IDC_DRIVER_ACK 0x2210238c | |
128 | #define QLA83XX_IDC_CONTROL 0x22102390 | |
129 | #define QLA83XX_IDC_AUDIT 0x22102394 | |
130 | #define QLA83XX_IDC_LOCK_RECOVERY 0x2210239c | |
131 | #define QLA83XX_DRIVER_LOCKID 0x22102104 | |
132 | #define QLA83XX_DRIVER_LOCK 0x8111c028 | |
133 | #define QLA83XX_DRIVER_UNLOCK 0x8111c02c | |
134 | #define QLA83XX_FLASH_LOCKID 0x22102100 | |
135 | #define QLA83XX_FLASH_LOCK 0x8111c010 | |
136 | #define QLA83XX_FLASH_UNLOCK 0x8111c014 | |
137 | #define QLA83XX_DEV_PARTINFO1 0x221023e0 | |
138 | #define QLA83XX_DEV_PARTINFO2 0x221023e4 | |
139 | #define QLA83XX_FW_HEARTBEAT 0x221020b0 | |
140 | #define QLA83XX_PEG_HALT_STATUS1 0x221020a8 | |
141 | #define QLA83XX_PEG_HALT_STATUS2 0x221020ac | |
142 | ||
143 | /* 83XX: Macros defining 8200 AEN Reason codes */ | |
144 | #define IDC_DEVICE_STATE_CHANGE BIT_0 | |
145 | #define IDC_PEG_HALT_STATUS_CHANGE BIT_1 | |
146 | #define IDC_NIC_FW_REPORTED_FAILURE BIT_2 | |
147 | #define IDC_HEARTBEAT_FAILURE BIT_3 | |
148 | ||
149 | /* 83XX: Macros defining 8200 AEN Error-levels */ | |
150 | #define ERR_LEVEL_NON_FATAL 0x1 | |
151 | #define ERR_LEVEL_RECOVERABLE_FATAL 0x2 | |
152 | #define ERR_LEVEL_UNRECOVERABLE_FATAL 0x4 | |
153 | ||
154 | /* 83XX: Macros for IDC Version */ | |
155 | #define QLA83XX_SUPP_IDC_MAJOR_VERSION 0x01 | |
156 | #define QLA83XX_SUPP_IDC_MINOR_VERSION 0x0 | |
157 | ||
158 | /* 83XX: Macros for scheduling dpc tasks */ | |
159 | #define QLA83XX_NIC_CORE_RESET 0x1 | |
160 | #define QLA83XX_IDC_STATE_HANDLER 0x2 | |
161 | #define QLA83XX_NIC_CORE_UNRECOVERABLE 0x3 | |
162 | ||
163 | /* 83XX: Macros for defining IDC-Control bits */ | |
164 | #define QLA83XX_IDC_RESET_DISABLED BIT_0 | |
165 | #define QLA83XX_IDC_GRACEFUL_RESET BIT_1 | |
166 | ||
167 | /* 83XX: Macros for different timeouts */ | |
168 | #define QLA83XX_IDC_INITIALIZATION_TIMEOUT 30 | |
169 | #define QLA83XX_IDC_RESET_ACK_TIMEOUT 10 | |
170 | #define QLA83XX_MAX_LOCK_RECOVERY_WAIT (2 * HZ) | |
171 | ||
172 | /* 83XX: Macros for defining class in DEV-Partition Info register */ | |
173 | #define QLA83XX_CLASS_TYPE_NONE 0x0 | |
174 | #define QLA83XX_CLASS_TYPE_NIC 0x1 | |
175 | #define QLA83XX_CLASS_TYPE_FCOE 0x2 | |
176 | #define QLA83XX_CLASS_TYPE_ISCSI 0x3 | |
177 | ||
178 | /* 83XX: Macros for IDC Lock-Recovery stages */ | |
179 | #define IDC_LOCK_RECOVERY_STAGE1 0x1 /* Stage1: Intent for | |
180 | * lock-recovery | |
181 | */ | |
182 | #define IDC_LOCK_RECOVERY_STAGE2 0x2 /* Stage2: Perform lock-recovery */ | |
183 | ||
184 | /* 83XX: Macros for IDC Audit type */ | |
185 | #define IDC_AUDIT_TIMESTAMP 0x0 /* IDC-AUDIT: Record timestamp of | |
186 | * dev-state change to NEED-RESET | |
187 | * or NEED-QUIESCENT | |
188 | */ | |
189 | #define IDC_AUDIT_COMPLETION 0x1 /* IDC-AUDIT: Record duration of | |
190 | * reset-recovery completion is | |
191 | * second | |
192 | */ | |
193 | ||
f6df144c AV |
194 | /* |
195 | * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an | |
196 | * 133Mhz slot. | |
197 | */ | |
198 | #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr)) | |
199 | #define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr)) | |
200 | ||
1da177e4 LT |
201 | /* |
202 | * Fibre Channel device definitions. | |
203 | */ | |
204 | #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */ | |
642ef983 CD |
205 | #define MAX_FIBRE_DEVICES_2100 512 |
206 | #define MAX_FIBRE_DEVICES_2400 2048 | |
207 | #define MAX_FIBRE_DEVICES_LOOP 128 | |
208 | #define MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400 | |
5f16b331 | 209 | #define LOOPID_MAP_SIZE (ha->max_fibre_devices) |
cc4731f5 | 210 | #define MAX_FIBRE_LUNS 0xFFFF |
1da177e4 LT |
211 | #define MAX_HOST_COUNT 16 |
212 | ||
213 | /* | |
214 | * Host adapter default definitions. | |
215 | */ | |
216 | #define MAX_BUSES 1 /* We only have one bus today */ | |
1da177e4 LT |
217 | #define MIN_LUNS 8 |
218 | #define MAX_LUNS MAX_FIBRE_LUNS | |
fa2a1ce5 AV |
219 | #define MAX_CMDS_PER_LUN 255 |
220 | ||
1da177e4 LT |
221 | /* |
222 | * Fibre Channel device definitions. | |
223 | */ | |
224 | #define SNS_LAST_LOOP_ID_2100 0xfe | |
225 | #define SNS_LAST_LOOP_ID_2300 0x7ff | |
226 | ||
227 | #define LAST_LOCAL_LOOP_ID 0x7d | |
228 | #define SNS_FL_PORT 0x7e | |
229 | #define FABRIC_CONTROLLER 0x7f | |
230 | #define SIMPLE_NAME_SERVER 0x80 | |
231 | #define SNS_FIRST_LOOP_ID 0x81 | |
232 | #define MANAGEMENT_SERVER 0xfe | |
233 | #define BROADCAST 0xff | |
234 | ||
3d71644c AV |
235 | /* |
236 | * There is no correspondence between an N-PORT id and an AL_PA. Therefore the | |
237 | * valid range of an N-PORT id is 0 through 0x7ef. | |
238 | */ | |
239 | #define NPH_LAST_HANDLE 0x7ef | |
cca5335c | 240 | #define NPH_MGMT_SERVER 0x7fa /* FFFFFA */ |
3d71644c AV |
241 | #define NPH_SNS 0x7fc /* FFFFFC */ |
242 | #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */ | |
243 | #define NPH_F_PORT 0x7fe /* FFFFFE */ | |
244 | #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */ | |
245 | ||
246 | #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */ | |
247 | #include "qla_fw.h" | |
1da177e4 LT |
248 | |
249 | /* | |
250 | * Timeout timer counts in seconds | |
251 | */ | |
8482e118 | 252 | #define PORT_RETRY_TIME 1 |
1da177e4 LT |
253 | #define LOOP_DOWN_TIMEOUT 60 |
254 | #define LOOP_DOWN_TIME 255 /* 240 */ | |
255 | #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30) | |
256 | ||
8d93f550 CD |
257 | #define DEFAULT_OUTSTANDING_COMMANDS 1024 |
258 | #define MIN_OUTSTANDING_COMMANDS 128 | |
1da177e4 LT |
259 | |
260 | /* ISP request and response entry counts (37-65535) */ | |
261 | #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */ | |
262 | #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */ | |
d743de66 | 263 | #define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */ |
1da177e4 LT |
264 | #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/ |
265 | #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/ | |
2afa19a9 | 266 | #define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/ |
2d70c103 | 267 | #define ATIO_ENTRY_CNT_24XX 4096 /* Number of ATIO entries. */ |
1da177e4 | 268 | |
17d98630 AC |
269 | struct req_que; |
270 | ||
bad75002 AE |
271 | /* |
272 | * (sd.h is not exported, hence local inclusion) | |
273 | * Data Integrity Field tuple. | |
274 | */ | |
275 | struct sd_dif_tuple { | |
276 | __be16 guard_tag; /* Checksum */ | |
277 | __be16 app_tag; /* Opaque storage */ | |
278 | __be32 ref_tag; /* Target LBA or indirect LBA */ | |
279 | }; | |
280 | ||
1da177e4 | 281 | /* |
fa2a1ce5 | 282 | * SCSI Request Block |
1da177e4 | 283 | */ |
9ba56b95 | 284 | struct srb_cmd { |
1da177e4 | 285 | struct scsi_cmnd *cmd; /* Linux SCSI command pkt */ |
1da177e4 LT |
286 | uint32_t request_sense_length; |
287 | uint8_t *request_sense_ptr; | |
cf53b069 | 288 | void *ctx; |
9ba56b95 | 289 | }; |
1da177e4 LT |
290 | |
291 | /* | |
292 | * SRB flag definitions | |
293 | */ | |
bad75002 AE |
294 | #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */ |
295 | #define SRB_FCP_CMND_DMA_VALID BIT_12 /* DIF: DSD List valid */ | |
296 | #define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */ | |
297 | #define SRB_CRC_PROT_DMA_VALID BIT_4 /* DIF: prot DMA valid */ | |
298 | #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */ | |
299 | ||
300 | /* To identify if a srb is of T10-CRC type. @sp => srb_t pointer */ | |
301 | #define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID) | |
1da177e4 | 302 | |
ac280b67 AV |
303 | /* |
304 | * SRB extensions. | |
305 | */ | |
4916392b MI |
306 | struct srb_iocb { |
307 | union { | |
308 | struct { | |
309 | uint16_t flags; | |
310 | #define SRB_LOGIN_RETRIED BIT_0 | |
311 | #define SRB_LOGIN_COND_PLOGI BIT_1 | |
312 | #define SRB_LOGIN_SKIP_PRLI BIT_2 | |
313 | uint16_t data[2]; | |
314 | } logio; | |
3822263e MI |
315 | struct { |
316 | /* | |
317 | * Values for flags field below are as | |
318 | * defined in tsk_mgmt_entry struct | |
319 | * for control_flags field in qla_fw.h. | |
320 | */ | |
321 | uint32_t flags; | |
322 | uint32_t lun; | |
323 | uint32_t data; | |
324 | } tmf; | |
4916392b | 325 | } u; |
99b0bec7 | 326 | |
ac280b67 | 327 | struct timer_list timer; |
9ba56b95 | 328 | void (*timeout)(void *); |
ac280b67 AV |
329 | }; |
330 | ||
4916392b MI |
331 | /* Values for srb_ctx type */ |
332 | #define SRB_LOGIN_CMD 1 | |
333 | #define SRB_LOGOUT_CMD 2 | |
334 | #define SRB_ELS_CMD_RPT 3 | |
335 | #define SRB_ELS_CMD_HST 4 | |
336 | #define SRB_CT_CMD 5 | |
337 | #define SRB_ADISC_CMD 6 | |
3822263e | 338 | #define SRB_TM_CMD 7 |
9ba56b95 | 339 | #define SRB_SCSI_CMD 8 |
a9b6f722 | 340 | #define SRB_BIDI_CMD 9 |
ac280b67 | 341 | |
9ba56b95 GM |
342 | typedef struct srb { |
343 | atomic_t ref_count; | |
344 | struct fc_port *fcport; | |
345 | uint32_t handle; | |
346 | uint16_t flags; | |
9a069e19 | 347 | uint16_t type; |
4916392b | 348 | char *name; |
5780790e | 349 | int iocbs; |
4916392b | 350 | union { |
9ba56b95 | 351 | struct srb_iocb iocb_cmd; |
4916392b | 352 | struct fc_bsg_job *bsg_job; |
9ba56b95 | 353 | struct srb_cmd scmd; |
4916392b | 354 | } u; |
9ba56b95 GM |
355 | void (*done)(void *, void *, int); |
356 | void (*free)(void *, void *); | |
357 | } srb_t; | |
358 | ||
359 | #define GET_CMD_SP(sp) (sp->u.scmd.cmd) | |
360 | #define SET_CMD_SP(sp, cmd) (sp->u.scmd.cmd = cmd) | |
361 | #define GET_CMD_CTX_SP(sp) (sp->u.scmd.ctx) | |
362 | ||
363 | #define GET_CMD_SENSE_LEN(sp) \ | |
364 | (sp->u.scmd.request_sense_length) | |
365 | #define SET_CMD_SENSE_LEN(sp, len) \ | |
366 | (sp->u.scmd.request_sense_length = len) | |
367 | #define GET_CMD_SENSE_PTR(sp) \ | |
368 | (sp->u.scmd.request_sense_ptr) | |
369 | #define SET_CMD_SENSE_PTR(sp, ptr) \ | |
370 | (sp->u.scmd.request_sense_ptr = ptr) | |
9a069e19 GM |
371 | |
372 | struct msg_echo_lb { | |
373 | dma_addr_t send_dma; | |
374 | dma_addr_t rcv_dma; | |
375 | uint16_t req_sg_cnt; | |
376 | uint16_t rsp_sg_cnt; | |
377 | uint16_t options; | |
378 | uint32_t transfer_size; | |
379 | }; | |
380 | ||
1da177e4 LT |
381 | /* |
382 | * ISP I/O Register Set structure definitions. | |
383 | */ | |
3d71644c AV |
384 | struct device_reg_2xxx { |
385 | uint16_t flash_address; /* Flash BIOS address */ | |
386 | uint16_t flash_data; /* Flash BIOS data */ | |
1da177e4 | 387 | uint16_t unused_1[1]; /* Gap */ |
3d71644c | 388 | uint16_t ctrl_status; /* Control/Status */ |
fa2a1ce5 | 389 | #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */ |
1da177e4 LT |
390 | #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */ |
391 | #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */ | |
392 | ||
3d71644c | 393 | uint16_t ictrl; /* Interrupt control */ |
1da177e4 LT |
394 | #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */ |
395 | #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */ | |
396 | ||
3d71644c | 397 | uint16_t istatus; /* Interrupt status */ |
1da177e4 LT |
398 | #define ISR_RISC_INT BIT_3 /* RISC interrupt */ |
399 | ||
3d71644c AV |
400 | uint16_t semaphore; /* Semaphore */ |
401 | uint16_t nvram; /* NVRAM register. */ | |
1da177e4 LT |
402 | #define NVR_DESELECT 0 |
403 | #define NVR_BUSY BIT_15 | |
404 | #define NVR_WRT_ENABLE BIT_14 /* Write enable */ | |
405 | #define NVR_PR_ENABLE BIT_13 /* Protection register enable */ | |
406 | #define NVR_DATA_IN BIT_3 | |
407 | #define NVR_DATA_OUT BIT_2 | |
408 | #define NVR_SELECT BIT_1 | |
409 | #define NVR_CLOCK BIT_0 | |
410 | ||
45aeaf1e RA |
411 | #define NVR_WAIT_CNT 20000 |
412 | ||
1da177e4 LT |
413 | union { |
414 | struct { | |
3d71644c AV |
415 | uint16_t mailbox0; |
416 | uint16_t mailbox1; | |
417 | uint16_t mailbox2; | |
418 | uint16_t mailbox3; | |
419 | uint16_t mailbox4; | |
420 | uint16_t mailbox5; | |
421 | uint16_t mailbox6; | |
422 | uint16_t mailbox7; | |
423 | uint16_t unused_2[59]; /* Gap */ | |
1da177e4 LT |
424 | } __attribute__((packed)) isp2100; |
425 | struct { | |
3d71644c AV |
426 | /* Request Queue */ |
427 | uint16_t req_q_in; /* In-Pointer */ | |
428 | uint16_t req_q_out; /* Out-Pointer */ | |
429 | /* Response Queue */ | |
430 | uint16_t rsp_q_in; /* In-Pointer */ | |
431 | uint16_t rsp_q_out; /* Out-Pointer */ | |
1da177e4 LT |
432 | |
433 | /* RISC to Host Status */ | |
fa2a1ce5 | 434 | uint32_t host_status; |
1da177e4 LT |
435 | #define HSR_RISC_INT BIT_15 /* RISC interrupt */ |
436 | #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */ | |
437 | ||
438 | /* Host to Host Semaphore */ | |
fa2a1ce5 | 439 | uint16_t host_semaphore; |
3d71644c AV |
440 | uint16_t unused_3[17]; /* Gap */ |
441 | uint16_t mailbox0; | |
442 | uint16_t mailbox1; | |
443 | uint16_t mailbox2; | |
444 | uint16_t mailbox3; | |
445 | uint16_t mailbox4; | |
446 | uint16_t mailbox5; | |
447 | uint16_t mailbox6; | |
448 | uint16_t mailbox7; | |
449 | uint16_t mailbox8; | |
450 | uint16_t mailbox9; | |
451 | uint16_t mailbox10; | |
452 | uint16_t mailbox11; | |
453 | uint16_t mailbox12; | |
454 | uint16_t mailbox13; | |
455 | uint16_t mailbox14; | |
456 | uint16_t mailbox15; | |
457 | uint16_t mailbox16; | |
458 | uint16_t mailbox17; | |
459 | uint16_t mailbox18; | |
460 | uint16_t mailbox19; | |
461 | uint16_t mailbox20; | |
462 | uint16_t mailbox21; | |
463 | uint16_t mailbox22; | |
464 | uint16_t mailbox23; | |
465 | uint16_t mailbox24; | |
466 | uint16_t mailbox25; | |
467 | uint16_t mailbox26; | |
468 | uint16_t mailbox27; | |
469 | uint16_t mailbox28; | |
470 | uint16_t mailbox29; | |
471 | uint16_t mailbox30; | |
472 | uint16_t mailbox31; | |
473 | uint16_t fb_cmd; | |
474 | uint16_t unused_4[10]; /* Gap */ | |
1da177e4 LT |
475 | } __attribute__((packed)) isp2300; |
476 | } u; | |
477 | ||
3d71644c | 478 | uint16_t fpm_diag_config; |
c81d04c9 AV |
479 | uint16_t unused_5[0x4]; /* Gap */ |
480 | uint16_t risc_hw; | |
481 | uint16_t unused_5_1; /* Gap */ | |
3d71644c | 482 | uint16_t pcr; /* Processor Control Register. */ |
1da177e4 | 483 | uint16_t unused_6[0x5]; /* Gap */ |
3d71644c | 484 | uint16_t mctr; /* Memory Configuration and Timing. */ |
1da177e4 | 485 | uint16_t unused_7[0x3]; /* Gap */ |
3d71644c | 486 | uint16_t fb_cmd_2100; /* Unused on 23XX */ |
1da177e4 | 487 | uint16_t unused_8[0x3]; /* Gap */ |
3d71644c | 488 | uint16_t hccr; /* Host command & control register. */ |
1da177e4 LT |
489 | #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */ |
490 | #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */ | |
491 | /* HCCR commands */ | |
492 | #define HCCR_RESET_RISC 0x1000 /* Reset RISC */ | |
493 | #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */ | |
494 | #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */ | |
495 | #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */ | |
496 | #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */ | |
497 | #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */ | |
498 | #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */ | |
499 | #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */ | |
500 | ||
501 | uint16_t unused_9[5]; /* Gap */ | |
3d71644c AV |
502 | uint16_t gpiod; /* GPIO Data register. */ |
503 | uint16_t gpioe; /* GPIO Enable register. */ | |
1da177e4 LT |
504 | #define GPIO_LED_MASK 0x00C0 |
505 | #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000 | |
506 | #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040 | |
507 | #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080 | |
508 | #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0 | |
f6df144c AV |
509 | #define GPIO_LED_ALL_OFF 0x0000 |
510 | #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */ | |
511 | #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */ | |
1da177e4 LT |
512 | |
513 | union { | |
514 | struct { | |
3d71644c AV |
515 | uint16_t unused_10[8]; /* Gap */ |
516 | uint16_t mailbox8; | |
517 | uint16_t mailbox9; | |
518 | uint16_t mailbox10; | |
519 | uint16_t mailbox11; | |
520 | uint16_t mailbox12; | |
521 | uint16_t mailbox13; | |
522 | uint16_t mailbox14; | |
523 | uint16_t mailbox15; | |
524 | uint16_t mailbox16; | |
525 | uint16_t mailbox17; | |
526 | uint16_t mailbox18; | |
527 | uint16_t mailbox19; | |
528 | uint16_t mailbox20; | |
529 | uint16_t mailbox21; | |
530 | uint16_t mailbox22; | |
531 | uint16_t mailbox23; /* Also probe reg. */ | |
1da177e4 LT |
532 | } __attribute__((packed)) isp2200; |
533 | } u_end; | |
3d71644c AV |
534 | }; |
535 | ||
73208dfd | 536 | struct device_reg_25xxmq { |
08029990 AV |
537 | uint32_t req_q_in; |
538 | uint32_t req_q_out; | |
539 | uint32_t rsp_q_in; | |
540 | uint32_t rsp_q_out; | |
aa230bc5 AE |
541 | uint32_t atio_q_in; |
542 | uint32_t atio_q_out; | |
73208dfd AC |
543 | }; |
544 | ||
9a168bdd | 545 | typedef union { |
3d71644c AV |
546 | struct device_reg_2xxx isp; |
547 | struct device_reg_24xx isp24; | |
73208dfd | 548 | struct device_reg_25xxmq isp25mq; |
a9083016 | 549 | struct device_reg_82xx isp82; |
1da177e4 LT |
550 | } device_reg_t; |
551 | ||
552 | #define ISP_REQ_Q_IN(ha, reg) \ | |
553 | (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ | |
554 | &(reg)->u.isp2100.mailbox4 : \ | |
555 | &(reg)->u.isp2300.req_q_in) | |
556 | #define ISP_REQ_Q_OUT(ha, reg) \ | |
557 | (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ | |
558 | &(reg)->u.isp2100.mailbox4 : \ | |
559 | &(reg)->u.isp2300.req_q_out) | |
560 | #define ISP_RSP_Q_IN(ha, reg) \ | |
561 | (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ | |
562 | &(reg)->u.isp2100.mailbox5 : \ | |
563 | &(reg)->u.isp2300.rsp_q_in) | |
564 | #define ISP_RSP_Q_OUT(ha, reg) \ | |
565 | (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ | |
566 | &(reg)->u.isp2100.mailbox5 : \ | |
567 | &(reg)->u.isp2300.rsp_q_out) | |
568 | ||
aa230bc5 AE |
569 | #define ISP_ATIO_Q_IN(vha) (vha->hw->tgt.atio_q_in) |
570 | #define ISP_ATIO_Q_OUT(vha) (vha->hw->tgt.atio_q_out) | |
571 | ||
1da177e4 LT |
572 | #define MAILBOX_REG(ha, reg, num) \ |
573 | (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ | |
574 | (num < 8 ? \ | |
575 | &(reg)->u.isp2100.mailbox0 + (num) : \ | |
576 | &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \ | |
577 | &(reg)->u.isp2300.mailbox0 + (num)) | |
578 | #define RD_MAILBOX_REG(ha, reg, num) \ | |
579 | RD_REG_WORD(MAILBOX_REG(ha, reg, num)) | |
580 | #define WRT_MAILBOX_REG(ha, reg, num, data) \ | |
581 | WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data) | |
582 | ||
583 | #define FB_CMD_REG(ha, reg) \ | |
584 | (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ | |
585 | &(reg)->fb_cmd_2100 : \ | |
586 | &(reg)->u.isp2300.fb_cmd) | |
587 | #define RD_FB_CMD_REG(ha, reg) \ | |
588 | RD_REG_WORD(FB_CMD_REG(ha, reg)) | |
589 | #define WRT_FB_CMD_REG(ha, reg, data) \ | |
590 | WRT_REG_WORD(FB_CMD_REG(ha, reg), data) | |
591 | ||
592 | typedef struct { | |
593 | uint32_t out_mb; /* outbound from driver */ | |
594 | uint32_t in_mb; /* Incoming from RISC */ | |
595 | uint16_t mb[MAILBOX_REGISTER_COUNT]; | |
596 | long buf_size; | |
597 | void *bufp; | |
598 | uint32_t tov; | |
599 | uint8_t flags; | |
600 | #define MBX_DMA_IN BIT_0 | |
601 | #define MBX_DMA_OUT BIT_1 | |
602 | #define IOCTL_CMD BIT_2 | |
603 | } mbx_cmd_t; | |
604 | ||
605 | #define MBX_TOV_SECONDS 30 | |
606 | ||
607 | /* | |
608 | * ISP product identification definitions in mailboxes after reset. | |
609 | */ | |
610 | #define PROD_ID_1 0x4953 | |
611 | #define PROD_ID_2 0x0000 | |
612 | #define PROD_ID_2a 0x5020 | |
613 | #define PROD_ID_3 0x2020 | |
614 | ||
615 | /* | |
616 | * ISP mailbox Self-Test status codes | |
617 | */ | |
618 | #define MBS_FRM_ALIVE 0 /* Firmware Alive. */ | |
619 | #define MBS_CHKSUM_ERR 1 /* Checksum Error. */ | |
620 | #define MBS_BUSY 4 /* Busy. */ | |
621 | ||
622 | /* | |
623 | * ISP mailbox command complete status codes | |
624 | */ | |
625 | #define MBS_COMMAND_COMPLETE 0x4000 | |
626 | #define MBS_INVALID_COMMAND 0x4001 | |
627 | #define MBS_HOST_INTERFACE_ERROR 0x4002 | |
628 | #define MBS_TEST_FAILED 0x4003 | |
629 | #define MBS_COMMAND_ERROR 0x4005 | |
630 | #define MBS_COMMAND_PARAMETER_ERROR 0x4006 | |
631 | #define MBS_PORT_ID_USED 0x4007 | |
632 | #define MBS_LOOP_ID_USED 0x4008 | |
633 | #define MBS_ALL_IDS_IN_USE 0x4009 | |
634 | #define MBS_NOT_LOGGED_IN 0x400A | |
3d71644c AV |
635 | #define MBS_LINK_DOWN_ERROR 0x400B |
636 | #define MBS_DIAG_ECHO_TEST_ERROR 0x400C | |
1da177e4 LT |
637 | |
638 | /* | |
639 | * ISP mailbox asynchronous event status codes | |
640 | */ | |
641 | #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */ | |
642 | #define MBA_RESET 0x8001 /* Reset Detected. */ | |
643 | #define MBA_SYSTEM_ERR 0x8002 /* System Error. */ | |
644 | #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */ | |
645 | #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */ | |
646 | #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */ | |
647 | #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */ | |
648 | /* occurred. */ | |
649 | #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */ | |
650 | #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */ | |
651 | #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */ | |
652 | #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */ | |
653 | #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */ | |
654 | #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */ | |
655 | #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */ | |
656 | #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */ | |
657 | #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */ | |
658 | #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */ | |
659 | #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */ | |
660 | #define MBA_IP_RECEIVE 0x8023 /* IP Received. */ | |
661 | #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */ | |
662 | #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */ | |
663 | #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */ | |
664 | #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */ | |
665 | /* used. */ | |
45ebeb56 | 666 | #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */ |
1da177e4 LT |
667 | #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */ |
668 | #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */ | |
669 | #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */ | |
670 | #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */ | |
671 | #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */ | |
672 | #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */ | |
673 | #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */ | |
674 | #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */ | |
675 | #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */ | |
676 | #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */ | |
677 | #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */ | |
678 | #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */ | |
679 | #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */ | |
680 | ||
7d613ac6 SV |
681 | /* 83XX FCoE specific */ |
682 | #define MBA_IDC_AEN 0x8200 /* FCoE: NIC Core state change AEN */ | |
fafbda9f AE |
683 | |
684 | /* Interrupt type codes */ | |
685 | #define INTR_ROM_MB_SUCCESS 0x1 | |
686 | #define INTR_ROM_MB_FAILED 0x2 | |
687 | #define INTR_MB_SUCCESS 0x10 | |
688 | #define INTR_MB_FAILED 0x11 | |
689 | #define INTR_ASYNC_EVENT 0x12 | |
690 | #define INTR_RSP_QUE_UPDATE 0x13 | |
691 | #define INTR_RSP_QUE_UPDATE_83XX 0x14 | |
692 | #define INTR_ATIO_QUE_UPDATE 0x1C | |
693 | #define INTR_ATIO_RSP_QUE_UPDATE 0x1D | |
7d613ac6 | 694 | |
9a069e19 GM |
695 | /* ISP mailbox loopback echo diagnostic error code */ |
696 | #define MBS_LB_RESET 0x17 | |
1da177e4 LT |
697 | /* |
698 | * Firmware options 1, 2, 3. | |
699 | */ | |
700 | #define FO1_AE_ON_LIPF8 BIT_0 | |
701 | #define FO1_AE_ALL_LIP_RESET BIT_1 | |
702 | #define FO1_CTIO_RETRY BIT_3 | |
703 | #define FO1_DISABLE_LIP_F7_SW BIT_4 | |
704 | #define FO1_DISABLE_100MS_LOS_WAIT BIT_5 | |
3d71644c | 705 | #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */ |
1da177e4 LT |
706 | #define FO1_AE_ON_LOOP_INIT_ERR BIT_7 |
707 | #define FO1_SET_EMPHASIS_SWING BIT_8 | |
708 | #define FO1_AE_AUTO_BYPASS BIT_9 | |
709 | #define FO1_ENABLE_PURE_IOCB BIT_10 | |
710 | #define FO1_AE_PLOGI_RJT BIT_11 | |
711 | #define FO1_ENABLE_ABORT_SEQUENCE BIT_12 | |
712 | #define FO1_AE_QUEUE_FULL BIT_13 | |
713 | ||
714 | #define FO2_ENABLE_ATIO_TYPE_3 BIT_0 | |
715 | #define FO2_REV_LOOPBACK BIT_1 | |
716 | ||
717 | #define FO3_ENABLE_EMERG_IOCB BIT_0 | |
718 | #define FO3_AE_RND_ERROR BIT_1 | |
719 | ||
3d71644c AV |
720 | /* 24XX additional firmware options */ |
721 | #define ADD_FO_COUNT 3 | |
722 | #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */ | |
723 | #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10 | |
724 | ||
725 | #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5 | |
726 | ||
727 | #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14 | |
728 | ||
1da177e4 LT |
729 | /* |
730 | * ISP mailbox commands | |
731 | */ | |
732 | #define MBC_LOAD_RAM 1 /* Load RAM. */ | |
733 | #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */ | |
734 | #define MBC_WRITE_RAM_WORD 4 /* Write RAM word. */ | |
735 | #define MBC_READ_RAM_WORD 5 /* Read RAM word. */ | |
736 | #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */ | |
737 | #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */ | |
738 | #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */ | |
739 | #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */ | |
740 | #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */ | |
741 | #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */ | |
742 | #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */ | |
743 | #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */ | |
744 | #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */ | |
745 | #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */ | |
f6ef3b18 | 746 | #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */ |
1da177e4 LT |
747 | #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */ |
748 | #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */ | |
749 | #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */ | |
750 | #define MBC_RESET 0x18 /* Reset. */ | |
751 | #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */ | |
752 | #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */ | |
753 | #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */ | |
754 | #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */ | |
755 | #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */ | |
756 | #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */ | |
757 | #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */ | |
758 | #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */ | |
759 | #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */ | |
760 | #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */ | |
761 | #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */ | |
762 | #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */ | |
763 | #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */ | |
764 | #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */ | |
6246b8a1 | 765 | #define MBC_CONFIGURE_VF 0x4b /* Configure VFs */ |
1da177e4 LT |
766 | #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */ |
767 | #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */ | |
af11f64d | 768 | #define MBC_PORT_LOGOUT 0x56 /* Port Logout request */ |
1da177e4 LT |
769 | #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */ |
770 | #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */ | |
90687a1e JC |
771 | #define MBC_GET_RNID_PARAMS 0x5a /* Get RNID parameters */ |
772 | #define MBC_DATA_RATE 0x5d /* Data Rate */ | |
1da177e4 LT |
773 | #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */ |
774 | #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */ | |
775 | /* Initialization Procedure */ | |
776 | #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */ | |
777 | #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */ | |
778 | #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */ | |
779 | #define MBC_TARGET_RESET 0x66 /* Target Reset. */ | |
780 | #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */ | |
781 | #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */ | |
782 | #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */ | |
783 | #define MBC_GET_PORT_NAME 0x6a /* Get port name. */ | |
784 | #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */ | |
785 | #define MBC_LIP_RESET 0x6c /* LIP reset. */ | |
786 | #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */ | |
787 | /* commandd. */ | |
788 | #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */ | |
789 | #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */ | |
790 | #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */ | |
791 | #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */ | |
792 | #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */ | |
793 | #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */ | |
794 | #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */ | |
795 | #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */ | |
796 | #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */ | |
797 | #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */ | |
798 | #define MBC_LUN_RESET 0x7E /* Send LUN reset */ | |
799 | ||
3d71644c AV |
800 | /* |
801 | * ISP24xx mailbox commands | |
802 | */ | |
803 | #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */ | |
804 | #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */ | |
d8b45213 | 805 | #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */ |
3d71644c | 806 | #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */ |
a7a167bf | 807 | #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */ |
3d71644c | 808 | #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */ |
ad0ecd61 | 809 | #define MBC_WRITE_SFP 0x30 /* Write SFP Data. */ |
88729e53 | 810 | #define MBC_READ_SFP 0x31 /* Read SFP Data. */ |
3d71644c AV |
811 | #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */ |
812 | #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */ | |
813 | #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */ | |
814 | #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */ | |
815 | #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */ | |
816 | #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */ | |
817 | #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */ | |
61e1b269 | 818 | #define MBC_LINK_INITIALIZATION 0x72 /* Do link initialization. */ |
3d71644c | 819 | #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */ |
8fcd6b8b | 820 | #define MBC_PORT_RESET 0x120 /* Port Reset */ |
23f2ebd1 SR |
821 | #define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */ |
822 | #define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */ | |
3d71644c | 823 | |
b1d46989 MI |
824 | /* |
825 | * ISP81xx mailbox commands | |
826 | */ | |
827 | #define MBC_WRITE_MPI_REGISTER 0x01 /* Write MPI Register. */ | |
828 | ||
1da177e4 LT |
829 | /* Firmware return data sizes */ |
830 | #define FCAL_MAP_SIZE 128 | |
831 | ||
832 | /* Mailbox bit definitions for out_mb and in_mb */ | |
833 | #define MBX_31 BIT_31 | |
834 | #define MBX_30 BIT_30 | |
835 | #define MBX_29 BIT_29 | |
836 | #define MBX_28 BIT_28 | |
837 | #define MBX_27 BIT_27 | |
838 | #define MBX_26 BIT_26 | |
839 | #define MBX_25 BIT_25 | |
840 | #define MBX_24 BIT_24 | |
841 | #define MBX_23 BIT_23 | |
842 | #define MBX_22 BIT_22 | |
843 | #define MBX_21 BIT_21 | |
844 | #define MBX_20 BIT_20 | |
845 | #define MBX_19 BIT_19 | |
846 | #define MBX_18 BIT_18 | |
847 | #define MBX_17 BIT_17 | |
848 | #define MBX_16 BIT_16 | |
849 | #define MBX_15 BIT_15 | |
850 | #define MBX_14 BIT_14 | |
851 | #define MBX_13 BIT_13 | |
852 | #define MBX_12 BIT_12 | |
853 | #define MBX_11 BIT_11 | |
854 | #define MBX_10 BIT_10 | |
855 | #define MBX_9 BIT_9 | |
856 | #define MBX_8 BIT_8 | |
857 | #define MBX_7 BIT_7 | |
858 | #define MBX_6 BIT_6 | |
859 | #define MBX_5 BIT_5 | |
860 | #define MBX_4 BIT_4 | |
861 | #define MBX_3 BIT_3 | |
862 | #define MBX_2 BIT_2 | |
863 | #define MBX_1 BIT_1 | |
864 | #define MBX_0 BIT_0 | |
865 | ||
3a11711a | 866 | #define RNID_TYPE_SET_VERSION 0x9 |
fe52f6e1 | 867 | #define RNID_TYPE_ASIC_TEMP 0xC |
3a11711a | 868 | |
1da177e4 LT |
869 | /* |
870 | * Firmware state codes from get firmware state mailbox command | |
871 | */ | |
872 | #define FSTATE_CONFIG_WAIT 0 | |
873 | #define FSTATE_WAIT_AL_PA 1 | |
874 | #define FSTATE_WAIT_LOGIN 2 | |
875 | #define FSTATE_READY 3 | |
876 | #define FSTATE_LOSS_OF_SYNC 4 | |
877 | #define FSTATE_ERROR 5 | |
878 | #define FSTATE_REINIT 6 | |
879 | #define FSTATE_NON_PART 7 | |
880 | ||
881 | #define FSTATE_CONFIG_CORRECT 0 | |
882 | #define FSTATE_P2P_RCV_LIP 1 | |
883 | #define FSTATE_P2P_CHOOSE_LOOP 2 | |
884 | #define FSTATE_P2P_RCV_UNIDEN_LIP 3 | |
885 | #define FSTATE_FATAL_ERROR 4 | |
886 | #define FSTATE_LOOP_BACK_CONN 5 | |
887 | ||
888 | /* | |
889 | * Port Database structure definition | |
890 | * Little endian except where noted. | |
891 | */ | |
892 | #define PORT_DATABASE_SIZE 128 /* bytes */ | |
893 | typedef struct { | |
894 | uint8_t options; | |
895 | uint8_t control; | |
896 | uint8_t master_state; | |
897 | uint8_t slave_state; | |
898 | uint8_t reserved[2]; | |
899 | uint8_t hard_address; | |
900 | uint8_t reserved_1; | |
901 | uint8_t port_id[4]; | |
902 | uint8_t node_name[WWN_SIZE]; | |
903 | uint8_t port_name[WWN_SIZE]; | |
904 | uint16_t execution_throttle; | |
905 | uint16_t execution_count; | |
906 | uint8_t reset_count; | |
907 | uint8_t reserved_2; | |
908 | uint16_t resource_allocation; | |
909 | uint16_t current_allocation; | |
910 | uint16_t queue_head; | |
911 | uint16_t queue_tail; | |
912 | uint16_t transmit_execution_list_next; | |
913 | uint16_t transmit_execution_list_previous; | |
914 | uint16_t common_features; | |
915 | uint16_t total_concurrent_sequences; | |
916 | uint16_t RO_by_information_category; | |
917 | uint8_t recipient; | |
918 | uint8_t initiator; | |
919 | uint16_t receive_data_size; | |
920 | uint16_t concurrent_sequences; | |
921 | uint16_t open_sequences_per_exchange; | |
922 | uint16_t lun_abort_flags; | |
923 | uint16_t lun_stop_flags; | |
924 | uint16_t stop_queue_head; | |
925 | uint16_t stop_queue_tail; | |
926 | uint16_t port_retry_timer; | |
927 | uint16_t next_sequence_id; | |
928 | uint16_t frame_count; | |
929 | uint16_t PRLI_payload_length; | |
930 | uint8_t prli_svc_param_word_0[2]; /* Big endian */ | |
931 | /* Bits 15-0 of word 0 */ | |
932 | uint8_t prli_svc_param_word_3[2]; /* Big endian */ | |
933 | /* Bits 15-0 of word 3 */ | |
934 | uint16_t loop_id; | |
935 | uint16_t extended_lun_info_list_pointer; | |
936 | uint16_t extended_lun_stop_list_pointer; | |
937 | } port_database_t; | |
938 | ||
939 | /* | |
940 | * Port database slave/master states | |
941 | */ | |
942 | #define PD_STATE_DISCOVERY 0 | |
943 | #define PD_STATE_WAIT_DISCOVERY_ACK 1 | |
944 | #define PD_STATE_PORT_LOGIN 2 | |
945 | #define PD_STATE_WAIT_PORT_LOGIN_ACK 3 | |
946 | #define PD_STATE_PROCESS_LOGIN 4 | |
947 | #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5 | |
948 | #define PD_STATE_PORT_LOGGED_IN 6 | |
949 | #define PD_STATE_PORT_UNAVAILABLE 7 | |
950 | #define PD_STATE_PROCESS_LOGOUT 8 | |
951 | #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9 | |
952 | #define PD_STATE_PORT_LOGOUT 10 | |
953 | #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11 | |
954 | ||
955 | ||
4fdfefe5 AV |
956 | #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1) |
957 | #define QLA_ZIO_DISABLED 0 | |
958 | #define QLA_ZIO_DEFAULT_TIMER 2 | |
959 | ||
1da177e4 LT |
960 | /* |
961 | * ISP Initialization Control Block. | |
962 | * Little endian except where noted. | |
963 | */ | |
964 | #define ICB_VERSION 1 | |
965 | typedef struct { | |
966 | uint8_t version; | |
967 | uint8_t reserved_1; | |
968 | ||
969 | /* | |
970 | * LSB BIT 0 = Enable Hard Loop Id | |
971 | * LSB BIT 1 = Enable Fairness | |
972 | * LSB BIT 2 = Enable Full-Duplex | |
973 | * LSB BIT 3 = Enable Fast Posting | |
974 | * LSB BIT 4 = Enable Target Mode | |
975 | * LSB BIT 5 = Disable Initiator Mode | |
976 | * LSB BIT 6 = Enable ADISC | |
977 | * LSB BIT 7 = Enable Target Inquiry Data | |
978 | * | |
979 | * MSB BIT 0 = Enable PDBC Notify | |
980 | * MSB BIT 1 = Non Participating LIP | |
981 | * MSB BIT 2 = Descending Loop ID Search | |
982 | * MSB BIT 3 = Acquire Loop ID in LIPA | |
983 | * MSB BIT 4 = Stop PortQ on Full Status | |
984 | * MSB BIT 5 = Full Login after LIP | |
985 | * MSB BIT 6 = Node Name Option | |
986 | * MSB BIT 7 = Ext IFWCB enable bit | |
987 | */ | |
988 | uint8_t firmware_options[2]; | |
989 | ||
990 | uint16_t frame_payload_size; | |
991 | uint16_t max_iocb_allocation; | |
992 | uint16_t execution_throttle; | |
993 | uint8_t retry_count; | |
994 | uint8_t retry_delay; /* unused */ | |
995 | uint8_t port_name[WWN_SIZE]; /* Big endian. */ | |
996 | uint16_t hard_address; | |
997 | uint8_t inquiry_data; | |
998 | uint8_t login_timeout; | |
999 | uint8_t node_name[WWN_SIZE]; /* Big endian. */ | |
1000 | ||
1001 | uint16_t request_q_outpointer; | |
1002 | uint16_t response_q_inpointer; | |
1003 | uint16_t request_q_length; | |
1004 | uint16_t response_q_length; | |
1005 | uint32_t request_q_address[2]; | |
1006 | uint32_t response_q_address[2]; | |
1007 | ||
1008 | uint16_t lun_enables; | |
1009 | uint8_t command_resource_count; | |
1010 | uint8_t immediate_notify_resource_count; | |
1011 | uint16_t timeout; | |
1012 | uint8_t reserved_2[2]; | |
1013 | ||
1014 | /* | |
1015 | * LSB BIT 0 = Timer Operation mode bit 0 | |
1016 | * LSB BIT 1 = Timer Operation mode bit 1 | |
1017 | * LSB BIT 2 = Timer Operation mode bit 2 | |
1018 | * LSB BIT 3 = Timer Operation mode bit 3 | |
1019 | * LSB BIT 4 = Init Config Mode bit 0 | |
1020 | * LSB BIT 5 = Init Config Mode bit 1 | |
1021 | * LSB BIT 6 = Init Config Mode bit 2 | |
1022 | * LSB BIT 7 = Enable Non part on LIHA failure | |
1023 | * | |
1024 | * MSB BIT 0 = Enable class 2 | |
1025 | * MSB BIT 1 = Enable ACK0 | |
1026 | * MSB BIT 2 = | |
1027 | * MSB BIT 3 = | |
1028 | * MSB BIT 4 = FC Tape Enable | |
1029 | * MSB BIT 5 = Enable FC Confirm | |
1030 | * MSB BIT 6 = Enable command queuing in target mode | |
1031 | * MSB BIT 7 = No Logo On Link Down | |
1032 | */ | |
1033 | uint8_t add_firmware_options[2]; | |
1034 | ||
1035 | uint8_t response_accumulation_timer; | |
1036 | uint8_t interrupt_delay_timer; | |
1037 | ||
1038 | /* | |
1039 | * LSB BIT 0 = Enable Read xfr_rdy | |
1040 | * LSB BIT 1 = Soft ID only | |
1041 | * LSB BIT 2 = | |
1042 | * LSB BIT 3 = | |
1043 | * LSB BIT 4 = FCP RSP Payload [0] | |
1044 | * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 | |
1045 | * LSB BIT 6 = Enable Out-of-Order frame handling | |
1046 | * LSB BIT 7 = Disable Automatic PLOGI on Local Loop | |
1047 | * | |
1048 | * MSB BIT 0 = Sbus enable - 2300 | |
1049 | * MSB BIT 1 = | |
1050 | * MSB BIT 2 = | |
1051 | * MSB BIT 3 = | |
06c22bd1 | 1052 | * MSB BIT 4 = LED mode |
1da177e4 LT |
1053 | * MSB BIT 5 = enable 50 ohm termination |
1054 | * MSB BIT 6 = Data Rate (2300 only) | |
1055 | * MSB BIT 7 = Data Rate (2300 only) | |
1056 | */ | |
1057 | uint8_t special_options[2]; | |
1058 | ||
1059 | uint8_t reserved_3[26]; | |
1060 | } init_cb_t; | |
1061 | ||
1062 | /* | |
1063 | * Get Link Status mailbox command return buffer. | |
1064 | */ | |
3d71644c AV |
1065 | #define GLSO_SEND_RPS BIT_0 |
1066 | #define GLSO_USE_DID BIT_3 | |
1067 | ||
43ef0580 AV |
1068 | struct link_statistics { |
1069 | uint32_t link_fail_cnt; | |
1070 | uint32_t loss_sync_cnt; | |
1071 | uint32_t loss_sig_cnt; | |
1072 | uint32_t prim_seq_err_cnt; | |
1073 | uint32_t inval_xmit_word_cnt; | |
1074 | uint32_t inval_crc_cnt; | |
032d8dd7 HZ |
1075 | uint32_t lip_cnt; |
1076 | uint32_t unused1[0x1a]; | |
43ef0580 AV |
1077 | uint32_t tx_frames; |
1078 | uint32_t rx_frames; | |
1079 | uint32_t dumped_frames; | |
1080 | uint32_t unused2[2]; | |
1081 | uint32_t nos_rcvd; | |
1082 | }; | |
1da177e4 LT |
1083 | |
1084 | /* | |
1085 | * NVRAM Command values. | |
1086 | */ | |
1087 | #define NV_START_BIT BIT_2 | |
1088 | #define NV_WRITE_OP (BIT_26+BIT_24) | |
1089 | #define NV_READ_OP (BIT_26+BIT_25) | |
1090 | #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24) | |
1091 | #define NV_MASK_OP (BIT_26+BIT_25+BIT_24) | |
1092 | #define NV_DELAY_COUNT 10 | |
1093 | ||
1094 | /* | |
1095 | * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition. | |
1096 | */ | |
1097 | typedef struct { | |
1098 | /* | |
1099 | * NVRAM header | |
1100 | */ | |
1101 | uint8_t id[4]; | |
1102 | uint8_t nvram_version; | |
1103 | uint8_t reserved_0; | |
1104 | ||
1105 | /* | |
1106 | * NVRAM RISC parameter block | |
1107 | */ | |
1108 | uint8_t parameter_block_version; | |
1109 | uint8_t reserved_1; | |
1110 | ||
1111 | /* | |
1112 | * LSB BIT 0 = Enable Hard Loop Id | |
1113 | * LSB BIT 1 = Enable Fairness | |
1114 | * LSB BIT 2 = Enable Full-Duplex | |
1115 | * LSB BIT 3 = Enable Fast Posting | |
1116 | * LSB BIT 4 = Enable Target Mode | |
1117 | * LSB BIT 5 = Disable Initiator Mode | |
1118 | * LSB BIT 6 = Enable ADISC | |
1119 | * LSB BIT 7 = Enable Target Inquiry Data | |
1120 | * | |
1121 | * MSB BIT 0 = Enable PDBC Notify | |
1122 | * MSB BIT 1 = Non Participating LIP | |
1123 | * MSB BIT 2 = Descending Loop ID Search | |
1124 | * MSB BIT 3 = Acquire Loop ID in LIPA | |
1125 | * MSB BIT 4 = Stop PortQ on Full Status | |
1126 | * MSB BIT 5 = Full Login after LIP | |
1127 | * MSB BIT 6 = Node Name Option | |
1128 | * MSB BIT 7 = Ext IFWCB enable bit | |
1129 | */ | |
1130 | uint8_t firmware_options[2]; | |
1131 | ||
1132 | uint16_t frame_payload_size; | |
1133 | uint16_t max_iocb_allocation; | |
1134 | uint16_t execution_throttle; | |
1135 | uint8_t retry_count; | |
1136 | uint8_t retry_delay; /* unused */ | |
1137 | uint8_t port_name[WWN_SIZE]; /* Big endian. */ | |
1138 | uint16_t hard_address; | |
1139 | uint8_t inquiry_data; | |
1140 | uint8_t login_timeout; | |
1141 | uint8_t node_name[WWN_SIZE]; /* Big endian. */ | |
1142 | ||
1143 | /* | |
1144 | * LSB BIT 0 = Timer Operation mode bit 0 | |
1145 | * LSB BIT 1 = Timer Operation mode bit 1 | |
1146 | * LSB BIT 2 = Timer Operation mode bit 2 | |
1147 | * LSB BIT 3 = Timer Operation mode bit 3 | |
1148 | * LSB BIT 4 = Init Config Mode bit 0 | |
1149 | * LSB BIT 5 = Init Config Mode bit 1 | |
1150 | * LSB BIT 6 = Init Config Mode bit 2 | |
1151 | * LSB BIT 7 = Enable Non part on LIHA failure | |
1152 | * | |
1153 | * MSB BIT 0 = Enable class 2 | |
1154 | * MSB BIT 1 = Enable ACK0 | |
1155 | * MSB BIT 2 = | |
1156 | * MSB BIT 3 = | |
1157 | * MSB BIT 4 = FC Tape Enable | |
1158 | * MSB BIT 5 = Enable FC Confirm | |
1159 | * MSB BIT 6 = Enable command queuing in target mode | |
1160 | * MSB BIT 7 = No Logo On Link Down | |
1161 | */ | |
1162 | uint8_t add_firmware_options[2]; | |
1163 | ||
1164 | uint8_t response_accumulation_timer; | |
1165 | uint8_t interrupt_delay_timer; | |
1166 | ||
1167 | /* | |
1168 | * LSB BIT 0 = Enable Read xfr_rdy | |
1169 | * LSB BIT 1 = Soft ID only | |
1170 | * LSB BIT 2 = | |
1171 | * LSB BIT 3 = | |
1172 | * LSB BIT 4 = FCP RSP Payload [0] | |
1173 | * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 | |
1174 | * LSB BIT 6 = Enable Out-of-Order frame handling | |
1175 | * LSB BIT 7 = Disable Automatic PLOGI on Local Loop | |
1176 | * | |
1177 | * MSB BIT 0 = Sbus enable - 2300 | |
1178 | * MSB BIT 1 = | |
1179 | * MSB BIT 2 = | |
1180 | * MSB BIT 3 = | |
06c22bd1 | 1181 | * MSB BIT 4 = LED mode |
1da177e4 LT |
1182 | * MSB BIT 5 = enable 50 ohm termination |
1183 | * MSB BIT 6 = Data Rate (2300 only) | |
1184 | * MSB BIT 7 = Data Rate (2300 only) | |
1185 | */ | |
1186 | uint8_t special_options[2]; | |
1187 | ||
1188 | /* Reserved for expanded RISC parameter block */ | |
1189 | uint8_t reserved_2[22]; | |
1190 | ||
1191 | /* | |
1192 | * LSB BIT 0 = Tx Sensitivity 1G bit 0 | |
1193 | * LSB BIT 1 = Tx Sensitivity 1G bit 1 | |
1194 | * LSB BIT 2 = Tx Sensitivity 1G bit 2 | |
1195 | * LSB BIT 3 = Tx Sensitivity 1G bit 3 | |
1196 | * LSB BIT 4 = Rx Sensitivity 1G bit 0 | |
1197 | * LSB BIT 5 = Rx Sensitivity 1G bit 1 | |
1198 | * LSB BIT 6 = Rx Sensitivity 1G bit 2 | |
1199 | * LSB BIT 7 = Rx Sensitivity 1G bit 3 | |
fa2a1ce5 | 1200 | * |
1da177e4 LT |
1201 | * MSB BIT 0 = Tx Sensitivity 2G bit 0 |
1202 | * MSB BIT 1 = Tx Sensitivity 2G bit 1 | |
1203 | * MSB BIT 2 = Tx Sensitivity 2G bit 2 | |
1204 | * MSB BIT 3 = Tx Sensitivity 2G bit 3 | |
1205 | * MSB BIT 4 = Rx Sensitivity 2G bit 0 | |
1206 | * MSB BIT 5 = Rx Sensitivity 2G bit 1 | |
1207 | * MSB BIT 6 = Rx Sensitivity 2G bit 2 | |
1208 | * MSB BIT 7 = Rx Sensitivity 2G bit 3 | |
1209 | * | |
1210 | * LSB BIT 0 = Output Swing 1G bit 0 | |
1211 | * LSB BIT 1 = Output Swing 1G bit 1 | |
1212 | * LSB BIT 2 = Output Swing 1G bit 2 | |
1213 | * LSB BIT 3 = Output Emphasis 1G bit 0 | |
1214 | * LSB BIT 4 = Output Emphasis 1G bit 1 | |
1215 | * LSB BIT 5 = Output Swing 2G bit 0 | |
1216 | * LSB BIT 6 = Output Swing 2G bit 1 | |
1217 | * LSB BIT 7 = Output Swing 2G bit 2 | |
fa2a1ce5 | 1218 | * |
1da177e4 LT |
1219 | * MSB BIT 0 = Output Emphasis 2G bit 0 |
1220 | * MSB BIT 1 = Output Emphasis 2G bit 1 | |
1221 | * MSB BIT 2 = Output Enable | |
1222 | * MSB BIT 3 = | |
1223 | * MSB BIT 4 = | |
1224 | * MSB BIT 5 = | |
1225 | * MSB BIT 6 = | |
1226 | * MSB BIT 7 = | |
1227 | */ | |
1228 | uint8_t seriallink_options[4]; | |
1229 | ||
1230 | /* | |
1231 | * NVRAM host parameter block | |
1232 | * | |
1233 | * LSB BIT 0 = Enable spinup delay | |
1234 | * LSB BIT 1 = Disable BIOS | |
1235 | * LSB BIT 2 = Enable Memory Map BIOS | |
1236 | * LSB BIT 3 = Enable Selectable Boot | |
1237 | * LSB BIT 4 = Disable RISC code load | |
1238 | * LSB BIT 5 = Set cache line size 1 | |
1239 | * LSB BIT 6 = PCI Parity Disable | |
1240 | * LSB BIT 7 = Enable extended logging | |
1241 | * | |
1242 | * MSB BIT 0 = Enable 64bit addressing | |
1243 | * MSB BIT 1 = Enable lip reset | |
1244 | * MSB BIT 2 = Enable lip full login | |
1245 | * MSB BIT 3 = Enable target reset | |
1246 | * MSB BIT 4 = Enable database storage | |
1247 | * MSB BIT 5 = Enable cache flush read | |
1248 | * MSB BIT 6 = Enable database load | |
1249 | * MSB BIT 7 = Enable alternate WWN | |
1250 | */ | |
1251 | uint8_t host_p[2]; | |
1252 | ||
1253 | uint8_t boot_node_name[WWN_SIZE]; | |
1254 | uint8_t boot_lun_number; | |
1255 | uint8_t reset_delay; | |
1256 | uint8_t port_down_retry_count; | |
1257 | uint8_t boot_id_number; | |
1258 | uint16_t max_luns_per_target; | |
1259 | uint8_t fcode_boot_port_name[WWN_SIZE]; | |
1260 | uint8_t alternate_port_name[WWN_SIZE]; | |
1261 | uint8_t alternate_node_name[WWN_SIZE]; | |
1262 | ||
1263 | /* | |
1264 | * BIT 0 = Selective Login | |
1265 | * BIT 1 = Alt-Boot Enable | |
1266 | * BIT 2 = | |
1267 | * BIT 3 = Boot Order List | |
1268 | * BIT 4 = | |
1269 | * BIT 5 = Selective LUN | |
1270 | * BIT 6 = | |
1271 | * BIT 7 = unused | |
1272 | */ | |
1273 | uint8_t efi_parameters; | |
1274 | ||
1275 | uint8_t link_down_timeout; | |
1276 | ||
cca5335c | 1277 | uint8_t adapter_id[16]; |
1da177e4 LT |
1278 | |
1279 | uint8_t alt1_boot_node_name[WWN_SIZE]; | |
1280 | uint16_t alt1_boot_lun_number; | |
1281 | uint8_t alt2_boot_node_name[WWN_SIZE]; | |
1282 | uint16_t alt2_boot_lun_number; | |
1283 | uint8_t alt3_boot_node_name[WWN_SIZE]; | |
1284 | uint16_t alt3_boot_lun_number; | |
1285 | uint8_t alt4_boot_node_name[WWN_SIZE]; | |
1286 | uint16_t alt4_boot_lun_number; | |
1287 | uint8_t alt5_boot_node_name[WWN_SIZE]; | |
1288 | uint16_t alt5_boot_lun_number; | |
1289 | uint8_t alt6_boot_node_name[WWN_SIZE]; | |
1290 | uint16_t alt6_boot_lun_number; | |
1291 | uint8_t alt7_boot_node_name[WWN_SIZE]; | |
1292 | uint16_t alt7_boot_lun_number; | |
1293 | ||
1294 | uint8_t reserved_3[2]; | |
1295 | ||
1296 | /* Offset 200-215 : Model Number */ | |
1297 | uint8_t model_number[16]; | |
1298 | ||
1299 | /* OEM related items */ | |
1300 | uint8_t oem_specific[16]; | |
1301 | ||
1302 | /* | |
1303 | * NVRAM Adapter Features offset 232-239 | |
1304 | * | |
1305 | * LSB BIT 0 = External GBIC | |
1306 | * LSB BIT 1 = Risc RAM parity | |
1307 | * LSB BIT 2 = Buffer Plus Module | |
1308 | * LSB BIT 3 = Multi Chip Adapter | |
1309 | * LSB BIT 4 = Internal connector | |
1310 | * LSB BIT 5 = | |
1311 | * LSB BIT 6 = | |
1312 | * LSB BIT 7 = | |
1313 | * | |
1314 | * MSB BIT 0 = | |
1315 | * MSB BIT 1 = | |
1316 | * MSB BIT 2 = | |
1317 | * MSB BIT 3 = | |
1318 | * MSB BIT 4 = | |
1319 | * MSB BIT 5 = | |
1320 | * MSB BIT 6 = | |
1321 | * MSB BIT 7 = | |
1322 | */ | |
1323 | uint8_t adapter_features[2]; | |
1324 | ||
1325 | uint8_t reserved_4[16]; | |
1326 | ||
1327 | /* Subsystem vendor ID for ISP2200 */ | |
1328 | uint16_t subsystem_vendor_id_2200; | |
1329 | ||
1330 | /* Subsystem device ID for ISP2200 */ | |
1331 | uint16_t subsystem_device_id_2200; | |
1332 | ||
1333 | uint8_t reserved_5; | |
1334 | uint8_t checksum; | |
1335 | } nvram_t; | |
1336 | ||
1337 | /* | |
1338 | * ISP queue - response queue entry definition. | |
1339 | */ | |
1340 | typedef struct { | |
2d70c103 NB |
1341 | uint8_t entry_type; /* Entry type. */ |
1342 | uint8_t entry_count; /* Entry count. */ | |
1343 | uint8_t sys_define; /* System defined. */ | |
1344 | uint8_t entry_status; /* Entry Status. */ | |
1345 | uint32_t handle; /* System defined handle */ | |
1346 | uint8_t data[52]; | |
1da177e4 LT |
1347 | uint32_t signature; |
1348 | #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */ | |
1349 | } response_t; | |
1350 | ||
2d70c103 NB |
1351 | /* |
1352 | * ISP queue - ATIO queue entry definition. | |
1353 | */ | |
1354 | struct atio { | |
1355 | uint8_t entry_type; /* Entry type. */ | |
1356 | uint8_t entry_count; /* Entry count. */ | |
1357 | uint8_t data[58]; | |
1358 | uint32_t signature; | |
1359 | #define ATIO_PROCESSED 0xDEADDEAD /* Signature */ | |
1360 | }; | |
1361 | ||
1da177e4 LT |
1362 | typedef union { |
1363 | uint16_t extended; | |
1364 | struct { | |
1365 | uint8_t reserved; | |
1366 | uint8_t standard; | |
1367 | } id; | |
1368 | } target_id_t; | |
1369 | ||
1370 | #define SET_TARGET_ID(ha, to, from) \ | |
1371 | do { \ | |
1372 | if (HAS_EXTENDED_IDS(ha)) \ | |
1373 | to.extended = cpu_to_le16(from); \ | |
1374 | else \ | |
1375 | to.id.standard = (uint8_t)from; \ | |
1376 | } while (0) | |
1377 | ||
1378 | /* | |
1379 | * ISP queue - command entry structure definition. | |
1380 | */ | |
1381 | #define COMMAND_TYPE 0x11 /* Command entry */ | |
1da177e4 LT |
1382 | typedef struct { |
1383 | uint8_t entry_type; /* Entry type. */ | |
1384 | uint8_t entry_count; /* Entry count. */ | |
1385 | uint8_t sys_define; /* System defined. */ | |
1386 | uint8_t entry_status; /* Entry Status. */ | |
1387 | uint32_t handle; /* System handle. */ | |
1388 | target_id_t target; /* SCSI ID */ | |
1389 | uint16_t lun; /* SCSI LUN */ | |
1390 | uint16_t control_flags; /* Control flags. */ | |
1391 | #define CF_WRITE BIT_6 | |
1392 | #define CF_READ BIT_5 | |
1393 | #define CF_SIMPLE_TAG BIT_3 | |
1394 | #define CF_ORDERED_TAG BIT_2 | |
1395 | #define CF_HEAD_TAG BIT_1 | |
1396 | uint16_t reserved_1; | |
1397 | uint16_t timeout; /* Command timeout. */ | |
1398 | uint16_t dseg_count; /* Data segment count. */ | |
1399 | uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ | |
1400 | uint32_t byte_count; /* Total byte count. */ | |
1401 | uint32_t dseg_0_address; /* Data segment 0 address. */ | |
1402 | uint32_t dseg_0_length; /* Data segment 0 length. */ | |
1403 | uint32_t dseg_1_address; /* Data segment 1 address. */ | |
1404 | uint32_t dseg_1_length; /* Data segment 1 length. */ | |
1405 | uint32_t dseg_2_address; /* Data segment 2 address. */ | |
1406 | uint32_t dseg_2_length; /* Data segment 2 length. */ | |
1407 | } cmd_entry_t; | |
1408 | ||
1409 | /* | |
1410 | * ISP queue - 64-Bit addressing, command entry structure definition. | |
1411 | */ | |
1412 | #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */ | |
1413 | typedef struct { | |
1414 | uint8_t entry_type; /* Entry type. */ | |
1415 | uint8_t entry_count; /* Entry count. */ | |
1416 | uint8_t sys_define; /* System defined. */ | |
1417 | uint8_t entry_status; /* Entry Status. */ | |
1418 | uint32_t handle; /* System handle. */ | |
1419 | target_id_t target; /* SCSI ID */ | |
1420 | uint16_t lun; /* SCSI LUN */ | |
1421 | uint16_t control_flags; /* Control flags. */ | |
1422 | uint16_t reserved_1; | |
1423 | uint16_t timeout; /* Command timeout. */ | |
1424 | uint16_t dseg_count; /* Data segment count. */ | |
1425 | uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ | |
1426 | uint32_t byte_count; /* Total byte count. */ | |
1427 | uint32_t dseg_0_address[2]; /* Data segment 0 address. */ | |
1428 | uint32_t dseg_0_length; /* Data segment 0 length. */ | |
1429 | uint32_t dseg_1_address[2]; /* Data segment 1 address. */ | |
1430 | uint32_t dseg_1_length; /* Data segment 1 length. */ | |
1431 | } cmd_a64_entry_t, request_t; | |
1432 | ||
1433 | /* | |
1434 | * ISP queue - continuation entry structure definition. | |
1435 | */ | |
1436 | #define CONTINUE_TYPE 0x02 /* Continuation entry. */ | |
1437 | typedef struct { | |
1438 | uint8_t entry_type; /* Entry type. */ | |
1439 | uint8_t entry_count; /* Entry count. */ | |
1440 | uint8_t sys_define; /* System defined. */ | |
1441 | uint8_t entry_status; /* Entry Status. */ | |
1442 | uint32_t reserved; | |
1443 | uint32_t dseg_0_address; /* Data segment 0 address. */ | |
1444 | uint32_t dseg_0_length; /* Data segment 0 length. */ | |
1445 | uint32_t dseg_1_address; /* Data segment 1 address. */ | |
1446 | uint32_t dseg_1_length; /* Data segment 1 length. */ | |
1447 | uint32_t dseg_2_address; /* Data segment 2 address. */ | |
1448 | uint32_t dseg_2_length; /* Data segment 2 length. */ | |
1449 | uint32_t dseg_3_address; /* Data segment 3 address. */ | |
1450 | uint32_t dseg_3_length; /* Data segment 3 length. */ | |
1451 | uint32_t dseg_4_address; /* Data segment 4 address. */ | |
1452 | uint32_t dseg_4_length; /* Data segment 4 length. */ | |
1453 | uint32_t dseg_5_address; /* Data segment 5 address. */ | |
1454 | uint32_t dseg_5_length; /* Data segment 5 length. */ | |
1455 | uint32_t dseg_6_address; /* Data segment 6 address. */ | |
1456 | uint32_t dseg_6_length; /* Data segment 6 length. */ | |
1457 | } cont_entry_t; | |
1458 | ||
1459 | /* | |
1460 | * ISP queue - 64-Bit addressing, continuation entry structure definition. | |
1461 | */ | |
1462 | #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */ | |
1463 | typedef struct { | |
1464 | uint8_t entry_type; /* Entry type. */ | |
1465 | uint8_t entry_count; /* Entry count. */ | |
1466 | uint8_t sys_define; /* System defined. */ | |
1467 | uint8_t entry_status; /* Entry Status. */ | |
1468 | uint32_t dseg_0_address[2]; /* Data segment 0 address. */ | |
1469 | uint32_t dseg_0_length; /* Data segment 0 length. */ | |
1470 | uint32_t dseg_1_address[2]; /* Data segment 1 address. */ | |
1471 | uint32_t dseg_1_length; /* Data segment 1 length. */ | |
1472 | uint32_t dseg_2_address [2]; /* Data segment 2 address. */ | |
1473 | uint32_t dseg_2_length; /* Data segment 2 length. */ | |
1474 | uint32_t dseg_3_address[2]; /* Data segment 3 address. */ | |
1475 | uint32_t dseg_3_length; /* Data segment 3 length. */ | |
1476 | uint32_t dseg_4_address[2]; /* Data segment 4 address. */ | |
1477 | uint32_t dseg_4_length; /* Data segment 4 length. */ | |
1478 | } cont_a64_entry_t; | |
1479 | ||
bad75002 | 1480 | #define PO_MODE_DIF_INSERT 0 |
9e522cd8 AE |
1481 | #define PO_MODE_DIF_REMOVE 1 |
1482 | #define PO_MODE_DIF_PASS 2 | |
1483 | #define PO_MODE_DIF_REPLACE 3 | |
1484 | #define PO_MODE_DIF_TCP_CKSUM 6 | |
bad75002 AE |
1485 | #define PO_ENABLE_DIF_BUNDLING BIT_8 |
1486 | #define PO_ENABLE_INCR_GUARD_SEED BIT_3 | |
1487 | #define PO_DISABLE_INCR_REF_TAG BIT_5 | |
1488 | #define PO_DISABLE_GUARD_CHECK BIT_4 | |
1489 | /* | |
1490 | * ISP queue - 64-Bit addressing, continuation crc entry structure definition. | |
1491 | */ | |
1492 | struct crc_context { | |
1493 | uint32_t handle; /* System handle. */ | |
1494 | uint32_t ref_tag; | |
1495 | uint16_t app_tag; | |
1496 | uint8_t ref_tag_mask[4]; /* Validation/Replacement Mask*/ | |
1497 | uint8_t app_tag_mask[2]; /* Validation/Replacement Mask*/ | |
1498 | uint16_t guard_seed; /* Initial Guard Seed */ | |
1499 | uint16_t prot_opts; /* Requested Data Protection Mode */ | |
1500 | uint16_t blk_size; /* Data size in bytes */ | |
1501 | uint16_t runt_blk_guard; /* Guard value for runt block (tape | |
1502 | * only) */ | |
1503 | uint32_t byte_count; /* Total byte count/ total data | |
1504 | * transfer count */ | |
1505 | union { | |
1506 | struct { | |
1507 | uint32_t reserved_1; | |
1508 | uint16_t reserved_2; | |
1509 | uint16_t reserved_3; | |
1510 | uint32_t reserved_4; | |
1511 | uint32_t data_address[2]; | |
1512 | uint32_t data_length; | |
1513 | uint32_t reserved_5[2]; | |
1514 | uint32_t reserved_6; | |
1515 | } nobundling; | |
1516 | struct { | |
1517 | uint32_t dif_byte_count; /* Total DIF byte | |
1518 | * count */ | |
1519 | uint16_t reserved_1; | |
1520 | uint16_t dseg_count; /* Data segment count */ | |
1521 | uint32_t reserved_2; | |
1522 | uint32_t data_address[2]; | |
1523 | uint32_t data_length; | |
1524 | uint32_t dif_address[2]; | |
1525 | uint32_t dif_length; /* Data segment 0 | |
1526 | * length */ | |
1527 | } bundling; | |
1528 | } u; | |
1529 | ||
1530 | struct fcp_cmnd fcp_cmnd; | |
1531 | dma_addr_t crc_ctx_dma; | |
1532 | /* List of DMA context transfers */ | |
1533 | struct list_head dsd_list; | |
1534 | ||
1535 | /* This structure should not exceed 512 bytes */ | |
1536 | }; | |
1537 | ||
1538 | #define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun)) | |
1539 | #define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun)) | |
1540 | ||
1da177e4 LT |
1541 | /* |
1542 | * ISP queue - status entry structure definition. | |
1543 | */ | |
1544 | #define STATUS_TYPE 0x03 /* Status entry. */ | |
1545 | typedef struct { | |
1546 | uint8_t entry_type; /* Entry type. */ | |
1547 | uint8_t entry_count; /* Entry count. */ | |
1548 | uint8_t sys_define; /* System defined. */ | |
1549 | uint8_t entry_status; /* Entry Status. */ | |
1550 | uint32_t handle; /* System handle. */ | |
1551 | uint16_t scsi_status; /* SCSI status. */ | |
1552 | uint16_t comp_status; /* Completion status. */ | |
1553 | uint16_t state_flags; /* State flags. */ | |
1554 | uint16_t status_flags; /* Status flags. */ | |
1555 | uint16_t rsp_info_len; /* Response Info Length. */ | |
1556 | uint16_t req_sense_length; /* Request sense data length. */ | |
1557 | uint32_t residual_length; /* Residual transfer length. */ | |
1558 | uint8_t rsp_info[8]; /* FCP response information. */ | |
1559 | uint8_t req_sense_data[32]; /* Request sense data. */ | |
1560 | } sts_entry_t; | |
1561 | ||
1562 | /* | |
1563 | * Status entry entry status | |
1564 | */ | |
3d71644c | 1565 | #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */ |
1da177e4 LT |
1566 | #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */ |
1567 | #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */ | |
1568 | #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */ | |
1569 | #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */ | |
1570 | #define RF_BUSY BIT_1 /* Busy */ | |
3d71644c AV |
1571 | #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \ |
1572 | RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY) | |
1573 | #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \ | |
1574 | RF_INV_E_TYPE) | |
1da177e4 LT |
1575 | |
1576 | /* | |
1577 | * Status entry SCSI status bit definitions. | |
1578 | */ | |
1579 | #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/ | |
1580 | #define SS_RESIDUAL_UNDER BIT_11 | |
1581 | #define SS_RESIDUAL_OVER BIT_10 | |
1582 | #define SS_SENSE_LEN_VALID BIT_9 | |
1583 | #define SS_RESPONSE_INFO_LEN_VALID BIT_8 | |
1584 | ||
1585 | #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3) | |
1586 | #define SS_BUSY_CONDITION BIT_3 | |
1587 | #define SS_CONDITION_MET BIT_2 | |
1588 | #define SS_CHECK_CONDITION BIT_1 | |
1589 | ||
1590 | /* | |
1591 | * Status entry completion status | |
1592 | */ | |
1593 | #define CS_COMPLETE 0x0 /* No errors */ | |
1594 | #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */ | |
1595 | #define CS_DMA 0x2 /* A DMA direction error. */ | |
1596 | #define CS_TRANSPORT 0x3 /* Transport error. */ | |
1597 | #define CS_RESET 0x4 /* SCSI bus reset occurred */ | |
1598 | #define CS_ABORTED 0x5 /* System aborted command. */ | |
1599 | #define CS_TIMEOUT 0x6 /* Timeout error. */ | |
1600 | #define CS_DATA_OVERRUN 0x7 /* Data overrun. */ | |
bad75002 | 1601 | #define CS_DIF_ERROR 0xC /* DIF error detected */ |
1da177e4 LT |
1602 | |
1603 | #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */ | |
1604 | #define CS_QUEUE_FULL 0x1C /* Queue Full. */ | |
1605 | #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */ | |
1606 | /* (selection timeout) */ | |
1607 | #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */ | |
1608 | #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */ | |
1609 | #define CS_PORT_BUSY 0x2B /* Port Busy */ | |
1610 | #define CS_COMPLETE_CHKCOND 0x30 /* Error? */ | |
1611 | #define CS_BAD_PAYLOAD 0x80 /* Driver defined */ | |
1612 | #define CS_UNKNOWN 0x81 /* Driver defined */ | |
1613 | #define CS_RETRY 0x82 /* Driver defined */ | |
1614 | #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */ | |
1615 | ||
a9b6f722 SK |
1616 | #define CS_BIDIR_RD_OVERRUN 0x700 |
1617 | #define CS_BIDIR_RD_WR_OVERRUN 0x707 | |
1618 | #define CS_BIDIR_RD_OVERRUN_WR_UNDERRUN 0x715 | |
1619 | #define CS_BIDIR_RD_UNDERRUN 0x1500 | |
1620 | #define CS_BIDIR_RD_UNDERRUN_WR_OVERRUN 0x1507 | |
1621 | #define CS_BIDIR_RD_WR_UNDERRUN 0x1515 | |
1622 | #define CS_BIDIR_DMA 0x200 | |
1da177e4 LT |
1623 | /* |
1624 | * Status entry status flags | |
1625 | */ | |
1626 | #define SF_ABTS_TERMINATED BIT_10 | |
1627 | #define SF_LOGOUT_SENT BIT_13 | |
1628 | ||
1629 | /* | |
1630 | * ISP queue - status continuation entry structure definition. | |
1631 | */ | |
1632 | #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */ | |
1633 | typedef struct { | |
1634 | uint8_t entry_type; /* Entry type. */ | |
1635 | uint8_t entry_count; /* Entry count. */ | |
1636 | uint8_t sys_define; /* System defined. */ | |
1637 | uint8_t entry_status; /* Entry Status. */ | |
1638 | uint8_t data[60]; /* data */ | |
1639 | } sts_cont_entry_t; | |
1640 | ||
1641 | /* | |
1642 | * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles) | |
1643 | * structure definition. | |
1644 | */ | |
1645 | #define STATUS_TYPE_21 0x21 /* Status entry. */ | |
1646 | typedef struct { | |
1647 | uint8_t entry_type; /* Entry type. */ | |
1648 | uint8_t entry_count; /* Entry count. */ | |
1649 | uint8_t handle_count; /* Handle count. */ | |
1650 | uint8_t entry_status; /* Entry Status. */ | |
1651 | uint32_t handle[15]; /* System handles. */ | |
1652 | } sts21_entry_t; | |
1653 | ||
1654 | /* | |
1655 | * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles) | |
1656 | * structure definition. | |
1657 | */ | |
1658 | #define STATUS_TYPE_22 0x22 /* Status entry. */ | |
1659 | typedef struct { | |
1660 | uint8_t entry_type; /* Entry type. */ | |
1661 | uint8_t entry_count; /* Entry count. */ | |
1662 | uint8_t handle_count; /* Handle count. */ | |
1663 | uint8_t entry_status; /* Entry Status. */ | |
1664 | uint16_t handle[30]; /* System handles. */ | |
1665 | } sts22_entry_t; | |
1666 | ||
1667 | /* | |
1668 | * ISP queue - marker entry structure definition. | |
1669 | */ | |
1670 | #define MARKER_TYPE 0x04 /* Marker entry. */ | |
1671 | typedef struct { | |
1672 | uint8_t entry_type; /* Entry type. */ | |
1673 | uint8_t entry_count; /* Entry count. */ | |
1674 | uint8_t handle_count; /* Handle count. */ | |
1675 | uint8_t entry_status; /* Entry Status. */ | |
1676 | uint32_t sys_define_2; /* System defined. */ | |
1677 | target_id_t target; /* SCSI ID */ | |
1678 | uint8_t modifier; /* Modifier (7-0). */ | |
1679 | #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */ | |
1680 | #define MK_SYNC_ID 1 /* Synchronize ID */ | |
1681 | #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */ | |
1682 | #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */ | |
1683 | /* clear port changed, */ | |
1684 | /* use sequence number. */ | |
1685 | uint8_t reserved_1; | |
1686 | uint16_t sequence_number; /* Sequence number of event */ | |
1687 | uint16_t lun; /* SCSI LUN */ | |
1688 | uint8_t reserved_2[48]; | |
1689 | } mrk_entry_t; | |
1690 | ||
1691 | /* | |
1692 | * ISP queue - Management Server entry structure definition. | |
1693 | */ | |
1694 | #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */ | |
1695 | typedef struct { | |
1696 | uint8_t entry_type; /* Entry type. */ | |
1697 | uint8_t entry_count; /* Entry count. */ | |
1698 | uint8_t handle_count; /* Handle count. */ | |
1699 | uint8_t entry_status; /* Entry Status. */ | |
1700 | uint32_t handle1; /* System handle. */ | |
1701 | target_id_t loop_id; | |
1702 | uint16_t status; | |
1703 | uint16_t control_flags; /* Control flags. */ | |
1704 | uint16_t reserved2; | |
1705 | uint16_t timeout; | |
1706 | uint16_t cmd_dsd_count; | |
1707 | uint16_t total_dsd_count; | |
1708 | uint8_t type; | |
1709 | uint8_t r_ctl; | |
1710 | uint16_t rx_id; | |
1711 | uint16_t reserved3; | |
1712 | uint32_t handle2; | |
1713 | uint32_t rsp_bytecount; | |
1714 | uint32_t req_bytecount; | |
1715 | uint32_t dseg_req_address[2]; /* Data segment 0 address. */ | |
1716 | uint32_t dseg_req_length; /* Data segment 0 length. */ | |
1717 | uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */ | |
1718 | uint32_t dseg_rsp_length; /* Data segment 1 length. */ | |
1719 | } ms_iocb_entry_t; | |
1720 | ||
1721 | ||
1722 | /* | |
1723 | * ISP queue - Mailbox Command entry structure definition. | |
1724 | */ | |
1725 | #define MBX_IOCB_TYPE 0x39 | |
1726 | struct mbx_entry { | |
1727 | uint8_t entry_type; | |
1728 | uint8_t entry_count; | |
1729 | uint8_t sys_define1; | |
1730 | /* Use sys_define1 for source type */ | |
1731 | #define SOURCE_SCSI 0x00 | |
1732 | #define SOURCE_IP 0x01 | |
1733 | #define SOURCE_VI 0x02 | |
1734 | #define SOURCE_SCTP 0x03 | |
1735 | #define SOURCE_MP 0x04 | |
1736 | #define SOURCE_MPIOCTL 0x05 | |
1737 | #define SOURCE_ASYNC_IOCB 0x07 | |
1738 | ||
1739 | uint8_t entry_status; | |
1740 | ||
1741 | uint32_t handle; | |
1742 | target_id_t loop_id; | |
1743 | ||
1744 | uint16_t status; | |
1745 | uint16_t state_flags; | |
1746 | uint16_t status_flags; | |
1747 | ||
1748 | uint32_t sys_define2[2]; | |
1749 | ||
1750 | uint16_t mb0; | |
1751 | uint16_t mb1; | |
1752 | uint16_t mb2; | |
1753 | uint16_t mb3; | |
1754 | uint16_t mb6; | |
1755 | uint16_t mb7; | |
1756 | uint16_t mb9; | |
1757 | uint16_t mb10; | |
1758 | uint32_t reserved_2[2]; | |
1759 | uint8_t node_name[WWN_SIZE]; | |
1760 | uint8_t port_name[WWN_SIZE]; | |
1761 | }; | |
1762 | ||
1763 | /* | |
1764 | * ISP request and response queue entry sizes | |
1765 | */ | |
1766 | #define RESPONSE_ENTRY_SIZE (sizeof(response_t)) | |
1767 | #define REQUEST_ENTRY_SIZE (sizeof(request_t)) | |
1768 | ||
1769 | ||
1770 | /* | |
1771 | * 24 bit port ID type definition. | |
1772 | */ | |
1773 | typedef union { | |
1774 | uint32_t b24 : 24; | |
1775 | ||
1776 | struct { | |
b889d531 MN |
1777 | #ifdef __BIG_ENDIAN |
1778 | uint8_t domain; | |
1779 | uint8_t area; | |
1780 | uint8_t al_pa; | |
0fd30f77 | 1781 | #elif defined(__LITTLE_ENDIAN) |
1da177e4 LT |
1782 | uint8_t al_pa; |
1783 | uint8_t area; | |
1784 | uint8_t domain; | |
b889d531 MN |
1785 | #else |
1786 | #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!" | |
1787 | #endif | |
1da177e4 LT |
1788 | uint8_t rsvd_1; |
1789 | } b; | |
1790 | } port_id_t; | |
1791 | #define INVALID_PORT_ID 0xFFFFFF | |
1792 | ||
1793 | /* | |
1794 | * Switch info gathering structure. | |
1795 | */ | |
1796 | typedef struct { | |
1797 | port_id_t d_id; | |
1798 | uint8_t node_name[WWN_SIZE]; | |
1799 | uint8_t port_name[WWN_SIZE]; | |
d8b45213 | 1800 | uint8_t fabric_port_name[WWN_SIZE]; |
d8b45213 | 1801 | uint16_t fp_speed; |
e8c72ba5 | 1802 | uint8_t fc4_type; |
1da177e4 LT |
1803 | } sw_info_t; |
1804 | ||
e8c72ba5 CD |
1805 | /* FCP-4 types */ |
1806 | #define FC4_TYPE_FCP_SCSI 0x08 | |
1807 | #define FC4_TYPE_OTHER 0x0 | |
1808 | #define FC4_TYPE_UNKNOWN 0xff | |
1809 | ||
1da177e4 LT |
1810 | /* |
1811 | * Fibre channel port type. | |
1812 | */ | |
1813 | typedef enum { | |
1814 | FCT_UNKNOWN, | |
1815 | FCT_RSCN, | |
1816 | FCT_SWITCH, | |
1817 | FCT_BROADCAST, | |
1818 | FCT_INITIATOR, | |
1819 | FCT_TARGET | |
1820 | } fc_port_type_t; | |
1821 | ||
1822 | /* | |
1823 | * Fibre channel port structure. | |
1824 | */ | |
1825 | typedef struct fc_port { | |
1826 | struct list_head list; | |
7b867cf7 | 1827 | struct scsi_qla_host *vha; |
1da177e4 LT |
1828 | |
1829 | uint8_t node_name[WWN_SIZE]; | |
1830 | uint8_t port_name[WWN_SIZE]; | |
1831 | port_id_t d_id; | |
1832 | uint16_t loop_id; | |
1833 | uint16_t old_loop_id; | |
1834 | ||
09ff701a SR |
1835 | uint8_t fcp_prio; |
1836 | ||
d8b45213 AV |
1837 | uint8_t fabric_port_name[WWN_SIZE]; |
1838 | uint16_t fp_speed; | |
1839 | ||
1da177e4 LT |
1840 | fc_port_type_t port_type; |
1841 | ||
1842 | atomic_t state; | |
1843 | uint32_t flags; | |
1844 | ||
1da177e4 | 1845 | int login_retry; |
1da177e4 | 1846 | |
d97994dc | 1847 | struct fc_rport *rport, *drport; |
ad3e0eda | 1848 | u32 supported_classes; |
df7baa50 | 1849 | |
e8c72ba5 | 1850 | uint8_t fc4_type; |
b3b02e6e | 1851 | uint8_t scan_state; |
1da177e4 LT |
1852 | } fc_port_t; |
1853 | ||
1854 | /* | |
1855 | * Fibre channel port/lun states. | |
1856 | */ | |
1857 | #define FCS_UNCONFIGURED 1 | |
1858 | #define FCS_DEVICE_DEAD 2 | |
1859 | #define FCS_DEVICE_LOST 3 | |
1860 | #define FCS_ONLINE 4 | |
1da177e4 | 1861 | |
ec426e10 CD |
1862 | static const char * const port_state_str[] = { |
1863 | "Unknown", | |
1864 | "UNCONFIGURED", | |
1865 | "DEAD", | |
1866 | "LOST", | |
1867 | "ONLINE" | |
1868 | }; | |
1869 | ||
1da177e4 LT |
1870 | /* |
1871 | * FC port flags. | |
1872 | */ | |
1873 | #define FCF_FABRIC_DEVICE BIT_0 | |
1874 | #define FCF_LOGIN_NEEDED BIT_1 | |
f08b7251 | 1875 | #define FCF_FCP2_DEVICE BIT_2 |
5ff1d584 | 1876 | #define FCF_ASYNC_SENT BIT_3 |
2d70c103 | 1877 | #define FCF_CONF_COMP_SUPPORTED BIT_4 |
1da177e4 LT |
1878 | |
1879 | /* No loop ID flag. */ | |
1880 | #define FC_NO_LOOP_ID 0x1000 | |
1881 | ||
1da177e4 LT |
1882 | /* |
1883 | * FC-CT interface | |
1884 | * | |
1885 | * NOTE: All structures are big-endian in form. | |
1886 | */ | |
1887 | ||
1888 | #define CT_REJECT_RESPONSE 0x8001 | |
1889 | #define CT_ACCEPT_RESPONSE 0x8002 | |
4346b149 | 1890 | #define CT_REASON_INVALID_COMMAND_CODE 0x01 |
cca5335c | 1891 | #define CT_REASON_CANNOT_PERFORM 0x09 |
3fe7cfb9 | 1892 | #define CT_REASON_COMMAND_UNSUPPORTED 0x0b |
cca5335c | 1893 | #define CT_EXPL_ALREADY_REGISTERED 0x10 |
1da177e4 LT |
1894 | |
1895 | #define NS_N_PORT_TYPE 0x01 | |
1896 | #define NS_NL_PORT_TYPE 0x02 | |
1897 | #define NS_NX_PORT_TYPE 0x7F | |
1898 | ||
1899 | #define GA_NXT_CMD 0x100 | |
1900 | #define GA_NXT_REQ_SIZE (16 + 4) | |
1901 | #define GA_NXT_RSP_SIZE (16 + 620) | |
1902 | ||
1903 | #define GID_PT_CMD 0x1A1 | |
1904 | #define GID_PT_REQ_SIZE (16 + 4) | |
1da177e4 LT |
1905 | |
1906 | #define GPN_ID_CMD 0x112 | |
1907 | #define GPN_ID_REQ_SIZE (16 + 4) | |
1908 | #define GPN_ID_RSP_SIZE (16 + 8) | |
1909 | ||
1910 | #define GNN_ID_CMD 0x113 | |
1911 | #define GNN_ID_REQ_SIZE (16 + 4) | |
1912 | #define GNN_ID_RSP_SIZE (16 + 8) | |
1913 | ||
1914 | #define GFT_ID_CMD 0x117 | |
1915 | #define GFT_ID_REQ_SIZE (16 + 4) | |
1916 | #define GFT_ID_RSP_SIZE (16 + 32) | |
1917 | ||
1918 | #define RFT_ID_CMD 0x217 | |
1919 | #define RFT_ID_REQ_SIZE (16 + 4 + 32) | |
1920 | #define RFT_ID_RSP_SIZE 16 | |
1921 | ||
1922 | #define RFF_ID_CMD 0x21F | |
1923 | #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1) | |
1924 | #define RFF_ID_RSP_SIZE 16 | |
1925 | ||
1926 | #define RNN_ID_CMD 0x213 | |
1927 | #define RNN_ID_REQ_SIZE (16 + 4 + 8) | |
1928 | #define RNN_ID_RSP_SIZE 16 | |
1929 | ||
1930 | #define RSNN_NN_CMD 0x239 | |
1931 | #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255) | |
1932 | #define RSNN_NN_RSP_SIZE 16 | |
1933 | ||
d8b45213 AV |
1934 | #define GFPN_ID_CMD 0x11C |
1935 | #define GFPN_ID_REQ_SIZE (16 + 4) | |
1936 | #define GFPN_ID_RSP_SIZE (16 + 8) | |
1937 | ||
1938 | #define GPSC_CMD 0x127 | |
1939 | #define GPSC_REQ_SIZE (16 + 8) | |
1940 | #define GPSC_RSP_SIZE (16 + 2 + 2) | |
1941 | ||
e8c72ba5 CD |
1942 | #define GFF_ID_CMD 0x011F |
1943 | #define GFF_ID_REQ_SIZE (16 + 4) | |
1944 | #define GFF_ID_RSP_SIZE (16 + 128) | |
d8b45213 | 1945 | |
cca5335c AV |
1946 | /* |
1947 | * HBA attribute types. | |
1948 | */ | |
1949 | #define FDMI_HBA_ATTR_COUNT 9 | |
1950 | #define FDMI_HBA_NODE_NAME 1 | |
1951 | #define FDMI_HBA_MANUFACTURER 2 | |
1952 | #define FDMI_HBA_SERIAL_NUMBER 3 | |
1953 | #define FDMI_HBA_MODEL 4 | |
1954 | #define FDMI_HBA_MODEL_DESCRIPTION 5 | |
1955 | #define FDMI_HBA_HARDWARE_VERSION 6 | |
1956 | #define FDMI_HBA_DRIVER_VERSION 7 | |
1957 | #define FDMI_HBA_OPTION_ROM_VERSION 8 | |
1958 | #define FDMI_HBA_FIRMWARE_VERSION 9 | |
1959 | #define FDMI_HBA_OS_NAME_AND_VERSION 0xa | |
1960 | #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb | |
1961 | ||
1962 | struct ct_fdmi_hba_attr { | |
1963 | uint16_t type; | |
1964 | uint16_t len; | |
1965 | union { | |
1966 | uint8_t node_name[WWN_SIZE]; | |
1967 | uint8_t manufacturer[32]; | |
1968 | uint8_t serial_num[8]; | |
1969 | uint8_t model[16]; | |
1970 | uint8_t model_desc[80]; | |
1971 | uint8_t hw_version[16]; | |
1972 | uint8_t driver_version[32]; | |
1973 | uint8_t orom_version[16]; | |
1974 | uint8_t fw_version[16]; | |
1975 | uint8_t os_version[128]; | |
1976 | uint8_t max_ct_len[4]; | |
1977 | } a; | |
1978 | }; | |
1979 | ||
1980 | struct ct_fdmi_hba_attributes { | |
1981 | uint32_t count; | |
1982 | struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT]; | |
1983 | }; | |
1984 | ||
1985 | /* | |
1986 | * Port attribute types. | |
1987 | */ | |
8a85e171 | 1988 | #define FDMI_PORT_ATTR_COUNT 6 |
cca5335c AV |
1989 | #define FDMI_PORT_FC4_TYPES 1 |
1990 | #define FDMI_PORT_SUPPORT_SPEED 2 | |
1991 | #define FDMI_PORT_CURRENT_SPEED 3 | |
1992 | #define FDMI_PORT_MAX_FRAME_SIZE 4 | |
1993 | #define FDMI_PORT_OS_DEVICE_NAME 5 | |
1994 | #define FDMI_PORT_HOST_NAME 6 | |
1995 | ||
5881569b AV |
1996 | #define FDMI_PORT_SPEED_1GB 0x1 |
1997 | #define FDMI_PORT_SPEED_2GB 0x2 | |
1998 | #define FDMI_PORT_SPEED_10GB 0x4 | |
1999 | #define FDMI_PORT_SPEED_4GB 0x8 | |
2000 | #define FDMI_PORT_SPEED_8GB 0x10 | |
2001 | #define FDMI_PORT_SPEED_16GB 0x20 | |
2002 | #define FDMI_PORT_SPEED_UNKNOWN 0x8000 | |
2003 | ||
cca5335c AV |
2004 | struct ct_fdmi_port_attr { |
2005 | uint16_t type; | |
2006 | uint16_t len; | |
2007 | union { | |
2008 | uint8_t fc4_types[32]; | |
2009 | uint32_t sup_speed; | |
2010 | uint32_t cur_speed; | |
2011 | uint32_t max_frame_size; | |
2012 | uint8_t os_dev_name[32]; | |
2013 | uint8_t host_name[32]; | |
2014 | } a; | |
2015 | }; | |
2016 | ||
2017 | /* | |
2018 | * Port Attribute Block. | |
2019 | */ | |
2020 | struct ct_fdmi_port_attributes { | |
2021 | uint32_t count; | |
2022 | struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT]; | |
2023 | }; | |
2024 | ||
2025 | /* FDMI definitions. */ | |
2026 | #define GRHL_CMD 0x100 | |
2027 | #define GHAT_CMD 0x101 | |
2028 | #define GRPL_CMD 0x102 | |
2029 | #define GPAT_CMD 0x110 | |
2030 | ||
2031 | #define RHBA_CMD 0x200 | |
2032 | #define RHBA_RSP_SIZE 16 | |
2033 | ||
2034 | #define RHAT_CMD 0x201 | |
2035 | #define RPRT_CMD 0x210 | |
2036 | ||
2037 | #define RPA_CMD 0x211 | |
2038 | #define RPA_RSP_SIZE 16 | |
2039 | ||
2040 | #define DHBA_CMD 0x300 | |
2041 | #define DHBA_REQ_SIZE (16 + 8) | |
2042 | #define DHBA_RSP_SIZE 16 | |
2043 | ||
2044 | #define DHAT_CMD 0x301 | |
2045 | #define DPRT_CMD 0x310 | |
2046 | #define DPA_CMD 0x311 | |
2047 | ||
1da177e4 LT |
2048 | /* CT command header -- request/response common fields */ |
2049 | struct ct_cmd_hdr { | |
2050 | uint8_t revision; | |
2051 | uint8_t in_id[3]; | |
2052 | uint8_t gs_type; | |
2053 | uint8_t gs_subtype; | |
2054 | uint8_t options; | |
2055 | uint8_t reserved; | |
2056 | }; | |
2057 | ||
2058 | /* CT command request */ | |
2059 | struct ct_sns_req { | |
2060 | struct ct_cmd_hdr header; | |
2061 | uint16_t command; | |
2062 | uint16_t max_rsp_size; | |
2063 | uint8_t fragment_id; | |
2064 | uint8_t reserved[3]; | |
2065 | ||
2066 | union { | |
d8b45213 | 2067 | /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */ |
1da177e4 LT |
2068 | struct { |
2069 | uint8_t reserved; | |
2070 | uint8_t port_id[3]; | |
2071 | } port_id; | |
2072 | ||
2073 | struct { | |
2074 | uint8_t port_type; | |
2075 | uint8_t domain; | |
2076 | uint8_t area; | |
2077 | uint8_t reserved; | |
2078 | } gid_pt; | |
2079 | ||
2080 | struct { | |
2081 | uint8_t reserved; | |
2082 | uint8_t port_id[3]; | |
2083 | uint8_t fc4_types[32]; | |
2084 | } rft_id; | |
2085 | ||
2086 | struct { | |
2087 | uint8_t reserved; | |
2088 | uint8_t port_id[3]; | |
2089 | uint16_t reserved2; | |
2090 | uint8_t fc4_feature; | |
2091 | uint8_t fc4_type; | |
2092 | } rff_id; | |
2093 | ||
2094 | struct { | |
2095 | uint8_t reserved; | |
2096 | uint8_t port_id[3]; | |
2097 | uint8_t node_name[8]; | |
2098 | } rnn_id; | |
2099 | ||
2100 | struct { | |
2101 | uint8_t node_name[8]; | |
2102 | uint8_t name_len; | |
2103 | uint8_t sym_node_name[255]; | |
2104 | } rsnn_nn; | |
cca5335c AV |
2105 | |
2106 | struct { | |
2107 | uint8_t hba_indentifier[8]; | |
2108 | } ghat; | |
2109 | ||
2110 | struct { | |
2111 | uint8_t hba_identifier[8]; | |
2112 | uint32_t entry_count; | |
2113 | uint8_t port_name[8]; | |
2114 | struct ct_fdmi_hba_attributes attrs; | |
2115 | } rhba; | |
2116 | ||
2117 | struct { | |
2118 | uint8_t hba_identifier[8]; | |
2119 | struct ct_fdmi_hba_attributes attrs; | |
2120 | } rhat; | |
2121 | ||
2122 | struct { | |
2123 | uint8_t port_name[8]; | |
2124 | struct ct_fdmi_port_attributes attrs; | |
2125 | } rpa; | |
2126 | ||
2127 | struct { | |
2128 | uint8_t port_name[8]; | |
2129 | } dhba; | |
2130 | ||
2131 | struct { | |
2132 | uint8_t port_name[8]; | |
2133 | } dhat; | |
2134 | ||
2135 | struct { | |
2136 | uint8_t port_name[8]; | |
2137 | } dprt; | |
2138 | ||
2139 | struct { | |
2140 | uint8_t port_name[8]; | |
2141 | } dpa; | |
d8b45213 AV |
2142 | |
2143 | struct { | |
2144 | uint8_t port_name[8]; | |
2145 | } gpsc; | |
e8c72ba5 CD |
2146 | |
2147 | struct { | |
2148 | uint8_t reserved; | |
2149 | uint8_t port_name[3]; | |
2150 | } gff_id; | |
1da177e4 LT |
2151 | } req; |
2152 | }; | |
2153 | ||
2154 | /* CT command response header */ | |
2155 | struct ct_rsp_hdr { | |
2156 | struct ct_cmd_hdr header; | |
2157 | uint16_t response; | |
2158 | uint16_t residual; | |
2159 | uint8_t fragment_id; | |
2160 | uint8_t reason_code; | |
2161 | uint8_t explanation_code; | |
2162 | uint8_t vendor_unique; | |
2163 | }; | |
2164 | ||
2165 | struct ct_sns_gid_pt_data { | |
2166 | uint8_t control_byte; | |
2167 | uint8_t port_id[3]; | |
2168 | }; | |
2169 | ||
2170 | struct ct_sns_rsp { | |
2171 | struct ct_rsp_hdr header; | |
2172 | ||
2173 | union { | |
2174 | struct { | |
2175 | uint8_t port_type; | |
2176 | uint8_t port_id[3]; | |
2177 | uint8_t port_name[8]; | |
2178 | uint8_t sym_port_name_len; | |
2179 | uint8_t sym_port_name[255]; | |
2180 | uint8_t node_name[8]; | |
2181 | uint8_t sym_node_name_len; | |
2182 | uint8_t sym_node_name[255]; | |
2183 | uint8_t init_proc_assoc[8]; | |
2184 | uint8_t node_ip_addr[16]; | |
2185 | uint8_t class_of_service[4]; | |
2186 | uint8_t fc4_types[32]; | |
2187 | uint8_t ip_address[16]; | |
2188 | uint8_t fabric_port_name[8]; | |
2189 | uint8_t reserved; | |
2190 | uint8_t hard_address[3]; | |
2191 | } ga_nxt; | |
2192 | ||
2193 | struct { | |
642ef983 CD |
2194 | /* Assume the largest number of targets for the union */ |
2195 | struct ct_sns_gid_pt_data | |
2196 | entries[MAX_FIBRE_DEVICES_MAX]; | |
1da177e4 LT |
2197 | } gid_pt; |
2198 | ||
2199 | struct { | |
2200 | uint8_t port_name[8]; | |
2201 | } gpn_id; | |
2202 | ||
2203 | struct { | |
2204 | uint8_t node_name[8]; | |
2205 | } gnn_id; | |
2206 | ||
2207 | struct { | |
2208 | uint8_t fc4_types[32]; | |
2209 | } gft_id; | |
cca5335c AV |
2210 | |
2211 | struct { | |
2212 | uint32_t entry_count; | |
2213 | uint8_t port_name[8]; | |
2214 | struct ct_fdmi_hba_attributes attrs; | |
2215 | } ghat; | |
d8b45213 AV |
2216 | |
2217 | struct { | |
2218 | uint8_t port_name[8]; | |
2219 | } gfpn_id; | |
2220 | ||
2221 | struct { | |
2222 | uint16_t speeds; | |
2223 | uint16_t speed; | |
2224 | } gpsc; | |
e8c72ba5 CD |
2225 | |
2226 | #define GFF_FCP_SCSI_OFFSET 7 | |
2227 | struct { | |
2228 | uint8_t fc4_features[128]; | |
2229 | } gff_id; | |
1da177e4 LT |
2230 | } rsp; |
2231 | }; | |
2232 | ||
2233 | struct ct_sns_pkt { | |
2234 | union { | |
2235 | struct ct_sns_req req; | |
2236 | struct ct_sns_rsp rsp; | |
2237 | } p; | |
2238 | }; | |
2239 | ||
2240 | /* | |
25985edc | 2241 | * SNS command structures -- for 2200 compatibility. |
1da177e4 LT |
2242 | */ |
2243 | #define RFT_ID_SNS_SCMD_LEN 22 | |
2244 | #define RFT_ID_SNS_CMD_SIZE 60 | |
2245 | #define RFT_ID_SNS_DATA_SIZE 16 | |
2246 | ||
2247 | #define RNN_ID_SNS_SCMD_LEN 10 | |
2248 | #define RNN_ID_SNS_CMD_SIZE 36 | |
2249 | #define RNN_ID_SNS_DATA_SIZE 16 | |
2250 | ||
2251 | #define GA_NXT_SNS_SCMD_LEN 6 | |
2252 | #define GA_NXT_SNS_CMD_SIZE 28 | |
2253 | #define GA_NXT_SNS_DATA_SIZE (620 + 16) | |
2254 | ||
2255 | #define GID_PT_SNS_SCMD_LEN 6 | |
2256 | #define GID_PT_SNS_CMD_SIZE 28 | |
642ef983 CD |
2257 | /* |
2258 | * Assume MAX_FIBRE_DEVICES_2100 as these defines are only used with older | |
2259 | * adapters. | |
2260 | */ | |
2261 | #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16) | |
1da177e4 LT |
2262 | |
2263 | #define GPN_ID_SNS_SCMD_LEN 6 | |
2264 | #define GPN_ID_SNS_CMD_SIZE 28 | |
2265 | #define GPN_ID_SNS_DATA_SIZE (8 + 16) | |
2266 | ||
2267 | #define GNN_ID_SNS_SCMD_LEN 6 | |
2268 | #define GNN_ID_SNS_CMD_SIZE 28 | |
2269 | #define GNN_ID_SNS_DATA_SIZE (8 + 16) | |
2270 | ||
2271 | struct sns_cmd_pkt { | |
2272 | union { | |
2273 | struct { | |
2274 | uint16_t buffer_length; | |
2275 | uint16_t reserved_1; | |
2276 | uint32_t buffer_address[2]; | |
2277 | uint16_t subcommand_length; | |
2278 | uint16_t reserved_2; | |
2279 | uint16_t subcommand; | |
2280 | uint16_t size; | |
2281 | uint32_t reserved_3; | |
2282 | uint8_t param[36]; | |
2283 | } cmd; | |
2284 | ||
2285 | uint8_t rft_data[RFT_ID_SNS_DATA_SIZE]; | |
2286 | uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE]; | |
2287 | uint8_t gan_data[GA_NXT_SNS_DATA_SIZE]; | |
2288 | uint8_t gid_data[GID_PT_SNS_DATA_SIZE]; | |
2289 | uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE]; | |
2290 | uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE]; | |
2291 | } p; | |
2292 | }; | |
2293 | ||
5433383e AV |
2294 | struct fw_blob { |
2295 | char *name; | |
2296 | uint32_t segs[4]; | |
2297 | const struct firmware *fw; | |
2298 | }; | |
2299 | ||
1da177e4 LT |
2300 | /* Return data from MBC_GET_ID_LIST call. */ |
2301 | struct gid_list_info { | |
2302 | uint8_t al_pa; | |
2303 | uint8_t area; | |
fa2a1ce5 | 2304 | uint8_t domain; |
1da177e4 LT |
2305 | uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */ |
2306 | uint16_t loop_id; /* ISP23XX -- 6 bytes. */ | |
3d71644c | 2307 | uint16_t reserved_1; /* ISP24XX -- 8 bytes. */ |
1da177e4 | 2308 | }; |
1da177e4 | 2309 | |
2c3dfe3f SJ |
2310 | /* NPIV */ |
2311 | typedef struct vport_info { | |
2312 | uint8_t port_name[WWN_SIZE]; | |
2313 | uint8_t node_name[WWN_SIZE]; | |
2314 | int vp_id; | |
2315 | uint16_t loop_id; | |
2316 | unsigned long host_no; | |
2317 | uint8_t port_id[3]; | |
2318 | int loop_state; | |
2319 | } vport_info_t; | |
2320 | ||
2321 | typedef struct vport_params { | |
2322 | uint8_t port_name[WWN_SIZE]; | |
2323 | uint8_t node_name[WWN_SIZE]; | |
2324 | uint32_t options; | |
2325 | #define VP_OPTS_RETRY_ENABLE BIT_0 | |
2326 | #define VP_OPTS_VP_DISABLE BIT_1 | |
2327 | } vport_params_t; | |
2328 | ||
2329 | /* NPIV - return codes of VP create and modify */ | |
2330 | #define VP_RET_CODE_OK 0 | |
2331 | #define VP_RET_CODE_FATAL 1 | |
2332 | #define VP_RET_CODE_WRONG_ID 2 | |
2333 | #define VP_RET_CODE_WWPN 3 | |
2334 | #define VP_RET_CODE_RESOURCES 4 | |
2335 | #define VP_RET_CODE_NO_MEM 5 | |
2336 | #define VP_RET_CODE_NOT_FOUND 6 | |
2337 | ||
7b867cf7 | 2338 | struct qla_hw_data; |
2afa19a9 | 2339 | struct rsp_que; |
abbd8870 AV |
2340 | /* |
2341 | * ISP operations | |
2342 | */ | |
2343 | struct isp_operations { | |
2344 | ||
2345 | int (*pci_config) (struct scsi_qla_host *); | |
2346 | void (*reset_chip) (struct scsi_qla_host *); | |
2347 | int (*chip_diag) (struct scsi_qla_host *); | |
2348 | void (*config_rings) (struct scsi_qla_host *); | |
2349 | void (*reset_adapter) (struct scsi_qla_host *); | |
2350 | int (*nvram_config) (struct scsi_qla_host *); | |
2351 | void (*update_fw_options) (struct scsi_qla_host *); | |
2352 | int (*load_risc) (struct scsi_qla_host *, uint32_t *); | |
2353 | ||
2354 | char * (*pci_info_str) (struct scsi_qla_host *, char *); | |
2355 | char * (*fw_version_str) (struct scsi_qla_host *, char *); | |
2356 | ||
7d12e780 | 2357 | irq_handler_t intr_handler; |
7b867cf7 AC |
2358 | void (*enable_intrs) (struct qla_hw_data *); |
2359 | void (*disable_intrs) (struct qla_hw_data *); | |
abbd8870 | 2360 | |
2afa19a9 AC |
2361 | int (*abort_command) (srb_t *); |
2362 | int (*target_reset) (struct fc_port *, unsigned int, int); | |
2363 | int (*lun_reset) (struct fc_port *, unsigned int, int); | |
abbd8870 AV |
2364 | int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t, |
2365 | uint8_t, uint8_t, uint16_t *, uint8_t); | |
1c7c6357 AV |
2366 | int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t, |
2367 | uint8_t, uint8_t); | |
abbd8870 AV |
2368 | |
2369 | uint16_t (*calc_req_entries) (uint16_t); | |
2370 | void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t); | |
8c958a99 | 2371 | void * (*prep_ms_iocb) (struct scsi_qla_host *, uint32_t, uint32_t); |
cca5335c AV |
2372 | void * (*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t, |
2373 | uint32_t); | |
abbd8870 AV |
2374 | |
2375 | uint8_t * (*read_nvram) (struct scsi_qla_host *, uint8_t *, | |
2376 | uint32_t, uint32_t); | |
2377 | int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t, | |
2378 | uint32_t); | |
2379 | ||
2380 | void (*fw_dump) (struct scsi_qla_host *, int); | |
f6df144c AV |
2381 | |
2382 | int (*beacon_on) (struct scsi_qla_host *); | |
2383 | int (*beacon_off) (struct scsi_qla_host *); | |
2384 | void (*beacon_blink) (struct scsi_qla_host *); | |
854165f4 AV |
2385 | |
2386 | uint8_t * (*read_optrom) (struct scsi_qla_host *, uint8_t *, | |
2387 | uint32_t, uint32_t); | |
2388 | int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t, | |
2389 | uint32_t); | |
30c47662 AV |
2390 | |
2391 | int (*get_flash_version) (struct scsi_qla_host *, void *); | |
7b867cf7 | 2392 | int (*start_scsi) (srb_t *); |
a9083016 | 2393 | int (*abort_isp) (struct scsi_qla_host *); |
706f457d | 2394 | int (*iospace_config)(struct qla_hw_data*); |
abbd8870 AV |
2395 | }; |
2396 | ||
a8488abe AV |
2397 | /* MSI-X Support *************************************************************/ |
2398 | ||
2399 | #define QLA_MSIX_CHIP_REV_24XX 3 | |
2400 | #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7) | |
2401 | #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1) | |
2402 | ||
2403 | #define QLA_MSIX_DEFAULT 0x00 | |
2404 | #define QLA_MSIX_RSP_Q 0x01 | |
2405 | ||
a8488abe AV |
2406 | #define QLA_MIDX_DEFAULT 0 |
2407 | #define QLA_MIDX_RSP_Q 1 | |
73208dfd | 2408 | #define QLA_PCI_MSIX_CONTROL 0xa2 |
6246b8a1 | 2409 | #define QLA_83XX_PCI_MSIX_CONTROL 0x92 |
a8488abe AV |
2410 | |
2411 | struct scsi_qla_host; | |
2412 | ||
2413 | struct qla_msix_entry { | |
2414 | int have_irq; | |
73208dfd AC |
2415 | uint32_t vector; |
2416 | uint16_t entry; | |
2417 | struct rsp_que *rsp; | |
a8488abe AV |
2418 | }; |
2419 | ||
2c3dfe3f SJ |
2420 | #define WATCH_INTERVAL 1 /* number of seconds */ |
2421 | ||
0971de7f AV |
2422 | /* Work events. */ |
2423 | enum qla_work_type { | |
2424 | QLA_EVT_AEN, | |
8a659571 | 2425 | QLA_EVT_IDC_ACK, |
ac280b67 AV |
2426 | QLA_EVT_ASYNC_LOGIN, |
2427 | QLA_EVT_ASYNC_LOGIN_DONE, | |
2428 | QLA_EVT_ASYNC_LOGOUT, | |
2429 | QLA_EVT_ASYNC_LOGOUT_DONE, | |
5ff1d584 AV |
2430 | QLA_EVT_ASYNC_ADISC, |
2431 | QLA_EVT_ASYNC_ADISC_DONE, | |
3420d36c | 2432 | QLA_EVT_UEVENT, |
0971de7f AV |
2433 | }; |
2434 | ||
2435 | ||
2436 | struct qla_work_evt { | |
2437 | struct list_head list; | |
2438 | enum qla_work_type type; | |
2439 | u32 flags; | |
2440 | #define QLA_EVT_FLAG_FREE 0x1 | |
2441 | ||
2442 | union { | |
2443 | struct { | |
2444 | enum fc_host_event_code code; | |
2445 | u32 data; | |
2446 | } aen; | |
8a659571 AV |
2447 | struct { |
2448 | #define QLA_IDC_ACK_REGS 7 | |
2449 | uint16_t mb[QLA_IDC_ACK_REGS]; | |
2450 | } idc_ack; | |
ac280b67 AV |
2451 | struct { |
2452 | struct fc_port *fcport; | |
2453 | #define QLA_LOGIO_LOGIN_RETRIED BIT_0 | |
2454 | u16 data[2]; | |
2455 | } logio; | |
3420d36c AV |
2456 | struct { |
2457 | u32 code; | |
2458 | #define QLA_UEVENT_CODE_FW_DUMP 0 | |
2459 | } uevent; | |
0971de7f AV |
2460 | } u; |
2461 | }; | |
2462 | ||
4d4df193 HK |
2463 | struct qla_chip_state_84xx { |
2464 | struct list_head list; | |
2465 | struct kref kref; | |
2466 | ||
2467 | void *bus; | |
2468 | spinlock_t access_lock; | |
2469 | struct mutex fw_update_mutex; | |
2470 | uint32_t fw_update; | |
2471 | uint32_t op_fw_version; | |
2472 | uint32_t op_fw_size; | |
2473 | uint32_t op_fw_seq_size; | |
2474 | uint32_t diag_fw_version; | |
2475 | uint32_t gold_fw_version; | |
2476 | }; | |
2477 | ||
e5f5f6f7 HZ |
2478 | struct qla_statistics { |
2479 | uint32_t total_isp_aborts; | |
49fd462a HZ |
2480 | uint64_t input_bytes; |
2481 | uint64_t output_bytes; | |
e5f5f6f7 HZ |
2482 | }; |
2483 | ||
a9b6f722 SK |
2484 | struct bidi_statistics { |
2485 | unsigned long long io_count; | |
2486 | unsigned long long transfer_bytes; | |
2487 | }; | |
2488 | ||
73208dfd AC |
2489 | /* Multi queue support */ |
2490 | #define MBC_INITIALIZE_MULTIQ 0x1f | |
2491 | #define QLA_QUE_PAGE 0X1000 | |
2492 | #define QLA_MQ_SIZE 32 | |
73208dfd AC |
2493 | #define QLA_MAX_QUEUES 256 |
2494 | #define ISP_QUE_REG(ha, id) \ | |
6246b8a1 | 2495 | ((ha->mqenable || IS_QLA83XX(ha)) ? \ |
fa492630 | 2496 | ((device_reg_t __iomem *)(ha->mqiobase) +\ |
73208dfd | 2497 | (QLA_QUE_PAGE * id)) :\ |
fa492630 | 2498 | ((device_reg_t __iomem *)(ha->iobase))) |
73208dfd AC |
2499 | #define QLA_REQ_QUE_ID(tag) \ |
2500 | ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0) | |
2501 | #define QLA_DEFAULT_QUE_QOS 5 | |
2502 | #define QLA_PRECONFIG_VPORTS 32 | |
2503 | #define QLA_MAX_VPORTS_QLA24XX 128 | |
2504 | #define QLA_MAX_VPORTS_QLA25XX 256 | |
7b867cf7 AC |
2505 | /* Response queue data structure */ |
2506 | struct rsp_que { | |
2507 | dma_addr_t dma; | |
2508 | response_t *ring; | |
2509 | response_t *ring_ptr; | |
08029990 AV |
2510 | uint32_t __iomem *rsp_q_in; /* FWI2-capable only. */ |
2511 | uint32_t __iomem *rsp_q_out; | |
7b867cf7 AC |
2512 | uint16_t ring_index; |
2513 | uint16_t out_ptr; | |
2514 | uint16_t length; | |
2515 | uint16_t options; | |
7b867cf7 | 2516 | uint16_t rid; |
73208dfd AC |
2517 | uint16_t id; |
2518 | uint16_t vp_idx; | |
7b867cf7 | 2519 | struct qla_hw_data *hw; |
73208dfd AC |
2520 | struct qla_msix_entry *msix; |
2521 | struct req_que *req; | |
2afa19a9 | 2522 | srb_t *status_srb; /* status continuation entry */ |
68ca949c | 2523 | struct work_struct q_work; |
7b867cf7 | 2524 | }; |
1da177e4 | 2525 | |
7b867cf7 AC |
2526 | /* Request queue data structure */ |
2527 | struct req_que { | |
2528 | dma_addr_t dma; | |
2529 | request_t *ring; | |
2530 | request_t *ring_ptr; | |
08029990 AV |
2531 | uint32_t __iomem *req_q_in; /* FWI2-capable only. */ |
2532 | uint32_t __iomem *req_q_out; | |
7b867cf7 AC |
2533 | uint16_t ring_index; |
2534 | uint16_t in_ptr; | |
2535 | uint16_t cnt; | |
2536 | uint16_t length; | |
2537 | uint16_t options; | |
2538 | uint16_t rid; | |
73208dfd | 2539 | uint16_t id; |
7b867cf7 AC |
2540 | uint16_t qos; |
2541 | uint16_t vp_idx; | |
73208dfd | 2542 | struct rsp_que *rsp; |
8d93f550 | 2543 | srb_t **outstanding_cmds; |
7b867cf7 | 2544 | uint32_t current_outstanding_cmd; |
8d93f550 | 2545 | uint16_t num_outstanding_cmds; |
3c290d0b | 2546 | #define MAX_Q_DEPTH 32 |
7b867cf7 AC |
2547 | int max_q_depth; |
2548 | }; | |
1da177e4 | 2549 | |
9a069e19 GM |
2550 | /* Place holder for FW buffer parameters */ |
2551 | struct qlfc_fw { | |
2552 | void *fw_buf; | |
2553 | dma_addr_t fw_dma; | |
2554 | uint32_t len; | |
2555 | }; | |
2556 | ||
2d70c103 NB |
2557 | struct qlt_hw_data { |
2558 | /* Protected by hw lock */ | |
2559 | uint32_t enable_class_2:1; | |
2560 | uint32_t enable_explicit_conf:1; | |
2561 | uint32_t ini_mode_force_reverse:1; | |
2562 | uint32_t node_name_set:1; | |
2563 | ||
2564 | dma_addr_t atio_dma; /* Physical address. */ | |
2565 | struct atio *atio_ring; /* Base virtual address */ | |
2566 | struct atio *atio_ring_ptr; /* Current address. */ | |
2567 | uint16_t atio_ring_index; /* Current index. */ | |
2568 | uint16_t atio_q_length; | |
aa230bc5 AE |
2569 | uint32_t __iomem *atio_q_in; |
2570 | uint32_t __iomem *atio_q_out; | |
2d70c103 NB |
2571 | |
2572 | void *target_lport_ptr; | |
2573 | struct qla_tgt_func_tmpl *tgt_ops; | |
2574 | struct qla_tgt *qla_tgt; | |
8d93f550 | 2575 | struct qla_tgt_cmd *cmds[DEFAULT_OUTSTANDING_COMMANDS]; |
2d70c103 NB |
2576 | uint16_t current_handle; |
2577 | ||
2578 | struct qla_tgt_vp_map *tgt_vp_map; | |
2579 | struct mutex tgt_mutex; | |
2580 | struct mutex tgt_host_action_mutex; | |
2581 | ||
2582 | int saved_set; | |
2583 | uint16_t saved_exchange_count; | |
2584 | uint32_t saved_firmware_options_1; | |
2585 | uint32_t saved_firmware_options_2; | |
2586 | uint32_t saved_firmware_options_3; | |
2587 | uint8_t saved_firmware_options[2]; | |
2588 | uint8_t saved_add_firmware_options[2]; | |
2589 | ||
2590 | uint8_t tgt_node_name[WWN_SIZE]; | |
2591 | }; | |
2592 | ||
7b867cf7 AC |
2593 | /* |
2594 | * Qlogic host adapter specific data structure. | |
2595 | */ | |
2596 | struct qla_hw_data { | |
2597 | struct pci_dev *pdev; | |
2598 | /* SRB cache. */ | |
2599 | #define SRB_MIN_REQ 128 | |
2600 | mempool_t *srb_mempool; | |
1da177e4 LT |
2601 | |
2602 | volatile struct { | |
1da177e4 LT |
2603 | uint32_t mbox_int :1; |
2604 | uint32_t mbox_busy :1; | |
1da177e4 LT |
2605 | uint32_t disable_risc_code_load :1; |
2606 | uint32_t enable_64bit_addressing :1; | |
2607 | uint32_t enable_lip_reset :1; | |
1da177e4 | 2608 | uint32_t enable_target_reset :1; |
7b867cf7 | 2609 | uint32_t enable_lip_full_login :1; |
1da177e4 | 2610 | uint32_t enable_led_scheme :1; |
7190575f | 2611 | |
3d71644c AV |
2612 | uint32_t msi_enabled :1; |
2613 | uint32_t msix_enabled :1; | |
d4c760c2 | 2614 | uint32_t disable_serdes :1; |
4346b149 | 2615 | uint32_t gpsc_supported :1; |
2c3dfe3f | 2616 | uint32_t npiv_supported :1; |
85880801 | 2617 | uint32_t pci_channel_io_perm_failure :1; |
df613b96 | 2618 | uint32_t fce_enabled :1; |
1d2874de | 2619 | uint32_t fac_supported :1; |
7190575f | 2620 | |
2533cf67 | 2621 | uint32_t chip_reset_done :1; |
e5b68a61 | 2622 | uint32_t port0 :1; |
cbc8eb67 | 2623 | uint32_t running_gold_fw :1; |
85880801 | 2624 | uint32_t eeh_busy :1; |
7163ea81 | 2625 | uint32_t cpu_affinity_enabled :1; |
3155754a | 2626 | uint32_t disable_msix_handshake :1; |
09ff701a | 2627 | uint32_t fcp_prio_enabled :1; |
7190575f | 2628 | uint32_t isp82xx_fw_hung:1; |
7d613ac6 | 2629 | uint32_t nic_core_hung:1; |
7190575f GM |
2630 | |
2631 | uint32_t quiesce_owner:1; | |
7d613ac6 SV |
2632 | uint32_t nic_core_reset_hdlr_active:1; |
2633 | uint32_t nic_core_reset_owner:1; | |
b6d0d9d5 | 2634 | uint32_t isp82xx_no_md_cap:1; |
2d70c103 | 2635 | uint32_t host_shutting_down:1; |
bf5b8ad7 CD |
2636 | uint32_t idc_compl_status:1; |
2637 | /* 32 bits */ | |
1da177e4 LT |
2638 | } flags; |
2639 | ||
fa2a1ce5 | 2640 | /* This spinlock is used to protect "io transactions", you must |
7b867cf7 AC |
2641 | * acquire it before doing any IO to the card, eg with RD_REG*() and |
2642 | * WRT_REG*() for the duration of your entire commandtransaction. | |
2643 | * | |
2644 | * This spinlock is of lower priority than the io request lock. | |
2645 | */ | |
1da177e4 | 2646 | |
7b867cf7 | 2647 | spinlock_t hardware_lock ____cacheline_aligned; |
285d0321 | 2648 | int bars; |
09483916 | 2649 | int mem_only; |
7b867cf7 | 2650 | device_reg_t __iomem *iobase; /* Base I/O address */ |
3776541d | 2651 | resource_size_t pio_address; |
fa2a1ce5 | 2652 | |
7b867cf7 | 2653 | #define MIN_IOBASE_LEN 0x100 |
73208dfd | 2654 | /* Multi queue data structs */ |
08029990 | 2655 | device_reg_t __iomem *mqiobase; |
6246b8a1 | 2656 | device_reg_t __iomem *msixbase; |
73208dfd AC |
2657 | uint16_t msix_count; |
2658 | uint8_t mqenable; | |
2659 | struct req_que **req_q_map; | |
2660 | struct rsp_que **rsp_q_map; | |
2661 | unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; | |
2662 | unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; | |
2afa19a9 AC |
2663 | uint8_t max_req_queues; |
2664 | uint8_t max_rsp_queues; | |
73208dfd AC |
2665 | struct qla_npiv_entry *npiv_info; |
2666 | uint16_t nvram_npiv_size; | |
1da177e4 | 2667 | |
7b867cf7 AC |
2668 | uint16_t switch_cap; |
2669 | #define FLOGI_SEQ_DEL BIT_8 | |
2670 | #define FLOGI_MID_SUPPORT BIT_10 | |
2671 | #define FLOGI_VSAN_SUPPORT BIT_12 | |
2672 | #define FLOGI_SP_SUPPORT BIT_13 | |
e5b68a61 AC |
2673 | |
2674 | uint8_t port_no; /* Physical port of adapter */ | |
2675 | ||
7b867cf7 AC |
2676 | /* Timeout timers. */ |
2677 | uint8_t loop_down_abort_time; /* port down timer */ | |
2678 | atomic_t loop_down_timer; /* loop down timer */ | |
2679 | uint8_t link_down_timeout; /* link down timeout */ | |
2680 | uint16_t max_loop_id; | |
642ef983 | 2681 | uint16_t max_fibre_devices; /* Maximum number of targets */ |
1da177e4 | 2682 | |
1da177e4 | 2683 | uint16_t fb_rev; |
7b867cf7 | 2684 | uint16_t min_external_loopid; /* First external loop Id */ |
1da177e4 | 2685 | |
d8b45213 | 2686 | #define PORT_SPEED_UNKNOWN 0xFFFF |
7b867cf7 AC |
2687 | #define PORT_SPEED_1GB 0x00 |
2688 | #define PORT_SPEED_2GB 0x01 | |
2689 | #define PORT_SPEED_4GB 0x03 | |
2690 | #define PORT_SPEED_8GB 0x04 | |
6246b8a1 | 2691 | #define PORT_SPEED_16GB 0x05 |
3a03eb79 | 2692 | #define PORT_SPEED_10GB 0x13 |
7b867cf7 | 2693 | uint16_t link_data_rate; /* F/W operating speed */ |
1da177e4 LT |
2694 | |
2695 | uint8_t current_topology; | |
2696 | uint8_t prev_topology; | |
2697 | #define ISP_CFG_NL 1 | |
2698 | #define ISP_CFG_N 2 | |
2699 | #define ISP_CFG_FL 4 | |
2700 | #define ISP_CFG_F 8 | |
2701 | ||
7b867cf7 | 2702 | uint8_t operating_mode; /* F/W operating mode */ |
1da177e4 LT |
2703 | #define LOOP 0 |
2704 | #define P2P 1 | |
2705 | #define LOOP_P2P 2 | |
2706 | #define P2P_LOOP 3 | |
1da177e4 | 2707 | uint8_t interrupts_on; |
7b867cf7 AC |
2708 | uint32_t isp_abort_cnt; |
2709 | ||
2710 | #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532 | |
2711 | #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432 | |
3a03eb79 | 2712 | #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001 |
6246b8a1 GM |
2713 | #define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031 |
2714 | #define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031 | |
7b867cf7 AC |
2715 | uint32_t device_type; |
2716 | #define DT_ISP2100 BIT_0 | |
2717 | #define DT_ISP2200 BIT_1 | |
2718 | #define DT_ISP2300 BIT_2 | |
2719 | #define DT_ISP2312 BIT_3 | |
2720 | #define DT_ISP2322 BIT_4 | |
2721 | #define DT_ISP6312 BIT_5 | |
2722 | #define DT_ISP6322 BIT_6 | |
2723 | #define DT_ISP2422 BIT_7 | |
2724 | #define DT_ISP2432 BIT_8 | |
2725 | #define DT_ISP5422 BIT_9 | |
2726 | #define DT_ISP5432 BIT_10 | |
2727 | #define DT_ISP2532 BIT_11 | |
2728 | #define DT_ISP8432 BIT_12 | |
3a03eb79 | 2729 | #define DT_ISP8001 BIT_13 |
a9083016 | 2730 | #define DT_ISP8021 BIT_14 |
6246b8a1 GM |
2731 | #define DT_ISP2031 BIT_15 |
2732 | #define DT_ISP8031 BIT_16 | |
2733 | #define DT_ISP_LAST (DT_ISP8031 << 1) | |
7b867cf7 | 2734 | |
e02587d7 | 2735 | #define DT_T10_PI BIT_25 |
7b867cf7 AC |
2736 | #define DT_IIDMA BIT_26 |
2737 | #define DT_FWI2 BIT_27 | |
2738 | #define DT_ZIO_SUPPORTED BIT_28 | |
2739 | #define DT_OEM_001 BIT_29 | |
2740 | #define DT_ISP2200A BIT_30 | |
2741 | #define DT_EXTENDED_IDS BIT_31 | |
2742 | #define DT_MASK(ha) ((ha)->device_type & (DT_ISP_LAST - 1)) | |
2743 | #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100) | |
2744 | #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200) | |
2745 | #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300) | |
2746 | #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312) | |
2747 | #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322) | |
2748 | #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312) | |
2749 | #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322) | |
2750 | #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422) | |
2751 | #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432) | |
2752 | #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422) | |
2753 | #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432) | |
2754 | #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532) | |
2755 | #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432) | |
3a03eb79 | 2756 | #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001) |
6246b8a1 | 2757 | #define IS_QLA81XX(ha) (IS_QLA8001(ha)) |
a9083016 | 2758 | #define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021) |
6246b8a1 GM |
2759 | #define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031) |
2760 | #define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031) | |
7b867cf7 AC |
2761 | |
2762 | #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \ | |
2763 | IS_QLA6312(ha) || IS_QLA6322(ha)) | |
2764 | #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha)) | |
2765 | #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha)) | |
2766 | #define IS_QLA25XX(ha) (IS_QLA2532(ha)) | |
6246b8a1 | 2767 | #define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha)) |
7b867cf7 AC |
2768 | #define IS_QLA84XX(ha) (IS_QLA8432(ha)) |
2769 | #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \ | |
2770 | IS_QLA84XX(ha)) | |
6246b8a1 GM |
2771 | #define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \ |
2772 | IS_QLA8031(ha)) | |
7b867cf7 | 2773 | #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \ |
a9083016 | 2774 | IS_QLA25XX(ha) || IS_QLA81XX(ha) || \ |
6246b8a1 GM |
2775 | IS_QLA82XX(ha) || IS_QLA83XX(ha)) |
2776 | #define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha)) | |
2777 | #define IS_NOPOLLING_TYPE(ha) ((IS_QLA25XX(ha) || IS_QLA81XX(ha) || \ | |
2778 | IS_QLA83XX(ha)) && (ha)->flags.msix_enabled) | |
2779 | #define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha)) | |
2780 | #define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha)) | |
ac280b67 | 2781 | #define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha)) |
7b867cf7 | 2782 | |
e02587d7 | 2783 | #define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI) |
7b867cf7 AC |
2784 | #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA) |
2785 | #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2) | |
2786 | #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED) | |
2787 | #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001) | |
2788 | #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS) | |
6246b8a1 GM |
2789 | #define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED) |
2790 | #define IS_MQUE_CAPABLE(ha) ((ha)->mqenable || IS_QLA83XX(ha)) | |
a9b6f722 | 2791 | #define IS_BIDI_CAPABLE(ha) ((IS_QLA25XX(ha) || IS_QLA2031(ha))) |
81178772 SK |
2792 | /* Bit 21 of fw_attributes decides the MCTP capabilities */ |
2793 | #define IS_MCTP_CAPABLE(ha) (IS_QLA2031(ha) && \ | |
2794 | ((ha)->fw_attributes_ext[0] & BIT_0)) | |
9e522cd8 AE |
2795 | #define IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha)) |
2796 | #define IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha)) | |
2797 | #define IS_PI_DIFB_DIX0_CAPABLE(ha) (0) | |
2798 | #define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha)) | |
2799 | #define IS_PI_SPLIT_DET_CAPABLE(ha) (IS_PI_SPLIT_DET_CAPABLE_HBA(ha) && \ | |
2800 | (((ha)->fw_attributes_h << 16 | (ha)->fw_attributes) & BIT_22)) | |
aa230bc5 | 2801 | #define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha)) |
33c36c0a | 2802 | #define IS_TGT_MODE_CAPABLE(ha) (ha->tgt.atio_q_length) |
1da177e4 LT |
2803 | |
2804 | /* HBA serial number */ | |
2805 | uint8_t serial0; | |
2806 | uint8_t serial1; | |
2807 | uint8_t serial2; | |
2808 | ||
2809 | /* NVRAM configuration data */ | |
7b867cf7 AC |
2810 | #define MAX_NVRAM_SIZE 4096 |
2811 | #define VPD_OFFSET MAX_NVRAM_SIZE / 2 | |
3d71644c | 2812 | uint16_t nvram_size; |
1da177e4 | 2813 | uint16_t nvram_base; |
281afe19 | 2814 | void *nvram; |
6f641790 AV |
2815 | uint16_t vpd_size; |
2816 | uint16_t vpd_base; | |
281afe19 | 2817 | void *vpd; |
1da177e4 LT |
2818 | |
2819 | uint16_t loop_reset_delay; | |
1da177e4 LT |
2820 | uint8_t retry_count; |
2821 | uint8_t login_timeout; | |
2822 | uint16_t r_a_tov; | |
2823 | int port_down_retry_count; | |
1da177e4 | 2824 | uint8_t mbx_count; |
1da177e4 | 2825 | |
7b867cf7 | 2826 | uint32_t login_retry_count; |
1da177e4 LT |
2827 | /* SNS command interfaces. */ |
2828 | ms_iocb_entry_t *ms_iocb; | |
2829 | dma_addr_t ms_iocb_dma; | |
2830 | struct ct_sns_pkt *ct_sns; | |
2831 | dma_addr_t ct_sns_dma; | |
2832 | /* SNS command interfaces for 2200. */ | |
2833 | struct sns_cmd_pkt *sns_cmd; | |
2834 | dma_addr_t sns_cmd_dma; | |
2835 | ||
7b867cf7 AC |
2836 | #define SFP_DEV_SIZE 256 |
2837 | #define SFP_BLOCK_SIZE 64 | |
2838 | void *sfp_data; | |
2839 | dma_addr_t sfp_data_dma; | |
88729e53 | 2840 | |
b5d0329f | 2841 | #define XGMAC_DATA_SIZE 4096 |
ce0423f4 AV |
2842 | void *xgmac_data; |
2843 | dma_addr_t xgmac_data_dma; | |
2844 | ||
b5d0329f | 2845 | #define DCBX_TLV_DATA_SIZE 4096 |
11bbc1d8 AV |
2846 | void *dcbx_tlv; |
2847 | dma_addr_t dcbx_tlv_dma; | |
2848 | ||
39a11240 | 2849 | struct task_struct *dpc_thread; |
1da177e4 LT |
2850 | uint8_t dpc_active; /* DPC routine is active */ |
2851 | ||
1da177e4 LT |
2852 | dma_addr_t gid_list_dma; |
2853 | struct gid_list_info *gid_list; | |
abbd8870 | 2854 | int gid_list_info_size; |
1da177e4 | 2855 | |
fa2a1ce5 | 2856 | /* Small DMA pool allocations -- maximum 256 bytes in length. */ |
7b867cf7 | 2857 | #define DMA_POOL_SIZE 256 |
1da177e4 LT |
2858 | struct dma_pool *s_dma_pool; |
2859 | ||
2860 | dma_addr_t init_cb_dma; | |
3d71644c AV |
2861 | init_cb_t *init_cb; |
2862 | int init_cb_size; | |
b64b0e8f AV |
2863 | dma_addr_t ex_init_cb_dma; |
2864 | struct ex_init_cb_81xx *ex_init_cb; | |
1da177e4 | 2865 | |
5ff1d584 AV |
2866 | void *async_pd; |
2867 | dma_addr_t async_pd_dma; | |
2868 | ||
7a67735b AV |
2869 | void *swl; |
2870 | ||
1da177e4 LT |
2871 | /* These are used by mailbox operations. */ |
2872 | volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT]; | |
2873 | ||
2874 | mbx_cmd_t *mcp; | |
2875 | unsigned long mbx_cmd_flags; | |
7b867cf7 AC |
2876 | #define MBX_INTERRUPT 1 |
2877 | #define MBX_INTR_WAIT 2 | |
1da177e4 LT |
2878 | #define MBX_UPDATE_FLASH_ACTIVE 3 |
2879 | ||
7b867cf7 | 2880 | struct mutex vport_lock; /* Virtual port synchronization */ |
feafb7b1 | 2881 | spinlock_t vport_slock; /* order is hardware_lock, then vport_slock */ |
7b867cf7 | 2882 | struct completion mbx_cmd_comp; /* Serialize mbx access */ |
0b05a1f0 | 2883 | struct completion mbx_intr_comp; /* Used for completion notification */ |
23f2ebd1 SR |
2884 | struct completion dcbx_comp; /* For set port config notification */ |
2885 | int notify_dcbx_comp; | |
a9b6f722 | 2886 | struct mutex selflogin_lock; |
1da177e4 | 2887 | |
1da177e4 | 2888 | /* Basic firmware related information. */ |
1da177e4 LT |
2889 | uint16_t fw_major_version; |
2890 | uint16_t fw_minor_version; | |
2891 | uint16_t fw_subminor_version; | |
2892 | uint16_t fw_attributes; | |
6246b8a1 GM |
2893 | uint16_t fw_attributes_h; |
2894 | uint16_t fw_attributes_ext[2]; | |
1da177e4 LT |
2895 | uint32_t fw_memory_size; |
2896 | uint32_t fw_transfer_size; | |
441d1072 AV |
2897 | uint32_t fw_srisc_address; |
2898 | #define RISC_START_ADDRESS_2100 0x1000 | |
2899 | #define RISC_START_ADDRESS_2300 0x800 | |
2900 | #define RISC_START_ADDRESS_2400 0x100000 | |
24a08138 | 2901 | uint16_t fw_xcb_count; |
8d93f550 | 2902 | uint16_t fw_iocb_count; |
1da177e4 | 2903 | |
7b867cf7 | 2904 | uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */ |
1da177e4 | 2905 | uint8_t fw_seriallink_options[4]; |
3d71644c | 2906 | uint16_t fw_seriallink_options24[4]; |
1da177e4 | 2907 | |
55a96158 | 2908 | uint8_t mpi_version[3]; |
3a03eb79 | 2909 | uint32_t mpi_capabilities; |
55a96158 | 2910 | uint8_t phy_version[3]; |
3a03eb79 | 2911 | |
1da177e4 | 2912 | /* Firmware dump information. */ |
a7a167bf AV |
2913 | struct qla2xxx_fw_dump *fw_dump; |
2914 | uint32_t fw_dump_len; | |
d4e3e04d | 2915 | int fw_dumped; |
1da177e4 | 2916 | int fw_dump_reading; |
a7a167bf AV |
2917 | dma_addr_t eft_dma; |
2918 | void *eft; | |
81178772 SK |
2919 | /* Current size of mctp dump is 0x086064 bytes */ |
2920 | #define MCTP_DUMP_SIZE 0x086064 | |
2921 | dma_addr_t mctp_dump_dma; | |
2922 | void *mctp_dump; | |
2923 | int mctp_dumped; | |
2924 | int mctp_dump_reading; | |
bb99de67 | 2925 | uint32_t chain_offset; |
df613b96 AV |
2926 | struct dentry *dfs_dir; |
2927 | struct dentry *dfs_fce; | |
2928 | dma_addr_t fce_dma; | |
2929 | void *fce; | |
2930 | uint32_t fce_bufs; | |
2931 | uint16_t fce_mb[8]; | |
2932 | uint64_t fce_wr, fce_rd; | |
2933 | struct mutex fce_mutex; | |
2934 | ||
3d71644c | 2935 | uint32_t pci_attr; |
a8488abe | 2936 | uint16_t chip_revision; |
1da177e4 LT |
2937 | |
2938 | uint16_t product_id[4]; | |
2939 | ||
2940 | uint8_t model_number[16+1]; | |
2941 | #define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0" | |
1ee27146 | 2942 | char model_desc[80]; |
cca5335c | 2943 | uint8_t adapter_id[16+1]; |
1da177e4 | 2944 | |
854165f4 AV |
2945 | /* Option ROM information. */ |
2946 | char *optrom_buffer; | |
2947 | uint32_t optrom_size; | |
2948 | int optrom_state; | |
2949 | #define QLA_SWAITING 0 | |
2950 | #define QLA_SREADING 1 | |
2951 | #define QLA_SWRITING 2 | |
b7cc176c JC |
2952 | uint32_t optrom_region_start; |
2953 | uint32_t optrom_region_size; | |
854165f4 | 2954 | |
7b867cf7 | 2955 | /* PCI expansion ROM image information. */ |
30c47662 AV |
2956 | #define ROM_CODE_TYPE_BIOS 0 |
2957 | #define ROM_CODE_TYPE_FCODE 1 | |
2958 | #define ROM_CODE_TYPE_EFI 3 | |
7b867cf7 AC |
2959 | uint8_t bios_revision[2]; |
2960 | uint8_t efi_revision[2]; | |
2961 | uint8_t fcode_revision[16]; | |
30c47662 AV |
2962 | uint32_t fw_revision[4]; |
2963 | ||
0f2d962f MI |
2964 | uint32_t gold_fw_version[4]; |
2965 | ||
3a03eb79 AV |
2966 | /* Offsets for flash/nvram access (set to ~0 if not used). */ |
2967 | uint32_t flash_conf_off; | |
2968 | uint32_t flash_data_off; | |
2969 | uint32_t nvram_conf_off; | |
2970 | uint32_t nvram_data_off; | |
2971 | ||
7d232c74 AV |
2972 | uint32_t fdt_wrt_disable; |
2973 | uint32_t fdt_erase_cmd; | |
2974 | uint32_t fdt_block_size; | |
2975 | uint32_t fdt_unprotect_sec_cmd; | |
2976 | uint32_t fdt_protect_sec_cmd; | |
2977 | ||
7b867cf7 AC |
2978 | uint32_t flt_region_flt; |
2979 | uint32_t flt_region_fdt; | |
2980 | uint32_t flt_region_boot; | |
2981 | uint32_t flt_region_fw; | |
2982 | uint32_t flt_region_vpd_nvram; | |
3d79038f AV |
2983 | uint32_t flt_region_vpd; |
2984 | uint32_t flt_region_nvram; | |
7b867cf7 | 2985 | uint32_t flt_region_npiv_conf; |
cbc8eb67 | 2986 | uint32_t flt_region_gold_fw; |
09ff701a | 2987 | uint32_t flt_region_fcp_prio; |
a9083016 | 2988 | uint32_t flt_region_bootload; |
c00d8994 | 2989 | |
1da177e4 | 2990 | /* Needed for BEACON */ |
7b867cf7 AC |
2991 | uint16_t beacon_blink_led; |
2992 | uint8_t beacon_color_state; | |
f6df144c AV |
2993 | #define QLA_LED_GRN_ON 0x01 |
2994 | #define QLA_LED_YLW_ON 0x02 | |
2995 | #define QLA_LED_ABR_ON 0x04 | |
2996 | #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */ | |
2997 | /* ISP2322: red, green, amber. */ | |
7b867cf7 AC |
2998 | uint16_t zio_mode; |
2999 | uint16_t zio_timer; | |
a8488abe | 3000 | |
73208dfd | 3001 | struct qla_msix_entry *msix_entries; |
2c3dfe3f | 3002 | |
7b867cf7 AC |
3003 | struct list_head vp_list; /* list of VP */ |
3004 | unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) / | |
3005 | sizeof(unsigned long)]; | |
3006 | uint16_t num_vhosts; /* number of vports created */ | |
3007 | uint16_t num_vsans; /* number of vsan created */ | |
3008 | uint16_t max_npiv_vports; /* 63 or 125 per topoloty */ | |
3009 | int cur_vport_count; | |
3010 | ||
3011 | struct qla_chip_state_84xx *cs84xx; | |
7b867cf7 | 3012 | struct isp_operations *isp_ops; |
68ca949c | 3013 | struct workqueue_struct *wq; |
9a069e19 | 3014 | struct qlfc_fw fw_buf; |
09ff701a SR |
3015 | |
3016 | /* FCP_CMND priority support */ | |
3017 | struct qla_fcp_prio_cfg *fcp_prio_cfg; | |
a9083016 GM |
3018 | |
3019 | struct dma_pool *dl_dma_pool; | |
3020 | #define DSD_LIST_DMA_POOL_SIZE 512 | |
3021 | ||
3022 | struct dma_pool *fcp_cmnd_dma_pool; | |
3023 | mempool_t *ctx_mempool; | |
3024 | #define FCP_CMND_DMA_POOL_SIZE 512 | |
3025 | ||
3026 | unsigned long nx_pcibase; /* Base I/O address */ | |
3027 | uint8_t *nxdb_rd_ptr; /* Doorbell read pointer */ | |
3028 | unsigned long nxdb_wr_ptr; /* Door bell write pointer */ | |
a9083016 GM |
3029 | |
3030 | uint32_t crb_win; | |
3031 | uint32_t curr_window; | |
3032 | uint32_t ddr_mn_window; | |
3033 | unsigned long mn_win_crb; | |
3034 | unsigned long ms_win_crb; | |
3035 | int qdr_sn_window; | |
7d613ac6 SV |
3036 | uint32_t fcoe_dev_init_timeout; |
3037 | uint32_t fcoe_reset_timeout; | |
a9083016 GM |
3038 | rwlock_t hw_lock; |
3039 | uint16_t portnum; /* port number */ | |
3040 | int link_width; | |
3041 | struct fw_blob *hablob; | |
3042 | struct qla82xx_legacy_intr_set nx_legacy_intr; | |
3043 | ||
3044 | uint16_t gbl_dsd_inuse; | |
3045 | uint16_t gbl_dsd_avail; | |
3046 | struct list_head gbl_dsd_list; | |
3047 | #define NUM_DSD_CHAIN 4096 | |
9c2b2975 HZ |
3048 | |
3049 | uint8_t fw_type; | |
3050 | __le32 file_prd_off; /* File firmware product offset */ | |
08de2844 GM |
3051 | |
3052 | uint32_t md_template_size; | |
3053 | void *md_tmplt_hdr; | |
3054 | dma_addr_t md_tmplt_hdr_dma; | |
3055 | void *md_dump; | |
3056 | uint32_t md_dump_size; | |
2d70c103 | 3057 | |
5f16b331 | 3058 | void *loop_id_map; |
7d613ac6 SV |
3059 | |
3060 | /* QLA83XX IDC specific fields */ | |
3061 | uint32_t idc_audit_ts; | |
3062 | ||
3063 | /* DPC low-priority workqueue */ | |
3064 | struct workqueue_struct *dpc_lp_wq; | |
3065 | struct work_struct idc_aen; | |
3066 | /* DPC high-priority workqueue */ | |
3067 | struct workqueue_struct *dpc_hp_wq; | |
3068 | struct work_struct nic_core_reset; | |
3069 | struct work_struct idc_state_handler; | |
3070 | struct work_struct nic_core_unrecoverable; | |
3071 | ||
3c290d0b CD |
3072 | #define HOST_QUEUE_RAMPDOWN_INTERVAL (60 * HZ) |
3073 | #define HOST_QUEUE_RAMPUP_INTERVAL (30 * HZ) | |
3074 | unsigned long host_last_rampdown_time; | |
3075 | unsigned long host_last_rampup_time; | |
3076 | int cfg_lun_q_depth; | |
3077 | ||
2d70c103 | 3078 | struct qlt_hw_data tgt; |
fe52f6e1 JC |
3079 | uint16_t thermal_support; |
3080 | #define THERMAL_SUPPORT_I2C BIT_0 | |
3081 | #define THERMAL_SUPPORT_ISP BIT_1 | |
7b867cf7 AC |
3082 | }; |
3083 | ||
3084 | /* | |
3085 | * Qlogic scsi host structure | |
3086 | */ | |
3087 | typedef struct scsi_qla_host { | |
3088 | struct list_head list; | |
3089 | struct list_head vp_fcports; /* list of fcports */ | |
3090 | struct list_head work_list; | |
f999f4c1 AV |
3091 | spinlock_t work_lock; |
3092 | ||
7b867cf7 AC |
3093 | /* Commonly used flags and state information. */ |
3094 | struct Scsi_Host *host; | |
3095 | unsigned long host_no; | |
3096 | uint8_t host_str[16]; | |
3097 | ||
3098 | volatile struct { | |
3099 | uint32_t init_done :1; | |
3100 | uint32_t online :1; | |
7b867cf7 AC |
3101 | uint32_t reset_active :1; |
3102 | ||
3103 | uint32_t management_server_logged_in :1; | |
3104 | uint32_t process_response_queue :1; | |
bad75002 | 3105 | uint32_t difdix_supported:1; |
feafb7b1 | 3106 | uint32_t delete_progress:1; |
7b867cf7 AC |
3107 | } flags; |
3108 | ||
3109 | atomic_t loop_state; | |
3110 | #define LOOP_TIMEOUT 1 | |
3111 | #define LOOP_DOWN 2 | |
3112 | #define LOOP_UP 3 | |
3113 | #define LOOP_UPDATE 4 | |
3114 | #define LOOP_READY 5 | |
3115 | #define LOOP_DEAD 6 | |
3116 | ||
3117 | unsigned long dpc_flags; | |
3118 | #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */ | |
3119 | #define RESET_ACTIVE 1 | |
3120 | #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */ | |
3121 | #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */ | |
3122 | #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */ | |
3123 | #define LOOP_RESYNC_ACTIVE 5 | |
3124 | #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */ | |
3125 | #define RSCN_UPDATE 7 /* Perform an RSCN update. */ | |
ddb9b126 SS |
3126 | #define RELOGIN_NEEDED 8 |
3127 | #define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */ | |
3128 | #define ISP_ABORT_RETRY 10 /* ISP aborted. */ | |
3129 | #define BEACON_BLINK_NEEDED 11 | |
3130 | #define REGISTER_FDMI_NEEDED 12 | |
3131 | #define FCPORT_UPDATE_NEEDED 13 | |
3132 | #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */ | |
3133 | #define UNLOADING 15 | |
3134 | #define NPIV_CONFIG_NEEDED 16 | |
a9083016 GM |
3135 | #define ISP_UNRECOVERABLE 17 |
3136 | #define FCOE_CTX_RESET_NEEDED 18 /* Initiate FCoE context reset */ | |
b1d46989 | 3137 | #define MPI_RESET_NEEDED 19 /* Initiate MPI FW reset */ |
579d12b5 | 3138 | #define ISP_QUIESCE_NEEDED 20 /* Driver need some quiescence */ |
2d70c103 | 3139 | #define SCR_PENDING 21 /* SCR in target mode */ |
3c290d0b CD |
3140 | #define HOST_RAMP_DOWN_QUEUE_DEPTH 22 |
3141 | #define HOST_RAMP_UP_QUEUE_DEPTH 23 | |
7b867cf7 AC |
3142 | |
3143 | uint32_t device_flags; | |
ddb9b126 SS |
3144 | #define SWITCH_FOUND BIT_0 |
3145 | #define DFLG_NO_CABLE BIT_1 | |
a9083016 | 3146 | #define DFLG_DEV_FAILED BIT_5 |
7b867cf7 | 3147 | |
7b867cf7 AC |
3148 | /* ISP configuration data. */ |
3149 | uint16_t loop_id; /* Host adapter loop id */ | |
a9b6f722 SK |
3150 | uint16_t self_login_loop_id; /* host adapter loop id |
3151 | * get it on self login | |
3152 | */ | |
3153 | fc_port_t bidir_fcport; /* fcport used for bidir cmnds | |
3154 | * no need of allocating it for | |
3155 | * each command | |
3156 | */ | |
7b867cf7 AC |
3157 | |
3158 | port_id_t d_id; /* Host adapter port id */ | |
3159 | uint8_t marker_needed; | |
3160 | uint16_t mgmt_svr_loop_id; | |
3161 | ||
3162 | ||
3163 | ||
7b867cf7 AC |
3164 | /* Timeout timers. */ |
3165 | uint8_t loop_down_abort_time; /* port down timer */ | |
3166 | atomic_t loop_down_timer; /* loop down timer */ | |
3167 | uint8_t link_down_timeout; /* link down timeout */ | |
3168 | ||
3169 | uint32_t timer_active; | |
3170 | struct timer_list timer; | |
3171 | ||
3172 | uint8_t node_name[WWN_SIZE]; | |
3173 | uint8_t port_name[WWN_SIZE]; | |
3174 | uint8_t fabric_node_name[WWN_SIZE]; | |
bad7001c AV |
3175 | |
3176 | uint16_t fcoe_vlan_id; | |
3177 | uint16_t fcoe_fcf_idx; | |
3178 | uint8_t fcoe_vn_port_mac[6]; | |
3179 | ||
7b867cf7 AC |
3180 | uint32_t vp_abort_cnt; |
3181 | ||
2c3dfe3f | 3182 | struct fc_vport *fc_vport; /* holds fc_vport * for each vport */ |
2c3dfe3f SJ |
3183 | uint16_t vp_idx; /* vport ID */ |
3184 | ||
2c3dfe3f | 3185 | unsigned long vp_flags; |
2c3dfe3f SJ |
3186 | #define VP_IDX_ACQUIRED 0 /* bit no 0 */ |
3187 | #define VP_CREATE_NEEDED 1 | |
3188 | #define VP_BIND_NEEDED 2 | |
3189 | #define VP_DELETE_NEEDED 3 | |
3190 | #define VP_SCR_NEEDED 4 /* State Change Request registration */ | |
3191 | atomic_t vp_state; | |
3192 | #define VP_OFFLINE 0 | |
3193 | #define VP_ACTIVE 1 | |
3194 | #define VP_FAILED 2 | |
3195 | // #define VP_DISABLE 3 | |
3196 | uint16_t vp_err_state; | |
3197 | uint16_t vp_prev_err_state; | |
3198 | #define VP_ERR_UNKWN 0 | |
3199 | #define VP_ERR_PORTDWN 1 | |
3200 | #define VP_ERR_FAB_UNSUPPORTED 2 | |
3201 | #define VP_ERR_FAB_NORESOURCES 3 | |
3202 | #define VP_ERR_FAB_LOGOUT 4 | |
3203 | #define VP_ERR_ADAP_NORESOURCES 5 | |
7b867cf7 | 3204 | struct qla_hw_data *hw; |
2afa19a9 | 3205 | struct req_que *req; |
a9083016 GM |
3206 | int fw_heartbeat_counter; |
3207 | int seconds_since_last_heartbeat; | |
2be21fa2 SK |
3208 | struct fc_host_statistics fc_host_stat; |
3209 | struct qla_statistics qla_stats; | |
a9b6f722 | 3210 | struct bidi_statistics bidi_stats; |
feafb7b1 AE |
3211 | |
3212 | atomic_t vref_count; | |
1da177e4 LT |
3213 | } scsi_qla_host_t; |
3214 | ||
2d70c103 NB |
3215 | #define SET_VP_IDX 1 |
3216 | #define SET_AL_PA 2 | |
3217 | #define RESET_VP_IDX 3 | |
3218 | #define RESET_AL_PA 4 | |
3219 | struct qla_tgt_vp_map { | |
3220 | uint8_t idx; | |
3221 | scsi_qla_host_t *vha; | |
3222 | }; | |
3223 | ||
1da177e4 LT |
3224 | /* |
3225 | * Macros to help code, maintain, etc. | |
3226 | */ | |
3227 | #define LOOP_TRANSITION(ha) \ | |
3228 | (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \ | |
23443b1d | 3229 | test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \ |
1da177e4 | 3230 | atomic_read(&ha->loop_state) == LOOP_DOWN) |
fa2a1ce5 | 3231 | |
feafb7b1 AE |
3232 | #define QLA_VHA_MARK_BUSY(__vha, __bail) do { \ |
3233 | atomic_inc(&__vha->vref_count); \ | |
3234 | mb(); \ | |
3235 | if (__vha->flags.delete_progress) { \ | |
3236 | atomic_dec(&__vha->vref_count); \ | |
3237 | __bail = 1; \ | |
3238 | } else { \ | |
3239 | __bail = 0; \ | |
3240 | } \ | |
3241 | } while (0) | |
3242 | ||
3243 | #define QLA_VHA_MARK_NOT_BUSY(__vha) do { \ | |
3244 | atomic_dec(&__vha->vref_count); \ | |
3245 | } while (0) | |
3246 | ||
1da177e4 LT |
3247 | /* |
3248 | * qla2x00 local function return status codes | |
3249 | */ | |
3250 | #define MBS_MASK 0x3fff | |
3251 | ||
3252 | #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK) | |
3253 | #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK) | |
3254 | #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK) | |
3255 | #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK) | |
3256 | #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK) | |
3257 | #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK) | |
3258 | #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK) | |
3259 | #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK) | |
3260 | #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK) | |
3261 | #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK) | |
3262 | ||
3263 | #define QLA_FUNCTION_TIMEOUT 0x100 | |
3264 | #define QLA_FUNCTION_PARAMETER_ERROR 0x101 | |
3265 | #define QLA_FUNCTION_FAILED 0x102 | |
3266 | #define QLA_MEMORY_ALLOC_FAILED 0x103 | |
3267 | #define QLA_LOCK_TIMEOUT 0x104 | |
3268 | #define QLA_ABORTED 0x105 | |
3269 | #define QLA_SUSPENDED 0x106 | |
3270 | #define QLA_BUSY 0x107 | |
cca5335c | 3271 | #define QLA_ALREADY_REGISTERED 0x109 |
1da177e4 | 3272 | |
1da177e4 LT |
3273 | #define NVRAM_DELAY() udelay(10) |
3274 | ||
1da177e4 LT |
3275 | /* |
3276 | * Flash support definitions | |
3277 | */ | |
854165f4 AV |
3278 | #define OPTROM_SIZE_2300 0x20000 |
3279 | #define OPTROM_SIZE_2322 0x100000 | |
3280 | #define OPTROM_SIZE_24XX 0x100000 | |
c3a2f0df | 3281 | #define OPTROM_SIZE_25XX 0x200000 |
3a03eb79 | 3282 | #define OPTROM_SIZE_81XX 0x400000 |
a9083016 | 3283 | #define OPTROM_SIZE_82XX 0x800000 |
6246b8a1 | 3284 | #define OPTROM_SIZE_83XX 0x1000000 |
a9083016 GM |
3285 | |
3286 | #define OPTROM_BURST_SIZE 0x1000 | |
3287 | #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4) | |
1da177e4 | 3288 | |
bad75002 AE |
3289 | #define QLA_DSDS_PER_IOCB 37 |
3290 | ||
4d78c973 GM |
3291 | #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr) |
3292 | ||
58548cb5 GM |
3293 | #define QLA_SG_ALL 1024 |
3294 | ||
4d78c973 GM |
3295 | enum nexus_wait_type { |
3296 | WAIT_HOST = 0, | |
3297 | WAIT_TARGET, | |
3298 | WAIT_LUN, | |
3299 | }; | |
3300 | ||
1da177e4 LT |
3301 | #include "qla_gbl.h" |
3302 | #include "qla_dbg.h" | |
3303 | #include "qla_inline.h" | |
1da177e4 | 3304 | #endif |