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scsi: qla2xxx: Fix Async GPN_FT for FCP and FC-NVMe scan
[mirror_ubuntu-hirsute-kernel.git] / drivers / scsi / qla2xxx / qla_init.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
73208dfd 8#include "qla_gbl.h"
1da177e4
LT		 9
10#include <linux/delay.h>
5a0e3ad6 11#include <linux/slab.h>
0107109e 12#include <linux/vmalloc.h>
1da177e4
LT		 13
14#include "qla_devtbl.h"
15
4e08df3f
DM		 16#ifdef CONFIG_SPARC
17#include <asm/prom.h>
4e08df3f
DM		 18#endif
19
2d70c103
NB		 20#include <target/target_core_base.h>
21#include "qla_target.h"
22
1da177e4
LT		 23/*
24* QLogic ISP2x00 Hardware Support Function Prototypes.
25*/
1da177e4 26static int qla2x00_isp_firmware(scsi_qla_host_t *);
1da177e4 27static int qla2x00_setup_chip(scsi_qla_host_t *);
1da177e4
LT		 28static int qla2x00_fw_ready(scsi_qla_host_t *);
29static int qla2x00_configure_hba(scsi_qla_host_t *);
1da177e4
LT		 30static int qla2x00_configure_loop(scsi_qla_host_t *);
31static int qla2x00_configure_local_loop(scsi_qla_host_t *);
1da177e4 32static int qla2x00_configure_fabric(scsi_qla_host_t *);
726b8548 33static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *);
1da177e4 34static int qla2x00_restart_isp(scsi_qla_host_t *);
1da177e4 35
4d4df193
HK		 36static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *);
37static int qla84xx_init_chip(scsi_qla_host_t *);
73208dfd 38static int qla25xx_init_queues(struct qla_hw_data *);
a5d42f4c 39static int qla24xx_post_prli_work(struct scsi_qla_host*, fc_port_t *);
726b8548
QT		 40static void qla24xx_handle_plogi_done_event(struct scsi_qla_host *,
41 struct event_arg *);
a5d42f4c
DG		 42static void qla24xx_handle_prli_done_event(struct scsi_qla_host *,
43 struct event_arg *);
a4239945 44static void __qla24xx_handle_gpdb_event(scsi_qla_host_t *, struct event_arg *);
4d4df193 45
ac280b67
AV		 46/* SRB Extensions ---------------------------------------------------------- */
47
9ba56b95 48void
8e5f4ba0 49qla2x00_sp_timeout(struct timer_list *t)
ac280b67 50{
8e5f4ba0 51 srb_t *sp = from_timer(sp, t, u.iocb_cmd.timer);
4916392b 52 struct srb_iocb *iocb;
25ff6af1 53 scsi_qla_host_t *vha = sp->vha;
ac280b67
AV		 54 struct req_que *req;
55 unsigned long flags;
56
25ff6af1
JC		 57 spin_lock_irqsave(&vha->hw->hardware_lock, flags);
58 req = vha->hw->req_q_map[0];
ac280b67 59 req->outstanding_cmds[sp->handle] = NULL;
9ba56b95 60 iocb = &sp->u.iocb_cmd;
4916392b 61 iocb->timeout(sp);
045d6ea2
GM		 62 if (sp->type != SRB_ELS_DCMD)
63 sp->free(sp);
25ff6af1 64 spin_unlock_irqrestore(&vha->hw->hardware_lock, flags);
ac280b67
AV		 65}
66
9ba56b95 67void
25ff6af1 68qla2x00_sp_free(void *ptr)
ac280b67 69{
25ff6af1 70 srb_t *sp = ptr;
9ba56b95 71 struct srb_iocb *iocb = &sp->u.iocb_cmd;
ac280b67 72
4d97cc53 73 del_timer(&iocb->timer);
25ff6af1 74 qla2x00_rel_sp(sp);
ac280b67
AV		 75}
76
ac280b67
AV		 77/* Asynchronous Login/Logout Routines -------------------------------------- */
78
a9b6f722 79unsigned long
5b91490e
AV		 80qla2x00_get_async_timeout(struct scsi_qla_host *vha)
81{
82 unsigned long tmo;
83 struct qla_hw_data *ha = vha->hw;
84
85 /* Firmware should use switch negotiated r_a_tov for timeout. */
86 tmo = ha->r_a_tov / 10 * 2;
8ae6d9c7
GM		 87 if (IS_QLAFX00(ha)) {
88 tmo = FX00_DEF_RATOV * 2;
89 } else if (!IS_FWI2_CAPABLE(ha)) {
5b91490e
AV		 90 /*
91 * Except for earlier ISPs where the timeout is seeded from the
92 * initialization control block.
93 */
94 tmo = ha->login_timeout;
95 }
96 return tmo;
97}
ac280b67 98
726b8548 99void
9ba56b95 100qla2x00_async_iocb_timeout(void *data)
ac280b67 101{
25ff6af1 102 srb_t *sp = data;
ac280b67 103 fc_port_t *fcport = sp->fcport;
726b8548
QT		 104 struct srb_iocb *lio = &sp->u.iocb_cmd;
105 struct event_arg ea;
ac280b67 106
5c25d451
QT		 107 if (fcport) {
108 ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
109 "Async-%s timeout - hdl=%x portid=%06x %8phC.\n",
110 sp->name, sp->handle, fcport->d_id.b24, fcport->port_name);
111
6d674927 112 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
5c25d451
QT		 113 } else {
114 pr_info("Async-%s timeout - hdl=%x.\n",
115 sp->name, sp->handle);
116 }
726b8548
QT		 117
118 switch (sp->type) {
119 case SRB_LOGIN_CMD:
7ac0c332 120 if (!fcport)
121 break;
6ac52608
AV		 122 /* Retry as needed. */
123 lio->u.logio.data[0] = MBS_COMMAND_ERROR;
124 lio->u.logio.data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
125 QLA_LOGIO_LOGIN_RETRIED : 0;
726b8548
QT		 126 memset(&ea, 0, sizeof(ea));
127 ea.event = FCME_PLOGI_DONE;
128 ea.fcport = sp->fcport;
129 ea.data[0] = lio->u.logio.data[0];
130 ea.data[1] = lio->u.logio.data[1];
131 ea.sp = sp;
132 qla24xx_handle_plogi_done_event(fcport->vha, &ea);
133 break;
134 case SRB_LOGOUT_CMD:
7ac0c332 135 if (!fcport)
136 break;
a6ca8878 137 qlt_logo_completion_handler(fcport, QLA_FUNCTION_TIMEOUT);
726b8548
QT		 138 break;
139 case SRB_CT_PTHRU_CMD:
140 case SRB_MB_IOCB:
141 case SRB_NACK_PLOGI:
142 case SRB_NACK_PRLI:
143 case SRB_NACK_LOGO:
2853192e 144 case SRB_CTRL_VP:
25ff6af1 145 sp->done(sp, QLA_FUNCTION_TIMEOUT);
726b8548 146 break;
6ac52608 147 }
ac280b67
AV		 148}
149
99b0bec7 150static void
25ff6af1 151qla2x00_async_login_sp_done(void *ptr, int res)
99b0bec7 152{
25ff6af1
JC		 153 srb_t *sp = ptr;
154 struct scsi_qla_host *vha = sp->vha;
9ba56b95 155 struct srb_iocb *lio = &sp->u.iocb_cmd;
726b8548 156 struct event_arg ea;
9ba56b95 157
83548fe2 158 ql_dbg(ql_dbg_disc, vha, 0x20dd,
25ff6af1 159 "%s %8phC res %d \n", __func__, sp->fcport->port_name, res);
726b8548 160
6d674927
QT		 161 sp->fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
162
726b8548
QT		 163 if (!test_bit(UNLOADING, &vha->dpc_flags)) {
164 memset(&ea, 0, sizeof(ea));
165 ea.event = FCME_PLOGI_DONE;
166 ea.fcport = sp->fcport;
167 ea.data[0] = lio->u.logio.data[0];
168 ea.data[1] = lio->u.logio.data[1];
169 ea.iop[0] = lio->u.logio.iop[0];
170 ea.iop[1] = lio->u.logio.iop[1];
171 ea.sp = sp;
172 qla2x00_fcport_event_handler(vha, &ea);
173 }
9ba56b95 174
25ff6af1 175 sp->free(sp);
99b0bec7
AV		 176}
177
ac280b67
AV		 178int
179qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport,
180 uint16_t *data)
181{
ac280b67 182 srb_t *sp;
4916392b 183 struct srb_iocb *lio;
726b8548
QT		 184 int rval = QLA_FUNCTION_FAILED;
185
186 if (!vha->flags.online)
187 goto done;
188
9ba56b95 189 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 190 if (!sp)
191 goto done;
192
726b8548
QT		 193 fcport->flags |= FCF_ASYNC_SENT;
194 fcport->logout_completed = 0;
195
a4239945 196 fcport->disc_state = DSC_LOGIN_PEND;
9ba56b95
GM		 197 sp->type = SRB_LOGIN_CMD;
198 sp->name = "login";
a4239945
QT		 199 sp->gen1 = fcport->rscn_gen;
200 sp->gen2 = fcport->login_gen;
9ba56b95
GM		 201 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
202
203 lio = &sp->u.iocb_cmd;
3822263e 204 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 205 sp->done = qla2x00_async_login_sp_done;
4916392b 206 lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI;
a5d42f4c
DG		 207
208 if (fcport->fc4f_nvme)
209 lio->u.logio.flags |= SRB_LOGIN_SKIP_PRLI;
210
ac280b67 211 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 212 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
ac280b67 213 rval = qla2x00_start_sp(sp);
080c9517 214 if (rval != QLA_SUCCESS) {
080c9517
CD		 215 fcport->flags |= FCF_LOGIN_NEEDED;
216 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
ac280b67 217 goto done_free_sp;
080c9517 218 }
ac280b67 219
7c3df132 220 ql_dbg(ql_dbg_disc, vha, 0x2072,
726b8548
QT		 221 "Async-login - %8phC hdl=%x, loopid=%x portid=%02x%02x%02x "
222 "retries=%d.\n", fcport->port_name, sp->handle, fcport->loop_id,
cfb0919c
CD		 223 fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
224 fcport->login_retry);
ac280b67
AV		 225 return rval;
226
227done_free_sp:
25ff6af1 228 sp->free(sp);
726b8548 229 fcport->flags &= ~FCF_ASYNC_SENT;
3dbec59b 230done:
ac280b67
AV		 231 return rval;
232}
233
99b0bec7 234static void
25ff6af1 235qla2x00_async_logout_sp_done(void *ptr, int res)
99b0bec7 236{
25ff6af1 237 srb_t *sp = ptr;
9ba56b95 238 struct srb_iocb *lio = &sp->u.iocb_cmd;
9ba56b95 239
6d674927 240 sp->fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
25ff6af1
JC		 241 if (!test_bit(UNLOADING, &sp->vha->dpc_flags))
242 qla2x00_post_async_logout_done_work(sp->vha, sp->fcport,
9ba56b95 243 lio->u.logio.data);
25ff6af1 244 sp->free(sp);
99b0bec7
AV		 245}
246
ac280b67
AV		 247int
248qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport)
249{
ac280b67 250 srb_t *sp;
4916392b 251 struct srb_iocb *lio;
3dbec59b
QT		 252 int rval = QLA_FUNCTION_FAILED;
253
254 if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT))
255 return rval;
ac280b67 256
726b8548 257 fcport->flags |= FCF_ASYNC_SENT;
9ba56b95 258 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 259 if (!sp)
260 goto done;
261
9ba56b95
GM		 262 sp->type = SRB_LOGOUT_CMD;
263 sp->name = "logout";
264 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
265
266 lio = &sp->u.iocb_cmd;
3822263e 267 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 268 sp->done = qla2x00_async_logout_sp_done;
ac280b67
AV		 269 rval = qla2x00_start_sp(sp);
270 if (rval != QLA_SUCCESS)
271 goto done_free_sp;
272
7c3df132 273 ql_dbg(ql_dbg_disc, vha, 0x2070,
726b8548 274 "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x %8phC.\n",
cfb0919c 275 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
726b8548
QT		 276 fcport->d_id.b.area, fcport->d_id.b.al_pa,
277 fcport->port_name);
ac280b67
AV		 278 return rval;
279
280done_free_sp:
25ff6af1 281 sp->free(sp);
ac280b67 282done:
726b8548 283 fcport->flags &= ~FCF_ASYNC_SENT;
ac280b67
AV		 284 return rval;
285}
11aea16a
QT		 286
287void
288qla2x00_async_prlo_done(struct scsi_qla_host *vha, fc_port_t *fcport,
289 uint16_t *data)
290{
291 /* Don't re-login in target mode */
292 if (!fcport->tgt_session)
293 qla2x00_mark_device_lost(vha, fcport, 1, 0);
294 qlt_logo_completion_handler(fcport, data[0]);
295}
296
297static void
298qla2x00_async_prlo_sp_done(void *s, int res)
299{
300 srb_t *sp = (srb_t *)s;
301 struct srb_iocb *lio = &sp->u.iocb_cmd;
302 struct scsi_qla_host *vha = sp->vha;
303
304 if (!test_bit(UNLOADING, &vha->dpc_flags))
305 qla2x00_post_async_prlo_done_work(sp->fcport->vha, sp->fcport,
306 lio->u.logio.data);
307 sp->free(sp);
308}
309
310int
311qla2x00_async_prlo(struct scsi_qla_host *vha, fc_port_t *fcport)
312{
313 srb_t *sp;
314 struct srb_iocb *lio;
315 int rval;
316
317 rval = QLA_FUNCTION_FAILED;
318 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
319 if (!sp)
320 goto done;
321
322 sp->type = SRB_PRLO_CMD;
323 sp->name = "prlo";
324 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
325
326 lio = &sp->u.iocb_cmd;
327 lio->timeout = qla2x00_async_iocb_timeout;
328 sp->done = qla2x00_async_prlo_sp_done;
329 rval = qla2x00_start_sp(sp);
330 if (rval != QLA_SUCCESS)
331 goto done_free_sp;
332
333 ql_dbg(ql_dbg_disc, vha, 0x2070,
334 "Async-prlo - hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
335 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
336 fcport->d_id.b.area, fcport->d_id.b.al_pa);
337 return rval;
338
339done_free_sp:
340 sp->free(sp);
341done:
342 return rval;
343}
344
f13515ac
QT		 345static
346void qla24xx_handle_adisc_event(scsi_qla_host_t *vha, struct event_arg *ea)
347{
0616e965
QT		 348 struct fc_port *fcport = ea->fcport;
349
350 ql_dbg(ql_dbg_disc, vha, 0x20d2,
351 "%s %8phC DS %d LS %d rc %d login %d|%d rscn %d|%d lid %d\n",
352 __func__, fcport->port_name, fcport->disc_state,
353 fcport->fw_login_state, ea->rc, fcport->login_gen, ea->sp->gen2,
354 fcport->rscn_gen, ea->sp->gen1, fcport->loop_id);
355
356 if (ea->data[0] != MBS_COMMAND_COMPLETE) {
a4239945
QT		 357 ql_dbg(ql_dbg_disc, vha, 0x2066,
358 "%s %8phC: adisc fail: post delete\n",
359 __func__, ea->fcport->port_name);
94cff6e1 360 qlt_schedule_sess_for_deletion(ea->fcport);
a4239945
QT		 361 return;
362 }
a4239945
QT		 363
364 if (ea->fcport->disc_state == DSC_DELETE_PEND)
365 return;
366
367 if (ea->sp->gen2 != ea->fcport->login_gen) {
368 /* target side must have changed it. */
369 ql_dbg(ql_dbg_disc, vha, 0x20d3,
0616e965
QT		 370 "%s %8phC generation changed\n",
371 __func__, ea->fcport->port_name);
a4239945
QT		 372 return;
373 } else if (ea->sp->gen1 != ea->fcport->rscn_gen) {
374 ql_dbg(ql_dbg_disc, vha, 0x20d4, "%s %d %8phC post gidpn\n",
375 __func__, __LINE__, ea->fcport->port_name);
376 qla24xx_post_gidpn_work(vha, ea->fcport);
377 return;
378 }
379
380 __qla24xx_handle_gpdb_event(vha, ea);
f13515ac 381}
ac280b67 382
5ff1d584 383static void
25ff6af1 384qla2x00_async_adisc_sp_done(void *ptr, int res)
5ff1d584 385{
25ff6af1
JC		 386 srb_t *sp = ptr;
387 struct scsi_qla_host *vha = sp->vha;
f13515ac 388 struct event_arg ea;
0616e965 389 struct srb_iocb *lio = &sp->u.iocb_cmd;
f13515ac
QT		 390
391 ql_dbg(ql_dbg_disc, vha, 0x2066,
392 "Async done-%s res %x %8phC\n",
393 sp->name, res, sp->fcport->port_name);
394
395 memset(&ea, 0, sizeof(ea));
396 ea.event = FCME_ADISC_DONE;
397 ea.rc = res;
0616e965
QT		 398 ea.data[0] = lio->u.logio.data[0];
399 ea.data[1] = lio->u.logio.data[1];
400 ea.iop[0] = lio->u.logio.iop[0];
401 ea.iop[1] = lio->u.logio.iop[1];
f13515ac
QT		 402 ea.fcport = sp->fcport;
403 ea.sp = sp;
404
405 qla2x00_fcport_event_handler(vha, &ea);
9ba56b95 406
25ff6af1 407 sp->free(sp);
5ff1d584
AV		 408}
409
410int
411qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport,
412 uint16_t *data)
413{
5ff1d584 414 srb_t *sp;
4916392b 415 struct srb_iocb *lio;
5ff1d584
AV		 416 int rval;
417
418 rval = QLA_FUNCTION_FAILED;
726b8548 419 fcport->flags |= FCF_ASYNC_SENT;
9ba56b95 420 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
5ff1d584
AV		 421 if (!sp)
422 goto done;
423
9ba56b95
GM		 424 sp->type = SRB_ADISC_CMD;
425 sp->name = "adisc";
426 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
427
428 lio = &sp->u.iocb_cmd;
3822263e 429 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 430 sp->done = qla2x00_async_adisc_sp_done;
5ff1d584 431 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 432 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
5ff1d584
AV		 433 rval = qla2x00_start_sp(sp);
434 if (rval != QLA_SUCCESS)
435 goto done_free_sp;
436
7c3df132 437 ql_dbg(ql_dbg_disc, vha, 0x206f,
f13515ac
QT		 438 "Async-adisc - hdl=%x loopid=%x portid=%06x %8phC.\n",
439 sp->handle, fcport->loop_id, fcport->d_id.b24, fcport->port_name);
5ff1d584
AV		 440 return rval;
441
442done_free_sp:
25ff6af1 443 sp->free(sp);
5ff1d584 444done:
726b8548 445 fcport->flags &= ~FCF_ASYNC_SENT;
f13515ac 446 qla2x00_post_async_adisc_work(vha, fcport, data);
726b8548
QT		 447 return rval;
448}
449
450static void qla24xx_handle_gnl_done_event(scsi_qla_host_t *vha,
451 struct event_arg *ea)
452{
453 fc_port_t *fcport, *conflict_fcport;
454 struct get_name_list_extended *e;
455 u16 i, n, found = 0, loop_id;
456 port_id_t id;
457 u64 wwn;
a4239945
QT		 458 u16 data[2];
459 u8 current_login_state;
726b8548
QT		 460
461 fcport = ea->fcport;
f352eeb7
QT		 462 ql_dbg(ql_dbg_disc, vha, 0xffff,
463 "%s %8phC DS %d LS rc %d %d login %d|%d rscn %d|%d lid %d\n",
464 __func__, fcport->port_name, fcport->disc_state,
465 fcport->fw_login_state, ea->rc,
466 fcport->login_gen, fcport->last_login_gen,
467 fcport->rscn_gen, fcport->last_rscn_gen, vha->loop_id);
726b8548 468
a4239945
QT		 469 if (fcport->disc_state == DSC_DELETE_PEND)
470 return;
471
726b8548
QT		 472 if (ea->rc) { /* rval */
473 if (fcport->login_retry == 0) {
474 fcport->login_retry = vha->hw->login_retry_count;
83548fe2
QT		 475 ql_dbg(ql_dbg_disc, vha, 0x20de,
476 "GNL failed Port login retry %8phN, retry cnt=%d.\n",
477 fcport->port_name, fcport->login_retry);
726b8548
QT		 478 }
479 return;
480 }
481
482 if (fcport->last_rscn_gen != fcport->rscn_gen) {
83548fe2 483 ql_dbg(ql_dbg_disc, vha, 0x20df,
726b8548
QT		 484 "%s %8phC rscn gen changed rscn %d|%d \n",
485 __func__, fcport->port_name,
486 fcport->last_rscn_gen, fcport->rscn_gen);
487 qla24xx_post_gidpn_work(vha, fcport);
488 return;
489 } else if (fcport->last_login_gen != fcport->login_gen) {
83548fe2 490 ql_dbg(ql_dbg_disc, vha, 0x20e0,
f352eeb7
QT		 491 "%s %8phC login gen changed\n",
492 __func__, fcport->port_name);
726b8548
QT		 493 return;
494 }
495
496 n = ea->data[0] / sizeof(struct get_name_list_extended);
497
83548fe2 498 ql_dbg(ql_dbg_disc, vha, 0x20e1,
726b8548
QT		 499 "%s %d %8phC n %d %02x%02x%02x lid %d \n",
500 __func__, __LINE__, fcport->port_name, n,
501 fcport->d_id.b.domain, fcport->d_id.b.area,
502 fcport->d_id.b.al_pa, fcport->loop_id);
503
504 for (i = 0; i < n; i++) {
505 e = &vha->gnl.l[i];
506 wwn = wwn_to_u64(e->port_name);
507
508 if (memcmp((u8 *)&wwn, fcport->port_name, WWN_SIZE))
509 continue;
510
511 found = 1;
512 id.b.domain = e->port_id[2];
513 id.b.area = e->port_id[1];
514 id.b.al_pa = e->port_id[0];
515 id.b.rsvd_1 = 0;
516
517 loop_id = le16_to_cpu(e->nport_handle);
518 loop_id = (loop_id & 0x7fff);
519
83548fe2
QT		 520 ql_dbg(ql_dbg_disc, vha, 0x20e2,
521 "%s found %8phC CLS [%d|%d] ID[%02x%02x%02x|%02x%02x%02x] lid[%d|%d]\n",
522 __func__, fcport->port_name,
523 e->current_login_state, fcport->fw_login_state,
524 id.b.domain, id.b.area, id.b.al_pa,
525 fcport->d_id.b.domain, fcport->d_id.b.area,
526 fcport->d_id.b.al_pa, loop_id, fcport->loop_id);
726b8548
QT		 527
528 if ((id.b24 != fcport->d_id.b24) ||
529 ((fcport->loop_id != FC_NO_LOOP_ID) &&
530 (fcport->loop_id != loop_id))) {
83548fe2
QT		 531 ql_dbg(ql_dbg_disc, vha, 0x20e3,
532 "%s %d %8phC post del sess\n",
533 __func__, __LINE__, fcport->port_name);
94cff6e1 534 qlt_schedule_sess_for_deletion(fcport);
726b8548
QT		 535 return;
536 }
537
538 fcport->loop_id = loop_id;
539
540 wwn = wwn_to_u64(fcport->port_name);
541 qlt_find_sess_invalidate_other(vha, wwn,
542 id, loop_id, &conflict_fcport);
543
544 if (conflict_fcport) {
545 /*
546 * Another share fcport share the same loop_id &
547 * nport id. Conflict fcport needs to finish
548 * cleanup before this fcport can proceed to login.
549 */
550 conflict_fcport->conflict = fcport;
551 fcport->login_pause = 1;
552 }
553
a5d42f4c
DG		 554 if (fcport->fc4f_nvme)
555 current_login_state = e->current_login_state >> 4;
556 else
557 current_login_state = e->current_login_state & 0xf;
558
559 switch (current_login_state) {
726b8548 560 case DSC_LS_PRLI_COMP:
83548fe2
QT		 561 ql_dbg(ql_dbg_disc, vha, 0x20e4,
562 "%s %d %8phC post gpdb\n",
563 __func__, __LINE__, fcport->port_name);
a4239945
QT		 564
565 if ((e->prli_svc_param_word_3[0] & BIT_4) == 0)
566 fcport->port_type = FCT_INITIATOR;
567 else
568 fcport->port_type = FCT_TARGET;
569
570 data[0] = data[1] = 0;
571 qla2x00_post_async_adisc_work(vha, fcport, data);
726b8548 572 break;
726b8548
QT		 573 case DSC_LS_PORT_UNAVAIL:
574 default:
575 if (fcport->loop_id == FC_NO_LOOP_ID) {
576 qla2x00_find_new_loop_id(vha, fcport);
577 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL;
578 }
83548fe2
QT		 579 ql_dbg(ql_dbg_disc, vha, 0x20e5,
580 "%s %d %8phC\n",
581 __func__, __LINE__, fcport->port_name);
726b8548
QT		 582 qla24xx_fcport_handle_login(vha, fcport);
583 break;
584 }
585 }
586
587 if (!found) {
588 /* fw has no record of this port */
040036bb
QT		 589 for (i = 0; i < n; i++) {
590 e = &vha->gnl.l[i];
591 id.b.domain = e->port_id[0];
592 id.b.area = e->port_id[1];
593 id.b.al_pa = e->port_id[2];
594 id.b.rsvd_1 = 0;
595 loop_id = le16_to_cpu(e->nport_handle);
596
597 if (fcport->d_id.b24 == id.b24) {
598 conflict_fcport =
599 qla2x00_find_fcport_by_wwpn(vha,
600 e->port_name, 0);
601 ql_dbg(ql_dbg_disc, vha, 0x20e6,
602 "%s %d %8phC post del sess\n",
603 __func__, __LINE__,
604 conflict_fcport->port_name);
605 qlt_schedule_sess_for_deletion
94cff6e1 606 (conflict_fcport);
726b8548 607 }
040036bb
QT		 608
609 /* FW already picked this loop id for another fcport */
610 if (fcport->loop_id == loop_id)
611 fcport->loop_id = FC_NO_LOOP_ID;
726b8548
QT		 612 }
613 qla24xx_fcport_handle_login(vha, fcport);
614 }
615} /* gnl_event */
616
617static void
25ff6af1 618qla24xx_async_gnl_sp_done(void *s, int res)
726b8548 619{
25ff6af1
JC		 620 struct srb *sp = s;
621 struct scsi_qla_host *vha = sp->vha;
726b8548
QT		 622 unsigned long flags;
623 struct fc_port *fcport = NULL, *tf;
624 u16 i, n = 0, loop_id;
625 struct event_arg ea;
626 struct get_name_list_extended *e;
627 u64 wwn;
628 struct list_head h;
a4239945 629 bool found = false;
726b8548 630
83548fe2 631 ql_dbg(ql_dbg_disc, vha, 0x20e7,
726b8548
QT		 632 "Async done-%s res %x mb[1]=%x mb[2]=%x \n",
633 sp->name, res, sp->u.iocb_cmd.u.mbx.in_mb[1],
634 sp->u.iocb_cmd.u.mbx.in_mb[2]);
635
636 memset(&ea, 0, sizeof(ea));
637 ea.sp = sp;
638 ea.rc = res;
639 ea.event = FCME_GNL_DONE;
640
641 if (sp->u.iocb_cmd.u.mbx.in_mb[1] >=
642 sizeof(struct get_name_list_extended)) {
643 n = sp->u.iocb_cmd.u.mbx.in_mb[1] /
644 sizeof(struct get_name_list_extended);
645 ea.data[0] = sp->u.iocb_cmd.u.mbx.in_mb[1]; /* amnt xfered */
646 }
647
648 for (i = 0; i < n; i++) {
649 e = &vha->gnl.l[i];
650 loop_id = le16_to_cpu(e->nport_handle);
651 /* mask out reserve bit */
652 loop_id = (loop_id & 0x7fff);
653 set_bit(loop_id, vha->hw->loop_id_map);
654 wwn = wwn_to_u64(e->port_name);
655
83548fe2 656 ql_dbg(ql_dbg_disc + ql_dbg_verbose, vha, 0x20e8,
726b8548
QT		 657 "%s %8phC %02x:%02x:%02x state %d/%d lid %x \n",
658 __func__, (void *)&wwn, e->port_id[2], e->port_id[1],
659 e->port_id[0], e->current_login_state, e->last_login_state,
660 (loop_id & 0x7fff));
661 }
662
663 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
664 vha->gnl.sent = 0;
665
666 INIT_LIST_HEAD(&h);
667 fcport = tf = NULL;
668 if (!list_empty(&vha->gnl.fcports))
669 list_splice_init(&vha->gnl.fcports, &h);
670
671 list_for_each_entry_safe(fcport, tf, &h, gnl_entry) {
672 list_del_init(&fcport->gnl_entry);
6d674927 673 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
726b8548
QT		 674 ea.fcport = fcport;
675
676 qla2x00_fcport_event_handler(vha, &ea);
677 }
678
a4239945
QT		 679 /* create new fcport if fw has knowledge of new sessions */
680 for (i = 0; i < n; i++) {
681 port_id_t id;
682 u64 wwnn;
683
684 e = &vha->gnl.l[i];
685 wwn = wwn_to_u64(e->port_name);
686
687 found = false;
688 list_for_each_entry_safe(fcport, tf, &vha->vp_fcports, list) {
689 if (!memcmp((u8 *)&wwn, fcport->port_name,
690 WWN_SIZE)) {
691 found = true;
692 break;
693 }
694 }
695
cf055fb0 696 id.b.domain = e->port_id[2];
a4239945 697 id.b.area = e->port_id[1];
cf055fb0 698 id.b.al_pa = e->port_id[0];
a4239945
QT		 699 id.b.rsvd_1 = 0;
700
701 if (!found && wwn && !IS_SW_RESV_ADDR(id)) {
702 ql_dbg(ql_dbg_disc, vha, 0x2065,
cf055fb0
QT		 703 "%s %d %8phC %06x post new sess\n",
704 __func__, __LINE__, (u8 *)&wwn, id.b24);
a4239945
QT		 705 wwnn = wwn_to_u64(e->node_name);
706 qla24xx_post_newsess_work(vha, &id, (u8 *)&wwn,
707 (u8 *)&wwnn, NULL, FC4_TYPE_UNKNOWN);
708 }
709 }
710
726b8548
QT		 711 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
712
25ff6af1 713 sp->free(sp);
726b8548
QT		 714}
715
716int qla24xx_async_gnl(struct scsi_qla_host *vha, fc_port_t *fcport)
717{
718 srb_t *sp;
719 struct srb_iocb *mbx;
720 int rval = QLA_FUNCTION_FAILED;
721 unsigned long flags;
722 u16 *mb;
723
3dbec59b
QT		 724 if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT))
725 return rval;
726b8548 726
83548fe2 727 ql_dbg(ql_dbg_disc, vha, 0x20d9,
726b8548
QT		 728 "Async-gnlist WWPN %8phC \n", fcport->port_name);
729
730 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
726b8548
QT		 731 fcport->disc_state = DSC_GNL;
732 fcport->last_rscn_gen = fcport->rscn_gen;
733 fcport->last_login_gen = fcport->login_gen;
734
735 list_add_tail(&fcport->gnl_entry, &vha->gnl.fcports);
736 if (vha->gnl.sent) {
737 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
3dbec59b 738 return QLA_SUCCESS;
726b8548
QT		 739 }
740 vha->gnl.sent = 1;
741 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
742
743 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
744 if (!sp)
745 goto done;
3dbec59b
QT		 746
747 fcport->flags |= FCF_ASYNC_SENT;
726b8548
QT		 748 sp->type = SRB_MB_IOCB;
749 sp->name = "gnlist";
750 sp->gen1 = fcport->rscn_gen;
751 sp->gen2 = fcport->login_gen;
752
753 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha)+2);
754
755 mb = sp->u.iocb_cmd.u.mbx.out_mb;
756 mb[0] = MBC_PORT_NODE_NAME_LIST;
757 mb[1] = BIT_2 | BIT_3;
758 mb[2] = MSW(vha->gnl.ldma);
759 mb[3] = LSW(vha->gnl.ldma);
760 mb[6] = MSW(MSD(vha->gnl.ldma));
761 mb[7] = LSW(MSD(vha->gnl.ldma));
762 mb[8] = vha->gnl.size;
763 mb[9] = vha->vp_idx;
764
765 mbx = &sp->u.iocb_cmd;
766 mbx->timeout = qla2x00_async_iocb_timeout;
767
768 sp->done = qla24xx_async_gnl_sp_done;
769
770 rval = qla2x00_start_sp(sp);
771 if (rval != QLA_SUCCESS)
772 goto done_free_sp;
773
83548fe2
QT		 774 ql_dbg(ql_dbg_disc, vha, 0x20da,
775 "Async-%s - OUT WWPN %8phC hndl %x\n",
776 sp->name, fcport->port_name, sp->handle);
726b8548
QT		 777
778 return rval;
779
780done_free_sp:
25ff6af1 781 sp->free(sp);
726b8548 782 fcport->flags &= ~FCF_ASYNC_SENT;
3dbec59b 783done:
726b8548
QT		 784 return rval;
785}
786
787int qla24xx_post_gnl_work(struct scsi_qla_host *vha, fc_port_t *fcport)
788{
789 struct qla_work_evt *e;
790
791 e = qla2x00_alloc_work(vha, QLA_EVT_GNL);
792 if (!e)
793 return QLA_FUNCTION_FAILED;
794
795 e->u.fcport.fcport = fcport;
6d674927 796 fcport->flags |= FCF_ASYNC_ACTIVE;
726b8548
QT		 797 return qla2x00_post_work(vha, e);
798}
799
800static
25ff6af1 801void qla24xx_async_gpdb_sp_done(void *s, int res)
726b8548 802{
25ff6af1
JC		 803 struct srb *sp = s;
804 struct scsi_qla_host *vha = sp->vha;
726b8548 805 struct qla_hw_data *ha = vha->hw;
726b8548
QT		 806 fc_port_t *fcport = sp->fcport;
807 u16 *mb = sp->u.iocb_cmd.u.mbx.in_mb;
726b8548
QT		 808 struct event_arg ea;
809
83548fe2 810 ql_dbg(ql_dbg_disc, vha, 0x20db,
726b8548
QT		 811 "Async done-%s res %x, WWPN %8phC mb[1]=%x mb[2]=%x \n",
812 sp->name, res, fcport->port_name, mb[1], mb[2]);
813
6d674927 814 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
726b8548 815
726b8548
QT		 816 memset(&ea, 0, sizeof(ea));
817 ea.event = FCME_GPDB_DONE;
726b8548
QT		 818 ea.fcport = fcport;
819 ea.sp = sp;
820
821 qla2x00_fcport_event_handler(vha, &ea);
822
823 dma_pool_free(ha->s_dma_pool, sp->u.iocb_cmd.u.mbx.in,
824 sp->u.iocb_cmd.u.mbx.in_dma);
825
25ff6af1 826 sp->free(sp);
726b8548
QT		 827}
828
a5d42f4c
DG		 829static int qla24xx_post_prli_work(struct scsi_qla_host *vha, fc_port_t *fcport)
830{
831 struct qla_work_evt *e;
832
833 e = qla2x00_alloc_work(vha, QLA_EVT_PRLI);
834 if (!e)
835 return QLA_FUNCTION_FAILED;
836
837 e->u.fcport.fcport = fcport;
838
839 return qla2x00_post_work(vha, e);
840}
841
842static void
843qla2x00_async_prli_sp_done(void *ptr, int res)
844{
845 srb_t *sp = ptr;
846 struct scsi_qla_host *vha = sp->vha;
847 struct srb_iocb *lio = &sp->u.iocb_cmd;
848 struct event_arg ea;
849
850 ql_dbg(ql_dbg_disc, vha, 0x2129,
851 "%s %8phC res %d \n", __func__,
852 sp->fcport->port_name, res);
853
854 sp->fcport->flags &= ~FCF_ASYNC_SENT;
855
856 if (!test_bit(UNLOADING, &vha->dpc_flags)) {
857 memset(&ea, 0, sizeof(ea));
858 ea.event = FCME_PRLI_DONE;
859 ea.fcport = sp->fcport;
860 ea.data[0] = lio->u.logio.data[0];
861 ea.data[1] = lio->u.logio.data[1];
862 ea.iop[0] = lio->u.logio.iop[0];
863 ea.iop[1] = lio->u.logio.iop[1];
864 ea.sp = sp;
865
866 qla2x00_fcport_event_handler(vha, &ea);
867 }
868
869 sp->free(sp);
870}
871
872int
873qla24xx_async_prli(struct scsi_qla_host *vha, fc_port_t *fcport)
874{
875 srb_t *sp;
876 struct srb_iocb *lio;
877 int rval = QLA_FUNCTION_FAILED;
878
879 if (!vha->flags.online)
880 return rval;
881
882 if (fcport->fw_login_state == DSC_LS_PLOGI_PEND ||
a5d42f4c
DG		 883 fcport->fw_login_state == DSC_LS_PRLI_PEND)
884 return rval;
885
886 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
887 if (!sp)
888 return rval;
889
890 fcport->flags |= FCF_ASYNC_SENT;
891 fcport->logout_completed = 0;
892
893 sp->type = SRB_PRLI_CMD;
894 sp->name = "prli";
895 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
896
897 lio = &sp->u.iocb_cmd;
898 lio->timeout = qla2x00_async_iocb_timeout;
899 sp->done = qla2x00_async_prli_sp_done;
900 lio->u.logio.flags = 0;
901
902 if (fcport->fc4f_nvme)
903 lio->u.logio.flags |= SRB_LOGIN_NVME_PRLI;
904
905 rval = qla2x00_start_sp(sp);
906 if (rval != QLA_SUCCESS) {
a5d42f4c
DG		 907 fcport->flags |= FCF_LOGIN_NEEDED;
908 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
909 goto done_free_sp;
910 }
911
912 ql_dbg(ql_dbg_disc, vha, 0x211b,
913 "Async-prli - %8phC hdl=%x, loopid=%x portid=%06x retries=%d.\n",
914 fcport->port_name, sp->handle, fcport->loop_id,
915 fcport->d_id.b24, fcport->login_retry);
916
917 return rval;
918
919done_free_sp:
920 sp->free(sp);
921 fcport->flags &= ~FCF_ASYNC_SENT;
922 return rval;
923}
924
a07fc0a4 925int qla24xx_post_gpdb_work(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt)
726b8548
QT		 926{
927 struct qla_work_evt *e;
928
929 e = qla2x00_alloc_work(vha, QLA_EVT_GPDB);
930 if (!e)
931 return QLA_FUNCTION_FAILED;
932
933 e->u.fcport.fcport = fcport;
934 e->u.fcport.opt = opt;
6d674927 935 fcport->flags |= FCF_ASYNC_ACTIVE;
726b8548
QT		 936 return qla2x00_post_work(vha, e);
937}
938
939int qla24xx_async_gpdb(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt)
940{
941 srb_t *sp;
942 struct srb_iocb *mbx;
943 int rval = QLA_FUNCTION_FAILED;
944 u16 *mb;
945 dma_addr_t pd_dma;
946 struct port_database_24xx *pd;
947 struct qla_hw_data *ha = vha->hw;
948
3dbec59b
QT		 949 if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT))
950 return rval;
726b8548 951
726b8548
QT		 952 fcport->disc_state = DSC_GPDB;
953
954 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
955 if (!sp)
956 goto done;
957
3dbec59b 958 fcport->flags |= FCF_ASYNC_SENT;
e0824e69
JC		 959 sp->type = SRB_MB_IOCB;
960 sp->name = "gpdb";
961 sp->gen1 = fcport->rscn_gen;
962 sp->gen2 = fcport->login_gen;
963 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
964
08eb7f45 965 pd = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
726b8548 966 if (pd == NULL) {
83548fe2
QT		 967 ql_log(ql_log_warn, vha, 0xd043,
968 "Failed to allocate port database structure.\n");
726b8548
QT		 969 goto done_free_sp;
970 }
726b8548 971
726b8548
QT		 972 mb = sp->u.iocb_cmd.u.mbx.out_mb;
973 mb[0] = MBC_GET_PORT_DATABASE;
974 mb[1] = fcport->loop_id;
975 mb[2] = MSW(pd_dma);
976 mb[3] = LSW(pd_dma);
977 mb[6] = MSW(MSD(pd_dma));
978 mb[7] = LSW(MSD(pd_dma));
979 mb[9] = vha->vp_idx;
980 mb[10] = opt;
981
982 mbx = &sp->u.iocb_cmd;
983 mbx->timeout = qla2x00_async_iocb_timeout;
984 mbx->u.mbx.in = (void *)pd;
985 mbx->u.mbx.in_dma = pd_dma;
986
987 sp->done = qla24xx_async_gpdb_sp_done;
988
989 rval = qla2x00_start_sp(sp);
990 if (rval != QLA_SUCCESS)
991 goto done_free_sp;
992
83548fe2
QT		 993 ql_dbg(ql_dbg_disc, vha, 0x20dc,
994 "Async-%s %8phC hndl %x opt %x\n",
995 sp->name, fcport->port_name, sp->handle, opt);
726b8548
QT		 996
997 return rval;
998
999done_free_sp:
1000 if (pd)
1001 dma_pool_free(ha->s_dma_pool, pd, pd_dma);
1002
25ff6af1 1003 sp->free(sp);
726b8548 1004 fcport->flags &= ~FCF_ASYNC_SENT;
3dbec59b 1005done:
726b8548 1006 qla24xx_post_gpdb_work(vha, fcport, opt);
5ff1d584
AV		 1007 return rval;
1008}
1009
726b8548 1010static
a4239945 1011void __qla24xx_handle_gpdb_event(scsi_qla_host_t *vha, struct event_arg *ea)
726b8548 1012{
726b8548
QT		 1013 unsigned long flags;
1014
726b8548 1015 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
f13515ac 1016 ea->fcport->login_gen++;
726b8548
QT		 1017 ea->fcport->deleted = 0;
1018 ea->fcport->logout_on_delete = 1;
1019
1020 if (!ea->fcport->login_succ && !IS_SW_RESV_ADDR(ea->fcport->d_id)) {
1021 vha->fcport_count++;
1022 ea->fcport->login_succ = 1;
1023
1024 if (!IS_IIDMA_CAPABLE(vha->hw) ||
1025 !vha->hw->flags.gpsc_supported) {
83548fe2 1026 ql_dbg(ql_dbg_disc, vha, 0x20d6,
726b8548 1027 "%s %d %8phC post upd_fcport fcp_cnt %d\n",
a4239945 1028 __func__, __LINE__, ea->fcport->port_name,
726b8548
QT		 1029 vha->fcport_count);
1030
a4239945 1031 qla24xx_post_upd_fcport_work(vha, ea->fcport);
726b8548 1032 } else {
a4239945
QT		 1033 if (ea->fcport->id_changed) {
1034 ea->fcport->id_changed = 0;
1035 ql_dbg(ql_dbg_disc, vha, 0x20d7,
1036 "%s %d %8phC post gfpnid fcp_cnt %d\n",
1037 __func__, __LINE__, ea->fcport->port_name,
1038 vha->fcport_count);
1039 qla24xx_post_gfpnid_work(vha, ea->fcport);
1040 } else {
1041 ql_dbg(ql_dbg_disc, vha, 0x20d7,
1042 "%s %d %8phC post gpsc fcp_cnt %d\n",
1043 __func__, __LINE__, ea->fcport->port_name,
1044 vha->fcport_count);
1045 qla24xx_post_gpsc_work(vha, ea->fcport);
1046 }
726b8548 1047 }
414d9ff3
QT		 1048 } else if (ea->fcport->login_succ) {
1049 /*
1050 * We have an existing session. A late RSCN delivery
1051 * must have triggered the session to be re-validate.
a4239945 1052 * Session is still valid.
414d9ff3 1053 */
5ef696aa
QT		 1054 ql_dbg(ql_dbg_disc, vha, 0x20d6,
1055 "%s %d %8phC session revalidate success\n",
a4239945 1056 __func__, __LINE__, ea->fcport->port_name);
8a7eac2f 1057 ea->fcport->disc_state = DSC_LOGIN_COMPLETE;
726b8548
QT		 1058 }
1059 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
a4239945
QT		 1060}
1061
1062static
1063void qla24xx_handle_gpdb_event(scsi_qla_host_t *vha, struct event_arg *ea)
1064{
a4239945
QT		 1065 fc_port_t *fcport = ea->fcport;
1066 struct port_database_24xx *pd;
1067 struct srb *sp = ea->sp;
1068
1069 pd = (struct port_database_24xx *)sp->u.iocb_cmd.u.mbx.in;
1070
1071 fcport->flags &= ~FCF_ASYNC_SENT;
1072
1073 ql_dbg(ql_dbg_disc, vha, 0x20d2,
f352eeb7
QT		 1074 "%s %8phC DS %d LS %d rc %d\n", __func__, fcport->port_name,
1075 fcport->disc_state, pd->current_login_state, ea->rc);
a4239945
QT		 1076
1077 if (fcport->disc_state == DSC_DELETE_PEND)
1078 return;
726b8548 1079
a4239945
QT		 1080 switch (pd->current_login_state) {
1081 case PDS_PRLI_COMPLETE:
1082 __qla24xx_parse_gpdb(vha, fcport, pd);
1083 break;
1084 case PDS_PLOGI_PENDING:
1085 case PDS_PLOGI_COMPLETE:
1086 case PDS_PRLI_PENDING:
1087 case PDS_PRLI2_PENDING:
1088 ql_dbg(ql_dbg_disc, vha, 0x20d5, "%s %d %8phC relogin needed\n",
1089 __func__, __LINE__, fcport->port_name);
1090 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1091 return;
1092 case PDS_LOGO_PENDING:
1093 case PDS_PORT_UNAVAILABLE:
1094 default:
1095 ql_dbg(ql_dbg_disc, vha, 0x20d5, "%s %d %8phC post del sess\n",
1096 __func__, __LINE__, fcport->port_name);
d8630bb9 1097 qlt_schedule_sess_for_deletion(fcport);
a4239945
QT		 1098 return;
1099 }
1100 __qla24xx_handle_gpdb_event(vha, ea);
1101} /* gpdb event */
9cd883f0
QT		 1102
1103static void qla_chk_n2n_b4_login(struct scsi_qla_host *vha, fc_port_t *fcport)
1104{
1105 u8 login = 0;
040036bb 1106 int rc;
9cd883f0
QT		 1107
1108 if (qla_tgt_mode_enabled(vha))
1109 return;
1110
1111 if (qla_dual_mode_enabled(vha)) {
1112 if (N2N_TOPO(vha->hw)) {
1113 u64 mywwn, wwn;
1114
1115 mywwn = wwn_to_u64(vha->port_name);
1116 wwn = wwn_to_u64(fcport->port_name);
1117 if (mywwn > wwn)
1118 login = 1;
1119 else if ((fcport->fw_login_state == DSC_LS_PLOGI_COMP)
1120 && time_after_eq(jiffies,
1121 fcport->plogi_nack_done_deadline))
1122 login = 1;
1123 } else {
1124 login = 1;
1125 }
1126 } else {
1127 /* initiator mode */
1128 login = 1;
1129 }
1130
1131 if (login) {
040036bb
QT		 1132 if (fcport->loop_id == FC_NO_LOOP_ID) {
1133 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL;
1134 rc = qla2x00_find_new_loop_id(vha, fcport);
1135 if (rc) {
1136 ql_dbg(ql_dbg_disc, vha, 0x20e6,
1137 "%s %d %8phC post del sess - out of loopid\n",
1138 __func__, __LINE__, fcport->port_name);
1139 fcport->scan_state = 0;
94cff6e1 1140 qlt_schedule_sess_for_deletion(fcport);
040036bb
QT		 1141 return;
1142 }
1143 }
9cd883f0
QT		 1144 ql_dbg(ql_dbg_disc, vha, 0x20bf,
1145 "%s %d %8phC post login\n",
1146 __func__, __LINE__, fcport->port_name);
9cd883f0
QT		 1147 qla2x00_post_async_login_work(vha, fcport, NULL);
1148 }
1149}
1150
726b8548
QT		 1151int qla24xx_fcport_handle_login(struct scsi_qla_host *vha, fc_port_t *fcport)
1152{
f13515ac 1153 u16 data[2];
a4239945 1154 u64 wwn;
726b8548 1155
83548fe2 1156 ql_dbg(ql_dbg_disc, vha, 0x20d8,
f352eeb7 1157 "%s %8phC DS %d LS %d P %d fl %x confl %p rscn %d|%d login %d retry %d lid %d scan %d\n",
726b8548
QT		 1158 __func__, fcport->port_name, fcport->disc_state,
1159 fcport->fw_login_state, fcport->login_pause, fcport->flags,
1160 fcport->conflict, fcport->last_rscn_gen, fcport->rscn_gen,
f352eeb7 1161 fcport->login_gen, fcport->login_retry,
a4239945 1162 fcport->loop_id, fcport->scan_state);
726b8548 1163
a4239945
QT		 1164 if (fcport->login_retry == 0)
1165 return 0;
1166
1167 if (fcport->scan_state != QLA_FCPORT_FOUND)
1168 return 0;
726b8548
QT		 1169
1170 if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) ||
726b8548
QT		 1171 (fcport->fw_login_state == DSC_LS_PRLI_PEND))
1172 return 0;
1173
5b33469a 1174 if (fcport->fw_login_state == DSC_LS_PLOGI_COMP) {
9cd883f0
QT		 1175 if (time_before_eq(jiffies, fcport->plogi_nack_done_deadline)) {
1176 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5b33469a 1177 return 0;
9cd883f0 1178 }
5b33469a
QT		 1179 }
1180
726b8548
QT		 1181 /* for pure Target Mode. Login will not be initiated */
1182 if (vha->host->active_mode == MODE_TARGET)
1183 return 0;
1184
1185 if (fcport->flags & FCF_ASYNC_SENT) {
1186 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1187 return 0;
1188 }
1189
a4239945
QT		 1190 fcport->login_retry--;
1191
726b8548
QT		 1192 switch (fcport->disc_state) {
1193 case DSC_DELETED:
a4239945
QT		 1194 wwn = wwn_to_u64(fcport->node_name);
1195 if (wwn == 0) {
1196 ql_dbg(ql_dbg_disc, vha, 0xffff,
1197 "%s %d %8phC post GNNID\n",
1198 __func__, __LINE__, fcport->port_name);
1199 qla24xx_post_gnnid_work(vha, fcport);
1200 } else if (fcport->loop_id == FC_NO_LOOP_ID) {
83548fe2
QT		 1201 ql_dbg(ql_dbg_disc, vha, 0x20bd,
1202 "%s %d %8phC post gnl\n",
1203 __func__, __LINE__, fcport->port_name);
5d3300a9 1204 qla24xx_post_gnl_work(vha, fcport);
726b8548 1205 } else {
9cd883f0 1206 qla_chk_n2n_b4_login(vha, fcport);
726b8548
QT		 1207 }
1208 break;
1209
1210 case DSC_GNL:
1211 if (fcport->login_pause) {
1212 fcport->last_rscn_gen = fcport->rscn_gen;
1213 fcport->last_login_gen = fcport->login_gen;
1214 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1215 break;
1216 }
1217
9cd883f0 1218 qla_chk_n2n_b4_login(vha, fcport);
726b8548
QT		 1219 break;
1220
1221 case DSC_LOGIN_FAILED:
83548fe2
QT		 1222 ql_dbg(ql_dbg_disc, vha, 0x20d0,
1223 "%s %d %8phC post gidpn\n",
1224 __func__, __LINE__, fcport->port_name);
9cd883f0
QT		 1225 if (N2N_TOPO(vha->hw))
1226 qla_chk_n2n_b4_login(vha, fcport);
1227 else
1228 qla24xx_post_gidpn_work(vha, fcport);
726b8548
QT		 1229 break;
1230
1231 case DSC_LOGIN_COMPLETE:
1232 /* recheck login state */
83548fe2 1233 ql_dbg(ql_dbg_disc, vha, 0x20d1,
f13515ac 1234 "%s %d %8phC post adisc\n",
83548fe2 1235 __func__, __LINE__, fcport->port_name);
f13515ac
QT		 1236 data[0] = data[1] = 0;
1237 qla2x00_post_async_adisc_work(vha, fcport, data);
726b8548
QT		 1238 break;
1239
1cbc0efc
DT		 1240 case DSC_LOGIN_PEND:
1241 if (fcport->fw_login_state == DSC_LS_PLOGI_COMP)
1242 qla24xx_post_prli_work(vha, fcport);
1243 break;
1244
726b8548
QT		 1245 default:
1246 break;
1247 }
1248
1249 return 0;
1250}
1251
1252static
1253void qla24xx_handle_rscn_event(fc_port_t *fcport, struct event_arg *ea)
1254{
1255 fcport->rscn_gen++;
1256
83548fe2
QT		 1257 ql_dbg(ql_dbg_disc, fcport->vha, 0x210c,
1258 "%s %8phC DS %d LS %d\n",
1259 __func__, fcport->port_name, fcport->disc_state,
1260 fcport->fw_login_state);
726b8548
QT		 1261
1262 if (fcport->flags & FCF_ASYNC_SENT)
1263 return;
1264
1265 switch (fcport->disc_state) {
1266 case DSC_DELETED:
1267 case DSC_LOGIN_COMPLETE:
5ef696aa 1268 qla24xx_post_gpnid_work(fcport->vha, &ea->id);
726b8548 1269 break;
726b8548
QT		 1270 default:
1271 break;
1272 }
1273}
1274
1275int qla24xx_post_newsess_work(struct scsi_qla_host *vha, port_id_t *id,
a4239945 1276 u8 *port_name, u8 *node_name, void *pla, u8 fc4_type)
726b8548
QT		 1277{
1278 struct qla_work_evt *e;
1279 e = qla2x00_alloc_work(vha, QLA_EVT_NEW_SESS);
1280 if (!e)
1281 return QLA_FUNCTION_FAILED;
1282
1283 e->u.new_sess.id = *id;
1284 e->u.new_sess.pla = pla;
a4239945 1285 e->u.new_sess.fc4_type = fc4_type;
726b8548 1286 memcpy(e->u.new_sess.port_name, port_name, WWN_SIZE);
a4239945
QT		 1287 if (node_name)
1288 memcpy(e->u.new_sess.node_name, node_name, WWN_SIZE);
726b8548
QT		 1289
1290 return qla2x00_post_work(vha, e);
1291}
1292
726b8548
QT		 1293static
1294void qla24xx_handle_relogin_event(scsi_qla_host_t *vha,
1295 struct event_arg *ea)
1296{
1297 fc_port_t *fcport = ea->fcport;
1298
83548fe2
QT		 1299 ql_dbg(ql_dbg_disc, vha, 0x2102,
1300 "%s %8phC DS %d LS %d P %d del %d cnfl %p rscn %d|%d login %d|%d fl %x\n",
1301 __func__, fcport->port_name, fcport->disc_state,
1302 fcport->fw_login_state, fcport->login_pause,
1303 fcport->deleted, fcport->conflict,
1304 fcport->last_rscn_gen, fcport->rscn_gen,
1305 fcport->last_login_gen, fcport->login_gen,
1306 fcport->flags);
726b8548
QT		 1307
1308 if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) ||
726b8548
QT		 1309 (fcport->fw_login_state == DSC_LS_PRLI_PEND))
1310 return;
1311
5b33469a 1312 if (fcport->fw_login_state == DSC_LS_PLOGI_COMP) {
9cd883f0
QT		 1313 if (time_before_eq(jiffies, fcport->plogi_nack_done_deadline)) {
1314 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5b33469a 1315 return;
9cd883f0 1316 }
5b33469a
QT		 1317 }
1318
726b8548
QT		 1319 if (fcport->flags & FCF_ASYNC_SENT) {
1320 fcport->login_retry++;
1321 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1322 return;
1323 }
1324
1325 if (fcport->disc_state == DSC_DELETE_PEND) {
1326 fcport->login_retry++;
1327 return;
1328 }
1329
1330 if (fcport->last_rscn_gen != fcport->rscn_gen) {
83548fe2 1331 ql_dbg(ql_dbg_disc, vha, 0x20e9, "%s %d %8phC post gidpn\n",
726b8548
QT		 1332 __func__, __LINE__, fcport->port_name);
1333
5d3300a9 1334 qla24xx_post_gidpn_work(vha, fcport);
726b8548
QT		 1335 return;
1336 }
1337
1338 qla24xx_fcport_handle_login(vha, fcport);
1339}
1340
41dc529a 1341void qla2x00_fcport_event_handler(scsi_qla_host_t *vha, struct event_arg *ea)
726b8548 1342{
f352eeb7 1343 fc_port_t *f, *tf;
41dc529a 1344 uint32_t id = 0, mask, rid;
f352eeb7 1345 unsigned long flags;
726b8548 1346
b98ae0d7 1347 switch (ea->event) {
b98ae0d7
QT		 1348 case FCME_RSCN:
1349 case FCME_GIDPN_DONE:
1350 case FCME_GPSC_DONE:
1351 case FCME_GPNID_DONE:
a4239945 1352 case FCME_GNNID_DONE:
b98ae0d7
QT		 1353 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
1354 test_bit(LOOP_RESYNC_ACTIVE, &vha->dpc_flags))
1355 return;
1356 break;
1357 default:
1358 break;
1359 }
1360
726b8548
QT		 1361 switch (ea->event) {
1362 case FCME_RELOGIN:
1363 if (test_bit(UNLOADING, &vha->dpc_flags))
1364 return;
5ff1d584 1365
726b8548
QT		 1366 qla24xx_handle_relogin_event(vha, ea);
1367 break;
1368 case FCME_RSCN:
1369 if (test_bit(UNLOADING, &vha->dpc_flags))
1370 return;
41dc529a
QT		 1371 switch (ea->id.b.rsvd_1) {
1372 case RSCN_PORT_ADDR:
f352eeb7
QT		 1373 spin_lock_irqsave(&vha->work_lock, flags);
1374 if (vha->scan.scan_flags == 0) {
1375 ql_dbg(ql_dbg_disc, vha, 0xffff,
1376 "%s: schedule\n", __func__);
1377 vha->scan.scan_flags |= SF_QUEUED;
1378 schedule_delayed_work(&vha->scan.scan_work, 5);
41dc529a 1379 }
f352eeb7
QT		 1380 spin_unlock_irqrestore(&vha->work_lock, flags);
1381
41dc529a
QT		 1382 break;
1383 case RSCN_AREA_ADDR:
1384 case RSCN_DOM_ADDR:
1385 if (ea->id.b.rsvd_1 == RSCN_AREA_ADDR) {
1386 mask = 0xffff00;
83548fe2
QT		 1387 ql_dbg(ql_dbg_async, vha, 0x5044,
1388 "RSCN: Area 0x%06x was affected\n",
1389 ea->id.b24);
41dc529a
QT		 1390 } else {
1391 mask = 0xff0000;
83548fe2
QT		 1392 ql_dbg(ql_dbg_async, vha, 0x507a,
1393 "RSCN: Domain 0x%06x was affected\n",
1394 ea->id.b24);
41dc529a 1395 }
726b8548 1396
41dc529a
QT		 1397 rid = ea->id.b24 & mask;
1398 list_for_each_entry_safe(f, tf, &vha->vp_fcports,
1399 list) {
1400 id = f->d_id.b24 & mask;
1401 if (rid == id) {
1402 ea->fcport = f;
1403 qla24xx_handle_rscn_event(f, ea);
1404 }
726b8548 1405 }
41dc529a
QT		 1406 break;
1407 case RSCN_FAB_ADDR:
1408 default:
83548fe2
QT		 1409 ql_log(ql_log_warn, vha, 0xd045,
1410 "RSCN: Fabric was affected. Addr format %d\n",
1411 ea->id.b.rsvd_1);
41dc529a
QT		 1412 qla2x00_mark_all_devices_lost(vha, 1);
1413 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1414 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
726b8548
QT		 1415 }
1416 break;
1417 case FCME_GIDPN_DONE:
1418 qla24xx_handle_gidpn_event(vha, ea);
1419 break;
1420 case FCME_GNL_DONE:
1421 qla24xx_handle_gnl_done_event(vha, ea);
1422 break;
1423 case FCME_GPSC_DONE:
a4239945 1424 qla24xx_handle_gpsc_event(vha, ea);
726b8548
QT		 1425 break;
1426 case FCME_PLOGI_DONE: /* Initiator side sent LLIOCB */
1427 qla24xx_handle_plogi_done_event(vha, ea);
1428 break;
a5d42f4c
DG		 1429 case FCME_PRLI_DONE:
1430 qla24xx_handle_prli_done_event(vha, ea);
1431 break;
726b8548
QT		 1432 case FCME_GPDB_DONE:
1433 qla24xx_handle_gpdb_event(vha, ea);
1434 break;
1435 case FCME_GPNID_DONE:
1436 qla24xx_handle_gpnid_event(vha, ea);
1437 break;
d3bae931
DG		 1438 case FCME_GFFID_DONE:
1439 qla24xx_handle_gffid_event(vha, ea);
1440 break;
f13515ac
QT		 1441 case FCME_ADISC_DONE:
1442 qla24xx_handle_adisc_event(vha, ea);
1443 break;
a4239945
QT		 1444 case FCME_GNNID_DONE:
1445 qla24xx_handle_gnnid_event(vha, ea);
1446 break;
1447 case FCME_GFPNID_DONE:
1448 qla24xx_handle_gfpnid_event(vha, ea);
1449 break;
726b8548
QT		 1450 default:
1451 BUG_ON(1);
1452 break;
1453 }
5ff1d584
AV		 1454}
1455
3822263e 1456static void
faef62d1 1457qla2x00_tmf_iocb_timeout(void *data)
3822263e 1458{
25ff6af1 1459 srb_t *sp = data;
faef62d1 1460 struct srb_iocb *tmf = &sp->u.iocb_cmd;
3822263e 1461
faef62d1
AB		 1462 tmf->u.tmf.comp_status = CS_TIMEOUT;
1463 complete(&tmf->u.tmf.comp);
1464}
9ba56b95 1465
faef62d1 1466static void
25ff6af1 1467qla2x00_tmf_sp_done(void *ptr, int res)
faef62d1 1468{
25ff6af1 1469 srb_t *sp = ptr;
faef62d1 1470 struct srb_iocb *tmf = &sp->u.iocb_cmd;
25ff6af1 1471
faef62d1 1472 complete(&tmf->u.tmf.comp);
3822263e
MI		 1473}
1474
1475int
faef62d1 1476qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t flags, uint32_t lun,
3822263e
MI		 1477 uint32_t tag)
1478{
1479 struct scsi_qla_host *vha = fcport->vha;
faef62d1 1480 struct srb_iocb *tm_iocb;
3822263e 1481 srb_t *sp;
faef62d1 1482 int rval = QLA_FUNCTION_FAILED;
3822263e 1483
9ba56b95 1484 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
3822263e
MI		 1485 if (!sp)
1486 goto done;
1487
faef62d1 1488 tm_iocb = &sp->u.iocb_cmd;
9ba56b95
GM		 1489 sp->type = SRB_TM_CMD;
1490 sp->name = "tmf";
faef62d1
AB		 1491 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
1492 tm_iocb->u.tmf.flags = flags;
1493 tm_iocb->u.tmf.lun = lun;
1494 tm_iocb->u.tmf.data = tag;
1495 sp->done = qla2x00_tmf_sp_done;
1496 tm_iocb->timeout = qla2x00_tmf_iocb_timeout;
1497 init_completion(&tm_iocb->u.tmf.comp);
3822263e
MI		 1498
1499 rval = qla2x00_start_sp(sp);
1500 if (rval != QLA_SUCCESS)
1501 goto done_free_sp;
1502
7c3df132 1503 ql_dbg(ql_dbg_taskm, vha, 0x802f,
cfb0919c
CD		 1504 "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
1505 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
1506 fcport->d_id.b.area, fcport->d_id.b.al_pa);
faef62d1
AB		 1507
1508 wait_for_completion(&tm_iocb->u.tmf.comp);
1509
1510 rval = tm_iocb->u.tmf.comp_status == CS_COMPLETE ?
1511 QLA_SUCCESS : QLA_FUNCTION_FAILED;
1512
1513 if ((rval != QLA_SUCCESS) || tm_iocb->u.tmf.data) {
1514 ql_dbg(ql_dbg_taskm, vha, 0x8030,
1515 "TM IOCB failed (%x).\n", rval);
1516 }
1517
1518 if (!test_bit(UNLOADING, &vha->dpc_flags) && !IS_QLAFX00(vha->hw)) {
1519 flags = tm_iocb->u.tmf.flags;
1520 lun = (uint16_t)tm_iocb->u.tmf.lun;
1521
1522 /* Issue Marker IOCB */
1523 qla2x00_marker(vha, vha->hw->req_q_map[0],
1524 vha->hw->rsp_q_map[0], sp->fcport->loop_id, lun,
1525 flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
1526 }
3822263e
MI		 1527
1528done_free_sp:
25ff6af1 1529 sp->free(sp);
6d674927 1530 sp->fcport->flags &= ~FCF_ASYNC_SENT;
3822263e
MI		 1531done:
1532 return rval;
1533}
1534
4440e46d
AB		 1535static void
1536qla24xx_abort_iocb_timeout(void *data)
1537{
25ff6af1 1538 srb_t *sp = data;
4440e46d
AB		 1539 struct srb_iocb *abt = &sp->u.iocb_cmd;
1540
1541 abt->u.abt.comp_status = CS_TIMEOUT;
1542 complete(&abt->u.abt.comp);
1543}
1544
1545static void
25ff6af1 1546qla24xx_abort_sp_done(void *ptr, int res)
4440e46d 1547{
25ff6af1 1548 srb_t *sp = ptr;
4440e46d
AB		 1549 struct srb_iocb *abt = &sp->u.iocb_cmd;
1550
1551 complete(&abt->u.abt.comp);
1552}
1553
15f30a57 1554int
4440e46d
AB		 1555qla24xx_async_abort_cmd(srb_t *cmd_sp)
1556{
25ff6af1 1557 scsi_qla_host_t *vha = cmd_sp->vha;
4440e46d
AB		 1558 fc_port_t *fcport = cmd_sp->fcport;
1559 struct srb_iocb *abt_iocb;
1560 srb_t *sp;
1561 int rval = QLA_FUNCTION_FAILED;
1562
1563 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
1564 if (!sp)
1565 goto done;
1566
1567 abt_iocb = &sp->u.iocb_cmd;
1568 sp->type = SRB_ABT_CMD;
1569 sp->name = "abort";
1570 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
1571 abt_iocb->u.abt.cmd_hndl = cmd_sp->handle;
b027a5ac
DT		 1572
1573 if (vha->flags.qpairs_available && cmd_sp->qpair)
1574 abt_iocb->u.abt.req_que_no =
1575 cpu_to_le16(cmd_sp->qpair->req->id);
1576 else
1577 abt_iocb->u.abt.req_que_no = cpu_to_le16(vha->req->id);
1578
4440e46d
AB		 1579 sp->done = qla24xx_abort_sp_done;
1580 abt_iocb->timeout = qla24xx_abort_iocb_timeout;
1581 init_completion(&abt_iocb->u.abt.comp);
1582
1583 rval = qla2x00_start_sp(sp);
1584 if (rval != QLA_SUCCESS)
1585 goto done_free_sp;
1586
1587 ql_dbg(ql_dbg_async, vha, 0x507c,
1588 "Abort command issued - hdl=%x, target_id=%x\n",
1589 cmd_sp->handle, fcport->tgt_id);
1590
1591 wait_for_completion(&abt_iocb->u.abt.comp);
1592
1593 rval = abt_iocb->u.abt.comp_status == CS_COMPLETE ?
1594 QLA_SUCCESS : QLA_FUNCTION_FAILED;
1595
1596done_free_sp:
25ff6af1 1597 sp->free(sp);
4440e46d
AB		 1598done:
1599 return rval;
1600}
1601
1602int
1603qla24xx_async_abort_command(srb_t *sp)
1604{
1605 unsigned long flags = 0;
1606
1607 uint32_t handle;
1608 fc_port_t *fcport = sp->fcport;
1609 struct scsi_qla_host *vha = fcport->vha;
1610 struct qla_hw_data *ha = vha->hw;
1611 struct req_que *req = vha->req;
1612
b027a5ac
DT		 1613 if (vha->flags.qpairs_available && sp->qpair)
1614 req = sp->qpair->req;
1615
4440e46d
AB		 1616 spin_lock_irqsave(&ha->hardware_lock, flags);
1617 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
1618 if (req->outstanding_cmds[handle] == sp)
1619 break;
1620 }
1621 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1622 if (handle == req->num_outstanding_cmds) {
1623 /* Command not found. */
1624 return QLA_FUNCTION_FAILED;
1625 }
1626 if (sp->type == SRB_FXIOCB_DCMD)
1627 return qlafx00_fx_disc(vha, &vha->hw->mr.fcport,
1628 FXDISC_ABORT_IOCTL);
1629
1630 return qla24xx_async_abort_cmd(sp);
1631}
1632
a5d42f4c
DG		 1633static void
1634qla24xx_handle_prli_done_event(struct scsi_qla_host *vha, struct event_arg *ea)
1635{
1636 switch (ea->data[0]) {
1637 case MBS_COMMAND_COMPLETE:
1638 ql_dbg(ql_dbg_disc, vha, 0x2118,
1639 "%s %d %8phC post gpdb\n",
1640 __func__, __LINE__, ea->fcport->port_name);
1641
1642 ea->fcport->chip_reset = vha->hw->base_qpair->chip_reset;
1643 ea->fcport->logout_on_delete = 1;
1644 qla24xx_post_gpdb_work(vha, ea->fcport, 0);
1645 break;
1646 default:
1cbc0efc
DT		 1647 if ((ea->iop[0] == LSC_SCODE_ELS_REJECT) &&
1648 (ea->iop[1] == 0x50000)) { /* reson 5=busy expl:0x0 */
1649 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1650 ea->fcport->fw_login_state = DSC_LS_PLOGI_COMP;
1651 break;
1652 }
1653
edd05de1
DG		 1654 if (ea->fcport->n2n_flag) {
1655 ql_dbg(ql_dbg_disc, vha, 0x2118,
1656 "%s %d %8phC post fc4 prli\n",
1657 __func__, __LINE__, ea->fcport->port_name);
1658 ea->fcport->fc4f_nvme = 0;
1659 ea->fcport->n2n_flag = 0;
1660 qla24xx_post_prli_work(vha, ea->fcport);
1661 }
a5d42f4c
DG		 1662 ql_dbg(ql_dbg_disc, vha, 0x2119,
1663 "%s %d %8phC unhandle event of %x\n",
1664 __func__, __LINE__, ea->fcport->port_name, ea->data[0]);
1665 break;
1666 }
1667}
1668
726b8548
QT		 1669static void
1670qla24xx_handle_plogi_done_event(struct scsi_qla_host *vha, struct event_arg *ea)
ac280b67 1671{
726b8548 1672 port_id_t cid; /* conflict Nport id */
a084fd68
QT		 1673 u16 lid;
1674 struct fc_port *conflict_fcport;
82abdcaf 1675 unsigned long flags;
a4239945
QT		 1676 struct fc_port *fcport = ea->fcport;
1677
f352eeb7
QT		 1678 ql_dbg(ql_dbg_disc, vha, 0xffff,
1679 "%s %8phC DS %d LS %d rc %d login %d|%d rscn %d|%d data %x|%x iop %x|%x\n",
1680 __func__, fcport->port_name, fcport->disc_state,
1681 fcport->fw_login_state, ea->rc, ea->sp->gen2, fcport->login_gen,
1682 ea->sp->gen2, fcport->rscn_gen|ea->sp->gen1,
1683 ea->data[0], ea->data[1], ea->iop[0], ea->iop[1]);
1684
a4239945
QT		 1685 if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) ||
1686 (fcport->fw_login_state == DSC_LS_PRLI_PEND)) {
1687 ql_dbg(ql_dbg_disc, vha, 0x20ea,
1688 "%s %d %8phC Remote is trying to login\n",
1689 __func__, __LINE__, fcport->port_name);
1690 return;
1691 }
1692
1693 if (fcport->disc_state == DSC_DELETE_PEND)
1694 return;
1695
1696 if (ea->sp->gen2 != fcport->login_gen) {
1697 /* target side must have changed it. */
1698 ql_dbg(ql_dbg_disc, vha, 0x20d3,
f352eeb7
QT		 1699 "%s %8phC generation changed\n",
1700 __func__, fcport->port_name);
1701 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
a4239945
QT		 1702 return;
1703 } else if (ea->sp->gen1 != fcport->rscn_gen) {
1704 ql_dbg(ql_dbg_disc, vha, 0x20d4, "%s %d %8phC post gidpn\n",
1705 __func__, __LINE__, fcport->port_name);
1706 qla24xx_post_gidpn_work(vha, fcport);
1707 return;
1708 }
ac280b67 1709
726b8548 1710 switch (ea->data[0]) {
ac280b67 1711 case MBS_COMMAND_COMPLETE:
a4f92a32
AV		 1712 /*
1713 * Driver must validate login state - If PRLI not complete,
1714 * force a relogin attempt via implicit LOGO, PLOGI, and PRLI
1715 * requests.
1716 */
a5d42f4c
DG		 1717 if (ea->fcport->fc4f_nvme) {
1718 ql_dbg(ql_dbg_disc, vha, 0x2117,
1719 "%s %d %8phC post prli\n",
1720 __func__, __LINE__, ea->fcport->port_name);
1721 qla24xx_post_prli_work(vha, ea->fcport);
1722 } else {
1723 ql_dbg(ql_dbg_disc, vha, 0x20ea,
a084fd68
QT		 1724 "%s %d %8phC LoopID 0x%x in use with %06x. post gnl\n",
1725 __func__, __LINE__, ea->fcport->port_name,
1726 ea->fcport->loop_id, ea->fcport->d_id.b24);
1727
1728 set_bit(ea->fcport->loop_id, vha->hw->loop_id_map);
82abdcaf 1729 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
a084fd68 1730 ea->fcport->loop_id = FC_NO_LOOP_ID;
a5d42f4c
DG		 1731 ea->fcport->chip_reset = vha->hw->base_qpair->chip_reset;
1732 ea->fcport->logout_on_delete = 1;
3515832c 1733 ea->fcport->send_els_logo = 0;
82abdcaf
QT		 1734 ea->fcport->fw_login_state = DSC_LS_PRLI_COMP;
1735 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1736
a5d42f4c
DG		 1737 qla24xx_post_gpdb_work(vha, ea->fcport, 0);
1738 }
ac280b67
AV		 1739 break;
1740 case MBS_COMMAND_ERROR:
83548fe2 1741 ql_dbg(ql_dbg_disc, vha, 0x20eb, "%s %d %8phC cmd error %x\n",
726b8548
QT		 1742 __func__, __LINE__, ea->fcport->port_name, ea->data[1]);
1743
1744 ea->fcport->flags &= ~FCF_ASYNC_SENT;
1745 ea->fcport->disc_state = DSC_LOGIN_FAILED;
1746 if (ea->data[1] & QLA_LOGIO_LOGIN_RETRIED)
ac280b67
AV		 1747 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1748 else
726b8548 1749 qla2x00_mark_device_lost(vha, ea->fcport, 1, 0);
ac280b67
AV		 1750 break;
1751 case MBS_LOOP_ID_USED:
726b8548
QT		 1752 /* data[1] = IO PARAM 1 = nport ID */
1753 cid.b.domain = (ea->iop[1] >> 16) & 0xff;
1754 cid.b.area = (ea->iop[1] >> 8) & 0xff;
1755 cid.b.al_pa = ea->iop[1] & 0xff;
1756 cid.b.rsvd_1 = 0;
1757
83548fe2
QT		 1758 ql_dbg(ql_dbg_disc, vha, 0x20ec,
1759 "%s %d %8phC LoopID 0x%x in use post gnl\n",
1760 __func__, __LINE__, ea->fcport->port_name,
1761 ea->fcport->loop_id);
726b8548
QT		 1762
1763 if (IS_SW_RESV_ADDR(cid)) {
1764 set_bit(ea->fcport->loop_id, vha->hw->loop_id_map);
1765 ea->fcport->loop_id = FC_NO_LOOP_ID;
1766 } else {
1767 qla2x00_clear_loop_id(ea->fcport);
ac280b67 1768 }
726b8548
QT		 1769 qla24xx_post_gnl_work(vha, ea->fcport);
1770 break;
1771 case MBS_PORT_ID_USED:
83548fe2
QT		 1772 ql_dbg(ql_dbg_disc, vha, 0x20ed,
1773 "%s %d %8phC NPortId %02x%02x%02x inuse post gidpn\n",
1774 __func__, __LINE__, ea->fcport->port_name,
1775 ea->fcport->d_id.b.domain, ea->fcport->d_id.b.area,
1776 ea->fcport->d_id.b.al_pa);
726b8548 1777
a084fd68
QT		 1778 lid = ea->iop[1] & 0xffff;
1779 qlt_find_sess_invalidate_other(vha,
1780 wwn_to_u64(ea->fcport->port_name),
1781 ea->fcport->d_id, lid, &conflict_fcport);
1782
1783 if (conflict_fcport) {
1784 /*
1785 * Another fcport share the same loop_id/nport id.
1786 * Conflict fcport needs to finish cleanup before this
1787 * fcport can proceed to login.
1788 */
1789 conflict_fcport->conflict = ea->fcport;
1790 ea->fcport->login_pause = 1;
1791
1792 ql_dbg(ql_dbg_disc, vha, 0x20ed,
1793 "%s %d %8phC NPortId %06x inuse with loopid 0x%x. post gidpn\n",
1794 __func__, __LINE__, ea->fcport->port_name,
1795 ea->fcport->d_id.b24, lid);
1796 qla2x00_clear_loop_id(ea->fcport);
1797 qla24xx_post_gidpn_work(vha, ea->fcport);
1798 } else {
1799 ql_dbg(ql_dbg_disc, vha, 0x20ed,
1800 "%s %d %8phC NPortId %06x inuse with loopid 0x%x. sched delete\n",
1801 __func__, __LINE__, ea->fcport->port_name,
1802 ea->fcport->d_id.b24, lid);
1803
1804 qla2x00_clear_loop_id(ea->fcport);
1805 set_bit(lid, vha->hw->loop_id_map);
1806 ea->fcport->loop_id = lid;
1807 ea->fcport->keep_nport_handle = 0;
94cff6e1 1808 qlt_schedule_sess_for_deletion(ea->fcport);
a084fd68 1809 }
ac280b67
AV		 1810 break;
1811 }
4916392b 1812 return;
ac280b67
AV		 1813}
1814
4916392b 1815void
ac280b67
AV		 1816qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport,
1817 uint16_t *data)
1818{
726b8548 1819 qla2x00_mark_device_lost(vha, fcport, 1, 0);
a6ca8878 1820 qlt_logo_completion_handler(fcport, data[0]);
726b8548 1821 fcport->login_gen++;
4916392b 1822 return;
ac280b67
AV		 1823}
1824
4916392b 1825void
5ff1d584
AV		 1826qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport,
1827 uint16_t *data)
1828{
1829 if (data[0] == MBS_COMMAND_COMPLETE) {
1830 qla2x00_update_fcport(vha, fcport);
1831
4916392b 1832 return;
5ff1d584
AV		 1833 }
1834
1835 /* Retry login. */
1836 fcport->flags &= ~FCF_ASYNC_SENT;
1837 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
1838 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1839 else
80d79440 1840 qla2x00_mark_device_lost(vha, fcport, 1, 0);
5ff1d584 1841
4916392b 1842 return;
5ff1d584
AV		 1843}
1844
1da177e4
LT		 1845/****************************************************************************/
1846/* QLogic ISP2x00 Hardware Support Functions. */
1847/****************************************************************************/
1848
fa492630 1849static int
7d613ac6
SV		 1850qla83xx_nic_core_fw_load(scsi_qla_host_t *vha)
1851{
1852 int rval = QLA_SUCCESS;
1853 struct qla_hw_data *ha = vha->hw;
1854 uint32_t idc_major_ver, idc_minor_ver;
711aa7f7 1855 uint16_t config[4];
7d613ac6
SV		 1856
1857 qla83xx_idc_lock(vha, 0);
1858
1859 /* SV: TODO: Assign initialization timeout from
1860 * flash-info / other param
1861 */
1862 ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT;
1863 ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT;
1864
1865 /* Set our fcoe function presence */
1866 if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) {
1867 ql_dbg(ql_dbg_p3p, vha, 0xb077,
1868 "Error while setting DRV-Presence.\n");
1869 rval = QLA_FUNCTION_FAILED;
1870 goto exit;
1871 }
1872
1873 /* Decide the reset ownership */
1874 qla83xx_reset_ownership(vha);
1875
1876 /*
1877 * On first protocol driver load:
1878 * Init-Owner: Set IDC-Major-Version and Clear IDC-Lock-Recovery
1879 * register.
1880 * Others: Check compatibility with current IDC Major version.
1881 */
1882 qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver);
1883 if (ha->flags.nic_core_reset_owner) {
1884 /* Set IDC Major version */
1885 idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION;
1886 qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver);
1887
1888 /* Clearing IDC-Lock-Recovery register */
1889 qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0);
1890 } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) {
1891 /*
1892 * Clear further IDC participation if we are not compatible with
1893 * the current IDC Major Version.
1894 */
1895 ql_log(ql_log_warn, vha, 0xb07d,
1896 "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n",
1897 idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION);
1898 __qla83xx_clear_drv_presence(vha);
1899 rval = QLA_FUNCTION_FAILED;
1900 goto exit;
1901 }
1902 /* Each function sets its supported Minor version. */
1903 qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver);
1904 idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2));
1905 qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver);
1906
711aa7f7
SK		 1907 if (ha->flags.nic_core_reset_owner) {
1908 memset(config, 0, sizeof(config));
1909 if (!qla81xx_get_port_config(vha, config))
1910 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
1911 QLA8XXX_DEV_READY);
1912 }
1913
7d613ac6
SV		 1914 rval = qla83xx_idc_state_handler(vha);
1915
1916exit:
1917 qla83xx_idc_unlock(vha, 0);
1918
1919 return rval;
1920}
1921
1da177e4
LT		 1922/*
1923* qla2x00_initialize_adapter
1924* Initialize board.
1925*
1926* Input:
1927* ha = adapter block pointer.
1928*
1929* Returns:
1930* 0 = success
1931*/
1932int
e315cd28 1933qla2x00_initialize_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 1934{
1935 int rval;
e315cd28 1936 struct qla_hw_data *ha = vha->hw;
73208dfd 1937 struct req_que *req = ha->req_q_map[0];
2533cf67 1938
fc90adaf
JC		 1939 memset(&vha->qla_stats, 0, sizeof(vha->qla_stats));
1940 memset(&vha->fc_host_stat, 0, sizeof(vha->fc_host_stat));
1941
1da177e4 1942 /* Clear adapter flags. */
e315cd28 1943 vha->flags.online = 0;
2533cf67 1944 ha->flags.chip_reset_done = 0;
e315cd28 1945 vha->flags.reset_active = 0;
85880801
AV		 1946 ha->flags.pci_channel_io_perm_failure = 0;
1947 ha->flags.eeh_busy = 0;
fabbb8df 1948 vha->qla_stats.jiffies_at_last_reset = get_jiffies_64();
e315cd28
AC		 1949 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1950 atomic_set(&vha->loop_state, LOOP_DOWN);
1951 vha->device_flags = DFLG_NO_CABLE;
1952 vha->dpc_flags = 0;
1953 vha->flags.management_server_logged_in = 0;
1954 vha->marker_needed = 0;
1da177e4
LT		 1955 ha->isp_abort_cnt = 0;
1956 ha->beacon_blink_led = 0;
1957
73208dfd
AC		 1958 set_bit(0, ha->req_qid_map);
1959 set_bit(0, ha->rsp_qid_map);
1960
cfb0919c 1961 ql_dbg(ql_dbg_init, vha, 0x0040,
7c3df132 1962 "Configuring PCI space...\n");
e315cd28 1963 rval = ha->isp_ops->pci_config(vha);
1da177e4 1964 if (rval) {
7c3df132
SK		 1965 ql_log(ql_log_warn, vha, 0x0044,
1966 "Unable to configure PCI space.\n");
1da177e4
LT		 1967 return (rval);
1968 }
1969
e315cd28 1970 ha->isp_ops->reset_chip(vha);
1da177e4 1971
e315cd28 1972 rval = qla2xxx_get_flash_info(vha);
c00d8994 1973 if (rval) {
7c3df132
SK		 1974 ql_log(ql_log_fatal, vha, 0x004f,
1975 "Unable to validate FLASH data.\n");
7ec0effd
AD		 1976 return rval;
1977 }
1978
1979 if (IS_QLA8044(ha)) {
1980 qla8044_read_reset_template(vha);
1981
1982 /* NOTE: If ql2xdontresethba==1, set IDC_CTRL DONTRESET_BIT0.
1983 * If DONRESET_BIT0 is set, drivers should not set dev_state
1984 * to NEED_RESET. But if NEED_RESET is set, drivers should
1985 * should honor the reset. */
1986 if (ql2xdontresethba == 1)
1987 qla8044_set_idc_dontreset(vha);
c00d8994
AV		 1988 }
1989
73208dfd 1990 ha->isp_ops->get_flash_version(vha, req->ring);
cfb0919c 1991 ql_dbg(ql_dbg_init, vha, 0x0061,
7c3df132 1992 "Configure NVRAM parameters...\n");
0107109e 1993
e315cd28 1994 ha->isp_ops->nvram_config(vha);
1da177e4 1995
d4c760c2
AV		 1996 if (ha->flags.disable_serdes) {
1997 /* Mask HBA via NVRAM settings? */
7c3df132 1998 ql_log(ql_log_info, vha, 0x0077,
7b833558 1999 "Masking HBA WWPN %8phN (via NVRAM).\n", vha->port_name);
d4c760c2
AV		 2000 return QLA_FUNCTION_FAILED;
2001 }
2002
cfb0919c 2003 ql_dbg(ql_dbg_init, vha, 0x0078,
7c3df132 2004 "Verifying loaded RISC code...\n");
1da177e4 2005
e315cd28
AC		 2006 if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) {
2007 rval = ha->isp_ops->chip_diag(vha);
d19044c3
AV		 2008 if (rval)
2009 return (rval);
e315cd28 2010 rval = qla2x00_setup_chip(vha);
d19044c3
AV		 2011 if (rval)
2012 return (rval);
1da177e4 2013 }
a9083016 2014
4d4df193 2015 if (IS_QLA84XX(ha)) {
e315cd28 2016 ha->cs84xx = qla84xx_get_chip(vha);
4d4df193 2017 if (!ha->cs84xx) {
7c3df132 2018 ql_log(ql_log_warn, vha, 0x00d0,
4d4df193
HK		 2019 "Unable to configure ISP84XX.\n");
2020 return QLA_FUNCTION_FAILED;
2021 }
2022 }
2d70c103 2023
ead03855 2024 if (qla_ini_mode_enabled(vha) || qla_dual_mode_enabled(vha))
2d70c103
NB		 2025 rval = qla2x00_init_rings(vha);
2026
2533cf67 2027 ha->flags.chip_reset_done = 1;
1da177e4 2028
9a069e19 2029 if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) {
6c452a45 2030 /* Issue verify 84xx FW IOCB to complete 84xx initialization */
9a069e19
GM		 2031 rval = qla84xx_init_chip(vha);
2032 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2033 ql_log(ql_log_warn, vha, 0x00d4,
2034 "Unable to initialize ISP84XX.\n");
8d2b21db 2035 qla84xx_put_chip(vha);
9a069e19
GM		 2036 }
2037 }
2038
7d613ac6
SV		 2039 /* Load the NIC Core f/w if we are the first protocol driver. */
2040 if (IS_QLA8031(ha)) {
2041 rval = qla83xx_nic_core_fw_load(vha);
2042 if (rval)
2043 ql_log(ql_log_warn, vha, 0x0124,
2044 "Error in initializing NIC Core f/w.\n");
2045 }
2046
2f0f3f4f
MI		 2047 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
2048 qla24xx_read_fcp_prio_cfg(vha);
09ff701a 2049
c46e65c7
JC		 2050 if (IS_P3P_TYPE(ha))
2051 qla82xx_set_driver_version(vha, QLA2XXX_VERSION);
2052 else
2053 qla25xx_set_driver_version(vha, QLA2XXX_VERSION);
2054
1da177e4
LT		 2055 return (rval);
2056}
2057
2058/**
abbd8870 2059 * qla2100_pci_config() - Setup ISP21xx PCI configuration registers.
2db6228d 2060 * @vha: HA context
1da177e4
LT		 2061 *
2062 * Returns 0 on success.
2063 */
abbd8870 2064int
e315cd28 2065qla2100_pci_config(scsi_qla_host_t *vha)
1da177e4 2066{
a157b101 2067 uint16_t w;
abbd8870 2068 unsigned long flags;
e315cd28 2069 struct qla_hw_data *ha = vha->hw;
3d71644c 2070 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 2071
1da177e4 2072 pci_set_master(ha->pdev);
af6177d8 2073 pci_try_set_mwi(ha->pdev);
1da177e4 2074
1da177e4 2075 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 2076 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
abbd8870
AV		 2077 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
2078
737faece 2079 pci_disable_rom(ha->pdev);
1da177e4
LT		 2080
2081 /* Get PCI bus information. */
2082 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 2083 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
1da177e4
LT		 2084 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2085
abbd8870
AV		 2086 return QLA_SUCCESS;
2087}
1da177e4 2088
abbd8870
AV		 2089/**
2090 * qla2300_pci_config() - Setup ISP23xx PCI configuration registers.
2db6228d 2091 * @vha: HA context
abbd8870
AV		 2092 *
2093 * Returns 0 on success.
2094 */
2095int
e315cd28 2096qla2300_pci_config(scsi_qla_host_t *vha)
abbd8870 2097{
a157b101 2098 uint16_t w;
abbd8870
AV		 2099 unsigned long flags = 0;
2100 uint32_t cnt;
e315cd28 2101 struct qla_hw_data *ha = vha->hw;
3d71644c 2102 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 2103
abbd8870 2104 pci_set_master(ha->pdev);
af6177d8 2105 pci_try_set_mwi(ha->pdev);
1da177e4 2106
abbd8870 2107 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 2108 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
1da177e4 2109
abbd8870
AV		 2110 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2111 w &= ~PCI_COMMAND_INTX_DISABLE;
a157b101 2112 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1da177e4 2113
abbd8870
AV		 2114 /*
2115 * If this is a 2300 card and not 2312, reset the
2116 * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately,
2117 * the 2310 also reports itself as a 2300 so we need to get the
2118 * fb revision level -- a 6 indicates it really is a 2300 and
2119 * not a 2310.
2120 */
2121 if (IS_QLA2300(ha)) {
2122 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 2123
abbd8870 2124 /* Pause RISC. */
3d71644c 2125 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
abbd8870 2126 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 2127 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
abbd8870 2128 break;
1da177e4 2129
abbd8870
AV		 2130 udelay(10);
2131 }
1da177e4 2132
abbd8870 2133 /* Select FPM registers. */
3d71644c
AV		 2134 WRT_REG_WORD(&reg->ctrl_status, 0x20);
2135 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 2136
2137 /* Get the fb rev level */
3d71644c 2138 ha->fb_rev = RD_FB_CMD_REG(ha, reg);
abbd8870
AV		 2139
2140 if (ha->fb_rev == FPM_2300)
a157b101 2141 pci_clear_mwi(ha->pdev);
abbd8870
AV		 2142
2143 /* Deselect FPM registers. */
3d71644c
AV		 2144 WRT_REG_WORD(&reg->ctrl_status, 0x0);
2145 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 2146
2147 /* Release RISC module. */
3d71644c 2148 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
abbd8870 2149 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 2150 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0)
abbd8870
AV		 2151 break;
2152
2153 udelay(10);
1da177e4 2154 }
1da177e4 2155
abbd8870
AV		 2156 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2157 }
1da177e4 2158
abbd8870
AV		 2159 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
2160
737faece 2161 pci_disable_rom(ha->pdev);
1da177e4 2162
abbd8870
AV		 2163 /* Get PCI bus information. */
2164 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 2165 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 2166 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2167
2168 return QLA_SUCCESS;
1da177e4
LT		 2169}
2170
0107109e
AV		 2171/**
2172 * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers.
2db6228d 2173 * @vha: HA context
0107109e
AV		 2174 *
2175 * Returns 0 on success.
2176 */
2177int
e315cd28 2178qla24xx_pci_config(scsi_qla_host_t *vha)
0107109e 2179{
a157b101 2180 uint16_t w;
0107109e 2181 unsigned long flags = 0;
e315cd28 2182 struct qla_hw_data *ha = vha->hw;
0107109e 2183 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
0107109e
AV		 2184
2185 pci_set_master(ha->pdev);
af6177d8 2186 pci_try_set_mwi(ha->pdev);
0107109e
AV		 2187
2188 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 2189 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
0107109e
AV		 2190 w &= ~PCI_COMMAND_INTX_DISABLE;
2191 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
2192
2193 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
2194
2195 /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */
f85ec187
AV		 2196 if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
2197 pcix_set_mmrbc(ha->pdev, 2048);
0107109e
AV		 2198
2199 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 2200 if (pci_is_pcie(ha->pdev))
5ffd3a52 2201 pcie_set_readrq(ha->pdev, 4096);
0107109e 2202
737faece 2203 pci_disable_rom(ha->pdev);
0107109e 2204
44c10138 2205 ha->chip_revision = ha->pdev->revision;
a8488abe 2206
0107109e
AV		 2207 /* Get PCI bus information. */
2208 spin_lock_irqsave(&ha->hardware_lock, flags);
2209 ha->pci_attr = RD_REG_DWORD(&reg->ctrl_status);
2210 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2211
2212 return QLA_SUCCESS;
2213}
2214
c3a2f0df
AV		 2215/**
2216 * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers.
2db6228d 2217 * @vha: HA context
c3a2f0df
AV		 2218 *
2219 * Returns 0 on success.
2220 */
2221int
e315cd28 2222qla25xx_pci_config(scsi_qla_host_t *vha)
c3a2f0df
AV		 2223{
2224 uint16_t w;
e315cd28 2225 struct qla_hw_data *ha = vha->hw;
c3a2f0df
AV		 2226
2227 pci_set_master(ha->pdev);
2228 pci_try_set_mwi(ha->pdev);
2229
2230 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
2231 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
2232 w &= ~PCI_COMMAND_INTX_DISABLE;
2233 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
2234
2235 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 2236 if (pci_is_pcie(ha->pdev))
5ffd3a52 2237 pcie_set_readrq(ha->pdev, 4096);
c3a2f0df 2238
737faece 2239 pci_disable_rom(ha->pdev);
c3a2f0df
AV		 2240
2241 ha->chip_revision = ha->pdev->revision;
2242
2243 return QLA_SUCCESS;
2244}
2245
1da177e4
LT		 2246/**
2247 * qla2x00_isp_firmware() - Choose firmware image.
2db6228d 2248 * @vha: HA context
1da177e4
LT		 2249 *
2250 * Returns 0 on success.
2251 */
2252static int
e315cd28 2253qla2x00_isp_firmware(scsi_qla_host_t *vha)
1da177e4
LT		 2254{
2255 int rval;
42e421b1
AV		 2256 uint16_t loop_id, topo, sw_cap;
2257 uint8_t domain, area, al_pa;
e315cd28 2258 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2259
2260 /* Assume loading risc code */
fa2a1ce5 2261 rval = QLA_FUNCTION_FAILED;
1da177e4
LT		 2262
2263 if (ha->flags.disable_risc_code_load) {
7c3df132 2264 ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n");
1da177e4
LT		 2265
2266 /* Verify checksum of loaded RISC code. */
e315cd28 2267 rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address);
42e421b1
AV		 2268 if (rval == QLA_SUCCESS) {
2269 /* And, verify we are not in ROM code. */
e315cd28 2270 rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa,
42e421b1
AV		 2271 &area, &domain, &topo, &sw_cap);
2272 }
1da177e4
LT		 2273 }
2274
7c3df132
SK		 2275 if (rval)
2276 ql_dbg(ql_dbg_init, vha, 0x007a,
2277 "**** Load RISC code ****.\n");
1da177e4
LT		 2278
2279 return (rval);
2280}
2281
2282/**
2283 * qla2x00_reset_chip() - Reset ISP chip.
2db6228d 2284 * @vha: HA context
1da177e4
LT		 2285 *
2286 * Returns 0 on success.
2287 */
abbd8870 2288void
e315cd28 2289qla2x00_reset_chip(scsi_qla_host_t *vha)
1da177e4
LT		 2290{
2291 unsigned long flags = 0;
e315cd28 2292 struct qla_hw_data *ha = vha->hw;
3d71644c 2293 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 2294 uint32_t cnt;
1da177e4
LT		 2295 uint16_t cmd;
2296
85880801
AV		 2297 if (unlikely(pci_channel_offline(ha->pdev)))
2298 return;
2299
fd34f556 2300 ha->isp_ops->disable_intrs(ha);
1da177e4
LT		 2301
2302 spin_lock_irqsave(&ha->hardware_lock, flags);
2303
2304 /* Turn off master enable */
2305 cmd = 0;
2306 pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd);
2307 cmd &= ~PCI_COMMAND_MASTER;
2308 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
2309
2310 if (!IS_QLA2100(ha)) {
2311 /* Pause RISC. */
2312 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
2313 if (IS_QLA2200(ha) || IS_QLA2300(ha)) {
2314 for (cnt = 0; cnt < 30000; cnt++) {
2315 if ((RD_REG_WORD(&reg->hccr) &
2316 HCCR_RISC_PAUSE) != 0)
2317 break;
2318 udelay(100);
2319 }
2320 } else {
2321 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
2322 udelay(10);
2323 }
2324
2325 /* Select FPM registers. */
2326 WRT_REG_WORD(&reg->ctrl_status, 0x20);
2327 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2328
2329 /* FPM Soft Reset. */
2330 WRT_REG_WORD(&reg->fpm_diag_config, 0x100);
2331 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
2332
2333 /* Toggle Fpm Reset. */
2334 if (!IS_QLA2200(ha)) {
2335 WRT_REG_WORD(&reg->fpm_diag_config, 0x0);
2336 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
2337 }
2338
2339 /* Select frame buffer registers. */
2340 WRT_REG_WORD(&reg->ctrl_status, 0x10);
2341 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2342
2343 /* Reset frame buffer FIFOs. */
2344 if (IS_QLA2200(ha)) {
2345 WRT_FB_CMD_REG(ha, reg, 0xa000);
2346 RD_FB_CMD_REG(ha, reg); /* PCI Posting. */
2347 } else {
2348 WRT_FB_CMD_REG(ha, reg, 0x00fc);
2349
2350 /* Read back fb_cmd until zero or 3 seconds max */
2351 for (cnt = 0; cnt < 3000; cnt++) {
2352 if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0)
2353 break;
2354 udelay(100);
2355 }
2356 }
2357
2358 /* Select RISC module registers. */
2359 WRT_REG_WORD(&reg->ctrl_status, 0);
2360 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2361
2362 /* Reset RISC processor. */
2363 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
2364 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
2365
2366 /* Release RISC processor. */
2367 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
2368 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
2369 }
2370
2371 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
2372 WRT_REG_WORD(&reg->hccr, HCCR_CLR_HOST_INT);
2373
2374 /* Reset ISP chip. */
2375 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
2376
2377 /* Wait for RISC to recover from reset. */
2378 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
2379 /*
2380 * It is necessary to for a delay here since the card doesn't
2381 * respond to PCI reads during a reset. On some architectures
2382 * this will result in an MCA.
2383 */
2384 udelay(20);
2385 for (cnt = 30000; cnt; cnt--) {
2386 if ((RD_REG_WORD(&reg->ctrl_status) &
2387 CSR_ISP_SOFT_RESET) == 0)
2388 break;
2389 udelay(100);
2390 }
2391 } else
2392 udelay(10);
2393
2394 /* Reset RISC processor. */
2395 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
2396
2397 WRT_REG_WORD(&reg->semaphore, 0);
2398
2399 /* Release RISC processor. */
2400 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
2401 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
2402
2403 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
2404 for (cnt = 0; cnt < 30000; cnt++) {
ffb39f03 2405 if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY)
1da177e4 2406 break;
1da177e4
LT		 2407
2408 udelay(100);
2409 }
2410 } else
2411 udelay(100);
2412
2413 /* Turn on master enable */
2414 cmd |= PCI_COMMAND_MASTER;
2415 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
2416
2417 /* Disable RISC pause on FPM parity error. */
2418 if (!IS_QLA2100(ha)) {
2419 WRT_REG_WORD(&reg->hccr, HCCR_DISABLE_PARITY_PAUSE);
2420 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
2421 }
2422
2423 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2424}
2425
b1d46989
MI		 2426/**
2427 * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC.
2db6228d 2428 * @vha: HA context
b1d46989
MI		 2429 *
2430 * Returns 0 on success.
2431 */
fa492630 2432static int
b1d46989
MI		 2433qla81xx_reset_mpi(scsi_qla_host_t *vha)
2434{
2435 uint16_t mb[4] = {0x1010, 0, 1, 0};
2436
6246b8a1
GM		 2437 if (!IS_QLA81XX(vha->hw))
2438 return QLA_SUCCESS;
2439
b1d46989
MI		 2440 return qla81xx_write_mpi_register(vha, mb);
2441}
2442
0107109e 2443/**
88c26663 2444 * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC.
2db6228d 2445 * @vha: HA context
0107109e
AV		 2446 *
2447 * Returns 0 on success.
2448 */
d14e72fb 2449static inline int
e315cd28 2450qla24xx_reset_risc(scsi_qla_host_t *vha)
0107109e
AV		 2451{
2452 unsigned long flags = 0;
e315cd28 2453 struct qla_hw_data *ha = vha->hw;
0107109e 2454 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
52c82823 2455 uint32_t cnt;
335a1cc9 2456 uint16_t wd;
b1d46989 2457 static int abts_cnt; /* ISP abort retry counts */
d14e72fb 2458 int rval = QLA_SUCCESS;
0107109e 2459
0107109e
AV		 2460 spin_lock_irqsave(&ha->hardware_lock, flags);
2461
2462 /* Reset RISC. */
2463 WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
2464 for (cnt = 0; cnt < 30000; cnt++) {
2465 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
2466 break;
2467
2468 udelay(10);
2469 }
2470
d14e72fb
HM		 2471 if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE))
2472 set_bit(DMA_SHUTDOWN_CMPL, &ha->fw_dump_cap_flags);
2473
2474 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017e,
2475 "HCCR: 0x%x, Control Status %x, DMA active status:0x%x\n",
2476 RD_REG_DWORD(&reg->hccr),
2477 RD_REG_DWORD(&reg->ctrl_status),
2478 (RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE));
2479
0107109e
AV		 2480 WRT_REG_DWORD(&reg->ctrl_status,
2481 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
335a1cc9 2482 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
88c26663 2483
335a1cc9 2484 udelay(100);
d14e72fb 2485
88c26663 2486 /* Wait for firmware to complete NVRAM accesses. */
52c82823 2487 RD_REG_WORD(&reg->mailbox0);
d14e72fb
HM		 2488 for (cnt = 10000; RD_REG_WORD(&reg->mailbox0) != 0 &&
2489 rval == QLA_SUCCESS; cnt--) {
88c26663 2490 barrier();
d14e72fb
HM		 2491 if (cnt)
2492 udelay(5);
2493 else
2494 rval = QLA_FUNCTION_TIMEOUT;
88c26663
AV		 2495 }
2496
d14e72fb
HM		 2497 if (rval == QLA_SUCCESS)
2498 set_bit(ISP_MBX_RDY, &ha->fw_dump_cap_flags);
2499
2500 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017f,
2501 "HCCR: 0x%x, MailBox0 Status 0x%x\n",
2502 RD_REG_DWORD(&reg->hccr),
2503 RD_REG_DWORD(&reg->mailbox0));
2504
335a1cc9 2505 /* Wait for soft-reset to complete. */
52c82823 2506 RD_REG_DWORD(&reg->ctrl_status);
200ffb15 2507 for (cnt = 0; cnt < 60; cnt++) {
0107109e 2508 barrier();
d14e72fb
HM		 2509 if ((RD_REG_DWORD(&reg->ctrl_status) &
2510 CSRX_ISP_SOFT_RESET) == 0)
2511 break;
2512
2513 udelay(5);
0107109e 2514 }
d14e72fb
HM		 2515 if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_ISP_SOFT_RESET))
2516 set_bit(ISP_SOFT_RESET_CMPL, &ha->fw_dump_cap_flags);
2517
2518 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015d,
2519 "HCCR: 0x%x, Soft Reset status: 0x%x\n",
2520 RD_REG_DWORD(&reg->hccr),
2521 RD_REG_DWORD(&reg->ctrl_status));
0107109e 2522
b1d46989
MI		 2523 /* If required, do an MPI FW reset now */
2524 if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
2525 if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
2526 if (++abts_cnt < 5) {
2527 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2528 set_bit(MPI_RESET_NEEDED, &vha->dpc_flags);
2529 } else {
2530 /*
2531 * We exhausted the ISP abort retries. We have to
2532 * set the board offline.
2533 */
2534 abts_cnt = 0;
2535 vha->flags.online = 0;
2536 }
2537 }
2538 }
2539
0107109e
AV		 2540 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
2541 RD_REG_DWORD(&reg->hccr);
2542
2543 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
2544 RD_REG_DWORD(&reg->hccr);
2545
2546 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
2547 RD_REG_DWORD(&reg->hccr);
2548
52c82823 2549 RD_REG_WORD(&reg->mailbox0);
200ffb15 2550 for (cnt = 60; RD_REG_WORD(&reg->mailbox0) != 0 &&
d14e72fb 2551 rval == QLA_SUCCESS; cnt--) {
0107109e 2552 barrier();
d14e72fb
HM		 2553 if (cnt)
2554 udelay(5);
2555 else
2556 rval = QLA_FUNCTION_TIMEOUT;
0107109e 2557 }
d14e72fb
HM		 2558 if (rval == QLA_SUCCESS)
2559 set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags);
2560
2561 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015e,
2562 "Host Risc 0x%x, mailbox0 0x%x\n",
2563 RD_REG_DWORD(&reg->hccr),
2564 RD_REG_WORD(&reg->mailbox0));
0107109e
AV		 2565
2566 spin_unlock_irqrestore(&ha->hardware_lock, flags);
124f85e6 2567
d14e72fb
HM		 2568 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015f,
2569 "Driver in %s mode\n",
2570 IS_NOPOLLING_TYPE(ha) ? "Interrupt" : "Polling");
2571
124f85e6
AV		 2572 if (IS_NOPOLLING_TYPE(ha))
2573 ha->isp_ops->enable_intrs(ha);
d14e72fb
HM		 2574
2575 return rval;
0107109e
AV		 2576}
2577
4ea2c9c7
JC		 2578static void
2579qla25xx_read_risc_sema_reg(scsi_qla_host_t *vha, uint32_t *data)
2580{
2581 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
2582
2583 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
2584 *data = RD_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET);
2585
2586}
2587
2588static void
2589qla25xx_write_risc_sema_reg(scsi_qla_host_t *vha, uint32_t data)
2590{
2591 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
2592
2593 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
2594 WRT_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET, data);
2595}
2596
2597static void
2598qla25xx_manipulate_risc_semaphore(scsi_qla_host_t *vha)
2599{
4ea2c9c7
JC		 2600 uint32_t wd32 = 0;
2601 uint delta_msec = 100;
2602 uint elapsed_msec = 0;
2603 uint timeout_msec;
2604 ulong n;
2605
cc790764
JC		 2606 if (vha->hw->pdev->subsystem_device != 0x0175 &&
2607 vha->hw->pdev->subsystem_device != 0x0240)
4ea2c9c7
JC		 2608 return;
2609
8dd7e3a5
JC		 2610 WRT_REG_DWORD(&vha->hw->iobase->isp24.hccr, HCCRX_SET_RISC_PAUSE);
2611 udelay(100);
2612
4ea2c9c7
JC		 2613attempt:
2614 timeout_msec = TIMEOUT_SEMAPHORE;
2615 n = timeout_msec / delta_msec;
2616 while (n--) {
2617 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_SET);
2618 qla25xx_read_risc_sema_reg(vha, &wd32);
2619 if (wd32 & RISC_SEMAPHORE)
2620 break;
2621 msleep(delta_msec);
2622 elapsed_msec += delta_msec;
2623 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
2624 goto force;
2625 }
2626
2627 if (!(wd32 & RISC_SEMAPHORE))
2628 goto force;
2629
2630 if (!(wd32 & RISC_SEMAPHORE_FORCE))
2631 goto acquired;
2632
2633 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_CLR);
2634 timeout_msec = TIMEOUT_SEMAPHORE_FORCE;
2635 n = timeout_msec / delta_msec;
2636 while (n--) {
2637 qla25xx_read_risc_sema_reg(vha, &wd32);
2638 if (!(wd32 & RISC_SEMAPHORE_FORCE))
2639 break;
2640 msleep(delta_msec);
2641 elapsed_msec += delta_msec;
2642 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
2643 goto force;
2644 }
2645
2646 if (wd32 & RISC_SEMAPHORE_FORCE)
2647 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_CLR);
2648
2649 goto attempt;
2650
2651force:
2652 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_SET);
2653
2654acquired:
2655 return;
2656}
2657
88c26663
AV		 2658/**
2659 * qla24xx_reset_chip() - Reset ISP24xx chip.
2db6228d 2660 * @vha: HA context
88c26663
AV		 2661 *
2662 * Returns 0 on success.
2663 */
2664void
e315cd28 2665qla24xx_reset_chip(scsi_qla_host_t *vha)
88c26663 2666{
e315cd28 2667 struct qla_hw_data *ha = vha->hw;
85880801
AV		 2668
2669 if (pci_channel_offline(ha->pdev) &&
2670 ha->flags.pci_channel_io_perm_failure) {
2671 return;
2672 }
2673
fd34f556 2674 ha->isp_ops->disable_intrs(ha);
88c26663 2675
4ea2c9c7
JC		 2676 qla25xx_manipulate_risc_semaphore(vha);
2677
88c26663 2678 /* Perform RISC reset. */
e315cd28 2679 qla24xx_reset_risc(vha);
88c26663
AV		 2680}
2681
1da177e4
LT		 2682/**
2683 * qla2x00_chip_diag() - Test chip for proper operation.
2db6228d 2684 * @vha: HA context
1da177e4
LT		 2685 *
2686 * Returns 0 on success.
2687 */
abbd8870 2688int
e315cd28 2689qla2x00_chip_diag(scsi_qla_host_t *vha)
1da177e4
LT		 2690{
2691 int rval;
e315cd28 2692 struct qla_hw_data *ha = vha->hw;
3d71644c 2693 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 2694 unsigned long flags = 0;
2695 uint16_t data;
2696 uint32_t cnt;
2697 uint16_t mb[5];
73208dfd 2698 struct req_que *req = ha->req_q_map[0];
1da177e4
LT		 2699
2700 /* Assume a failed state */
2701 rval = QLA_FUNCTION_FAILED;
2702
da4704d9
BVA		 2703 ql_dbg(ql_dbg_init, vha, 0x007b, "Testing device at %p.\n",
2704 &reg->flash_address);
1da177e4
LT		 2705
2706 spin_lock_irqsave(&ha->hardware_lock, flags);
2707
2708 /* Reset ISP chip. */
2709 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
2710
2711 /*
2712 * We need to have a delay here since the card will not respond while
2713 * in reset causing an MCA on some architectures.
2714 */
2715 udelay(20);
2716 data = qla2x00_debounce_register(&reg->ctrl_status);
2717 for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {
2718 udelay(5);
2719 data = RD_REG_WORD(&reg->ctrl_status);
2720 barrier();
2721 }
2722
2723 if (!cnt)
2724 goto chip_diag_failed;
2725
7c3df132
SK		 2726 ql_dbg(ql_dbg_init, vha, 0x007c,
2727 "Reset register cleared by chip reset.\n");
1da177e4
LT		 2728
2729 /* Reset RISC processor. */
2730 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
2731 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
2732
2733 /* Workaround for QLA2312 PCI parity error */
2734 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
2735 data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0));
2736 for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) {
2737 udelay(5);
2738 data = RD_MAILBOX_REG(ha, reg, 0);
fa2a1ce5 2739 barrier();
1da177e4
LT		 2740 }
2741 } else
2742 udelay(10);
2743
2744 if (!cnt)
2745 goto chip_diag_failed;
2746
2747 /* Check product ID of chip */
5a68a1c2 2748 ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product ID of chip.\n");
1da177e4
LT		 2749
2750 mb[1] = RD_MAILBOX_REG(ha, reg, 1);
2751 mb[2] = RD_MAILBOX_REG(ha, reg, 2);
2752 mb[3] = RD_MAILBOX_REG(ha, reg, 3);
2753 mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4));
2754 if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) ||
2755 mb[3] != PROD_ID_3) {
7c3df132
SK		 2756 ql_log(ql_log_warn, vha, 0x0062,
2757 "Wrong product ID = 0x%x,0x%x,0x%x.\n",
2758 mb[1], mb[2], mb[3]);
1da177e4
LT		 2759
2760 goto chip_diag_failed;
2761 }
2762 ha->product_id[0] = mb[1];
2763 ha->product_id[1] = mb[2];
2764 ha->product_id[2] = mb[3];
2765 ha->product_id[3] = mb[4];
2766
2767 /* Adjust fw RISC transfer size */
73208dfd 2768 if (req->length > 1024)
1da177e4
LT		 2769 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024;
2770 else
2771 ha->fw_transfer_size = REQUEST_ENTRY_SIZE *
73208dfd 2772 req->length;
1da177e4
LT		 2773
2774 if (IS_QLA2200(ha) &&
2775 RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) {
2776 /* Limit firmware transfer size with a 2200A */
7c3df132 2777 ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n");
1da177e4 2778
ea5b6382 2779 ha->device_type |= DT_ISP2200A;
1da177e4
LT		 2780 ha->fw_transfer_size = 128;
2781 }
2782
2783 /* Wrap Incoming Mailboxes Test. */
2784 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2785
7c3df132 2786 ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n");
e315cd28 2787 rval = qla2x00_mbx_reg_test(vha);
7c3df132
SK		 2788 if (rval)
2789 ql_log(ql_log_warn, vha, 0x0080,
2790 "Failed mailbox send register test.\n");
2791 else
1da177e4
LT		 2792 /* Flag a successful rval */
2793 rval = QLA_SUCCESS;
1da177e4
LT		 2794 spin_lock_irqsave(&ha->hardware_lock, flags);
2795
2796chip_diag_failed:
2797 if (rval)
7c3df132
SK		 2798 ql_log(ql_log_info, vha, 0x0081,
2799 "Chip diagnostics **** FAILED ****.\n");
1da177e4
LT		 2800
2801 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2802
2803 return (rval);
2804}
2805
0107109e
AV		 2806/**
2807 * qla24xx_chip_diag() - Test ISP24xx for proper operation.
2db6228d 2808 * @vha: HA context
0107109e
AV		 2809 *
2810 * Returns 0 on success.
2811 */
2812int
e315cd28 2813qla24xx_chip_diag(scsi_qla_host_t *vha)
0107109e
AV		 2814{
2815 int rval;
e315cd28 2816 struct qla_hw_data *ha = vha->hw;
73208dfd 2817 struct req_que *req = ha->req_q_map[0];
0107109e 2818
7ec0effd 2819 if (IS_P3P_TYPE(ha))
a9083016
GM		 2820 return QLA_SUCCESS;
2821
73208dfd 2822 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
0107109e 2823
e315cd28 2824 rval = qla2x00_mbx_reg_test(vha);
0107109e 2825 if (rval) {
7c3df132
SK		 2826 ql_log(ql_log_warn, vha, 0x0082,
2827 "Failed mailbox send register test.\n");
0107109e
AV		 2828 } else {
2829 /* Flag a successful rval */
2830 rval = QLA_SUCCESS;
2831 }
2832
2833 return rval;
2834}
2835
ad0a0b01
QT		 2836static void
2837qla2x00_alloc_offload_mem(scsi_qla_host_t *vha)
0107109e 2838{
a7a167bf 2839 int rval;
df613b96
AV		 2840 dma_addr_t tc_dma;
2841 void *tc;
e315cd28 2842 struct qla_hw_data *ha = vha->hw;
a7a167bf 2843
ad0a0b01 2844 if (ha->eft) {
7c3df132 2845 ql_dbg(ql_dbg_init, vha, 0x00bd,
ad0a0b01
QT		 2846 "%s: Offload Mem is already allocated.\n",
2847 __func__);
a7a167bf
AV		 2848 return;
2849 }
d4e3e04d 2850
ad0a0b01 2851 if (IS_FWI2_CAPABLE(ha)) {
df613b96 2852 /* Allocate memory for Fibre Channel Event Buffer. */
f73cb695
CD		 2853 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
2854 !IS_QLA27XX(ha))
436a7b11 2855 goto try_eft;
df613b96 2856
f73cb695
CD		 2857 if (ha->fce)
2858 dma_free_coherent(&ha->pdev->dev,
2859 FCE_SIZE, ha->fce, ha->fce_dma);
2860
2861 /* Allocate memory for Fibre Channel Event Buffer. */
0ea85b50
JP		 2862 tc = dma_zalloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
2863 GFP_KERNEL);
df613b96 2864 if (!tc) {
7c3df132
SK		 2865 ql_log(ql_log_warn, vha, 0x00be,
2866 "Unable to allocate (%d KB) for FCE.\n",
2867 FCE_SIZE / 1024);
17d98630 2868 goto try_eft;
df613b96
AV		 2869 }
2870
e315cd28 2871 rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS,
df613b96
AV		 2872 ha->fce_mb, &ha->fce_bufs);
2873 if (rval) {
7c3df132
SK		 2874 ql_log(ql_log_warn, vha, 0x00bf,
2875 "Unable to initialize FCE (%d).\n", rval);
df613b96
AV		 2876 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc,
2877 tc_dma);
2878 ha->flags.fce_enabled = 0;
17d98630 2879 goto try_eft;
df613b96 2880 }
cfb0919c 2881 ql_dbg(ql_dbg_init, vha, 0x00c0,
7c3df132 2882 "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024);
df613b96 2883
df613b96
AV		 2884 ha->flags.fce_enabled = 1;
2885 ha->fce_dma = tc_dma;
2886 ha->fce = tc;
f73cb695 2887
436a7b11 2888try_eft:
f73cb695
CD		 2889 if (ha->eft)
2890 dma_free_coherent(&ha->pdev->dev,
2891 EFT_SIZE, ha->eft, ha->eft_dma);
2892
436a7b11 2893 /* Allocate memory for Extended Trace Buffer. */
0ea85b50
JP		 2894 tc = dma_zalloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
2895 GFP_KERNEL);
436a7b11 2896 if (!tc) {
7c3df132
SK		 2897 ql_log(ql_log_warn, vha, 0x00c1,
2898 "Unable to allocate (%d KB) for EFT.\n",
2899 EFT_SIZE / 1024);
ad0a0b01 2900 goto eft_err;
436a7b11
AV		 2901 }
2902
e315cd28 2903 rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
436a7b11 2904 if (rval) {
7c3df132
SK		 2905 ql_log(ql_log_warn, vha, 0x00c2,
2906 "Unable to initialize EFT (%d).\n", rval);
436a7b11
AV		 2907 dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc,
2908 tc_dma);
ad0a0b01 2909 goto eft_err;
436a7b11 2910 }
cfb0919c 2911 ql_dbg(ql_dbg_init, vha, 0x00c3,
7c3df132 2912 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
436a7b11 2913
436a7b11
AV		 2914 ha->eft_dma = tc_dma;
2915 ha->eft = tc;
d4e3e04d 2916 }
f73cb695 2917
ad0a0b01
QT		 2918eft_err:
2919 return;
2920}
2921
2922void
2923qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
2924{
2925 uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
2926 eft_size, fce_size, mq_size;
2927 struct qla_hw_data *ha = vha->hw;
2928 struct req_que *req = ha->req_q_map[0];
2929 struct rsp_que *rsp = ha->rsp_q_map[0];
2930 struct qla2xxx_fw_dump *fw_dump;
2931
2932 dump_size = fixed_size = mem_size = eft_size = fce_size = mq_size = 0;
2933 req_q_size = rsp_q_size = 0;
2934
2935 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
2936 fixed_size = sizeof(struct qla2100_fw_dump);
2937 } else if (IS_QLA23XX(ha)) {
2938 fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
2939 mem_size = (ha->fw_memory_size - 0x11000 + 1) *
2940 sizeof(uint16_t);
2941 } else if (IS_FWI2_CAPABLE(ha)) {
2942 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
2943 fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem);
2944 else if (IS_QLA81XX(ha))
2945 fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
2946 else if (IS_QLA25XX(ha))
2947 fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
2948 else
2949 fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
2950
2951 mem_size = (ha->fw_memory_size - 0x100000 + 1) *
2952 sizeof(uint32_t);
2953 if (ha->mqenable) {
2954 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
2955 mq_size = sizeof(struct qla2xxx_mq_chain);
2956 /*
2957 * Allocate maximum buffer size for all queues.
2958 * Resizing must be done at end-of-dump processing.
2959 */
2960 mq_size += ha->max_req_queues *
2961 (req->length * sizeof(request_t));
2962 mq_size += ha->max_rsp_queues *
2963 (rsp->length * sizeof(response_t));
2964 }
2965 if (ha->tgt.atio_ring)
2966 mq_size += ha->tgt.atio_q_length * sizeof(request_t);
2967 /* Allocate memory for Fibre Channel Event Buffer. */
2968 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
2969 !IS_QLA27XX(ha))
2970 goto try_eft;
2971
2972 fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE;
2973try_eft:
2974 ql_dbg(ql_dbg_init, vha, 0x00c3,
2975 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
2976 eft_size = EFT_SIZE;
2977 }
2978
f73cb695
CD		 2979 if (IS_QLA27XX(ha)) {
2980 if (!ha->fw_dump_template) {
2981 ql_log(ql_log_warn, vha, 0x00ba,
2982 "Failed missing fwdump template\n");
2983 return;
2984 }
2985 dump_size = qla27xx_fwdt_calculate_dump_size(vha);
2986 ql_dbg(ql_dbg_init, vha, 0x00fa,
2987 "-> allocating fwdump (%x bytes)...\n", dump_size);
2988 goto allocate;
2989 }
2990
73208dfd
AC		 2991 req_q_size = req->length * sizeof(request_t);
2992 rsp_q_size = rsp->length * sizeof(response_t);
a7a167bf 2993 dump_size = offsetof(struct qla2xxx_fw_dump, isp);
2afa19a9 2994 dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size;
bb99de67
AV		 2995 ha->chain_offset = dump_size;
2996 dump_size += mq_size + fce_size;
d4e3e04d 2997
b945e777
QT		 2998 if (ha->exchoffld_buf)
2999 dump_size += sizeof(struct qla2xxx_offld_chain) +
3000 ha->exchoffld_size;
3001 if (ha->exlogin_buf)
3002 dump_size += sizeof(struct qla2xxx_offld_chain) +
3003 ha->exlogin_size;
3004
f73cb695 3005allocate:
ad0a0b01
QT		 3006 if (!ha->fw_dump_len || dump_size != ha->fw_dump_len) {
3007 fw_dump = vmalloc(dump_size);
3008 if (!fw_dump) {
3009 ql_log(ql_log_warn, vha, 0x00c4,
3010 "Unable to allocate (%d KB) for firmware dump.\n",
3011 dump_size / 1024);
3012 } else {
3013 if (ha->fw_dump)
3014 vfree(ha->fw_dump);
3015 ha->fw_dump = fw_dump;
3016
3017 ha->fw_dump_len = dump_size;
3018 ql_dbg(ql_dbg_init, vha, 0x00c5,
3019 "Allocated (%d KB) for firmware dump.\n",
3020 dump_size / 1024);
3021
3022 if (IS_QLA27XX(ha))
3023 return;
3024
3025 ha->fw_dump->signature[0] = 'Q';
3026 ha->fw_dump->signature[1] = 'L';
3027 ha->fw_dump->signature[2] = 'G';
3028 ha->fw_dump->signature[3] = 'C';
3029 ha->fw_dump->version = htonl(1);
3030
3031 ha->fw_dump->fixed_size = htonl(fixed_size);
3032 ha->fw_dump->mem_size = htonl(mem_size);
3033 ha->fw_dump->req_q_size = htonl(req_q_size);
3034 ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
3035
3036 ha->fw_dump->eft_size = htonl(eft_size);
3037 ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma));
3038 ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma));
3039
3040 ha->fw_dump->header_size =
3041 htonl(offsetof(struct qla2xxx_fw_dump, isp));
a7a167bf 3042 }
a7a167bf 3043 }
0107109e
AV		 3044}
3045
18e7555a
AV		 3046static int
3047qla81xx_mpi_sync(scsi_qla_host_t *vha)
3048{
3049#define MPS_MASK 0xe0
3050 int rval;
3051 uint16_t dc;
3052 uint32_t dw;
18e7555a
AV		 3053
3054 if (!IS_QLA81XX(vha->hw))
3055 return QLA_SUCCESS;
3056
3057 rval = qla2x00_write_ram_word(vha, 0x7c00, 1);
3058 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3059 ql_log(ql_log_warn, vha, 0x0105,
3060 "Unable to acquire semaphore.\n");
18e7555a
AV		 3061 goto done;
3062 }
3063
3064 pci_read_config_word(vha->hw->pdev, 0x54, &dc);
3065 rval = qla2x00_read_ram_word(vha, 0x7a15, &dw);
3066 if (rval != QLA_SUCCESS) {
7c3df132 3067 ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n");
18e7555a
AV		 3068 goto done_release;
3069 }
3070
3071 dc &= MPS_MASK;
3072 if (dc == (dw & MPS_MASK))
3073 goto done_release;
3074
3075 dw &= ~MPS_MASK;
3076 dw |= dc;
3077 rval = qla2x00_write_ram_word(vha, 0x7a15, dw);
3078 if (rval != QLA_SUCCESS) {
7c3df132 3079 ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n");
18e7555a
AV		 3080 }
3081
3082done_release:
3083 rval = qla2x00_write_ram_word(vha, 0x7c00, 0);
3084 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3085 ql_log(ql_log_warn, vha, 0x006d,
3086 "Unable to release semaphore.\n");
18e7555a
AV		 3087 }
3088
3089done:
3090 return rval;
3091}
3092
8d93f550
CD		 3093int
3094qla2x00_alloc_outstanding_cmds(struct qla_hw_data *ha, struct req_que *req)
3095{
3096 /* Don't try to reallocate the array */
3097 if (req->outstanding_cmds)
3098 return QLA_SUCCESS;
3099
d7459527 3100 if (!IS_FWI2_CAPABLE(ha))
8d93f550
CD		 3101 req->num_outstanding_cmds = DEFAULT_OUTSTANDING_COMMANDS;
3102 else {
03e8c680
QT		 3103 if (ha->cur_fw_xcb_count <= ha->cur_fw_iocb_count)
3104 req->num_outstanding_cmds = ha->cur_fw_xcb_count;
8d93f550 3105 else
03e8c680 3106 req->num_outstanding_cmds = ha->cur_fw_iocb_count;
8d93f550
CD		 3107 }
3108
3109 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
3110 req->num_outstanding_cmds, GFP_KERNEL);
3111
3112 if (!req->outstanding_cmds) {
3113 /*
3114 * Try to allocate a minimal size just so we can get through
3115 * initialization.
3116 */
3117 req->num_outstanding_cmds = MIN_OUTSTANDING_COMMANDS;
3118 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
3119 req->num_outstanding_cmds, GFP_KERNEL);
3120
3121 if (!req->outstanding_cmds) {
3122 ql_log(ql_log_fatal, NULL, 0x0126,
3123 "Failed to allocate memory for "
3124 "outstanding_cmds for req_que %p.\n", req);
3125 req->num_outstanding_cmds = 0;
3126 return QLA_FUNCTION_FAILED;
3127 }
3128 }
3129
3130 return QLA_SUCCESS;
3131}
3132
e4e3a2ce
QT		 3133#define PRINT_FIELD(_field, _flag, _str) { \
3134 if (a0->_field & _flag) {\
3135 if (p) {\
3136 strcat(ptr, "|");\
3137 ptr++;\
3138 leftover--;\
3139 } \
3140 len = snprintf(ptr, leftover, "%s", _str); \
3141 p = 1;\
3142 leftover -= len;\
3143 ptr += len; \
3144 } \
3145}
3146
3147static void qla2xxx_print_sfp_info(struct scsi_qla_host *vha)
3148{
3149#define STR_LEN 64
3150 struct sff_8247_a0 *a0 = (struct sff_8247_a0 *)vha->hw->sfp_data;
3151 u8 str[STR_LEN], *ptr, p;
3152 int leftover, len;
3153
3154 memset(str, 0, STR_LEN);
3155 snprintf(str, SFF_VEN_NAME_LEN+1, a0->vendor_name);
3156 ql_dbg(ql_dbg_init, vha, 0x015a,
3157 "SFP MFG Name: %s\n", str);
3158
3159 memset(str, 0, STR_LEN);
3160 snprintf(str, SFF_PART_NAME_LEN+1, a0->vendor_pn);
3161 ql_dbg(ql_dbg_init, vha, 0x015c,
3162 "SFP Part Name: %s\n", str);
3163
3164 /* media */
3165 memset(str, 0, STR_LEN);
3166 ptr = str;
3167 leftover = STR_LEN;
3168 p = len = 0;
3169 PRINT_FIELD(fc_med_cc9, FC_MED_TW, "Twin AX");
3170 PRINT_FIELD(fc_med_cc9, FC_MED_TP, "Twisted Pair");
3171 PRINT_FIELD(fc_med_cc9, FC_MED_MI, "Min Coax");
3172 PRINT_FIELD(fc_med_cc9, FC_MED_TV, "Video Coax");
3173 PRINT_FIELD(fc_med_cc9, FC_MED_M6, "MultiMode 62.5um");
3174 PRINT_FIELD(fc_med_cc9, FC_MED_M5, "MultiMode 50um");
3175 PRINT_FIELD(fc_med_cc9, FC_MED_SM, "SingleMode");
3176 ql_dbg(ql_dbg_init, vha, 0x0160,
3177 "SFP Media: %s\n", str);
3178
3179 /* link length */
3180 memset(str, 0, STR_LEN);
3181 ptr = str;
3182 leftover = STR_LEN;
3183 p = len = 0;
3184 PRINT_FIELD(fc_ll_cc7, FC_LL_VL, "Very Long");
3185 PRINT_FIELD(fc_ll_cc7, FC_LL_S, "Short");
3186 PRINT_FIELD(fc_ll_cc7, FC_LL_I, "Intermediate");
3187 PRINT_FIELD(fc_ll_cc7, FC_LL_L, "Long");
3188 PRINT_FIELD(fc_ll_cc7, FC_LL_M, "Medium");
3189 ql_dbg(ql_dbg_init, vha, 0x0196,
3190 "SFP Link Length: %s\n", str);
3191
3192 memset(str, 0, STR_LEN);
3193 ptr = str;
3194 leftover = STR_LEN;
3195 p = len = 0;
3196 PRINT_FIELD(fc_ll_cc7, FC_LL_SA, "Short Wave (SA)");
3197 PRINT_FIELD(fc_ll_cc7, FC_LL_LC, "Long Wave(LC)");
3198 PRINT_FIELD(fc_tec_cc8, FC_TEC_SN, "Short Wave (SN)");
3199 PRINT_FIELD(fc_tec_cc8, FC_TEC_SL, "Short Wave (SL)");
3200 PRINT_FIELD(fc_tec_cc8, FC_TEC_LL, "Long Wave (LL)");
3201 ql_dbg(ql_dbg_init, vha, 0x016e,
3202 "SFP FC Link Tech: %s\n", str);
3203
3204 if (a0->length_km)
3205 ql_dbg(ql_dbg_init, vha, 0x016f,
3206 "SFP Distant: %d km\n", a0->length_km);
3207 if (a0->length_100m)
3208 ql_dbg(ql_dbg_init, vha, 0x0170,
3209 "SFP Distant: %d m\n", a0->length_100m*100);
3210 if (a0->length_50um_10m)
3211 ql_dbg(ql_dbg_init, vha, 0x0189,
3212 "SFP Distant (WL=50um): %d m\n", a0->length_50um_10m * 10);
3213 if (a0->length_62um_10m)
3214 ql_dbg(ql_dbg_init, vha, 0x018a,
3215 "SFP Distant (WL=62.5um): %d m\n", a0->length_62um_10m * 10);
3216 if (a0->length_om4_10m)
3217 ql_dbg(ql_dbg_init, vha, 0x0194,
3218 "SFP Distant (OM4): %d m\n", a0->length_om4_10m * 10);
3219 if (a0->length_om3_10m)
3220 ql_dbg(ql_dbg_init, vha, 0x0195,
3221 "SFP Distant (OM3): %d m\n", a0->length_om3_10m * 10);
3222}
3223
3224
3225/*
3226 * Return Code:
3227 * QLA_SUCCESS: no action
3228 * QLA_INTERFACE_ERROR: SFP is not there.
3229 * QLA_FUNCTION_FAILED: detected New SFP
3230 */
3231int
3232qla24xx_detect_sfp(scsi_qla_host_t *vha)
3233{
3234 int rc = QLA_SUCCESS;
3235 struct sff_8247_a0 *a;
3236 struct qla_hw_data *ha = vha->hw;
3237
3238 if (!AUTO_DETECT_SFP_SUPPORT(vha))
3239 goto out;
3240
3241 rc = qla2x00_read_sfp_dev(vha, NULL, 0);
3242 if (rc)
3243 goto out;
3244
3245 a = (struct sff_8247_a0 *)vha->hw->sfp_data;
3246 qla2xxx_print_sfp_info(vha);
3247
3248 if (a->fc_ll_cc7 & FC_LL_VL || a->fc_ll_cc7 & FC_LL_L) {
3249 /* long range */
3250 ha->flags.detected_lr_sfp = 1;
3251
3252 if (a->length_km > 5 || a->length_100m > 50)
3253 ha->long_range_distance = LR_DISTANCE_10K;
3254 else
3255 ha->long_range_distance = LR_DISTANCE_5K;
3256
3257 if (ha->flags.detected_lr_sfp != ha->flags.using_lr_setting)
3258 ql_dbg(ql_dbg_async, vha, 0x507b,
3259 "Detected Long Range SFP.\n");
3260 } else {
3261 /* short range */
3262 ha->flags.detected_lr_sfp = 0;
3263 if (ha->flags.using_lr_setting)
3264 ql_dbg(ql_dbg_async, vha, 0x5084,
3265 "Detected Short Range SFP.\n");
3266 }
3267
3268 if (!vha->flags.init_done)
3269 rc = QLA_SUCCESS;
3270out:
3271 return rc;
3272}
3273
1da177e4
LT		 3274/**
3275 * qla2x00_setup_chip() - Load and start RISC firmware.
2db6228d 3276 * @vha: HA context
1da177e4
LT		 3277 *
3278 * Returns 0 on success.
3279 */
3280static int
e315cd28 3281qla2x00_setup_chip(scsi_qla_host_t *vha)
1da177e4 3282{
0107109e
AV		 3283 int rval;
3284 uint32_t srisc_address = 0;
e315cd28 3285 struct qla_hw_data *ha = vha->hw;
3db0652e
AV		 3286 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
3287 unsigned long flags;
dda772e8 3288 uint16_t fw_major_version;
3db0652e 3289
7ec0effd 3290 if (IS_P3P_TYPE(ha)) {
a9083016 3291 rval = ha->isp_ops->load_risc(vha, &srisc_address);
14e303d9
AV		 3292 if (rval == QLA_SUCCESS) {
3293 qla2x00_stop_firmware(vha);
a9083016 3294 goto enable_82xx_npiv;
14e303d9 3295 } else
b963752f 3296 goto failed;
a9083016
GM		 3297 }
3298
3db0652e
AV		 3299 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
3300 /* Disable SRAM, Instruction RAM and GP RAM parity. */
3301 spin_lock_irqsave(&ha->hardware_lock, flags);
3302 WRT_REG_WORD(&reg->hccr, (HCCR_ENABLE_PARITY + 0x0));
3303 RD_REG_WORD(&reg->hccr);
3304 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3305 }
1da177e4 3306
18e7555a
AV		 3307 qla81xx_mpi_sync(vha);
3308
1da177e4 3309 /* Load firmware sequences */
e315cd28 3310 rval = ha->isp_ops->load_risc(vha, &srisc_address);
0107109e 3311 if (rval == QLA_SUCCESS) {
7c3df132
SK		 3312 ql_dbg(ql_dbg_init, vha, 0x00c9,
3313 "Verifying Checksum of loaded RISC code.\n");
1da177e4 3314
e315cd28 3315 rval = qla2x00_verify_checksum(vha, srisc_address);
1da177e4
LT		 3316 if (rval == QLA_SUCCESS) {
3317 /* Start firmware execution. */
7c3df132
SK		 3318 ql_dbg(ql_dbg_init, vha, 0x00ca,
3319 "Starting firmware.\n");
1da177e4 3320
b0d6cabd
HM		 3321 if (ql2xexlogins)
3322 ha->flags.exlogins_enabled = 1;
3323
99e1b683 3324 if (qla_is_exch_offld_enabled(vha))
2f56a7f1
HM		 3325 ha->flags.exchoffld_enabled = 1;
3326
e315cd28 3327 rval = qla2x00_execute_fw(vha, srisc_address);
1da177e4 3328 /* Retrieve firmware information. */
dda772e8 3329 if (rval == QLA_SUCCESS) {
e4e3a2ce
QT		 3330 qla24xx_detect_sfp(vha);
3331
b0d6cabd
HM		 3332 rval = qla2x00_set_exlogins_buffer(vha);
3333 if (rval != QLA_SUCCESS)
3334 goto failed;
3335
2f56a7f1
HM		 3336 rval = qla2x00_set_exchoffld_buffer(vha);
3337 if (rval != QLA_SUCCESS)
3338 goto failed;
3339
a9083016 3340enable_82xx_npiv:
dda772e8 3341 fw_major_version = ha->fw_major_version;
7ec0effd 3342 if (IS_P3P_TYPE(ha))
3173167f 3343 qla82xx_check_md_needed(vha);
6246b8a1
GM		 3344 else
3345 rval = qla2x00_get_fw_version(vha);
ca9e9c3e
AV		 3346 if (rval != QLA_SUCCESS)
3347 goto failed;
2c3dfe3f 3348 ha->flags.npiv_supported = 0;
e315cd28 3349 if (IS_QLA2XXX_MIDTYPE(ha) &&
946fb891 3350 (ha->fw_attributes & BIT_2)) {
2c3dfe3f 3351 ha->flags.npiv_supported = 1;
4d0ea247
SJ		 3352 if ((!ha->max_npiv_vports) ||
3353 ((ha->max_npiv_vports + 1) %
eb66dc60 3354 MIN_MULTI_ID_FABRIC))
4d0ea247 3355 ha->max_npiv_vports =
eb66dc60 3356 MIN_MULTI_ID_FABRIC - 1;
4d0ea247 3357 }
03e8c680 3358 qla2x00_get_resource_cnts(vha);
d743de66 3359
8d93f550
CD		 3360 /*
3361 * Allocate the array of outstanding commands
3362 * now that we know the firmware resources.
3363 */
3364 rval = qla2x00_alloc_outstanding_cmds(ha,
3365 vha->req);
3366 if (rval != QLA_SUCCESS)
3367 goto failed;
3368
ad0a0b01
QT		 3369 if (!fw_major_version && !(IS_P3P_TYPE(ha)))
3370 qla2x00_alloc_offload_mem(vha);
3371
3372 if (ql2xallocfwdump && !(IS_P3P_TYPE(ha)))
08de2844 3373 qla2x00_alloc_fw_dump(vha);
ad0a0b01 3374
3b6e5b9d
CD		 3375 } else {
3376 goto failed;
1da177e4
LT		 3377 }
3378 } else {
7c3df132
SK		 3379 ql_log(ql_log_fatal, vha, 0x00cd,
3380 "ISP Firmware failed checksum.\n");
3381 goto failed;
1da177e4 3382 }
c74d88a4
AV		 3383 } else
3384 goto failed;
1da177e4 3385
3db0652e
AV		 3386 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
3387 /* Enable proper parity. */
3388 spin_lock_irqsave(&ha->hardware_lock, flags);
3389 if (IS_QLA2300(ha))
3390 /* SRAM parity */
3391 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x1);
3392 else
3393 /* SRAM, Instruction RAM and GP RAM parity */
3394 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x7);
3395 RD_REG_WORD(&reg->hccr);
3396 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3397 }
3398
f3982d89
CD		 3399 if (IS_QLA27XX(ha))
3400 ha->flags.fac_supported = 1;
3401 else if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
1d2874de
JC		 3402 uint32_t size;
3403
3404 rval = qla81xx_fac_get_sector_size(vha, &size);
3405 if (rval == QLA_SUCCESS) {
3406 ha->flags.fac_supported = 1;
3407 ha->fdt_block_size = size << 2;
3408 } else {
7c3df132 3409 ql_log(ql_log_warn, vha, 0x00ce,
1d2874de
JC		 3410 "Unsupported FAC firmware (%d.%02d.%02d).\n",
3411 ha->fw_major_version, ha->fw_minor_version,
3412 ha->fw_subminor_version);
1ca60e3b 3413
f73cb695 3414 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
6246b8a1
GM		 3415 ha->flags.fac_supported = 0;
3416 rval = QLA_SUCCESS;
3417 }
1d2874de
JC		 3418 }
3419 }
ca9e9c3e 3420failed:
1da177e4 3421 if (rval) {
7c3df132
SK		 3422 ql_log(ql_log_fatal, vha, 0x00cf,
3423 "Setup chip ****FAILED****.\n");
1da177e4
LT		 3424 }
3425
3426 return (rval);
3427}
3428
3429/**
3430 * qla2x00_init_response_q_entries() - Initializes response queue entries.
2db6228d 3431 * @rsp: response queue
1da177e4
LT		 3432 *
3433 * Beginning of request ring has initialization control block already built
3434 * by nvram config routine.
3435 *
3436 * Returns 0 on success.
3437 */
73208dfd
AC		 3438void
3439qla2x00_init_response_q_entries(struct rsp_que *rsp)
1da177e4
LT		 3440{
3441 uint16_t cnt;
3442 response_t *pkt;
3443
2afa19a9
AC		 3444 rsp->ring_ptr = rsp->ring;
3445 rsp->ring_index = 0;
3446 rsp->status_srb = NULL;
e315cd28
AC		 3447 pkt = rsp->ring_ptr;
3448 for (cnt = 0; cnt < rsp->length; cnt++) {
1da177e4
LT		 3449 pkt->signature = RESPONSE_PROCESSED;
3450 pkt++;
3451 }
1da177e4
LT		 3452}
3453
3454/**
3455 * qla2x00_update_fw_options() - Read and process firmware options.
2db6228d 3456 * @vha: HA context
1da177e4
LT		 3457 *
3458 * Returns 0 on success.
3459 */
abbd8870 3460void
e315cd28 3461qla2x00_update_fw_options(scsi_qla_host_t *vha)
1da177e4
LT		 3462{
3463 uint16_t swing, emphasis, tx_sens, rx_sens;
e315cd28 3464 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3465
3466 memset(ha->fw_options, 0, sizeof(ha->fw_options));
e315cd28 3467 qla2x00_get_fw_options(vha, ha->fw_options);
1da177e4
LT		 3468
3469 if (IS_QLA2100(ha) || IS_QLA2200(ha))
3470 return;
3471
3472 /* Serial Link options. */
7c3df132
SK		 3473 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
3474 "Serial link options.\n");
3475 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
3476 (uint8_t *)&ha->fw_seriallink_options,
3477 sizeof(ha->fw_seriallink_options));
1da177e4
LT		 3478
3479 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
3480 if (ha->fw_seriallink_options[3] & BIT_2) {
3481 ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING;
3482
3483 /* 1G settings */
3484 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
3485 emphasis = (ha->fw_seriallink_options[2] &
3486 (BIT_4 | BIT_3)) >> 3;
3487 tx_sens = ha->fw_seriallink_options[0] &
fa2a1ce5 3488 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 3489 rx_sens = (ha->fw_seriallink_options[0] &
3490 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
3491 ha->fw_options[10] = (emphasis << 14) | (swing << 8);
3492 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
3493 if (rx_sens == 0x0)
3494 rx_sens = 0x3;
3495 ha->fw_options[10] |= (tx_sens << 4) | rx_sens;
3496 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
3497 ha->fw_options[10] |= BIT_5 |
3498 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
3499 (tx_sens & (BIT_1 | BIT_0));
3500
3501 /* 2G settings */
3502 swing = (ha->fw_seriallink_options[2] &
3503 (BIT_7 | BIT_6 | BIT_5)) >> 5;
3504 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
3505 tx_sens = ha->fw_seriallink_options[1] &
fa2a1ce5 3506 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 3507 rx_sens = (ha->fw_seriallink_options[1] &
3508 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
3509 ha->fw_options[11] = (emphasis << 14) | (swing << 8);
3510 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
3511 if (rx_sens == 0x0)
3512 rx_sens = 0x3;
3513 ha->fw_options[11] |= (tx_sens << 4) | rx_sens;
3514 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
3515 ha->fw_options[11] |= BIT_5 |
3516 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
3517 (tx_sens & (BIT_1 | BIT_0));
3518 }
3519
3520 /* FCP2 options. */
3521 /* Return command IOCBs without waiting for an ABTS to complete. */
3522 ha->fw_options[3] |= BIT_13;
3523
3524 /* LED scheme. */
3525 if (ha->flags.enable_led_scheme)
3526 ha->fw_options[2] |= BIT_12;
3527
48c02fde
AV		 3528 /* Detect ISP6312. */
3529 if (IS_QLA6312(ha))
3530 ha->fw_options[2] |= BIT_13;
3531
088d09d4
GM		 3532 /* Set Retry FLOGI in case of P2P connection */
3533 if (ha->operating_mode == P2P) {
3534 ha->fw_options[2] |= BIT_3;
3535 ql_dbg(ql_dbg_disc, vha, 0x2100,
3536 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
3537 __func__, ha->fw_options[2]);
3538 }
3539
1da177e4 3540 /* Update firmware options. */
e315cd28 3541 qla2x00_set_fw_options(vha, ha->fw_options);
1da177e4
LT		 3542}
3543
0107109e 3544void
e315cd28 3545qla24xx_update_fw_options(scsi_qla_host_t *vha)
0107109e
AV		 3546{
3547 int rval;
e315cd28 3548 struct qla_hw_data *ha = vha->hw;
0107109e 3549
7ec0effd 3550 if (IS_P3P_TYPE(ha))
a9083016
GM		 3551 return;
3552
f198cafa
HM		 3553 /* Hold status IOCBs until ABTS response received. */
3554 if (ql2xfwholdabts)
3555 ha->fw_options[3] |= BIT_12;
3556
088d09d4
GM		 3557 /* Set Retry FLOGI in case of P2P connection */
3558 if (ha->operating_mode == P2P) {
3559 ha->fw_options[2] |= BIT_3;
3560 ql_dbg(ql_dbg_disc, vha, 0x2101,
3561 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
3562 __func__, ha->fw_options[2]);
3563 }
3564
41dc529a 3565 /* Move PUREX, ABTS RX & RIDA to ATIOQ */
3c4810ff
QT		 3566 if (ql2xmvasynctoatio &&
3567 (IS_QLA83XX(ha) || IS_QLA27XX(ha))) {
41dc529a
QT		 3568 if (qla_tgt_mode_enabled(vha) ||
3569 qla_dual_mode_enabled(vha))
3570 ha->fw_options[2] |= BIT_11;
3571 else
3572 ha->fw_options[2] &= ~BIT_11;
3573 }
3574
f7e761f5
QT		 3575 if (IS_QLA25XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
3576 /*
3577 * Tell FW to track each exchange to prevent
3578 * driver from using stale exchange.
3579 */
3580 if (qla_tgt_mode_enabled(vha) ||
3581 qla_dual_mode_enabled(vha))
3582 ha->fw_options[2] |= BIT_4;
3583 else
3584 ha->fw_options[2] &= ~BIT_4;
9ecf0b0d
QT		 3585
3586 /* Reserve 1/2 of emergency exchanges for ELS.*/
3587 if (qla2xuseresexchforels)
3588 ha->fw_options[2] |= BIT_8;
3589 else
3590 ha->fw_options[2] &= ~BIT_8;
f7e761f5
QT		 3591 }
3592
83548fe2
QT		 3593 ql_dbg(ql_dbg_init, vha, 0x00e8,
3594 "%s, add FW options 1-3 = 0x%04x 0x%04x 0x%04x mode %x\n",
3595 __func__, ha->fw_options[1], ha->fw_options[2],
3596 ha->fw_options[3], vha->host->active_mode);
3c4810ff
QT		 3597
3598 if (ha->fw_options[1] || ha->fw_options[2] || ha->fw_options[3])
3599 qla2x00_set_fw_options(vha, ha->fw_options);
41dc529a 3600
0107109e 3601 /* Update Serial Link options. */
f94097ed 3602 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0)
0107109e
AV		 3603 return;
3604
e315cd28 3605 rval = qla2x00_set_serdes_params(vha,
f94097ed
AV		 3606 le16_to_cpu(ha->fw_seriallink_options24[1]),
3607 le16_to_cpu(ha->fw_seriallink_options24[2]),
3608 le16_to_cpu(ha->fw_seriallink_options24[3]));
0107109e 3609 if (rval != QLA_SUCCESS) {
7c3df132 3610 ql_log(ql_log_warn, vha, 0x0104,
0107109e
AV		 3611 "Unable to update Serial Link options (%x).\n", rval);
3612 }
3613}
3614
abbd8870 3615void
e315cd28 3616qla2x00_config_rings(struct scsi_qla_host *vha)
abbd8870 3617{
e315cd28 3618 struct qla_hw_data *ha = vha->hw;
3d71644c 3619 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
73208dfd
AC		 3620 struct req_que *req = ha->req_q_map[0];
3621 struct rsp_que *rsp = ha->rsp_q_map[0];
abbd8870
AV		 3622
3623 /* Setup ring parameters in initialization control block. */
ad950360
BVA		 3624 ha->init_cb->request_q_outpointer = cpu_to_le16(0);
3625 ha->init_cb->response_q_inpointer = cpu_to_le16(0);
e315cd28
AC		 3626 ha->init_cb->request_q_length = cpu_to_le16(req->length);
3627 ha->init_cb->response_q_length = cpu_to_le16(rsp->length);
3628 ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
3629 ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
3630 ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
3631 ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
abbd8870
AV		 3632
3633 WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0);
3634 WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0);
3635 WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0);
3636 WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0);
3637 RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */
3638}
3639
0107109e 3640void
e315cd28 3641qla24xx_config_rings(struct scsi_qla_host *vha)
0107109e 3642{
e315cd28 3643 struct qla_hw_data *ha = vha->hw;
118e2ef9 3644 device_reg_t *reg = ISP_QUE_REG(ha, 0);
73208dfd
AC		 3645 struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
3646 struct qla_msix_entry *msix;
0107109e 3647 struct init_cb_24xx *icb;
73208dfd
AC		 3648 uint16_t rid = 0;
3649 struct req_que *req = ha->req_q_map[0];
3650 struct rsp_que *rsp = ha->rsp_q_map[0];
0107109e 3651
6246b8a1 3652 /* Setup ring parameters in initialization control block. */
0107109e 3653 icb = (struct init_cb_24xx *)ha->init_cb;
ad950360
BVA		 3654 icb->request_q_outpointer = cpu_to_le16(0);
3655 icb->response_q_inpointer = cpu_to_le16(0);
e315cd28
AC		 3656 icb->request_q_length = cpu_to_le16(req->length);
3657 icb->response_q_length = cpu_to_le16(rsp->length);
3658 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
3659 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
3660 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
3661 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
0107109e 3662
2d70c103 3663 /* Setup ATIO queue dma pointers for target mode */
ad950360 3664 icb->atio_q_inpointer = cpu_to_le16(0);
2d70c103
NB		 3665 icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length);
3666 icb->atio_q_address[0] = cpu_to_le32(LSD(ha->tgt.atio_dma));
3667 icb->atio_q_address[1] = cpu_to_le32(MSD(ha->tgt.atio_dma));
3668
7c6300e3 3669 if (IS_SHADOW_REG_CAPABLE(ha))
ad950360 3670 icb->firmware_options_2 |= cpu_to_le32(BIT_30|BIT_29);
7c6300e3 3671
f73cb695 3672 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
ad950360
BVA		 3673 icb->qos = cpu_to_le16(QLA_DEFAULT_QUE_QOS);
3674 icb->rid = cpu_to_le16(rid);
73208dfd
AC		 3675 if (ha->flags.msix_enabled) {
3676 msix = &ha->msix_entries[1];
83548fe2 3677 ql_dbg(ql_dbg_init, vha, 0x0019,
7c3df132
SK		 3678 "Registering vector 0x%x for base que.\n",
3679 msix->entry);
73208dfd
AC		 3680 icb->msix = cpu_to_le16(msix->entry);
3681 }
3682 /* Use alternate PCI bus number */
3683 if (MSB(rid))
ad950360 3684 icb->firmware_options_2 |= cpu_to_le32(BIT_19);
73208dfd
AC		 3685 /* Use alternate PCI devfn */
3686 if (LSB(rid))
ad950360 3687 icb->firmware_options_2 |= cpu_to_le32(BIT_18);
73208dfd 3688
3155754a 3689 /* Use Disable MSIX Handshake mode for capable adapters */
6246b8a1
GM		 3690 if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) &&
3691 (ha->flags.msix_enabled)) {
ad950360 3692 icb->firmware_options_2 &= cpu_to_le32(~BIT_22);
3155754a 3693 ha->flags.disable_msix_handshake = 1;
7c3df132
SK		 3694 ql_dbg(ql_dbg_init, vha, 0x00fe,
3695 "MSIX Handshake Disable Mode turned on.\n");
3155754a 3696 } else {
ad950360 3697 icb->firmware_options_2 |= cpu_to_le32(BIT_22);
3155754a 3698 }
ad950360 3699 icb->firmware_options_2 |= cpu_to_le32(BIT_23);
73208dfd
AC		 3700
3701 WRT_REG_DWORD(&reg->isp25mq.req_q_in, 0);
3702 WRT_REG_DWORD(&reg->isp25mq.req_q_out, 0);
3703 WRT_REG_DWORD(&reg->isp25mq.rsp_q_in, 0);
3704 WRT_REG_DWORD(&reg->isp25mq.rsp_q_out, 0);
3705 } else {
3706 WRT_REG_DWORD(&reg->isp24.req_q_in, 0);
3707 WRT_REG_DWORD(&reg->isp24.req_q_out, 0);
3708 WRT_REG_DWORD(&reg->isp24.rsp_q_in, 0);
3709 WRT_REG_DWORD(&reg->isp24.rsp_q_out, 0);
3710 }
aa230bc5 3711 qlt_24xx_config_rings(vha);
2d70c103 3712
73208dfd
AC		 3713 /* PCI posting */
3714 RD_REG_DWORD(&ioreg->hccr);
0107109e
AV		 3715}
3716
1da177e4
LT		 3717/**
3718 * qla2x00_init_rings() - Initializes firmware.
2db6228d 3719 * @vha: HA context
1da177e4
LT		 3720 *
3721 * Beginning of request ring has initialization control block already built
3722 * by nvram config routine.
3723 *
3724 * Returns 0 on success.
3725 */
8ae6d9c7 3726int
e315cd28 3727qla2x00_init_rings(scsi_qla_host_t *vha)
1da177e4
LT		 3728{
3729 int rval;
3730 unsigned long flags = 0;
29bdccbe 3731 int cnt, que;
e315cd28 3732 struct qla_hw_data *ha = vha->hw;
29bdccbe
AC		 3733 struct req_que *req;
3734 struct rsp_que *rsp;
2c3dfe3f
SJ		 3735 struct mid_init_cb_24xx *mid_init_cb =
3736 (struct mid_init_cb_24xx *) ha->init_cb;
1da177e4
LT		 3737
3738 spin_lock_irqsave(&ha->hardware_lock, flags);
3739
3740 /* Clear outstanding commands array. */
2afa19a9 3741 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 3742 req = ha->req_q_map[que];
cb43285f 3743 if (!req || !test_bit(que, ha->req_qid_map))
29bdccbe 3744 continue;
7c6300e3
JC		 3745 req->out_ptr = (void *)(req->ring + req->length);
3746 *req->out_ptr = 0;
8d93f550 3747 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++)
29bdccbe 3748 req->outstanding_cmds[cnt] = NULL;
1da177e4 3749
2afa19a9 3750 req->current_outstanding_cmd = 1;
1da177e4 3751
29bdccbe
AC		 3752 /* Initialize firmware. */
3753 req->ring_ptr = req->ring;
3754 req->ring_index = 0;
3755 req->cnt = req->length;
3756 }
1da177e4 3757
2afa19a9 3758 for (que = 0; que < ha->max_rsp_queues; que++) {
29bdccbe 3759 rsp = ha->rsp_q_map[que];
cb43285f 3760 if (!rsp || !test_bit(que, ha->rsp_qid_map))
29bdccbe 3761 continue;
7c6300e3
JC		 3762 rsp->in_ptr = (void *)(rsp->ring + rsp->length);
3763 *rsp->in_ptr = 0;
29bdccbe 3764 /* Initialize response queue entries */
8ae6d9c7
GM		 3765 if (IS_QLAFX00(ha))
3766 qlafx00_init_response_q_entries(rsp);
3767 else
3768 qla2x00_init_response_q_entries(rsp);
29bdccbe 3769 }
1da177e4 3770
2d70c103
NB		 3771 ha->tgt.atio_ring_ptr = ha->tgt.atio_ring;
3772 ha->tgt.atio_ring_index = 0;
3773 /* Initialize ATIO queue entries */
3774 qlt_init_atio_q_entries(vha);
3775
e315cd28 3776 ha->isp_ops->config_rings(vha);
1da177e4
LT		 3777
3778 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3779
8ae6d9c7
GM		 3780 ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n");
3781
3782 if (IS_QLAFX00(ha)) {
3783 rval = qlafx00_init_firmware(vha, ha->init_cb_size);
3784 goto next_check;
3785 }
3786
1da177e4 3787 /* Update any ISP specific firmware options before initialization. */
e315cd28 3788 ha->isp_ops->update_fw_options(vha);
1da177e4 3789
605aa2bc 3790 if (ha->flags.npiv_supported) {
45980cc2 3791 if (ha->operating_mode == LOOP && !IS_CNA_CAPABLE(ha))
605aa2bc 3792 ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
c48339de 3793 mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
605aa2bc
LC		 3794 }
3795
24a08138 3796 if (IS_FWI2_CAPABLE(ha)) {
ad950360 3797 mid_init_cb->options = cpu_to_le16(BIT_1);
24a08138 3798 mid_init_cb->init_cb.execution_throttle =
03e8c680 3799 cpu_to_le16(ha->cur_fw_xcb_count);
40f3862b
JC		 3800 ha->flags.dport_enabled =
3801 (mid_init_cb->init_cb.firmware_options_1 & BIT_7) != 0;
3802 ql_dbg(ql_dbg_init, vha, 0x0191, "DPORT Support: %s.\n",
3803 (ha->flags.dport_enabled) ? "enabled" : "disabled");
3804 /* FA-WWPN Status */
2486c627 3805 ha->flags.fawwpn_enabled =
40f3862b 3806 (mid_init_cb->init_cb.firmware_options_1 & BIT_6) != 0;
83548fe2 3807 ql_dbg(ql_dbg_init, vha, 0x00bc, "FA-WWPN Support: %s.\n",
2486c627 3808 (ha->flags.fawwpn_enabled) ? "enabled" : "disabled");
24a08138 3809 }
2c3dfe3f 3810
e315cd28 3811 rval = qla2x00_init_firmware(vha, ha->init_cb_size);
8ae6d9c7 3812next_check:
1da177e4 3813 if (rval) {
7c3df132
SK		 3814 ql_log(ql_log_fatal, vha, 0x00d2,
3815 "Init Firmware **** FAILED ****.\n");
1da177e4 3816 } else {
7c3df132
SK		 3817 ql_dbg(ql_dbg_init, vha, 0x00d3,
3818 "Init Firmware -- success.\n");
4b60c827 3819 QLA_FW_STARTED(ha);
1da177e4
LT		 3820 }
3821
3822 return (rval);
3823}
3824
3825/**
3826 * qla2x00_fw_ready() - Waits for firmware ready.
2db6228d 3827 * @vha: HA context
1da177e4
LT		 3828 *
3829 * Returns 0 on success.
3830 */
3831static int
e315cd28 3832qla2x00_fw_ready(scsi_qla_host_t *vha)
1da177e4
LT		 3833{
3834 int rval;
4d4df193 3835 unsigned long wtime, mtime, cs84xx_time;
1da177e4
LT		 3836 uint16_t min_wait; /* Minimum wait time if loop is down */
3837 uint16_t wait_time; /* Wait time if loop is coming ready */
b5a340dd 3838 uint16_t state[6];
e315cd28 3839 struct qla_hw_data *ha = vha->hw;
1da177e4 3840
8ae6d9c7
GM		 3841 if (IS_QLAFX00(vha->hw))
3842 return qlafx00_fw_ready(vha);
3843
1da177e4
LT		 3844 rval = QLA_SUCCESS;
3845
33461491
CD		 3846 /* Time to wait for loop down */
3847 if (IS_P3P_TYPE(ha))
3848 min_wait = 30;
3849 else
3850 min_wait = 20;
1da177e4
LT		 3851
3852 /*
3853 * Firmware should take at most one RATOV to login, plus 5 seconds for
3854 * our own processing.
3855 */
3856 if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) {
3857 wait_time = min_wait;
3858 }
3859
3860 /* Min wait time if loop down */
3861 mtime = jiffies + (min_wait * HZ);
3862
3863 /* wait time before firmware ready */
3864 wtime = jiffies + (wait_time * HZ);
3865
3866 /* Wait for ISP to finish LIP */
e315cd28 3867 if (!vha->flags.init_done)
7c3df132
SK		 3868 ql_log(ql_log_info, vha, 0x801e,
3869 "Waiting for LIP to complete.\n");
1da177e4
LT		 3870
3871 do {
5b939038 3872 memset(state, -1, sizeof(state));
e315cd28 3873 rval = qla2x00_get_firmware_state(vha, state);
1da177e4 3874 if (rval == QLA_SUCCESS) {
4d4df193 3875 if (state[0] < FSTATE_LOSS_OF_SYNC) {
e315cd28 3876 vha->device_flags &= ~DFLG_NO_CABLE;
1da177e4 3877 }
4d4df193 3878 if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) {
7c3df132
SK		 3879 ql_dbg(ql_dbg_taskm, vha, 0x801f,
3880 "fw_state=%x 84xx=%x.\n", state[0],
3881 state[2]);
4d4df193
HK		 3882 if ((state[2] & FSTATE_LOGGED_IN) &&
3883 (state[2] & FSTATE_WAITING_FOR_VERIFY)) {
7c3df132
SK		 3884 ql_dbg(ql_dbg_taskm, vha, 0x8028,
3885 "Sending verify iocb.\n");
4d4df193
HK		 3886
3887 cs84xx_time = jiffies;
e315cd28 3888 rval = qla84xx_init_chip(vha);
7c3df132
SK		 3889 if (rval != QLA_SUCCESS) {
3890 ql_log(ql_log_warn,
cfb0919c 3891 vha, 0x8007,
7c3df132 3892 "Init chip failed.\n");
4d4df193 3893 break;
7c3df132 3894 }
4d4df193
HK		 3895
3896 /* Add time taken to initialize. */
3897 cs84xx_time = jiffies - cs84xx_time;
3898 wtime += cs84xx_time;
3899 mtime += cs84xx_time;
cfb0919c 3900 ql_dbg(ql_dbg_taskm, vha, 0x8008,
7c3df132
SK		 3901 "Increasing wait time by %ld. "
3902 "New time %ld.\n", cs84xx_time,
3903 wtime);
4d4df193
HK		 3904 }
3905 } else if (state[0] == FSTATE_READY) {
7c3df132
SK		 3906 ql_dbg(ql_dbg_taskm, vha, 0x8037,
3907 "F/W Ready - OK.\n");
1da177e4 3908
e315cd28 3909 qla2x00_get_retry_cnt(vha, &ha->retry_count,
1da177e4
LT		 3910 &ha->login_timeout, &ha->r_a_tov);
3911
3912 rval = QLA_SUCCESS;
3913 break;
3914 }
3915
3916 rval = QLA_FUNCTION_FAILED;
3917
e315cd28 3918 if (atomic_read(&vha->loop_down_timer) &&
4d4df193 3919 state[0] != FSTATE_READY) {
1da177e4 3920 /* Loop down. Timeout on min_wait for states
fa2a1ce5
AV		 3921 * other than Wait for Login.
3922 */
1da177e4 3923 if (time_after_eq(jiffies, mtime)) {
7c3df132 3924 ql_log(ql_log_info, vha, 0x8038,
1da177e4
LT		 3925 "Cable is unplugged...\n");
3926
e315cd28 3927 vha->device_flags |= DFLG_NO_CABLE;
1da177e4
LT		 3928 break;
3929 }
3930 }
3931 } else {
3932 /* Mailbox cmd failed. Timeout on min_wait. */
cdbb0a4f 3933 if (time_after_eq(jiffies, mtime) ||
7190575f 3934 ha->flags.isp82xx_fw_hung)
1da177e4
LT		 3935 break;
3936 }
3937
3938 if (time_after_eq(jiffies, wtime))
3939 break;
3940
3941 /* Delay for a while */
3942 msleep(500);
1da177e4
LT		 3943 } while (1);
3944
7c3df132 3945 ql_dbg(ql_dbg_taskm, vha, 0x803a,
b5a340dd
JC		 3946 "fw_state=%x (%x, %x, %x, %x %x) curr time=%lx.\n", state[0],
3947 state[1], state[2], state[3], state[4], state[5], jiffies);
1da177e4 3948
cfb0919c 3949 if (rval && !(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132
SK		 3950 ql_log(ql_log_warn, vha, 0x803b,
3951 "Firmware ready **** FAILED ****.\n");
1da177e4
LT		 3952 }
3953
3954 return (rval);
3955}
3956
3957/*
3958* qla2x00_configure_hba
3959* Setup adapter context.
3960*
3961* Input:
3962* ha = adapter state pointer.
3963*
3964* Returns:
3965* 0 = success
3966*
3967* Context:
3968* Kernel context.
3969*/
3970static int
e315cd28 3971qla2x00_configure_hba(scsi_qla_host_t *vha)
1da177e4
LT		 3972{
3973 int rval;
3974 uint16_t loop_id;
3975 uint16_t topo;
2c3dfe3f 3976 uint16_t sw_cap;
1da177e4
LT		 3977 uint8_t al_pa;
3978 uint8_t area;
3979 uint8_t domain;
3980 char connect_type[22];
e315cd28 3981 struct qla_hw_data *ha = vha->hw;
61e1b269 3982 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
482c9dc7 3983 port_id_t id;
9d1aa4e1 3984 unsigned long flags;
1da177e4
LT		 3985
3986 /* Get host addresses. */
e315cd28 3987 rval = qla2x00_get_adapter_id(vha,
2c3dfe3f 3988 &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
1da177e4 3989 if (rval != QLA_SUCCESS) {
e315cd28 3990 if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
6246b8a1 3991 IS_CNA_CAPABLE(ha) ||
33135aa2 3992 (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
7c3df132
SK		 3993 ql_dbg(ql_dbg_disc, vha, 0x2008,
3994 "Loop is in a transition state.\n");
33135aa2 3995 } else {
7c3df132
SK		 3996 ql_log(ql_log_warn, vha, 0x2009,
3997 "Unable to get host loop ID.\n");
61e1b269
JC		 3998 if (IS_FWI2_CAPABLE(ha) && (vha == base_vha) &&
3999 (rval == QLA_COMMAND_ERROR && loop_id == 0x1b)) {
4000 ql_log(ql_log_warn, vha, 0x1151,
4001 "Doing link init.\n");
4002 if (qla24xx_link_initialize(vha) == QLA_SUCCESS)
4003 return rval;
4004 }
e315cd28 4005 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
33135aa2 4006 }
1da177e4
LT		 4007 return (rval);
4008 }
4009
4010 if (topo == 4) {
7c3df132
SK		 4011 ql_log(ql_log_info, vha, 0x200a,
4012 "Cannot get topology - retrying.\n");
1da177e4
LT		 4013 return (QLA_FUNCTION_FAILED);
4014 }
4015
e315cd28 4016 vha->loop_id = loop_id;
1da177e4
LT		 4017
4018 /* initialize */
4019 ha->min_external_loopid = SNS_FIRST_LOOP_ID;
4020 ha->operating_mode = LOOP;
2c3dfe3f 4021 ha->switch_cap = 0;
1da177e4
LT		 4022
4023 switch (topo) {
4024 case 0:
7c3df132 4025 ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n");
1da177e4
LT		 4026 ha->current_topology = ISP_CFG_NL;
4027 strcpy(connect_type, "(Loop)");
4028 break;
4029
4030 case 1:
7c3df132 4031 ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n");
2c3dfe3f 4032 ha->switch_cap = sw_cap;
1da177e4
LT		 4033 ha->current_topology = ISP_CFG_FL;
4034 strcpy(connect_type, "(FL_Port)");
4035 break;
4036
4037 case 2:
7c3df132 4038 ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n");
1da177e4
LT		 4039 ha->operating_mode = P2P;
4040 ha->current_topology = ISP_CFG_N;
4041 strcpy(connect_type, "(N_Port-to-N_Port)");
4042 break;
4043
4044 case 3:
7c3df132 4045 ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n");
2c3dfe3f 4046 ha->switch_cap = sw_cap;
1da177e4
LT		 4047 ha->operating_mode = P2P;
4048 ha->current_topology = ISP_CFG_F;
4049 strcpy(connect_type, "(F_Port)");
4050 break;
4051
4052 default:
7c3df132
SK		 4053 ql_dbg(ql_dbg_disc, vha, 0x200f,
4054 "HBA in unknown topology %x, using NL.\n", topo);
1da177e4
LT		 4055 ha->current_topology = ISP_CFG_NL;
4056 strcpy(connect_type, "(Loop)");
4057 break;
4058 }
4059
4060 /* Save Host port and loop ID. */
4061 /* byte order - Big Endian */
482c9dc7
QT		 4062 id.b.domain = domain;
4063 id.b.area = area;
4064 id.b.al_pa = al_pa;
4065 id.b.rsvd_1 = 0;
9d1aa4e1 4066 spin_lock_irqsave(&ha->hardware_lock, flags);
482c9dc7 4067 qlt_update_host_map(vha, id);
9d1aa4e1 4068 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2d70c103 4069
e315cd28 4070 if (!vha->flags.init_done)
7c3df132
SK		 4071 ql_log(ql_log_info, vha, 0x2010,
4072 "Topology - %s, Host Loop address 0x%x.\n",
e315cd28 4073 connect_type, vha->loop_id);
1da177e4 4074
1da177e4
LT		 4075 return(rval);
4076}
4077
a9083016 4078inline void
e315cd28
AC		 4079qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
4080 char *def)
9bb9fcf2
AV		 4081{
4082 char *st, *en;
4083 uint16_t index;
e315cd28 4084 struct qla_hw_data *ha = vha->hw;
ab671149 4085 int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
6246b8a1 4086 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha);
9bb9fcf2
AV		 4087
4088 if (memcmp(model, BINZERO, len) != 0) {
4089 strncpy(ha->model_number, model, len);
4090 st = en = ha->model_number;
4091 en += len - 1;
4092 while (en > st) {
4093 if (*en != 0x20 && *en != 0x00)
4094 break;
4095 *en-- = '\0';
4096 }
4097
4098 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 4099 if (use_tbl &&
4100 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2 4101 index < QLA_MODEL_NAMES)
1ee27146
JC		 4102 strncpy(ha->model_desc,
4103 qla2x00_model_name[index * 2 + 1],
4104 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 4105 } else {
4106 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 4107 if (use_tbl &&
4108 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2
AV		 4109 index < QLA_MODEL_NAMES) {
4110 strcpy(ha->model_number,
4111 qla2x00_model_name[index * 2]);
1ee27146
JC		 4112 strncpy(ha->model_desc,
4113 qla2x00_model_name[index * 2 + 1],
4114 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 4115 } else {
4116 strcpy(ha->model_number, def);
4117 }
4118 }
1ee27146 4119 if (IS_FWI2_CAPABLE(ha))
e315cd28 4120 qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc,
1ee27146 4121 sizeof(ha->model_desc));
9bb9fcf2
AV		 4122}
4123
4e08df3f
DM		 4124/* On sparc systems, obtain port and node WWN from firmware
4125 * properties.
4126 */
e315cd28 4127static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv)
4e08df3f
DM		 4128{
4129#ifdef CONFIG_SPARC
e315cd28 4130 struct qla_hw_data *ha = vha->hw;
4e08df3f 4131 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 4132 struct device_node *dp = pci_device_to_OF_node(pdev);
4133 const u8 *val;
4e08df3f
DM		 4134 int len;
4135
4136 val = of_get_property(dp, "port-wwn", &len);
4137 if (val && len >= WWN_SIZE)
4138 memcpy(nv->port_name, val, WWN_SIZE);
4139
4140 val = of_get_property(dp, "node-wwn", &len);
4141 if (val && len >= WWN_SIZE)
4142 memcpy(nv->node_name, val, WWN_SIZE);
4143#endif
4144}
4145
1da177e4
LT		 4146/*
4147* NVRAM configuration for ISP 2xxx
4148*
4149* Input:
4150* ha = adapter block pointer.
4151*
4152* Output:
4153* initialization control block in response_ring
4154* host adapters parameters in host adapter block
4155*
4156* Returns:
4157* 0 = success.
4158*/
abbd8870 4159int
e315cd28 4160qla2x00_nvram_config(scsi_qla_host_t *vha)
1da177e4 4161{
4e08df3f 4162 int rval;
0107109e
AV		 4163 uint8_t chksum = 0;
4164 uint16_t cnt;
4165 uint8_t *dptr1, *dptr2;
e315cd28 4166 struct qla_hw_data *ha = vha->hw;
0107109e 4167 init_cb_t *icb = ha->init_cb;
281afe19
SJ		 4168 nvram_t *nv = ha->nvram;
4169 uint8_t *ptr = ha->nvram;
3d71644c 4170 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 4171
4e08df3f
DM		 4172 rval = QLA_SUCCESS;
4173
1da177e4 4174 /* Determine NVRAM starting address. */
0107109e 4175 ha->nvram_size = sizeof(nvram_t);
1da177e4
LT		 4176 ha->nvram_base = 0;
4177 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
4178 if ((RD_REG_WORD(&reg->ctrl_status) >> 14) == 1)
4179 ha->nvram_base = 0x80;
4180
4181 /* Get NVRAM data and calculate checksum. */
e315cd28 4182 ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size);
0107109e
AV		 4183 for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++)
4184 chksum += *ptr++;
1da177e4 4185
7c3df132
SK		 4186 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
4187 "Contents of NVRAM.\n");
4188 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
4189 (uint8_t *)nv, ha->nvram_size);
1da177e4
LT		 4190
4191 /* Bad NVRAM data, set defaults parameters. */
4192 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' ||
4193 nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) {
4194 /* Reset NVRAM data. */
7c3df132 4195 ql_log(ql_log_warn, vha, 0x0064,
9e336520 4196 "Inconsistent NVRAM "
7c3df132
SK		 4197 "detected: checksum=0x%x id=%c version=0x%x.\n",
4198 chksum, nv->id[0], nv->nvram_version);
4199 ql_log(ql_log_warn, vha, 0x0065,
4200 "Falling back to "
4201 "functioning (yet invalid -- WWPN) defaults.\n");
4e08df3f
DM		 4202
4203 /*
4204 * Set default initialization control block.
4205 */
4206 memset(nv, 0, ha->nvram_size);
4207 nv->parameter_block_version = ICB_VERSION;
4208
4209 if (IS_QLA23XX(ha)) {
4210 nv->firmware_options[0] = BIT_2 | BIT_1;
4211 nv->firmware_options[1] = BIT_7 | BIT_5;
4212 nv->add_firmware_options[0] = BIT_5;
4213 nv->add_firmware_options[1] = BIT_5 | BIT_4;
98aee70d 4214 nv->frame_payload_size = 2048;
4e08df3f
DM		 4215 nv->special_options[1] = BIT_7;
4216 } else if (IS_QLA2200(ha)) {
4217 nv->firmware_options[0] = BIT_2 | BIT_1;
4218 nv->firmware_options[1] = BIT_7 | BIT_5;
4219 nv->add_firmware_options[0] = BIT_5;
4220 nv->add_firmware_options[1] = BIT_5 | BIT_4;
98aee70d 4221 nv->frame_payload_size = 1024;
4e08df3f
DM		 4222 } else if (IS_QLA2100(ha)) {
4223 nv->firmware_options[0] = BIT_3 | BIT_1;
4224 nv->firmware_options[1] = BIT_5;
98aee70d 4225 nv->frame_payload_size = 1024;
4e08df3f
DM		 4226 }
4227
ad950360
BVA		 4228 nv->max_iocb_allocation = cpu_to_le16(256);
4229 nv->execution_throttle = cpu_to_le16(16);
4e08df3f
DM		 4230 nv->retry_count = 8;
4231 nv->retry_delay = 1;
4232
4233 nv->port_name[0] = 33;
4234 nv->port_name[3] = 224;
4235 nv->port_name[4] = 139;
4236
e315cd28 4237 qla2xxx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 4238
4239 nv->login_timeout = 4;
4240
4241 /*
4242 * Set default host adapter parameters
4243 */
4244 nv->host_p[1] = BIT_2;
4245 nv->reset_delay = 5;
4246 nv->port_down_retry_count = 8;
ad950360 4247 nv->max_luns_per_target = cpu_to_le16(8);
4e08df3f
DM		 4248 nv->link_down_timeout = 60;
4249
4250 rval = 1;
1da177e4
LT		 4251 }
4252
4253#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
4254 /*
4255 * The SN2 does not provide BIOS emulation which means you can't change
4256 * potentially bogus BIOS settings. Force the use of default settings
4257 * for link rate and frame size. Hope that the rest of the settings
4258 * are valid.
4259 */
4260 if (ia64_platform_is("sn2")) {
98aee70d 4261 nv->frame_payload_size = 2048;
1da177e4
LT		 4262 if (IS_QLA23XX(ha))
4263 nv->special_options[1] = BIT_7;
4264 }
4265#endif
4266
4267 /* Reset Initialization control block */
0107109e 4268 memset(icb, 0, ha->init_cb_size);
1da177e4
LT		 4269
4270 /*
4271 * Setup driver NVRAM options.
4272 */
4273 nv->firmware_options[0] |= (BIT_6 | BIT_1);
4274 nv->firmware_options[0] &= ~(BIT_5 | BIT_4);
4275 nv->firmware_options[1] |= (BIT_5 | BIT_0);
4276 nv->firmware_options[1] &= ~BIT_4;
4277
4278 if (IS_QLA23XX(ha)) {
4279 nv->firmware_options[0] |= BIT_2;
4280 nv->firmware_options[0] &= ~BIT_3;
2d70c103 4281 nv->special_options[0] &= ~BIT_6;
0107109e 4282 nv->add_firmware_options[1] |= BIT_5 | BIT_4;
1da177e4
LT		 4283
4284 if (IS_QLA2300(ha)) {
4285 if (ha->fb_rev == FPM_2310) {
4286 strcpy(ha->model_number, "QLA2310");
4287 } else {
4288 strcpy(ha->model_number, "QLA2300");
4289 }
4290 } else {
e315cd28 4291 qla2x00_set_model_info(vha, nv->model_number,
9bb9fcf2 4292 sizeof(nv->model_number), "QLA23xx");
1da177e4
LT		 4293 }
4294 } else if (IS_QLA2200(ha)) {
4295 nv->firmware_options[0] |= BIT_2;
4296 /*
4297 * 'Point-to-point preferred, else loop' is not a safe
4298 * connection mode setting.
4299 */
4300 if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
4301 (BIT_5 | BIT_4)) {
4302 /* Force 'loop preferred, else point-to-point'. */
4303 nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
4304 nv->add_firmware_options[0] |= BIT_5;
4305 }
4306 strcpy(ha->model_number, "QLA22xx");
4307 } else /*if (IS_QLA2100(ha))*/ {
4308 strcpy(ha->model_number, "QLA2100");
4309 }
4310
4311 /*
4312 * Copy over NVRAM RISC parameter block to initialization control block.
4313 */
4314 dptr1 = (uint8_t *)icb;
4315 dptr2 = (uint8_t *)&nv->parameter_block_version;
4316 cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;
4317 while (cnt--)
4318 *dptr1++ = *dptr2++;
4319
4320 /* Copy 2nd half. */
4321 dptr1 = (uint8_t *)icb->add_firmware_options;
4322 cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;
4323 while (cnt--)
4324 *dptr1++ = *dptr2++;
4325
5341e868
AV		 4326 /* Use alternate WWN? */
4327 if (nv->host_p[1] & BIT_7) {
4328 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
4329 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
4330 }
4331
1da177e4
LT		 4332 /* Prepare nodename */
4333 if ((icb->firmware_options[1] & BIT_6) == 0) {
4334 /*
4335 * Firmware will apply the following mask if the nodename was
4336 * not provided.
4337 */
4338 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
4339 icb->node_name[0] &= 0xF0;
4340 }
4341
4342 /*
4343 * Set host adapter parameters.
4344 */
3ce8866c
SK		 4345
4346 /*
4347 * BIT_7 in the host-parameters section allows for modification to
4348 * internal driver logging.
4349 */
0181944f 4350 if (nv->host_p[0] & BIT_7)
cfb0919c 4351 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
1da177e4
LT		 4352 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
4353 /* Always load RISC code on non ISP2[12]00 chips. */
4354 if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
4355 ha->flags.disable_risc_code_load = 0;
4356 ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0);
4357 ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
4358 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
06c22bd1 4359 ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
d4c760c2 4360 ha->flags.disable_serdes = 0;
1da177e4
LT		 4361
4362 ha->operating_mode =
4363 (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
4364
4365 memcpy(ha->fw_seriallink_options, nv->seriallink_options,
4366 sizeof(ha->fw_seriallink_options));
4367
4368 /* save HBA serial number */
4369 ha->serial0 = icb->port_name[5];
4370 ha->serial1 = icb->port_name[6];
4371 ha->serial2 = icb->port_name[7];
e315cd28
AC		 4372 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
4373 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
1da177e4 4374
ad950360 4375 icb->execution_throttle = cpu_to_le16(0xFFFF);
1da177e4
LT		 4376
4377 ha->retry_count = nv->retry_count;
4378
4379 /* Set minimum login_timeout to 4 seconds. */
5b91490e 4380 if (nv->login_timeout != ql2xlogintimeout)
1da177e4
LT		 4381 nv->login_timeout = ql2xlogintimeout;
4382 if (nv->login_timeout < 4)
4383 nv->login_timeout = 4;
4384 ha->login_timeout = nv->login_timeout;
1da177e4 4385
00a537b8
AV		 4386 /* Set minimum RATOV to 100 tenths of a second. */
4387 ha->r_a_tov = 100;
1da177e4 4388
1da177e4
LT		 4389 ha->loop_reset_delay = nv->reset_delay;
4390
1da177e4
LT		 4391 /* Link Down Timeout = 0:
4392 *
4393 * When Port Down timer expires we will start returning
4394 * I/O's to OS with "DID_NO_CONNECT".
4395 *
4396 * Link Down Timeout != 0:
4397 *
4398 * The driver waits for the link to come up after link down
4399 * before returning I/Os to OS with "DID_NO_CONNECT".
fa2a1ce5 4400 */
1da177e4
LT		 4401 if (nv->link_down_timeout == 0) {
4402 ha->loop_down_abort_time =
354d6b21 4403 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
1da177e4
LT		 4404 } else {
4405 ha->link_down_timeout = nv->link_down_timeout;
4406 ha->loop_down_abort_time =
4407 (LOOP_DOWN_TIME - ha->link_down_timeout);
fa2a1ce5 4408 }
1da177e4 4409
1da177e4
LT		 4410 /*
4411 * Need enough time to try and get the port back.
4412 */
4413 ha->port_down_retry_count = nv->port_down_retry_count;
4414 if (qlport_down_retry)
4415 ha->port_down_retry_count = qlport_down_retry;
4416 /* Set login_retry_count */
4417 ha->login_retry_count = nv->retry_count;
4418 if (ha->port_down_retry_count == nv->port_down_retry_count &&
4419 ha->port_down_retry_count > 3)
4420 ha->login_retry_count = ha->port_down_retry_count;
4421 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
4422 ha->login_retry_count = ha->port_down_retry_count;
4423 if (ql2xloginretrycount)
4424 ha->login_retry_count = ql2xloginretrycount;
4425
ad950360 4426 icb->lun_enables = cpu_to_le16(0);
1da177e4
LT		 4427 icb->command_resource_count = 0;
4428 icb->immediate_notify_resource_count = 0;
ad950360 4429 icb->timeout = cpu_to_le16(0);
1da177e4
LT		 4430
4431 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
4432 /* Enable RIO */
4433 icb->firmware_options[0] &= ~BIT_3;
4434 icb->add_firmware_options[0] &=
4435 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
4436 icb->add_firmware_options[0] |= BIT_2;
4437 icb->response_accumulation_timer = 3;
4438 icb->interrupt_delay_timer = 5;
4439
e315cd28 4440 vha->flags.process_response_queue = 1;
1da177e4 4441 } else {
4fdfefe5 4442 /* Enable ZIO. */
e315cd28 4443 if (!vha->flags.init_done) {
4fdfefe5
AV		 4444 ha->zio_mode = icb->add_firmware_options[0] &
4445 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
4446 ha->zio_timer = icb->interrupt_delay_timer ?
4447 icb->interrupt_delay_timer: 2;
4448 }
1da177e4
LT		 4449 icb->add_firmware_options[0] &=
4450 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
e315cd28 4451 vha->flags.process_response_queue = 0;
4fdfefe5 4452 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d
AV		 4453 ha->zio_mode = QLA_ZIO_MODE_6;
4454
7c3df132 4455 ql_log(ql_log_info, vha, 0x0068,
4fdfefe5
AV		 4456 "ZIO mode %d enabled; timer delay (%d us).\n",
4457 ha->zio_mode, ha->zio_timer * 100);
1da177e4 4458
4fdfefe5
AV		 4459 icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;
4460 icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;
e315cd28 4461 vha->flags.process_response_queue = 1;
1da177e4
LT		 4462 }
4463 }
4464
4e08df3f 4465 if (rval) {
7c3df132
SK		 4466 ql_log(ql_log_warn, vha, 0x0069,
4467 "NVRAM configuration failed.\n");
4e08df3f
DM		 4468 }
4469 return (rval);
1da177e4
LT		 4470}
4471
19a7b4ae
JSEC		 4472static void
4473qla2x00_rport_del(void *data)
4474{
4475 fc_port_t *fcport = data;
d97994dc 4476 struct fc_rport *rport;
044d78e1 4477 unsigned long flags;
d97994dc 4478
044d78e1 4479 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
ac280b67 4480 rport = fcport->drport ? fcport->drport: fcport->rport;
d97994dc 4481 fcport->drport = NULL;
044d78e1 4482 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
726b8548 4483 if (rport) {
83548fe2
QT		 4484 ql_dbg(ql_dbg_disc, fcport->vha, 0x210b,
4485 "%s %8phN. rport %p roles %x\n",
4486 __func__, fcport->port_name, rport,
4487 rport->roles);
726b8548 4488
d97994dc 4489 fc_remote_port_delete(rport);
726b8548 4490 }
19a7b4ae
JSEC		 4491}
4492
1da177e4
LT		 4493/**
4494 * qla2x00_alloc_fcport() - Allocate a generic fcport.
2db6228d 4495 * @vha: HA context
1da177e4
LT		 4496 * @flags: allocation flags
4497 *
4498 * Returns a pointer to the allocated fcport, or NULL, if none available.
4499 */
9a069e19 4500fc_port_t *
e315cd28 4501qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags)
1da177e4
LT		 4502{
4503 fc_port_t *fcport;
4504
bbfbbbc1
MK		 4505 fcport = kzalloc(sizeof(fc_port_t), flags);
4506 if (!fcport)
4507 return NULL;
1da177e4
LT		 4508
4509 /* Setup fcport template structure. */
e315cd28 4510 fcport->vha = vha;
1da177e4
LT		 4511 fcport->port_type = FCT_UNKNOWN;
4512 fcport->loop_id = FC_NO_LOOP_ID;
ec426e10 4513 qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
ad3e0eda 4514 fcport->supported_classes = FC_COS_UNSPECIFIED;
1da177e4 4515
726b8548
QT		 4516 fcport->ct_desc.ct_sns = dma_alloc_coherent(&vha->hw->pdev->dev,
4517 sizeof(struct ct_sns_pkt), &fcport->ct_desc.ct_sns_dma,
6cb3216a 4518 flags);
726b8548
QT		 4519 fcport->disc_state = DSC_DELETED;
4520 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL;
4521 fcport->deleted = QLA_SESS_DELETED;
4522 fcport->login_retry = vha->hw->login_retry_count;
4523 fcport->login_retry = 5;
4524 fcport->logout_on_delete = 1;
4525
4526 if (!fcport->ct_desc.ct_sns) {
83548fe2 4527 ql_log(ql_log_warn, vha, 0xd049,
726b8548
QT		 4528 "Failed to allocate ct_sns request.\n");
4529 kfree(fcport);
4530 fcport = NULL;
4531 }
4532 INIT_WORK(&fcport->del_work, qla24xx_delete_sess_fn);
4533 INIT_LIST_HEAD(&fcport->gnl_entry);
4534 INIT_LIST_HEAD(&fcport->list);
4535
bbfbbbc1 4536 return fcport;
1da177e4
LT		 4537}
4538
726b8548
QT		 4539void
4540qla2x00_free_fcport(fc_port_t *fcport)
4541{
4542 if (fcport->ct_desc.ct_sns) {
4543 dma_free_coherent(&fcport->vha->hw->pdev->dev,
4544 sizeof(struct ct_sns_pkt), fcport->ct_desc.ct_sns,
4545 fcport->ct_desc.ct_sns_dma);
4546
4547 fcport->ct_desc.ct_sns = NULL;
4548 }
4549 kfree(fcport);
4550}
4551
1da177e4
LT		 4552/*
4553 * qla2x00_configure_loop
4554 * Updates Fibre Channel Device Database with what is actually on loop.
4555 *
4556 * Input:
4557 * ha = adapter block pointer.
4558 *
4559 * Returns:
4560 * 0 = success.
4561 * 1 = error.
4562 * 2 = database was full and device was not configured.
4563 */
4564static int
e315cd28 4565qla2x00_configure_loop(scsi_qla_host_t *vha)
1da177e4
LT		 4566{
4567 int rval;
4568 unsigned long flags, save_flags;
e315cd28 4569 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 4570 rval = QLA_SUCCESS;
4571
4572 /* Get Initiator ID */
e315cd28
AC		 4573 if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) {
4574 rval = qla2x00_configure_hba(vha);
1da177e4 4575 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4576 ql_dbg(ql_dbg_disc, vha, 0x2013,
4577 "Unable to configure HBA.\n");
1da177e4
LT		 4578 return (rval);
4579 }
4580 }
4581
e315cd28 4582 save_flags = flags = vha->dpc_flags;
7c3df132
SK		 4583 ql_dbg(ql_dbg_disc, vha, 0x2014,
4584 "Configure loop -- dpc flags = 0x%lx.\n", flags);
1da177e4
LT		 4585
4586 /*
4587 * If we have both an RSCN and PORT UPDATE pending then handle them
4588 * both at the same time.
4589 */
e315cd28
AC		 4590 clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
4591 clear_bit(RSCN_UPDATE, &vha->dpc_flags);
1da177e4 4592
3064ff39
MH		 4593 qla2x00_get_data_rate(vha);
4594
1da177e4
LT		 4595 /* Determine what we need to do */
4596 if (ha->current_topology == ISP_CFG_FL &&
4597 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
4598
1da177e4
LT		 4599 set_bit(RSCN_UPDATE, &flags);
4600
4601 } else if (ha->current_topology == ISP_CFG_F &&
4602 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
4603
1da177e4
LT		 4604 set_bit(RSCN_UPDATE, &flags);
4605 clear_bit(LOCAL_LOOP_UPDATE, &flags);
21333b48
AV		 4606
4607 } else if (ha->current_topology == ISP_CFG_N) {
4608 clear_bit(RSCN_UPDATE, &flags);
9cd883f0
QT		 4609 if (ha->flags.rida_fmt2) {
4610 /* With Rida Format 2, the login is already triggered.
4611 * We know who is on the other side of the wire.
4612 * No need to login to do login to find out or drop into
4613 * qla2x00_configure_local_loop().
4614 */
4615 clear_bit(LOCAL_LOOP_UPDATE, &flags);
4616 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4617 } else {
4618 if (qla_tgt_mode_enabled(vha)) {
4619 /* allow the other side to start the login */
4620 clear_bit(LOCAL_LOOP_UPDATE, &flags);
4621 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4622 }
4623 }
41dc529a
QT		 4624 } else if (ha->current_topology == ISP_CFG_NL) {
4625 clear_bit(RSCN_UPDATE, &flags);
4626 set_bit(LOCAL_LOOP_UPDATE, &flags);
e315cd28 4627 } else if (!vha->flags.online ||
1da177e4 4628 (test_bit(ABORT_ISP_ACTIVE, &flags))) {
1da177e4
LT		 4629 set_bit(RSCN_UPDATE, &flags);
4630 set_bit(LOCAL_LOOP_UPDATE, &flags);
4631 }
4632
4633 if (test_bit(LOCAL_LOOP_UPDATE, &flags)) {
7c3df132
SK		 4634 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
4635 ql_dbg(ql_dbg_disc, vha, 0x2015,
4636 "Loop resync needed, failing.\n");
1da177e4 4637 rval = QLA_FUNCTION_FAILED;
642ef983 4638 } else
e315cd28 4639 rval = qla2x00_configure_local_loop(vha);
1da177e4
LT		 4640 }
4641
4642 if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
7c3df132 4643 if (LOOP_TRANSITION(vha)) {
83548fe2 4644 ql_dbg(ql_dbg_disc, vha, 0x2099,
7c3df132 4645 "Needs RSCN update and loop transition.\n");
1da177e4 4646 rval = QLA_FUNCTION_FAILED;
7c3df132 4647 }
e315cd28
AC		 4648 else
4649 rval = qla2x00_configure_fabric(vha);
1da177e4
LT		 4650 }
4651
4652 if (rval == QLA_SUCCESS) {
e315cd28
AC		 4653 if (atomic_read(&vha->loop_down_timer) ||
4654 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4
LT		 4655 rval = QLA_FUNCTION_FAILED;
4656 } else {
e315cd28 4657 atomic_set(&vha->loop_state, LOOP_READY);
7c3df132
SK		 4658 ql_dbg(ql_dbg_disc, vha, 0x2069,
4659 "LOOP READY.\n");
ec7193e2 4660 ha->flags.fw_init_done = 1;
3bb67df5
DKU		 4661
4662 /*
4663 * Process any ATIO queue entries that came in
4664 * while we weren't online.
4665 */
ead03855
QT		 4666 if (qla_tgt_mode_enabled(vha) ||
4667 qla_dual_mode_enabled(vha)) {
3bb67df5
DKU		 4668 if (IS_QLA27XX(ha) || IS_QLA83XX(ha)) {
4669 spin_lock_irqsave(&ha->tgt.atio_lock,
4670 flags);
4671 qlt_24xx_process_atio_queue(vha, 0);
4672 spin_unlock_irqrestore(
4673 &ha->tgt.atio_lock, flags);
4674 } else {
4675 spin_lock_irqsave(&ha->hardware_lock,
4676 flags);
4677 qlt_24xx_process_atio_queue(vha, 1);
4678 spin_unlock_irqrestore(
4679 &ha->hardware_lock, flags);
4680 }
4681 }
1da177e4
LT		 4682 }
4683 }
4684
4685 if (rval) {
7c3df132
SK		 4686 ql_dbg(ql_dbg_disc, vha, 0x206a,
4687 "%s *** FAILED ***.\n", __func__);
1da177e4 4688 } else {
7c3df132
SK		 4689 ql_dbg(ql_dbg_disc, vha, 0x206b,
4690 "%s: exiting normally.\n", __func__);
1da177e4
LT		 4691 }
4692
cc3ef7bc 4693 /* Restore state if a resync event occurred during processing */
e315cd28 4694 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4 4695 if (test_bit(LOCAL_LOOP_UPDATE, &save_flags))
e315cd28 4696 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
f4658b6c 4697 if (test_bit(RSCN_UPDATE, &save_flags)) {
e315cd28 4698 set_bit(RSCN_UPDATE, &vha->dpc_flags);
f4658b6c 4699 }
1da177e4
LT		 4700 }
4701
4702 return (rval);
4703}
4704
edd05de1
DG		 4705/*
4706 * N2N Login
4707 * Updates Fibre Channel Device Database with local loop devices.
4708 *
4709 * Input:
4710 * ha = adapter block pointer.
4711 *
4712 * Returns:
4713 */
4714static int qla24xx_n2n_handle_login(struct scsi_qla_host *vha,
4715 fc_port_t *fcport)
4716{
4717 struct qla_hw_data *ha = vha->hw;
4718 int res = QLA_SUCCESS, rval;
4719 int greater_wwpn = 0;
4720 int logged_in = 0;
4721
4722 if (ha->current_topology != ISP_CFG_N)
4723 return res;
4724
4725 if (wwn_to_u64(vha->port_name) >
4726 wwn_to_u64(vha->n2n_port_name)) {
4727 ql_dbg(ql_dbg_disc, vha, 0x2002,
4728 "HBA WWPN is greater %llx > target %llx\n",
4729 wwn_to_u64(vha->port_name),
4730 wwn_to_u64(vha->n2n_port_name));
4731 greater_wwpn = 1;
4732 fcport->d_id.b24 = vha->n2n_id;
4733 }
4734
4735 fcport->loop_id = vha->loop_id;
4736 fcport->fc4f_nvme = 0;
4737 fcport->query = 1;
4738
4739 ql_dbg(ql_dbg_disc, vha, 0x4001,
4740 "Initiate N2N login handler: HBA port_id=%06x loopid=%d\n",
4741 fcport->d_id.b24, vha->loop_id);
4742
4743 /* Fill in member data. */
4744 if (!greater_wwpn) {
4745 rval = qla2x00_get_port_database(vha, fcport, 0);
4746 ql_dbg(ql_dbg_disc, vha, 0x1051,
4747 "Remote login-state (%x/%x) port_id=%06x loop_id=%x, rval=%d\n",
4748 fcport->current_login_state, fcport->last_login_state,
4749 fcport->d_id.b24, fcport->loop_id, rval);
4750
4751 if (((fcport->current_login_state & 0xf) == 0x4) ||
4752 ((fcport->current_login_state & 0xf) == 0x6))
4753 logged_in = 1;
4754 }
4755
4756 if (logged_in || greater_wwpn) {
4757 if (!vha->nvme_local_port && vha->flags.nvme_enabled)
4758 qla_nvme_register_hba(vha);
4759
4760 /* Set connected N_Port d_id */
4761 if (vha->flags.nvme_enabled)
4762 fcport->fc4f_nvme = 1;
4763
4764 fcport->scan_state = QLA_FCPORT_FOUND;
4765 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL;
4766 fcport->disc_state = DSC_GNL;
4767 fcport->n2n_flag = 1;
4768 fcport->flags = 3;
4769 vha->hw->flags.gpsc_supported = 0;
4770
4771 if (greater_wwpn) {
4772 ql_dbg(ql_dbg_disc, vha, 0x20e5,
4773 "%s %d PLOGI ELS %8phC\n",
4774 __func__, __LINE__, fcport->port_name);
4775
4776 res = qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI,
4777 fcport, fcport->d_id);
4778 }
4779
4780 if (res != QLA_SUCCESS) {
4781 ql_log(ql_log_info, vha, 0xd04d,
4782 "PLOGI Failed: portid=%06x - retrying\n",
4783 fcport->d_id.b24);
4784 res = QLA_SUCCESS;
4785 } else {
4786 /* State 0x6 means FCP PRLI complete */
4787 if ((fcport->current_login_state & 0xf) == 0x6) {
4788 ql_dbg(ql_dbg_disc, vha, 0x2118,
4789 "%s %d %8phC post GPDB work\n",
4790 __func__, __LINE__, fcport->port_name);
4791 fcport->chip_reset =
4792 vha->hw->base_qpair->chip_reset;
4793 qla24xx_post_gpdb_work(vha, fcport, 0);
4794 } else {
4795 ql_dbg(ql_dbg_disc, vha, 0x2118,
4796 "%s %d %8phC post NVMe PRLI\n",
4797 __func__, __LINE__, fcport->port_name);
4798 qla24xx_post_prli_work(vha, fcport);
4799 }
4800 }
4801 } else {
4802 /* Wait for next database change */
4803 set_bit(N2N_LOGIN_NEEDED, &vha->dpc_flags);
4804 }
1da177e4 4805
edd05de1
DG		 4806 return res;
4807}
1da177e4
LT		 4808
4809/*
4810 * qla2x00_configure_local_loop
4811 * Updates Fibre Channel Device Database with local loop devices.
4812 *
4813 * Input:
4814 * ha = adapter block pointer.
4815 *
4816 * Returns:
4817 * 0 = success.
4818 */
4819static int
e315cd28 4820qla2x00_configure_local_loop(scsi_qla_host_t *vha)
1da177e4
LT		 4821{
4822 int rval, rval2;
4823 int found_devs;
4824 int found;
4825 fc_port_t *fcport, *new_fcport;
4826
4827 uint16_t index;
4828 uint16_t entries;
4829 char *id_iter;
4830 uint16_t loop_id;
4831 uint8_t domain, area, al_pa;
e315cd28 4832 struct qla_hw_data *ha = vha->hw;
41dc529a 4833 unsigned long flags;
1da177e4
LT		 4834
4835 found_devs = 0;
4836 new_fcport = NULL;
642ef983 4837 entries = MAX_FIBRE_DEVICES_LOOP;
1da177e4 4838
1da177e4 4839 /* Get list of logged in devices. */
642ef983 4840 memset(ha->gid_list, 0, qla2x00_gid_list_size(ha));
e315cd28 4841 rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma,
1da177e4
LT		 4842 &entries);
4843 if (rval != QLA_SUCCESS)
4844 goto cleanup_allocation;
4845
83548fe2 4846 ql_dbg(ql_dbg_disc, vha, 0x2011,
7c3df132
SK		 4847 "Entries in ID list (%d).\n", entries);
4848 ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
4849 (uint8_t *)ha->gid_list,
4850 entries * sizeof(struct gid_list_info));
1da177e4 4851
9cd883f0
QT		 4852 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4853 fcport->scan_state = QLA_FCPORT_SCAN;
4854 }
4855
1da177e4 4856 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 4857 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 4858 if (new_fcport == NULL) {
83548fe2 4859 ql_log(ql_log_warn, vha, 0x2012,
7c3df132 4860 "Memory allocation failed for fcport.\n");
1da177e4
LT		 4861 rval = QLA_MEMORY_ALLOC_FAILED;
4862 goto cleanup_allocation;
4863 }
4864 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
4865
edd05de1
DG		 4866 /* Inititae N2N login. */
4867 if (test_and_clear_bit(N2N_LOGIN_NEEDED, &vha->dpc_flags)) {
4868 rval = qla24xx_n2n_handle_login(vha, new_fcport);
4869 if (rval != QLA_SUCCESS)
4870 goto cleanup_allocation;
4871 return QLA_SUCCESS;
4872 }
4873
1da177e4
LT		 4874 /* Add devices to port list. */
4875 id_iter = (char *)ha->gid_list;
4876 for (index = 0; index < entries; index++) {
4877 domain = ((struct gid_list_info *)id_iter)->domain;
4878 area = ((struct gid_list_info *)id_iter)->area;
4879 al_pa = ((struct gid_list_info *)id_iter)->al_pa;
abbd8870 4880 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1da177e4
LT		 4881 loop_id = (uint16_t)
4882 ((struct gid_list_info *)id_iter)->loop_id_2100;
abbd8870 4883 else
1da177e4
LT		 4884 loop_id = le16_to_cpu(
4885 ((struct gid_list_info *)id_iter)->loop_id);
abbd8870 4886 id_iter += ha->gid_list_info_size;
1da177e4
LT		 4887
4888 /* Bypass reserved domain fields. */
4889 if ((domain & 0xf0) == 0xf0)
4890 continue;
4891
4892 /* Bypass if not same domain and area of adapter. */
f7d289f6 4893 if (area && domain &&
e315cd28 4894 (area != vha->d_id.b.area || domain != vha->d_id.b.domain))
1da177e4
LT		 4895 continue;
4896
4897 /* Bypass invalid local loop ID. */
4898 if (loop_id > LAST_LOCAL_LOOP_ID)
4899 continue;
4900
41dc529a 4901 memset(new_fcport->port_name, 0, WWN_SIZE);
370d550e 4902
1da177e4
LT		 4903 /* Fill in member data. */
4904 new_fcport->d_id.b.domain = domain;
4905 new_fcport->d_id.b.area = area;
4906 new_fcport->d_id.b.al_pa = al_pa;
4907 new_fcport->loop_id = loop_id;
9cd883f0 4908 new_fcport->scan_state = QLA_FCPORT_FOUND;
41dc529a 4909
e315cd28 4910 rval2 = qla2x00_get_port_database(vha, new_fcport, 0);
1da177e4 4911 if (rval2 != QLA_SUCCESS) {
83548fe2 4912 ql_dbg(ql_dbg_disc, vha, 0x2097,
7c3df132
SK		 4913 "Failed to retrieve fcport information "
4914 "-- get_port_database=%x, loop_id=0x%04x.\n",
4915 rval2, new_fcport->loop_id);
edd05de1
DG		 4916 /* Skip retry if N2N */
4917 if (ha->current_topology != ISP_CFG_N) {
4918 ql_dbg(ql_dbg_disc, vha, 0x2105,
4919 "Scheduling resync.\n");
4920 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
4921 continue;
4922 }
1da177e4
LT		 4923 }
4924
41dc529a 4925 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
1da177e4
LT		 4926 /* Check for matching device in port list. */
4927 found = 0;
4928 fcport = NULL;
e315cd28 4929 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 4930 if (memcmp(new_fcport->port_name, fcport->port_name,
4931 WWN_SIZE))
4932 continue;
4933
ddb9b126 4934 fcport->flags &= ~FCF_FABRIC_DEVICE;
1da177e4
LT		 4935 fcport->loop_id = new_fcport->loop_id;
4936 fcport->port_type = new_fcport->port_type;
4937 fcport->d_id.b24 = new_fcport->d_id.b24;
4938 memcpy(fcport->node_name, new_fcport->node_name,
4939 WWN_SIZE);
9cd883f0 4940 fcport->scan_state = QLA_FCPORT_FOUND;
1da177e4
LT		 4941 found++;
4942 break;
4943 }
4944
4945 if (!found) {
4946 /* New device, add to fcports list. */
e315cd28 4947 list_add_tail(&new_fcport->list, &vha->vp_fcports);
1da177e4
LT		 4948
4949 /* Allocate a new replacement fcport. */
4950 fcport = new_fcport;
41dc529a
QT		 4951
4952 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
4953
e315cd28 4954 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
41dc529a 4955
1da177e4 4956 if (new_fcport == NULL) {
83548fe2 4957 ql_log(ql_log_warn, vha, 0xd031,
7c3df132 4958 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 4959 rval = QLA_MEMORY_ALLOC_FAILED;
4960 goto cleanup_allocation;
4961 }
41dc529a 4962 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
1da177e4
LT		 4963 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
4964 }
4965
41dc529a
QT		 4966 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
4967
d8b45213 4968 /* Base iIDMA settings on HBA port speed. */
a3cbdfad 4969 fcport->fp_speed = ha->link_data_rate;
d8b45213 4970
1da177e4
LT		 4971 found_devs++;
4972 }
4973
9cd883f0
QT		 4974 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4975 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4976 break;
4977
4978 if (fcport->scan_state == QLA_FCPORT_SCAN) {
4979 if ((qla_dual_mode_enabled(vha) ||
4980 qla_ini_mode_enabled(vha)) &&
4981 atomic_read(&fcport->state) == FCS_ONLINE) {
4982 qla2x00_mark_device_lost(vha, fcport,
4983 ql2xplogiabsentdevice, 0);
4984 if (fcport->loop_id != FC_NO_LOOP_ID &&
4985 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
4986 fcport->port_type != FCT_INITIATOR &&
4987 fcport->port_type != FCT_BROADCAST) {
4988 ql_dbg(ql_dbg_disc, vha, 0x20f0,
4989 "%s %d %8phC post del sess\n",
4990 __func__, __LINE__,
4991 fcport->port_name);
4992
d8630bb9 4993 qlt_schedule_sess_for_deletion(fcport);
9cd883f0
QT		 4994 continue;
4995 }
4996 }
4997 }
4998
4999 if (fcport->scan_state == QLA_FCPORT_FOUND)
5000 qla24xx_fcport_handle_login(vha, fcport);
5001 }
5002
1da177e4 5003cleanup_allocation:
c9475cb0 5004 kfree(new_fcport);
1da177e4
LT		 5005
5006 if (rval != QLA_SUCCESS) {
83548fe2 5007 ql_dbg(ql_dbg_disc, vha, 0x2098,
7c3df132 5008 "Configure local loop error exit: rval=%x.\n", rval);
1da177e4
LT		 5009 }
5010
1da177e4
LT		 5011 return (rval);
5012}
5013
d8b45213 5014static void
e315cd28 5015qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
d8b45213 5016{
d8b45213 5017 int rval;
93f2bd67 5018 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 5019 struct qla_hw_data *ha = vha->hw;
d8b45213 5020
c76f2c01 5021 if (!IS_IIDMA_CAPABLE(ha))
d8b45213
AV		 5022 return;
5023
c9afb9a2
GM		 5024 if (atomic_read(&fcport->state) != FCS_ONLINE)
5025 return;
5026
39bd9622
AV		 5027 if (fcport->fp_speed == PORT_SPEED_UNKNOWN ||
5028 fcport->fp_speed > ha->link_data_rate)
d8b45213
AV		 5029 return;
5030
e315cd28 5031 rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed,
a3cbdfad 5032 mb);
d8b45213 5033 if (rval != QLA_SUCCESS) {
7c3df132 5034 ql_dbg(ql_dbg_disc, vha, 0x2004,
7b833558
OK		 5035 "Unable to adjust iIDMA %8phN -- %04x %x %04x %04x.\n",
5036 fcport->port_name, rval, fcport->fp_speed, mb[0], mb[1]);
d8b45213 5037 } else {
7c3df132 5038 ql_dbg(ql_dbg_disc, vha, 0x2005,
33b28357 5039 "iIDMA adjusted to %s GB/s (%X) on %8phN.\n",
d0297c9a 5040 qla2x00_get_link_speed_str(ha, fcport->fp_speed),
33b28357 5041 fcport->fp_speed, fcport->port_name);
d8b45213
AV		 5042 }
5043}
5044
726b8548 5045/* qla2x00_reg_remote_port is reserved for Initiator Mode only.*/
23be331d 5046static void
e315cd28 5047qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport)
8482e118
AV		 5048{
5049 struct fc_rport_identifiers rport_ids;
bdf79621 5050 struct fc_rport *rport;
044d78e1 5051 unsigned long flags;
8482e118 5052
f8b02a85
AV		 5053 rport_ids.node_name = wwn_to_u64(fcport->node_name);
5054 rport_ids.port_name = wwn_to_u64(fcport->port_name);
8482e118
AV		 5055 rport_ids.port_id = fcport->d_id.b.domain << 16 |
5056 fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa;
77d74143 5057 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
e315cd28 5058 fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids);
77d74143 5059 if (!rport) {
7c3df132
SK		 5060 ql_log(ql_log_warn, vha, 0x2006,
5061 "Unable to allocate fc remote port.\n");
77d74143
AV		 5062 return;
5063 }
2d70c103 5064
044d78e1 5065 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
19a7b4ae 5066 *((fc_port_t **)rport->dd_data) = fcport;
044d78e1 5067 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
d97994dc 5068
ad3e0eda 5069 rport->supported_classes = fcport->supported_classes;
77d74143 5070
8482e118
AV		 5071 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
5072 if (fcport->port_type == FCT_INITIATOR)
5073 rport_ids.roles |= FC_RPORT_ROLE_FCP_INITIATOR;
5074 if (fcport->port_type == FCT_TARGET)
5075 rport_ids.roles |= FC_RPORT_ROLE_FCP_TARGET;
726b8548 5076
83548fe2
QT		 5077 ql_dbg(ql_dbg_disc, vha, 0x20ee,
5078 "%s %8phN. rport %p is %s mode\n",
5079 __func__, fcport->port_name, rport,
5080 (fcport->port_type == FCT_TARGET) ? "tgt" : "ini");
726b8548 5081
77d74143 5082 fc_remote_port_rolechg(rport, rport_ids.roles);
1da177e4
LT		 5083}
5084
23be331d
AB		 5085/*
5086 * qla2x00_update_fcport
5087 * Updates device on list.
5088 *
5089 * Input:
5090 * ha = adapter block pointer.
5091 * fcport = port structure pointer.
5092 *
5093 * Return:
5094 * 0 - Success
5095 * BIT_0 - error
5096 *
5097 * Context:
5098 * Kernel context.
5099 */
5100void
e315cd28 5101qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
23be331d 5102{
e315cd28 5103 fcport->vha = vha;
8ae6d9c7 5104
726b8548
QT		 5105 if (IS_SW_RESV_ADDR(fcport->d_id))
5106 return;
5107
83548fe2 5108 ql_dbg(ql_dbg_disc, vha, 0x20ef, "%s %8phC\n",
726b8548
QT		 5109 __func__, fcport->port_name);
5110
8ae6d9c7
GM		 5111 if (IS_QLAFX00(vha->hw)) {
5112 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
d20ed91b 5113 goto reg_port;
8ae6d9c7 5114 }
23be331d 5115 fcport->login_retry = 0;
5ff1d584 5116 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
726b8548
QT		 5117 fcport->disc_state = DSC_LOGIN_COMPLETE;
5118 fcport->deleted = 0;
5119 fcport->logout_on_delete = 1;
23be331d 5120
dbe18018
DT		 5121 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
5122 qla2x00_iidma_fcport(vha, fcport);
5123
e84067d7
DG		 5124 if (fcport->fc4f_nvme) {
5125 qla_nvme_register_remote(vha, fcport);
5126 return;
5127 }
5128
21090cbe 5129 qla24xx_update_fcport_fcp_prio(vha, fcport);
d20ed91b
AP		 5130
5131reg_port:
726b8548
QT		 5132 switch (vha->host->active_mode) {
5133 case MODE_INITIATOR:
d20ed91b 5134 qla2x00_reg_remote_port(vha, fcport);
726b8548
QT		 5135 break;
5136 case MODE_TARGET:
5137 if (!vha->vha_tgt.qla_tgt->tgt_stop &&
5138 !vha->vha_tgt.qla_tgt->tgt_stopped)
5139 qlt_fc_port_added(vha, fcport);
5140 break;
5141 case MODE_DUAL:
d20ed91b 5142 qla2x00_reg_remote_port(vha, fcport);
726b8548
QT		 5143 if (!vha->vha_tgt.qla_tgt->tgt_stop &&
5144 !vha->vha_tgt.qla_tgt->tgt_stopped)
5145 qlt_fc_port_added(vha, fcport);
5146 break;
5147 default:
5148 break;
d20ed91b 5149 }
23be331d
AB		 5150}
5151
1da177e4
LT		 5152/*
5153 * qla2x00_configure_fabric
5154 * Setup SNS devices with loop ID's.
5155 *
5156 * Input:
5157 * ha = adapter block pointer.
5158 *
5159 * Returns:
5160 * 0 = success.
5161 * BIT_0 = error
5162 */
5163static int
e315cd28 5164qla2x00_configure_fabric(scsi_qla_host_t *vha)
1da177e4 5165{
b3b02e6e 5166 int rval;
726b8548 5167 fc_port_t *fcport;
1da177e4 5168 uint16_t mb[MAILBOX_REGISTER_COUNT];
0107109e 5169 uint16_t loop_id;
1da177e4 5170 LIST_HEAD(new_fcports);
e315cd28 5171 struct qla_hw_data *ha = vha->hw;
df673274 5172 int discovery_gen;
1da177e4
LT		 5173
5174 /* If FL port exists, then SNS is present */
e428924c 5175 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 5176 loop_id = NPH_F_PORT;
5177 else
5178 loop_id = SNS_FL_PORT;
e315cd28 5179 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1);
1da177e4 5180 if (rval != QLA_SUCCESS) {
83548fe2 5181 ql_dbg(ql_dbg_disc, vha, 0x20a0,
7c3df132 5182 "MBX_GET_PORT_NAME failed, No FL Port.\n");
1da177e4 5183
e315cd28 5184 vha->device_flags &= ~SWITCH_FOUND;
1da177e4
LT		 5185 return (QLA_SUCCESS);
5186 }
e315cd28 5187 vha->device_flags |= SWITCH_FOUND;
1da177e4 5188
41dc529a
QT		 5189
5190 if (qla_tgt_mode_enabled(vha) || qla_dual_mode_enabled(vha)) {
5191 rval = qla2x00_send_change_request(vha, 0x3, 0);
5192 if (rval != QLA_SUCCESS)
5193 ql_log(ql_log_warn, vha, 0x121,
5194 "Failed to enable receiving of RSCN requests: 0x%x.\n",
5195 rval);
5196 }
5197
5198
1da177e4 5199 do {
726b8548
QT		 5200 qla2x00_mgmt_svr_login(vha);
5201
cca5335c
AV		 5202 /* FDMI support. */
5203 if (ql2xfdmienable &&
e315cd28
AC		 5204 test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags))
5205 qla2x00_fdmi_register(vha);
cca5335c 5206
1da177e4 5207 /* Ensure we are logged into the SNS. */
a14c7711 5208 loop_id = NPH_SNS_LID(ha);
0b91d116
CD		 5209 rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff,
5210 0xfc, mb, BIT_1|BIT_0);
a14c7711
JC		 5211 if (rval != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
5212 ql_dbg(ql_dbg_disc, vha, 0x20a1,
5213 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[6]=%x mb[7]=%x (%x).\n",
5214 loop_id, mb[0], mb[1], mb[2], mb[6], mb[7], rval);
0b91d116 5215 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
e452ceb6 5216 return rval;
0b91d116 5217 }
e315cd28
AC		 5218 if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) {
5219 if (qla2x00_rft_id(vha)) {
1da177e4 5220 /* EMPTY */
83548fe2 5221 ql_dbg(ql_dbg_disc, vha, 0x20a2,
7c3df132 5222 "Register FC-4 TYPE failed.\n");
b98ae0d7
QT		 5223 if (test_bit(LOOP_RESYNC_NEEDED,
5224 &vha->dpc_flags))
5225 break;
1da177e4 5226 }
d3bae931 5227 if (qla2x00_rff_id(vha, FC4_TYPE_FCP_SCSI)) {
1da177e4 5228 /* EMPTY */
83548fe2 5229 ql_dbg(ql_dbg_disc, vha, 0x209a,
7c3df132 5230 "Register FC-4 Features failed.\n");
b98ae0d7
QT		 5231 if (test_bit(LOOP_RESYNC_NEEDED,
5232 &vha->dpc_flags))
5233 break;
1da177e4 5234 }
d3bae931
DG		 5235 if (vha->flags.nvme_enabled) {
5236 if (qla2x00_rff_id(vha, FC_TYPE_NVME)) {
5237 ql_dbg(ql_dbg_disc, vha, 0x2049,
5238 "Register NVME FC Type Features failed.\n");
5239 }
5240 }
e315cd28 5241 if (qla2x00_rnn_id(vha)) {
1da177e4 5242 /* EMPTY */
83548fe2 5243 ql_dbg(ql_dbg_disc, vha, 0x2104,
7c3df132 5244 "Register Node Name failed.\n");
b98ae0d7
QT		 5245 if (test_bit(LOOP_RESYNC_NEEDED,
5246 &vha->dpc_flags))
5247 break;
e315cd28 5248 } else if (qla2x00_rsnn_nn(vha)) {
1da177e4 5249 /* EMPTY */
83548fe2 5250 ql_dbg(ql_dbg_disc, vha, 0x209b,
0bf0efa1 5251 "Register Symbolic Node Name failed.\n");
b98ae0d7
QT		 5252 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5253 break;
1da177e4
LT		 5254 }
5255 }
5256
827210ba 5257
df673274
AP		 5258 /* Mark the time right before querying FW for connected ports.
5259 * This process is long, asynchronous and by the time it's done,
5260 * collected information might not be accurate anymore. E.g.
5261 * disconnected port might have re-connected and a brand new
5262 * session has been created. In this case session's generation
5263 * will be newer than discovery_gen. */
5264 qlt_do_generation_tick(vha, &discovery_gen);
5265
a4239945 5266 if (USE_ASYNC_SCAN(ha)) {
33b28357
QT		 5267 rval = qla24xx_async_gpnft(vha, FC4_TYPE_FCP_SCSI,
5268 NULL);
a4239945
QT		 5269 if (rval)
5270 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5271 } else {
f352eeb7
QT		 5272 list_for_each_entry(fcport, &vha->vp_fcports, list)
5273 fcport->scan_state = QLA_FCPORT_SCAN;
5274
a4239945
QT		 5275 rval = qla2x00_find_all_fabric_devs(vha);
5276 }
1da177e4
LT		 5277 if (rval != QLA_SUCCESS)
5278 break;
1da177e4
LT		 5279 } while (0);
5280
e84067d7
DG		 5281 if (!vha->nvme_local_port && vha->flags.nvme_enabled)
5282 qla_nvme_register_hba(vha);
5283
726b8548 5284 if (rval)
7c3df132
SK		 5285 ql_dbg(ql_dbg_disc, vha, 0x2068,
5286 "Configure fabric error exit rval=%d.\n", rval);
1da177e4
LT		 5287
5288 return (rval);
5289}
5290
1da177e4
LT		 5291/*
5292 * qla2x00_find_all_fabric_devs
5293 *
5294 * Input:
5295 * ha = adapter block pointer.
5296 * dev = database device entry pointer.
5297 *
5298 * Returns:
5299 * 0 = success.
5300 *
5301 * Context:
5302 * Kernel context.
5303 */
5304static int
726b8548 5305qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha)
1da177e4
LT		 5306{
5307 int rval;
5308 uint16_t loop_id;
726b8548 5309 fc_port_t *fcport, *new_fcport;
1da177e4
LT		 5310 int found;
5311
5312 sw_info_t *swl;
5313 int swl_idx;
5314 int first_dev, last_dev;
1516ef44 5315 port_id_t wrap = {}, nxt_d_id;
e315cd28 5316 struct qla_hw_data *ha = vha->hw;
bb4cf5b7 5317 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
726b8548 5318 unsigned long flags;
1da177e4
LT		 5319
5320 rval = QLA_SUCCESS;
5321
5322 /* Try GID_PT to get device list, else GAN. */
7a67735b 5323 if (!ha->swl)
642ef983 5324 ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t),
7a67735b
AV		 5325 GFP_KERNEL);
5326 swl = ha->swl;
bbfbbbc1 5327 if (!swl) {
1da177e4 5328 /*EMPTY*/
83548fe2 5329 ql_dbg(ql_dbg_disc, vha, 0x209c,
7c3df132 5330 "GID_PT allocations failed, fallback on GA_NXT.\n");
1da177e4 5331 } else {
642ef983 5332 memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t));
e315cd28 5333 if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) {
1da177e4 5334 swl = NULL;
b98ae0d7
QT		 5335 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5336 return rval;
e315cd28 5337 } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 5338 swl = NULL;
b98ae0d7
QT		 5339 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5340 return rval;
e315cd28 5341 } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 5342 swl = NULL;
b98ae0d7
QT		 5343 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5344 return rval;
726b8548
QT		 5345 } else if (qla2x00_gfpn_id(vha, swl) != QLA_SUCCESS) {
5346 swl = NULL;
b98ae0d7
QT		 5347 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5348 return rval;
1da177e4 5349 }
e8c72ba5
CD		 5350
5351 /* If other queries succeeded probe for FC-4 type */
b98ae0d7 5352 if (swl) {
e8c72ba5 5353 qla2x00_gff_id(vha, swl);
b98ae0d7
QT		 5354 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5355 return rval;
5356 }
1da177e4
LT		 5357 }
5358 swl_idx = 0;
5359
5360 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 5361 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 5362 if (new_fcport == NULL) {
83548fe2 5363 ql_log(ql_log_warn, vha, 0x209d,
7c3df132 5364 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 5365 return (QLA_MEMORY_ALLOC_FAILED);
5366 }
5367 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
1da177e4
LT		 5368 /* Set start port ID scan at adapter ID. */
5369 first_dev = 1;
5370 last_dev = 0;
5371
5372 /* Starting free loop ID. */
e315cd28
AC		 5373 loop_id = ha->min_external_loopid;
5374 for (; loop_id <= ha->max_loop_id; loop_id++) {
5375 if (qla2x00_is_reserved_id(vha, loop_id))
1da177e4
LT		 5376 continue;
5377
3a6478df
GM		 5378 if (ha->current_topology == ISP_CFG_FL &&
5379 (atomic_read(&vha->loop_down_timer) ||
5380 LOOP_TRANSITION(vha))) {
bb2d52b2
AV		 5381 atomic_set(&vha->loop_down_timer, 0);
5382 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5383 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
1da177e4 5384 break;
bb2d52b2 5385 }
1da177e4
LT		 5386
5387 if (swl != NULL) {
5388 if (last_dev) {
5389 wrap.b24 = new_fcport->d_id.b24;
5390 } else {
5391 new_fcport->d_id.b24 = swl[swl_idx].d_id.b24;
5392 memcpy(new_fcport->node_name,
5393 swl[swl_idx].node_name, WWN_SIZE);
5394 memcpy(new_fcport->port_name,
5395 swl[swl_idx].port_name, WWN_SIZE);
d8b45213
AV		 5396 memcpy(new_fcport->fabric_port_name,
5397 swl[swl_idx].fabric_port_name, WWN_SIZE);
5398 new_fcport->fp_speed = swl[swl_idx].fp_speed;
e8c72ba5 5399 new_fcport->fc4_type = swl[swl_idx].fc4_type;
1da177e4 5400
a5d42f4c 5401 new_fcport->nvme_flag = 0;
1a28faa0 5402 new_fcport->fc4f_nvme = 0;
a5d42f4c
DG		 5403 if (vha->flags.nvme_enabled &&
5404 swl[swl_idx].fc4f_nvme) {
5405 new_fcport->fc4f_nvme =
5406 swl[swl_idx].fc4f_nvme;
5407 ql_log(ql_log_info, vha, 0x2131,
5408 "FOUND: NVME port %8phC as FC Type 28h\n",
5409 new_fcport->port_name);
5410 }
5411
1da177e4
LT		 5412 if (swl[swl_idx].d_id.b.rsvd_1 != 0) {
5413 last_dev = 1;
5414 }
5415 swl_idx++;
5416 }
5417 } else {
5418 /* Send GA_NXT to the switch */
e315cd28 5419 rval = qla2x00_ga_nxt(vha, new_fcport);
1da177e4 5420 if (rval != QLA_SUCCESS) {
83548fe2 5421 ql_log(ql_log_warn, vha, 0x209e,
7c3df132
SK		 5422 "SNS scan failed -- assuming "
5423 "zero-entry result.\n");
1da177e4
LT		 5424 rval = QLA_SUCCESS;
5425 break;
5426 }
5427 }
5428
5429 /* If wrap on switch device list, exit. */
5430 if (first_dev) {
5431 wrap.b24 = new_fcport->d_id.b24;
5432 first_dev = 0;
5433 } else if (new_fcport->d_id.b24 == wrap.b24) {
83548fe2 5434 ql_dbg(ql_dbg_disc, vha, 0x209f,
7c3df132
SK		 5435 "Device wrap (%02x%02x%02x).\n",
5436 new_fcport->d_id.b.domain,
5437 new_fcport->d_id.b.area,
5438 new_fcport->d_id.b.al_pa);
1da177e4
LT		 5439 break;
5440 }
5441
2c3dfe3f 5442 /* Bypass if same physical adapter. */
e315cd28 5443 if (new_fcport->d_id.b24 == base_vha->d_id.b24)
1da177e4
LT		 5444 continue;
5445
2c3dfe3f 5446 /* Bypass virtual ports of the same host. */
bb4cf5b7
CD		 5447 if (qla2x00_is_a_vp_did(vha, new_fcport->d_id.b24))
5448 continue;
2c3dfe3f 5449
f7d289f6
AV		 5450 /* Bypass if same domain and area of adapter. */
5451 if (((new_fcport->d_id.b24 & 0xffff00) ==
e315cd28 5452 (vha->d_id.b24 & 0xffff00)) && ha->current_topology ==
f7d289f6
AV		 5453 ISP_CFG_FL)
5454 continue;
5455
1da177e4
LT		 5456 /* Bypass reserved domain fields. */
5457 if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0)
5458 continue;
5459
e8c72ba5 5460 /* Bypass ports whose FCP-4 type is not FCP_SCSI */
4da26e16
CD		 5461 if (ql2xgffidenable &&
5462 (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI &&
5463 new_fcport->fc4_type != FC4_TYPE_UNKNOWN))
e8c72ba5
CD		 5464 continue;
5465
726b8548
QT		 5466 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5467
1da177e4
LT		 5468 /* Locate matching device in database. */
5469 found = 0;
e315cd28 5470 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 5471 if (memcmp(new_fcport->port_name, fcport->port_name,
5472 WWN_SIZE))
5473 continue;
5474
827210ba 5475 fcport->scan_state = QLA_FCPORT_FOUND;
b3b02e6e 5476
1da177e4
LT		 5477 found++;
5478
d8b45213
AV		 5479 /* Update port state. */
5480 memcpy(fcport->fabric_port_name,
5481 new_fcport->fabric_port_name, WWN_SIZE);
5482 fcport->fp_speed = new_fcport->fp_speed;
5483
1da177e4 5484 /*
b2032fd5
RD		 5485 * If address the same and state FCS_ONLINE
5486 * (or in target mode), nothing changed.
1da177e4
LT		 5487 */
5488 if (fcport->d_id.b24 == new_fcport->d_id.b24 &&
b2032fd5 5489 (atomic_read(&fcport->state) == FCS_ONLINE ||
726b8548 5490 (vha->host->active_mode == MODE_TARGET))) {
1da177e4
LT		 5491 break;
5492 }
5493
5494 /*
5495 * If device was not a fabric device before.
5496 */
5497 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) {
5498 fcport->d_id.b24 = new_fcport->d_id.b24;
5f16b331 5499 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 5500 fcport->flags |= (FCF_FABRIC_DEVICE |
5501 FCF_LOGIN_NEEDED);
1da177e4
LT		 5502 break;
5503 }
5504
5505 /*
5506 * Port ID changed or device was marked to be updated;
5507 * Log it out if still logged in and mark it for
5508 * relogin later.
5509 */
726b8548 5510 if (qla_tgt_mode_enabled(base_vha)) {
b2032fd5
RD		 5511 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf080,
5512 "port changed FC ID, %8phC"
5513 " old %x:%x:%x (loop_id 0x%04x)-> new %x:%x:%x\n",
5514 fcport->port_name,
5515 fcport->d_id.b.domain,
5516 fcport->d_id.b.area,
5517 fcport->d_id.b.al_pa,
5518 fcport->loop_id,
5519 new_fcport->d_id.b.domain,
5520 new_fcport->d_id.b.area,
5521 new_fcport->d_id.b.al_pa);
5522 fcport->d_id.b24 = new_fcport->d_id.b24;
5523 break;
5524 }
5525
1da177e4
LT		 5526 fcport->d_id.b24 = new_fcport->d_id.b24;
5527 fcport->flags |= FCF_LOGIN_NEEDED;
1da177e4
LT		 5528 break;
5529 }
5530
9dd9686b
DT		 5531 if (fcport->fc4f_nvme) {
5532 if (fcport->disc_state == DSC_DELETE_PEND) {
5533 fcport->disc_state = DSC_GNL;
5534 vha->fcport_count--;
5535 fcport->login_succ = 0;
5536 }
5537 }
5538
726b8548
QT		 5539 if (found) {
5540 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1da177e4 5541 continue;
726b8548 5542 }
1da177e4 5543 /* If device was not in our fcports list, then add it. */
b2032fd5 5544 new_fcport->scan_state = QLA_FCPORT_FOUND;
726b8548
QT		 5545 list_add_tail(&new_fcport->list, &vha->vp_fcports);
5546
5547 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5548
1da177e4
LT		 5549
5550 /* Allocate a new replacement fcport. */
5551 nxt_d_id.b24 = new_fcport->d_id.b24;
e315cd28 5552 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 5553 if (new_fcport == NULL) {
83548fe2 5554 ql_log(ql_log_warn, vha, 0xd032,
7c3df132 5555 "Memory allocation failed for fcport.\n");
1da177e4
LT		 5556 return (QLA_MEMORY_ALLOC_FAILED);
5557 }
5558 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
5559 new_fcport->d_id.b24 = nxt_d_id.b24;
5560 }
5561
726b8548
QT		 5562 qla2x00_free_fcport(new_fcport);
5563
5564 /*
5565 * Logout all previous fabric dev marked lost, except FCP2 devices.
5566 */
5567 list_for_each_entry(fcport, &vha->vp_fcports, list) {
5568 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5569 break;
5570
5571 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0 ||
5572 (fcport->flags & FCF_LOGIN_NEEDED) == 0)
5573 continue;
5574
5575 if (fcport->scan_state == QLA_FCPORT_SCAN) {
5576 if ((qla_dual_mode_enabled(vha) ||
5577 qla_ini_mode_enabled(vha)) &&
5578 atomic_read(&fcport->state) == FCS_ONLINE) {
5579 qla2x00_mark_device_lost(vha, fcport,
5580 ql2xplogiabsentdevice, 0);
5581 if (fcport->loop_id != FC_NO_LOOP_ID &&
5582 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
5583 fcport->port_type != FCT_INITIATOR &&
5584 fcport->port_type != FCT_BROADCAST) {
83548fe2 5585 ql_dbg(ql_dbg_disc, vha, 0x20f0,
726b8548
QT		 5586 "%s %d %8phC post del sess\n",
5587 __func__, __LINE__,
5588 fcport->port_name);
d8630bb9 5589 qlt_schedule_sess_for_deletion(fcport);
726b8548
QT		 5590 continue;
5591 }
5592 }
5593 }
1da177e4 5594
726b8548
QT		 5595 if (fcport->scan_state == QLA_FCPORT_FOUND)
5596 qla24xx_fcport_handle_login(vha, fcport);
5597 }
1da177e4
LT		 5598 return (rval);
5599}
5600
5601/*
5602 * qla2x00_find_new_loop_id
5603 * Scan through our port list and find a new usable loop ID.
5604 *
5605 * Input:
5606 * ha: adapter state pointer.
5607 * dev: port structure pointer.
5608 *
5609 * Returns:
5610 * qla2x00 local function return status code.
5611 *
5612 * Context:
5613 * Kernel context.
5614 */
03bcfb57 5615int
e315cd28 5616qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
1da177e4
LT		 5617{
5618 int rval;
e315cd28 5619 struct qla_hw_data *ha = vha->hw;
feafb7b1 5620 unsigned long flags = 0;
1da177e4
LT		 5621
5622 rval = QLA_SUCCESS;
5623
5f16b331 5624 spin_lock_irqsave(&ha->vport_slock, flags);
1da177e4 5625
5f16b331
CD		 5626 dev->loop_id = find_first_zero_bit(ha->loop_id_map,
5627 LOOPID_MAP_SIZE);
5628 if (dev->loop_id >= LOOPID_MAP_SIZE ||
5629 qla2x00_is_reserved_id(vha, dev->loop_id)) {
5630 dev->loop_id = FC_NO_LOOP_ID;
5631 rval = QLA_FUNCTION_FAILED;
5632 } else
5633 set_bit(dev->loop_id, ha->loop_id_map);
1da177e4 5634
5f16b331 5635 spin_unlock_irqrestore(&ha->vport_slock, flags);
1da177e4 5636
5f16b331
CD		 5637 if (rval == QLA_SUCCESS)
5638 ql_dbg(ql_dbg_disc, dev->vha, 0x2086,
5639 "Assigning new loopid=%x, portid=%x.\n",
5640 dev->loop_id, dev->d_id.b24);
5641 else
5642 ql_log(ql_log_warn, dev->vha, 0x2087,
5643 "No loop_id's available, portid=%x.\n",
5644 dev->d_id.b24);
1da177e4
LT		 5645
5646 return (rval);
5647}
5648
1da177e4
LT		 5649
5650/*
5651 * qla2x00_fabric_login
5652 * Issue fabric login command.
5653 *
5654 * Input:
5655 * ha = adapter block pointer.
5656 * device = pointer to FC device type structure.
5657 *
5658 * Returns:
5659 * 0 - Login successfully
5660 * 1 - Login failed
5661 * 2 - Initiator device
5662 * 3 - Fatal error
5663 */
5664int
e315cd28 5665qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 5666 uint16_t *next_loopid)
5667{
5668 int rval;
5669 int retry;
5670 uint16_t tmp_loopid;
5671 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 5672 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 5673
5674 retry = 0;
5675 tmp_loopid = 0;
5676
5677 for (;;) {
7c3df132
SK		 5678 ql_dbg(ql_dbg_disc, vha, 0x2000,
5679 "Trying Fabric Login w/loop id 0x%04x for port "
5680 "%02x%02x%02x.\n",
5681 fcport->loop_id, fcport->d_id.b.domain,
5682 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 5683
5684 /* Login fcport on switch. */
0b91d116 5685 rval = ha->isp_ops->fabric_login(vha, fcport->loop_id,
1da177e4
LT		 5686 fcport->d_id.b.domain, fcport->d_id.b.area,
5687 fcport->d_id.b.al_pa, mb, BIT_0);
0b91d116
CD		 5688 if (rval != QLA_SUCCESS) {
5689 return rval;
5690 }
1da177e4
LT		 5691 if (mb[0] == MBS_PORT_ID_USED) {
5692 /*
5693 * Device has another loop ID. The firmware team
0107109e
AV		 5694 * recommends the driver perform an implicit login with
5695 * the specified ID again. The ID we just used is save
5696 * here so we return with an ID that can be tried by
5697 * the next login.
1da177e4
LT		 5698 */
5699 retry++;
5700 tmp_loopid = fcport->loop_id;
5701 fcport->loop_id = mb[1];
5702
7c3df132
SK		 5703 ql_dbg(ql_dbg_disc, vha, 0x2001,
5704 "Fabric Login: port in use - next loop "
5705 "id=0x%04x, port id= %02x%02x%02x.\n",
1da177e4 5706 fcport->loop_id, fcport->d_id.b.domain,
7c3df132 5707 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 5708
5709 } else if (mb[0] == MBS_COMMAND_COMPLETE) {
5710 /*
5711 * Login succeeded.
5712 */
5713 if (retry) {
5714 /* A retry occurred before. */
5715 *next_loopid = tmp_loopid;
5716 } else {
5717 /*
5718 * No retry occurred before. Just increment the
5719 * ID value for next login.
5720 */
5721 *next_loopid = (fcport->loop_id + 1);
5722 }
5723
5724 if (mb[1] & BIT_0) {
5725 fcport->port_type = FCT_INITIATOR;
5726 } else {
5727 fcport->port_type = FCT_TARGET;
5728 if (mb[1] & BIT_1) {
8474f3a0 5729 fcport->flags |= FCF_FCP2_DEVICE;
1da177e4
LT		 5730 }
5731 }
5732
ad3e0eda
AV		 5733 if (mb[10] & BIT_0)
5734 fcport->supported_classes |= FC_COS_CLASS2;
5735 if (mb[10] & BIT_1)
5736 fcport->supported_classes |= FC_COS_CLASS3;
5737
2d70c103
NB		 5738 if (IS_FWI2_CAPABLE(ha)) {
5739 if (mb[10] & BIT_7)
5740 fcport->flags |=
5741 FCF_CONF_COMP_SUPPORTED;
5742 }
5743
1da177e4
LT		 5744 rval = QLA_SUCCESS;
5745 break;
5746 } else if (mb[0] == MBS_LOOP_ID_USED) {
5747 /*
5748 * Loop ID already used, try next loop ID.
5749 */
5750 fcport->loop_id++;
e315cd28 5751 rval = qla2x00_find_new_loop_id(vha, fcport);
1da177e4
LT		 5752 if (rval != QLA_SUCCESS) {
5753 /* Ran out of loop IDs to use */
5754 break;
5755 }
5756 } else if (mb[0] == MBS_COMMAND_ERROR) {
5757 /*
5758 * Firmware possibly timed out during login. If NO
5759 * retries are left to do then the device is declared
5760 * dead.
5761 */
5762 *next_loopid = fcport->loop_id;
e315cd28 5763 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 5764 fcport->d_id.b.domain, fcport->d_id.b.area,
5765 fcport->d_id.b.al_pa);
e315cd28 5766 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 5767
5768 rval = 1;
5769 break;
5770 } else {
5771 /*
5772 * unrecoverable / not handled error
5773 */
7c3df132
SK		 5774 ql_dbg(ql_dbg_disc, vha, 0x2002,
5775 "Failed=%x port_id=%02x%02x%02x loop_id=%x "
5776 "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain,
5777 fcport->d_id.b.area, fcport->d_id.b.al_pa,
5778 fcport->loop_id, jiffies);
1da177e4
LT		 5779
5780 *next_loopid = fcport->loop_id;
e315cd28 5781 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 5782 fcport->d_id.b.domain, fcport->d_id.b.area,
5783 fcport->d_id.b.al_pa);
5f16b331 5784 qla2x00_clear_loop_id(fcport);
0eedfcf0 5785 fcport->login_retry = 0;
1da177e4
LT		 5786
5787 rval = 3;
5788 break;
5789 }
5790 }
5791
5792 return (rval);
5793}
5794
5795/*
5796 * qla2x00_local_device_login
5797 * Issue local device login command.
5798 *
5799 * Input:
5800 * ha = adapter block pointer.
5801 * loop_id = loop id of device to login to.
5802 *
5803 * Returns (Where's the #define!!!!):
5804 * 0 - Login successfully
5805 * 1 - Login failed
5806 * 3 - Fatal error
5807 */
5808int
e315cd28 5809qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport)
1da177e4
LT		 5810{
5811 int rval;
5812 uint16_t mb[MAILBOX_REGISTER_COUNT];
5813
5814 memset(mb, 0, sizeof(mb));
e315cd28 5815 rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0);
1da177e4
LT		 5816 if (rval == QLA_SUCCESS) {
5817 /* Interrogate mailbox registers for any errors */
5818 if (mb[0] == MBS_COMMAND_ERROR)
5819 rval = 1;
5820 else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR)
5821 /* device not in PCB table */
5822 rval = 3;
5823 }
5824
5825 return (rval);
5826}
5827
5828/*
5829 * qla2x00_loop_resync
5830 * Resync with fibre channel devices.
5831 *
5832 * Input:
5833 * ha = adapter block pointer.
5834 *
5835 * Returns:
5836 * 0 = success
5837 */
5838int
e315cd28 5839qla2x00_loop_resync(scsi_qla_host_t *vha)
1da177e4 5840{
73208dfd 5841 int rval = QLA_SUCCESS;
1da177e4 5842 uint32_t wait_time;
67c2e93a
AC		 5843 struct req_que *req;
5844 struct rsp_que *rsp;
5845
d7459527 5846 req = vha->req;
67c2e93a 5847 rsp = req->rsp;
1da177e4 5848
e315cd28
AC		 5849 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
5850 if (vha->flags.online) {
5851 if (!(rval = qla2x00_fw_ready(vha))) {
1da177e4
LT		 5852 /* Wait at most MAX_TARGET RSCNs for a stable link. */
5853 wait_time = 256;
5854 do {
8ae6d9c7
GM		 5855 if (!IS_QLAFX00(vha->hw)) {
5856 /*
5857 * Issue a marker after FW becomes
5858 * ready.
5859 */
5860 qla2x00_marker(vha, req, rsp, 0, 0,
5861 MK_SYNC_ALL);
5862 vha->marker_needed = 0;
5863 }
1da177e4
LT		 5864
5865 /* Remap devices on Loop. */
e315cd28 5866 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4 5867
8ae6d9c7
GM		 5868 if (IS_QLAFX00(vha->hw))
5869 qlafx00_configure_devices(vha);
5870 else
5871 qla2x00_configure_loop(vha);
5872
1da177e4 5873 wait_time--;
e315cd28
AC		 5874 } while (!atomic_read(&vha->loop_down_timer) &&
5875 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
5876 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
5877 &vha->dpc_flags)));
1da177e4 5878 }
1da177e4
LT		 5879 }
5880
e315cd28 5881 if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
1da177e4 5882 return (QLA_FUNCTION_FAILED);
1da177e4 5883
e315cd28 5884 if (rval)
7c3df132
SK		 5885 ql_dbg(ql_dbg_disc, vha, 0x206c,
5886 "%s *** FAILED ***.\n", __func__);
1da177e4
LT		 5887
5888 return (rval);
5889}
5890
579d12b5
SK		 5891/*
5892* qla2x00_perform_loop_resync
5893* Description: This function will set the appropriate flags and call
5894* qla2x00_loop_resync. If successful loop will be resynced
5895* Arguments : scsi_qla_host_t pointer
5896* returm : Success or Failure
5897*/
5898
5899int qla2x00_perform_loop_resync(scsi_qla_host_t *ha)
5900{
5901 int32_t rval = 0;
5902
5903 if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) {
5904 /*Configure the flags so that resync happens properly*/
5905 atomic_set(&ha->loop_down_timer, 0);
5906 if (!(ha->device_flags & DFLG_NO_CABLE)) {
5907 atomic_set(&ha->loop_state, LOOP_UP);
5908 set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags);
5909 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
5910 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
5911
5912 rval = qla2x00_loop_resync(ha);
5913 } else
5914 atomic_set(&ha->loop_state, LOOP_DEAD);
5915
5916 clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags);
5917 }
5918
5919 return rval;
5920}
5921
d97994dc 5922void
67becc00 5923qla2x00_update_fcports(scsi_qla_host_t *base_vha)
d97994dc
AV		 5924{
5925 fc_port_t *fcport;
feafb7b1
AE		 5926 struct scsi_qla_host *vha;
5927 struct qla_hw_data *ha = base_vha->hw;
5928 unsigned long flags;
d97994dc 5929
feafb7b1 5930 spin_lock_irqsave(&ha->vport_slock, flags);
d97994dc 5931 /* Go with deferred removal of rport references. */
feafb7b1
AE		 5932 list_for_each_entry(vha, &base_vha->hw->vp_list, list) {
5933 atomic_inc(&vha->vref_count);
5934 list_for_each_entry(fcport, &vha->vp_fcports, list) {
8ae598d0 5935 if (fcport->drport &&
feafb7b1
AE		 5936 atomic_read(&fcport->state) != FCS_UNCONFIGURED) {
5937 spin_unlock_irqrestore(&ha->vport_slock, flags);
67becc00 5938 qla2x00_rport_del(fcport);
df673274 5939
feafb7b1
AE		 5940 spin_lock_irqsave(&ha->vport_slock, flags);
5941 }
5942 }
5943 atomic_dec(&vha->vref_count);
c4a9b538 5944 wake_up(&vha->vref_waitq);
feafb7b1
AE		 5945 }
5946 spin_unlock_irqrestore(&ha->vport_slock, flags);
d97994dc
AV		 5947}
5948
7d613ac6
SV		 5949/* Assumes idc_lock always held on entry */
5950void
5951qla83xx_reset_ownership(scsi_qla_host_t *vha)
5952{
5953 struct qla_hw_data *ha = vha->hw;
5954 uint32_t drv_presence, drv_presence_mask;
5955 uint32_t dev_part_info1, dev_part_info2, class_type;
5956 uint32_t class_type_mask = 0x3;
5957 uint16_t fcoe_other_function = 0xffff, i;
5958
7ec0effd
AD		 5959 if (IS_QLA8044(ha)) {
5960 drv_presence = qla8044_rd_direct(vha,
5961 QLA8044_CRB_DRV_ACTIVE_INDEX);
5962 dev_part_info1 = qla8044_rd_direct(vha,
5963 QLA8044_CRB_DEV_PART_INFO_INDEX);
5964 dev_part_info2 = qla8044_rd_direct(vha,
5965 QLA8044_CRB_DEV_PART_INFO2);
5966 } else {
5967 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5968 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1);
5969 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2);
5970 }
7d613ac6
SV		 5971 for (i = 0; i < 8; i++) {
5972 class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask);
5973 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
5974 (i != ha->portnum)) {
5975 fcoe_other_function = i;
5976 break;
5977 }
5978 }
5979 if (fcoe_other_function == 0xffff) {
5980 for (i = 0; i < 8; i++) {
5981 class_type = ((dev_part_info2 >> (i * 4)) &
5982 class_type_mask);
5983 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
5984 ((i + 8) != ha->portnum)) {
5985 fcoe_other_function = i + 8;
5986 break;
5987 }
5988 }
5989 }
5990 /*
5991 * Prepare drv-presence mask based on fcoe functions present.
5992 * However consider only valid physical fcoe function numbers (0-15).
5993 */
5994 drv_presence_mask = ~((1 << (ha->portnum)) |
5995 ((fcoe_other_function == 0xffff) ?
5996 0 : (1 << (fcoe_other_function))));
5997
5998 /* We are the reset owner iff:
5999 * - No other protocol drivers present.
6000 * - This is the lowest among fcoe functions. */
6001 if (!(drv_presence & drv_presence_mask) &&
6002 (ha->portnum < fcoe_other_function)) {
6003 ql_dbg(ql_dbg_p3p, vha, 0xb07f,
6004 "This host is Reset owner.\n");
6005 ha->flags.nic_core_reset_owner = 1;
6006 }
6007}
6008
fa492630 6009static int
7d613ac6
SV		 6010__qla83xx_set_drv_ack(scsi_qla_host_t *vha)
6011{
6012 int rval = QLA_SUCCESS;
6013 struct qla_hw_data *ha = vha->hw;
6014 uint32_t drv_ack;
6015
6016 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
6017 if (rval == QLA_SUCCESS) {
6018 drv_ack |= (1 << ha->portnum);
6019 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
6020 }
6021
6022 return rval;
6023}
6024
fa492630 6025static int
7d613ac6
SV		 6026__qla83xx_clear_drv_ack(scsi_qla_host_t *vha)
6027{
6028 int rval = QLA_SUCCESS;
6029 struct qla_hw_data *ha = vha->hw;
6030 uint32_t drv_ack;
6031
6032 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
6033 if (rval == QLA_SUCCESS) {
6034 drv_ack &= ~(1 << ha->portnum);
6035 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
6036 }
6037
6038 return rval;
6039}
6040
fa492630 6041static const char *
7d613ac6
SV		 6042qla83xx_dev_state_to_string(uint32_t dev_state)
6043{
6044 switch (dev_state) {
6045 case QLA8XXX_DEV_COLD:
6046 return "COLD/RE-INIT";
6047 case QLA8XXX_DEV_INITIALIZING:
6048 return "INITIALIZING";
6049 case QLA8XXX_DEV_READY:
6050 return "READY";
6051 case QLA8XXX_DEV_NEED_RESET:
6052 return "NEED RESET";
6053 case QLA8XXX_DEV_NEED_QUIESCENT:
6054 return "NEED QUIESCENT";
6055 case QLA8XXX_DEV_FAILED:
6056 return "FAILED";
6057 case QLA8XXX_DEV_QUIESCENT:
6058 return "QUIESCENT";
6059 default:
6060 return "Unknown";
6061 }
6062}
6063
6064/* Assumes idc-lock always held on entry */
6065void
6066qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type)
6067{
6068 struct qla_hw_data *ha = vha->hw;
6069 uint32_t idc_audit_reg = 0, duration_secs = 0;
6070
6071 switch (audit_type) {
6072 case IDC_AUDIT_TIMESTAMP:
6073 ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000);
6074 idc_audit_reg = (ha->portnum) |
6075 (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8);
6076 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
6077 break;
6078
6079 case IDC_AUDIT_COMPLETION:
6080 duration_secs = ((jiffies_to_msecs(jiffies) -
6081 jiffies_to_msecs(ha->idc_audit_ts)) / 1000);
6082 idc_audit_reg = (ha->portnum) |
6083 (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8);
6084 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
6085 break;
6086
6087 default:
6088 ql_log(ql_log_warn, vha, 0xb078,
6089 "Invalid audit type specified.\n");
6090 break;
6091 }
6092}
6093
6094/* Assumes idc_lock always held on entry */
fa492630 6095static int
7d613ac6
SV		 6096qla83xx_initiating_reset(scsi_qla_host_t *vha)
6097{
6098 struct qla_hw_data *ha = vha->hw;
6099 uint32_t idc_control, dev_state;
6100
6101 __qla83xx_get_idc_control(vha, &idc_control);
6102 if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) {
6103 ql_log(ql_log_info, vha, 0xb080,
6104 "NIC Core reset has been disabled. idc-control=0x%x\n",
6105 idc_control);
6106 return QLA_FUNCTION_FAILED;
6107 }
6108
6109 /* Set NEED-RESET iff in READY state and we are the reset-owner */
6110 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
6111 if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) {
6112 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
6113 QLA8XXX_DEV_NEED_RESET);
6114 ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n");
6115 qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP);
6116 } else {
6117 const char *state = qla83xx_dev_state_to_string(dev_state);
6118 ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n", state);
6119
6120 /* SV: XXX: Is timeout required here? */
6121 /* Wait for IDC state change READY -> NEED_RESET */
6122 while (dev_state == QLA8XXX_DEV_READY) {
6123 qla83xx_idc_unlock(vha, 0);
6124 msleep(200);
6125 qla83xx_idc_lock(vha, 0);
6126 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
6127 }
6128 }
6129
6130 /* Send IDC ack by writing to drv-ack register */
6131 __qla83xx_set_drv_ack(vha);
6132
6133 return QLA_SUCCESS;
6134}
6135
6136int
6137__qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control)
6138{
6139 return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
6140}
6141
7d613ac6
SV		 6142int
6143__qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control)
6144{
6145 return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
6146}
6147
fa492630 6148static int
7d613ac6
SV		 6149qla83xx_check_driver_presence(scsi_qla_host_t *vha)
6150{
6151 uint32_t drv_presence = 0;
6152 struct qla_hw_data *ha = vha->hw;
6153
6154 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6155 if (drv_presence & (1 << ha->portnum))
6156 return QLA_SUCCESS;
6157 else
6158 return QLA_TEST_FAILED;
6159}
6160
6161int
6162qla83xx_nic_core_reset(scsi_qla_host_t *vha)
6163{
6164 int rval = QLA_SUCCESS;
6165 struct qla_hw_data *ha = vha->hw;
6166
6167 ql_dbg(ql_dbg_p3p, vha, 0xb058,
6168 "Entered %s().\n", __func__);
6169
6170 if (vha->device_flags & DFLG_DEV_FAILED) {
6171 ql_log(ql_log_warn, vha, 0xb059,
6172 "Device in unrecoverable FAILED state.\n");
6173 return QLA_FUNCTION_FAILED;
6174 }
6175
6176 qla83xx_idc_lock(vha, 0);
6177
6178 if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) {
6179 ql_log(ql_log_warn, vha, 0xb05a,
6180 "Function=0x%x has been removed from IDC participation.\n",
6181 ha->portnum);
6182 rval = QLA_FUNCTION_FAILED;
6183 goto exit;
6184 }
6185
6186 qla83xx_reset_ownership(vha);
6187
6188 rval = qla83xx_initiating_reset(vha);
6189
6190 /*
6191 * Perform reset if we are the reset-owner,
6192 * else wait till IDC state changes to READY/FAILED.
6193 */
6194 if (rval == QLA_SUCCESS) {
6195 rval = qla83xx_idc_state_handler(vha);
6196
6197 if (rval == QLA_SUCCESS)
6198 ha->flags.nic_core_hung = 0;
6199 __qla83xx_clear_drv_ack(vha);
6200 }
6201
6202exit:
6203 qla83xx_idc_unlock(vha, 0);
6204
6205 ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__);
6206
6207 return rval;
6208}
6209
81178772
SK		 6210int
6211qla2xxx_mctp_dump(scsi_qla_host_t *vha)
6212{
6213 struct qla_hw_data *ha = vha->hw;
6214 int rval = QLA_FUNCTION_FAILED;
6215
6216 if (!IS_MCTP_CAPABLE(ha)) {
6217 /* This message can be removed from the final version */
6218 ql_log(ql_log_info, vha, 0x506d,
6219 "This board is not MCTP capable\n");
6220 return rval;
6221 }
6222
6223 if (!ha->mctp_dump) {
6224 ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev,
6225 MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL);
6226
6227 if (!ha->mctp_dump) {
6228 ql_log(ql_log_warn, vha, 0x506e,
6229 "Failed to allocate memory for mctp dump\n");
6230 return rval;
6231 }
6232 }
6233
6234#define MCTP_DUMP_STR_ADDR 0x00000000
6235 rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma,
6236 MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4);
6237 if (rval != QLA_SUCCESS) {
6238 ql_log(ql_log_warn, vha, 0x506f,
6239 "Failed to capture mctp dump\n");
6240 } else {
6241 ql_log(ql_log_info, vha, 0x5070,
6242 "Mctp dump capture for host (%ld/%p).\n",
6243 vha->host_no, ha->mctp_dump);
6244 ha->mctp_dumped = 1;
6245 }
6246
409ee0fe 6247 if (!ha->flags.nic_core_reset_hdlr_active && !ha->portnum) {
81178772
SK		 6248 ha->flags.nic_core_reset_hdlr_active = 1;
6249 rval = qla83xx_restart_nic_firmware(vha);
6250 if (rval)
6251 /* NIC Core reset failed. */
6252 ql_log(ql_log_warn, vha, 0x5071,
6253 "Failed to restart nic firmware\n");
6254 else
6255 ql_dbg(ql_dbg_p3p, vha, 0xb084,
6256 "Restarted NIC firmware successfully.\n");
6257 ha->flags.nic_core_reset_hdlr_active = 0;
6258 }
6259
6260 return rval;
6261
6262}
6263
579d12b5 6264/*
8fcd6b8b 6265* qla2x00_quiesce_io
579d12b5
SK		 6266* Description: This function will block the new I/Os
6267* Its not aborting any I/Os as context
6268* is not destroyed during quiescence
6269* Arguments: scsi_qla_host_t
6270* return : void
6271*/
6272void
8fcd6b8b 6273qla2x00_quiesce_io(scsi_qla_host_t *vha)
579d12b5
SK		 6274{
6275 struct qla_hw_data *ha = vha->hw;
6276 struct scsi_qla_host *vp;
6277
8fcd6b8b
CD		 6278 ql_dbg(ql_dbg_dpc, vha, 0x401d,
6279 "Quiescing I/O - ha=%p.\n", ha);
579d12b5
SK		 6280
6281 atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME);
6282 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
6283 atomic_set(&vha->loop_state, LOOP_DOWN);
6284 qla2x00_mark_all_devices_lost(vha, 0);
6285 list_for_each_entry(vp, &ha->vp_list, list)
8fcd6b8b 6286 qla2x00_mark_all_devices_lost(vp, 0);
579d12b5
SK		 6287 } else {
6288 if (!atomic_read(&vha->loop_down_timer))
6289 atomic_set(&vha->loop_down_timer,
6290 LOOP_DOWN_TIME);
6291 }
6292 /* Wait for pending cmds to complete */
6293 qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST);
6294}
6295
a9083016
GM		 6296void
6297qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
6298{
6299 struct qla_hw_data *ha = vha->hw;
579d12b5 6300 struct scsi_qla_host *vp;
feafb7b1 6301 unsigned long flags;
6aef87be 6302 fc_port_t *fcport;
7c3f8fd1 6303 u16 i;
a9083016 6304
e46ef004
SK		 6305 /* For ISP82XX, driver waits for completion of the commands.
6306 * online flag should be set.
6307 */
7ec0effd 6308 if (!(IS_P3P_TYPE(ha)))
e46ef004 6309 vha->flags.online = 0;
a9083016
GM		 6310 ha->flags.chip_reset_done = 0;
6311 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2be21fa2 6312 vha->qla_stats.total_isp_aborts++;
a9083016 6313
7c3df132
SK		 6314 ql_log(ql_log_info, vha, 0x00af,
6315 "Performing ISP error recovery - ha=%p.\n", ha);
a9083016 6316
e46ef004
SK		 6317 /* For ISP82XX, reset_chip is just disabling interrupts.
6318 * Driver waits for the completion of the commands.
6319 * the interrupts need to be enabled.
6320 */
7ec0effd 6321 if (!(IS_P3P_TYPE(ha)))
a9083016
GM		 6322 ha->isp_ops->reset_chip(vha);
6323
9cd883f0
QT		 6324 SAVE_TOPO(ha);
6325 ha->flags.rida_fmt2 = 0;
ec7193e2
QT		 6326 ha->flags.n2n_ae = 0;
6327 ha->flags.lip_ae = 0;
6328 ha->current_topology = 0;
6329 ha->flags.fw_started = 0;
6330 ha->flags.fw_init_done = 0;
7c3f8fd1
QT		 6331 ha->base_qpair->chip_reset++;
6332 for (i = 0; i < ha->max_qpairs; i++) {
6333 if (ha->queue_pair_map[i])
6334 ha->queue_pair_map[i]->chip_reset =
6335 ha->base_qpair->chip_reset;
6336 }
726b8548 6337
a9083016
GM		 6338 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
6339 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
6340 atomic_set(&vha->loop_state, LOOP_DOWN);
6341 qla2x00_mark_all_devices_lost(vha, 0);
feafb7b1
AE		 6342
6343 spin_lock_irqsave(&ha->vport_slock, flags);
579d12b5 6344 list_for_each_entry(vp, &ha->vp_list, list) {
feafb7b1
AE		 6345 atomic_inc(&vp->vref_count);
6346 spin_unlock_irqrestore(&ha->vport_slock, flags);
6347
a9083016 6348 qla2x00_mark_all_devices_lost(vp, 0);
feafb7b1
AE		 6349
6350 spin_lock_irqsave(&ha->vport_slock, flags);
6351 atomic_dec(&vp->vref_count);
6352 }
6353 spin_unlock_irqrestore(&ha->vport_slock, flags);
a9083016
GM		 6354 } else {
6355 if (!atomic_read(&vha->loop_down_timer))
6356 atomic_set(&vha->loop_down_timer,
6357 LOOP_DOWN_TIME);
6358 }
6359
6aef87be
AV		 6360 /* Clear all async request states across all VPs. */
6361 list_for_each_entry(fcport, &vha->vp_fcports, list)
6362 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
6363 spin_lock_irqsave(&ha->vport_slock, flags);
6364 list_for_each_entry(vp, &ha->vp_list, list) {
6365 atomic_inc(&vp->vref_count);
6366 spin_unlock_irqrestore(&ha->vport_slock, flags);
6367
6368 list_for_each_entry(fcport, &vp->vp_fcports, list)
6369 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
6370
6371 spin_lock_irqsave(&ha->vport_slock, flags);
6372 atomic_dec(&vp->vref_count);
6373 }
6374 spin_unlock_irqrestore(&ha->vport_slock, flags);
6375
bddd2d65
LC		 6376 if (!ha->flags.eeh_busy) {
6377 /* Make sure for ISP 82XX IO DMA is complete */
7ec0effd 6378 if (IS_P3P_TYPE(ha)) {
7190575f 6379 qla82xx_chip_reset_cleanup(vha);
7c3df132
SK		 6380 ql_log(ql_log_info, vha, 0x00b4,
6381 "Done chip reset cleanup.\n");
a9083016 6382
e46ef004
SK		 6383 /* Done waiting for pending commands.
6384 * Reset the online flag.
6385 */
6386 vha->flags.online = 0;
4d78c973 6387 }
a9083016 6388
bddd2d65
LC		 6389 /* Requeue all commands in outstanding command list. */
6390 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
6391 }
b6a029e1
AE		 6392 /* memory barrier */
6393 wmb();
a9083016
GM		 6394}
6395
1da177e4
LT		 6396/*
6397* qla2x00_abort_isp
6398* Resets ISP and aborts all outstanding commands.
6399*
6400* Input:
6401* ha = adapter block pointer.
6402*
6403* Returns:
6404* 0 = success
6405*/
6406int
e315cd28 6407qla2x00_abort_isp(scsi_qla_host_t *vha)
1da177e4 6408{
476e8978 6409 int rval;
1da177e4 6410 uint8_t status = 0;
e315cd28
AC		 6411 struct qla_hw_data *ha = vha->hw;
6412 struct scsi_qla_host *vp;
73208dfd 6413 struct req_que *req = ha->req_q_map[0];
feafb7b1 6414 unsigned long flags;
1da177e4 6415
e315cd28 6416 if (vha->flags.online) {
a9083016 6417 qla2x00_abort_isp_cleanup(vha);
1da177e4 6418
a6171297
SV		 6419 if (IS_QLA8031(ha)) {
6420 ql_dbg(ql_dbg_p3p, vha, 0xb05c,
6421 "Clearing fcoe driver presence.\n");
6422 if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS)
6423 ql_dbg(ql_dbg_p3p, vha, 0xb073,
6424 "Error while clearing DRV-Presence.\n");
6425 }
6426
85880801
AV		 6427 if (unlikely(pci_channel_offline(ha->pdev) &&
6428 ha->flags.pci_channel_io_perm_failure)) {
6429 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
6430 status = 0;
6431 return status;
6432 }
6433
73208dfd 6434 ha->isp_ops->get_flash_version(vha, req->ring);
30c47662 6435
e315cd28 6436 ha->isp_ops->nvram_config(vha);
1da177e4 6437
e315cd28
AC		 6438 if (!qla2x00_restart_isp(vha)) {
6439 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4 6440
e315cd28 6441 if (!atomic_read(&vha->loop_down_timer)) {
1da177e4
LT		 6442 /*
6443 * Issue marker command only when we are going
6444 * to start the I/O .
6445 */
e315cd28 6446 vha->marker_needed = 1;
1da177e4
LT		 6447 }
6448
e315cd28 6449 vha->flags.online = 1;
1da177e4 6450
fd34f556 6451 ha->isp_ops->enable_intrs(ha);
1da177e4 6452
fa2a1ce5 6453 ha->isp_abort_cnt = 0;
e315cd28 6454 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
476e8978 6455
6246b8a1
GM		 6456 if (IS_QLA81XX(ha) || IS_QLA8031(ha))
6457 qla2x00_get_fw_version(vha);
df613b96
AV		 6458 if (ha->fce) {
6459 ha->flags.fce_enabled = 1;
6460 memset(ha->fce, 0,
6461 fce_calc_size(ha->fce_bufs));
e315cd28 6462 rval = qla2x00_enable_fce_trace(vha,
df613b96
AV		 6463 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
6464 &ha->fce_bufs);
6465 if (rval) {
7c3df132 6466 ql_log(ql_log_warn, vha, 0x8033,
df613b96
AV		 6467 "Unable to reinitialize FCE "
6468 "(%d).\n", rval);
6469 ha->flags.fce_enabled = 0;
6470 }
6471 }
436a7b11
AV		 6472
6473 if (ha->eft) {
6474 memset(ha->eft, 0, EFT_SIZE);
e315cd28 6475 rval = qla2x00_enable_eft_trace(vha,
436a7b11
AV		 6476 ha->eft_dma, EFT_NUM_BUFFERS);
6477 if (rval) {
7c3df132 6478 ql_log(ql_log_warn, vha, 0x8034,
436a7b11
AV		 6479 "Unable to reinitialize EFT "
6480 "(%d).\n", rval);
6481 }
6482 }
1da177e4 6483 } else { /* failed the ISP abort */
e315cd28
AC		 6484 vha->flags.online = 1;
6485 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
1da177e4 6486 if (ha->isp_abort_cnt == 0) {
7c3df132
SK		 6487 ql_log(ql_log_fatal, vha, 0x8035,
6488 "ISP error recover failed - "
6489 "board disabled.\n");
fa2a1ce5 6490 /*
1da177e4
LT		 6491 * The next call disables the board
6492 * completely.
6493 */
e315cd28
AC		 6494 ha->isp_ops->reset_adapter(vha);
6495 vha->flags.online = 0;
1da177e4 6496 clear_bit(ISP_ABORT_RETRY,
e315cd28 6497 &vha->dpc_flags);
1da177e4
LT		 6498 status = 0;
6499 } else { /* schedule another ISP abort */
6500 ha->isp_abort_cnt--;
7c3df132
SK		 6501 ql_dbg(ql_dbg_taskm, vha, 0x8020,
6502 "ISP abort - retry remaining %d.\n",
6503 ha->isp_abort_cnt);
1da177e4
LT		 6504 status = 1;
6505 }
6506 } else {
6507 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
7c3df132
SK		 6508 ql_dbg(ql_dbg_taskm, vha, 0x8021,
6509 "ISP error recovery - retrying (%d) "
6510 "more times.\n", ha->isp_abort_cnt);
e315cd28 6511 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
1da177e4
LT		 6512 status = 1;
6513 }
6514 }
fa2a1ce5 6515
1da177e4
LT		 6516 }
6517
e315cd28 6518 if (!status) {
7c3df132 6519 ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__);
1608cc4a 6520 qla2x00_configure_hba(vha);
feafb7b1
AE		 6521 spin_lock_irqsave(&ha->vport_slock, flags);
6522 list_for_each_entry(vp, &ha->vp_list, list) {
6523 if (vp->vp_idx) {
6524 atomic_inc(&vp->vref_count);
6525 spin_unlock_irqrestore(&ha->vport_slock, flags);
6526
e315cd28 6527 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 6528
6529 spin_lock_irqsave(&ha->vport_slock, flags);
6530 atomic_dec(&vp->vref_count);
6531 }
e315cd28 6532 }
feafb7b1
AE		 6533 spin_unlock_irqrestore(&ha->vport_slock, flags);
6534
7d613ac6
SV		 6535 if (IS_QLA8031(ha)) {
6536 ql_dbg(ql_dbg_p3p, vha, 0xb05d,
6537 "Setting back fcoe driver presence.\n");
6538 if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS)
6539 ql_dbg(ql_dbg_p3p, vha, 0xb074,
6540 "Error while setting DRV-Presence.\n");
6541 }
e315cd28 6542 } else {
d8424f68
JP		 6543 ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n",
6544 __func__);
1da177e4
LT		 6545 }
6546
6547 return(status);
6548}
6549
6550/*
6551* qla2x00_restart_isp
6552* restarts the ISP after a reset
6553*
6554* Input:
6555* ha = adapter block pointer.
6556*
6557* Returns:
6558* 0 = success
6559*/
6560static int
e315cd28 6561qla2x00_restart_isp(scsi_qla_host_t *vha)
1da177e4 6562{
c6b2fca8 6563 int status = 0;
e315cd28 6564 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 6565 struct req_que *req = ha->req_q_map[0];
6566 struct rsp_que *rsp = ha->rsp_q_map[0];
1da177e4
LT		 6567
6568 /* If firmware needs to be loaded */
e315cd28
AC		 6569 if (qla2x00_isp_firmware(vha)) {
6570 vha->flags.online = 0;
6571 status = ha->isp_ops->chip_diag(vha);
6572 if (!status)
6573 status = qla2x00_setup_chip(vha);
1da177e4
LT		 6574 }
6575
e315cd28
AC		 6576 if (!status && !(status = qla2x00_init_rings(vha))) {
6577 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
2533cf67 6578 ha->flags.chip_reset_done = 1;
7108b76e 6579
73208dfd
AC		 6580 /* Initialize the queues in use */
6581 qla25xx_init_queues(ha);
6582
e315cd28
AC		 6583 status = qla2x00_fw_ready(vha);
6584 if (!status) {
0107109e 6585 /* Issue a marker after FW becomes ready. */
73208dfd 6586 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
7108b76e 6587 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4
LT		 6588 }
6589
6590 /* if no cable then assume it's good */
e315cd28 6591 if ((vha->device_flags & DFLG_NO_CABLE))
1da177e4 6592 status = 0;
1da177e4
LT		 6593 }
6594 return (status);
6595}
6596
73208dfd
AC		 6597static int
6598qla25xx_init_queues(struct qla_hw_data *ha)
6599{
6600 struct rsp_que *rsp = NULL;
6601 struct req_que *req = NULL;
6602 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
6603 int ret = -1;
6604 int i;
6605
2afa19a9 6606 for (i = 1; i < ha->max_rsp_queues; i++) {
73208dfd 6607 rsp = ha->rsp_q_map[i];
cb43285f 6608 if (rsp && test_bit(i, ha->rsp_qid_map)) {
73208dfd 6609 rsp->options &= ~BIT_0;
618a7523 6610 ret = qla25xx_init_rsp_que(base_vha, rsp);
73208dfd 6611 if (ret != QLA_SUCCESS)
7c3df132
SK		 6612 ql_dbg(ql_dbg_init, base_vha, 0x00ff,
6613 "%s Rsp que: %d init failed.\n",
6614 __func__, rsp->id);
73208dfd 6615 else
7c3df132
SK		 6616 ql_dbg(ql_dbg_init, base_vha, 0x0100,
6617 "%s Rsp que: %d inited.\n",
6618 __func__, rsp->id);
73208dfd 6619 }
2afa19a9
AC		 6620 }
6621 for (i = 1; i < ha->max_req_queues; i++) {
73208dfd 6622 req = ha->req_q_map[i];
cb43285f
QT		 6623 if (req && test_bit(i, ha->req_qid_map)) {
6624 /* Clear outstanding commands array. */
73208dfd 6625 req->options &= ~BIT_0;
618a7523 6626 ret = qla25xx_init_req_que(base_vha, req);
73208dfd 6627 if (ret != QLA_SUCCESS)
7c3df132
SK		 6628 ql_dbg(ql_dbg_init, base_vha, 0x0101,
6629 "%s Req que: %d init failed.\n",
6630 __func__, req->id);
73208dfd 6631 else
7c3df132
SK		 6632 ql_dbg(ql_dbg_init, base_vha, 0x0102,
6633 "%s Req que: %d inited.\n",
6634 __func__, req->id);
73208dfd
AC		 6635 }
6636 }
6637 return ret;
6638}
6639
1da177e4
LT		 6640/*
6641* qla2x00_reset_adapter
6642* Reset adapter.
6643*
6644* Input:
6645* ha = adapter block pointer.
6646*/
abbd8870 6647void
e315cd28 6648qla2x00_reset_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 6649{
6650 unsigned long flags = 0;
e315cd28 6651 struct qla_hw_data *ha = vha->hw;
3d71644c 6652 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 6653
e315cd28 6654 vha->flags.online = 0;
fd34f556 6655 ha->isp_ops->disable_intrs(ha);
1da177e4 6656
1da177e4
LT		 6657 spin_lock_irqsave(&ha->hardware_lock, flags);
6658 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
6659 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
6660 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
6661 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
6662 spin_unlock_irqrestore(&ha->hardware_lock, flags);
6663}
0107109e
AV		 6664
6665void
e315cd28 6666qla24xx_reset_adapter(scsi_qla_host_t *vha)
0107109e
AV		 6667{
6668 unsigned long flags = 0;
e315cd28 6669 struct qla_hw_data *ha = vha->hw;
0107109e
AV		 6670 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
6671
7ec0effd 6672 if (IS_P3P_TYPE(ha))
a9083016
GM		 6673 return;
6674
e315cd28 6675 vha->flags.online = 0;
fd34f556 6676 ha->isp_ops->disable_intrs(ha);
0107109e
AV		 6677
6678 spin_lock_irqsave(&ha->hardware_lock, flags);
6679 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
6680 RD_REG_DWORD(&reg->hccr);
6681 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
6682 RD_REG_DWORD(&reg->hccr);
6683 spin_unlock_irqrestore(&ha->hardware_lock, flags);
09ff36d3
AV		 6684
6685 if (IS_NOPOLLING_TYPE(ha))
6686 ha->isp_ops->enable_intrs(ha);
0107109e
AV		 6687}
6688
4e08df3f
DM		 6689/* On sparc systems, obtain port and node WWN from firmware
6690 * properties.
6691 */
e315cd28
AC		 6692static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha,
6693 struct nvram_24xx *nv)
4e08df3f
DM		 6694{
6695#ifdef CONFIG_SPARC
e315cd28 6696 struct qla_hw_data *ha = vha->hw;
4e08df3f 6697 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 6698 struct device_node *dp = pci_device_to_OF_node(pdev);
6699 const u8 *val;
4e08df3f
DM		 6700 int len;
6701
6702 val = of_get_property(dp, "port-wwn", &len);
6703 if (val && len >= WWN_SIZE)
6704 memcpy(nv->port_name, val, WWN_SIZE);
6705
6706 val = of_get_property(dp, "node-wwn", &len);
6707 if (val && len >= WWN_SIZE)
6708 memcpy(nv->node_name, val, WWN_SIZE);
6709#endif
6710}
6711
0107109e 6712int
e315cd28 6713qla24xx_nvram_config(scsi_qla_host_t *vha)
0107109e 6714{
4e08df3f 6715 int rval;
0107109e
AV		 6716 struct init_cb_24xx *icb;
6717 struct nvram_24xx *nv;
6718 uint32_t *dptr;
6719 uint8_t *dptr1, *dptr2;
6720 uint32_t chksum;
6721 uint16_t cnt;
e315cd28 6722 struct qla_hw_data *ha = vha->hw;
0107109e 6723
4e08df3f 6724 rval = QLA_SUCCESS;
0107109e 6725 icb = (struct init_cb_24xx *)ha->init_cb;
281afe19 6726 nv = ha->nvram;
0107109e
AV		 6727
6728 /* Determine NVRAM starting address. */
f73cb695 6729 if (ha->port_no == 0) {
e5b68a61
AC		 6730 ha->nvram_base = FA_NVRAM_FUNC0_ADDR;
6731 ha->vpd_base = FA_NVRAM_VPD0_ADDR;
6732 } else {
0107109e 6733 ha->nvram_base = FA_NVRAM_FUNC1_ADDR;
6f641790
AV		 6734 ha->vpd_base = FA_NVRAM_VPD1_ADDR;
6735 }
f73cb695 6736
e5b68a61
AC		 6737 ha->nvram_size = sizeof(struct nvram_24xx);
6738 ha->vpd_size = FA_NVRAM_VPD_SIZE;
0107109e 6739
281afe19
SJ		 6740 /* Get VPD data into cache */
6741 ha->vpd = ha->nvram + VPD_OFFSET;
e315cd28 6742 ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd,
281afe19
SJ		 6743 ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
6744
6745 /* Get NVRAM data into cache and calculate checksum. */
0107109e 6746 dptr = (uint32_t *)nv;
e315cd28 6747 ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base,
0107109e 6748 ha->nvram_size);
da08ef5c
JC		 6749 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++)
6750 chksum += le32_to_cpu(*dptr);
0107109e 6751
7c3df132
SK		 6752 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
6753 "Contents of NVRAM\n");
6754 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
6755 (uint8_t *)nv, ha->nvram_size);
0107109e
AV		 6756
6757 /* Bad NVRAM data, set defaults parameters. */
6758 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
6759 || nv->id[3] != ' ' ||
ad950360 6760 nv->nvram_version < cpu_to_le16(ICB_VERSION)) {
0107109e 6761 /* Reset NVRAM data. */
7c3df132 6762 ql_log(ql_log_warn, vha, 0x006b,
9e336520 6763 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132
SK		 6764 "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version);
6765 ql_log(ql_log_warn, vha, 0x006c,
6766 "Falling back to functioning (yet invalid -- WWPN) "
6767 "defaults.\n");
4e08df3f
DM		 6768
6769 /*
6770 * Set default initialization control block.
6771 */
6772 memset(nv, 0, ha->nvram_size);
ad950360
BVA		 6773 nv->nvram_version = cpu_to_le16(ICB_VERSION);
6774 nv->version = cpu_to_le16(ICB_VERSION);
98aee70d 6775 nv->frame_payload_size = 2048;
ad950360
BVA		 6776 nv->execution_throttle = cpu_to_le16(0xFFFF);
6777 nv->exchange_count = cpu_to_le16(0);
6778 nv->hard_address = cpu_to_le16(124);
4e08df3f 6779 nv->port_name[0] = 0x21;
f73cb695 6780 nv->port_name[1] = 0x00 + ha->port_no + 1;
4e08df3f
DM		 6781 nv->port_name[2] = 0x00;
6782 nv->port_name[3] = 0xe0;
6783 nv->port_name[4] = 0x8b;
6784 nv->port_name[5] = 0x1c;
6785 nv->port_name[6] = 0x55;
6786 nv->port_name[7] = 0x86;
6787 nv->node_name[0] = 0x20;
6788 nv->node_name[1] = 0x00;
6789 nv->node_name[2] = 0x00;
6790 nv->node_name[3] = 0xe0;
6791 nv->node_name[4] = 0x8b;
6792 nv->node_name[5] = 0x1c;
6793 nv->node_name[6] = 0x55;
6794 nv->node_name[7] = 0x86;
e315cd28 6795 qla24xx_nvram_wwn_from_ofw(vha, nv);
ad950360
BVA		 6796 nv->login_retry_count = cpu_to_le16(8);
6797 nv->interrupt_delay_timer = cpu_to_le16(0);
6798 nv->login_timeout = cpu_to_le16(0);
4e08df3f 6799 nv->firmware_options_1 =
ad950360
BVA		 6800 cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
6801 nv->firmware_options_2 = cpu_to_le32(2 << 4);
6802 nv->firmware_options_2 |= cpu_to_le32(BIT_12);
6803 nv->firmware_options_3 = cpu_to_le32(2 << 13);
6804 nv->host_p = cpu_to_le32(BIT_11|BIT_10);
6805 nv->efi_parameters = cpu_to_le32(0);
4e08df3f 6806 nv->reset_delay = 5;
ad950360
BVA		 6807 nv->max_luns_per_target = cpu_to_le16(128);
6808 nv->port_down_retry_count = cpu_to_le16(30);
6809 nv->link_down_timeout = cpu_to_le16(30);
4e08df3f
DM		 6810
6811 rval = 1;
0107109e
AV		 6812 }
6813
726b8548 6814 if (qla_tgt_mode_enabled(vha)) {
2d70c103 6815 /* Don't enable full login after initial LIP */
ad950360 6816 nv->firmware_options_1 &= cpu_to_le32(~BIT_13);
2d70c103 6817 /* Don't enable LIP full login for initiator */
ad950360 6818 nv->host_p &= cpu_to_le32(~BIT_10);
2d70c103
NB		 6819 }
6820
6821 qlt_24xx_config_nvram_stage1(vha, nv);
6822
0107109e 6823 /* Reset Initialization control block */
e315cd28 6824 memset(icb, 0, ha->init_cb_size);
0107109e
AV		 6825
6826 /* Copy 1st segment. */
6827 dptr1 = (uint8_t *)icb;
6828 dptr2 = (uint8_t *)&nv->version;
6829 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
6830 while (cnt--)
6831 *dptr1++ = *dptr2++;
6832
6833 icb->login_retry_count = nv->login_retry_count;
3ea66e28 6834 icb->link_down_on_nos = nv->link_down_on_nos;
0107109e
AV		 6835
6836 /* Copy 2nd segment. */
6837 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
6838 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
6839 cnt = (uint8_t *)&icb->reserved_3 -
6840 (uint8_t *)&icb->interrupt_delay_timer;
6841 while (cnt--)
6842 *dptr1++ = *dptr2++;
6843
6844 /*
6845 * Setup driver NVRAM options.
6846 */
e315cd28 6847 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
9bb9fcf2 6848 "QLA2462");
0107109e 6849
2d70c103
NB		 6850 qlt_24xx_config_nvram_stage2(vha, icb);
6851
ad950360 6852 if (nv->host_p & cpu_to_le32(BIT_15)) {
2d70c103 6853 /* Use alternate WWN? */
5341e868
AV		 6854 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
6855 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
6856 }
6857
0107109e 6858 /* Prepare nodename */
ad950360 6859 if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) {
0107109e
AV		 6860 /*
6861 * Firmware will apply the following mask if the nodename was
6862 * not provided.
6863 */
6864 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
6865 icb->node_name[0] &= 0xF0;
6866 }
6867
6868 /* Set host adapter parameters. */
6869 ha->flags.disable_risc_code_load = 0;
0c8c39af
AV		 6870 ha->flags.enable_lip_reset = 0;
6871 ha->flags.enable_lip_full_login =
6872 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
6873 ha->flags.enable_target_reset =
6874 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
0107109e 6875 ha->flags.enable_led_scheme = 0;
d4c760c2 6876 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
0107109e 6877
fd0e7e4d
AV		 6878 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
6879 (BIT_6 | BIT_5 | BIT_4)) >> 4;
0107109e
AV		 6880
6881 memcpy(ha->fw_seriallink_options24, nv->seriallink_options,
6882 sizeof(ha->fw_seriallink_options24));
6883
6884 /* save HBA serial number */
6885 ha->serial0 = icb->port_name[5];
6886 ha->serial1 = icb->port_name[6];
6887 ha->serial2 = icb->port_name[7];
e315cd28
AC		 6888 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
6889 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
0107109e 6890
ad950360 6891 icb->execution_throttle = cpu_to_le16(0xFFFF);
bc8fb3cb 6892
0107109e
AV		 6893 ha->retry_count = le16_to_cpu(nv->login_retry_count);
6894
6895 /* Set minimum login_timeout to 4 seconds. */
6896 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
6897 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
6898 if (le16_to_cpu(nv->login_timeout) < 4)
ad950360 6899 nv->login_timeout = cpu_to_le16(4);
0107109e 6900 ha->login_timeout = le16_to_cpu(nv->login_timeout);
0107109e 6901
00a537b8
AV		 6902 /* Set minimum RATOV to 100 tenths of a second. */
6903 ha->r_a_tov = 100;
0107109e
AV		 6904
6905 ha->loop_reset_delay = nv->reset_delay;
6906
6907 /* Link Down Timeout = 0:
6908 *
6909 * When Port Down timer expires we will start returning
6910 * I/O's to OS with "DID_NO_CONNECT".
6911 *
6912 * Link Down Timeout != 0:
6913 *
6914 * The driver waits for the link to come up after link down
6915 * before returning I/Os to OS with "DID_NO_CONNECT".
6916 */
6917 if (le16_to_cpu(nv->link_down_timeout) == 0) {
6918 ha->loop_down_abort_time =
6919 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
6920 } else {
6921 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
6922 ha->loop_down_abort_time =
6923 (LOOP_DOWN_TIME - ha->link_down_timeout);
6924 }
6925
6926 /* Need enough time to try and get the port back. */
6927 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
6928 if (qlport_down_retry)
6929 ha->port_down_retry_count = qlport_down_retry;
6930
6931 /* Set login_retry_count */
6932 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
6933 if (ha->port_down_retry_count ==
6934 le16_to_cpu(nv->port_down_retry_count) &&
6935 ha->port_down_retry_count > 3)
6936 ha->login_retry_count = ha->port_down_retry_count;
6937 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
6938 ha->login_retry_count = ha->port_down_retry_count;
6939 if (ql2xloginretrycount)
6940 ha->login_retry_count = ql2xloginretrycount;
6941
4fdfefe5 6942 /* Enable ZIO. */
e315cd28 6943 if (!vha->flags.init_done) {
4fdfefe5
AV		 6944 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
6945 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
6946 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
6947 le16_to_cpu(icb->interrupt_delay_timer): 2;
6948 }
ad950360 6949 icb->firmware_options_2 &= cpu_to_le32(
4fdfefe5 6950 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
e315cd28 6951 vha->flags.process_response_queue = 0;
4fdfefe5 6952 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d
AV		 6953 ha->zio_mode = QLA_ZIO_MODE_6;
6954
7c3df132 6955 ql_log(ql_log_info, vha, 0x006f,
4fdfefe5
AV		 6956 "ZIO mode %d enabled; timer delay (%d us).\n",
6957 ha->zio_mode, ha->zio_timer * 100);
6958
6959 icb->firmware_options_2 |= cpu_to_le32(
6960 (uint32_t)ha->zio_mode);
6961 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
e315cd28 6962 vha->flags.process_response_queue = 1;
4fdfefe5
AV		 6963 }
6964
4e08df3f 6965 if (rval) {
7c3df132
SK		 6966 ql_log(ql_log_warn, vha, 0x0070,
6967 "NVRAM configuration failed.\n");
4e08df3f
DM		 6968 }
6969 return (rval);
0107109e
AV		 6970}
6971
4243c115
SC		 6972uint8_t qla27xx_find_valid_image(struct scsi_qla_host *vha)
6973{
6974 struct qla27xx_image_status pri_image_status, sec_image_status;
6975 uint8_t valid_pri_image, valid_sec_image;
6976 uint32_t *wptr;
6977 uint32_t cnt, chksum, size;
6978 struct qla_hw_data *ha = vha->hw;
6979
6980 valid_pri_image = valid_sec_image = 1;
6981 ha->active_image = 0;
6982 size = sizeof(struct qla27xx_image_status) / sizeof(uint32_t);
6983
6984 if (!ha->flt_region_img_status_pri) {
6985 valid_pri_image = 0;
6986 goto check_sec_image;
6987 }
6988
6989 qla24xx_read_flash_data(vha, (uint32_t *)(&pri_image_status),
6990 ha->flt_region_img_status_pri, size);
6991
6992 if (pri_image_status.signature != QLA27XX_IMG_STATUS_SIGN) {
6993 ql_dbg(ql_dbg_init, vha, 0x018b,
6994 "Primary image signature (0x%x) not valid\n",
6995 pri_image_status.signature);
6996 valid_pri_image = 0;
6997 goto check_sec_image;
6998 }
6999
7000 wptr = (uint32_t *)(&pri_image_status);
7001 cnt = size;
7002
da08ef5c
JC		 7003 for (chksum = 0; cnt--; wptr++)
7004 chksum += le32_to_cpu(*wptr);
41dc529a 7005
4243c115
SC		 7006 if (chksum) {
7007 ql_dbg(ql_dbg_init, vha, 0x018c,
7008 "Checksum validation failed for primary image (0x%x)\n",
7009 chksum);
7010 valid_pri_image = 0;
7011 }
7012
7013check_sec_image:
7014 if (!ha->flt_region_img_status_sec) {
7015 valid_sec_image = 0;
7016 goto check_valid_image;
7017 }
7018
7019 qla24xx_read_flash_data(vha, (uint32_t *)(&sec_image_status),
7020 ha->flt_region_img_status_sec, size);
7021
7022 if (sec_image_status.signature != QLA27XX_IMG_STATUS_SIGN) {
7023 ql_dbg(ql_dbg_init, vha, 0x018d,
7024 "Secondary image signature(0x%x) not valid\n",
7025 sec_image_status.signature);
7026 valid_sec_image = 0;
7027 goto check_valid_image;
7028 }
7029
7030 wptr = (uint32_t *)(&sec_image_status);
7031 cnt = size;
da08ef5c
JC		 7032 for (chksum = 0; cnt--; wptr++)
7033 chksum += le32_to_cpu(*wptr);
4243c115
SC		 7034 if (chksum) {
7035 ql_dbg(ql_dbg_init, vha, 0x018e,
7036 "Checksum validation failed for secondary image (0x%x)\n",
7037 chksum);
7038 valid_sec_image = 0;
7039 }
7040
7041check_valid_image:
7042 if (valid_pri_image && (pri_image_status.image_status_mask & 0x1))
7043 ha->active_image = QLA27XX_PRIMARY_IMAGE;
7044 if (valid_sec_image && (sec_image_status.image_status_mask & 0x1)) {
7045 if (!ha->active_image ||
7046 pri_image_status.generation_number <
7047 sec_image_status.generation_number)
7048 ha->active_image = QLA27XX_SECONDARY_IMAGE;
7049 }
7050
7051 ql_dbg(ql_dbg_init, vha, 0x018f, "%s image\n",
7052 ha->active_image == 0 ? "default bootld and fw" :
7053 ha->active_image == 1 ? "primary" :
7054 ha->active_image == 2 ? "secondary" :
7055 "Invalid");
7056
7057 return ha->active_image;
7058}
7059
413975a0 7060static int
cbc8eb67
AV		 7061qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
7062 uint32_t faddr)
d1c61909 7063{
73208dfd 7064 int rval = QLA_SUCCESS;
d1c61909 7065 int segments, fragment;
d1c61909
AV		 7066 uint32_t *dcode, dlen;
7067 uint32_t risc_addr;
7068 uint32_t risc_size;
7069 uint32_t i;
e315cd28 7070 struct qla_hw_data *ha = vha->hw;
73208dfd 7071 struct req_que *req = ha->req_q_map[0];
eaac30be 7072
7c3df132 7073 ql_dbg(ql_dbg_init, vha, 0x008b,
cfb0919c 7074 "FW: Loading firmware from flash (%x).\n", faddr);
eaac30be 7075
d1c61909
AV		 7076 rval = QLA_SUCCESS;
7077
7078 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 7079 dcode = (uint32_t *)req->ring;
d1c61909
AV		 7080 *srisc_addr = 0;
7081
4243c115
SC		 7082 if (IS_QLA27XX(ha) &&
7083 qla27xx_find_valid_image(vha) == QLA27XX_SECONDARY_IMAGE)
7084 faddr = ha->flt_region_fw_sec;
7085
d1c61909 7086 /* Validate firmware image by checking version. */
e315cd28 7087 qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
d1c61909
AV		 7088 for (i = 0; i < 4; i++)
7089 dcode[i] = be32_to_cpu(dcode[i]);
7090 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
7091 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
7092 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
7093 dcode[3] == 0)) {
7c3df132
SK		 7094 ql_log(ql_log_fatal, vha, 0x008c,
7095 "Unable to verify the integrity of flash firmware "
7096 "image.\n");
7097 ql_log(ql_log_fatal, vha, 0x008d,
7098 "Firmware data: %08x %08x %08x %08x.\n",
7099 dcode[0], dcode[1], dcode[2], dcode[3]);
d1c61909
AV		 7100
7101 return QLA_FUNCTION_FAILED;
7102 }
7103
7104 while (segments && rval == QLA_SUCCESS) {
7105 /* Read segment's load information. */
e315cd28 7106 qla24xx_read_flash_data(vha, dcode, faddr, 4);
d1c61909
AV		 7107
7108 risc_addr = be32_to_cpu(dcode[2]);
7109 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
7110 risc_size = be32_to_cpu(dcode[3]);
7111
7112 fragment = 0;
7113 while (risc_size > 0 && rval == QLA_SUCCESS) {
7114 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
7115 if (dlen > risc_size)
7116 dlen = risc_size;
7117
7c3df132
SK		 7118 ql_dbg(ql_dbg_init, vha, 0x008e,
7119 "Loading risc segment@ risc addr %x "
7120 "number of dwords 0x%x offset 0x%x.\n",
7121 risc_addr, dlen, faddr);
d1c61909 7122
e315cd28 7123 qla24xx_read_flash_data(vha, dcode, faddr, dlen);
d1c61909
AV		 7124 for (i = 0; i < dlen; i++)
7125 dcode[i] = swab32(dcode[i]);
7126
73208dfd 7127 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
d1c61909
AV		 7128 dlen);
7129 if (rval) {
7c3df132
SK		 7130 ql_log(ql_log_fatal, vha, 0x008f,
7131 "Failed to load segment %d of firmware.\n",
7132 fragment);
f261f7af 7133 return QLA_FUNCTION_FAILED;
d1c61909
AV		 7134 }
7135
7136 faddr += dlen;
7137 risc_addr += dlen;
7138 risc_size -= dlen;
7139 fragment++;
7140 }
7141
7142 /* Next segment. */
7143 segments--;
7144 }
7145
f73cb695
CD		 7146 if (!IS_QLA27XX(ha))
7147 return rval;
7148
7149 if (ha->fw_dump_template)
7150 vfree(ha->fw_dump_template);
7151 ha->fw_dump_template = NULL;
7152 ha->fw_dump_template_len = 0;
7153
7154 ql_dbg(ql_dbg_init, vha, 0x0161,
7155 "Loading fwdump template from %x\n", faddr);
7156 qla24xx_read_flash_data(vha, dcode, faddr, 7);
7157 risc_size = be32_to_cpu(dcode[2]);
7158 ql_dbg(ql_dbg_init, vha, 0x0162,
7159 "-> array size %x dwords\n", risc_size);
7160 if (risc_size == 0 || risc_size == ~0)
7161 goto default_template;
7162
7163 dlen = (risc_size - 8) * sizeof(*dcode);
7164 ql_dbg(ql_dbg_init, vha, 0x0163,
7165 "-> template allocating %x bytes...\n", dlen);
7166 ha->fw_dump_template = vmalloc(dlen);
7167 if (!ha->fw_dump_template) {
7168 ql_log(ql_log_warn, vha, 0x0164,
7169 "Failed fwdump template allocate %x bytes.\n", risc_size);
7170 goto default_template;
7171 }
7172
7173 faddr += 7;
7174 risc_size -= 8;
7175 dcode = ha->fw_dump_template;
7176 qla24xx_read_flash_data(vha, dcode, faddr, risc_size);
7177 for (i = 0; i < risc_size; i++)
7178 dcode[i] = le32_to_cpu(dcode[i]);
7179
7180 if (!qla27xx_fwdt_template_valid(dcode)) {
7181 ql_log(ql_log_warn, vha, 0x0165,
7182 "Failed fwdump template validate\n");
7183 goto default_template;
7184 }
7185
7186 dlen = qla27xx_fwdt_template_size(dcode);
7187 ql_dbg(ql_dbg_init, vha, 0x0166,
7188 "-> template size %x bytes\n", dlen);
7189 if (dlen > risc_size * sizeof(*dcode)) {
7190 ql_log(ql_log_warn, vha, 0x0167,
4fae52b5 7191 "Failed fwdump template exceeds array by %zx bytes\n",
383a298b 7192 (size_t)(dlen - risc_size * sizeof(*dcode)));
f73cb695
CD		 7193 goto default_template;
7194 }
7195 ha->fw_dump_template_len = dlen;
7196 return rval;
7197
7198default_template:
7199 ql_log(ql_log_warn, vha, 0x0168, "Using default fwdump template\n");
7200 if (ha->fw_dump_template)
7201 vfree(ha->fw_dump_template);
7202 ha->fw_dump_template = NULL;
7203 ha->fw_dump_template_len = 0;
7204
7205 dlen = qla27xx_fwdt_template_default_size();
7206 ql_dbg(ql_dbg_init, vha, 0x0169,
7207 "-> template allocating %x bytes...\n", dlen);
7208 ha->fw_dump_template = vmalloc(dlen);
7209 if (!ha->fw_dump_template) {
7210 ql_log(ql_log_warn, vha, 0x016a,
7211 "Failed fwdump template allocate %x bytes.\n", risc_size);
7212 goto failed_template;
7213 }
7214
7215 dcode = ha->fw_dump_template;
7216 risc_size = dlen / sizeof(*dcode);
7217 memcpy(dcode, qla27xx_fwdt_template_default(), dlen);
7218 for (i = 0; i < risc_size; i++)
7219 dcode[i] = be32_to_cpu(dcode[i]);
7220
7221 if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) {
7222 ql_log(ql_log_warn, vha, 0x016b,
7223 "Failed fwdump template validate\n");
7224 goto failed_template;
7225 }
7226
7227 dlen = qla27xx_fwdt_template_size(ha->fw_dump_template);
7228 ql_dbg(ql_dbg_init, vha, 0x016c,
7229 "-> template size %x bytes\n", dlen);
7230 ha->fw_dump_template_len = dlen;
7231 return rval;
7232
7233failed_template:
7234 ql_log(ql_log_warn, vha, 0x016d, "Failed default fwdump template\n");
7235 if (ha->fw_dump_template)
7236 vfree(ha->fw_dump_template);
7237 ha->fw_dump_template = NULL;
7238 ha->fw_dump_template_len = 0;
d1c61909
AV		 7239 return rval;
7240}
7241
e9454a88 7242#define QLA_FW_URL "http://ldriver.qlogic.com/firmware/"
d1c61909 7243
0107109e 7244int
e315cd28 7245qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5433383e
AV		 7246{
7247 int rval;
7248 int i, fragment;
7249 uint16_t *wcode, *fwcode;
7250 uint32_t risc_addr, risc_size, fwclen, wlen, *seg;
7251 struct fw_blob *blob;
e315cd28 7252 struct qla_hw_data *ha = vha->hw;
73208dfd 7253 struct req_que *req = ha->req_q_map[0];
5433383e
AV		 7254
7255 /* Load firmware blob. */
e315cd28 7256 blob = qla2x00_request_firmware(vha);
5433383e 7257 if (!blob) {
7c3df132 7258 ql_log(ql_log_info, vha, 0x0083,
94bcf830 7259 "Firmware image unavailable.\n");
7c3df132
SK		 7260 ql_log(ql_log_info, vha, 0x0084,
7261 "Firmware images can be retrieved from: "QLA_FW_URL ".\n");
5433383e
AV		 7262 return QLA_FUNCTION_FAILED;
7263 }
7264
7265 rval = QLA_SUCCESS;
7266
73208dfd 7267 wcode = (uint16_t *)req->ring;
5433383e
AV		 7268 *srisc_addr = 0;
7269 fwcode = (uint16_t *)blob->fw->data;
7270 fwclen = 0;
7271
7272 /* Validate firmware image by checking version. */
7273 if (blob->fw->size < 8 * sizeof(uint16_t)) {
7c3df132 7274 ql_log(ql_log_fatal, vha, 0x0085,
5b5e0928 7275 "Unable to verify integrity of firmware image (%zd).\n",
5433383e
AV		 7276 blob->fw->size);
7277 goto fail_fw_integrity;
7278 }
7279 for (i = 0; i < 4; i++)
7280 wcode[i] = be16_to_cpu(fwcode[i + 4]);
7281 if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff &&
7282 wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 &&
7283 wcode[2] == 0 && wcode[3] == 0)) {
7c3df132
SK		 7284 ql_log(ql_log_fatal, vha, 0x0086,
7285 "Unable to verify integrity of firmware image.\n");
7286 ql_log(ql_log_fatal, vha, 0x0087,
7287 "Firmware data: %04x %04x %04x %04x.\n",
7288 wcode[0], wcode[1], wcode[2], wcode[3]);
5433383e
AV		 7289 goto fail_fw_integrity;
7290 }
7291
7292 seg = blob->segs;
7293 while (*seg && rval == QLA_SUCCESS) {
7294 risc_addr = *seg;
7295 *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr;
7296 risc_size = be16_to_cpu(fwcode[3]);
7297
7298 /* Validate firmware image size. */
7299 fwclen += risc_size * sizeof(uint16_t);
7300 if (blob->fw->size < fwclen) {
7c3df132 7301 ql_log(ql_log_fatal, vha, 0x0088,
5433383e 7302 "Unable to verify integrity of firmware image "
5b5e0928 7303 "(%zd).\n", blob->fw->size);
5433383e
AV		 7304 goto fail_fw_integrity;
7305 }
7306
7307 fragment = 0;
7308 while (risc_size > 0 && rval == QLA_SUCCESS) {
7309 wlen = (uint16_t)(ha->fw_transfer_size >> 1);
7310 if (wlen > risc_size)
7311 wlen = risc_size;
7c3df132
SK		 7312 ql_dbg(ql_dbg_init, vha, 0x0089,
7313 "Loading risc segment@ risc addr %x number of "
7314 "words 0x%x.\n", risc_addr, wlen);
5433383e
AV		 7315
7316 for (i = 0; i < wlen; i++)
7317 wcode[i] = swab16(fwcode[i]);
7318
73208dfd 7319 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
5433383e
AV		 7320 wlen);
7321 if (rval) {
7c3df132
SK		 7322 ql_log(ql_log_fatal, vha, 0x008a,
7323 "Failed to load segment %d of firmware.\n",
7324 fragment);
5433383e
AV		 7325 break;
7326 }
7327
7328 fwcode += wlen;
7329 risc_addr += wlen;
7330 risc_size -= wlen;
7331 fragment++;
7332 }
7333
7334 /* Next segment. */
7335 seg++;
7336 }
7337 return rval;
7338
7339fail_fw_integrity:
7340 return QLA_FUNCTION_FAILED;
7341}
7342
eaac30be
AV		 7343static int
7344qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
0107109e
AV		 7345{
7346 int rval;
7347 int segments, fragment;
7348 uint32_t *dcode, dlen;
7349 uint32_t risc_addr;
7350 uint32_t risc_size;
7351 uint32_t i;
5433383e 7352 struct fw_blob *blob;
f73cb695
CD		 7353 const uint32_t *fwcode;
7354 uint32_t fwclen;
e315cd28 7355 struct qla_hw_data *ha = vha->hw;
73208dfd 7356 struct req_que *req = ha->req_q_map[0];
0107109e 7357
5433383e 7358 /* Load firmware blob. */
e315cd28 7359 blob = qla2x00_request_firmware(vha);
5433383e 7360 if (!blob) {
7c3df132 7361 ql_log(ql_log_warn, vha, 0x0090,
94bcf830 7362 "Firmware image unavailable.\n");
7c3df132
SK		 7363 ql_log(ql_log_warn, vha, 0x0091,
7364 "Firmware images can be retrieved from: "
7365 QLA_FW_URL ".\n");
d1c61909 7366
eaac30be 7367 return QLA_FUNCTION_FAILED;
0107109e
AV		 7368 }
7369
cfb0919c
CD		 7370 ql_dbg(ql_dbg_init, vha, 0x0092,
7371 "FW: Loading via request-firmware.\n");
eaac30be 7372
0107109e
AV		 7373 rval = QLA_SUCCESS;
7374
7375 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 7376 dcode = (uint32_t *)req->ring;
0107109e 7377 *srisc_addr = 0;
5433383e 7378 fwcode = (uint32_t *)blob->fw->data;
0107109e
AV		 7379 fwclen = 0;
7380
7381 /* Validate firmware image by checking version. */
5433383e 7382 if (blob->fw->size < 8 * sizeof(uint32_t)) {
7c3df132 7383 ql_log(ql_log_fatal, vha, 0x0093,
5b5e0928 7384 "Unable to verify integrity of firmware image (%zd).\n",
5433383e 7385 blob->fw->size);
f73cb695 7386 return QLA_FUNCTION_FAILED;
0107109e
AV		 7387 }
7388 for (i = 0; i < 4; i++)
7389 dcode[i] = be32_to_cpu(fwcode[i + 4]);
7390 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
7391 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
7392 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
7393 dcode[3] == 0)) {
7c3df132 7394 ql_log(ql_log_fatal, vha, 0x0094,
5b5e0928 7395 "Unable to verify integrity of firmware image (%zd).\n",
7c3df132
SK		 7396 blob->fw->size);
7397 ql_log(ql_log_fatal, vha, 0x0095,
7398 "Firmware data: %08x %08x %08x %08x.\n",
7399 dcode[0], dcode[1], dcode[2], dcode[3]);
f73cb695 7400 return QLA_FUNCTION_FAILED;
0107109e
AV		 7401 }
7402
7403 while (segments && rval == QLA_SUCCESS) {
7404 risc_addr = be32_to_cpu(fwcode[2]);
7405 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
7406 risc_size = be32_to_cpu(fwcode[3]);
7407
7408 /* Validate firmware image size. */
7409 fwclen += risc_size * sizeof(uint32_t);
5433383e 7410 if (blob->fw->size < fwclen) {
7c3df132 7411 ql_log(ql_log_fatal, vha, 0x0096,
5433383e 7412 "Unable to verify integrity of firmware image "
5b5e0928 7413 "(%zd).\n", blob->fw->size);
f73cb695 7414 return QLA_FUNCTION_FAILED;
0107109e
AV		 7415 }
7416
7417 fragment = 0;
7418 while (risc_size > 0 && rval == QLA_SUCCESS) {
7419 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
7420 if (dlen > risc_size)
7421 dlen = risc_size;
7422
7c3df132
SK		 7423 ql_dbg(ql_dbg_init, vha, 0x0097,
7424 "Loading risc segment@ risc addr %x "
7425 "number of dwords 0x%x.\n", risc_addr, dlen);
0107109e
AV		 7426
7427 for (i = 0; i < dlen; i++)
7428 dcode[i] = swab32(fwcode[i]);
7429
73208dfd 7430 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
590f98e5 7431 dlen);
0107109e 7432 if (rval) {
7c3df132
SK		 7433 ql_log(ql_log_fatal, vha, 0x0098,
7434 "Failed to load segment %d of firmware.\n",
7435 fragment);
f261f7af 7436 return QLA_FUNCTION_FAILED;
0107109e
AV		 7437 }
7438
7439 fwcode += dlen;
7440 risc_addr += dlen;
7441 risc_size -= dlen;
7442 fragment++;
7443 }
7444
7445 /* Next segment. */
7446 segments--;
7447 }
f73cb695
CD		 7448
7449 if (!IS_QLA27XX(ha))
7450 return rval;
7451
7452 if (ha->fw_dump_template)
7453 vfree(ha->fw_dump_template);
7454 ha->fw_dump_template = NULL;
7455 ha->fw_dump_template_len = 0;
7456
7457 ql_dbg(ql_dbg_init, vha, 0x171,
97ea702b
CD		 7458 "Loading fwdump template from %x\n",
7459 (uint32_t)((void *)fwcode - (void *)blob->fw->data));
f73cb695
CD		 7460 risc_size = be32_to_cpu(fwcode[2]);
7461 ql_dbg(ql_dbg_init, vha, 0x172,
7462 "-> array size %x dwords\n", risc_size);
7463 if (risc_size == 0 || risc_size == ~0)
7464 goto default_template;
7465
7466 dlen = (risc_size - 8) * sizeof(*fwcode);
7467 ql_dbg(ql_dbg_init, vha, 0x0173,
7468 "-> template allocating %x bytes...\n", dlen);
7469 ha->fw_dump_template = vmalloc(dlen);
7470 if (!ha->fw_dump_template) {
7471 ql_log(ql_log_warn, vha, 0x0174,
7472 "Failed fwdump template allocate %x bytes.\n", risc_size);
7473 goto default_template;
7474 }
7475
7476 fwcode += 7;
7477 risc_size -= 8;
7478 dcode = ha->fw_dump_template;
7479 for (i = 0; i < risc_size; i++)
7480 dcode[i] = le32_to_cpu(fwcode[i]);
7481
7482 if (!qla27xx_fwdt_template_valid(dcode)) {
7483 ql_log(ql_log_warn, vha, 0x0175,
7484 "Failed fwdump template validate\n");
7485 goto default_template;
7486 }
7487
7488 dlen = qla27xx_fwdt_template_size(dcode);
7489 ql_dbg(ql_dbg_init, vha, 0x0176,
7490 "-> template size %x bytes\n", dlen);
7491 if (dlen > risc_size * sizeof(*fwcode)) {
7492 ql_log(ql_log_warn, vha, 0x0177,
4fae52b5 7493 "Failed fwdump template exceeds array by %zx bytes\n",
383a298b 7494 (size_t)(dlen - risc_size * sizeof(*fwcode)));
f73cb695
CD		 7495 goto default_template;
7496 }
7497 ha->fw_dump_template_len = dlen;
0107109e
AV		 7498 return rval;
7499
f73cb695
CD		 7500default_template:
7501 ql_log(ql_log_warn, vha, 0x0178, "Using default fwdump template\n");
7502 if (ha->fw_dump_template)
7503 vfree(ha->fw_dump_template);
7504 ha->fw_dump_template = NULL;
7505 ha->fw_dump_template_len = 0;
7506
7507 dlen = qla27xx_fwdt_template_default_size();
7508 ql_dbg(ql_dbg_init, vha, 0x0179,
7509 "-> template allocating %x bytes...\n", dlen);
7510 ha->fw_dump_template = vmalloc(dlen);
7511 if (!ha->fw_dump_template) {
7512 ql_log(ql_log_warn, vha, 0x017a,
7513 "Failed fwdump template allocate %x bytes.\n", risc_size);
7514 goto failed_template;
7515 }
7516
7517 dcode = ha->fw_dump_template;
7518 risc_size = dlen / sizeof(*fwcode);
7519 fwcode = qla27xx_fwdt_template_default();
7520 for (i = 0; i < risc_size; i++)
7521 dcode[i] = be32_to_cpu(fwcode[i]);
7522
7523 if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) {
7524 ql_log(ql_log_warn, vha, 0x017b,
7525 "Failed fwdump template validate\n");
7526 goto failed_template;
7527 }
7528
7529 dlen = qla27xx_fwdt_template_size(ha->fw_dump_template);
7530 ql_dbg(ql_dbg_init, vha, 0x017c,
7531 "-> template size %x bytes\n", dlen);
7532 ha->fw_dump_template_len = dlen;
7533 return rval;
7534
7535failed_template:
7536 ql_log(ql_log_warn, vha, 0x017d, "Failed default fwdump template\n");
7537 if (ha->fw_dump_template)
7538 vfree(ha->fw_dump_template);
7539 ha->fw_dump_template = NULL;
7540 ha->fw_dump_template_len = 0;
7541 return rval;
0107109e 7542}
18c6c127 7543
eaac30be
AV		 7544int
7545qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
7546{
7547 int rval;
7548
e337d907
AV		 7549 if (ql2xfwloadbin == 1)
7550 return qla81xx_load_risc(vha, srisc_addr);
7551
eaac30be
AV		 7552 /*
7553 * FW Load priority:
7554 * 1) Firmware via request-firmware interface (.bin file).
7555 * 2) Firmware residing in flash.
7556 */
7557 rval = qla24xx_load_risc_blob(vha, srisc_addr);
7558 if (rval == QLA_SUCCESS)
7559 return rval;
7560
cbc8eb67
AV		 7561 return qla24xx_load_risc_flash(vha, srisc_addr,
7562 vha->hw->flt_region_fw);
eaac30be
AV		 7563}
7564
7565int
7566qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
7567{
7568 int rval;
cbc8eb67 7569 struct qla_hw_data *ha = vha->hw;
eaac30be 7570
e337d907 7571 if (ql2xfwloadbin == 2)
cbc8eb67 7572 goto try_blob_fw;
e337d907 7573
eaac30be
AV		 7574 /*
7575 * FW Load priority:
7576 * 1) Firmware residing in flash.
7577 * 2) Firmware via request-firmware interface (.bin file).
cbc8eb67 7578 * 3) Golden-Firmware residing in flash -- limited operation.
eaac30be 7579 */
cbc8eb67 7580 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
eaac30be
AV		 7581 if (rval == QLA_SUCCESS)
7582 return rval;
7583
cbc8eb67
AV		 7584try_blob_fw:
7585 rval = qla24xx_load_risc_blob(vha, srisc_addr);
7586 if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw)
7587 return rval;
7588
7c3df132
SK		 7589 ql_log(ql_log_info, vha, 0x0099,
7590 "Attempting to fallback to golden firmware.\n");
cbc8eb67
AV		 7591 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
7592 if (rval != QLA_SUCCESS)
7593 return rval;
7594
7c3df132 7595 ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n");
cbc8eb67 7596 ha->flags.running_gold_fw = 1;
cbc8eb67 7597 return rval;
eaac30be
AV		 7598}
7599
18c6c127 7600void
e315cd28 7601qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha)
18c6c127
AV		 7602{
7603 int ret, retries;
e315cd28 7604 struct qla_hw_data *ha = vha->hw;
18c6c127 7605
85880801
AV		 7606 if (ha->flags.pci_channel_io_perm_failure)
7607 return;
e428924c 7608 if (!IS_FWI2_CAPABLE(ha))
18c6c127 7609 return;
75edf81d
AV		 7610 if (!ha->fw_major_version)
7611 return;
ec7193e2
QT		 7612 if (!ha->flags.fw_started)
7613 return;
18c6c127 7614
e315cd28 7615 ret = qla2x00_stop_firmware(vha);
7c7f1f29 7616 for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&
b469a7cb 7617 ret != QLA_INVALID_COMMAND && retries ; retries--) {
e315cd28
AC		 7618 ha->isp_ops->reset_chip(vha);
7619 if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS)
18c6c127 7620 continue;
e315cd28 7621 if (qla2x00_setup_chip(vha) != QLA_SUCCESS)
18c6c127 7622 continue;
7c3df132
SK		 7623 ql_log(ql_log_info, vha, 0x8015,
7624 "Attempting retry of stop-firmware command.\n");
e315cd28 7625 ret = qla2x00_stop_firmware(vha);
18c6c127 7626 }
ec7193e2 7627
4b60c827 7628 QLA_FW_STOPPED(ha);
ec7193e2 7629 ha->flags.fw_init_done = 0;
18c6c127 7630}
2c3dfe3f
SJ		 7631
7632int
e315cd28 7633qla24xx_configure_vhba(scsi_qla_host_t *vha)
2c3dfe3f
SJ		 7634{
7635 int rval = QLA_SUCCESS;
0b91d116 7636 int rval2;
2c3dfe3f 7637 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28
AC		 7638 struct qla_hw_data *ha = vha->hw;
7639 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
67c2e93a
AC		 7640 struct req_que *req;
7641 struct rsp_que *rsp;
2c3dfe3f 7642
e315cd28 7643 if (!vha->vp_idx)
2c3dfe3f
SJ		 7644 return -EINVAL;
7645
e315cd28 7646 rval = qla2x00_fw_ready(base_vha);
d7459527
MH		 7647 if (vha->qpair)
7648 req = vha->qpair->req;
67c2e93a 7649 else
d7459527 7650 req = ha->req_q_map[0];
67c2e93a
AC		 7651 rsp = req->rsp;
7652
2c3dfe3f 7653 if (rval == QLA_SUCCESS) {
e315cd28 7654 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
73208dfd 7655 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
2c3dfe3f
SJ		 7656 }
7657
e315cd28 7658 vha->flags.management_server_logged_in = 0;
2c3dfe3f
SJ		 7659
7660 /* Login to SNS first */
0b91d116
CD		 7661 rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb,
7662 BIT_1);
7663 if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
7664 if (rval2 == QLA_MEMORY_ALLOC_FAILED)
7665 ql_dbg(ql_dbg_init, vha, 0x0120,
7666 "Failed SNS login: loop_id=%x, rval2=%d\n",
7667 NPH_SNS, rval2);
7668 else
7669 ql_dbg(ql_dbg_init, vha, 0x0103,
7670 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x "
7671 "mb[2]=%x mb[6]=%x mb[7]=%x.\n",
7672 NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]);
2c3dfe3f
SJ		 7673 return (QLA_FUNCTION_FAILED);
7674 }
7675
e315cd28
AC		 7676 atomic_set(&vha->loop_down_timer, 0);
7677 atomic_set(&vha->loop_state, LOOP_UP);
7678 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
7679 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
7680 rval = qla2x00_loop_resync(base_vha);
2c3dfe3f
SJ		 7681
7682 return rval;
7683}
4d4df193
HK		 7684
7685/* 84XX Support **************************************************************/
7686
7687static LIST_HEAD(qla_cs84xx_list);
7688static DEFINE_MUTEX(qla_cs84xx_mutex);
7689
7690static struct qla_chip_state_84xx *
e315cd28 7691qla84xx_get_chip(struct scsi_qla_host *vha)
4d4df193
HK		 7692{
7693 struct qla_chip_state_84xx *cs84xx;
e315cd28 7694 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 7695
7696 mutex_lock(&qla_cs84xx_mutex);
7697
7698 /* Find any shared 84xx chip. */
7699 list_for_each_entry(cs84xx, &qla_cs84xx_list, list) {
7700 if (cs84xx->bus == ha->pdev->bus) {
7701 kref_get(&cs84xx->kref);
7702 goto done;
7703 }
7704 }
7705
7706 cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL);
7707 if (!cs84xx)
7708 goto done;
7709
7710 kref_init(&cs84xx->kref);
7711 spin_lock_init(&cs84xx->access_lock);
7712 mutex_init(&cs84xx->fw_update_mutex);
7713 cs84xx->bus = ha->pdev->bus;
7714
7715 list_add_tail(&cs84xx->list, &qla_cs84xx_list);
7716done:
7717 mutex_unlock(&qla_cs84xx_mutex);
7718 return cs84xx;
7719}
7720
7721static void
7722__qla84xx_chip_release(struct kref *kref)
7723{
7724 struct qla_chip_state_84xx *cs84xx =
7725 container_of(kref, struct qla_chip_state_84xx, kref);
7726
7727 mutex_lock(&qla_cs84xx_mutex);
7728 list_del(&cs84xx->list);
7729 mutex_unlock(&qla_cs84xx_mutex);
7730 kfree(cs84xx);
7731}
7732
7733void
e315cd28 7734qla84xx_put_chip(struct scsi_qla_host *vha)
4d4df193 7735{
e315cd28 7736 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 7737 if (ha->cs84xx)
7738 kref_put(&ha->cs84xx->kref, __qla84xx_chip_release);
7739}
7740
7741static int
e315cd28 7742qla84xx_init_chip(scsi_qla_host_t *vha)
4d4df193
HK		 7743{
7744 int rval;
7745 uint16_t status[2];
e315cd28 7746 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 7747
7748 mutex_lock(&ha->cs84xx->fw_update_mutex);
7749
e315cd28 7750 rval = qla84xx_verify_chip(vha, status);
4d4df193
HK		 7751
7752 mutex_unlock(&ha->cs84xx->fw_update_mutex);
7753
7754 return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED:
7755 QLA_SUCCESS;
7756}
3a03eb79
AV		 7757
7758/* 81XX Support **************************************************************/
7759
7760int
7761qla81xx_nvram_config(scsi_qla_host_t *vha)
7762{
7763 int rval;
7764 struct init_cb_81xx *icb;
7765 struct nvram_81xx *nv;
7766 uint32_t *dptr;
7767 uint8_t *dptr1, *dptr2;
7768 uint32_t chksum;
7769 uint16_t cnt;
7770 struct qla_hw_data *ha = vha->hw;
7771
7772 rval = QLA_SUCCESS;
7773 icb = (struct init_cb_81xx *)ha->init_cb;
7774 nv = ha->nvram;
7775
7776 /* Determine NVRAM starting address. */
7777 ha->nvram_size = sizeof(struct nvram_81xx);
3a03eb79 7778 ha->vpd_size = FA_NVRAM_VPD_SIZE;
7ec0effd
AD		 7779 if (IS_P3P_TYPE(ha) || IS_QLA8031(ha))
7780 ha->vpd_size = FA_VPD_SIZE_82XX;
3a03eb79
AV		 7781
7782 /* Get VPD data into cache */
7783 ha->vpd = ha->nvram + VPD_OFFSET;
3d79038f
AV		 7784 ha->isp_ops->read_optrom(vha, ha->vpd, ha->flt_region_vpd << 2,
7785 ha->vpd_size);
3a03eb79
AV		 7786
7787 /* Get NVRAM data into cache and calculate checksum. */
3d79038f 7788 ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2,
3a03eb79 7789 ha->nvram_size);
3d79038f 7790 dptr = (uint32_t *)nv;
da08ef5c
JC		 7791 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++)
7792 chksum += le32_to_cpu(*dptr);
3a03eb79 7793
7c3df132
SK		 7794 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
7795 "Contents of NVRAM:\n");
7796 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
7797 (uint8_t *)nv, ha->nvram_size);
3a03eb79
AV		 7798
7799 /* Bad NVRAM data, set defaults parameters. */
7800 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
7801 || nv->id[3] != ' ' ||
ad950360 7802 nv->nvram_version < cpu_to_le16(ICB_VERSION)) {
3a03eb79 7803 /* Reset NVRAM data. */
7c3df132 7804 ql_log(ql_log_info, vha, 0x0073,
9e336520 7805 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132 7806 "version=0x%x.\n", chksum, nv->id[0],
3a03eb79 7807 le16_to_cpu(nv->nvram_version));
7c3df132
SK		 7808 ql_log(ql_log_info, vha, 0x0074,
7809 "Falling back to functioning (yet invalid -- WWPN) "
7810 "defaults.\n");
3a03eb79
AV		 7811
7812 /*
7813 * Set default initialization control block.
7814 */
7815 memset(nv, 0, ha->nvram_size);
ad950360
BVA		 7816 nv->nvram_version = cpu_to_le16(ICB_VERSION);
7817 nv->version = cpu_to_le16(ICB_VERSION);
98aee70d 7818 nv->frame_payload_size = 2048;
ad950360
BVA		 7819 nv->execution_throttle = cpu_to_le16(0xFFFF);
7820 nv->exchange_count = cpu_to_le16(0);
3a03eb79 7821 nv->port_name[0] = 0x21;
f73cb695 7822 nv->port_name[1] = 0x00 + ha->port_no + 1;
3a03eb79
AV		 7823 nv->port_name[2] = 0x00;
7824 nv->port_name[3] = 0xe0;
7825 nv->port_name[4] = 0x8b;
7826 nv->port_name[5] = 0x1c;
7827 nv->port_name[6] = 0x55;
7828 nv->port_name[7] = 0x86;
7829 nv->node_name[0] = 0x20;
7830 nv->node_name[1] = 0x00;
7831 nv->node_name[2] = 0x00;
7832 nv->node_name[3] = 0xe0;
7833 nv->node_name[4] = 0x8b;
7834 nv->node_name[5] = 0x1c;
7835 nv->node_name[6] = 0x55;
7836 nv->node_name[7] = 0x86;
ad950360
BVA		 7837 nv->login_retry_count = cpu_to_le16(8);
7838 nv->interrupt_delay_timer = cpu_to_le16(0);
7839 nv->login_timeout = cpu_to_le16(0);
3a03eb79 7840 nv->firmware_options_1 =
ad950360
BVA		 7841 cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
7842 nv->firmware_options_2 = cpu_to_le32(2 << 4);
7843 nv->firmware_options_2 |= cpu_to_le32(BIT_12);
7844 nv->firmware_options_3 = cpu_to_le32(2 << 13);
7845 nv->host_p = cpu_to_le32(BIT_11|BIT_10);
7846 nv->efi_parameters = cpu_to_le32(0);
3a03eb79 7847 nv->reset_delay = 5;
ad950360
BVA		 7848 nv->max_luns_per_target = cpu_to_le16(128);
7849 nv->port_down_retry_count = cpu_to_le16(30);
7850 nv->link_down_timeout = cpu_to_le16(180);
eeebcc92 7851 nv->enode_mac[0] = 0x00;
6246b8a1
GM		 7852 nv->enode_mac[1] = 0xC0;
7853 nv->enode_mac[2] = 0xDD;
3a03eb79
AV		 7854 nv->enode_mac[3] = 0x04;
7855 nv->enode_mac[4] = 0x05;
f73cb695 7856 nv->enode_mac[5] = 0x06 + ha->port_no + 1;
3a03eb79
AV		 7857
7858 rval = 1;
7859 }
7860
9e522cd8
AE		 7861 if (IS_T10_PI_CAPABLE(ha))
7862 nv->frame_payload_size &= ~7;
7863
aa230bc5
AE		 7864 qlt_81xx_config_nvram_stage1(vha, nv);
7865
3a03eb79 7866 /* Reset Initialization control block */
773120e4 7867 memset(icb, 0, ha->init_cb_size);
3a03eb79
AV		 7868
7869 /* Copy 1st segment. */
7870 dptr1 = (uint8_t *)icb;
7871 dptr2 = (uint8_t *)&nv->version;
7872 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
7873 while (cnt--)
7874 *dptr1++ = *dptr2++;
7875
7876 icb->login_retry_count = nv->login_retry_count;
7877
7878 /* Copy 2nd segment. */
7879 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
7880 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
7881 cnt = (uint8_t *)&icb->reserved_5 -
7882 (uint8_t *)&icb->interrupt_delay_timer;
7883 while (cnt--)
7884 *dptr1++ = *dptr2++;
7885
7886 memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac));
7887 /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */
7888 if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) {
69e5f1ea
AV		 7889 icb->enode_mac[0] = 0x00;
7890 icb->enode_mac[1] = 0xC0;
7891 icb->enode_mac[2] = 0xDD;
3a03eb79
AV		 7892 icb->enode_mac[3] = 0x04;
7893 icb->enode_mac[4] = 0x05;
f73cb695 7894 icb->enode_mac[5] = 0x06 + ha->port_no + 1;
3a03eb79
AV		 7895 }
7896
b64b0e8f
AV		 7897 /* Use extended-initialization control block. */
7898 memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb));
7899
3a03eb79
AV		 7900 /*
7901 * Setup driver NVRAM options.
7902 */
7903 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
a9083016 7904 "QLE8XXX");
3a03eb79 7905
aa230bc5
AE		 7906 qlt_81xx_config_nvram_stage2(vha, icb);
7907
3a03eb79 7908 /* Use alternate WWN? */
ad950360 7909 if (nv->host_p & cpu_to_le32(BIT_15)) {
3a03eb79
AV		 7910 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
7911 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
7912 }
7913
7914 /* Prepare nodename */
ad950360 7915 if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) {
3a03eb79
AV		 7916 /*
7917 * Firmware will apply the following mask if the nodename was
7918 * not provided.
7919 */
7920 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
7921 icb->node_name[0] &= 0xF0;
7922 }
7923
7924 /* Set host adapter parameters. */
7925 ha->flags.disable_risc_code_load = 0;
7926 ha->flags.enable_lip_reset = 0;
7927 ha->flags.enable_lip_full_login =
7928 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
7929 ha->flags.enable_target_reset =
7930 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
7931 ha->flags.enable_led_scheme = 0;
7932 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
7933
7934 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
7935 (BIT_6 | BIT_5 | BIT_4)) >> 4;
7936
7937 /* save HBA serial number */
7938 ha->serial0 = icb->port_name[5];
7939 ha->serial1 = icb->port_name[6];
7940 ha->serial2 = icb->port_name[7];
7941 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
7942 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
7943
ad950360 7944 icb->execution_throttle = cpu_to_le16(0xFFFF);
3a03eb79
AV		 7945
7946 ha->retry_count = le16_to_cpu(nv->login_retry_count);
7947
7948 /* Set minimum login_timeout to 4 seconds. */
7949 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
7950 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
7951 if (le16_to_cpu(nv->login_timeout) < 4)
ad950360 7952 nv->login_timeout = cpu_to_le16(4);
3a03eb79 7953 ha->login_timeout = le16_to_cpu(nv->login_timeout);
3a03eb79
AV		 7954
7955 /* Set minimum RATOV to 100 tenths of a second. */
7956 ha->r_a_tov = 100;
7957
7958 ha->loop_reset_delay = nv->reset_delay;
7959
7960 /* Link Down Timeout = 0:
7961 *
7ec0effd 7962 * When Port Down timer expires we will start returning
3a03eb79
AV		 7963 * I/O's to OS with "DID_NO_CONNECT".
7964 *
7965 * Link Down Timeout != 0:
7966 *
7967 * The driver waits for the link to come up after link down
7968 * before returning I/Os to OS with "DID_NO_CONNECT".
7969 */
7970 if (le16_to_cpu(nv->link_down_timeout) == 0) {
7971 ha->loop_down_abort_time =
7972 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
7973 } else {
7974 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
7975 ha->loop_down_abort_time =
7976 (LOOP_DOWN_TIME - ha->link_down_timeout);
7977 }
7978
7979 /* Need enough time to try and get the port back. */
7980 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
7981 if (qlport_down_retry)
7982 ha->port_down_retry_count = qlport_down_retry;
7983
7984 /* Set login_retry_count */
7985 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
7986 if (ha->port_down_retry_count ==
7987 le16_to_cpu(nv->port_down_retry_count) &&
7988 ha->port_down_retry_count > 3)
7989 ha->login_retry_count = ha->port_down_retry_count;
7990 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
7991 ha->login_retry_count = ha->port_down_retry_count;
7992 if (ql2xloginretrycount)
7993 ha->login_retry_count = ql2xloginretrycount;
7994
6246b8a1 7995 /* if not running MSI-X we need handshaking on interrupts */
f73cb695 7996 if (!vha->hw->flags.msix_enabled && (IS_QLA83XX(ha) || IS_QLA27XX(ha)))
ad950360 7997 icb->firmware_options_2 |= cpu_to_le32(BIT_22);
6246b8a1 7998
3a03eb79
AV		 7999 /* Enable ZIO. */
8000 if (!vha->flags.init_done) {
8001 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
8002 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
8003 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
8004 le16_to_cpu(icb->interrupt_delay_timer): 2;
8005 }
ad950360 8006 icb->firmware_options_2 &= cpu_to_le32(
3a03eb79
AV		 8007 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
8008 vha->flags.process_response_queue = 0;
8009 if (ha->zio_mode != QLA_ZIO_DISABLED) {
8010 ha->zio_mode = QLA_ZIO_MODE_6;
8011
7c3df132 8012 ql_log(ql_log_info, vha, 0x0075,
3a03eb79 8013 "ZIO mode %d enabled; timer delay (%d us).\n",
7c3df132
SK		 8014 ha->zio_mode,
8015 ha->zio_timer * 100);
3a03eb79
AV		 8016
8017 icb->firmware_options_2 |= cpu_to_le32(
8018 (uint32_t)ha->zio_mode);
8019 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
8020 vha->flags.process_response_queue = 1;
8021 }
8022
41dc529a
QT		 8023 /* enable RIDA Format2 */
8024 if (qla_tgt_mode_enabled(vha) || qla_dual_mode_enabled(vha))
8025 icb->firmware_options_3 |= BIT_0;
8026
edd05de1
DG		 8027 if (IS_QLA27XX(ha)) {
8028 icb->firmware_options_3 |= BIT_8;
8029 ql_dbg(ql_log_info, vha, 0x0075,
8030 "Enabling direct connection.\n");
8031 }
8032
3a03eb79 8033 if (rval) {
7c3df132
SK		 8034 ql_log(ql_log_warn, vha, 0x0076,
8035 "NVRAM configuration failed.\n");
3a03eb79
AV		 8036 }
8037 return (rval);
8038}
8039
a9083016
GM		 8040int
8041qla82xx_restart_isp(scsi_qla_host_t *vha)
8042{
8043 int status, rval;
a9083016
GM		 8044 struct qla_hw_data *ha = vha->hw;
8045 struct req_que *req = ha->req_q_map[0];
8046 struct rsp_que *rsp = ha->rsp_q_map[0];
8047 struct scsi_qla_host *vp;
feafb7b1 8048 unsigned long flags;
a9083016
GM		 8049
8050 status = qla2x00_init_rings(vha);
8051 if (!status) {
8052 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
8053 ha->flags.chip_reset_done = 1;
8054
8055 status = qla2x00_fw_ready(vha);
8056 if (!status) {
a9083016
GM		 8057 /* Issue a marker after FW becomes ready. */
8058 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
a9083016 8059 vha->flags.online = 1;
7108b76e 8060 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
a9083016
GM		 8061 }
8062
8063 /* if no cable then assume it's good */
8064 if ((vha->device_flags & DFLG_NO_CABLE))
8065 status = 0;
a9083016
GM		 8066 }
8067
8068 if (!status) {
8069 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
8070
8071 if (!atomic_read(&vha->loop_down_timer)) {
8072 /*
8073 * Issue marker command only when we are going
8074 * to start the I/O .
8075 */
8076 vha->marker_needed = 1;
8077 }
8078
a9083016
GM		 8079 ha->isp_ops->enable_intrs(ha);
8080
8081 ha->isp_abort_cnt = 0;
8082 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
8083
53296788 8084 /* Update the firmware version */
3173167f 8085 status = qla82xx_check_md_needed(vha);
53296788 8086
a9083016
GM		 8087 if (ha->fce) {
8088 ha->flags.fce_enabled = 1;
8089 memset(ha->fce, 0,
8090 fce_calc_size(ha->fce_bufs));
8091 rval = qla2x00_enable_fce_trace(vha,
8092 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
8093 &ha->fce_bufs);
8094 if (rval) {
cfb0919c 8095 ql_log(ql_log_warn, vha, 0x8001,
7c3df132
SK		 8096 "Unable to reinitialize FCE (%d).\n",
8097 rval);
a9083016
GM		 8098 ha->flags.fce_enabled = 0;
8099 }
8100 }
8101
8102 if (ha->eft) {
8103 memset(ha->eft, 0, EFT_SIZE);
8104 rval = qla2x00_enable_eft_trace(vha,
8105 ha->eft_dma, EFT_NUM_BUFFERS);
8106 if (rval) {
cfb0919c 8107 ql_log(ql_log_warn, vha, 0x8010,
7c3df132
SK		 8108 "Unable to reinitialize EFT (%d).\n",
8109 rval);
a9083016
GM		 8110 }
8111 }
a9083016
GM		 8112 }
8113
8114 if (!status) {
cfb0919c 8115 ql_dbg(ql_dbg_taskm, vha, 0x8011,
7c3df132 8116 "qla82xx_restart_isp succeeded.\n");
feafb7b1
AE		 8117
8118 spin_lock_irqsave(&ha->vport_slock, flags);
8119 list_for_each_entry(vp, &ha->vp_list, list) {
8120 if (vp->vp_idx) {
8121 atomic_inc(&vp->vref_count);
8122 spin_unlock_irqrestore(&ha->vport_slock, flags);
8123
a9083016 8124 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 8125
8126 spin_lock_irqsave(&ha->vport_slock, flags);
8127 atomic_dec(&vp->vref_count);
8128 }
a9083016 8129 }
feafb7b1
AE		 8130 spin_unlock_irqrestore(&ha->vport_slock, flags);
8131
a9083016 8132 } else {
cfb0919c 8133 ql_log(ql_log_warn, vha, 0x8016,
7c3df132 8134 "qla82xx_restart_isp **** FAILED ****.\n");
a9083016
GM		 8135 }
8136
8137 return status;
8138}
8139
3a03eb79 8140void
ae97c91e 8141qla81xx_update_fw_options(scsi_qla_host_t *vha)
3a03eb79 8142{
ae97c91e
AV		 8143 struct qla_hw_data *ha = vha->hw;
8144
f198cafa
HM		 8145 /* Hold status IOCBs until ABTS response received. */
8146 if (ql2xfwholdabts)
8147 ha->fw_options[3] |= BIT_12;
8148
088d09d4
GM		 8149 /* Set Retry FLOGI in case of P2P connection */
8150 if (ha->operating_mode == P2P) {
8151 ha->fw_options[2] |= BIT_3;
8152 ql_dbg(ql_dbg_disc, vha, 0x2103,
8153 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
8154 __func__, ha->fw_options[2]);
8155 }
8156
41dc529a
QT		 8157 /* Move PUREX, ABTS RX & RIDA to ATIOQ */
8158 if (ql2xmvasynctoatio) {
8159 if (qla_tgt_mode_enabled(vha) ||
8160 qla_dual_mode_enabled(vha))
8161 ha->fw_options[2] |= BIT_11;
8162 else
8163 ha->fw_options[2] &= ~BIT_11;
8164 }
8165
f7e761f5 8166 if (qla_tgt_mode_enabled(vha) ||
2da52737
QT		 8167 qla_dual_mode_enabled(vha)) {
8168 /* FW auto send SCSI status during */
8169 ha->fw_options[1] |= BIT_8;
8170 ha->fw_options[10] |= (u16)SAM_STAT_BUSY << 8;
8171
8172 /* FW perform Exchange validation */
f7e761f5 8173 ha->fw_options[2] |= BIT_4;
2da52737
QT		 8174 } else {
8175 ha->fw_options[1] &= ~BIT_8;
8176 ha->fw_options[10] &= 0x00ff;
8177
f7e761f5 8178 ha->fw_options[2] &= ~BIT_4;
2da52737 8179 }
f7e761f5 8180
41dc529a
QT		 8181 if (ql2xetsenable) {
8182 /* Enable ETS Burst. */
8183 memset(ha->fw_options, 0, sizeof(ha->fw_options));
8184 ha->fw_options[2] |= BIT_9;
8185 }
8186
83548fe2
QT		 8187 ql_dbg(ql_dbg_init, vha, 0x00e9,
8188 "%s, add FW options 1-3 = 0x%04x 0x%04x 0x%04x mode %x\n",
8189 __func__, ha->fw_options[1], ha->fw_options[2],
8190 ha->fw_options[3], vha->host->active_mode);
ae97c91e 8191
ae97c91e 8192 qla2x00_set_fw_options(vha, ha->fw_options);
3a03eb79 8193}
09ff701a
SR		 8194
8195/*
8196 * qla24xx_get_fcp_prio
8197 * Gets the fcp cmd priority value for the logged in port.
8198 * Looks for a match of the port descriptors within
8199 * each of the fcp prio config entries. If a match is found,
8200 * the tag (priority) value is returned.
8201 *
8202 * Input:
21090cbe 8203 * vha = scsi host structure pointer.
09ff701a
SR		 8204 * fcport = port structure pointer.
8205 *
8206 * Return:
6c452a45 8207 * non-zero (if found)
f28a0a96 8208 * -1 (if not found)
09ff701a
SR		 8209 *
8210 * Context:
8211 * Kernel context
8212 */
f28a0a96 8213static int
09ff701a
SR		 8214qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
8215{
8216 int i, entries;
8217 uint8_t pid_match, wwn_match;
f28a0a96 8218 int priority;
09ff701a
SR		 8219 uint32_t pid1, pid2;
8220 uint64_t wwn1, wwn2;
8221 struct qla_fcp_prio_entry *pri_entry;
8222 struct qla_hw_data *ha = vha->hw;
8223
8224 if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled)
f28a0a96 8225 return -1;
09ff701a 8226
f28a0a96 8227 priority = -1;
09ff701a
SR		 8228 entries = ha->fcp_prio_cfg->num_entries;
8229 pri_entry = &ha->fcp_prio_cfg->entry[0];
8230
8231 for (i = 0; i < entries; i++) {
8232 pid_match = wwn_match = 0;
8233
8234 if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) {
8235 pri_entry++;
8236 continue;
8237 }
8238
8239 /* check source pid for a match */
8240 if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) {
8241 pid1 = pri_entry->src_pid & INVALID_PORT_ID;
8242 pid2 = vha->d_id.b24 & INVALID_PORT_ID;
8243 if (pid1 == INVALID_PORT_ID)
8244 pid_match++;
8245 else if (pid1 == pid2)
8246 pid_match++;
8247 }
8248
8249 /* check destination pid for a match */
8250 if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) {
8251 pid1 = pri_entry->dst_pid & INVALID_PORT_ID;
8252 pid2 = fcport->d_id.b24 & INVALID_PORT_ID;
8253 if (pid1 == INVALID_PORT_ID)
8254 pid_match++;
8255 else if (pid1 == pid2)
8256 pid_match++;
8257 }
8258
8259 /* check source WWN for a match */
8260 if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) {
8261 wwn1 = wwn_to_u64(vha->port_name);
8262 wwn2 = wwn_to_u64(pri_entry->src_wwpn);
8263 if (wwn2 == (uint64_t)-1)
8264 wwn_match++;
8265 else if (wwn1 == wwn2)
8266 wwn_match++;
8267 }
8268
8269 /* check destination WWN for a match */
8270 if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) {
8271 wwn1 = wwn_to_u64(fcport->port_name);
8272 wwn2 = wwn_to_u64(pri_entry->dst_wwpn);
8273 if (wwn2 == (uint64_t)-1)
8274 wwn_match++;
8275 else if (wwn1 == wwn2)
8276 wwn_match++;
8277 }
8278
8279 if (pid_match == 2 || wwn_match == 2) {
8280 /* Found a matching entry */
8281 if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID)
8282 priority = pri_entry->tag;
8283 break;
8284 }
8285
8286 pri_entry++;
8287 }
8288
8289 return priority;
8290}
8291
8292/*
8293 * qla24xx_update_fcport_fcp_prio
8294 * Activates fcp priority for the logged in fc port
8295 *
8296 * Input:
21090cbe 8297 * vha = scsi host structure pointer.
09ff701a
SR		 8298 * fcp = port structure pointer.
8299 *
8300 * Return:
8301 * QLA_SUCCESS or QLA_FUNCTION_FAILED
8302 *
8303 * Context:
8304 * Kernel context.
8305 */
8306int
21090cbe 8307qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
09ff701a
SR		 8308{
8309 int ret;
f28a0a96 8310 int priority;
09ff701a
SR		 8311 uint16_t mb[5];
8312
21090cbe
MI		 8313 if (fcport->port_type != FCT_TARGET ||
8314 fcport->loop_id == FC_NO_LOOP_ID)
09ff701a
SR		 8315 return QLA_FUNCTION_FAILED;
8316
21090cbe 8317 priority = qla24xx_get_fcp_prio(vha, fcport);
f28a0a96
AV		 8318 if (priority < 0)
8319 return QLA_FUNCTION_FAILED;
8320
7ec0effd 8321 if (IS_P3P_TYPE(vha->hw)) {
a00f6296
SK		 8322 fcport->fcp_prio = priority & 0xf;
8323 return QLA_SUCCESS;
8324 }
8325
21090cbe 8326 ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb);
cfb0919c
CD		 8327 if (ret == QLA_SUCCESS) {
8328 if (fcport->fcp_prio != priority)
8329 ql_dbg(ql_dbg_user, vha, 0x709e,
8330 "Updated FCP_CMND priority - value=%d loop_id=%d "
8331 "port_id=%02x%02x%02x.\n", priority,
8332 fcport->loop_id, fcport->d_id.b.domain,
8333 fcport->d_id.b.area, fcport->d_id.b.al_pa);
a00f6296 8334 fcport->fcp_prio = priority & 0xf;
cfb0919c 8335 } else
7c3df132 8336 ql_dbg(ql_dbg_user, vha, 0x704f,
cfb0919c
CD		 8337 "Unable to update FCP_CMND priority - ret=0x%x for "
8338 "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id,
8339 fcport->d_id.b.domain, fcport->d_id.b.area,
8340 fcport->d_id.b.al_pa);
09ff701a
SR		 8341 return ret;
8342}
8343
8344/*
8345 * qla24xx_update_all_fcp_prio
8346 * Activates fcp priority for all the logged in ports
8347 *
8348 * Input:
8349 * ha = adapter block pointer.
8350 *
8351 * Return:
8352 * QLA_SUCCESS or QLA_FUNCTION_FAILED
8353 *
8354 * Context:
8355 * Kernel context.
8356 */
8357int
8358qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha)
8359{
8360 int ret;
8361 fc_port_t *fcport;
8362
8363 ret = QLA_FUNCTION_FAILED;
8364 /* We need to set priority for all logged in ports */
8365 list_for_each_entry(fcport, &vha->vp_fcports, list)
8366 ret = qla24xx_update_fcport_fcp_prio(vha, fcport);
8367
8368 return ret;
8369}
d7459527 8370
82de802a
QT		 8371struct qla_qpair *qla2xxx_create_qpair(struct scsi_qla_host *vha, int qos,
8372 int vp_idx, bool startqp)
d7459527
MH		 8373{
8374 int rsp_id = 0;
8375 int req_id = 0;
8376 int i;
8377 struct qla_hw_data *ha = vha->hw;
8378 uint16_t qpair_id = 0;
8379 struct qla_qpair *qpair = NULL;
8380 struct qla_msix_entry *msix;
8381
8382 if (!(ha->fw_attributes & BIT_6) || !ha->flags.msix_enabled) {
8383 ql_log(ql_log_warn, vha, 0x00181,
8384 "FW/Driver is not multi-queue capable.\n");
8385 return NULL;
8386 }
8387
c38d1baf 8388 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 8389 qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
8390 if (qpair == NULL) {
8391 ql_log(ql_log_warn, vha, 0x0182,
8392 "Failed to allocate memory for queue pair.\n");
8393 return NULL;
8394 }
8395 memset(qpair, 0, sizeof(struct qla_qpair));
8396
8397 qpair->hw = vha->hw;
25ff6af1 8398 qpair->vha = vha;
82de802a
QT		 8399 qpair->qp_lock_ptr = &qpair->qp_lock;
8400 spin_lock_init(&qpair->qp_lock);
af7bb382 8401 qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
d7459527
MH		 8402
8403 /* Assign available que pair id */
8404 mutex_lock(&ha->mq_lock);
8405 qpair_id = find_first_zero_bit(ha->qpair_qid_map, ha->max_qpairs);
b95b9452 8406 if (ha->num_qpairs >= ha->max_qpairs) {
d7459527
MH		 8407 mutex_unlock(&ha->mq_lock);
8408 ql_log(ql_log_warn, vha, 0x0183,
8409 "No resources to create additional q pair.\n");
8410 goto fail_qid_map;
8411 }
b95b9452 8412 ha->num_qpairs++;
d7459527
MH		 8413 set_bit(qpair_id, ha->qpair_qid_map);
8414 ha->queue_pair_map[qpair_id] = qpair;
8415 qpair->id = qpair_id;
8416 qpair->vp_idx = vp_idx;
e6373f33 8417 qpair->fw_started = ha->flags.fw_started;
e326d22a 8418 INIT_LIST_HEAD(&qpair->hints_list);
7c3f8fd1
QT		 8419 qpair->chip_reset = ha->base_qpair->chip_reset;
8420 qpair->enable_class_2 = ha->base_qpair->enable_class_2;
8421 qpair->enable_explicit_conf =
8422 ha->base_qpair->enable_explicit_conf;
d7459527
MH		 8423
8424 for (i = 0; i < ha->msix_count; i++) {
093df737 8425 msix = &ha->msix_entries[i];
d7459527
MH		 8426 if (msix->in_use)
8427 continue;
8428 qpair->msix = msix;
83548fe2 8429 ql_dbg(ql_dbg_multiq, vha, 0xc00f,
d7459527
MH		 8430 "Vector %x selected for qpair\n", msix->vector);
8431 break;
8432 }
8433 if (!qpair->msix) {
8434 ql_log(ql_log_warn, vha, 0x0184,
8435 "Out of MSI-X vectors!.\n");
8436 goto fail_msix;
8437 }
8438
8439 qpair->msix->in_use = 1;
8440 list_add_tail(&qpair->qp_list_elem, &vha->qp_list);
8abfa9e2
QT		 8441 qpair->pdev = ha->pdev;
8442 if (IS_QLA27XX(ha) || IS_QLA83XX(ha))
8443 qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
d7459527
MH		 8444
8445 mutex_unlock(&ha->mq_lock);
8446
8447 /* Create response queue first */
82de802a 8448 rsp_id = qla25xx_create_rsp_que(ha, 0, 0, 0, qpair, startqp);
d7459527
MH		 8449 if (!rsp_id) {
8450 ql_log(ql_log_warn, vha, 0x0185,
8451 "Failed to create response queue.\n");
8452 goto fail_rsp;
8453 }
8454
8455 qpair->rsp = ha->rsp_q_map[rsp_id];
8456
8457 /* Create request queue */
82de802a
QT		 8458 req_id = qla25xx_create_req_que(ha, 0, vp_idx, 0, rsp_id, qos,
8459 startqp);
d7459527
MH		 8460 if (!req_id) {
8461 ql_log(ql_log_warn, vha, 0x0186,
8462 "Failed to create request queue.\n");
8463 goto fail_req;
8464 }
8465
8466 qpair->req = ha->req_q_map[req_id];
8467 qpair->rsp->req = qpair->req;
82de802a 8468 qpair->rsp->qpair = qpair;
e326d22a
QT		 8469 /* init qpair to this cpu. Will adjust at run time. */
8470 qla_cpu_update(qpair, smp_processor_id());
d7459527
MH		 8471
8472 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
8473 if (ha->fw_attributes & BIT_4)
8474 qpair->difdix_supported = 1;
8475 }
8476
8477 qpair->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
8478 if (!qpair->srb_mempool) {
83548fe2 8479 ql_log(ql_log_warn, vha, 0xd036,
d7459527
MH		 8480 "Failed to create srb mempool for qpair %d\n",
8481 qpair->id);
8482 goto fail_mempool;
8483 }
8484
8485 /* Mark as online */
8486 qpair->online = 1;
8487
8488 if (!vha->flags.qpairs_available)
8489 vha->flags.qpairs_available = 1;
8490
8491 ql_dbg(ql_dbg_multiq, vha, 0xc00d,
8492 "Request/Response queue pair created, id %d\n",
8493 qpair->id);
8494 ql_dbg(ql_dbg_init, vha, 0x0187,
8495 "Request/Response queue pair created, id %d\n",
8496 qpair->id);
8497 }
8498 return qpair;
8499
8500fail_mempool:
8501fail_req:
8502 qla25xx_delete_rsp_que(vha, qpair->rsp);
8503fail_rsp:
8504 mutex_lock(&ha->mq_lock);
8505 qpair->msix->in_use = 0;
8506 list_del(&qpair->qp_list_elem);
8507 if (list_empty(&vha->qp_list))
8508 vha->flags.qpairs_available = 0;
8509fail_msix:
8510 ha->queue_pair_map[qpair_id] = NULL;
8511 clear_bit(qpair_id, ha->qpair_qid_map);
b95b9452 8512 ha->num_qpairs--;
d7459527
MH		 8513 mutex_unlock(&ha->mq_lock);
8514fail_qid_map:
8515 kfree(qpair);
8516 return NULL;
8517}
8518
8519int qla2xxx_delete_qpair(struct scsi_qla_host *vha, struct qla_qpair *qpair)
8520{
d65237c7 8521 int ret = QLA_FUNCTION_FAILED;
d7459527
MH		 8522 struct qla_hw_data *ha = qpair->hw;
8523
8524 qpair->delete_in_progress = 1;
8525 while (atomic_read(&qpair->ref_count))
8526 msleep(500);
8527
8528 ret = qla25xx_delete_req_que(vha, qpair->req);
8529 if (ret != QLA_SUCCESS)
8530 goto fail;
7867b98d 8531
d7459527
MH		 8532 ret = qla25xx_delete_rsp_que(vha, qpair->rsp);
8533 if (ret != QLA_SUCCESS)
8534 goto fail;
8535
8536 mutex_lock(&ha->mq_lock);
8537 ha->queue_pair_map[qpair->id] = NULL;
8538 clear_bit(qpair->id, ha->qpair_qid_map);
b95b9452 8539 ha->num_qpairs--;
d7459527 8540 list_del(&qpair->qp_list_elem);
d65237c7 8541 if (list_empty(&vha->qp_list)) {
d7459527 8542 vha->flags.qpairs_available = 0;
d65237c7
SC		 8543 vha->flags.qpairs_req_created = 0;
8544 vha->flags.qpairs_rsp_created = 0;
8545 }
d7459527
MH		 8546 mempool_destroy(qpair->srb_mempool);
8547 kfree(qpair);
8548 mutex_unlock(&ha->mq_lock);
8549
8550 return QLA_SUCCESS;
8551fail:
8552 return ret;
8553}
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