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scsi: qla2xxx: Retain loop test for fwdump length exceeding buffer length
[mirror_ubuntu-artful-kernel.git] / drivers / scsi / qla2xxx / qla_init.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
73208dfd 8#include "qla_gbl.h"
1da177e4
LT		 9
10#include <linux/delay.h>
5a0e3ad6 11#include <linux/slab.h>
0107109e 12#include <linux/vmalloc.h>
1da177e4
LT		 13
14#include "qla_devtbl.h"
15
4e08df3f
DM		 16#ifdef CONFIG_SPARC
17#include <asm/prom.h>
4e08df3f
DM		 18#endif
19
2d70c103
NB		 20#include <target/target_core_base.h>
21#include "qla_target.h"
22
1da177e4
LT		 23/*
24* QLogic ISP2x00 Hardware Support Function Prototypes.
25*/
1da177e4 26static int qla2x00_isp_firmware(scsi_qla_host_t *);
1da177e4 27static int qla2x00_setup_chip(scsi_qla_host_t *);
1da177e4
LT		 28static int qla2x00_fw_ready(scsi_qla_host_t *);
29static int qla2x00_configure_hba(scsi_qla_host_t *);
1da177e4
LT		 30static int qla2x00_configure_loop(scsi_qla_host_t *);
31static int qla2x00_configure_local_loop(scsi_qla_host_t *);
1da177e4 32static int qla2x00_configure_fabric(scsi_qla_host_t *);
726b8548 33static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *);
1da177e4 34static int qla2x00_restart_isp(scsi_qla_host_t *);
1da177e4 35
4d4df193
HK		 36static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *);
37static int qla84xx_init_chip(scsi_qla_host_t *);
73208dfd 38static int qla25xx_init_queues(struct qla_hw_data *);
726b8548
QT		 39static int qla24xx_post_gpdb_work(struct scsi_qla_host *, fc_port_t *, u8);
40static void qla24xx_handle_plogi_done_event(struct scsi_qla_host *,
41 struct event_arg *);
4d4df193 42
ac280b67
AV		 43/* SRB Extensions ---------------------------------------------------------- */
44
9ba56b95
GM		 45void
46qla2x00_sp_timeout(unsigned long __data)
ac280b67
AV		 47{
48 srb_t *sp = (srb_t *)__data;
4916392b 49 struct srb_iocb *iocb;
25ff6af1 50 scsi_qla_host_t *vha = sp->vha;
ac280b67
AV		 51 struct req_que *req;
52 unsigned long flags;
53
25ff6af1
JC		 54 spin_lock_irqsave(&vha->hw->hardware_lock, flags);
55 req = vha->hw->req_q_map[0];
ac280b67 56 req->outstanding_cmds[sp->handle] = NULL;
9ba56b95 57 iocb = &sp->u.iocb_cmd;
4916392b 58 iocb->timeout(sp);
25ff6af1
JC		 59 sp->free(sp);
60 spin_unlock_irqrestore(&vha->hw->hardware_lock, flags);
ac280b67
AV		 61}
62
9ba56b95 63void
25ff6af1 64qla2x00_sp_free(void *ptr)
ac280b67 65{
25ff6af1 66 srb_t *sp = ptr;
9ba56b95 67 struct srb_iocb *iocb = &sp->u.iocb_cmd;
ac280b67 68
4d97cc53 69 del_timer(&iocb->timer);
25ff6af1 70 qla2x00_rel_sp(sp);
ac280b67
AV		 71}
72
ac280b67
AV		 73/* Asynchronous Login/Logout Routines -------------------------------------- */
74
a9b6f722 75unsigned long
5b91490e
AV		 76qla2x00_get_async_timeout(struct scsi_qla_host *vha)
77{
78 unsigned long tmo;
79 struct qla_hw_data *ha = vha->hw;
80
81 /* Firmware should use switch negotiated r_a_tov for timeout. */
82 tmo = ha->r_a_tov / 10 * 2;
8ae6d9c7
GM		 83 if (IS_QLAFX00(ha)) {
84 tmo = FX00_DEF_RATOV * 2;
85 } else if (!IS_FWI2_CAPABLE(ha)) {
5b91490e
AV		 86 /*
87 * Except for earlier ISPs where the timeout is seeded from the
88 * initialization control block.
89 */
90 tmo = ha->login_timeout;
91 }
92 return tmo;
93}
ac280b67 94
726b8548 95void
9ba56b95 96qla2x00_async_iocb_timeout(void *data)
ac280b67 97{
25ff6af1 98 srb_t *sp = data;
ac280b67 99 fc_port_t *fcport = sp->fcport;
726b8548
QT		 100 struct srb_iocb *lio = &sp->u.iocb_cmd;
101 struct event_arg ea;
ac280b67 102
7c3df132 103 ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
726b8548
QT		 104 "Async-%s timeout - hdl=%x portid=%06x %8phC.\n",
105 sp->name, sp->handle, fcport->d_id.b24, fcport->port_name);
ac280b67 106
5ff1d584 107 fcport->flags &= ~FCF_ASYNC_SENT;
726b8548
QT		 108
109 switch (sp->type) {
110 case SRB_LOGIN_CMD:
6ac52608
AV		 111 /* Retry as needed. */
112 lio->u.logio.data[0] = MBS_COMMAND_ERROR;
113 lio->u.logio.data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
114 QLA_LOGIO_LOGIN_RETRIED : 0;
726b8548
QT		 115 memset(&ea, 0, sizeof(ea));
116 ea.event = FCME_PLOGI_DONE;
117 ea.fcport = sp->fcport;
118 ea.data[0] = lio->u.logio.data[0];
119 ea.data[1] = lio->u.logio.data[1];
120 ea.sp = sp;
121 qla24xx_handle_plogi_done_event(fcport->vha, &ea);
122 break;
123 case SRB_LOGOUT_CMD:
a6ca8878 124 qlt_logo_completion_handler(fcport, QLA_FUNCTION_TIMEOUT);
726b8548
QT		 125 break;
126 case SRB_CT_PTHRU_CMD:
127 case SRB_MB_IOCB:
128 case SRB_NACK_PLOGI:
129 case SRB_NACK_PRLI:
130 case SRB_NACK_LOGO:
25ff6af1 131 sp->done(sp, QLA_FUNCTION_TIMEOUT);
726b8548 132 break;
6ac52608 133 }
ac280b67
AV		 134}
135
99b0bec7 136static void
25ff6af1 137qla2x00_async_login_sp_done(void *ptr, int res)
99b0bec7 138{
25ff6af1
JC		 139 srb_t *sp = ptr;
140 struct scsi_qla_host *vha = sp->vha;
9ba56b95 141 struct srb_iocb *lio = &sp->u.iocb_cmd;
726b8548 142 struct event_arg ea;
9ba56b95 143
726b8548 144 ql_dbg(ql_dbg_disc, vha, 0xffff,
25ff6af1 145 "%s %8phC res %d \n", __func__, sp->fcport->port_name, res);
726b8548
QT		 146
147 sp->fcport->flags &= ~FCF_ASYNC_SENT;
148 if (!test_bit(UNLOADING, &vha->dpc_flags)) {
149 memset(&ea, 0, sizeof(ea));
150 ea.event = FCME_PLOGI_DONE;
151 ea.fcport = sp->fcport;
152 ea.data[0] = lio->u.logio.data[0];
153 ea.data[1] = lio->u.logio.data[1];
154 ea.iop[0] = lio->u.logio.iop[0];
155 ea.iop[1] = lio->u.logio.iop[1];
156 ea.sp = sp;
157 qla2x00_fcport_event_handler(vha, &ea);
158 }
9ba56b95 159
25ff6af1 160 sp->free(sp);
99b0bec7
AV		 161}
162
ac280b67
AV		 163int
164qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport,
165 uint16_t *data)
166{
ac280b67 167 srb_t *sp;
4916392b 168 struct srb_iocb *lio;
726b8548
QT		 169 int rval = QLA_FUNCTION_FAILED;
170
171 if (!vha->flags.online)
172 goto done;
173
174 if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) ||
175 (fcport->fw_login_state == DSC_LS_PLOGI_COMP) ||
176 (fcport->fw_login_state == DSC_LS_PRLI_PEND))
177 goto done;
ac280b67 178
9ba56b95 179 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 180 if (!sp)
181 goto done;
182
726b8548
QT		 183 fcport->flags |= FCF_ASYNC_SENT;
184 fcport->logout_completed = 0;
185
9ba56b95
GM		 186 sp->type = SRB_LOGIN_CMD;
187 sp->name = "login";
188 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
189
190 lio = &sp->u.iocb_cmd;
3822263e 191 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 192 sp->done = qla2x00_async_login_sp_done;
4916392b 193 lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI;
ac280b67 194 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 195 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
ac280b67 196 rval = qla2x00_start_sp(sp);
080c9517
CD		 197 if (rval != QLA_SUCCESS) {
198 fcport->flags &= ~FCF_ASYNC_SENT;
199 fcport->flags |= FCF_LOGIN_NEEDED;
200 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
ac280b67 201 goto done_free_sp;
080c9517 202 }
ac280b67 203
7c3df132 204 ql_dbg(ql_dbg_disc, vha, 0x2072,
726b8548
QT		 205 "Async-login - %8phC hdl=%x, loopid=%x portid=%02x%02x%02x "
206 "retries=%d.\n", fcport->port_name, sp->handle, fcport->loop_id,
cfb0919c
CD		 207 fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
208 fcport->login_retry);
ac280b67
AV		 209 return rval;
210
211done_free_sp:
25ff6af1 212 sp->free(sp);
ac280b67 213done:
726b8548 214 fcport->flags &= ~FCF_ASYNC_SENT;
ac280b67
AV		 215 return rval;
216}
217
99b0bec7 218static void
25ff6af1 219qla2x00_async_logout_sp_done(void *ptr, int res)
99b0bec7 220{
25ff6af1 221 srb_t *sp = ptr;
9ba56b95 222 struct srb_iocb *lio = &sp->u.iocb_cmd;
9ba56b95 223
726b8548 224 sp->fcport->flags &= ~FCF_ASYNC_SENT;
25ff6af1
JC		 225 if (!test_bit(UNLOADING, &sp->vha->dpc_flags))
226 qla2x00_post_async_logout_done_work(sp->vha, sp->fcport,
9ba56b95 227 lio->u.logio.data);
25ff6af1 228 sp->free(sp);
99b0bec7
AV		 229}
230
ac280b67
AV		 231int
232qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport)
233{
ac280b67 234 srb_t *sp;
4916392b 235 struct srb_iocb *lio;
ac280b67
AV		 236 int rval;
237
238 rval = QLA_FUNCTION_FAILED;
726b8548 239 fcport->flags |= FCF_ASYNC_SENT;
9ba56b95 240 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 241 if (!sp)
242 goto done;
243
9ba56b95
GM		 244 sp->type = SRB_LOGOUT_CMD;
245 sp->name = "logout";
246 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
247
248 lio = &sp->u.iocb_cmd;
3822263e 249 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 250 sp->done = qla2x00_async_logout_sp_done;
ac280b67
AV		 251 rval = qla2x00_start_sp(sp);
252 if (rval != QLA_SUCCESS)
253 goto done_free_sp;
254
7c3df132 255 ql_dbg(ql_dbg_disc, vha, 0x2070,
726b8548 256 "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x %8phC.\n",
cfb0919c 257 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
726b8548
QT		 258 fcport->d_id.b.area, fcport->d_id.b.al_pa,
259 fcport->port_name);
ac280b67
AV		 260 return rval;
261
262done_free_sp:
25ff6af1 263 sp->free(sp);
ac280b67 264done:
726b8548 265 fcport->flags &= ~FCF_ASYNC_SENT;
ac280b67
AV		 266 return rval;
267}
268
5ff1d584 269static void
25ff6af1 270qla2x00_async_adisc_sp_done(void *ptr, int res)
5ff1d584 271{
25ff6af1
JC		 272 srb_t *sp = ptr;
273 struct scsi_qla_host *vha = sp->vha;
9ba56b95 274 struct srb_iocb *lio = &sp->u.iocb_cmd;
9ba56b95
GM		 275
276 if (!test_bit(UNLOADING, &vha->dpc_flags))
25ff6af1 277 qla2x00_post_async_adisc_done_work(sp->vha, sp->fcport,
9ba56b95 278 lio->u.logio.data);
25ff6af1 279 sp->free(sp);
5ff1d584
AV		 280}
281
282int
283qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport,
284 uint16_t *data)
285{
5ff1d584 286 srb_t *sp;
4916392b 287 struct srb_iocb *lio;
5ff1d584
AV		 288 int rval;
289
290 rval = QLA_FUNCTION_FAILED;
726b8548 291 fcport->flags |= FCF_ASYNC_SENT;
9ba56b95 292 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
5ff1d584
AV		 293 if (!sp)
294 goto done;
295
9ba56b95
GM		 296 sp->type = SRB_ADISC_CMD;
297 sp->name = "adisc";
298 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
299
300 lio = &sp->u.iocb_cmd;
3822263e 301 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 302 sp->done = qla2x00_async_adisc_sp_done;
5ff1d584 303 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 304 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
5ff1d584
AV		 305 rval = qla2x00_start_sp(sp);
306 if (rval != QLA_SUCCESS)
307 goto done_free_sp;
308
7c3df132 309 ql_dbg(ql_dbg_disc, vha, 0x206f,
cfb0919c
CD		 310 "Async-adisc - hdl=%x loopid=%x portid=%02x%02x%02x.\n",
311 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
312 fcport->d_id.b.area, fcport->d_id.b.al_pa);
5ff1d584
AV		 313 return rval;
314
315done_free_sp:
25ff6af1 316 sp->free(sp);
5ff1d584 317done:
726b8548
QT		 318 fcport->flags &= ~FCF_ASYNC_SENT;
319 return rval;
320}
321
322static void qla24xx_handle_gnl_done_event(scsi_qla_host_t *vha,
323 struct event_arg *ea)
324{
325 fc_port_t *fcport, *conflict_fcport;
326 struct get_name_list_extended *e;
327 u16 i, n, found = 0, loop_id;
328 port_id_t id;
329 u64 wwn;
330 u8 opt = 0;
331
332 fcport = ea->fcport;
333
334 if (ea->rc) { /* rval */
335 if (fcport->login_retry == 0) {
336 fcport->login_retry = vha->hw->login_retry_count;
337 ql_dbg(ql_dbg_disc, vha, 0xffff,
338 "GNL failed Port login retry %8phN, retry cnt=%d.\n",
339 fcport->port_name, fcport->login_retry);
340 }
341 return;
342 }
343
344 if (fcport->last_rscn_gen != fcport->rscn_gen) {
345 ql_dbg(ql_dbg_disc, vha, 0xffff,
346 "%s %8phC rscn gen changed rscn %d|%d \n",
347 __func__, fcport->port_name,
348 fcport->last_rscn_gen, fcport->rscn_gen);
349 qla24xx_post_gidpn_work(vha, fcport);
350 return;
351 } else if (fcport->last_login_gen != fcport->login_gen) {
352 ql_dbg(ql_dbg_disc, vha, 0xffff,
353 "%s %8phC login gen changed login %d|%d \n",
354 __func__, fcport->port_name,
355 fcport->last_login_gen, fcport->login_gen);
356 return;
357 }
358
359 n = ea->data[0] / sizeof(struct get_name_list_extended);
360
361 ql_dbg(ql_dbg_disc, vha, 0xffff,
362 "%s %d %8phC n %d %02x%02x%02x lid %d \n",
363 __func__, __LINE__, fcport->port_name, n,
364 fcport->d_id.b.domain, fcport->d_id.b.area,
365 fcport->d_id.b.al_pa, fcport->loop_id);
366
367 for (i = 0; i < n; i++) {
368 e = &vha->gnl.l[i];
369 wwn = wwn_to_u64(e->port_name);
370
371 if (memcmp((u8 *)&wwn, fcport->port_name, WWN_SIZE))
372 continue;
373
374 found = 1;
375 id.b.domain = e->port_id[2];
376 id.b.area = e->port_id[1];
377 id.b.al_pa = e->port_id[0];
378 id.b.rsvd_1 = 0;
379
380 loop_id = le16_to_cpu(e->nport_handle);
381 loop_id = (loop_id & 0x7fff);
382
383 ql_dbg(ql_dbg_disc, vha, 0xffff,
384 "%s found %8phC CLS [%d|%d] ID[%02x%02x%02x|%02x%02x%02x] lid[%d|%d]\n",
385 __func__, fcport->port_name,
386 e->current_login_state, fcport->fw_login_state,
387 id.b.domain, id.b.area, id.b.al_pa,
388 fcport->d_id.b.domain, fcport->d_id.b.area,
389 fcport->d_id.b.al_pa, loop_id, fcport->loop_id);
390
391 if ((id.b24 != fcport->d_id.b24) ||
392 ((fcport->loop_id != FC_NO_LOOP_ID) &&
393 (fcport->loop_id != loop_id))) {
394 ql_dbg(ql_dbg_disc, vha, 0xffff,
395 "%s %d %8phC post del sess\n",
396 __func__, __LINE__, fcport->port_name);
397 qlt_schedule_sess_for_deletion(fcport, 1);
398 return;
399 }
400
401 fcport->loop_id = loop_id;
402
403 wwn = wwn_to_u64(fcport->port_name);
404 qlt_find_sess_invalidate_other(vha, wwn,
405 id, loop_id, &conflict_fcport);
406
407 if (conflict_fcport) {
408 /*
409 * Another share fcport share the same loop_id &
410 * nport id. Conflict fcport needs to finish
411 * cleanup before this fcport can proceed to login.
412 */
413 conflict_fcport->conflict = fcport;
414 fcport->login_pause = 1;
415 }
416
417 switch (e->current_login_state) {
418 case DSC_LS_PRLI_COMP:
419 ql_dbg(ql_dbg_disc, vha, 0xffff,
420 "%s %d %8phC post gpdb\n",
421 __func__, __LINE__, fcport->port_name);
422 opt = PDO_FORCE_ADISC;
423 qla24xx_post_gpdb_work(vha, fcport, opt);
424 break;
425
426 case DSC_LS_PORT_UNAVAIL:
427 default:
428 if (fcport->loop_id == FC_NO_LOOP_ID) {
429 qla2x00_find_new_loop_id(vha, fcport);
430 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL;
431 }
432 ql_dbg(ql_dbg_disc, vha, 0xffff,
433 "%s %d %8phC \n",
434 __func__, __LINE__, fcport->port_name);
435 qla24xx_fcport_handle_login(vha, fcport);
436 break;
437 }
438 }
439
440 if (!found) {
441 /* fw has no record of this port */
442 if (fcport->loop_id == FC_NO_LOOP_ID) {
443 qla2x00_find_new_loop_id(vha, fcport);
444 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL;
445 } else {
446 for (i = 0; i < n; i++) {
447 e = &vha->gnl.l[i];
448 id.b.domain = e->port_id[0];
449 id.b.area = e->port_id[1];
450 id.b.al_pa = e->port_id[2];
451 id.b.rsvd_1 = 0;
452 loop_id = le16_to_cpu(e->nport_handle);
453
454 if (fcport->d_id.b24 == id.b24) {
455 conflict_fcport =
456 qla2x00_find_fcport_by_wwpn(vha,
457 e->port_name, 0);
458
459 ql_dbg(ql_dbg_disc, vha, 0xffff,
460 "%s %d %8phC post del sess\n",
461 __func__, __LINE__,
462 conflict_fcport->port_name);
463 qlt_schedule_sess_for_deletion
464 (conflict_fcport, 1);
465 }
466
467 if (fcport->loop_id == loop_id) {
468 /* FW already picked this loop id for another fcport */
469 qla2x00_find_new_loop_id(vha, fcport);
470 }
471 }
472 }
473 qla24xx_fcport_handle_login(vha, fcport);
474 }
475} /* gnl_event */
476
477static void
25ff6af1 478qla24xx_async_gnl_sp_done(void *s, int res)
726b8548 479{
25ff6af1
JC		 480 struct srb *sp = s;
481 struct scsi_qla_host *vha = sp->vha;
726b8548
QT		 482 unsigned long flags;
483 struct fc_port *fcport = NULL, *tf;
484 u16 i, n = 0, loop_id;
485 struct event_arg ea;
486 struct get_name_list_extended *e;
487 u64 wwn;
488 struct list_head h;
489
490 ql_dbg(ql_dbg_disc, vha, 0xffff,
491 "Async done-%s res %x mb[1]=%x mb[2]=%x \n",
492 sp->name, res, sp->u.iocb_cmd.u.mbx.in_mb[1],
493 sp->u.iocb_cmd.u.mbx.in_mb[2]);
494
495 memset(&ea, 0, sizeof(ea));
496 ea.sp = sp;
497 ea.rc = res;
498 ea.event = FCME_GNL_DONE;
499
500 if (sp->u.iocb_cmd.u.mbx.in_mb[1] >=
501 sizeof(struct get_name_list_extended)) {
502 n = sp->u.iocb_cmd.u.mbx.in_mb[1] /
503 sizeof(struct get_name_list_extended);
504 ea.data[0] = sp->u.iocb_cmd.u.mbx.in_mb[1]; /* amnt xfered */
505 }
506
507 for (i = 0; i < n; i++) {
508 e = &vha->gnl.l[i];
509 loop_id = le16_to_cpu(e->nport_handle);
510 /* mask out reserve bit */
511 loop_id = (loop_id & 0x7fff);
512 set_bit(loop_id, vha->hw->loop_id_map);
513 wwn = wwn_to_u64(e->port_name);
514
515 ql_dbg(ql_dbg_disc + ql_dbg_verbose, vha, 0xffff,
516 "%s %8phC %02x:%02x:%02x state %d/%d lid %x \n",
517 __func__, (void *)&wwn, e->port_id[2], e->port_id[1],
518 e->port_id[0], e->current_login_state, e->last_login_state,
519 (loop_id & 0x7fff));
520 }
521
522 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
523 vha->gnl.sent = 0;
524
525 INIT_LIST_HEAD(&h);
526 fcport = tf = NULL;
527 if (!list_empty(&vha->gnl.fcports))
528 list_splice_init(&vha->gnl.fcports, &h);
529
530 list_for_each_entry_safe(fcport, tf, &h, gnl_entry) {
531 list_del_init(&fcport->gnl_entry);
532 fcport->flags &= ~FCF_ASYNC_SENT;
533 ea.fcport = fcport;
534
535 qla2x00_fcport_event_handler(vha, &ea);
536 }
537
538 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
539
25ff6af1 540 sp->free(sp);
726b8548
QT		 541}
542
543int qla24xx_async_gnl(struct scsi_qla_host *vha, fc_port_t *fcport)
544{
545 srb_t *sp;
546 struct srb_iocb *mbx;
547 int rval = QLA_FUNCTION_FAILED;
548 unsigned long flags;
549 u16 *mb;
550
551 if (!vha->flags.online)
552 goto done;
553
554 ql_dbg(ql_dbg_disc, vha, 0xffff,
555 "Async-gnlist WWPN %8phC \n", fcport->port_name);
556
557 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
558 fcport->flags |= FCF_ASYNC_SENT;
559 fcport->disc_state = DSC_GNL;
560 fcport->last_rscn_gen = fcport->rscn_gen;
561 fcport->last_login_gen = fcport->login_gen;
562
563 list_add_tail(&fcport->gnl_entry, &vha->gnl.fcports);
564 if (vha->gnl.sent) {
565 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
566 rval = QLA_SUCCESS;
567 goto done;
568 }
569 vha->gnl.sent = 1;
570 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
571
572 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
573 if (!sp)
574 goto done;
575 sp->type = SRB_MB_IOCB;
576 sp->name = "gnlist";
577 sp->gen1 = fcport->rscn_gen;
578 sp->gen2 = fcport->login_gen;
579
580 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha)+2);
581
582 mb = sp->u.iocb_cmd.u.mbx.out_mb;
583 mb[0] = MBC_PORT_NODE_NAME_LIST;
584 mb[1] = BIT_2 | BIT_3;
585 mb[2] = MSW(vha->gnl.ldma);
586 mb[3] = LSW(vha->gnl.ldma);
587 mb[6] = MSW(MSD(vha->gnl.ldma));
588 mb[7] = LSW(MSD(vha->gnl.ldma));
589 mb[8] = vha->gnl.size;
590 mb[9] = vha->vp_idx;
591
592 mbx = &sp->u.iocb_cmd;
593 mbx->timeout = qla2x00_async_iocb_timeout;
594
595 sp->done = qla24xx_async_gnl_sp_done;
596
597 rval = qla2x00_start_sp(sp);
598 if (rval != QLA_SUCCESS)
599 goto done_free_sp;
600
601 ql_dbg(ql_dbg_disc, vha, 0xffff,
602 "Async-%s - OUT WWPN %8phC hndl %x\n",
603 sp->name, fcport->port_name, sp->handle);
604
605 return rval;
606
607done_free_sp:
25ff6af1 608 sp->free(sp);
726b8548
QT		 609done:
610 fcport->flags &= ~FCF_ASYNC_SENT;
611 return rval;
612}
613
614int qla24xx_post_gnl_work(struct scsi_qla_host *vha, fc_port_t *fcport)
615{
616 struct qla_work_evt *e;
617
618 e = qla2x00_alloc_work(vha, QLA_EVT_GNL);
619 if (!e)
620 return QLA_FUNCTION_FAILED;
621
622 e->u.fcport.fcport = fcport;
623 return qla2x00_post_work(vha, e);
624}
625
626static
25ff6af1 627void qla24xx_async_gpdb_sp_done(void *s, int res)
726b8548 628{
25ff6af1
JC		 629 struct srb *sp = s;
630 struct scsi_qla_host *vha = sp->vha;
726b8548 631 struct qla_hw_data *ha = vha->hw;
726b8548
QT		 632 struct port_database_24xx *pd;
633 fc_port_t *fcport = sp->fcport;
634 u16 *mb = sp->u.iocb_cmd.u.mbx.in_mb;
635 int rval = QLA_SUCCESS;
636 struct event_arg ea;
637
638 ql_dbg(ql_dbg_disc, vha, 0xffff,
639 "Async done-%s res %x, WWPN %8phC mb[1]=%x mb[2]=%x \n",
640 sp->name, res, fcport->port_name, mb[1], mb[2]);
641
642 fcport->flags &= ~FCF_ASYNC_SENT;
643
644 if (res) {
645 rval = res;
646 goto gpd_error_out;
647 }
648
649 pd = (struct port_database_24xx *)sp->u.iocb_cmd.u.mbx.in;
650
15f30a57 651 rval = __qla24xx_parse_gpdb(vha, fcport, pd);
726b8548
QT		 652
653gpd_error_out:
654 memset(&ea, 0, sizeof(ea));
655 ea.event = FCME_GPDB_DONE;
656 ea.rc = rval;
657 ea.fcport = fcport;
658 ea.sp = sp;
659
660 qla2x00_fcport_event_handler(vha, &ea);
661
662 dma_pool_free(ha->s_dma_pool, sp->u.iocb_cmd.u.mbx.in,
663 sp->u.iocb_cmd.u.mbx.in_dma);
664
25ff6af1 665 sp->free(sp);
726b8548
QT		 666}
667
668static int qla24xx_post_gpdb_work(struct scsi_qla_host *vha, fc_port_t *fcport,
669 u8 opt)
670{
671 struct qla_work_evt *e;
672
673 e = qla2x00_alloc_work(vha, QLA_EVT_GPDB);
674 if (!e)
675 return QLA_FUNCTION_FAILED;
676
677 e->u.fcport.fcport = fcport;
678 e->u.fcport.opt = opt;
679 return qla2x00_post_work(vha, e);
680}
681
682int qla24xx_async_gpdb(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt)
683{
684 srb_t *sp;
685 struct srb_iocb *mbx;
686 int rval = QLA_FUNCTION_FAILED;
687 u16 *mb;
688 dma_addr_t pd_dma;
689 struct port_database_24xx *pd;
690 struct qla_hw_data *ha = vha->hw;
691
692 if (!vha->flags.online)
693 goto done;
694
695 fcport->flags |= FCF_ASYNC_SENT;
696 fcport->disc_state = DSC_GPDB;
697
698 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
699 if (!sp)
700 goto done;
701
702 pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
703 if (pd == NULL) {
704 ql_log(ql_log_warn, vha, 0xffff,
705 "Failed to allocate port database structure.\n");
706 goto done_free_sp;
707 }
708 memset(pd, 0, max(PORT_DATABASE_SIZE, PORT_DATABASE_24XX_SIZE));
709
710 sp->type = SRB_MB_IOCB;
711 sp->name = "gpdb";
712 sp->gen1 = fcport->rscn_gen;
713 sp->gen2 = fcport->login_gen;
714 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
715
716 mb = sp->u.iocb_cmd.u.mbx.out_mb;
717 mb[0] = MBC_GET_PORT_DATABASE;
718 mb[1] = fcport->loop_id;
719 mb[2] = MSW(pd_dma);
720 mb[3] = LSW(pd_dma);
721 mb[6] = MSW(MSD(pd_dma));
722 mb[7] = LSW(MSD(pd_dma));
723 mb[9] = vha->vp_idx;
724 mb[10] = opt;
725
726 mbx = &sp->u.iocb_cmd;
727 mbx->timeout = qla2x00_async_iocb_timeout;
728 mbx->u.mbx.in = (void *)pd;
729 mbx->u.mbx.in_dma = pd_dma;
730
731 sp->done = qla24xx_async_gpdb_sp_done;
732
733 rval = qla2x00_start_sp(sp);
734 if (rval != QLA_SUCCESS)
735 goto done_free_sp;
736
737 ql_dbg(ql_dbg_disc, vha, 0xffff,
738 "Async-%s %8phC hndl %x opt %x\n",
739 sp->name, fcport->port_name, sp->handle, opt);
740
741 return rval;
742
743done_free_sp:
744 if (pd)
745 dma_pool_free(ha->s_dma_pool, pd, pd_dma);
746
25ff6af1 747 sp->free(sp);
726b8548
QT		 748done:
749 fcport->flags &= ~FCF_ASYNC_SENT;
750 qla24xx_post_gpdb_work(vha, fcport, opt);
5ff1d584
AV		 751 return rval;
752}
753
726b8548
QT		 754static
755void qla24xx_handle_gpdb_event(scsi_qla_host_t *vha, struct event_arg *ea)
756{
757 int rval = ea->rc;
758 fc_port_t *fcport = ea->fcport;
759 unsigned long flags;
760
761 fcport->flags &= ~FCF_ASYNC_SENT;
762
763 ql_dbg(ql_dbg_disc, vha, 0xffff,
764 "%s %8phC DS %d LS %d rval %d\n", __func__, fcport->port_name,
765 fcport->disc_state, fcport->fw_login_state, rval);
766
767 if (ea->sp->gen2 != fcport->login_gen) {
768 /* target side must have changed it. */
769 ql_dbg(ql_dbg_disc, vha, 0xffff,
770 "%s %8phC generation changed rscn %d|%d login %d|%d \n",
771 __func__, fcport->port_name, fcport->last_rscn_gen,
772 fcport->rscn_gen, fcport->last_login_gen,
773 fcport->login_gen);
774 return;
775 } else if (ea->sp->gen1 != fcport->rscn_gen) {
776 ql_dbg(ql_dbg_disc, vha, 0xffff, "%s %d %8phC post gidpn\n",
777 __func__, __LINE__, fcport->port_name);
778 qla24xx_post_gidpn_work(vha, fcport);
779 return;
780 }
781
782 if (rval != QLA_SUCCESS) {
783 ql_dbg(ql_dbg_disc, vha, 0xffff, "%s %d %8phC post del sess\n",
784 __func__, __LINE__, fcport->port_name);
785 qlt_schedule_sess_for_deletion_lock(fcport);
786 return;
787 }
788
789 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
790 ea->fcport->login_gen++;
791 ea->fcport->deleted = 0;
792 ea->fcport->logout_on_delete = 1;
793
794 if (!ea->fcport->login_succ && !IS_SW_RESV_ADDR(ea->fcport->d_id)) {
795 vha->fcport_count++;
796 ea->fcport->login_succ = 1;
797
798 if (!IS_IIDMA_CAPABLE(vha->hw) ||
799 !vha->hw->flags.gpsc_supported) {
800 ql_dbg(ql_dbg_disc, vha, 0xffff,
801 "%s %d %8phC post upd_fcport fcp_cnt %d\n",
802 __func__, __LINE__, fcport->port_name,
803 vha->fcport_count);
804
805 qla24xx_post_upd_fcport_work(vha, fcport);
806 } else {
807 ql_dbg(ql_dbg_disc, vha, 0xffff,
808 "%s %d %8phC post gpsc fcp_cnt %d\n",
809 __func__, __LINE__, fcport->port_name,
810 vha->fcport_count);
811
812 qla24xx_post_gpsc_work(vha, fcport);
813 }
814 }
815 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
816} /* gpdb event */
817
818int qla24xx_fcport_handle_login(struct scsi_qla_host *vha, fc_port_t *fcport)
819{
820 if (fcport->login_retry == 0)
821 return 0;
822
823 if (fcport->scan_state != QLA_FCPORT_FOUND)
824 return 0;
825
826 ql_dbg(ql_dbg_disc, vha, 0xffff,
827 "%s %8phC DS %d LS %d P %d fl %x confl %p rscn %d|%d login %d|%d retry %d lid %d\n",
828 __func__, fcport->port_name, fcport->disc_state,
829 fcport->fw_login_state, fcport->login_pause, fcport->flags,
830 fcport->conflict, fcport->last_rscn_gen, fcport->rscn_gen,
831 fcport->last_login_gen, fcport->login_gen, fcport->login_retry,
832 fcport->loop_id);
833
834 fcport->login_retry--;
835
836 if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) ||
726b8548
QT		 837 (fcport->fw_login_state == DSC_LS_PRLI_PEND))
838 return 0;
839
5b33469a
QT		 840 if (fcport->fw_login_state == DSC_LS_PLOGI_COMP) {
841 if (time_before_eq(jiffies, fcport->plogi_nack_done_deadline))
842 return 0;
843 }
844
726b8548
QT		 845 /* for pure Target Mode. Login will not be initiated */
846 if (vha->host->active_mode == MODE_TARGET)
847 return 0;
848
849 if (fcport->flags & FCF_ASYNC_SENT) {
850 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
851 return 0;
852 }
853
854 switch (fcport->disc_state) {
855 case DSC_DELETED:
856 if (fcport->loop_id == FC_NO_LOOP_ID) {
857 ql_dbg(ql_dbg_disc, vha, 0xffff,
858 "%s %d %8phC post gnl\n",
859 __func__, __LINE__, fcport->port_name);
860 qla24xx_async_gnl(vha, fcport);
861 } else {
862 ql_dbg(ql_dbg_disc, vha, 0xffff,
863 "%s %d %8phC post login\n",
864 __func__, __LINE__, fcport->port_name);
865 fcport->disc_state = DSC_LOGIN_PEND;
866 qla2x00_post_async_login_work(vha, fcport, NULL);
867 }
868 break;
869
870 case DSC_GNL:
871 if (fcport->login_pause) {
872 fcport->last_rscn_gen = fcport->rscn_gen;
873 fcport->last_login_gen = fcport->login_gen;
874 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
875 break;
876 }
877
878 if (fcport->flags & FCF_FCP2_DEVICE) {
879 u8 opt = PDO_FORCE_ADISC;
880
881 ql_dbg(ql_dbg_disc, vha, 0xffff,
882 "%s %d %8phC post gpdb\n",
883 __func__, __LINE__, fcport->port_name);
884
885 fcport->disc_state = DSC_GPDB;
886 qla24xx_post_gpdb_work(vha, fcport, opt);
887 } else {
888 ql_dbg(ql_dbg_disc, vha, 0xffff,
889 "%s %d %8phC post login \n",
890 __func__, __LINE__, fcport->port_name);
891 fcport->disc_state = DSC_LOGIN_PEND;
892 qla2x00_post_async_login_work(vha, fcport, NULL);
893 }
894
895 break;
896
897 case DSC_LOGIN_FAILED:
898 ql_dbg(ql_dbg_disc, vha, 0xffff,
899 "%s %d %8phC post gidpn \n",
900 __func__, __LINE__, fcport->port_name);
901
902 qla24xx_post_gidpn_work(vha, fcport);
903 break;
904
905 case DSC_LOGIN_COMPLETE:
906 /* recheck login state */
907 ql_dbg(ql_dbg_disc, vha, 0xffff,
908 "%s %d %8phC post gpdb \n",
909 __func__, __LINE__, fcport->port_name);
910
911 qla24xx_post_gpdb_work(vha, fcport, PDO_FORCE_ADISC);
912 break;
913
914 default:
915 break;
916 }
917
918 return 0;
919}
920
921static
922void qla24xx_handle_rscn_event(fc_port_t *fcport, struct event_arg *ea)
923{
924 fcport->rscn_gen++;
925
926 ql_dbg(ql_dbg_disc, fcport->vha, 0xffff,
927 "%s %8phC DS %d LS %d\n",
928 __func__, fcport->port_name, fcport->disc_state,
929 fcport->fw_login_state);
930
931 if (fcport->flags & FCF_ASYNC_SENT)
932 return;
933
934 switch (fcport->disc_state) {
935 case DSC_DELETED:
936 case DSC_LOGIN_COMPLETE:
937 qla24xx_post_gidpn_work(fcport->vha, fcport);
938 break;
939
940 default:
941 break;
942 }
943}
944
945int qla24xx_post_newsess_work(struct scsi_qla_host *vha, port_id_t *id,
946 u8 *port_name, void *pla)
947{
948 struct qla_work_evt *e;
949 e = qla2x00_alloc_work(vha, QLA_EVT_NEW_SESS);
950 if (!e)
951 return QLA_FUNCTION_FAILED;
952
953 e->u.new_sess.id = *id;
954 e->u.new_sess.pla = pla;
955 memcpy(e->u.new_sess.port_name, port_name, WWN_SIZE);
956
957 return qla2x00_post_work(vha, e);
958}
959
960static
961int qla24xx_handle_delete_done_event(scsi_qla_host_t *vha,
962 struct event_arg *ea)
963{
964 fc_port_t *fcport = ea->fcport;
965
966 if (test_bit(UNLOADING, &vha->dpc_flags))
967 return 0;
968
969 switch (vha->host->active_mode) {
970 case MODE_INITIATOR:
971 case MODE_DUAL:
972 if (fcport->scan_state == QLA_FCPORT_FOUND)
973 qla24xx_fcport_handle_login(vha, fcport);
974 break;
975
976 case MODE_TARGET:
977 default:
978 /* no-op */
979 break;
980 }
981
982 return 0;
983}
984
985static
986void qla24xx_handle_relogin_event(scsi_qla_host_t *vha,
987 struct event_arg *ea)
988{
989 fc_port_t *fcport = ea->fcport;
990
991 if (fcport->scan_state != QLA_FCPORT_FOUND) {
992 fcport->login_retry++;
993 return;
994 }
995
996 ql_dbg(ql_dbg_disc, vha, 0xffff,
997 "%s %8phC DS %d LS %d P %d del %d cnfl %p rscn %d|%d login %d|%d fl %x\n",
998 __func__, fcport->port_name, fcport->disc_state,
999 fcport->fw_login_state, fcport->login_pause,
1000 fcport->deleted, fcport->conflict,
1001 fcport->last_rscn_gen, fcport->rscn_gen,
1002 fcport->last_login_gen, fcport->login_gen,
1003 fcport->flags);
1004
1005 if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) ||
726b8548
QT		 1006 (fcport->fw_login_state == DSC_LS_PRLI_PEND))
1007 return;
1008
5b33469a
QT		 1009 if (fcport->fw_login_state == DSC_LS_PLOGI_COMP) {
1010 if (time_before_eq(jiffies, fcport->plogi_nack_done_deadline))
1011 return;
1012 }
1013
726b8548
QT		 1014 if (fcport->flags & FCF_ASYNC_SENT) {
1015 fcport->login_retry++;
1016 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1017 return;
1018 }
1019
1020 if (fcport->disc_state == DSC_DELETE_PEND) {
1021 fcport->login_retry++;
1022 return;
1023 }
1024
1025 if (fcport->last_rscn_gen != fcport->rscn_gen) {
1026 ql_dbg(ql_dbg_disc, vha, 0xffff, "%s %d %8phC post gidpn\n",
1027 __func__, __LINE__, fcport->port_name);
1028
1029 qla24xx_async_gidpn(vha, fcport);
1030 return;
1031 }
1032
1033 qla24xx_fcport_handle_login(vha, fcport);
1034}
1035
41dc529a 1036void qla2x00_fcport_event_handler(scsi_qla_host_t *vha, struct event_arg *ea)
726b8548 1037{
41dc529a
QT		 1038 fc_port_t *fcport, *f, *tf;
1039 uint32_t id = 0, mask, rid;
726b8548
QT		 1040 int rc;
1041
1042 switch (ea->event) {
1043 case FCME_RELOGIN:
1044 if (test_bit(UNLOADING, &vha->dpc_flags))
1045 return;
5ff1d584 1046
726b8548
QT		 1047 qla24xx_handle_relogin_event(vha, ea);
1048 break;
1049 case FCME_RSCN:
1050 if (test_bit(UNLOADING, &vha->dpc_flags))
1051 return;
41dc529a
QT		 1052 switch (ea->id.b.rsvd_1) {
1053 case RSCN_PORT_ADDR:
1054 fcport = qla2x00_find_fcport_by_nportid(vha, &ea->id, 1);
1055 if (!fcport) {
1056 /* cable moved */
1057 rc = qla24xx_post_gpnid_work(vha, &ea->id);
1058 if (rc) {
1059 ql_log(ql_log_warn, vha, 0xffff,
1060 "RSCN GPNID work failed %02x%02x%02x\n",
1061 ea->id.b.domain, ea->id.b.area,
1062 ea->id.b.al_pa);
1063 }
1064 } else {
1065 ea->fcport = fcport;
1066 qla24xx_handle_rscn_event(fcport, ea);
1067 }
1068 break;
1069 case RSCN_AREA_ADDR:
1070 case RSCN_DOM_ADDR:
1071 if (ea->id.b.rsvd_1 == RSCN_AREA_ADDR) {
1072 mask = 0xffff00;
1073 ql_log(ql_dbg_async, vha, 0xffff,
1074 "RSCN: Area 0x%06x was affected\n",
1075 ea->id.b24);
1076 } else {
1077 mask = 0xff0000;
1078 ql_log(ql_dbg_async, vha, 0xffff,
1079 "RSCN: Domain 0x%06x was affected\n",
1080 ea->id.b24);
1081 }
726b8548 1082
41dc529a
QT		 1083 rid = ea->id.b24 & mask;
1084 list_for_each_entry_safe(f, tf, &vha->vp_fcports,
1085 list) {
1086 id = f->d_id.b24 & mask;
1087 if (rid == id) {
1088 ea->fcport = f;
1089 qla24xx_handle_rscn_event(f, ea);
1090 }
726b8548 1091 }
41dc529a
QT		 1092 break;
1093 case RSCN_FAB_ADDR:
1094 default:
1095 ql_log(ql_log_warn, vha, 0xffff,
1096 "RSCN: Fabric was affected. Addr format %d\n",
1097 ea->id.b.rsvd_1);
1098 qla2x00_mark_all_devices_lost(vha, 1);
1099 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1100 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
726b8548
QT		 1101 }
1102 break;
1103 case FCME_GIDPN_DONE:
1104 qla24xx_handle_gidpn_event(vha, ea);
1105 break;
1106 case FCME_GNL_DONE:
1107 qla24xx_handle_gnl_done_event(vha, ea);
1108 break;
1109 case FCME_GPSC_DONE:
1110 qla24xx_post_upd_fcport_work(vha, ea->fcport);
1111 break;
1112 case FCME_PLOGI_DONE: /* Initiator side sent LLIOCB */
1113 qla24xx_handle_plogi_done_event(vha, ea);
1114 break;
1115 case FCME_GPDB_DONE:
1116 qla24xx_handle_gpdb_event(vha, ea);
1117 break;
1118 case FCME_GPNID_DONE:
1119 qla24xx_handle_gpnid_event(vha, ea);
1120 break;
1121 case FCME_DELETE_DONE:
1122 qla24xx_handle_delete_done_event(vha, ea);
1123 break;
1124 default:
1125 BUG_ON(1);
1126 break;
1127 }
5ff1d584
AV		 1128}
1129
3822263e 1130static void
faef62d1 1131qla2x00_tmf_iocb_timeout(void *data)
3822263e 1132{
25ff6af1 1133 srb_t *sp = data;
faef62d1 1134 struct srb_iocb *tmf = &sp->u.iocb_cmd;
3822263e 1135
faef62d1
AB		 1136 tmf->u.tmf.comp_status = CS_TIMEOUT;
1137 complete(&tmf->u.tmf.comp);
1138}
9ba56b95 1139
faef62d1 1140static void
25ff6af1 1141qla2x00_tmf_sp_done(void *ptr, int res)
faef62d1 1142{
25ff6af1 1143 srb_t *sp = ptr;
faef62d1 1144 struct srb_iocb *tmf = &sp->u.iocb_cmd;
25ff6af1 1145
faef62d1 1146 complete(&tmf->u.tmf.comp);
3822263e
MI		 1147}
1148
1149int
faef62d1 1150qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t flags, uint32_t lun,
3822263e
MI		 1151 uint32_t tag)
1152{
1153 struct scsi_qla_host *vha = fcport->vha;
faef62d1 1154 struct srb_iocb *tm_iocb;
3822263e 1155 srb_t *sp;
faef62d1 1156 int rval = QLA_FUNCTION_FAILED;
3822263e 1157
9ba56b95 1158 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
3822263e
MI		 1159 if (!sp)
1160 goto done;
1161
faef62d1 1162 tm_iocb = &sp->u.iocb_cmd;
9ba56b95
GM		 1163 sp->type = SRB_TM_CMD;
1164 sp->name = "tmf";
faef62d1
AB		 1165 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
1166 tm_iocb->u.tmf.flags = flags;
1167 tm_iocb->u.tmf.lun = lun;
1168 tm_iocb->u.tmf.data = tag;
1169 sp->done = qla2x00_tmf_sp_done;
1170 tm_iocb->timeout = qla2x00_tmf_iocb_timeout;
1171 init_completion(&tm_iocb->u.tmf.comp);
3822263e
MI		 1172
1173 rval = qla2x00_start_sp(sp);
1174 if (rval != QLA_SUCCESS)
1175 goto done_free_sp;
1176
7c3df132 1177 ql_dbg(ql_dbg_taskm, vha, 0x802f,
cfb0919c
CD		 1178 "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
1179 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
1180 fcport->d_id.b.area, fcport->d_id.b.al_pa);
faef62d1
AB		 1181
1182 wait_for_completion(&tm_iocb->u.tmf.comp);
1183
1184 rval = tm_iocb->u.tmf.comp_status == CS_COMPLETE ?
1185 QLA_SUCCESS : QLA_FUNCTION_FAILED;
1186
1187 if ((rval != QLA_SUCCESS) || tm_iocb->u.tmf.data) {
1188 ql_dbg(ql_dbg_taskm, vha, 0x8030,
1189 "TM IOCB failed (%x).\n", rval);
1190 }
1191
1192 if (!test_bit(UNLOADING, &vha->dpc_flags) && !IS_QLAFX00(vha->hw)) {
1193 flags = tm_iocb->u.tmf.flags;
1194 lun = (uint16_t)tm_iocb->u.tmf.lun;
1195
1196 /* Issue Marker IOCB */
1197 qla2x00_marker(vha, vha->hw->req_q_map[0],
1198 vha->hw->rsp_q_map[0], sp->fcport->loop_id, lun,
1199 flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
1200 }
3822263e
MI		 1201
1202done_free_sp:
25ff6af1 1203 sp->free(sp);
3822263e
MI		 1204done:
1205 return rval;
1206}
1207
4440e46d
AB		 1208static void
1209qla24xx_abort_iocb_timeout(void *data)
1210{
25ff6af1 1211 srb_t *sp = data;
4440e46d
AB		 1212 struct srb_iocb *abt = &sp->u.iocb_cmd;
1213
1214 abt->u.abt.comp_status = CS_TIMEOUT;
1215 complete(&abt->u.abt.comp);
1216}
1217
1218static void
25ff6af1 1219qla24xx_abort_sp_done(void *ptr, int res)
4440e46d 1220{
25ff6af1 1221 srb_t *sp = ptr;
4440e46d
AB		 1222 struct srb_iocb *abt = &sp->u.iocb_cmd;
1223
1224 complete(&abt->u.abt.comp);
1225}
1226
15f30a57 1227int
4440e46d
AB		 1228qla24xx_async_abort_cmd(srb_t *cmd_sp)
1229{
25ff6af1 1230 scsi_qla_host_t *vha = cmd_sp->vha;
4440e46d
AB		 1231 fc_port_t *fcport = cmd_sp->fcport;
1232 struct srb_iocb *abt_iocb;
1233 srb_t *sp;
1234 int rval = QLA_FUNCTION_FAILED;
1235
1236 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
1237 if (!sp)
1238 goto done;
1239
1240 abt_iocb = &sp->u.iocb_cmd;
1241 sp->type = SRB_ABT_CMD;
1242 sp->name = "abort";
1243 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
1244 abt_iocb->u.abt.cmd_hndl = cmd_sp->handle;
1245 sp->done = qla24xx_abort_sp_done;
1246 abt_iocb->timeout = qla24xx_abort_iocb_timeout;
1247 init_completion(&abt_iocb->u.abt.comp);
1248
1249 rval = qla2x00_start_sp(sp);
1250 if (rval != QLA_SUCCESS)
1251 goto done_free_sp;
1252
1253 ql_dbg(ql_dbg_async, vha, 0x507c,
1254 "Abort command issued - hdl=%x, target_id=%x\n",
1255 cmd_sp->handle, fcport->tgt_id);
1256
1257 wait_for_completion(&abt_iocb->u.abt.comp);
1258
1259 rval = abt_iocb->u.abt.comp_status == CS_COMPLETE ?
1260 QLA_SUCCESS : QLA_FUNCTION_FAILED;
1261
1262done_free_sp:
25ff6af1 1263 sp->free(sp);
4440e46d
AB		 1264done:
1265 return rval;
1266}
1267
1268int
1269qla24xx_async_abort_command(srb_t *sp)
1270{
1271 unsigned long flags = 0;
1272
1273 uint32_t handle;
1274 fc_port_t *fcport = sp->fcport;
1275 struct scsi_qla_host *vha = fcport->vha;
1276 struct qla_hw_data *ha = vha->hw;
1277 struct req_que *req = vha->req;
1278
1279 spin_lock_irqsave(&ha->hardware_lock, flags);
1280 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
1281 if (req->outstanding_cmds[handle] == sp)
1282 break;
1283 }
1284 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1285 if (handle == req->num_outstanding_cmds) {
1286 /* Command not found. */
1287 return QLA_FUNCTION_FAILED;
1288 }
1289 if (sp->type == SRB_FXIOCB_DCMD)
1290 return qlafx00_fx_disc(vha, &vha->hw->mr.fcport,
1291 FXDISC_ABORT_IOCTL);
1292
1293 return qla24xx_async_abort_cmd(sp);
1294}
1295
726b8548
QT		 1296static void
1297qla24xx_handle_plogi_done_event(struct scsi_qla_host *vha, struct event_arg *ea)
ac280b67 1298{
726b8548 1299 port_id_t cid; /* conflict Nport id */
ac280b67 1300
726b8548 1301 switch (ea->data[0]) {
ac280b67 1302 case MBS_COMMAND_COMPLETE:
a4f92a32
AV		 1303 /*
1304 * Driver must validate login state - If PRLI not complete,
1305 * force a relogin attempt via implicit LOGO, PLOGI, and PRLI
1306 * requests.
1307 */
726b8548
QT		 1308 ql_dbg(ql_dbg_disc, vha, 0xffff,
1309 "%s %d %8phC post gpdb\n",
1310 __func__, __LINE__, ea->fcport->port_name);
1311 ea->fcport->chip_reset = vha->hw->chip_reset;
1312 ea->fcport->logout_on_delete = 1;
1313 qla24xx_post_gpdb_work(vha, ea->fcport, 0);
ac280b67
AV		 1314 break;
1315 case MBS_COMMAND_ERROR:
726b8548
QT		 1316 ql_dbg(ql_dbg_disc, vha, 0xffff, "%s %d %8phC cmd error %x\n",
1317 __func__, __LINE__, ea->fcport->port_name, ea->data[1]);
1318
1319 ea->fcport->flags &= ~FCF_ASYNC_SENT;
1320 ea->fcport->disc_state = DSC_LOGIN_FAILED;
1321 if (ea->data[1] & QLA_LOGIO_LOGIN_RETRIED)
ac280b67
AV		 1322 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1323 else
726b8548 1324 qla2x00_mark_device_lost(vha, ea->fcport, 1, 0);
ac280b67
AV		 1325 break;
1326 case MBS_LOOP_ID_USED:
726b8548
QT		 1327 /* data[1] = IO PARAM 1 = nport ID */
1328 cid.b.domain = (ea->iop[1] >> 16) & 0xff;
1329 cid.b.area = (ea->iop[1] >> 8) & 0xff;
1330 cid.b.al_pa = ea->iop[1] & 0xff;
1331 cid.b.rsvd_1 = 0;
1332
1333 ql_dbg(ql_dbg_disc, vha, 0xffff,
1334 "%s %d %8phC LoopID 0x%x in use post gnl\n",
1335 __func__, __LINE__, ea->fcport->port_name,
1336 ea->fcport->loop_id);
1337
1338 if (IS_SW_RESV_ADDR(cid)) {
1339 set_bit(ea->fcport->loop_id, vha->hw->loop_id_map);
1340 ea->fcport->loop_id = FC_NO_LOOP_ID;
1341 } else {
1342 qla2x00_clear_loop_id(ea->fcport);
ac280b67 1343 }
726b8548
QT		 1344 qla24xx_post_gnl_work(vha, ea->fcport);
1345 break;
1346 case MBS_PORT_ID_USED:
1347 ql_dbg(ql_dbg_disc, vha, 0xffff,
1348 "%s %d %8phC NPortId %02x%02x%02x inuse post gidpn\n",
1349 __func__, __LINE__, ea->fcport->port_name,
1350 ea->fcport->d_id.b.domain, ea->fcport->d_id.b.area,
1351 ea->fcport->d_id.b.al_pa);
1352
1353 qla2x00_clear_loop_id(ea->fcport);
1354 qla24xx_post_gidpn_work(vha, ea->fcport);
ac280b67
AV		 1355 break;
1356 }
4916392b 1357 return;
ac280b67
AV		 1358}
1359
4916392b 1360void
ac280b67
AV		 1361qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport,
1362 uint16_t *data)
1363{
726b8548 1364 qla2x00_mark_device_lost(vha, fcport, 1, 0);
a6ca8878 1365 qlt_logo_completion_handler(fcport, data[0]);
726b8548 1366 fcport->login_gen++;
4916392b 1367 return;
ac280b67
AV		 1368}
1369
4916392b 1370void
5ff1d584
AV		 1371qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport,
1372 uint16_t *data)
1373{
1374 if (data[0] == MBS_COMMAND_COMPLETE) {
1375 qla2x00_update_fcport(vha, fcport);
1376
4916392b 1377 return;
5ff1d584
AV		 1378 }
1379
1380 /* Retry login. */
1381 fcport->flags &= ~FCF_ASYNC_SENT;
1382 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
1383 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1384 else
80d79440 1385 qla2x00_mark_device_lost(vha, fcport, 1, 0);
5ff1d584 1386
4916392b 1387 return;
5ff1d584
AV		 1388}
1389
1da177e4
LT		 1390/****************************************************************************/
1391/* QLogic ISP2x00 Hardware Support Functions. */
1392/****************************************************************************/
1393
fa492630 1394static int
7d613ac6
SV		 1395qla83xx_nic_core_fw_load(scsi_qla_host_t *vha)
1396{
1397 int rval = QLA_SUCCESS;
1398 struct qla_hw_data *ha = vha->hw;
1399 uint32_t idc_major_ver, idc_minor_ver;
711aa7f7 1400 uint16_t config[4];
7d613ac6
SV		 1401
1402 qla83xx_idc_lock(vha, 0);
1403
1404 /* SV: TODO: Assign initialization timeout from
1405 * flash-info / other param
1406 */
1407 ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT;
1408 ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT;
1409
1410 /* Set our fcoe function presence */
1411 if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) {
1412 ql_dbg(ql_dbg_p3p, vha, 0xb077,
1413 "Error while setting DRV-Presence.\n");
1414 rval = QLA_FUNCTION_FAILED;
1415 goto exit;
1416 }
1417
1418 /* Decide the reset ownership */
1419 qla83xx_reset_ownership(vha);
1420
1421 /*
1422 * On first protocol driver load:
1423 * Init-Owner: Set IDC-Major-Version and Clear IDC-Lock-Recovery
1424 * register.
1425 * Others: Check compatibility with current IDC Major version.
1426 */
1427 qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver);
1428 if (ha->flags.nic_core_reset_owner) {
1429 /* Set IDC Major version */
1430 idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION;
1431 qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver);
1432
1433 /* Clearing IDC-Lock-Recovery register */
1434 qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0);
1435 } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) {
1436 /*
1437 * Clear further IDC participation if we are not compatible with
1438 * the current IDC Major Version.
1439 */
1440 ql_log(ql_log_warn, vha, 0xb07d,
1441 "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n",
1442 idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION);
1443 __qla83xx_clear_drv_presence(vha);
1444 rval = QLA_FUNCTION_FAILED;
1445 goto exit;
1446 }
1447 /* Each function sets its supported Minor version. */
1448 qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver);
1449 idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2));
1450 qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver);
1451
711aa7f7
SK		 1452 if (ha->flags.nic_core_reset_owner) {
1453 memset(config, 0, sizeof(config));
1454 if (!qla81xx_get_port_config(vha, config))
1455 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
1456 QLA8XXX_DEV_READY);
1457 }
1458
7d613ac6
SV		 1459 rval = qla83xx_idc_state_handler(vha);
1460
1461exit:
1462 qla83xx_idc_unlock(vha, 0);
1463
1464 return rval;
1465}
1466
1da177e4
LT		 1467/*
1468* qla2x00_initialize_adapter
1469* Initialize board.
1470*
1471* Input:
1472* ha = adapter block pointer.
1473*
1474* Returns:
1475* 0 = success
1476*/
1477int
e315cd28 1478qla2x00_initialize_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 1479{
1480 int rval;
e315cd28 1481 struct qla_hw_data *ha = vha->hw;
73208dfd 1482 struct req_que *req = ha->req_q_map[0];
2533cf67 1483
fc90adaf
JC		 1484 memset(&vha->qla_stats, 0, sizeof(vha->qla_stats));
1485 memset(&vha->fc_host_stat, 0, sizeof(vha->fc_host_stat));
1486
1da177e4 1487 /* Clear adapter flags. */
e315cd28 1488 vha->flags.online = 0;
2533cf67 1489 ha->flags.chip_reset_done = 0;
e315cd28 1490 vha->flags.reset_active = 0;
85880801
AV		 1491 ha->flags.pci_channel_io_perm_failure = 0;
1492 ha->flags.eeh_busy = 0;
fabbb8df 1493 vha->qla_stats.jiffies_at_last_reset = get_jiffies_64();
e315cd28
AC		 1494 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1495 atomic_set(&vha->loop_state, LOOP_DOWN);
1496 vha->device_flags = DFLG_NO_CABLE;
1497 vha->dpc_flags = 0;
1498 vha->flags.management_server_logged_in = 0;
1499 vha->marker_needed = 0;
1da177e4
LT		 1500 ha->isp_abort_cnt = 0;
1501 ha->beacon_blink_led = 0;
1502
73208dfd
AC		 1503 set_bit(0, ha->req_qid_map);
1504 set_bit(0, ha->rsp_qid_map);
1505
cfb0919c 1506 ql_dbg(ql_dbg_init, vha, 0x0040,
7c3df132 1507 "Configuring PCI space...\n");
e315cd28 1508 rval = ha->isp_ops->pci_config(vha);
1da177e4 1509 if (rval) {
7c3df132
SK		 1510 ql_log(ql_log_warn, vha, 0x0044,
1511 "Unable to configure PCI space.\n");
1da177e4
LT		 1512 return (rval);
1513 }
1514
e315cd28 1515 ha->isp_ops->reset_chip(vha);
1da177e4 1516
e315cd28 1517 rval = qla2xxx_get_flash_info(vha);
c00d8994 1518 if (rval) {
7c3df132
SK		 1519 ql_log(ql_log_fatal, vha, 0x004f,
1520 "Unable to validate FLASH data.\n");
7ec0effd
AD		 1521 return rval;
1522 }
1523
1524 if (IS_QLA8044(ha)) {
1525 qla8044_read_reset_template(vha);
1526
1527 /* NOTE: If ql2xdontresethba==1, set IDC_CTRL DONTRESET_BIT0.
1528 * If DONRESET_BIT0 is set, drivers should not set dev_state
1529 * to NEED_RESET. But if NEED_RESET is set, drivers should
1530 * should honor the reset. */
1531 if (ql2xdontresethba == 1)
1532 qla8044_set_idc_dontreset(vha);
c00d8994
AV		 1533 }
1534
73208dfd 1535 ha->isp_ops->get_flash_version(vha, req->ring);
cfb0919c 1536 ql_dbg(ql_dbg_init, vha, 0x0061,
7c3df132 1537 "Configure NVRAM parameters...\n");
0107109e 1538
e315cd28 1539 ha->isp_ops->nvram_config(vha);
1da177e4 1540
d4c760c2
AV		 1541 if (ha->flags.disable_serdes) {
1542 /* Mask HBA via NVRAM settings? */
7c3df132 1543 ql_log(ql_log_info, vha, 0x0077,
7b833558 1544 "Masking HBA WWPN %8phN (via NVRAM).\n", vha->port_name);
d4c760c2
AV		 1545 return QLA_FUNCTION_FAILED;
1546 }
1547
cfb0919c 1548 ql_dbg(ql_dbg_init, vha, 0x0078,
7c3df132 1549 "Verifying loaded RISC code...\n");
1da177e4 1550
e315cd28
AC		 1551 if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) {
1552 rval = ha->isp_ops->chip_diag(vha);
d19044c3
AV		 1553 if (rval)
1554 return (rval);
e315cd28 1555 rval = qla2x00_setup_chip(vha);
d19044c3
AV		 1556 if (rval)
1557 return (rval);
1da177e4 1558 }
a9083016 1559
4d4df193 1560 if (IS_QLA84XX(ha)) {
e315cd28 1561 ha->cs84xx = qla84xx_get_chip(vha);
4d4df193 1562 if (!ha->cs84xx) {
7c3df132 1563 ql_log(ql_log_warn, vha, 0x00d0,
4d4df193
HK		 1564 "Unable to configure ISP84XX.\n");
1565 return QLA_FUNCTION_FAILED;
1566 }
1567 }
2d70c103 1568
ead03855 1569 if (qla_ini_mode_enabled(vha) || qla_dual_mode_enabled(vha))
2d70c103
NB		 1570 rval = qla2x00_init_rings(vha);
1571
2533cf67 1572 ha->flags.chip_reset_done = 1;
1da177e4 1573
9a069e19 1574 if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) {
6c452a45 1575 /* Issue verify 84xx FW IOCB to complete 84xx initialization */
9a069e19
GM		 1576 rval = qla84xx_init_chip(vha);
1577 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1578 ql_log(ql_log_warn, vha, 0x00d4,
1579 "Unable to initialize ISP84XX.\n");
8d2b21db 1580 qla84xx_put_chip(vha);
9a069e19
GM		 1581 }
1582 }
1583
7d613ac6
SV		 1584 /* Load the NIC Core f/w if we are the first protocol driver. */
1585 if (IS_QLA8031(ha)) {
1586 rval = qla83xx_nic_core_fw_load(vha);
1587 if (rval)
1588 ql_log(ql_log_warn, vha, 0x0124,
1589 "Error in initializing NIC Core f/w.\n");
1590 }
1591
2f0f3f4f
MI		 1592 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
1593 qla24xx_read_fcp_prio_cfg(vha);
09ff701a 1594
c46e65c7
JC		 1595 if (IS_P3P_TYPE(ha))
1596 qla82xx_set_driver_version(vha, QLA2XXX_VERSION);
1597 else
1598 qla25xx_set_driver_version(vha, QLA2XXX_VERSION);
1599
1da177e4
LT		 1600 return (rval);
1601}
1602
1603/**
abbd8870 1604 * qla2100_pci_config() - Setup ISP21xx PCI configuration registers.
1da177e4
LT		 1605 * @ha: HA context
1606 *
1607 * Returns 0 on success.
1608 */
abbd8870 1609int
e315cd28 1610qla2100_pci_config(scsi_qla_host_t *vha)
1da177e4 1611{
a157b101 1612 uint16_t w;
abbd8870 1613 unsigned long flags;
e315cd28 1614 struct qla_hw_data *ha = vha->hw;
3d71644c 1615 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 1616
1da177e4 1617 pci_set_master(ha->pdev);
af6177d8 1618 pci_try_set_mwi(ha->pdev);
1da177e4 1619
1da177e4 1620 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 1621 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
abbd8870
AV		 1622 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1623
737faece 1624 pci_disable_rom(ha->pdev);
1da177e4
LT		 1625
1626 /* Get PCI bus information. */
1627 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 1628 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
1da177e4
LT		 1629 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1630
abbd8870
AV		 1631 return QLA_SUCCESS;
1632}
1da177e4 1633
abbd8870
AV		 1634/**
1635 * qla2300_pci_config() - Setup ISP23xx PCI configuration registers.
1636 * @ha: HA context
1637 *
1638 * Returns 0 on success.
1639 */
1640int
e315cd28 1641qla2300_pci_config(scsi_qla_host_t *vha)
abbd8870 1642{
a157b101 1643 uint16_t w;
abbd8870
AV		 1644 unsigned long flags = 0;
1645 uint32_t cnt;
e315cd28 1646 struct qla_hw_data *ha = vha->hw;
3d71644c 1647 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 1648
abbd8870 1649 pci_set_master(ha->pdev);
af6177d8 1650 pci_try_set_mwi(ha->pdev);
1da177e4 1651
abbd8870 1652 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 1653 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
1da177e4 1654
abbd8870
AV		 1655 if (IS_QLA2322(ha) || IS_QLA6322(ha))
1656 w &= ~PCI_COMMAND_INTX_DISABLE;
a157b101 1657 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1da177e4 1658
abbd8870
AV		 1659 /*
1660 * If this is a 2300 card and not 2312, reset the
1661 * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately,
1662 * the 2310 also reports itself as a 2300 so we need to get the
1663 * fb revision level -- a 6 indicates it really is a 2300 and
1664 * not a 2310.
1665 */
1666 if (IS_QLA2300(ha)) {
1667 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1668
abbd8870 1669 /* Pause RISC. */
3d71644c 1670 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
abbd8870 1671 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 1672 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
abbd8870 1673 break;
1da177e4 1674
abbd8870
AV		 1675 udelay(10);
1676 }
1da177e4 1677
abbd8870 1678 /* Select FPM registers. */
3d71644c
AV		 1679 WRT_REG_WORD(&reg->ctrl_status, 0x20);
1680 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 1681
1682 /* Get the fb rev level */
3d71644c 1683 ha->fb_rev = RD_FB_CMD_REG(ha, reg);
abbd8870
AV		 1684
1685 if (ha->fb_rev == FPM_2300)
a157b101 1686 pci_clear_mwi(ha->pdev);
abbd8870
AV		 1687
1688 /* Deselect FPM registers. */
3d71644c
AV		 1689 WRT_REG_WORD(&reg->ctrl_status, 0x0);
1690 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 1691
1692 /* Release RISC module. */
3d71644c 1693 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
abbd8870 1694 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 1695 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0)
abbd8870
AV		 1696 break;
1697
1698 udelay(10);
1da177e4 1699 }
1da177e4 1700
abbd8870
AV		 1701 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1702 }
1da177e4 1703
abbd8870
AV		 1704 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
1705
737faece 1706 pci_disable_rom(ha->pdev);
1da177e4 1707
abbd8870
AV		 1708 /* Get PCI bus information. */
1709 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 1710 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 1711 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1712
1713 return QLA_SUCCESS;
1da177e4
LT		 1714}
1715
0107109e
AV		 1716/**
1717 * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers.
1718 * @ha: HA context
1719 *
1720 * Returns 0 on success.
1721 */
1722int
e315cd28 1723qla24xx_pci_config(scsi_qla_host_t *vha)
0107109e 1724{
a157b101 1725 uint16_t w;
0107109e 1726 unsigned long flags = 0;
e315cd28 1727 struct qla_hw_data *ha = vha->hw;
0107109e 1728 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
0107109e
AV		 1729
1730 pci_set_master(ha->pdev);
af6177d8 1731 pci_try_set_mwi(ha->pdev);
0107109e
AV		 1732
1733 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 1734 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
0107109e
AV		 1735 w &= ~PCI_COMMAND_INTX_DISABLE;
1736 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1737
1738 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
1739
1740 /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */
f85ec187
AV		 1741 if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
1742 pcix_set_mmrbc(ha->pdev, 2048);
0107109e
AV		 1743
1744 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 1745 if (pci_is_pcie(ha->pdev))
5ffd3a52 1746 pcie_set_readrq(ha->pdev, 4096);
0107109e 1747
737faece 1748 pci_disable_rom(ha->pdev);
0107109e 1749
44c10138 1750 ha->chip_revision = ha->pdev->revision;
a8488abe 1751
0107109e
AV		 1752 /* Get PCI bus information. */
1753 spin_lock_irqsave(&ha->hardware_lock, flags);
1754 ha->pci_attr = RD_REG_DWORD(&reg->ctrl_status);
1755 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1756
1757 return QLA_SUCCESS;
1758}
1759
c3a2f0df
AV		 1760/**
1761 * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers.
1762 * @ha: HA context
1763 *
1764 * Returns 0 on success.
1765 */
1766int
e315cd28 1767qla25xx_pci_config(scsi_qla_host_t *vha)
c3a2f0df
AV		 1768{
1769 uint16_t w;
e315cd28 1770 struct qla_hw_data *ha = vha->hw;
c3a2f0df
AV		 1771
1772 pci_set_master(ha->pdev);
1773 pci_try_set_mwi(ha->pdev);
1774
1775 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
1776 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
1777 w &= ~PCI_COMMAND_INTX_DISABLE;
1778 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1779
1780 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 1781 if (pci_is_pcie(ha->pdev))
5ffd3a52 1782 pcie_set_readrq(ha->pdev, 4096);
c3a2f0df 1783
737faece 1784 pci_disable_rom(ha->pdev);
c3a2f0df
AV		 1785
1786 ha->chip_revision = ha->pdev->revision;
1787
1788 return QLA_SUCCESS;
1789}
1790
1da177e4
LT		 1791/**
1792 * qla2x00_isp_firmware() - Choose firmware image.
1793 * @ha: HA context
1794 *
1795 * Returns 0 on success.
1796 */
1797static int
e315cd28 1798qla2x00_isp_firmware(scsi_qla_host_t *vha)
1da177e4
LT		 1799{
1800 int rval;
42e421b1
AV		 1801 uint16_t loop_id, topo, sw_cap;
1802 uint8_t domain, area, al_pa;
e315cd28 1803 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 1804
1805 /* Assume loading risc code */
fa2a1ce5 1806 rval = QLA_FUNCTION_FAILED;
1da177e4
LT		 1807
1808 if (ha->flags.disable_risc_code_load) {
7c3df132 1809 ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n");
1da177e4
LT		 1810
1811 /* Verify checksum of loaded RISC code. */
e315cd28 1812 rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address);
42e421b1
AV		 1813 if (rval == QLA_SUCCESS) {
1814 /* And, verify we are not in ROM code. */
e315cd28 1815 rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa,
42e421b1
AV		 1816 &area, &domain, &topo, &sw_cap);
1817 }
1da177e4
LT		 1818 }
1819
7c3df132
SK		 1820 if (rval)
1821 ql_dbg(ql_dbg_init, vha, 0x007a,
1822 "**** Load RISC code ****.\n");
1da177e4
LT		 1823
1824 return (rval);
1825}
1826
1827/**
1828 * qla2x00_reset_chip() - Reset ISP chip.
1829 * @ha: HA context
1830 *
1831 * Returns 0 on success.
1832 */
abbd8870 1833void
e315cd28 1834qla2x00_reset_chip(scsi_qla_host_t *vha)
1da177e4
LT		 1835{
1836 unsigned long flags = 0;
e315cd28 1837 struct qla_hw_data *ha = vha->hw;
3d71644c 1838 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 1839 uint32_t cnt;
1da177e4
LT		 1840 uint16_t cmd;
1841
85880801
AV		 1842 if (unlikely(pci_channel_offline(ha->pdev)))
1843 return;
1844
fd34f556 1845 ha->isp_ops->disable_intrs(ha);
1da177e4
LT		 1846
1847 spin_lock_irqsave(&ha->hardware_lock, flags);
1848
1849 /* Turn off master enable */
1850 cmd = 0;
1851 pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd);
1852 cmd &= ~PCI_COMMAND_MASTER;
1853 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
1854
1855 if (!IS_QLA2100(ha)) {
1856 /* Pause RISC. */
1857 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1858 if (IS_QLA2200(ha) || IS_QLA2300(ha)) {
1859 for (cnt = 0; cnt < 30000; cnt++) {
1860 if ((RD_REG_WORD(&reg->hccr) &
1861 HCCR_RISC_PAUSE) != 0)
1862 break;
1863 udelay(100);
1864 }
1865 } else {
1866 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1867 udelay(10);
1868 }
1869
1870 /* Select FPM registers. */
1871 WRT_REG_WORD(&reg->ctrl_status, 0x20);
1872 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1873
1874 /* FPM Soft Reset. */
1875 WRT_REG_WORD(&reg->fpm_diag_config, 0x100);
1876 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
1877
1878 /* Toggle Fpm Reset. */
1879 if (!IS_QLA2200(ha)) {
1880 WRT_REG_WORD(&reg->fpm_diag_config, 0x0);
1881 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
1882 }
1883
1884 /* Select frame buffer registers. */
1885 WRT_REG_WORD(&reg->ctrl_status, 0x10);
1886 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1887
1888 /* Reset frame buffer FIFOs. */
1889 if (IS_QLA2200(ha)) {
1890 WRT_FB_CMD_REG(ha, reg, 0xa000);
1891 RD_FB_CMD_REG(ha, reg); /* PCI Posting. */
1892 } else {
1893 WRT_FB_CMD_REG(ha, reg, 0x00fc);
1894
1895 /* Read back fb_cmd until zero or 3 seconds max */
1896 for (cnt = 0; cnt < 3000; cnt++) {
1897 if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0)
1898 break;
1899 udelay(100);
1900 }
1901 }
1902
1903 /* Select RISC module registers. */
1904 WRT_REG_WORD(&reg->ctrl_status, 0);
1905 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1906
1907 /* Reset RISC processor. */
1908 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
1909 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1910
1911 /* Release RISC processor. */
1912 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
1913 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1914 }
1915
1916 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
1917 WRT_REG_WORD(&reg->hccr, HCCR_CLR_HOST_INT);
1918
1919 /* Reset ISP chip. */
1920 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1921
1922 /* Wait for RISC to recover from reset. */
1923 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1924 /*
1925 * It is necessary to for a delay here since the card doesn't
1926 * respond to PCI reads during a reset. On some architectures
1927 * this will result in an MCA.
1928 */
1929 udelay(20);
1930 for (cnt = 30000; cnt; cnt--) {
1931 if ((RD_REG_WORD(&reg->ctrl_status) &
1932 CSR_ISP_SOFT_RESET) == 0)
1933 break;
1934 udelay(100);
1935 }
1936 } else
1937 udelay(10);
1938
1939 /* Reset RISC processor. */
1940 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
1941
1942 WRT_REG_WORD(&reg->semaphore, 0);
1943
1944 /* Release RISC processor. */
1945 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
1946 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1947
1948 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1949 for (cnt = 0; cnt < 30000; cnt++) {
ffb39f03 1950 if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY)
1da177e4 1951 break;
1da177e4
LT		 1952
1953 udelay(100);
1954 }
1955 } else
1956 udelay(100);
1957
1958 /* Turn on master enable */
1959 cmd |= PCI_COMMAND_MASTER;
1960 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
1961
1962 /* Disable RISC pause on FPM parity error. */
1963 if (!IS_QLA2100(ha)) {
1964 WRT_REG_WORD(&reg->hccr, HCCR_DISABLE_PARITY_PAUSE);
1965 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1966 }
1967
1968 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1969}
1970
b1d46989
MI		 1971/**
1972 * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC.
1973 *
1974 * Returns 0 on success.
1975 */
fa492630 1976static int
b1d46989
MI		 1977qla81xx_reset_mpi(scsi_qla_host_t *vha)
1978{
1979 uint16_t mb[4] = {0x1010, 0, 1, 0};
1980
6246b8a1
GM		 1981 if (!IS_QLA81XX(vha->hw))
1982 return QLA_SUCCESS;
1983
b1d46989
MI		 1984 return qla81xx_write_mpi_register(vha, mb);
1985}
1986
0107109e 1987/**
88c26663 1988 * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC.
0107109e
AV		 1989 * @ha: HA context
1990 *
1991 * Returns 0 on success.
1992 */
d14e72fb 1993static inline int
e315cd28 1994qla24xx_reset_risc(scsi_qla_host_t *vha)
0107109e
AV		 1995{
1996 unsigned long flags = 0;
e315cd28 1997 struct qla_hw_data *ha = vha->hw;
0107109e 1998 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
52c82823 1999 uint32_t cnt;
335a1cc9 2000 uint16_t wd;
b1d46989 2001 static int abts_cnt; /* ISP abort retry counts */
d14e72fb 2002 int rval = QLA_SUCCESS;
0107109e 2003
0107109e
AV		 2004 spin_lock_irqsave(&ha->hardware_lock, flags);
2005
2006 /* Reset RISC. */
2007 WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
2008 for (cnt = 0; cnt < 30000; cnt++) {
2009 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
2010 break;
2011
2012 udelay(10);
2013 }
2014
d14e72fb
HM		 2015 if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE))
2016 set_bit(DMA_SHUTDOWN_CMPL, &ha->fw_dump_cap_flags);
2017
2018 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017e,
2019 "HCCR: 0x%x, Control Status %x, DMA active status:0x%x\n",
2020 RD_REG_DWORD(&reg->hccr),
2021 RD_REG_DWORD(&reg->ctrl_status),
2022 (RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE));
2023
0107109e
AV		 2024 WRT_REG_DWORD(&reg->ctrl_status,
2025 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
335a1cc9 2026 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
88c26663 2027
335a1cc9 2028 udelay(100);
d14e72fb 2029
88c26663 2030 /* Wait for firmware to complete NVRAM accesses. */
52c82823 2031 RD_REG_WORD(&reg->mailbox0);
d14e72fb
HM		 2032 for (cnt = 10000; RD_REG_WORD(&reg->mailbox0) != 0 &&
2033 rval == QLA_SUCCESS; cnt--) {
88c26663 2034 barrier();
d14e72fb
HM		 2035 if (cnt)
2036 udelay(5);
2037 else
2038 rval = QLA_FUNCTION_TIMEOUT;
88c26663
AV		 2039 }
2040
d14e72fb
HM		 2041 if (rval == QLA_SUCCESS)
2042 set_bit(ISP_MBX_RDY, &ha->fw_dump_cap_flags);
2043
2044 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017f,
2045 "HCCR: 0x%x, MailBox0 Status 0x%x\n",
2046 RD_REG_DWORD(&reg->hccr),
2047 RD_REG_DWORD(&reg->mailbox0));
2048
335a1cc9 2049 /* Wait for soft-reset to complete. */
52c82823 2050 RD_REG_DWORD(&reg->ctrl_status);
200ffb15 2051 for (cnt = 0; cnt < 60; cnt++) {
0107109e 2052 barrier();
d14e72fb
HM		 2053 if ((RD_REG_DWORD(&reg->ctrl_status) &
2054 CSRX_ISP_SOFT_RESET) == 0)
2055 break;
2056
2057 udelay(5);
0107109e 2058 }
d14e72fb
HM		 2059 if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_ISP_SOFT_RESET))
2060 set_bit(ISP_SOFT_RESET_CMPL, &ha->fw_dump_cap_flags);
2061
2062 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015d,
2063 "HCCR: 0x%x, Soft Reset status: 0x%x\n",
2064 RD_REG_DWORD(&reg->hccr),
2065 RD_REG_DWORD(&reg->ctrl_status));
0107109e 2066
b1d46989
MI		 2067 /* If required, do an MPI FW reset now */
2068 if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
2069 if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
2070 if (++abts_cnt < 5) {
2071 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2072 set_bit(MPI_RESET_NEEDED, &vha->dpc_flags);
2073 } else {
2074 /*
2075 * We exhausted the ISP abort retries. We have to
2076 * set the board offline.
2077 */
2078 abts_cnt = 0;
2079 vha->flags.online = 0;
2080 }
2081 }
2082 }
2083
0107109e
AV		 2084 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
2085 RD_REG_DWORD(&reg->hccr);
2086
2087 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
2088 RD_REG_DWORD(&reg->hccr);
2089
2090 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
2091 RD_REG_DWORD(&reg->hccr);
2092
52c82823 2093 RD_REG_WORD(&reg->mailbox0);
200ffb15 2094 for (cnt = 60; RD_REG_WORD(&reg->mailbox0) != 0 &&
d14e72fb 2095 rval == QLA_SUCCESS; cnt--) {
0107109e 2096 barrier();
d14e72fb
HM		 2097 if (cnt)
2098 udelay(5);
2099 else
2100 rval = QLA_FUNCTION_TIMEOUT;
0107109e 2101 }
d14e72fb
HM		 2102 if (rval == QLA_SUCCESS)
2103 set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags);
2104
2105 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015e,
2106 "Host Risc 0x%x, mailbox0 0x%x\n",
2107 RD_REG_DWORD(&reg->hccr),
2108 RD_REG_WORD(&reg->mailbox0));
0107109e
AV		 2109
2110 spin_unlock_irqrestore(&ha->hardware_lock, flags);
124f85e6 2111
d14e72fb
HM		 2112 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015f,
2113 "Driver in %s mode\n",
2114 IS_NOPOLLING_TYPE(ha) ? "Interrupt" : "Polling");
2115
124f85e6
AV		 2116 if (IS_NOPOLLING_TYPE(ha))
2117 ha->isp_ops->enable_intrs(ha);
d14e72fb
HM		 2118
2119 return rval;
0107109e
AV		 2120}
2121
4ea2c9c7
JC		 2122static void
2123qla25xx_read_risc_sema_reg(scsi_qla_host_t *vha, uint32_t *data)
2124{
2125 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
2126
2127 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
2128 *data = RD_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET);
2129
2130}
2131
2132static void
2133qla25xx_write_risc_sema_reg(scsi_qla_host_t *vha, uint32_t data)
2134{
2135 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
2136
2137 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
2138 WRT_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET, data);
2139}
2140
2141static void
2142qla25xx_manipulate_risc_semaphore(scsi_qla_host_t *vha)
2143{
4ea2c9c7
JC		 2144 uint32_t wd32 = 0;
2145 uint delta_msec = 100;
2146 uint elapsed_msec = 0;
2147 uint timeout_msec;
2148 ulong n;
2149
cc790764
JC		 2150 if (vha->hw->pdev->subsystem_device != 0x0175 &&
2151 vha->hw->pdev->subsystem_device != 0x0240)
4ea2c9c7
JC		 2152 return;
2153
8dd7e3a5
JC		 2154 WRT_REG_DWORD(&vha->hw->iobase->isp24.hccr, HCCRX_SET_RISC_PAUSE);
2155 udelay(100);
2156
4ea2c9c7
JC		 2157attempt:
2158 timeout_msec = TIMEOUT_SEMAPHORE;
2159 n = timeout_msec / delta_msec;
2160 while (n--) {
2161 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_SET);
2162 qla25xx_read_risc_sema_reg(vha, &wd32);
2163 if (wd32 & RISC_SEMAPHORE)
2164 break;
2165 msleep(delta_msec);
2166 elapsed_msec += delta_msec;
2167 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
2168 goto force;
2169 }
2170
2171 if (!(wd32 & RISC_SEMAPHORE))
2172 goto force;
2173
2174 if (!(wd32 & RISC_SEMAPHORE_FORCE))
2175 goto acquired;
2176
2177 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_CLR);
2178 timeout_msec = TIMEOUT_SEMAPHORE_FORCE;
2179 n = timeout_msec / delta_msec;
2180 while (n--) {
2181 qla25xx_read_risc_sema_reg(vha, &wd32);
2182 if (!(wd32 & RISC_SEMAPHORE_FORCE))
2183 break;
2184 msleep(delta_msec);
2185 elapsed_msec += delta_msec;
2186 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
2187 goto force;
2188 }
2189
2190 if (wd32 & RISC_SEMAPHORE_FORCE)
2191 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_CLR);
2192
2193 goto attempt;
2194
2195force:
2196 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_SET);
2197
2198acquired:
2199 return;
2200}
2201
88c26663
AV		 2202/**
2203 * qla24xx_reset_chip() - Reset ISP24xx chip.
2204 * @ha: HA context
2205 *
2206 * Returns 0 on success.
2207 */
2208void
e315cd28 2209qla24xx_reset_chip(scsi_qla_host_t *vha)
88c26663 2210{
e315cd28 2211 struct qla_hw_data *ha = vha->hw;
85880801
AV		 2212
2213 if (pci_channel_offline(ha->pdev) &&
2214 ha->flags.pci_channel_io_perm_failure) {
2215 return;
2216 }
2217
fd34f556 2218 ha->isp_ops->disable_intrs(ha);
88c26663 2219
4ea2c9c7
JC		 2220 qla25xx_manipulate_risc_semaphore(vha);
2221
88c26663 2222 /* Perform RISC reset. */
e315cd28 2223 qla24xx_reset_risc(vha);
88c26663
AV		 2224}
2225
1da177e4
LT		 2226/**
2227 * qla2x00_chip_diag() - Test chip for proper operation.
2228 * @ha: HA context
2229 *
2230 * Returns 0 on success.
2231 */
abbd8870 2232int
e315cd28 2233qla2x00_chip_diag(scsi_qla_host_t *vha)
1da177e4
LT		 2234{
2235 int rval;
e315cd28 2236 struct qla_hw_data *ha = vha->hw;
3d71644c 2237 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 2238 unsigned long flags = 0;
2239 uint16_t data;
2240 uint32_t cnt;
2241 uint16_t mb[5];
73208dfd 2242 struct req_que *req = ha->req_q_map[0];
1da177e4
LT		 2243
2244 /* Assume a failed state */
2245 rval = QLA_FUNCTION_FAILED;
2246
7c3df132
SK		 2247 ql_dbg(ql_dbg_init, vha, 0x007b,
2248 "Testing device at %lx.\n", (u_long)&reg->flash_address);
1da177e4
LT		 2249
2250 spin_lock_irqsave(&ha->hardware_lock, flags);
2251
2252 /* Reset ISP chip. */
2253 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
2254
2255 /*
2256 * We need to have a delay here since the card will not respond while
2257 * in reset causing an MCA on some architectures.
2258 */
2259 udelay(20);
2260 data = qla2x00_debounce_register(&reg->ctrl_status);
2261 for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {
2262 udelay(5);
2263 data = RD_REG_WORD(&reg->ctrl_status);
2264 barrier();
2265 }
2266
2267 if (!cnt)
2268 goto chip_diag_failed;
2269
7c3df132
SK		 2270 ql_dbg(ql_dbg_init, vha, 0x007c,
2271 "Reset register cleared by chip reset.\n");
1da177e4
LT		 2272
2273 /* Reset RISC processor. */
2274 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
2275 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
2276
2277 /* Workaround for QLA2312 PCI parity error */
2278 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
2279 data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0));
2280 for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) {
2281 udelay(5);
2282 data = RD_MAILBOX_REG(ha, reg, 0);
fa2a1ce5 2283 barrier();
1da177e4
LT		 2284 }
2285 } else
2286 udelay(10);
2287
2288 if (!cnt)
2289 goto chip_diag_failed;
2290
2291 /* Check product ID of chip */
5a68a1c2 2292 ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product ID of chip.\n");
1da177e4
LT		 2293
2294 mb[1] = RD_MAILBOX_REG(ha, reg, 1);
2295 mb[2] = RD_MAILBOX_REG(ha, reg, 2);
2296 mb[3] = RD_MAILBOX_REG(ha, reg, 3);
2297 mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4));
2298 if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) ||
2299 mb[3] != PROD_ID_3) {
7c3df132
SK		 2300 ql_log(ql_log_warn, vha, 0x0062,
2301 "Wrong product ID = 0x%x,0x%x,0x%x.\n",
2302 mb[1], mb[2], mb[3]);
1da177e4
LT		 2303
2304 goto chip_diag_failed;
2305 }
2306 ha->product_id[0] = mb[1];
2307 ha->product_id[1] = mb[2];
2308 ha->product_id[2] = mb[3];
2309 ha->product_id[3] = mb[4];
2310
2311 /* Adjust fw RISC transfer size */
73208dfd 2312 if (req->length > 1024)
1da177e4
LT		 2313 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024;
2314 else
2315 ha->fw_transfer_size = REQUEST_ENTRY_SIZE *
73208dfd 2316 req->length;
1da177e4
LT		 2317
2318 if (IS_QLA2200(ha) &&
2319 RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) {
2320 /* Limit firmware transfer size with a 2200A */
7c3df132 2321 ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n");
1da177e4 2322
ea5b6382 2323 ha->device_type |= DT_ISP2200A;
1da177e4
LT		 2324 ha->fw_transfer_size = 128;
2325 }
2326
2327 /* Wrap Incoming Mailboxes Test. */
2328 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2329
7c3df132 2330 ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n");
e315cd28 2331 rval = qla2x00_mbx_reg_test(vha);
7c3df132
SK		 2332 if (rval)
2333 ql_log(ql_log_warn, vha, 0x0080,
2334 "Failed mailbox send register test.\n");
2335 else
1da177e4
LT		 2336 /* Flag a successful rval */
2337 rval = QLA_SUCCESS;
1da177e4
LT		 2338 spin_lock_irqsave(&ha->hardware_lock, flags);
2339
2340chip_diag_failed:
2341 if (rval)
7c3df132
SK		 2342 ql_log(ql_log_info, vha, 0x0081,
2343 "Chip diagnostics **** FAILED ****.\n");
1da177e4
LT		 2344
2345 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2346
2347 return (rval);
2348}
2349
0107109e
AV		 2350/**
2351 * qla24xx_chip_diag() - Test ISP24xx for proper operation.
2352 * @ha: HA context
2353 *
2354 * Returns 0 on success.
2355 */
2356int
e315cd28 2357qla24xx_chip_diag(scsi_qla_host_t *vha)
0107109e
AV		 2358{
2359 int rval;
e315cd28 2360 struct qla_hw_data *ha = vha->hw;
73208dfd 2361 struct req_que *req = ha->req_q_map[0];
0107109e 2362
7ec0effd 2363 if (IS_P3P_TYPE(ha))
a9083016
GM		 2364 return QLA_SUCCESS;
2365
73208dfd 2366 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
0107109e 2367
e315cd28 2368 rval = qla2x00_mbx_reg_test(vha);
0107109e 2369 if (rval) {
7c3df132
SK		 2370 ql_log(ql_log_warn, vha, 0x0082,
2371 "Failed mailbox send register test.\n");
0107109e
AV		 2372 } else {
2373 /* Flag a successful rval */
2374 rval = QLA_SUCCESS;
2375 }
2376
2377 return rval;
2378}
2379
a7a167bf 2380void
e315cd28 2381qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
0107109e 2382{
a7a167bf
AV		 2383 int rval;
2384 uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
73208dfd 2385 eft_size, fce_size, mq_size;
df613b96
AV		 2386 dma_addr_t tc_dma;
2387 void *tc;
e315cd28 2388 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 2389 struct req_que *req = ha->req_q_map[0];
2390 struct rsp_que *rsp = ha->rsp_q_map[0];
a7a167bf
AV		 2391
2392 if (ha->fw_dump) {
7c3df132
SK		 2393 ql_dbg(ql_dbg_init, vha, 0x00bd,
2394 "Firmware dump already allocated.\n");
a7a167bf
AV		 2395 return;
2396 }
d4e3e04d 2397
0107109e 2398 ha->fw_dumped = 0;
61f098dd 2399 ha->fw_dump_cap_flags = 0;
f73cb695
CD		 2400 dump_size = fixed_size = mem_size = eft_size = fce_size = mq_size = 0;
2401 req_q_size = rsp_q_size = 0;
2402
2403 if (IS_QLA27XX(ha))
2404 goto try_fce;
2405
d4e3e04d 2406 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
a7a167bf 2407 fixed_size = sizeof(struct qla2100_fw_dump);
d4e3e04d 2408 } else if (IS_QLA23XX(ha)) {
a7a167bf
AV		 2409 fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
2410 mem_size = (ha->fw_memory_size - 0x11000 + 1) *
2411 sizeof(uint16_t);
e428924c 2412 } else if (IS_FWI2_CAPABLE(ha)) {
b20f02e1 2413 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
6246b8a1
GM		 2414 fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem);
2415 else if (IS_QLA81XX(ha))
3a03eb79
AV		 2416 fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
2417 else if (IS_QLA25XX(ha))
2418 fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
2419 else
2420 fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
f73cb695 2421
a7a167bf
AV		 2422 mem_size = (ha->fw_memory_size - 0x100000 + 1) *
2423 sizeof(uint32_t);
050c9bb1 2424 if (ha->mqenable) {
b20f02e1 2425 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
6246b8a1 2426 mq_size = sizeof(struct qla2xxx_mq_chain);
050c9bb1
GM		 2427 /*
2428 * Allocate maximum buffer size for all queues.
2429 * Resizing must be done at end-of-dump processing.
2430 */
2431 mq_size += ha->max_req_queues *
2432 (req->length * sizeof(request_t));
2433 mq_size += ha->max_rsp_queues *
2434 (rsp->length * sizeof(response_t));
2435 }
00876ae8 2436 if (ha->tgt.atio_ring)
2d70c103 2437 mq_size += ha->tgt.atio_q_length * sizeof(request_t);
df613b96 2438 /* Allocate memory for Fibre Channel Event Buffer. */
f73cb695
CD		 2439 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
2440 !IS_QLA27XX(ha))
436a7b11 2441 goto try_eft;
df613b96 2442
f73cb695
CD		 2443try_fce:
2444 if (ha->fce)
2445 dma_free_coherent(&ha->pdev->dev,
2446 FCE_SIZE, ha->fce, ha->fce_dma);
2447
2448 /* Allocate memory for Fibre Channel Event Buffer. */
0ea85b50
JP		 2449 tc = dma_zalloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
2450 GFP_KERNEL);
df613b96 2451 if (!tc) {
7c3df132
SK		 2452 ql_log(ql_log_warn, vha, 0x00be,
2453 "Unable to allocate (%d KB) for FCE.\n",
2454 FCE_SIZE / 1024);
17d98630 2455 goto try_eft;
df613b96
AV		 2456 }
2457
e315cd28 2458 rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS,
df613b96
AV		 2459 ha->fce_mb, &ha->fce_bufs);
2460 if (rval) {
7c3df132
SK		 2461 ql_log(ql_log_warn, vha, 0x00bf,
2462 "Unable to initialize FCE (%d).\n", rval);
df613b96
AV		 2463 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc,
2464 tc_dma);
2465 ha->flags.fce_enabled = 0;
17d98630 2466 goto try_eft;
df613b96 2467 }
cfb0919c 2468 ql_dbg(ql_dbg_init, vha, 0x00c0,
7c3df132 2469 "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024);
df613b96 2470
7d9dade3 2471 fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE;
df613b96
AV		 2472 ha->flags.fce_enabled = 1;
2473 ha->fce_dma = tc_dma;
2474 ha->fce = tc;
f73cb695 2475
436a7b11 2476try_eft:
f73cb695
CD		 2477 if (ha->eft)
2478 dma_free_coherent(&ha->pdev->dev,
2479 EFT_SIZE, ha->eft, ha->eft_dma);
2480
436a7b11 2481 /* Allocate memory for Extended Trace Buffer. */
0ea85b50
JP		 2482 tc = dma_zalloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
2483 GFP_KERNEL);
436a7b11 2484 if (!tc) {
7c3df132
SK		 2485 ql_log(ql_log_warn, vha, 0x00c1,
2486 "Unable to allocate (%d KB) for EFT.\n",
2487 EFT_SIZE / 1024);
436a7b11
AV		 2488 goto cont_alloc;
2489 }
2490
e315cd28 2491 rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
436a7b11 2492 if (rval) {
7c3df132
SK		 2493 ql_log(ql_log_warn, vha, 0x00c2,
2494 "Unable to initialize EFT (%d).\n", rval);
436a7b11
AV		 2495 dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc,
2496 tc_dma);
2497 goto cont_alloc;
2498 }
cfb0919c 2499 ql_dbg(ql_dbg_init, vha, 0x00c3,
7c3df132 2500 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
436a7b11
AV		 2501
2502 eft_size = EFT_SIZE;
2503 ha->eft_dma = tc_dma;
2504 ha->eft = tc;
d4e3e04d 2505 }
f73cb695 2506
a7a167bf 2507cont_alloc:
f73cb695
CD		 2508 if (IS_QLA27XX(ha)) {
2509 if (!ha->fw_dump_template) {
2510 ql_log(ql_log_warn, vha, 0x00ba,
2511 "Failed missing fwdump template\n");
2512 return;
2513 }
2514 dump_size = qla27xx_fwdt_calculate_dump_size(vha);
2515 ql_dbg(ql_dbg_init, vha, 0x00fa,
2516 "-> allocating fwdump (%x bytes)...\n", dump_size);
2517 goto allocate;
2518 }
2519
73208dfd
AC		 2520 req_q_size = req->length * sizeof(request_t);
2521 rsp_q_size = rsp->length * sizeof(response_t);
a7a167bf 2522 dump_size = offsetof(struct qla2xxx_fw_dump, isp);
2afa19a9 2523 dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size;
bb99de67
AV		 2524 ha->chain_offset = dump_size;
2525 dump_size += mq_size + fce_size;
d4e3e04d 2526
f73cb695 2527allocate:
d4e3e04d 2528 ha->fw_dump = vmalloc(dump_size);
a7a167bf 2529 if (!ha->fw_dump) {
7c3df132
SK		 2530 ql_log(ql_log_warn, vha, 0x00c4,
2531 "Unable to allocate (%d KB) for firmware dump.\n",
2532 dump_size / 1024);
a7a167bf 2533
e30d1756
MI		 2534 if (ha->fce) {
2535 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
2536 ha->fce_dma);
2537 ha->fce = NULL;
2538 ha->fce_dma = 0;
2539 }
2540
a7a167bf
AV		 2541 if (ha->eft) {
2542 dma_free_coherent(&ha->pdev->dev, eft_size, ha->eft,
2543 ha->eft_dma);
2544 ha->eft = NULL;
2545 ha->eft_dma = 0;
2546 }
2547 return;
2548 }
f73cb695 2549 ha->fw_dump_len = dump_size;
cfb0919c 2550 ql_dbg(ql_dbg_init, vha, 0x00c5,
7c3df132 2551 "Allocated (%d KB) for firmware dump.\n", dump_size / 1024);
a7a167bf 2552
f73cb695
CD		 2553 if (IS_QLA27XX(ha))
2554 return;
2555
a7a167bf
AV		 2556 ha->fw_dump->signature[0] = 'Q';
2557 ha->fw_dump->signature[1] = 'L';
2558 ha->fw_dump->signature[2] = 'G';
2559 ha->fw_dump->signature[3] = 'C';
ad950360 2560 ha->fw_dump->version = htonl(1);
a7a167bf
AV		 2561
2562 ha->fw_dump->fixed_size = htonl(fixed_size);
2563 ha->fw_dump->mem_size = htonl(mem_size);
2564 ha->fw_dump->req_q_size = htonl(req_q_size);
2565 ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
2566
2567 ha->fw_dump->eft_size = htonl(eft_size);
2568 ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma));
2569 ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma));
2570
2571 ha->fw_dump->header_size =
2572 htonl(offsetof(struct qla2xxx_fw_dump, isp));
0107109e
AV		 2573}
2574
18e7555a
AV		 2575static int
2576qla81xx_mpi_sync(scsi_qla_host_t *vha)
2577{
2578#define MPS_MASK 0xe0
2579 int rval;
2580 uint16_t dc;
2581 uint32_t dw;
18e7555a
AV		 2582
2583 if (!IS_QLA81XX(vha->hw))
2584 return QLA_SUCCESS;
2585
2586 rval = qla2x00_write_ram_word(vha, 0x7c00, 1);
2587 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2588 ql_log(ql_log_warn, vha, 0x0105,
2589 "Unable to acquire semaphore.\n");
18e7555a
AV		 2590 goto done;
2591 }
2592
2593 pci_read_config_word(vha->hw->pdev, 0x54, &dc);
2594 rval = qla2x00_read_ram_word(vha, 0x7a15, &dw);
2595 if (rval != QLA_SUCCESS) {
7c3df132 2596 ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n");
18e7555a
AV		 2597 goto done_release;
2598 }
2599
2600 dc &= MPS_MASK;
2601 if (dc == (dw & MPS_MASK))
2602 goto done_release;
2603
2604 dw &= ~MPS_MASK;
2605 dw |= dc;
2606 rval = qla2x00_write_ram_word(vha, 0x7a15, dw);
2607 if (rval != QLA_SUCCESS) {
7c3df132 2608 ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n");
18e7555a
AV		 2609 }
2610
2611done_release:
2612 rval = qla2x00_write_ram_word(vha, 0x7c00, 0);
2613 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2614 ql_log(ql_log_warn, vha, 0x006d,
2615 "Unable to release semaphore.\n");
18e7555a
AV		 2616 }
2617
2618done:
2619 return rval;
2620}
2621
8d93f550
CD		 2622int
2623qla2x00_alloc_outstanding_cmds(struct qla_hw_data *ha, struct req_que *req)
2624{
2625 /* Don't try to reallocate the array */
2626 if (req->outstanding_cmds)
2627 return QLA_SUCCESS;
2628
d7459527 2629 if (!IS_FWI2_CAPABLE(ha))
8d93f550
CD		 2630 req->num_outstanding_cmds = DEFAULT_OUTSTANDING_COMMANDS;
2631 else {
03e8c680
QT		 2632 if (ha->cur_fw_xcb_count <= ha->cur_fw_iocb_count)
2633 req->num_outstanding_cmds = ha->cur_fw_xcb_count;
8d93f550 2634 else
03e8c680 2635 req->num_outstanding_cmds = ha->cur_fw_iocb_count;
8d93f550
CD		 2636 }
2637
2638 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
2639 req->num_outstanding_cmds, GFP_KERNEL);
2640
2641 if (!req->outstanding_cmds) {
2642 /*
2643 * Try to allocate a minimal size just so we can get through
2644 * initialization.
2645 */
2646 req->num_outstanding_cmds = MIN_OUTSTANDING_COMMANDS;
2647 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
2648 req->num_outstanding_cmds, GFP_KERNEL);
2649
2650 if (!req->outstanding_cmds) {
2651 ql_log(ql_log_fatal, NULL, 0x0126,
2652 "Failed to allocate memory for "
2653 "outstanding_cmds for req_que %p.\n", req);
2654 req->num_outstanding_cmds = 0;
2655 return QLA_FUNCTION_FAILED;
2656 }
2657 }
2658
2659 return QLA_SUCCESS;
2660}
2661
1da177e4
LT		 2662/**
2663 * qla2x00_setup_chip() - Load and start RISC firmware.
2664 * @ha: HA context
2665 *
2666 * Returns 0 on success.
2667 */
2668static int
e315cd28 2669qla2x00_setup_chip(scsi_qla_host_t *vha)
1da177e4 2670{
0107109e
AV		 2671 int rval;
2672 uint32_t srisc_address = 0;
e315cd28 2673 struct qla_hw_data *ha = vha->hw;
3db0652e
AV		 2674 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2675 unsigned long flags;
dda772e8 2676 uint16_t fw_major_version;
3db0652e 2677
7ec0effd 2678 if (IS_P3P_TYPE(ha)) {
a9083016 2679 rval = ha->isp_ops->load_risc(vha, &srisc_address);
14e303d9
AV		 2680 if (rval == QLA_SUCCESS) {
2681 qla2x00_stop_firmware(vha);
a9083016 2682 goto enable_82xx_npiv;
14e303d9 2683 } else
b963752f 2684 goto failed;
a9083016
GM		 2685 }
2686
3db0652e
AV		 2687 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
2688 /* Disable SRAM, Instruction RAM and GP RAM parity. */
2689 spin_lock_irqsave(&ha->hardware_lock, flags);
2690 WRT_REG_WORD(&reg->hccr, (HCCR_ENABLE_PARITY + 0x0));
2691 RD_REG_WORD(&reg->hccr);
2692 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2693 }
1da177e4 2694
18e7555a
AV		 2695 qla81xx_mpi_sync(vha);
2696
1da177e4 2697 /* Load firmware sequences */
e315cd28 2698 rval = ha->isp_ops->load_risc(vha, &srisc_address);
0107109e 2699 if (rval == QLA_SUCCESS) {
7c3df132
SK		 2700 ql_dbg(ql_dbg_init, vha, 0x00c9,
2701 "Verifying Checksum of loaded RISC code.\n");
1da177e4 2702
e315cd28 2703 rval = qla2x00_verify_checksum(vha, srisc_address);
1da177e4
LT		 2704 if (rval == QLA_SUCCESS) {
2705 /* Start firmware execution. */
7c3df132
SK		 2706 ql_dbg(ql_dbg_init, vha, 0x00ca,
2707 "Starting firmware.\n");
1da177e4 2708
b0d6cabd
HM		 2709 if (ql2xexlogins)
2710 ha->flags.exlogins_enabled = 1;
2711
2f56a7f1
HM		 2712 if (ql2xexchoffld)
2713 ha->flags.exchoffld_enabled = 1;
2714
e315cd28 2715 rval = qla2x00_execute_fw(vha, srisc_address);
1da177e4 2716 /* Retrieve firmware information. */
dda772e8 2717 if (rval == QLA_SUCCESS) {
b0d6cabd
HM		 2718 rval = qla2x00_set_exlogins_buffer(vha);
2719 if (rval != QLA_SUCCESS)
2720 goto failed;
2721
2f56a7f1
HM		 2722 rval = qla2x00_set_exchoffld_buffer(vha);
2723 if (rval != QLA_SUCCESS)
2724 goto failed;
2725
a9083016 2726enable_82xx_npiv:
dda772e8 2727 fw_major_version = ha->fw_major_version;
7ec0effd 2728 if (IS_P3P_TYPE(ha))
3173167f 2729 qla82xx_check_md_needed(vha);
6246b8a1
GM		 2730 else
2731 rval = qla2x00_get_fw_version(vha);
ca9e9c3e
AV		 2732 if (rval != QLA_SUCCESS)
2733 goto failed;
2c3dfe3f 2734 ha->flags.npiv_supported = 0;
e315cd28 2735 if (IS_QLA2XXX_MIDTYPE(ha) &&
946fb891 2736 (ha->fw_attributes & BIT_2)) {
2c3dfe3f 2737 ha->flags.npiv_supported = 1;
4d0ea247
SJ		 2738 if ((!ha->max_npiv_vports) ||
2739 ((ha->max_npiv_vports + 1) %
eb66dc60 2740 MIN_MULTI_ID_FABRIC))
4d0ea247 2741 ha->max_npiv_vports =
eb66dc60 2742 MIN_MULTI_ID_FABRIC - 1;
4d0ea247 2743 }
03e8c680 2744 qla2x00_get_resource_cnts(vha);
d743de66 2745
8d93f550
CD		 2746 /*
2747 * Allocate the array of outstanding commands
2748 * now that we know the firmware resources.
2749 */
2750 rval = qla2x00_alloc_outstanding_cmds(ha,
2751 vha->req);
2752 if (rval != QLA_SUCCESS)
2753 goto failed;
2754
be5ea3cf 2755 if (!fw_major_version && ql2xallocfwdump
7ec0effd 2756 && !(IS_P3P_TYPE(ha)))
08de2844 2757 qla2x00_alloc_fw_dump(vha);
3b6e5b9d
CD		 2758 } else {
2759 goto failed;
1da177e4
LT		 2760 }
2761 } else {
7c3df132
SK		 2762 ql_log(ql_log_fatal, vha, 0x00cd,
2763 "ISP Firmware failed checksum.\n");
2764 goto failed;
1da177e4 2765 }
c74d88a4
AV		 2766 } else
2767 goto failed;
1da177e4 2768
3db0652e
AV		 2769 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
2770 /* Enable proper parity. */
2771 spin_lock_irqsave(&ha->hardware_lock, flags);
2772 if (IS_QLA2300(ha))
2773 /* SRAM parity */
2774 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x1);
2775 else
2776 /* SRAM, Instruction RAM and GP RAM parity */
2777 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x7);
2778 RD_REG_WORD(&reg->hccr);
2779 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2780 }
2781
f3982d89
CD		 2782 if (IS_QLA27XX(ha))
2783 ha->flags.fac_supported = 1;
2784 else if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
1d2874de
JC		 2785 uint32_t size;
2786
2787 rval = qla81xx_fac_get_sector_size(vha, &size);
2788 if (rval == QLA_SUCCESS) {
2789 ha->flags.fac_supported = 1;
2790 ha->fdt_block_size = size << 2;
2791 } else {
7c3df132 2792 ql_log(ql_log_warn, vha, 0x00ce,
1d2874de
JC		 2793 "Unsupported FAC firmware (%d.%02d.%02d).\n",
2794 ha->fw_major_version, ha->fw_minor_version,
2795 ha->fw_subminor_version);
1ca60e3b 2796
f73cb695 2797 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
6246b8a1
GM		 2798 ha->flags.fac_supported = 0;
2799 rval = QLA_SUCCESS;
2800 }
1d2874de
JC		 2801 }
2802 }
ca9e9c3e 2803failed:
1da177e4 2804 if (rval) {
7c3df132
SK		 2805 ql_log(ql_log_fatal, vha, 0x00cf,
2806 "Setup chip ****FAILED****.\n");
1da177e4
LT		 2807 }
2808
2809 return (rval);
2810}
2811
2812/**
2813 * qla2x00_init_response_q_entries() - Initializes response queue entries.
2814 * @ha: HA context
2815 *
2816 * Beginning of request ring has initialization control block already built
2817 * by nvram config routine.
2818 *
2819 * Returns 0 on success.
2820 */
73208dfd
AC		 2821void
2822qla2x00_init_response_q_entries(struct rsp_que *rsp)
1da177e4
LT		 2823{
2824 uint16_t cnt;
2825 response_t *pkt;
2826
2afa19a9
AC		 2827 rsp->ring_ptr = rsp->ring;
2828 rsp->ring_index = 0;
2829 rsp->status_srb = NULL;
e315cd28
AC		 2830 pkt = rsp->ring_ptr;
2831 for (cnt = 0; cnt < rsp->length; cnt++) {
1da177e4
LT		 2832 pkt->signature = RESPONSE_PROCESSED;
2833 pkt++;
2834 }
1da177e4
LT		 2835}
2836
2837/**
2838 * qla2x00_update_fw_options() - Read and process firmware options.
2839 * @ha: HA context
2840 *
2841 * Returns 0 on success.
2842 */
abbd8870 2843void
e315cd28 2844qla2x00_update_fw_options(scsi_qla_host_t *vha)
1da177e4
LT		 2845{
2846 uint16_t swing, emphasis, tx_sens, rx_sens;
e315cd28 2847 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2848
2849 memset(ha->fw_options, 0, sizeof(ha->fw_options));
e315cd28 2850 qla2x00_get_fw_options(vha, ha->fw_options);
1da177e4
LT		 2851
2852 if (IS_QLA2100(ha) || IS_QLA2200(ha))
2853 return;
2854
2855 /* Serial Link options. */
7c3df132
SK		 2856 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
2857 "Serial link options.\n");
2858 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
2859 (uint8_t *)&ha->fw_seriallink_options,
2860 sizeof(ha->fw_seriallink_options));
1da177e4
LT		 2861
2862 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
2863 if (ha->fw_seriallink_options[3] & BIT_2) {
2864 ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING;
2865
2866 /* 1G settings */
2867 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
2868 emphasis = (ha->fw_seriallink_options[2] &
2869 (BIT_4 | BIT_3)) >> 3;
2870 tx_sens = ha->fw_seriallink_options[0] &
fa2a1ce5 2871 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 2872 rx_sens = (ha->fw_seriallink_options[0] &
2873 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
2874 ha->fw_options[10] = (emphasis << 14) | (swing << 8);
2875 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
2876 if (rx_sens == 0x0)
2877 rx_sens = 0x3;
2878 ha->fw_options[10] |= (tx_sens << 4) | rx_sens;
2879 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
2880 ha->fw_options[10] |= BIT_5 |
2881 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
2882 (tx_sens & (BIT_1 | BIT_0));
2883
2884 /* 2G settings */
2885 swing = (ha->fw_seriallink_options[2] &
2886 (BIT_7 | BIT_6 | BIT_5)) >> 5;
2887 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
2888 tx_sens = ha->fw_seriallink_options[1] &
fa2a1ce5 2889 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 2890 rx_sens = (ha->fw_seriallink_options[1] &
2891 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
2892 ha->fw_options[11] = (emphasis << 14) | (swing << 8);
2893 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
2894 if (rx_sens == 0x0)
2895 rx_sens = 0x3;
2896 ha->fw_options[11] |= (tx_sens << 4) | rx_sens;
2897 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
2898 ha->fw_options[11] |= BIT_5 |
2899 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
2900 (tx_sens & (BIT_1 | BIT_0));
2901 }
2902
2903 /* FCP2 options. */
2904 /* Return command IOCBs without waiting for an ABTS to complete. */
2905 ha->fw_options[3] |= BIT_13;
2906
2907 /* LED scheme. */
2908 if (ha->flags.enable_led_scheme)
2909 ha->fw_options[2] |= BIT_12;
2910
48c02fde
AV		 2911 /* Detect ISP6312. */
2912 if (IS_QLA6312(ha))
2913 ha->fw_options[2] |= BIT_13;
2914
088d09d4
GM		 2915 /* Set Retry FLOGI in case of P2P connection */
2916 if (ha->operating_mode == P2P) {
2917 ha->fw_options[2] |= BIT_3;
2918 ql_dbg(ql_dbg_disc, vha, 0x2100,
2919 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
2920 __func__, ha->fw_options[2]);
2921 }
2922
1da177e4 2923 /* Update firmware options. */
e315cd28 2924 qla2x00_set_fw_options(vha, ha->fw_options);
1da177e4
LT		 2925}
2926
0107109e 2927void
e315cd28 2928qla24xx_update_fw_options(scsi_qla_host_t *vha)
0107109e
AV		 2929{
2930 int rval;
e315cd28 2931 struct qla_hw_data *ha = vha->hw;
0107109e 2932
7ec0effd 2933 if (IS_P3P_TYPE(ha))
a9083016
GM		 2934 return;
2935
f198cafa
HM		 2936 /* Hold status IOCBs until ABTS response received. */
2937 if (ql2xfwholdabts)
2938 ha->fw_options[3] |= BIT_12;
2939
088d09d4
GM		 2940 /* Set Retry FLOGI in case of P2P connection */
2941 if (ha->operating_mode == P2P) {
2942 ha->fw_options[2] |= BIT_3;
2943 ql_dbg(ql_dbg_disc, vha, 0x2101,
2944 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
2945 __func__, ha->fw_options[2]);
2946 }
2947
41dc529a 2948 /* Move PUREX, ABTS RX & RIDA to ATIOQ */
3c4810ff
QT		 2949 if (ql2xmvasynctoatio &&
2950 (IS_QLA83XX(ha) || IS_QLA27XX(ha))) {
41dc529a
QT		 2951 if (qla_tgt_mode_enabled(vha) ||
2952 qla_dual_mode_enabled(vha))
2953 ha->fw_options[2] |= BIT_11;
2954 else
2955 ha->fw_options[2] &= ~BIT_11;
2956 }
2957
2958 ql_dbg(ql_dbg_init, vha, 0xffff,
2959 "%s, add FW options 1-3 = 0x%04x 0x%04x 0x%04x mode %x\n",
2960 __func__, ha->fw_options[1], ha->fw_options[2],
2961 ha->fw_options[3], vha->host->active_mode);
3c4810ff
QT		 2962
2963 if (ha->fw_options[1] || ha->fw_options[2] || ha->fw_options[3])
2964 qla2x00_set_fw_options(vha, ha->fw_options);
41dc529a 2965
0107109e 2966 /* Update Serial Link options. */
f94097ed 2967 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0)
0107109e
AV		 2968 return;
2969
e315cd28 2970 rval = qla2x00_set_serdes_params(vha,
f94097ed
AV		 2971 le16_to_cpu(ha->fw_seriallink_options24[1]),
2972 le16_to_cpu(ha->fw_seriallink_options24[2]),
2973 le16_to_cpu(ha->fw_seriallink_options24[3]));
0107109e 2974 if (rval != QLA_SUCCESS) {
7c3df132 2975 ql_log(ql_log_warn, vha, 0x0104,
0107109e
AV		 2976 "Unable to update Serial Link options (%x).\n", rval);
2977 }
2978}
2979
abbd8870 2980void
e315cd28 2981qla2x00_config_rings(struct scsi_qla_host *vha)
abbd8870 2982{
e315cd28 2983 struct qla_hw_data *ha = vha->hw;
3d71644c 2984 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
73208dfd
AC		 2985 struct req_que *req = ha->req_q_map[0];
2986 struct rsp_que *rsp = ha->rsp_q_map[0];
abbd8870
AV		 2987
2988 /* Setup ring parameters in initialization control block. */
ad950360
BVA		 2989 ha->init_cb->request_q_outpointer = cpu_to_le16(0);
2990 ha->init_cb->response_q_inpointer = cpu_to_le16(0);
e315cd28
AC		 2991 ha->init_cb->request_q_length = cpu_to_le16(req->length);
2992 ha->init_cb->response_q_length = cpu_to_le16(rsp->length);
2993 ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
2994 ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
2995 ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
2996 ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
abbd8870
AV		 2997
2998 WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0);
2999 WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0);
3000 WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0);
3001 WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0);
3002 RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */
3003}
3004
0107109e 3005void
e315cd28 3006qla24xx_config_rings(struct scsi_qla_host *vha)
0107109e 3007{
e315cd28 3008 struct qla_hw_data *ha = vha->hw;
118e2ef9 3009 device_reg_t *reg = ISP_QUE_REG(ha, 0);
73208dfd
AC		 3010 struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
3011 struct qla_msix_entry *msix;
0107109e 3012 struct init_cb_24xx *icb;
73208dfd
AC		 3013 uint16_t rid = 0;
3014 struct req_que *req = ha->req_q_map[0];
3015 struct rsp_que *rsp = ha->rsp_q_map[0];
0107109e 3016
6246b8a1 3017 /* Setup ring parameters in initialization control block. */
0107109e 3018 icb = (struct init_cb_24xx *)ha->init_cb;
ad950360
BVA		 3019 icb->request_q_outpointer = cpu_to_le16(0);
3020 icb->response_q_inpointer = cpu_to_le16(0);
e315cd28
AC		 3021 icb->request_q_length = cpu_to_le16(req->length);
3022 icb->response_q_length = cpu_to_le16(rsp->length);
3023 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
3024 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
3025 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
3026 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
0107109e 3027
2d70c103 3028 /* Setup ATIO queue dma pointers for target mode */
ad950360 3029 icb->atio_q_inpointer = cpu_to_le16(0);
2d70c103
NB		 3030 icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length);
3031 icb->atio_q_address[0] = cpu_to_le32(LSD(ha->tgt.atio_dma));
3032 icb->atio_q_address[1] = cpu_to_le32(MSD(ha->tgt.atio_dma));
3033
7c6300e3 3034 if (IS_SHADOW_REG_CAPABLE(ha))
ad950360 3035 icb->firmware_options_2 |= cpu_to_le32(BIT_30|BIT_29);
7c6300e3 3036
f73cb695 3037 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
ad950360
BVA		 3038 icb->qos = cpu_to_le16(QLA_DEFAULT_QUE_QOS);
3039 icb->rid = cpu_to_le16(rid);
73208dfd
AC		 3040 if (ha->flags.msix_enabled) {
3041 msix = &ha->msix_entries[1];
7c3df132
SK		 3042 ql_dbg(ql_dbg_init, vha, 0x00fd,
3043 "Registering vector 0x%x for base que.\n",
3044 msix->entry);
73208dfd
AC		 3045 icb->msix = cpu_to_le16(msix->entry);
3046 }
3047 /* Use alternate PCI bus number */
3048 if (MSB(rid))
ad950360 3049 icb->firmware_options_2 |= cpu_to_le32(BIT_19);
73208dfd
AC		 3050 /* Use alternate PCI devfn */
3051 if (LSB(rid))
ad950360 3052 icb->firmware_options_2 |= cpu_to_le32(BIT_18);
73208dfd 3053
3155754a 3054 /* Use Disable MSIX Handshake mode for capable adapters */
6246b8a1
GM		 3055 if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) &&
3056 (ha->flags.msix_enabled)) {
ad950360 3057 icb->firmware_options_2 &= cpu_to_le32(~BIT_22);
3155754a 3058 ha->flags.disable_msix_handshake = 1;
7c3df132
SK		 3059 ql_dbg(ql_dbg_init, vha, 0x00fe,
3060 "MSIX Handshake Disable Mode turned on.\n");
3155754a 3061 } else {
ad950360 3062 icb->firmware_options_2 |= cpu_to_le32(BIT_22);
3155754a 3063 }
ad950360 3064 icb->firmware_options_2 |= cpu_to_le32(BIT_23);
73208dfd
AC		 3065
3066 WRT_REG_DWORD(&reg->isp25mq.req_q_in, 0);
3067 WRT_REG_DWORD(&reg->isp25mq.req_q_out, 0);
3068 WRT_REG_DWORD(&reg->isp25mq.rsp_q_in, 0);
3069 WRT_REG_DWORD(&reg->isp25mq.rsp_q_out, 0);
3070 } else {
3071 WRT_REG_DWORD(&reg->isp24.req_q_in, 0);
3072 WRT_REG_DWORD(&reg->isp24.req_q_out, 0);
3073 WRT_REG_DWORD(&reg->isp24.rsp_q_in, 0);
3074 WRT_REG_DWORD(&reg->isp24.rsp_q_out, 0);
3075 }
aa230bc5 3076 qlt_24xx_config_rings(vha);
2d70c103 3077
73208dfd
AC		 3078 /* PCI posting */
3079 RD_REG_DWORD(&ioreg->hccr);
0107109e
AV		 3080}
3081
1da177e4
LT		 3082/**
3083 * qla2x00_init_rings() - Initializes firmware.
3084 * @ha: HA context
3085 *
3086 * Beginning of request ring has initialization control block already built
3087 * by nvram config routine.
3088 *
3089 * Returns 0 on success.
3090 */
8ae6d9c7 3091int
e315cd28 3092qla2x00_init_rings(scsi_qla_host_t *vha)
1da177e4
LT		 3093{
3094 int rval;
3095 unsigned long flags = 0;
29bdccbe 3096 int cnt, que;
e315cd28 3097 struct qla_hw_data *ha = vha->hw;
29bdccbe
AC		 3098 struct req_que *req;
3099 struct rsp_que *rsp;
2c3dfe3f
SJ		 3100 struct mid_init_cb_24xx *mid_init_cb =
3101 (struct mid_init_cb_24xx *) ha->init_cb;
1da177e4
LT		 3102
3103 spin_lock_irqsave(&ha->hardware_lock, flags);
3104
3105 /* Clear outstanding commands array. */
2afa19a9 3106 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 3107 req = ha->req_q_map[que];
cb43285f 3108 if (!req || !test_bit(que, ha->req_qid_map))
29bdccbe 3109 continue;
7c6300e3
JC		 3110 req->out_ptr = (void *)(req->ring + req->length);
3111 *req->out_ptr = 0;
8d93f550 3112 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++)
29bdccbe 3113 req->outstanding_cmds[cnt] = NULL;
1da177e4 3114
2afa19a9 3115 req->current_outstanding_cmd = 1;
1da177e4 3116
29bdccbe
AC		 3117 /* Initialize firmware. */
3118 req->ring_ptr = req->ring;
3119 req->ring_index = 0;
3120 req->cnt = req->length;
3121 }
1da177e4 3122
2afa19a9 3123 for (que = 0; que < ha->max_rsp_queues; que++) {
29bdccbe 3124 rsp = ha->rsp_q_map[que];
cb43285f 3125 if (!rsp || !test_bit(que, ha->rsp_qid_map))
29bdccbe 3126 continue;
7c6300e3
JC		 3127 rsp->in_ptr = (void *)(rsp->ring + rsp->length);
3128 *rsp->in_ptr = 0;
29bdccbe 3129 /* Initialize response queue entries */
8ae6d9c7
GM		 3130 if (IS_QLAFX00(ha))
3131 qlafx00_init_response_q_entries(rsp);
3132 else
3133 qla2x00_init_response_q_entries(rsp);
29bdccbe 3134 }
1da177e4 3135
2d70c103
NB		 3136 ha->tgt.atio_ring_ptr = ha->tgt.atio_ring;
3137 ha->tgt.atio_ring_index = 0;
3138 /* Initialize ATIO queue entries */
3139 qlt_init_atio_q_entries(vha);
3140
e315cd28 3141 ha->isp_ops->config_rings(vha);
1da177e4
LT		 3142
3143 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3144
8ae6d9c7
GM		 3145 ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n");
3146
3147 if (IS_QLAFX00(ha)) {
3148 rval = qlafx00_init_firmware(vha, ha->init_cb_size);
3149 goto next_check;
3150 }
3151
1da177e4 3152 /* Update any ISP specific firmware options before initialization. */
e315cd28 3153 ha->isp_ops->update_fw_options(vha);
1da177e4 3154
605aa2bc 3155 if (ha->flags.npiv_supported) {
45980cc2 3156 if (ha->operating_mode == LOOP && !IS_CNA_CAPABLE(ha))
605aa2bc 3157 ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
c48339de 3158 mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
605aa2bc
LC		 3159 }
3160
24a08138 3161 if (IS_FWI2_CAPABLE(ha)) {
ad950360 3162 mid_init_cb->options = cpu_to_le16(BIT_1);
24a08138 3163 mid_init_cb->init_cb.execution_throttle =
03e8c680 3164 cpu_to_le16(ha->cur_fw_xcb_count);
40f3862b
JC		 3165 ha->flags.dport_enabled =
3166 (mid_init_cb->init_cb.firmware_options_1 & BIT_7) != 0;
3167 ql_dbg(ql_dbg_init, vha, 0x0191, "DPORT Support: %s.\n",
3168 (ha->flags.dport_enabled) ? "enabled" : "disabled");
3169 /* FA-WWPN Status */
2486c627 3170 ha->flags.fawwpn_enabled =
40f3862b 3171 (mid_init_cb->init_cb.firmware_options_1 & BIT_6) != 0;
2486c627
HM		 3172 ql_dbg(ql_dbg_init, vha, 0x0141, "FA-WWPN Support: %s.\n",
3173 (ha->flags.fawwpn_enabled) ? "enabled" : "disabled");
24a08138 3174 }
2c3dfe3f 3175
e315cd28 3176 rval = qla2x00_init_firmware(vha, ha->init_cb_size);
8ae6d9c7 3177next_check:
1da177e4 3178 if (rval) {
7c3df132
SK		 3179 ql_log(ql_log_fatal, vha, 0x00d2,
3180 "Init Firmware **** FAILED ****.\n");
1da177e4 3181 } else {
7c3df132
SK		 3182 ql_dbg(ql_dbg_init, vha, 0x00d3,
3183 "Init Firmware -- success.\n");
ec7193e2 3184 ha->flags.fw_started = 1;
1da177e4
LT		 3185 }
3186
3187 return (rval);
3188}
3189
3190/**
3191 * qla2x00_fw_ready() - Waits for firmware ready.
3192 * @ha: HA context
3193 *
3194 * Returns 0 on success.
3195 */
3196static int
e315cd28 3197qla2x00_fw_ready(scsi_qla_host_t *vha)
1da177e4
LT		 3198{
3199 int rval;
4d4df193 3200 unsigned long wtime, mtime, cs84xx_time;
1da177e4
LT		 3201 uint16_t min_wait; /* Minimum wait time if loop is down */
3202 uint16_t wait_time; /* Wait time if loop is coming ready */
b5a340dd 3203 uint16_t state[6];
e315cd28 3204 struct qla_hw_data *ha = vha->hw;
1da177e4 3205
8ae6d9c7
GM		 3206 if (IS_QLAFX00(vha->hw))
3207 return qlafx00_fw_ready(vha);
3208
1da177e4
LT		 3209 rval = QLA_SUCCESS;
3210
33461491
CD		 3211 /* Time to wait for loop down */
3212 if (IS_P3P_TYPE(ha))
3213 min_wait = 30;
3214 else
3215 min_wait = 20;
1da177e4
LT		 3216
3217 /*
3218 * Firmware should take at most one RATOV to login, plus 5 seconds for
3219 * our own processing.
3220 */
3221 if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) {
3222 wait_time = min_wait;
3223 }
3224
3225 /* Min wait time if loop down */
3226 mtime = jiffies + (min_wait * HZ);
3227
3228 /* wait time before firmware ready */
3229 wtime = jiffies + (wait_time * HZ);
3230
3231 /* Wait for ISP to finish LIP */
e315cd28 3232 if (!vha->flags.init_done)
7c3df132
SK		 3233 ql_log(ql_log_info, vha, 0x801e,
3234 "Waiting for LIP to complete.\n");
1da177e4
LT		 3235
3236 do {
5b939038 3237 memset(state, -1, sizeof(state));
e315cd28 3238 rval = qla2x00_get_firmware_state(vha, state);
1da177e4 3239 if (rval == QLA_SUCCESS) {
4d4df193 3240 if (state[0] < FSTATE_LOSS_OF_SYNC) {
e315cd28 3241 vha->device_flags &= ~DFLG_NO_CABLE;
1da177e4 3242 }
4d4df193 3243 if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) {
7c3df132
SK		 3244 ql_dbg(ql_dbg_taskm, vha, 0x801f,
3245 "fw_state=%x 84xx=%x.\n", state[0],
3246 state[2]);
4d4df193
HK		 3247 if ((state[2] & FSTATE_LOGGED_IN) &&
3248 (state[2] & FSTATE_WAITING_FOR_VERIFY)) {
7c3df132
SK		 3249 ql_dbg(ql_dbg_taskm, vha, 0x8028,
3250 "Sending verify iocb.\n");
4d4df193
HK		 3251
3252 cs84xx_time = jiffies;
e315cd28 3253 rval = qla84xx_init_chip(vha);
7c3df132
SK		 3254 if (rval != QLA_SUCCESS) {
3255 ql_log(ql_log_warn,
cfb0919c 3256 vha, 0x8007,
7c3df132 3257 "Init chip failed.\n");
4d4df193 3258 break;
7c3df132 3259 }
4d4df193
HK		 3260
3261 /* Add time taken to initialize. */
3262 cs84xx_time = jiffies - cs84xx_time;
3263 wtime += cs84xx_time;
3264 mtime += cs84xx_time;
cfb0919c 3265 ql_dbg(ql_dbg_taskm, vha, 0x8008,
7c3df132
SK		 3266 "Increasing wait time by %ld. "
3267 "New time %ld.\n", cs84xx_time,
3268 wtime);
4d4df193
HK		 3269 }
3270 } else if (state[0] == FSTATE_READY) {
7c3df132
SK		 3271 ql_dbg(ql_dbg_taskm, vha, 0x8037,
3272 "F/W Ready - OK.\n");
1da177e4 3273
e315cd28 3274 qla2x00_get_retry_cnt(vha, &ha->retry_count,
1da177e4
LT		 3275 &ha->login_timeout, &ha->r_a_tov);
3276
3277 rval = QLA_SUCCESS;
3278 break;
3279 }
3280
3281 rval = QLA_FUNCTION_FAILED;
3282
e315cd28 3283 if (atomic_read(&vha->loop_down_timer) &&
4d4df193 3284 state[0] != FSTATE_READY) {
1da177e4 3285 /* Loop down. Timeout on min_wait for states
fa2a1ce5
AV		 3286 * other than Wait for Login.
3287 */
1da177e4 3288 if (time_after_eq(jiffies, mtime)) {
7c3df132 3289 ql_log(ql_log_info, vha, 0x8038,
1da177e4
LT		 3290 "Cable is unplugged...\n");
3291
e315cd28 3292 vha->device_flags |= DFLG_NO_CABLE;
1da177e4
LT		 3293 break;
3294 }
3295 }
3296 } else {
3297 /* Mailbox cmd failed. Timeout on min_wait. */
cdbb0a4f 3298 if (time_after_eq(jiffies, mtime) ||
7190575f 3299 ha->flags.isp82xx_fw_hung)
1da177e4
LT		 3300 break;
3301 }
3302
3303 if (time_after_eq(jiffies, wtime))
3304 break;
3305
3306 /* Delay for a while */
3307 msleep(500);
1da177e4
LT		 3308 } while (1);
3309
7c3df132 3310 ql_dbg(ql_dbg_taskm, vha, 0x803a,
b5a340dd
JC		 3311 "fw_state=%x (%x, %x, %x, %x %x) curr time=%lx.\n", state[0],
3312 state[1], state[2], state[3], state[4], state[5], jiffies);
1da177e4 3313
cfb0919c 3314 if (rval && !(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132
SK		 3315 ql_log(ql_log_warn, vha, 0x803b,
3316 "Firmware ready **** FAILED ****.\n");
1da177e4
LT		 3317 }
3318
3319 return (rval);
3320}
3321
3322/*
3323* qla2x00_configure_hba
3324* Setup adapter context.
3325*
3326* Input:
3327* ha = adapter state pointer.
3328*
3329* Returns:
3330* 0 = success
3331*
3332* Context:
3333* Kernel context.
3334*/
3335static int
e315cd28 3336qla2x00_configure_hba(scsi_qla_host_t *vha)
1da177e4
LT		 3337{
3338 int rval;
3339 uint16_t loop_id;
3340 uint16_t topo;
2c3dfe3f 3341 uint16_t sw_cap;
1da177e4
LT		 3342 uint8_t al_pa;
3343 uint8_t area;
3344 uint8_t domain;
3345 char connect_type[22];
e315cd28 3346 struct qla_hw_data *ha = vha->hw;
61e1b269 3347 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
482c9dc7 3348 port_id_t id;
1da177e4
LT		 3349
3350 /* Get host addresses. */
e315cd28 3351 rval = qla2x00_get_adapter_id(vha,
2c3dfe3f 3352 &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
1da177e4 3353 if (rval != QLA_SUCCESS) {
e315cd28 3354 if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
6246b8a1 3355 IS_CNA_CAPABLE(ha) ||
33135aa2 3356 (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
7c3df132
SK		 3357 ql_dbg(ql_dbg_disc, vha, 0x2008,
3358 "Loop is in a transition state.\n");
33135aa2 3359 } else {
7c3df132
SK		 3360 ql_log(ql_log_warn, vha, 0x2009,
3361 "Unable to get host loop ID.\n");
61e1b269
JC		 3362 if (IS_FWI2_CAPABLE(ha) && (vha == base_vha) &&
3363 (rval == QLA_COMMAND_ERROR && loop_id == 0x1b)) {
3364 ql_log(ql_log_warn, vha, 0x1151,
3365 "Doing link init.\n");
3366 if (qla24xx_link_initialize(vha) == QLA_SUCCESS)
3367 return rval;
3368 }
e315cd28 3369 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
33135aa2 3370 }
1da177e4
LT		 3371 return (rval);
3372 }
3373
3374 if (topo == 4) {
7c3df132
SK		 3375 ql_log(ql_log_info, vha, 0x200a,
3376 "Cannot get topology - retrying.\n");
1da177e4
LT		 3377 return (QLA_FUNCTION_FAILED);
3378 }
3379
e315cd28 3380 vha->loop_id = loop_id;
1da177e4
LT		 3381
3382 /* initialize */
3383 ha->min_external_loopid = SNS_FIRST_LOOP_ID;
3384 ha->operating_mode = LOOP;
2c3dfe3f 3385 ha->switch_cap = 0;
1da177e4
LT		 3386
3387 switch (topo) {
3388 case 0:
7c3df132 3389 ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n");
1da177e4
LT		 3390 ha->current_topology = ISP_CFG_NL;
3391 strcpy(connect_type, "(Loop)");
3392 break;
3393
3394 case 1:
7c3df132 3395 ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n");
2c3dfe3f 3396 ha->switch_cap = sw_cap;
1da177e4
LT		 3397 ha->current_topology = ISP_CFG_FL;
3398 strcpy(connect_type, "(FL_Port)");
3399 break;
3400
3401 case 2:
7c3df132 3402 ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n");
1da177e4
LT		 3403 ha->operating_mode = P2P;
3404 ha->current_topology = ISP_CFG_N;
3405 strcpy(connect_type, "(N_Port-to-N_Port)");
3406 break;
3407
3408 case 3:
7c3df132 3409 ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n");
2c3dfe3f 3410 ha->switch_cap = sw_cap;
1da177e4
LT		 3411 ha->operating_mode = P2P;
3412 ha->current_topology = ISP_CFG_F;
3413 strcpy(connect_type, "(F_Port)");
3414 break;
3415
3416 default:
7c3df132
SK		 3417 ql_dbg(ql_dbg_disc, vha, 0x200f,
3418 "HBA in unknown topology %x, using NL.\n", topo);
1da177e4
LT		 3419 ha->current_topology = ISP_CFG_NL;
3420 strcpy(connect_type, "(Loop)");
3421 break;
3422 }
3423
3424 /* Save Host port and loop ID. */
3425 /* byte order - Big Endian */
482c9dc7
QT		 3426 id.b.domain = domain;
3427 id.b.area = area;
3428 id.b.al_pa = al_pa;
3429 id.b.rsvd_1 = 0;
3430 qlt_update_host_map(vha, id);
2d70c103 3431
e315cd28 3432 if (!vha->flags.init_done)
7c3df132
SK		 3433 ql_log(ql_log_info, vha, 0x2010,
3434 "Topology - %s, Host Loop address 0x%x.\n",
e315cd28 3435 connect_type, vha->loop_id);
1da177e4 3436
1da177e4
LT		 3437 return(rval);
3438}
3439
a9083016 3440inline void
e315cd28
AC		 3441qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
3442 char *def)
9bb9fcf2
AV		 3443{
3444 char *st, *en;
3445 uint16_t index;
e315cd28 3446 struct qla_hw_data *ha = vha->hw;
ab671149 3447 int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
6246b8a1 3448 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha);
9bb9fcf2
AV		 3449
3450 if (memcmp(model, BINZERO, len) != 0) {
3451 strncpy(ha->model_number, model, len);
3452 st = en = ha->model_number;
3453 en += len - 1;
3454 while (en > st) {
3455 if (*en != 0x20 && *en != 0x00)
3456 break;
3457 *en-- = '\0';
3458 }
3459
3460 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 3461 if (use_tbl &&
3462 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2 3463 index < QLA_MODEL_NAMES)
1ee27146
JC		 3464 strncpy(ha->model_desc,
3465 qla2x00_model_name[index * 2 + 1],
3466 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 3467 } else {
3468 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 3469 if (use_tbl &&
3470 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2
AV		 3471 index < QLA_MODEL_NAMES) {
3472 strcpy(ha->model_number,
3473 qla2x00_model_name[index * 2]);
1ee27146
JC		 3474 strncpy(ha->model_desc,
3475 qla2x00_model_name[index * 2 + 1],
3476 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 3477 } else {
3478 strcpy(ha->model_number, def);
3479 }
3480 }
1ee27146 3481 if (IS_FWI2_CAPABLE(ha))
e315cd28 3482 qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc,
1ee27146 3483 sizeof(ha->model_desc));
9bb9fcf2
AV		 3484}
3485
4e08df3f
DM		 3486/* On sparc systems, obtain port and node WWN from firmware
3487 * properties.
3488 */
e315cd28 3489static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv)
4e08df3f
DM		 3490{
3491#ifdef CONFIG_SPARC
e315cd28 3492 struct qla_hw_data *ha = vha->hw;
4e08df3f 3493 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 3494 struct device_node *dp = pci_device_to_OF_node(pdev);
3495 const u8 *val;
4e08df3f
DM		 3496 int len;
3497
3498 val = of_get_property(dp, "port-wwn", &len);
3499 if (val && len >= WWN_SIZE)
3500 memcpy(nv->port_name, val, WWN_SIZE);
3501
3502 val = of_get_property(dp, "node-wwn", &len);
3503 if (val && len >= WWN_SIZE)
3504 memcpy(nv->node_name, val, WWN_SIZE);
3505#endif
3506}
3507
1da177e4
LT		 3508/*
3509* NVRAM configuration for ISP 2xxx
3510*
3511* Input:
3512* ha = adapter block pointer.
3513*
3514* Output:
3515* initialization control block in response_ring
3516* host adapters parameters in host adapter block
3517*
3518* Returns:
3519* 0 = success.
3520*/
abbd8870 3521int
e315cd28 3522qla2x00_nvram_config(scsi_qla_host_t *vha)
1da177e4 3523{
4e08df3f 3524 int rval;
0107109e
AV		 3525 uint8_t chksum = 0;
3526 uint16_t cnt;
3527 uint8_t *dptr1, *dptr2;
e315cd28 3528 struct qla_hw_data *ha = vha->hw;
0107109e 3529 init_cb_t *icb = ha->init_cb;
281afe19
SJ		 3530 nvram_t *nv = ha->nvram;
3531 uint8_t *ptr = ha->nvram;
3d71644c 3532 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 3533
4e08df3f
DM		 3534 rval = QLA_SUCCESS;
3535
1da177e4 3536 /* Determine NVRAM starting address. */
0107109e 3537 ha->nvram_size = sizeof(nvram_t);
1da177e4
LT		 3538 ha->nvram_base = 0;
3539 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
3540 if ((RD_REG_WORD(&reg->ctrl_status) >> 14) == 1)
3541 ha->nvram_base = 0x80;
3542
3543 /* Get NVRAM data and calculate checksum. */
e315cd28 3544 ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size);
0107109e
AV		 3545 for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++)
3546 chksum += *ptr++;
1da177e4 3547
7c3df132
SK		 3548 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
3549 "Contents of NVRAM.\n");
3550 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
3551 (uint8_t *)nv, ha->nvram_size);
1da177e4
LT		 3552
3553 /* Bad NVRAM data, set defaults parameters. */
3554 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' ||
3555 nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) {
3556 /* Reset NVRAM data. */
7c3df132 3557 ql_log(ql_log_warn, vha, 0x0064,
9e336520 3558 "Inconsistent NVRAM "
7c3df132
SK		 3559 "detected: checksum=0x%x id=%c version=0x%x.\n",
3560 chksum, nv->id[0], nv->nvram_version);
3561 ql_log(ql_log_warn, vha, 0x0065,
3562 "Falling back to "
3563 "functioning (yet invalid -- WWPN) defaults.\n");
4e08df3f
DM		 3564
3565 /*
3566 * Set default initialization control block.
3567 */
3568 memset(nv, 0, ha->nvram_size);
3569 nv->parameter_block_version = ICB_VERSION;
3570
3571 if (IS_QLA23XX(ha)) {
3572 nv->firmware_options[0] = BIT_2 | BIT_1;
3573 nv->firmware_options[1] = BIT_7 | BIT_5;
3574 nv->add_firmware_options[0] = BIT_5;
3575 nv->add_firmware_options[1] = BIT_5 | BIT_4;
98aee70d 3576 nv->frame_payload_size = 2048;
4e08df3f
DM		 3577 nv->special_options[1] = BIT_7;
3578 } else if (IS_QLA2200(ha)) {
3579 nv->firmware_options[0] = BIT_2 | BIT_1;
3580 nv->firmware_options[1] = BIT_7 | BIT_5;
3581 nv->add_firmware_options[0] = BIT_5;
3582 nv->add_firmware_options[1] = BIT_5 | BIT_4;
98aee70d 3583 nv->frame_payload_size = 1024;
4e08df3f
DM		 3584 } else if (IS_QLA2100(ha)) {
3585 nv->firmware_options[0] = BIT_3 | BIT_1;
3586 nv->firmware_options[1] = BIT_5;
98aee70d 3587 nv->frame_payload_size = 1024;
4e08df3f
DM		 3588 }
3589
ad950360
BVA		 3590 nv->max_iocb_allocation = cpu_to_le16(256);
3591 nv->execution_throttle = cpu_to_le16(16);
4e08df3f
DM		 3592 nv->retry_count = 8;
3593 nv->retry_delay = 1;
3594
3595 nv->port_name[0] = 33;
3596 nv->port_name[3] = 224;
3597 nv->port_name[4] = 139;
3598
e315cd28 3599 qla2xxx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 3600
3601 nv->login_timeout = 4;
3602
3603 /*
3604 * Set default host adapter parameters
3605 */
3606 nv->host_p[1] = BIT_2;
3607 nv->reset_delay = 5;
3608 nv->port_down_retry_count = 8;
ad950360 3609 nv->max_luns_per_target = cpu_to_le16(8);
4e08df3f
DM		 3610 nv->link_down_timeout = 60;
3611
3612 rval = 1;
1da177e4
LT		 3613 }
3614
3615#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
3616 /*
3617 * The SN2 does not provide BIOS emulation which means you can't change
3618 * potentially bogus BIOS settings. Force the use of default settings
3619 * for link rate and frame size. Hope that the rest of the settings
3620 * are valid.
3621 */
3622 if (ia64_platform_is("sn2")) {
98aee70d 3623 nv->frame_payload_size = 2048;
1da177e4
LT		 3624 if (IS_QLA23XX(ha))
3625 nv->special_options[1] = BIT_7;
3626 }
3627#endif
3628
3629 /* Reset Initialization control block */
0107109e 3630 memset(icb, 0, ha->init_cb_size);
1da177e4
LT		 3631
3632 /*
3633 * Setup driver NVRAM options.
3634 */
3635 nv->firmware_options[0] |= (BIT_6 | BIT_1);
3636 nv->firmware_options[0] &= ~(BIT_5 | BIT_4);
3637 nv->firmware_options[1] |= (BIT_5 | BIT_0);
3638 nv->firmware_options[1] &= ~BIT_4;
3639
3640 if (IS_QLA23XX(ha)) {
3641 nv->firmware_options[0] |= BIT_2;
3642 nv->firmware_options[0] &= ~BIT_3;
2d70c103 3643 nv->special_options[0] &= ~BIT_6;
0107109e 3644 nv->add_firmware_options[1] |= BIT_5 | BIT_4;
1da177e4
LT		 3645
3646 if (IS_QLA2300(ha)) {
3647 if (ha->fb_rev == FPM_2310) {
3648 strcpy(ha->model_number, "QLA2310");
3649 } else {
3650 strcpy(ha->model_number, "QLA2300");
3651 }
3652 } else {
e315cd28 3653 qla2x00_set_model_info(vha, nv->model_number,
9bb9fcf2 3654 sizeof(nv->model_number), "QLA23xx");
1da177e4
LT		 3655 }
3656 } else if (IS_QLA2200(ha)) {
3657 nv->firmware_options[0] |= BIT_2;
3658 /*
3659 * 'Point-to-point preferred, else loop' is not a safe
3660 * connection mode setting.
3661 */
3662 if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
3663 (BIT_5 | BIT_4)) {
3664 /* Force 'loop preferred, else point-to-point'. */
3665 nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
3666 nv->add_firmware_options[0] |= BIT_5;
3667 }
3668 strcpy(ha->model_number, "QLA22xx");
3669 } else /*if (IS_QLA2100(ha))*/ {
3670 strcpy(ha->model_number, "QLA2100");
3671 }
3672
3673 /*
3674 * Copy over NVRAM RISC parameter block to initialization control block.
3675 */
3676 dptr1 = (uint8_t *)icb;
3677 dptr2 = (uint8_t *)&nv->parameter_block_version;
3678 cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;
3679 while (cnt--)
3680 *dptr1++ = *dptr2++;
3681
3682 /* Copy 2nd half. */
3683 dptr1 = (uint8_t *)icb->add_firmware_options;
3684 cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;
3685 while (cnt--)
3686 *dptr1++ = *dptr2++;
3687
5341e868
AV		 3688 /* Use alternate WWN? */
3689 if (nv->host_p[1] & BIT_7) {
3690 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
3691 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
3692 }
3693
1da177e4
LT		 3694 /* Prepare nodename */
3695 if ((icb->firmware_options[1] & BIT_6) == 0) {
3696 /*
3697 * Firmware will apply the following mask if the nodename was
3698 * not provided.
3699 */
3700 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
3701 icb->node_name[0] &= 0xF0;
3702 }
3703
3704 /*
3705 * Set host adapter parameters.
3706 */
3ce8866c
SK		 3707
3708 /*
3709 * BIT_7 in the host-parameters section allows for modification to
3710 * internal driver logging.
3711 */
0181944f 3712 if (nv->host_p[0] & BIT_7)
cfb0919c 3713 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
1da177e4
LT		 3714 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
3715 /* Always load RISC code on non ISP2[12]00 chips. */
3716 if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
3717 ha->flags.disable_risc_code_load = 0;
3718 ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0);
3719 ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
3720 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
06c22bd1 3721 ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
d4c760c2 3722 ha->flags.disable_serdes = 0;
1da177e4
LT		 3723
3724 ha->operating_mode =
3725 (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
3726
3727 memcpy(ha->fw_seriallink_options, nv->seriallink_options,
3728 sizeof(ha->fw_seriallink_options));
3729
3730 /* save HBA serial number */
3731 ha->serial0 = icb->port_name[5];
3732 ha->serial1 = icb->port_name[6];
3733 ha->serial2 = icb->port_name[7];
e315cd28
AC		 3734 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
3735 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
1da177e4 3736
ad950360 3737 icb->execution_throttle = cpu_to_le16(0xFFFF);
1da177e4
LT		 3738
3739 ha->retry_count = nv->retry_count;
3740
3741 /* Set minimum login_timeout to 4 seconds. */
5b91490e 3742 if (nv->login_timeout != ql2xlogintimeout)
1da177e4
LT		 3743 nv->login_timeout = ql2xlogintimeout;
3744 if (nv->login_timeout < 4)
3745 nv->login_timeout = 4;
3746 ha->login_timeout = nv->login_timeout;
1da177e4 3747
00a537b8
AV		 3748 /* Set minimum RATOV to 100 tenths of a second. */
3749 ha->r_a_tov = 100;
1da177e4 3750
1da177e4
LT		 3751 ha->loop_reset_delay = nv->reset_delay;
3752
1da177e4
LT		 3753 /* Link Down Timeout = 0:
3754 *
3755 * When Port Down timer expires we will start returning
3756 * I/O's to OS with "DID_NO_CONNECT".
3757 *
3758 * Link Down Timeout != 0:
3759 *
3760 * The driver waits for the link to come up after link down
3761 * before returning I/Os to OS with "DID_NO_CONNECT".
fa2a1ce5 3762 */
1da177e4
LT		 3763 if (nv->link_down_timeout == 0) {
3764 ha->loop_down_abort_time =
354d6b21 3765 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
1da177e4
LT		 3766 } else {
3767 ha->link_down_timeout = nv->link_down_timeout;
3768 ha->loop_down_abort_time =
3769 (LOOP_DOWN_TIME - ha->link_down_timeout);
fa2a1ce5 3770 }
1da177e4 3771
1da177e4
LT		 3772 /*
3773 * Need enough time to try and get the port back.
3774 */
3775 ha->port_down_retry_count = nv->port_down_retry_count;
3776 if (qlport_down_retry)
3777 ha->port_down_retry_count = qlport_down_retry;
3778 /* Set login_retry_count */
3779 ha->login_retry_count = nv->retry_count;
3780 if (ha->port_down_retry_count == nv->port_down_retry_count &&
3781 ha->port_down_retry_count > 3)
3782 ha->login_retry_count = ha->port_down_retry_count;
3783 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
3784 ha->login_retry_count = ha->port_down_retry_count;
3785 if (ql2xloginretrycount)
3786 ha->login_retry_count = ql2xloginretrycount;
3787
ad950360 3788 icb->lun_enables = cpu_to_le16(0);
1da177e4
LT		 3789 icb->command_resource_count = 0;
3790 icb->immediate_notify_resource_count = 0;
ad950360 3791 icb->timeout = cpu_to_le16(0);
1da177e4
LT		 3792
3793 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
3794 /* Enable RIO */
3795 icb->firmware_options[0] &= ~BIT_3;
3796 icb->add_firmware_options[0] &=
3797 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
3798 icb->add_firmware_options[0] |= BIT_2;
3799 icb->response_accumulation_timer = 3;
3800 icb->interrupt_delay_timer = 5;
3801
e315cd28 3802 vha->flags.process_response_queue = 1;
1da177e4 3803 } else {
4fdfefe5 3804 /* Enable ZIO. */
e315cd28 3805 if (!vha->flags.init_done) {
4fdfefe5
AV		 3806 ha->zio_mode = icb->add_firmware_options[0] &
3807 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
3808 ha->zio_timer = icb->interrupt_delay_timer ?
3809 icb->interrupt_delay_timer: 2;
3810 }
1da177e4
LT		 3811 icb->add_firmware_options[0] &=
3812 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
e315cd28 3813 vha->flags.process_response_queue = 0;
4fdfefe5 3814 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d
AV		 3815 ha->zio_mode = QLA_ZIO_MODE_6;
3816
7c3df132 3817 ql_log(ql_log_info, vha, 0x0068,
4fdfefe5
AV		 3818 "ZIO mode %d enabled; timer delay (%d us).\n",
3819 ha->zio_mode, ha->zio_timer * 100);
1da177e4 3820
4fdfefe5
AV		 3821 icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;
3822 icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;
e315cd28 3823 vha->flags.process_response_queue = 1;
1da177e4
LT		 3824 }
3825 }
3826
4e08df3f 3827 if (rval) {
7c3df132
SK		 3828 ql_log(ql_log_warn, vha, 0x0069,
3829 "NVRAM configuration failed.\n");
4e08df3f
DM		 3830 }
3831 return (rval);
1da177e4
LT		 3832}
3833
19a7b4ae
JSEC		 3834static void
3835qla2x00_rport_del(void *data)
3836{
3837 fc_port_t *fcport = data;
d97994dc 3838 struct fc_rport *rport;
044d78e1 3839 unsigned long flags;
d97994dc 3840
044d78e1 3841 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
ac280b67 3842 rport = fcport->drport ? fcport->drport: fcport->rport;
d97994dc 3843 fcport->drport = NULL;
044d78e1 3844 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
726b8548
QT		 3845 if (rport) {
3846 ql_dbg(ql_dbg_disc, fcport->vha, 0xffff,
3847 "%s %8phN. rport %p roles %x \n",
3848 __func__, fcport->port_name, rport,
3849 rport->roles);
3850
d97994dc 3851 fc_remote_port_delete(rport);
726b8548 3852 }
19a7b4ae
JSEC		 3853}
3854
1da177e4
LT		 3855/**
3856 * qla2x00_alloc_fcport() - Allocate a generic fcport.
3857 * @ha: HA context
3858 * @flags: allocation flags
3859 *
3860 * Returns a pointer to the allocated fcport, or NULL, if none available.
3861 */
9a069e19 3862fc_port_t *
e315cd28 3863qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags)
1da177e4
LT		 3864{
3865 fc_port_t *fcport;
3866
bbfbbbc1
MK		 3867 fcport = kzalloc(sizeof(fc_port_t), flags);
3868 if (!fcport)
3869 return NULL;
1da177e4
LT		 3870
3871 /* Setup fcport template structure. */
e315cd28 3872 fcport->vha = vha;
1da177e4
LT		 3873 fcport->port_type = FCT_UNKNOWN;
3874 fcport->loop_id = FC_NO_LOOP_ID;
ec426e10 3875 qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
ad3e0eda 3876 fcport->supported_classes = FC_COS_UNSPECIFIED;
1da177e4 3877
726b8548
QT		 3878 fcport->ct_desc.ct_sns = dma_alloc_coherent(&vha->hw->pdev->dev,
3879 sizeof(struct ct_sns_pkt), &fcport->ct_desc.ct_sns_dma,
6cb3216a 3880 flags);
726b8548
QT		 3881 fcport->disc_state = DSC_DELETED;
3882 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL;
3883 fcport->deleted = QLA_SESS_DELETED;
3884 fcport->login_retry = vha->hw->login_retry_count;
3885 fcport->login_retry = 5;
3886 fcport->logout_on_delete = 1;
3887
3888 if (!fcport->ct_desc.ct_sns) {
3889 ql_log(ql_log_warn, vha, 0xffff,
3890 "Failed to allocate ct_sns request.\n");
3891 kfree(fcport);
3892 fcport = NULL;
3893 }
3894 INIT_WORK(&fcport->del_work, qla24xx_delete_sess_fn);
3895 INIT_LIST_HEAD(&fcport->gnl_entry);
3896 INIT_LIST_HEAD(&fcport->list);
3897
bbfbbbc1 3898 return fcport;
1da177e4
LT		 3899}
3900
726b8548
QT		 3901void
3902qla2x00_free_fcport(fc_port_t *fcport)
3903{
3904 if (fcport->ct_desc.ct_sns) {
3905 dma_free_coherent(&fcport->vha->hw->pdev->dev,
3906 sizeof(struct ct_sns_pkt), fcport->ct_desc.ct_sns,
3907 fcport->ct_desc.ct_sns_dma);
3908
3909 fcport->ct_desc.ct_sns = NULL;
3910 }
3911 kfree(fcport);
3912}
3913
1da177e4
LT		 3914/*
3915 * qla2x00_configure_loop
3916 * Updates Fibre Channel Device Database with what is actually on loop.
3917 *
3918 * Input:
3919 * ha = adapter block pointer.
3920 *
3921 * Returns:
3922 * 0 = success.
3923 * 1 = error.
3924 * 2 = database was full and device was not configured.
3925 */
3926static int
e315cd28 3927qla2x00_configure_loop(scsi_qla_host_t *vha)
1da177e4
LT		 3928{
3929 int rval;
3930 unsigned long flags, save_flags;
e315cd28 3931 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3932 rval = QLA_SUCCESS;
3933
3934 /* Get Initiator ID */
e315cd28
AC		 3935 if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) {
3936 rval = qla2x00_configure_hba(vha);
1da177e4 3937 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3938 ql_dbg(ql_dbg_disc, vha, 0x2013,
3939 "Unable to configure HBA.\n");
1da177e4
LT		 3940 return (rval);
3941 }
3942 }
3943
e315cd28 3944 save_flags = flags = vha->dpc_flags;
7c3df132
SK		 3945 ql_dbg(ql_dbg_disc, vha, 0x2014,
3946 "Configure loop -- dpc flags = 0x%lx.\n", flags);
1da177e4
LT		 3947
3948 /*
3949 * If we have both an RSCN and PORT UPDATE pending then handle them
3950 * both at the same time.
3951 */
e315cd28
AC		 3952 clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
3953 clear_bit(RSCN_UPDATE, &vha->dpc_flags);
1da177e4 3954
3064ff39
MH		 3955 qla2x00_get_data_rate(vha);
3956
1da177e4
LT		 3957 /* Determine what we need to do */
3958 if (ha->current_topology == ISP_CFG_FL &&
3959 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
3960
1da177e4
LT		 3961 set_bit(RSCN_UPDATE, &flags);
3962
3963 } else if (ha->current_topology == ISP_CFG_F &&
3964 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
3965
1da177e4
LT		 3966 set_bit(RSCN_UPDATE, &flags);
3967 clear_bit(LOCAL_LOOP_UPDATE, &flags);
21333b48
AV		 3968
3969 } else if (ha->current_topology == ISP_CFG_N) {
3970 clear_bit(RSCN_UPDATE, &flags);
41dc529a
QT		 3971 } else if (ha->current_topology == ISP_CFG_NL) {
3972 clear_bit(RSCN_UPDATE, &flags);
3973 set_bit(LOCAL_LOOP_UPDATE, &flags);
e315cd28 3974 } else if (!vha->flags.online ||
1da177e4 3975 (test_bit(ABORT_ISP_ACTIVE, &flags))) {
1da177e4
LT		 3976 set_bit(RSCN_UPDATE, &flags);
3977 set_bit(LOCAL_LOOP_UPDATE, &flags);
3978 }
3979
3980 if (test_bit(LOCAL_LOOP_UPDATE, &flags)) {
7c3df132
SK		 3981 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
3982 ql_dbg(ql_dbg_disc, vha, 0x2015,
3983 "Loop resync needed, failing.\n");
1da177e4 3984 rval = QLA_FUNCTION_FAILED;
642ef983 3985 } else
e315cd28 3986 rval = qla2x00_configure_local_loop(vha);
1da177e4
LT		 3987 }
3988
3989 if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
7c3df132
SK		 3990 if (LOOP_TRANSITION(vha)) {
3991 ql_dbg(ql_dbg_disc, vha, 0x201e,
3992 "Needs RSCN update and loop transition.\n");
1da177e4 3993 rval = QLA_FUNCTION_FAILED;
7c3df132 3994 }
e315cd28
AC		 3995 else
3996 rval = qla2x00_configure_fabric(vha);
1da177e4
LT		 3997 }
3998
3999 if (rval == QLA_SUCCESS) {
e315cd28
AC		 4000 if (atomic_read(&vha->loop_down_timer) ||
4001 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4
LT		 4002 rval = QLA_FUNCTION_FAILED;
4003 } else {
e315cd28 4004 atomic_set(&vha->loop_state, LOOP_READY);
7c3df132
SK		 4005 ql_dbg(ql_dbg_disc, vha, 0x2069,
4006 "LOOP READY.\n");
ec7193e2 4007 ha->flags.fw_init_done = 1;
3bb67df5
DKU		 4008
4009 /*
4010 * Process any ATIO queue entries that came in
4011 * while we weren't online.
4012 */
ead03855
QT		 4013 if (qla_tgt_mode_enabled(vha) ||
4014 qla_dual_mode_enabled(vha)) {
3bb67df5
DKU		 4015 if (IS_QLA27XX(ha) || IS_QLA83XX(ha)) {
4016 spin_lock_irqsave(&ha->tgt.atio_lock,
4017 flags);
4018 qlt_24xx_process_atio_queue(vha, 0);
4019 spin_unlock_irqrestore(
4020 &ha->tgt.atio_lock, flags);
4021 } else {
4022 spin_lock_irqsave(&ha->hardware_lock,
4023 flags);
4024 qlt_24xx_process_atio_queue(vha, 1);
4025 spin_unlock_irqrestore(
4026 &ha->hardware_lock, flags);
4027 }
4028 }
1da177e4
LT		 4029 }
4030 }
4031
4032 if (rval) {
7c3df132
SK		 4033 ql_dbg(ql_dbg_disc, vha, 0x206a,
4034 "%s *** FAILED ***.\n", __func__);
1da177e4 4035 } else {
7c3df132
SK		 4036 ql_dbg(ql_dbg_disc, vha, 0x206b,
4037 "%s: exiting normally.\n", __func__);
1da177e4
LT		 4038 }
4039
cc3ef7bc 4040 /* Restore state if a resync event occurred during processing */
e315cd28 4041 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4 4042 if (test_bit(LOCAL_LOOP_UPDATE, &save_flags))
e315cd28 4043 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
f4658b6c 4044 if (test_bit(RSCN_UPDATE, &save_flags)) {
e315cd28 4045 set_bit(RSCN_UPDATE, &vha->dpc_flags);
f4658b6c 4046 }
1da177e4
LT		 4047 }
4048
4049 return (rval);
4050}
4051
4052
4053
4054/*
4055 * qla2x00_configure_local_loop
4056 * Updates Fibre Channel Device Database with local loop devices.
4057 *
4058 * Input:
4059 * ha = adapter block pointer.
4060 *
4061 * Returns:
4062 * 0 = success.
4063 */
4064static int
e315cd28 4065qla2x00_configure_local_loop(scsi_qla_host_t *vha)
1da177e4
LT		 4066{
4067 int rval, rval2;
4068 int found_devs;
4069 int found;
4070 fc_port_t *fcport, *new_fcport;
4071
4072 uint16_t index;
4073 uint16_t entries;
4074 char *id_iter;
4075 uint16_t loop_id;
4076 uint8_t domain, area, al_pa;
e315cd28 4077 struct qla_hw_data *ha = vha->hw;
41dc529a 4078 unsigned long flags;
1da177e4
LT		 4079
4080 found_devs = 0;
4081 new_fcport = NULL;
642ef983 4082 entries = MAX_FIBRE_DEVICES_LOOP;
1da177e4 4083
1da177e4 4084 /* Get list of logged in devices. */
642ef983 4085 memset(ha->gid_list, 0, qla2x00_gid_list_size(ha));
e315cd28 4086 rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma,
1da177e4
LT		 4087 &entries);
4088 if (rval != QLA_SUCCESS)
4089 goto cleanup_allocation;
4090
7c3df132
SK		 4091 ql_dbg(ql_dbg_disc, vha, 0x2017,
4092 "Entries in ID list (%d).\n", entries);
4093 ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
4094 (uint8_t *)ha->gid_list,
4095 entries * sizeof(struct gid_list_info));
1da177e4
LT		 4096
4097 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 4098 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 4099 if (new_fcport == NULL) {
7c3df132
SK		 4100 ql_log(ql_log_warn, vha, 0x2018,
4101 "Memory allocation failed for fcport.\n");
1da177e4
LT		 4102 rval = QLA_MEMORY_ALLOC_FAILED;
4103 goto cleanup_allocation;
4104 }
4105 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
4106
4107 /*
4108 * Mark local devices that were present with FCF_DEVICE_LOST for now.
4109 */
e315cd28 4110 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 4111 if (atomic_read(&fcport->state) == FCS_ONLINE &&
4112 fcport->port_type != FCT_BROADCAST &&
4113 (fcport->flags & FCF_FABRIC_DEVICE) == 0) {
4114
7c3df132
SK		 4115 ql_dbg(ql_dbg_disc, vha, 0x2019,
4116 "Marking port lost loop_id=0x%04x.\n",
4117 fcport->loop_id);
1da177e4 4118
41dc529a 4119 qla2x00_mark_device_lost(vha, fcport, 0, 0);
1da177e4
LT		 4120 }
4121 }
4122
4123 /* Add devices to port list. */
4124 id_iter = (char *)ha->gid_list;
4125 for (index = 0; index < entries; index++) {
4126 domain = ((struct gid_list_info *)id_iter)->domain;
4127 area = ((struct gid_list_info *)id_iter)->area;
4128 al_pa = ((struct gid_list_info *)id_iter)->al_pa;
abbd8870 4129 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1da177e4
LT		 4130 loop_id = (uint16_t)
4131 ((struct gid_list_info *)id_iter)->loop_id_2100;
abbd8870 4132 else
1da177e4
LT		 4133 loop_id = le16_to_cpu(
4134 ((struct gid_list_info *)id_iter)->loop_id);
abbd8870 4135 id_iter += ha->gid_list_info_size;
1da177e4
LT		 4136
4137 /* Bypass reserved domain fields. */
4138 if ((domain & 0xf0) == 0xf0)
4139 continue;
4140
4141 /* Bypass if not same domain and area of adapter. */
f7d289f6 4142 if (area && domain &&
e315cd28 4143 (area != vha->d_id.b.area || domain != vha->d_id.b.domain))
1da177e4
LT		 4144 continue;
4145
4146 /* Bypass invalid local loop ID. */
4147 if (loop_id > LAST_LOCAL_LOOP_ID)
4148 continue;
4149
41dc529a 4150 memset(new_fcport->port_name, 0, WWN_SIZE);
370d550e 4151
1da177e4
LT		 4152 /* Fill in member data. */
4153 new_fcport->d_id.b.domain = domain;
4154 new_fcport->d_id.b.area = area;
4155 new_fcport->d_id.b.al_pa = al_pa;
4156 new_fcport->loop_id = loop_id;
41dc529a 4157
e315cd28 4158 rval2 = qla2x00_get_port_database(vha, new_fcport, 0);
1da177e4 4159 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 4160 ql_dbg(ql_dbg_disc, vha, 0x201a,
4161 "Failed to retrieve fcport information "
4162 "-- get_port_database=%x, loop_id=0x%04x.\n",
4163 rval2, new_fcport->loop_id);
4164 ql_dbg(ql_dbg_disc, vha, 0x201b,
4165 "Scheduling resync.\n");
e315cd28 4166 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4
LT		 4167 continue;
4168 }
4169
41dc529a 4170 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
1da177e4
LT		 4171 /* Check for matching device in port list. */
4172 found = 0;
4173 fcport = NULL;
e315cd28 4174 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 4175 if (memcmp(new_fcport->port_name, fcport->port_name,
4176 WWN_SIZE))
4177 continue;
4178
ddb9b126 4179 fcport->flags &= ~FCF_FABRIC_DEVICE;
1da177e4
LT		 4180 fcport->loop_id = new_fcport->loop_id;
4181 fcport->port_type = new_fcport->port_type;
4182 fcport->d_id.b24 = new_fcport->d_id.b24;
4183 memcpy(fcport->node_name, new_fcport->node_name,
4184 WWN_SIZE);
4185
41dc529a
QT		 4186 if (!fcport->login_succ) {
4187 vha->fcport_count++;
4188 fcport->login_succ = 1;
4189 fcport->disc_state = DSC_LOGIN_COMPLETE;
4190 }
4191
1da177e4
LT		 4192 found++;
4193 break;
4194 }
4195
4196 if (!found) {
4197 /* New device, add to fcports list. */
e315cd28 4198 list_add_tail(&new_fcport->list, &vha->vp_fcports);
1da177e4
LT		 4199
4200 /* Allocate a new replacement fcport. */
4201 fcport = new_fcport;
41dc529a
QT		 4202 if (!fcport->login_succ) {
4203 vha->fcport_count++;
4204 fcport->login_succ = 1;
4205 fcport->disc_state = DSC_LOGIN_COMPLETE;
4206 }
4207
4208 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
4209
e315cd28 4210 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
41dc529a 4211
1da177e4 4212 if (new_fcport == NULL) {
7c3df132
SK		 4213 ql_log(ql_log_warn, vha, 0x201c,
4214 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 4215 rval = QLA_MEMORY_ALLOC_FAILED;
4216 goto cleanup_allocation;
4217 }
41dc529a 4218 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
1da177e4
LT		 4219 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
4220 }
4221
41dc529a
QT		 4222 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
4223
d8b45213 4224 /* Base iIDMA settings on HBA port speed. */
a3cbdfad 4225 fcport->fp_speed = ha->link_data_rate;
d8b45213 4226
e315cd28 4227 qla2x00_update_fcport(vha, fcport);
1da177e4
LT		 4228
4229 found_devs++;
4230 }
4231
4232cleanup_allocation:
c9475cb0 4233 kfree(new_fcport);
1da177e4
LT		 4234
4235 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4236 ql_dbg(ql_dbg_disc, vha, 0x201d,
4237 "Configure local loop error exit: rval=%x.\n", rval);
1da177e4
LT		 4238 }
4239
1da177e4
LT		 4240 return (rval);
4241}
4242
d8b45213 4243static void
e315cd28 4244qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
d8b45213 4245{
d8b45213 4246 int rval;
93f2bd67 4247 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 4248 struct qla_hw_data *ha = vha->hw;
d8b45213 4249
c76f2c01 4250 if (!IS_IIDMA_CAPABLE(ha))
d8b45213
AV		 4251 return;
4252
c9afb9a2
GM		 4253 if (atomic_read(&fcport->state) != FCS_ONLINE)
4254 return;
4255
39bd9622
AV		 4256 if (fcport->fp_speed == PORT_SPEED_UNKNOWN ||
4257 fcport->fp_speed > ha->link_data_rate)
d8b45213
AV		 4258 return;
4259
e315cd28 4260 rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed,
a3cbdfad 4261 mb);
d8b45213 4262 if (rval != QLA_SUCCESS) {
7c3df132 4263 ql_dbg(ql_dbg_disc, vha, 0x2004,
7b833558
OK		 4264 "Unable to adjust iIDMA %8phN -- %04x %x %04x %04x.\n",
4265 fcport->port_name, rval, fcport->fp_speed, mb[0], mb[1]);
d8b45213 4266 } else {
7c3df132 4267 ql_dbg(ql_dbg_disc, vha, 0x2005,
7b833558 4268 "iIDMA adjusted to %s GB/s on %8phN.\n",
d0297c9a 4269 qla2x00_get_link_speed_str(ha, fcport->fp_speed),
7b833558 4270 fcport->port_name);
d8b45213
AV		 4271 }
4272}
4273
726b8548 4274/* qla2x00_reg_remote_port is reserved for Initiator Mode only.*/
23be331d 4275static void
e315cd28 4276qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport)
8482e118
AV		 4277{
4278 struct fc_rport_identifiers rport_ids;
bdf79621 4279 struct fc_rport *rport;
044d78e1 4280 unsigned long flags;
8482e118 4281
f8b02a85
AV		 4282 rport_ids.node_name = wwn_to_u64(fcport->node_name);
4283 rport_ids.port_name = wwn_to_u64(fcport->port_name);
8482e118
AV		 4284 rport_ids.port_id = fcport->d_id.b.domain << 16 |
4285 fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa;
77d74143 4286 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
e315cd28 4287 fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids);
77d74143 4288 if (!rport) {
7c3df132
SK		 4289 ql_log(ql_log_warn, vha, 0x2006,
4290 "Unable to allocate fc remote port.\n");
77d74143
AV		 4291 return;
4292 }
2d70c103 4293
044d78e1 4294 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
19a7b4ae 4295 *((fc_port_t **)rport->dd_data) = fcport;
044d78e1 4296 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
d97994dc 4297
ad3e0eda 4298 rport->supported_classes = fcport->supported_classes;
77d74143 4299
8482e118
AV		 4300 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
4301 if (fcport->port_type == FCT_INITIATOR)
4302 rport_ids.roles |= FC_RPORT_ROLE_FCP_INITIATOR;
4303 if (fcport->port_type == FCT_TARGET)
4304 rport_ids.roles |= FC_RPORT_ROLE_FCP_TARGET;
726b8548
QT		 4305
4306 ql_dbg(ql_dbg_disc, vha, 0xffff,
4307 "%s %8phN. rport %p is %s mode \n",
4308 __func__, fcport->port_name, rport,
4309 (fcport->port_type == FCT_TARGET) ? "tgt" : "ini");
4310
77d74143 4311 fc_remote_port_rolechg(rport, rport_ids.roles);
1da177e4
LT		 4312}
4313
23be331d
AB		 4314/*
4315 * qla2x00_update_fcport
4316 * Updates device on list.
4317 *
4318 * Input:
4319 * ha = adapter block pointer.
4320 * fcport = port structure pointer.
4321 *
4322 * Return:
4323 * 0 - Success
4324 * BIT_0 - error
4325 *
4326 * Context:
4327 * Kernel context.
4328 */
4329void
e315cd28 4330qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
23be331d 4331{
e315cd28 4332 fcport->vha = vha;
8ae6d9c7 4333
726b8548
QT		 4334 if (IS_SW_RESV_ADDR(fcport->d_id))
4335 return;
4336
4337 ql_dbg(ql_dbg_disc, vha, 0xffff, "%s %8phC \n",
4338 __func__, fcport->port_name);
4339
8ae6d9c7
GM		 4340 if (IS_QLAFX00(vha->hw)) {
4341 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
d20ed91b 4342 goto reg_port;
8ae6d9c7 4343 }
23be331d 4344 fcport->login_retry = 0;
5ff1d584 4345 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
726b8548
QT		 4346 fcport->disc_state = DSC_LOGIN_COMPLETE;
4347 fcport->deleted = 0;
4348 fcport->logout_on_delete = 1;
23be331d 4349
1f93da52 4350 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
e315cd28 4351 qla2x00_iidma_fcport(vha, fcport);
21090cbe 4352 qla24xx_update_fcport_fcp_prio(vha, fcport);
d20ed91b
AP		 4353
4354reg_port:
726b8548
QT		 4355 switch (vha->host->active_mode) {
4356 case MODE_INITIATOR:
d20ed91b 4357 qla2x00_reg_remote_port(vha, fcport);
726b8548
QT		 4358 break;
4359 case MODE_TARGET:
4360 if (!vha->vha_tgt.qla_tgt->tgt_stop &&
4361 !vha->vha_tgt.qla_tgt->tgt_stopped)
4362 qlt_fc_port_added(vha, fcport);
4363 break;
4364 case MODE_DUAL:
d20ed91b 4365 qla2x00_reg_remote_port(vha, fcport);
726b8548
QT		 4366 if (!vha->vha_tgt.qla_tgt->tgt_stop &&
4367 !vha->vha_tgt.qla_tgt->tgt_stopped)
4368 qlt_fc_port_added(vha, fcport);
4369 break;
4370 default:
4371 break;
d20ed91b 4372 }
23be331d
AB		 4373}
4374
1da177e4
LT		 4375/*
4376 * qla2x00_configure_fabric
4377 * Setup SNS devices with loop ID's.
4378 *
4379 * Input:
4380 * ha = adapter block pointer.
4381 *
4382 * Returns:
4383 * 0 = success.
4384 * BIT_0 = error
4385 */
4386static int
e315cd28 4387qla2x00_configure_fabric(scsi_qla_host_t *vha)
1da177e4 4388{
b3b02e6e 4389 int rval;
726b8548 4390 fc_port_t *fcport;
1da177e4 4391 uint16_t mb[MAILBOX_REGISTER_COUNT];
0107109e 4392 uint16_t loop_id;
1da177e4 4393 LIST_HEAD(new_fcports);
e315cd28 4394 struct qla_hw_data *ha = vha->hw;
df673274 4395 int discovery_gen;
1da177e4
LT		 4396
4397 /* If FL port exists, then SNS is present */
e428924c 4398 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 4399 loop_id = NPH_F_PORT;
4400 else
4401 loop_id = SNS_FL_PORT;
e315cd28 4402 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1);
1da177e4 4403 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4404 ql_dbg(ql_dbg_disc, vha, 0x201f,
4405 "MBX_GET_PORT_NAME failed, No FL Port.\n");
1da177e4 4406
e315cd28 4407 vha->device_flags &= ~SWITCH_FOUND;
1da177e4
LT		 4408 return (QLA_SUCCESS);
4409 }
e315cd28 4410 vha->device_flags |= SWITCH_FOUND;
1da177e4 4411
41dc529a
QT		 4412
4413 if (qla_tgt_mode_enabled(vha) || qla_dual_mode_enabled(vha)) {
4414 rval = qla2x00_send_change_request(vha, 0x3, 0);
4415 if (rval != QLA_SUCCESS)
4416 ql_log(ql_log_warn, vha, 0x121,
4417 "Failed to enable receiving of RSCN requests: 0x%x.\n",
4418 rval);
4419 }
4420
4421
1da177e4 4422 do {
726b8548
QT		 4423 qla2x00_mgmt_svr_login(vha);
4424
cca5335c
AV		 4425 /* FDMI support. */
4426 if (ql2xfdmienable &&
e315cd28
AC		 4427 test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags))
4428 qla2x00_fdmi_register(vha);
cca5335c 4429
1da177e4 4430 /* Ensure we are logged into the SNS. */
e428924c 4431 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 4432 loop_id = NPH_SNS;
4433 else
4434 loop_id = SIMPLE_NAME_SERVER;
0b91d116
CD		 4435 rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff,
4436 0xfc, mb, BIT_1|BIT_0);
4437 if (rval != QLA_SUCCESS) {
4438 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
e452ceb6 4439 return rval;
0b91d116 4440 }
1da177e4 4441 if (mb[0] != MBS_COMMAND_COMPLETE) {
7c3df132
SK		 4442 ql_dbg(ql_dbg_disc, vha, 0x2042,
4443 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x "
4444 "mb[6]=%x mb[7]=%x.\n", loop_id, mb[0], mb[1],
4445 mb[2], mb[6], mb[7]);
1da177e4
LT		 4446 return (QLA_SUCCESS);
4447 }
4448
e315cd28
AC		 4449 if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) {
4450 if (qla2x00_rft_id(vha)) {
1da177e4 4451 /* EMPTY */
7c3df132
SK		 4452 ql_dbg(ql_dbg_disc, vha, 0x2045,
4453 "Register FC-4 TYPE failed.\n");
1da177e4 4454 }
e315cd28 4455 if (qla2x00_rff_id(vha)) {
1da177e4 4456 /* EMPTY */
7c3df132
SK		 4457 ql_dbg(ql_dbg_disc, vha, 0x2049,
4458 "Register FC-4 Features failed.\n");
1da177e4 4459 }
e315cd28 4460 if (qla2x00_rnn_id(vha)) {
1da177e4 4461 /* EMPTY */
7c3df132
SK		 4462 ql_dbg(ql_dbg_disc, vha, 0x204f,
4463 "Register Node Name failed.\n");
e315cd28 4464 } else if (qla2x00_rsnn_nn(vha)) {
1da177e4 4465 /* EMPTY */
7c3df132
SK		 4466 ql_dbg(ql_dbg_disc, vha, 0x2053,
4467 "Register Symobilic Node Name failed.\n");
1da177e4
LT		 4468 }
4469 }
4470
827210ba
JC		 4471 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4472 fcport->scan_state = QLA_FCPORT_SCAN;
4473 }
4474
df673274
AP		 4475 /* Mark the time right before querying FW for connected ports.
4476 * This process is long, asynchronous and by the time it's done,
4477 * collected information might not be accurate anymore. E.g.
4478 * disconnected port might have re-connected and a brand new
4479 * session has been created. In this case session's generation
4480 * will be newer than discovery_gen. */
4481 qlt_do_generation_tick(vha, &discovery_gen);
4482
726b8548 4483 rval = qla2x00_find_all_fabric_devs(vha);
1da177e4
LT		 4484 if (rval != QLA_SUCCESS)
4485 break;
1da177e4
LT		 4486 } while (0);
4487
726b8548 4488 if (rval)
7c3df132
SK		 4489 ql_dbg(ql_dbg_disc, vha, 0x2068,
4490 "Configure fabric error exit rval=%d.\n", rval);
1da177e4
LT		 4491
4492 return (rval);
4493}
4494
1da177e4
LT		 4495/*
4496 * qla2x00_find_all_fabric_devs
4497 *
4498 * Input:
4499 * ha = adapter block pointer.
4500 * dev = database device entry pointer.
4501 *
4502 * Returns:
4503 * 0 = success.
4504 *
4505 * Context:
4506 * Kernel context.
4507 */
4508static int
726b8548 4509qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha)
1da177e4
LT		 4510{
4511 int rval;
4512 uint16_t loop_id;
726b8548 4513 fc_port_t *fcport, *new_fcport;
1da177e4
LT		 4514 int found;
4515
4516 sw_info_t *swl;
4517 int swl_idx;
4518 int first_dev, last_dev;
1516ef44 4519 port_id_t wrap = {}, nxt_d_id;
e315cd28 4520 struct qla_hw_data *ha = vha->hw;
bb4cf5b7 4521 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
726b8548 4522 unsigned long flags;
1da177e4
LT		 4523
4524 rval = QLA_SUCCESS;
4525
4526 /* Try GID_PT to get device list, else GAN. */
7a67735b 4527 if (!ha->swl)
642ef983 4528 ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t),
7a67735b
AV		 4529 GFP_KERNEL);
4530 swl = ha->swl;
bbfbbbc1 4531 if (!swl) {
1da177e4 4532 /*EMPTY*/
7c3df132
SK		 4533 ql_dbg(ql_dbg_disc, vha, 0x2054,
4534 "GID_PT allocations failed, fallback on GA_NXT.\n");
1da177e4 4535 } else {
642ef983 4536 memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t));
e315cd28 4537 if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) {
1da177e4 4538 swl = NULL;
e315cd28 4539 } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 4540 swl = NULL;
e315cd28 4541 } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 4542 swl = NULL;
726b8548
QT		 4543 } else if (qla2x00_gfpn_id(vha, swl) != QLA_SUCCESS) {
4544 swl = NULL;
1da177e4 4545 }
e8c72ba5
CD		 4546
4547 /* If other queries succeeded probe for FC-4 type */
4548 if (swl)
4549 qla2x00_gff_id(vha, swl);
1da177e4
LT		 4550 }
4551 swl_idx = 0;
4552
4553 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 4554 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 4555 if (new_fcport == NULL) {
7c3df132
SK		 4556 ql_log(ql_log_warn, vha, 0x205e,
4557 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 4558 return (QLA_MEMORY_ALLOC_FAILED);
4559 }
4560 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
1da177e4
LT		 4561 /* Set start port ID scan at adapter ID. */
4562 first_dev = 1;
4563 last_dev = 0;
4564
4565 /* Starting free loop ID. */
e315cd28
AC		 4566 loop_id = ha->min_external_loopid;
4567 for (; loop_id <= ha->max_loop_id; loop_id++) {
4568 if (qla2x00_is_reserved_id(vha, loop_id))
1da177e4
LT		 4569 continue;
4570
3a6478df
GM		 4571 if (ha->current_topology == ISP_CFG_FL &&
4572 (atomic_read(&vha->loop_down_timer) ||
4573 LOOP_TRANSITION(vha))) {
bb2d52b2
AV		 4574 atomic_set(&vha->loop_down_timer, 0);
4575 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
4576 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
1da177e4 4577 break;
bb2d52b2 4578 }
1da177e4
LT		 4579
4580 if (swl != NULL) {
4581 if (last_dev) {
4582 wrap.b24 = new_fcport->d_id.b24;
4583 } else {
4584 new_fcport->d_id.b24 = swl[swl_idx].d_id.b24;
4585 memcpy(new_fcport->node_name,
4586 swl[swl_idx].node_name, WWN_SIZE);
4587 memcpy(new_fcport->port_name,
4588 swl[swl_idx].port_name, WWN_SIZE);
d8b45213
AV		 4589 memcpy(new_fcport->fabric_port_name,
4590 swl[swl_idx].fabric_port_name, WWN_SIZE);
4591 new_fcport->fp_speed = swl[swl_idx].fp_speed;
e8c72ba5 4592 new_fcport->fc4_type = swl[swl_idx].fc4_type;
1da177e4
LT		 4593
4594 if (swl[swl_idx].d_id.b.rsvd_1 != 0) {
4595 last_dev = 1;
4596 }
4597 swl_idx++;
4598 }
4599 } else {
4600 /* Send GA_NXT to the switch */
e315cd28 4601 rval = qla2x00_ga_nxt(vha, new_fcport);
1da177e4 4602 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4603 ql_log(ql_log_warn, vha, 0x2064,
4604 "SNS scan failed -- assuming "
4605 "zero-entry result.\n");
1da177e4
LT		 4606 rval = QLA_SUCCESS;
4607 break;
4608 }
4609 }
4610
4611 /* If wrap on switch device list, exit. */
4612 if (first_dev) {
4613 wrap.b24 = new_fcport->d_id.b24;
4614 first_dev = 0;
4615 } else if (new_fcport->d_id.b24 == wrap.b24) {
7c3df132
SK		 4616 ql_dbg(ql_dbg_disc, vha, 0x2065,
4617 "Device wrap (%02x%02x%02x).\n",
4618 new_fcport->d_id.b.domain,
4619 new_fcport->d_id.b.area,
4620 new_fcport->d_id.b.al_pa);
1da177e4
LT		 4621 break;
4622 }
4623
2c3dfe3f 4624 /* Bypass if same physical adapter. */
e315cd28 4625 if (new_fcport->d_id.b24 == base_vha->d_id.b24)
1da177e4
LT		 4626 continue;
4627
2c3dfe3f 4628 /* Bypass virtual ports of the same host. */
bb4cf5b7
CD		 4629 if (qla2x00_is_a_vp_did(vha, new_fcport->d_id.b24))
4630 continue;
2c3dfe3f 4631
f7d289f6
AV		 4632 /* Bypass if same domain and area of adapter. */
4633 if (((new_fcport->d_id.b24 & 0xffff00) ==
e315cd28 4634 (vha->d_id.b24 & 0xffff00)) && ha->current_topology ==
f7d289f6
AV		 4635 ISP_CFG_FL)
4636 continue;
4637
1da177e4
LT		 4638 /* Bypass reserved domain fields. */
4639 if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0)
4640 continue;
4641
e8c72ba5 4642 /* Bypass ports whose FCP-4 type is not FCP_SCSI */
4da26e16
CD		 4643 if (ql2xgffidenable &&
4644 (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI &&
4645 new_fcport->fc4_type != FC4_TYPE_UNKNOWN))
e8c72ba5
CD		 4646 continue;
4647
726b8548
QT		 4648 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
4649
1da177e4
LT		 4650 /* Locate matching device in database. */
4651 found = 0;
e315cd28 4652 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 4653 if (memcmp(new_fcport->port_name, fcport->port_name,
4654 WWN_SIZE))
4655 continue;
4656
827210ba 4657 fcport->scan_state = QLA_FCPORT_FOUND;
b3b02e6e 4658
1da177e4
LT		 4659 found++;
4660
d8b45213
AV		 4661 /* Update port state. */
4662 memcpy(fcport->fabric_port_name,
4663 new_fcport->fabric_port_name, WWN_SIZE);
4664 fcport->fp_speed = new_fcport->fp_speed;
4665
1da177e4 4666 /*
b2032fd5
RD		 4667 * If address the same and state FCS_ONLINE
4668 * (or in target mode), nothing changed.
1da177e4
LT		 4669 */
4670 if (fcport->d_id.b24 == new_fcport->d_id.b24 &&
b2032fd5 4671 (atomic_read(&fcport->state) == FCS_ONLINE ||
726b8548 4672 (vha->host->active_mode == MODE_TARGET))) {
1da177e4
LT		 4673 break;
4674 }
4675
4676 /*
4677 * If device was not a fabric device before.
4678 */
4679 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) {
4680 fcport->d_id.b24 = new_fcport->d_id.b24;
5f16b331 4681 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 4682 fcport->flags |= (FCF_FABRIC_DEVICE |
4683 FCF_LOGIN_NEEDED);
1da177e4
LT		 4684 break;
4685 }
4686
4687 /*
4688 * Port ID changed or device was marked to be updated;
4689 * Log it out if still logged in and mark it for
4690 * relogin later.
4691 */
726b8548 4692 if (qla_tgt_mode_enabled(base_vha)) {
b2032fd5
RD		 4693 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf080,
4694 "port changed FC ID, %8phC"
4695 " old %x:%x:%x (loop_id 0x%04x)-> new %x:%x:%x\n",
4696 fcport->port_name,
4697 fcport->d_id.b.domain,
4698 fcport->d_id.b.area,
4699 fcport->d_id.b.al_pa,
4700 fcport->loop_id,
4701 new_fcport->d_id.b.domain,
4702 new_fcport->d_id.b.area,
4703 new_fcport->d_id.b.al_pa);
4704 fcport->d_id.b24 = new_fcport->d_id.b24;
4705 break;
4706 }
4707
1da177e4
LT		 4708 fcport->d_id.b24 = new_fcport->d_id.b24;
4709 fcport->flags |= FCF_LOGIN_NEEDED;
1da177e4
LT		 4710 break;
4711 }
4712
726b8548
QT		 4713 if (found) {
4714 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1da177e4 4715 continue;
726b8548 4716 }
1da177e4 4717 /* If device was not in our fcports list, then add it. */
b2032fd5 4718 new_fcport->scan_state = QLA_FCPORT_FOUND;
726b8548
QT		 4719 list_add_tail(&new_fcport->list, &vha->vp_fcports);
4720
4721 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
4722
1da177e4
LT		 4723
4724 /* Allocate a new replacement fcport. */
4725 nxt_d_id.b24 = new_fcport->d_id.b24;
e315cd28 4726 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 4727 if (new_fcport == NULL) {
7c3df132
SK		 4728 ql_log(ql_log_warn, vha, 0x2066,
4729 "Memory allocation failed for fcport.\n");
1da177e4
LT		 4730 return (QLA_MEMORY_ALLOC_FAILED);
4731 }
4732 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
4733 new_fcport->d_id.b24 = nxt_d_id.b24;
4734 }
4735
726b8548
QT		 4736 qla2x00_free_fcport(new_fcport);
4737
4738 /*
4739 * Logout all previous fabric dev marked lost, except FCP2 devices.
4740 */
4741 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4742 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4743 break;
4744
4745 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0 ||
4746 (fcport->flags & FCF_LOGIN_NEEDED) == 0)
4747 continue;
4748
4749 if (fcport->scan_state == QLA_FCPORT_SCAN) {
4750 if ((qla_dual_mode_enabled(vha) ||
4751 qla_ini_mode_enabled(vha)) &&
4752 atomic_read(&fcport->state) == FCS_ONLINE) {
4753 qla2x00_mark_device_lost(vha, fcport,
4754 ql2xplogiabsentdevice, 0);
4755 if (fcport->loop_id != FC_NO_LOOP_ID &&
4756 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
4757 fcport->port_type != FCT_INITIATOR &&
4758 fcport->port_type != FCT_BROADCAST) {
4759 ql_dbg(ql_dbg_disc, vha, 0xffff,
4760 "%s %d %8phC post del sess\n",
4761 __func__, __LINE__,
4762 fcport->port_name);
4763
4764 qlt_schedule_sess_for_deletion_lock
4765 (fcport);
4766 continue;
4767 }
4768 }
4769 }
1da177e4 4770
726b8548
QT		 4771 if (fcport->scan_state == QLA_FCPORT_FOUND)
4772 qla24xx_fcport_handle_login(vha, fcport);
4773 }
1da177e4
LT		 4774 return (rval);
4775}
4776
4777/*
4778 * qla2x00_find_new_loop_id
4779 * Scan through our port list and find a new usable loop ID.
4780 *
4781 * Input:
4782 * ha: adapter state pointer.
4783 * dev: port structure pointer.
4784 *
4785 * Returns:
4786 * qla2x00 local function return status code.
4787 *
4788 * Context:
4789 * Kernel context.
4790 */
03bcfb57 4791int
e315cd28 4792qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
1da177e4
LT		 4793{
4794 int rval;
e315cd28 4795 struct qla_hw_data *ha = vha->hw;
feafb7b1 4796 unsigned long flags = 0;
1da177e4
LT		 4797
4798 rval = QLA_SUCCESS;
4799
5f16b331 4800 spin_lock_irqsave(&ha->vport_slock, flags);
1da177e4 4801
5f16b331
CD		 4802 dev->loop_id = find_first_zero_bit(ha->loop_id_map,
4803 LOOPID_MAP_SIZE);
4804 if (dev->loop_id >= LOOPID_MAP_SIZE ||
4805 qla2x00_is_reserved_id(vha, dev->loop_id)) {
4806 dev->loop_id = FC_NO_LOOP_ID;
4807 rval = QLA_FUNCTION_FAILED;
4808 } else
4809 set_bit(dev->loop_id, ha->loop_id_map);
1da177e4 4810
5f16b331 4811 spin_unlock_irqrestore(&ha->vport_slock, flags);
1da177e4 4812
5f16b331
CD		 4813 if (rval == QLA_SUCCESS)
4814 ql_dbg(ql_dbg_disc, dev->vha, 0x2086,
4815 "Assigning new loopid=%x, portid=%x.\n",
4816 dev->loop_id, dev->d_id.b24);
4817 else
4818 ql_log(ql_log_warn, dev->vha, 0x2087,
4819 "No loop_id's available, portid=%x.\n",
4820 dev->d_id.b24);
1da177e4
LT		 4821
4822 return (rval);
4823}
4824
1da177e4
LT		 4825
4826/*
4827 * qla2x00_fabric_login
4828 * Issue fabric login command.
4829 *
4830 * Input:
4831 * ha = adapter block pointer.
4832 * device = pointer to FC device type structure.
4833 *
4834 * Returns:
4835 * 0 - Login successfully
4836 * 1 - Login failed
4837 * 2 - Initiator device
4838 * 3 - Fatal error
4839 */
4840int
e315cd28 4841qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 4842 uint16_t *next_loopid)
4843{
4844 int rval;
4845 int retry;
4846 uint16_t tmp_loopid;
4847 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 4848 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 4849
4850 retry = 0;
4851 tmp_loopid = 0;
4852
4853 for (;;) {
7c3df132
SK		 4854 ql_dbg(ql_dbg_disc, vha, 0x2000,
4855 "Trying Fabric Login w/loop id 0x%04x for port "
4856 "%02x%02x%02x.\n",
4857 fcport->loop_id, fcport->d_id.b.domain,
4858 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 4859
4860 /* Login fcport on switch. */
0b91d116 4861 rval = ha->isp_ops->fabric_login(vha, fcport->loop_id,
1da177e4
LT		 4862 fcport->d_id.b.domain, fcport->d_id.b.area,
4863 fcport->d_id.b.al_pa, mb, BIT_0);
0b91d116
CD		 4864 if (rval != QLA_SUCCESS) {
4865 return rval;
4866 }
1da177e4
LT		 4867 if (mb[0] == MBS_PORT_ID_USED) {
4868 /*
4869 * Device has another loop ID. The firmware team
0107109e
AV		 4870 * recommends the driver perform an implicit login with
4871 * the specified ID again. The ID we just used is save
4872 * here so we return with an ID that can be tried by
4873 * the next login.
1da177e4
LT		 4874 */
4875 retry++;
4876 tmp_loopid = fcport->loop_id;
4877 fcport->loop_id = mb[1];
4878
7c3df132
SK		 4879 ql_dbg(ql_dbg_disc, vha, 0x2001,
4880 "Fabric Login: port in use - next loop "
4881 "id=0x%04x, port id= %02x%02x%02x.\n",
1da177e4 4882 fcport->loop_id, fcport->d_id.b.domain,
7c3df132 4883 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 4884
4885 } else if (mb[0] == MBS_COMMAND_COMPLETE) {
4886 /*
4887 * Login succeeded.
4888 */
4889 if (retry) {
4890 /* A retry occurred before. */
4891 *next_loopid = tmp_loopid;
4892 } else {
4893 /*
4894 * No retry occurred before. Just increment the
4895 * ID value for next login.
4896 */
4897 *next_loopid = (fcport->loop_id + 1);
4898 }
4899
4900 if (mb[1] & BIT_0) {
4901 fcport->port_type = FCT_INITIATOR;
4902 } else {
4903 fcport->port_type = FCT_TARGET;
4904 if (mb[1] & BIT_1) {
8474f3a0 4905 fcport->flags |= FCF_FCP2_DEVICE;
1da177e4
LT		 4906 }
4907 }
4908
ad3e0eda
AV		 4909 if (mb[10] & BIT_0)
4910 fcport->supported_classes |= FC_COS_CLASS2;
4911 if (mb[10] & BIT_1)
4912 fcport->supported_classes |= FC_COS_CLASS3;
4913
2d70c103
NB		 4914 if (IS_FWI2_CAPABLE(ha)) {
4915 if (mb[10] & BIT_7)
4916 fcport->flags |=
4917 FCF_CONF_COMP_SUPPORTED;
4918 }
4919
1da177e4
LT		 4920 rval = QLA_SUCCESS;
4921 break;
4922 } else if (mb[0] == MBS_LOOP_ID_USED) {
4923 /*
4924 * Loop ID already used, try next loop ID.
4925 */
4926 fcport->loop_id++;
e315cd28 4927 rval = qla2x00_find_new_loop_id(vha, fcport);
1da177e4
LT		 4928 if (rval != QLA_SUCCESS) {
4929 /* Ran out of loop IDs to use */
4930 break;
4931 }
4932 } else if (mb[0] == MBS_COMMAND_ERROR) {
4933 /*
4934 * Firmware possibly timed out during login. If NO
4935 * retries are left to do then the device is declared
4936 * dead.
4937 */
4938 *next_loopid = fcport->loop_id;
e315cd28 4939 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 4940 fcport->d_id.b.domain, fcport->d_id.b.area,
4941 fcport->d_id.b.al_pa);
e315cd28 4942 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 4943
4944 rval = 1;
4945 break;
4946 } else {
4947 /*
4948 * unrecoverable / not handled error
4949 */
7c3df132
SK		 4950 ql_dbg(ql_dbg_disc, vha, 0x2002,
4951 "Failed=%x port_id=%02x%02x%02x loop_id=%x "
4952 "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain,
4953 fcport->d_id.b.area, fcport->d_id.b.al_pa,
4954 fcport->loop_id, jiffies);
1da177e4
LT		 4955
4956 *next_loopid = fcport->loop_id;
e315cd28 4957 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 4958 fcport->d_id.b.domain, fcport->d_id.b.area,
4959 fcport->d_id.b.al_pa);
5f16b331 4960 qla2x00_clear_loop_id(fcport);
0eedfcf0 4961 fcport->login_retry = 0;
1da177e4
LT		 4962
4963 rval = 3;
4964 break;
4965 }
4966 }
4967
4968 return (rval);
4969}
4970
4971/*
4972 * qla2x00_local_device_login
4973 * Issue local device login command.
4974 *
4975 * Input:
4976 * ha = adapter block pointer.
4977 * loop_id = loop id of device to login to.
4978 *
4979 * Returns (Where's the #define!!!!):
4980 * 0 - Login successfully
4981 * 1 - Login failed
4982 * 3 - Fatal error
4983 */
4984int
e315cd28 4985qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport)
1da177e4
LT		 4986{
4987 int rval;
4988 uint16_t mb[MAILBOX_REGISTER_COUNT];
4989
4990 memset(mb, 0, sizeof(mb));
e315cd28 4991 rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0);
1da177e4
LT		 4992 if (rval == QLA_SUCCESS) {
4993 /* Interrogate mailbox registers for any errors */
4994 if (mb[0] == MBS_COMMAND_ERROR)
4995 rval = 1;
4996 else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR)
4997 /* device not in PCB table */
4998 rval = 3;
4999 }
5000
5001 return (rval);
5002}
5003
5004/*
5005 * qla2x00_loop_resync
5006 * Resync with fibre channel devices.
5007 *
5008 * Input:
5009 * ha = adapter block pointer.
5010 *
5011 * Returns:
5012 * 0 = success
5013 */
5014int
e315cd28 5015qla2x00_loop_resync(scsi_qla_host_t *vha)
1da177e4 5016{
73208dfd 5017 int rval = QLA_SUCCESS;
1da177e4 5018 uint32_t wait_time;
67c2e93a
AC		 5019 struct req_que *req;
5020 struct rsp_que *rsp;
5021
d7459527 5022 req = vha->req;
67c2e93a 5023 rsp = req->rsp;
1da177e4 5024
e315cd28
AC		 5025 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
5026 if (vha->flags.online) {
5027 if (!(rval = qla2x00_fw_ready(vha))) {
1da177e4
LT		 5028 /* Wait at most MAX_TARGET RSCNs for a stable link. */
5029 wait_time = 256;
5030 do {
8ae6d9c7
GM		 5031 if (!IS_QLAFX00(vha->hw)) {
5032 /*
5033 * Issue a marker after FW becomes
5034 * ready.
5035 */
5036 qla2x00_marker(vha, req, rsp, 0, 0,
5037 MK_SYNC_ALL);
5038 vha->marker_needed = 0;
5039 }
1da177e4
LT		 5040
5041 /* Remap devices on Loop. */
e315cd28 5042 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4 5043
8ae6d9c7
GM		 5044 if (IS_QLAFX00(vha->hw))
5045 qlafx00_configure_devices(vha);
5046 else
5047 qla2x00_configure_loop(vha);
5048
1da177e4 5049 wait_time--;
e315cd28
AC		 5050 } while (!atomic_read(&vha->loop_down_timer) &&
5051 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
5052 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
5053 &vha->dpc_flags)));
1da177e4 5054 }
1da177e4
LT		 5055 }
5056
e315cd28 5057 if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
1da177e4 5058 return (QLA_FUNCTION_FAILED);
1da177e4 5059
e315cd28 5060 if (rval)
7c3df132
SK		 5061 ql_dbg(ql_dbg_disc, vha, 0x206c,
5062 "%s *** FAILED ***.\n", __func__);
1da177e4
LT		 5063
5064 return (rval);
5065}
5066
579d12b5
SK		 5067/*
5068* qla2x00_perform_loop_resync
5069* Description: This function will set the appropriate flags and call
5070* qla2x00_loop_resync. If successful loop will be resynced
5071* Arguments : scsi_qla_host_t pointer
5072* returm : Success or Failure
5073*/
5074
5075int qla2x00_perform_loop_resync(scsi_qla_host_t *ha)
5076{
5077 int32_t rval = 0;
5078
5079 if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) {
5080 /*Configure the flags so that resync happens properly*/
5081 atomic_set(&ha->loop_down_timer, 0);
5082 if (!(ha->device_flags & DFLG_NO_CABLE)) {
5083 atomic_set(&ha->loop_state, LOOP_UP);
5084 set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags);
5085 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
5086 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
5087
5088 rval = qla2x00_loop_resync(ha);
5089 } else
5090 atomic_set(&ha->loop_state, LOOP_DEAD);
5091
5092 clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags);
5093 }
5094
5095 return rval;
5096}
5097
d97994dc 5098void
67becc00 5099qla2x00_update_fcports(scsi_qla_host_t *base_vha)
d97994dc
AV		 5100{
5101 fc_port_t *fcport;
feafb7b1
AE		 5102 struct scsi_qla_host *vha;
5103 struct qla_hw_data *ha = base_vha->hw;
5104 unsigned long flags;
d97994dc 5105
feafb7b1 5106 spin_lock_irqsave(&ha->vport_slock, flags);
d97994dc 5107 /* Go with deferred removal of rport references. */
feafb7b1
AE		 5108 list_for_each_entry(vha, &base_vha->hw->vp_list, list) {
5109 atomic_inc(&vha->vref_count);
5110 list_for_each_entry(fcport, &vha->vp_fcports, list) {
8ae598d0 5111 if (fcport->drport &&
feafb7b1
AE		 5112 atomic_read(&fcport->state) != FCS_UNCONFIGURED) {
5113 spin_unlock_irqrestore(&ha->vport_slock, flags);
67becc00 5114 qla2x00_rport_del(fcport);
df673274 5115
feafb7b1
AE		 5116 spin_lock_irqsave(&ha->vport_slock, flags);
5117 }
5118 }
5119 atomic_dec(&vha->vref_count);
c4a9b538 5120 wake_up(&vha->vref_waitq);
feafb7b1
AE		 5121 }
5122 spin_unlock_irqrestore(&ha->vport_slock, flags);
d97994dc
AV		 5123}
5124
7d613ac6
SV		 5125/* Assumes idc_lock always held on entry */
5126void
5127qla83xx_reset_ownership(scsi_qla_host_t *vha)
5128{
5129 struct qla_hw_data *ha = vha->hw;
5130 uint32_t drv_presence, drv_presence_mask;
5131 uint32_t dev_part_info1, dev_part_info2, class_type;
5132 uint32_t class_type_mask = 0x3;
5133 uint16_t fcoe_other_function = 0xffff, i;
5134
7ec0effd
AD		 5135 if (IS_QLA8044(ha)) {
5136 drv_presence = qla8044_rd_direct(vha,
5137 QLA8044_CRB_DRV_ACTIVE_INDEX);
5138 dev_part_info1 = qla8044_rd_direct(vha,
5139 QLA8044_CRB_DEV_PART_INFO_INDEX);
5140 dev_part_info2 = qla8044_rd_direct(vha,
5141 QLA8044_CRB_DEV_PART_INFO2);
5142 } else {
5143 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5144 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1);
5145 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2);
5146 }
7d613ac6
SV		 5147 for (i = 0; i < 8; i++) {
5148 class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask);
5149 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
5150 (i != ha->portnum)) {
5151 fcoe_other_function = i;
5152 break;
5153 }
5154 }
5155 if (fcoe_other_function == 0xffff) {
5156 for (i = 0; i < 8; i++) {
5157 class_type = ((dev_part_info2 >> (i * 4)) &
5158 class_type_mask);
5159 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
5160 ((i + 8) != ha->portnum)) {
5161 fcoe_other_function = i + 8;
5162 break;
5163 }
5164 }
5165 }
5166 /*
5167 * Prepare drv-presence mask based on fcoe functions present.
5168 * However consider only valid physical fcoe function numbers (0-15).
5169 */
5170 drv_presence_mask = ~((1 << (ha->portnum)) |
5171 ((fcoe_other_function == 0xffff) ?
5172 0 : (1 << (fcoe_other_function))));
5173
5174 /* We are the reset owner iff:
5175 * - No other protocol drivers present.
5176 * - This is the lowest among fcoe functions. */
5177 if (!(drv_presence & drv_presence_mask) &&
5178 (ha->portnum < fcoe_other_function)) {
5179 ql_dbg(ql_dbg_p3p, vha, 0xb07f,
5180 "This host is Reset owner.\n");
5181 ha->flags.nic_core_reset_owner = 1;
5182 }
5183}
5184
fa492630 5185static int
7d613ac6
SV		 5186__qla83xx_set_drv_ack(scsi_qla_host_t *vha)
5187{
5188 int rval = QLA_SUCCESS;
5189 struct qla_hw_data *ha = vha->hw;
5190 uint32_t drv_ack;
5191
5192 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
5193 if (rval == QLA_SUCCESS) {
5194 drv_ack |= (1 << ha->portnum);
5195 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
5196 }
5197
5198 return rval;
5199}
5200
fa492630 5201static int
7d613ac6
SV		 5202__qla83xx_clear_drv_ack(scsi_qla_host_t *vha)
5203{
5204 int rval = QLA_SUCCESS;
5205 struct qla_hw_data *ha = vha->hw;
5206 uint32_t drv_ack;
5207
5208 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
5209 if (rval == QLA_SUCCESS) {
5210 drv_ack &= ~(1 << ha->portnum);
5211 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
5212 }
5213
5214 return rval;
5215}
5216
fa492630 5217static const char *
7d613ac6
SV		 5218qla83xx_dev_state_to_string(uint32_t dev_state)
5219{
5220 switch (dev_state) {
5221 case QLA8XXX_DEV_COLD:
5222 return "COLD/RE-INIT";
5223 case QLA8XXX_DEV_INITIALIZING:
5224 return "INITIALIZING";
5225 case QLA8XXX_DEV_READY:
5226 return "READY";
5227 case QLA8XXX_DEV_NEED_RESET:
5228 return "NEED RESET";
5229 case QLA8XXX_DEV_NEED_QUIESCENT:
5230 return "NEED QUIESCENT";
5231 case QLA8XXX_DEV_FAILED:
5232 return "FAILED";
5233 case QLA8XXX_DEV_QUIESCENT:
5234 return "QUIESCENT";
5235 default:
5236 return "Unknown";
5237 }
5238}
5239
5240/* Assumes idc-lock always held on entry */
5241void
5242qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type)
5243{
5244 struct qla_hw_data *ha = vha->hw;
5245 uint32_t idc_audit_reg = 0, duration_secs = 0;
5246
5247 switch (audit_type) {
5248 case IDC_AUDIT_TIMESTAMP:
5249 ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000);
5250 idc_audit_reg = (ha->portnum) |
5251 (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8);
5252 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
5253 break;
5254
5255 case IDC_AUDIT_COMPLETION:
5256 duration_secs = ((jiffies_to_msecs(jiffies) -
5257 jiffies_to_msecs(ha->idc_audit_ts)) / 1000);
5258 idc_audit_reg = (ha->portnum) |
5259 (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8);
5260 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
5261 break;
5262
5263 default:
5264 ql_log(ql_log_warn, vha, 0xb078,
5265 "Invalid audit type specified.\n");
5266 break;
5267 }
5268}
5269
5270/* Assumes idc_lock always held on entry */
fa492630 5271static int
7d613ac6
SV		 5272qla83xx_initiating_reset(scsi_qla_host_t *vha)
5273{
5274 struct qla_hw_data *ha = vha->hw;
5275 uint32_t idc_control, dev_state;
5276
5277 __qla83xx_get_idc_control(vha, &idc_control);
5278 if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) {
5279 ql_log(ql_log_info, vha, 0xb080,
5280 "NIC Core reset has been disabled. idc-control=0x%x\n",
5281 idc_control);
5282 return QLA_FUNCTION_FAILED;
5283 }
5284
5285 /* Set NEED-RESET iff in READY state and we are the reset-owner */
5286 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5287 if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) {
5288 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
5289 QLA8XXX_DEV_NEED_RESET);
5290 ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n");
5291 qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP);
5292 } else {
5293 const char *state = qla83xx_dev_state_to_string(dev_state);
5294 ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n", state);
5295
5296 /* SV: XXX: Is timeout required here? */
5297 /* Wait for IDC state change READY -> NEED_RESET */
5298 while (dev_state == QLA8XXX_DEV_READY) {
5299 qla83xx_idc_unlock(vha, 0);
5300 msleep(200);
5301 qla83xx_idc_lock(vha, 0);
5302 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5303 }
5304 }
5305
5306 /* Send IDC ack by writing to drv-ack register */
5307 __qla83xx_set_drv_ack(vha);
5308
5309 return QLA_SUCCESS;
5310}
5311
5312int
5313__qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control)
5314{
5315 return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
5316}
5317
7d613ac6
SV		 5318int
5319__qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control)
5320{
5321 return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
5322}
5323
fa492630 5324static int
7d613ac6
SV		 5325qla83xx_check_driver_presence(scsi_qla_host_t *vha)
5326{
5327 uint32_t drv_presence = 0;
5328 struct qla_hw_data *ha = vha->hw;
5329
5330 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5331 if (drv_presence & (1 << ha->portnum))
5332 return QLA_SUCCESS;
5333 else
5334 return QLA_TEST_FAILED;
5335}
5336
5337int
5338qla83xx_nic_core_reset(scsi_qla_host_t *vha)
5339{
5340 int rval = QLA_SUCCESS;
5341 struct qla_hw_data *ha = vha->hw;
5342
5343 ql_dbg(ql_dbg_p3p, vha, 0xb058,
5344 "Entered %s().\n", __func__);
5345
5346 if (vha->device_flags & DFLG_DEV_FAILED) {
5347 ql_log(ql_log_warn, vha, 0xb059,
5348 "Device in unrecoverable FAILED state.\n");
5349 return QLA_FUNCTION_FAILED;
5350 }
5351
5352 qla83xx_idc_lock(vha, 0);
5353
5354 if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) {
5355 ql_log(ql_log_warn, vha, 0xb05a,
5356 "Function=0x%x has been removed from IDC participation.\n",
5357 ha->portnum);
5358 rval = QLA_FUNCTION_FAILED;
5359 goto exit;
5360 }
5361
5362 qla83xx_reset_ownership(vha);
5363
5364 rval = qla83xx_initiating_reset(vha);
5365
5366 /*
5367 * Perform reset if we are the reset-owner,
5368 * else wait till IDC state changes to READY/FAILED.
5369 */
5370 if (rval == QLA_SUCCESS) {
5371 rval = qla83xx_idc_state_handler(vha);
5372
5373 if (rval == QLA_SUCCESS)
5374 ha->flags.nic_core_hung = 0;
5375 __qla83xx_clear_drv_ack(vha);
5376 }
5377
5378exit:
5379 qla83xx_idc_unlock(vha, 0);
5380
5381 ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__);
5382
5383 return rval;
5384}
5385
81178772
SK		 5386int
5387qla2xxx_mctp_dump(scsi_qla_host_t *vha)
5388{
5389 struct qla_hw_data *ha = vha->hw;
5390 int rval = QLA_FUNCTION_FAILED;
5391
5392 if (!IS_MCTP_CAPABLE(ha)) {
5393 /* This message can be removed from the final version */
5394 ql_log(ql_log_info, vha, 0x506d,
5395 "This board is not MCTP capable\n");
5396 return rval;
5397 }
5398
5399 if (!ha->mctp_dump) {
5400 ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev,
5401 MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL);
5402
5403 if (!ha->mctp_dump) {
5404 ql_log(ql_log_warn, vha, 0x506e,
5405 "Failed to allocate memory for mctp dump\n");
5406 return rval;
5407 }
5408 }
5409
5410#define MCTP_DUMP_STR_ADDR 0x00000000
5411 rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma,
5412 MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4);
5413 if (rval != QLA_SUCCESS) {
5414 ql_log(ql_log_warn, vha, 0x506f,
5415 "Failed to capture mctp dump\n");
5416 } else {
5417 ql_log(ql_log_info, vha, 0x5070,
5418 "Mctp dump capture for host (%ld/%p).\n",
5419 vha->host_no, ha->mctp_dump);
5420 ha->mctp_dumped = 1;
5421 }
5422
409ee0fe 5423 if (!ha->flags.nic_core_reset_hdlr_active && !ha->portnum) {
81178772
SK		 5424 ha->flags.nic_core_reset_hdlr_active = 1;
5425 rval = qla83xx_restart_nic_firmware(vha);
5426 if (rval)
5427 /* NIC Core reset failed. */
5428 ql_log(ql_log_warn, vha, 0x5071,
5429 "Failed to restart nic firmware\n");
5430 else
5431 ql_dbg(ql_dbg_p3p, vha, 0xb084,
5432 "Restarted NIC firmware successfully.\n");
5433 ha->flags.nic_core_reset_hdlr_active = 0;
5434 }
5435
5436 return rval;
5437
5438}
5439
579d12b5 5440/*
8fcd6b8b 5441* qla2x00_quiesce_io
579d12b5
SK		 5442* Description: This function will block the new I/Os
5443* Its not aborting any I/Os as context
5444* is not destroyed during quiescence
5445* Arguments: scsi_qla_host_t
5446* return : void
5447*/
5448void
8fcd6b8b 5449qla2x00_quiesce_io(scsi_qla_host_t *vha)
579d12b5
SK		 5450{
5451 struct qla_hw_data *ha = vha->hw;
5452 struct scsi_qla_host *vp;
5453
8fcd6b8b
CD		 5454 ql_dbg(ql_dbg_dpc, vha, 0x401d,
5455 "Quiescing I/O - ha=%p.\n", ha);
579d12b5
SK		 5456
5457 atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME);
5458 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
5459 atomic_set(&vha->loop_state, LOOP_DOWN);
5460 qla2x00_mark_all_devices_lost(vha, 0);
5461 list_for_each_entry(vp, &ha->vp_list, list)
8fcd6b8b 5462 qla2x00_mark_all_devices_lost(vp, 0);
579d12b5
SK		 5463 } else {
5464 if (!atomic_read(&vha->loop_down_timer))
5465 atomic_set(&vha->loop_down_timer,
5466 LOOP_DOWN_TIME);
5467 }
5468 /* Wait for pending cmds to complete */
5469 qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST);
5470}
5471
a9083016
GM		 5472void
5473qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
5474{
5475 struct qla_hw_data *ha = vha->hw;
579d12b5 5476 struct scsi_qla_host *vp;
feafb7b1 5477 unsigned long flags;
6aef87be 5478 fc_port_t *fcport;
a9083016 5479
e46ef004
SK		 5480 /* For ISP82XX, driver waits for completion of the commands.
5481 * online flag should be set.
5482 */
7ec0effd 5483 if (!(IS_P3P_TYPE(ha)))
e46ef004 5484 vha->flags.online = 0;
a9083016
GM		 5485 ha->flags.chip_reset_done = 0;
5486 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2be21fa2 5487 vha->qla_stats.total_isp_aborts++;
a9083016 5488
7c3df132
SK		 5489 ql_log(ql_log_info, vha, 0x00af,
5490 "Performing ISP error recovery - ha=%p.\n", ha);
a9083016 5491
e46ef004
SK		 5492 /* For ISP82XX, reset_chip is just disabling interrupts.
5493 * Driver waits for the completion of the commands.
5494 * the interrupts need to be enabled.
5495 */
7ec0effd 5496 if (!(IS_P3P_TYPE(ha)))
a9083016
GM		 5497 ha->isp_ops->reset_chip(vha);
5498
ec7193e2
QT		 5499 ha->flags.n2n_ae = 0;
5500 ha->flags.lip_ae = 0;
5501 ha->current_topology = 0;
5502 ha->flags.fw_started = 0;
5503 ha->flags.fw_init_done = 0;
726b8548
QT		 5504 ha->chip_reset++;
5505
a9083016
GM		 5506 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
5507 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
5508 atomic_set(&vha->loop_state, LOOP_DOWN);
5509 qla2x00_mark_all_devices_lost(vha, 0);
feafb7b1
AE		 5510
5511 spin_lock_irqsave(&ha->vport_slock, flags);
579d12b5 5512 list_for_each_entry(vp, &ha->vp_list, list) {
feafb7b1
AE		 5513 atomic_inc(&vp->vref_count);
5514 spin_unlock_irqrestore(&ha->vport_slock, flags);
5515
a9083016 5516 qla2x00_mark_all_devices_lost(vp, 0);
feafb7b1
AE		 5517
5518 spin_lock_irqsave(&ha->vport_slock, flags);
5519 atomic_dec(&vp->vref_count);
5520 }
5521 spin_unlock_irqrestore(&ha->vport_slock, flags);
a9083016
GM		 5522 } else {
5523 if (!atomic_read(&vha->loop_down_timer))
5524 atomic_set(&vha->loop_down_timer,
5525 LOOP_DOWN_TIME);
5526 }
5527
6aef87be
AV		 5528 /* Clear all async request states across all VPs. */
5529 list_for_each_entry(fcport, &vha->vp_fcports, list)
5530 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
5531 spin_lock_irqsave(&ha->vport_slock, flags);
5532 list_for_each_entry(vp, &ha->vp_list, list) {
5533 atomic_inc(&vp->vref_count);
5534 spin_unlock_irqrestore(&ha->vport_slock, flags);
5535
5536 list_for_each_entry(fcport, &vp->vp_fcports, list)
5537 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
5538
5539 spin_lock_irqsave(&ha->vport_slock, flags);
5540 atomic_dec(&vp->vref_count);
5541 }
5542 spin_unlock_irqrestore(&ha->vport_slock, flags);
5543
bddd2d65
LC		 5544 if (!ha->flags.eeh_busy) {
5545 /* Make sure for ISP 82XX IO DMA is complete */
7ec0effd 5546 if (IS_P3P_TYPE(ha)) {
7190575f 5547 qla82xx_chip_reset_cleanup(vha);
7c3df132
SK		 5548 ql_log(ql_log_info, vha, 0x00b4,
5549 "Done chip reset cleanup.\n");
a9083016 5550
e46ef004
SK		 5551 /* Done waiting for pending commands.
5552 * Reset the online flag.
5553 */
5554 vha->flags.online = 0;
4d78c973 5555 }
a9083016 5556
bddd2d65
LC		 5557 /* Requeue all commands in outstanding command list. */
5558 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
5559 }
b6a029e1
AE		 5560 /* memory barrier */
5561 wmb();
a9083016
GM		 5562}
5563
1da177e4
LT		 5564/*
5565* qla2x00_abort_isp
5566* Resets ISP and aborts all outstanding commands.
5567*
5568* Input:
5569* ha = adapter block pointer.
5570*
5571* Returns:
5572* 0 = success
5573*/
5574int
e315cd28 5575qla2x00_abort_isp(scsi_qla_host_t *vha)
1da177e4 5576{
476e8978 5577 int rval;
1da177e4 5578 uint8_t status = 0;
e315cd28
AC		 5579 struct qla_hw_data *ha = vha->hw;
5580 struct scsi_qla_host *vp;
73208dfd 5581 struct req_que *req = ha->req_q_map[0];
feafb7b1 5582 unsigned long flags;
1da177e4 5583
e315cd28 5584 if (vha->flags.online) {
a9083016 5585 qla2x00_abort_isp_cleanup(vha);
1da177e4 5586
a6171297
SV		 5587 if (IS_QLA8031(ha)) {
5588 ql_dbg(ql_dbg_p3p, vha, 0xb05c,
5589 "Clearing fcoe driver presence.\n");
5590 if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS)
5591 ql_dbg(ql_dbg_p3p, vha, 0xb073,
5592 "Error while clearing DRV-Presence.\n");
5593 }
5594
85880801
AV		 5595 if (unlikely(pci_channel_offline(ha->pdev) &&
5596 ha->flags.pci_channel_io_perm_failure)) {
5597 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
5598 status = 0;
5599 return status;
5600 }
5601
73208dfd 5602 ha->isp_ops->get_flash_version(vha, req->ring);
30c47662 5603
e315cd28 5604 ha->isp_ops->nvram_config(vha);
1da177e4 5605
e315cd28
AC		 5606 if (!qla2x00_restart_isp(vha)) {
5607 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4 5608
e315cd28 5609 if (!atomic_read(&vha->loop_down_timer)) {
1da177e4
LT		 5610 /*
5611 * Issue marker command only when we are going
5612 * to start the I/O .
5613 */
e315cd28 5614 vha->marker_needed = 1;
1da177e4
LT		 5615 }
5616
e315cd28 5617 vha->flags.online = 1;
1da177e4 5618
fd34f556 5619 ha->isp_ops->enable_intrs(ha);
1da177e4 5620
fa2a1ce5 5621 ha->isp_abort_cnt = 0;
e315cd28 5622 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
476e8978 5623
6246b8a1
GM		 5624 if (IS_QLA81XX(ha) || IS_QLA8031(ha))
5625 qla2x00_get_fw_version(vha);
df613b96
AV		 5626 if (ha->fce) {
5627 ha->flags.fce_enabled = 1;
5628 memset(ha->fce, 0,
5629 fce_calc_size(ha->fce_bufs));
e315cd28 5630 rval = qla2x00_enable_fce_trace(vha,
df613b96
AV		 5631 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
5632 &ha->fce_bufs);
5633 if (rval) {
7c3df132 5634 ql_log(ql_log_warn, vha, 0x8033,
df613b96
AV		 5635 "Unable to reinitialize FCE "
5636 "(%d).\n", rval);
5637 ha->flags.fce_enabled = 0;
5638 }
5639 }
436a7b11
AV		 5640
5641 if (ha->eft) {
5642 memset(ha->eft, 0, EFT_SIZE);
e315cd28 5643 rval = qla2x00_enable_eft_trace(vha,
436a7b11
AV		 5644 ha->eft_dma, EFT_NUM_BUFFERS);
5645 if (rval) {
7c3df132 5646 ql_log(ql_log_warn, vha, 0x8034,
436a7b11
AV		 5647 "Unable to reinitialize EFT "
5648 "(%d).\n", rval);
5649 }
5650 }
1da177e4 5651 } else { /* failed the ISP abort */
e315cd28
AC		 5652 vha->flags.online = 1;
5653 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
1da177e4 5654 if (ha->isp_abort_cnt == 0) {
7c3df132
SK		 5655 ql_log(ql_log_fatal, vha, 0x8035,
5656 "ISP error recover failed - "
5657 "board disabled.\n");
fa2a1ce5 5658 /*
1da177e4
LT		 5659 * The next call disables the board
5660 * completely.
5661 */
e315cd28
AC		 5662 ha->isp_ops->reset_adapter(vha);
5663 vha->flags.online = 0;
1da177e4 5664 clear_bit(ISP_ABORT_RETRY,
e315cd28 5665 &vha->dpc_flags);
1da177e4
LT		 5666 status = 0;
5667 } else { /* schedule another ISP abort */
5668 ha->isp_abort_cnt--;
7c3df132
SK		 5669 ql_dbg(ql_dbg_taskm, vha, 0x8020,
5670 "ISP abort - retry remaining %d.\n",
5671 ha->isp_abort_cnt);
1da177e4
LT		 5672 status = 1;
5673 }
5674 } else {
5675 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
7c3df132
SK		 5676 ql_dbg(ql_dbg_taskm, vha, 0x8021,
5677 "ISP error recovery - retrying (%d) "
5678 "more times.\n", ha->isp_abort_cnt);
e315cd28 5679 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
1da177e4
LT		 5680 status = 1;
5681 }
5682 }
fa2a1ce5 5683
1da177e4
LT		 5684 }
5685
e315cd28 5686 if (!status) {
7c3df132 5687 ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__);
feafb7b1
AE		 5688
5689 spin_lock_irqsave(&ha->vport_slock, flags);
5690 list_for_each_entry(vp, &ha->vp_list, list) {
5691 if (vp->vp_idx) {
5692 atomic_inc(&vp->vref_count);
5693 spin_unlock_irqrestore(&ha->vport_slock, flags);
5694
e315cd28 5695 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 5696
5697 spin_lock_irqsave(&ha->vport_slock, flags);
5698 atomic_dec(&vp->vref_count);
5699 }
e315cd28 5700 }
feafb7b1
AE		 5701 spin_unlock_irqrestore(&ha->vport_slock, flags);
5702
7d613ac6
SV		 5703 if (IS_QLA8031(ha)) {
5704 ql_dbg(ql_dbg_p3p, vha, 0xb05d,
5705 "Setting back fcoe driver presence.\n");
5706 if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS)
5707 ql_dbg(ql_dbg_p3p, vha, 0xb074,
5708 "Error while setting DRV-Presence.\n");
5709 }
e315cd28 5710 } else {
d8424f68
JP		 5711 ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n",
5712 __func__);
1da177e4
LT		 5713 }
5714
5715 return(status);
5716}
5717
5718/*
5719* qla2x00_restart_isp
5720* restarts the ISP after a reset
5721*
5722* Input:
5723* ha = adapter block pointer.
5724*
5725* Returns:
5726* 0 = success
5727*/
5728static int
e315cd28 5729qla2x00_restart_isp(scsi_qla_host_t *vha)
1da177e4 5730{
c6b2fca8 5731 int status = 0;
e315cd28 5732 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 5733 struct req_que *req = ha->req_q_map[0];
5734 struct rsp_que *rsp = ha->rsp_q_map[0];
1da177e4
LT		 5735
5736 /* If firmware needs to be loaded */
e315cd28
AC		 5737 if (qla2x00_isp_firmware(vha)) {
5738 vha->flags.online = 0;
5739 status = ha->isp_ops->chip_diag(vha);
5740 if (!status)
5741 status = qla2x00_setup_chip(vha);
1da177e4
LT		 5742 }
5743
e315cd28
AC		 5744 if (!status && !(status = qla2x00_init_rings(vha))) {
5745 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
2533cf67 5746 ha->flags.chip_reset_done = 1;
7108b76e 5747
73208dfd
AC		 5748 /* Initialize the queues in use */
5749 qla25xx_init_queues(ha);
5750
e315cd28
AC		 5751 status = qla2x00_fw_ready(vha);
5752 if (!status) {
0107109e 5753 /* Issue a marker after FW becomes ready. */
73208dfd 5754 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
7108b76e 5755 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4
LT		 5756 }
5757
5758 /* if no cable then assume it's good */
e315cd28 5759 if ((vha->device_flags & DFLG_NO_CABLE))
1da177e4 5760 status = 0;
1da177e4
LT		 5761 }
5762 return (status);
5763}
5764
73208dfd
AC		 5765static int
5766qla25xx_init_queues(struct qla_hw_data *ha)
5767{
5768 struct rsp_que *rsp = NULL;
5769 struct req_que *req = NULL;
5770 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
5771 int ret = -1;
5772 int i;
5773
2afa19a9 5774 for (i = 1; i < ha->max_rsp_queues; i++) {
73208dfd 5775 rsp = ha->rsp_q_map[i];
cb43285f 5776 if (rsp && test_bit(i, ha->rsp_qid_map)) {
73208dfd 5777 rsp->options &= ~BIT_0;
618a7523 5778 ret = qla25xx_init_rsp_que(base_vha, rsp);
73208dfd 5779 if (ret != QLA_SUCCESS)
7c3df132
SK		 5780 ql_dbg(ql_dbg_init, base_vha, 0x00ff,
5781 "%s Rsp que: %d init failed.\n",
5782 __func__, rsp->id);
73208dfd 5783 else
7c3df132
SK		 5784 ql_dbg(ql_dbg_init, base_vha, 0x0100,
5785 "%s Rsp que: %d inited.\n",
5786 __func__, rsp->id);
73208dfd 5787 }
2afa19a9
AC		 5788 }
5789 for (i = 1; i < ha->max_req_queues; i++) {
73208dfd 5790 req = ha->req_q_map[i];
cb43285f
QT		 5791 if (req && test_bit(i, ha->req_qid_map)) {
5792 /* Clear outstanding commands array. */
73208dfd 5793 req->options &= ~BIT_0;
618a7523 5794 ret = qla25xx_init_req_que(base_vha, req);
73208dfd 5795 if (ret != QLA_SUCCESS)
7c3df132
SK		 5796 ql_dbg(ql_dbg_init, base_vha, 0x0101,
5797 "%s Req que: %d init failed.\n",
5798 __func__, req->id);
73208dfd 5799 else
7c3df132
SK		 5800 ql_dbg(ql_dbg_init, base_vha, 0x0102,
5801 "%s Req que: %d inited.\n",
5802 __func__, req->id);
73208dfd
AC		 5803 }
5804 }
5805 return ret;
5806}
5807
1da177e4
LT		 5808/*
5809* qla2x00_reset_adapter
5810* Reset adapter.
5811*
5812* Input:
5813* ha = adapter block pointer.
5814*/
abbd8870 5815void
e315cd28 5816qla2x00_reset_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 5817{
5818 unsigned long flags = 0;
e315cd28 5819 struct qla_hw_data *ha = vha->hw;
3d71644c 5820 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 5821
e315cd28 5822 vha->flags.online = 0;
fd34f556 5823 ha->isp_ops->disable_intrs(ha);
1da177e4 5824
1da177e4
LT		 5825 spin_lock_irqsave(&ha->hardware_lock, flags);
5826 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
5827 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
5828 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
5829 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
5830 spin_unlock_irqrestore(&ha->hardware_lock, flags);
5831}
0107109e
AV		 5832
5833void
e315cd28 5834qla24xx_reset_adapter(scsi_qla_host_t *vha)
0107109e
AV		 5835{
5836 unsigned long flags = 0;
e315cd28 5837 struct qla_hw_data *ha = vha->hw;
0107109e
AV		 5838 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
5839
7ec0effd 5840 if (IS_P3P_TYPE(ha))
a9083016
GM		 5841 return;
5842
e315cd28 5843 vha->flags.online = 0;
fd34f556 5844 ha->isp_ops->disable_intrs(ha);
0107109e
AV		 5845
5846 spin_lock_irqsave(&ha->hardware_lock, flags);
5847 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
5848 RD_REG_DWORD(&reg->hccr);
5849 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
5850 RD_REG_DWORD(&reg->hccr);
5851 spin_unlock_irqrestore(&ha->hardware_lock, flags);
09ff36d3
AV		 5852
5853 if (IS_NOPOLLING_TYPE(ha))
5854 ha->isp_ops->enable_intrs(ha);
0107109e
AV		 5855}
5856
4e08df3f
DM		 5857/* On sparc systems, obtain port and node WWN from firmware
5858 * properties.
5859 */
e315cd28
AC		 5860static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha,
5861 struct nvram_24xx *nv)
4e08df3f
DM		 5862{
5863#ifdef CONFIG_SPARC
e315cd28 5864 struct qla_hw_data *ha = vha->hw;
4e08df3f 5865 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 5866 struct device_node *dp = pci_device_to_OF_node(pdev);
5867 const u8 *val;
4e08df3f
DM		 5868 int len;
5869
5870 val = of_get_property(dp, "port-wwn", &len);
5871 if (val && len >= WWN_SIZE)
5872 memcpy(nv->port_name, val, WWN_SIZE);
5873
5874 val = of_get_property(dp, "node-wwn", &len);
5875 if (val && len >= WWN_SIZE)
5876 memcpy(nv->node_name, val, WWN_SIZE);
5877#endif
5878}
5879
0107109e 5880int
e315cd28 5881qla24xx_nvram_config(scsi_qla_host_t *vha)
0107109e 5882{
4e08df3f 5883 int rval;
0107109e
AV		 5884 struct init_cb_24xx *icb;
5885 struct nvram_24xx *nv;
5886 uint32_t *dptr;
5887 uint8_t *dptr1, *dptr2;
5888 uint32_t chksum;
5889 uint16_t cnt;
e315cd28 5890 struct qla_hw_data *ha = vha->hw;
0107109e 5891
4e08df3f 5892 rval = QLA_SUCCESS;
0107109e 5893 icb = (struct init_cb_24xx *)ha->init_cb;
281afe19 5894 nv = ha->nvram;
0107109e
AV		 5895
5896 /* Determine NVRAM starting address. */
f73cb695 5897 if (ha->port_no == 0) {
e5b68a61
AC		 5898 ha->nvram_base = FA_NVRAM_FUNC0_ADDR;
5899 ha->vpd_base = FA_NVRAM_VPD0_ADDR;
5900 } else {
0107109e 5901 ha->nvram_base = FA_NVRAM_FUNC1_ADDR;
6f641790
AV		 5902 ha->vpd_base = FA_NVRAM_VPD1_ADDR;
5903 }
f73cb695 5904
e5b68a61
AC		 5905 ha->nvram_size = sizeof(struct nvram_24xx);
5906 ha->vpd_size = FA_NVRAM_VPD_SIZE;
0107109e 5907
281afe19
SJ		 5908 /* Get VPD data into cache */
5909 ha->vpd = ha->nvram + VPD_OFFSET;
e315cd28 5910 ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd,
281afe19
SJ		 5911 ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
5912
5913 /* Get NVRAM data into cache and calculate checksum. */
0107109e 5914 dptr = (uint32_t *)nv;
e315cd28 5915 ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base,
0107109e 5916 ha->nvram_size);
da08ef5c
JC		 5917 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++)
5918 chksum += le32_to_cpu(*dptr);
0107109e 5919
7c3df132
SK		 5920 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
5921 "Contents of NVRAM\n");
5922 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
5923 (uint8_t *)nv, ha->nvram_size);
0107109e
AV		 5924
5925 /* Bad NVRAM data, set defaults parameters. */
5926 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
5927 || nv->id[3] != ' ' ||
ad950360 5928 nv->nvram_version < cpu_to_le16(ICB_VERSION)) {
0107109e 5929 /* Reset NVRAM data. */
7c3df132 5930 ql_log(ql_log_warn, vha, 0x006b,
9e336520 5931 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132
SK		 5932 "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version);
5933 ql_log(ql_log_warn, vha, 0x006c,
5934 "Falling back to functioning (yet invalid -- WWPN) "
5935 "defaults.\n");
4e08df3f
DM		 5936
5937 /*
5938 * Set default initialization control block.
5939 */
5940 memset(nv, 0, ha->nvram_size);
ad950360
BVA		 5941 nv->nvram_version = cpu_to_le16(ICB_VERSION);
5942 nv->version = cpu_to_le16(ICB_VERSION);
98aee70d 5943 nv->frame_payload_size = 2048;
ad950360
BVA		 5944 nv->execution_throttle = cpu_to_le16(0xFFFF);
5945 nv->exchange_count = cpu_to_le16(0);
5946 nv->hard_address = cpu_to_le16(124);
4e08df3f 5947 nv->port_name[0] = 0x21;
f73cb695 5948 nv->port_name[1] = 0x00 + ha->port_no + 1;
4e08df3f
DM		 5949 nv->port_name[2] = 0x00;
5950 nv->port_name[3] = 0xe0;
5951 nv->port_name[4] = 0x8b;
5952 nv->port_name[5] = 0x1c;
5953 nv->port_name[6] = 0x55;
5954 nv->port_name[7] = 0x86;
5955 nv->node_name[0] = 0x20;
5956 nv->node_name[1] = 0x00;
5957 nv->node_name[2] = 0x00;
5958 nv->node_name[3] = 0xe0;
5959 nv->node_name[4] = 0x8b;
5960 nv->node_name[5] = 0x1c;
5961 nv->node_name[6] = 0x55;
5962 nv->node_name[7] = 0x86;
e315cd28 5963 qla24xx_nvram_wwn_from_ofw(vha, nv);
ad950360
BVA		 5964 nv->login_retry_count = cpu_to_le16(8);
5965 nv->interrupt_delay_timer = cpu_to_le16(0);
5966 nv->login_timeout = cpu_to_le16(0);
4e08df3f 5967 nv->firmware_options_1 =
ad950360
BVA		 5968 cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
5969 nv->firmware_options_2 = cpu_to_le32(2 << 4);
5970 nv->firmware_options_2 |= cpu_to_le32(BIT_12);
5971 nv->firmware_options_3 = cpu_to_le32(2 << 13);
5972 nv->host_p = cpu_to_le32(BIT_11|BIT_10);
5973 nv->efi_parameters = cpu_to_le32(0);
4e08df3f 5974 nv->reset_delay = 5;
ad950360
BVA		 5975 nv->max_luns_per_target = cpu_to_le16(128);
5976 nv->port_down_retry_count = cpu_to_le16(30);
5977 nv->link_down_timeout = cpu_to_le16(30);
4e08df3f
DM		 5978
5979 rval = 1;
0107109e
AV		 5980 }
5981
726b8548 5982 if (qla_tgt_mode_enabled(vha)) {
2d70c103 5983 /* Don't enable full login after initial LIP */
ad950360 5984 nv->firmware_options_1 &= cpu_to_le32(~BIT_13);
2d70c103 5985 /* Don't enable LIP full login for initiator */
ad950360 5986 nv->host_p &= cpu_to_le32(~BIT_10);
2d70c103
NB		 5987 }
5988
5989 qlt_24xx_config_nvram_stage1(vha, nv);
5990
0107109e 5991 /* Reset Initialization control block */
e315cd28 5992 memset(icb, 0, ha->init_cb_size);
0107109e
AV		 5993
5994 /* Copy 1st segment. */
5995 dptr1 = (uint8_t *)icb;
5996 dptr2 = (uint8_t *)&nv->version;
5997 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
5998 while (cnt--)
5999 *dptr1++ = *dptr2++;
6000
6001 icb->login_retry_count = nv->login_retry_count;
3ea66e28 6002 icb->link_down_on_nos = nv->link_down_on_nos;
0107109e
AV		 6003
6004 /* Copy 2nd segment. */
6005 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
6006 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
6007 cnt = (uint8_t *)&icb->reserved_3 -
6008 (uint8_t *)&icb->interrupt_delay_timer;
6009 while (cnt--)
6010 *dptr1++ = *dptr2++;
6011
6012 /*
6013 * Setup driver NVRAM options.
6014 */
e315cd28 6015 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
9bb9fcf2 6016 "QLA2462");
0107109e 6017
2d70c103
NB		 6018 qlt_24xx_config_nvram_stage2(vha, icb);
6019
ad950360 6020 if (nv->host_p & cpu_to_le32(BIT_15)) {
2d70c103 6021 /* Use alternate WWN? */
5341e868
AV		 6022 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
6023 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
6024 }
6025
0107109e 6026 /* Prepare nodename */
ad950360 6027 if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) {
0107109e
AV		 6028 /*
6029 * Firmware will apply the following mask if the nodename was
6030 * not provided.
6031 */
6032 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
6033 icb->node_name[0] &= 0xF0;
6034 }
6035
6036 /* Set host adapter parameters. */
6037 ha->flags.disable_risc_code_load = 0;
0c8c39af
AV		 6038 ha->flags.enable_lip_reset = 0;
6039 ha->flags.enable_lip_full_login =
6040 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
6041 ha->flags.enable_target_reset =
6042 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
0107109e 6043 ha->flags.enable_led_scheme = 0;
d4c760c2 6044 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
0107109e 6045
fd0e7e4d
AV		 6046 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
6047 (BIT_6 | BIT_5 | BIT_4)) >> 4;
0107109e
AV		 6048
6049 memcpy(ha->fw_seriallink_options24, nv->seriallink_options,
6050 sizeof(ha->fw_seriallink_options24));
6051
6052 /* save HBA serial number */
6053 ha->serial0 = icb->port_name[5];
6054 ha->serial1 = icb->port_name[6];
6055 ha->serial2 = icb->port_name[7];
e315cd28
AC		 6056 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
6057 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
0107109e 6058
ad950360 6059 icb->execution_throttle = cpu_to_le16(0xFFFF);
bc8fb3cb 6060
0107109e
AV		 6061 ha->retry_count = le16_to_cpu(nv->login_retry_count);
6062
6063 /* Set minimum login_timeout to 4 seconds. */
6064 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
6065 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
6066 if (le16_to_cpu(nv->login_timeout) < 4)
ad950360 6067 nv->login_timeout = cpu_to_le16(4);
0107109e 6068 ha->login_timeout = le16_to_cpu(nv->login_timeout);
0107109e 6069
00a537b8
AV		 6070 /* Set minimum RATOV to 100 tenths of a second. */
6071 ha->r_a_tov = 100;
0107109e
AV		 6072
6073 ha->loop_reset_delay = nv->reset_delay;
6074
6075 /* Link Down Timeout = 0:
6076 *
6077 * When Port Down timer expires we will start returning
6078 * I/O's to OS with "DID_NO_CONNECT".
6079 *
6080 * Link Down Timeout != 0:
6081 *
6082 * The driver waits for the link to come up after link down
6083 * before returning I/Os to OS with "DID_NO_CONNECT".
6084 */
6085 if (le16_to_cpu(nv->link_down_timeout) == 0) {
6086 ha->loop_down_abort_time =
6087 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
6088 } else {
6089 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
6090 ha->loop_down_abort_time =
6091 (LOOP_DOWN_TIME - ha->link_down_timeout);
6092 }
6093
6094 /* Need enough time to try and get the port back. */
6095 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
6096 if (qlport_down_retry)
6097 ha->port_down_retry_count = qlport_down_retry;
6098
6099 /* Set login_retry_count */
6100 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
6101 if (ha->port_down_retry_count ==
6102 le16_to_cpu(nv->port_down_retry_count) &&
6103 ha->port_down_retry_count > 3)
6104 ha->login_retry_count = ha->port_down_retry_count;
6105 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
6106 ha->login_retry_count = ha->port_down_retry_count;
6107 if (ql2xloginretrycount)
6108 ha->login_retry_count = ql2xloginretrycount;
6109
4fdfefe5 6110 /* Enable ZIO. */
e315cd28 6111 if (!vha->flags.init_done) {
4fdfefe5
AV		 6112 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
6113 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
6114 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
6115 le16_to_cpu(icb->interrupt_delay_timer): 2;
6116 }
ad950360 6117 icb->firmware_options_2 &= cpu_to_le32(
4fdfefe5 6118 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
e315cd28 6119 vha->flags.process_response_queue = 0;
4fdfefe5 6120 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d
AV		 6121 ha->zio_mode = QLA_ZIO_MODE_6;
6122
7c3df132 6123 ql_log(ql_log_info, vha, 0x006f,
4fdfefe5
AV		 6124 "ZIO mode %d enabled; timer delay (%d us).\n",
6125 ha->zio_mode, ha->zio_timer * 100);
6126
6127 icb->firmware_options_2 |= cpu_to_le32(
6128 (uint32_t)ha->zio_mode);
6129 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
e315cd28 6130 vha->flags.process_response_queue = 1;
4fdfefe5
AV		 6131 }
6132
4e08df3f 6133 if (rval) {
7c3df132
SK		 6134 ql_log(ql_log_warn, vha, 0x0070,
6135 "NVRAM configuration failed.\n");
4e08df3f
DM		 6136 }
6137 return (rval);
0107109e
AV		 6138}
6139
4243c115
SC		 6140uint8_t qla27xx_find_valid_image(struct scsi_qla_host *vha)
6141{
6142 struct qla27xx_image_status pri_image_status, sec_image_status;
6143 uint8_t valid_pri_image, valid_sec_image;
6144 uint32_t *wptr;
6145 uint32_t cnt, chksum, size;
6146 struct qla_hw_data *ha = vha->hw;
6147
6148 valid_pri_image = valid_sec_image = 1;
6149 ha->active_image = 0;
6150 size = sizeof(struct qla27xx_image_status) / sizeof(uint32_t);
6151
6152 if (!ha->flt_region_img_status_pri) {
6153 valid_pri_image = 0;
6154 goto check_sec_image;
6155 }
6156
6157 qla24xx_read_flash_data(vha, (uint32_t *)(&pri_image_status),
6158 ha->flt_region_img_status_pri, size);
6159
6160 if (pri_image_status.signature != QLA27XX_IMG_STATUS_SIGN) {
6161 ql_dbg(ql_dbg_init, vha, 0x018b,
6162 "Primary image signature (0x%x) not valid\n",
6163 pri_image_status.signature);
6164 valid_pri_image = 0;
6165 goto check_sec_image;
6166 }
6167
6168 wptr = (uint32_t *)(&pri_image_status);
6169 cnt = size;
6170
da08ef5c
JC		 6171 for (chksum = 0; cnt--; wptr++)
6172 chksum += le32_to_cpu(*wptr);
41dc529a 6173
4243c115
SC		 6174 if (chksum) {
6175 ql_dbg(ql_dbg_init, vha, 0x018c,
6176 "Checksum validation failed for primary image (0x%x)\n",
6177 chksum);
6178 valid_pri_image = 0;
6179 }
6180
6181check_sec_image:
6182 if (!ha->flt_region_img_status_sec) {
6183 valid_sec_image = 0;
6184 goto check_valid_image;
6185 }
6186
6187 qla24xx_read_flash_data(vha, (uint32_t *)(&sec_image_status),
6188 ha->flt_region_img_status_sec, size);
6189
6190 if (sec_image_status.signature != QLA27XX_IMG_STATUS_SIGN) {
6191 ql_dbg(ql_dbg_init, vha, 0x018d,
6192 "Secondary image signature(0x%x) not valid\n",
6193 sec_image_status.signature);
6194 valid_sec_image = 0;
6195 goto check_valid_image;
6196 }
6197
6198 wptr = (uint32_t *)(&sec_image_status);
6199 cnt = size;
da08ef5c
JC		 6200 for (chksum = 0; cnt--; wptr++)
6201 chksum += le32_to_cpu(*wptr);
4243c115
SC		 6202 if (chksum) {
6203 ql_dbg(ql_dbg_init, vha, 0x018e,
6204 "Checksum validation failed for secondary image (0x%x)\n",
6205 chksum);
6206 valid_sec_image = 0;
6207 }
6208
6209check_valid_image:
6210 if (valid_pri_image && (pri_image_status.image_status_mask & 0x1))
6211 ha->active_image = QLA27XX_PRIMARY_IMAGE;
6212 if (valid_sec_image && (sec_image_status.image_status_mask & 0x1)) {
6213 if (!ha->active_image ||
6214 pri_image_status.generation_number <
6215 sec_image_status.generation_number)
6216 ha->active_image = QLA27XX_SECONDARY_IMAGE;
6217 }
6218
6219 ql_dbg(ql_dbg_init, vha, 0x018f, "%s image\n",
6220 ha->active_image == 0 ? "default bootld and fw" :
6221 ha->active_image == 1 ? "primary" :
6222 ha->active_image == 2 ? "secondary" :
6223 "Invalid");
6224
6225 return ha->active_image;
6226}
6227
413975a0 6228static int
cbc8eb67
AV		 6229qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
6230 uint32_t faddr)
d1c61909 6231{
73208dfd 6232 int rval = QLA_SUCCESS;
d1c61909 6233 int segments, fragment;
d1c61909
AV		 6234 uint32_t *dcode, dlen;
6235 uint32_t risc_addr;
6236 uint32_t risc_size;
6237 uint32_t i;
e315cd28 6238 struct qla_hw_data *ha = vha->hw;
73208dfd 6239 struct req_que *req = ha->req_q_map[0];
eaac30be 6240
7c3df132 6241 ql_dbg(ql_dbg_init, vha, 0x008b,
cfb0919c 6242 "FW: Loading firmware from flash (%x).\n", faddr);
eaac30be 6243
d1c61909
AV		 6244 rval = QLA_SUCCESS;
6245
6246 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 6247 dcode = (uint32_t *)req->ring;
d1c61909
AV		 6248 *srisc_addr = 0;
6249
4243c115
SC		 6250 if (IS_QLA27XX(ha) &&
6251 qla27xx_find_valid_image(vha) == QLA27XX_SECONDARY_IMAGE)
6252 faddr = ha->flt_region_fw_sec;
6253
d1c61909 6254 /* Validate firmware image by checking version. */
e315cd28 6255 qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
d1c61909
AV		 6256 for (i = 0; i < 4; i++)
6257 dcode[i] = be32_to_cpu(dcode[i]);
6258 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
6259 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
6260 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
6261 dcode[3] == 0)) {
7c3df132
SK		 6262 ql_log(ql_log_fatal, vha, 0x008c,
6263 "Unable to verify the integrity of flash firmware "
6264 "image.\n");
6265 ql_log(ql_log_fatal, vha, 0x008d,
6266 "Firmware data: %08x %08x %08x %08x.\n",
6267 dcode[0], dcode[1], dcode[2], dcode[3]);
d1c61909
AV		 6268
6269 return QLA_FUNCTION_FAILED;
6270 }
6271
6272 while (segments && rval == QLA_SUCCESS) {
6273 /* Read segment's load information. */
e315cd28 6274 qla24xx_read_flash_data(vha, dcode, faddr, 4);
d1c61909
AV		 6275
6276 risc_addr = be32_to_cpu(dcode[2]);
6277 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
6278 risc_size = be32_to_cpu(dcode[3]);
6279
6280 fragment = 0;
6281 while (risc_size > 0 && rval == QLA_SUCCESS) {
6282 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
6283 if (dlen > risc_size)
6284 dlen = risc_size;
6285
7c3df132
SK		 6286 ql_dbg(ql_dbg_init, vha, 0x008e,
6287 "Loading risc segment@ risc addr %x "
6288 "number of dwords 0x%x offset 0x%x.\n",
6289 risc_addr, dlen, faddr);
d1c61909 6290
e315cd28 6291 qla24xx_read_flash_data(vha, dcode, faddr, dlen);
d1c61909
AV		 6292 for (i = 0; i < dlen; i++)
6293 dcode[i] = swab32(dcode[i]);
6294
73208dfd 6295 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
d1c61909
AV		 6296 dlen);
6297 if (rval) {
7c3df132
SK		 6298 ql_log(ql_log_fatal, vha, 0x008f,
6299 "Failed to load segment %d of firmware.\n",
6300 fragment);
f261f7af 6301 return QLA_FUNCTION_FAILED;
d1c61909
AV		 6302 }
6303
6304 faddr += dlen;
6305 risc_addr += dlen;
6306 risc_size -= dlen;
6307 fragment++;
6308 }
6309
6310 /* Next segment. */
6311 segments--;
6312 }
6313
f73cb695
CD		 6314 if (!IS_QLA27XX(ha))
6315 return rval;
6316
6317 if (ha->fw_dump_template)
6318 vfree(ha->fw_dump_template);
6319 ha->fw_dump_template = NULL;
6320 ha->fw_dump_template_len = 0;
6321
6322 ql_dbg(ql_dbg_init, vha, 0x0161,
6323 "Loading fwdump template from %x\n", faddr);
6324 qla24xx_read_flash_data(vha, dcode, faddr, 7);
6325 risc_size = be32_to_cpu(dcode[2]);
6326 ql_dbg(ql_dbg_init, vha, 0x0162,
6327 "-> array size %x dwords\n", risc_size);
6328 if (risc_size == 0 || risc_size == ~0)
6329 goto default_template;
6330
6331 dlen = (risc_size - 8) * sizeof(*dcode);
6332 ql_dbg(ql_dbg_init, vha, 0x0163,
6333 "-> template allocating %x bytes...\n", dlen);
6334 ha->fw_dump_template = vmalloc(dlen);
6335 if (!ha->fw_dump_template) {
6336 ql_log(ql_log_warn, vha, 0x0164,
6337 "Failed fwdump template allocate %x bytes.\n", risc_size);
6338 goto default_template;
6339 }
6340
6341 faddr += 7;
6342 risc_size -= 8;
6343 dcode = ha->fw_dump_template;
6344 qla24xx_read_flash_data(vha, dcode, faddr, risc_size);
6345 for (i = 0; i < risc_size; i++)
6346 dcode[i] = le32_to_cpu(dcode[i]);
6347
6348 if (!qla27xx_fwdt_template_valid(dcode)) {
6349 ql_log(ql_log_warn, vha, 0x0165,
6350 "Failed fwdump template validate\n");
6351 goto default_template;
6352 }
6353
6354 dlen = qla27xx_fwdt_template_size(dcode);
6355 ql_dbg(ql_dbg_init, vha, 0x0166,
6356 "-> template size %x bytes\n", dlen);
6357 if (dlen > risc_size * sizeof(*dcode)) {
6358 ql_log(ql_log_warn, vha, 0x0167,
383a298b
JC		 6359 "Failed fwdump template exceeds array by %lx bytes\n",
6360 (size_t)(dlen - risc_size * sizeof(*dcode)));
f73cb695
CD		 6361 goto default_template;
6362 }
6363 ha->fw_dump_template_len = dlen;
6364 return rval;
6365
6366default_template:
6367 ql_log(ql_log_warn, vha, 0x0168, "Using default fwdump template\n");
6368 if (ha->fw_dump_template)
6369 vfree(ha->fw_dump_template);
6370 ha->fw_dump_template = NULL;
6371 ha->fw_dump_template_len = 0;
6372
6373 dlen = qla27xx_fwdt_template_default_size();
6374 ql_dbg(ql_dbg_init, vha, 0x0169,
6375 "-> template allocating %x bytes...\n", dlen);
6376 ha->fw_dump_template = vmalloc(dlen);
6377 if (!ha->fw_dump_template) {
6378 ql_log(ql_log_warn, vha, 0x016a,
6379 "Failed fwdump template allocate %x bytes.\n", risc_size);
6380 goto failed_template;
6381 }
6382
6383 dcode = ha->fw_dump_template;
6384 risc_size = dlen / sizeof(*dcode);
6385 memcpy(dcode, qla27xx_fwdt_template_default(), dlen);
6386 for (i = 0; i < risc_size; i++)
6387 dcode[i] = be32_to_cpu(dcode[i]);
6388
6389 if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) {
6390 ql_log(ql_log_warn, vha, 0x016b,
6391 "Failed fwdump template validate\n");
6392 goto failed_template;
6393 }
6394
6395 dlen = qla27xx_fwdt_template_size(ha->fw_dump_template);
6396 ql_dbg(ql_dbg_init, vha, 0x016c,
6397 "-> template size %x bytes\n", dlen);
6398 ha->fw_dump_template_len = dlen;
6399 return rval;
6400
6401failed_template:
6402 ql_log(ql_log_warn, vha, 0x016d, "Failed default fwdump template\n");
6403 if (ha->fw_dump_template)
6404 vfree(ha->fw_dump_template);
6405 ha->fw_dump_template = NULL;
6406 ha->fw_dump_template_len = 0;
d1c61909
AV		 6407 return rval;
6408}
6409
e9454a88 6410#define QLA_FW_URL "http://ldriver.qlogic.com/firmware/"
d1c61909 6411
0107109e 6412int
e315cd28 6413qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5433383e
AV		 6414{
6415 int rval;
6416 int i, fragment;
6417 uint16_t *wcode, *fwcode;
6418 uint32_t risc_addr, risc_size, fwclen, wlen, *seg;
6419 struct fw_blob *blob;
e315cd28 6420 struct qla_hw_data *ha = vha->hw;
73208dfd 6421 struct req_que *req = ha->req_q_map[0];
5433383e
AV		 6422
6423 /* Load firmware blob. */
e315cd28 6424 blob = qla2x00_request_firmware(vha);
5433383e 6425 if (!blob) {
7c3df132 6426 ql_log(ql_log_info, vha, 0x0083,
94bcf830 6427 "Firmware image unavailable.\n");
7c3df132
SK		 6428 ql_log(ql_log_info, vha, 0x0084,
6429 "Firmware images can be retrieved from: "QLA_FW_URL ".\n");
5433383e
AV		 6430 return QLA_FUNCTION_FAILED;
6431 }
6432
6433 rval = QLA_SUCCESS;
6434
73208dfd 6435 wcode = (uint16_t *)req->ring;
5433383e
AV		 6436 *srisc_addr = 0;
6437 fwcode = (uint16_t *)blob->fw->data;
6438 fwclen = 0;
6439
6440 /* Validate firmware image by checking version. */
6441 if (blob->fw->size < 8 * sizeof(uint16_t)) {
7c3df132 6442 ql_log(ql_log_fatal, vha, 0x0085,
5b5e0928 6443 "Unable to verify integrity of firmware image (%zd).\n",
5433383e
AV		 6444 blob->fw->size);
6445 goto fail_fw_integrity;
6446 }
6447 for (i = 0; i < 4; i++)
6448 wcode[i] = be16_to_cpu(fwcode[i + 4]);
6449 if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff &&
6450 wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 &&
6451 wcode[2] == 0 && wcode[3] == 0)) {
7c3df132
SK		 6452 ql_log(ql_log_fatal, vha, 0x0086,
6453 "Unable to verify integrity of firmware image.\n");
6454 ql_log(ql_log_fatal, vha, 0x0087,
6455 "Firmware data: %04x %04x %04x %04x.\n",
6456 wcode[0], wcode[1], wcode[2], wcode[3]);
5433383e
AV		 6457 goto fail_fw_integrity;
6458 }
6459
6460 seg = blob->segs;
6461 while (*seg && rval == QLA_SUCCESS) {
6462 risc_addr = *seg;
6463 *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr;
6464 risc_size = be16_to_cpu(fwcode[3]);
6465
6466 /* Validate firmware image size. */
6467 fwclen += risc_size * sizeof(uint16_t);
6468 if (blob->fw->size < fwclen) {
7c3df132 6469 ql_log(ql_log_fatal, vha, 0x0088,
5433383e 6470 "Unable to verify integrity of firmware image "
5b5e0928 6471 "(%zd).\n", blob->fw->size);
5433383e
AV		 6472 goto fail_fw_integrity;
6473 }
6474
6475 fragment = 0;
6476 while (risc_size > 0 && rval == QLA_SUCCESS) {
6477 wlen = (uint16_t)(ha->fw_transfer_size >> 1);
6478 if (wlen > risc_size)
6479 wlen = risc_size;
7c3df132
SK		 6480 ql_dbg(ql_dbg_init, vha, 0x0089,
6481 "Loading risc segment@ risc addr %x number of "
6482 "words 0x%x.\n", risc_addr, wlen);
5433383e
AV		 6483
6484 for (i = 0; i < wlen; i++)
6485 wcode[i] = swab16(fwcode[i]);
6486
73208dfd 6487 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
5433383e
AV		 6488 wlen);
6489 if (rval) {
7c3df132
SK		 6490 ql_log(ql_log_fatal, vha, 0x008a,
6491 "Failed to load segment %d of firmware.\n",
6492 fragment);
5433383e
AV		 6493 break;
6494 }
6495
6496 fwcode += wlen;
6497 risc_addr += wlen;
6498 risc_size -= wlen;
6499 fragment++;
6500 }
6501
6502 /* Next segment. */
6503 seg++;
6504 }
6505 return rval;
6506
6507fail_fw_integrity:
6508 return QLA_FUNCTION_FAILED;
6509}
6510
eaac30be
AV		 6511static int
6512qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
0107109e
AV		 6513{
6514 int rval;
6515 int segments, fragment;
6516 uint32_t *dcode, dlen;
6517 uint32_t risc_addr;
6518 uint32_t risc_size;
6519 uint32_t i;
5433383e 6520 struct fw_blob *blob;
f73cb695
CD		 6521 const uint32_t *fwcode;
6522 uint32_t fwclen;
e315cd28 6523 struct qla_hw_data *ha = vha->hw;
73208dfd 6524 struct req_que *req = ha->req_q_map[0];
0107109e 6525
5433383e 6526 /* Load firmware blob. */
e315cd28 6527 blob = qla2x00_request_firmware(vha);
5433383e 6528 if (!blob) {
7c3df132 6529 ql_log(ql_log_warn, vha, 0x0090,
94bcf830 6530 "Firmware image unavailable.\n");
7c3df132
SK		 6531 ql_log(ql_log_warn, vha, 0x0091,
6532 "Firmware images can be retrieved from: "
6533 QLA_FW_URL ".\n");
d1c61909 6534
eaac30be 6535 return QLA_FUNCTION_FAILED;
0107109e
AV		 6536 }
6537
cfb0919c
CD		 6538 ql_dbg(ql_dbg_init, vha, 0x0092,
6539 "FW: Loading via request-firmware.\n");
eaac30be 6540
0107109e
AV		 6541 rval = QLA_SUCCESS;
6542
6543 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 6544 dcode = (uint32_t *)req->ring;
0107109e 6545 *srisc_addr = 0;
5433383e 6546 fwcode = (uint32_t *)blob->fw->data;
0107109e
AV		 6547 fwclen = 0;
6548
6549 /* Validate firmware image by checking version. */
5433383e 6550 if (blob->fw->size < 8 * sizeof(uint32_t)) {
7c3df132 6551 ql_log(ql_log_fatal, vha, 0x0093,
5b5e0928 6552 "Unable to verify integrity of firmware image (%zd).\n",
5433383e 6553 blob->fw->size);
f73cb695 6554 return QLA_FUNCTION_FAILED;
0107109e
AV		 6555 }
6556 for (i = 0; i < 4; i++)
6557 dcode[i] = be32_to_cpu(fwcode[i + 4]);
6558 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
6559 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
6560 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
6561 dcode[3] == 0)) {
7c3df132 6562 ql_log(ql_log_fatal, vha, 0x0094,
5b5e0928 6563 "Unable to verify integrity of firmware image (%zd).\n",
7c3df132
SK		 6564 blob->fw->size);
6565 ql_log(ql_log_fatal, vha, 0x0095,
6566 "Firmware data: %08x %08x %08x %08x.\n",
6567 dcode[0], dcode[1], dcode[2], dcode[3]);
f73cb695 6568 return QLA_FUNCTION_FAILED;
0107109e
AV		 6569 }
6570
6571 while (segments && rval == QLA_SUCCESS) {
6572 risc_addr = be32_to_cpu(fwcode[2]);
6573 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
6574 risc_size = be32_to_cpu(fwcode[3]);
6575
6576 /* Validate firmware image size. */
6577 fwclen += risc_size * sizeof(uint32_t);
5433383e 6578 if (blob->fw->size < fwclen) {
7c3df132 6579 ql_log(ql_log_fatal, vha, 0x0096,
5433383e 6580 "Unable to verify integrity of firmware image "
5b5e0928 6581 "(%zd).\n", blob->fw->size);
f73cb695 6582 return QLA_FUNCTION_FAILED;
0107109e
AV		 6583 }
6584
6585 fragment = 0;
6586 while (risc_size > 0 && rval == QLA_SUCCESS) {
6587 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
6588 if (dlen > risc_size)
6589 dlen = risc_size;
6590
7c3df132
SK		 6591 ql_dbg(ql_dbg_init, vha, 0x0097,
6592 "Loading risc segment@ risc addr %x "
6593 "number of dwords 0x%x.\n", risc_addr, dlen);
0107109e
AV		 6594
6595 for (i = 0; i < dlen; i++)
6596 dcode[i] = swab32(fwcode[i]);
6597
73208dfd 6598 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
590f98e5 6599 dlen);
0107109e 6600 if (rval) {
7c3df132
SK		 6601 ql_log(ql_log_fatal, vha, 0x0098,
6602 "Failed to load segment %d of firmware.\n",
6603 fragment);
f261f7af 6604 return QLA_FUNCTION_FAILED;
0107109e
AV		 6605 }
6606
6607 fwcode += dlen;
6608 risc_addr += dlen;
6609 risc_size -= dlen;
6610 fragment++;
6611 }
6612
6613 /* Next segment. */
6614 segments--;
6615 }
f73cb695
CD		 6616
6617 if (!IS_QLA27XX(ha))
6618 return rval;
6619
6620 if (ha->fw_dump_template)
6621 vfree(ha->fw_dump_template);
6622 ha->fw_dump_template = NULL;
6623 ha->fw_dump_template_len = 0;
6624
6625 ql_dbg(ql_dbg_init, vha, 0x171,
97ea702b
CD		 6626 "Loading fwdump template from %x\n",
6627 (uint32_t)((void *)fwcode - (void *)blob->fw->data));
f73cb695
CD		 6628 risc_size = be32_to_cpu(fwcode[2]);
6629 ql_dbg(ql_dbg_init, vha, 0x172,
6630 "-> array size %x dwords\n", risc_size);
6631 if (risc_size == 0 || risc_size == ~0)
6632 goto default_template;
6633
6634 dlen = (risc_size - 8) * sizeof(*fwcode);
6635 ql_dbg(ql_dbg_init, vha, 0x0173,
6636 "-> template allocating %x bytes...\n", dlen);
6637 ha->fw_dump_template = vmalloc(dlen);
6638 if (!ha->fw_dump_template) {
6639 ql_log(ql_log_warn, vha, 0x0174,
6640 "Failed fwdump template allocate %x bytes.\n", risc_size);
6641 goto default_template;
6642 }
6643
6644 fwcode += 7;
6645 risc_size -= 8;
6646 dcode = ha->fw_dump_template;
6647 for (i = 0; i < risc_size; i++)
6648 dcode[i] = le32_to_cpu(fwcode[i]);
6649
6650 if (!qla27xx_fwdt_template_valid(dcode)) {
6651 ql_log(ql_log_warn, vha, 0x0175,
6652 "Failed fwdump template validate\n");
6653 goto default_template;
6654 }
6655
6656 dlen = qla27xx_fwdt_template_size(dcode);
6657 ql_dbg(ql_dbg_init, vha, 0x0176,
6658 "-> template size %x bytes\n", dlen);
6659 if (dlen > risc_size * sizeof(*fwcode)) {
6660 ql_log(ql_log_warn, vha, 0x0177,
383a298b
JC		 6661 "Failed fwdump template exceeds array by %lx bytes\n",
6662 (size_t)(dlen - risc_size * sizeof(*fwcode)));
f73cb695
CD		 6663 goto default_template;
6664 }
6665 ha->fw_dump_template_len = dlen;
0107109e
AV		 6666 return rval;
6667
f73cb695
CD		 6668default_template:
6669 ql_log(ql_log_warn, vha, 0x0178, "Using default fwdump template\n");
6670 if (ha->fw_dump_template)
6671 vfree(ha->fw_dump_template);
6672 ha->fw_dump_template = NULL;
6673 ha->fw_dump_template_len = 0;
6674
6675 dlen = qla27xx_fwdt_template_default_size();
6676 ql_dbg(ql_dbg_init, vha, 0x0179,
6677 "-> template allocating %x bytes...\n", dlen);
6678 ha->fw_dump_template = vmalloc(dlen);
6679 if (!ha->fw_dump_template) {
6680 ql_log(ql_log_warn, vha, 0x017a,
6681 "Failed fwdump template allocate %x bytes.\n", risc_size);
6682 goto failed_template;
6683 }
6684
6685 dcode = ha->fw_dump_template;
6686 risc_size = dlen / sizeof(*fwcode);
6687 fwcode = qla27xx_fwdt_template_default();
6688 for (i = 0; i < risc_size; i++)
6689 dcode[i] = be32_to_cpu(fwcode[i]);
6690
6691 if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) {
6692 ql_log(ql_log_warn, vha, 0x017b,
6693 "Failed fwdump template validate\n");
6694 goto failed_template;
6695 }
6696
6697 dlen = qla27xx_fwdt_template_size(ha->fw_dump_template);
6698 ql_dbg(ql_dbg_init, vha, 0x017c,
6699 "-> template size %x bytes\n", dlen);
6700 ha->fw_dump_template_len = dlen;
6701 return rval;
6702
6703failed_template:
6704 ql_log(ql_log_warn, vha, 0x017d, "Failed default fwdump template\n");
6705 if (ha->fw_dump_template)
6706 vfree(ha->fw_dump_template);
6707 ha->fw_dump_template = NULL;
6708 ha->fw_dump_template_len = 0;
6709 return rval;
0107109e 6710}
18c6c127 6711
eaac30be
AV		 6712int
6713qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
6714{
6715 int rval;
6716
e337d907
AV		 6717 if (ql2xfwloadbin == 1)
6718 return qla81xx_load_risc(vha, srisc_addr);
6719
eaac30be
AV		 6720 /*
6721 * FW Load priority:
6722 * 1) Firmware via request-firmware interface (.bin file).
6723 * 2) Firmware residing in flash.
6724 */
6725 rval = qla24xx_load_risc_blob(vha, srisc_addr);
6726 if (rval == QLA_SUCCESS)
6727 return rval;
6728
cbc8eb67
AV		 6729 return qla24xx_load_risc_flash(vha, srisc_addr,
6730 vha->hw->flt_region_fw);
eaac30be
AV		 6731}
6732
6733int
6734qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
6735{
6736 int rval;
cbc8eb67 6737 struct qla_hw_data *ha = vha->hw;
eaac30be 6738
e337d907 6739 if (ql2xfwloadbin == 2)
cbc8eb67 6740 goto try_blob_fw;
e337d907 6741
eaac30be
AV		 6742 /*
6743 * FW Load priority:
6744 * 1) Firmware residing in flash.
6745 * 2) Firmware via request-firmware interface (.bin file).
cbc8eb67 6746 * 3) Golden-Firmware residing in flash -- limited operation.
eaac30be 6747 */
cbc8eb67 6748 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
eaac30be
AV		 6749 if (rval == QLA_SUCCESS)
6750 return rval;
6751
cbc8eb67
AV		 6752try_blob_fw:
6753 rval = qla24xx_load_risc_blob(vha, srisc_addr);
6754 if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw)
6755 return rval;
6756
7c3df132
SK		 6757 ql_log(ql_log_info, vha, 0x0099,
6758 "Attempting to fallback to golden firmware.\n");
cbc8eb67
AV		 6759 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
6760 if (rval != QLA_SUCCESS)
6761 return rval;
6762
7c3df132 6763 ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n");
cbc8eb67 6764 ha->flags.running_gold_fw = 1;
cbc8eb67 6765 return rval;
eaac30be
AV		 6766}
6767
18c6c127 6768void
e315cd28 6769qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha)
18c6c127
AV		 6770{
6771 int ret, retries;
e315cd28 6772 struct qla_hw_data *ha = vha->hw;
18c6c127 6773
85880801
AV		 6774 if (ha->flags.pci_channel_io_perm_failure)
6775 return;
e428924c 6776 if (!IS_FWI2_CAPABLE(ha))
18c6c127 6777 return;
75edf81d
AV		 6778 if (!ha->fw_major_version)
6779 return;
ec7193e2
QT		 6780 if (!ha->flags.fw_started)
6781 return;
18c6c127 6782
e315cd28 6783 ret = qla2x00_stop_firmware(vha);
7c7f1f29 6784 for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&
b469a7cb 6785 ret != QLA_INVALID_COMMAND && retries ; retries--) {
e315cd28
AC		 6786 ha->isp_ops->reset_chip(vha);
6787 if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS)
18c6c127 6788 continue;
e315cd28 6789 if (qla2x00_setup_chip(vha) != QLA_SUCCESS)
18c6c127 6790 continue;
7c3df132
SK		 6791 ql_log(ql_log_info, vha, 0x8015,
6792 "Attempting retry of stop-firmware command.\n");
e315cd28 6793 ret = qla2x00_stop_firmware(vha);
18c6c127 6794 }
ec7193e2
QT		 6795
6796 ha->flags.fw_started = 0;
6797 ha->flags.fw_init_done = 0;
18c6c127 6798}
2c3dfe3f
SJ		 6799
6800int
e315cd28 6801qla24xx_configure_vhba(scsi_qla_host_t *vha)
2c3dfe3f
SJ		 6802{
6803 int rval = QLA_SUCCESS;
0b91d116 6804 int rval2;
2c3dfe3f 6805 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28
AC		 6806 struct qla_hw_data *ha = vha->hw;
6807 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
67c2e93a
AC		 6808 struct req_que *req;
6809 struct rsp_que *rsp;
2c3dfe3f 6810
e315cd28 6811 if (!vha->vp_idx)
2c3dfe3f
SJ		 6812 return -EINVAL;
6813
e315cd28 6814 rval = qla2x00_fw_ready(base_vha);
d7459527
MH		 6815 if (vha->qpair)
6816 req = vha->qpair->req;
67c2e93a 6817 else
d7459527 6818 req = ha->req_q_map[0];
67c2e93a
AC		 6819 rsp = req->rsp;
6820
2c3dfe3f 6821 if (rval == QLA_SUCCESS) {
e315cd28 6822 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
73208dfd 6823 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
2c3dfe3f
SJ		 6824 }
6825
e315cd28 6826 vha->flags.management_server_logged_in = 0;
2c3dfe3f
SJ		 6827
6828 /* Login to SNS first */
0b91d116
CD		 6829 rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb,
6830 BIT_1);
6831 if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
6832 if (rval2 == QLA_MEMORY_ALLOC_FAILED)
6833 ql_dbg(ql_dbg_init, vha, 0x0120,
6834 "Failed SNS login: loop_id=%x, rval2=%d\n",
6835 NPH_SNS, rval2);
6836 else
6837 ql_dbg(ql_dbg_init, vha, 0x0103,
6838 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x "
6839 "mb[2]=%x mb[6]=%x mb[7]=%x.\n",
6840 NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]);
2c3dfe3f
SJ		 6841 return (QLA_FUNCTION_FAILED);
6842 }
6843
e315cd28
AC		 6844 atomic_set(&vha->loop_down_timer, 0);
6845 atomic_set(&vha->loop_state, LOOP_UP);
6846 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
6847 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
6848 rval = qla2x00_loop_resync(base_vha);
2c3dfe3f
SJ		 6849
6850 return rval;
6851}
4d4df193
HK		 6852
6853/* 84XX Support **************************************************************/
6854
6855static LIST_HEAD(qla_cs84xx_list);
6856static DEFINE_MUTEX(qla_cs84xx_mutex);
6857
6858static struct qla_chip_state_84xx *
e315cd28 6859qla84xx_get_chip(struct scsi_qla_host *vha)
4d4df193
HK		 6860{
6861 struct qla_chip_state_84xx *cs84xx;
e315cd28 6862 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 6863
6864 mutex_lock(&qla_cs84xx_mutex);
6865
6866 /* Find any shared 84xx chip. */
6867 list_for_each_entry(cs84xx, &qla_cs84xx_list, list) {
6868 if (cs84xx->bus == ha->pdev->bus) {
6869 kref_get(&cs84xx->kref);
6870 goto done;
6871 }
6872 }
6873
6874 cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL);
6875 if (!cs84xx)
6876 goto done;
6877
6878 kref_init(&cs84xx->kref);
6879 spin_lock_init(&cs84xx->access_lock);
6880 mutex_init(&cs84xx->fw_update_mutex);
6881 cs84xx->bus = ha->pdev->bus;
6882
6883 list_add_tail(&cs84xx->list, &qla_cs84xx_list);
6884done:
6885 mutex_unlock(&qla_cs84xx_mutex);
6886 return cs84xx;
6887}
6888
6889static void
6890__qla84xx_chip_release(struct kref *kref)
6891{
6892 struct qla_chip_state_84xx *cs84xx =
6893 container_of(kref, struct qla_chip_state_84xx, kref);
6894
6895 mutex_lock(&qla_cs84xx_mutex);
6896 list_del(&cs84xx->list);
6897 mutex_unlock(&qla_cs84xx_mutex);
6898 kfree(cs84xx);
6899}
6900
6901void
e315cd28 6902qla84xx_put_chip(struct scsi_qla_host *vha)
4d4df193 6903{
e315cd28 6904 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 6905 if (ha->cs84xx)
6906 kref_put(&ha->cs84xx->kref, __qla84xx_chip_release);
6907}
6908
6909static int
e315cd28 6910qla84xx_init_chip(scsi_qla_host_t *vha)
4d4df193
HK		 6911{
6912 int rval;
6913 uint16_t status[2];
e315cd28 6914 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 6915
6916 mutex_lock(&ha->cs84xx->fw_update_mutex);
6917
e315cd28 6918 rval = qla84xx_verify_chip(vha, status);
4d4df193
HK		 6919
6920 mutex_unlock(&ha->cs84xx->fw_update_mutex);
6921
6922 return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED:
6923 QLA_SUCCESS;
6924}
3a03eb79
AV		 6925
6926/* 81XX Support **************************************************************/
6927
6928int
6929qla81xx_nvram_config(scsi_qla_host_t *vha)
6930{
6931 int rval;
6932 struct init_cb_81xx *icb;
6933 struct nvram_81xx *nv;
6934 uint32_t *dptr;
6935 uint8_t *dptr1, *dptr2;
6936 uint32_t chksum;
6937 uint16_t cnt;
6938 struct qla_hw_data *ha = vha->hw;
6939
6940 rval = QLA_SUCCESS;
6941 icb = (struct init_cb_81xx *)ha->init_cb;
6942 nv = ha->nvram;
6943
6944 /* Determine NVRAM starting address. */
6945 ha->nvram_size = sizeof(struct nvram_81xx);
3a03eb79 6946 ha->vpd_size = FA_NVRAM_VPD_SIZE;
7ec0effd
AD		 6947 if (IS_P3P_TYPE(ha) || IS_QLA8031(ha))
6948 ha->vpd_size = FA_VPD_SIZE_82XX;
3a03eb79
AV		 6949
6950 /* Get VPD data into cache */
6951 ha->vpd = ha->nvram + VPD_OFFSET;
3d79038f
AV		 6952 ha->isp_ops->read_optrom(vha, ha->vpd, ha->flt_region_vpd << 2,
6953 ha->vpd_size);
3a03eb79
AV		 6954
6955 /* Get NVRAM data into cache and calculate checksum. */
3d79038f 6956 ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2,
3a03eb79 6957 ha->nvram_size);
3d79038f 6958 dptr = (uint32_t *)nv;
da08ef5c
JC		 6959 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++)
6960 chksum += le32_to_cpu(*dptr);
3a03eb79 6961
7c3df132
SK		 6962 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
6963 "Contents of NVRAM:\n");
6964 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
6965 (uint8_t *)nv, ha->nvram_size);
3a03eb79
AV		 6966
6967 /* Bad NVRAM data, set defaults parameters. */
6968 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
6969 || nv->id[3] != ' ' ||
ad950360 6970 nv->nvram_version < cpu_to_le16(ICB_VERSION)) {
3a03eb79 6971 /* Reset NVRAM data. */
7c3df132 6972 ql_log(ql_log_info, vha, 0x0073,
9e336520 6973 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132 6974 "version=0x%x.\n", chksum, nv->id[0],
3a03eb79 6975 le16_to_cpu(nv->nvram_version));
7c3df132
SK		 6976 ql_log(ql_log_info, vha, 0x0074,
6977 "Falling back to functioning (yet invalid -- WWPN) "
6978 "defaults.\n");
3a03eb79
AV		 6979
6980 /*
6981 * Set default initialization control block.
6982 */
6983 memset(nv, 0, ha->nvram_size);
ad950360
BVA		 6984 nv->nvram_version = cpu_to_le16(ICB_VERSION);
6985 nv->version = cpu_to_le16(ICB_VERSION);
98aee70d 6986 nv->frame_payload_size = 2048;
ad950360
BVA		 6987 nv->execution_throttle = cpu_to_le16(0xFFFF);
6988 nv->exchange_count = cpu_to_le16(0);
3a03eb79 6989 nv->port_name[0] = 0x21;
f73cb695 6990 nv->port_name[1] = 0x00 + ha->port_no + 1;
3a03eb79
AV		 6991 nv->port_name[2] = 0x00;
6992 nv->port_name[3] = 0xe0;
6993 nv->port_name[4] = 0x8b;
6994 nv->port_name[5] = 0x1c;
6995 nv->port_name[6] = 0x55;
6996 nv->port_name[7] = 0x86;
6997 nv->node_name[0] = 0x20;
6998 nv->node_name[1] = 0x00;
6999 nv->node_name[2] = 0x00;
7000 nv->node_name[3] = 0xe0;
7001 nv->node_name[4] = 0x8b;
7002 nv->node_name[5] = 0x1c;
7003 nv->node_name[6] = 0x55;
7004 nv->node_name[7] = 0x86;
ad950360
BVA		 7005 nv->login_retry_count = cpu_to_le16(8);
7006 nv->interrupt_delay_timer = cpu_to_le16(0);
7007 nv->login_timeout = cpu_to_le16(0);
3a03eb79 7008 nv->firmware_options_1 =
ad950360
BVA		 7009 cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
7010 nv->firmware_options_2 = cpu_to_le32(2 << 4);
7011 nv->firmware_options_2 |= cpu_to_le32(BIT_12);
7012 nv->firmware_options_3 = cpu_to_le32(2 << 13);
7013 nv->host_p = cpu_to_le32(BIT_11|BIT_10);
7014 nv->efi_parameters = cpu_to_le32(0);
3a03eb79 7015 nv->reset_delay = 5;
ad950360
BVA		 7016 nv->max_luns_per_target = cpu_to_le16(128);
7017 nv->port_down_retry_count = cpu_to_le16(30);
7018 nv->link_down_timeout = cpu_to_le16(180);
eeebcc92 7019 nv->enode_mac[0] = 0x00;
6246b8a1
GM		 7020 nv->enode_mac[1] = 0xC0;
7021 nv->enode_mac[2] = 0xDD;
3a03eb79
AV		 7022 nv->enode_mac[3] = 0x04;
7023 nv->enode_mac[4] = 0x05;
f73cb695 7024 nv->enode_mac[5] = 0x06 + ha->port_no + 1;
3a03eb79
AV		 7025
7026 rval = 1;
7027 }
7028
9e522cd8
AE		 7029 if (IS_T10_PI_CAPABLE(ha))
7030 nv->frame_payload_size &= ~7;
7031
aa230bc5
AE		 7032 qlt_81xx_config_nvram_stage1(vha, nv);
7033
3a03eb79 7034 /* Reset Initialization control block */
773120e4 7035 memset(icb, 0, ha->init_cb_size);
3a03eb79
AV		 7036
7037 /* Copy 1st segment. */
7038 dptr1 = (uint8_t *)icb;
7039 dptr2 = (uint8_t *)&nv->version;
7040 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
7041 while (cnt--)
7042 *dptr1++ = *dptr2++;
7043
7044 icb->login_retry_count = nv->login_retry_count;
7045
7046 /* Copy 2nd segment. */
7047 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
7048 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
7049 cnt = (uint8_t *)&icb->reserved_5 -
7050 (uint8_t *)&icb->interrupt_delay_timer;
7051 while (cnt--)
7052 *dptr1++ = *dptr2++;
7053
7054 memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac));
7055 /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */
7056 if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) {
69e5f1ea
AV		 7057 icb->enode_mac[0] = 0x00;
7058 icb->enode_mac[1] = 0xC0;
7059 icb->enode_mac[2] = 0xDD;
3a03eb79
AV		 7060 icb->enode_mac[3] = 0x04;
7061 icb->enode_mac[4] = 0x05;
f73cb695 7062 icb->enode_mac[5] = 0x06 + ha->port_no + 1;
3a03eb79
AV		 7063 }
7064
b64b0e8f
AV		 7065 /* Use extended-initialization control block. */
7066 memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb));
7067
3a03eb79
AV		 7068 /*
7069 * Setup driver NVRAM options.
7070 */
7071 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
a9083016 7072 "QLE8XXX");
3a03eb79 7073
aa230bc5
AE		 7074 qlt_81xx_config_nvram_stage2(vha, icb);
7075
3a03eb79 7076 /* Use alternate WWN? */
ad950360 7077 if (nv->host_p & cpu_to_le32(BIT_15)) {
3a03eb79
AV		 7078 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
7079 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
7080 }
7081
7082 /* Prepare nodename */
ad950360 7083 if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) {
3a03eb79
AV		 7084 /*
7085 * Firmware will apply the following mask if the nodename was
7086 * not provided.
7087 */
7088 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
7089 icb->node_name[0] &= 0xF0;
7090 }
7091
7092 /* Set host adapter parameters. */
7093 ha->flags.disable_risc_code_load = 0;
7094 ha->flags.enable_lip_reset = 0;
7095 ha->flags.enable_lip_full_login =
7096 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
7097 ha->flags.enable_target_reset =
7098 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
7099 ha->flags.enable_led_scheme = 0;
7100 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
7101
7102 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
7103 (BIT_6 | BIT_5 | BIT_4)) >> 4;
7104
7105 /* save HBA serial number */
7106 ha->serial0 = icb->port_name[5];
7107 ha->serial1 = icb->port_name[6];
7108 ha->serial2 = icb->port_name[7];
7109 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
7110 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
7111
ad950360 7112 icb->execution_throttle = cpu_to_le16(0xFFFF);
3a03eb79
AV		 7113
7114 ha->retry_count = le16_to_cpu(nv->login_retry_count);
7115
7116 /* Set minimum login_timeout to 4 seconds. */
7117 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
7118 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
7119 if (le16_to_cpu(nv->login_timeout) < 4)
ad950360 7120 nv->login_timeout = cpu_to_le16(4);
3a03eb79 7121 ha->login_timeout = le16_to_cpu(nv->login_timeout);
3a03eb79
AV		 7122
7123 /* Set minimum RATOV to 100 tenths of a second. */
7124 ha->r_a_tov = 100;
7125
7126 ha->loop_reset_delay = nv->reset_delay;
7127
7128 /* Link Down Timeout = 0:
7129 *
7ec0effd 7130 * When Port Down timer expires we will start returning
3a03eb79
AV		 7131 * I/O's to OS with "DID_NO_CONNECT".
7132 *
7133 * Link Down Timeout != 0:
7134 *
7135 * The driver waits for the link to come up after link down
7136 * before returning I/Os to OS with "DID_NO_CONNECT".
7137 */
7138 if (le16_to_cpu(nv->link_down_timeout) == 0) {
7139 ha->loop_down_abort_time =
7140 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
7141 } else {
7142 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
7143 ha->loop_down_abort_time =
7144 (LOOP_DOWN_TIME - ha->link_down_timeout);
7145 }
7146
7147 /* Need enough time to try and get the port back. */
7148 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
7149 if (qlport_down_retry)
7150 ha->port_down_retry_count = qlport_down_retry;
7151
7152 /* Set login_retry_count */
7153 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
7154 if (ha->port_down_retry_count ==
7155 le16_to_cpu(nv->port_down_retry_count) &&
7156 ha->port_down_retry_count > 3)
7157 ha->login_retry_count = ha->port_down_retry_count;
7158 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
7159 ha->login_retry_count = ha->port_down_retry_count;
7160 if (ql2xloginretrycount)
7161 ha->login_retry_count = ql2xloginretrycount;
7162
6246b8a1 7163 /* if not running MSI-X we need handshaking on interrupts */
f73cb695 7164 if (!vha->hw->flags.msix_enabled && (IS_QLA83XX(ha) || IS_QLA27XX(ha)))
ad950360 7165 icb->firmware_options_2 |= cpu_to_le32(BIT_22);
6246b8a1 7166
3a03eb79
AV		 7167 /* Enable ZIO. */
7168 if (!vha->flags.init_done) {
7169 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
7170 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
7171 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
7172 le16_to_cpu(icb->interrupt_delay_timer): 2;
7173 }
ad950360 7174 icb->firmware_options_2 &= cpu_to_le32(
3a03eb79
AV		 7175 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
7176 vha->flags.process_response_queue = 0;
7177 if (ha->zio_mode != QLA_ZIO_DISABLED) {
7178 ha->zio_mode = QLA_ZIO_MODE_6;
7179
7c3df132 7180 ql_log(ql_log_info, vha, 0x0075,
3a03eb79 7181 "ZIO mode %d enabled; timer delay (%d us).\n",
7c3df132
SK		 7182 ha->zio_mode,
7183 ha->zio_timer * 100);
3a03eb79
AV		 7184
7185 icb->firmware_options_2 |= cpu_to_le32(
7186 (uint32_t)ha->zio_mode);
7187 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
7188 vha->flags.process_response_queue = 1;
7189 }
7190
41dc529a
QT		 7191 /* enable RIDA Format2 */
7192 if (qla_tgt_mode_enabled(vha) || qla_dual_mode_enabled(vha))
7193 icb->firmware_options_3 |= BIT_0;
7194
3a03eb79 7195 if (rval) {
7c3df132
SK		 7196 ql_log(ql_log_warn, vha, 0x0076,
7197 "NVRAM configuration failed.\n");
3a03eb79
AV		 7198 }
7199 return (rval);
7200}
7201
a9083016
GM		 7202int
7203qla82xx_restart_isp(scsi_qla_host_t *vha)
7204{
7205 int status, rval;
a9083016
GM		 7206 struct qla_hw_data *ha = vha->hw;
7207 struct req_que *req = ha->req_q_map[0];
7208 struct rsp_que *rsp = ha->rsp_q_map[0];
7209 struct scsi_qla_host *vp;
feafb7b1 7210 unsigned long flags;
a9083016
GM		 7211
7212 status = qla2x00_init_rings(vha);
7213 if (!status) {
7214 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
7215 ha->flags.chip_reset_done = 1;
7216
7217 status = qla2x00_fw_ready(vha);
7218 if (!status) {
a9083016
GM		 7219 /* Issue a marker after FW becomes ready. */
7220 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
a9083016 7221 vha->flags.online = 1;
7108b76e 7222 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
a9083016
GM		 7223 }
7224
7225 /* if no cable then assume it's good */
7226 if ((vha->device_flags & DFLG_NO_CABLE))
7227 status = 0;
a9083016
GM		 7228 }
7229
7230 if (!status) {
7231 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
7232
7233 if (!atomic_read(&vha->loop_down_timer)) {
7234 /*
7235 * Issue marker command only when we are going
7236 * to start the I/O .
7237 */
7238 vha->marker_needed = 1;
7239 }
7240
a9083016
GM		 7241 ha->isp_ops->enable_intrs(ha);
7242
7243 ha->isp_abort_cnt = 0;
7244 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
7245
53296788 7246 /* Update the firmware version */
3173167f 7247 status = qla82xx_check_md_needed(vha);
53296788 7248
a9083016
GM		 7249 if (ha->fce) {
7250 ha->flags.fce_enabled = 1;
7251 memset(ha->fce, 0,
7252 fce_calc_size(ha->fce_bufs));
7253 rval = qla2x00_enable_fce_trace(vha,
7254 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
7255 &ha->fce_bufs);
7256 if (rval) {
cfb0919c 7257 ql_log(ql_log_warn, vha, 0x8001,
7c3df132
SK		 7258 "Unable to reinitialize FCE (%d).\n",
7259 rval);
a9083016
GM		 7260 ha->flags.fce_enabled = 0;
7261 }
7262 }
7263
7264 if (ha->eft) {
7265 memset(ha->eft, 0, EFT_SIZE);
7266 rval = qla2x00_enable_eft_trace(vha,
7267 ha->eft_dma, EFT_NUM_BUFFERS);
7268 if (rval) {
cfb0919c 7269 ql_log(ql_log_warn, vha, 0x8010,
7c3df132
SK		 7270 "Unable to reinitialize EFT (%d).\n",
7271 rval);
a9083016
GM		 7272 }
7273 }
a9083016
GM		 7274 }
7275
7276 if (!status) {
cfb0919c 7277 ql_dbg(ql_dbg_taskm, vha, 0x8011,
7c3df132 7278 "qla82xx_restart_isp succeeded.\n");
feafb7b1
AE		 7279
7280 spin_lock_irqsave(&ha->vport_slock, flags);
7281 list_for_each_entry(vp, &ha->vp_list, list) {
7282 if (vp->vp_idx) {
7283 atomic_inc(&vp->vref_count);
7284 spin_unlock_irqrestore(&ha->vport_slock, flags);
7285
a9083016 7286 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 7287
7288 spin_lock_irqsave(&ha->vport_slock, flags);
7289 atomic_dec(&vp->vref_count);
7290 }
a9083016 7291 }
feafb7b1
AE		 7292 spin_unlock_irqrestore(&ha->vport_slock, flags);
7293
a9083016 7294 } else {
cfb0919c 7295 ql_log(ql_log_warn, vha, 0x8016,
7c3df132 7296 "qla82xx_restart_isp **** FAILED ****.\n");
a9083016
GM		 7297 }
7298
7299 return status;
7300}
7301
3a03eb79 7302void
ae97c91e 7303qla81xx_update_fw_options(scsi_qla_host_t *vha)
3a03eb79 7304{
ae97c91e
AV		 7305 struct qla_hw_data *ha = vha->hw;
7306
f198cafa
HM		 7307 /* Hold status IOCBs until ABTS response received. */
7308 if (ql2xfwholdabts)
7309 ha->fw_options[3] |= BIT_12;
7310
088d09d4
GM		 7311 /* Set Retry FLOGI in case of P2P connection */
7312 if (ha->operating_mode == P2P) {
7313 ha->fw_options[2] |= BIT_3;
7314 ql_dbg(ql_dbg_disc, vha, 0x2103,
7315 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
7316 __func__, ha->fw_options[2]);
7317 }
7318
41dc529a
QT		 7319 /* Move PUREX, ABTS RX & RIDA to ATIOQ */
7320 if (ql2xmvasynctoatio) {
7321 if (qla_tgt_mode_enabled(vha) ||
7322 qla_dual_mode_enabled(vha))
7323 ha->fw_options[2] |= BIT_11;
7324 else
7325 ha->fw_options[2] &= ~BIT_11;
7326 }
7327
7328 if (ql2xetsenable) {
7329 /* Enable ETS Burst. */
7330 memset(ha->fw_options, 0, sizeof(ha->fw_options));
7331 ha->fw_options[2] |= BIT_9;
7332 }
7333
7334 ql_dbg(ql_dbg_init, vha, 0xffff,
7335 "%s, add FW options 1-3 = 0x%04x 0x%04x 0x%04x mode %x\n",
7336 __func__, ha->fw_options[1], ha->fw_options[2],
7337 ha->fw_options[3], vha->host->active_mode);
ae97c91e 7338
ae97c91e 7339 qla2x00_set_fw_options(vha, ha->fw_options);
3a03eb79 7340}
09ff701a
SR		 7341
7342/*
7343 * qla24xx_get_fcp_prio
7344 * Gets the fcp cmd priority value for the logged in port.
7345 * Looks for a match of the port descriptors within
7346 * each of the fcp prio config entries. If a match is found,
7347 * the tag (priority) value is returned.
7348 *
7349 * Input:
21090cbe 7350 * vha = scsi host structure pointer.
09ff701a
SR		 7351 * fcport = port structure pointer.
7352 *
7353 * Return:
6c452a45 7354 * non-zero (if found)
f28a0a96 7355 * -1 (if not found)
09ff701a
SR		 7356 *
7357 * Context:
7358 * Kernel context
7359 */
f28a0a96 7360static int
09ff701a
SR		 7361qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
7362{
7363 int i, entries;
7364 uint8_t pid_match, wwn_match;
f28a0a96 7365 int priority;
09ff701a
SR		 7366 uint32_t pid1, pid2;
7367 uint64_t wwn1, wwn2;
7368 struct qla_fcp_prio_entry *pri_entry;
7369 struct qla_hw_data *ha = vha->hw;
7370
7371 if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled)
f28a0a96 7372 return -1;
09ff701a 7373
f28a0a96 7374 priority = -1;
09ff701a
SR		 7375 entries = ha->fcp_prio_cfg->num_entries;
7376 pri_entry = &ha->fcp_prio_cfg->entry[0];
7377
7378 for (i = 0; i < entries; i++) {
7379 pid_match = wwn_match = 0;
7380
7381 if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) {
7382 pri_entry++;
7383 continue;
7384 }
7385
7386 /* check source pid for a match */
7387 if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) {
7388 pid1 = pri_entry->src_pid & INVALID_PORT_ID;
7389 pid2 = vha->d_id.b24 & INVALID_PORT_ID;
7390 if (pid1 == INVALID_PORT_ID)
7391 pid_match++;
7392 else if (pid1 == pid2)
7393 pid_match++;
7394 }
7395
7396 /* check destination pid for a match */
7397 if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) {
7398 pid1 = pri_entry->dst_pid & INVALID_PORT_ID;
7399 pid2 = fcport->d_id.b24 & INVALID_PORT_ID;
7400 if (pid1 == INVALID_PORT_ID)
7401 pid_match++;
7402 else if (pid1 == pid2)
7403 pid_match++;
7404 }
7405
7406 /* check source WWN for a match */
7407 if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) {
7408 wwn1 = wwn_to_u64(vha->port_name);
7409 wwn2 = wwn_to_u64(pri_entry->src_wwpn);
7410 if (wwn2 == (uint64_t)-1)
7411 wwn_match++;
7412 else if (wwn1 == wwn2)
7413 wwn_match++;
7414 }
7415
7416 /* check destination WWN for a match */
7417 if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) {
7418 wwn1 = wwn_to_u64(fcport->port_name);
7419 wwn2 = wwn_to_u64(pri_entry->dst_wwpn);
7420 if (wwn2 == (uint64_t)-1)
7421 wwn_match++;
7422 else if (wwn1 == wwn2)
7423 wwn_match++;
7424 }
7425
7426 if (pid_match == 2 || wwn_match == 2) {
7427 /* Found a matching entry */
7428 if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID)
7429 priority = pri_entry->tag;
7430 break;
7431 }
7432
7433 pri_entry++;
7434 }
7435
7436 return priority;
7437}
7438
7439/*
7440 * qla24xx_update_fcport_fcp_prio
7441 * Activates fcp priority for the logged in fc port
7442 *
7443 * Input:
21090cbe 7444 * vha = scsi host structure pointer.
09ff701a
SR		 7445 * fcp = port structure pointer.
7446 *
7447 * Return:
7448 * QLA_SUCCESS or QLA_FUNCTION_FAILED
7449 *
7450 * Context:
7451 * Kernel context.
7452 */
7453int
21090cbe 7454qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
09ff701a
SR		 7455{
7456 int ret;
f28a0a96 7457 int priority;
09ff701a
SR		 7458 uint16_t mb[5];
7459
21090cbe
MI		 7460 if (fcport->port_type != FCT_TARGET ||
7461 fcport->loop_id == FC_NO_LOOP_ID)
09ff701a
SR		 7462 return QLA_FUNCTION_FAILED;
7463
21090cbe 7464 priority = qla24xx_get_fcp_prio(vha, fcport);
f28a0a96
AV		 7465 if (priority < 0)
7466 return QLA_FUNCTION_FAILED;
7467
7ec0effd 7468 if (IS_P3P_TYPE(vha->hw)) {
a00f6296
SK		 7469 fcport->fcp_prio = priority & 0xf;
7470 return QLA_SUCCESS;
7471 }
7472
21090cbe 7473 ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb);
cfb0919c
CD		 7474 if (ret == QLA_SUCCESS) {
7475 if (fcport->fcp_prio != priority)
7476 ql_dbg(ql_dbg_user, vha, 0x709e,
7477 "Updated FCP_CMND priority - value=%d loop_id=%d "
7478 "port_id=%02x%02x%02x.\n", priority,
7479 fcport->loop_id, fcport->d_id.b.domain,
7480 fcport->d_id.b.area, fcport->d_id.b.al_pa);
a00f6296 7481 fcport->fcp_prio = priority & 0xf;
cfb0919c 7482 } else
7c3df132 7483 ql_dbg(ql_dbg_user, vha, 0x704f,
cfb0919c
CD		 7484 "Unable to update FCP_CMND priority - ret=0x%x for "
7485 "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id,
7486 fcport->d_id.b.domain, fcport->d_id.b.area,
7487 fcport->d_id.b.al_pa);
09ff701a
SR		 7488 return ret;
7489}
7490
7491/*
7492 * qla24xx_update_all_fcp_prio
7493 * Activates fcp priority for all the logged in ports
7494 *
7495 * Input:
7496 * ha = adapter block pointer.
7497 *
7498 * Return:
7499 * QLA_SUCCESS or QLA_FUNCTION_FAILED
7500 *
7501 * Context:
7502 * Kernel context.
7503 */
7504int
7505qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha)
7506{
7507 int ret;
7508 fc_port_t *fcport;
7509
7510 ret = QLA_FUNCTION_FAILED;
7511 /* We need to set priority for all logged in ports */
7512 list_for_each_entry(fcport, &vha->vp_fcports, list)
7513 ret = qla24xx_update_fcport_fcp_prio(vha, fcport);
7514
7515 return ret;
7516}
d7459527
MH		 7517
7518struct qla_qpair *qla2xxx_create_qpair(struct scsi_qla_host *vha, int qos, int vp_idx)
7519{
7520 int rsp_id = 0;
7521 int req_id = 0;
7522 int i;
7523 struct qla_hw_data *ha = vha->hw;
7524 uint16_t qpair_id = 0;
7525 struct qla_qpair *qpair = NULL;
7526 struct qla_msix_entry *msix;
7527
7528 if (!(ha->fw_attributes & BIT_6) || !ha->flags.msix_enabled) {
7529 ql_log(ql_log_warn, vha, 0x00181,
7530 "FW/Driver is not multi-queue capable.\n");
7531 return NULL;
7532 }
7533
7534 if (ql2xmqsupport) {
7535 qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
7536 if (qpair == NULL) {
7537 ql_log(ql_log_warn, vha, 0x0182,
7538 "Failed to allocate memory for queue pair.\n");
7539 return NULL;
7540 }
7541 memset(qpair, 0, sizeof(struct qla_qpair));
7542
7543 qpair->hw = vha->hw;
25ff6af1 7544 qpair->vha = vha;
d7459527
MH		 7545
7546 /* Assign available que pair id */
7547 mutex_lock(&ha->mq_lock);
7548 qpair_id = find_first_zero_bit(ha->qpair_qid_map, ha->max_qpairs);
b95b9452 7549 if (ha->num_qpairs >= ha->max_qpairs) {
d7459527
MH		 7550 mutex_unlock(&ha->mq_lock);
7551 ql_log(ql_log_warn, vha, 0x0183,
7552 "No resources to create additional q pair.\n");
7553 goto fail_qid_map;
7554 }
b95b9452 7555 ha->num_qpairs++;
d7459527
MH		 7556 set_bit(qpair_id, ha->qpair_qid_map);
7557 ha->queue_pair_map[qpair_id] = qpair;
7558 qpair->id = qpair_id;
7559 qpair->vp_idx = vp_idx;
7560
7561 for (i = 0; i < ha->msix_count; i++) {
093df737 7562 msix = &ha->msix_entries[i];
d7459527
MH		 7563 if (msix->in_use)
7564 continue;
7565 qpair->msix = msix;
7566 ql_log(ql_dbg_multiq, vha, 0xc00f,
7567 "Vector %x selected for qpair\n", msix->vector);
7568 break;
7569 }
7570 if (!qpair->msix) {
7571 ql_log(ql_log_warn, vha, 0x0184,
7572 "Out of MSI-X vectors!.\n");
7573 goto fail_msix;
7574 }
7575
7576 qpair->msix->in_use = 1;
7577 list_add_tail(&qpair->qp_list_elem, &vha->qp_list);
7578
7579 mutex_unlock(&ha->mq_lock);
7580
7581 /* Create response queue first */
7582 rsp_id = qla25xx_create_rsp_que(ha, 0, 0, 0, qpair);
7583 if (!rsp_id) {
7584 ql_log(ql_log_warn, vha, 0x0185,
7585 "Failed to create response queue.\n");
7586 goto fail_rsp;
7587 }
7588
7589 qpair->rsp = ha->rsp_q_map[rsp_id];
7590
7591 /* Create request queue */
7592 req_id = qla25xx_create_req_que(ha, 0, vp_idx, 0, rsp_id, qos);
7593 if (!req_id) {
7594 ql_log(ql_log_warn, vha, 0x0186,
7595 "Failed to create request queue.\n");
7596 goto fail_req;
7597 }
7598
7599 qpair->req = ha->req_q_map[req_id];
7600 qpair->rsp->req = qpair->req;
7601
7602 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
7603 if (ha->fw_attributes & BIT_4)
7604 qpair->difdix_supported = 1;
7605 }
7606
7607 qpair->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
7608 if (!qpair->srb_mempool) {
7609 ql_log(ql_log_warn, vha, 0x0191,
7610 "Failed to create srb mempool for qpair %d\n",
7611 qpair->id);
7612 goto fail_mempool;
7613 }
7614
7615 /* Mark as online */
7616 qpair->online = 1;
7617
7618 if (!vha->flags.qpairs_available)
7619 vha->flags.qpairs_available = 1;
7620
7621 ql_dbg(ql_dbg_multiq, vha, 0xc00d,
7622 "Request/Response queue pair created, id %d\n",
7623 qpair->id);
7624 ql_dbg(ql_dbg_init, vha, 0x0187,
7625 "Request/Response queue pair created, id %d\n",
7626 qpair->id);
7627 }
7628 return qpair;
7629
7630fail_mempool:
7631fail_req:
7632 qla25xx_delete_rsp_que(vha, qpair->rsp);
7633fail_rsp:
7634 mutex_lock(&ha->mq_lock);
7635 qpair->msix->in_use = 0;
7636 list_del(&qpair->qp_list_elem);
7637 if (list_empty(&vha->qp_list))
7638 vha->flags.qpairs_available = 0;
7639fail_msix:
7640 ha->queue_pair_map[qpair_id] = NULL;
7641 clear_bit(qpair_id, ha->qpair_qid_map);
b95b9452 7642 ha->num_qpairs--;
d7459527
MH		 7643 mutex_unlock(&ha->mq_lock);
7644fail_qid_map:
7645 kfree(qpair);
7646 return NULL;
7647}
7648
7649int qla2xxx_delete_qpair(struct scsi_qla_host *vha, struct qla_qpair *qpair)
7650{
7651 int ret;
7652 struct qla_hw_data *ha = qpair->hw;
7653
7654 qpair->delete_in_progress = 1;
7655 while (atomic_read(&qpair->ref_count))
7656 msleep(500);
7657
7658 ret = qla25xx_delete_req_que(vha, qpair->req);
7659 if (ret != QLA_SUCCESS)
7660 goto fail;
7661 ret = qla25xx_delete_rsp_que(vha, qpair->rsp);
7662 if (ret != QLA_SUCCESS)
7663 goto fail;
7664
7665 mutex_lock(&ha->mq_lock);
7666 ha->queue_pair_map[qpair->id] = NULL;
7667 clear_bit(qpair->id, ha->qpair_qid_map);
b95b9452 7668 ha->num_qpairs--;
d7459527
MH		 7669 list_del(&qpair->qp_list_elem);
7670 if (list_empty(&vha->qp_list))
7671 vha->flags.qpairs_available = 0;
7672 mempool_destroy(qpair->srb_mempool);
7673 kfree(qpair);
7674 mutex_unlock(&ha->mq_lock);
7675
7676 return QLA_SUCCESS;
7677fail:
7678 return ret;
7679}
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