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[SCSI] qla2xxx: Correct the port no assignment for ISP82XX.
[mirror_ubuntu-zesty-kernel.git] / drivers / scsi / qla2xxx / qla_init.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
1e63395c 3 * Copyright (c) 2003-2013 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
73208dfd 8#include "qla_gbl.h"
1da177e4
LT		 9
10#include <linux/delay.h>
5a0e3ad6 11#include <linux/slab.h>
0107109e 12#include <linux/vmalloc.h>
1da177e4
LT		 13
14#include "qla_devtbl.h"
15
4e08df3f
DM		 16#ifdef CONFIG_SPARC
17#include <asm/prom.h>
4e08df3f
DM		 18#endif
19
2d70c103
NB		 20#include <target/target_core_base.h>
21#include "qla_target.h"
22
1da177e4
LT		 23/*
24* QLogic ISP2x00 Hardware Support Function Prototypes.
25*/
1da177e4 26static int qla2x00_isp_firmware(scsi_qla_host_t *);
1da177e4 27static int qla2x00_setup_chip(scsi_qla_host_t *);
1da177e4
LT		 28static int qla2x00_fw_ready(scsi_qla_host_t *);
29static int qla2x00_configure_hba(scsi_qla_host_t *);
1da177e4
LT		 30static int qla2x00_configure_loop(scsi_qla_host_t *);
31static int qla2x00_configure_local_loop(scsi_qla_host_t *);
1da177e4
LT		 32static int qla2x00_configure_fabric(scsi_qla_host_t *);
33static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *, struct list_head *);
1da177e4
LT		 34static int qla2x00_fabric_dev_login(scsi_qla_host_t *, fc_port_t *,
35 uint16_t *);
1da177e4
LT		 36
37static int qla2x00_restart_isp(scsi_qla_host_t *);
1da177e4 38
4d4df193
HK		 39static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *);
40static int qla84xx_init_chip(scsi_qla_host_t *);
73208dfd 41static int qla25xx_init_queues(struct qla_hw_data *);
4d4df193 42
ac280b67
AV		 43/* SRB Extensions ---------------------------------------------------------- */
44
9ba56b95
GM		 45void
46qla2x00_sp_timeout(unsigned long __data)
ac280b67
AV		 47{
48 srb_t *sp = (srb_t *)__data;
4916392b 49 struct srb_iocb *iocb;
ac280b67
AV		 50 fc_port_t *fcport = sp->fcport;
51 struct qla_hw_data *ha = fcport->vha->hw;
52 struct req_que *req;
53 unsigned long flags;
54
55 spin_lock_irqsave(&ha->hardware_lock, flags);
56 req = ha->req_q_map[0];
57 req->outstanding_cmds[sp->handle] = NULL;
9ba56b95 58 iocb = &sp->u.iocb_cmd;
4916392b 59 iocb->timeout(sp);
9ba56b95 60 sp->free(fcport->vha, sp);
6ac52608 61 spin_unlock_irqrestore(&ha->hardware_lock, flags);
ac280b67
AV		 62}
63
9ba56b95
GM		 64void
65qla2x00_sp_free(void *data, void *ptr)
ac280b67 66{
9ba56b95
GM		 67 srb_t *sp = (srb_t *)ptr;
68 struct srb_iocb *iocb = &sp->u.iocb_cmd;
69 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
ac280b67 70
4d97cc53 71 del_timer(&iocb->timer);
b00ee7d7 72 qla2x00_rel_sp(vha, sp);
ac280b67
AV		 73}
74
ac280b67
AV		 75/* Asynchronous Login/Logout Routines -------------------------------------- */
76
a9b6f722 77unsigned long
5b91490e
AV		 78qla2x00_get_async_timeout(struct scsi_qla_host *vha)
79{
80 unsigned long tmo;
81 struct qla_hw_data *ha = vha->hw;
82
83 /* Firmware should use switch negotiated r_a_tov for timeout. */
84 tmo = ha->r_a_tov / 10 * 2;
8ae6d9c7
GM		 85 if (IS_QLAFX00(ha)) {
86 tmo = FX00_DEF_RATOV * 2;
87 } else if (!IS_FWI2_CAPABLE(ha)) {
5b91490e
AV		 88 /*
89 * Except for earlier ISPs where the timeout is seeded from the
90 * initialization control block.
91 */
92 tmo = ha->login_timeout;
93 }
94 return tmo;
95}
ac280b67
AV		 96
97static void
9ba56b95 98qla2x00_async_iocb_timeout(void *data)
ac280b67 99{
9ba56b95 100 srb_t *sp = (srb_t *)data;
ac280b67 101 fc_port_t *fcport = sp->fcport;
ac280b67 102
7c3df132 103 ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
cfb0919c 104 "Async-%s timeout - hdl=%x portid=%02x%02x%02x.\n",
9ba56b95 105 sp->name, sp->handle, fcport->d_id.b.domain, fcport->d_id.b.area,
7c3df132 106 fcport->d_id.b.al_pa);
ac280b67 107
5ff1d584 108 fcport->flags &= ~FCF_ASYNC_SENT;
9ba56b95
GM		 109 if (sp->type == SRB_LOGIN_CMD) {
110 struct srb_iocb *lio = &sp->u.iocb_cmd;
ac280b67 111 qla2x00_post_async_logout_work(fcport->vha, fcport, NULL);
6ac52608
AV		 112 /* Retry as needed. */
113 lio->u.logio.data[0] = MBS_COMMAND_ERROR;
114 lio->u.logio.data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
115 QLA_LOGIO_LOGIN_RETRIED : 0;
116 qla2x00_post_async_login_done_work(fcport->vha, fcport,
117 lio->u.logio.data);
118 }
ac280b67
AV		 119}
120
99b0bec7 121static void
9ba56b95 122qla2x00_async_login_sp_done(void *data, void *ptr, int res)
99b0bec7 123{
9ba56b95
GM		 124 srb_t *sp = (srb_t *)ptr;
125 struct srb_iocb *lio = &sp->u.iocb_cmd;
126 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
127
128 if (!test_bit(UNLOADING, &vha->dpc_flags))
129 qla2x00_post_async_login_done_work(sp->fcport->vha, sp->fcport,
130 lio->u.logio.data);
131 sp->free(sp->fcport->vha, sp);
99b0bec7
AV		 132}
133
ac280b67
AV		 134int
135qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport,
136 uint16_t *data)
137{
ac280b67 138 srb_t *sp;
4916392b 139 struct srb_iocb *lio;
ac280b67
AV		 140 int rval;
141
142 rval = QLA_FUNCTION_FAILED;
9ba56b95 143 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 144 if (!sp)
145 goto done;
146
9ba56b95
GM		 147 sp->type = SRB_LOGIN_CMD;
148 sp->name = "login";
149 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
150
151 lio = &sp->u.iocb_cmd;
3822263e 152 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 153 sp->done = qla2x00_async_login_sp_done;
4916392b 154 lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI;
ac280b67 155 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 156 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
ac280b67
AV		 157 rval = qla2x00_start_sp(sp);
158 if (rval != QLA_SUCCESS)
159 goto done_free_sp;
160
7c3df132 161 ql_dbg(ql_dbg_disc, vha, 0x2072,
cfb0919c
CD		 162 "Async-login - hdl=%x, loopid=%x portid=%02x%02x%02x "
163 "retries=%d.\n", sp->handle, fcport->loop_id,
164 fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
165 fcport->login_retry);
ac280b67
AV		 166 return rval;
167
168done_free_sp:
9ba56b95 169 sp->free(fcport->vha, sp);
ac280b67
AV		 170done:
171 return rval;
172}
173
99b0bec7 174static void
9ba56b95 175qla2x00_async_logout_sp_done(void *data, void *ptr, int res)
99b0bec7 176{
9ba56b95
GM		 177 srb_t *sp = (srb_t *)ptr;
178 struct srb_iocb *lio = &sp->u.iocb_cmd;
179 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
180
181 if (!test_bit(UNLOADING, &vha->dpc_flags))
182 qla2x00_post_async_logout_done_work(sp->fcport->vha, sp->fcport,
183 lio->u.logio.data);
184 sp->free(sp->fcport->vha, sp);
99b0bec7
AV		 185}
186
ac280b67
AV		 187int
188qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport)
189{
ac280b67 190 srb_t *sp;
4916392b 191 struct srb_iocb *lio;
ac280b67
AV		 192 int rval;
193
194 rval = QLA_FUNCTION_FAILED;
9ba56b95 195 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 196 if (!sp)
197 goto done;
198
9ba56b95
GM		 199 sp->type = SRB_LOGOUT_CMD;
200 sp->name = "logout";
201 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
202
203 lio = &sp->u.iocb_cmd;
3822263e 204 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 205 sp->done = qla2x00_async_logout_sp_done;
ac280b67
AV		 206 rval = qla2x00_start_sp(sp);
207 if (rval != QLA_SUCCESS)
208 goto done_free_sp;
209
7c3df132 210 ql_dbg(ql_dbg_disc, vha, 0x2070,
cfb0919c
CD		 211 "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
212 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
213 fcport->d_id.b.area, fcport->d_id.b.al_pa);
ac280b67
AV		 214 return rval;
215
216done_free_sp:
9ba56b95 217 sp->free(fcport->vha, sp);
ac280b67
AV		 218done:
219 return rval;
220}
221
5ff1d584 222static void
9ba56b95 223qla2x00_async_adisc_sp_done(void *data, void *ptr, int res)
5ff1d584 224{
9ba56b95
GM		 225 srb_t *sp = (srb_t *)ptr;
226 struct srb_iocb *lio = &sp->u.iocb_cmd;
227 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
228
229 if (!test_bit(UNLOADING, &vha->dpc_flags))
230 qla2x00_post_async_adisc_done_work(sp->fcport->vha, sp->fcport,
231 lio->u.logio.data);
232 sp->free(sp->fcport->vha, sp);
5ff1d584
AV		 233}
234
235int
236qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport,
237 uint16_t *data)
238{
5ff1d584 239 srb_t *sp;
4916392b 240 struct srb_iocb *lio;
5ff1d584
AV		 241 int rval;
242
243 rval = QLA_FUNCTION_FAILED;
9ba56b95 244 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
5ff1d584
AV		 245 if (!sp)
246 goto done;
247
9ba56b95
GM		 248 sp->type = SRB_ADISC_CMD;
249 sp->name = "adisc";
250 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
251
252 lio = &sp->u.iocb_cmd;
3822263e 253 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 254 sp->done = qla2x00_async_adisc_sp_done;
5ff1d584 255 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 256 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
5ff1d584
AV		 257 rval = qla2x00_start_sp(sp);
258 if (rval != QLA_SUCCESS)
259 goto done_free_sp;
260
7c3df132 261 ql_dbg(ql_dbg_disc, vha, 0x206f,
cfb0919c
CD		 262 "Async-adisc - hdl=%x loopid=%x portid=%02x%02x%02x.\n",
263 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
264 fcport->d_id.b.area, fcport->d_id.b.al_pa);
5ff1d584
AV		 265 return rval;
266
267done_free_sp:
9ba56b95 268 sp->free(fcport->vha, sp);
5ff1d584
AV		 269done:
270 return rval;
271}
272
3822263e 273static void
9ba56b95 274qla2x00_async_tm_cmd_done(void *data, void *ptr, int res)
3822263e 275{
9ba56b95
GM		 276 srb_t *sp = (srb_t *)ptr;
277 struct srb_iocb *iocb = &sp->u.iocb_cmd;
278 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
279 uint32_t flags;
280 uint16_t lun;
281 int rval;
3822263e 282
9ba56b95
GM		 283 if (!test_bit(UNLOADING, &vha->dpc_flags)) {
284 flags = iocb->u.tmf.flags;
285 lun = (uint16_t)iocb->u.tmf.lun;
286
287 /* Issue Marker IOCB */
288 rval = qla2x00_marker(vha, vha->hw->req_q_map[0],
289 vha->hw->rsp_q_map[0], sp->fcport->loop_id, lun,
290 flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
291
292 if ((rval != QLA_SUCCESS) || iocb->u.tmf.data) {
293 ql_dbg(ql_dbg_taskm, vha, 0x8030,
294 "TM IOCB failed (%x).\n", rval);
295 }
296 }
297 sp->free(sp->fcport->vha, sp);
3822263e
MI		 298}
299
300int
9ba56b95 301qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t tm_flags, uint32_t lun,
3822263e
MI		 302 uint32_t tag)
303{
304 struct scsi_qla_host *vha = fcport->vha;
3822263e 305 srb_t *sp;
3822263e
MI		 306 struct srb_iocb *tcf;
307 int rval;
308
309 rval = QLA_FUNCTION_FAILED;
9ba56b95 310 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
3822263e
MI		 311 if (!sp)
312 goto done;
313
9ba56b95
GM		 314 sp->type = SRB_TM_CMD;
315 sp->name = "tmf";
316 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
317
318 tcf = &sp->u.iocb_cmd;
319 tcf->u.tmf.flags = tm_flags;
3822263e
MI		 320 tcf->u.tmf.lun = lun;
321 tcf->u.tmf.data = tag;
322 tcf->timeout = qla2x00_async_iocb_timeout;
9ba56b95 323 sp->done = qla2x00_async_tm_cmd_done;
3822263e
MI		 324
325 rval = qla2x00_start_sp(sp);
326 if (rval != QLA_SUCCESS)
327 goto done_free_sp;
328
7c3df132 329 ql_dbg(ql_dbg_taskm, vha, 0x802f,
cfb0919c
CD		 330 "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
331 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
332 fcport->d_id.b.area, fcport->d_id.b.al_pa);
3822263e
MI		 333 return rval;
334
335done_free_sp:
9ba56b95 336 sp->free(fcport->vha, sp);
3822263e
MI		 337done:
338 return rval;
339}
340
4916392b 341void
ac280b67
AV		 342qla2x00_async_login_done(struct scsi_qla_host *vha, fc_port_t *fcport,
343 uint16_t *data)
344{
345 int rval;
ac280b67
AV		 346
347 switch (data[0]) {
348 case MBS_COMMAND_COMPLETE:
a4f92a32
AV		 349 /*
350 * Driver must validate login state - If PRLI not complete,
351 * force a relogin attempt via implicit LOGO, PLOGI, and PRLI
352 * requests.
353 */
354 rval = qla2x00_get_port_database(vha, fcport, 0);
0eba25df
AE		 355 if (rval == QLA_NOT_LOGGED_IN) {
356 fcport->flags &= ~FCF_ASYNC_SENT;
357 fcport->flags |= FCF_LOGIN_NEEDED;
358 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
359 break;
360 }
361
a4f92a32
AV		 362 if (rval != QLA_SUCCESS) {
363 qla2x00_post_async_logout_work(vha, fcport, NULL);
364 qla2x00_post_async_login_work(vha, fcport, NULL);
365 break;
366 }
99b0bec7 367 if (fcport->flags & FCF_FCP2_DEVICE) {
5ff1d584
AV		 368 qla2x00_post_async_adisc_work(vha, fcport, data);
369 break;
99b0bec7
AV		 370 }
371 qla2x00_update_fcport(vha, fcport);
ac280b67
AV		 372 break;
373 case MBS_COMMAND_ERROR:
5ff1d584 374 fcport->flags &= ~FCF_ASYNC_SENT;
ac280b67
AV		 375 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
376 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
377 else
80d79440 378 qla2x00_mark_device_lost(vha, fcport, 1, 0);
ac280b67
AV		 379 break;
380 case MBS_PORT_ID_USED:
381 fcport->loop_id = data[1];
6ac52608 382 qla2x00_post_async_logout_work(vha, fcport, NULL);
ac280b67
AV		 383 qla2x00_post_async_login_work(vha, fcport, NULL);
384 break;
385 case MBS_LOOP_ID_USED:
386 fcport->loop_id++;
387 rval = qla2x00_find_new_loop_id(vha, fcport);
388 if (rval != QLA_SUCCESS) {
5ff1d584 389 fcport->flags &= ~FCF_ASYNC_SENT;
80d79440 390 qla2x00_mark_device_lost(vha, fcport, 1, 0);
ac280b67
AV		 391 break;
392 }
393 qla2x00_post_async_login_work(vha, fcport, NULL);
394 break;
395 }
4916392b 396 return;
ac280b67
AV		 397}
398
4916392b 399void
ac280b67
AV		 400qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport,
401 uint16_t *data)
402{
403 qla2x00_mark_device_lost(vha, fcport, 1, 0);
4916392b 404 return;
ac280b67
AV		 405}
406
4916392b 407void
5ff1d584
AV		 408qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport,
409 uint16_t *data)
410{
411 if (data[0] == MBS_COMMAND_COMPLETE) {
412 qla2x00_update_fcport(vha, fcport);
413
4916392b 414 return;
5ff1d584
AV		 415 }
416
417 /* Retry login. */
418 fcport->flags &= ~FCF_ASYNC_SENT;
419 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
420 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
421 else
80d79440 422 qla2x00_mark_device_lost(vha, fcport, 1, 0);
5ff1d584 423
4916392b 424 return;
5ff1d584
AV		 425}
426
1da177e4
LT		 427/****************************************************************************/
428/* QLogic ISP2x00 Hardware Support Functions. */
429/****************************************************************************/
430
fa492630 431static int
7d613ac6
SV		 432qla83xx_nic_core_fw_load(scsi_qla_host_t *vha)
433{
434 int rval = QLA_SUCCESS;
435 struct qla_hw_data *ha = vha->hw;
436 uint32_t idc_major_ver, idc_minor_ver;
711aa7f7 437 uint16_t config[4];
7d613ac6
SV		 438
439 qla83xx_idc_lock(vha, 0);
440
441 /* SV: TODO: Assign initialization timeout from
442 * flash-info / other param
443 */
444 ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT;
445 ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT;
446
447 /* Set our fcoe function presence */
448 if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) {
449 ql_dbg(ql_dbg_p3p, vha, 0xb077,
450 "Error while setting DRV-Presence.\n");
451 rval = QLA_FUNCTION_FAILED;
452 goto exit;
453 }
454
455 /* Decide the reset ownership */
456 qla83xx_reset_ownership(vha);
457
458 /*
459 * On first protocol driver load:
460 * Init-Owner: Set IDC-Major-Version and Clear IDC-Lock-Recovery
461 * register.
462 * Others: Check compatibility with current IDC Major version.
463 */
464 qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver);
465 if (ha->flags.nic_core_reset_owner) {
466 /* Set IDC Major version */
467 idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION;
468 qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver);
469
470 /* Clearing IDC-Lock-Recovery register */
471 qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0);
472 } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) {
473 /*
474 * Clear further IDC participation if we are not compatible with
475 * the current IDC Major Version.
476 */
477 ql_log(ql_log_warn, vha, 0xb07d,
478 "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n",
479 idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION);
480 __qla83xx_clear_drv_presence(vha);
481 rval = QLA_FUNCTION_FAILED;
482 goto exit;
483 }
484 /* Each function sets its supported Minor version. */
485 qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver);
486 idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2));
487 qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver);
488
711aa7f7
SK		 489 if (ha->flags.nic_core_reset_owner) {
490 memset(config, 0, sizeof(config));
491 if (!qla81xx_get_port_config(vha, config))
492 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
493 QLA8XXX_DEV_READY);
494 }
495
7d613ac6
SV		 496 rval = qla83xx_idc_state_handler(vha);
497
498exit:
499 qla83xx_idc_unlock(vha, 0);
500
501 return rval;
502}
503
1da177e4
LT		 504/*
505* qla2x00_initialize_adapter
506* Initialize board.
507*
508* Input:
509* ha = adapter block pointer.
510*
511* Returns:
512* 0 = success
513*/
514int
e315cd28 515qla2x00_initialize_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 516{
517 int rval;
e315cd28 518 struct qla_hw_data *ha = vha->hw;
73208dfd 519 struct req_que *req = ha->req_q_map[0];
2533cf67 520
1da177e4 521 /* Clear adapter flags. */
e315cd28 522 vha->flags.online = 0;
2533cf67 523 ha->flags.chip_reset_done = 0;
e315cd28 524 vha->flags.reset_active = 0;
85880801
AV		 525 ha->flags.pci_channel_io_perm_failure = 0;
526 ha->flags.eeh_busy = 0;
fabbb8df 527 vha->qla_stats.jiffies_at_last_reset = get_jiffies_64();
e315cd28
AC		 528 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
529 atomic_set(&vha->loop_state, LOOP_DOWN);
530 vha->device_flags = DFLG_NO_CABLE;
531 vha->dpc_flags = 0;
532 vha->flags.management_server_logged_in = 0;
533 vha->marker_needed = 0;
1da177e4
LT		 534 ha->isp_abort_cnt = 0;
535 ha->beacon_blink_led = 0;
536
73208dfd
AC		 537 set_bit(0, ha->req_qid_map);
538 set_bit(0, ha->rsp_qid_map);
539
cfb0919c 540 ql_dbg(ql_dbg_init, vha, 0x0040,
7c3df132 541 "Configuring PCI space...\n");
e315cd28 542 rval = ha->isp_ops->pci_config(vha);
1da177e4 543 if (rval) {
7c3df132
SK		 544 ql_log(ql_log_warn, vha, 0x0044,
545 "Unable to configure PCI space.\n");
1da177e4
LT		 546 return (rval);
547 }
548
e315cd28 549 ha->isp_ops->reset_chip(vha);
1da177e4 550
e315cd28 551 rval = qla2xxx_get_flash_info(vha);
c00d8994 552 if (rval) {
7c3df132
SK		 553 ql_log(ql_log_fatal, vha, 0x004f,
554 "Unable to validate FLASH data.\n");
7ec0effd
AD		 555 return rval;
556 }
557
558 if (IS_QLA8044(ha)) {
559 qla8044_read_reset_template(vha);
560
561 /* NOTE: If ql2xdontresethba==1, set IDC_CTRL DONTRESET_BIT0.
562 * If DONRESET_BIT0 is set, drivers should not set dev_state
563 * to NEED_RESET. But if NEED_RESET is set, drivers should
564 * should honor the reset. */
565 if (ql2xdontresethba == 1)
566 qla8044_set_idc_dontreset(vha);
c00d8994
AV		 567 }
568
73208dfd 569 ha->isp_ops->get_flash_version(vha, req->ring);
cfb0919c 570 ql_dbg(ql_dbg_init, vha, 0x0061,
7c3df132 571 "Configure NVRAM parameters...\n");
0107109e 572
e315cd28 573 ha->isp_ops->nvram_config(vha);
1da177e4 574
d4c760c2
AV		 575 if (ha->flags.disable_serdes) {
576 /* Mask HBA via NVRAM settings? */
7c3df132 577 ql_log(ql_log_info, vha, 0x0077,
7b833558 578 "Masking HBA WWPN %8phN (via NVRAM).\n", vha->port_name);
d4c760c2
AV		 579 return QLA_FUNCTION_FAILED;
580 }
581
cfb0919c 582 ql_dbg(ql_dbg_init, vha, 0x0078,
7c3df132 583 "Verifying loaded RISC code...\n");
1da177e4 584
e315cd28
AC		 585 if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) {
586 rval = ha->isp_ops->chip_diag(vha);
d19044c3
AV		 587 if (rval)
588 return (rval);
e315cd28 589 rval = qla2x00_setup_chip(vha);
d19044c3
AV		 590 if (rval)
591 return (rval);
1da177e4 592 }
a9083016 593
4d4df193 594 if (IS_QLA84XX(ha)) {
e315cd28 595 ha->cs84xx = qla84xx_get_chip(vha);
4d4df193 596 if (!ha->cs84xx) {
7c3df132 597 ql_log(ql_log_warn, vha, 0x00d0,
4d4df193
HK		 598 "Unable to configure ISP84XX.\n");
599 return QLA_FUNCTION_FAILED;
600 }
601 }
2d70c103
NB		 602
603 if (qla_ini_mode_enabled(vha))
604 rval = qla2x00_init_rings(vha);
605
2533cf67 606 ha->flags.chip_reset_done = 1;
1da177e4 607
9a069e19 608 if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) {
6c452a45 609 /* Issue verify 84xx FW IOCB to complete 84xx initialization */
9a069e19
GM		 610 rval = qla84xx_init_chip(vha);
611 if (rval != QLA_SUCCESS) {
7c3df132
SK		 612 ql_log(ql_log_warn, vha, 0x00d4,
613 "Unable to initialize ISP84XX.\n");
9a069e19
GM		 614 qla84xx_put_chip(vha);
615 }
616 }
617
7d613ac6
SV		 618 /* Load the NIC Core f/w if we are the first protocol driver. */
619 if (IS_QLA8031(ha)) {
620 rval = qla83xx_nic_core_fw_load(vha);
621 if (rval)
622 ql_log(ql_log_warn, vha, 0x0124,
623 "Error in initializing NIC Core f/w.\n");
624 }
625
2f0f3f4f
MI		 626 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
627 qla24xx_read_fcp_prio_cfg(vha);
09ff701a 628
c46e65c7
JC		 629 if (IS_P3P_TYPE(ha))
630 qla82xx_set_driver_version(vha, QLA2XXX_VERSION);
631 else
632 qla25xx_set_driver_version(vha, QLA2XXX_VERSION);
633
1da177e4
LT		 634 return (rval);
635}
636
637/**
abbd8870 638 * qla2100_pci_config() - Setup ISP21xx PCI configuration registers.
1da177e4
LT		 639 * @ha: HA context
640 *
641 * Returns 0 on success.
642 */
abbd8870 643int
e315cd28 644qla2100_pci_config(scsi_qla_host_t *vha)
1da177e4 645{
a157b101 646 uint16_t w;
abbd8870 647 unsigned long flags;
e315cd28 648 struct qla_hw_data *ha = vha->hw;
3d71644c 649 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 650
1da177e4 651 pci_set_master(ha->pdev);
af6177d8 652 pci_try_set_mwi(ha->pdev);
1da177e4 653
1da177e4 654 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 655 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
abbd8870
AV		 656 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
657
737faece 658 pci_disable_rom(ha->pdev);
1da177e4
LT		 659
660 /* Get PCI bus information. */
661 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 662 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
1da177e4
LT		 663 spin_unlock_irqrestore(&ha->hardware_lock, flags);
664
abbd8870
AV		 665 return QLA_SUCCESS;
666}
1da177e4 667
abbd8870
AV		 668/**
669 * qla2300_pci_config() - Setup ISP23xx PCI configuration registers.
670 * @ha: HA context
671 *
672 * Returns 0 on success.
673 */
674int
e315cd28 675qla2300_pci_config(scsi_qla_host_t *vha)
abbd8870 676{
a157b101 677 uint16_t w;
abbd8870
AV		 678 unsigned long flags = 0;
679 uint32_t cnt;
e315cd28 680 struct qla_hw_data *ha = vha->hw;
3d71644c 681 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 682
abbd8870 683 pci_set_master(ha->pdev);
af6177d8 684 pci_try_set_mwi(ha->pdev);
1da177e4 685
abbd8870 686 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 687 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
1da177e4 688
abbd8870
AV		 689 if (IS_QLA2322(ha) || IS_QLA6322(ha))
690 w &= ~PCI_COMMAND_INTX_DISABLE;
a157b101 691 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1da177e4 692
abbd8870
AV		 693 /*
694 * If this is a 2300 card and not 2312, reset the
695 * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately,
696 * the 2310 also reports itself as a 2300 so we need to get the
697 * fb revision level -- a 6 indicates it really is a 2300 and
698 * not a 2310.
699 */
700 if (IS_QLA2300(ha)) {
701 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 702
abbd8870 703 /* Pause RISC. */
3d71644c 704 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
abbd8870 705 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 706 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
abbd8870 707 break;
1da177e4 708
abbd8870
AV		 709 udelay(10);
710 }
1da177e4 711
abbd8870 712 /* Select FPM registers. */
3d71644c
AV		 713 WRT_REG_WORD(&reg->ctrl_status, 0x20);
714 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 715
716 /* Get the fb rev level */
3d71644c 717 ha->fb_rev = RD_FB_CMD_REG(ha, reg);
abbd8870
AV		 718
719 if (ha->fb_rev == FPM_2300)
a157b101 720 pci_clear_mwi(ha->pdev);
abbd8870
AV		 721
722 /* Deselect FPM registers. */
3d71644c
AV		 723 WRT_REG_WORD(&reg->ctrl_status, 0x0);
724 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 725
726 /* Release RISC module. */
3d71644c 727 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
abbd8870 728 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 729 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0)
abbd8870
AV		 730 break;
731
732 udelay(10);
1da177e4 733 }
1da177e4 734
abbd8870
AV		 735 spin_unlock_irqrestore(&ha->hardware_lock, flags);
736 }
1da177e4 737
abbd8870
AV		 738 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
739
737faece 740 pci_disable_rom(ha->pdev);
1da177e4 741
abbd8870
AV		 742 /* Get PCI bus information. */
743 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 744 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 745 spin_unlock_irqrestore(&ha->hardware_lock, flags);
746
747 return QLA_SUCCESS;
1da177e4
LT		 748}
749
0107109e
AV		 750/**
751 * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers.
752 * @ha: HA context
753 *
754 * Returns 0 on success.
755 */
756int
e315cd28 757qla24xx_pci_config(scsi_qla_host_t *vha)
0107109e 758{
a157b101 759 uint16_t w;
0107109e 760 unsigned long flags = 0;
e315cd28 761 struct qla_hw_data *ha = vha->hw;
0107109e 762 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
0107109e
AV		 763
764 pci_set_master(ha->pdev);
af6177d8 765 pci_try_set_mwi(ha->pdev);
0107109e
AV		 766
767 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 768 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
0107109e
AV		 769 w &= ~PCI_COMMAND_INTX_DISABLE;
770 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
771
772 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
773
774 /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */
f85ec187
AV		 775 if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
776 pcix_set_mmrbc(ha->pdev, 2048);
0107109e
AV		 777
778 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 779 if (pci_is_pcie(ha->pdev))
5ffd3a52 780 pcie_set_readrq(ha->pdev, 4096);
0107109e 781
737faece 782 pci_disable_rom(ha->pdev);
0107109e 783
44c10138 784 ha->chip_revision = ha->pdev->revision;
a8488abe 785
0107109e
AV		 786 /* Get PCI bus information. */
787 spin_lock_irqsave(&ha->hardware_lock, flags);
788 ha->pci_attr = RD_REG_DWORD(&reg->ctrl_status);
789 spin_unlock_irqrestore(&ha->hardware_lock, flags);
790
791 return QLA_SUCCESS;
792}
793
c3a2f0df
AV		 794/**
795 * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers.
796 * @ha: HA context
797 *
798 * Returns 0 on success.
799 */
800int
e315cd28 801qla25xx_pci_config(scsi_qla_host_t *vha)
c3a2f0df
AV		 802{
803 uint16_t w;
e315cd28 804 struct qla_hw_data *ha = vha->hw;
c3a2f0df
AV		 805
806 pci_set_master(ha->pdev);
807 pci_try_set_mwi(ha->pdev);
808
809 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
810 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
811 w &= ~PCI_COMMAND_INTX_DISABLE;
812 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
813
814 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 815 if (pci_is_pcie(ha->pdev))
5ffd3a52 816 pcie_set_readrq(ha->pdev, 4096);
c3a2f0df 817
737faece 818 pci_disable_rom(ha->pdev);
c3a2f0df
AV		 819
820 ha->chip_revision = ha->pdev->revision;
821
822 return QLA_SUCCESS;
823}
824
1da177e4
LT		 825/**
826 * qla2x00_isp_firmware() - Choose firmware image.
827 * @ha: HA context
828 *
829 * Returns 0 on success.
830 */
831static int
e315cd28 832qla2x00_isp_firmware(scsi_qla_host_t *vha)
1da177e4
LT		 833{
834 int rval;
42e421b1
AV		 835 uint16_t loop_id, topo, sw_cap;
836 uint8_t domain, area, al_pa;
e315cd28 837 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 838
839 /* Assume loading risc code */
fa2a1ce5 840 rval = QLA_FUNCTION_FAILED;
1da177e4
LT		 841
842 if (ha->flags.disable_risc_code_load) {
7c3df132 843 ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n");
1da177e4
LT		 844
845 /* Verify checksum of loaded RISC code. */
e315cd28 846 rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address);
42e421b1
AV		 847 if (rval == QLA_SUCCESS) {
848 /* And, verify we are not in ROM code. */
e315cd28 849 rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa,
42e421b1
AV		 850 &area, &domain, &topo, &sw_cap);
851 }
1da177e4
LT		 852 }
853
7c3df132
SK		 854 if (rval)
855 ql_dbg(ql_dbg_init, vha, 0x007a,
856 "**** Load RISC code ****.\n");
1da177e4
LT		 857
858 return (rval);
859}
860
861/**
862 * qla2x00_reset_chip() - Reset ISP chip.
863 * @ha: HA context
864 *
865 * Returns 0 on success.
866 */
abbd8870 867void
e315cd28 868qla2x00_reset_chip(scsi_qla_host_t *vha)
1da177e4
LT		 869{
870 unsigned long flags = 0;
e315cd28 871 struct qla_hw_data *ha = vha->hw;
3d71644c 872 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 873 uint32_t cnt;
1da177e4
LT		 874 uint16_t cmd;
875
85880801
AV		 876 if (unlikely(pci_channel_offline(ha->pdev)))
877 return;
878
fd34f556 879 ha->isp_ops->disable_intrs(ha);
1da177e4
LT		 880
881 spin_lock_irqsave(&ha->hardware_lock, flags);
882
883 /* Turn off master enable */
884 cmd = 0;
885 pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd);
886 cmd &= ~PCI_COMMAND_MASTER;
887 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
888
889 if (!IS_QLA2100(ha)) {
890 /* Pause RISC. */
891 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
892 if (IS_QLA2200(ha) || IS_QLA2300(ha)) {
893 for (cnt = 0; cnt < 30000; cnt++) {
894 if ((RD_REG_WORD(&reg->hccr) &
895 HCCR_RISC_PAUSE) != 0)
896 break;
897 udelay(100);
898 }
899 } else {
900 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
901 udelay(10);
902 }
903
904 /* Select FPM registers. */
905 WRT_REG_WORD(&reg->ctrl_status, 0x20);
906 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
907
908 /* FPM Soft Reset. */
909 WRT_REG_WORD(&reg->fpm_diag_config, 0x100);
910 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
911
912 /* Toggle Fpm Reset. */
913 if (!IS_QLA2200(ha)) {
914 WRT_REG_WORD(&reg->fpm_diag_config, 0x0);
915 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
916 }
917
918 /* Select frame buffer registers. */
919 WRT_REG_WORD(&reg->ctrl_status, 0x10);
920 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
921
922 /* Reset frame buffer FIFOs. */
923 if (IS_QLA2200(ha)) {
924 WRT_FB_CMD_REG(ha, reg, 0xa000);
925 RD_FB_CMD_REG(ha, reg); /* PCI Posting. */
926 } else {
927 WRT_FB_CMD_REG(ha, reg, 0x00fc);
928
929 /* Read back fb_cmd until zero or 3 seconds max */
930 for (cnt = 0; cnt < 3000; cnt++) {
931 if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0)
932 break;
933 udelay(100);
934 }
935 }
936
937 /* Select RISC module registers. */
938 WRT_REG_WORD(&reg->ctrl_status, 0);
939 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
940
941 /* Reset RISC processor. */
942 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
943 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
944
945 /* Release RISC processor. */
946 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
947 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
948 }
949
950 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
951 WRT_REG_WORD(&reg->hccr, HCCR_CLR_HOST_INT);
952
953 /* Reset ISP chip. */
954 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
955
956 /* Wait for RISC to recover from reset. */
957 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
958 /*
959 * It is necessary to for a delay here since the card doesn't
960 * respond to PCI reads during a reset. On some architectures
961 * this will result in an MCA.
962 */
963 udelay(20);
964 for (cnt = 30000; cnt; cnt--) {
965 if ((RD_REG_WORD(&reg->ctrl_status) &
966 CSR_ISP_SOFT_RESET) == 0)
967 break;
968 udelay(100);
969 }
970 } else
971 udelay(10);
972
973 /* Reset RISC processor. */
974 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
975
976 WRT_REG_WORD(&reg->semaphore, 0);
977
978 /* Release RISC processor. */
979 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
980 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
981
982 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
983 for (cnt = 0; cnt < 30000; cnt++) {
ffb39f03 984 if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY)
1da177e4 985 break;
1da177e4
LT		 986
987 udelay(100);
988 }
989 } else
990 udelay(100);
991
992 /* Turn on master enable */
993 cmd |= PCI_COMMAND_MASTER;
994 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
995
996 /* Disable RISC pause on FPM parity error. */
997 if (!IS_QLA2100(ha)) {
998 WRT_REG_WORD(&reg->hccr, HCCR_DISABLE_PARITY_PAUSE);
999 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1000 }
1001
1002 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1003}
1004
b1d46989
MI		 1005/**
1006 * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC.
1007 *
1008 * Returns 0 on success.
1009 */
fa492630 1010static int
b1d46989
MI		 1011qla81xx_reset_mpi(scsi_qla_host_t *vha)
1012{
1013 uint16_t mb[4] = {0x1010, 0, 1, 0};
1014
6246b8a1
GM		 1015 if (!IS_QLA81XX(vha->hw))
1016 return QLA_SUCCESS;
1017
b1d46989
MI		 1018 return qla81xx_write_mpi_register(vha, mb);
1019}
1020
0107109e 1021/**
88c26663 1022 * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC.
0107109e
AV		 1023 * @ha: HA context
1024 *
1025 * Returns 0 on success.
1026 */
88c26663 1027static inline void
e315cd28 1028qla24xx_reset_risc(scsi_qla_host_t *vha)
0107109e
AV		 1029{
1030 unsigned long flags = 0;
e315cd28 1031 struct qla_hw_data *ha = vha->hw;
0107109e
AV		 1032 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1033 uint32_t cnt, d2;
335a1cc9 1034 uint16_t wd;
b1d46989 1035 static int abts_cnt; /* ISP abort retry counts */
0107109e 1036
0107109e
AV		 1037 spin_lock_irqsave(&ha->hardware_lock, flags);
1038
1039 /* Reset RISC. */
1040 WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
1041 for (cnt = 0; cnt < 30000; cnt++) {
1042 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
1043 break;
1044
1045 udelay(10);
1046 }
1047
1048 WRT_REG_DWORD(&reg->ctrl_status,
1049 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
335a1cc9 1050 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
88c26663 1051
335a1cc9 1052 udelay(100);
88c26663 1053 /* Wait for firmware to complete NVRAM accesses. */
88c26663
AV		 1054 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1055 for (cnt = 10000 ; cnt && d2; cnt--) {
1056 udelay(5);
1057 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1058 barrier();
1059 }
1060
335a1cc9 1061 /* Wait for soft-reset to complete. */
0107109e
AV		 1062 d2 = RD_REG_DWORD(&reg->ctrl_status);
1063 for (cnt = 6000000 ; cnt && (d2 & CSRX_ISP_SOFT_RESET); cnt--) {
1064 udelay(5);
1065 d2 = RD_REG_DWORD(&reg->ctrl_status);
1066 barrier();
1067 }
1068
b1d46989
MI		 1069 /* If required, do an MPI FW reset now */
1070 if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
1071 if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
1072 if (++abts_cnt < 5) {
1073 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1074 set_bit(MPI_RESET_NEEDED, &vha->dpc_flags);
1075 } else {
1076 /*
1077 * We exhausted the ISP abort retries. We have to
1078 * set the board offline.
1079 */
1080 abts_cnt = 0;
1081 vha->flags.online = 0;
1082 }
1083 }
1084 }
1085
0107109e
AV		 1086 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
1087 RD_REG_DWORD(&reg->hccr);
1088
1089 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
1090 RD_REG_DWORD(&reg->hccr);
1091
1092 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
1093 RD_REG_DWORD(&reg->hccr);
1094
1095 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1096 for (cnt = 6000000 ; cnt && d2; cnt--) {
1097 udelay(5);
1098 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1099 barrier();
1100 }
1101
1102 spin_unlock_irqrestore(&ha->hardware_lock, flags);
124f85e6
AV		 1103
1104 if (IS_NOPOLLING_TYPE(ha))
1105 ha->isp_ops->enable_intrs(ha);
0107109e
AV		 1106}
1107
4ea2c9c7
JC		 1108static void
1109qla25xx_read_risc_sema_reg(scsi_qla_host_t *vha, uint32_t *data)
1110{
1111 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
1112
1113 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
1114 *data = RD_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET);
1115
1116}
1117
1118static void
1119qla25xx_write_risc_sema_reg(scsi_qla_host_t *vha, uint32_t data)
1120{
1121 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
1122
1123 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
1124 WRT_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET, data);
1125}
1126
1127static void
1128qla25xx_manipulate_risc_semaphore(scsi_qla_host_t *vha)
1129{
1130 struct qla_hw_data *ha = vha->hw;
1131 uint32_t wd32 = 0;
1132 uint delta_msec = 100;
1133 uint elapsed_msec = 0;
1134 uint timeout_msec;
1135 ulong n;
1136
1137 if (!IS_QLA25XX(ha) && !IS_QLA2031(ha))
1138 return;
1139
1140attempt:
1141 timeout_msec = TIMEOUT_SEMAPHORE;
1142 n = timeout_msec / delta_msec;
1143 while (n--) {
1144 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_SET);
1145 qla25xx_read_risc_sema_reg(vha, &wd32);
1146 if (wd32 & RISC_SEMAPHORE)
1147 break;
1148 msleep(delta_msec);
1149 elapsed_msec += delta_msec;
1150 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
1151 goto force;
1152 }
1153
1154 if (!(wd32 & RISC_SEMAPHORE))
1155 goto force;
1156
1157 if (!(wd32 & RISC_SEMAPHORE_FORCE))
1158 goto acquired;
1159
1160 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_CLR);
1161 timeout_msec = TIMEOUT_SEMAPHORE_FORCE;
1162 n = timeout_msec / delta_msec;
1163 while (n--) {
1164 qla25xx_read_risc_sema_reg(vha, &wd32);
1165 if (!(wd32 & RISC_SEMAPHORE_FORCE))
1166 break;
1167 msleep(delta_msec);
1168 elapsed_msec += delta_msec;
1169 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
1170 goto force;
1171 }
1172
1173 if (wd32 & RISC_SEMAPHORE_FORCE)
1174 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_CLR);
1175
1176 goto attempt;
1177
1178force:
1179 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_SET);
1180
1181acquired:
1182 return;
1183}
1184
88c26663
AV		 1185/**
1186 * qla24xx_reset_chip() - Reset ISP24xx chip.
1187 * @ha: HA context
1188 *
1189 * Returns 0 on success.
1190 */
1191void
e315cd28 1192qla24xx_reset_chip(scsi_qla_host_t *vha)
88c26663 1193{
e315cd28 1194 struct qla_hw_data *ha = vha->hw;
85880801
AV		 1195
1196 if (pci_channel_offline(ha->pdev) &&
1197 ha->flags.pci_channel_io_perm_failure) {
1198 return;
1199 }
1200
fd34f556 1201 ha->isp_ops->disable_intrs(ha);
88c26663 1202
4ea2c9c7
JC		 1203 qla25xx_manipulate_risc_semaphore(vha);
1204
88c26663 1205 /* Perform RISC reset. */
e315cd28 1206 qla24xx_reset_risc(vha);
88c26663
AV		 1207}
1208
1da177e4
LT		 1209/**
1210 * qla2x00_chip_diag() - Test chip for proper operation.
1211 * @ha: HA context
1212 *
1213 * Returns 0 on success.
1214 */
abbd8870 1215int
e315cd28 1216qla2x00_chip_diag(scsi_qla_host_t *vha)
1da177e4
LT		 1217{
1218 int rval;
e315cd28 1219 struct qla_hw_data *ha = vha->hw;
3d71644c 1220 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 1221 unsigned long flags = 0;
1222 uint16_t data;
1223 uint32_t cnt;
1224 uint16_t mb[5];
73208dfd 1225 struct req_que *req = ha->req_q_map[0];
1da177e4
LT		 1226
1227 /* Assume a failed state */
1228 rval = QLA_FUNCTION_FAILED;
1229
7c3df132
SK		 1230 ql_dbg(ql_dbg_init, vha, 0x007b,
1231 "Testing device at %lx.\n", (u_long)&reg->flash_address);
1da177e4
LT		 1232
1233 spin_lock_irqsave(&ha->hardware_lock, flags);
1234
1235 /* Reset ISP chip. */
1236 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1237
1238 /*
1239 * We need to have a delay here since the card will not respond while
1240 * in reset causing an MCA on some architectures.
1241 */
1242 udelay(20);
1243 data = qla2x00_debounce_register(&reg->ctrl_status);
1244 for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {
1245 udelay(5);
1246 data = RD_REG_WORD(&reg->ctrl_status);
1247 barrier();
1248 }
1249
1250 if (!cnt)
1251 goto chip_diag_failed;
1252
7c3df132
SK		 1253 ql_dbg(ql_dbg_init, vha, 0x007c,
1254 "Reset register cleared by chip reset.\n");
1da177e4
LT		 1255
1256 /* Reset RISC processor. */
1257 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
1258 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
1259
1260 /* Workaround for QLA2312 PCI parity error */
1261 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1262 data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0));
1263 for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) {
1264 udelay(5);
1265 data = RD_MAILBOX_REG(ha, reg, 0);
fa2a1ce5 1266 barrier();
1da177e4
LT		 1267 }
1268 } else
1269 udelay(10);
1270
1271 if (!cnt)
1272 goto chip_diag_failed;
1273
1274 /* Check product ID of chip */
7c3df132 1275 ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product Id of chip.\n");
1da177e4
LT		 1276
1277 mb[1] = RD_MAILBOX_REG(ha, reg, 1);
1278 mb[2] = RD_MAILBOX_REG(ha, reg, 2);
1279 mb[3] = RD_MAILBOX_REG(ha, reg, 3);
1280 mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4));
1281 if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) ||
1282 mb[3] != PROD_ID_3) {
7c3df132
SK		 1283 ql_log(ql_log_warn, vha, 0x0062,
1284 "Wrong product ID = 0x%x,0x%x,0x%x.\n",
1285 mb[1], mb[2], mb[3]);
1da177e4
LT		 1286
1287 goto chip_diag_failed;
1288 }
1289 ha->product_id[0] = mb[1];
1290 ha->product_id[1] = mb[2];
1291 ha->product_id[2] = mb[3];
1292 ha->product_id[3] = mb[4];
1293
1294 /* Adjust fw RISC transfer size */
73208dfd 1295 if (req->length > 1024)
1da177e4
LT		 1296 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024;
1297 else
1298 ha->fw_transfer_size = REQUEST_ENTRY_SIZE *
73208dfd 1299 req->length;
1da177e4
LT		 1300
1301 if (IS_QLA2200(ha) &&
1302 RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) {
1303 /* Limit firmware transfer size with a 2200A */
7c3df132 1304 ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n");
1da177e4 1305
ea5b6382 1306 ha->device_type |= DT_ISP2200A;
1da177e4
LT		 1307 ha->fw_transfer_size = 128;
1308 }
1309
1310 /* Wrap Incoming Mailboxes Test. */
1311 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1312
7c3df132 1313 ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n");
e315cd28 1314 rval = qla2x00_mbx_reg_test(vha);
7c3df132
SK		 1315 if (rval)
1316 ql_log(ql_log_warn, vha, 0x0080,
1317 "Failed mailbox send register test.\n");
1318 else
1da177e4
LT		 1319 /* Flag a successful rval */
1320 rval = QLA_SUCCESS;
1da177e4
LT		 1321 spin_lock_irqsave(&ha->hardware_lock, flags);
1322
1323chip_diag_failed:
1324 if (rval)
7c3df132
SK		 1325 ql_log(ql_log_info, vha, 0x0081,
1326 "Chip diagnostics **** FAILED ****.\n");
1da177e4
LT		 1327
1328 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1329
1330 return (rval);
1331}
1332
0107109e
AV		 1333/**
1334 * qla24xx_chip_diag() - Test ISP24xx for proper operation.
1335 * @ha: HA context
1336 *
1337 * Returns 0 on success.
1338 */
1339int
e315cd28 1340qla24xx_chip_diag(scsi_qla_host_t *vha)
0107109e
AV		 1341{
1342 int rval;
e315cd28 1343 struct qla_hw_data *ha = vha->hw;
73208dfd 1344 struct req_que *req = ha->req_q_map[0];
0107109e 1345
7ec0effd 1346 if (IS_P3P_TYPE(ha))
a9083016
GM		 1347 return QLA_SUCCESS;
1348
73208dfd 1349 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
0107109e 1350
e315cd28 1351 rval = qla2x00_mbx_reg_test(vha);
0107109e 1352 if (rval) {
7c3df132
SK		 1353 ql_log(ql_log_warn, vha, 0x0082,
1354 "Failed mailbox send register test.\n");
0107109e
AV		 1355 } else {
1356 /* Flag a successful rval */
1357 rval = QLA_SUCCESS;
1358 }
1359
1360 return rval;
1361}
1362
a7a167bf 1363void
e315cd28 1364qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
0107109e 1365{
a7a167bf
AV		 1366 int rval;
1367 uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
73208dfd 1368 eft_size, fce_size, mq_size;
df613b96
AV		 1369 dma_addr_t tc_dma;
1370 void *tc;
e315cd28 1371 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 1372 struct req_que *req = ha->req_q_map[0];
1373 struct rsp_que *rsp = ha->rsp_q_map[0];
a7a167bf
AV		 1374
1375 if (ha->fw_dump) {
7c3df132
SK		 1376 ql_dbg(ql_dbg_init, vha, 0x00bd,
1377 "Firmware dump already allocated.\n");
a7a167bf
AV		 1378 return;
1379 }
d4e3e04d 1380
0107109e 1381 ha->fw_dumped = 0;
f73cb695
CD		 1382 dump_size = fixed_size = mem_size = eft_size = fce_size = mq_size = 0;
1383 req_q_size = rsp_q_size = 0;
1384
1385 if (IS_QLA27XX(ha))
1386 goto try_fce;
1387
d4e3e04d 1388 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
a7a167bf 1389 fixed_size = sizeof(struct qla2100_fw_dump);
d4e3e04d 1390 } else if (IS_QLA23XX(ha)) {
a7a167bf
AV		 1391 fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
1392 mem_size = (ha->fw_memory_size - 0x11000 + 1) *
1393 sizeof(uint16_t);
e428924c 1394 } else if (IS_FWI2_CAPABLE(ha)) {
6246b8a1
GM		 1395 if (IS_QLA83XX(ha))
1396 fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem);
1397 else if (IS_QLA81XX(ha))
3a03eb79
AV		 1398 fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
1399 else if (IS_QLA25XX(ha))
1400 fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
1401 else
1402 fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
f73cb695 1403
a7a167bf
AV		 1404 mem_size = (ha->fw_memory_size - 0x100000 + 1) *
1405 sizeof(uint32_t);
050c9bb1 1406 if (ha->mqenable) {
6246b8a1
GM		 1407 if (!IS_QLA83XX(ha))
1408 mq_size = sizeof(struct qla2xxx_mq_chain);
050c9bb1
GM		 1409 /*
1410 * Allocate maximum buffer size for all queues.
1411 * Resizing must be done at end-of-dump processing.
1412 */
1413 mq_size += ha->max_req_queues *
1414 (req->length * sizeof(request_t));
1415 mq_size += ha->max_rsp_queues *
1416 (rsp->length * sizeof(response_t));
1417 }
00876ae8 1418 if (ha->tgt.atio_ring)
2d70c103 1419 mq_size += ha->tgt.atio_q_length * sizeof(request_t);
df613b96 1420 /* Allocate memory for Fibre Channel Event Buffer. */
f73cb695
CD		 1421 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
1422 !IS_QLA27XX(ha))
436a7b11 1423 goto try_eft;
df613b96 1424
f73cb695
CD		 1425try_fce:
1426 if (ha->fce)
1427 dma_free_coherent(&ha->pdev->dev,
1428 FCE_SIZE, ha->fce, ha->fce_dma);
1429
1430 /* Allocate memory for Fibre Channel Event Buffer. */
df613b96
AV		 1431 tc = dma_alloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
1432 GFP_KERNEL);
1433 if (!tc) {
7c3df132
SK		 1434 ql_log(ql_log_warn, vha, 0x00be,
1435 "Unable to allocate (%d KB) for FCE.\n",
1436 FCE_SIZE / 1024);
17d98630 1437 goto try_eft;
df613b96
AV		 1438 }
1439
1440 memset(tc, 0, FCE_SIZE);
e315cd28 1441 rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS,
df613b96
AV		 1442 ha->fce_mb, &ha->fce_bufs);
1443 if (rval) {
7c3df132
SK		 1444 ql_log(ql_log_warn, vha, 0x00bf,
1445 "Unable to initialize FCE (%d).\n", rval);
df613b96
AV		 1446 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc,
1447 tc_dma);
1448 ha->flags.fce_enabled = 0;
17d98630 1449 goto try_eft;
df613b96 1450 }
cfb0919c 1451 ql_dbg(ql_dbg_init, vha, 0x00c0,
7c3df132 1452 "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024);
df613b96 1453
7d9dade3 1454 fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE;
df613b96
AV		 1455 ha->flags.fce_enabled = 1;
1456 ha->fce_dma = tc_dma;
1457 ha->fce = tc;
f73cb695 1458
436a7b11 1459try_eft:
f73cb695
CD		 1460 if (ha->eft)
1461 dma_free_coherent(&ha->pdev->dev,
1462 EFT_SIZE, ha->eft, ha->eft_dma);
1463
436a7b11
AV		 1464 /* Allocate memory for Extended Trace Buffer. */
1465 tc = dma_alloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
1466 GFP_KERNEL);
1467 if (!tc) {
7c3df132
SK		 1468 ql_log(ql_log_warn, vha, 0x00c1,
1469 "Unable to allocate (%d KB) for EFT.\n",
1470 EFT_SIZE / 1024);
436a7b11
AV		 1471 goto cont_alloc;
1472 }
1473
1474 memset(tc, 0, EFT_SIZE);
e315cd28 1475 rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
436a7b11 1476 if (rval) {
7c3df132
SK		 1477 ql_log(ql_log_warn, vha, 0x00c2,
1478 "Unable to initialize EFT (%d).\n", rval);
436a7b11
AV		 1479 dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc,
1480 tc_dma);
1481 goto cont_alloc;
1482 }
cfb0919c 1483 ql_dbg(ql_dbg_init, vha, 0x00c3,
7c3df132 1484 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
436a7b11
AV		 1485
1486 eft_size = EFT_SIZE;
1487 ha->eft_dma = tc_dma;
1488 ha->eft = tc;
d4e3e04d 1489 }
f73cb695 1490
a7a167bf 1491cont_alloc:
f73cb695
CD		 1492 if (IS_QLA27XX(ha)) {
1493 if (!ha->fw_dump_template) {
1494 ql_log(ql_log_warn, vha, 0x00ba,
1495 "Failed missing fwdump template\n");
1496 return;
1497 }
1498 dump_size = qla27xx_fwdt_calculate_dump_size(vha);
1499 ql_dbg(ql_dbg_init, vha, 0x00fa,
1500 "-> allocating fwdump (%x bytes)...\n", dump_size);
1501 goto allocate;
1502 }
1503
73208dfd
AC		 1504 req_q_size = req->length * sizeof(request_t);
1505 rsp_q_size = rsp->length * sizeof(response_t);
a7a167bf 1506 dump_size = offsetof(struct qla2xxx_fw_dump, isp);
2afa19a9 1507 dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size;
bb99de67
AV		 1508 ha->chain_offset = dump_size;
1509 dump_size += mq_size + fce_size;
d4e3e04d 1510
f73cb695 1511allocate:
d4e3e04d 1512 ha->fw_dump = vmalloc(dump_size);
a7a167bf 1513 if (!ha->fw_dump) {
7c3df132
SK		 1514 ql_log(ql_log_warn, vha, 0x00c4,
1515 "Unable to allocate (%d KB) for firmware dump.\n",
1516 dump_size / 1024);
a7a167bf 1517
e30d1756
MI		 1518 if (ha->fce) {
1519 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
1520 ha->fce_dma);
1521 ha->fce = NULL;
1522 ha->fce_dma = 0;
1523 }
1524
a7a167bf
AV		 1525 if (ha->eft) {
1526 dma_free_coherent(&ha->pdev->dev, eft_size, ha->eft,
1527 ha->eft_dma);
1528 ha->eft = NULL;
1529 ha->eft_dma = 0;
1530 }
1531 return;
1532 }
f73cb695 1533 ha->fw_dump_len = dump_size;
cfb0919c 1534 ql_dbg(ql_dbg_init, vha, 0x00c5,
7c3df132 1535 "Allocated (%d KB) for firmware dump.\n", dump_size / 1024);
a7a167bf 1536
f73cb695
CD		 1537 if (IS_QLA27XX(ha))
1538 return;
1539
a7a167bf
AV		 1540 ha->fw_dump->signature[0] = 'Q';
1541 ha->fw_dump->signature[1] = 'L';
1542 ha->fw_dump->signature[2] = 'G';
1543 ha->fw_dump->signature[3] = 'C';
1544 ha->fw_dump->version = __constant_htonl(1);
1545
1546 ha->fw_dump->fixed_size = htonl(fixed_size);
1547 ha->fw_dump->mem_size = htonl(mem_size);
1548 ha->fw_dump->req_q_size = htonl(req_q_size);
1549 ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
1550
1551 ha->fw_dump->eft_size = htonl(eft_size);
1552 ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma));
1553 ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma));
1554
1555 ha->fw_dump->header_size =
1556 htonl(offsetof(struct qla2xxx_fw_dump, isp));
0107109e
AV		 1557}
1558
18e7555a
AV		 1559static int
1560qla81xx_mpi_sync(scsi_qla_host_t *vha)
1561{
1562#define MPS_MASK 0xe0
1563 int rval;
1564 uint16_t dc;
1565 uint32_t dw;
18e7555a
AV		 1566
1567 if (!IS_QLA81XX(vha->hw))
1568 return QLA_SUCCESS;
1569
1570 rval = qla2x00_write_ram_word(vha, 0x7c00, 1);
1571 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1572 ql_log(ql_log_warn, vha, 0x0105,
1573 "Unable to acquire semaphore.\n");
18e7555a
AV		 1574 goto done;
1575 }
1576
1577 pci_read_config_word(vha->hw->pdev, 0x54, &dc);
1578 rval = qla2x00_read_ram_word(vha, 0x7a15, &dw);
1579 if (rval != QLA_SUCCESS) {
7c3df132 1580 ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n");
18e7555a
AV		 1581 goto done_release;
1582 }
1583
1584 dc &= MPS_MASK;
1585 if (dc == (dw & MPS_MASK))
1586 goto done_release;
1587
1588 dw &= ~MPS_MASK;
1589 dw |= dc;
1590 rval = qla2x00_write_ram_word(vha, 0x7a15, dw);
1591 if (rval != QLA_SUCCESS) {
7c3df132 1592 ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n");
18e7555a
AV		 1593 }
1594
1595done_release:
1596 rval = qla2x00_write_ram_word(vha, 0x7c00, 0);
1597 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1598 ql_log(ql_log_warn, vha, 0x006d,
1599 "Unable to release semaphore.\n");
18e7555a
AV		 1600 }
1601
1602done:
1603 return rval;
1604}
1605
8d93f550
CD		 1606int
1607qla2x00_alloc_outstanding_cmds(struct qla_hw_data *ha, struct req_que *req)
1608{
1609 /* Don't try to reallocate the array */
1610 if (req->outstanding_cmds)
1611 return QLA_SUCCESS;
1612
1613 if (!IS_FWI2_CAPABLE(ha) || (ha->mqiobase &&
1614 (ql2xmultique_tag || ql2xmaxqueues > 1)))
1615 req->num_outstanding_cmds = DEFAULT_OUTSTANDING_COMMANDS;
1616 else {
1617 if (ha->fw_xcb_count <= ha->fw_iocb_count)
1618 req->num_outstanding_cmds = ha->fw_xcb_count;
1619 else
1620 req->num_outstanding_cmds = ha->fw_iocb_count;
1621 }
1622
1623 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
1624 req->num_outstanding_cmds, GFP_KERNEL);
1625
1626 if (!req->outstanding_cmds) {
1627 /*
1628 * Try to allocate a minimal size just so we can get through
1629 * initialization.
1630 */
1631 req->num_outstanding_cmds = MIN_OUTSTANDING_COMMANDS;
1632 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
1633 req->num_outstanding_cmds, GFP_KERNEL);
1634
1635 if (!req->outstanding_cmds) {
1636 ql_log(ql_log_fatal, NULL, 0x0126,
1637 "Failed to allocate memory for "
1638 "outstanding_cmds for req_que %p.\n", req);
1639 req->num_outstanding_cmds = 0;
1640 return QLA_FUNCTION_FAILED;
1641 }
1642 }
1643
1644 return QLA_SUCCESS;
1645}
1646
1da177e4
LT		 1647/**
1648 * qla2x00_setup_chip() - Load and start RISC firmware.
1649 * @ha: HA context
1650 *
1651 * Returns 0 on success.
1652 */
1653static int
e315cd28 1654qla2x00_setup_chip(scsi_qla_host_t *vha)
1da177e4 1655{
0107109e
AV		 1656 int rval;
1657 uint32_t srisc_address = 0;
e315cd28 1658 struct qla_hw_data *ha = vha->hw;
3db0652e
AV		 1659 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1660 unsigned long flags;
dda772e8 1661 uint16_t fw_major_version;
3db0652e 1662
7ec0effd 1663 if (IS_P3P_TYPE(ha)) {
a9083016 1664 rval = ha->isp_ops->load_risc(vha, &srisc_address);
14e303d9
AV		 1665 if (rval == QLA_SUCCESS) {
1666 qla2x00_stop_firmware(vha);
a9083016 1667 goto enable_82xx_npiv;
14e303d9 1668 } else
b963752f 1669 goto failed;
a9083016
GM		 1670 }
1671
3db0652e
AV		 1672 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1673 /* Disable SRAM, Instruction RAM and GP RAM parity. */
1674 spin_lock_irqsave(&ha->hardware_lock, flags);
1675 WRT_REG_WORD(&reg->hccr, (HCCR_ENABLE_PARITY + 0x0));
1676 RD_REG_WORD(&reg->hccr);
1677 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1678 }
1da177e4 1679
18e7555a
AV		 1680 qla81xx_mpi_sync(vha);
1681
1da177e4 1682 /* Load firmware sequences */
e315cd28 1683 rval = ha->isp_ops->load_risc(vha, &srisc_address);
0107109e 1684 if (rval == QLA_SUCCESS) {
7c3df132
SK		 1685 ql_dbg(ql_dbg_init, vha, 0x00c9,
1686 "Verifying Checksum of loaded RISC code.\n");
1da177e4 1687
e315cd28 1688 rval = qla2x00_verify_checksum(vha, srisc_address);
1da177e4
LT		 1689 if (rval == QLA_SUCCESS) {
1690 /* Start firmware execution. */
7c3df132
SK		 1691 ql_dbg(ql_dbg_init, vha, 0x00ca,
1692 "Starting firmware.\n");
1da177e4 1693
e315cd28 1694 rval = qla2x00_execute_fw(vha, srisc_address);
1da177e4 1695 /* Retrieve firmware information. */
dda772e8 1696 if (rval == QLA_SUCCESS) {
a9083016 1697enable_82xx_npiv:
dda772e8 1698 fw_major_version = ha->fw_major_version;
7ec0effd 1699 if (IS_P3P_TYPE(ha))
3173167f 1700 qla82xx_check_md_needed(vha);
6246b8a1
GM		 1701 else
1702 rval = qla2x00_get_fw_version(vha);
ca9e9c3e
AV		 1703 if (rval != QLA_SUCCESS)
1704 goto failed;
2c3dfe3f 1705 ha->flags.npiv_supported = 0;
e315cd28 1706 if (IS_QLA2XXX_MIDTYPE(ha) &&
946fb891 1707 (ha->fw_attributes & BIT_2)) {
2c3dfe3f 1708 ha->flags.npiv_supported = 1;
4d0ea247
SJ		 1709 if ((!ha->max_npiv_vports) ||
1710 ((ha->max_npiv_vports + 1) %
eb66dc60 1711 MIN_MULTI_ID_FABRIC))
4d0ea247 1712 ha->max_npiv_vports =
eb66dc60 1713 MIN_MULTI_ID_FABRIC - 1;
4d0ea247 1714 }
24a08138 1715 qla2x00_get_resource_cnts(vha, NULL,
8d93f550 1716 &ha->fw_xcb_count, NULL, &ha->fw_iocb_count,
f3a0a77e 1717 &ha->max_npiv_vports, NULL);
d743de66 1718
8d93f550
CD		 1719 /*
1720 * Allocate the array of outstanding commands
1721 * now that we know the firmware resources.
1722 */
1723 rval = qla2x00_alloc_outstanding_cmds(ha,
1724 vha->req);
1725 if (rval != QLA_SUCCESS)
1726 goto failed;
1727
be5ea3cf 1728 if (!fw_major_version && ql2xallocfwdump
7ec0effd 1729 && !(IS_P3P_TYPE(ha)))
08de2844 1730 qla2x00_alloc_fw_dump(vha);
3b6e5b9d
CD		 1731 } else {
1732 goto failed;
1da177e4
LT		 1733 }
1734 } else {
7c3df132
SK		 1735 ql_log(ql_log_fatal, vha, 0x00cd,
1736 "ISP Firmware failed checksum.\n");
1737 goto failed;
1da177e4 1738 }
c74d88a4
AV		 1739 } else
1740 goto failed;
1da177e4 1741
3db0652e
AV		 1742 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1743 /* Enable proper parity. */
1744 spin_lock_irqsave(&ha->hardware_lock, flags);
1745 if (IS_QLA2300(ha))
1746 /* SRAM parity */
1747 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x1);
1748 else
1749 /* SRAM, Instruction RAM and GP RAM parity */
1750 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x7);
1751 RD_REG_WORD(&reg->hccr);
1752 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1753 }
1754
1d2874de
JC		 1755 if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
1756 uint32_t size;
1757
1758 rval = qla81xx_fac_get_sector_size(vha, &size);
1759 if (rval == QLA_SUCCESS) {
1760 ha->flags.fac_supported = 1;
1761 ha->fdt_block_size = size << 2;
1762 } else {
7c3df132 1763 ql_log(ql_log_warn, vha, 0x00ce,
1d2874de
JC		 1764 "Unsupported FAC firmware (%d.%02d.%02d).\n",
1765 ha->fw_major_version, ha->fw_minor_version,
1766 ha->fw_subminor_version);
1ca60e3b 1767
f73cb695 1768 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
6246b8a1
GM		 1769 ha->flags.fac_supported = 0;
1770 rval = QLA_SUCCESS;
1771 }
1d2874de
JC		 1772 }
1773 }
ca9e9c3e 1774failed:
1da177e4 1775 if (rval) {
7c3df132
SK		 1776 ql_log(ql_log_fatal, vha, 0x00cf,
1777 "Setup chip ****FAILED****.\n");
1da177e4
LT		 1778 }
1779
1780 return (rval);
1781}
1782
1783/**
1784 * qla2x00_init_response_q_entries() - Initializes response queue entries.
1785 * @ha: HA context
1786 *
1787 * Beginning of request ring has initialization control block already built
1788 * by nvram config routine.
1789 *
1790 * Returns 0 on success.
1791 */
73208dfd
AC		 1792void
1793qla2x00_init_response_q_entries(struct rsp_que *rsp)
1da177e4
LT		 1794{
1795 uint16_t cnt;
1796 response_t *pkt;
1797
2afa19a9
AC		 1798 rsp->ring_ptr = rsp->ring;
1799 rsp->ring_index = 0;
1800 rsp->status_srb = NULL;
e315cd28
AC		 1801 pkt = rsp->ring_ptr;
1802 for (cnt = 0; cnt < rsp->length; cnt++) {
1da177e4
LT		 1803 pkt->signature = RESPONSE_PROCESSED;
1804 pkt++;
1805 }
1da177e4
LT		 1806}
1807
1808/**
1809 * qla2x00_update_fw_options() - Read and process firmware options.
1810 * @ha: HA context
1811 *
1812 * Returns 0 on success.
1813 */
abbd8870 1814void
e315cd28 1815qla2x00_update_fw_options(scsi_qla_host_t *vha)
1da177e4
LT		 1816{
1817 uint16_t swing, emphasis, tx_sens, rx_sens;
e315cd28 1818 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 1819
1820 memset(ha->fw_options, 0, sizeof(ha->fw_options));
e315cd28 1821 qla2x00_get_fw_options(vha, ha->fw_options);
1da177e4
LT		 1822
1823 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1824 return;
1825
1826 /* Serial Link options. */
7c3df132
SK		 1827 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
1828 "Serial link options.\n");
1829 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
1830 (uint8_t *)&ha->fw_seriallink_options,
1831 sizeof(ha->fw_seriallink_options));
1da177e4
LT		 1832
1833 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1834 if (ha->fw_seriallink_options[3] & BIT_2) {
1835 ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING;
1836
1837 /* 1G settings */
1838 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
1839 emphasis = (ha->fw_seriallink_options[2] &
1840 (BIT_4 | BIT_3)) >> 3;
1841 tx_sens = ha->fw_seriallink_options[0] &
fa2a1ce5 1842 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 1843 rx_sens = (ha->fw_seriallink_options[0] &
1844 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
1845 ha->fw_options[10] = (emphasis << 14) | (swing << 8);
1846 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
1847 if (rx_sens == 0x0)
1848 rx_sens = 0x3;
1849 ha->fw_options[10] |= (tx_sens << 4) | rx_sens;
1850 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
1851 ha->fw_options[10] |= BIT_5 |
1852 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
1853 (tx_sens & (BIT_1 | BIT_0));
1854
1855 /* 2G settings */
1856 swing = (ha->fw_seriallink_options[2] &
1857 (BIT_7 | BIT_6 | BIT_5)) >> 5;
1858 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
1859 tx_sens = ha->fw_seriallink_options[1] &
fa2a1ce5 1860 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 1861 rx_sens = (ha->fw_seriallink_options[1] &
1862 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
1863 ha->fw_options[11] = (emphasis << 14) | (swing << 8);
1864 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
1865 if (rx_sens == 0x0)
1866 rx_sens = 0x3;
1867 ha->fw_options[11] |= (tx_sens << 4) | rx_sens;
1868 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
1869 ha->fw_options[11] |= BIT_5 |
1870 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
1871 (tx_sens & (BIT_1 | BIT_0));
1872 }
1873
1874 /* FCP2 options. */
1875 /* Return command IOCBs without waiting for an ABTS to complete. */
1876 ha->fw_options[3] |= BIT_13;
1877
1878 /* LED scheme. */
1879 if (ha->flags.enable_led_scheme)
1880 ha->fw_options[2] |= BIT_12;
1881
48c02fde
AV		 1882 /* Detect ISP6312. */
1883 if (IS_QLA6312(ha))
1884 ha->fw_options[2] |= BIT_13;
1885
1da177e4 1886 /* Update firmware options. */
e315cd28 1887 qla2x00_set_fw_options(vha, ha->fw_options);
1da177e4
LT		 1888}
1889
0107109e 1890void
e315cd28 1891qla24xx_update_fw_options(scsi_qla_host_t *vha)
0107109e
AV		 1892{
1893 int rval;
e315cd28 1894 struct qla_hw_data *ha = vha->hw;
0107109e 1895
7ec0effd 1896 if (IS_P3P_TYPE(ha))
a9083016
GM		 1897 return;
1898
0107109e 1899 /* Update Serial Link options. */
f94097ed 1900 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0)
0107109e
AV		 1901 return;
1902
e315cd28 1903 rval = qla2x00_set_serdes_params(vha,
f94097ed
AV		 1904 le16_to_cpu(ha->fw_seriallink_options24[1]),
1905 le16_to_cpu(ha->fw_seriallink_options24[2]),
1906 le16_to_cpu(ha->fw_seriallink_options24[3]));
0107109e 1907 if (rval != QLA_SUCCESS) {
7c3df132 1908 ql_log(ql_log_warn, vha, 0x0104,
0107109e
AV		 1909 "Unable to update Serial Link options (%x).\n", rval);
1910 }
1911}
1912
abbd8870 1913void
e315cd28 1914qla2x00_config_rings(struct scsi_qla_host *vha)
abbd8870 1915{
e315cd28 1916 struct qla_hw_data *ha = vha->hw;
3d71644c 1917 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
73208dfd
AC		 1918 struct req_que *req = ha->req_q_map[0];
1919 struct rsp_que *rsp = ha->rsp_q_map[0];
abbd8870
AV		 1920
1921 /* Setup ring parameters in initialization control block. */
1922 ha->init_cb->request_q_outpointer = __constant_cpu_to_le16(0);
1923 ha->init_cb->response_q_inpointer = __constant_cpu_to_le16(0);
e315cd28
AC		 1924 ha->init_cb->request_q_length = cpu_to_le16(req->length);
1925 ha->init_cb->response_q_length = cpu_to_le16(rsp->length);
1926 ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
1927 ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
1928 ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
1929 ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
abbd8870
AV		 1930
1931 WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0);
1932 WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0);
1933 WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0);
1934 WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0);
1935 RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */
1936}
1937
0107109e 1938void
e315cd28 1939qla24xx_config_rings(struct scsi_qla_host *vha)
0107109e 1940{
e315cd28 1941 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 1942 device_reg_t __iomem *reg = ISP_QUE_REG(ha, 0);
1943 struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
1944 struct qla_msix_entry *msix;
0107109e 1945 struct init_cb_24xx *icb;
73208dfd
AC		 1946 uint16_t rid = 0;
1947 struct req_que *req = ha->req_q_map[0];
1948 struct rsp_que *rsp = ha->rsp_q_map[0];
0107109e 1949
6246b8a1 1950 /* Setup ring parameters in initialization control block. */
0107109e
AV		 1951 icb = (struct init_cb_24xx *)ha->init_cb;
1952 icb->request_q_outpointer = __constant_cpu_to_le16(0);
1953 icb->response_q_inpointer = __constant_cpu_to_le16(0);
e315cd28
AC		 1954 icb->request_q_length = cpu_to_le16(req->length);
1955 icb->response_q_length = cpu_to_le16(rsp->length);
1956 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
1957 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
1958 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
1959 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
0107109e 1960
2d70c103
NB		 1961 /* Setup ATIO queue dma pointers for target mode */
1962 icb->atio_q_inpointer = __constant_cpu_to_le16(0);
1963 icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length);
1964 icb->atio_q_address[0] = cpu_to_le32(LSD(ha->tgt.atio_dma));
1965 icb->atio_q_address[1] = cpu_to_le32(MSD(ha->tgt.atio_dma));
1966
f73cb695 1967 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
73208dfd
AC		 1968 icb->qos = __constant_cpu_to_le16(QLA_DEFAULT_QUE_QOS);
1969 icb->rid = __constant_cpu_to_le16(rid);
1970 if (ha->flags.msix_enabled) {
1971 msix = &ha->msix_entries[1];
7c3df132
SK		 1972 ql_dbg(ql_dbg_init, vha, 0x00fd,
1973 "Registering vector 0x%x for base que.\n",
1974 msix->entry);
73208dfd
AC		 1975 icb->msix = cpu_to_le16(msix->entry);
1976 }
1977 /* Use alternate PCI bus number */
1978 if (MSB(rid))
1979 icb->firmware_options_2 |=
1980 __constant_cpu_to_le32(BIT_19);
1981 /* Use alternate PCI devfn */
1982 if (LSB(rid))
1983 icb->firmware_options_2 |=
1984 __constant_cpu_to_le32(BIT_18);
1985
3155754a 1986 /* Use Disable MSIX Handshake mode for capable adapters */
6246b8a1
GM		 1987 if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) &&
1988 (ha->flags.msix_enabled)) {
3155754a
AC		 1989 icb->firmware_options_2 &=
1990 __constant_cpu_to_le32(~BIT_22);
1991 ha->flags.disable_msix_handshake = 1;
7c3df132
SK		 1992 ql_dbg(ql_dbg_init, vha, 0x00fe,
1993 "MSIX Handshake Disable Mode turned on.\n");
3155754a
AC		 1994 } else {
1995 icb->firmware_options_2 |=
1996 __constant_cpu_to_le32(BIT_22);
1997 }
73208dfd 1998 icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_23);
73208dfd
AC		 1999
2000 WRT_REG_DWORD(&reg->isp25mq.req_q_in, 0);
2001 WRT_REG_DWORD(&reg->isp25mq.req_q_out, 0);
2002 WRT_REG_DWORD(&reg->isp25mq.rsp_q_in, 0);
2003 WRT_REG_DWORD(&reg->isp25mq.rsp_q_out, 0);
2004 } else {
2005 WRT_REG_DWORD(&reg->isp24.req_q_in, 0);
2006 WRT_REG_DWORD(&reg->isp24.req_q_out, 0);
2007 WRT_REG_DWORD(&reg->isp24.rsp_q_in, 0);
2008 WRT_REG_DWORD(&reg->isp24.rsp_q_out, 0);
2009 }
aa230bc5 2010 qlt_24xx_config_rings(vha);
2d70c103 2011
73208dfd
AC		 2012 /* PCI posting */
2013 RD_REG_DWORD(&ioreg->hccr);
0107109e
AV		 2014}
2015
1da177e4
LT		 2016/**
2017 * qla2x00_init_rings() - Initializes firmware.
2018 * @ha: HA context
2019 *
2020 * Beginning of request ring has initialization control block already built
2021 * by nvram config routine.
2022 *
2023 * Returns 0 on success.
2024 */
8ae6d9c7 2025int
e315cd28 2026qla2x00_init_rings(scsi_qla_host_t *vha)
1da177e4
LT		 2027{
2028 int rval;
2029 unsigned long flags = 0;
29bdccbe 2030 int cnt, que;
e315cd28 2031 struct qla_hw_data *ha = vha->hw;
29bdccbe
AC		 2032 struct req_que *req;
2033 struct rsp_que *rsp;
2c3dfe3f
SJ		 2034 struct mid_init_cb_24xx *mid_init_cb =
2035 (struct mid_init_cb_24xx *) ha->init_cb;
1da177e4
LT		 2036
2037 spin_lock_irqsave(&ha->hardware_lock, flags);
2038
2039 /* Clear outstanding commands array. */
2afa19a9 2040 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe
AC		 2041 req = ha->req_q_map[que];
2042 if (!req)
2043 continue;
8d93f550 2044 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++)
29bdccbe 2045 req->outstanding_cmds[cnt] = NULL;
1da177e4 2046
2afa19a9 2047 req->current_outstanding_cmd = 1;
1da177e4 2048
29bdccbe
AC		 2049 /* Initialize firmware. */
2050 req->ring_ptr = req->ring;
2051 req->ring_index = 0;
2052 req->cnt = req->length;
2053 }
1da177e4 2054
2afa19a9 2055 for (que = 0; que < ha->max_rsp_queues; que++) {
29bdccbe
AC		 2056 rsp = ha->rsp_q_map[que];
2057 if (!rsp)
2058 continue;
29bdccbe 2059 /* Initialize response queue entries */
8ae6d9c7
GM		 2060 if (IS_QLAFX00(ha))
2061 qlafx00_init_response_q_entries(rsp);
2062 else
2063 qla2x00_init_response_q_entries(rsp);
29bdccbe 2064 }
1da177e4 2065
2d70c103
NB		 2066 ha->tgt.atio_ring_ptr = ha->tgt.atio_ring;
2067 ha->tgt.atio_ring_index = 0;
2068 /* Initialize ATIO queue entries */
2069 qlt_init_atio_q_entries(vha);
2070
e315cd28 2071 ha->isp_ops->config_rings(vha);
1da177e4
LT		 2072
2073 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2074
8ae6d9c7
GM		 2075 ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n");
2076
2077 if (IS_QLAFX00(ha)) {
2078 rval = qlafx00_init_firmware(vha, ha->init_cb_size);
2079 goto next_check;
2080 }
2081
1da177e4 2082 /* Update any ISP specific firmware options before initialization. */
e315cd28 2083 ha->isp_ops->update_fw_options(vha);
1da177e4 2084
605aa2bc 2085 if (ha->flags.npiv_supported) {
45980cc2 2086 if (ha->operating_mode == LOOP && !IS_CNA_CAPABLE(ha))
605aa2bc 2087 ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
c48339de 2088 mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
605aa2bc
LC		 2089 }
2090
24a08138
AV		 2091 if (IS_FWI2_CAPABLE(ha)) {
2092 mid_init_cb->options = __constant_cpu_to_le16(BIT_1);
2093 mid_init_cb->init_cb.execution_throttle =
2094 cpu_to_le16(ha->fw_xcb_count);
2095 }
2c3dfe3f 2096
e315cd28 2097 rval = qla2x00_init_firmware(vha, ha->init_cb_size);
8ae6d9c7 2098next_check:
1da177e4 2099 if (rval) {
7c3df132
SK		 2100 ql_log(ql_log_fatal, vha, 0x00d2,
2101 "Init Firmware **** FAILED ****.\n");
1da177e4 2102 } else {
7c3df132
SK		 2103 ql_dbg(ql_dbg_init, vha, 0x00d3,
2104 "Init Firmware -- success.\n");
1da177e4
LT		 2105 }
2106
2107 return (rval);
2108}
2109
2110/**
2111 * qla2x00_fw_ready() - Waits for firmware ready.
2112 * @ha: HA context
2113 *
2114 * Returns 0 on success.
2115 */
2116static int
e315cd28 2117qla2x00_fw_ready(scsi_qla_host_t *vha)
1da177e4
LT		 2118{
2119 int rval;
4d4df193 2120 unsigned long wtime, mtime, cs84xx_time;
1da177e4
LT		 2121 uint16_t min_wait; /* Minimum wait time if loop is down */
2122 uint16_t wait_time; /* Wait time if loop is coming ready */
656e8912 2123 uint16_t state[5];
e315cd28 2124 struct qla_hw_data *ha = vha->hw;
1da177e4 2125
8ae6d9c7
GM		 2126 if (IS_QLAFX00(vha->hw))
2127 return qlafx00_fw_ready(vha);
2128
1da177e4
LT		 2129 rval = QLA_SUCCESS;
2130
2131 /* 20 seconds for loop down. */
fa2a1ce5 2132 min_wait = 20;
1da177e4
LT		 2133
2134 /*
2135 * Firmware should take at most one RATOV to login, plus 5 seconds for
2136 * our own processing.
2137 */
2138 if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) {
2139 wait_time = min_wait;
2140 }
2141
2142 /* Min wait time if loop down */
2143 mtime = jiffies + (min_wait * HZ);
2144
2145 /* wait time before firmware ready */
2146 wtime = jiffies + (wait_time * HZ);
2147
2148 /* Wait for ISP to finish LIP */
e315cd28 2149 if (!vha->flags.init_done)
7c3df132
SK		 2150 ql_log(ql_log_info, vha, 0x801e,
2151 "Waiting for LIP to complete.\n");
1da177e4
LT		 2152
2153 do {
5b939038 2154 memset(state, -1, sizeof(state));
e315cd28 2155 rval = qla2x00_get_firmware_state(vha, state);
1da177e4 2156 if (rval == QLA_SUCCESS) {
4d4df193 2157 if (state[0] < FSTATE_LOSS_OF_SYNC) {
e315cd28 2158 vha->device_flags &= ~DFLG_NO_CABLE;
1da177e4 2159 }
4d4df193 2160 if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) {
7c3df132
SK		 2161 ql_dbg(ql_dbg_taskm, vha, 0x801f,
2162 "fw_state=%x 84xx=%x.\n", state[0],
2163 state[2]);
4d4df193
HK		 2164 if ((state[2] & FSTATE_LOGGED_IN) &&
2165 (state[2] & FSTATE_WAITING_FOR_VERIFY)) {
7c3df132
SK		 2166 ql_dbg(ql_dbg_taskm, vha, 0x8028,
2167 "Sending verify iocb.\n");
4d4df193
HK		 2168
2169 cs84xx_time = jiffies;
e315cd28 2170 rval = qla84xx_init_chip(vha);
7c3df132
SK		 2171 if (rval != QLA_SUCCESS) {
2172 ql_log(ql_log_warn,
cfb0919c 2173 vha, 0x8007,
7c3df132 2174 "Init chip failed.\n");
4d4df193 2175 break;
7c3df132 2176 }
4d4df193
HK		 2177
2178 /* Add time taken to initialize. */
2179 cs84xx_time = jiffies - cs84xx_time;
2180 wtime += cs84xx_time;
2181 mtime += cs84xx_time;
cfb0919c 2182 ql_dbg(ql_dbg_taskm, vha, 0x8008,
7c3df132
SK		 2183 "Increasing wait time by %ld. "
2184 "New time %ld.\n", cs84xx_time,
2185 wtime);
4d4df193
HK		 2186 }
2187 } else if (state[0] == FSTATE_READY) {
7c3df132
SK		 2188 ql_dbg(ql_dbg_taskm, vha, 0x8037,
2189 "F/W Ready - OK.\n");
1da177e4 2190
e315cd28 2191 qla2x00_get_retry_cnt(vha, &ha->retry_count,
1da177e4
LT		 2192 &ha->login_timeout, &ha->r_a_tov);
2193
2194 rval = QLA_SUCCESS;
2195 break;
2196 }
2197
2198 rval = QLA_FUNCTION_FAILED;
2199
e315cd28 2200 if (atomic_read(&vha->loop_down_timer) &&
4d4df193 2201 state[0] != FSTATE_READY) {
1da177e4 2202 /* Loop down. Timeout on min_wait for states
fa2a1ce5
AV		 2203 * other than Wait for Login.
2204 */
1da177e4 2205 if (time_after_eq(jiffies, mtime)) {
7c3df132 2206 ql_log(ql_log_info, vha, 0x8038,
1da177e4
LT		 2207 "Cable is unplugged...\n");
2208
e315cd28 2209 vha->device_flags |= DFLG_NO_CABLE;
1da177e4
LT		 2210 break;
2211 }
2212 }
2213 } else {
2214 /* Mailbox cmd failed. Timeout on min_wait. */
cdbb0a4f 2215 if (time_after_eq(jiffies, mtime) ||
7190575f 2216 ha->flags.isp82xx_fw_hung)
1da177e4
LT		 2217 break;
2218 }
2219
2220 if (time_after_eq(jiffies, wtime))
2221 break;
2222
2223 /* Delay for a while */
2224 msleep(500);
1da177e4
LT		 2225 } while (1);
2226
7c3df132
SK		 2227 ql_dbg(ql_dbg_taskm, vha, 0x803a,
2228 "fw_state=%x (%x, %x, %x, %x) " "curr time=%lx.\n", state[0],
2229 state[1], state[2], state[3], state[4], jiffies);
1da177e4 2230
cfb0919c 2231 if (rval && !(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132
SK		 2232 ql_log(ql_log_warn, vha, 0x803b,
2233 "Firmware ready **** FAILED ****.\n");
1da177e4
LT		 2234 }
2235
2236 return (rval);
2237}
2238
2239/*
2240* qla2x00_configure_hba
2241* Setup adapter context.
2242*
2243* Input:
2244* ha = adapter state pointer.
2245*
2246* Returns:
2247* 0 = success
2248*
2249* Context:
2250* Kernel context.
2251*/
2252static int
e315cd28 2253qla2x00_configure_hba(scsi_qla_host_t *vha)
1da177e4
LT		 2254{
2255 int rval;
2256 uint16_t loop_id;
2257 uint16_t topo;
2c3dfe3f 2258 uint16_t sw_cap;
1da177e4
LT		 2259 uint8_t al_pa;
2260 uint8_t area;
2261 uint8_t domain;
2262 char connect_type[22];
e315cd28 2263 struct qla_hw_data *ha = vha->hw;
f24b5cb8 2264 unsigned long flags;
61e1b269 2265 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 2266
2267 /* Get host addresses. */
e315cd28 2268 rval = qla2x00_get_adapter_id(vha,
2c3dfe3f 2269 &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
1da177e4 2270 if (rval != QLA_SUCCESS) {
e315cd28 2271 if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
6246b8a1 2272 IS_CNA_CAPABLE(ha) ||
33135aa2 2273 (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
7c3df132
SK		 2274 ql_dbg(ql_dbg_disc, vha, 0x2008,
2275 "Loop is in a transition state.\n");
33135aa2 2276 } else {
7c3df132
SK		 2277 ql_log(ql_log_warn, vha, 0x2009,
2278 "Unable to get host loop ID.\n");
61e1b269
JC		 2279 if (IS_FWI2_CAPABLE(ha) && (vha == base_vha) &&
2280 (rval == QLA_COMMAND_ERROR && loop_id == 0x1b)) {
2281 ql_log(ql_log_warn, vha, 0x1151,
2282 "Doing link init.\n");
2283 if (qla24xx_link_initialize(vha) == QLA_SUCCESS)
2284 return rval;
2285 }
e315cd28 2286 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
33135aa2 2287 }
1da177e4
LT		 2288 return (rval);
2289 }
2290
2291 if (topo == 4) {
7c3df132
SK		 2292 ql_log(ql_log_info, vha, 0x200a,
2293 "Cannot get topology - retrying.\n");
1da177e4
LT		 2294 return (QLA_FUNCTION_FAILED);
2295 }
2296
e315cd28 2297 vha->loop_id = loop_id;
1da177e4
LT		 2298
2299 /* initialize */
2300 ha->min_external_loopid = SNS_FIRST_LOOP_ID;
2301 ha->operating_mode = LOOP;
2c3dfe3f 2302 ha->switch_cap = 0;
1da177e4
LT		 2303
2304 switch (topo) {
2305 case 0:
7c3df132 2306 ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n");
1da177e4
LT		 2307 ha->current_topology = ISP_CFG_NL;
2308 strcpy(connect_type, "(Loop)");
2309 break;
2310
2311 case 1:
7c3df132 2312 ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n");
2c3dfe3f 2313 ha->switch_cap = sw_cap;
1da177e4
LT		 2314 ha->current_topology = ISP_CFG_FL;
2315 strcpy(connect_type, "(FL_Port)");
2316 break;
2317
2318 case 2:
7c3df132 2319 ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n");
1da177e4
LT		 2320 ha->operating_mode = P2P;
2321 ha->current_topology = ISP_CFG_N;
2322 strcpy(connect_type, "(N_Port-to-N_Port)");
2323 break;
2324
2325 case 3:
7c3df132 2326 ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n");
2c3dfe3f 2327 ha->switch_cap = sw_cap;
1da177e4
LT		 2328 ha->operating_mode = P2P;
2329 ha->current_topology = ISP_CFG_F;
2330 strcpy(connect_type, "(F_Port)");
2331 break;
2332
2333 default:
7c3df132
SK		 2334 ql_dbg(ql_dbg_disc, vha, 0x200f,
2335 "HBA in unknown topology %x, using NL.\n", topo);
1da177e4
LT		 2336 ha->current_topology = ISP_CFG_NL;
2337 strcpy(connect_type, "(Loop)");
2338 break;
2339 }
2340
2341 /* Save Host port and loop ID. */
2342 /* byte order - Big Endian */
e315cd28
AC		 2343 vha->d_id.b.domain = domain;
2344 vha->d_id.b.area = area;
2345 vha->d_id.b.al_pa = al_pa;
1da177e4 2346
f24b5cb8 2347 spin_lock_irqsave(&ha->vport_slock, flags);
2d70c103 2348 qlt_update_vp_map(vha, SET_AL_PA);
f24b5cb8 2349 spin_unlock_irqrestore(&ha->vport_slock, flags);
2d70c103 2350
e315cd28 2351 if (!vha->flags.init_done)
7c3df132
SK		 2352 ql_log(ql_log_info, vha, 0x2010,
2353 "Topology - %s, Host Loop address 0x%x.\n",
e315cd28 2354 connect_type, vha->loop_id);
1da177e4 2355
1da177e4
LT		 2356 return(rval);
2357}
2358
a9083016 2359inline void
e315cd28
AC		 2360qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
2361 char *def)
9bb9fcf2
AV		 2362{
2363 char *st, *en;
2364 uint16_t index;
e315cd28 2365 struct qla_hw_data *ha = vha->hw;
ab671149 2366 int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
6246b8a1 2367 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha);
9bb9fcf2
AV		 2368
2369 if (memcmp(model, BINZERO, len) != 0) {
2370 strncpy(ha->model_number, model, len);
2371 st = en = ha->model_number;
2372 en += len - 1;
2373 while (en > st) {
2374 if (*en != 0x20 && *en != 0x00)
2375 break;
2376 *en-- = '\0';
2377 }
2378
2379 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 2380 if (use_tbl &&
2381 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2 2382 index < QLA_MODEL_NAMES)
1ee27146
JC		 2383 strncpy(ha->model_desc,
2384 qla2x00_model_name[index * 2 + 1],
2385 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 2386 } else {
2387 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 2388 if (use_tbl &&
2389 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2
AV		 2390 index < QLA_MODEL_NAMES) {
2391 strcpy(ha->model_number,
2392 qla2x00_model_name[index * 2]);
1ee27146
JC		 2393 strncpy(ha->model_desc,
2394 qla2x00_model_name[index * 2 + 1],
2395 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 2396 } else {
2397 strcpy(ha->model_number, def);
2398 }
2399 }
1ee27146 2400 if (IS_FWI2_CAPABLE(ha))
e315cd28 2401 qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc,
1ee27146 2402 sizeof(ha->model_desc));
9bb9fcf2
AV		 2403}
2404
4e08df3f
DM		 2405/* On sparc systems, obtain port and node WWN from firmware
2406 * properties.
2407 */
e315cd28 2408static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv)
4e08df3f
DM		 2409{
2410#ifdef CONFIG_SPARC
e315cd28 2411 struct qla_hw_data *ha = vha->hw;
4e08df3f 2412 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 2413 struct device_node *dp = pci_device_to_OF_node(pdev);
2414 const u8 *val;
4e08df3f
DM		 2415 int len;
2416
2417 val = of_get_property(dp, "port-wwn", &len);
2418 if (val && len >= WWN_SIZE)
2419 memcpy(nv->port_name, val, WWN_SIZE);
2420
2421 val = of_get_property(dp, "node-wwn", &len);
2422 if (val && len >= WWN_SIZE)
2423 memcpy(nv->node_name, val, WWN_SIZE);
2424#endif
2425}
2426
1da177e4
LT		 2427/*
2428* NVRAM configuration for ISP 2xxx
2429*
2430* Input:
2431* ha = adapter block pointer.
2432*
2433* Output:
2434* initialization control block in response_ring
2435* host adapters parameters in host adapter block
2436*
2437* Returns:
2438* 0 = success.
2439*/
abbd8870 2440int
e315cd28 2441qla2x00_nvram_config(scsi_qla_host_t *vha)
1da177e4 2442{
4e08df3f 2443 int rval;
0107109e
AV		 2444 uint8_t chksum = 0;
2445 uint16_t cnt;
2446 uint8_t *dptr1, *dptr2;
e315cd28 2447 struct qla_hw_data *ha = vha->hw;
0107109e 2448 init_cb_t *icb = ha->init_cb;
281afe19
SJ		 2449 nvram_t *nv = ha->nvram;
2450 uint8_t *ptr = ha->nvram;
3d71644c 2451 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 2452
4e08df3f
DM		 2453 rval = QLA_SUCCESS;
2454
1da177e4 2455 /* Determine NVRAM starting address. */
0107109e 2456 ha->nvram_size = sizeof(nvram_t);
1da177e4
LT		 2457 ha->nvram_base = 0;
2458 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
2459 if ((RD_REG_WORD(&reg->ctrl_status) >> 14) == 1)
2460 ha->nvram_base = 0x80;
2461
2462 /* Get NVRAM data and calculate checksum. */
e315cd28 2463 ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size);
0107109e
AV		 2464 for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++)
2465 chksum += *ptr++;
1da177e4 2466
7c3df132
SK		 2467 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
2468 "Contents of NVRAM.\n");
2469 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
2470 (uint8_t *)nv, ha->nvram_size);
1da177e4
LT		 2471
2472 /* Bad NVRAM data, set defaults parameters. */
2473 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' ||
2474 nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) {
2475 /* Reset NVRAM data. */
7c3df132 2476 ql_log(ql_log_warn, vha, 0x0064,
9e336520 2477 "Inconsistent NVRAM "
7c3df132
SK		 2478 "detected: checksum=0x%x id=%c version=0x%x.\n",
2479 chksum, nv->id[0], nv->nvram_version);
2480 ql_log(ql_log_warn, vha, 0x0065,
2481 "Falling back to "
2482 "functioning (yet invalid -- WWPN) defaults.\n");
4e08df3f
DM		 2483
2484 /*
2485 * Set default initialization control block.
2486 */
2487 memset(nv, 0, ha->nvram_size);
2488 nv->parameter_block_version = ICB_VERSION;
2489
2490 if (IS_QLA23XX(ha)) {
2491 nv->firmware_options[0] = BIT_2 | BIT_1;
2492 nv->firmware_options[1] = BIT_7 | BIT_5;
2493 nv->add_firmware_options[0] = BIT_5;
2494 nv->add_firmware_options[1] = BIT_5 | BIT_4;
2495 nv->frame_payload_size = __constant_cpu_to_le16(2048);
2496 nv->special_options[1] = BIT_7;
2497 } else if (IS_QLA2200(ha)) {
2498 nv->firmware_options[0] = BIT_2 | BIT_1;
2499 nv->firmware_options[1] = BIT_7 | BIT_5;
2500 nv->add_firmware_options[0] = BIT_5;
2501 nv->add_firmware_options[1] = BIT_5 | BIT_4;
2502 nv->frame_payload_size = __constant_cpu_to_le16(1024);
2503 } else if (IS_QLA2100(ha)) {
2504 nv->firmware_options[0] = BIT_3 | BIT_1;
2505 nv->firmware_options[1] = BIT_5;
2506 nv->frame_payload_size = __constant_cpu_to_le16(1024);
2507 }
2508
2509 nv->max_iocb_allocation = __constant_cpu_to_le16(256);
2510 nv->execution_throttle = __constant_cpu_to_le16(16);
2511 nv->retry_count = 8;
2512 nv->retry_delay = 1;
2513
2514 nv->port_name[0] = 33;
2515 nv->port_name[3] = 224;
2516 nv->port_name[4] = 139;
2517
e315cd28 2518 qla2xxx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 2519
2520 nv->login_timeout = 4;
2521
2522 /*
2523 * Set default host adapter parameters
2524 */
2525 nv->host_p[1] = BIT_2;
2526 nv->reset_delay = 5;
2527 nv->port_down_retry_count = 8;
2528 nv->max_luns_per_target = __constant_cpu_to_le16(8);
2529 nv->link_down_timeout = 60;
2530
2531 rval = 1;
1da177e4
LT		 2532 }
2533
2534#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
2535 /*
2536 * The SN2 does not provide BIOS emulation which means you can't change
2537 * potentially bogus BIOS settings. Force the use of default settings
2538 * for link rate and frame size. Hope that the rest of the settings
2539 * are valid.
2540 */
2541 if (ia64_platform_is("sn2")) {
2542 nv->frame_payload_size = __constant_cpu_to_le16(2048);
2543 if (IS_QLA23XX(ha))
2544 nv->special_options[1] = BIT_7;
2545 }
2546#endif
2547
2548 /* Reset Initialization control block */
0107109e 2549 memset(icb, 0, ha->init_cb_size);
1da177e4
LT		 2550
2551 /*
2552 * Setup driver NVRAM options.
2553 */
2554 nv->firmware_options[0] |= (BIT_6 | BIT_1);
2555 nv->firmware_options[0] &= ~(BIT_5 | BIT_4);
2556 nv->firmware_options[1] |= (BIT_5 | BIT_0);
2557 nv->firmware_options[1] &= ~BIT_4;
2558
2559 if (IS_QLA23XX(ha)) {
2560 nv->firmware_options[0] |= BIT_2;
2561 nv->firmware_options[0] &= ~BIT_3;
2d70c103 2562 nv->special_options[0] &= ~BIT_6;
0107109e 2563 nv->add_firmware_options[1] |= BIT_5 | BIT_4;
1da177e4
LT		 2564
2565 if (IS_QLA2300(ha)) {
2566 if (ha->fb_rev == FPM_2310) {
2567 strcpy(ha->model_number, "QLA2310");
2568 } else {
2569 strcpy(ha->model_number, "QLA2300");
2570 }
2571 } else {
e315cd28 2572 qla2x00_set_model_info(vha, nv->model_number,
9bb9fcf2 2573 sizeof(nv->model_number), "QLA23xx");
1da177e4
LT		 2574 }
2575 } else if (IS_QLA2200(ha)) {
2576 nv->firmware_options[0] |= BIT_2;
2577 /*
2578 * 'Point-to-point preferred, else loop' is not a safe
2579 * connection mode setting.
2580 */
2581 if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
2582 (BIT_5 | BIT_4)) {
2583 /* Force 'loop preferred, else point-to-point'. */
2584 nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
2585 nv->add_firmware_options[0] |= BIT_5;
2586 }
2587 strcpy(ha->model_number, "QLA22xx");
2588 } else /*if (IS_QLA2100(ha))*/ {
2589 strcpy(ha->model_number, "QLA2100");
2590 }
2591
2592 /*
2593 * Copy over NVRAM RISC parameter block to initialization control block.
2594 */
2595 dptr1 = (uint8_t *)icb;
2596 dptr2 = (uint8_t *)&nv->parameter_block_version;
2597 cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;
2598 while (cnt--)
2599 *dptr1++ = *dptr2++;
2600
2601 /* Copy 2nd half. */
2602 dptr1 = (uint8_t *)icb->add_firmware_options;
2603 cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;
2604 while (cnt--)
2605 *dptr1++ = *dptr2++;
2606
5341e868
AV		 2607 /* Use alternate WWN? */
2608 if (nv->host_p[1] & BIT_7) {
2609 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
2610 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
2611 }
2612
1da177e4
LT		 2613 /* Prepare nodename */
2614 if ((icb->firmware_options[1] & BIT_6) == 0) {
2615 /*
2616 * Firmware will apply the following mask if the nodename was
2617 * not provided.
2618 */
2619 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
2620 icb->node_name[0] &= 0xF0;
2621 }
2622
2623 /*
2624 * Set host adapter parameters.
2625 */
3ce8866c
SK		 2626
2627 /*
2628 * BIT_7 in the host-parameters section allows for modification to
2629 * internal driver logging.
2630 */
0181944f 2631 if (nv->host_p[0] & BIT_7)
cfb0919c 2632 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
1da177e4
LT		 2633 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
2634 /* Always load RISC code on non ISP2[12]00 chips. */
2635 if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
2636 ha->flags.disable_risc_code_load = 0;
2637 ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0);
2638 ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
2639 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
06c22bd1 2640 ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
d4c760c2 2641 ha->flags.disable_serdes = 0;
1da177e4
LT		 2642
2643 ha->operating_mode =
2644 (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
2645
2646 memcpy(ha->fw_seriallink_options, nv->seriallink_options,
2647 sizeof(ha->fw_seriallink_options));
2648
2649 /* save HBA serial number */
2650 ha->serial0 = icb->port_name[5];
2651 ha->serial1 = icb->port_name[6];
2652 ha->serial2 = icb->port_name[7];
e315cd28
AC		 2653 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
2654 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
1da177e4
LT		 2655
2656 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
2657
2658 ha->retry_count = nv->retry_count;
2659
2660 /* Set minimum login_timeout to 4 seconds. */
5b91490e 2661 if (nv->login_timeout != ql2xlogintimeout)
1da177e4
LT		 2662 nv->login_timeout = ql2xlogintimeout;
2663 if (nv->login_timeout < 4)
2664 nv->login_timeout = 4;
2665 ha->login_timeout = nv->login_timeout;
2666 icb->login_timeout = nv->login_timeout;
2667
00a537b8
AV		 2668 /* Set minimum RATOV to 100 tenths of a second. */
2669 ha->r_a_tov = 100;
1da177e4 2670
1da177e4
LT		 2671 ha->loop_reset_delay = nv->reset_delay;
2672
1da177e4
LT		 2673 /* Link Down Timeout = 0:
2674 *
2675 * When Port Down timer expires we will start returning
2676 * I/O's to OS with "DID_NO_CONNECT".
2677 *
2678 * Link Down Timeout != 0:
2679 *
2680 * The driver waits for the link to come up after link down
2681 * before returning I/Os to OS with "DID_NO_CONNECT".
fa2a1ce5 2682 */
1da177e4
LT		 2683 if (nv->link_down_timeout == 0) {
2684 ha->loop_down_abort_time =
354d6b21 2685 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
1da177e4
LT		 2686 } else {
2687 ha->link_down_timeout = nv->link_down_timeout;
2688 ha->loop_down_abort_time =
2689 (LOOP_DOWN_TIME - ha->link_down_timeout);
fa2a1ce5 2690 }
1da177e4 2691
1da177e4
LT		 2692 /*
2693 * Need enough time to try and get the port back.
2694 */
2695 ha->port_down_retry_count = nv->port_down_retry_count;
2696 if (qlport_down_retry)
2697 ha->port_down_retry_count = qlport_down_retry;
2698 /* Set login_retry_count */
2699 ha->login_retry_count = nv->retry_count;
2700 if (ha->port_down_retry_count == nv->port_down_retry_count &&
2701 ha->port_down_retry_count > 3)
2702 ha->login_retry_count = ha->port_down_retry_count;
2703 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
2704 ha->login_retry_count = ha->port_down_retry_count;
2705 if (ql2xloginretrycount)
2706 ha->login_retry_count = ql2xloginretrycount;
2707
1da177e4
LT		 2708 icb->lun_enables = __constant_cpu_to_le16(0);
2709 icb->command_resource_count = 0;
2710 icb->immediate_notify_resource_count = 0;
2711 icb->timeout = __constant_cpu_to_le16(0);
2712
2713 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
2714 /* Enable RIO */
2715 icb->firmware_options[0] &= ~BIT_3;
2716 icb->add_firmware_options[0] &=
2717 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
2718 icb->add_firmware_options[0] |= BIT_2;
2719 icb->response_accumulation_timer = 3;
2720 icb->interrupt_delay_timer = 5;
2721
e315cd28 2722 vha->flags.process_response_queue = 1;
1da177e4 2723 } else {
4fdfefe5 2724 /* Enable ZIO. */
e315cd28 2725 if (!vha->flags.init_done) {
4fdfefe5
AV		 2726 ha->zio_mode = icb->add_firmware_options[0] &
2727 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
2728 ha->zio_timer = icb->interrupt_delay_timer ?
2729 icb->interrupt_delay_timer: 2;
2730 }
1da177e4
LT		 2731 icb->add_firmware_options[0] &=
2732 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
e315cd28 2733 vha->flags.process_response_queue = 0;
4fdfefe5 2734 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d
AV		 2735 ha->zio_mode = QLA_ZIO_MODE_6;
2736
7c3df132 2737 ql_log(ql_log_info, vha, 0x0068,
4fdfefe5
AV		 2738 "ZIO mode %d enabled; timer delay (%d us).\n",
2739 ha->zio_mode, ha->zio_timer * 100);
1da177e4 2740
4fdfefe5
AV		 2741 icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;
2742 icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;
e315cd28 2743 vha->flags.process_response_queue = 1;
1da177e4
LT		 2744 }
2745 }
2746
4e08df3f 2747 if (rval) {
7c3df132
SK		 2748 ql_log(ql_log_warn, vha, 0x0069,
2749 "NVRAM configuration failed.\n");
4e08df3f
DM		 2750 }
2751 return (rval);
1da177e4
LT		 2752}
2753
19a7b4ae
JSEC		 2754static void
2755qla2x00_rport_del(void *data)
2756{
2757 fc_port_t *fcport = data;
d97994dc 2758 struct fc_rport *rport;
2d70c103 2759 scsi_qla_host_t *vha = fcport->vha;
044d78e1 2760 unsigned long flags;
d97994dc 2761
044d78e1 2762 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
ac280b67 2763 rport = fcport->drport ? fcport->drport: fcport->rport;
d97994dc 2764 fcport->drport = NULL;
044d78e1 2765 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
2d70c103 2766 if (rport) {
d97994dc 2767 fc_remote_port_delete(rport);
2d70c103
NB		 2768 /*
2769 * Release the target mode FC NEXUS in qla_target.c code
2770 * if target mod is enabled.
2771 */
2772 qlt_fc_port_deleted(vha, fcport);
2773 }
19a7b4ae
JSEC		 2774}
2775
1da177e4
LT		 2776/**
2777 * qla2x00_alloc_fcport() - Allocate a generic fcport.
2778 * @ha: HA context
2779 * @flags: allocation flags
2780 *
2781 * Returns a pointer to the allocated fcport, or NULL, if none available.
2782 */
9a069e19 2783fc_port_t *
e315cd28 2784qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags)
1da177e4
LT		 2785{
2786 fc_port_t *fcport;
2787
bbfbbbc1
MK		 2788 fcport = kzalloc(sizeof(fc_port_t), flags);
2789 if (!fcport)
2790 return NULL;
1da177e4
LT		 2791
2792 /* Setup fcport template structure. */
e315cd28 2793 fcport->vha = vha;
1da177e4
LT		 2794 fcport->port_type = FCT_UNKNOWN;
2795 fcport->loop_id = FC_NO_LOOP_ID;
ec426e10 2796 qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
ad3e0eda 2797 fcport->supported_classes = FC_COS_UNSPECIFIED;
1da177e4 2798
bbfbbbc1 2799 return fcport;
1da177e4
LT		 2800}
2801
2802/*
2803 * qla2x00_configure_loop
2804 * Updates Fibre Channel Device Database with what is actually on loop.
2805 *
2806 * Input:
2807 * ha = adapter block pointer.
2808 *
2809 * Returns:
2810 * 0 = success.
2811 * 1 = error.
2812 * 2 = database was full and device was not configured.
2813 */
2814static int
e315cd28 2815qla2x00_configure_loop(scsi_qla_host_t *vha)
1da177e4
LT		 2816{
2817 int rval;
2818 unsigned long flags, save_flags;
e315cd28 2819 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2820 rval = QLA_SUCCESS;
2821
2822 /* Get Initiator ID */
e315cd28
AC		 2823 if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) {
2824 rval = qla2x00_configure_hba(vha);
1da177e4 2825 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2826 ql_dbg(ql_dbg_disc, vha, 0x2013,
2827 "Unable to configure HBA.\n");
1da177e4
LT		 2828 return (rval);
2829 }
2830 }
2831
e315cd28 2832 save_flags = flags = vha->dpc_flags;
7c3df132
SK		 2833 ql_dbg(ql_dbg_disc, vha, 0x2014,
2834 "Configure loop -- dpc flags = 0x%lx.\n", flags);
1da177e4
LT		 2835
2836 /*
2837 * If we have both an RSCN and PORT UPDATE pending then handle them
2838 * both at the same time.
2839 */
e315cd28
AC		 2840 clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2841 clear_bit(RSCN_UPDATE, &vha->dpc_flags);
1da177e4 2842
3064ff39
MH		 2843 qla2x00_get_data_rate(vha);
2844
1da177e4
LT		 2845 /* Determine what we need to do */
2846 if (ha->current_topology == ISP_CFG_FL &&
2847 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
2848
1da177e4
LT		 2849 set_bit(RSCN_UPDATE, &flags);
2850
2851 } else if (ha->current_topology == ISP_CFG_F &&
2852 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
2853
1da177e4
LT		 2854 set_bit(RSCN_UPDATE, &flags);
2855 clear_bit(LOCAL_LOOP_UPDATE, &flags);
21333b48
AV		 2856
2857 } else if (ha->current_topology == ISP_CFG_N) {
2858 clear_bit(RSCN_UPDATE, &flags);
1da177e4 2859
e315cd28 2860 } else if (!vha->flags.online ||
1da177e4
LT		 2861 (test_bit(ABORT_ISP_ACTIVE, &flags))) {
2862
1da177e4
LT		 2863 set_bit(RSCN_UPDATE, &flags);
2864 set_bit(LOCAL_LOOP_UPDATE, &flags);
2865 }
2866
2867 if (test_bit(LOCAL_LOOP_UPDATE, &flags)) {
7c3df132
SK		 2868 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
2869 ql_dbg(ql_dbg_disc, vha, 0x2015,
2870 "Loop resync needed, failing.\n");
1da177e4 2871 rval = QLA_FUNCTION_FAILED;
642ef983 2872 } else
e315cd28 2873 rval = qla2x00_configure_local_loop(vha);
1da177e4
LT		 2874 }
2875
2876 if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
7c3df132
SK		 2877 if (LOOP_TRANSITION(vha)) {
2878 ql_dbg(ql_dbg_disc, vha, 0x201e,
2879 "Needs RSCN update and loop transition.\n");
1da177e4 2880 rval = QLA_FUNCTION_FAILED;
7c3df132 2881 }
e315cd28
AC		 2882 else
2883 rval = qla2x00_configure_fabric(vha);
1da177e4
LT		 2884 }
2885
2886 if (rval == QLA_SUCCESS) {
e315cd28
AC		 2887 if (atomic_read(&vha->loop_down_timer) ||
2888 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4
LT		 2889 rval = QLA_FUNCTION_FAILED;
2890 } else {
e315cd28 2891 atomic_set(&vha->loop_state, LOOP_READY);
7c3df132
SK		 2892 ql_dbg(ql_dbg_disc, vha, 0x2069,
2893 "LOOP READY.\n");
1da177e4
LT		 2894 }
2895 }
2896
2897 if (rval) {
7c3df132
SK		 2898 ql_dbg(ql_dbg_disc, vha, 0x206a,
2899 "%s *** FAILED ***.\n", __func__);
1da177e4 2900 } else {
7c3df132
SK		 2901 ql_dbg(ql_dbg_disc, vha, 0x206b,
2902 "%s: exiting normally.\n", __func__);
1da177e4
LT		 2903 }
2904
cc3ef7bc 2905 /* Restore state if a resync event occurred during processing */
e315cd28 2906 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4 2907 if (test_bit(LOCAL_LOOP_UPDATE, &save_flags))
e315cd28 2908 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
f4658b6c 2909 if (test_bit(RSCN_UPDATE, &save_flags)) {
e315cd28 2910 set_bit(RSCN_UPDATE, &vha->dpc_flags);
f4658b6c 2911 }
1da177e4
LT		 2912 }
2913
2914 return (rval);
2915}
2916
2917
2918
2919/*
2920 * qla2x00_configure_local_loop
2921 * Updates Fibre Channel Device Database with local loop devices.
2922 *
2923 * Input:
2924 * ha = adapter block pointer.
2925 *
2926 * Returns:
2927 * 0 = success.
2928 */
2929static int
e315cd28 2930qla2x00_configure_local_loop(scsi_qla_host_t *vha)
1da177e4
LT		 2931{
2932 int rval, rval2;
2933 int found_devs;
2934 int found;
2935 fc_port_t *fcport, *new_fcport;
2936
2937 uint16_t index;
2938 uint16_t entries;
2939 char *id_iter;
2940 uint16_t loop_id;
2941 uint8_t domain, area, al_pa;
e315cd28 2942 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2943
2944 found_devs = 0;
2945 new_fcport = NULL;
642ef983 2946 entries = MAX_FIBRE_DEVICES_LOOP;
1da177e4 2947
1da177e4 2948 /* Get list of logged in devices. */
642ef983 2949 memset(ha->gid_list, 0, qla2x00_gid_list_size(ha));
e315cd28 2950 rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma,
1da177e4
LT		 2951 &entries);
2952 if (rval != QLA_SUCCESS)
2953 goto cleanup_allocation;
2954
7c3df132
SK		 2955 ql_dbg(ql_dbg_disc, vha, 0x2017,
2956 "Entries in ID list (%d).\n", entries);
2957 ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
2958 (uint8_t *)ha->gid_list,
2959 entries * sizeof(struct gid_list_info));
1da177e4
LT		 2960
2961 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 2962 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 2963 if (new_fcport == NULL) {
7c3df132
SK		 2964 ql_log(ql_log_warn, vha, 0x2018,
2965 "Memory allocation failed for fcport.\n");
1da177e4
LT		 2966 rval = QLA_MEMORY_ALLOC_FAILED;
2967 goto cleanup_allocation;
2968 }
2969 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
2970
2971 /*
2972 * Mark local devices that were present with FCF_DEVICE_LOST for now.
2973 */
e315cd28 2974 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 2975 if (atomic_read(&fcport->state) == FCS_ONLINE &&
2976 fcport->port_type != FCT_BROADCAST &&
2977 (fcport->flags & FCF_FABRIC_DEVICE) == 0) {
2978
7c3df132
SK		 2979 ql_dbg(ql_dbg_disc, vha, 0x2019,
2980 "Marking port lost loop_id=0x%04x.\n",
2981 fcport->loop_id);
1da177e4 2982
ec426e10 2983 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 2984 }
2985 }
2986
2987 /* Add devices to port list. */
2988 id_iter = (char *)ha->gid_list;
2989 for (index = 0; index < entries; index++) {
2990 domain = ((struct gid_list_info *)id_iter)->domain;
2991 area = ((struct gid_list_info *)id_iter)->area;
2992 al_pa = ((struct gid_list_info *)id_iter)->al_pa;
abbd8870 2993 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1da177e4
LT		 2994 loop_id = (uint16_t)
2995 ((struct gid_list_info *)id_iter)->loop_id_2100;
abbd8870 2996 else
1da177e4
LT		 2997 loop_id = le16_to_cpu(
2998 ((struct gid_list_info *)id_iter)->loop_id);
abbd8870 2999 id_iter += ha->gid_list_info_size;
1da177e4
LT		 3000
3001 /* Bypass reserved domain fields. */
3002 if ((domain & 0xf0) == 0xf0)
3003 continue;
3004
3005 /* Bypass if not same domain and area of adapter. */
f7d289f6 3006 if (area && domain &&
e315cd28 3007 (area != vha->d_id.b.area || domain != vha->d_id.b.domain))
1da177e4
LT		 3008 continue;
3009
3010 /* Bypass invalid local loop ID. */
3011 if (loop_id > LAST_LOCAL_LOOP_ID)
3012 continue;
3013
370d550e
AE		 3014 memset(new_fcport, 0, sizeof(fc_port_t));
3015
1da177e4
LT		 3016 /* Fill in member data. */
3017 new_fcport->d_id.b.domain = domain;
3018 new_fcport->d_id.b.area = area;
3019 new_fcport->d_id.b.al_pa = al_pa;
3020 new_fcport->loop_id = loop_id;
e315cd28 3021 rval2 = qla2x00_get_port_database(vha, new_fcport, 0);
1da177e4 3022 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 3023 ql_dbg(ql_dbg_disc, vha, 0x201a,
3024 "Failed to retrieve fcport information "
3025 "-- get_port_database=%x, loop_id=0x%04x.\n",
3026 rval2, new_fcport->loop_id);
3027 ql_dbg(ql_dbg_disc, vha, 0x201b,
3028 "Scheduling resync.\n");
e315cd28 3029 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4
LT		 3030 continue;
3031 }
3032
3033 /* Check for matching device in port list. */
3034 found = 0;
3035 fcport = NULL;
e315cd28 3036 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 3037 if (memcmp(new_fcport->port_name, fcport->port_name,
3038 WWN_SIZE))
3039 continue;
3040
ddb9b126 3041 fcport->flags &= ~FCF_FABRIC_DEVICE;
1da177e4
LT		 3042 fcport->loop_id = new_fcport->loop_id;
3043 fcport->port_type = new_fcport->port_type;
3044 fcport->d_id.b24 = new_fcport->d_id.b24;
3045 memcpy(fcport->node_name, new_fcport->node_name,
3046 WWN_SIZE);
3047
3048 found++;
3049 break;
3050 }
3051
3052 if (!found) {
3053 /* New device, add to fcports list. */
e315cd28 3054 list_add_tail(&new_fcport->list, &vha->vp_fcports);
1da177e4
LT		 3055
3056 /* Allocate a new replacement fcport. */
3057 fcport = new_fcport;
e315cd28 3058 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3059 if (new_fcport == NULL) {
7c3df132
SK		 3060 ql_log(ql_log_warn, vha, 0x201c,
3061 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 3062 rval = QLA_MEMORY_ALLOC_FAILED;
3063 goto cleanup_allocation;
3064 }
3065 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
3066 }
3067
d8b45213 3068 /* Base iIDMA settings on HBA port speed. */
a3cbdfad 3069 fcport->fp_speed = ha->link_data_rate;
d8b45213 3070
e315cd28 3071 qla2x00_update_fcport(vha, fcport);
1da177e4
LT		 3072
3073 found_devs++;
3074 }
3075
3076cleanup_allocation:
c9475cb0 3077 kfree(new_fcport);
1da177e4
LT		 3078
3079 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3080 ql_dbg(ql_dbg_disc, vha, 0x201d,
3081 "Configure local loop error exit: rval=%x.\n", rval);
1da177e4
LT		 3082 }
3083
1da177e4
LT		 3084 return (rval);
3085}
3086
d8b45213 3087static void
e315cd28 3088qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
d8b45213 3089{
d8b45213 3090 int rval;
1bb39548 3091 uint16_t mb[4];
e315cd28 3092 struct qla_hw_data *ha = vha->hw;
d8b45213 3093
c76f2c01 3094 if (!IS_IIDMA_CAPABLE(ha))
d8b45213
AV		 3095 return;
3096
c9afb9a2
GM		 3097 if (atomic_read(&fcport->state) != FCS_ONLINE)
3098 return;
3099
39bd9622
AV		 3100 if (fcport->fp_speed == PORT_SPEED_UNKNOWN ||
3101 fcport->fp_speed > ha->link_data_rate)
d8b45213
AV		 3102 return;
3103
e315cd28 3104 rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed,
a3cbdfad 3105 mb);
d8b45213 3106 if (rval != QLA_SUCCESS) {
7c3df132 3107 ql_dbg(ql_dbg_disc, vha, 0x2004,
7b833558
OK		 3108 "Unable to adjust iIDMA %8phN -- %04x %x %04x %04x.\n",
3109 fcport->port_name, rval, fcport->fp_speed, mb[0], mb[1]);
d8b45213 3110 } else {
7c3df132 3111 ql_dbg(ql_dbg_disc, vha, 0x2005,
7b833558 3112 "iIDMA adjusted to %s GB/s on %8phN.\n",
d0297c9a 3113 qla2x00_get_link_speed_str(ha, fcport->fp_speed),
7b833558 3114 fcport->port_name);
d8b45213
AV		 3115 }
3116}
3117
23be331d 3118static void
e315cd28 3119qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport)
8482e118
AV		 3120{
3121 struct fc_rport_identifiers rport_ids;
bdf79621 3122 struct fc_rport *rport;
044d78e1 3123 unsigned long flags;
8482e118 3124
ac280b67 3125 qla2x00_rport_del(fcport);
8482e118 3126
f8b02a85
AV		 3127 rport_ids.node_name = wwn_to_u64(fcport->node_name);
3128 rport_ids.port_name = wwn_to_u64(fcport->port_name);
8482e118
AV		 3129 rport_ids.port_id = fcport->d_id.b.domain << 16 |
3130 fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa;
77d74143 3131 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
e315cd28 3132 fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids);
77d74143 3133 if (!rport) {
7c3df132
SK		 3134 ql_log(ql_log_warn, vha, 0x2006,
3135 "Unable to allocate fc remote port.\n");
77d74143
AV		 3136 return;
3137 }
2d70c103
NB		 3138 /*
3139 * Create target mode FC NEXUS in qla_target.c if target mode is
3140 * enabled..
3141 */
3142 qlt_fc_port_added(vha, fcport);
3143
044d78e1 3144 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
19a7b4ae 3145 *((fc_port_t **)rport->dd_data) = fcport;
044d78e1 3146 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
d97994dc 3147
ad3e0eda 3148 rport->supported_classes = fcport->supported_classes;
77d74143 3149
8482e118
AV		 3150 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
3151 if (fcport->port_type == FCT_INITIATOR)
3152 rport_ids.roles |= FC_RPORT_ROLE_FCP_INITIATOR;
3153 if (fcport->port_type == FCT_TARGET)
3154 rport_ids.roles |= FC_RPORT_ROLE_FCP_TARGET;
77d74143 3155 fc_remote_port_rolechg(rport, rport_ids.roles);
1da177e4
LT		 3156}
3157
23be331d
AB		 3158/*
3159 * qla2x00_update_fcport
3160 * Updates device on list.
3161 *
3162 * Input:
3163 * ha = adapter block pointer.
3164 * fcport = port structure pointer.
3165 *
3166 * Return:
3167 * 0 - Success
3168 * BIT_0 - error
3169 *
3170 * Context:
3171 * Kernel context.
3172 */
3173void
e315cd28 3174qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
23be331d 3175{
e315cd28 3176 fcport->vha = vha;
8ae6d9c7
GM		 3177
3178 if (IS_QLAFX00(vha->hw)) {
3179 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
3180 qla2x00_reg_remote_port(vha, fcport);
3181 return;
3182 }
23be331d 3183 fcport->login_retry = 0;
5ff1d584 3184 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
23be331d 3185
1f93da52 3186 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
e315cd28 3187 qla2x00_iidma_fcport(vha, fcport);
21090cbe 3188 qla24xx_update_fcport_fcp_prio(vha, fcport);
e315cd28 3189 qla2x00_reg_remote_port(vha, fcport);
23be331d
AB		 3190}
3191
1da177e4
LT		 3192/*
3193 * qla2x00_configure_fabric
3194 * Setup SNS devices with loop ID's.
3195 *
3196 * Input:
3197 * ha = adapter block pointer.
3198 *
3199 * Returns:
3200 * 0 = success.
3201 * BIT_0 = error
3202 */
3203static int
e315cd28 3204qla2x00_configure_fabric(scsi_qla_host_t *vha)
1da177e4 3205{
b3b02e6e 3206 int rval;
e452ceb6 3207 fc_port_t *fcport, *fcptemp;
1da177e4
LT		 3208 uint16_t next_loopid;
3209 uint16_t mb[MAILBOX_REGISTER_COUNT];
0107109e 3210 uint16_t loop_id;
1da177e4 3211 LIST_HEAD(new_fcports);
e315cd28
AC		 3212 struct qla_hw_data *ha = vha->hw;
3213 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 3214
3215 /* If FL port exists, then SNS is present */
e428924c 3216 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 3217 loop_id = NPH_F_PORT;
3218 else
3219 loop_id = SNS_FL_PORT;
e315cd28 3220 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1);
1da177e4 3221 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3222 ql_dbg(ql_dbg_disc, vha, 0x201f,
3223 "MBX_GET_PORT_NAME failed, No FL Port.\n");
1da177e4 3224
e315cd28 3225 vha->device_flags &= ~SWITCH_FOUND;
1da177e4
LT		 3226 return (QLA_SUCCESS);
3227 }
e315cd28 3228 vha->device_flags |= SWITCH_FOUND;
1da177e4 3229
1da177e4 3230 do {
cca5335c
AV		 3231 /* FDMI support. */
3232 if (ql2xfdmienable &&
e315cd28
AC		 3233 test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags))
3234 qla2x00_fdmi_register(vha);
cca5335c 3235
1da177e4 3236 /* Ensure we are logged into the SNS. */
e428924c 3237 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 3238 loop_id = NPH_SNS;
3239 else
3240 loop_id = SIMPLE_NAME_SERVER;
0b91d116
CD		 3241 rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff,
3242 0xfc, mb, BIT_1|BIT_0);
3243 if (rval != QLA_SUCCESS) {
3244 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
e452ceb6 3245 return rval;
0b91d116 3246 }
1da177e4 3247 if (mb[0] != MBS_COMMAND_COMPLETE) {
7c3df132
SK		 3248 ql_dbg(ql_dbg_disc, vha, 0x2042,
3249 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x "
3250 "mb[6]=%x mb[7]=%x.\n", loop_id, mb[0], mb[1],
3251 mb[2], mb[6], mb[7]);
1da177e4
LT		 3252 return (QLA_SUCCESS);
3253 }
3254
e315cd28
AC		 3255 if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) {
3256 if (qla2x00_rft_id(vha)) {
1da177e4 3257 /* EMPTY */
7c3df132
SK		 3258 ql_dbg(ql_dbg_disc, vha, 0x2045,
3259 "Register FC-4 TYPE failed.\n");
1da177e4 3260 }
e315cd28 3261 if (qla2x00_rff_id(vha)) {
1da177e4 3262 /* EMPTY */
7c3df132
SK		 3263 ql_dbg(ql_dbg_disc, vha, 0x2049,
3264 "Register FC-4 Features failed.\n");
1da177e4 3265 }
e315cd28 3266 if (qla2x00_rnn_id(vha)) {
1da177e4 3267 /* EMPTY */
7c3df132
SK		 3268 ql_dbg(ql_dbg_disc, vha, 0x204f,
3269 "Register Node Name failed.\n");
e315cd28 3270 } else if (qla2x00_rsnn_nn(vha)) {
1da177e4 3271 /* EMPTY */
7c3df132
SK		 3272 ql_dbg(ql_dbg_disc, vha, 0x2053,
3273 "Register Symobilic Node Name failed.\n");
1da177e4
LT		 3274 }
3275 }
3276
827210ba
JC		 3277#define QLA_FCPORT_SCAN 1
3278#define QLA_FCPORT_FOUND 2
3279
3280 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3281 fcport->scan_state = QLA_FCPORT_SCAN;
3282 }
3283
e315cd28 3284 rval = qla2x00_find_all_fabric_devs(vha, &new_fcports);
1da177e4
LT		 3285 if (rval != QLA_SUCCESS)
3286 break;
3287
e452ceb6
JC		 3288 /*
3289 * Logout all previous fabric devices marked lost, except
3290 * FCP2 devices.
3291 */
e315cd28
AC		 3292 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3293 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
1da177e4
LT		 3294 break;
3295
3296 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0)
3297 continue;
3298
827210ba 3299 if (fcport->scan_state == QLA_FCPORT_SCAN &&
b3b02e6e 3300 atomic_read(&fcport->state) == FCS_ONLINE) {
e315cd28 3301 qla2x00_mark_device_lost(vha, fcport,
d97994dc 3302 ql2xplogiabsentdevice, 0);
1da177e4 3303 if (fcport->loop_id != FC_NO_LOOP_ID &&
f08b7251 3304 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
1da177e4
LT		 3305 fcport->port_type != FCT_INITIATOR &&
3306 fcport->port_type != FCT_BROADCAST) {
e315cd28 3307 ha->isp_ops->fabric_logout(vha,
1c7c6357
AV		 3308 fcport->loop_id,
3309 fcport->d_id.b.domain,
3310 fcport->d_id.b.area,
3311 fcport->d_id.b.al_pa);
e452ceb6 3312 fcport->loop_id = FC_NO_LOOP_ID;
1da177e4
LT		 3313 }
3314 }
e452ceb6 3315 }
1da177e4 3316
e452ceb6
JC		 3317 /* Starting free loop ID. */
3318 next_loopid = ha->min_external_loopid;
3319
3320 /*
3321 * Scan through our port list and login entries that need to be
3322 * logged in.
3323 */
3324 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3325 if (atomic_read(&vha->loop_down_timer) ||
3326 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3327 break;
3328
3329 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0 ||
3330 (fcport->flags & FCF_LOGIN_NEEDED) == 0)
3331 continue;
3332
3333 if (fcport->loop_id == FC_NO_LOOP_ID) {
3334 fcport->loop_id = next_loopid;
3335 rval = qla2x00_find_new_loop_id(
3336 base_vha, fcport);
3337 if (rval != QLA_SUCCESS) {
3338 /* Ran out of IDs to use */
3339 break;
1da177e4
LT		 3340 }
3341 }
e452ceb6
JC		 3342 /* Login and update database */
3343 qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
3344 }
3345
3346 /* Exit if out of loop IDs. */
3347 if (rval != QLA_SUCCESS) {
3348 break;
3349 }
3350
3351 /*
3352 * Login and add the new devices to our port list.
3353 */
3354 list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) {
3355 if (atomic_read(&vha->loop_down_timer) ||
3356 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3357 break;
3358
3359 /* Find a new loop ID to use. */
3360 fcport->loop_id = next_loopid;
3361 rval = qla2x00_find_new_loop_id(base_vha, fcport);
3362 if (rval != QLA_SUCCESS) {
3363 /* Ran out of IDs to use */
3364 break;
3365 }
1da177e4 3366
bdf79621 3367 /* Login and update database */
e315cd28 3368 qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
e452ceb6
JC		 3369
3370 list_move_tail(&fcport->list, &vha->vp_fcports);
1da177e4
LT		 3371 }
3372 } while (0);
3373
e452ceb6
JC		 3374 /* Free all new device structures not processed. */
3375 list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) {
3376 list_del(&fcport->list);
3377 kfree(fcport);
3378 }
3379
1da177e4 3380 if (rval) {
7c3df132
SK		 3381 ql_dbg(ql_dbg_disc, vha, 0x2068,
3382 "Configure fabric error exit rval=%d.\n", rval);
1da177e4
LT		 3383 }
3384
3385 return (rval);
3386}
3387
1da177e4
LT		 3388/*
3389 * qla2x00_find_all_fabric_devs
3390 *
3391 * Input:
3392 * ha = adapter block pointer.
3393 * dev = database device entry pointer.
3394 *
3395 * Returns:
3396 * 0 = success.
3397 *
3398 * Context:
3399 * Kernel context.
3400 */
3401static int
e315cd28
AC		 3402qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha,
3403 struct list_head *new_fcports)
1da177e4
LT		 3404{
3405 int rval;
3406 uint16_t loop_id;
3407 fc_port_t *fcport, *new_fcport, *fcptemp;
3408 int found;
3409
3410 sw_info_t *swl;
3411 int swl_idx;
3412 int first_dev, last_dev;
1516ef44 3413 port_id_t wrap = {}, nxt_d_id;
e315cd28 3414 struct qla_hw_data *ha = vha->hw;
bb4cf5b7 3415 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 3416
3417 rval = QLA_SUCCESS;
3418
3419 /* Try GID_PT to get device list, else GAN. */
7a67735b 3420 if (!ha->swl)
642ef983 3421 ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t),
7a67735b
AV		 3422 GFP_KERNEL);
3423 swl = ha->swl;
bbfbbbc1 3424 if (!swl) {
1da177e4 3425 /*EMPTY*/
7c3df132
SK		 3426 ql_dbg(ql_dbg_disc, vha, 0x2054,
3427 "GID_PT allocations failed, fallback on GA_NXT.\n");
1da177e4 3428 } else {
642ef983 3429 memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t));
e315cd28 3430 if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) {
1da177e4 3431 swl = NULL;
e315cd28 3432 } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 3433 swl = NULL;
e315cd28 3434 } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 3435 swl = NULL;
e5896bd5 3436 } else if (ql2xiidmaenable &&
e315cd28
AC		 3437 qla2x00_gfpn_id(vha, swl) == QLA_SUCCESS) {
3438 qla2x00_gpsc(vha, swl);
1da177e4 3439 }
e8c72ba5
CD		 3440
3441 /* If other queries succeeded probe for FC-4 type */
3442 if (swl)
3443 qla2x00_gff_id(vha, swl);
1da177e4
LT		 3444 }
3445 swl_idx = 0;
3446
3447 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 3448 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3449 if (new_fcport == NULL) {
7c3df132
SK		 3450 ql_log(ql_log_warn, vha, 0x205e,
3451 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 3452 return (QLA_MEMORY_ALLOC_FAILED);
3453 }
3454 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
1da177e4
LT		 3455 /* Set start port ID scan at adapter ID. */
3456 first_dev = 1;
3457 last_dev = 0;
3458
3459 /* Starting free loop ID. */
e315cd28
AC		 3460 loop_id = ha->min_external_loopid;
3461 for (; loop_id <= ha->max_loop_id; loop_id++) {
3462 if (qla2x00_is_reserved_id(vha, loop_id))
1da177e4
LT		 3463 continue;
3464
3a6478df
GM		 3465 if (ha->current_topology == ISP_CFG_FL &&
3466 (atomic_read(&vha->loop_down_timer) ||
3467 LOOP_TRANSITION(vha))) {
bb2d52b2
AV		 3468 atomic_set(&vha->loop_down_timer, 0);
3469 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
3470 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
1da177e4 3471 break;
bb2d52b2 3472 }
1da177e4
LT		 3473
3474 if (swl != NULL) {
3475 if (last_dev) {
3476 wrap.b24 = new_fcport->d_id.b24;
3477 } else {
3478 new_fcport->d_id.b24 = swl[swl_idx].d_id.b24;
3479 memcpy(new_fcport->node_name,
3480 swl[swl_idx].node_name, WWN_SIZE);
3481 memcpy(new_fcport->port_name,
3482 swl[swl_idx].port_name, WWN_SIZE);
d8b45213
AV		 3483 memcpy(new_fcport->fabric_port_name,
3484 swl[swl_idx].fabric_port_name, WWN_SIZE);
3485 new_fcport->fp_speed = swl[swl_idx].fp_speed;
e8c72ba5 3486 new_fcport->fc4_type = swl[swl_idx].fc4_type;
1da177e4
LT		 3487
3488 if (swl[swl_idx].d_id.b.rsvd_1 != 0) {
3489 last_dev = 1;
3490 }
3491 swl_idx++;
3492 }
3493 } else {
3494 /* Send GA_NXT to the switch */
e315cd28 3495 rval = qla2x00_ga_nxt(vha, new_fcport);
1da177e4 3496 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3497 ql_log(ql_log_warn, vha, 0x2064,
3498 "SNS scan failed -- assuming "
3499 "zero-entry result.\n");
1da177e4
LT		 3500 list_for_each_entry_safe(fcport, fcptemp,
3501 new_fcports, list) {
3502 list_del(&fcport->list);
3503 kfree(fcport);
3504 }
3505 rval = QLA_SUCCESS;
3506 break;
3507 }
3508 }
3509
3510 /* If wrap on switch device list, exit. */
3511 if (first_dev) {
3512 wrap.b24 = new_fcport->d_id.b24;
3513 first_dev = 0;
3514 } else if (new_fcport->d_id.b24 == wrap.b24) {
7c3df132
SK		 3515 ql_dbg(ql_dbg_disc, vha, 0x2065,
3516 "Device wrap (%02x%02x%02x).\n",
3517 new_fcport->d_id.b.domain,
3518 new_fcport->d_id.b.area,
3519 new_fcport->d_id.b.al_pa);
1da177e4
LT		 3520 break;
3521 }
3522
2c3dfe3f 3523 /* Bypass if same physical adapter. */
e315cd28 3524 if (new_fcport->d_id.b24 == base_vha->d_id.b24)
1da177e4
LT		 3525 continue;
3526
2c3dfe3f 3527 /* Bypass virtual ports of the same host. */
bb4cf5b7
CD		 3528 if (qla2x00_is_a_vp_did(vha, new_fcport->d_id.b24))
3529 continue;
2c3dfe3f 3530
f7d289f6
AV		 3531 /* Bypass if same domain and area of adapter. */
3532 if (((new_fcport->d_id.b24 & 0xffff00) ==
e315cd28 3533 (vha->d_id.b24 & 0xffff00)) && ha->current_topology ==
f7d289f6
AV		 3534 ISP_CFG_FL)
3535 continue;
3536
1da177e4
LT		 3537 /* Bypass reserved domain fields. */
3538 if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0)
3539 continue;
3540
e8c72ba5 3541 /* Bypass ports whose FCP-4 type is not FCP_SCSI */
4da26e16
CD		 3542 if (ql2xgffidenable &&
3543 (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI &&
3544 new_fcport->fc4_type != FC4_TYPE_UNKNOWN))
e8c72ba5
CD		 3545 continue;
3546
1da177e4
LT		 3547 /* Locate matching device in database. */
3548 found = 0;
e315cd28 3549 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 3550 if (memcmp(new_fcport->port_name, fcport->port_name,
3551 WWN_SIZE))
3552 continue;
3553
827210ba 3554 fcport->scan_state = QLA_FCPORT_FOUND;
b3b02e6e 3555
1da177e4
LT		 3556 found++;
3557
d8b45213
AV		 3558 /* Update port state. */
3559 memcpy(fcport->fabric_port_name,
3560 new_fcport->fabric_port_name, WWN_SIZE);
3561 fcport->fp_speed = new_fcport->fp_speed;
3562
1da177e4
LT		 3563 /*
3564 * If address the same and state FCS_ONLINE, nothing
3565 * changed.
3566 */
3567 if (fcport->d_id.b24 == new_fcport->d_id.b24 &&
3568 atomic_read(&fcport->state) == FCS_ONLINE) {
3569 break;
3570 }
3571
3572 /*
3573 * If device was not a fabric device before.
3574 */
3575 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) {
3576 fcport->d_id.b24 = new_fcport->d_id.b24;
5f16b331 3577 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 3578 fcport->flags |= (FCF_FABRIC_DEVICE |
3579 FCF_LOGIN_NEEDED);
1da177e4
LT		 3580 break;
3581 }
3582
3583 /*
3584 * Port ID changed or device was marked to be updated;
3585 * Log it out if still logged in and mark it for
3586 * relogin later.
3587 */
3588 fcport->d_id.b24 = new_fcport->d_id.b24;
3589 fcport->flags |= FCF_LOGIN_NEEDED;
3590 if (fcport->loop_id != FC_NO_LOOP_ID &&
f08b7251 3591 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
0eba25df 3592 (fcport->flags & FCF_ASYNC_SENT) == 0 &&
1da177e4
LT		 3593 fcport->port_type != FCT_INITIATOR &&
3594 fcport->port_type != FCT_BROADCAST) {
e315cd28 3595 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3596 fcport->d_id.b.domain, fcport->d_id.b.area,
3597 fcport->d_id.b.al_pa);
5f16b331 3598 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 3599 }
3600
3601 break;
3602 }
3603
3604 if (found)
3605 continue;
1da177e4
LT		 3606 /* If device was not in our fcports list, then add it. */
3607 list_add_tail(&new_fcport->list, new_fcports);
3608
3609 /* Allocate a new replacement fcport. */
3610 nxt_d_id.b24 = new_fcport->d_id.b24;
e315cd28 3611 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3612 if (new_fcport == NULL) {
7c3df132
SK		 3613 ql_log(ql_log_warn, vha, 0x2066,
3614 "Memory allocation failed for fcport.\n");
1da177e4
LT		 3615 return (QLA_MEMORY_ALLOC_FAILED);
3616 }
3617 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
3618 new_fcport->d_id.b24 = nxt_d_id.b24;
3619 }
3620
c9475cb0 3621 kfree(new_fcport);
1da177e4 3622
1da177e4
LT		 3623 return (rval);
3624}
3625
3626/*
3627 * qla2x00_find_new_loop_id
3628 * Scan through our port list and find a new usable loop ID.
3629 *
3630 * Input:
3631 * ha: adapter state pointer.
3632 * dev: port structure pointer.
3633 *
3634 * Returns:
3635 * qla2x00 local function return status code.
3636 *
3637 * Context:
3638 * Kernel context.
3639 */
03bcfb57 3640int
e315cd28 3641qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
1da177e4
LT		 3642{
3643 int rval;
e315cd28 3644 struct qla_hw_data *ha = vha->hw;
feafb7b1 3645 unsigned long flags = 0;
1da177e4
LT		 3646
3647 rval = QLA_SUCCESS;
3648
5f16b331 3649 spin_lock_irqsave(&ha->vport_slock, flags);
1da177e4 3650
5f16b331
CD		 3651 dev->loop_id = find_first_zero_bit(ha->loop_id_map,
3652 LOOPID_MAP_SIZE);
3653 if (dev->loop_id >= LOOPID_MAP_SIZE ||
3654 qla2x00_is_reserved_id(vha, dev->loop_id)) {
3655 dev->loop_id = FC_NO_LOOP_ID;
3656 rval = QLA_FUNCTION_FAILED;
3657 } else
3658 set_bit(dev->loop_id, ha->loop_id_map);
1da177e4 3659
5f16b331 3660 spin_unlock_irqrestore(&ha->vport_slock, flags);
1da177e4 3661
5f16b331
CD		 3662 if (rval == QLA_SUCCESS)
3663 ql_dbg(ql_dbg_disc, dev->vha, 0x2086,
3664 "Assigning new loopid=%x, portid=%x.\n",
3665 dev->loop_id, dev->d_id.b24);
3666 else
3667 ql_log(ql_log_warn, dev->vha, 0x2087,
3668 "No loop_id's available, portid=%x.\n",
3669 dev->d_id.b24);
1da177e4
LT		 3670
3671 return (rval);
3672}
3673
1da177e4
LT		 3674/*
3675 * qla2x00_fabric_dev_login
3676 * Login fabric target device and update FC port database.
3677 *
3678 * Input:
3679 * ha: adapter state pointer.
3680 * fcport: port structure list pointer.
3681 * next_loopid: contains value of a new loop ID that can be used
3682 * by the next login attempt.
3683 *
3684 * Returns:
3685 * qla2x00 local function return status code.
3686 *
3687 * Context:
3688 * Kernel context.
3689 */
3690static int
e315cd28 3691qla2x00_fabric_dev_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 3692 uint16_t *next_loopid)
3693{
3694 int rval;
3695 int retry;
0107109e 3696 uint8_t opts;
e315cd28 3697 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3698
3699 rval = QLA_SUCCESS;
3700 retry = 0;
3701
ac280b67 3702 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584
AV		 3703 if (fcport->flags & FCF_ASYNC_SENT)
3704 return rval;
3705 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 3706 rval = qla2x00_post_async_login_work(vha, fcport, NULL);
3707 if (!rval)
3708 return rval;
3709 }
3710
5ff1d584 3711 fcport->flags &= ~FCF_ASYNC_SENT;
e315cd28 3712 rval = qla2x00_fabric_login(vha, fcport, next_loopid);
1da177e4 3713 if (rval == QLA_SUCCESS) {
f08b7251 3714 /* Send an ADISC to FCP2 devices.*/
0107109e 3715 opts = 0;
f08b7251 3716 if (fcport->flags & FCF_FCP2_DEVICE)
0107109e 3717 opts |= BIT_1;
e315cd28 3718 rval = qla2x00_get_port_database(vha, fcport, opts);
1da177e4 3719 if (rval != QLA_SUCCESS) {
e315cd28 3720 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3721 fcport->d_id.b.domain, fcport->d_id.b.area,
3722 fcport->d_id.b.al_pa);
e315cd28 3723 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4 3724 } else {
e315cd28 3725 qla2x00_update_fcport(vha, fcport);
1da177e4 3726 }
0b91d116
CD		 3727 } else {
3728 /* Retry Login. */
3729 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 3730 }
3731
3732 return (rval);
3733}
3734
3735/*
3736 * qla2x00_fabric_login
3737 * Issue fabric login command.
3738 *
3739 * Input:
3740 * ha = adapter block pointer.
3741 * device = pointer to FC device type structure.
3742 *
3743 * Returns:
3744 * 0 - Login successfully
3745 * 1 - Login failed
3746 * 2 - Initiator device
3747 * 3 - Fatal error
3748 */
3749int
e315cd28 3750qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 3751 uint16_t *next_loopid)
3752{
3753 int rval;
3754 int retry;
3755 uint16_t tmp_loopid;
3756 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 3757 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3758
3759 retry = 0;
3760 tmp_loopid = 0;
3761
3762 for (;;) {
7c3df132
SK		 3763 ql_dbg(ql_dbg_disc, vha, 0x2000,
3764 "Trying Fabric Login w/loop id 0x%04x for port "
3765 "%02x%02x%02x.\n",
3766 fcport->loop_id, fcport->d_id.b.domain,
3767 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 3768
3769 /* Login fcport on switch. */
0b91d116 3770 rval = ha->isp_ops->fabric_login(vha, fcport->loop_id,
1da177e4
LT		 3771 fcport->d_id.b.domain, fcport->d_id.b.area,
3772 fcport->d_id.b.al_pa, mb, BIT_0);
0b91d116
CD		 3773 if (rval != QLA_SUCCESS) {
3774 return rval;
3775 }
1da177e4
LT		 3776 if (mb[0] == MBS_PORT_ID_USED) {
3777 /*
3778 * Device has another loop ID. The firmware team
0107109e
AV		 3779 * recommends the driver perform an implicit login with
3780 * the specified ID again. The ID we just used is save
3781 * here so we return with an ID that can be tried by
3782 * the next login.
1da177e4
LT		 3783 */
3784 retry++;
3785 tmp_loopid = fcport->loop_id;
3786 fcport->loop_id = mb[1];
3787
7c3df132
SK		 3788 ql_dbg(ql_dbg_disc, vha, 0x2001,
3789 "Fabric Login: port in use - next loop "
3790 "id=0x%04x, port id= %02x%02x%02x.\n",
1da177e4 3791 fcport->loop_id, fcport->d_id.b.domain,
7c3df132 3792 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 3793
3794 } else if (mb[0] == MBS_COMMAND_COMPLETE) {
3795 /*
3796 * Login succeeded.
3797 */
3798 if (retry) {
3799 /* A retry occurred before. */
3800 *next_loopid = tmp_loopid;
3801 } else {
3802 /*
3803 * No retry occurred before. Just increment the
3804 * ID value for next login.
3805 */
3806 *next_loopid = (fcport->loop_id + 1);
3807 }
3808
3809 if (mb[1] & BIT_0) {
3810 fcport->port_type = FCT_INITIATOR;
3811 } else {
3812 fcport->port_type = FCT_TARGET;
3813 if (mb[1] & BIT_1) {
8474f3a0 3814 fcport->flags |= FCF_FCP2_DEVICE;
1da177e4
LT		 3815 }
3816 }
3817
ad3e0eda
AV		 3818 if (mb[10] & BIT_0)
3819 fcport->supported_classes |= FC_COS_CLASS2;
3820 if (mb[10] & BIT_1)
3821 fcport->supported_classes |= FC_COS_CLASS3;
3822
2d70c103
NB		 3823 if (IS_FWI2_CAPABLE(ha)) {
3824 if (mb[10] & BIT_7)
3825 fcport->flags |=
3826 FCF_CONF_COMP_SUPPORTED;
3827 }
3828
1da177e4
LT		 3829 rval = QLA_SUCCESS;
3830 break;
3831 } else if (mb[0] == MBS_LOOP_ID_USED) {
3832 /*
3833 * Loop ID already used, try next loop ID.
3834 */
3835 fcport->loop_id++;
e315cd28 3836 rval = qla2x00_find_new_loop_id(vha, fcport);
1da177e4
LT		 3837 if (rval != QLA_SUCCESS) {
3838 /* Ran out of loop IDs to use */
3839 break;
3840 }
3841 } else if (mb[0] == MBS_COMMAND_ERROR) {
3842 /*
3843 * Firmware possibly timed out during login. If NO
3844 * retries are left to do then the device is declared
3845 * dead.
3846 */
3847 *next_loopid = fcport->loop_id;
e315cd28 3848 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3849 fcport->d_id.b.domain, fcport->d_id.b.area,
3850 fcport->d_id.b.al_pa);
e315cd28 3851 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 3852
3853 rval = 1;
3854 break;
3855 } else {
3856 /*
3857 * unrecoverable / not handled error
3858 */
7c3df132
SK		 3859 ql_dbg(ql_dbg_disc, vha, 0x2002,
3860 "Failed=%x port_id=%02x%02x%02x loop_id=%x "
3861 "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain,
3862 fcport->d_id.b.area, fcport->d_id.b.al_pa,
3863 fcport->loop_id, jiffies);
1da177e4
LT		 3864
3865 *next_loopid = fcport->loop_id;
e315cd28 3866 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3867 fcport->d_id.b.domain, fcport->d_id.b.area,
3868 fcport->d_id.b.al_pa);
5f16b331 3869 qla2x00_clear_loop_id(fcport);
0eedfcf0 3870 fcport->login_retry = 0;
1da177e4
LT		 3871
3872 rval = 3;
3873 break;
3874 }
3875 }
3876
3877 return (rval);
3878}
3879
3880/*
3881 * qla2x00_local_device_login
3882 * Issue local device login command.
3883 *
3884 * Input:
3885 * ha = adapter block pointer.
3886 * loop_id = loop id of device to login to.
3887 *
3888 * Returns (Where's the #define!!!!):
3889 * 0 - Login successfully
3890 * 1 - Login failed
3891 * 3 - Fatal error
3892 */
3893int
e315cd28 3894qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport)
1da177e4
LT		 3895{
3896 int rval;
3897 uint16_t mb[MAILBOX_REGISTER_COUNT];
3898
3899 memset(mb, 0, sizeof(mb));
e315cd28 3900 rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0);
1da177e4
LT		 3901 if (rval == QLA_SUCCESS) {
3902 /* Interrogate mailbox registers for any errors */
3903 if (mb[0] == MBS_COMMAND_ERROR)
3904 rval = 1;
3905 else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR)
3906 /* device not in PCB table */
3907 rval = 3;
3908 }
3909
3910 return (rval);
3911}
3912
3913/*
3914 * qla2x00_loop_resync
3915 * Resync with fibre channel devices.
3916 *
3917 * Input:
3918 * ha = adapter block pointer.
3919 *
3920 * Returns:
3921 * 0 = success
3922 */
3923int
e315cd28 3924qla2x00_loop_resync(scsi_qla_host_t *vha)
1da177e4 3925{
73208dfd 3926 int rval = QLA_SUCCESS;
1da177e4 3927 uint32_t wait_time;
67c2e93a
AC		 3928 struct req_que *req;
3929 struct rsp_que *rsp;
3930
7163ea81 3931 if (vha->hw->flags.cpu_affinity_enabled)
67c2e93a
AC		 3932 req = vha->hw->req_q_map[0];
3933 else
3934 req = vha->req;
3935 rsp = req->rsp;
1da177e4 3936
e315cd28
AC		 3937 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
3938 if (vha->flags.online) {
3939 if (!(rval = qla2x00_fw_ready(vha))) {
1da177e4
LT		 3940 /* Wait at most MAX_TARGET RSCNs for a stable link. */
3941 wait_time = 256;
3942 do {
8ae6d9c7
GM		 3943 if (!IS_QLAFX00(vha->hw)) {
3944 /*
3945 * Issue a marker after FW becomes
3946 * ready.
3947 */
3948 qla2x00_marker(vha, req, rsp, 0, 0,
3949 MK_SYNC_ALL);
3950 vha->marker_needed = 0;
3951 }
1da177e4
LT		 3952
3953 /* Remap devices on Loop. */
e315cd28 3954 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4 3955
8ae6d9c7
GM		 3956 if (IS_QLAFX00(vha->hw))
3957 qlafx00_configure_devices(vha);
3958 else
3959 qla2x00_configure_loop(vha);
3960
1da177e4 3961 wait_time--;
e315cd28
AC		 3962 } while (!atomic_read(&vha->loop_down_timer) &&
3963 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
3964 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
3965 &vha->dpc_flags)));
1da177e4 3966 }
1da177e4
LT		 3967 }
3968
e315cd28 3969 if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
1da177e4 3970 return (QLA_FUNCTION_FAILED);
1da177e4 3971
e315cd28 3972 if (rval)
7c3df132
SK		 3973 ql_dbg(ql_dbg_disc, vha, 0x206c,
3974 "%s *** FAILED ***.\n", __func__);
1da177e4
LT		 3975
3976 return (rval);
3977}
3978
579d12b5
SK		 3979/*
3980* qla2x00_perform_loop_resync
3981* Description: This function will set the appropriate flags and call
3982* qla2x00_loop_resync. If successful loop will be resynced
3983* Arguments : scsi_qla_host_t pointer
3984* returm : Success or Failure
3985*/
3986
3987int qla2x00_perform_loop_resync(scsi_qla_host_t *ha)
3988{
3989 int32_t rval = 0;
3990
3991 if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) {
3992 /*Configure the flags so that resync happens properly*/
3993 atomic_set(&ha->loop_down_timer, 0);
3994 if (!(ha->device_flags & DFLG_NO_CABLE)) {
3995 atomic_set(&ha->loop_state, LOOP_UP);
3996 set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags);
3997 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
3998 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
3999
4000 rval = qla2x00_loop_resync(ha);
4001 } else
4002 atomic_set(&ha->loop_state, LOOP_DEAD);
4003
4004 clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags);
4005 }
4006
4007 return rval;
4008}
4009
d97994dc 4010void
67becc00 4011qla2x00_update_fcports(scsi_qla_host_t *base_vha)
d97994dc
AV		 4012{
4013 fc_port_t *fcport;
feafb7b1
AE		 4014 struct scsi_qla_host *vha;
4015 struct qla_hw_data *ha = base_vha->hw;
4016 unsigned long flags;
d97994dc 4017
feafb7b1 4018 spin_lock_irqsave(&ha->vport_slock, flags);
d97994dc 4019 /* Go with deferred removal of rport references. */
feafb7b1
AE		 4020 list_for_each_entry(vha, &base_vha->hw->vp_list, list) {
4021 atomic_inc(&vha->vref_count);
4022 list_for_each_entry(fcport, &vha->vp_fcports, list) {
8ae598d0 4023 if (fcport->drport &&
feafb7b1
AE		 4024 atomic_read(&fcport->state) != FCS_UNCONFIGURED) {
4025 spin_unlock_irqrestore(&ha->vport_slock, flags);
67becc00 4026 qla2x00_rport_del(fcport);
feafb7b1
AE		 4027 spin_lock_irqsave(&ha->vport_slock, flags);
4028 }
4029 }
4030 atomic_dec(&vha->vref_count);
4031 }
4032 spin_unlock_irqrestore(&ha->vport_slock, flags);
d97994dc
AV		 4033}
4034
7d613ac6
SV		 4035/* Assumes idc_lock always held on entry */
4036void
4037qla83xx_reset_ownership(scsi_qla_host_t *vha)
4038{
4039 struct qla_hw_data *ha = vha->hw;
4040 uint32_t drv_presence, drv_presence_mask;
4041 uint32_t dev_part_info1, dev_part_info2, class_type;
4042 uint32_t class_type_mask = 0x3;
4043 uint16_t fcoe_other_function = 0xffff, i;
4044
7ec0effd
AD		 4045 if (IS_QLA8044(ha)) {
4046 drv_presence = qla8044_rd_direct(vha,
4047 QLA8044_CRB_DRV_ACTIVE_INDEX);
4048 dev_part_info1 = qla8044_rd_direct(vha,
4049 QLA8044_CRB_DEV_PART_INFO_INDEX);
4050 dev_part_info2 = qla8044_rd_direct(vha,
4051 QLA8044_CRB_DEV_PART_INFO2);
4052 } else {
4053 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4054 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1);
4055 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2);
4056 }
7d613ac6
SV		 4057 for (i = 0; i < 8; i++) {
4058 class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask);
4059 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
4060 (i != ha->portnum)) {
4061 fcoe_other_function = i;
4062 break;
4063 }
4064 }
4065 if (fcoe_other_function == 0xffff) {
4066 for (i = 0; i < 8; i++) {
4067 class_type = ((dev_part_info2 >> (i * 4)) &
4068 class_type_mask);
4069 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
4070 ((i + 8) != ha->portnum)) {
4071 fcoe_other_function = i + 8;
4072 break;
4073 }
4074 }
4075 }
4076 /*
4077 * Prepare drv-presence mask based on fcoe functions present.
4078 * However consider only valid physical fcoe function numbers (0-15).
4079 */
4080 drv_presence_mask = ~((1 << (ha->portnum)) |
4081 ((fcoe_other_function == 0xffff) ?
4082 0 : (1 << (fcoe_other_function))));
4083
4084 /* We are the reset owner iff:
4085 * - No other protocol drivers present.
4086 * - This is the lowest among fcoe functions. */
4087 if (!(drv_presence & drv_presence_mask) &&
4088 (ha->portnum < fcoe_other_function)) {
4089 ql_dbg(ql_dbg_p3p, vha, 0xb07f,
4090 "This host is Reset owner.\n");
4091 ha->flags.nic_core_reset_owner = 1;
4092 }
4093}
4094
fa492630 4095static int
7d613ac6
SV		 4096__qla83xx_set_drv_ack(scsi_qla_host_t *vha)
4097{
4098 int rval = QLA_SUCCESS;
4099 struct qla_hw_data *ha = vha->hw;
4100 uint32_t drv_ack;
4101
4102 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4103 if (rval == QLA_SUCCESS) {
4104 drv_ack |= (1 << ha->portnum);
4105 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
4106 }
4107
4108 return rval;
4109}
4110
fa492630 4111static int
7d613ac6
SV		 4112__qla83xx_clear_drv_ack(scsi_qla_host_t *vha)
4113{
4114 int rval = QLA_SUCCESS;
4115 struct qla_hw_data *ha = vha->hw;
4116 uint32_t drv_ack;
4117
4118 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4119 if (rval == QLA_SUCCESS) {
4120 drv_ack &= ~(1 << ha->portnum);
4121 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
4122 }
4123
4124 return rval;
4125}
4126
fa492630 4127static const char *
7d613ac6
SV		 4128qla83xx_dev_state_to_string(uint32_t dev_state)
4129{
4130 switch (dev_state) {
4131 case QLA8XXX_DEV_COLD:
4132 return "COLD/RE-INIT";
4133 case QLA8XXX_DEV_INITIALIZING:
4134 return "INITIALIZING";
4135 case QLA8XXX_DEV_READY:
4136 return "READY";
4137 case QLA8XXX_DEV_NEED_RESET:
4138 return "NEED RESET";
4139 case QLA8XXX_DEV_NEED_QUIESCENT:
4140 return "NEED QUIESCENT";
4141 case QLA8XXX_DEV_FAILED:
4142 return "FAILED";
4143 case QLA8XXX_DEV_QUIESCENT:
4144 return "QUIESCENT";
4145 default:
4146 return "Unknown";
4147 }
4148}
4149
4150/* Assumes idc-lock always held on entry */
4151void
4152qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type)
4153{
4154 struct qla_hw_data *ha = vha->hw;
4155 uint32_t idc_audit_reg = 0, duration_secs = 0;
4156
4157 switch (audit_type) {
4158 case IDC_AUDIT_TIMESTAMP:
4159 ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000);
4160 idc_audit_reg = (ha->portnum) |
4161 (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8);
4162 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
4163 break;
4164
4165 case IDC_AUDIT_COMPLETION:
4166 duration_secs = ((jiffies_to_msecs(jiffies) -
4167 jiffies_to_msecs(ha->idc_audit_ts)) / 1000);
4168 idc_audit_reg = (ha->portnum) |
4169 (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8);
4170 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
4171 break;
4172
4173 default:
4174 ql_log(ql_log_warn, vha, 0xb078,
4175 "Invalid audit type specified.\n");
4176 break;
4177 }
4178}
4179
4180/* Assumes idc_lock always held on entry */
fa492630 4181static int
7d613ac6
SV		 4182qla83xx_initiating_reset(scsi_qla_host_t *vha)
4183{
4184 struct qla_hw_data *ha = vha->hw;
4185 uint32_t idc_control, dev_state;
4186
4187 __qla83xx_get_idc_control(vha, &idc_control);
4188 if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) {
4189 ql_log(ql_log_info, vha, 0xb080,
4190 "NIC Core reset has been disabled. idc-control=0x%x\n",
4191 idc_control);
4192 return QLA_FUNCTION_FAILED;
4193 }
4194
4195 /* Set NEED-RESET iff in READY state and we are the reset-owner */
4196 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4197 if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) {
4198 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
4199 QLA8XXX_DEV_NEED_RESET);
4200 ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n");
4201 qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP);
4202 } else {
4203 const char *state = qla83xx_dev_state_to_string(dev_state);
4204 ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n", state);
4205
4206 /* SV: XXX: Is timeout required here? */
4207 /* Wait for IDC state change READY -> NEED_RESET */
4208 while (dev_state == QLA8XXX_DEV_READY) {
4209 qla83xx_idc_unlock(vha, 0);
4210 msleep(200);
4211 qla83xx_idc_lock(vha, 0);
4212 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4213 }
4214 }
4215
4216 /* Send IDC ack by writing to drv-ack register */
4217 __qla83xx_set_drv_ack(vha);
4218
4219 return QLA_SUCCESS;
4220}
4221
4222int
4223__qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control)
4224{
4225 return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
4226}
4227
7d613ac6
SV		 4228int
4229__qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control)
4230{
4231 return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
4232}
4233
fa492630 4234static int
7d613ac6
SV		 4235qla83xx_check_driver_presence(scsi_qla_host_t *vha)
4236{
4237 uint32_t drv_presence = 0;
4238 struct qla_hw_data *ha = vha->hw;
4239
4240 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4241 if (drv_presence & (1 << ha->portnum))
4242 return QLA_SUCCESS;
4243 else
4244 return QLA_TEST_FAILED;
4245}
4246
4247int
4248qla83xx_nic_core_reset(scsi_qla_host_t *vha)
4249{
4250 int rval = QLA_SUCCESS;
4251 struct qla_hw_data *ha = vha->hw;
4252
4253 ql_dbg(ql_dbg_p3p, vha, 0xb058,
4254 "Entered %s().\n", __func__);
4255
4256 if (vha->device_flags & DFLG_DEV_FAILED) {
4257 ql_log(ql_log_warn, vha, 0xb059,
4258 "Device in unrecoverable FAILED state.\n");
4259 return QLA_FUNCTION_FAILED;
4260 }
4261
4262 qla83xx_idc_lock(vha, 0);
4263
4264 if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) {
4265 ql_log(ql_log_warn, vha, 0xb05a,
4266 "Function=0x%x has been removed from IDC participation.\n",
4267 ha->portnum);
4268 rval = QLA_FUNCTION_FAILED;
4269 goto exit;
4270 }
4271
4272 qla83xx_reset_ownership(vha);
4273
4274 rval = qla83xx_initiating_reset(vha);
4275
4276 /*
4277 * Perform reset if we are the reset-owner,
4278 * else wait till IDC state changes to READY/FAILED.
4279 */
4280 if (rval == QLA_SUCCESS) {
4281 rval = qla83xx_idc_state_handler(vha);
4282
4283 if (rval == QLA_SUCCESS)
4284 ha->flags.nic_core_hung = 0;
4285 __qla83xx_clear_drv_ack(vha);
4286 }
4287
4288exit:
4289 qla83xx_idc_unlock(vha, 0);
4290
4291 ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__);
4292
4293 return rval;
4294}
4295
81178772
SK		 4296int
4297qla2xxx_mctp_dump(scsi_qla_host_t *vha)
4298{
4299 struct qla_hw_data *ha = vha->hw;
4300 int rval = QLA_FUNCTION_FAILED;
4301
4302 if (!IS_MCTP_CAPABLE(ha)) {
4303 /* This message can be removed from the final version */
4304 ql_log(ql_log_info, vha, 0x506d,
4305 "This board is not MCTP capable\n");
4306 return rval;
4307 }
4308
4309 if (!ha->mctp_dump) {
4310 ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev,
4311 MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL);
4312
4313 if (!ha->mctp_dump) {
4314 ql_log(ql_log_warn, vha, 0x506e,
4315 "Failed to allocate memory for mctp dump\n");
4316 return rval;
4317 }
4318 }
4319
4320#define MCTP_DUMP_STR_ADDR 0x00000000
4321 rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma,
4322 MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4);
4323 if (rval != QLA_SUCCESS) {
4324 ql_log(ql_log_warn, vha, 0x506f,
4325 "Failed to capture mctp dump\n");
4326 } else {
4327 ql_log(ql_log_info, vha, 0x5070,
4328 "Mctp dump capture for host (%ld/%p).\n",
4329 vha->host_no, ha->mctp_dump);
4330 ha->mctp_dumped = 1;
4331 }
4332
409ee0fe 4333 if (!ha->flags.nic_core_reset_hdlr_active && !ha->portnum) {
81178772
SK		 4334 ha->flags.nic_core_reset_hdlr_active = 1;
4335 rval = qla83xx_restart_nic_firmware(vha);
4336 if (rval)
4337 /* NIC Core reset failed. */
4338 ql_log(ql_log_warn, vha, 0x5071,
4339 "Failed to restart nic firmware\n");
4340 else
4341 ql_dbg(ql_dbg_p3p, vha, 0xb084,
4342 "Restarted NIC firmware successfully.\n");
4343 ha->flags.nic_core_reset_hdlr_active = 0;
4344 }
4345
4346 return rval;
4347
4348}
4349
579d12b5 4350/*
8fcd6b8b 4351* qla2x00_quiesce_io
579d12b5
SK		 4352* Description: This function will block the new I/Os
4353* Its not aborting any I/Os as context
4354* is not destroyed during quiescence
4355* Arguments: scsi_qla_host_t
4356* return : void
4357*/
4358void
8fcd6b8b 4359qla2x00_quiesce_io(scsi_qla_host_t *vha)
579d12b5
SK		 4360{
4361 struct qla_hw_data *ha = vha->hw;
4362 struct scsi_qla_host *vp;
4363
8fcd6b8b
CD		 4364 ql_dbg(ql_dbg_dpc, vha, 0x401d,
4365 "Quiescing I/O - ha=%p.\n", ha);
579d12b5
SK		 4366
4367 atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME);
4368 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
4369 atomic_set(&vha->loop_state, LOOP_DOWN);
4370 qla2x00_mark_all_devices_lost(vha, 0);
4371 list_for_each_entry(vp, &ha->vp_list, list)
8fcd6b8b 4372 qla2x00_mark_all_devices_lost(vp, 0);
579d12b5
SK		 4373 } else {
4374 if (!atomic_read(&vha->loop_down_timer))
4375 atomic_set(&vha->loop_down_timer,
4376 LOOP_DOWN_TIME);
4377 }
4378 /* Wait for pending cmds to complete */
4379 qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST);
4380}
4381
a9083016
GM		 4382void
4383qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
4384{
4385 struct qla_hw_data *ha = vha->hw;
579d12b5 4386 struct scsi_qla_host *vp;
feafb7b1 4387 unsigned long flags;
6aef87be 4388 fc_port_t *fcport;
a9083016 4389
e46ef004
SK		 4390 /* For ISP82XX, driver waits for completion of the commands.
4391 * online flag should be set.
4392 */
7ec0effd 4393 if (!(IS_P3P_TYPE(ha)))
e46ef004 4394 vha->flags.online = 0;
a9083016
GM		 4395 ha->flags.chip_reset_done = 0;
4396 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2be21fa2 4397 vha->qla_stats.total_isp_aborts++;
a9083016 4398
7c3df132
SK		 4399 ql_log(ql_log_info, vha, 0x00af,
4400 "Performing ISP error recovery - ha=%p.\n", ha);
a9083016 4401
e46ef004
SK		 4402 /* For ISP82XX, reset_chip is just disabling interrupts.
4403 * Driver waits for the completion of the commands.
4404 * the interrupts need to be enabled.
4405 */
7ec0effd 4406 if (!(IS_P3P_TYPE(ha)))
a9083016
GM		 4407 ha->isp_ops->reset_chip(vha);
4408
4409 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
4410 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
4411 atomic_set(&vha->loop_state, LOOP_DOWN);
4412 qla2x00_mark_all_devices_lost(vha, 0);
feafb7b1
AE		 4413
4414 spin_lock_irqsave(&ha->vport_slock, flags);
579d12b5 4415 list_for_each_entry(vp, &ha->vp_list, list) {
feafb7b1
AE		 4416 atomic_inc(&vp->vref_count);
4417 spin_unlock_irqrestore(&ha->vport_slock, flags);
4418
a9083016 4419 qla2x00_mark_all_devices_lost(vp, 0);
feafb7b1
AE		 4420
4421 spin_lock_irqsave(&ha->vport_slock, flags);
4422 atomic_dec(&vp->vref_count);
4423 }
4424 spin_unlock_irqrestore(&ha->vport_slock, flags);
a9083016
GM		 4425 } else {
4426 if (!atomic_read(&vha->loop_down_timer))
4427 atomic_set(&vha->loop_down_timer,
4428 LOOP_DOWN_TIME);
4429 }
4430
6aef87be
AV		 4431 /* Clear all async request states across all VPs. */
4432 list_for_each_entry(fcport, &vha->vp_fcports, list)
4433 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
4434 spin_lock_irqsave(&ha->vport_slock, flags);
4435 list_for_each_entry(vp, &ha->vp_list, list) {
4436 atomic_inc(&vp->vref_count);
4437 spin_unlock_irqrestore(&ha->vport_slock, flags);
4438
4439 list_for_each_entry(fcport, &vp->vp_fcports, list)
4440 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
4441
4442 spin_lock_irqsave(&ha->vport_slock, flags);
4443 atomic_dec(&vp->vref_count);
4444 }
4445 spin_unlock_irqrestore(&ha->vport_slock, flags);
4446
bddd2d65
LC		 4447 if (!ha->flags.eeh_busy) {
4448 /* Make sure for ISP 82XX IO DMA is complete */
7ec0effd 4449 if (IS_P3P_TYPE(ha)) {
7190575f 4450 qla82xx_chip_reset_cleanup(vha);
7c3df132
SK		 4451 ql_log(ql_log_info, vha, 0x00b4,
4452 "Done chip reset cleanup.\n");
a9083016 4453
e46ef004
SK		 4454 /* Done waiting for pending commands.
4455 * Reset the online flag.
4456 */
4457 vha->flags.online = 0;
4d78c973 4458 }
a9083016 4459
bddd2d65
LC		 4460 /* Requeue all commands in outstanding command list. */
4461 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
4462 }
a9083016
GM		 4463}
4464
1da177e4
LT		 4465/*
4466* qla2x00_abort_isp
4467* Resets ISP and aborts all outstanding commands.
4468*
4469* Input:
4470* ha = adapter block pointer.
4471*
4472* Returns:
4473* 0 = success
4474*/
4475int
e315cd28 4476qla2x00_abort_isp(scsi_qla_host_t *vha)
1da177e4 4477{
476e8978 4478 int rval;
1da177e4 4479 uint8_t status = 0;
e315cd28
AC		 4480 struct qla_hw_data *ha = vha->hw;
4481 struct scsi_qla_host *vp;
73208dfd 4482 struct req_que *req = ha->req_q_map[0];
feafb7b1 4483 unsigned long flags;
1da177e4 4484
e315cd28 4485 if (vha->flags.online) {
a9083016 4486 qla2x00_abort_isp_cleanup(vha);
1da177e4 4487
a6171297
SV		 4488 if (IS_QLA8031(ha)) {
4489 ql_dbg(ql_dbg_p3p, vha, 0xb05c,
4490 "Clearing fcoe driver presence.\n");
4491 if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS)
4492 ql_dbg(ql_dbg_p3p, vha, 0xb073,
4493 "Error while clearing DRV-Presence.\n");
4494 }
4495
85880801
AV		 4496 if (unlikely(pci_channel_offline(ha->pdev) &&
4497 ha->flags.pci_channel_io_perm_failure)) {
4498 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
4499 status = 0;
4500 return status;
4501 }
4502
73208dfd 4503 ha->isp_ops->get_flash_version(vha, req->ring);
30c47662 4504
e315cd28 4505 ha->isp_ops->nvram_config(vha);
1da177e4 4506
e315cd28
AC		 4507 if (!qla2x00_restart_isp(vha)) {
4508 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4 4509
e315cd28 4510 if (!atomic_read(&vha->loop_down_timer)) {
1da177e4
LT		 4511 /*
4512 * Issue marker command only when we are going
4513 * to start the I/O .
4514 */
e315cd28 4515 vha->marker_needed = 1;
1da177e4
LT		 4516 }
4517
e315cd28 4518 vha->flags.online = 1;
1da177e4 4519
fd34f556 4520 ha->isp_ops->enable_intrs(ha);
1da177e4 4521
fa2a1ce5 4522 ha->isp_abort_cnt = 0;
e315cd28 4523 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
476e8978 4524
6246b8a1
GM		 4525 if (IS_QLA81XX(ha) || IS_QLA8031(ha))
4526 qla2x00_get_fw_version(vha);
df613b96
AV		 4527 if (ha->fce) {
4528 ha->flags.fce_enabled = 1;
4529 memset(ha->fce, 0,
4530 fce_calc_size(ha->fce_bufs));
e315cd28 4531 rval = qla2x00_enable_fce_trace(vha,
df613b96
AV		 4532 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
4533 &ha->fce_bufs);
4534 if (rval) {
7c3df132 4535 ql_log(ql_log_warn, vha, 0x8033,
df613b96
AV		 4536 "Unable to reinitialize FCE "
4537 "(%d).\n", rval);
4538 ha->flags.fce_enabled = 0;
4539 }
4540 }
436a7b11
AV		 4541
4542 if (ha->eft) {
4543 memset(ha->eft, 0, EFT_SIZE);
e315cd28 4544 rval = qla2x00_enable_eft_trace(vha,
436a7b11
AV		 4545 ha->eft_dma, EFT_NUM_BUFFERS);
4546 if (rval) {
7c3df132 4547 ql_log(ql_log_warn, vha, 0x8034,
436a7b11
AV		 4548 "Unable to reinitialize EFT "
4549 "(%d).\n", rval);
4550 }
4551 }
1da177e4 4552 } else { /* failed the ISP abort */
e315cd28
AC		 4553 vha->flags.online = 1;
4554 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
1da177e4 4555 if (ha->isp_abort_cnt == 0) {
7c3df132
SK		 4556 ql_log(ql_log_fatal, vha, 0x8035,
4557 "ISP error recover failed - "
4558 "board disabled.\n");
fa2a1ce5 4559 /*
1da177e4
LT		 4560 * The next call disables the board
4561 * completely.
4562 */
e315cd28
AC		 4563 ha->isp_ops->reset_adapter(vha);
4564 vha->flags.online = 0;
1da177e4 4565 clear_bit(ISP_ABORT_RETRY,
e315cd28 4566 &vha->dpc_flags);
1da177e4
LT		 4567 status = 0;
4568 } else { /* schedule another ISP abort */
4569 ha->isp_abort_cnt--;
7c3df132
SK		 4570 ql_dbg(ql_dbg_taskm, vha, 0x8020,
4571 "ISP abort - retry remaining %d.\n",
4572 ha->isp_abort_cnt);
1da177e4
LT		 4573 status = 1;
4574 }
4575 } else {
4576 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
7c3df132
SK		 4577 ql_dbg(ql_dbg_taskm, vha, 0x8021,
4578 "ISP error recovery - retrying (%d) "
4579 "more times.\n", ha->isp_abort_cnt);
e315cd28 4580 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
1da177e4
LT		 4581 status = 1;
4582 }
4583 }
fa2a1ce5 4584
1da177e4
LT		 4585 }
4586
e315cd28 4587 if (!status) {
7c3df132 4588 ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__);
feafb7b1
AE		 4589
4590 spin_lock_irqsave(&ha->vport_slock, flags);
4591 list_for_each_entry(vp, &ha->vp_list, list) {
4592 if (vp->vp_idx) {
4593 atomic_inc(&vp->vref_count);
4594 spin_unlock_irqrestore(&ha->vport_slock, flags);
4595
e315cd28 4596 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 4597
4598 spin_lock_irqsave(&ha->vport_slock, flags);
4599 atomic_dec(&vp->vref_count);
4600 }
e315cd28 4601 }
feafb7b1
AE		 4602 spin_unlock_irqrestore(&ha->vport_slock, flags);
4603
7d613ac6
SV		 4604 if (IS_QLA8031(ha)) {
4605 ql_dbg(ql_dbg_p3p, vha, 0xb05d,
4606 "Setting back fcoe driver presence.\n");
4607 if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS)
4608 ql_dbg(ql_dbg_p3p, vha, 0xb074,
4609 "Error while setting DRV-Presence.\n");
4610 }
e315cd28 4611 } else {
d8424f68
JP		 4612 ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n",
4613 __func__);
1da177e4
LT		 4614 }
4615
4616 return(status);
4617}
4618
4619/*
4620* qla2x00_restart_isp
4621* restarts the ISP after a reset
4622*
4623* Input:
4624* ha = adapter block pointer.
4625*
4626* Returns:
4627* 0 = success
4628*/
4629static int
e315cd28 4630qla2x00_restart_isp(scsi_qla_host_t *vha)
1da177e4 4631{
c6b2fca8 4632 int status = 0;
1da177e4 4633 uint32_t wait_time;
e315cd28 4634 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 4635 struct req_que *req = ha->req_q_map[0];
4636 struct rsp_que *rsp = ha->rsp_q_map[0];
2d70c103 4637 unsigned long flags;
1da177e4
LT		 4638
4639 /* If firmware needs to be loaded */
e315cd28
AC		 4640 if (qla2x00_isp_firmware(vha)) {
4641 vha->flags.online = 0;
4642 status = ha->isp_ops->chip_diag(vha);
4643 if (!status)
4644 status = qla2x00_setup_chip(vha);
1da177e4
LT		 4645 }
4646
e315cd28
AC		 4647 if (!status && !(status = qla2x00_init_rings(vha))) {
4648 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
2533cf67 4649 ha->flags.chip_reset_done = 1;
73208dfd
AC		 4650 /* Initialize the queues in use */
4651 qla25xx_init_queues(ha);
4652
e315cd28
AC		 4653 status = qla2x00_fw_ready(vha);
4654 if (!status) {
7c3df132
SK		 4655 ql_dbg(ql_dbg_taskm, vha, 0x8031,
4656 "Start configure loop status = %d.\n", status);
0107109e
AV		 4657
4658 /* Issue a marker after FW becomes ready. */
73208dfd 4659 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
0107109e 4660
e315cd28 4661 vha->flags.online = 1;
2d70c103
NB		 4662
4663 /*
4664 * Process any ATIO queue entries that came in
4665 * while we weren't online.
4666 */
4667 spin_lock_irqsave(&ha->hardware_lock, flags);
4668 if (qla_tgt_mode_enabled(vha))
4669 qlt_24xx_process_atio_queue(vha);
4670 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4671
1da177e4
LT		 4672 /* Wait at most MAX_TARGET RSCNs for a stable link. */
4673 wait_time = 256;
4674 do {
e315cd28
AC		 4675 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
4676 qla2x00_configure_loop(vha);
1da177e4 4677 wait_time--;
e315cd28
AC		 4678 } while (!atomic_read(&vha->loop_down_timer) &&
4679 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
4680 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
4681 &vha->dpc_flags)));
1da177e4
LT		 4682 }
4683
4684 /* if no cable then assume it's good */
e315cd28 4685 if ((vha->device_flags & DFLG_NO_CABLE))
1da177e4
LT		 4686 status = 0;
4687
7c3df132
SK		 4688 ql_dbg(ql_dbg_taskm, vha, 0x8032,
4689 "Configure loop done, status = 0x%x.\n", status);
1da177e4
LT		 4690 }
4691 return (status);
4692}
4693
73208dfd
AC		 4694static int
4695qla25xx_init_queues(struct qla_hw_data *ha)
4696{
4697 struct rsp_que *rsp = NULL;
4698 struct req_que *req = NULL;
4699 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
4700 int ret = -1;
4701 int i;
4702
2afa19a9 4703 for (i = 1; i < ha->max_rsp_queues; i++) {
73208dfd
AC		 4704 rsp = ha->rsp_q_map[i];
4705 if (rsp) {
4706 rsp->options &= ~BIT_0;
618a7523 4707 ret = qla25xx_init_rsp_que(base_vha, rsp);
73208dfd 4708 if (ret != QLA_SUCCESS)
7c3df132
SK		 4709 ql_dbg(ql_dbg_init, base_vha, 0x00ff,
4710 "%s Rsp que: %d init failed.\n",
4711 __func__, rsp->id);
73208dfd 4712 else
7c3df132
SK		 4713 ql_dbg(ql_dbg_init, base_vha, 0x0100,
4714 "%s Rsp que: %d inited.\n",
4715 __func__, rsp->id);
73208dfd 4716 }
2afa19a9
AC		 4717 }
4718 for (i = 1; i < ha->max_req_queues; i++) {
73208dfd
AC		 4719 req = ha->req_q_map[i];
4720 if (req) {
29bdccbe 4721 /* Clear outstanding commands array. */
73208dfd 4722 req->options &= ~BIT_0;
618a7523 4723 ret = qla25xx_init_req_que(base_vha, req);
73208dfd 4724 if (ret != QLA_SUCCESS)
7c3df132
SK		 4725 ql_dbg(ql_dbg_init, base_vha, 0x0101,
4726 "%s Req que: %d init failed.\n",
4727 __func__, req->id);
73208dfd 4728 else
7c3df132
SK		 4729 ql_dbg(ql_dbg_init, base_vha, 0x0102,
4730 "%s Req que: %d inited.\n",
4731 __func__, req->id);
73208dfd
AC		 4732 }
4733 }
4734 return ret;
4735}
4736
1da177e4
LT		 4737/*
4738* qla2x00_reset_adapter
4739* Reset adapter.
4740*
4741* Input:
4742* ha = adapter block pointer.
4743*/
abbd8870 4744void
e315cd28 4745qla2x00_reset_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 4746{
4747 unsigned long flags = 0;
e315cd28 4748 struct qla_hw_data *ha = vha->hw;
3d71644c 4749 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 4750
e315cd28 4751 vha->flags.online = 0;
fd34f556 4752 ha->isp_ops->disable_intrs(ha);
1da177e4 4753
1da177e4
LT		 4754 spin_lock_irqsave(&ha->hardware_lock, flags);
4755 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
4756 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
4757 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
4758 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
4759 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4760}
0107109e
AV		 4761
4762void
e315cd28 4763qla24xx_reset_adapter(scsi_qla_host_t *vha)
0107109e
AV		 4764{
4765 unsigned long flags = 0;
e315cd28 4766 struct qla_hw_data *ha = vha->hw;
0107109e
AV		 4767 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
4768
7ec0effd 4769 if (IS_P3P_TYPE(ha))
a9083016
GM		 4770 return;
4771
e315cd28 4772 vha->flags.online = 0;
fd34f556 4773 ha->isp_ops->disable_intrs(ha);
0107109e
AV		 4774
4775 spin_lock_irqsave(&ha->hardware_lock, flags);
4776 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
4777 RD_REG_DWORD(&reg->hccr);
4778 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
4779 RD_REG_DWORD(&reg->hccr);
4780 spin_unlock_irqrestore(&ha->hardware_lock, flags);
09ff36d3
AV		 4781
4782 if (IS_NOPOLLING_TYPE(ha))
4783 ha->isp_ops->enable_intrs(ha);
0107109e
AV		 4784}
4785
4e08df3f
DM		 4786/* On sparc systems, obtain port and node WWN from firmware
4787 * properties.
4788 */
e315cd28
AC		 4789static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha,
4790 struct nvram_24xx *nv)
4e08df3f
DM		 4791{
4792#ifdef CONFIG_SPARC
e315cd28 4793 struct qla_hw_data *ha = vha->hw;
4e08df3f 4794 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 4795 struct device_node *dp = pci_device_to_OF_node(pdev);
4796 const u8 *val;
4e08df3f
DM		 4797 int len;
4798
4799 val = of_get_property(dp, "port-wwn", &len);
4800 if (val && len >= WWN_SIZE)
4801 memcpy(nv->port_name, val, WWN_SIZE);
4802
4803 val = of_get_property(dp, "node-wwn", &len);
4804 if (val && len >= WWN_SIZE)
4805 memcpy(nv->node_name, val, WWN_SIZE);
4806#endif
4807}
4808
0107109e 4809int
e315cd28 4810qla24xx_nvram_config(scsi_qla_host_t *vha)
0107109e 4811{
4e08df3f 4812 int rval;
0107109e
AV		 4813 struct init_cb_24xx *icb;
4814 struct nvram_24xx *nv;
4815 uint32_t *dptr;
4816 uint8_t *dptr1, *dptr2;
4817 uint32_t chksum;
4818 uint16_t cnt;
e315cd28 4819 struct qla_hw_data *ha = vha->hw;
0107109e 4820
4e08df3f 4821 rval = QLA_SUCCESS;
0107109e 4822 icb = (struct init_cb_24xx *)ha->init_cb;
281afe19 4823 nv = ha->nvram;
0107109e
AV		 4824
4825 /* Determine NVRAM starting address. */
f73cb695 4826 if (ha->port_no == 0) {
e5b68a61
AC		 4827 ha->nvram_base = FA_NVRAM_FUNC0_ADDR;
4828 ha->vpd_base = FA_NVRAM_VPD0_ADDR;
4829 } else {
0107109e 4830 ha->nvram_base = FA_NVRAM_FUNC1_ADDR;
6f641790
AV		 4831 ha->vpd_base = FA_NVRAM_VPD1_ADDR;
4832 }
f73cb695 4833
e5b68a61
AC		 4834 ha->nvram_size = sizeof(struct nvram_24xx);
4835 ha->vpd_size = FA_NVRAM_VPD_SIZE;
0107109e 4836
281afe19
SJ		 4837 /* Get VPD data into cache */
4838 ha->vpd = ha->nvram + VPD_OFFSET;
e315cd28 4839 ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd,
281afe19
SJ		 4840 ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
4841
4842 /* Get NVRAM data into cache and calculate checksum. */
0107109e 4843 dptr = (uint32_t *)nv;
e315cd28 4844 ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base,
0107109e
AV		 4845 ha->nvram_size);
4846 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
4847 chksum += le32_to_cpu(*dptr++);
4848
7c3df132
SK		 4849 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
4850 "Contents of NVRAM\n");
4851 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
4852 (uint8_t *)nv, ha->nvram_size);
0107109e
AV		 4853
4854 /* Bad NVRAM data, set defaults parameters. */
4855 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
4856 || nv->id[3] != ' ' ||
4857 nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
4858 /* Reset NVRAM data. */
7c3df132 4859 ql_log(ql_log_warn, vha, 0x006b,
9e336520 4860 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132
SK		 4861 "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version);
4862 ql_log(ql_log_warn, vha, 0x006c,
4863 "Falling back to functioning (yet invalid -- WWPN) "
4864 "defaults.\n");
4e08df3f
DM		 4865
4866 /*
4867 * Set default initialization control block.
4868 */
4869 memset(nv, 0, ha->nvram_size);
4870 nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
4871 nv->version = __constant_cpu_to_le16(ICB_VERSION);
4872 nv->frame_payload_size = __constant_cpu_to_le16(2048);
4873 nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
4874 nv->exchange_count = __constant_cpu_to_le16(0);
4875 nv->hard_address = __constant_cpu_to_le16(124);
4876 nv->port_name[0] = 0x21;
f73cb695 4877 nv->port_name[1] = 0x00 + ha->port_no + 1;
4e08df3f
DM		 4878 nv->port_name[2] = 0x00;
4879 nv->port_name[3] = 0xe0;
4880 nv->port_name[4] = 0x8b;
4881 nv->port_name[5] = 0x1c;
4882 nv->port_name[6] = 0x55;
4883 nv->port_name[7] = 0x86;
4884 nv->node_name[0] = 0x20;
4885 nv->node_name[1] = 0x00;
4886 nv->node_name[2] = 0x00;
4887 nv->node_name[3] = 0xe0;
4888 nv->node_name[4] = 0x8b;
4889 nv->node_name[5] = 0x1c;
4890 nv->node_name[6] = 0x55;
4891 nv->node_name[7] = 0x86;
e315cd28 4892 qla24xx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 4893 nv->login_retry_count = __constant_cpu_to_le16(8);
4894 nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
4895 nv->login_timeout = __constant_cpu_to_le16(0);
4896 nv->firmware_options_1 =
4897 __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
4898 nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
4899 nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
4900 nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
4901 nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
4902 nv->efi_parameters = __constant_cpu_to_le32(0);
4903 nv->reset_delay = 5;
4904 nv->max_luns_per_target = __constant_cpu_to_le16(128);
4905 nv->port_down_retry_count = __constant_cpu_to_le16(30);
4906 nv->link_down_timeout = __constant_cpu_to_le16(30);
4907
4908 rval = 1;
0107109e
AV		 4909 }
4910
2d70c103
NB		 4911 if (!qla_ini_mode_enabled(vha)) {
4912 /* Don't enable full login after initial LIP */
4913 nv->firmware_options_1 &= __constant_cpu_to_le32(~BIT_13);
4914 /* Don't enable LIP full login for initiator */
4915 nv->host_p &= __constant_cpu_to_le32(~BIT_10);
4916 }
4917
4918 qlt_24xx_config_nvram_stage1(vha, nv);
4919
0107109e 4920 /* Reset Initialization control block */
e315cd28 4921 memset(icb, 0, ha->init_cb_size);
0107109e
AV		 4922
4923 /* Copy 1st segment. */
4924 dptr1 = (uint8_t *)icb;
4925 dptr2 = (uint8_t *)&nv->version;
4926 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
4927 while (cnt--)
4928 *dptr1++ = *dptr2++;
4929
4930 icb->login_retry_count = nv->login_retry_count;
3ea66e28 4931 icb->link_down_on_nos = nv->link_down_on_nos;
0107109e
AV		 4932
4933 /* Copy 2nd segment. */
4934 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
4935 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
4936 cnt = (uint8_t *)&icb->reserved_3 -
4937 (uint8_t *)&icb->interrupt_delay_timer;
4938 while (cnt--)
4939 *dptr1++ = *dptr2++;
4940
4941 /*
4942 * Setup driver NVRAM options.
4943 */
e315cd28 4944 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
9bb9fcf2 4945 "QLA2462");
0107109e 4946
2d70c103
NB		 4947 qlt_24xx_config_nvram_stage2(vha, icb);
4948
5341e868 4949 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
2d70c103 4950 /* Use alternate WWN? */
5341e868
AV		 4951 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
4952 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
4953 }
4954
0107109e 4955 /* Prepare nodename */
fd0e7e4d 4956 if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
0107109e
AV		 4957 /*
4958 * Firmware will apply the following mask if the nodename was
4959 * not provided.
4960 */
4961 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
4962 icb->node_name[0] &= 0xF0;
4963 }
4964
4965 /* Set host adapter parameters. */
4966 ha->flags.disable_risc_code_load = 0;
0c8c39af
AV		 4967 ha->flags.enable_lip_reset = 0;
4968 ha->flags.enable_lip_full_login =
4969 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
4970 ha->flags.enable_target_reset =
4971 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
0107109e 4972 ha->flags.enable_led_scheme = 0;
d4c760c2 4973 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
0107109e 4974
fd0e7e4d
AV		 4975 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
4976 (BIT_6 | BIT_5 | BIT_4)) >> 4;
0107109e
AV		 4977
4978 memcpy(ha->fw_seriallink_options24, nv->seriallink_options,
4979 sizeof(ha->fw_seriallink_options24));
4980
4981 /* save HBA serial number */
4982 ha->serial0 = icb->port_name[5];
4983 ha->serial1 = icb->port_name[6];
4984 ha->serial2 = icb->port_name[7];
e315cd28
AC		 4985 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
4986 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
0107109e 4987
bc8fb3cb
AV		 4988 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
4989
0107109e
AV		 4990 ha->retry_count = le16_to_cpu(nv->login_retry_count);
4991
4992 /* Set minimum login_timeout to 4 seconds. */
4993 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
4994 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
4995 if (le16_to_cpu(nv->login_timeout) < 4)
4996 nv->login_timeout = __constant_cpu_to_le16(4);
4997 ha->login_timeout = le16_to_cpu(nv->login_timeout);
c6852c4c 4998 icb->login_timeout = nv->login_timeout;
0107109e 4999
00a537b8
AV		 5000 /* Set minimum RATOV to 100 tenths of a second. */
5001 ha->r_a_tov = 100;
0107109e
AV		 5002
5003 ha->loop_reset_delay = nv->reset_delay;
5004
5005 /* Link Down Timeout = 0:
5006 *
5007 * When Port Down timer expires we will start returning
5008 * I/O's to OS with "DID_NO_CONNECT".
5009 *
5010 * Link Down Timeout != 0:
5011 *
5012 * The driver waits for the link to come up after link down
5013 * before returning I/Os to OS with "DID_NO_CONNECT".
5014 */
5015 if (le16_to_cpu(nv->link_down_timeout) == 0) {
5016 ha->loop_down_abort_time =
5017 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
5018 } else {
5019 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
5020 ha->loop_down_abort_time =
5021 (LOOP_DOWN_TIME - ha->link_down_timeout);
5022 }
5023
5024 /* Need enough time to try and get the port back. */
5025 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
5026 if (qlport_down_retry)
5027 ha->port_down_retry_count = qlport_down_retry;
5028
5029 /* Set login_retry_count */
5030 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
5031 if (ha->port_down_retry_count ==
5032 le16_to_cpu(nv->port_down_retry_count) &&
5033 ha->port_down_retry_count > 3)
5034 ha->login_retry_count = ha->port_down_retry_count;
5035 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
5036 ha->login_retry_count = ha->port_down_retry_count;
5037 if (ql2xloginretrycount)
5038 ha->login_retry_count = ql2xloginretrycount;
5039
4fdfefe5 5040 /* Enable ZIO. */
e315cd28 5041 if (!vha->flags.init_done) {
4fdfefe5
AV		 5042 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
5043 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
5044 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
5045 le16_to_cpu(icb->interrupt_delay_timer): 2;
5046 }
5047 icb->firmware_options_2 &= __constant_cpu_to_le32(
5048 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
e315cd28 5049 vha->flags.process_response_queue = 0;
4fdfefe5 5050 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d
AV		 5051 ha->zio_mode = QLA_ZIO_MODE_6;
5052
7c3df132 5053 ql_log(ql_log_info, vha, 0x006f,
4fdfefe5
AV		 5054 "ZIO mode %d enabled; timer delay (%d us).\n",
5055 ha->zio_mode, ha->zio_timer * 100);
5056
5057 icb->firmware_options_2 |= cpu_to_le32(
5058 (uint32_t)ha->zio_mode);
5059 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
e315cd28 5060 vha->flags.process_response_queue = 1;
4fdfefe5
AV		 5061 }
5062
4e08df3f 5063 if (rval) {
7c3df132
SK		 5064 ql_log(ql_log_warn, vha, 0x0070,
5065 "NVRAM configuration failed.\n");
4e08df3f
DM		 5066 }
5067 return (rval);
0107109e
AV		 5068}
5069
413975a0 5070static int
cbc8eb67
AV		 5071qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
5072 uint32_t faddr)
d1c61909 5073{
73208dfd 5074 int rval = QLA_SUCCESS;
d1c61909 5075 int segments, fragment;
d1c61909
AV		 5076 uint32_t *dcode, dlen;
5077 uint32_t risc_addr;
5078 uint32_t risc_size;
5079 uint32_t i;
e315cd28 5080 struct qla_hw_data *ha = vha->hw;
73208dfd 5081 struct req_que *req = ha->req_q_map[0];
eaac30be 5082
7c3df132 5083 ql_dbg(ql_dbg_init, vha, 0x008b,
cfb0919c 5084 "FW: Loading firmware from flash (%x).\n", faddr);
eaac30be 5085
d1c61909
AV		 5086 rval = QLA_SUCCESS;
5087
5088 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 5089 dcode = (uint32_t *)req->ring;
d1c61909
AV		 5090 *srisc_addr = 0;
5091
5092 /* Validate firmware image by checking version. */
e315cd28 5093 qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
d1c61909
AV		 5094 for (i = 0; i < 4; i++)
5095 dcode[i] = be32_to_cpu(dcode[i]);
5096 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
5097 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
5098 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
5099 dcode[3] == 0)) {
7c3df132
SK		 5100 ql_log(ql_log_fatal, vha, 0x008c,
5101 "Unable to verify the integrity of flash firmware "
5102 "image.\n");
5103 ql_log(ql_log_fatal, vha, 0x008d,
5104 "Firmware data: %08x %08x %08x %08x.\n",
5105 dcode[0], dcode[1], dcode[2], dcode[3]);
d1c61909
AV		 5106
5107 return QLA_FUNCTION_FAILED;
5108 }
5109
5110 while (segments && rval == QLA_SUCCESS) {
5111 /* Read segment's load information. */
e315cd28 5112 qla24xx_read_flash_data(vha, dcode, faddr, 4);
d1c61909
AV		 5113
5114 risc_addr = be32_to_cpu(dcode[2]);
5115 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
5116 risc_size = be32_to_cpu(dcode[3]);
5117
5118 fragment = 0;
5119 while (risc_size > 0 && rval == QLA_SUCCESS) {
5120 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
5121 if (dlen > risc_size)
5122 dlen = risc_size;
5123
7c3df132
SK		 5124 ql_dbg(ql_dbg_init, vha, 0x008e,
5125 "Loading risc segment@ risc addr %x "
5126 "number of dwords 0x%x offset 0x%x.\n",
5127 risc_addr, dlen, faddr);
d1c61909 5128
e315cd28 5129 qla24xx_read_flash_data(vha, dcode, faddr, dlen);
d1c61909
AV		 5130 for (i = 0; i < dlen; i++)
5131 dcode[i] = swab32(dcode[i]);
5132
73208dfd 5133 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
d1c61909
AV		 5134 dlen);
5135 if (rval) {
7c3df132
SK		 5136 ql_log(ql_log_fatal, vha, 0x008f,
5137 "Failed to load segment %d of firmware.\n",
5138 fragment);
d1c61909
AV		 5139 break;
5140 }
5141
5142 faddr += dlen;
5143 risc_addr += dlen;
5144 risc_size -= dlen;
5145 fragment++;
5146 }
5147
5148 /* Next segment. */
5149 segments--;
5150 }
5151
f73cb695
CD		 5152 if (!IS_QLA27XX(ha))
5153 return rval;
5154
5155 if (ha->fw_dump_template)
5156 vfree(ha->fw_dump_template);
5157 ha->fw_dump_template = NULL;
5158 ha->fw_dump_template_len = 0;
5159
5160 ql_dbg(ql_dbg_init, vha, 0x0161,
5161 "Loading fwdump template from %x\n", faddr);
5162 qla24xx_read_flash_data(vha, dcode, faddr, 7);
5163 risc_size = be32_to_cpu(dcode[2]);
5164 ql_dbg(ql_dbg_init, vha, 0x0162,
5165 "-> array size %x dwords\n", risc_size);
5166 if (risc_size == 0 || risc_size == ~0)
5167 goto default_template;
5168
5169 dlen = (risc_size - 8) * sizeof(*dcode);
5170 ql_dbg(ql_dbg_init, vha, 0x0163,
5171 "-> template allocating %x bytes...\n", dlen);
5172 ha->fw_dump_template = vmalloc(dlen);
5173 if (!ha->fw_dump_template) {
5174 ql_log(ql_log_warn, vha, 0x0164,
5175 "Failed fwdump template allocate %x bytes.\n", risc_size);
5176 goto default_template;
5177 }
5178
5179 faddr += 7;
5180 risc_size -= 8;
5181 dcode = ha->fw_dump_template;
5182 qla24xx_read_flash_data(vha, dcode, faddr, risc_size);
5183 for (i = 0; i < risc_size; i++)
5184 dcode[i] = le32_to_cpu(dcode[i]);
5185
5186 if (!qla27xx_fwdt_template_valid(dcode)) {
5187 ql_log(ql_log_warn, vha, 0x0165,
5188 "Failed fwdump template validate\n");
5189 goto default_template;
5190 }
5191
5192 dlen = qla27xx_fwdt_template_size(dcode);
5193 ql_dbg(ql_dbg_init, vha, 0x0166,
5194 "-> template size %x bytes\n", dlen);
5195 if (dlen > risc_size * sizeof(*dcode)) {
5196 ql_log(ql_log_warn, vha, 0x0167,
5197 "Failed fwdump template exceeds array by %lx bytes\n",
5198 dlen - risc_size * sizeof(*dcode));
5199 goto default_template;
5200 }
5201 ha->fw_dump_template_len = dlen;
5202 return rval;
5203
5204default_template:
5205 ql_log(ql_log_warn, vha, 0x0168, "Using default fwdump template\n");
5206 if (ha->fw_dump_template)
5207 vfree(ha->fw_dump_template);
5208 ha->fw_dump_template = NULL;
5209 ha->fw_dump_template_len = 0;
5210
5211 dlen = qla27xx_fwdt_template_default_size();
5212 ql_dbg(ql_dbg_init, vha, 0x0169,
5213 "-> template allocating %x bytes...\n", dlen);
5214 ha->fw_dump_template = vmalloc(dlen);
5215 if (!ha->fw_dump_template) {
5216 ql_log(ql_log_warn, vha, 0x016a,
5217 "Failed fwdump template allocate %x bytes.\n", risc_size);
5218 goto failed_template;
5219 }
5220
5221 dcode = ha->fw_dump_template;
5222 risc_size = dlen / sizeof(*dcode);
5223 memcpy(dcode, qla27xx_fwdt_template_default(), dlen);
5224 for (i = 0; i < risc_size; i++)
5225 dcode[i] = be32_to_cpu(dcode[i]);
5226
5227 if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) {
5228 ql_log(ql_log_warn, vha, 0x016b,
5229 "Failed fwdump template validate\n");
5230 goto failed_template;
5231 }
5232
5233 dlen = qla27xx_fwdt_template_size(ha->fw_dump_template);
5234 ql_dbg(ql_dbg_init, vha, 0x016c,
5235 "-> template size %x bytes\n", dlen);
5236 ha->fw_dump_template_len = dlen;
5237 return rval;
5238
5239failed_template:
5240 ql_log(ql_log_warn, vha, 0x016d, "Failed default fwdump template\n");
5241 if (ha->fw_dump_template)
5242 vfree(ha->fw_dump_template);
5243 ha->fw_dump_template = NULL;
5244 ha->fw_dump_template_len = 0;
d1c61909
AV		 5245 return rval;
5246}
5247
e9454a88 5248#define QLA_FW_URL "http://ldriver.qlogic.com/firmware/"
d1c61909 5249
0107109e 5250int
e315cd28 5251qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5433383e
AV		 5252{
5253 int rval;
5254 int i, fragment;
5255 uint16_t *wcode, *fwcode;
5256 uint32_t risc_addr, risc_size, fwclen, wlen, *seg;
5257 struct fw_blob *blob;
e315cd28 5258 struct qla_hw_data *ha = vha->hw;
73208dfd 5259 struct req_que *req = ha->req_q_map[0];
5433383e
AV		 5260
5261 /* Load firmware blob. */
e315cd28 5262 blob = qla2x00_request_firmware(vha);
5433383e 5263 if (!blob) {
7c3df132
SK		 5264 ql_log(ql_log_info, vha, 0x0083,
5265 "Fimware image unavailable.\n");
5266 ql_log(ql_log_info, vha, 0x0084,
5267 "Firmware images can be retrieved from: "QLA_FW_URL ".\n");
5433383e
AV		 5268 return QLA_FUNCTION_FAILED;
5269 }
5270
5271 rval = QLA_SUCCESS;
5272
73208dfd 5273 wcode = (uint16_t *)req->ring;
5433383e
AV		 5274 *srisc_addr = 0;
5275 fwcode = (uint16_t *)blob->fw->data;
5276 fwclen = 0;
5277
5278 /* Validate firmware image by checking version. */
5279 if (blob->fw->size < 8 * sizeof(uint16_t)) {
7c3df132
SK		 5280 ql_log(ql_log_fatal, vha, 0x0085,
5281 "Unable to verify integrity of firmware image (%Zd).\n",
5433383e
AV		 5282 blob->fw->size);
5283 goto fail_fw_integrity;
5284 }
5285 for (i = 0; i < 4; i++)
5286 wcode[i] = be16_to_cpu(fwcode[i + 4]);
5287 if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff &&
5288 wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 &&
5289 wcode[2] == 0 && wcode[3] == 0)) {
7c3df132
SK		 5290 ql_log(ql_log_fatal, vha, 0x0086,
5291 "Unable to verify integrity of firmware image.\n");
5292 ql_log(ql_log_fatal, vha, 0x0087,
5293 "Firmware data: %04x %04x %04x %04x.\n",
5294 wcode[0], wcode[1], wcode[2], wcode[3]);
5433383e
AV		 5295 goto fail_fw_integrity;
5296 }
5297
5298 seg = blob->segs;
5299 while (*seg && rval == QLA_SUCCESS) {
5300 risc_addr = *seg;
5301 *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr;
5302 risc_size = be16_to_cpu(fwcode[3]);
5303
5304 /* Validate firmware image size. */
5305 fwclen += risc_size * sizeof(uint16_t);
5306 if (blob->fw->size < fwclen) {
7c3df132 5307 ql_log(ql_log_fatal, vha, 0x0088,
5433383e 5308 "Unable to verify integrity of firmware image "
7c3df132 5309 "(%Zd).\n", blob->fw->size);
5433383e
AV		 5310 goto fail_fw_integrity;
5311 }
5312
5313 fragment = 0;
5314 while (risc_size > 0 && rval == QLA_SUCCESS) {
5315 wlen = (uint16_t)(ha->fw_transfer_size >> 1);
5316 if (wlen > risc_size)
5317 wlen = risc_size;
7c3df132
SK		 5318 ql_dbg(ql_dbg_init, vha, 0x0089,
5319 "Loading risc segment@ risc addr %x number of "
5320 "words 0x%x.\n", risc_addr, wlen);
5433383e
AV		 5321
5322 for (i = 0; i < wlen; i++)
5323 wcode[i] = swab16(fwcode[i]);
5324
73208dfd 5325 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
5433383e
AV		 5326 wlen);
5327 if (rval) {
7c3df132
SK		 5328 ql_log(ql_log_fatal, vha, 0x008a,
5329 "Failed to load segment %d of firmware.\n",
5330 fragment);
5433383e
AV		 5331 break;
5332 }
5333
5334 fwcode += wlen;
5335 risc_addr += wlen;
5336 risc_size -= wlen;
5337 fragment++;
5338 }
5339
5340 /* Next segment. */
5341 seg++;
5342 }
5343 return rval;
5344
5345fail_fw_integrity:
5346 return QLA_FUNCTION_FAILED;
5347}
5348
eaac30be
AV		 5349static int
5350qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
0107109e
AV		 5351{
5352 int rval;
5353 int segments, fragment;
5354 uint32_t *dcode, dlen;
5355 uint32_t risc_addr;
5356 uint32_t risc_size;
5357 uint32_t i;
5433383e 5358 struct fw_blob *blob;
f73cb695
CD		 5359 const uint32_t *fwcode;
5360 uint32_t fwclen;
e315cd28 5361 struct qla_hw_data *ha = vha->hw;
73208dfd 5362 struct req_que *req = ha->req_q_map[0];
0107109e 5363
5433383e 5364 /* Load firmware blob. */
e315cd28 5365 blob = qla2x00_request_firmware(vha);
5433383e 5366 if (!blob) {
7c3df132
SK		 5367 ql_log(ql_log_warn, vha, 0x0090,
5368 "Fimware image unavailable.\n");
5369 ql_log(ql_log_warn, vha, 0x0091,
5370 "Firmware images can be retrieved from: "
5371 QLA_FW_URL ".\n");
d1c61909 5372
eaac30be 5373 return QLA_FUNCTION_FAILED;
0107109e
AV		 5374 }
5375
cfb0919c
CD		 5376 ql_dbg(ql_dbg_init, vha, 0x0092,
5377 "FW: Loading via request-firmware.\n");
eaac30be 5378
0107109e
AV		 5379 rval = QLA_SUCCESS;
5380
5381 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 5382 dcode = (uint32_t *)req->ring;
0107109e 5383 *srisc_addr = 0;
5433383e 5384 fwcode = (uint32_t *)blob->fw->data;
0107109e
AV		 5385 fwclen = 0;
5386
5387 /* Validate firmware image by checking version. */
5433383e 5388 if (blob->fw->size < 8 * sizeof(uint32_t)) {
7c3df132
SK		 5389 ql_log(ql_log_fatal, vha, 0x0093,
5390 "Unable to verify integrity of firmware image (%Zd).\n",
5433383e 5391 blob->fw->size);
f73cb695 5392 return QLA_FUNCTION_FAILED;
0107109e
AV		 5393 }
5394 for (i = 0; i < 4; i++)
5395 dcode[i] = be32_to_cpu(fwcode[i + 4]);
5396 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
5397 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
5398 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
5399 dcode[3] == 0)) {
7c3df132
SK		 5400 ql_log(ql_log_fatal, vha, 0x0094,
5401 "Unable to verify integrity of firmware image (%Zd).\n",
5402 blob->fw->size);
5403 ql_log(ql_log_fatal, vha, 0x0095,
5404 "Firmware data: %08x %08x %08x %08x.\n",
5405 dcode[0], dcode[1], dcode[2], dcode[3]);
f73cb695 5406 return QLA_FUNCTION_FAILED;
0107109e
AV		 5407 }
5408
5409 while (segments && rval == QLA_SUCCESS) {
5410 risc_addr = be32_to_cpu(fwcode[2]);
5411 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
5412 risc_size = be32_to_cpu(fwcode[3]);
5413
5414 /* Validate firmware image size. */
5415 fwclen += risc_size * sizeof(uint32_t);
5433383e 5416 if (blob->fw->size < fwclen) {
7c3df132 5417 ql_log(ql_log_fatal, vha, 0x0096,
5433383e 5418 "Unable to verify integrity of firmware image "
7c3df132 5419 "(%Zd).\n", blob->fw->size);
f73cb695 5420 return QLA_FUNCTION_FAILED;
0107109e
AV		 5421 }
5422
5423 fragment = 0;
5424 while (risc_size > 0 && rval == QLA_SUCCESS) {
5425 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
5426 if (dlen > risc_size)
5427 dlen = risc_size;
5428
7c3df132
SK		 5429 ql_dbg(ql_dbg_init, vha, 0x0097,
5430 "Loading risc segment@ risc addr %x "
5431 "number of dwords 0x%x.\n", risc_addr, dlen);
0107109e
AV		 5432
5433 for (i = 0; i < dlen; i++)
5434 dcode[i] = swab32(fwcode[i]);
5435
73208dfd 5436 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
590f98e5 5437 dlen);
0107109e 5438 if (rval) {
7c3df132
SK		 5439 ql_log(ql_log_fatal, vha, 0x0098,
5440 "Failed to load segment %d of firmware.\n",
5441 fragment);
0107109e
AV		 5442 break;
5443 }
5444
5445 fwcode += dlen;
5446 risc_addr += dlen;
5447 risc_size -= dlen;
5448 fragment++;
5449 }
5450
5451 /* Next segment. */
5452 segments--;
5453 }
f73cb695
CD		 5454
5455 if (!IS_QLA27XX(ha))
5456 return rval;
5457
5458 if (ha->fw_dump_template)
5459 vfree(ha->fw_dump_template);
5460 ha->fw_dump_template = NULL;
5461 ha->fw_dump_template_len = 0;
5462
5463 ql_dbg(ql_dbg_init, vha, 0x171,
5464 "Loading fwdump template from %lx\n",
5465 (void *)fwcode - (void *)blob->fw->data);
5466 risc_size = be32_to_cpu(fwcode[2]);
5467 ql_dbg(ql_dbg_init, vha, 0x172,
5468 "-> array size %x dwords\n", risc_size);
5469 if (risc_size == 0 || risc_size == ~0)
5470 goto default_template;
5471
5472 dlen = (risc_size - 8) * sizeof(*fwcode);
5473 ql_dbg(ql_dbg_init, vha, 0x0173,
5474 "-> template allocating %x bytes...\n", dlen);
5475 ha->fw_dump_template = vmalloc(dlen);
5476 if (!ha->fw_dump_template) {
5477 ql_log(ql_log_warn, vha, 0x0174,
5478 "Failed fwdump template allocate %x bytes.\n", risc_size);
5479 goto default_template;
5480 }
5481
5482 fwcode += 7;
5483 risc_size -= 8;
5484 dcode = ha->fw_dump_template;
5485 for (i = 0; i < risc_size; i++)
5486 dcode[i] = le32_to_cpu(fwcode[i]);
5487
5488 if (!qla27xx_fwdt_template_valid(dcode)) {
5489 ql_log(ql_log_warn, vha, 0x0175,
5490 "Failed fwdump template validate\n");
5491 goto default_template;
5492 }
5493
5494 dlen = qla27xx_fwdt_template_size(dcode);
5495 ql_dbg(ql_dbg_init, vha, 0x0176,
5496 "-> template size %x bytes\n", dlen);
5497 if (dlen > risc_size * sizeof(*fwcode)) {
5498 ql_log(ql_log_warn, vha, 0x0177,
5499 "Failed fwdump template exceeds array by %lx bytes\n",
5500 dlen - risc_size * sizeof(*fwcode));
5501 goto default_template;
5502 }
5503 ha->fw_dump_template_len = dlen;
0107109e
AV		 5504 return rval;
5505
f73cb695
CD		 5506default_template:
5507 ql_log(ql_log_warn, vha, 0x0178, "Using default fwdump template\n");
5508 if (ha->fw_dump_template)
5509 vfree(ha->fw_dump_template);
5510 ha->fw_dump_template = NULL;
5511 ha->fw_dump_template_len = 0;
5512
5513 dlen = qla27xx_fwdt_template_default_size();
5514 ql_dbg(ql_dbg_init, vha, 0x0179,
5515 "-> template allocating %x bytes...\n", dlen);
5516 ha->fw_dump_template = vmalloc(dlen);
5517 if (!ha->fw_dump_template) {
5518 ql_log(ql_log_warn, vha, 0x017a,
5519 "Failed fwdump template allocate %x bytes.\n", risc_size);
5520 goto failed_template;
5521 }
5522
5523 dcode = ha->fw_dump_template;
5524 risc_size = dlen / sizeof(*fwcode);
5525 fwcode = qla27xx_fwdt_template_default();
5526 for (i = 0; i < risc_size; i++)
5527 dcode[i] = be32_to_cpu(fwcode[i]);
5528
5529 if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) {
5530 ql_log(ql_log_warn, vha, 0x017b,
5531 "Failed fwdump template validate\n");
5532 goto failed_template;
5533 }
5534
5535 dlen = qla27xx_fwdt_template_size(ha->fw_dump_template);
5536 ql_dbg(ql_dbg_init, vha, 0x017c,
5537 "-> template size %x bytes\n", dlen);
5538 ha->fw_dump_template_len = dlen;
5539 return rval;
5540
5541failed_template:
5542 ql_log(ql_log_warn, vha, 0x017d, "Failed default fwdump template\n");
5543 if (ha->fw_dump_template)
5544 vfree(ha->fw_dump_template);
5545 ha->fw_dump_template = NULL;
5546 ha->fw_dump_template_len = 0;
5547 return rval;
0107109e 5548}
18c6c127 5549
eaac30be
AV		 5550int
5551qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5552{
5553 int rval;
5554
e337d907
AV		 5555 if (ql2xfwloadbin == 1)
5556 return qla81xx_load_risc(vha, srisc_addr);
5557
eaac30be
AV		 5558 /*
5559 * FW Load priority:
5560 * 1) Firmware via request-firmware interface (.bin file).
5561 * 2) Firmware residing in flash.
5562 */
5563 rval = qla24xx_load_risc_blob(vha, srisc_addr);
5564 if (rval == QLA_SUCCESS)
5565 return rval;
5566
cbc8eb67
AV		 5567 return qla24xx_load_risc_flash(vha, srisc_addr,
5568 vha->hw->flt_region_fw);
eaac30be
AV		 5569}
5570
5571int
5572qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5573{
5574 int rval;
cbc8eb67 5575 struct qla_hw_data *ha = vha->hw;
eaac30be 5576
e337d907 5577 if (ql2xfwloadbin == 2)
cbc8eb67 5578 goto try_blob_fw;
e337d907 5579
eaac30be
AV		 5580 /*
5581 * FW Load priority:
5582 * 1) Firmware residing in flash.
5583 * 2) Firmware via request-firmware interface (.bin file).
cbc8eb67 5584 * 3) Golden-Firmware residing in flash -- limited operation.
eaac30be 5585 */
cbc8eb67 5586 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
eaac30be
AV		 5587 if (rval == QLA_SUCCESS)
5588 return rval;
5589
cbc8eb67
AV		 5590try_blob_fw:
5591 rval = qla24xx_load_risc_blob(vha, srisc_addr);
5592 if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw)
5593 return rval;
5594
7c3df132
SK		 5595 ql_log(ql_log_info, vha, 0x0099,
5596 "Attempting to fallback to golden firmware.\n");
cbc8eb67
AV		 5597 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
5598 if (rval != QLA_SUCCESS)
5599 return rval;
5600
7c3df132 5601 ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n");
cbc8eb67 5602 ha->flags.running_gold_fw = 1;
cbc8eb67 5603 return rval;
eaac30be
AV		 5604}
5605
18c6c127 5606void
e315cd28 5607qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha)
18c6c127
AV		 5608{
5609 int ret, retries;
e315cd28 5610 struct qla_hw_data *ha = vha->hw;
18c6c127 5611
85880801
AV		 5612 if (ha->flags.pci_channel_io_perm_failure)
5613 return;
e428924c 5614 if (!IS_FWI2_CAPABLE(ha))
18c6c127 5615 return;
75edf81d
AV		 5616 if (!ha->fw_major_version)
5617 return;
18c6c127 5618
e315cd28 5619 ret = qla2x00_stop_firmware(vha);
7c7f1f29 5620 for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&
b469a7cb 5621 ret != QLA_INVALID_COMMAND && retries ; retries--) {
e315cd28
AC		 5622 ha->isp_ops->reset_chip(vha);
5623 if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS)
18c6c127 5624 continue;
e315cd28 5625 if (qla2x00_setup_chip(vha) != QLA_SUCCESS)
18c6c127 5626 continue;
7c3df132
SK		 5627 ql_log(ql_log_info, vha, 0x8015,
5628 "Attempting retry of stop-firmware command.\n");
e315cd28 5629 ret = qla2x00_stop_firmware(vha);
18c6c127
AV		 5630 }
5631}
2c3dfe3f
SJ		 5632
5633int
e315cd28 5634qla24xx_configure_vhba(scsi_qla_host_t *vha)
2c3dfe3f
SJ		 5635{
5636 int rval = QLA_SUCCESS;
0b91d116 5637 int rval2;
2c3dfe3f 5638 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28
AC		 5639 struct qla_hw_data *ha = vha->hw;
5640 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
67c2e93a
AC		 5641 struct req_que *req;
5642 struct rsp_que *rsp;
2c3dfe3f 5643
e315cd28 5644 if (!vha->vp_idx)
2c3dfe3f
SJ		 5645 return -EINVAL;
5646
e315cd28 5647 rval = qla2x00_fw_ready(base_vha);
7163ea81 5648 if (ha->flags.cpu_affinity_enabled)
67c2e93a
AC		 5649 req = ha->req_q_map[0];
5650 else
5651 req = vha->req;
5652 rsp = req->rsp;
5653
2c3dfe3f 5654 if (rval == QLA_SUCCESS) {
e315cd28 5655 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
73208dfd 5656 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
2c3dfe3f
SJ		 5657 }
5658
e315cd28 5659 vha->flags.management_server_logged_in = 0;
2c3dfe3f
SJ		 5660
5661 /* Login to SNS first */
0b91d116
CD		 5662 rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb,
5663 BIT_1);
5664 if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
5665 if (rval2 == QLA_MEMORY_ALLOC_FAILED)
5666 ql_dbg(ql_dbg_init, vha, 0x0120,
5667 "Failed SNS login: loop_id=%x, rval2=%d\n",
5668 NPH_SNS, rval2);
5669 else
5670 ql_dbg(ql_dbg_init, vha, 0x0103,
5671 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x "
5672 "mb[2]=%x mb[6]=%x mb[7]=%x.\n",
5673 NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]);
2c3dfe3f
SJ		 5674 return (QLA_FUNCTION_FAILED);
5675 }
5676
e315cd28
AC		 5677 atomic_set(&vha->loop_down_timer, 0);
5678 atomic_set(&vha->loop_state, LOOP_UP);
5679 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5680 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
5681 rval = qla2x00_loop_resync(base_vha);
2c3dfe3f
SJ		 5682
5683 return rval;
5684}
4d4df193
HK		 5685
5686/* 84XX Support **************************************************************/
5687
5688static LIST_HEAD(qla_cs84xx_list);
5689static DEFINE_MUTEX(qla_cs84xx_mutex);
5690
5691static struct qla_chip_state_84xx *
e315cd28 5692qla84xx_get_chip(struct scsi_qla_host *vha)
4d4df193
HK		 5693{
5694 struct qla_chip_state_84xx *cs84xx;
e315cd28 5695 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5696
5697 mutex_lock(&qla_cs84xx_mutex);
5698
5699 /* Find any shared 84xx chip. */
5700 list_for_each_entry(cs84xx, &qla_cs84xx_list, list) {
5701 if (cs84xx->bus == ha->pdev->bus) {
5702 kref_get(&cs84xx->kref);
5703 goto done;
5704 }
5705 }
5706
5707 cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL);
5708 if (!cs84xx)
5709 goto done;
5710
5711 kref_init(&cs84xx->kref);
5712 spin_lock_init(&cs84xx->access_lock);
5713 mutex_init(&cs84xx->fw_update_mutex);
5714 cs84xx->bus = ha->pdev->bus;
5715
5716 list_add_tail(&cs84xx->list, &qla_cs84xx_list);
5717done:
5718 mutex_unlock(&qla_cs84xx_mutex);
5719 return cs84xx;
5720}
5721
5722static void
5723__qla84xx_chip_release(struct kref *kref)
5724{
5725 struct qla_chip_state_84xx *cs84xx =
5726 container_of(kref, struct qla_chip_state_84xx, kref);
5727
5728 mutex_lock(&qla_cs84xx_mutex);
5729 list_del(&cs84xx->list);
5730 mutex_unlock(&qla_cs84xx_mutex);
5731 kfree(cs84xx);
5732}
5733
5734void
e315cd28 5735qla84xx_put_chip(struct scsi_qla_host *vha)
4d4df193 5736{
e315cd28 5737 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5738 if (ha->cs84xx)
5739 kref_put(&ha->cs84xx->kref, __qla84xx_chip_release);
5740}
5741
5742static int
e315cd28 5743qla84xx_init_chip(scsi_qla_host_t *vha)
4d4df193
HK		 5744{
5745 int rval;
5746 uint16_t status[2];
e315cd28 5747 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5748
5749 mutex_lock(&ha->cs84xx->fw_update_mutex);
5750
e315cd28 5751 rval = qla84xx_verify_chip(vha, status);
4d4df193
HK		 5752
5753 mutex_unlock(&ha->cs84xx->fw_update_mutex);
5754
5755 return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED:
5756 QLA_SUCCESS;
5757}
3a03eb79
AV		 5758
5759/* 81XX Support **************************************************************/
5760
5761int
5762qla81xx_nvram_config(scsi_qla_host_t *vha)
5763{
5764 int rval;
5765 struct init_cb_81xx *icb;
5766 struct nvram_81xx *nv;
5767 uint32_t *dptr;
5768 uint8_t *dptr1, *dptr2;
5769 uint32_t chksum;
5770 uint16_t cnt;
5771 struct qla_hw_data *ha = vha->hw;
5772
5773 rval = QLA_SUCCESS;
5774 icb = (struct init_cb_81xx *)ha->init_cb;
5775 nv = ha->nvram;
5776
5777 /* Determine NVRAM starting address. */
5778 ha->nvram_size = sizeof(struct nvram_81xx);
3a03eb79 5779 ha->vpd_size = FA_NVRAM_VPD_SIZE;
7ec0effd
AD		 5780 if (IS_P3P_TYPE(ha) || IS_QLA8031(ha))
5781 ha->vpd_size = FA_VPD_SIZE_82XX;
3a03eb79
AV		 5782
5783 /* Get VPD data into cache */
5784 ha->vpd = ha->nvram + VPD_OFFSET;
3d79038f
AV		 5785 ha->isp_ops->read_optrom(vha, ha->vpd, ha->flt_region_vpd << 2,
5786 ha->vpd_size);
3a03eb79
AV		 5787
5788 /* Get NVRAM data into cache and calculate checksum. */
3d79038f 5789 ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2,
3a03eb79 5790 ha->nvram_size);
3d79038f 5791 dptr = (uint32_t *)nv;
3a03eb79
AV		 5792 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
5793 chksum += le32_to_cpu(*dptr++);
5794
7c3df132
SK		 5795 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
5796 "Contents of NVRAM:\n");
5797 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
5798 (uint8_t *)nv, ha->nvram_size);
3a03eb79
AV		 5799
5800 /* Bad NVRAM data, set defaults parameters. */
5801 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
5802 || nv->id[3] != ' ' ||
5803 nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
5804 /* Reset NVRAM data. */
7c3df132 5805 ql_log(ql_log_info, vha, 0x0073,
9e336520 5806 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132 5807 "version=0x%x.\n", chksum, nv->id[0],
3a03eb79 5808 le16_to_cpu(nv->nvram_version));
7c3df132
SK		 5809 ql_log(ql_log_info, vha, 0x0074,
5810 "Falling back to functioning (yet invalid -- WWPN) "
5811 "defaults.\n");
3a03eb79
AV		 5812
5813 /*
5814 * Set default initialization control block.
5815 */
5816 memset(nv, 0, ha->nvram_size);
5817 nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
5818 nv->version = __constant_cpu_to_le16(ICB_VERSION);
5819 nv->frame_payload_size = __constant_cpu_to_le16(2048);
5820 nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
5821 nv->exchange_count = __constant_cpu_to_le16(0);
5822 nv->port_name[0] = 0x21;
f73cb695 5823 nv->port_name[1] = 0x00 + ha->port_no + 1;
3a03eb79
AV		 5824 nv->port_name[2] = 0x00;
5825 nv->port_name[3] = 0xe0;
5826 nv->port_name[4] = 0x8b;
5827 nv->port_name[5] = 0x1c;
5828 nv->port_name[6] = 0x55;
5829 nv->port_name[7] = 0x86;
5830 nv->node_name[0] = 0x20;
5831 nv->node_name[1] = 0x00;
5832 nv->node_name[2] = 0x00;
5833 nv->node_name[3] = 0xe0;
5834 nv->node_name[4] = 0x8b;
5835 nv->node_name[5] = 0x1c;
5836 nv->node_name[6] = 0x55;
5837 nv->node_name[7] = 0x86;
5838 nv->login_retry_count = __constant_cpu_to_le16(8);
5839 nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
5840 nv->login_timeout = __constant_cpu_to_le16(0);
5841 nv->firmware_options_1 =
5842 __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
5843 nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
5844 nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
5845 nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
5846 nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
5847 nv->efi_parameters = __constant_cpu_to_le32(0);
5848 nv->reset_delay = 5;
5849 nv->max_luns_per_target = __constant_cpu_to_le16(128);
5850 nv->port_down_retry_count = __constant_cpu_to_le16(30);
6246b8a1 5851 nv->link_down_timeout = __constant_cpu_to_le16(180);
eeebcc92 5852 nv->enode_mac[0] = 0x00;
6246b8a1
GM		 5853 nv->enode_mac[1] = 0xC0;
5854 nv->enode_mac[2] = 0xDD;
3a03eb79
AV		 5855 nv->enode_mac[3] = 0x04;
5856 nv->enode_mac[4] = 0x05;
f73cb695 5857 nv->enode_mac[5] = 0x06 + ha->port_no + 1;
3a03eb79
AV		 5858
5859 rval = 1;
5860 }
5861
9e522cd8
AE		 5862 if (IS_T10_PI_CAPABLE(ha))
5863 nv->frame_payload_size &= ~7;
5864
aa230bc5
AE		 5865 qlt_81xx_config_nvram_stage1(vha, nv);
5866
3a03eb79 5867 /* Reset Initialization control block */
773120e4 5868 memset(icb, 0, ha->init_cb_size);
3a03eb79
AV		 5869
5870 /* Copy 1st segment. */
5871 dptr1 = (uint8_t *)icb;
5872 dptr2 = (uint8_t *)&nv->version;
5873 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
5874 while (cnt--)
5875 *dptr1++ = *dptr2++;
5876
5877 icb->login_retry_count = nv->login_retry_count;
5878
5879 /* Copy 2nd segment. */
5880 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
5881 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
5882 cnt = (uint8_t *)&icb->reserved_5 -
5883 (uint8_t *)&icb->interrupt_delay_timer;
5884 while (cnt--)
5885 *dptr1++ = *dptr2++;
5886
5887 memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac));
5888 /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */
5889 if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) {
69e5f1ea
AV		 5890 icb->enode_mac[0] = 0x00;
5891 icb->enode_mac[1] = 0xC0;
5892 icb->enode_mac[2] = 0xDD;
3a03eb79
AV		 5893 icb->enode_mac[3] = 0x04;
5894 icb->enode_mac[4] = 0x05;
f73cb695 5895 icb->enode_mac[5] = 0x06 + ha->port_no + 1;
3a03eb79
AV		 5896 }
5897
b64b0e8f
AV		 5898 /* Use extended-initialization control block. */
5899 memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb));
5900
3a03eb79
AV		 5901 /*
5902 * Setup driver NVRAM options.
5903 */
5904 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
a9083016 5905 "QLE8XXX");
3a03eb79 5906
aa230bc5
AE		 5907 qlt_81xx_config_nvram_stage2(vha, icb);
5908
3a03eb79
AV		 5909 /* Use alternate WWN? */
5910 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
5911 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
5912 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
5913 }
5914
5915 /* Prepare nodename */
5916 if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
5917 /*
5918 * Firmware will apply the following mask if the nodename was
5919 * not provided.
5920 */
5921 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
5922 icb->node_name[0] &= 0xF0;
5923 }
5924
5925 /* Set host adapter parameters. */
5926 ha->flags.disable_risc_code_load = 0;
5927 ha->flags.enable_lip_reset = 0;
5928 ha->flags.enable_lip_full_login =
5929 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
5930 ha->flags.enable_target_reset =
5931 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
5932 ha->flags.enable_led_scheme = 0;
5933 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
5934
5935 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
5936 (BIT_6 | BIT_5 | BIT_4)) >> 4;
5937
5938 /* save HBA serial number */
5939 ha->serial0 = icb->port_name[5];
5940 ha->serial1 = icb->port_name[6];
5941 ha->serial2 = icb->port_name[7];
5942 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
5943 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
5944
5945 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
5946
5947 ha->retry_count = le16_to_cpu(nv->login_retry_count);
5948
5949 /* Set minimum login_timeout to 4 seconds. */
5950 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
5951 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
5952 if (le16_to_cpu(nv->login_timeout) < 4)
5953 nv->login_timeout = __constant_cpu_to_le16(4);
5954 ha->login_timeout = le16_to_cpu(nv->login_timeout);
5955 icb->login_timeout = nv->login_timeout;
5956
5957 /* Set minimum RATOV to 100 tenths of a second. */
5958 ha->r_a_tov = 100;
5959
5960 ha->loop_reset_delay = nv->reset_delay;
5961
5962 /* Link Down Timeout = 0:
5963 *
7ec0effd 5964 * When Port Down timer expires we will start returning
3a03eb79
AV		 5965 * I/O's to OS with "DID_NO_CONNECT".
5966 *
5967 * Link Down Timeout != 0:
5968 *
5969 * The driver waits for the link to come up after link down
5970 * before returning I/Os to OS with "DID_NO_CONNECT".
5971 */
5972 if (le16_to_cpu(nv->link_down_timeout) == 0) {
5973 ha->loop_down_abort_time =
5974 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
5975 } else {
5976 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
5977 ha->loop_down_abort_time =
5978 (LOOP_DOWN_TIME - ha->link_down_timeout);
5979 }
5980
5981 /* Need enough time to try and get the port back. */
5982 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
5983 if (qlport_down_retry)
5984 ha->port_down_retry_count = qlport_down_retry;
5985
5986 /* Set login_retry_count */
5987 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
5988 if (ha->port_down_retry_count ==
5989 le16_to_cpu(nv->port_down_retry_count) &&
5990 ha->port_down_retry_count > 3)
5991 ha->login_retry_count = ha->port_down_retry_count;
5992 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
5993 ha->login_retry_count = ha->port_down_retry_count;
5994 if (ql2xloginretrycount)
5995 ha->login_retry_count = ql2xloginretrycount;
5996
6246b8a1 5997 /* if not running MSI-X we need handshaking on interrupts */
f73cb695 5998 if (!vha->hw->flags.msix_enabled && (IS_QLA83XX(ha) || IS_QLA27XX(ha)))
6246b8a1
GM		 5999 icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_22);
6000
3a03eb79
AV		 6001 /* Enable ZIO. */
6002 if (!vha->flags.init_done) {
6003 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
6004 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
6005 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
6006 le16_to_cpu(icb->interrupt_delay_timer): 2;
6007 }
6008 icb->firmware_options_2 &= __constant_cpu_to_le32(
6009 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
6010 vha->flags.process_response_queue = 0;
6011 if (ha->zio_mode != QLA_ZIO_DISABLED) {
6012 ha->zio_mode = QLA_ZIO_MODE_6;
6013
7c3df132 6014 ql_log(ql_log_info, vha, 0x0075,
3a03eb79 6015 "ZIO mode %d enabled; timer delay (%d us).\n",
7c3df132
SK		 6016 ha->zio_mode,
6017 ha->zio_timer * 100);
3a03eb79
AV		 6018
6019 icb->firmware_options_2 |= cpu_to_le32(
6020 (uint32_t)ha->zio_mode);
6021 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
6022 vha->flags.process_response_queue = 1;
6023 }
6024
6025 if (rval) {
7c3df132
SK		 6026 ql_log(ql_log_warn, vha, 0x0076,
6027 "NVRAM configuration failed.\n");
3a03eb79
AV		 6028 }
6029 return (rval);
6030}
6031
a9083016
GM		 6032int
6033qla82xx_restart_isp(scsi_qla_host_t *vha)
6034{
6035 int status, rval;
6036 uint32_t wait_time;
6037 struct qla_hw_data *ha = vha->hw;
6038 struct req_que *req = ha->req_q_map[0];
6039 struct rsp_que *rsp = ha->rsp_q_map[0];
6040 struct scsi_qla_host *vp;
feafb7b1 6041 unsigned long flags;
a9083016
GM		 6042
6043 status = qla2x00_init_rings(vha);
6044 if (!status) {
6045 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
6046 ha->flags.chip_reset_done = 1;
6047
6048 status = qla2x00_fw_ready(vha);
6049 if (!status) {
7c3df132
SK		 6050 ql_log(ql_log_info, vha, 0x803c,
6051 "Start configure loop, status =%d.\n", status);
a9083016
GM		 6052
6053 /* Issue a marker after FW becomes ready. */
6054 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
6055
6056 vha->flags.online = 1;
6057 /* Wait at most MAX_TARGET RSCNs for a stable link. */
6058 wait_time = 256;
6059 do {
6060 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
6061 qla2x00_configure_loop(vha);
6062 wait_time--;
6063 } while (!atomic_read(&vha->loop_down_timer) &&
6064 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) &&
6065 wait_time &&
6066 (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)));
6067 }
6068
6069 /* if no cable then assume it's good */
6070 if ((vha->device_flags & DFLG_NO_CABLE))
6071 status = 0;
6072
cfb0919c 6073 ql_log(ql_log_info, vha, 0x8000,
7c3df132 6074 "Configure loop done, status = 0x%x.\n", status);
a9083016
GM		 6075 }
6076
6077 if (!status) {
6078 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
6079
6080 if (!atomic_read(&vha->loop_down_timer)) {
6081 /*
6082 * Issue marker command only when we are going
6083 * to start the I/O .
6084 */
6085 vha->marker_needed = 1;
6086 }
6087
6088 vha->flags.online = 1;
6089
6090 ha->isp_ops->enable_intrs(ha);
6091
6092 ha->isp_abort_cnt = 0;
6093 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
6094
53296788 6095 /* Update the firmware version */
3173167f 6096 status = qla82xx_check_md_needed(vha);
53296788 6097
a9083016
GM		 6098 if (ha->fce) {
6099 ha->flags.fce_enabled = 1;
6100 memset(ha->fce, 0,
6101 fce_calc_size(ha->fce_bufs));
6102 rval = qla2x00_enable_fce_trace(vha,
6103 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
6104 &ha->fce_bufs);
6105 if (rval) {
cfb0919c 6106 ql_log(ql_log_warn, vha, 0x8001,
7c3df132
SK		 6107 "Unable to reinitialize FCE (%d).\n",
6108 rval);
a9083016
GM		 6109 ha->flags.fce_enabled = 0;
6110 }
6111 }
6112
6113 if (ha->eft) {
6114 memset(ha->eft, 0, EFT_SIZE);
6115 rval = qla2x00_enable_eft_trace(vha,
6116 ha->eft_dma, EFT_NUM_BUFFERS);
6117 if (rval) {
cfb0919c 6118 ql_log(ql_log_warn, vha, 0x8010,
7c3df132
SK		 6119 "Unable to reinitialize EFT (%d).\n",
6120 rval);
a9083016
GM		 6121 }
6122 }
a9083016
GM		 6123 }
6124
6125 if (!status) {
cfb0919c 6126 ql_dbg(ql_dbg_taskm, vha, 0x8011,
7c3df132 6127 "qla82xx_restart_isp succeeded.\n");
feafb7b1
AE		 6128
6129 spin_lock_irqsave(&ha->vport_slock, flags);
6130 list_for_each_entry(vp, &ha->vp_list, list) {
6131 if (vp->vp_idx) {
6132 atomic_inc(&vp->vref_count);
6133 spin_unlock_irqrestore(&ha->vport_slock, flags);
6134
a9083016 6135 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 6136
6137 spin_lock_irqsave(&ha->vport_slock, flags);
6138 atomic_dec(&vp->vref_count);
6139 }
a9083016 6140 }
feafb7b1
AE		 6141 spin_unlock_irqrestore(&ha->vport_slock, flags);
6142
a9083016 6143 } else {
cfb0919c 6144 ql_log(ql_log_warn, vha, 0x8016,
7c3df132 6145 "qla82xx_restart_isp **** FAILED ****.\n");
a9083016
GM		 6146 }
6147
6148 return status;
6149}
6150
3a03eb79 6151void
ae97c91e 6152qla81xx_update_fw_options(scsi_qla_host_t *vha)
3a03eb79 6153{
ae97c91e
AV		 6154 struct qla_hw_data *ha = vha->hw;
6155
6156 if (!ql2xetsenable)
6157 return;
6158
6159 /* Enable ETS Burst. */
6160 memset(ha->fw_options, 0, sizeof(ha->fw_options));
6161 ha->fw_options[2] |= BIT_9;
6162 qla2x00_set_fw_options(vha, ha->fw_options);
3a03eb79 6163}
09ff701a
SR		 6164
6165/*
6166 * qla24xx_get_fcp_prio
6167 * Gets the fcp cmd priority value for the logged in port.
6168 * Looks for a match of the port descriptors within
6169 * each of the fcp prio config entries. If a match is found,
6170 * the tag (priority) value is returned.
6171 *
6172 * Input:
21090cbe 6173 * vha = scsi host structure pointer.
09ff701a
SR		 6174 * fcport = port structure pointer.
6175 *
6176 * Return:
6c452a45 6177 * non-zero (if found)
f28a0a96 6178 * -1 (if not found)
09ff701a
SR		 6179 *
6180 * Context:
6181 * Kernel context
6182 */
f28a0a96 6183static int
09ff701a
SR		 6184qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
6185{
6186 int i, entries;
6187 uint8_t pid_match, wwn_match;
f28a0a96 6188 int priority;
09ff701a
SR		 6189 uint32_t pid1, pid2;
6190 uint64_t wwn1, wwn2;
6191 struct qla_fcp_prio_entry *pri_entry;
6192 struct qla_hw_data *ha = vha->hw;
6193
6194 if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled)
f28a0a96 6195 return -1;
09ff701a 6196
f28a0a96 6197 priority = -1;
09ff701a
SR		 6198 entries = ha->fcp_prio_cfg->num_entries;
6199 pri_entry = &ha->fcp_prio_cfg->entry[0];
6200
6201 for (i = 0; i < entries; i++) {
6202 pid_match = wwn_match = 0;
6203
6204 if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) {
6205 pri_entry++;
6206 continue;
6207 }
6208
6209 /* check source pid for a match */
6210 if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) {
6211 pid1 = pri_entry->src_pid & INVALID_PORT_ID;
6212 pid2 = vha->d_id.b24 & INVALID_PORT_ID;
6213 if (pid1 == INVALID_PORT_ID)
6214 pid_match++;
6215 else if (pid1 == pid2)
6216 pid_match++;
6217 }
6218
6219 /* check destination pid for a match */
6220 if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) {
6221 pid1 = pri_entry->dst_pid & INVALID_PORT_ID;
6222 pid2 = fcport->d_id.b24 & INVALID_PORT_ID;
6223 if (pid1 == INVALID_PORT_ID)
6224 pid_match++;
6225 else if (pid1 == pid2)
6226 pid_match++;
6227 }
6228
6229 /* check source WWN for a match */
6230 if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) {
6231 wwn1 = wwn_to_u64(vha->port_name);
6232 wwn2 = wwn_to_u64(pri_entry->src_wwpn);
6233 if (wwn2 == (uint64_t)-1)
6234 wwn_match++;
6235 else if (wwn1 == wwn2)
6236 wwn_match++;
6237 }
6238
6239 /* check destination WWN for a match */
6240 if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) {
6241 wwn1 = wwn_to_u64(fcport->port_name);
6242 wwn2 = wwn_to_u64(pri_entry->dst_wwpn);
6243 if (wwn2 == (uint64_t)-1)
6244 wwn_match++;
6245 else if (wwn1 == wwn2)
6246 wwn_match++;
6247 }
6248
6249 if (pid_match == 2 || wwn_match == 2) {
6250 /* Found a matching entry */
6251 if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID)
6252 priority = pri_entry->tag;
6253 break;
6254 }
6255
6256 pri_entry++;
6257 }
6258
6259 return priority;
6260}
6261
6262/*
6263 * qla24xx_update_fcport_fcp_prio
6264 * Activates fcp priority for the logged in fc port
6265 *
6266 * Input:
21090cbe 6267 * vha = scsi host structure pointer.
09ff701a
SR		 6268 * fcp = port structure pointer.
6269 *
6270 * Return:
6271 * QLA_SUCCESS or QLA_FUNCTION_FAILED
6272 *
6273 * Context:
6274 * Kernel context.
6275 */
6276int
21090cbe 6277qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
09ff701a
SR		 6278{
6279 int ret;
f28a0a96 6280 int priority;
09ff701a
SR		 6281 uint16_t mb[5];
6282
21090cbe
MI		 6283 if (fcport->port_type != FCT_TARGET ||
6284 fcport->loop_id == FC_NO_LOOP_ID)
09ff701a
SR		 6285 return QLA_FUNCTION_FAILED;
6286
21090cbe 6287 priority = qla24xx_get_fcp_prio(vha, fcport);
f28a0a96
AV		 6288 if (priority < 0)
6289 return QLA_FUNCTION_FAILED;
6290
7ec0effd 6291 if (IS_P3P_TYPE(vha->hw)) {
a00f6296
SK		 6292 fcport->fcp_prio = priority & 0xf;
6293 return QLA_SUCCESS;
6294 }
6295
21090cbe 6296 ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb);
cfb0919c
CD		 6297 if (ret == QLA_SUCCESS) {
6298 if (fcport->fcp_prio != priority)
6299 ql_dbg(ql_dbg_user, vha, 0x709e,
6300 "Updated FCP_CMND priority - value=%d loop_id=%d "
6301 "port_id=%02x%02x%02x.\n", priority,
6302 fcport->loop_id, fcport->d_id.b.domain,
6303 fcport->d_id.b.area, fcport->d_id.b.al_pa);
a00f6296 6304 fcport->fcp_prio = priority & 0xf;
cfb0919c 6305 } else
7c3df132 6306 ql_dbg(ql_dbg_user, vha, 0x704f,
cfb0919c
CD		 6307 "Unable to update FCP_CMND priority - ret=0x%x for "
6308 "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id,
6309 fcport->d_id.b.domain, fcport->d_id.b.area,
6310 fcport->d_id.b.al_pa);
09ff701a
SR		 6311 return ret;
6312}
6313
6314/*
6315 * qla24xx_update_all_fcp_prio
6316 * Activates fcp priority for all the logged in ports
6317 *
6318 * Input:
6319 * ha = adapter block pointer.
6320 *
6321 * Return:
6322 * QLA_SUCCESS or QLA_FUNCTION_FAILED
6323 *
6324 * Context:
6325 * Kernel context.
6326 */
6327int
6328qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha)
6329{
6330 int ret;
6331 fc_port_t *fcport;
6332
6333 ret = QLA_FUNCTION_FAILED;
6334 /* We need to set priority for all logged in ports */
6335 list_for_each_entry(fcport, &vha->vp_fcports, list)
6336 ret = qla24xx_update_fcport_fcp_prio(vha, fcport);
6337
6338 return ret;
6339}
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