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qla2xxx: Track I-T nexus as single fc_port struct
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / qla2xxx / qla_init.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
73208dfd 8#include "qla_gbl.h"
1da177e4
LT		 9
10#include <linux/delay.h>
5a0e3ad6 11#include <linux/slab.h>
0107109e 12#include <linux/vmalloc.h>
1da177e4
LT		 13
14#include "qla_devtbl.h"
15
4e08df3f
DM		 16#ifdef CONFIG_SPARC
17#include <asm/prom.h>
4e08df3f
DM		 18#endif
19
2d70c103
NB		 20#include <target/target_core_base.h>
21#include "qla_target.h"
22
1da177e4
LT		 23/*
24* QLogic ISP2x00 Hardware Support Function Prototypes.
25*/
1da177e4 26static int qla2x00_isp_firmware(scsi_qla_host_t *);
1da177e4 27static int qla2x00_setup_chip(scsi_qla_host_t *);
1da177e4
LT		 28static int qla2x00_fw_ready(scsi_qla_host_t *);
29static int qla2x00_configure_hba(scsi_qla_host_t *);
1da177e4
LT		 30static int qla2x00_configure_loop(scsi_qla_host_t *);
31static int qla2x00_configure_local_loop(scsi_qla_host_t *);
1da177e4
LT		 32static int qla2x00_configure_fabric(scsi_qla_host_t *);
33static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *, struct list_head *);
1da177e4
LT		 34static int qla2x00_fabric_dev_login(scsi_qla_host_t *, fc_port_t *,
35 uint16_t *);
1da177e4
LT		 36
37static int qla2x00_restart_isp(scsi_qla_host_t *);
1da177e4 38
4d4df193
HK		 39static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *);
40static int qla84xx_init_chip(scsi_qla_host_t *);
73208dfd 41static int qla25xx_init_queues(struct qla_hw_data *);
4d4df193 42
ac280b67
AV		 43/* SRB Extensions ---------------------------------------------------------- */
44
9ba56b95
GM		 45void
46qla2x00_sp_timeout(unsigned long __data)
ac280b67
AV		 47{
48 srb_t *sp = (srb_t *)__data;
4916392b 49 struct srb_iocb *iocb;
ac280b67
AV		 50 fc_port_t *fcport = sp->fcport;
51 struct qla_hw_data *ha = fcport->vha->hw;
52 struct req_que *req;
53 unsigned long flags;
54
55 spin_lock_irqsave(&ha->hardware_lock, flags);
56 req = ha->req_q_map[0];
57 req->outstanding_cmds[sp->handle] = NULL;
9ba56b95 58 iocb = &sp->u.iocb_cmd;
4916392b 59 iocb->timeout(sp);
9ba56b95 60 sp->free(fcport->vha, sp);
6ac52608 61 spin_unlock_irqrestore(&ha->hardware_lock, flags);
ac280b67
AV		 62}
63
9ba56b95
GM		 64void
65qla2x00_sp_free(void *data, void *ptr)
ac280b67 66{
9ba56b95
GM		 67 srb_t *sp = (srb_t *)ptr;
68 struct srb_iocb *iocb = &sp->u.iocb_cmd;
69 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
ac280b67 70
4d97cc53 71 del_timer(&iocb->timer);
b00ee7d7 72 qla2x00_rel_sp(vha, sp);
ac280b67
AV		 73}
74
ac280b67
AV		 75/* Asynchronous Login/Logout Routines -------------------------------------- */
76
a9b6f722 77unsigned long
5b91490e
AV		 78qla2x00_get_async_timeout(struct scsi_qla_host *vha)
79{
80 unsigned long tmo;
81 struct qla_hw_data *ha = vha->hw;
82
83 /* Firmware should use switch negotiated r_a_tov for timeout. */
84 tmo = ha->r_a_tov / 10 * 2;
8ae6d9c7
GM		 85 if (IS_QLAFX00(ha)) {
86 tmo = FX00_DEF_RATOV * 2;
87 } else if (!IS_FWI2_CAPABLE(ha)) {
5b91490e
AV		 88 /*
89 * Except for earlier ISPs where the timeout is seeded from the
90 * initialization control block.
91 */
92 tmo = ha->login_timeout;
93 }
94 return tmo;
95}
ac280b67
AV		 96
97static void
9ba56b95 98qla2x00_async_iocb_timeout(void *data)
ac280b67 99{
9ba56b95 100 srb_t *sp = (srb_t *)data;
ac280b67 101 fc_port_t *fcport = sp->fcport;
ac280b67 102
7c3df132 103 ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
cfb0919c 104 "Async-%s timeout - hdl=%x portid=%02x%02x%02x.\n",
9ba56b95 105 sp->name, sp->handle, fcport->d_id.b.domain, fcport->d_id.b.area,
7c3df132 106 fcport->d_id.b.al_pa);
ac280b67 107
5ff1d584 108 fcport->flags &= ~FCF_ASYNC_SENT;
9ba56b95
GM		 109 if (sp->type == SRB_LOGIN_CMD) {
110 struct srb_iocb *lio = &sp->u.iocb_cmd;
ac280b67 111 qla2x00_post_async_logout_work(fcport->vha, fcport, NULL);
6ac52608
AV		 112 /* Retry as needed. */
113 lio->u.logio.data[0] = MBS_COMMAND_ERROR;
114 lio->u.logio.data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
115 QLA_LOGIO_LOGIN_RETRIED : 0;
116 qla2x00_post_async_login_done_work(fcport->vha, fcport,
117 lio->u.logio.data);
a6ca8878
AP		 118 } else if (sp->type == SRB_LOGOUT_CMD) {
119 qlt_logo_completion_handler(fcport, QLA_FUNCTION_TIMEOUT);
6ac52608 120 }
ac280b67
AV		 121}
122
99b0bec7 123static void
9ba56b95 124qla2x00_async_login_sp_done(void *data, void *ptr, int res)
99b0bec7 125{
9ba56b95
GM		 126 srb_t *sp = (srb_t *)ptr;
127 struct srb_iocb *lio = &sp->u.iocb_cmd;
128 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
129
130 if (!test_bit(UNLOADING, &vha->dpc_flags))
131 qla2x00_post_async_login_done_work(sp->fcport->vha, sp->fcport,
132 lio->u.logio.data);
133 sp->free(sp->fcport->vha, sp);
99b0bec7
AV		 134}
135
ac280b67
AV		 136int
137qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport,
138 uint16_t *data)
139{
ac280b67 140 srb_t *sp;
4916392b 141 struct srb_iocb *lio;
ac280b67
AV		 142 int rval;
143
144 rval = QLA_FUNCTION_FAILED;
9ba56b95 145 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 146 if (!sp)
147 goto done;
148
9ba56b95
GM		 149 sp->type = SRB_LOGIN_CMD;
150 sp->name = "login";
151 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
152
153 lio = &sp->u.iocb_cmd;
3822263e 154 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 155 sp->done = qla2x00_async_login_sp_done;
4916392b 156 lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI;
ac280b67 157 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 158 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
ac280b67 159 rval = qla2x00_start_sp(sp);
080c9517
CD		 160 if (rval != QLA_SUCCESS) {
161 fcport->flags &= ~FCF_ASYNC_SENT;
162 fcport->flags |= FCF_LOGIN_NEEDED;
163 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
ac280b67 164 goto done_free_sp;
080c9517 165 }
ac280b67 166
7c3df132 167 ql_dbg(ql_dbg_disc, vha, 0x2072,
cfb0919c
CD		 168 "Async-login - hdl=%x, loopid=%x portid=%02x%02x%02x "
169 "retries=%d.\n", sp->handle, fcport->loop_id,
170 fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
171 fcport->login_retry);
ac280b67
AV		 172 return rval;
173
174done_free_sp:
9ba56b95 175 sp->free(fcport->vha, sp);
ac280b67
AV		 176done:
177 return rval;
178}
179
99b0bec7 180static void
9ba56b95 181qla2x00_async_logout_sp_done(void *data, void *ptr, int res)
99b0bec7 182{
9ba56b95
GM		 183 srb_t *sp = (srb_t *)ptr;
184 struct srb_iocb *lio = &sp->u.iocb_cmd;
185 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
186
187 if (!test_bit(UNLOADING, &vha->dpc_flags))
188 qla2x00_post_async_logout_done_work(sp->fcport->vha, sp->fcport,
189 lio->u.logio.data);
190 sp->free(sp->fcport->vha, sp);
99b0bec7
AV		 191}
192
ac280b67
AV		 193int
194qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport)
195{
ac280b67 196 srb_t *sp;
4916392b 197 struct srb_iocb *lio;
ac280b67
AV		 198 int rval;
199
200 rval = QLA_FUNCTION_FAILED;
9ba56b95 201 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 202 if (!sp)
203 goto done;
204
9ba56b95
GM		 205 sp->type = SRB_LOGOUT_CMD;
206 sp->name = "logout";
207 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
208
209 lio = &sp->u.iocb_cmd;
3822263e 210 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 211 sp->done = qla2x00_async_logout_sp_done;
ac280b67
AV		 212 rval = qla2x00_start_sp(sp);
213 if (rval != QLA_SUCCESS)
214 goto done_free_sp;
215
7c3df132 216 ql_dbg(ql_dbg_disc, vha, 0x2070,
cfb0919c
CD		 217 "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
218 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
219 fcport->d_id.b.area, fcport->d_id.b.al_pa);
ac280b67
AV		 220 return rval;
221
222done_free_sp:
9ba56b95 223 sp->free(fcport->vha, sp);
ac280b67
AV		 224done:
225 return rval;
226}
227
5ff1d584 228static void
9ba56b95 229qla2x00_async_adisc_sp_done(void *data, void *ptr, int res)
5ff1d584 230{
9ba56b95
GM		 231 srb_t *sp = (srb_t *)ptr;
232 struct srb_iocb *lio = &sp->u.iocb_cmd;
233 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
234
235 if (!test_bit(UNLOADING, &vha->dpc_flags))
236 qla2x00_post_async_adisc_done_work(sp->fcport->vha, sp->fcport,
237 lio->u.logio.data);
238 sp->free(sp->fcport->vha, sp);
5ff1d584
AV		 239}
240
241int
242qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport,
243 uint16_t *data)
244{
5ff1d584 245 srb_t *sp;
4916392b 246 struct srb_iocb *lio;
5ff1d584
AV		 247 int rval;
248
249 rval = QLA_FUNCTION_FAILED;
9ba56b95 250 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
5ff1d584
AV		 251 if (!sp)
252 goto done;
253
9ba56b95
GM		 254 sp->type = SRB_ADISC_CMD;
255 sp->name = "adisc";
256 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
257
258 lio = &sp->u.iocb_cmd;
3822263e 259 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 260 sp->done = qla2x00_async_adisc_sp_done;
5ff1d584 261 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 262 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
5ff1d584
AV		 263 rval = qla2x00_start_sp(sp);
264 if (rval != QLA_SUCCESS)
265 goto done_free_sp;
266
7c3df132 267 ql_dbg(ql_dbg_disc, vha, 0x206f,
cfb0919c
CD		 268 "Async-adisc - hdl=%x loopid=%x portid=%02x%02x%02x.\n",
269 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
270 fcport->d_id.b.area, fcport->d_id.b.al_pa);
5ff1d584
AV		 271 return rval;
272
273done_free_sp:
9ba56b95 274 sp->free(fcport->vha, sp);
5ff1d584
AV		 275done:
276 return rval;
277}
278
3822263e 279static void
faef62d1 280qla2x00_tmf_iocb_timeout(void *data)
3822263e 281{
faef62d1
AB		 282 srb_t *sp = (srb_t *)data;
283 struct srb_iocb *tmf = &sp->u.iocb_cmd;
3822263e 284
faef62d1
AB		 285 tmf->u.tmf.comp_status = CS_TIMEOUT;
286 complete(&tmf->u.tmf.comp);
287}
9ba56b95 288
faef62d1
AB		 289static void
290qla2x00_tmf_sp_done(void *data, void *ptr, int res)
291{
292 srb_t *sp = (srb_t *)ptr;
293 struct srb_iocb *tmf = &sp->u.iocb_cmd;
294 complete(&tmf->u.tmf.comp);
3822263e
MI		 295}
296
297int
faef62d1 298qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t flags, uint32_t lun,
3822263e
MI		 299 uint32_t tag)
300{
301 struct scsi_qla_host *vha = fcport->vha;
faef62d1 302 struct srb_iocb *tm_iocb;
3822263e 303 srb_t *sp;
faef62d1 304 int rval = QLA_FUNCTION_FAILED;
3822263e 305
9ba56b95 306 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
3822263e
MI		 307 if (!sp)
308 goto done;
309
faef62d1 310 tm_iocb = &sp->u.iocb_cmd;
9ba56b95
GM		 311 sp->type = SRB_TM_CMD;
312 sp->name = "tmf";
faef62d1
AB		 313 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
314 tm_iocb->u.tmf.flags = flags;
315 tm_iocb->u.tmf.lun = lun;
316 tm_iocb->u.tmf.data = tag;
317 sp->done = qla2x00_tmf_sp_done;
318 tm_iocb->timeout = qla2x00_tmf_iocb_timeout;
319 init_completion(&tm_iocb->u.tmf.comp);
3822263e
MI		 320
321 rval = qla2x00_start_sp(sp);
322 if (rval != QLA_SUCCESS)
323 goto done_free_sp;
324
7c3df132 325 ql_dbg(ql_dbg_taskm, vha, 0x802f,
cfb0919c
CD		 326 "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
327 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
328 fcport->d_id.b.area, fcport->d_id.b.al_pa);
faef62d1
AB		 329
330 wait_for_completion(&tm_iocb->u.tmf.comp);
331
332 rval = tm_iocb->u.tmf.comp_status == CS_COMPLETE ?
333 QLA_SUCCESS : QLA_FUNCTION_FAILED;
334
335 if ((rval != QLA_SUCCESS) || tm_iocb->u.tmf.data) {
336 ql_dbg(ql_dbg_taskm, vha, 0x8030,
337 "TM IOCB failed (%x).\n", rval);
338 }
339
340 if (!test_bit(UNLOADING, &vha->dpc_flags) && !IS_QLAFX00(vha->hw)) {
341 flags = tm_iocb->u.tmf.flags;
342 lun = (uint16_t)tm_iocb->u.tmf.lun;
343
344 /* Issue Marker IOCB */
345 qla2x00_marker(vha, vha->hw->req_q_map[0],
346 vha->hw->rsp_q_map[0], sp->fcport->loop_id, lun,
347 flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
348 }
3822263e
MI		 349
350done_free_sp:
faef62d1 351 sp->free(vha, sp);
3822263e
MI		 352done:
353 return rval;
354}
355
4440e46d
AB		 356static void
357qla24xx_abort_iocb_timeout(void *data)
358{
359 srb_t *sp = (srb_t *)data;
360 struct srb_iocb *abt = &sp->u.iocb_cmd;
361
362 abt->u.abt.comp_status = CS_TIMEOUT;
363 complete(&abt->u.abt.comp);
364}
365
366static void
367qla24xx_abort_sp_done(void *data, void *ptr, int res)
368{
369 srb_t *sp = (srb_t *)ptr;
370 struct srb_iocb *abt = &sp->u.iocb_cmd;
371
372 complete(&abt->u.abt.comp);
373}
374
375static int
376qla24xx_async_abort_cmd(srb_t *cmd_sp)
377{
378 scsi_qla_host_t *vha = cmd_sp->fcport->vha;
379 fc_port_t *fcport = cmd_sp->fcport;
380 struct srb_iocb *abt_iocb;
381 srb_t *sp;
382 int rval = QLA_FUNCTION_FAILED;
383
384 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
385 if (!sp)
386 goto done;
387
388 abt_iocb = &sp->u.iocb_cmd;
389 sp->type = SRB_ABT_CMD;
390 sp->name = "abort";
391 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
392 abt_iocb->u.abt.cmd_hndl = cmd_sp->handle;
393 sp->done = qla24xx_abort_sp_done;
394 abt_iocb->timeout = qla24xx_abort_iocb_timeout;
395 init_completion(&abt_iocb->u.abt.comp);
396
397 rval = qla2x00_start_sp(sp);
398 if (rval != QLA_SUCCESS)
399 goto done_free_sp;
400
401 ql_dbg(ql_dbg_async, vha, 0x507c,
402 "Abort command issued - hdl=%x, target_id=%x\n",
403 cmd_sp->handle, fcport->tgt_id);
404
405 wait_for_completion(&abt_iocb->u.abt.comp);
406
407 rval = abt_iocb->u.abt.comp_status == CS_COMPLETE ?
408 QLA_SUCCESS : QLA_FUNCTION_FAILED;
409
410done_free_sp:
411 sp->free(vha, sp);
412done:
413 return rval;
414}
415
416int
417qla24xx_async_abort_command(srb_t *sp)
418{
419 unsigned long flags = 0;
420
421 uint32_t handle;
422 fc_port_t *fcport = sp->fcport;
423 struct scsi_qla_host *vha = fcport->vha;
424 struct qla_hw_data *ha = vha->hw;
425 struct req_que *req = vha->req;
426
427 spin_lock_irqsave(&ha->hardware_lock, flags);
428 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
429 if (req->outstanding_cmds[handle] == sp)
430 break;
431 }
432 spin_unlock_irqrestore(&ha->hardware_lock, flags);
433 if (handle == req->num_outstanding_cmds) {
434 /* Command not found. */
435 return QLA_FUNCTION_FAILED;
436 }
437 if (sp->type == SRB_FXIOCB_DCMD)
438 return qlafx00_fx_disc(vha, &vha->hw->mr.fcport,
439 FXDISC_ABORT_IOCTL);
440
441 return qla24xx_async_abort_cmd(sp);
442}
443
4916392b 444void
ac280b67
AV		 445qla2x00_async_login_done(struct scsi_qla_host *vha, fc_port_t *fcport,
446 uint16_t *data)
447{
448 int rval;
ac280b67
AV		 449
450 switch (data[0]) {
451 case MBS_COMMAND_COMPLETE:
a4f92a32
AV		 452 /*
453 * Driver must validate login state - If PRLI not complete,
454 * force a relogin attempt via implicit LOGO, PLOGI, and PRLI
455 * requests.
456 */
457 rval = qla2x00_get_port_database(vha, fcport, 0);
0eba25df
AE		 458 if (rval == QLA_NOT_LOGGED_IN) {
459 fcport->flags &= ~FCF_ASYNC_SENT;
460 fcport->flags |= FCF_LOGIN_NEEDED;
461 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
462 break;
463 }
464
a4f92a32
AV		 465 if (rval != QLA_SUCCESS) {
466 qla2x00_post_async_logout_work(vha, fcport, NULL);
467 qla2x00_post_async_login_work(vha, fcport, NULL);
468 break;
469 }
99b0bec7 470 if (fcport->flags & FCF_FCP2_DEVICE) {
5ff1d584
AV		 471 qla2x00_post_async_adisc_work(vha, fcport, data);
472 break;
99b0bec7
AV		 473 }
474 qla2x00_update_fcport(vha, fcport);
ac280b67
AV		 475 break;
476 case MBS_COMMAND_ERROR:
5ff1d584 477 fcport->flags &= ~FCF_ASYNC_SENT;
ac280b67
AV		 478 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
479 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
480 else
80d79440 481 qla2x00_mark_device_lost(vha, fcport, 1, 0);
ac280b67
AV		 482 break;
483 case MBS_PORT_ID_USED:
484 fcport->loop_id = data[1];
6ac52608 485 qla2x00_post_async_logout_work(vha, fcport, NULL);
ac280b67
AV		 486 qla2x00_post_async_login_work(vha, fcport, NULL);
487 break;
488 case MBS_LOOP_ID_USED:
489 fcport->loop_id++;
490 rval = qla2x00_find_new_loop_id(vha, fcport);
491 if (rval != QLA_SUCCESS) {
5ff1d584 492 fcport->flags &= ~FCF_ASYNC_SENT;
80d79440 493 qla2x00_mark_device_lost(vha, fcport, 1, 0);
ac280b67
AV		 494 break;
495 }
496 qla2x00_post_async_login_work(vha, fcport, NULL);
497 break;
498 }
4916392b 499 return;
ac280b67
AV		 500}
501
4916392b 502void
ac280b67
AV		 503qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport,
504 uint16_t *data)
505{
a6ca8878
AP		 506 /* Don't re-login in target mode */
507 if (!fcport->tgt_session)
508 qla2x00_mark_device_lost(vha, fcport, 1, 0);
509 qlt_logo_completion_handler(fcport, data[0]);
4916392b 510 return;
ac280b67
AV		 511}
512
4916392b 513void
5ff1d584
AV		 514qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport,
515 uint16_t *data)
516{
517 if (data[0] == MBS_COMMAND_COMPLETE) {
518 qla2x00_update_fcport(vha, fcport);
519
4916392b 520 return;
5ff1d584
AV		 521 }
522
523 /* Retry login. */
524 fcport->flags &= ~FCF_ASYNC_SENT;
525 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
526 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
527 else
80d79440 528 qla2x00_mark_device_lost(vha, fcport, 1, 0);
5ff1d584 529
4916392b 530 return;
5ff1d584
AV		 531}
532
1da177e4
LT		 533/****************************************************************************/
534/* QLogic ISP2x00 Hardware Support Functions. */
535/****************************************************************************/
536
fa492630 537static int
7d613ac6
SV		 538qla83xx_nic_core_fw_load(scsi_qla_host_t *vha)
539{
540 int rval = QLA_SUCCESS;
541 struct qla_hw_data *ha = vha->hw;
542 uint32_t idc_major_ver, idc_minor_ver;
711aa7f7 543 uint16_t config[4];
7d613ac6
SV		 544
545 qla83xx_idc_lock(vha, 0);
546
547 /* SV: TODO: Assign initialization timeout from
548 * flash-info / other param
549 */
550 ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT;
551 ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT;
552
553 /* Set our fcoe function presence */
554 if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) {
555 ql_dbg(ql_dbg_p3p, vha, 0xb077,
556 "Error while setting DRV-Presence.\n");
557 rval = QLA_FUNCTION_FAILED;
558 goto exit;
559 }
560
561 /* Decide the reset ownership */
562 qla83xx_reset_ownership(vha);
563
564 /*
565 * On first protocol driver load:
566 * Init-Owner: Set IDC-Major-Version and Clear IDC-Lock-Recovery
567 * register.
568 * Others: Check compatibility with current IDC Major version.
569 */
570 qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver);
571 if (ha->flags.nic_core_reset_owner) {
572 /* Set IDC Major version */
573 idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION;
574 qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver);
575
576 /* Clearing IDC-Lock-Recovery register */
577 qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0);
578 } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) {
579 /*
580 * Clear further IDC participation if we are not compatible with
581 * the current IDC Major Version.
582 */
583 ql_log(ql_log_warn, vha, 0xb07d,
584 "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n",
585 idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION);
586 __qla83xx_clear_drv_presence(vha);
587 rval = QLA_FUNCTION_FAILED;
588 goto exit;
589 }
590 /* Each function sets its supported Minor version. */
591 qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver);
592 idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2));
593 qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver);
594
711aa7f7
SK		 595 if (ha->flags.nic_core_reset_owner) {
596 memset(config, 0, sizeof(config));
597 if (!qla81xx_get_port_config(vha, config))
598 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
599 QLA8XXX_DEV_READY);
600 }
601
7d613ac6
SV		 602 rval = qla83xx_idc_state_handler(vha);
603
604exit:
605 qla83xx_idc_unlock(vha, 0);
606
607 return rval;
608}
609
1da177e4
LT		 610/*
611* qla2x00_initialize_adapter
612* Initialize board.
613*
614* Input:
615* ha = adapter block pointer.
616*
617* Returns:
618* 0 = success
619*/
620int
e315cd28 621qla2x00_initialize_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 622{
623 int rval;
e315cd28 624 struct qla_hw_data *ha = vha->hw;
73208dfd 625 struct req_que *req = ha->req_q_map[0];
2533cf67 626
fc90adaf
JC		 627 memset(&vha->qla_stats, 0, sizeof(vha->qla_stats));
628 memset(&vha->fc_host_stat, 0, sizeof(vha->fc_host_stat));
629
1da177e4 630 /* Clear adapter flags. */
e315cd28 631 vha->flags.online = 0;
2533cf67 632 ha->flags.chip_reset_done = 0;
e315cd28 633 vha->flags.reset_active = 0;
85880801
AV		 634 ha->flags.pci_channel_io_perm_failure = 0;
635 ha->flags.eeh_busy = 0;
fabbb8df 636 vha->qla_stats.jiffies_at_last_reset = get_jiffies_64();
e315cd28
AC		 637 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
638 atomic_set(&vha->loop_state, LOOP_DOWN);
639 vha->device_flags = DFLG_NO_CABLE;
640 vha->dpc_flags = 0;
641 vha->flags.management_server_logged_in = 0;
642 vha->marker_needed = 0;
1da177e4
LT		 643 ha->isp_abort_cnt = 0;
644 ha->beacon_blink_led = 0;
645
73208dfd
AC		 646 set_bit(0, ha->req_qid_map);
647 set_bit(0, ha->rsp_qid_map);
648
cfb0919c 649 ql_dbg(ql_dbg_init, vha, 0x0040,
7c3df132 650 "Configuring PCI space...\n");
e315cd28 651 rval = ha->isp_ops->pci_config(vha);
1da177e4 652 if (rval) {
7c3df132
SK		 653 ql_log(ql_log_warn, vha, 0x0044,
654 "Unable to configure PCI space.\n");
1da177e4
LT		 655 return (rval);
656 }
657
e315cd28 658 ha->isp_ops->reset_chip(vha);
1da177e4 659
e315cd28 660 rval = qla2xxx_get_flash_info(vha);
c00d8994 661 if (rval) {
7c3df132
SK		 662 ql_log(ql_log_fatal, vha, 0x004f,
663 "Unable to validate FLASH data.\n");
7ec0effd
AD		 664 return rval;
665 }
666
667 if (IS_QLA8044(ha)) {
668 qla8044_read_reset_template(vha);
669
670 /* NOTE: If ql2xdontresethba==1, set IDC_CTRL DONTRESET_BIT0.
671 * If DONRESET_BIT0 is set, drivers should not set dev_state
672 * to NEED_RESET. But if NEED_RESET is set, drivers should
673 * should honor the reset. */
674 if (ql2xdontresethba == 1)
675 qla8044_set_idc_dontreset(vha);
c00d8994
AV		 676 }
677
73208dfd 678 ha->isp_ops->get_flash_version(vha, req->ring);
cfb0919c 679 ql_dbg(ql_dbg_init, vha, 0x0061,
7c3df132 680 "Configure NVRAM parameters...\n");
0107109e 681
e315cd28 682 ha->isp_ops->nvram_config(vha);
1da177e4 683
d4c760c2
AV		 684 if (ha->flags.disable_serdes) {
685 /* Mask HBA via NVRAM settings? */
7c3df132 686 ql_log(ql_log_info, vha, 0x0077,
7b833558 687 "Masking HBA WWPN %8phN (via NVRAM).\n", vha->port_name);
d4c760c2
AV		 688 return QLA_FUNCTION_FAILED;
689 }
690
cfb0919c 691 ql_dbg(ql_dbg_init, vha, 0x0078,
7c3df132 692 "Verifying loaded RISC code...\n");
1da177e4 693
e315cd28
AC		 694 if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) {
695 rval = ha->isp_ops->chip_diag(vha);
d19044c3
AV		 696 if (rval)
697 return (rval);
e315cd28 698 rval = qla2x00_setup_chip(vha);
d19044c3
AV		 699 if (rval)
700 return (rval);
1da177e4 701 }
a9083016 702
4d4df193 703 if (IS_QLA84XX(ha)) {
e315cd28 704 ha->cs84xx = qla84xx_get_chip(vha);
4d4df193 705 if (!ha->cs84xx) {
7c3df132 706 ql_log(ql_log_warn, vha, 0x00d0,
4d4df193
HK		 707 "Unable to configure ISP84XX.\n");
708 return QLA_FUNCTION_FAILED;
709 }
710 }
2d70c103
NB		 711
712 if (qla_ini_mode_enabled(vha))
713 rval = qla2x00_init_rings(vha);
714
2533cf67 715 ha->flags.chip_reset_done = 1;
1da177e4 716
9a069e19 717 if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) {
6c452a45 718 /* Issue verify 84xx FW IOCB to complete 84xx initialization */
9a069e19
GM		 719 rval = qla84xx_init_chip(vha);
720 if (rval != QLA_SUCCESS) {
7c3df132
SK		 721 ql_log(ql_log_warn, vha, 0x00d4,
722 "Unable to initialize ISP84XX.\n");
8d2b21db 723 qla84xx_put_chip(vha);
9a069e19
GM		 724 }
725 }
726
7d613ac6
SV		 727 /* Load the NIC Core f/w if we are the first protocol driver. */
728 if (IS_QLA8031(ha)) {
729 rval = qla83xx_nic_core_fw_load(vha);
730 if (rval)
731 ql_log(ql_log_warn, vha, 0x0124,
732 "Error in initializing NIC Core f/w.\n");
733 }
734
2f0f3f4f
MI		 735 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
736 qla24xx_read_fcp_prio_cfg(vha);
09ff701a 737
c46e65c7
JC		 738 if (IS_P3P_TYPE(ha))
739 qla82xx_set_driver_version(vha, QLA2XXX_VERSION);
740 else
741 qla25xx_set_driver_version(vha, QLA2XXX_VERSION);
742
1da177e4
LT		 743 return (rval);
744}
745
746/**
abbd8870 747 * qla2100_pci_config() - Setup ISP21xx PCI configuration registers.
1da177e4
LT		 748 * @ha: HA context
749 *
750 * Returns 0 on success.
751 */
abbd8870 752int
e315cd28 753qla2100_pci_config(scsi_qla_host_t *vha)
1da177e4 754{
a157b101 755 uint16_t w;
abbd8870 756 unsigned long flags;
e315cd28 757 struct qla_hw_data *ha = vha->hw;
3d71644c 758 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 759
1da177e4 760 pci_set_master(ha->pdev);
af6177d8 761 pci_try_set_mwi(ha->pdev);
1da177e4 762
1da177e4 763 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 764 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
abbd8870
AV		 765 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
766
737faece 767 pci_disable_rom(ha->pdev);
1da177e4
LT		 768
769 /* Get PCI bus information. */
770 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 771 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
1da177e4
LT		 772 spin_unlock_irqrestore(&ha->hardware_lock, flags);
773
abbd8870
AV		 774 return QLA_SUCCESS;
775}
1da177e4 776
abbd8870
AV		 777/**
778 * qla2300_pci_config() - Setup ISP23xx PCI configuration registers.
779 * @ha: HA context
780 *
781 * Returns 0 on success.
782 */
783int
e315cd28 784qla2300_pci_config(scsi_qla_host_t *vha)
abbd8870 785{
a157b101 786 uint16_t w;
abbd8870
AV		 787 unsigned long flags = 0;
788 uint32_t cnt;
e315cd28 789 struct qla_hw_data *ha = vha->hw;
3d71644c 790 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 791
abbd8870 792 pci_set_master(ha->pdev);
af6177d8 793 pci_try_set_mwi(ha->pdev);
1da177e4 794
abbd8870 795 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 796 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
1da177e4 797
abbd8870
AV		 798 if (IS_QLA2322(ha) || IS_QLA6322(ha))
799 w &= ~PCI_COMMAND_INTX_DISABLE;
a157b101 800 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1da177e4 801
abbd8870
AV		 802 /*
803 * If this is a 2300 card and not 2312, reset the
804 * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately,
805 * the 2310 also reports itself as a 2300 so we need to get the
806 * fb revision level -- a 6 indicates it really is a 2300 and
807 * not a 2310.
808 */
809 if (IS_QLA2300(ha)) {
810 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 811
abbd8870 812 /* Pause RISC. */
3d71644c 813 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
abbd8870 814 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 815 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
abbd8870 816 break;
1da177e4 817
abbd8870
AV		 818 udelay(10);
819 }
1da177e4 820
abbd8870 821 /* Select FPM registers. */
3d71644c
AV		 822 WRT_REG_WORD(&reg->ctrl_status, 0x20);
823 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 824
825 /* Get the fb rev level */
3d71644c 826 ha->fb_rev = RD_FB_CMD_REG(ha, reg);
abbd8870
AV		 827
828 if (ha->fb_rev == FPM_2300)
a157b101 829 pci_clear_mwi(ha->pdev);
abbd8870
AV		 830
831 /* Deselect FPM registers. */
3d71644c
AV		 832 WRT_REG_WORD(&reg->ctrl_status, 0x0);
833 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 834
835 /* Release RISC module. */
3d71644c 836 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
abbd8870 837 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 838 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0)
abbd8870
AV		 839 break;
840
841 udelay(10);
1da177e4 842 }
1da177e4 843
abbd8870
AV		 844 spin_unlock_irqrestore(&ha->hardware_lock, flags);
845 }
1da177e4 846
abbd8870
AV		 847 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
848
737faece 849 pci_disable_rom(ha->pdev);
1da177e4 850
abbd8870
AV		 851 /* Get PCI bus information. */
852 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 853 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 854 spin_unlock_irqrestore(&ha->hardware_lock, flags);
855
856 return QLA_SUCCESS;
1da177e4
LT		 857}
858
0107109e
AV		 859/**
860 * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers.
861 * @ha: HA context
862 *
863 * Returns 0 on success.
864 */
865int
e315cd28 866qla24xx_pci_config(scsi_qla_host_t *vha)
0107109e 867{
a157b101 868 uint16_t w;
0107109e 869 unsigned long flags = 0;
e315cd28 870 struct qla_hw_data *ha = vha->hw;
0107109e 871 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
0107109e
AV		 872
873 pci_set_master(ha->pdev);
af6177d8 874 pci_try_set_mwi(ha->pdev);
0107109e
AV		 875
876 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 877 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
0107109e
AV		 878 w &= ~PCI_COMMAND_INTX_DISABLE;
879 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
880
881 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
882
883 /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */
f85ec187
AV		 884 if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
885 pcix_set_mmrbc(ha->pdev, 2048);
0107109e
AV		 886
887 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 888 if (pci_is_pcie(ha->pdev))
5ffd3a52 889 pcie_set_readrq(ha->pdev, 4096);
0107109e 890
737faece 891 pci_disable_rom(ha->pdev);
0107109e 892
44c10138 893 ha->chip_revision = ha->pdev->revision;
a8488abe 894
0107109e
AV		 895 /* Get PCI bus information. */
896 spin_lock_irqsave(&ha->hardware_lock, flags);
897 ha->pci_attr = RD_REG_DWORD(&reg->ctrl_status);
898 spin_unlock_irqrestore(&ha->hardware_lock, flags);
899
900 return QLA_SUCCESS;
901}
902
c3a2f0df
AV		 903/**
904 * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers.
905 * @ha: HA context
906 *
907 * Returns 0 on success.
908 */
909int
e315cd28 910qla25xx_pci_config(scsi_qla_host_t *vha)
c3a2f0df
AV		 911{
912 uint16_t w;
e315cd28 913 struct qla_hw_data *ha = vha->hw;
c3a2f0df
AV		 914
915 pci_set_master(ha->pdev);
916 pci_try_set_mwi(ha->pdev);
917
918 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
919 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
920 w &= ~PCI_COMMAND_INTX_DISABLE;
921 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
922
923 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 924 if (pci_is_pcie(ha->pdev))
5ffd3a52 925 pcie_set_readrq(ha->pdev, 4096);
c3a2f0df 926
737faece 927 pci_disable_rom(ha->pdev);
c3a2f0df
AV		 928
929 ha->chip_revision = ha->pdev->revision;
930
931 return QLA_SUCCESS;
932}
933
1da177e4
LT		 934/**
935 * qla2x00_isp_firmware() - Choose firmware image.
936 * @ha: HA context
937 *
938 * Returns 0 on success.
939 */
940static int
e315cd28 941qla2x00_isp_firmware(scsi_qla_host_t *vha)
1da177e4
LT		 942{
943 int rval;
42e421b1
AV		 944 uint16_t loop_id, topo, sw_cap;
945 uint8_t domain, area, al_pa;
e315cd28 946 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 947
948 /* Assume loading risc code */
fa2a1ce5 949 rval = QLA_FUNCTION_FAILED;
1da177e4
LT		 950
951 if (ha->flags.disable_risc_code_load) {
7c3df132 952 ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n");
1da177e4
LT		 953
954 /* Verify checksum of loaded RISC code. */
e315cd28 955 rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address);
42e421b1
AV		 956 if (rval == QLA_SUCCESS) {
957 /* And, verify we are not in ROM code. */
e315cd28 958 rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa,
42e421b1
AV		 959 &area, &domain, &topo, &sw_cap);
960 }
1da177e4
LT		 961 }
962
7c3df132
SK		 963 if (rval)
964 ql_dbg(ql_dbg_init, vha, 0x007a,
965 "**** Load RISC code ****.\n");
1da177e4
LT		 966
967 return (rval);
968}
969
970/**
971 * qla2x00_reset_chip() - Reset ISP chip.
972 * @ha: HA context
973 *
974 * Returns 0 on success.
975 */
abbd8870 976void
e315cd28 977qla2x00_reset_chip(scsi_qla_host_t *vha)
1da177e4
LT		 978{
979 unsigned long flags = 0;
e315cd28 980 struct qla_hw_data *ha = vha->hw;
3d71644c 981 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 982 uint32_t cnt;
1da177e4
LT		 983 uint16_t cmd;
984
85880801
AV		 985 if (unlikely(pci_channel_offline(ha->pdev)))
986 return;
987
fd34f556 988 ha->isp_ops->disable_intrs(ha);
1da177e4
LT		 989
990 spin_lock_irqsave(&ha->hardware_lock, flags);
991
992 /* Turn off master enable */
993 cmd = 0;
994 pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd);
995 cmd &= ~PCI_COMMAND_MASTER;
996 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
997
998 if (!IS_QLA2100(ha)) {
999 /* Pause RISC. */
1000 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1001 if (IS_QLA2200(ha) || IS_QLA2300(ha)) {
1002 for (cnt = 0; cnt < 30000; cnt++) {
1003 if ((RD_REG_WORD(&reg->hccr) &
1004 HCCR_RISC_PAUSE) != 0)
1005 break;
1006 udelay(100);
1007 }
1008 } else {
1009 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1010 udelay(10);
1011 }
1012
1013 /* Select FPM registers. */
1014 WRT_REG_WORD(&reg->ctrl_status, 0x20);
1015 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1016
1017 /* FPM Soft Reset. */
1018 WRT_REG_WORD(&reg->fpm_diag_config, 0x100);
1019 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
1020
1021 /* Toggle Fpm Reset. */
1022 if (!IS_QLA2200(ha)) {
1023 WRT_REG_WORD(&reg->fpm_diag_config, 0x0);
1024 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
1025 }
1026
1027 /* Select frame buffer registers. */
1028 WRT_REG_WORD(&reg->ctrl_status, 0x10);
1029 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1030
1031 /* Reset frame buffer FIFOs. */
1032 if (IS_QLA2200(ha)) {
1033 WRT_FB_CMD_REG(ha, reg, 0xa000);
1034 RD_FB_CMD_REG(ha, reg); /* PCI Posting. */
1035 } else {
1036 WRT_FB_CMD_REG(ha, reg, 0x00fc);
1037
1038 /* Read back fb_cmd until zero or 3 seconds max */
1039 for (cnt = 0; cnt < 3000; cnt++) {
1040 if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0)
1041 break;
1042 udelay(100);
1043 }
1044 }
1045
1046 /* Select RISC module registers. */
1047 WRT_REG_WORD(&reg->ctrl_status, 0);
1048 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1049
1050 /* Reset RISC processor. */
1051 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
1052 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1053
1054 /* Release RISC processor. */
1055 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
1056 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1057 }
1058
1059 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
1060 WRT_REG_WORD(&reg->hccr, HCCR_CLR_HOST_INT);
1061
1062 /* Reset ISP chip. */
1063 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1064
1065 /* Wait for RISC to recover from reset. */
1066 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1067 /*
1068 * It is necessary to for a delay here since the card doesn't
1069 * respond to PCI reads during a reset. On some architectures
1070 * this will result in an MCA.
1071 */
1072 udelay(20);
1073 for (cnt = 30000; cnt; cnt--) {
1074 if ((RD_REG_WORD(&reg->ctrl_status) &
1075 CSR_ISP_SOFT_RESET) == 0)
1076 break;
1077 udelay(100);
1078 }
1079 } else
1080 udelay(10);
1081
1082 /* Reset RISC processor. */
1083 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
1084
1085 WRT_REG_WORD(&reg->semaphore, 0);
1086
1087 /* Release RISC processor. */
1088 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
1089 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1090
1091 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1092 for (cnt = 0; cnt < 30000; cnt++) {
ffb39f03 1093 if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY)
1da177e4 1094 break;
1da177e4
LT		 1095
1096 udelay(100);
1097 }
1098 } else
1099 udelay(100);
1100
1101 /* Turn on master enable */
1102 cmd |= PCI_COMMAND_MASTER;
1103 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
1104
1105 /* Disable RISC pause on FPM parity error. */
1106 if (!IS_QLA2100(ha)) {
1107 WRT_REG_WORD(&reg->hccr, HCCR_DISABLE_PARITY_PAUSE);
1108 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1109 }
1110
1111 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1112}
1113
b1d46989
MI		 1114/**
1115 * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC.
1116 *
1117 * Returns 0 on success.
1118 */
fa492630 1119static int
b1d46989
MI		 1120qla81xx_reset_mpi(scsi_qla_host_t *vha)
1121{
1122 uint16_t mb[4] = {0x1010, 0, 1, 0};
1123
6246b8a1
GM		 1124 if (!IS_QLA81XX(vha->hw))
1125 return QLA_SUCCESS;
1126
b1d46989
MI		 1127 return qla81xx_write_mpi_register(vha, mb);
1128}
1129
0107109e 1130/**
88c26663 1131 * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC.
0107109e
AV		 1132 * @ha: HA context
1133 *
1134 * Returns 0 on success.
1135 */
d14e72fb 1136static inline int
e315cd28 1137qla24xx_reset_risc(scsi_qla_host_t *vha)
0107109e
AV		 1138{
1139 unsigned long flags = 0;
e315cd28 1140 struct qla_hw_data *ha = vha->hw;
0107109e 1141 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
52c82823 1142 uint32_t cnt;
335a1cc9 1143 uint16_t wd;
b1d46989 1144 static int abts_cnt; /* ISP abort retry counts */
d14e72fb 1145 int rval = QLA_SUCCESS;
0107109e 1146
0107109e
AV		 1147 spin_lock_irqsave(&ha->hardware_lock, flags);
1148
1149 /* Reset RISC. */
1150 WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
1151 for (cnt = 0; cnt < 30000; cnt++) {
1152 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
1153 break;
1154
1155 udelay(10);
1156 }
1157
d14e72fb
HM		 1158 if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE))
1159 set_bit(DMA_SHUTDOWN_CMPL, &ha->fw_dump_cap_flags);
1160
1161 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017e,
1162 "HCCR: 0x%x, Control Status %x, DMA active status:0x%x\n",
1163 RD_REG_DWORD(&reg->hccr),
1164 RD_REG_DWORD(&reg->ctrl_status),
1165 (RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE));
1166
0107109e
AV		 1167 WRT_REG_DWORD(&reg->ctrl_status,
1168 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
335a1cc9 1169 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
88c26663 1170
335a1cc9 1171 udelay(100);
d14e72fb 1172
88c26663 1173 /* Wait for firmware to complete NVRAM accesses. */
52c82823 1174 RD_REG_WORD(&reg->mailbox0);
d14e72fb
HM		 1175 for (cnt = 10000; RD_REG_WORD(&reg->mailbox0) != 0 &&
1176 rval == QLA_SUCCESS; cnt--) {
88c26663 1177 barrier();
d14e72fb
HM		 1178 if (cnt)
1179 udelay(5);
1180 else
1181 rval = QLA_FUNCTION_TIMEOUT;
88c26663
AV		 1182 }
1183
d14e72fb
HM		 1184 if (rval == QLA_SUCCESS)
1185 set_bit(ISP_MBX_RDY, &ha->fw_dump_cap_flags);
1186
1187 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017f,
1188 "HCCR: 0x%x, MailBox0 Status 0x%x\n",
1189 RD_REG_DWORD(&reg->hccr),
1190 RD_REG_DWORD(&reg->mailbox0));
1191
335a1cc9 1192 /* Wait for soft-reset to complete. */
52c82823 1193 RD_REG_DWORD(&reg->ctrl_status);
200ffb15 1194 for (cnt = 0; cnt < 60; cnt++) {
0107109e 1195 barrier();
d14e72fb
HM		 1196 if ((RD_REG_DWORD(&reg->ctrl_status) &
1197 CSRX_ISP_SOFT_RESET) == 0)
1198 break;
1199
1200 udelay(5);
0107109e 1201 }
d14e72fb
HM		 1202 if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_ISP_SOFT_RESET))
1203 set_bit(ISP_SOFT_RESET_CMPL, &ha->fw_dump_cap_flags);
1204
1205 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015d,
1206 "HCCR: 0x%x, Soft Reset status: 0x%x\n",
1207 RD_REG_DWORD(&reg->hccr),
1208 RD_REG_DWORD(&reg->ctrl_status));
0107109e 1209
b1d46989
MI		 1210 /* If required, do an MPI FW reset now */
1211 if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
1212 if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
1213 if (++abts_cnt < 5) {
1214 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1215 set_bit(MPI_RESET_NEEDED, &vha->dpc_flags);
1216 } else {
1217 /*
1218 * We exhausted the ISP abort retries. We have to
1219 * set the board offline.
1220 */
1221 abts_cnt = 0;
1222 vha->flags.online = 0;
1223 }
1224 }
1225 }
1226
0107109e
AV		 1227 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
1228 RD_REG_DWORD(&reg->hccr);
1229
1230 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
1231 RD_REG_DWORD(&reg->hccr);
1232
1233 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
1234 RD_REG_DWORD(&reg->hccr);
1235
52c82823 1236 RD_REG_WORD(&reg->mailbox0);
200ffb15 1237 for (cnt = 60; RD_REG_WORD(&reg->mailbox0) != 0 &&
d14e72fb 1238 rval == QLA_SUCCESS; cnt--) {
0107109e 1239 barrier();
d14e72fb
HM		 1240 if (cnt)
1241 udelay(5);
1242 else
1243 rval = QLA_FUNCTION_TIMEOUT;
0107109e 1244 }
d14e72fb
HM		 1245 if (rval == QLA_SUCCESS)
1246 set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags);
1247
1248 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015e,
1249 "Host Risc 0x%x, mailbox0 0x%x\n",
1250 RD_REG_DWORD(&reg->hccr),
1251 RD_REG_WORD(&reg->mailbox0));
0107109e
AV		 1252
1253 spin_unlock_irqrestore(&ha->hardware_lock, flags);
124f85e6 1254
d14e72fb
HM		 1255 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015f,
1256 "Driver in %s mode\n",
1257 IS_NOPOLLING_TYPE(ha) ? "Interrupt" : "Polling");
1258
124f85e6
AV		 1259 if (IS_NOPOLLING_TYPE(ha))
1260 ha->isp_ops->enable_intrs(ha);
d14e72fb
HM		 1261
1262 return rval;
0107109e
AV		 1263}
1264
4ea2c9c7
JC		 1265static void
1266qla25xx_read_risc_sema_reg(scsi_qla_host_t *vha, uint32_t *data)
1267{
1268 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
1269
1270 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
1271 *data = RD_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET);
1272
1273}
1274
1275static void
1276qla25xx_write_risc_sema_reg(scsi_qla_host_t *vha, uint32_t data)
1277{
1278 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
1279
1280 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
1281 WRT_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET, data);
1282}
1283
1284static void
1285qla25xx_manipulate_risc_semaphore(scsi_qla_host_t *vha)
1286{
4ea2c9c7
JC		 1287 uint32_t wd32 = 0;
1288 uint delta_msec = 100;
1289 uint elapsed_msec = 0;
1290 uint timeout_msec;
1291 ulong n;
1292
cc790764
JC		 1293 if (vha->hw->pdev->subsystem_device != 0x0175 &&
1294 vha->hw->pdev->subsystem_device != 0x0240)
4ea2c9c7
JC		 1295 return;
1296
8dd7e3a5
JC		 1297 WRT_REG_DWORD(&vha->hw->iobase->isp24.hccr, HCCRX_SET_RISC_PAUSE);
1298 udelay(100);
1299
4ea2c9c7
JC		 1300attempt:
1301 timeout_msec = TIMEOUT_SEMAPHORE;
1302 n = timeout_msec / delta_msec;
1303 while (n--) {
1304 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_SET);
1305 qla25xx_read_risc_sema_reg(vha, &wd32);
1306 if (wd32 & RISC_SEMAPHORE)
1307 break;
1308 msleep(delta_msec);
1309 elapsed_msec += delta_msec;
1310 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
1311 goto force;
1312 }
1313
1314 if (!(wd32 & RISC_SEMAPHORE))
1315 goto force;
1316
1317 if (!(wd32 & RISC_SEMAPHORE_FORCE))
1318 goto acquired;
1319
1320 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_CLR);
1321 timeout_msec = TIMEOUT_SEMAPHORE_FORCE;
1322 n = timeout_msec / delta_msec;
1323 while (n--) {
1324 qla25xx_read_risc_sema_reg(vha, &wd32);
1325 if (!(wd32 & RISC_SEMAPHORE_FORCE))
1326 break;
1327 msleep(delta_msec);
1328 elapsed_msec += delta_msec;
1329 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
1330 goto force;
1331 }
1332
1333 if (wd32 & RISC_SEMAPHORE_FORCE)
1334 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_CLR);
1335
1336 goto attempt;
1337
1338force:
1339 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_SET);
1340
1341acquired:
1342 return;
1343}
1344
88c26663
AV		 1345/**
1346 * qla24xx_reset_chip() - Reset ISP24xx chip.
1347 * @ha: HA context
1348 *
1349 * Returns 0 on success.
1350 */
1351void
e315cd28 1352qla24xx_reset_chip(scsi_qla_host_t *vha)
88c26663 1353{
e315cd28 1354 struct qla_hw_data *ha = vha->hw;
85880801
AV		 1355
1356 if (pci_channel_offline(ha->pdev) &&
1357 ha->flags.pci_channel_io_perm_failure) {
1358 return;
1359 }
1360
fd34f556 1361 ha->isp_ops->disable_intrs(ha);
88c26663 1362
4ea2c9c7
JC		 1363 qla25xx_manipulate_risc_semaphore(vha);
1364
88c26663 1365 /* Perform RISC reset. */
e315cd28 1366 qla24xx_reset_risc(vha);
88c26663
AV		 1367}
1368
1da177e4
LT		 1369/**
1370 * qla2x00_chip_diag() - Test chip for proper operation.
1371 * @ha: HA context
1372 *
1373 * Returns 0 on success.
1374 */
abbd8870 1375int
e315cd28 1376qla2x00_chip_diag(scsi_qla_host_t *vha)
1da177e4
LT		 1377{
1378 int rval;
e315cd28 1379 struct qla_hw_data *ha = vha->hw;
3d71644c 1380 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 1381 unsigned long flags = 0;
1382 uint16_t data;
1383 uint32_t cnt;
1384 uint16_t mb[5];
73208dfd 1385 struct req_que *req = ha->req_q_map[0];
1da177e4
LT		 1386
1387 /* Assume a failed state */
1388 rval = QLA_FUNCTION_FAILED;
1389
7c3df132
SK		 1390 ql_dbg(ql_dbg_init, vha, 0x007b,
1391 "Testing device at %lx.\n", (u_long)&reg->flash_address);
1da177e4
LT		 1392
1393 spin_lock_irqsave(&ha->hardware_lock, flags);
1394
1395 /* Reset ISP chip. */
1396 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1397
1398 /*
1399 * We need to have a delay here since the card will not respond while
1400 * in reset causing an MCA on some architectures.
1401 */
1402 udelay(20);
1403 data = qla2x00_debounce_register(&reg->ctrl_status);
1404 for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {
1405 udelay(5);
1406 data = RD_REG_WORD(&reg->ctrl_status);
1407 barrier();
1408 }
1409
1410 if (!cnt)
1411 goto chip_diag_failed;
1412
7c3df132
SK		 1413 ql_dbg(ql_dbg_init, vha, 0x007c,
1414 "Reset register cleared by chip reset.\n");
1da177e4
LT		 1415
1416 /* Reset RISC processor. */
1417 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
1418 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
1419
1420 /* Workaround for QLA2312 PCI parity error */
1421 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1422 data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0));
1423 for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) {
1424 udelay(5);
1425 data = RD_MAILBOX_REG(ha, reg, 0);
fa2a1ce5 1426 barrier();
1da177e4
LT		 1427 }
1428 } else
1429 udelay(10);
1430
1431 if (!cnt)
1432 goto chip_diag_failed;
1433
1434 /* Check product ID of chip */
7c3df132 1435 ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product Id of chip.\n");
1da177e4
LT		 1436
1437 mb[1] = RD_MAILBOX_REG(ha, reg, 1);
1438 mb[2] = RD_MAILBOX_REG(ha, reg, 2);
1439 mb[3] = RD_MAILBOX_REG(ha, reg, 3);
1440 mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4));
1441 if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) ||
1442 mb[3] != PROD_ID_3) {
7c3df132
SK		 1443 ql_log(ql_log_warn, vha, 0x0062,
1444 "Wrong product ID = 0x%x,0x%x,0x%x.\n",
1445 mb[1], mb[2], mb[3]);
1da177e4
LT		 1446
1447 goto chip_diag_failed;
1448 }
1449 ha->product_id[0] = mb[1];
1450 ha->product_id[1] = mb[2];
1451 ha->product_id[2] = mb[3];
1452 ha->product_id[3] = mb[4];
1453
1454 /* Adjust fw RISC transfer size */
73208dfd 1455 if (req->length > 1024)
1da177e4
LT		 1456 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024;
1457 else
1458 ha->fw_transfer_size = REQUEST_ENTRY_SIZE *
73208dfd 1459 req->length;
1da177e4
LT		 1460
1461 if (IS_QLA2200(ha) &&
1462 RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) {
1463 /* Limit firmware transfer size with a 2200A */
7c3df132 1464 ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n");
1da177e4 1465
ea5b6382 1466 ha->device_type |= DT_ISP2200A;
1da177e4
LT		 1467 ha->fw_transfer_size = 128;
1468 }
1469
1470 /* Wrap Incoming Mailboxes Test. */
1471 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1472
7c3df132 1473 ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n");
e315cd28 1474 rval = qla2x00_mbx_reg_test(vha);
7c3df132
SK		 1475 if (rval)
1476 ql_log(ql_log_warn, vha, 0x0080,
1477 "Failed mailbox send register test.\n");
1478 else
1da177e4
LT		 1479 /* Flag a successful rval */
1480 rval = QLA_SUCCESS;
1da177e4
LT		 1481 spin_lock_irqsave(&ha->hardware_lock, flags);
1482
1483chip_diag_failed:
1484 if (rval)
7c3df132
SK		 1485 ql_log(ql_log_info, vha, 0x0081,
1486 "Chip diagnostics **** FAILED ****.\n");
1da177e4
LT		 1487
1488 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1489
1490 return (rval);
1491}
1492
0107109e
AV		 1493/**
1494 * qla24xx_chip_diag() - Test ISP24xx for proper operation.
1495 * @ha: HA context
1496 *
1497 * Returns 0 on success.
1498 */
1499int
e315cd28 1500qla24xx_chip_diag(scsi_qla_host_t *vha)
0107109e
AV		 1501{
1502 int rval;
e315cd28 1503 struct qla_hw_data *ha = vha->hw;
73208dfd 1504 struct req_que *req = ha->req_q_map[0];
0107109e 1505
7ec0effd 1506 if (IS_P3P_TYPE(ha))
a9083016
GM		 1507 return QLA_SUCCESS;
1508
73208dfd 1509 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
0107109e 1510
e315cd28 1511 rval = qla2x00_mbx_reg_test(vha);
0107109e 1512 if (rval) {
7c3df132
SK		 1513 ql_log(ql_log_warn, vha, 0x0082,
1514 "Failed mailbox send register test.\n");
0107109e
AV		 1515 } else {
1516 /* Flag a successful rval */
1517 rval = QLA_SUCCESS;
1518 }
1519
1520 return rval;
1521}
1522
a7a167bf 1523void
e315cd28 1524qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
0107109e 1525{
a7a167bf
AV		 1526 int rval;
1527 uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
73208dfd 1528 eft_size, fce_size, mq_size;
df613b96
AV		 1529 dma_addr_t tc_dma;
1530 void *tc;
e315cd28 1531 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 1532 struct req_que *req = ha->req_q_map[0];
1533 struct rsp_que *rsp = ha->rsp_q_map[0];
a7a167bf
AV		 1534
1535 if (ha->fw_dump) {
7c3df132
SK		 1536 ql_dbg(ql_dbg_init, vha, 0x00bd,
1537 "Firmware dump already allocated.\n");
a7a167bf
AV		 1538 return;
1539 }
d4e3e04d 1540
0107109e 1541 ha->fw_dumped = 0;
61f098dd 1542 ha->fw_dump_cap_flags = 0;
f73cb695
CD		 1543 dump_size = fixed_size = mem_size = eft_size = fce_size = mq_size = 0;
1544 req_q_size = rsp_q_size = 0;
1545
1546 if (IS_QLA27XX(ha))
1547 goto try_fce;
1548
d4e3e04d 1549 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
a7a167bf 1550 fixed_size = sizeof(struct qla2100_fw_dump);
d4e3e04d 1551 } else if (IS_QLA23XX(ha)) {
a7a167bf
AV		 1552 fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
1553 mem_size = (ha->fw_memory_size - 0x11000 + 1) *
1554 sizeof(uint16_t);
e428924c 1555 } else if (IS_FWI2_CAPABLE(ha)) {
b20f02e1 1556 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
6246b8a1
GM		 1557 fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem);
1558 else if (IS_QLA81XX(ha))
3a03eb79
AV		 1559 fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
1560 else if (IS_QLA25XX(ha))
1561 fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
1562 else
1563 fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
f73cb695 1564
a7a167bf
AV		 1565 mem_size = (ha->fw_memory_size - 0x100000 + 1) *
1566 sizeof(uint32_t);
050c9bb1 1567 if (ha->mqenable) {
b20f02e1 1568 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
6246b8a1 1569 mq_size = sizeof(struct qla2xxx_mq_chain);
050c9bb1
GM		 1570 /*
1571 * Allocate maximum buffer size for all queues.
1572 * Resizing must be done at end-of-dump processing.
1573 */
1574 mq_size += ha->max_req_queues *
1575 (req->length * sizeof(request_t));
1576 mq_size += ha->max_rsp_queues *
1577 (rsp->length * sizeof(response_t));
1578 }
00876ae8 1579 if (ha->tgt.atio_ring)
2d70c103 1580 mq_size += ha->tgt.atio_q_length * sizeof(request_t);
df613b96 1581 /* Allocate memory for Fibre Channel Event Buffer. */
f73cb695
CD		 1582 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
1583 !IS_QLA27XX(ha))
436a7b11 1584 goto try_eft;
df613b96 1585
f73cb695
CD		 1586try_fce:
1587 if (ha->fce)
1588 dma_free_coherent(&ha->pdev->dev,
1589 FCE_SIZE, ha->fce, ha->fce_dma);
1590
1591 /* Allocate memory for Fibre Channel Event Buffer. */
0ea85b50
JP		 1592 tc = dma_zalloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
1593 GFP_KERNEL);
df613b96 1594 if (!tc) {
7c3df132
SK		 1595 ql_log(ql_log_warn, vha, 0x00be,
1596 "Unable to allocate (%d KB) for FCE.\n",
1597 FCE_SIZE / 1024);
17d98630 1598 goto try_eft;
df613b96
AV		 1599 }
1600
e315cd28 1601 rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS,
df613b96
AV		 1602 ha->fce_mb, &ha->fce_bufs);
1603 if (rval) {
7c3df132
SK		 1604 ql_log(ql_log_warn, vha, 0x00bf,
1605 "Unable to initialize FCE (%d).\n", rval);
df613b96
AV		 1606 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc,
1607 tc_dma);
1608 ha->flags.fce_enabled = 0;
17d98630 1609 goto try_eft;
df613b96 1610 }
cfb0919c 1611 ql_dbg(ql_dbg_init, vha, 0x00c0,
7c3df132 1612 "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024);
df613b96 1613
7d9dade3 1614 fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE;
df613b96
AV		 1615 ha->flags.fce_enabled = 1;
1616 ha->fce_dma = tc_dma;
1617 ha->fce = tc;
f73cb695 1618
436a7b11 1619try_eft:
f73cb695
CD		 1620 if (ha->eft)
1621 dma_free_coherent(&ha->pdev->dev,
1622 EFT_SIZE, ha->eft, ha->eft_dma);
1623
436a7b11 1624 /* Allocate memory for Extended Trace Buffer. */
0ea85b50
JP		 1625 tc = dma_zalloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
1626 GFP_KERNEL);
436a7b11 1627 if (!tc) {
7c3df132
SK		 1628 ql_log(ql_log_warn, vha, 0x00c1,
1629 "Unable to allocate (%d KB) for EFT.\n",
1630 EFT_SIZE / 1024);
436a7b11
AV		 1631 goto cont_alloc;
1632 }
1633
e315cd28 1634 rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
436a7b11 1635 if (rval) {
7c3df132
SK		 1636 ql_log(ql_log_warn, vha, 0x00c2,
1637 "Unable to initialize EFT (%d).\n", rval);
436a7b11
AV		 1638 dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc,
1639 tc_dma);
1640 goto cont_alloc;
1641 }
cfb0919c 1642 ql_dbg(ql_dbg_init, vha, 0x00c3,
7c3df132 1643 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
436a7b11
AV		 1644
1645 eft_size = EFT_SIZE;
1646 ha->eft_dma = tc_dma;
1647 ha->eft = tc;
d4e3e04d 1648 }
f73cb695 1649
a7a167bf 1650cont_alloc:
f73cb695
CD		 1651 if (IS_QLA27XX(ha)) {
1652 if (!ha->fw_dump_template) {
1653 ql_log(ql_log_warn, vha, 0x00ba,
1654 "Failed missing fwdump template\n");
1655 return;
1656 }
1657 dump_size = qla27xx_fwdt_calculate_dump_size(vha);
1658 ql_dbg(ql_dbg_init, vha, 0x00fa,
1659 "-> allocating fwdump (%x bytes)...\n", dump_size);
1660 goto allocate;
1661 }
1662
73208dfd
AC		 1663 req_q_size = req->length * sizeof(request_t);
1664 rsp_q_size = rsp->length * sizeof(response_t);
a7a167bf 1665 dump_size = offsetof(struct qla2xxx_fw_dump, isp);
2afa19a9 1666 dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size;
bb99de67
AV		 1667 ha->chain_offset = dump_size;
1668 dump_size += mq_size + fce_size;
d4e3e04d 1669
f73cb695 1670allocate:
d4e3e04d 1671 ha->fw_dump = vmalloc(dump_size);
a7a167bf 1672 if (!ha->fw_dump) {
7c3df132
SK		 1673 ql_log(ql_log_warn, vha, 0x00c4,
1674 "Unable to allocate (%d KB) for firmware dump.\n",
1675 dump_size / 1024);
a7a167bf 1676
e30d1756
MI		 1677 if (ha->fce) {
1678 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
1679 ha->fce_dma);
1680 ha->fce = NULL;
1681 ha->fce_dma = 0;
1682 }
1683
a7a167bf
AV		 1684 if (ha->eft) {
1685 dma_free_coherent(&ha->pdev->dev, eft_size, ha->eft,
1686 ha->eft_dma);
1687 ha->eft = NULL;
1688 ha->eft_dma = 0;
1689 }
1690 return;
1691 }
f73cb695 1692 ha->fw_dump_len = dump_size;
cfb0919c 1693 ql_dbg(ql_dbg_init, vha, 0x00c5,
7c3df132 1694 "Allocated (%d KB) for firmware dump.\n", dump_size / 1024);
a7a167bf 1695
f73cb695
CD		 1696 if (IS_QLA27XX(ha))
1697 return;
1698
a7a167bf
AV		 1699 ha->fw_dump->signature[0] = 'Q';
1700 ha->fw_dump->signature[1] = 'L';
1701 ha->fw_dump->signature[2] = 'G';
1702 ha->fw_dump->signature[3] = 'C';
ad950360 1703 ha->fw_dump->version = htonl(1);
a7a167bf
AV		 1704
1705 ha->fw_dump->fixed_size = htonl(fixed_size);
1706 ha->fw_dump->mem_size = htonl(mem_size);
1707 ha->fw_dump->req_q_size = htonl(req_q_size);
1708 ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
1709
1710 ha->fw_dump->eft_size = htonl(eft_size);
1711 ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma));
1712 ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma));
1713
1714 ha->fw_dump->header_size =
1715 htonl(offsetof(struct qla2xxx_fw_dump, isp));
0107109e
AV		 1716}
1717
18e7555a
AV		 1718static int
1719qla81xx_mpi_sync(scsi_qla_host_t *vha)
1720{
1721#define MPS_MASK 0xe0
1722 int rval;
1723 uint16_t dc;
1724 uint32_t dw;
18e7555a
AV		 1725
1726 if (!IS_QLA81XX(vha->hw))
1727 return QLA_SUCCESS;
1728
1729 rval = qla2x00_write_ram_word(vha, 0x7c00, 1);
1730 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1731 ql_log(ql_log_warn, vha, 0x0105,
1732 "Unable to acquire semaphore.\n");
18e7555a
AV		 1733 goto done;
1734 }
1735
1736 pci_read_config_word(vha->hw->pdev, 0x54, &dc);
1737 rval = qla2x00_read_ram_word(vha, 0x7a15, &dw);
1738 if (rval != QLA_SUCCESS) {
7c3df132 1739 ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n");
18e7555a
AV		 1740 goto done_release;
1741 }
1742
1743 dc &= MPS_MASK;
1744 if (dc == (dw & MPS_MASK))
1745 goto done_release;
1746
1747 dw &= ~MPS_MASK;
1748 dw |= dc;
1749 rval = qla2x00_write_ram_word(vha, 0x7a15, dw);
1750 if (rval != QLA_SUCCESS) {
7c3df132 1751 ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n");
18e7555a
AV		 1752 }
1753
1754done_release:
1755 rval = qla2x00_write_ram_word(vha, 0x7c00, 0);
1756 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1757 ql_log(ql_log_warn, vha, 0x006d,
1758 "Unable to release semaphore.\n");
18e7555a
AV		 1759 }
1760
1761done:
1762 return rval;
1763}
1764
8d93f550
CD		 1765int
1766qla2x00_alloc_outstanding_cmds(struct qla_hw_data *ha, struct req_que *req)
1767{
1768 /* Don't try to reallocate the array */
1769 if (req->outstanding_cmds)
1770 return QLA_SUCCESS;
1771
d7459527 1772 if (!IS_FWI2_CAPABLE(ha))
8d93f550
CD		 1773 req->num_outstanding_cmds = DEFAULT_OUTSTANDING_COMMANDS;
1774 else {
03e8c680
QT		 1775 if (ha->cur_fw_xcb_count <= ha->cur_fw_iocb_count)
1776 req->num_outstanding_cmds = ha->cur_fw_xcb_count;
8d93f550 1777 else
03e8c680 1778 req->num_outstanding_cmds = ha->cur_fw_iocb_count;
8d93f550
CD		 1779 }
1780
1781 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
1782 req->num_outstanding_cmds, GFP_KERNEL);
1783
1784 if (!req->outstanding_cmds) {
1785 /*
1786 * Try to allocate a minimal size just so we can get through
1787 * initialization.
1788 */
1789 req->num_outstanding_cmds = MIN_OUTSTANDING_COMMANDS;
1790 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
1791 req->num_outstanding_cmds, GFP_KERNEL);
1792
1793 if (!req->outstanding_cmds) {
1794 ql_log(ql_log_fatal, NULL, 0x0126,
1795 "Failed to allocate memory for "
1796 "outstanding_cmds for req_que %p.\n", req);
1797 req->num_outstanding_cmds = 0;
1798 return QLA_FUNCTION_FAILED;
1799 }
1800 }
1801
1802 return QLA_SUCCESS;
1803}
1804
1da177e4
LT		 1805/**
1806 * qla2x00_setup_chip() - Load and start RISC firmware.
1807 * @ha: HA context
1808 *
1809 * Returns 0 on success.
1810 */
1811static int
e315cd28 1812qla2x00_setup_chip(scsi_qla_host_t *vha)
1da177e4 1813{
0107109e
AV		 1814 int rval;
1815 uint32_t srisc_address = 0;
e315cd28 1816 struct qla_hw_data *ha = vha->hw;
3db0652e
AV		 1817 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1818 unsigned long flags;
dda772e8 1819 uint16_t fw_major_version;
3db0652e 1820
7ec0effd 1821 if (IS_P3P_TYPE(ha)) {
a9083016 1822 rval = ha->isp_ops->load_risc(vha, &srisc_address);
14e303d9
AV		 1823 if (rval == QLA_SUCCESS) {
1824 qla2x00_stop_firmware(vha);
a9083016 1825 goto enable_82xx_npiv;
14e303d9 1826 } else
b963752f 1827 goto failed;
a9083016
GM		 1828 }
1829
3db0652e
AV		 1830 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1831 /* Disable SRAM, Instruction RAM and GP RAM parity. */
1832 spin_lock_irqsave(&ha->hardware_lock, flags);
1833 WRT_REG_WORD(&reg->hccr, (HCCR_ENABLE_PARITY + 0x0));
1834 RD_REG_WORD(&reg->hccr);
1835 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1836 }
1da177e4 1837
18e7555a
AV		 1838 qla81xx_mpi_sync(vha);
1839
1da177e4 1840 /* Load firmware sequences */
e315cd28 1841 rval = ha->isp_ops->load_risc(vha, &srisc_address);
0107109e 1842 if (rval == QLA_SUCCESS) {
7c3df132
SK		 1843 ql_dbg(ql_dbg_init, vha, 0x00c9,
1844 "Verifying Checksum of loaded RISC code.\n");
1da177e4 1845
e315cd28 1846 rval = qla2x00_verify_checksum(vha, srisc_address);
1da177e4
LT		 1847 if (rval == QLA_SUCCESS) {
1848 /* Start firmware execution. */
7c3df132
SK		 1849 ql_dbg(ql_dbg_init, vha, 0x00ca,
1850 "Starting firmware.\n");
1da177e4 1851
b0d6cabd
HM		 1852 if (ql2xexlogins)
1853 ha->flags.exlogins_enabled = 1;
1854
2f56a7f1
HM		 1855 if (ql2xexchoffld)
1856 ha->flags.exchoffld_enabled = 1;
1857
e315cd28 1858 rval = qla2x00_execute_fw(vha, srisc_address);
1da177e4 1859 /* Retrieve firmware information. */
dda772e8 1860 if (rval == QLA_SUCCESS) {
b0d6cabd
HM		 1861 rval = qla2x00_set_exlogins_buffer(vha);
1862 if (rval != QLA_SUCCESS)
1863 goto failed;
1864
2f56a7f1
HM		 1865 rval = qla2x00_set_exchoffld_buffer(vha);
1866 if (rval != QLA_SUCCESS)
1867 goto failed;
1868
a9083016 1869enable_82xx_npiv:
dda772e8 1870 fw_major_version = ha->fw_major_version;
7ec0effd 1871 if (IS_P3P_TYPE(ha))
3173167f 1872 qla82xx_check_md_needed(vha);
6246b8a1
GM		 1873 else
1874 rval = qla2x00_get_fw_version(vha);
ca9e9c3e
AV		 1875 if (rval != QLA_SUCCESS)
1876 goto failed;
2c3dfe3f 1877 ha->flags.npiv_supported = 0;
e315cd28 1878 if (IS_QLA2XXX_MIDTYPE(ha) &&
946fb891 1879 (ha->fw_attributes & BIT_2)) {
2c3dfe3f 1880 ha->flags.npiv_supported = 1;
4d0ea247
SJ		 1881 if ((!ha->max_npiv_vports) ||
1882 ((ha->max_npiv_vports + 1) %
eb66dc60 1883 MIN_MULTI_ID_FABRIC))
4d0ea247 1884 ha->max_npiv_vports =
eb66dc60 1885 MIN_MULTI_ID_FABRIC - 1;
4d0ea247 1886 }
03e8c680 1887 qla2x00_get_resource_cnts(vha);
d743de66 1888
8d93f550
CD		 1889 /*
1890 * Allocate the array of outstanding commands
1891 * now that we know the firmware resources.
1892 */
1893 rval = qla2x00_alloc_outstanding_cmds(ha,
1894 vha->req);
1895 if (rval != QLA_SUCCESS)
1896 goto failed;
1897
be5ea3cf 1898 if (!fw_major_version && ql2xallocfwdump
7ec0effd 1899 && !(IS_P3P_TYPE(ha)))
08de2844 1900 qla2x00_alloc_fw_dump(vha);
3b6e5b9d
CD		 1901 } else {
1902 goto failed;
1da177e4
LT		 1903 }
1904 } else {
7c3df132
SK		 1905 ql_log(ql_log_fatal, vha, 0x00cd,
1906 "ISP Firmware failed checksum.\n");
1907 goto failed;
1da177e4 1908 }
c74d88a4
AV		 1909 } else
1910 goto failed;
1da177e4 1911
3db0652e
AV		 1912 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1913 /* Enable proper parity. */
1914 spin_lock_irqsave(&ha->hardware_lock, flags);
1915 if (IS_QLA2300(ha))
1916 /* SRAM parity */
1917 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x1);
1918 else
1919 /* SRAM, Instruction RAM and GP RAM parity */
1920 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x7);
1921 RD_REG_WORD(&reg->hccr);
1922 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1923 }
1924
f3982d89
CD		 1925 if (IS_QLA27XX(ha))
1926 ha->flags.fac_supported = 1;
1927 else if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
1d2874de
JC		 1928 uint32_t size;
1929
1930 rval = qla81xx_fac_get_sector_size(vha, &size);
1931 if (rval == QLA_SUCCESS) {
1932 ha->flags.fac_supported = 1;
1933 ha->fdt_block_size = size << 2;
1934 } else {
7c3df132 1935 ql_log(ql_log_warn, vha, 0x00ce,
1d2874de
JC		 1936 "Unsupported FAC firmware (%d.%02d.%02d).\n",
1937 ha->fw_major_version, ha->fw_minor_version,
1938 ha->fw_subminor_version);
1ca60e3b 1939
f73cb695 1940 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
6246b8a1
GM		 1941 ha->flags.fac_supported = 0;
1942 rval = QLA_SUCCESS;
1943 }
1d2874de
JC		 1944 }
1945 }
ca9e9c3e 1946failed:
1da177e4 1947 if (rval) {
7c3df132
SK		 1948 ql_log(ql_log_fatal, vha, 0x00cf,
1949 "Setup chip ****FAILED****.\n");
1da177e4
LT		 1950 }
1951
1952 return (rval);
1953}
1954
1955/**
1956 * qla2x00_init_response_q_entries() - Initializes response queue entries.
1957 * @ha: HA context
1958 *
1959 * Beginning of request ring has initialization control block already built
1960 * by nvram config routine.
1961 *
1962 * Returns 0 on success.
1963 */
73208dfd
AC		 1964void
1965qla2x00_init_response_q_entries(struct rsp_que *rsp)
1da177e4
LT		 1966{
1967 uint16_t cnt;
1968 response_t *pkt;
1969
2afa19a9
AC		 1970 rsp->ring_ptr = rsp->ring;
1971 rsp->ring_index = 0;
1972 rsp->status_srb = NULL;
e315cd28
AC		 1973 pkt = rsp->ring_ptr;
1974 for (cnt = 0; cnt < rsp->length; cnt++) {
1da177e4
LT		 1975 pkt->signature = RESPONSE_PROCESSED;
1976 pkt++;
1977 }
1da177e4
LT		 1978}
1979
1980/**
1981 * qla2x00_update_fw_options() - Read and process firmware options.
1982 * @ha: HA context
1983 *
1984 * Returns 0 on success.
1985 */
abbd8870 1986void
e315cd28 1987qla2x00_update_fw_options(scsi_qla_host_t *vha)
1da177e4
LT		 1988{
1989 uint16_t swing, emphasis, tx_sens, rx_sens;
e315cd28 1990 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 1991
1992 memset(ha->fw_options, 0, sizeof(ha->fw_options));
e315cd28 1993 qla2x00_get_fw_options(vha, ha->fw_options);
1da177e4
LT		 1994
1995 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1996 return;
1997
1998 /* Serial Link options. */
7c3df132
SK		 1999 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
2000 "Serial link options.\n");
2001 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
2002 (uint8_t *)&ha->fw_seriallink_options,
2003 sizeof(ha->fw_seriallink_options));
1da177e4
LT		 2004
2005 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
2006 if (ha->fw_seriallink_options[3] & BIT_2) {
2007 ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING;
2008
2009 /* 1G settings */
2010 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
2011 emphasis = (ha->fw_seriallink_options[2] &
2012 (BIT_4 | BIT_3)) >> 3;
2013 tx_sens = ha->fw_seriallink_options[0] &
fa2a1ce5 2014 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 2015 rx_sens = (ha->fw_seriallink_options[0] &
2016 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
2017 ha->fw_options[10] = (emphasis << 14) | (swing << 8);
2018 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
2019 if (rx_sens == 0x0)
2020 rx_sens = 0x3;
2021 ha->fw_options[10] |= (tx_sens << 4) | rx_sens;
2022 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
2023 ha->fw_options[10] |= BIT_5 |
2024 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
2025 (tx_sens & (BIT_1 | BIT_0));
2026
2027 /* 2G settings */
2028 swing = (ha->fw_seriallink_options[2] &
2029 (BIT_7 | BIT_6 | BIT_5)) >> 5;
2030 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
2031 tx_sens = ha->fw_seriallink_options[1] &
fa2a1ce5 2032 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 2033 rx_sens = (ha->fw_seriallink_options[1] &
2034 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
2035 ha->fw_options[11] = (emphasis << 14) | (swing << 8);
2036 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
2037 if (rx_sens == 0x0)
2038 rx_sens = 0x3;
2039 ha->fw_options[11] |= (tx_sens << 4) | rx_sens;
2040 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
2041 ha->fw_options[11] |= BIT_5 |
2042 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
2043 (tx_sens & (BIT_1 | BIT_0));
2044 }
2045
2046 /* FCP2 options. */
2047 /* Return command IOCBs without waiting for an ABTS to complete. */
2048 ha->fw_options[3] |= BIT_13;
2049
2050 /* LED scheme. */
2051 if (ha->flags.enable_led_scheme)
2052 ha->fw_options[2] |= BIT_12;
2053
48c02fde
AV		 2054 /* Detect ISP6312. */
2055 if (IS_QLA6312(ha))
2056 ha->fw_options[2] |= BIT_13;
2057
088d09d4
GM		 2058 /* Set Retry FLOGI in case of P2P connection */
2059 if (ha->operating_mode == P2P) {
2060 ha->fw_options[2] |= BIT_3;
2061 ql_dbg(ql_dbg_disc, vha, 0x2100,
2062 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
2063 __func__, ha->fw_options[2]);
2064 }
2065
1da177e4 2066 /* Update firmware options. */
e315cd28 2067 qla2x00_set_fw_options(vha, ha->fw_options);
1da177e4
LT		 2068}
2069
0107109e 2070void
e315cd28 2071qla24xx_update_fw_options(scsi_qla_host_t *vha)
0107109e
AV		 2072{
2073 int rval;
e315cd28 2074 struct qla_hw_data *ha = vha->hw;
0107109e 2075
7ec0effd 2076 if (IS_P3P_TYPE(ha))
a9083016
GM		 2077 return;
2078
f198cafa
HM		 2079 /* Hold status IOCBs until ABTS response received. */
2080 if (ql2xfwholdabts)
2081 ha->fw_options[3] |= BIT_12;
2082
088d09d4
GM		 2083 /* Set Retry FLOGI in case of P2P connection */
2084 if (ha->operating_mode == P2P) {
2085 ha->fw_options[2] |= BIT_3;
2086 ql_dbg(ql_dbg_disc, vha, 0x2101,
2087 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
2088 __func__, ha->fw_options[2]);
2089 }
2090
0107109e 2091 /* Update Serial Link options. */
f94097ed 2092 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0)
0107109e
AV		 2093 return;
2094
e315cd28 2095 rval = qla2x00_set_serdes_params(vha,
f94097ed
AV		 2096 le16_to_cpu(ha->fw_seriallink_options24[1]),
2097 le16_to_cpu(ha->fw_seriallink_options24[2]),
2098 le16_to_cpu(ha->fw_seriallink_options24[3]));
0107109e 2099 if (rval != QLA_SUCCESS) {
7c3df132 2100 ql_log(ql_log_warn, vha, 0x0104,
0107109e
AV		 2101 "Unable to update Serial Link options (%x).\n", rval);
2102 }
2103}
2104
abbd8870 2105void
e315cd28 2106qla2x00_config_rings(struct scsi_qla_host *vha)
abbd8870 2107{
e315cd28 2108 struct qla_hw_data *ha = vha->hw;
3d71644c 2109 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
73208dfd
AC		 2110 struct req_que *req = ha->req_q_map[0];
2111 struct rsp_que *rsp = ha->rsp_q_map[0];
abbd8870
AV		 2112
2113 /* Setup ring parameters in initialization control block. */
ad950360
BVA		 2114 ha->init_cb->request_q_outpointer = cpu_to_le16(0);
2115 ha->init_cb->response_q_inpointer = cpu_to_le16(0);
e315cd28
AC		 2116 ha->init_cb->request_q_length = cpu_to_le16(req->length);
2117 ha->init_cb->response_q_length = cpu_to_le16(rsp->length);
2118 ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
2119 ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
2120 ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
2121 ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
abbd8870
AV		 2122
2123 WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0);
2124 WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0);
2125 WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0);
2126 WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0);
2127 RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */
2128}
2129
0107109e 2130void
e315cd28 2131qla24xx_config_rings(struct scsi_qla_host *vha)
0107109e 2132{
e315cd28 2133 struct qla_hw_data *ha = vha->hw;
118e2ef9 2134 device_reg_t *reg = ISP_QUE_REG(ha, 0);
73208dfd
AC		 2135 struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
2136 struct qla_msix_entry *msix;
0107109e 2137 struct init_cb_24xx *icb;
73208dfd
AC		 2138 uint16_t rid = 0;
2139 struct req_que *req = ha->req_q_map[0];
2140 struct rsp_que *rsp = ha->rsp_q_map[0];
0107109e 2141
6246b8a1 2142 /* Setup ring parameters in initialization control block. */
0107109e 2143 icb = (struct init_cb_24xx *)ha->init_cb;
ad950360
BVA		 2144 icb->request_q_outpointer = cpu_to_le16(0);
2145 icb->response_q_inpointer = cpu_to_le16(0);
e315cd28
AC		 2146 icb->request_q_length = cpu_to_le16(req->length);
2147 icb->response_q_length = cpu_to_le16(rsp->length);
2148 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
2149 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
2150 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
2151 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
0107109e 2152
2d70c103 2153 /* Setup ATIO queue dma pointers for target mode */
ad950360 2154 icb->atio_q_inpointer = cpu_to_le16(0);
2d70c103
NB		 2155 icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length);
2156 icb->atio_q_address[0] = cpu_to_le32(LSD(ha->tgt.atio_dma));
2157 icb->atio_q_address[1] = cpu_to_le32(MSD(ha->tgt.atio_dma));
2158
7c6300e3 2159 if (IS_SHADOW_REG_CAPABLE(ha))
ad950360 2160 icb->firmware_options_2 |= cpu_to_le32(BIT_30|BIT_29);
7c6300e3 2161
f73cb695 2162 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
ad950360
BVA		 2163 icb->qos = cpu_to_le16(QLA_DEFAULT_QUE_QOS);
2164 icb->rid = cpu_to_le16(rid);
73208dfd
AC		 2165 if (ha->flags.msix_enabled) {
2166 msix = &ha->msix_entries[1];
7c3df132
SK		 2167 ql_dbg(ql_dbg_init, vha, 0x00fd,
2168 "Registering vector 0x%x for base que.\n",
2169 msix->entry);
73208dfd
AC		 2170 icb->msix = cpu_to_le16(msix->entry);
2171 }
2172 /* Use alternate PCI bus number */
2173 if (MSB(rid))
ad950360 2174 icb->firmware_options_2 |= cpu_to_le32(BIT_19);
73208dfd
AC		 2175 /* Use alternate PCI devfn */
2176 if (LSB(rid))
ad950360 2177 icb->firmware_options_2 |= cpu_to_le32(BIT_18);
73208dfd 2178
3155754a 2179 /* Use Disable MSIX Handshake mode for capable adapters */
6246b8a1
GM		 2180 if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) &&
2181 (ha->flags.msix_enabled)) {
ad950360 2182 icb->firmware_options_2 &= cpu_to_le32(~BIT_22);
3155754a 2183 ha->flags.disable_msix_handshake = 1;
7c3df132
SK		 2184 ql_dbg(ql_dbg_init, vha, 0x00fe,
2185 "MSIX Handshake Disable Mode turned on.\n");
3155754a 2186 } else {
ad950360 2187 icb->firmware_options_2 |= cpu_to_le32(BIT_22);
3155754a 2188 }
ad950360 2189 icb->firmware_options_2 |= cpu_to_le32(BIT_23);
73208dfd
AC		 2190
2191 WRT_REG_DWORD(&reg->isp25mq.req_q_in, 0);
2192 WRT_REG_DWORD(&reg->isp25mq.req_q_out, 0);
2193 WRT_REG_DWORD(&reg->isp25mq.rsp_q_in, 0);
2194 WRT_REG_DWORD(&reg->isp25mq.rsp_q_out, 0);
2195 } else {
2196 WRT_REG_DWORD(&reg->isp24.req_q_in, 0);
2197 WRT_REG_DWORD(&reg->isp24.req_q_out, 0);
2198 WRT_REG_DWORD(&reg->isp24.rsp_q_in, 0);
2199 WRT_REG_DWORD(&reg->isp24.rsp_q_out, 0);
2200 }
aa230bc5 2201 qlt_24xx_config_rings(vha);
2d70c103 2202
73208dfd
AC		 2203 /* PCI posting */
2204 RD_REG_DWORD(&ioreg->hccr);
0107109e
AV		 2205}
2206
1da177e4
LT		 2207/**
2208 * qla2x00_init_rings() - Initializes firmware.
2209 * @ha: HA context
2210 *
2211 * Beginning of request ring has initialization control block already built
2212 * by nvram config routine.
2213 *
2214 * Returns 0 on success.
2215 */
8ae6d9c7 2216int
e315cd28 2217qla2x00_init_rings(scsi_qla_host_t *vha)
1da177e4
LT		 2218{
2219 int rval;
2220 unsigned long flags = 0;
29bdccbe 2221 int cnt, que;
e315cd28 2222 struct qla_hw_data *ha = vha->hw;
29bdccbe
AC		 2223 struct req_que *req;
2224 struct rsp_que *rsp;
2c3dfe3f
SJ		 2225 struct mid_init_cb_24xx *mid_init_cb =
2226 (struct mid_init_cb_24xx *) ha->init_cb;
1da177e4
LT		 2227
2228 spin_lock_irqsave(&ha->hardware_lock, flags);
2229
2230 /* Clear outstanding commands array. */
2afa19a9 2231 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 2232 req = ha->req_q_map[que];
cb43285f 2233 if (!req || !test_bit(que, ha->req_qid_map))
29bdccbe 2234 continue;
7c6300e3
JC		 2235 req->out_ptr = (void *)(req->ring + req->length);
2236 *req->out_ptr = 0;
8d93f550 2237 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++)
29bdccbe 2238 req->outstanding_cmds[cnt] = NULL;
1da177e4 2239
2afa19a9 2240 req->current_outstanding_cmd = 1;
1da177e4 2241
29bdccbe
AC		 2242 /* Initialize firmware. */
2243 req->ring_ptr = req->ring;
2244 req->ring_index = 0;
2245 req->cnt = req->length;
2246 }
1da177e4 2247
2afa19a9 2248 for (que = 0; que < ha->max_rsp_queues; que++) {
29bdccbe 2249 rsp = ha->rsp_q_map[que];
cb43285f 2250 if (!rsp || !test_bit(que, ha->rsp_qid_map))
29bdccbe 2251 continue;
7c6300e3
JC		 2252 rsp->in_ptr = (void *)(rsp->ring + rsp->length);
2253 *rsp->in_ptr = 0;
29bdccbe 2254 /* Initialize response queue entries */
8ae6d9c7
GM		 2255 if (IS_QLAFX00(ha))
2256 qlafx00_init_response_q_entries(rsp);
2257 else
2258 qla2x00_init_response_q_entries(rsp);
29bdccbe 2259 }
1da177e4 2260
2d70c103
NB		 2261 ha->tgt.atio_ring_ptr = ha->tgt.atio_ring;
2262 ha->tgt.atio_ring_index = 0;
2263 /* Initialize ATIO queue entries */
2264 qlt_init_atio_q_entries(vha);
2265
e315cd28 2266 ha->isp_ops->config_rings(vha);
1da177e4
LT		 2267
2268 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2269
8ae6d9c7
GM		 2270 ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n");
2271
2272 if (IS_QLAFX00(ha)) {
2273 rval = qlafx00_init_firmware(vha, ha->init_cb_size);
2274 goto next_check;
2275 }
2276
1da177e4 2277 /* Update any ISP specific firmware options before initialization. */
e315cd28 2278 ha->isp_ops->update_fw_options(vha);
1da177e4 2279
605aa2bc 2280 if (ha->flags.npiv_supported) {
45980cc2 2281 if (ha->operating_mode == LOOP && !IS_CNA_CAPABLE(ha))
605aa2bc 2282 ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
c48339de 2283 mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
605aa2bc
LC		 2284 }
2285
24a08138 2286 if (IS_FWI2_CAPABLE(ha)) {
ad950360 2287 mid_init_cb->options = cpu_to_le16(BIT_1);
24a08138 2288 mid_init_cb->init_cb.execution_throttle =
03e8c680 2289 cpu_to_le16(ha->cur_fw_xcb_count);
40f3862b
JC		 2290 ha->flags.dport_enabled =
2291 (mid_init_cb->init_cb.firmware_options_1 & BIT_7) != 0;
2292 ql_dbg(ql_dbg_init, vha, 0x0191, "DPORT Support: %s.\n",
2293 (ha->flags.dport_enabled) ? "enabled" : "disabled");
2294 /* FA-WWPN Status */
2486c627 2295 ha->flags.fawwpn_enabled =
40f3862b 2296 (mid_init_cb->init_cb.firmware_options_1 & BIT_6) != 0;
2486c627
HM		 2297 ql_dbg(ql_dbg_init, vha, 0x0141, "FA-WWPN Support: %s.\n",
2298 (ha->flags.fawwpn_enabled) ? "enabled" : "disabled");
24a08138 2299 }
2c3dfe3f 2300
e315cd28 2301 rval = qla2x00_init_firmware(vha, ha->init_cb_size);
8ae6d9c7 2302next_check:
1da177e4 2303 if (rval) {
7c3df132
SK		 2304 ql_log(ql_log_fatal, vha, 0x00d2,
2305 "Init Firmware **** FAILED ****.\n");
1da177e4 2306 } else {
7c3df132
SK		 2307 ql_dbg(ql_dbg_init, vha, 0x00d3,
2308 "Init Firmware -- success.\n");
1da177e4
LT		 2309 }
2310
2311 return (rval);
2312}
2313
2314/**
2315 * qla2x00_fw_ready() - Waits for firmware ready.
2316 * @ha: HA context
2317 *
2318 * Returns 0 on success.
2319 */
2320static int
e315cd28 2321qla2x00_fw_ready(scsi_qla_host_t *vha)
1da177e4
LT		 2322{
2323 int rval;
4d4df193 2324 unsigned long wtime, mtime, cs84xx_time;
1da177e4
LT		 2325 uint16_t min_wait; /* Minimum wait time if loop is down */
2326 uint16_t wait_time; /* Wait time if loop is coming ready */
b5a340dd 2327 uint16_t state[6];
e315cd28 2328 struct qla_hw_data *ha = vha->hw;
1da177e4 2329
8ae6d9c7
GM		 2330 if (IS_QLAFX00(vha->hw))
2331 return qlafx00_fw_ready(vha);
2332
1da177e4
LT		 2333 rval = QLA_SUCCESS;
2334
33461491
CD		 2335 /* Time to wait for loop down */
2336 if (IS_P3P_TYPE(ha))
2337 min_wait = 30;
2338 else
2339 min_wait = 20;
1da177e4
LT		 2340
2341 /*
2342 * Firmware should take at most one RATOV to login, plus 5 seconds for
2343 * our own processing.
2344 */
2345 if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) {
2346 wait_time = min_wait;
2347 }
2348
2349 /* Min wait time if loop down */
2350 mtime = jiffies + (min_wait * HZ);
2351
2352 /* wait time before firmware ready */
2353 wtime = jiffies + (wait_time * HZ);
2354
2355 /* Wait for ISP to finish LIP */
e315cd28 2356 if (!vha->flags.init_done)
7c3df132
SK		 2357 ql_log(ql_log_info, vha, 0x801e,
2358 "Waiting for LIP to complete.\n");
1da177e4
LT		 2359
2360 do {
5b939038 2361 memset(state, -1, sizeof(state));
e315cd28 2362 rval = qla2x00_get_firmware_state(vha, state);
1da177e4 2363 if (rval == QLA_SUCCESS) {
4d4df193 2364 if (state[0] < FSTATE_LOSS_OF_SYNC) {
e315cd28 2365 vha->device_flags &= ~DFLG_NO_CABLE;
1da177e4 2366 }
4d4df193 2367 if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) {
7c3df132
SK		 2368 ql_dbg(ql_dbg_taskm, vha, 0x801f,
2369 "fw_state=%x 84xx=%x.\n", state[0],
2370 state[2]);
4d4df193
HK		 2371 if ((state[2] & FSTATE_LOGGED_IN) &&
2372 (state[2] & FSTATE_WAITING_FOR_VERIFY)) {
7c3df132
SK		 2373 ql_dbg(ql_dbg_taskm, vha, 0x8028,
2374 "Sending verify iocb.\n");
4d4df193
HK		 2375
2376 cs84xx_time = jiffies;
e315cd28 2377 rval = qla84xx_init_chip(vha);
7c3df132
SK		 2378 if (rval != QLA_SUCCESS) {
2379 ql_log(ql_log_warn,
cfb0919c 2380 vha, 0x8007,
7c3df132 2381 "Init chip failed.\n");
4d4df193 2382 break;
7c3df132 2383 }
4d4df193
HK		 2384
2385 /* Add time taken to initialize. */
2386 cs84xx_time = jiffies - cs84xx_time;
2387 wtime += cs84xx_time;
2388 mtime += cs84xx_time;
cfb0919c 2389 ql_dbg(ql_dbg_taskm, vha, 0x8008,
7c3df132
SK		 2390 "Increasing wait time by %ld. "
2391 "New time %ld.\n", cs84xx_time,
2392 wtime);
4d4df193
HK		 2393 }
2394 } else if (state[0] == FSTATE_READY) {
7c3df132
SK		 2395 ql_dbg(ql_dbg_taskm, vha, 0x8037,
2396 "F/W Ready - OK.\n");
1da177e4 2397
e315cd28 2398 qla2x00_get_retry_cnt(vha, &ha->retry_count,
1da177e4
LT		 2399 &ha->login_timeout, &ha->r_a_tov);
2400
2401 rval = QLA_SUCCESS;
2402 break;
2403 }
2404
2405 rval = QLA_FUNCTION_FAILED;
2406
e315cd28 2407 if (atomic_read(&vha->loop_down_timer) &&
4d4df193 2408 state[0] != FSTATE_READY) {
1da177e4 2409 /* Loop down. Timeout on min_wait for states
fa2a1ce5
AV		 2410 * other than Wait for Login.
2411 */
1da177e4 2412 if (time_after_eq(jiffies, mtime)) {
7c3df132 2413 ql_log(ql_log_info, vha, 0x8038,
1da177e4
LT		 2414 "Cable is unplugged...\n");
2415
e315cd28 2416 vha->device_flags |= DFLG_NO_CABLE;
1da177e4
LT		 2417 break;
2418 }
2419 }
2420 } else {
2421 /* Mailbox cmd failed. Timeout on min_wait. */
cdbb0a4f 2422 if (time_after_eq(jiffies, mtime) ||
7190575f 2423 ha->flags.isp82xx_fw_hung)
1da177e4
LT		 2424 break;
2425 }
2426
2427 if (time_after_eq(jiffies, wtime))
2428 break;
2429
2430 /* Delay for a while */
2431 msleep(500);
1da177e4
LT		 2432 } while (1);
2433
7c3df132 2434 ql_dbg(ql_dbg_taskm, vha, 0x803a,
b5a340dd
JC		 2435 "fw_state=%x (%x, %x, %x, %x %x) curr time=%lx.\n", state[0],
2436 state[1], state[2], state[3], state[4], state[5], jiffies);
1da177e4 2437
cfb0919c 2438 if (rval && !(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132
SK		 2439 ql_log(ql_log_warn, vha, 0x803b,
2440 "Firmware ready **** FAILED ****.\n");
1da177e4
LT		 2441 }
2442
2443 return (rval);
2444}
2445
2446/*
2447* qla2x00_configure_hba
2448* Setup adapter context.
2449*
2450* Input:
2451* ha = adapter state pointer.
2452*
2453* Returns:
2454* 0 = success
2455*
2456* Context:
2457* Kernel context.
2458*/
2459static int
e315cd28 2460qla2x00_configure_hba(scsi_qla_host_t *vha)
1da177e4
LT		 2461{
2462 int rval;
2463 uint16_t loop_id;
2464 uint16_t topo;
2c3dfe3f 2465 uint16_t sw_cap;
1da177e4
LT		 2466 uint8_t al_pa;
2467 uint8_t area;
2468 uint8_t domain;
2469 char connect_type[22];
e315cd28 2470 struct qla_hw_data *ha = vha->hw;
f24b5cb8 2471 unsigned long flags;
61e1b269 2472 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 2473
2474 /* Get host addresses. */
e315cd28 2475 rval = qla2x00_get_adapter_id(vha,
2c3dfe3f 2476 &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
1da177e4 2477 if (rval != QLA_SUCCESS) {
e315cd28 2478 if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
6246b8a1 2479 IS_CNA_CAPABLE(ha) ||
33135aa2 2480 (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
7c3df132
SK		 2481 ql_dbg(ql_dbg_disc, vha, 0x2008,
2482 "Loop is in a transition state.\n");
33135aa2 2483 } else {
7c3df132
SK		 2484 ql_log(ql_log_warn, vha, 0x2009,
2485 "Unable to get host loop ID.\n");
61e1b269
JC		 2486 if (IS_FWI2_CAPABLE(ha) && (vha == base_vha) &&
2487 (rval == QLA_COMMAND_ERROR && loop_id == 0x1b)) {
2488 ql_log(ql_log_warn, vha, 0x1151,
2489 "Doing link init.\n");
2490 if (qla24xx_link_initialize(vha) == QLA_SUCCESS)
2491 return rval;
2492 }
e315cd28 2493 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
33135aa2 2494 }
1da177e4
LT		 2495 return (rval);
2496 }
2497
2498 if (topo == 4) {
7c3df132
SK		 2499 ql_log(ql_log_info, vha, 0x200a,
2500 "Cannot get topology - retrying.\n");
1da177e4
LT		 2501 return (QLA_FUNCTION_FAILED);
2502 }
2503
e315cd28 2504 vha->loop_id = loop_id;
1da177e4
LT		 2505
2506 /* initialize */
2507 ha->min_external_loopid = SNS_FIRST_LOOP_ID;
2508 ha->operating_mode = LOOP;
2c3dfe3f 2509 ha->switch_cap = 0;
1da177e4
LT		 2510
2511 switch (topo) {
2512 case 0:
7c3df132 2513 ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n");
1da177e4
LT		 2514 ha->current_topology = ISP_CFG_NL;
2515 strcpy(connect_type, "(Loop)");
2516 break;
2517
2518 case 1:
7c3df132 2519 ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n");
2c3dfe3f 2520 ha->switch_cap = sw_cap;
1da177e4
LT		 2521 ha->current_topology = ISP_CFG_FL;
2522 strcpy(connect_type, "(FL_Port)");
2523 break;
2524
2525 case 2:
7c3df132 2526 ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n");
1da177e4
LT		 2527 ha->operating_mode = P2P;
2528 ha->current_topology = ISP_CFG_N;
2529 strcpy(connect_type, "(N_Port-to-N_Port)");
2530 break;
2531
2532 case 3:
7c3df132 2533 ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n");
2c3dfe3f 2534 ha->switch_cap = sw_cap;
1da177e4
LT		 2535 ha->operating_mode = P2P;
2536 ha->current_topology = ISP_CFG_F;
2537 strcpy(connect_type, "(F_Port)");
2538 break;
2539
2540 default:
7c3df132
SK		 2541 ql_dbg(ql_dbg_disc, vha, 0x200f,
2542 "HBA in unknown topology %x, using NL.\n", topo);
1da177e4
LT		 2543 ha->current_topology = ISP_CFG_NL;
2544 strcpy(connect_type, "(Loop)");
2545 break;
2546 }
2547
2548 /* Save Host port and loop ID. */
2549 /* byte order - Big Endian */
e315cd28
AC		 2550 vha->d_id.b.domain = domain;
2551 vha->d_id.b.area = area;
2552 vha->d_id.b.al_pa = al_pa;
1da177e4 2553
f24b5cb8 2554 spin_lock_irqsave(&ha->vport_slock, flags);
2d70c103 2555 qlt_update_vp_map(vha, SET_AL_PA);
f24b5cb8 2556 spin_unlock_irqrestore(&ha->vport_slock, flags);
2d70c103 2557
e315cd28 2558 if (!vha->flags.init_done)
7c3df132
SK		 2559 ql_log(ql_log_info, vha, 0x2010,
2560 "Topology - %s, Host Loop address 0x%x.\n",
e315cd28 2561 connect_type, vha->loop_id);
1da177e4 2562
1da177e4
LT		 2563 return(rval);
2564}
2565
a9083016 2566inline void
e315cd28
AC		 2567qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
2568 char *def)
9bb9fcf2
AV		 2569{
2570 char *st, *en;
2571 uint16_t index;
e315cd28 2572 struct qla_hw_data *ha = vha->hw;
ab671149 2573 int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
6246b8a1 2574 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha);
9bb9fcf2
AV		 2575
2576 if (memcmp(model, BINZERO, len) != 0) {
2577 strncpy(ha->model_number, model, len);
2578 st = en = ha->model_number;
2579 en += len - 1;
2580 while (en > st) {
2581 if (*en != 0x20 && *en != 0x00)
2582 break;
2583 *en-- = '\0';
2584 }
2585
2586 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 2587 if (use_tbl &&
2588 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2 2589 index < QLA_MODEL_NAMES)
1ee27146
JC		 2590 strncpy(ha->model_desc,
2591 qla2x00_model_name[index * 2 + 1],
2592 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 2593 } else {
2594 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 2595 if (use_tbl &&
2596 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2
AV		 2597 index < QLA_MODEL_NAMES) {
2598 strcpy(ha->model_number,
2599 qla2x00_model_name[index * 2]);
1ee27146
JC		 2600 strncpy(ha->model_desc,
2601 qla2x00_model_name[index * 2 + 1],
2602 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 2603 } else {
2604 strcpy(ha->model_number, def);
2605 }
2606 }
1ee27146 2607 if (IS_FWI2_CAPABLE(ha))
e315cd28 2608 qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc,
1ee27146 2609 sizeof(ha->model_desc));
9bb9fcf2
AV		 2610}
2611
4e08df3f
DM		 2612/* On sparc systems, obtain port and node WWN from firmware
2613 * properties.
2614 */
e315cd28 2615static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv)
4e08df3f
DM		 2616{
2617#ifdef CONFIG_SPARC
e315cd28 2618 struct qla_hw_data *ha = vha->hw;
4e08df3f 2619 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 2620 struct device_node *dp = pci_device_to_OF_node(pdev);
2621 const u8 *val;
4e08df3f
DM		 2622 int len;
2623
2624 val = of_get_property(dp, "port-wwn", &len);
2625 if (val && len >= WWN_SIZE)
2626 memcpy(nv->port_name, val, WWN_SIZE);
2627
2628 val = of_get_property(dp, "node-wwn", &len);
2629 if (val && len >= WWN_SIZE)
2630 memcpy(nv->node_name, val, WWN_SIZE);
2631#endif
2632}
2633
1da177e4
LT		 2634/*
2635* NVRAM configuration for ISP 2xxx
2636*
2637* Input:
2638* ha = adapter block pointer.
2639*
2640* Output:
2641* initialization control block in response_ring
2642* host adapters parameters in host adapter block
2643*
2644* Returns:
2645* 0 = success.
2646*/
abbd8870 2647int
e315cd28 2648qla2x00_nvram_config(scsi_qla_host_t *vha)
1da177e4 2649{
4e08df3f 2650 int rval;
0107109e
AV		 2651 uint8_t chksum = 0;
2652 uint16_t cnt;
2653 uint8_t *dptr1, *dptr2;
e315cd28 2654 struct qla_hw_data *ha = vha->hw;
0107109e 2655 init_cb_t *icb = ha->init_cb;
281afe19
SJ		 2656 nvram_t *nv = ha->nvram;
2657 uint8_t *ptr = ha->nvram;
3d71644c 2658 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 2659
4e08df3f
DM		 2660 rval = QLA_SUCCESS;
2661
1da177e4 2662 /* Determine NVRAM starting address. */
0107109e 2663 ha->nvram_size = sizeof(nvram_t);
1da177e4
LT		 2664 ha->nvram_base = 0;
2665 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
2666 if ((RD_REG_WORD(&reg->ctrl_status) >> 14) == 1)
2667 ha->nvram_base = 0x80;
2668
2669 /* Get NVRAM data and calculate checksum. */
e315cd28 2670 ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size);
0107109e
AV		 2671 for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++)
2672 chksum += *ptr++;
1da177e4 2673
7c3df132
SK		 2674 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
2675 "Contents of NVRAM.\n");
2676 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
2677 (uint8_t *)nv, ha->nvram_size);
1da177e4
LT		 2678
2679 /* Bad NVRAM data, set defaults parameters. */
2680 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' ||
2681 nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) {
2682 /* Reset NVRAM data. */
7c3df132 2683 ql_log(ql_log_warn, vha, 0x0064,
9e336520 2684 "Inconsistent NVRAM "
7c3df132
SK		 2685 "detected: checksum=0x%x id=%c version=0x%x.\n",
2686 chksum, nv->id[0], nv->nvram_version);
2687 ql_log(ql_log_warn, vha, 0x0065,
2688 "Falling back to "
2689 "functioning (yet invalid -- WWPN) defaults.\n");
4e08df3f
DM		 2690
2691 /*
2692 * Set default initialization control block.
2693 */
2694 memset(nv, 0, ha->nvram_size);
2695 nv->parameter_block_version = ICB_VERSION;
2696
2697 if (IS_QLA23XX(ha)) {
2698 nv->firmware_options[0] = BIT_2 | BIT_1;
2699 nv->firmware_options[1] = BIT_7 | BIT_5;
2700 nv->add_firmware_options[0] = BIT_5;
2701 nv->add_firmware_options[1] = BIT_5 | BIT_4;
98aee70d 2702 nv->frame_payload_size = 2048;
4e08df3f
DM		 2703 nv->special_options[1] = BIT_7;
2704 } else if (IS_QLA2200(ha)) {
2705 nv->firmware_options[0] = BIT_2 | BIT_1;
2706 nv->firmware_options[1] = BIT_7 | BIT_5;
2707 nv->add_firmware_options[0] = BIT_5;
2708 nv->add_firmware_options[1] = BIT_5 | BIT_4;
98aee70d 2709 nv->frame_payload_size = 1024;
4e08df3f
DM		 2710 } else if (IS_QLA2100(ha)) {
2711 nv->firmware_options[0] = BIT_3 | BIT_1;
2712 nv->firmware_options[1] = BIT_5;
98aee70d 2713 nv->frame_payload_size = 1024;
4e08df3f
DM		 2714 }
2715
ad950360
BVA		 2716 nv->max_iocb_allocation = cpu_to_le16(256);
2717 nv->execution_throttle = cpu_to_le16(16);
4e08df3f
DM		 2718 nv->retry_count = 8;
2719 nv->retry_delay = 1;
2720
2721 nv->port_name[0] = 33;
2722 nv->port_name[3] = 224;
2723 nv->port_name[4] = 139;
2724
e315cd28 2725 qla2xxx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 2726
2727 nv->login_timeout = 4;
2728
2729 /*
2730 * Set default host adapter parameters
2731 */
2732 nv->host_p[1] = BIT_2;
2733 nv->reset_delay = 5;
2734 nv->port_down_retry_count = 8;
ad950360 2735 nv->max_luns_per_target = cpu_to_le16(8);
4e08df3f
DM		 2736 nv->link_down_timeout = 60;
2737
2738 rval = 1;
1da177e4
LT		 2739 }
2740
2741#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
2742 /*
2743 * The SN2 does not provide BIOS emulation which means you can't change
2744 * potentially bogus BIOS settings. Force the use of default settings
2745 * for link rate and frame size. Hope that the rest of the settings
2746 * are valid.
2747 */
2748 if (ia64_platform_is("sn2")) {
98aee70d 2749 nv->frame_payload_size = 2048;
1da177e4
LT		 2750 if (IS_QLA23XX(ha))
2751 nv->special_options[1] = BIT_7;
2752 }
2753#endif
2754
2755 /* Reset Initialization control block */
0107109e 2756 memset(icb, 0, ha->init_cb_size);
1da177e4
LT		 2757
2758 /*
2759 * Setup driver NVRAM options.
2760 */
2761 nv->firmware_options[0] |= (BIT_6 | BIT_1);
2762 nv->firmware_options[0] &= ~(BIT_5 | BIT_4);
2763 nv->firmware_options[1] |= (BIT_5 | BIT_0);
2764 nv->firmware_options[1] &= ~BIT_4;
2765
2766 if (IS_QLA23XX(ha)) {
2767 nv->firmware_options[0] |= BIT_2;
2768 nv->firmware_options[0] &= ~BIT_3;
2d70c103 2769 nv->special_options[0] &= ~BIT_6;
0107109e 2770 nv->add_firmware_options[1] |= BIT_5 | BIT_4;
1da177e4
LT		 2771
2772 if (IS_QLA2300(ha)) {
2773 if (ha->fb_rev == FPM_2310) {
2774 strcpy(ha->model_number, "QLA2310");
2775 } else {
2776 strcpy(ha->model_number, "QLA2300");
2777 }
2778 } else {
e315cd28 2779 qla2x00_set_model_info(vha, nv->model_number,
9bb9fcf2 2780 sizeof(nv->model_number), "QLA23xx");
1da177e4
LT		 2781 }
2782 } else if (IS_QLA2200(ha)) {
2783 nv->firmware_options[0] |= BIT_2;
2784 /*
2785 * 'Point-to-point preferred, else loop' is not a safe
2786 * connection mode setting.
2787 */
2788 if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
2789 (BIT_5 | BIT_4)) {
2790 /* Force 'loop preferred, else point-to-point'. */
2791 nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
2792 nv->add_firmware_options[0] |= BIT_5;
2793 }
2794 strcpy(ha->model_number, "QLA22xx");
2795 } else /*if (IS_QLA2100(ha))*/ {
2796 strcpy(ha->model_number, "QLA2100");
2797 }
2798
2799 /*
2800 * Copy over NVRAM RISC parameter block to initialization control block.
2801 */
2802 dptr1 = (uint8_t *)icb;
2803 dptr2 = (uint8_t *)&nv->parameter_block_version;
2804 cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;
2805 while (cnt--)
2806 *dptr1++ = *dptr2++;
2807
2808 /* Copy 2nd half. */
2809 dptr1 = (uint8_t *)icb->add_firmware_options;
2810 cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;
2811 while (cnt--)
2812 *dptr1++ = *dptr2++;
2813
5341e868
AV		 2814 /* Use alternate WWN? */
2815 if (nv->host_p[1] & BIT_7) {
2816 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
2817 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
2818 }
2819
1da177e4
LT		 2820 /* Prepare nodename */
2821 if ((icb->firmware_options[1] & BIT_6) == 0) {
2822 /*
2823 * Firmware will apply the following mask if the nodename was
2824 * not provided.
2825 */
2826 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
2827 icb->node_name[0] &= 0xF0;
2828 }
2829
2830 /*
2831 * Set host adapter parameters.
2832 */
3ce8866c
SK		 2833
2834 /*
2835 * BIT_7 in the host-parameters section allows for modification to
2836 * internal driver logging.
2837 */
0181944f 2838 if (nv->host_p[0] & BIT_7)
cfb0919c 2839 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
1da177e4
LT		 2840 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
2841 /* Always load RISC code on non ISP2[12]00 chips. */
2842 if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
2843 ha->flags.disable_risc_code_load = 0;
2844 ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0);
2845 ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
2846 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
06c22bd1 2847 ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
d4c760c2 2848 ha->flags.disable_serdes = 0;
1da177e4
LT		 2849
2850 ha->operating_mode =
2851 (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
2852
2853 memcpy(ha->fw_seriallink_options, nv->seriallink_options,
2854 sizeof(ha->fw_seriallink_options));
2855
2856 /* save HBA serial number */
2857 ha->serial0 = icb->port_name[5];
2858 ha->serial1 = icb->port_name[6];
2859 ha->serial2 = icb->port_name[7];
e315cd28
AC		 2860 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
2861 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
1da177e4 2862
ad950360 2863 icb->execution_throttle = cpu_to_le16(0xFFFF);
1da177e4
LT		 2864
2865 ha->retry_count = nv->retry_count;
2866
2867 /* Set minimum login_timeout to 4 seconds. */
5b91490e 2868 if (nv->login_timeout != ql2xlogintimeout)
1da177e4
LT		 2869 nv->login_timeout = ql2xlogintimeout;
2870 if (nv->login_timeout < 4)
2871 nv->login_timeout = 4;
2872 ha->login_timeout = nv->login_timeout;
1da177e4 2873
00a537b8
AV		 2874 /* Set minimum RATOV to 100 tenths of a second. */
2875 ha->r_a_tov = 100;
1da177e4 2876
1da177e4
LT		 2877 ha->loop_reset_delay = nv->reset_delay;
2878
1da177e4
LT		 2879 /* Link Down Timeout = 0:
2880 *
2881 * When Port Down timer expires we will start returning
2882 * I/O's to OS with "DID_NO_CONNECT".
2883 *
2884 * Link Down Timeout != 0:
2885 *
2886 * The driver waits for the link to come up after link down
2887 * before returning I/Os to OS with "DID_NO_CONNECT".
fa2a1ce5 2888 */
1da177e4
LT		 2889 if (nv->link_down_timeout == 0) {
2890 ha->loop_down_abort_time =
354d6b21 2891 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
1da177e4
LT		 2892 } else {
2893 ha->link_down_timeout = nv->link_down_timeout;
2894 ha->loop_down_abort_time =
2895 (LOOP_DOWN_TIME - ha->link_down_timeout);
fa2a1ce5 2896 }
1da177e4 2897
1da177e4
LT		 2898 /*
2899 * Need enough time to try and get the port back.
2900 */
2901 ha->port_down_retry_count = nv->port_down_retry_count;
2902 if (qlport_down_retry)
2903 ha->port_down_retry_count = qlport_down_retry;
2904 /* Set login_retry_count */
2905 ha->login_retry_count = nv->retry_count;
2906 if (ha->port_down_retry_count == nv->port_down_retry_count &&
2907 ha->port_down_retry_count > 3)
2908 ha->login_retry_count = ha->port_down_retry_count;
2909 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
2910 ha->login_retry_count = ha->port_down_retry_count;
2911 if (ql2xloginretrycount)
2912 ha->login_retry_count = ql2xloginretrycount;
2913
ad950360 2914 icb->lun_enables = cpu_to_le16(0);
1da177e4
LT		 2915 icb->command_resource_count = 0;
2916 icb->immediate_notify_resource_count = 0;
ad950360 2917 icb->timeout = cpu_to_le16(0);
1da177e4
LT		 2918
2919 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
2920 /* Enable RIO */
2921 icb->firmware_options[0] &= ~BIT_3;
2922 icb->add_firmware_options[0] &=
2923 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
2924 icb->add_firmware_options[0] |= BIT_2;
2925 icb->response_accumulation_timer = 3;
2926 icb->interrupt_delay_timer = 5;
2927
e315cd28 2928 vha->flags.process_response_queue = 1;
1da177e4 2929 } else {
4fdfefe5 2930 /* Enable ZIO. */
e315cd28 2931 if (!vha->flags.init_done) {
4fdfefe5
AV		 2932 ha->zio_mode = icb->add_firmware_options[0] &
2933 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
2934 ha->zio_timer = icb->interrupt_delay_timer ?
2935 icb->interrupt_delay_timer: 2;
2936 }
1da177e4
LT		 2937 icb->add_firmware_options[0] &=
2938 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
e315cd28 2939 vha->flags.process_response_queue = 0;
4fdfefe5 2940 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d
AV		 2941 ha->zio_mode = QLA_ZIO_MODE_6;
2942
7c3df132 2943 ql_log(ql_log_info, vha, 0x0068,
4fdfefe5
AV		 2944 "ZIO mode %d enabled; timer delay (%d us).\n",
2945 ha->zio_mode, ha->zio_timer * 100);
1da177e4 2946
4fdfefe5
AV		 2947 icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;
2948 icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;
e315cd28 2949 vha->flags.process_response_queue = 1;
1da177e4
LT		 2950 }
2951 }
2952
4e08df3f 2953 if (rval) {
7c3df132
SK		 2954 ql_log(ql_log_warn, vha, 0x0069,
2955 "NVRAM configuration failed.\n");
4e08df3f
DM		 2956 }
2957 return (rval);
1da177e4
LT		 2958}
2959
19a7b4ae
JSEC		 2960static void
2961qla2x00_rport_del(void *data)
2962{
2963 fc_port_t *fcport = data;
d97994dc 2964 struct fc_rport *rport;
044d78e1 2965 unsigned long flags;
d97994dc 2966
044d78e1 2967 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
ac280b67 2968 rport = fcport->drport ? fcport->drport: fcport->rport;
d97994dc 2969 fcport->drport = NULL;
044d78e1 2970 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
df673274 2971 if (rport)
d97994dc 2972 fc_remote_port_delete(rport);
19a7b4ae
JSEC		 2973}
2974
1da177e4
LT		 2975/**
2976 * qla2x00_alloc_fcport() - Allocate a generic fcport.
2977 * @ha: HA context
2978 * @flags: allocation flags
2979 *
2980 * Returns a pointer to the allocated fcport, or NULL, if none available.
2981 */
9a069e19 2982fc_port_t *
e315cd28 2983qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags)
1da177e4
LT		 2984{
2985 fc_port_t *fcport;
2986
bbfbbbc1
MK		 2987 fcport = kzalloc(sizeof(fc_port_t), flags);
2988 if (!fcport)
2989 return NULL;
1da177e4
LT		 2990
2991 /* Setup fcport template structure. */
e315cd28 2992 fcport->vha = vha;
1da177e4
LT		 2993 fcport->port_type = FCT_UNKNOWN;
2994 fcport->loop_id = FC_NO_LOOP_ID;
ec426e10 2995 qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
ad3e0eda 2996 fcport->supported_classes = FC_COS_UNSPECIFIED;
1da177e4 2997
bbfbbbc1 2998 return fcport;
1da177e4
LT		 2999}
3000
3001/*
3002 * qla2x00_configure_loop
3003 * Updates Fibre Channel Device Database with what is actually on loop.
3004 *
3005 * Input:
3006 * ha = adapter block pointer.
3007 *
3008 * Returns:
3009 * 0 = success.
3010 * 1 = error.
3011 * 2 = database was full and device was not configured.
3012 */
3013static int
e315cd28 3014qla2x00_configure_loop(scsi_qla_host_t *vha)
1da177e4
LT		 3015{
3016 int rval;
3017 unsigned long flags, save_flags;
e315cd28 3018 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3019 rval = QLA_SUCCESS;
3020
3021 /* Get Initiator ID */
e315cd28
AC		 3022 if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) {
3023 rval = qla2x00_configure_hba(vha);
1da177e4 3024 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3025 ql_dbg(ql_dbg_disc, vha, 0x2013,
3026 "Unable to configure HBA.\n");
1da177e4
LT		 3027 return (rval);
3028 }
3029 }
3030
e315cd28 3031 save_flags = flags = vha->dpc_flags;
7c3df132
SK		 3032 ql_dbg(ql_dbg_disc, vha, 0x2014,
3033 "Configure loop -- dpc flags = 0x%lx.\n", flags);
1da177e4
LT		 3034
3035 /*
3036 * If we have both an RSCN and PORT UPDATE pending then handle them
3037 * both at the same time.
3038 */
e315cd28
AC		 3039 clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
3040 clear_bit(RSCN_UPDATE, &vha->dpc_flags);
1da177e4 3041
3064ff39
MH		 3042 qla2x00_get_data_rate(vha);
3043
1da177e4
LT		 3044 /* Determine what we need to do */
3045 if (ha->current_topology == ISP_CFG_FL &&
3046 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
3047
1da177e4
LT		 3048 set_bit(RSCN_UPDATE, &flags);
3049
3050 } else if (ha->current_topology == ISP_CFG_F &&
3051 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
3052
1da177e4
LT		 3053 set_bit(RSCN_UPDATE, &flags);
3054 clear_bit(LOCAL_LOOP_UPDATE, &flags);
21333b48
AV		 3055
3056 } else if (ha->current_topology == ISP_CFG_N) {
3057 clear_bit(RSCN_UPDATE, &flags);
1da177e4 3058
e315cd28 3059 } else if (!vha->flags.online ||
1da177e4
LT		 3060 (test_bit(ABORT_ISP_ACTIVE, &flags))) {
3061
1da177e4
LT		 3062 set_bit(RSCN_UPDATE, &flags);
3063 set_bit(LOCAL_LOOP_UPDATE, &flags);
3064 }
3065
3066 if (test_bit(LOCAL_LOOP_UPDATE, &flags)) {
7c3df132
SK		 3067 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
3068 ql_dbg(ql_dbg_disc, vha, 0x2015,
3069 "Loop resync needed, failing.\n");
1da177e4 3070 rval = QLA_FUNCTION_FAILED;
642ef983 3071 } else
e315cd28 3072 rval = qla2x00_configure_local_loop(vha);
1da177e4
LT		 3073 }
3074
3075 if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
7c3df132
SK		 3076 if (LOOP_TRANSITION(vha)) {
3077 ql_dbg(ql_dbg_disc, vha, 0x201e,
3078 "Needs RSCN update and loop transition.\n");
1da177e4 3079 rval = QLA_FUNCTION_FAILED;
7c3df132 3080 }
e315cd28
AC		 3081 else
3082 rval = qla2x00_configure_fabric(vha);
1da177e4
LT		 3083 }
3084
3085 if (rval == QLA_SUCCESS) {
e315cd28
AC		 3086 if (atomic_read(&vha->loop_down_timer) ||
3087 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4
LT		 3088 rval = QLA_FUNCTION_FAILED;
3089 } else {
e315cd28 3090 atomic_set(&vha->loop_state, LOOP_READY);
7c3df132
SK		 3091 ql_dbg(ql_dbg_disc, vha, 0x2069,
3092 "LOOP READY.\n");
3bb67df5
DKU		 3093
3094 /*
3095 * Process any ATIO queue entries that came in
3096 * while we weren't online.
3097 */
3098 if (qla_tgt_mode_enabled(vha)) {
3099 if (IS_QLA27XX(ha) || IS_QLA83XX(ha)) {
3100 spin_lock_irqsave(&ha->tgt.atio_lock,
3101 flags);
3102 qlt_24xx_process_atio_queue(vha, 0);
3103 spin_unlock_irqrestore(
3104 &ha->tgt.atio_lock, flags);
3105 } else {
3106 spin_lock_irqsave(&ha->hardware_lock,
3107 flags);
3108 qlt_24xx_process_atio_queue(vha, 1);
3109 spin_unlock_irqrestore(
3110 &ha->hardware_lock, flags);
3111 }
3112 }
1da177e4
LT		 3113 }
3114 }
3115
3116 if (rval) {
7c3df132
SK		 3117 ql_dbg(ql_dbg_disc, vha, 0x206a,
3118 "%s *** FAILED ***.\n", __func__);
1da177e4 3119 } else {
7c3df132
SK		 3120 ql_dbg(ql_dbg_disc, vha, 0x206b,
3121 "%s: exiting normally.\n", __func__);
1da177e4
LT		 3122 }
3123
cc3ef7bc 3124 /* Restore state if a resync event occurred during processing */
e315cd28 3125 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4 3126 if (test_bit(LOCAL_LOOP_UPDATE, &save_flags))
e315cd28 3127 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
f4658b6c 3128 if (test_bit(RSCN_UPDATE, &save_flags)) {
e315cd28 3129 set_bit(RSCN_UPDATE, &vha->dpc_flags);
f4658b6c 3130 }
1da177e4
LT		 3131 }
3132
3133 return (rval);
3134}
3135
3136
3137
3138/*
3139 * qla2x00_configure_local_loop
3140 * Updates Fibre Channel Device Database with local loop devices.
3141 *
3142 * Input:
3143 * ha = adapter block pointer.
3144 *
3145 * Returns:
3146 * 0 = success.
3147 */
3148static int
e315cd28 3149qla2x00_configure_local_loop(scsi_qla_host_t *vha)
1da177e4
LT		 3150{
3151 int rval, rval2;
3152 int found_devs;
3153 int found;
3154 fc_port_t *fcport, *new_fcport;
3155
3156 uint16_t index;
3157 uint16_t entries;
3158 char *id_iter;
3159 uint16_t loop_id;
3160 uint8_t domain, area, al_pa;
e315cd28 3161 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3162
3163 found_devs = 0;
3164 new_fcport = NULL;
642ef983 3165 entries = MAX_FIBRE_DEVICES_LOOP;
1da177e4 3166
1da177e4 3167 /* Get list of logged in devices. */
642ef983 3168 memset(ha->gid_list, 0, qla2x00_gid_list_size(ha));
e315cd28 3169 rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma,
1da177e4
LT		 3170 &entries);
3171 if (rval != QLA_SUCCESS)
3172 goto cleanup_allocation;
3173
7c3df132
SK		 3174 ql_dbg(ql_dbg_disc, vha, 0x2017,
3175 "Entries in ID list (%d).\n", entries);
3176 ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
3177 (uint8_t *)ha->gid_list,
3178 entries * sizeof(struct gid_list_info));
1da177e4
LT		 3179
3180 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 3181 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3182 if (new_fcport == NULL) {
7c3df132
SK		 3183 ql_log(ql_log_warn, vha, 0x2018,
3184 "Memory allocation failed for fcport.\n");
1da177e4
LT		 3185 rval = QLA_MEMORY_ALLOC_FAILED;
3186 goto cleanup_allocation;
3187 }
3188 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
3189
3190 /*
3191 * Mark local devices that were present with FCF_DEVICE_LOST for now.
3192 */
e315cd28 3193 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 3194 if (atomic_read(&fcport->state) == FCS_ONLINE &&
3195 fcport->port_type != FCT_BROADCAST &&
3196 (fcport->flags & FCF_FABRIC_DEVICE) == 0) {
3197
7c3df132
SK		 3198 ql_dbg(ql_dbg_disc, vha, 0x2019,
3199 "Marking port lost loop_id=0x%04x.\n",
3200 fcport->loop_id);
1da177e4 3201
ec426e10 3202 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3203 }
3204 }
3205
3206 /* Add devices to port list. */
3207 id_iter = (char *)ha->gid_list;
3208 for (index = 0; index < entries; index++) {
3209 domain = ((struct gid_list_info *)id_iter)->domain;
3210 area = ((struct gid_list_info *)id_iter)->area;
3211 al_pa = ((struct gid_list_info *)id_iter)->al_pa;
abbd8870 3212 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1da177e4
LT		 3213 loop_id = (uint16_t)
3214 ((struct gid_list_info *)id_iter)->loop_id_2100;
abbd8870 3215 else
1da177e4
LT		 3216 loop_id = le16_to_cpu(
3217 ((struct gid_list_info *)id_iter)->loop_id);
abbd8870 3218 id_iter += ha->gid_list_info_size;
1da177e4
LT		 3219
3220 /* Bypass reserved domain fields. */
3221 if ((domain & 0xf0) == 0xf0)
3222 continue;
3223
3224 /* Bypass if not same domain and area of adapter. */
f7d289f6 3225 if (area && domain &&
e315cd28 3226 (area != vha->d_id.b.area || domain != vha->d_id.b.domain))
1da177e4
LT		 3227 continue;
3228
3229 /* Bypass invalid local loop ID. */
3230 if (loop_id > LAST_LOCAL_LOOP_ID)
3231 continue;
3232
370d550e
AE		 3233 memset(new_fcport, 0, sizeof(fc_port_t));
3234
1da177e4
LT		 3235 /* Fill in member data. */
3236 new_fcport->d_id.b.domain = domain;
3237 new_fcport->d_id.b.area = area;
3238 new_fcport->d_id.b.al_pa = al_pa;
3239 new_fcport->loop_id = loop_id;
e315cd28 3240 rval2 = qla2x00_get_port_database(vha, new_fcport, 0);
1da177e4 3241 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 3242 ql_dbg(ql_dbg_disc, vha, 0x201a,
3243 "Failed to retrieve fcport information "
3244 "-- get_port_database=%x, loop_id=0x%04x.\n",
3245 rval2, new_fcport->loop_id);
3246 ql_dbg(ql_dbg_disc, vha, 0x201b,
3247 "Scheduling resync.\n");
e315cd28 3248 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4
LT		 3249 continue;
3250 }
3251
3252 /* Check for matching device in port list. */
3253 found = 0;
3254 fcport = NULL;
e315cd28 3255 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 3256 if (memcmp(new_fcport->port_name, fcport->port_name,
3257 WWN_SIZE))
3258 continue;
3259
ddb9b126 3260 fcport->flags &= ~FCF_FABRIC_DEVICE;
1da177e4
LT		 3261 fcport->loop_id = new_fcport->loop_id;
3262 fcport->port_type = new_fcport->port_type;
3263 fcport->d_id.b24 = new_fcport->d_id.b24;
3264 memcpy(fcport->node_name, new_fcport->node_name,
3265 WWN_SIZE);
3266
3267 found++;
3268 break;
3269 }
3270
3271 if (!found) {
3272 /* New device, add to fcports list. */
e315cd28 3273 list_add_tail(&new_fcport->list, &vha->vp_fcports);
1da177e4
LT		 3274
3275 /* Allocate a new replacement fcport. */
3276 fcport = new_fcport;
e315cd28 3277 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3278 if (new_fcport == NULL) {
7c3df132
SK		 3279 ql_log(ql_log_warn, vha, 0x201c,
3280 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 3281 rval = QLA_MEMORY_ALLOC_FAILED;
3282 goto cleanup_allocation;
3283 }
3284 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
3285 }
3286
d8b45213 3287 /* Base iIDMA settings on HBA port speed. */
a3cbdfad 3288 fcport->fp_speed = ha->link_data_rate;
d8b45213 3289
e315cd28 3290 qla2x00_update_fcport(vha, fcport);
1da177e4
LT		 3291
3292 found_devs++;
3293 }
3294
3295cleanup_allocation:
c9475cb0 3296 kfree(new_fcport);
1da177e4
LT		 3297
3298 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3299 ql_dbg(ql_dbg_disc, vha, 0x201d,
3300 "Configure local loop error exit: rval=%x.\n", rval);
1da177e4
LT		 3301 }
3302
1da177e4
LT		 3303 return (rval);
3304}
3305
d8b45213 3306static void
e315cd28 3307qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
d8b45213 3308{
d8b45213 3309 int rval;
93f2bd67 3310 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 3311 struct qla_hw_data *ha = vha->hw;
d8b45213 3312
c76f2c01 3313 if (!IS_IIDMA_CAPABLE(ha))
d8b45213
AV		 3314 return;
3315
c9afb9a2
GM		 3316 if (atomic_read(&fcport->state) != FCS_ONLINE)
3317 return;
3318
39bd9622
AV		 3319 if (fcport->fp_speed == PORT_SPEED_UNKNOWN ||
3320 fcport->fp_speed > ha->link_data_rate)
d8b45213
AV		 3321 return;
3322
e315cd28 3323 rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed,
a3cbdfad 3324 mb);
d8b45213 3325 if (rval != QLA_SUCCESS) {
7c3df132 3326 ql_dbg(ql_dbg_disc, vha, 0x2004,
7b833558
OK		 3327 "Unable to adjust iIDMA %8phN -- %04x %x %04x %04x.\n",
3328 fcport->port_name, rval, fcport->fp_speed, mb[0], mb[1]);
d8b45213 3329 } else {
7c3df132 3330 ql_dbg(ql_dbg_disc, vha, 0x2005,
7b833558 3331 "iIDMA adjusted to %s GB/s on %8phN.\n",
d0297c9a 3332 qla2x00_get_link_speed_str(ha, fcport->fp_speed),
7b833558 3333 fcport->port_name);
d8b45213
AV		 3334 }
3335}
3336
23be331d 3337static void
e315cd28 3338qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport)
8482e118
AV		 3339{
3340 struct fc_rport_identifiers rport_ids;
bdf79621 3341 struct fc_rport *rport;
044d78e1 3342 unsigned long flags;
8482e118 3343
f8b02a85
AV		 3344 rport_ids.node_name = wwn_to_u64(fcport->node_name);
3345 rport_ids.port_name = wwn_to_u64(fcport->port_name);
8482e118
AV		 3346 rport_ids.port_id = fcport->d_id.b.domain << 16 |
3347 fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa;
77d74143 3348 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
e315cd28 3349 fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids);
77d74143 3350 if (!rport) {
7c3df132
SK		 3351 ql_log(ql_log_warn, vha, 0x2006,
3352 "Unable to allocate fc remote port.\n");
77d74143
AV		 3353 return;
3354 }
2d70c103 3355
044d78e1 3356 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
19a7b4ae 3357 *((fc_port_t **)rport->dd_data) = fcport;
044d78e1 3358 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
d97994dc 3359
ad3e0eda 3360 rport->supported_classes = fcport->supported_classes;
77d74143 3361
8482e118
AV		 3362 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
3363 if (fcport->port_type == FCT_INITIATOR)
3364 rport_ids.roles |= FC_RPORT_ROLE_FCP_INITIATOR;
3365 if (fcport->port_type == FCT_TARGET)
3366 rport_ids.roles |= FC_RPORT_ROLE_FCP_TARGET;
77d74143 3367 fc_remote_port_rolechg(rport, rport_ids.roles);
1da177e4
LT		 3368}
3369
23be331d
AB		 3370/*
3371 * qla2x00_update_fcport
3372 * Updates device on list.
3373 *
3374 * Input:
3375 * ha = adapter block pointer.
3376 * fcport = port structure pointer.
3377 *
3378 * Return:
3379 * 0 - Success
3380 * BIT_0 - error
3381 *
3382 * Context:
3383 * Kernel context.
3384 */
3385void
e315cd28 3386qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
23be331d 3387{
e315cd28 3388 fcport->vha = vha;
8ae6d9c7
GM		 3389
3390 if (IS_QLAFX00(vha->hw)) {
3391 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
d20ed91b 3392 goto reg_port;
8ae6d9c7 3393 }
23be331d 3394 fcport->login_retry = 0;
5ff1d584 3395 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
23be331d 3396
1f93da52 3397 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
e315cd28 3398 qla2x00_iidma_fcport(vha, fcport);
21090cbe 3399 qla24xx_update_fcport_fcp_prio(vha, fcport);
d20ed91b
AP		 3400
3401reg_port:
3402 if (qla_ini_mode_enabled(vha))
3403 qla2x00_reg_remote_port(vha, fcport);
23be331d
AB		 3404}
3405
1da177e4
LT		 3406/*
3407 * qla2x00_configure_fabric
3408 * Setup SNS devices with loop ID's.
3409 *
3410 * Input:
3411 * ha = adapter block pointer.
3412 *
3413 * Returns:
3414 * 0 = success.
3415 * BIT_0 = error
3416 */
3417static int
e315cd28 3418qla2x00_configure_fabric(scsi_qla_host_t *vha)
1da177e4 3419{
b3b02e6e 3420 int rval;
e452ceb6 3421 fc_port_t *fcport, *fcptemp;
1da177e4
LT		 3422 uint16_t next_loopid;
3423 uint16_t mb[MAILBOX_REGISTER_COUNT];
0107109e 3424 uint16_t loop_id;
1da177e4 3425 LIST_HEAD(new_fcports);
e315cd28
AC		 3426 struct qla_hw_data *ha = vha->hw;
3427 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
df673274 3428 int discovery_gen;
1da177e4
LT		 3429
3430 /* If FL port exists, then SNS is present */
e428924c 3431 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 3432 loop_id = NPH_F_PORT;
3433 else
3434 loop_id = SNS_FL_PORT;
e315cd28 3435 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1);
1da177e4 3436 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3437 ql_dbg(ql_dbg_disc, vha, 0x201f,
3438 "MBX_GET_PORT_NAME failed, No FL Port.\n");
1da177e4 3439
e315cd28 3440 vha->device_flags &= ~SWITCH_FOUND;
1da177e4
LT		 3441 return (QLA_SUCCESS);
3442 }
e315cd28 3443 vha->device_flags |= SWITCH_FOUND;
1da177e4 3444
1da177e4 3445 do {
cca5335c
AV		 3446 /* FDMI support. */
3447 if (ql2xfdmienable &&
e315cd28
AC		 3448 test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags))
3449 qla2x00_fdmi_register(vha);
cca5335c 3450
1da177e4 3451 /* Ensure we are logged into the SNS. */
e428924c 3452 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 3453 loop_id = NPH_SNS;
3454 else
3455 loop_id = SIMPLE_NAME_SERVER;
0b91d116
CD		 3456 rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff,
3457 0xfc, mb, BIT_1|BIT_0);
3458 if (rval != QLA_SUCCESS) {
3459 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
e452ceb6 3460 return rval;
0b91d116 3461 }
1da177e4 3462 if (mb[0] != MBS_COMMAND_COMPLETE) {
7c3df132
SK		 3463 ql_dbg(ql_dbg_disc, vha, 0x2042,
3464 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x "
3465 "mb[6]=%x mb[7]=%x.\n", loop_id, mb[0], mb[1],
3466 mb[2], mb[6], mb[7]);
1da177e4
LT		 3467 return (QLA_SUCCESS);
3468 }
3469
e315cd28
AC		 3470 if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) {
3471 if (qla2x00_rft_id(vha)) {
1da177e4 3472 /* EMPTY */
7c3df132
SK		 3473 ql_dbg(ql_dbg_disc, vha, 0x2045,
3474 "Register FC-4 TYPE failed.\n");
1da177e4 3475 }
e315cd28 3476 if (qla2x00_rff_id(vha)) {
1da177e4 3477 /* EMPTY */
7c3df132
SK		 3478 ql_dbg(ql_dbg_disc, vha, 0x2049,
3479 "Register FC-4 Features failed.\n");
1da177e4 3480 }
e315cd28 3481 if (qla2x00_rnn_id(vha)) {
1da177e4 3482 /* EMPTY */
7c3df132
SK		 3483 ql_dbg(ql_dbg_disc, vha, 0x204f,
3484 "Register Node Name failed.\n");
e315cd28 3485 } else if (qla2x00_rsnn_nn(vha)) {
1da177e4 3486 /* EMPTY */
7c3df132
SK		 3487 ql_dbg(ql_dbg_disc, vha, 0x2053,
3488 "Register Symobilic Node Name failed.\n");
1da177e4
LT		 3489 }
3490 }
3491
827210ba
JC		 3492#define QLA_FCPORT_SCAN 1
3493#define QLA_FCPORT_FOUND 2
3494
3495 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3496 fcport->scan_state = QLA_FCPORT_SCAN;
3497 }
3498
df673274
AP		 3499 /* Mark the time right before querying FW for connected ports.
3500 * This process is long, asynchronous and by the time it's done,
3501 * collected information might not be accurate anymore. E.g.
3502 * disconnected port might have re-connected and a brand new
3503 * session has been created. In this case session's generation
3504 * will be newer than discovery_gen. */
3505 qlt_do_generation_tick(vha, &discovery_gen);
3506
e315cd28 3507 rval = qla2x00_find_all_fabric_devs(vha, &new_fcports);
1da177e4
LT		 3508 if (rval != QLA_SUCCESS)
3509 break;
3510
e452ceb6
JC		 3511 /*
3512 * Logout all previous fabric devices marked lost, except
3513 * FCP2 devices.
3514 */
e315cd28
AC		 3515 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3516 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
1da177e4
LT		 3517 break;
3518
3519 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0)
3520 continue;
3521
b2032fd5
RD		 3522 if (fcport->scan_state == QLA_FCPORT_SCAN) {
3523 if (qla_ini_mode_enabled(base_vha) &&
3524 atomic_read(&fcport->state) == FCS_ONLINE) {
3525 qla2x00_mark_device_lost(vha, fcport,
3526 ql2xplogiabsentdevice, 0);
3527 if (fcport->loop_id != FC_NO_LOOP_ID &&
3528 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
3529 fcport->port_type != FCT_INITIATOR &&
3530 fcport->port_type != FCT_BROADCAST) {
3531 ha->isp_ops->fabric_logout(vha,
3532 fcport->loop_id,
3533 fcport->d_id.b.domain,
3534 fcport->d_id.b.area,
3535 fcport->d_id.b.al_pa);
3536 qla2x00_clear_loop_id(fcport);
3537 }
3538 } else if (!qla_ini_mode_enabled(base_vha)) {
3539 /*
3540 * In target mode, explicitly kill
3541 * sessions and log out of devices
3542 * that are gone, so that we don't
3543 * end up with an initiator using the
3544 * wrong ACL (if the fabric recycles
3545 * an FC address and we have a stale
3546 * session around) and so that we don't
3547 * report initiators that are no longer
3548 * on the fabric.
3549 */
3550 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf077,
3551 "port gone, logging out/killing session: "
3552 "%8phC state 0x%x flags 0x%x fc4_type 0x%x "
3553 "scan_state %d\n",
3554 fcport->port_name,
3555 atomic_read(&fcport->state),
3556 fcport->flags, fcport->fc4_type,
3557 fcport->scan_state);
df673274
AP		 3558 qlt_fc_port_deleted(vha, fcport,
3559 discovery_gen);
1da177e4
LT		 3560 }
3561 }
e452ceb6 3562 }
1da177e4 3563
e452ceb6
JC		 3564 /* Starting free loop ID. */
3565 next_loopid = ha->min_external_loopid;
3566
3567 /*
3568 * Scan through our port list and login entries that need to be
3569 * logged in.
3570 */
3571 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3572 if (atomic_read(&vha->loop_down_timer) ||
3573 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3574 break;
3575
3576 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0 ||
3577 (fcport->flags & FCF_LOGIN_NEEDED) == 0)
3578 continue;
3579
b2032fd5
RD		 3580 /*
3581 * If we're not an initiator, skip looking for devices
3582 * and logging in. There's no reason for us to do it,
3583 * and it seems to actively cause problems in target
3584 * mode if we race with the initiator logging into us
3585 * (we might get the "port ID used" status back from
3586 * our login command and log out the initiator, which
3587 * seems to cause havoc).
3588 */
3589 if (!qla_ini_mode_enabled(base_vha)) {
3590 if (fcport->scan_state == QLA_FCPORT_FOUND) {
3591 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf078,
3592 "port %8phC state 0x%x flags 0x%x fc4_type 0x%x "
3593 "scan_state %d (initiator mode disabled; skipping "
3594 "login)\n", fcport->port_name,
3595 atomic_read(&fcport->state),
3596 fcport->flags, fcport->fc4_type,
3597 fcport->scan_state);
3598 }
3599 continue;
3600 }
3601
e452ceb6
JC		 3602 if (fcport->loop_id == FC_NO_LOOP_ID) {
3603 fcport->loop_id = next_loopid;
3604 rval = qla2x00_find_new_loop_id(
3605 base_vha, fcport);
3606 if (rval != QLA_SUCCESS) {
3607 /* Ran out of IDs to use */
3608 break;
1da177e4
LT		 3609 }
3610 }
e452ceb6
JC		 3611 /* Login and update database */
3612 qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
3613 }
3614
3615 /* Exit if out of loop IDs. */
3616 if (rval != QLA_SUCCESS) {
3617 break;
3618 }
3619
3620 /*
3621 * Login and add the new devices to our port list.
3622 */
3623 list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) {
3624 if (atomic_read(&vha->loop_down_timer) ||
3625 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3626 break;
3627
b2032fd5
RD		 3628 /*
3629 * If we're not an initiator, skip looking for devices
3630 * and logging in. There's no reason for us to do it,
3631 * and it seems to actively cause problems in target
3632 * mode if we race with the initiator logging into us
3633 * (we might get the "port ID used" status back from
3634 * our login command and log out the initiator, which
3635 * seems to cause havoc).
3636 */
3637 if (qla_ini_mode_enabled(base_vha)) {
3638 /* Find a new loop ID to use. */
3639 fcport->loop_id = next_loopid;
3640 rval = qla2x00_find_new_loop_id(base_vha,
3641 fcport);
3642 if (rval != QLA_SUCCESS) {
3643 /* Ran out of IDs to use */
3644 break;
3645 }
1da177e4 3646
b2032fd5
RD		 3647 /* Login and update database */
3648 qla2x00_fabric_dev_login(vha, fcport,
3649 &next_loopid);
3650 } else {
3651 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf079,
3652 "new port %8phC state 0x%x flags 0x%x fc4_type "
3653 "0x%x scan_state %d (initiator mode disabled; "
3654 "skipping login)\n",
3655 fcport->port_name,
3656 atomic_read(&fcport->state),
3657 fcport->flags, fcport->fc4_type,
3658 fcport->scan_state);
3659 }
e452ceb6
JC		 3660
3661 list_move_tail(&fcport->list, &vha->vp_fcports);
1da177e4
LT		 3662 }
3663 } while (0);
3664
e452ceb6
JC		 3665 /* Free all new device structures not processed. */
3666 list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) {
3667 list_del(&fcport->list);
3668 kfree(fcport);
3669 }
3670
1da177e4 3671 if (rval) {
7c3df132
SK		 3672 ql_dbg(ql_dbg_disc, vha, 0x2068,
3673 "Configure fabric error exit rval=%d.\n", rval);
1da177e4
LT		 3674 }
3675
3676 return (rval);
3677}
3678
1da177e4
LT		 3679/*
3680 * qla2x00_find_all_fabric_devs
3681 *
3682 * Input:
3683 * ha = adapter block pointer.
3684 * dev = database device entry pointer.
3685 *
3686 * Returns:
3687 * 0 = success.
3688 *
3689 * Context:
3690 * Kernel context.
3691 */
3692static int
e315cd28
AC		 3693qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha,
3694 struct list_head *new_fcports)
1da177e4
LT		 3695{
3696 int rval;
3697 uint16_t loop_id;
3698 fc_port_t *fcport, *new_fcport, *fcptemp;
3699 int found;
3700
3701 sw_info_t *swl;
3702 int swl_idx;
3703 int first_dev, last_dev;
1516ef44 3704 port_id_t wrap = {}, nxt_d_id;
e315cd28 3705 struct qla_hw_data *ha = vha->hw;
bb4cf5b7 3706 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 3707
3708 rval = QLA_SUCCESS;
3709
3710 /* Try GID_PT to get device list, else GAN. */
7a67735b 3711 if (!ha->swl)
642ef983 3712 ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t),
7a67735b
AV		 3713 GFP_KERNEL);
3714 swl = ha->swl;
bbfbbbc1 3715 if (!swl) {
1da177e4 3716 /*EMPTY*/
7c3df132
SK		 3717 ql_dbg(ql_dbg_disc, vha, 0x2054,
3718 "GID_PT allocations failed, fallback on GA_NXT.\n");
1da177e4 3719 } else {
642ef983 3720 memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t));
e315cd28 3721 if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) {
1da177e4 3722 swl = NULL;
e315cd28 3723 } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 3724 swl = NULL;
e315cd28 3725 } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 3726 swl = NULL;
e5896bd5 3727 } else if (ql2xiidmaenable &&
e315cd28
AC		 3728 qla2x00_gfpn_id(vha, swl) == QLA_SUCCESS) {
3729 qla2x00_gpsc(vha, swl);
1da177e4 3730 }
e8c72ba5
CD		 3731
3732 /* If other queries succeeded probe for FC-4 type */
3733 if (swl)
3734 qla2x00_gff_id(vha, swl);
1da177e4
LT		 3735 }
3736 swl_idx = 0;
3737
3738 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 3739 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3740 if (new_fcport == NULL) {
7c3df132
SK		 3741 ql_log(ql_log_warn, vha, 0x205e,
3742 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 3743 return (QLA_MEMORY_ALLOC_FAILED);
3744 }
3745 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
1da177e4
LT		 3746 /* Set start port ID scan at adapter ID. */
3747 first_dev = 1;
3748 last_dev = 0;
3749
3750 /* Starting free loop ID. */
e315cd28
AC		 3751 loop_id = ha->min_external_loopid;
3752 for (; loop_id <= ha->max_loop_id; loop_id++) {
3753 if (qla2x00_is_reserved_id(vha, loop_id))
1da177e4
LT		 3754 continue;
3755
3a6478df
GM		 3756 if (ha->current_topology == ISP_CFG_FL &&
3757 (atomic_read(&vha->loop_down_timer) ||
3758 LOOP_TRANSITION(vha))) {
bb2d52b2
AV		 3759 atomic_set(&vha->loop_down_timer, 0);
3760 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
3761 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
1da177e4 3762 break;
bb2d52b2 3763 }
1da177e4
LT		 3764
3765 if (swl != NULL) {
3766 if (last_dev) {
3767 wrap.b24 = new_fcport->d_id.b24;
3768 } else {
3769 new_fcport->d_id.b24 = swl[swl_idx].d_id.b24;
3770 memcpy(new_fcport->node_name,
3771 swl[swl_idx].node_name, WWN_SIZE);
3772 memcpy(new_fcport->port_name,
3773 swl[swl_idx].port_name, WWN_SIZE);
d8b45213
AV		 3774 memcpy(new_fcport->fabric_port_name,
3775 swl[swl_idx].fabric_port_name, WWN_SIZE);
3776 new_fcport->fp_speed = swl[swl_idx].fp_speed;
e8c72ba5 3777 new_fcport->fc4_type = swl[swl_idx].fc4_type;
1da177e4
LT		 3778
3779 if (swl[swl_idx].d_id.b.rsvd_1 != 0) {
3780 last_dev = 1;
3781 }
3782 swl_idx++;
3783 }
3784 } else {
3785 /* Send GA_NXT to the switch */
e315cd28 3786 rval = qla2x00_ga_nxt(vha, new_fcport);
1da177e4 3787 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3788 ql_log(ql_log_warn, vha, 0x2064,
3789 "SNS scan failed -- assuming "
3790 "zero-entry result.\n");
1da177e4
LT		 3791 list_for_each_entry_safe(fcport, fcptemp,
3792 new_fcports, list) {
3793 list_del(&fcport->list);
3794 kfree(fcport);
3795 }
3796 rval = QLA_SUCCESS;
3797 break;
3798 }
3799 }
3800
3801 /* If wrap on switch device list, exit. */
3802 if (first_dev) {
3803 wrap.b24 = new_fcport->d_id.b24;
3804 first_dev = 0;
3805 } else if (new_fcport->d_id.b24 == wrap.b24) {
7c3df132
SK		 3806 ql_dbg(ql_dbg_disc, vha, 0x2065,
3807 "Device wrap (%02x%02x%02x).\n",
3808 new_fcport->d_id.b.domain,
3809 new_fcport->d_id.b.area,
3810 new_fcport->d_id.b.al_pa);
1da177e4
LT		 3811 break;
3812 }
3813
2c3dfe3f 3814 /* Bypass if same physical adapter. */
e315cd28 3815 if (new_fcport->d_id.b24 == base_vha->d_id.b24)
1da177e4
LT		 3816 continue;
3817
2c3dfe3f 3818 /* Bypass virtual ports of the same host. */
bb4cf5b7
CD		 3819 if (qla2x00_is_a_vp_did(vha, new_fcport->d_id.b24))
3820 continue;
2c3dfe3f 3821
f7d289f6
AV		 3822 /* Bypass if same domain and area of adapter. */
3823 if (((new_fcport->d_id.b24 & 0xffff00) ==
e315cd28 3824 (vha->d_id.b24 & 0xffff00)) && ha->current_topology ==
f7d289f6
AV		 3825 ISP_CFG_FL)
3826 continue;
3827
1da177e4
LT		 3828 /* Bypass reserved domain fields. */
3829 if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0)
3830 continue;
3831
e8c72ba5 3832 /* Bypass ports whose FCP-4 type is not FCP_SCSI */
4da26e16
CD		 3833 if (ql2xgffidenable &&
3834 (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI &&
3835 new_fcport->fc4_type != FC4_TYPE_UNKNOWN))
e8c72ba5
CD		 3836 continue;
3837
1da177e4
LT		 3838 /* Locate matching device in database. */
3839 found = 0;
e315cd28 3840 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 3841 if (memcmp(new_fcport->port_name, fcport->port_name,
3842 WWN_SIZE))
3843 continue;
3844
827210ba 3845 fcport->scan_state = QLA_FCPORT_FOUND;
b3b02e6e 3846
1da177e4
LT		 3847 found++;
3848
d8b45213
AV		 3849 /* Update port state. */
3850 memcpy(fcport->fabric_port_name,
3851 new_fcport->fabric_port_name, WWN_SIZE);
3852 fcport->fp_speed = new_fcport->fp_speed;
3853
1da177e4 3854 /*
b2032fd5
RD		 3855 * If address the same and state FCS_ONLINE
3856 * (or in target mode), nothing changed.
1da177e4
LT		 3857 */
3858 if (fcport->d_id.b24 == new_fcport->d_id.b24 &&
b2032fd5
RD		 3859 (atomic_read(&fcport->state) == FCS_ONLINE ||
3860 !qla_ini_mode_enabled(base_vha))) {
1da177e4
LT		 3861 break;
3862 }
3863
3864 /*
3865 * If device was not a fabric device before.
3866 */
3867 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) {
3868 fcport->d_id.b24 = new_fcport->d_id.b24;
5f16b331 3869 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 3870 fcport->flags |= (FCF_FABRIC_DEVICE |
3871 FCF_LOGIN_NEEDED);
1da177e4
LT		 3872 break;
3873 }
3874
3875 /*
3876 * Port ID changed or device was marked to be updated;
3877 * Log it out if still logged in and mark it for
3878 * relogin later.
3879 */
b2032fd5
RD		 3880 if (!qla_ini_mode_enabled(base_vha)) {
3881 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf080,
3882 "port changed FC ID, %8phC"
3883 " old %x:%x:%x (loop_id 0x%04x)-> new %x:%x:%x\n",
3884 fcport->port_name,
3885 fcport->d_id.b.domain,
3886 fcport->d_id.b.area,
3887 fcport->d_id.b.al_pa,
3888 fcport->loop_id,
3889 new_fcport->d_id.b.domain,
3890 new_fcport->d_id.b.area,
3891 new_fcport->d_id.b.al_pa);
3892 fcport->d_id.b24 = new_fcport->d_id.b24;
3893 break;
3894 }
3895
1da177e4
LT		 3896 fcport->d_id.b24 = new_fcport->d_id.b24;
3897 fcport->flags |= FCF_LOGIN_NEEDED;
3898 if (fcport->loop_id != FC_NO_LOOP_ID &&
f08b7251 3899 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
0eba25df 3900 (fcport->flags & FCF_ASYNC_SENT) == 0 &&
1da177e4
LT		 3901 fcport->port_type != FCT_INITIATOR &&
3902 fcport->port_type != FCT_BROADCAST) {
e315cd28 3903 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3904 fcport->d_id.b.domain, fcport->d_id.b.area,
3905 fcport->d_id.b.al_pa);
5f16b331 3906 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 3907 }
3908
3909 break;
3910 }
3911
3912 if (found)
3913 continue;
1da177e4 3914 /* If device was not in our fcports list, then add it. */
b2032fd5 3915 new_fcport->scan_state = QLA_FCPORT_FOUND;
1da177e4
LT		 3916 list_add_tail(&new_fcport->list, new_fcports);
3917
3918 /* Allocate a new replacement fcport. */
3919 nxt_d_id.b24 = new_fcport->d_id.b24;
e315cd28 3920 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3921 if (new_fcport == NULL) {
7c3df132
SK		 3922 ql_log(ql_log_warn, vha, 0x2066,
3923 "Memory allocation failed for fcport.\n");
1da177e4
LT		 3924 return (QLA_MEMORY_ALLOC_FAILED);
3925 }
3926 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
3927 new_fcport->d_id.b24 = nxt_d_id.b24;
3928 }
3929
c9475cb0 3930 kfree(new_fcport);
1da177e4 3931
1da177e4
LT		 3932 return (rval);
3933}
3934
3935/*
3936 * qla2x00_find_new_loop_id
3937 * Scan through our port list and find a new usable loop ID.
3938 *
3939 * Input:
3940 * ha: adapter state pointer.
3941 * dev: port structure pointer.
3942 *
3943 * Returns:
3944 * qla2x00 local function return status code.
3945 *
3946 * Context:
3947 * Kernel context.
3948 */
03bcfb57 3949int
e315cd28 3950qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
1da177e4
LT		 3951{
3952 int rval;
e315cd28 3953 struct qla_hw_data *ha = vha->hw;
feafb7b1 3954 unsigned long flags = 0;
1da177e4
LT		 3955
3956 rval = QLA_SUCCESS;
3957
5f16b331 3958 spin_lock_irqsave(&ha->vport_slock, flags);
1da177e4 3959
5f16b331
CD		 3960 dev->loop_id = find_first_zero_bit(ha->loop_id_map,
3961 LOOPID_MAP_SIZE);
3962 if (dev->loop_id >= LOOPID_MAP_SIZE ||
3963 qla2x00_is_reserved_id(vha, dev->loop_id)) {
3964 dev->loop_id = FC_NO_LOOP_ID;
3965 rval = QLA_FUNCTION_FAILED;
3966 } else
3967 set_bit(dev->loop_id, ha->loop_id_map);
1da177e4 3968
5f16b331 3969 spin_unlock_irqrestore(&ha->vport_slock, flags);
1da177e4 3970
5f16b331
CD		 3971 if (rval == QLA_SUCCESS)
3972 ql_dbg(ql_dbg_disc, dev->vha, 0x2086,
3973 "Assigning new loopid=%x, portid=%x.\n",
3974 dev->loop_id, dev->d_id.b24);
3975 else
3976 ql_log(ql_log_warn, dev->vha, 0x2087,
3977 "No loop_id's available, portid=%x.\n",
3978 dev->d_id.b24);
1da177e4
LT		 3979
3980 return (rval);
3981}
3982
1da177e4
LT		 3983/*
3984 * qla2x00_fabric_dev_login
3985 * Login fabric target device and update FC port database.
3986 *
3987 * Input:
3988 * ha: adapter state pointer.
3989 * fcport: port structure list pointer.
3990 * next_loopid: contains value of a new loop ID that can be used
3991 * by the next login attempt.
3992 *
3993 * Returns:
3994 * qla2x00 local function return status code.
3995 *
3996 * Context:
3997 * Kernel context.
3998 */
3999static int
e315cd28 4000qla2x00_fabric_dev_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 4001 uint16_t *next_loopid)
4002{
4003 int rval;
0107109e 4004 uint8_t opts;
e315cd28 4005 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 4006
4007 rval = QLA_SUCCESS;
1da177e4 4008
ac280b67 4009 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584
AV		 4010 if (fcport->flags & FCF_ASYNC_SENT)
4011 return rval;
4012 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 4013 rval = qla2x00_post_async_login_work(vha, fcport, NULL);
4014 if (!rval)
4015 return rval;
4016 }
4017
5ff1d584 4018 fcport->flags &= ~FCF_ASYNC_SENT;
e315cd28 4019 rval = qla2x00_fabric_login(vha, fcport, next_loopid);
1da177e4 4020 if (rval == QLA_SUCCESS) {
f08b7251 4021 /* Send an ADISC to FCP2 devices.*/
0107109e 4022 opts = 0;
f08b7251 4023 if (fcport->flags & FCF_FCP2_DEVICE)
0107109e 4024 opts |= BIT_1;
e315cd28 4025 rval = qla2x00_get_port_database(vha, fcport, opts);
1da177e4 4026 if (rval != QLA_SUCCESS) {
e315cd28 4027 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 4028 fcport->d_id.b.domain, fcport->d_id.b.area,
4029 fcport->d_id.b.al_pa);
e315cd28 4030 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4 4031 } else {
e315cd28 4032 qla2x00_update_fcport(vha, fcport);
1da177e4 4033 }
0b91d116
CD		 4034 } else {
4035 /* Retry Login. */
4036 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 4037 }
4038
4039 return (rval);
4040}
4041
4042/*
4043 * qla2x00_fabric_login
4044 * Issue fabric login command.
4045 *
4046 * Input:
4047 * ha = adapter block pointer.
4048 * device = pointer to FC device type structure.
4049 *
4050 * Returns:
4051 * 0 - Login successfully
4052 * 1 - Login failed
4053 * 2 - Initiator device
4054 * 3 - Fatal error
4055 */
4056int
e315cd28 4057qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 4058 uint16_t *next_loopid)
4059{
4060 int rval;
4061 int retry;
4062 uint16_t tmp_loopid;
4063 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 4064 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 4065
4066 retry = 0;
4067 tmp_loopid = 0;
4068
4069 for (;;) {
7c3df132
SK		 4070 ql_dbg(ql_dbg_disc, vha, 0x2000,
4071 "Trying Fabric Login w/loop id 0x%04x for port "
4072 "%02x%02x%02x.\n",
4073 fcport->loop_id, fcport->d_id.b.domain,
4074 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 4075
4076 /* Login fcport on switch. */
0b91d116 4077 rval = ha->isp_ops->fabric_login(vha, fcport->loop_id,
1da177e4
LT		 4078 fcport->d_id.b.domain, fcport->d_id.b.area,
4079 fcport->d_id.b.al_pa, mb, BIT_0);
0b91d116
CD		 4080 if (rval != QLA_SUCCESS) {
4081 return rval;
4082 }
1da177e4
LT		 4083 if (mb[0] == MBS_PORT_ID_USED) {
4084 /*
4085 * Device has another loop ID. The firmware team
0107109e
AV		 4086 * recommends the driver perform an implicit login with
4087 * the specified ID again. The ID we just used is save
4088 * here so we return with an ID that can be tried by
4089 * the next login.
1da177e4
LT		 4090 */
4091 retry++;
4092 tmp_loopid = fcport->loop_id;
4093 fcport->loop_id = mb[1];
4094
7c3df132
SK		 4095 ql_dbg(ql_dbg_disc, vha, 0x2001,
4096 "Fabric Login: port in use - next loop "
4097 "id=0x%04x, port id= %02x%02x%02x.\n",
1da177e4 4098 fcport->loop_id, fcport->d_id.b.domain,
7c3df132 4099 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 4100
4101 } else if (mb[0] == MBS_COMMAND_COMPLETE) {
4102 /*
4103 * Login succeeded.
4104 */
4105 if (retry) {
4106 /* A retry occurred before. */
4107 *next_loopid = tmp_loopid;
4108 } else {
4109 /*
4110 * No retry occurred before. Just increment the
4111 * ID value for next login.
4112 */
4113 *next_loopid = (fcport->loop_id + 1);
4114 }
4115
4116 if (mb[1] & BIT_0) {
4117 fcport->port_type = FCT_INITIATOR;
4118 } else {
4119 fcport->port_type = FCT_TARGET;
4120 if (mb[1] & BIT_1) {
8474f3a0 4121 fcport->flags |= FCF_FCP2_DEVICE;
1da177e4
LT		 4122 }
4123 }
4124
ad3e0eda
AV		 4125 if (mb[10] & BIT_0)
4126 fcport->supported_classes |= FC_COS_CLASS2;
4127 if (mb[10] & BIT_1)
4128 fcport->supported_classes |= FC_COS_CLASS3;
4129
2d70c103
NB		 4130 if (IS_FWI2_CAPABLE(ha)) {
4131 if (mb[10] & BIT_7)
4132 fcport->flags |=
4133 FCF_CONF_COMP_SUPPORTED;
4134 }
4135
1da177e4
LT		 4136 rval = QLA_SUCCESS;
4137 break;
4138 } else if (mb[0] == MBS_LOOP_ID_USED) {
4139 /*
4140 * Loop ID already used, try next loop ID.
4141 */
4142 fcport->loop_id++;
e315cd28 4143 rval = qla2x00_find_new_loop_id(vha, fcport);
1da177e4
LT		 4144 if (rval != QLA_SUCCESS) {
4145 /* Ran out of loop IDs to use */
4146 break;
4147 }
4148 } else if (mb[0] == MBS_COMMAND_ERROR) {
4149 /*
4150 * Firmware possibly timed out during login. If NO
4151 * retries are left to do then the device is declared
4152 * dead.
4153 */
4154 *next_loopid = fcport->loop_id;
e315cd28 4155 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 4156 fcport->d_id.b.domain, fcport->d_id.b.area,
4157 fcport->d_id.b.al_pa);
e315cd28 4158 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 4159
4160 rval = 1;
4161 break;
4162 } else {
4163 /*
4164 * unrecoverable / not handled error
4165 */
7c3df132
SK		 4166 ql_dbg(ql_dbg_disc, vha, 0x2002,
4167 "Failed=%x port_id=%02x%02x%02x loop_id=%x "
4168 "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain,
4169 fcport->d_id.b.area, fcport->d_id.b.al_pa,
4170 fcport->loop_id, jiffies);
1da177e4
LT		 4171
4172 *next_loopid = fcport->loop_id;
e315cd28 4173 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 4174 fcport->d_id.b.domain, fcport->d_id.b.area,
4175 fcport->d_id.b.al_pa);
5f16b331 4176 qla2x00_clear_loop_id(fcport);
0eedfcf0 4177 fcport->login_retry = 0;
1da177e4
LT		 4178
4179 rval = 3;
4180 break;
4181 }
4182 }
4183
4184 return (rval);
4185}
4186
4187/*
4188 * qla2x00_local_device_login
4189 * Issue local device login command.
4190 *
4191 * Input:
4192 * ha = adapter block pointer.
4193 * loop_id = loop id of device to login to.
4194 *
4195 * Returns (Where's the #define!!!!):
4196 * 0 - Login successfully
4197 * 1 - Login failed
4198 * 3 - Fatal error
4199 */
4200int
e315cd28 4201qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport)
1da177e4
LT		 4202{
4203 int rval;
4204 uint16_t mb[MAILBOX_REGISTER_COUNT];
4205
4206 memset(mb, 0, sizeof(mb));
e315cd28 4207 rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0);
1da177e4
LT		 4208 if (rval == QLA_SUCCESS) {
4209 /* Interrogate mailbox registers for any errors */
4210 if (mb[0] == MBS_COMMAND_ERROR)
4211 rval = 1;
4212 else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR)
4213 /* device not in PCB table */
4214 rval = 3;
4215 }
4216
4217 return (rval);
4218}
4219
4220/*
4221 * qla2x00_loop_resync
4222 * Resync with fibre channel devices.
4223 *
4224 * Input:
4225 * ha = adapter block pointer.
4226 *
4227 * Returns:
4228 * 0 = success
4229 */
4230int
e315cd28 4231qla2x00_loop_resync(scsi_qla_host_t *vha)
1da177e4 4232{
73208dfd 4233 int rval = QLA_SUCCESS;
1da177e4 4234 uint32_t wait_time;
67c2e93a
AC		 4235 struct req_que *req;
4236 struct rsp_que *rsp;
4237
d7459527 4238 req = vha->req;
67c2e93a 4239 rsp = req->rsp;
1da177e4 4240
e315cd28
AC		 4241 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
4242 if (vha->flags.online) {
4243 if (!(rval = qla2x00_fw_ready(vha))) {
1da177e4
LT		 4244 /* Wait at most MAX_TARGET RSCNs for a stable link. */
4245 wait_time = 256;
4246 do {
8ae6d9c7
GM		 4247 if (!IS_QLAFX00(vha->hw)) {
4248 /*
4249 * Issue a marker after FW becomes
4250 * ready.
4251 */
4252 qla2x00_marker(vha, req, rsp, 0, 0,
4253 MK_SYNC_ALL);
4254 vha->marker_needed = 0;
4255 }
1da177e4
LT		 4256
4257 /* Remap devices on Loop. */
e315cd28 4258 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4 4259
8ae6d9c7
GM		 4260 if (IS_QLAFX00(vha->hw))
4261 qlafx00_configure_devices(vha);
4262 else
4263 qla2x00_configure_loop(vha);
4264
1da177e4 4265 wait_time--;
e315cd28
AC		 4266 } while (!atomic_read(&vha->loop_down_timer) &&
4267 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
4268 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
4269 &vha->dpc_flags)));
1da177e4 4270 }
1da177e4
LT		 4271 }
4272
e315cd28 4273 if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
1da177e4 4274 return (QLA_FUNCTION_FAILED);
1da177e4 4275
e315cd28 4276 if (rval)
7c3df132
SK		 4277 ql_dbg(ql_dbg_disc, vha, 0x206c,
4278 "%s *** FAILED ***.\n", __func__);
1da177e4
LT		 4279
4280 return (rval);
4281}
4282
579d12b5
SK		 4283/*
4284* qla2x00_perform_loop_resync
4285* Description: This function will set the appropriate flags and call
4286* qla2x00_loop_resync. If successful loop will be resynced
4287* Arguments : scsi_qla_host_t pointer
4288* returm : Success or Failure
4289*/
4290
4291int qla2x00_perform_loop_resync(scsi_qla_host_t *ha)
4292{
4293 int32_t rval = 0;
4294
4295 if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) {
4296 /*Configure the flags so that resync happens properly*/
4297 atomic_set(&ha->loop_down_timer, 0);
4298 if (!(ha->device_flags & DFLG_NO_CABLE)) {
4299 atomic_set(&ha->loop_state, LOOP_UP);
4300 set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags);
4301 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
4302 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
4303
4304 rval = qla2x00_loop_resync(ha);
4305 } else
4306 atomic_set(&ha->loop_state, LOOP_DEAD);
4307
4308 clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags);
4309 }
4310
4311 return rval;
4312}
4313
d97994dc 4314void
67becc00 4315qla2x00_update_fcports(scsi_qla_host_t *base_vha)
d97994dc
AV		 4316{
4317 fc_port_t *fcport;
feafb7b1
AE		 4318 struct scsi_qla_host *vha;
4319 struct qla_hw_data *ha = base_vha->hw;
4320 unsigned long flags;
d97994dc 4321
feafb7b1 4322 spin_lock_irqsave(&ha->vport_slock, flags);
d97994dc 4323 /* Go with deferred removal of rport references. */
feafb7b1
AE		 4324 list_for_each_entry(vha, &base_vha->hw->vp_list, list) {
4325 atomic_inc(&vha->vref_count);
4326 list_for_each_entry(fcport, &vha->vp_fcports, list) {
8ae598d0 4327 if (fcport->drport &&
feafb7b1
AE		 4328 atomic_read(&fcport->state) != FCS_UNCONFIGURED) {
4329 spin_unlock_irqrestore(&ha->vport_slock, flags);
67becc00 4330 qla2x00_rport_del(fcport);
df673274
AP		 4331
4332 /*
4333 * Release the target mode FC NEXUS in
4334 * qla_target.c, if target mod is enabled.
4335 */
4336 qlt_fc_port_deleted(vha, fcport,
4337 base_vha->total_fcport_update_gen);
4338
feafb7b1
AE		 4339 spin_lock_irqsave(&ha->vport_slock, flags);
4340 }
4341 }
4342 atomic_dec(&vha->vref_count);
4343 }
4344 spin_unlock_irqrestore(&ha->vport_slock, flags);
d97994dc
AV		 4345}
4346
7d613ac6
SV		 4347/* Assumes idc_lock always held on entry */
4348void
4349qla83xx_reset_ownership(scsi_qla_host_t *vha)
4350{
4351 struct qla_hw_data *ha = vha->hw;
4352 uint32_t drv_presence, drv_presence_mask;
4353 uint32_t dev_part_info1, dev_part_info2, class_type;
4354 uint32_t class_type_mask = 0x3;
4355 uint16_t fcoe_other_function = 0xffff, i;
4356
7ec0effd
AD		 4357 if (IS_QLA8044(ha)) {
4358 drv_presence = qla8044_rd_direct(vha,
4359 QLA8044_CRB_DRV_ACTIVE_INDEX);
4360 dev_part_info1 = qla8044_rd_direct(vha,
4361 QLA8044_CRB_DEV_PART_INFO_INDEX);
4362 dev_part_info2 = qla8044_rd_direct(vha,
4363 QLA8044_CRB_DEV_PART_INFO2);
4364 } else {
4365 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4366 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1);
4367 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2);
4368 }
7d613ac6
SV		 4369 for (i = 0; i < 8; i++) {
4370 class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask);
4371 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
4372 (i != ha->portnum)) {
4373 fcoe_other_function = i;
4374 break;
4375 }
4376 }
4377 if (fcoe_other_function == 0xffff) {
4378 for (i = 0; i < 8; i++) {
4379 class_type = ((dev_part_info2 >> (i * 4)) &
4380 class_type_mask);
4381 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
4382 ((i + 8) != ha->portnum)) {
4383 fcoe_other_function = i + 8;
4384 break;
4385 }
4386 }
4387 }
4388 /*
4389 * Prepare drv-presence mask based on fcoe functions present.
4390 * However consider only valid physical fcoe function numbers (0-15).
4391 */
4392 drv_presence_mask = ~((1 << (ha->portnum)) |
4393 ((fcoe_other_function == 0xffff) ?
4394 0 : (1 << (fcoe_other_function))));
4395
4396 /* We are the reset owner iff:
4397 * - No other protocol drivers present.
4398 * - This is the lowest among fcoe functions. */
4399 if (!(drv_presence & drv_presence_mask) &&
4400 (ha->portnum < fcoe_other_function)) {
4401 ql_dbg(ql_dbg_p3p, vha, 0xb07f,
4402 "This host is Reset owner.\n");
4403 ha->flags.nic_core_reset_owner = 1;
4404 }
4405}
4406
fa492630 4407static int
7d613ac6
SV		 4408__qla83xx_set_drv_ack(scsi_qla_host_t *vha)
4409{
4410 int rval = QLA_SUCCESS;
4411 struct qla_hw_data *ha = vha->hw;
4412 uint32_t drv_ack;
4413
4414 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4415 if (rval == QLA_SUCCESS) {
4416 drv_ack |= (1 << ha->portnum);
4417 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
4418 }
4419
4420 return rval;
4421}
4422
fa492630 4423static int
7d613ac6
SV		 4424__qla83xx_clear_drv_ack(scsi_qla_host_t *vha)
4425{
4426 int rval = QLA_SUCCESS;
4427 struct qla_hw_data *ha = vha->hw;
4428 uint32_t drv_ack;
4429
4430 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4431 if (rval == QLA_SUCCESS) {
4432 drv_ack &= ~(1 << ha->portnum);
4433 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
4434 }
4435
4436 return rval;
4437}
4438
fa492630 4439static const char *
7d613ac6
SV		 4440qla83xx_dev_state_to_string(uint32_t dev_state)
4441{
4442 switch (dev_state) {
4443 case QLA8XXX_DEV_COLD:
4444 return "COLD/RE-INIT";
4445 case QLA8XXX_DEV_INITIALIZING:
4446 return "INITIALIZING";
4447 case QLA8XXX_DEV_READY:
4448 return "READY";
4449 case QLA8XXX_DEV_NEED_RESET:
4450 return "NEED RESET";
4451 case QLA8XXX_DEV_NEED_QUIESCENT:
4452 return "NEED QUIESCENT";
4453 case QLA8XXX_DEV_FAILED:
4454 return "FAILED";
4455 case QLA8XXX_DEV_QUIESCENT:
4456 return "QUIESCENT";
4457 default:
4458 return "Unknown";
4459 }
4460}
4461
4462/* Assumes idc-lock always held on entry */
4463void
4464qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type)
4465{
4466 struct qla_hw_data *ha = vha->hw;
4467 uint32_t idc_audit_reg = 0, duration_secs = 0;
4468
4469 switch (audit_type) {
4470 case IDC_AUDIT_TIMESTAMP:
4471 ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000);
4472 idc_audit_reg = (ha->portnum) |
4473 (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8);
4474 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
4475 break;
4476
4477 case IDC_AUDIT_COMPLETION:
4478 duration_secs = ((jiffies_to_msecs(jiffies) -
4479 jiffies_to_msecs(ha->idc_audit_ts)) / 1000);
4480 idc_audit_reg = (ha->portnum) |
4481 (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8);
4482 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
4483 break;
4484
4485 default:
4486 ql_log(ql_log_warn, vha, 0xb078,
4487 "Invalid audit type specified.\n");
4488 break;
4489 }
4490}
4491
4492/* Assumes idc_lock always held on entry */
fa492630 4493static int
7d613ac6
SV		 4494qla83xx_initiating_reset(scsi_qla_host_t *vha)
4495{
4496 struct qla_hw_data *ha = vha->hw;
4497 uint32_t idc_control, dev_state;
4498
4499 __qla83xx_get_idc_control(vha, &idc_control);
4500 if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) {
4501 ql_log(ql_log_info, vha, 0xb080,
4502 "NIC Core reset has been disabled. idc-control=0x%x\n",
4503 idc_control);
4504 return QLA_FUNCTION_FAILED;
4505 }
4506
4507 /* Set NEED-RESET iff in READY state and we are the reset-owner */
4508 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4509 if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) {
4510 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
4511 QLA8XXX_DEV_NEED_RESET);
4512 ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n");
4513 qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP);
4514 } else {
4515 const char *state = qla83xx_dev_state_to_string(dev_state);
4516 ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n", state);
4517
4518 /* SV: XXX: Is timeout required here? */
4519 /* Wait for IDC state change READY -> NEED_RESET */
4520 while (dev_state == QLA8XXX_DEV_READY) {
4521 qla83xx_idc_unlock(vha, 0);
4522 msleep(200);
4523 qla83xx_idc_lock(vha, 0);
4524 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4525 }
4526 }
4527
4528 /* Send IDC ack by writing to drv-ack register */
4529 __qla83xx_set_drv_ack(vha);
4530
4531 return QLA_SUCCESS;
4532}
4533
4534int
4535__qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control)
4536{
4537 return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
4538}
4539
7d613ac6
SV		 4540int
4541__qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control)
4542{
4543 return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
4544}
4545
fa492630 4546static int
7d613ac6
SV		 4547qla83xx_check_driver_presence(scsi_qla_host_t *vha)
4548{
4549 uint32_t drv_presence = 0;
4550 struct qla_hw_data *ha = vha->hw;
4551
4552 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4553 if (drv_presence & (1 << ha->portnum))
4554 return QLA_SUCCESS;
4555 else
4556 return QLA_TEST_FAILED;
4557}
4558
4559int
4560qla83xx_nic_core_reset(scsi_qla_host_t *vha)
4561{
4562 int rval = QLA_SUCCESS;
4563 struct qla_hw_data *ha = vha->hw;
4564
4565 ql_dbg(ql_dbg_p3p, vha, 0xb058,
4566 "Entered %s().\n", __func__);
4567
4568 if (vha->device_flags & DFLG_DEV_FAILED) {
4569 ql_log(ql_log_warn, vha, 0xb059,
4570 "Device in unrecoverable FAILED state.\n");
4571 return QLA_FUNCTION_FAILED;
4572 }
4573
4574 qla83xx_idc_lock(vha, 0);
4575
4576 if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) {
4577 ql_log(ql_log_warn, vha, 0xb05a,
4578 "Function=0x%x has been removed from IDC participation.\n",
4579 ha->portnum);
4580 rval = QLA_FUNCTION_FAILED;
4581 goto exit;
4582 }
4583
4584 qla83xx_reset_ownership(vha);
4585
4586 rval = qla83xx_initiating_reset(vha);
4587
4588 /*
4589 * Perform reset if we are the reset-owner,
4590 * else wait till IDC state changes to READY/FAILED.
4591 */
4592 if (rval == QLA_SUCCESS) {
4593 rval = qla83xx_idc_state_handler(vha);
4594
4595 if (rval == QLA_SUCCESS)
4596 ha->flags.nic_core_hung = 0;
4597 __qla83xx_clear_drv_ack(vha);
4598 }
4599
4600exit:
4601 qla83xx_idc_unlock(vha, 0);
4602
4603 ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__);
4604
4605 return rval;
4606}
4607
81178772
SK		 4608int
4609qla2xxx_mctp_dump(scsi_qla_host_t *vha)
4610{
4611 struct qla_hw_data *ha = vha->hw;
4612 int rval = QLA_FUNCTION_FAILED;
4613
4614 if (!IS_MCTP_CAPABLE(ha)) {
4615 /* This message can be removed from the final version */
4616 ql_log(ql_log_info, vha, 0x506d,
4617 "This board is not MCTP capable\n");
4618 return rval;
4619 }
4620
4621 if (!ha->mctp_dump) {
4622 ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev,
4623 MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL);
4624
4625 if (!ha->mctp_dump) {
4626 ql_log(ql_log_warn, vha, 0x506e,
4627 "Failed to allocate memory for mctp dump\n");
4628 return rval;
4629 }
4630 }
4631
4632#define MCTP_DUMP_STR_ADDR 0x00000000
4633 rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma,
4634 MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4);
4635 if (rval != QLA_SUCCESS) {
4636 ql_log(ql_log_warn, vha, 0x506f,
4637 "Failed to capture mctp dump\n");
4638 } else {
4639 ql_log(ql_log_info, vha, 0x5070,
4640 "Mctp dump capture for host (%ld/%p).\n",
4641 vha->host_no, ha->mctp_dump);
4642 ha->mctp_dumped = 1;
4643 }
4644
409ee0fe 4645 if (!ha->flags.nic_core_reset_hdlr_active && !ha->portnum) {
81178772
SK		 4646 ha->flags.nic_core_reset_hdlr_active = 1;
4647 rval = qla83xx_restart_nic_firmware(vha);
4648 if (rval)
4649 /* NIC Core reset failed. */
4650 ql_log(ql_log_warn, vha, 0x5071,
4651 "Failed to restart nic firmware\n");
4652 else
4653 ql_dbg(ql_dbg_p3p, vha, 0xb084,
4654 "Restarted NIC firmware successfully.\n");
4655 ha->flags.nic_core_reset_hdlr_active = 0;
4656 }
4657
4658 return rval;
4659
4660}
4661
579d12b5 4662/*
8fcd6b8b 4663* qla2x00_quiesce_io
579d12b5
SK		 4664* Description: This function will block the new I/Os
4665* Its not aborting any I/Os as context
4666* is not destroyed during quiescence
4667* Arguments: scsi_qla_host_t
4668* return : void
4669*/
4670void
8fcd6b8b 4671qla2x00_quiesce_io(scsi_qla_host_t *vha)
579d12b5
SK		 4672{
4673 struct qla_hw_data *ha = vha->hw;
4674 struct scsi_qla_host *vp;
4675
8fcd6b8b
CD		 4676 ql_dbg(ql_dbg_dpc, vha, 0x401d,
4677 "Quiescing I/O - ha=%p.\n", ha);
579d12b5
SK		 4678
4679 atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME);
4680 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
4681 atomic_set(&vha->loop_state, LOOP_DOWN);
4682 qla2x00_mark_all_devices_lost(vha, 0);
4683 list_for_each_entry(vp, &ha->vp_list, list)
8fcd6b8b 4684 qla2x00_mark_all_devices_lost(vp, 0);
579d12b5
SK		 4685 } else {
4686 if (!atomic_read(&vha->loop_down_timer))
4687 atomic_set(&vha->loop_down_timer,
4688 LOOP_DOWN_TIME);
4689 }
4690 /* Wait for pending cmds to complete */
4691 qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST);
4692}
4693
a9083016
GM		 4694void
4695qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
4696{
4697 struct qla_hw_data *ha = vha->hw;
579d12b5 4698 struct scsi_qla_host *vp;
feafb7b1 4699 unsigned long flags;
6aef87be 4700 fc_port_t *fcport;
a9083016 4701
e46ef004
SK		 4702 /* For ISP82XX, driver waits for completion of the commands.
4703 * online flag should be set.
4704 */
7ec0effd 4705 if (!(IS_P3P_TYPE(ha)))
e46ef004 4706 vha->flags.online = 0;
a9083016
GM		 4707 ha->flags.chip_reset_done = 0;
4708 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2be21fa2 4709 vha->qla_stats.total_isp_aborts++;
a9083016 4710
7c3df132
SK		 4711 ql_log(ql_log_info, vha, 0x00af,
4712 "Performing ISP error recovery - ha=%p.\n", ha);
a9083016 4713
e46ef004
SK		 4714 /* For ISP82XX, reset_chip is just disabling interrupts.
4715 * Driver waits for the completion of the commands.
4716 * the interrupts need to be enabled.
4717 */
7ec0effd 4718 if (!(IS_P3P_TYPE(ha)))
a9083016
GM		 4719 ha->isp_ops->reset_chip(vha);
4720
4721 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
4722 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
4723 atomic_set(&vha->loop_state, LOOP_DOWN);
4724 qla2x00_mark_all_devices_lost(vha, 0);
feafb7b1
AE		 4725
4726 spin_lock_irqsave(&ha->vport_slock, flags);
579d12b5 4727 list_for_each_entry(vp, &ha->vp_list, list) {
feafb7b1
AE		 4728 atomic_inc(&vp->vref_count);
4729 spin_unlock_irqrestore(&ha->vport_slock, flags);
4730
a9083016 4731 qla2x00_mark_all_devices_lost(vp, 0);
feafb7b1
AE		 4732
4733 spin_lock_irqsave(&ha->vport_slock, flags);
4734 atomic_dec(&vp->vref_count);
4735 }
4736 spin_unlock_irqrestore(&ha->vport_slock, flags);
a9083016
GM		 4737 } else {
4738 if (!atomic_read(&vha->loop_down_timer))
4739 atomic_set(&vha->loop_down_timer,
4740 LOOP_DOWN_TIME);
4741 }
4742
6aef87be
AV		 4743 /* Clear all async request states across all VPs. */
4744 list_for_each_entry(fcport, &vha->vp_fcports, list)
4745 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
4746 spin_lock_irqsave(&ha->vport_slock, flags);
4747 list_for_each_entry(vp, &ha->vp_list, list) {
4748 atomic_inc(&vp->vref_count);
4749 spin_unlock_irqrestore(&ha->vport_slock, flags);
4750
4751 list_for_each_entry(fcport, &vp->vp_fcports, list)
4752 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
4753
4754 spin_lock_irqsave(&ha->vport_slock, flags);
4755 atomic_dec(&vp->vref_count);
4756 }
4757 spin_unlock_irqrestore(&ha->vport_slock, flags);
4758
bddd2d65
LC		 4759 if (!ha->flags.eeh_busy) {
4760 /* Make sure for ISP 82XX IO DMA is complete */
7ec0effd 4761 if (IS_P3P_TYPE(ha)) {
7190575f 4762 qla82xx_chip_reset_cleanup(vha);
7c3df132
SK		 4763 ql_log(ql_log_info, vha, 0x00b4,
4764 "Done chip reset cleanup.\n");
a9083016 4765
e46ef004
SK		 4766 /* Done waiting for pending commands.
4767 * Reset the online flag.
4768 */
4769 vha->flags.online = 0;
4d78c973 4770 }
a9083016 4771
bddd2d65
LC		 4772 /* Requeue all commands in outstanding command list. */
4773 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
4774 }
b6a029e1
AE		 4775
4776 ha->chip_reset++;
4777 /* memory barrier */
4778 wmb();
a9083016
GM		 4779}
4780
1da177e4
LT		 4781/*
4782* qla2x00_abort_isp
4783* Resets ISP and aborts all outstanding commands.
4784*
4785* Input:
4786* ha = adapter block pointer.
4787*
4788* Returns:
4789* 0 = success
4790*/
4791int
e315cd28 4792qla2x00_abort_isp(scsi_qla_host_t *vha)
1da177e4 4793{
476e8978 4794 int rval;
1da177e4 4795 uint8_t status = 0;
e315cd28
AC		 4796 struct qla_hw_data *ha = vha->hw;
4797 struct scsi_qla_host *vp;
73208dfd 4798 struct req_que *req = ha->req_q_map[0];
feafb7b1 4799 unsigned long flags;
1da177e4 4800
e315cd28 4801 if (vha->flags.online) {
a9083016 4802 qla2x00_abort_isp_cleanup(vha);
1da177e4 4803
a6171297
SV		 4804 if (IS_QLA8031(ha)) {
4805 ql_dbg(ql_dbg_p3p, vha, 0xb05c,
4806 "Clearing fcoe driver presence.\n");
4807 if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS)
4808 ql_dbg(ql_dbg_p3p, vha, 0xb073,
4809 "Error while clearing DRV-Presence.\n");
4810 }
4811
85880801
AV		 4812 if (unlikely(pci_channel_offline(ha->pdev) &&
4813 ha->flags.pci_channel_io_perm_failure)) {
4814 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
4815 status = 0;
4816 return status;
4817 }
4818
73208dfd 4819 ha->isp_ops->get_flash_version(vha, req->ring);
30c47662 4820
e315cd28 4821 ha->isp_ops->nvram_config(vha);
1da177e4 4822
e315cd28
AC		 4823 if (!qla2x00_restart_isp(vha)) {
4824 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4 4825
e315cd28 4826 if (!atomic_read(&vha->loop_down_timer)) {
1da177e4
LT		 4827 /*
4828 * Issue marker command only when we are going
4829 * to start the I/O .
4830 */
e315cd28 4831 vha->marker_needed = 1;
1da177e4
LT		 4832 }
4833
e315cd28 4834 vha->flags.online = 1;
1da177e4 4835
fd34f556 4836 ha->isp_ops->enable_intrs(ha);
1da177e4 4837
fa2a1ce5 4838 ha->isp_abort_cnt = 0;
e315cd28 4839 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
476e8978 4840
6246b8a1
GM		 4841 if (IS_QLA81XX(ha) || IS_QLA8031(ha))
4842 qla2x00_get_fw_version(vha);
df613b96
AV		 4843 if (ha->fce) {
4844 ha->flags.fce_enabled = 1;
4845 memset(ha->fce, 0,
4846 fce_calc_size(ha->fce_bufs));
e315cd28 4847 rval = qla2x00_enable_fce_trace(vha,
df613b96
AV		 4848 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
4849 &ha->fce_bufs);
4850 if (rval) {
7c3df132 4851 ql_log(ql_log_warn, vha, 0x8033,
df613b96
AV		 4852 "Unable to reinitialize FCE "
4853 "(%d).\n", rval);
4854 ha->flags.fce_enabled = 0;
4855 }
4856 }
436a7b11
AV		 4857
4858 if (ha->eft) {
4859 memset(ha->eft, 0, EFT_SIZE);
e315cd28 4860 rval = qla2x00_enable_eft_trace(vha,
436a7b11
AV		 4861 ha->eft_dma, EFT_NUM_BUFFERS);
4862 if (rval) {
7c3df132 4863 ql_log(ql_log_warn, vha, 0x8034,
436a7b11
AV		 4864 "Unable to reinitialize EFT "
4865 "(%d).\n", rval);
4866 }
4867 }
1da177e4 4868 } else { /* failed the ISP abort */
e315cd28
AC		 4869 vha->flags.online = 1;
4870 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
1da177e4 4871 if (ha->isp_abort_cnt == 0) {
7c3df132
SK		 4872 ql_log(ql_log_fatal, vha, 0x8035,
4873 "ISP error recover failed - "
4874 "board disabled.\n");
fa2a1ce5 4875 /*
1da177e4
LT		 4876 * The next call disables the board
4877 * completely.
4878 */
e315cd28
AC		 4879 ha->isp_ops->reset_adapter(vha);
4880 vha->flags.online = 0;
1da177e4 4881 clear_bit(ISP_ABORT_RETRY,
e315cd28 4882 &vha->dpc_flags);
1da177e4
LT		 4883 status = 0;
4884 } else { /* schedule another ISP abort */
4885 ha->isp_abort_cnt--;
7c3df132
SK		 4886 ql_dbg(ql_dbg_taskm, vha, 0x8020,
4887 "ISP abort - retry remaining %d.\n",
4888 ha->isp_abort_cnt);
1da177e4
LT		 4889 status = 1;
4890 }
4891 } else {
4892 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
7c3df132
SK		 4893 ql_dbg(ql_dbg_taskm, vha, 0x8021,
4894 "ISP error recovery - retrying (%d) "
4895 "more times.\n", ha->isp_abort_cnt);
e315cd28 4896 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
1da177e4
LT		 4897 status = 1;
4898 }
4899 }
fa2a1ce5 4900
1da177e4
LT		 4901 }
4902
e315cd28 4903 if (!status) {
7c3df132 4904 ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__);
feafb7b1
AE		 4905
4906 spin_lock_irqsave(&ha->vport_slock, flags);
4907 list_for_each_entry(vp, &ha->vp_list, list) {
4908 if (vp->vp_idx) {
4909 atomic_inc(&vp->vref_count);
4910 spin_unlock_irqrestore(&ha->vport_slock, flags);
4911
e315cd28 4912 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 4913
4914 spin_lock_irqsave(&ha->vport_slock, flags);
4915 atomic_dec(&vp->vref_count);
4916 }
e315cd28 4917 }
feafb7b1
AE		 4918 spin_unlock_irqrestore(&ha->vport_slock, flags);
4919
7d613ac6
SV		 4920 if (IS_QLA8031(ha)) {
4921 ql_dbg(ql_dbg_p3p, vha, 0xb05d,
4922 "Setting back fcoe driver presence.\n");
4923 if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS)
4924 ql_dbg(ql_dbg_p3p, vha, 0xb074,
4925 "Error while setting DRV-Presence.\n");
4926 }
e315cd28 4927 } else {
d8424f68
JP		 4928 ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n",
4929 __func__);
1da177e4
LT		 4930 }
4931
4932 return(status);
4933}
4934
4935/*
4936* qla2x00_restart_isp
4937* restarts the ISP after a reset
4938*
4939* Input:
4940* ha = adapter block pointer.
4941*
4942* Returns:
4943* 0 = success
4944*/
4945static int
e315cd28 4946qla2x00_restart_isp(scsi_qla_host_t *vha)
1da177e4 4947{
c6b2fca8 4948 int status = 0;
e315cd28 4949 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 4950 struct req_que *req = ha->req_q_map[0];
4951 struct rsp_que *rsp = ha->rsp_q_map[0];
1da177e4
LT		 4952
4953 /* If firmware needs to be loaded */
e315cd28
AC		 4954 if (qla2x00_isp_firmware(vha)) {
4955 vha->flags.online = 0;
4956 status = ha->isp_ops->chip_diag(vha);
4957 if (!status)
4958 status = qla2x00_setup_chip(vha);
1da177e4
LT		 4959 }
4960
e315cd28
AC		 4961 if (!status && !(status = qla2x00_init_rings(vha))) {
4962 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
2533cf67 4963 ha->flags.chip_reset_done = 1;
7108b76e 4964
73208dfd
AC		 4965 /* Initialize the queues in use */
4966 qla25xx_init_queues(ha);
4967
e315cd28
AC		 4968 status = qla2x00_fw_ready(vha);
4969 if (!status) {
0107109e 4970 /* Issue a marker after FW becomes ready. */
73208dfd 4971 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
0107109e 4972
7108b76e 4973 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4
LT		 4974 }
4975
4976 /* if no cable then assume it's good */
e315cd28 4977 if ((vha->device_flags & DFLG_NO_CABLE))
1da177e4 4978 status = 0;
1da177e4
LT		 4979 }
4980 return (status);
4981}
4982
73208dfd
AC		 4983static int
4984qla25xx_init_queues(struct qla_hw_data *ha)
4985{
4986 struct rsp_que *rsp = NULL;
4987 struct req_que *req = NULL;
4988 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
4989 int ret = -1;
4990 int i;
4991
2afa19a9 4992 for (i = 1; i < ha->max_rsp_queues; i++) {
73208dfd 4993 rsp = ha->rsp_q_map[i];
cb43285f 4994 if (rsp && test_bit(i, ha->rsp_qid_map)) {
73208dfd 4995 rsp->options &= ~BIT_0;
618a7523 4996 ret = qla25xx_init_rsp_que(base_vha, rsp);
73208dfd 4997 if (ret != QLA_SUCCESS)
7c3df132
SK		 4998 ql_dbg(ql_dbg_init, base_vha, 0x00ff,
4999 "%s Rsp que: %d init failed.\n",
5000 __func__, rsp->id);
73208dfd 5001 else
7c3df132
SK		 5002 ql_dbg(ql_dbg_init, base_vha, 0x0100,
5003 "%s Rsp que: %d inited.\n",
5004 __func__, rsp->id);
73208dfd 5005 }
2afa19a9
AC		 5006 }
5007 for (i = 1; i < ha->max_req_queues; i++) {
73208dfd 5008 req = ha->req_q_map[i];
cb43285f
QT		 5009 if (req && test_bit(i, ha->req_qid_map)) {
5010 /* Clear outstanding commands array. */
73208dfd 5011 req->options &= ~BIT_0;
618a7523 5012 ret = qla25xx_init_req_que(base_vha, req);
73208dfd 5013 if (ret != QLA_SUCCESS)
7c3df132
SK		 5014 ql_dbg(ql_dbg_init, base_vha, 0x0101,
5015 "%s Req que: %d init failed.\n",
5016 __func__, req->id);
73208dfd 5017 else
7c3df132
SK		 5018 ql_dbg(ql_dbg_init, base_vha, 0x0102,
5019 "%s Req que: %d inited.\n",
5020 __func__, req->id);
73208dfd
AC		 5021 }
5022 }
5023 return ret;
5024}
5025
1da177e4
LT		 5026/*
5027* qla2x00_reset_adapter
5028* Reset adapter.
5029*
5030* Input:
5031* ha = adapter block pointer.
5032*/
abbd8870 5033void
e315cd28 5034qla2x00_reset_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 5035{
5036 unsigned long flags = 0;
e315cd28 5037 struct qla_hw_data *ha = vha->hw;
3d71644c 5038 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 5039
e315cd28 5040 vha->flags.online = 0;
fd34f556 5041 ha->isp_ops->disable_intrs(ha);
1da177e4 5042
1da177e4
LT		 5043 spin_lock_irqsave(&ha->hardware_lock, flags);
5044 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
5045 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
5046 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
5047 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
5048 spin_unlock_irqrestore(&ha->hardware_lock, flags);
5049}
0107109e
AV		 5050
5051void
e315cd28 5052qla24xx_reset_adapter(scsi_qla_host_t *vha)
0107109e
AV		 5053{
5054 unsigned long flags = 0;
e315cd28 5055 struct qla_hw_data *ha = vha->hw;
0107109e
AV		 5056 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
5057
7ec0effd 5058 if (IS_P3P_TYPE(ha))
a9083016
GM		 5059 return;
5060
e315cd28 5061 vha->flags.online = 0;
fd34f556 5062 ha->isp_ops->disable_intrs(ha);
0107109e
AV		 5063
5064 spin_lock_irqsave(&ha->hardware_lock, flags);
5065 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
5066 RD_REG_DWORD(&reg->hccr);
5067 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
5068 RD_REG_DWORD(&reg->hccr);
5069 spin_unlock_irqrestore(&ha->hardware_lock, flags);
09ff36d3
AV		 5070
5071 if (IS_NOPOLLING_TYPE(ha))
5072 ha->isp_ops->enable_intrs(ha);
0107109e
AV		 5073}
5074
4e08df3f
DM		 5075/* On sparc systems, obtain port and node WWN from firmware
5076 * properties.
5077 */
e315cd28
AC		 5078static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha,
5079 struct nvram_24xx *nv)
4e08df3f
DM		 5080{
5081#ifdef CONFIG_SPARC
e315cd28 5082 struct qla_hw_data *ha = vha->hw;
4e08df3f 5083 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 5084 struct device_node *dp = pci_device_to_OF_node(pdev);
5085 const u8 *val;
4e08df3f
DM		 5086 int len;
5087
5088 val = of_get_property(dp, "port-wwn", &len);
5089 if (val && len >= WWN_SIZE)
5090 memcpy(nv->port_name, val, WWN_SIZE);
5091
5092 val = of_get_property(dp, "node-wwn", &len);
5093 if (val && len >= WWN_SIZE)
5094 memcpy(nv->node_name, val, WWN_SIZE);
5095#endif
5096}
5097
0107109e 5098int
e315cd28 5099qla24xx_nvram_config(scsi_qla_host_t *vha)
0107109e 5100{
4e08df3f 5101 int rval;
0107109e
AV		 5102 struct init_cb_24xx *icb;
5103 struct nvram_24xx *nv;
5104 uint32_t *dptr;
5105 uint8_t *dptr1, *dptr2;
5106 uint32_t chksum;
5107 uint16_t cnt;
e315cd28 5108 struct qla_hw_data *ha = vha->hw;
0107109e 5109
4e08df3f 5110 rval = QLA_SUCCESS;
0107109e 5111 icb = (struct init_cb_24xx *)ha->init_cb;
281afe19 5112 nv = ha->nvram;
0107109e
AV		 5113
5114 /* Determine NVRAM starting address. */
f73cb695 5115 if (ha->port_no == 0) {
e5b68a61
AC		 5116 ha->nvram_base = FA_NVRAM_FUNC0_ADDR;
5117 ha->vpd_base = FA_NVRAM_VPD0_ADDR;
5118 } else {
0107109e 5119 ha->nvram_base = FA_NVRAM_FUNC1_ADDR;
6f641790
AV		 5120 ha->vpd_base = FA_NVRAM_VPD1_ADDR;
5121 }
f73cb695 5122
e5b68a61
AC		 5123 ha->nvram_size = sizeof(struct nvram_24xx);
5124 ha->vpd_size = FA_NVRAM_VPD_SIZE;
0107109e 5125
281afe19
SJ		 5126 /* Get VPD data into cache */
5127 ha->vpd = ha->nvram + VPD_OFFSET;
e315cd28 5128 ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd,
281afe19
SJ		 5129 ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
5130
5131 /* Get NVRAM data into cache and calculate checksum. */
0107109e 5132 dptr = (uint32_t *)nv;
e315cd28 5133 ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base,
0107109e 5134 ha->nvram_size);
da08ef5c
JC		 5135 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++)
5136 chksum += le32_to_cpu(*dptr);
0107109e 5137
7c3df132
SK		 5138 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
5139 "Contents of NVRAM\n");
5140 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
5141 (uint8_t *)nv, ha->nvram_size);
0107109e
AV		 5142
5143 /* Bad NVRAM data, set defaults parameters. */
5144 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
5145 || nv->id[3] != ' ' ||
ad950360 5146 nv->nvram_version < cpu_to_le16(ICB_VERSION)) {
0107109e 5147 /* Reset NVRAM data. */
7c3df132 5148 ql_log(ql_log_warn, vha, 0x006b,
9e336520 5149 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132
SK		 5150 "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version);
5151 ql_log(ql_log_warn, vha, 0x006c,
5152 "Falling back to functioning (yet invalid -- WWPN) "
5153 "defaults.\n");
4e08df3f
DM		 5154
5155 /*
5156 * Set default initialization control block.
5157 */
5158 memset(nv, 0, ha->nvram_size);
ad950360
BVA		 5159 nv->nvram_version = cpu_to_le16(ICB_VERSION);
5160 nv->version = cpu_to_le16(ICB_VERSION);
98aee70d 5161 nv->frame_payload_size = 2048;
ad950360
BVA		 5162 nv->execution_throttle = cpu_to_le16(0xFFFF);
5163 nv->exchange_count = cpu_to_le16(0);
5164 nv->hard_address = cpu_to_le16(124);
4e08df3f 5165 nv->port_name[0] = 0x21;
f73cb695 5166 nv->port_name[1] = 0x00 + ha->port_no + 1;
4e08df3f
DM		 5167 nv->port_name[2] = 0x00;
5168 nv->port_name[3] = 0xe0;
5169 nv->port_name[4] = 0x8b;
5170 nv->port_name[5] = 0x1c;
5171 nv->port_name[6] = 0x55;
5172 nv->port_name[7] = 0x86;
5173 nv->node_name[0] = 0x20;
5174 nv->node_name[1] = 0x00;
5175 nv->node_name[2] = 0x00;
5176 nv->node_name[3] = 0xe0;
5177 nv->node_name[4] = 0x8b;
5178 nv->node_name[5] = 0x1c;
5179 nv->node_name[6] = 0x55;
5180 nv->node_name[7] = 0x86;
e315cd28 5181 qla24xx_nvram_wwn_from_ofw(vha, nv);
ad950360
BVA		 5182 nv->login_retry_count = cpu_to_le16(8);
5183 nv->interrupt_delay_timer = cpu_to_le16(0);
5184 nv->login_timeout = cpu_to_le16(0);
4e08df3f 5185 nv->firmware_options_1 =
ad950360
BVA		 5186 cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
5187 nv->firmware_options_2 = cpu_to_le32(2 << 4);
5188 nv->firmware_options_2 |= cpu_to_le32(BIT_12);
5189 nv->firmware_options_3 = cpu_to_le32(2 << 13);
5190 nv->host_p = cpu_to_le32(BIT_11|BIT_10);
5191 nv->efi_parameters = cpu_to_le32(0);
4e08df3f 5192 nv->reset_delay = 5;
ad950360
BVA		 5193 nv->max_luns_per_target = cpu_to_le16(128);
5194 nv->port_down_retry_count = cpu_to_le16(30);
5195 nv->link_down_timeout = cpu_to_le16(30);
4e08df3f
DM		 5196
5197 rval = 1;
0107109e
AV		 5198 }
5199
2d70c103
NB		 5200 if (!qla_ini_mode_enabled(vha)) {
5201 /* Don't enable full login after initial LIP */
ad950360 5202 nv->firmware_options_1 &= cpu_to_le32(~BIT_13);
2d70c103 5203 /* Don't enable LIP full login for initiator */
ad950360 5204 nv->host_p &= cpu_to_le32(~BIT_10);
2d70c103
NB		 5205 }
5206
5207 qlt_24xx_config_nvram_stage1(vha, nv);
5208
0107109e 5209 /* Reset Initialization control block */
e315cd28 5210 memset(icb, 0, ha->init_cb_size);
0107109e
AV		 5211
5212 /* Copy 1st segment. */
5213 dptr1 = (uint8_t *)icb;
5214 dptr2 = (uint8_t *)&nv->version;
5215 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
5216 while (cnt--)
5217 *dptr1++ = *dptr2++;
5218
5219 icb->login_retry_count = nv->login_retry_count;
3ea66e28 5220 icb->link_down_on_nos = nv->link_down_on_nos;
0107109e
AV		 5221
5222 /* Copy 2nd segment. */
5223 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
5224 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
5225 cnt = (uint8_t *)&icb->reserved_3 -
5226 (uint8_t *)&icb->interrupt_delay_timer;
5227 while (cnt--)
5228 *dptr1++ = *dptr2++;
5229
5230 /*
5231 * Setup driver NVRAM options.
5232 */
e315cd28 5233 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
9bb9fcf2 5234 "QLA2462");
0107109e 5235
2d70c103
NB		 5236 qlt_24xx_config_nvram_stage2(vha, icb);
5237
ad950360 5238 if (nv->host_p & cpu_to_le32(BIT_15)) {
2d70c103 5239 /* Use alternate WWN? */
5341e868
AV		 5240 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
5241 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
5242 }
5243
0107109e 5244 /* Prepare nodename */
ad950360 5245 if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) {
0107109e
AV		 5246 /*
5247 * Firmware will apply the following mask if the nodename was
5248 * not provided.
5249 */
5250 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
5251 icb->node_name[0] &= 0xF0;
5252 }
5253
5254 /* Set host adapter parameters. */
5255 ha->flags.disable_risc_code_load = 0;
0c8c39af
AV		 5256 ha->flags.enable_lip_reset = 0;
5257 ha->flags.enable_lip_full_login =
5258 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
5259 ha->flags.enable_target_reset =
5260 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
0107109e 5261 ha->flags.enable_led_scheme = 0;
d4c760c2 5262 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
0107109e 5263
fd0e7e4d
AV		 5264 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
5265 (BIT_6 | BIT_5 | BIT_4)) >> 4;
0107109e
AV		 5266
5267 memcpy(ha->fw_seriallink_options24, nv->seriallink_options,
5268 sizeof(ha->fw_seriallink_options24));
5269
5270 /* save HBA serial number */
5271 ha->serial0 = icb->port_name[5];
5272 ha->serial1 = icb->port_name[6];
5273 ha->serial2 = icb->port_name[7];
e315cd28
AC		 5274 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
5275 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
0107109e 5276
ad950360 5277 icb->execution_throttle = cpu_to_le16(0xFFFF);
bc8fb3cb 5278
0107109e
AV		 5279 ha->retry_count = le16_to_cpu(nv->login_retry_count);
5280
5281 /* Set minimum login_timeout to 4 seconds. */
5282 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
5283 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
5284 if (le16_to_cpu(nv->login_timeout) < 4)
ad950360 5285 nv->login_timeout = cpu_to_le16(4);
0107109e 5286 ha->login_timeout = le16_to_cpu(nv->login_timeout);
0107109e 5287
00a537b8
AV		 5288 /* Set minimum RATOV to 100 tenths of a second. */
5289 ha->r_a_tov = 100;
0107109e
AV		 5290
5291 ha->loop_reset_delay = nv->reset_delay;
5292
5293 /* Link Down Timeout = 0:
5294 *
5295 * When Port Down timer expires we will start returning
5296 * I/O's to OS with "DID_NO_CONNECT".
5297 *
5298 * Link Down Timeout != 0:
5299 *
5300 * The driver waits for the link to come up after link down
5301 * before returning I/Os to OS with "DID_NO_CONNECT".
5302 */
5303 if (le16_to_cpu(nv->link_down_timeout) == 0) {
5304 ha->loop_down_abort_time =
5305 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
5306 } else {
5307 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
5308 ha->loop_down_abort_time =
5309 (LOOP_DOWN_TIME - ha->link_down_timeout);
5310 }
5311
5312 /* Need enough time to try and get the port back. */
5313 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
5314 if (qlport_down_retry)
5315 ha->port_down_retry_count = qlport_down_retry;
5316
5317 /* Set login_retry_count */
5318 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
5319 if (ha->port_down_retry_count ==
5320 le16_to_cpu(nv->port_down_retry_count) &&
5321 ha->port_down_retry_count > 3)
5322 ha->login_retry_count = ha->port_down_retry_count;
5323 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
5324 ha->login_retry_count = ha->port_down_retry_count;
5325 if (ql2xloginretrycount)
5326 ha->login_retry_count = ql2xloginretrycount;
5327
4fdfefe5 5328 /* Enable ZIO. */
e315cd28 5329 if (!vha->flags.init_done) {
4fdfefe5
AV		 5330 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
5331 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
5332 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
5333 le16_to_cpu(icb->interrupt_delay_timer): 2;
5334 }
ad950360 5335 icb->firmware_options_2 &= cpu_to_le32(
4fdfefe5 5336 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
e315cd28 5337 vha->flags.process_response_queue = 0;
4fdfefe5 5338 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d
AV		 5339 ha->zio_mode = QLA_ZIO_MODE_6;
5340
7c3df132 5341 ql_log(ql_log_info, vha, 0x006f,
4fdfefe5
AV		 5342 "ZIO mode %d enabled; timer delay (%d us).\n",
5343 ha->zio_mode, ha->zio_timer * 100);
5344
5345 icb->firmware_options_2 |= cpu_to_le32(
5346 (uint32_t)ha->zio_mode);
5347 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
e315cd28 5348 vha->flags.process_response_queue = 1;
4fdfefe5
AV		 5349 }
5350
4e08df3f 5351 if (rval) {
7c3df132
SK		 5352 ql_log(ql_log_warn, vha, 0x0070,
5353 "NVRAM configuration failed.\n");
4e08df3f
DM		 5354 }
5355 return (rval);
0107109e
AV		 5356}
5357
4243c115
SC		 5358uint8_t qla27xx_find_valid_image(struct scsi_qla_host *vha)
5359{
5360 struct qla27xx_image_status pri_image_status, sec_image_status;
5361 uint8_t valid_pri_image, valid_sec_image;
5362 uint32_t *wptr;
5363 uint32_t cnt, chksum, size;
5364 struct qla_hw_data *ha = vha->hw;
5365
5366 valid_pri_image = valid_sec_image = 1;
5367 ha->active_image = 0;
5368 size = sizeof(struct qla27xx_image_status) / sizeof(uint32_t);
5369
5370 if (!ha->flt_region_img_status_pri) {
5371 valid_pri_image = 0;
5372 goto check_sec_image;
5373 }
5374
5375 qla24xx_read_flash_data(vha, (uint32_t *)(&pri_image_status),
5376 ha->flt_region_img_status_pri, size);
5377
5378 if (pri_image_status.signature != QLA27XX_IMG_STATUS_SIGN) {
5379 ql_dbg(ql_dbg_init, vha, 0x018b,
5380 "Primary image signature (0x%x) not valid\n",
5381 pri_image_status.signature);
5382 valid_pri_image = 0;
5383 goto check_sec_image;
5384 }
5385
5386 wptr = (uint32_t *)(&pri_image_status);
5387 cnt = size;
5388
da08ef5c
JC		 5389 for (chksum = 0; cnt--; wptr++)
5390 chksum += le32_to_cpu(*wptr);
4243c115
SC		 5391 if (chksum) {
5392 ql_dbg(ql_dbg_init, vha, 0x018c,
5393 "Checksum validation failed for primary image (0x%x)\n",
5394 chksum);
5395 valid_pri_image = 0;
5396 }
5397
5398check_sec_image:
5399 if (!ha->flt_region_img_status_sec) {
5400 valid_sec_image = 0;
5401 goto check_valid_image;
5402 }
5403
5404 qla24xx_read_flash_data(vha, (uint32_t *)(&sec_image_status),
5405 ha->flt_region_img_status_sec, size);
5406
5407 if (sec_image_status.signature != QLA27XX_IMG_STATUS_SIGN) {
5408 ql_dbg(ql_dbg_init, vha, 0x018d,
5409 "Secondary image signature(0x%x) not valid\n",
5410 sec_image_status.signature);
5411 valid_sec_image = 0;
5412 goto check_valid_image;
5413 }
5414
5415 wptr = (uint32_t *)(&sec_image_status);
5416 cnt = size;
da08ef5c
JC		 5417 for (chksum = 0; cnt--; wptr++)
5418 chksum += le32_to_cpu(*wptr);
4243c115
SC		 5419 if (chksum) {
5420 ql_dbg(ql_dbg_init, vha, 0x018e,
5421 "Checksum validation failed for secondary image (0x%x)\n",
5422 chksum);
5423 valid_sec_image = 0;
5424 }
5425
5426check_valid_image:
5427 if (valid_pri_image && (pri_image_status.image_status_mask & 0x1))
5428 ha->active_image = QLA27XX_PRIMARY_IMAGE;
5429 if (valid_sec_image && (sec_image_status.image_status_mask & 0x1)) {
5430 if (!ha->active_image ||
5431 pri_image_status.generation_number <
5432 sec_image_status.generation_number)
5433 ha->active_image = QLA27XX_SECONDARY_IMAGE;
5434 }
5435
5436 ql_dbg(ql_dbg_init, vha, 0x018f, "%s image\n",
5437 ha->active_image == 0 ? "default bootld and fw" :
5438 ha->active_image == 1 ? "primary" :
5439 ha->active_image == 2 ? "secondary" :
5440 "Invalid");
5441
5442 return ha->active_image;
5443}
5444
413975a0 5445static int
cbc8eb67
AV		 5446qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
5447 uint32_t faddr)
d1c61909 5448{
73208dfd 5449 int rval = QLA_SUCCESS;
d1c61909 5450 int segments, fragment;
d1c61909
AV		 5451 uint32_t *dcode, dlen;
5452 uint32_t risc_addr;
5453 uint32_t risc_size;
5454 uint32_t i;
e315cd28 5455 struct qla_hw_data *ha = vha->hw;
73208dfd 5456 struct req_que *req = ha->req_q_map[0];
eaac30be 5457
7c3df132 5458 ql_dbg(ql_dbg_init, vha, 0x008b,
cfb0919c 5459 "FW: Loading firmware from flash (%x).\n", faddr);
eaac30be 5460
d1c61909
AV		 5461 rval = QLA_SUCCESS;
5462
5463 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 5464 dcode = (uint32_t *)req->ring;
d1c61909
AV		 5465 *srisc_addr = 0;
5466
4243c115
SC		 5467 if (IS_QLA27XX(ha) &&
5468 qla27xx_find_valid_image(vha) == QLA27XX_SECONDARY_IMAGE)
5469 faddr = ha->flt_region_fw_sec;
5470
d1c61909 5471 /* Validate firmware image by checking version. */
e315cd28 5472 qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
d1c61909
AV		 5473 for (i = 0; i < 4; i++)
5474 dcode[i] = be32_to_cpu(dcode[i]);
5475 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
5476 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
5477 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
5478 dcode[3] == 0)) {
7c3df132
SK		 5479 ql_log(ql_log_fatal, vha, 0x008c,
5480 "Unable to verify the integrity of flash firmware "
5481 "image.\n");
5482 ql_log(ql_log_fatal, vha, 0x008d,
5483 "Firmware data: %08x %08x %08x %08x.\n",
5484 dcode[0], dcode[1], dcode[2], dcode[3]);
d1c61909
AV		 5485
5486 return QLA_FUNCTION_FAILED;
5487 }
5488
5489 while (segments && rval == QLA_SUCCESS) {
5490 /* Read segment's load information. */
e315cd28 5491 qla24xx_read_flash_data(vha, dcode, faddr, 4);
d1c61909
AV		 5492
5493 risc_addr = be32_to_cpu(dcode[2]);
5494 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
5495 risc_size = be32_to_cpu(dcode[3]);
5496
5497 fragment = 0;
5498 while (risc_size > 0 && rval == QLA_SUCCESS) {
5499 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
5500 if (dlen > risc_size)
5501 dlen = risc_size;
5502
7c3df132
SK		 5503 ql_dbg(ql_dbg_init, vha, 0x008e,
5504 "Loading risc segment@ risc addr %x "
5505 "number of dwords 0x%x offset 0x%x.\n",
5506 risc_addr, dlen, faddr);
d1c61909 5507
e315cd28 5508 qla24xx_read_flash_data(vha, dcode, faddr, dlen);
d1c61909
AV		 5509 for (i = 0; i < dlen; i++)
5510 dcode[i] = swab32(dcode[i]);
5511
73208dfd 5512 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
d1c61909
AV		 5513 dlen);
5514 if (rval) {
7c3df132
SK		 5515 ql_log(ql_log_fatal, vha, 0x008f,
5516 "Failed to load segment %d of firmware.\n",
5517 fragment);
f261f7af 5518 return QLA_FUNCTION_FAILED;
d1c61909
AV		 5519 }
5520
5521 faddr += dlen;
5522 risc_addr += dlen;
5523 risc_size -= dlen;
5524 fragment++;
5525 }
5526
5527 /* Next segment. */
5528 segments--;
5529 }
5530
f73cb695
CD		 5531 if (!IS_QLA27XX(ha))
5532 return rval;
5533
5534 if (ha->fw_dump_template)
5535 vfree(ha->fw_dump_template);
5536 ha->fw_dump_template = NULL;
5537 ha->fw_dump_template_len = 0;
5538
5539 ql_dbg(ql_dbg_init, vha, 0x0161,
5540 "Loading fwdump template from %x\n", faddr);
5541 qla24xx_read_flash_data(vha, dcode, faddr, 7);
5542 risc_size = be32_to_cpu(dcode[2]);
5543 ql_dbg(ql_dbg_init, vha, 0x0162,
5544 "-> array size %x dwords\n", risc_size);
5545 if (risc_size == 0 || risc_size == ~0)
5546 goto default_template;
5547
5548 dlen = (risc_size - 8) * sizeof(*dcode);
5549 ql_dbg(ql_dbg_init, vha, 0x0163,
5550 "-> template allocating %x bytes...\n", dlen);
5551 ha->fw_dump_template = vmalloc(dlen);
5552 if (!ha->fw_dump_template) {
5553 ql_log(ql_log_warn, vha, 0x0164,
5554 "Failed fwdump template allocate %x bytes.\n", risc_size);
5555 goto default_template;
5556 }
5557
5558 faddr += 7;
5559 risc_size -= 8;
5560 dcode = ha->fw_dump_template;
5561 qla24xx_read_flash_data(vha, dcode, faddr, risc_size);
5562 for (i = 0; i < risc_size; i++)
5563 dcode[i] = le32_to_cpu(dcode[i]);
5564
5565 if (!qla27xx_fwdt_template_valid(dcode)) {
5566 ql_log(ql_log_warn, vha, 0x0165,
5567 "Failed fwdump template validate\n");
5568 goto default_template;
5569 }
5570
5571 dlen = qla27xx_fwdt_template_size(dcode);
5572 ql_dbg(ql_dbg_init, vha, 0x0166,
5573 "-> template size %x bytes\n", dlen);
5574 if (dlen > risc_size * sizeof(*dcode)) {
5575 ql_log(ql_log_warn, vha, 0x0167,
97ea702b
CD		 5576 "Failed fwdump template exceeds array by %x bytes\n",
5577 (uint32_t)(dlen - risc_size * sizeof(*dcode)));
f73cb695
CD		 5578 goto default_template;
5579 }
5580 ha->fw_dump_template_len = dlen;
5581 return rval;
5582
5583default_template:
5584 ql_log(ql_log_warn, vha, 0x0168, "Using default fwdump template\n");
5585 if (ha->fw_dump_template)
5586 vfree(ha->fw_dump_template);
5587 ha->fw_dump_template = NULL;
5588 ha->fw_dump_template_len = 0;
5589
5590 dlen = qla27xx_fwdt_template_default_size();
5591 ql_dbg(ql_dbg_init, vha, 0x0169,
5592 "-> template allocating %x bytes...\n", dlen);
5593 ha->fw_dump_template = vmalloc(dlen);
5594 if (!ha->fw_dump_template) {
5595 ql_log(ql_log_warn, vha, 0x016a,
5596 "Failed fwdump template allocate %x bytes.\n", risc_size);
5597 goto failed_template;
5598 }
5599
5600 dcode = ha->fw_dump_template;
5601 risc_size = dlen / sizeof(*dcode);
5602 memcpy(dcode, qla27xx_fwdt_template_default(), dlen);
5603 for (i = 0; i < risc_size; i++)
5604 dcode[i] = be32_to_cpu(dcode[i]);
5605
5606 if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) {
5607 ql_log(ql_log_warn, vha, 0x016b,
5608 "Failed fwdump template validate\n");
5609 goto failed_template;
5610 }
5611
5612 dlen = qla27xx_fwdt_template_size(ha->fw_dump_template);
5613 ql_dbg(ql_dbg_init, vha, 0x016c,
5614 "-> template size %x bytes\n", dlen);
5615 ha->fw_dump_template_len = dlen;
5616 return rval;
5617
5618failed_template:
5619 ql_log(ql_log_warn, vha, 0x016d, "Failed default fwdump template\n");
5620 if (ha->fw_dump_template)
5621 vfree(ha->fw_dump_template);
5622 ha->fw_dump_template = NULL;
5623 ha->fw_dump_template_len = 0;
d1c61909
AV		 5624 return rval;
5625}
5626
e9454a88 5627#define QLA_FW_URL "http://ldriver.qlogic.com/firmware/"
d1c61909 5628
0107109e 5629int
e315cd28 5630qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5433383e
AV		 5631{
5632 int rval;
5633 int i, fragment;
5634 uint16_t *wcode, *fwcode;
5635 uint32_t risc_addr, risc_size, fwclen, wlen, *seg;
5636 struct fw_blob *blob;
e315cd28 5637 struct qla_hw_data *ha = vha->hw;
73208dfd 5638 struct req_que *req = ha->req_q_map[0];
5433383e
AV		 5639
5640 /* Load firmware blob. */
e315cd28 5641 blob = qla2x00_request_firmware(vha);
5433383e 5642 if (!blob) {
7c3df132 5643 ql_log(ql_log_info, vha, 0x0083,
94bcf830 5644 "Firmware image unavailable.\n");
7c3df132
SK		 5645 ql_log(ql_log_info, vha, 0x0084,
5646 "Firmware images can be retrieved from: "QLA_FW_URL ".\n");
5433383e
AV		 5647 return QLA_FUNCTION_FAILED;
5648 }
5649
5650 rval = QLA_SUCCESS;
5651
73208dfd 5652 wcode = (uint16_t *)req->ring;
5433383e
AV		 5653 *srisc_addr = 0;
5654 fwcode = (uint16_t *)blob->fw->data;
5655 fwclen = 0;
5656
5657 /* Validate firmware image by checking version. */
5658 if (blob->fw->size < 8 * sizeof(uint16_t)) {
7c3df132
SK		 5659 ql_log(ql_log_fatal, vha, 0x0085,
5660 "Unable to verify integrity of firmware image (%Zd).\n",
5433383e
AV		 5661 blob->fw->size);
5662 goto fail_fw_integrity;
5663 }
5664 for (i = 0; i < 4; i++)
5665 wcode[i] = be16_to_cpu(fwcode[i + 4]);
5666 if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff &&
5667 wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 &&
5668 wcode[2] == 0 && wcode[3] == 0)) {
7c3df132
SK		 5669 ql_log(ql_log_fatal, vha, 0x0086,
5670 "Unable to verify integrity of firmware image.\n");
5671 ql_log(ql_log_fatal, vha, 0x0087,
5672 "Firmware data: %04x %04x %04x %04x.\n",
5673 wcode[0], wcode[1], wcode[2], wcode[3]);
5433383e
AV		 5674 goto fail_fw_integrity;
5675 }
5676
5677 seg = blob->segs;
5678 while (*seg && rval == QLA_SUCCESS) {
5679 risc_addr = *seg;
5680 *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr;
5681 risc_size = be16_to_cpu(fwcode[3]);
5682
5683 /* Validate firmware image size. */
5684 fwclen += risc_size * sizeof(uint16_t);
5685 if (blob->fw->size < fwclen) {
7c3df132 5686 ql_log(ql_log_fatal, vha, 0x0088,
5433383e 5687 "Unable to verify integrity of firmware image "
7c3df132 5688 "(%Zd).\n", blob->fw->size);
5433383e
AV		 5689 goto fail_fw_integrity;
5690 }
5691
5692 fragment = 0;
5693 while (risc_size > 0 && rval == QLA_SUCCESS) {
5694 wlen = (uint16_t)(ha->fw_transfer_size >> 1);
5695 if (wlen > risc_size)
5696 wlen = risc_size;
7c3df132
SK		 5697 ql_dbg(ql_dbg_init, vha, 0x0089,
5698 "Loading risc segment@ risc addr %x number of "
5699 "words 0x%x.\n", risc_addr, wlen);
5433383e
AV		 5700
5701 for (i = 0; i < wlen; i++)
5702 wcode[i] = swab16(fwcode[i]);
5703
73208dfd 5704 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
5433383e
AV		 5705 wlen);
5706 if (rval) {
7c3df132
SK		 5707 ql_log(ql_log_fatal, vha, 0x008a,
5708 "Failed to load segment %d of firmware.\n",
5709 fragment);
5433383e
AV		 5710 break;
5711 }
5712
5713 fwcode += wlen;
5714 risc_addr += wlen;
5715 risc_size -= wlen;
5716 fragment++;
5717 }
5718
5719 /* Next segment. */
5720 seg++;
5721 }
5722 return rval;
5723
5724fail_fw_integrity:
5725 return QLA_FUNCTION_FAILED;
5726}
5727
eaac30be
AV		 5728static int
5729qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
0107109e
AV		 5730{
5731 int rval;
5732 int segments, fragment;
5733 uint32_t *dcode, dlen;
5734 uint32_t risc_addr;
5735 uint32_t risc_size;
5736 uint32_t i;
5433383e 5737 struct fw_blob *blob;
f73cb695
CD		 5738 const uint32_t *fwcode;
5739 uint32_t fwclen;
e315cd28 5740 struct qla_hw_data *ha = vha->hw;
73208dfd 5741 struct req_que *req = ha->req_q_map[0];
0107109e 5742
5433383e 5743 /* Load firmware blob. */
e315cd28 5744 blob = qla2x00_request_firmware(vha);
5433383e 5745 if (!blob) {
7c3df132 5746 ql_log(ql_log_warn, vha, 0x0090,
94bcf830 5747 "Firmware image unavailable.\n");
7c3df132
SK		 5748 ql_log(ql_log_warn, vha, 0x0091,
5749 "Firmware images can be retrieved from: "
5750 QLA_FW_URL ".\n");
d1c61909 5751
eaac30be 5752 return QLA_FUNCTION_FAILED;
0107109e
AV		 5753 }
5754
cfb0919c
CD		 5755 ql_dbg(ql_dbg_init, vha, 0x0092,
5756 "FW: Loading via request-firmware.\n");
eaac30be 5757
0107109e
AV		 5758 rval = QLA_SUCCESS;
5759
5760 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 5761 dcode = (uint32_t *)req->ring;
0107109e 5762 *srisc_addr = 0;
5433383e 5763 fwcode = (uint32_t *)blob->fw->data;
0107109e
AV		 5764 fwclen = 0;
5765
5766 /* Validate firmware image by checking version. */
5433383e 5767 if (blob->fw->size < 8 * sizeof(uint32_t)) {
7c3df132
SK		 5768 ql_log(ql_log_fatal, vha, 0x0093,
5769 "Unable to verify integrity of firmware image (%Zd).\n",
5433383e 5770 blob->fw->size);
f73cb695 5771 return QLA_FUNCTION_FAILED;
0107109e
AV		 5772 }
5773 for (i = 0; i < 4; i++)
5774 dcode[i] = be32_to_cpu(fwcode[i + 4]);
5775 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
5776 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
5777 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
5778 dcode[3] == 0)) {
7c3df132
SK		 5779 ql_log(ql_log_fatal, vha, 0x0094,
5780 "Unable to verify integrity of firmware image (%Zd).\n",
5781 blob->fw->size);
5782 ql_log(ql_log_fatal, vha, 0x0095,
5783 "Firmware data: %08x %08x %08x %08x.\n",
5784 dcode[0], dcode[1], dcode[2], dcode[3]);
f73cb695 5785 return QLA_FUNCTION_FAILED;
0107109e
AV		 5786 }
5787
5788 while (segments && rval == QLA_SUCCESS) {
5789 risc_addr = be32_to_cpu(fwcode[2]);
5790 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
5791 risc_size = be32_to_cpu(fwcode[3]);
5792
5793 /* Validate firmware image size. */
5794 fwclen += risc_size * sizeof(uint32_t);
5433383e 5795 if (blob->fw->size < fwclen) {
7c3df132 5796 ql_log(ql_log_fatal, vha, 0x0096,
5433383e 5797 "Unable to verify integrity of firmware image "
7c3df132 5798 "(%Zd).\n", blob->fw->size);
f73cb695 5799 return QLA_FUNCTION_FAILED;
0107109e
AV		 5800 }
5801
5802 fragment = 0;
5803 while (risc_size > 0 && rval == QLA_SUCCESS) {
5804 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
5805 if (dlen > risc_size)
5806 dlen = risc_size;
5807
7c3df132
SK		 5808 ql_dbg(ql_dbg_init, vha, 0x0097,
5809 "Loading risc segment@ risc addr %x "
5810 "number of dwords 0x%x.\n", risc_addr, dlen);
0107109e
AV		 5811
5812 for (i = 0; i < dlen; i++)
5813 dcode[i] = swab32(fwcode[i]);
5814
73208dfd 5815 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
590f98e5 5816 dlen);
0107109e 5817 if (rval) {
7c3df132
SK		 5818 ql_log(ql_log_fatal, vha, 0x0098,
5819 "Failed to load segment %d of firmware.\n",
5820 fragment);
f261f7af 5821 return QLA_FUNCTION_FAILED;
0107109e
AV		 5822 }
5823
5824 fwcode += dlen;
5825 risc_addr += dlen;
5826 risc_size -= dlen;
5827 fragment++;
5828 }
5829
5830 /* Next segment. */
5831 segments--;
5832 }
f73cb695
CD		 5833
5834 if (!IS_QLA27XX(ha))
5835 return rval;
5836
5837 if (ha->fw_dump_template)
5838 vfree(ha->fw_dump_template);
5839 ha->fw_dump_template = NULL;
5840 ha->fw_dump_template_len = 0;
5841
5842 ql_dbg(ql_dbg_init, vha, 0x171,
97ea702b
CD		 5843 "Loading fwdump template from %x\n",
5844 (uint32_t)((void *)fwcode - (void *)blob->fw->data));
f73cb695
CD		 5845 risc_size = be32_to_cpu(fwcode[2]);
5846 ql_dbg(ql_dbg_init, vha, 0x172,
5847 "-> array size %x dwords\n", risc_size);
5848 if (risc_size == 0 || risc_size == ~0)
5849 goto default_template;
5850
5851 dlen = (risc_size - 8) * sizeof(*fwcode);
5852 ql_dbg(ql_dbg_init, vha, 0x0173,
5853 "-> template allocating %x bytes...\n", dlen);
5854 ha->fw_dump_template = vmalloc(dlen);
5855 if (!ha->fw_dump_template) {
5856 ql_log(ql_log_warn, vha, 0x0174,
5857 "Failed fwdump template allocate %x bytes.\n", risc_size);
5858 goto default_template;
5859 }
5860
5861 fwcode += 7;
5862 risc_size -= 8;
5863 dcode = ha->fw_dump_template;
5864 for (i = 0; i < risc_size; i++)
5865 dcode[i] = le32_to_cpu(fwcode[i]);
5866
5867 if (!qla27xx_fwdt_template_valid(dcode)) {
5868 ql_log(ql_log_warn, vha, 0x0175,
5869 "Failed fwdump template validate\n");
5870 goto default_template;
5871 }
5872
5873 dlen = qla27xx_fwdt_template_size(dcode);
5874 ql_dbg(ql_dbg_init, vha, 0x0176,
5875 "-> template size %x bytes\n", dlen);
5876 if (dlen > risc_size * sizeof(*fwcode)) {
5877 ql_log(ql_log_warn, vha, 0x0177,
97ea702b
CD		 5878 "Failed fwdump template exceeds array by %x bytes\n",
5879 (uint32_t)(dlen - risc_size * sizeof(*fwcode)));
f73cb695
CD		 5880 goto default_template;
5881 }
5882 ha->fw_dump_template_len = dlen;
0107109e
AV		 5883 return rval;
5884
f73cb695
CD		 5885default_template:
5886 ql_log(ql_log_warn, vha, 0x0178, "Using default fwdump template\n");
5887 if (ha->fw_dump_template)
5888 vfree(ha->fw_dump_template);
5889 ha->fw_dump_template = NULL;
5890 ha->fw_dump_template_len = 0;
5891
5892 dlen = qla27xx_fwdt_template_default_size();
5893 ql_dbg(ql_dbg_init, vha, 0x0179,
5894 "-> template allocating %x bytes...\n", dlen);
5895 ha->fw_dump_template = vmalloc(dlen);
5896 if (!ha->fw_dump_template) {
5897 ql_log(ql_log_warn, vha, 0x017a,
5898 "Failed fwdump template allocate %x bytes.\n", risc_size);
5899 goto failed_template;
5900 }
5901
5902 dcode = ha->fw_dump_template;
5903 risc_size = dlen / sizeof(*fwcode);
5904 fwcode = qla27xx_fwdt_template_default();
5905 for (i = 0; i < risc_size; i++)
5906 dcode[i] = be32_to_cpu(fwcode[i]);
5907
5908 if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) {
5909 ql_log(ql_log_warn, vha, 0x017b,
5910 "Failed fwdump template validate\n");
5911 goto failed_template;
5912 }
5913
5914 dlen = qla27xx_fwdt_template_size(ha->fw_dump_template);
5915 ql_dbg(ql_dbg_init, vha, 0x017c,
5916 "-> template size %x bytes\n", dlen);
5917 ha->fw_dump_template_len = dlen;
5918 return rval;
5919
5920failed_template:
5921 ql_log(ql_log_warn, vha, 0x017d, "Failed default fwdump template\n");
5922 if (ha->fw_dump_template)
5923 vfree(ha->fw_dump_template);
5924 ha->fw_dump_template = NULL;
5925 ha->fw_dump_template_len = 0;
5926 return rval;
0107109e 5927}
18c6c127 5928
eaac30be
AV		 5929int
5930qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5931{
5932 int rval;
5933
e337d907
AV		 5934 if (ql2xfwloadbin == 1)
5935 return qla81xx_load_risc(vha, srisc_addr);
5936
eaac30be
AV		 5937 /*
5938 * FW Load priority:
5939 * 1) Firmware via request-firmware interface (.bin file).
5940 * 2) Firmware residing in flash.
5941 */
5942 rval = qla24xx_load_risc_blob(vha, srisc_addr);
5943 if (rval == QLA_SUCCESS)
5944 return rval;
5945
cbc8eb67
AV		 5946 return qla24xx_load_risc_flash(vha, srisc_addr,
5947 vha->hw->flt_region_fw);
eaac30be
AV		 5948}
5949
5950int
5951qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5952{
5953 int rval;
cbc8eb67 5954 struct qla_hw_data *ha = vha->hw;
eaac30be 5955
e337d907 5956 if (ql2xfwloadbin == 2)
cbc8eb67 5957 goto try_blob_fw;
e337d907 5958
eaac30be
AV		 5959 /*
5960 * FW Load priority:
5961 * 1) Firmware residing in flash.
5962 * 2) Firmware via request-firmware interface (.bin file).
cbc8eb67 5963 * 3) Golden-Firmware residing in flash -- limited operation.
eaac30be 5964 */
cbc8eb67 5965 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
eaac30be
AV		 5966 if (rval == QLA_SUCCESS)
5967 return rval;
5968
cbc8eb67
AV		 5969try_blob_fw:
5970 rval = qla24xx_load_risc_blob(vha, srisc_addr);
5971 if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw)
5972 return rval;
5973
7c3df132
SK		 5974 ql_log(ql_log_info, vha, 0x0099,
5975 "Attempting to fallback to golden firmware.\n");
cbc8eb67
AV		 5976 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
5977 if (rval != QLA_SUCCESS)
5978 return rval;
5979
7c3df132 5980 ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n");
cbc8eb67 5981 ha->flags.running_gold_fw = 1;
cbc8eb67 5982 return rval;
eaac30be
AV		 5983}
5984
18c6c127 5985void
e315cd28 5986qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha)
18c6c127
AV		 5987{
5988 int ret, retries;
e315cd28 5989 struct qla_hw_data *ha = vha->hw;
18c6c127 5990
85880801
AV		 5991 if (ha->flags.pci_channel_io_perm_failure)
5992 return;
e428924c 5993 if (!IS_FWI2_CAPABLE(ha))
18c6c127 5994 return;
75edf81d
AV		 5995 if (!ha->fw_major_version)
5996 return;
18c6c127 5997
e315cd28 5998 ret = qla2x00_stop_firmware(vha);
7c7f1f29 5999 for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&
b469a7cb 6000 ret != QLA_INVALID_COMMAND && retries ; retries--) {
e315cd28
AC		 6001 ha->isp_ops->reset_chip(vha);
6002 if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS)
18c6c127 6003 continue;
e315cd28 6004 if (qla2x00_setup_chip(vha) != QLA_SUCCESS)
18c6c127 6005 continue;
7c3df132
SK		 6006 ql_log(ql_log_info, vha, 0x8015,
6007 "Attempting retry of stop-firmware command.\n");
e315cd28 6008 ret = qla2x00_stop_firmware(vha);
18c6c127
AV		 6009 }
6010}
2c3dfe3f
SJ		 6011
6012int
e315cd28 6013qla24xx_configure_vhba(scsi_qla_host_t *vha)
2c3dfe3f
SJ		 6014{
6015 int rval = QLA_SUCCESS;
0b91d116 6016 int rval2;
2c3dfe3f 6017 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28
AC		 6018 struct qla_hw_data *ha = vha->hw;
6019 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
67c2e93a
AC		 6020 struct req_que *req;
6021 struct rsp_que *rsp;
2c3dfe3f 6022
e315cd28 6023 if (!vha->vp_idx)
2c3dfe3f
SJ		 6024 return -EINVAL;
6025
e315cd28 6026 rval = qla2x00_fw_ready(base_vha);
d7459527
MH		 6027 if (vha->qpair)
6028 req = vha->qpair->req;
67c2e93a 6029 else
d7459527 6030 req = ha->req_q_map[0];
67c2e93a
AC		 6031 rsp = req->rsp;
6032
2c3dfe3f 6033 if (rval == QLA_SUCCESS) {
e315cd28 6034 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
73208dfd 6035 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
2c3dfe3f
SJ		 6036 }
6037
e315cd28 6038 vha->flags.management_server_logged_in = 0;
2c3dfe3f
SJ		 6039
6040 /* Login to SNS first */
0b91d116
CD		 6041 rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb,
6042 BIT_1);
6043 if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
6044 if (rval2 == QLA_MEMORY_ALLOC_FAILED)
6045 ql_dbg(ql_dbg_init, vha, 0x0120,
6046 "Failed SNS login: loop_id=%x, rval2=%d\n",
6047 NPH_SNS, rval2);
6048 else
6049 ql_dbg(ql_dbg_init, vha, 0x0103,
6050 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x "
6051 "mb[2]=%x mb[6]=%x mb[7]=%x.\n",
6052 NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]);
2c3dfe3f
SJ		 6053 return (QLA_FUNCTION_FAILED);
6054 }
6055
e315cd28
AC		 6056 atomic_set(&vha->loop_down_timer, 0);
6057 atomic_set(&vha->loop_state, LOOP_UP);
6058 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
6059 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
6060 rval = qla2x00_loop_resync(base_vha);
2c3dfe3f
SJ		 6061
6062 return rval;
6063}
4d4df193
HK		 6064
6065/* 84XX Support **************************************************************/
6066
6067static LIST_HEAD(qla_cs84xx_list);
6068static DEFINE_MUTEX(qla_cs84xx_mutex);
6069
6070static struct qla_chip_state_84xx *
e315cd28 6071qla84xx_get_chip(struct scsi_qla_host *vha)
4d4df193
HK		 6072{
6073 struct qla_chip_state_84xx *cs84xx;
e315cd28 6074 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 6075
6076 mutex_lock(&qla_cs84xx_mutex);
6077
6078 /* Find any shared 84xx chip. */
6079 list_for_each_entry(cs84xx, &qla_cs84xx_list, list) {
6080 if (cs84xx->bus == ha->pdev->bus) {
6081 kref_get(&cs84xx->kref);
6082 goto done;
6083 }
6084 }
6085
6086 cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL);
6087 if (!cs84xx)
6088 goto done;
6089
6090 kref_init(&cs84xx->kref);
6091 spin_lock_init(&cs84xx->access_lock);
6092 mutex_init(&cs84xx->fw_update_mutex);
6093 cs84xx->bus = ha->pdev->bus;
6094
6095 list_add_tail(&cs84xx->list, &qla_cs84xx_list);
6096done:
6097 mutex_unlock(&qla_cs84xx_mutex);
6098 return cs84xx;
6099}
6100
6101static void
6102__qla84xx_chip_release(struct kref *kref)
6103{
6104 struct qla_chip_state_84xx *cs84xx =
6105 container_of(kref, struct qla_chip_state_84xx, kref);
6106
6107 mutex_lock(&qla_cs84xx_mutex);
6108 list_del(&cs84xx->list);
6109 mutex_unlock(&qla_cs84xx_mutex);
6110 kfree(cs84xx);
6111}
6112
6113void
e315cd28 6114qla84xx_put_chip(struct scsi_qla_host *vha)
4d4df193 6115{
e315cd28 6116 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 6117 if (ha->cs84xx)
6118 kref_put(&ha->cs84xx->kref, __qla84xx_chip_release);
6119}
6120
6121static int
e315cd28 6122qla84xx_init_chip(scsi_qla_host_t *vha)
4d4df193
HK		 6123{
6124 int rval;
6125 uint16_t status[2];
e315cd28 6126 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 6127
6128 mutex_lock(&ha->cs84xx->fw_update_mutex);
6129
e315cd28 6130 rval = qla84xx_verify_chip(vha, status);
4d4df193
HK		 6131
6132 mutex_unlock(&ha->cs84xx->fw_update_mutex);
6133
6134 return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED:
6135 QLA_SUCCESS;
6136}
3a03eb79
AV		 6137
6138/* 81XX Support **************************************************************/
6139
6140int
6141qla81xx_nvram_config(scsi_qla_host_t *vha)
6142{
6143 int rval;
6144 struct init_cb_81xx *icb;
6145 struct nvram_81xx *nv;
6146 uint32_t *dptr;
6147 uint8_t *dptr1, *dptr2;
6148 uint32_t chksum;
6149 uint16_t cnt;
6150 struct qla_hw_data *ha = vha->hw;
6151
6152 rval = QLA_SUCCESS;
6153 icb = (struct init_cb_81xx *)ha->init_cb;
6154 nv = ha->nvram;
6155
6156 /* Determine NVRAM starting address. */
6157 ha->nvram_size = sizeof(struct nvram_81xx);
3a03eb79 6158 ha->vpd_size = FA_NVRAM_VPD_SIZE;
7ec0effd
AD		 6159 if (IS_P3P_TYPE(ha) || IS_QLA8031(ha))
6160 ha->vpd_size = FA_VPD_SIZE_82XX;
3a03eb79
AV		 6161
6162 /* Get VPD data into cache */
6163 ha->vpd = ha->nvram + VPD_OFFSET;
3d79038f
AV		 6164 ha->isp_ops->read_optrom(vha, ha->vpd, ha->flt_region_vpd << 2,
6165 ha->vpd_size);
3a03eb79
AV		 6166
6167 /* Get NVRAM data into cache and calculate checksum. */
3d79038f 6168 ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2,
3a03eb79 6169 ha->nvram_size);
3d79038f 6170 dptr = (uint32_t *)nv;
da08ef5c
JC		 6171 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++)
6172 chksum += le32_to_cpu(*dptr);
3a03eb79 6173
7c3df132
SK		 6174 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
6175 "Contents of NVRAM:\n");
6176 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
6177 (uint8_t *)nv, ha->nvram_size);
3a03eb79
AV		 6178
6179 /* Bad NVRAM data, set defaults parameters. */
6180 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
6181 || nv->id[3] != ' ' ||
ad950360 6182 nv->nvram_version < cpu_to_le16(ICB_VERSION)) {
3a03eb79 6183 /* Reset NVRAM data. */
7c3df132 6184 ql_log(ql_log_info, vha, 0x0073,
9e336520 6185 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132 6186 "version=0x%x.\n", chksum, nv->id[0],
3a03eb79 6187 le16_to_cpu(nv->nvram_version));
7c3df132
SK		 6188 ql_log(ql_log_info, vha, 0x0074,
6189 "Falling back to functioning (yet invalid -- WWPN) "
6190 "defaults.\n");
3a03eb79
AV		 6191
6192 /*
6193 * Set default initialization control block.
6194 */
6195 memset(nv, 0, ha->nvram_size);
ad950360
BVA		 6196 nv->nvram_version = cpu_to_le16(ICB_VERSION);
6197 nv->version = cpu_to_le16(ICB_VERSION);
98aee70d 6198 nv->frame_payload_size = 2048;
ad950360
BVA		 6199 nv->execution_throttle = cpu_to_le16(0xFFFF);
6200 nv->exchange_count = cpu_to_le16(0);
3a03eb79 6201 nv->port_name[0] = 0x21;
f73cb695 6202 nv->port_name[1] = 0x00 + ha->port_no + 1;
3a03eb79
AV		 6203 nv->port_name[2] = 0x00;
6204 nv->port_name[3] = 0xe0;
6205 nv->port_name[4] = 0x8b;
6206 nv->port_name[5] = 0x1c;
6207 nv->port_name[6] = 0x55;
6208 nv->port_name[7] = 0x86;
6209 nv->node_name[0] = 0x20;
6210 nv->node_name[1] = 0x00;
6211 nv->node_name[2] = 0x00;
6212 nv->node_name[3] = 0xe0;
6213 nv->node_name[4] = 0x8b;
6214 nv->node_name[5] = 0x1c;
6215 nv->node_name[6] = 0x55;
6216 nv->node_name[7] = 0x86;
ad950360
BVA		 6217 nv->login_retry_count = cpu_to_le16(8);
6218 nv->interrupt_delay_timer = cpu_to_le16(0);
6219 nv->login_timeout = cpu_to_le16(0);
3a03eb79 6220 nv->firmware_options_1 =
ad950360
BVA		 6221 cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
6222 nv->firmware_options_2 = cpu_to_le32(2 << 4);
6223 nv->firmware_options_2 |= cpu_to_le32(BIT_12);
6224 nv->firmware_options_3 = cpu_to_le32(2 << 13);
6225 nv->host_p = cpu_to_le32(BIT_11|BIT_10);
6226 nv->efi_parameters = cpu_to_le32(0);
3a03eb79 6227 nv->reset_delay = 5;
ad950360
BVA		 6228 nv->max_luns_per_target = cpu_to_le16(128);
6229 nv->port_down_retry_count = cpu_to_le16(30);
6230 nv->link_down_timeout = cpu_to_le16(180);
eeebcc92 6231 nv->enode_mac[0] = 0x00;
6246b8a1
GM		 6232 nv->enode_mac[1] = 0xC0;
6233 nv->enode_mac[2] = 0xDD;
3a03eb79
AV		 6234 nv->enode_mac[3] = 0x04;
6235 nv->enode_mac[4] = 0x05;
f73cb695 6236 nv->enode_mac[5] = 0x06 + ha->port_no + 1;
3a03eb79
AV		 6237
6238 rval = 1;
6239 }
6240
9e522cd8
AE		 6241 if (IS_T10_PI_CAPABLE(ha))
6242 nv->frame_payload_size &= ~7;
6243
aa230bc5
AE		 6244 qlt_81xx_config_nvram_stage1(vha, nv);
6245
3a03eb79 6246 /* Reset Initialization control block */
773120e4 6247 memset(icb, 0, ha->init_cb_size);
3a03eb79
AV		 6248
6249 /* Copy 1st segment. */
6250 dptr1 = (uint8_t *)icb;
6251 dptr2 = (uint8_t *)&nv->version;
6252 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
6253 while (cnt--)
6254 *dptr1++ = *dptr2++;
6255
6256 icb->login_retry_count = nv->login_retry_count;
6257
6258 /* Copy 2nd segment. */
6259 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
6260 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
6261 cnt = (uint8_t *)&icb->reserved_5 -
6262 (uint8_t *)&icb->interrupt_delay_timer;
6263 while (cnt--)
6264 *dptr1++ = *dptr2++;
6265
6266 memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac));
6267 /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */
6268 if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) {
69e5f1ea
AV		 6269 icb->enode_mac[0] = 0x00;
6270 icb->enode_mac[1] = 0xC0;
6271 icb->enode_mac[2] = 0xDD;
3a03eb79
AV		 6272 icb->enode_mac[3] = 0x04;
6273 icb->enode_mac[4] = 0x05;
f73cb695 6274 icb->enode_mac[5] = 0x06 + ha->port_no + 1;
3a03eb79
AV		 6275 }
6276
b64b0e8f
AV		 6277 /* Use extended-initialization control block. */
6278 memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb));
6279
3a03eb79
AV		 6280 /*
6281 * Setup driver NVRAM options.
6282 */
6283 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
a9083016 6284 "QLE8XXX");
3a03eb79 6285
aa230bc5
AE		 6286 qlt_81xx_config_nvram_stage2(vha, icb);
6287
3a03eb79 6288 /* Use alternate WWN? */
ad950360 6289 if (nv->host_p & cpu_to_le32(BIT_15)) {
3a03eb79
AV		 6290 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
6291 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
6292 }
6293
6294 /* Prepare nodename */
ad950360 6295 if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) {
3a03eb79
AV		 6296 /*
6297 * Firmware will apply the following mask if the nodename was
6298 * not provided.
6299 */
6300 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
6301 icb->node_name[0] &= 0xF0;
6302 }
6303
6304 /* Set host adapter parameters. */
6305 ha->flags.disable_risc_code_load = 0;
6306 ha->flags.enable_lip_reset = 0;
6307 ha->flags.enable_lip_full_login =
6308 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
6309 ha->flags.enable_target_reset =
6310 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
6311 ha->flags.enable_led_scheme = 0;
6312 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
6313
6314 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
6315 (BIT_6 | BIT_5 | BIT_4)) >> 4;
6316
6317 /* save HBA serial number */
6318 ha->serial0 = icb->port_name[5];
6319 ha->serial1 = icb->port_name[6];
6320 ha->serial2 = icb->port_name[7];
6321 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
6322 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
6323
ad950360 6324 icb->execution_throttle = cpu_to_le16(0xFFFF);
3a03eb79
AV		 6325
6326 ha->retry_count = le16_to_cpu(nv->login_retry_count);
6327
6328 /* Set minimum login_timeout to 4 seconds. */
6329 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
6330 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
6331 if (le16_to_cpu(nv->login_timeout) < 4)
ad950360 6332 nv->login_timeout = cpu_to_le16(4);
3a03eb79 6333 ha->login_timeout = le16_to_cpu(nv->login_timeout);
3a03eb79
AV		 6334
6335 /* Set minimum RATOV to 100 tenths of a second. */
6336 ha->r_a_tov = 100;
6337
6338 ha->loop_reset_delay = nv->reset_delay;
6339
6340 /* Link Down Timeout = 0:
6341 *
7ec0effd 6342 * When Port Down timer expires we will start returning
3a03eb79
AV		 6343 * I/O's to OS with "DID_NO_CONNECT".
6344 *
6345 * Link Down Timeout != 0:
6346 *
6347 * The driver waits for the link to come up after link down
6348 * before returning I/Os to OS with "DID_NO_CONNECT".
6349 */
6350 if (le16_to_cpu(nv->link_down_timeout) == 0) {
6351 ha->loop_down_abort_time =
6352 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
6353 } else {
6354 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
6355 ha->loop_down_abort_time =
6356 (LOOP_DOWN_TIME - ha->link_down_timeout);
6357 }
6358
6359 /* Need enough time to try and get the port back. */
6360 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
6361 if (qlport_down_retry)
6362 ha->port_down_retry_count = qlport_down_retry;
6363
6364 /* Set login_retry_count */
6365 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
6366 if (ha->port_down_retry_count ==
6367 le16_to_cpu(nv->port_down_retry_count) &&
6368 ha->port_down_retry_count > 3)
6369 ha->login_retry_count = ha->port_down_retry_count;
6370 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
6371 ha->login_retry_count = ha->port_down_retry_count;
6372 if (ql2xloginretrycount)
6373 ha->login_retry_count = ql2xloginretrycount;
6374
6246b8a1 6375 /* if not running MSI-X we need handshaking on interrupts */
f73cb695 6376 if (!vha->hw->flags.msix_enabled && (IS_QLA83XX(ha) || IS_QLA27XX(ha)))
ad950360 6377 icb->firmware_options_2 |= cpu_to_le32(BIT_22);
6246b8a1 6378
3a03eb79
AV		 6379 /* Enable ZIO. */
6380 if (!vha->flags.init_done) {
6381 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
6382 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
6383 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
6384 le16_to_cpu(icb->interrupt_delay_timer): 2;
6385 }
ad950360 6386 icb->firmware_options_2 &= cpu_to_le32(
3a03eb79
AV		 6387 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
6388 vha->flags.process_response_queue = 0;
6389 if (ha->zio_mode != QLA_ZIO_DISABLED) {
6390 ha->zio_mode = QLA_ZIO_MODE_6;
6391
7c3df132 6392 ql_log(ql_log_info, vha, 0x0075,
3a03eb79 6393 "ZIO mode %d enabled; timer delay (%d us).\n",
7c3df132
SK		 6394 ha->zio_mode,
6395 ha->zio_timer * 100);
3a03eb79
AV		 6396
6397 icb->firmware_options_2 |= cpu_to_le32(
6398 (uint32_t)ha->zio_mode);
6399 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
6400 vha->flags.process_response_queue = 1;
6401 }
6402
6403 if (rval) {
7c3df132
SK		 6404 ql_log(ql_log_warn, vha, 0x0076,
6405 "NVRAM configuration failed.\n");
3a03eb79
AV		 6406 }
6407 return (rval);
6408}
6409
a9083016
GM		 6410int
6411qla82xx_restart_isp(scsi_qla_host_t *vha)
6412{
6413 int status, rval;
a9083016
GM		 6414 struct qla_hw_data *ha = vha->hw;
6415 struct req_que *req = ha->req_q_map[0];
6416 struct rsp_que *rsp = ha->rsp_q_map[0];
6417 struct scsi_qla_host *vp;
feafb7b1 6418 unsigned long flags;
a9083016
GM		 6419
6420 status = qla2x00_init_rings(vha);
6421 if (!status) {
6422 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
6423 ha->flags.chip_reset_done = 1;
6424
6425 status = qla2x00_fw_ready(vha);
6426 if (!status) {
a9083016
GM		 6427 /* Issue a marker after FW becomes ready. */
6428 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
a9083016 6429 vha->flags.online = 1;
7108b76e 6430 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
a9083016
GM		 6431 }
6432
6433 /* if no cable then assume it's good */
6434 if ((vha->device_flags & DFLG_NO_CABLE))
6435 status = 0;
a9083016
GM		 6436 }
6437
6438 if (!status) {
6439 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
6440
6441 if (!atomic_read(&vha->loop_down_timer)) {
6442 /*
6443 * Issue marker command only when we are going
6444 * to start the I/O .
6445 */
6446 vha->marker_needed = 1;
6447 }
6448
a9083016
GM		 6449 ha->isp_ops->enable_intrs(ha);
6450
6451 ha->isp_abort_cnt = 0;
6452 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
6453
53296788 6454 /* Update the firmware version */
3173167f 6455 status = qla82xx_check_md_needed(vha);
53296788 6456
a9083016
GM		 6457 if (ha->fce) {
6458 ha->flags.fce_enabled = 1;
6459 memset(ha->fce, 0,
6460 fce_calc_size(ha->fce_bufs));
6461 rval = qla2x00_enable_fce_trace(vha,
6462 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
6463 &ha->fce_bufs);
6464 if (rval) {
cfb0919c 6465 ql_log(ql_log_warn, vha, 0x8001,
7c3df132
SK		 6466 "Unable to reinitialize FCE (%d).\n",
6467 rval);
a9083016
GM		 6468 ha->flags.fce_enabled = 0;
6469 }
6470 }
6471
6472 if (ha->eft) {
6473 memset(ha->eft, 0, EFT_SIZE);
6474 rval = qla2x00_enable_eft_trace(vha,
6475 ha->eft_dma, EFT_NUM_BUFFERS);
6476 if (rval) {
cfb0919c 6477 ql_log(ql_log_warn, vha, 0x8010,
7c3df132
SK		 6478 "Unable to reinitialize EFT (%d).\n",
6479 rval);
a9083016
GM		 6480 }
6481 }
a9083016
GM		 6482 }
6483
6484 if (!status) {
cfb0919c 6485 ql_dbg(ql_dbg_taskm, vha, 0x8011,
7c3df132 6486 "qla82xx_restart_isp succeeded.\n");
feafb7b1
AE		 6487
6488 spin_lock_irqsave(&ha->vport_slock, flags);
6489 list_for_each_entry(vp, &ha->vp_list, list) {
6490 if (vp->vp_idx) {
6491 atomic_inc(&vp->vref_count);
6492 spin_unlock_irqrestore(&ha->vport_slock, flags);
6493
a9083016 6494 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 6495
6496 spin_lock_irqsave(&ha->vport_slock, flags);
6497 atomic_dec(&vp->vref_count);
6498 }
a9083016 6499 }
feafb7b1
AE		 6500 spin_unlock_irqrestore(&ha->vport_slock, flags);
6501
a9083016 6502 } else {
cfb0919c 6503 ql_log(ql_log_warn, vha, 0x8016,
7c3df132 6504 "qla82xx_restart_isp **** FAILED ****.\n");
a9083016
GM		 6505 }
6506
6507 return status;
6508}
6509
3a03eb79 6510void
ae97c91e 6511qla81xx_update_fw_options(scsi_qla_host_t *vha)
3a03eb79 6512{
ae97c91e
AV		 6513 struct qla_hw_data *ha = vha->hw;
6514
f198cafa
HM		 6515 /* Hold status IOCBs until ABTS response received. */
6516 if (ql2xfwholdabts)
6517 ha->fw_options[3] |= BIT_12;
6518
088d09d4
GM		 6519 /* Set Retry FLOGI in case of P2P connection */
6520 if (ha->operating_mode == P2P) {
6521 ha->fw_options[2] |= BIT_3;
6522 ql_dbg(ql_dbg_disc, vha, 0x2103,
6523 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
6524 __func__, ha->fw_options[2]);
6525 }
6526
ae97c91e 6527 if (!ql2xetsenable)
f198cafa 6528 goto out;
ae97c91e
AV		 6529
6530 /* Enable ETS Burst. */
6531 memset(ha->fw_options, 0, sizeof(ha->fw_options));
6532 ha->fw_options[2] |= BIT_9;
f198cafa 6533out:
ae97c91e 6534 qla2x00_set_fw_options(vha, ha->fw_options);
3a03eb79 6535}
09ff701a
SR		 6536
6537/*
6538 * qla24xx_get_fcp_prio
6539 * Gets the fcp cmd priority value for the logged in port.
6540 * Looks for a match of the port descriptors within
6541 * each of the fcp prio config entries. If a match is found,
6542 * the tag (priority) value is returned.
6543 *
6544 * Input:
21090cbe 6545 * vha = scsi host structure pointer.
09ff701a
SR		 6546 * fcport = port structure pointer.
6547 *
6548 * Return:
6c452a45 6549 * non-zero (if found)
f28a0a96 6550 * -1 (if not found)
09ff701a
SR		 6551 *
6552 * Context:
6553 * Kernel context
6554 */
f28a0a96 6555static int
09ff701a
SR		 6556qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
6557{
6558 int i, entries;
6559 uint8_t pid_match, wwn_match;
f28a0a96 6560 int priority;
09ff701a
SR		 6561 uint32_t pid1, pid2;
6562 uint64_t wwn1, wwn2;
6563 struct qla_fcp_prio_entry *pri_entry;
6564 struct qla_hw_data *ha = vha->hw;
6565
6566 if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled)
f28a0a96 6567 return -1;
09ff701a 6568
f28a0a96 6569 priority = -1;
09ff701a
SR		 6570 entries = ha->fcp_prio_cfg->num_entries;
6571 pri_entry = &ha->fcp_prio_cfg->entry[0];
6572
6573 for (i = 0; i < entries; i++) {
6574 pid_match = wwn_match = 0;
6575
6576 if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) {
6577 pri_entry++;
6578 continue;
6579 }
6580
6581 /* check source pid for a match */
6582 if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) {
6583 pid1 = pri_entry->src_pid & INVALID_PORT_ID;
6584 pid2 = vha->d_id.b24 & INVALID_PORT_ID;
6585 if (pid1 == INVALID_PORT_ID)
6586 pid_match++;
6587 else if (pid1 == pid2)
6588 pid_match++;
6589 }
6590
6591 /* check destination pid for a match */
6592 if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) {
6593 pid1 = pri_entry->dst_pid & INVALID_PORT_ID;
6594 pid2 = fcport->d_id.b24 & INVALID_PORT_ID;
6595 if (pid1 == INVALID_PORT_ID)
6596 pid_match++;
6597 else if (pid1 == pid2)
6598 pid_match++;
6599 }
6600
6601 /* check source WWN for a match */
6602 if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) {
6603 wwn1 = wwn_to_u64(vha->port_name);
6604 wwn2 = wwn_to_u64(pri_entry->src_wwpn);
6605 if (wwn2 == (uint64_t)-1)
6606 wwn_match++;
6607 else if (wwn1 == wwn2)
6608 wwn_match++;
6609 }
6610
6611 /* check destination WWN for a match */
6612 if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) {
6613 wwn1 = wwn_to_u64(fcport->port_name);
6614 wwn2 = wwn_to_u64(pri_entry->dst_wwpn);
6615 if (wwn2 == (uint64_t)-1)
6616 wwn_match++;
6617 else if (wwn1 == wwn2)
6618 wwn_match++;
6619 }
6620
6621 if (pid_match == 2 || wwn_match == 2) {
6622 /* Found a matching entry */
6623 if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID)
6624 priority = pri_entry->tag;
6625 break;
6626 }
6627
6628 pri_entry++;
6629 }
6630
6631 return priority;
6632}
6633
6634/*
6635 * qla24xx_update_fcport_fcp_prio
6636 * Activates fcp priority for the logged in fc port
6637 *
6638 * Input:
21090cbe 6639 * vha = scsi host structure pointer.
09ff701a
SR		 6640 * fcp = port structure pointer.
6641 *
6642 * Return:
6643 * QLA_SUCCESS or QLA_FUNCTION_FAILED
6644 *
6645 * Context:
6646 * Kernel context.
6647 */
6648int
21090cbe 6649qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
09ff701a
SR		 6650{
6651 int ret;
f28a0a96 6652 int priority;
09ff701a
SR		 6653 uint16_t mb[5];
6654
21090cbe
MI		 6655 if (fcport->port_type != FCT_TARGET ||
6656 fcport->loop_id == FC_NO_LOOP_ID)
09ff701a
SR		 6657 return QLA_FUNCTION_FAILED;
6658
21090cbe 6659 priority = qla24xx_get_fcp_prio(vha, fcport);
f28a0a96
AV		 6660 if (priority < 0)
6661 return QLA_FUNCTION_FAILED;
6662
7ec0effd 6663 if (IS_P3P_TYPE(vha->hw)) {
a00f6296
SK		 6664 fcport->fcp_prio = priority & 0xf;
6665 return QLA_SUCCESS;
6666 }
6667
21090cbe 6668 ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb);
cfb0919c
CD		 6669 if (ret == QLA_SUCCESS) {
6670 if (fcport->fcp_prio != priority)
6671 ql_dbg(ql_dbg_user, vha, 0x709e,
6672 "Updated FCP_CMND priority - value=%d loop_id=%d "
6673 "port_id=%02x%02x%02x.\n", priority,
6674 fcport->loop_id, fcport->d_id.b.domain,
6675 fcport->d_id.b.area, fcport->d_id.b.al_pa);
a00f6296 6676 fcport->fcp_prio = priority & 0xf;
cfb0919c 6677 } else
7c3df132 6678 ql_dbg(ql_dbg_user, vha, 0x704f,
cfb0919c
CD		 6679 "Unable to update FCP_CMND priority - ret=0x%x for "
6680 "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id,
6681 fcport->d_id.b.domain, fcport->d_id.b.area,
6682 fcport->d_id.b.al_pa);
09ff701a
SR		 6683 return ret;
6684}
6685
6686/*
6687 * qla24xx_update_all_fcp_prio
6688 * Activates fcp priority for all the logged in ports
6689 *
6690 * Input:
6691 * ha = adapter block pointer.
6692 *
6693 * Return:
6694 * QLA_SUCCESS or QLA_FUNCTION_FAILED
6695 *
6696 * Context:
6697 * Kernel context.
6698 */
6699int
6700qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha)
6701{
6702 int ret;
6703 fc_port_t *fcport;
6704
6705 ret = QLA_FUNCTION_FAILED;
6706 /* We need to set priority for all logged in ports */
6707 list_for_each_entry(fcport, &vha->vp_fcports, list)
6708 ret = qla24xx_update_fcport_fcp_prio(vha, fcport);
6709
6710 return ret;
6711}
d7459527
MH		 6712
6713struct qla_qpair *qla2xxx_create_qpair(struct scsi_qla_host *vha, int qos, int vp_idx)
6714{
6715 int rsp_id = 0;
6716 int req_id = 0;
6717 int i;
6718 struct qla_hw_data *ha = vha->hw;
6719 uint16_t qpair_id = 0;
6720 struct qla_qpair *qpair = NULL;
6721 struct qla_msix_entry *msix;
6722
6723 if (!(ha->fw_attributes & BIT_6) || !ha->flags.msix_enabled) {
6724 ql_log(ql_log_warn, vha, 0x00181,
6725 "FW/Driver is not multi-queue capable.\n");
6726 return NULL;
6727 }
6728
6729 if (ql2xmqsupport) {
6730 qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
6731 if (qpair == NULL) {
6732 ql_log(ql_log_warn, vha, 0x0182,
6733 "Failed to allocate memory for queue pair.\n");
6734 return NULL;
6735 }
6736 memset(qpair, 0, sizeof(struct qla_qpair));
6737
6738 qpair->hw = vha->hw;
6739
6740 /* Assign available que pair id */
6741 mutex_lock(&ha->mq_lock);
6742 qpair_id = find_first_zero_bit(ha->qpair_qid_map, ha->max_qpairs);
6743 if (qpair_id >= ha->max_qpairs) {
6744 mutex_unlock(&ha->mq_lock);
6745 ql_log(ql_log_warn, vha, 0x0183,
6746 "No resources to create additional q pair.\n");
6747 goto fail_qid_map;
6748 }
6749 set_bit(qpair_id, ha->qpair_qid_map);
6750 ha->queue_pair_map[qpair_id] = qpair;
6751 qpair->id = qpair_id;
6752 qpair->vp_idx = vp_idx;
6753
6754 for (i = 0; i < ha->msix_count; i++) {
093df737 6755 msix = &ha->msix_entries[i];
d7459527
MH		 6756 if (msix->in_use)
6757 continue;
6758 qpair->msix = msix;
6759 ql_log(ql_dbg_multiq, vha, 0xc00f,
6760 "Vector %x selected for qpair\n", msix->vector);
6761 break;
6762 }
6763 if (!qpair->msix) {
6764 ql_log(ql_log_warn, vha, 0x0184,
6765 "Out of MSI-X vectors!.\n");
6766 goto fail_msix;
6767 }
6768
6769 qpair->msix->in_use = 1;
6770 list_add_tail(&qpair->qp_list_elem, &vha->qp_list);
6771
6772 mutex_unlock(&ha->mq_lock);
6773
6774 /* Create response queue first */
6775 rsp_id = qla25xx_create_rsp_que(ha, 0, 0, 0, qpair);
6776 if (!rsp_id) {
6777 ql_log(ql_log_warn, vha, 0x0185,
6778 "Failed to create response queue.\n");
6779 goto fail_rsp;
6780 }
6781
6782 qpair->rsp = ha->rsp_q_map[rsp_id];
6783
6784 /* Create request queue */
6785 req_id = qla25xx_create_req_que(ha, 0, vp_idx, 0, rsp_id, qos);
6786 if (!req_id) {
6787 ql_log(ql_log_warn, vha, 0x0186,
6788 "Failed to create request queue.\n");
6789 goto fail_req;
6790 }
6791
6792 qpair->req = ha->req_q_map[req_id];
6793 qpair->rsp->req = qpair->req;
6794
6795 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
6796 if (ha->fw_attributes & BIT_4)
6797 qpair->difdix_supported = 1;
6798 }
6799
6800 qpair->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
6801 if (!qpair->srb_mempool) {
6802 ql_log(ql_log_warn, vha, 0x0191,
6803 "Failed to create srb mempool for qpair %d\n",
6804 qpair->id);
6805 goto fail_mempool;
6806 }
6807
6808 /* Mark as online */
6809 qpair->online = 1;
6810
6811 if (!vha->flags.qpairs_available)
6812 vha->flags.qpairs_available = 1;
6813
6814 ql_dbg(ql_dbg_multiq, vha, 0xc00d,
6815 "Request/Response queue pair created, id %d\n",
6816 qpair->id);
6817 ql_dbg(ql_dbg_init, vha, 0x0187,
6818 "Request/Response queue pair created, id %d\n",
6819 qpair->id);
6820 }
6821 return qpair;
6822
6823fail_mempool:
6824fail_req:
6825 qla25xx_delete_rsp_que(vha, qpair->rsp);
6826fail_rsp:
6827 mutex_lock(&ha->mq_lock);
6828 qpair->msix->in_use = 0;
6829 list_del(&qpair->qp_list_elem);
6830 if (list_empty(&vha->qp_list))
6831 vha->flags.qpairs_available = 0;
6832fail_msix:
6833 ha->queue_pair_map[qpair_id] = NULL;
6834 clear_bit(qpair_id, ha->qpair_qid_map);
6835 mutex_unlock(&ha->mq_lock);
6836fail_qid_map:
6837 kfree(qpair);
6838 return NULL;
6839}
6840
6841int qla2xxx_delete_qpair(struct scsi_qla_host *vha, struct qla_qpair *qpair)
6842{
6843 int ret;
6844 struct qla_hw_data *ha = qpair->hw;
6845
6846 qpair->delete_in_progress = 1;
6847 while (atomic_read(&qpair->ref_count))
6848 msleep(500);
6849
6850 ret = qla25xx_delete_req_que(vha, qpair->req);
6851 if (ret != QLA_SUCCESS)
6852 goto fail;
6853 ret = qla25xx_delete_rsp_que(vha, qpair->rsp);
6854 if (ret != QLA_SUCCESS)
6855 goto fail;
6856
6857 mutex_lock(&ha->mq_lock);
6858 ha->queue_pair_map[qpair->id] = NULL;
6859 clear_bit(qpair->id, ha->qpair_qid_map);
6860 list_del(&qpair->qp_list_elem);
6861 if (list_empty(&vha->qp_list))
6862 vha->flags.qpairs_available = 0;
6863 mempool_destroy(qpair->srb_mempool);
6864 kfree(qpair);
6865 mutex_unlock(&ha->mq_lock);
6866
6867 return QLA_SUCCESS;
6868fail:
6869 return ret;
6870}
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