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[SCSI] qla2xxx: Don't process state change aen for reset owner.
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / qla2xxx / qla_init.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
1e63395c 3 * Copyright (c) 2003-2013 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
73208dfd 8#include "qla_gbl.h"
1da177e4
LT		 9
10#include <linux/delay.h>
5a0e3ad6 11#include <linux/slab.h>
0107109e 12#include <linux/vmalloc.h>
1da177e4
LT		 13
14#include "qla_devtbl.h"
15
4e08df3f
DM		 16#ifdef CONFIG_SPARC
17#include <asm/prom.h>
4e08df3f
DM		 18#endif
19
2d70c103
NB		 20#include <target/target_core_base.h>
21#include "qla_target.h"
22
1da177e4
LT		 23/*
24* QLogic ISP2x00 Hardware Support Function Prototypes.
25*/
1da177e4 26static int qla2x00_isp_firmware(scsi_qla_host_t *);
1da177e4 27static int qla2x00_setup_chip(scsi_qla_host_t *);
1da177e4
LT		 28static int qla2x00_init_rings(scsi_qla_host_t *);
29static int qla2x00_fw_ready(scsi_qla_host_t *);
30static int qla2x00_configure_hba(scsi_qla_host_t *);
1da177e4
LT		 31static int qla2x00_configure_loop(scsi_qla_host_t *);
32static int qla2x00_configure_local_loop(scsi_qla_host_t *);
1da177e4
LT		 33static int qla2x00_configure_fabric(scsi_qla_host_t *);
34static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *, struct list_head *);
1da177e4
LT		 35static int qla2x00_fabric_dev_login(scsi_qla_host_t *, fc_port_t *,
36 uint16_t *);
1da177e4
LT		 37
38static int qla2x00_restart_isp(scsi_qla_host_t *);
1da177e4 39
4d4df193
HK		 40static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *);
41static int qla84xx_init_chip(scsi_qla_host_t *);
73208dfd 42static int qla25xx_init_queues(struct qla_hw_data *);
4d4df193 43
ac280b67
AV		 44/* SRB Extensions ---------------------------------------------------------- */
45
9ba56b95
GM		 46void
47qla2x00_sp_timeout(unsigned long __data)
ac280b67
AV		 48{
49 srb_t *sp = (srb_t *)__data;
4916392b 50 struct srb_iocb *iocb;
ac280b67
AV		 51 fc_port_t *fcport = sp->fcport;
52 struct qla_hw_data *ha = fcport->vha->hw;
53 struct req_que *req;
54 unsigned long flags;
55
56 spin_lock_irqsave(&ha->hardware_lock, flags);
57 req = ha->req_q_map[0];
58 req->outstanding_cmds[sp->handle] = NULL;
9ba56b95 59 iocb = &sp->u.iocb_cmd;
4916392b 60 iocb->timeout(sp);
9ba56b95 61 sp->free(fcport->vha, sp);
6ac52608 62 spin_unlock_irqrestore(&ha->hardware_lock, flags);
ac280b67
AV		 63}
64
9ba56b95
GM		 65void
66qla2x00_sp_free(void *data, void *ptr)
ac280b67 67{
9ba56b95
GM		 68 srb_t *sp = (srb_t *)ptr;
69 struct srb_iocb *iocb = &sp->u.iocb_cmd;
70 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
ac280b67 71
4d97cc53 72 del_timer(&iocb->timer);
b00ee7d7 73 qla2x00_rel_sp(vha, sp);
ac280b67
AV		 74}
75
ac280b67
AV		 76/* Asynchronous Login/Logout Routines -------------------------------------- */
77
a9b6f722 78unsigned long
5b91490e
AV		 79qla2x00_get_async_timeout(struct scsi_qla_host *vha)
80{
81 unsigned long tmo;
82 struct qla_hw_data *ha = vha->hw;
83
84 /* Firmware should use switch negotiated r_a_tov for timeout. */
85 tmo = ha->r_a_tov / 10 * 2;
86 if (!IS_FWI2_CAPABLE(ha)) {
87 /*
88 * Except for earlier ISPs where the timeout is seeded from the
89 * initialization control block.
90 */
91 tmo = ha->login_timeout;
92 }
93 return tmo;
94}
ac280b67
AV		 95
96static void
9ba56b95 97qla2x00_async_iocb_timeout(void *data)
ac280b67 98{
9ba56b95 99 srb_t *sp = (srb_t *)data;
ac280b67 100 fc_port_t *fcport = sp->fcport;
ac280b67 101
7c3df132 102 ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
cfb0919c 103 "Async-%s timeout - hdl=%x portid=%02x%02x%02x.\n",
9ba56b95 104 sp->name, sp->handle, fcport->d_id.b.domain, fcport->d_id.b.area,
7c3df132 105 fcport->d_id.b.al_pa);
ac280b67 106
5ff1d584 107 fcport->flags &= ~FCF_ASYNC_SENT;
9ba56b95
GM		 108 if (sp->type == SRB_LOGIN_CMD) {
109 struct srb_iocb *lio = &sp->u.iocb_cmd;
ac280b67 110 qla2x00_post_async_logout_work(fcport->vha, fcport, NULL);
6ac52608
AV		 111 /* Retry as needed. */
112 lio->u.logio.data[0] = MBS_COMMAND_ERROR;
113 lio->u.logio.data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
114 QLA_LOGIO_LOGIN_RETRIED : 0;
115 qla2x00_post_async_login_done_work(fcport->vha, fcport,
116 lio->u.logio.data);
117 }
ac280b67
AV		 118}
119
99b0bec7 120static void
9ba56b95 121qla2x00_async_login_sp_done(void *data, void *ptr, int res)
99b0bec7 122{
9ba56b95
GM		 123 srb_t *sp = (srb_t *)ptr;
124 struct srb_iocb *lio = &sp->u.iocb_cmd;
125 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
126
127 if (!test_bit(UNLOADING, &vha->dpc_flags))
128 qla2x00_post_async_login_done_work(sp->fcport->vha, sp->fcport,
129 lio->u.logio.data);
130 sp->free(sp->fcport->vha, sp);
99b0bec7
AV		 131}
132
ac280b67
AV		 133int
134qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport,
135 uint16_t *data)
136{
ac280b67 137 srb_t *sp;
4916392b 138 struct srb_iocb *lio;
ac280b67
AV		 139 int rval;
140
141 rval = QLA_FUNCTION_FAILED;
9ba56b95 142 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 143 if (!sp)
144 goto done;
145
9ba56b95
GM		 146 sp->type = SRB_LOGIN_CMD;
147 sp->name = "login";
148 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
149
150 lio = &sp->u.iocb_cmd;
3822263e 151 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 152 sp->done = qla2x00_async_login_sp_done;
4916392b 153 lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI;
ac280b67 154 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 155 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
ac280b67
AV		 156 rval = qla2x00_start_sp(sp);
157 if (rval != QLA_SUCCESS)
158 goto done_free_sp;
159
7c3df132 160 ql_dbg(ql_dbg_disc, vha, 0x2072,
cfb0919c
CD		 161 "Async-login - hdl=%x, loopid=%x portid=%02x%02x%02x "
162 "retries=%d.\n", sp->handle, fcport->loop_id,
163 fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
164 fcport->login_retry);
ac280b67
AV		 165 return rval;
166
167done_free_sp:
9ba56b95 168 sp->free(fcport->vha, sp);
ac280b67
AV		 169done:
170 return rval;
171}
172
99b0bec7 173static void
9ba56b95 174qla2x00_async_logout_sp_done(void *data, void *ptr, int res)
99b0bec7 175{
9ba56b95
GM		 176 srb_t *sp = (srb_t *)ptr;
177 struct srb_iocb *lio = &sp->u.iocb_cmd;
178 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
179
180 if (!test_bit(UNLOADING, &vha->dpc_flags))
181 qla2x00_post_async_logout_done_work(sp->fcport->vha, sp->fcport,
182 lio->u.logio.data);
183 sp->free(sp->fcport->vha, sp);
99b0bec7
AV		 184}
185
ac280b67
AV		 186int
187qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport)
188{
ac280b67 189 srb_t *sp;
4916392b 190 struct srb_iocb *lio;
ac280b67
AV		 191 int rval;
192
193 rval = QLA_FUNCTION_FAILED;
9ba56b95 194 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 195 if (!sp)
196 goto done;
197
9ba56b95
GM		 198 sp->type = SRB_LOGOUT_CMD;
199 sp->name = "logout";
200 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
201
202 lio = &sp->u.iocb_cmd;
3822263e 203 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 204 sp->done = qla2x00_async_logout_sp_done;
ac280b67
AV		 205 rval = qla2x00_start_sp(sp);
206 if (rval != QLA_SUCCESS)
207 goto done_free_sp;
208
7c3df132 209 ql_dbg(ql_dbg_disc, vha, 0x2070,
cfb0919c
CD		 210 "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
211 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
212 fcport->d_id.b.area, fcport->d_id.b.al_pa);
ac280b67
AV		 213 return rval;
214
215done_free_sp:
9ba56b95 216 sp->free(fcport->vha, sp);
ac280b67
AV		 217done:
218 return rval;
219}
220
5ff1d584 221static void
9ba56b95 222qla2x00_async_adisc_sp_done(void *data, void *ptr, int res)
5ff1d584 223{
9ba56b95
GM		 224 srb_t *sp = (srb_t *)ptr;
225 struct srb_iocb *lio = &sp->u.iocb_cmd;
226 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
227
228 if (!test_bit(UNLOADING, &vha->dpc_flags))
229 qla2x00_post_async_adisc_done_work(sp->fcport->vha, sp->fcport,
230 lio->u.logio.data);
231 sp->free(sp->fcport->vha, sp);
5ff1d584
AV		 232}
233
234int
235qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport,
236 uint16_t *data)
237{
5ff1d584 238 srb_t *sp;
4916392b 239 struct srb_iocb *lio;
5ff1d584
AV		 240 int rval;
241
242 rval = QLA_FUNCTION_FAILED;
9ba56b95 243 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
5ff1d584
AV		 244 if (!sp)
245 goto done;
246
9ba56b95
GM		 247 sp->type = SRB_ADISC_CMD;
248 sp->name = "adisc";
249 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
250
251 lio = &sp->u.iocb_cmd;
3822263e 252 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 253 sp->done = qla2x00_async_adisc_sp_done;
5ff1d584 254 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 255 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
5ff1d584
AV		 256 rval = qla2x00_start_sp(sp);
257 if (rval != QLA_SUCCESS)
258 goto done_free_sp;
259
7c3df132 260 ql_dbg(ql_dbg_disc, vha, 0x206f,
cfb0919c
CD		 261 "Async-adisc - hdl=%x loopid=%x portid=%02x%02x%02x.\n",
262 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
263 fcport->d_id.b.area, fcport->d_id.b.al_pa);
5ff1d584
AV		 264 return rval;
265
266done_free_sp:
9ba56b95 267 sp->free(fcport->vha, sp);
5ff1d584
AV		 268done:
269 return rval;
270}
271
3822263e 272static void
9ba56b95 273qla2x00_async_tm_cmd_done(void *data, void *ptr, int res)
3822263e 274{
9ba56b95
GM		 275 srb_t *sp = (srb_t *)ptr;
276 struct srb_iocb *iocb = &sp->u.iocb_cmd;
277 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
278 uint32_t flags;
279 uint16_t lun;
280 int rval;
3822263e 281
9ba56b95
GM		 282 if (!test_bit(UNLOADING, &vha->dpc_flags)) {
283 flags = iocb->u.tmf.flags;
284 lun = (uint16_t)iocb->u.tmf.lun;
285
286 /* Issue Marker IOCB */
287 rval = qla2x00_marker(vha, vha->hw->req_q_map[0],
288 vha->hw->rsp_q_map[0], sp->fcport->loop_id, lun,
289 flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
290
291 if ((rval != QLA_SUCCESS) || iocb->u.tmf.data) {
292 ql_dbg(ql_dbg_taskm, vha, 0x8030,
293 "TM IOCB failed (%x).\n", rval);
294 }
295 }
296 sp->free(sp->fcport->vha, sp);
3822263e
MI		 297}
298
299int
9ba56b95 300qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t tm_flags, uint32_t lun,
3822263e
MI		 301 uint32_t tag)
302{
303 struct scsi_qla_host *vha = fcport->vha;
3822263e 304 srb_t *sp;
3822263e
MI		 305 struct srb_iocb *tcf;
306 int rval;
307
308 rval = QLA_FUNCTION_FAILED;
9ba56b95 309 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
3822263e
MI		 310 if (!sp)
311 goto done;
312
9ba56b95
GM		 313 sp->type = SRB_TM_CMD;
314 sp->name = "tmf";
315 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
316
317 tcf = &sp->u.iocb_cmd;
318 tcf->u.tmf.flags = tm_flags;
3822263e
MI		 319 tcf->u.tmf.lun = lun;
320 tcf->u.tmf.data = tag;
321 tcf->timeout = qla2x00_async_iocb_timeout;
9ba56b95 322 sp->done = qla2x00_async_tm_cmd_done;
3822263e
MI		 323
324 rval = qla2x00_start_sp(sp);
325 if (rval != QLA_SUCCESS)
326 goto done_free_sp;
327
7c3df132 328 ql_dbg(ql_dbg_taskm, vha, 0x802f,
cfb0919c
CD		 329 "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
330 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
331 fcport->d_id.b.area, fcport->d_id.b.al_pa);
3822263e
MI		 332 return rval;
333
334done_free_sp:
9ba56b95 335 sp->free(fcport->vha, sp);
3822263e
MI		 336done:
337 return rval;
338}
339
4916392b 340void
ac280b67
AV		 341qla2x00_async_login_done(struct scsi_qla_host *vha, fc_port_t *fcport,
342 uint16_t *data)
343{
344 int rval;
ac280b67
AV		 345
346 switch (data[0]) {
347 case MBS_COMMAND_COMPLETE:
a4f92a32
AV		 348 /*
349 * Driver must validate login state - If PRLI not complete,
350 * force a relogin attempt via implicit LOGO, PLOGI, and PRLI
351 * requests.
352 */
353 rval = qla2x00_get_port_database(vha, fcport, 0);
0eba25df
AE		 354 if (rval == QLA_NOT_LOGGED_IN) {
355 fcport->flags &= ~FCF_ASYNC_SENT;
356 fcport->flags |= FCF_LOGIN_NEEDED;
357 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
358 break;
359 }
360
a4f92a32
AV		 361 if (rval != QLA_SUCCESS) {
362 qla2x00_post_async_logout_work(vha, fcport, NULL);
363 qla2x00_post_async_login_work(vha, fcport, NULL);
364 break;
365 }
99b0bec7 366 if (fcport->flags & FCF_FCP2_DEVICE) {
5ff1d584
AV		 367 qla2x00_post_async_adisc_work(vha, fcport, data);
368 break;
99b0bec7
AV		 369 }
370 qla2x00_update_fcport(vha, fcport);
ac280b67
AV		 371 break;
372 case MBS_COMMAND_ERROR:
5ff1d584 373 fcport->flags &= ~FCF_ASYNC_SENT;
ac280b67
AV		 374 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
375 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
376 else
80d79440 377 qla2x00_mark_device_lost(vha, fcport, 1, 0);
ac280b67
AV		 378 break;
379 case MBS_PORT_ID_USED:
380 fcport->loop_id = data[1];
6ac52608 381 qla2x00_post_async_logout_work(vha, fcport, NULL);
ac280b67
AV		 382 qla2x00_post_async_login_work(vha, fcport, NULL);
383 break;
384 case MBS_LOOP_ID_USED:
385 fcport->loop_id++;
386 rval = qla2x00_find_new_loop_id(vha, fcport);
387 if (rval != QLA_SUCCESS) {
5ff1d584 388 fcport->flags &= ~FCF_ASYNC_SENT;
80d79440 389 qla2x00_mark_device_lost(vha, fcport, 1, 0);
ac280b67
AV		 390 break;
391 }
392 qla2x00_post_async_login_work(vha, fcport, NULL);
393 break;
394 }
4916392b 395 return;
ac280b67
AV		 396}
397
4916392b 398void
ac280b67
AV		 399qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport,
400 uint16_t *data)
401{
402 qla2x00_mark_device_lost(vha, fcport, 1, 0);
4916392b 403 return;
ac280b67
AV		 404}
405
4916392b 406void
5ff1d584
AV		 407qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport,
408 uint16_t *data)
409{
410 if (data[0] == MBS_COMMAND_COMPLETE) {
411 qla2x00_update_fcport(vha, fcport);
412
4916392b 413 return;
5ff1d584
AV		 414 }
415
416 /* Retry login. */
417 fcport->flags &= ~FCF_ASYNC_SENT;
418 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
419 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
420 else
80d79440 421 qla2x00_mark_device_lost(vha, fcport, 1, 0);
5ff1d584 422
4916392b 423 return;
5ff1d584
AV		 424}
425
1da177e4
LT		 426/****************************************************************************/
427/* QLogic ISP2x00 Hardware Support Functions. */
428/****************************************************************************/
429
fa492630 430static int
7d613ac6
SV		 431qla83xx_nic_core_fw_load(scsi_qla_host_t *vha)
432{
433 int rval = QLA_SUCCESS;
434 struct qla_hw_data *ha = vha->hw;
435 uint32_t idc_major_ver, idc_minor_ver;
711aa7f7 436 uint16_t config[4];
7d613ac6
SV		 437
438 qla83xx_idc_lock(vha, 0);
439
440 /* SV: TODO: Assign initialization timeout from
441 * flash-info / other param
442 */
443 ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT;
444 ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT;
445
446 /* Set our fcoe function presence */
447 if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) {
448 ql_dbg(ql_dbg_p3p, vha, 0xb077,
449 "Error while setting DRV-Presence.\n");
450 rval = QLA_FUNCTION_FAILED;
451 goto exit;
452 }
453
454 /* Decide the reset ownership */
455 qla83xx_reset_ownership(vha);
456
457 /*
458 * On first protocol driver load:
459 * Init-Owner: Set IDC-Major-Version and Clear IDC-Lock-Recovery
460 * register.
461 * Others: Check compatibility with current IDC Major version.
462 */
463 qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver);
464 if (ha->flags.nic_core_reset_owner) {
465 /* Set IDC Major version */
466 idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION;
467 qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver);
468
469 /* Clearing IDC-Lock-Recovery register */
470 qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0);
471 } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) {
472 /*
473 * Clear further IDC participation if we are not compatible with
474 * the current IDC Major Version.
475 */
476 ql_log(ql_log_warn, vha, 0xb07d,
477 "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n",
478 idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION);
479 __qla83xx_clear_drv_presence(vha);
480 rval = QLA_FUNCTION_FAILED;
481 goto exit;
482 }
483 /* Each function sets its supported Minor version. */
484 qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver);
485 idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2));
486 qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver);
487
711aa7f7
SK		 488 if (ha->flags.nic_core_reset_owner) {
489 memset(config, 0, sizeof(config));
490 if (!qla81xx_get_port_config(vha, config))
491 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
492 QLA8XXX_DEV_READY);
493 }
494
7d613ac6
SV		 495 rval = qla83xx_idc_state_handler(vha);
496
497exit:
498 qla83xx_idc_unlock(vha, 0);
499
500 return rval;
501}
502
1da177e4
LT		 503/*
504* qla2x00_initialize_adapter
505* Initialize board.
506*
507* Input:
508* ha = adapter block pointer.
509*
510* Returns:
511* 0 = success
512*/
513int
e315cd28 514qla2x00_initialize_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 515{
516 int rval;
e315cd28 517 struct qla_hw_data *ha = vha->hw;
73208dfd 518 struct req_que *req = ha->req_q_map[0];
2533cf67 519
1da177e4 520 /* Clear adapter flags. */
e315cd28 521 vha->flags.online = 0;
2533cf67 522 ha->flags.chip_reset_done = 0;
e315cd28 523 vha->flags.reset_active = 0;
85880801
AV		 524 ha->flags.pci_channel_io_perm_failure = 0;
525 ha->flags.eeh_busy = 0;
794a5691 526 ha->flags.thermal_supported = 1;
e315cd28
AC		 527 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
528 atomic_set(&vha->loop_state, LOOP_DOWN);
529 vha->device_flags = DFLG_NO_CABLE;
530 vha->dpc_flags = 0;
531 vha->flags.management_server_logged_in = 0;
532 vha->marker_needed = 0;
1da177e4
LT		 533 ha->isp_abort_cnt = 0;
534 ha->beacon_blink_led = 0;
535
73208dfd
AC		 536 set_bit(0, ha->req_qid_map);
537 set_bit(0, ha->rsp_qid_map);
538
cfb0919c 539 ql_dbg(ql_dbg_init, vha, 0x0040,
7c3df132 540 "Configuring PCI space...\n");
e315cd28 541 rval = ha->isp_ops->pci_config(vha);
1da177e4 542 if (rval) {
7c3df132
SK		 543 ql_log(ql_log_warn, vha, 0x0044,
544 "Unable to configure PCI space.\n");
1da177e4
LT		 545 return (rval);
546 }
547
e315cd28 548 ha->isp_ops->reset_chip(vha);
1da177e4 549
e315cd28 550 rval = qla2xxx_get_flash_info(vha);
c00d8994 551 if (rval) {
7c3df132
SK		 552 ql_log(ql_log_fatal, vha, 0x004f,
553 "Unable to validate FLASH data.\n");
c00d8994
AV		 554 return (rval);
555 }
556
73208dfd 557 ha->isp_ops->get_flash_version(vha, req->ring);
cfb0919c 558 ql_dbg(ql_dbg_init, vha, 0x0061,
7c3df132 559 "Configure NVRAM parameters...\n");
0107109e 560
e315cd28 561 ha->isp_ops->nvram_config(vha);
1da177e4 562
d4c760c2
AV		 563 if (ha->flags.disable_serdes) {
564 /* Mask HBA via NVRAM settings? */
7c3df132
SK		 565 ql_log(ql_log_info, vha, 0x0077,
566 "Masking HBA WWPN "
d4c760c2 567 "%02x%02x%02x%02x%02x%02x%02x%02x (via NVRAM).\n",
e315cd28
AC		 568 vha->port_name[0], vha->port_name[1],
569 vha->port_name[2], vha->port_name[3],
570 vha->port_name[4], vha->port_name[5],
571 vha->port_name[6], vha->port_name[7]);
d4c760c2
AV		 572 return QLA_FUNCTION_FAILED;
573 }
574
cfb0919c 575 ql_dbg(ql_dbg_init, vha, 0x0078,
7c3df132 576 "Verifying loaded RISC code...\n");
1da177e4 577
e315cd28
AC		 578 if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) {
579 rval = ha->isp_ops->chip_diag(vha);
d19044c3
AV		 580 if (rval)
581 return (rval);
e315cd28 582 rval = qla2x00_setup_chip(vha);
d19044c3
AV		 583 if (rval)
584 return (rval);
1da177e4 585 }
a9083016 586
4d4df193 587 if (IS_QLA84XX(ha)) {
e315cd28 588 ha->cs84xx = qla84xx_get_chip(vha);
4d4df193 589 if (!ha->cs84xx) {
7c3df132 590 ql_log(ql_log_warn, vha, 0x00d0,
4d4df193
HK		 591 "Unable to configure ISP84XX.\n");
592 return QLA_FUNCTION_FAILED;
593 }
594 }
2d70c103
NB		 595
596 if (qla_ini_mode_enabled(vha))
597 rval = qla2x00_init_rings(vha);
598
2533cf67 599 ha->flags.chip_reset_done = 1;
1da177e4 600
9a069e19 601 if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) {
6c452a45 602 /* Issue verify 84xx FW IOCB to complete 84xx initialization */
9a069e19
GM		 603 rval = qla84xx_init_chip(vha);
604 if (rval != QLA_SUCCESS) {
7c3df132
SK		 605 ql_log(ql_log_warn, vha, 0x00d4,
606 "Unable to initialize ISP84XX.\n");
9a069e19
GM		 607 qla84xx_put_chip(vha);
608 }
609 }
610
7d613ac6
SV		 611 /* Load the NIC Core f/w if we are the first protocol driver. */
612 if (IS_QLA8031(ha)) {
613 rval = qla83xx_nic_core_fw_load(vha);
614 if (rval)
615 ql_log(ql_log_warn, vha, 0x0124,
616 "Error in initializing NIC Core f/w.\n");
617 }
618
2f0f3f4f
MI		 619 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
620 qla24xx_read_fcp_prio_cfg(vha);
09ff701a 621
3a11711a
JC		 622 qla2x00_set_driver_version(vha, QLA2XXX_VERSION);
623
1da177e4
LT		 624 return (rval);
625}
626
627/**
abbd8870 628 * qla2100_pci_config() - Setup ISP21xx PCI configuration registers.
1da177e4
LT		 629 * @ha: HA context
630 *
631 * Returns 0 on success.
632 */
abbd8870 633int
e315cd28 634qla2100_pci_config(scsi_qla_host_t *vha)
1da177e4 635{
a157b101 636 uint16_t w;
abbd8870 637 unsigned long flags;
e315cd28 638 struct qla_hw_data *ha = vha->hw;
3d71644c 639 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 640
1da177e4 641 pci_set_master(ha->pdev);
af6177d8 642 pci_try_set_mwi(ha->pdev);
1da177e4 643
1da177e4 644 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 645 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
abbd8870
AV		 646 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
647
737faece 648 pci_disable_rom(ha->pdev);
1da177e4
LT		 649
650 /* Get PCI bus information. */
651 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 652 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
1da177e4
LT		 653 spin_unlock_irqrestore(&ha->hardware_lock, flags);
654
abbd8870
AV		 655 return QLA_SUCCESS;
656}
1da177e4 657
abbd8870
AV		 658/**
659 * qla2300_pci_config() - Setup ISP23xx PCI configuration registers.
660 * @ha: HA context
661 *
662 * Returns 0 on success.
663 */
664int
e315cd28 665qla2300_pci_config(scsi_qla_host_t *vha)
abbd8870 666{
a157b101 667 uint16_t w;
abbd8870
AV		 668 unsigned long flags = 0;
669 uint32_t cnt;
e315cd28 670 struct qla_hw_data *ha = vha->hw;
3d71644c 671 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 672
abbd8870 673 pci_set_master(ha->pdev);
af6177d8 674 pci_try_set_mwi(ha->pdev);
1da177e4 675
abbd8870 676 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 677 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
1da177e4 678
abbd8870
AV		 679 if (IS_QLA2322(ha) || IS_QLA6322(ha))
680 w &= ~PCI_COMMAND_INTX_DISABLE;
a157b101 681 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1da177e4 682
abbd8870
AV		 683 /*
684 * If this is a 2300 card and not 2312, reset the
685 * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately,
686 * the 2310 also reports itself as a 2300 so we need to get the
687 * fb revision level -- a 6 indicates it really is a 2300 and
688 * not a 2310.
689 */
690 if (IS_QLA2300(ha)) {
691 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 692
abbd8870 693 /* Pause RISC. */
3d71644c 694 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
abbd8870 695 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 696 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
abbd8870 697 break;
1da177e4 698
abbd8870
AV		 699 udelay(10);
700 }
1da177e4 701
abbd8870 702 /* Select FPM registers. */
3d71644c
AV		 703 WRT_REG_WORD(&reg->ctrl_status, 0x20);
704 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 705
706 /* Get the fb rev level */
3d71644c 707 ha->fb_rev = RD_FB_CMD_REG(ha, reg);
abbd8870
AV		 708
709 if (ha->fb_rev == FPM_2300)
a157b101 710 pci_clear_mwi(ha->pdev);
abbd8870
AV		 711
712 /* Deselect FPM registers. */
3d71644c
AV		 713 WRT_REG_WORD(&reg->ctrl_status, 0x0);
714 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 715
716 /* Release RISC module. */
3d71644c 717 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
abbd8870 718 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 719 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0)
abbd8870
AV		 720 break;
721
722 udelay(10);
1da177e4 723 }
1da177e4 724
abbd8870
AV		 725 spin_unlock_irqrestore(&ha->hardware_lock, flags);
726 }
1da177e4 727
abbd8870
AV		 728 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
729
737faece 730 pci_disable_rom(ha->pdev);
1da177e4 731
abbd8870
AV		 732 /* Get PCI bus information. */
733 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 734 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 735 spin_unlock_irqrestore(&ha->hardware_lock, flags);
736
737 return QLA_SUCCESS;
1da177e4
LT		 738}
739
0107109e
AV		 740/**
741 * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers.
742 * @ha: HA context
743 *
744 * Returns 0 on success.
745 */
746int
e315cd28 747qla24xx_pci_config(scsi_qla_host_t *vha)
0107109e 748{
a157b101 749 uint16_t w;
0107109e 750 unsigned long flags = 0;
e315cd28 751 struct qla_hw_data *ha = vha->hw;
0107109e 752 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
0107109e
AV		 753
754 pci_set_master(ha->pdev);
af6177d8 755 pci_try_set_mwi(ha->pdev);
0107109e
AV		 756
757 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 758 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
0107109e
AV		 759 w &= ~PCI_COMMAND_INTX_DISABLE;
760 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
761
762 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
763
764 /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */
f85ec187
AV		 765 if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
766 pcix_set_mmrbc(ha->pdev, 2048);
0107109e
AV		 767
768 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 769 if (pci_is_pcie(ha->pdev))
5ffd3a52 770 pcie_set_readrq(ha->pdev, 4096);
0107109e 771
737faece 772 pci_disable_rom(ha->pdev);
0107109e 773
44c10138 774 ha->chip_revision = ha->pdev->revision;
a8488abe 775
0107109e
AV		 776 /* Get PCI bus information. */
777 spin_lock_irqsave(&ha->hardware_lock, flags);
778 ha->pci_attr = RD_REG_DWORD(&reg->ctrl_status);
779 spin_unlock_irqrestore(&ha->hardware_lock, flags);
780
781 return QLA_SUCCESS;
782}
783
c3a2f0df
AV		 784/**
785 * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers.
786 * @ha: HA context
787 *
788 * Returns 0 on success.
789 */
790int
e315cd28 791qla25xx_pci_config(scsi_qla_host_t *vha)
c3a2f0df
AV		 792{
793 uint16_t w;
e315cd28 794 struct qla_hw_data *ha = vha->hw;
c3a2f0df
AV		 795
796 pci_set_master(ha->pdev);
797 pci_try_set_mwi(ha->pdev);
798
799 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
800 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
801 w &= ~PCI_COMMAND_INTX_DISABLE;
802 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
803
804 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 805 if (pci_is_pcie(ha->pdev))
5ffd3a52 806 pcie_set_readrq(ha->pdev, 4096);
c3a2f0df 807
737faece 808 pci_disable_rom(ha->pdev);
c3a2f0df
AV		 809
810 ha->chip_revision = ha->pdev->revision;
811
812 return QLA_SUCCESS;
813}
814
1da177e4
LT		 815/**
816 * qla2x00_isp_firmware() - Choose firmware image.
817 * @ha: HA context
818 *
819 * Returns 0 on success.
820 */
821static int
e315cd28 822qla2x00_isp_firmware(scsi_qla_host_t *vha)
1da177e4
LT		 823{
824 int rval;
42e421b1
AV		 825 uint16_t loop_id, topo, sw_cap;
826 uint8_t domain, area, al_pa;
e315cd28 827 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 828
829 /* Assume loading risc code */
fa2a1ce5 830 rval = QLA_FUNCTION_FAILED;
1da177e4
LT		 831
832 if (ha->flags.disable_risc_code_load) {
7c3df132 833 ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n");
1da177e4
LT		 834
835 /* Verify checksum of loaded RISC code. */
e315cd28 836 rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address);
42e421b1
AV		 837 if (rval == QLA_SUCCESS) {
838 /* And, verify we are not in ROM code. */
e315cd28 839 rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa,
42e421b1
AV		 840 &area, &domain, &topo, &sw_cap);
841 }
1da177e4
LT		 842 }
843
7c3df132
SK		 844 if (rval)
845 ql_dbg(ql_dbg_init, vha, 0x007a,
846 "**** Load RISC code ****.\n");
1da177e4
LT		 847
848 return (rval);
849}
850
851/**
852 * qla2x00_reset_chip() - Reset ISP chip.
853 * @ha: HA context
854 *
855 * Returns 0 on success.
856 */
abbd8870 857void
e315cd28 858qla2x00_reset_chip(scsi_qla_host_t *vha)
1da177e4
LT		 859{
860 unsigned long flags = 0;
e315cd28 861 struct qla_hw_data *ha = vha->hw;
3d71644c 862 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 863 uint32_t cnt;
1da177e4
LT		 864 uint16_t cmd;
865
85880801
AV		 866 if (unlikely(pci_channel_offline(ha->pdev)))
867 return;
868
fd34f556 869 ha->isp_ops->disable_intrs(ha);
1da177e4
LT		 870
871 spin_lock_irqsave(&ha->hardware_lock, flags);
872
873 /* Turn off master enable */
874 cmd = 0;
875 pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd);
876 cmd &= ~PCI_COMMAND_MASTER;
877 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
878
879 if (!IS_QLA2100(ha)) {
880 /* Pause RISC. */
881 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
882 if (IS_QLA2200(ha) || IS_QLA2300(ha)) {
883 for (cnt = 0; cnt < 30000; cnt++) {
884 if ((RD_REG_WORD(&reg->hccr) &
885 HCCR_RISC_PAUSE) != 0)
886 break;
887 udelay(100);
888 }
889 } else {
890 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
891 udelay(10);
892 }
893
894 /* Select FPM registers. */
895 WRT_REG_WORD(&reg->ctrl_status, 0x20);
896 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
897
898 /* FPM Soft Reset. */
899 WRT_REG_WORD(&reg->fpm_diag_config, 0x100);
900 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
901
902 /* Toggle Fpm Reset. */
903 if (!IS_QLA2200(ha)) {
904 WRT_REG_WORD(&reg->fpm_diag_config, 0x0);
905 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
906 }
907
908 /* Select frame buffer registers. */
909 WRT_REG_WORD(&reg->ctrl_status, 0x10);
910 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
911
912 /* Reset frame buffer FIFOs. */
913 if (IS_QLA2200(ha)) {
914 WRT_FB_CMD_REG(ha, reg, 0xa000);
915 RD_FB_CMD_REG(ha, reg); /* PCI Posting. */
916 } else {
917 WRT_FB_CMD_REG(ha, reg, 0x00fc);
918
919 /* Read back fb_cmd until zero or 3 seconds max */
920 for (cnt = 0; cnt < 3000; cnt++) {
921 if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0)
922 break;
923 udelay(100);
924 }
925 }
926
927 /* Select RISC module registers. */
928 WRT_REG_WORD(&reg->ctrl_status, 0);
929 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
930
931 /* Reset RISC processor. */
932 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
933 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
934
935 /* Release RISC processor. */
936 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
937 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
938 }
939
940 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
941 WRT_REG_WORD(&reg->hccr, HCCR_CLR_HOST_INT);
942
943 /* Reset ISP chip. */
944 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
945
946 /* Wait for RISC to recover from reset. */
947 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
948 /*
949 * It is necessary to for a delay here since the card doesn't
950 * respond to PCI reads during a reset. On some architectures
951 * this will result in an MCA.
952 */
953 udelay(20);
954 for (cnt = 30000; cnt; cnt--) {
955 if ((RD_REG_WORD(&reg->ctrl_status) &
956 CSR_ISP_SOFT_RESET) == 0)
957 break;
958 udelay(100);
959 }
960 } else
961 udelay(10);
962
963 /* Reset RISC processor. */
964 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
965
966 WRT_REG_WORD(&reg->semaphore, 0);
967
968 /* Release RISC processor. */
969 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
970 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
971
972 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
973 for (cnt = 0; cnt < 30000; cnt++) {
ffb39f03 974 if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY)
1da177e4 975 break;
1da177e4
LT		 976
977 udelay(100);
978 }
979 } else
980 udelay(100);
981
982 /* Turn on master enable */
983 cmd |= PCI_COMMAND_MASTER;
984 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
985
986 /* Disable RISC pause on FPM parity error. */
987 if (!IS_QLA2100(ha)) {
988 WRT_REG_WORD(&reg->hccr, HCCR_DISABLE_PARITY_PAUSE);
989 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
990 }
991
992 spin_unlock_irqrestore(&ha->hardware_lock, flags);
993}
994
b1d46989
MI		 995/**
996 * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC.
997 *
998 * Returns 0 on success.
999 */
fa492630 1000static int
b1d46989
MI		 1001qla81xx_reset_mpi(scsi_qla_host_t *vha)
1002{
1003 uint16_t mb[4] = {0x1010, 0, 1, 0};
1004
6246b8a1
GM		 1005 if (!IS_QLA81XX(vha->hw))
1006 return QLA_SUCCESS;
1007
b1d46989
MI		 1008 return qla81xx_write_mpi_register(vha, mb);
1009}
1010
0107109e 1011/**
88c26663 1012 * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC.
0107109e
AV		 1013 * @ha: HA context
1014 *
1015 * Returns 0 on success.
1016 */
88c26663 1017static inline void
e315cd28 1018qla24xx_reset_risc(scsi_qla_host_t *vha)
0107109e
AV		 1019{
1020 unsigned long flags = 0;
e315cd28 1021 struct qla_hw_data *ha = vha->hw;
0107109e
AV		 1022 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1023 uint32_t cnt, d2;
335a1cc9 1024 uint16_t wd;
b1d46989 1025 static int abts_cnt; /* ISP abort retry counts */
0107109e 1026
0107109e
AV		 1027 spin_lock_irqsave(&ha->hardware_lock, flags);
1028
1029 /* Reset RISC. */
1030 WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
1031 for (cnt = 0; cnt < 30000; cnt++) {
1032 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
1033 break;
1034
1035 udelay(10);
1036 }
1037
1038 WRT_REG_DWORD(&reg->ctrl_status,
1039 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
335a1cc9 1040 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
88c26663 1041
335a1cc9 1042 udelay(100);
88c26663 1043 /* Wait for firmware to complete NVRAM accesses. */
88c26663
AV		 1044 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1045 for (cnt = 10000 ; cnt && d2; cnt--) {
1046 udelay(5);
1047 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1048 barrier();
1049 }
1050
335a1cc9 1051 /* Wait for soft-reset to complete. */
0107109e
AV		 1052 d2 = RD_REG_DWORD(&reg->ctrl_status);
1053 for (cnt = 6000000 ; cnt && (d2 & CSRX_ISP_SOFT_RESET); cnt--) {
1054 udelay(5);
1055 d2 = RD_REG_DWORD(&reg->ctrl_status);
1056 barrier();
1057 }
1058
b1d46989
MI		 1059 /* If required, do an MPI FW reset now */
1060 if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
1061 if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
1062 if (++abts_cnt < 5) {
1063 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1064 set_bit(MPI_RESET_NEEDED, &vha->dpc_flags);
1065 } else {
1066 /*
1067 * We exhausted the ISP abort retries. We have to
1068 * set the board offline.
1069 */
1070 abts_cnt = 0;
1071 vha->flags.online = 0;
1072 }
1073 }
1074 }
1075
0107109e
AV		 1076 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
1077 RD_REG_DWORD(&reg->hccr);
1078
1079 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
1080 RD_REG_DWORD(&reg->hccr);
1081
1082 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
1083 RD_REG_DWORD(&reg->hccr);
1084
1085 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1086 for (cnt = 6000000 ; cnt && d2; cnt--) {
1087 udelay(5);
1088 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1089 barrier();
1090 }
1091
1092 spin_unlock_irqrestore(&ha->hardware_lock, flags);
124f85e6
AV		 1093
1094 if (IS_NOPOLLING_TYPE(ha))
1095 ha->isp_ops->enable_intrs(ha);
0107109e
AV		 1096}
1097
4ea2c9c7
JC		 1098static void
1099qla25xx_read_risc_sema_reg(scsi_qla_host_t *vha, uint32_t *data)
1100{
1101 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
1102
1103 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
1104 *data = RD_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET);
1105
1106}
1107
1108static void
1109qla25xx_write_risc_sema_reg(scsi_qla_host_t *vha, uint32_t data)
1110{
1111 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
1112
1113 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
1114 WRT_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET, data);
1115}
1116
1117static void
1118qla25xx_manipulate_risc_semaphore(scsi_qla_host_t *vha)
1119{
1120 struct qla_hw_data *ha = vha->hw;
1121 uint32_t wd32 = 0;
1122 uint delta_msec = 100;
1123 uint elapsed_msec = 0;
1124 uint timeout_msec;
1125 ulong n;
1126
1127 if (!IS_QLA25XX(ha) && !IS_QLA2031(ha))
1128 return;
1129
1130attempt:
1131 timeout_msec = TIMEOUT_SEMAPHORE;
1132 n = timeout_msec / delta_msec;
1133 while (n--) {
1134 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_SET);
1135 qla25xx_read_risc_sema_reg(vha, &wd32);
1136 if (wd32 & RISC_SEMAPHORE)
1137 break;
1138 msleep(delta_msec);
1139 elapsed_msec += delta_msec;
1140 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
1141 goto force;
1142 }
1143
1144 if (!(wd32 & RISC_SEMAPHORE))
1145 goto force;
1146
1147 if (!(wd32 & RISC_SEMAPHORE_FORCE))
1148 goto acquired;
1149
1150 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_CLR);
1151 timeout_msec = TIMEOUT_SEMAPHORE_FORCE;
1152 n = timeout_msec / delta_msec;
1153 while (n--) {
1154 qla25xx_read_risc_sema_reg(vha, &wd32);
1155 if (!(wd32 & RISC_SEMAPHORE_FORCE))
1156 break;
1157 msleep(delta_msec);
1158 elapsed_msec += delta_msec;
1159 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
1160 goto force;
1161 }
1162
1163 if (wd32 & RISC_SEMAPHORE_FORCE)
1164 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_CLR);
1165
1166 goto attempt;
1167
1168force:
1169 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_SET);
1170
1171acquired:
1172 return;
1173}
1174
88c26663
AV		 1175/**
1176 * qla24xx_reset_chip() - Reset ISP24xx chip.
1177 * @ha: HA context
1178 *
1179 * Returns 0 on success.
1180 */
1181void
e315cd28 1182qla24xx_reset_chip(scsi_qla_host_t *vha)
88c26663 1183{
e315cd28 1184 struct qla_hw_data *ha = vha->hw;
85880801
AV		 1185
1186 if (pci_channel_offline(ha->pdev) &&
1187 ha->flags.pci_channel_io_perm_failure) {
1188 return;
1189 }
1190
fd34f556 1191 ha->isp_ops->disable_intrs(ha);
88c26663 1192
4ea2c9c7
JC		 1193 qla25xx_manipulate_risc_semaphore(vha);
1194
88c26663 1195 /* Perform RISC reset. */
e315cd28 1196 qla24xx_reset_risc(vha);
88c26663
AV		 1197}
1198
1da177e4
LT		 1199/**
1200 * qla2x00_chip_diag() - Test chip for proper operation.
1201 * @ha: HA context
1202 *
1203 * Returns 0 on success.
1204 */
abbd8870 1205int
e315cd28 1206qla2x00_chip_diag(scsi_qla_host_t *vha)
1da177e4
LT		 1207{
1208 int rval;
e315cd28 1209 struct qla_hw_data *ha = vha->hw;
3d71644c 1210 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 1211 unsigned long flags = 0;
1212 uint16_t data;
1213 uint32_t cnt;
1214 uint16_t mb[5];
73208dfd 1215 struct req_que *req = ha->req_q_map[0];
1da177e4
LT		 1216
1217 /* Assume a failed state */
1218 rval = QLA_FUNCTION_FAILED;
1219
7c3df132
SK		 1220 ql_dbg(ql_dbg_init, vha, 0x007b,
1221 "Testing device at %lx.\n", (u_long)&reg->flash_address);
1da177e4
LT		 1222
1223 spin_lock_irqsave(&ha->hardware_lock, flags);
1224
1225 /* Reset ISP chip. */
1226 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1227
1228 /*
1229 * We need to have a delay here since the card will not respond while
1230 * in reset causing an MCA on some architectures.
1231 */
1232 udelay(20);
1233 data = qla2x00_debounce_register(&reg->ctrl_status);
1234 for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {
1235 udelay(5);
1236 data = RD_REG_WORD(&reg->ctrl_status);
1237 barrier();
1238 }
1239
1240 if (!cnt)
1241 goto chip_diag_failed;
1242
7c3df132
SK		 1243 ql_dbg(ql_dbg_init, vha, 0x007c,
1244 "Reset register cleared by chip reset.\n");
1da177e4
LT		 1245
1246 /* Reset RISC processor. */
1247 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
1248 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
1249
1250 /* Workaround for QLA2312 PCI parity error */
1251 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1252 data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0));
1253 for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) {
1254 udelay(5);
1255 data = RD_MAILBOX_REG(ha, reg, 0);
fa2a1ce5 1256 barrier();
1da177e4
LT		 1257 }
1258 } else
1259 udelay(10);
1260
1261 if (!cnt)
1262 goto chip_diag_failed;
1263
1264 /* Check product ID of chip */
7c3df132 1265 ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product Id of chip.\n");
1da177e4
LT		 1266
1267 mb[1] = RD_MAILBOX_REG(ha, reg, 1);
1268 mb[2] = RD_MAILBOX_REG(ha, reg, 2);
1269 mb[3] = RD_MAILBOX_REG(ha, reg, 3);
1270 mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4));
1271 if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) ||
1272 mb[3] != PROD_ID_3) {
7c3df132
SK		 1273 ql_log(ql_log_warn, vha, 0x0062,
1274 "Wrong product ID = 0x%x,0x%x,0x%x.\n",
1275 mb[1], mb[2], mb[3]);
1da177e4
LT		 1276
1277 goto chip_diag_failed;
1278 }
1279 ha->product_id[0] = mb[1];
1280 ha->product_id[1] = mb[2];
1281 ha->product_id[2] = mb[3];
1282 ha->product_id[3] = mb[4];
1283
1284 /* Adjust fw RISC transfer size */
73208dfd 1285 if (req->length > 1024)
1da177e4
LT		 1286 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024;
1287 else
1288 ha->fw_transfer_size = REQUEST_ENTRY_SIZE *
73208dfd 1289 req->length;
1da177e4
LT		 1290
1291 if (IS_QLA2200(ha) &&
1292 RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) {
1293 /* Limit firmware transfer size with a 2200A */
7c3df132 1294 ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n");
1da177e4 1295
ea5b6382 1296 ha->device_type |= DT_ISP2200A;
1da177e4
LT		 1297 ha->fw_transfer_size = 128;
1298 }
1299
1300 /* Wrap Incoming Mailboxes Test. */
1301 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1302
7c3df132 1303 ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n");
e315cd28 1304 rval = qla2x00_mbx_reg_test(vha);
7c3df132
SK		 1305 if (rval)
1306 ql_log(ql_log_warn, vha, 0x0080,
1307 "Failed mailbox send register test.\n");
1308 else
1da177e4
LT		 1309 /* Flag a successful rval */
1310 rval = QLA_SUCCESS;
1da177e4
LT		 1311 spin_lock_irqsave(&ha->hardware_lock, flags);
1312
1313chip_diag_failed:
1314 if (rval)
7c3df132
SK		 1315 ql_log(ql_log_info, vha, 0x0081,
1316 "Chip diagnostics **** FAILED ****.\n");
1da177e4
LT		 1317
1318 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1319
1320 return (rval);
1321}
1322
0107109e
AV		 1323/**
1324 * qla24xx_chip_diag() - Test ISP24xx for proper operation.
1325 * @ha: HA context
1326 *
1327 * Returns 0 on success.
1328 */
1329int
e315cd28 1330qla24xx_chip_diag(scsi_qla_host_t *vha)
0107109e
AV		 1331{
1332 int rval;
e315cd28 1333 struct qla_hw_data *ha = vha->hw;
73208dfd 1334 struct req_que *req = ha->req_q_map[0];
0107109e 1335
a9083016
GM		 1336 if (IS_QLA82XX(ha))
1337 return QLA_SUCCESS;
1338
73208dfd 1339 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
0107109e 1340
e315cd28 1341 rval = qla2x00_mbx_reg_test(vha);
0107109e 1342 if (rval) {
7c3df132
SK		 1343 ql_log(ql_log_warn, vha, 0x0082,
1344 "Failed mailbox send register test.\n");
0107109e
AV		 1345 } else {
1346 /* Flag a successful rval */
1347 rval = QLA_SUCCESS;
1348 }
1349
1350 return rval;
1351}
1352
a7a167bf 1353void
e315cd28 1354qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
0107109e 1355{
a7a167bf
AV		 1356 int rval;
1357 uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
73208dfd 1358 eft_size, fce_size, mq_size;
df613b96
AV		 1359 dma_addr_t tc_dma;
1360 void *tc;
e315cd28 1361 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 1362 struct req_que *req = ha->req_q_map[0];
1363 struct rsp_que *rsp = ha->rsp_q_map[0];
a7a167bf
AV		 1364
1365 if (ha->fw_dump) {
7c3df132
SK		 1366 ql_dbg(ql_dbg_init, vha, 0x00bd,
1367 "Firmware dump already allocated.\n");
a7a167bf
AV		 1368 return;
1369 }
d4e3e04d 1370
0107109e 1371 ha->fw_dumped = 0;
73208dfd 1372 fixed_size = mem_size = eft_size = fce_size = mq_size = 0;
d4e3e04d 1373 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
a7a167bf 1374 fixed_size = sizeof(struct qla2100_fw_dump);
d4e3e04d 1375 } else if (IS_QLA23XX(ha)) {
a7a167bf
AV		 1376 fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
1377 mem_size = (ha->fw_memory_size - 0x11000 + 1) *
1378 sizeof(uint16_t);
e428924c 1379 } else if (IS_FWI2_CAPABLE(ha)) {
6246b8a1
GM		 1380 if (IS_QLA83XX(ha))
1381 fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem);
1382 else if (IS_QLA81XX(ha))
3a03eb79
AV		 1383 fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
1384 else if (IS_QLA25XX(ha))
1385 fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
1386 else
1387 fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
a7a167bf
AV		 1388 mem_size = (ha->fw_memory_size - 0x100000 + 1) *
1389 sizeof(uint32_t);
050c9bb1 1390 if (ha->mqenable) {
6246b8a1
GM		 1391 if (!IS_QLA83XX(ha))
1392 mq_size = sizeof(struct qla2xxx_mq_chain);
050c9bb1
GM		 1393 /*
1394 * Allocate maximum buffer size for all queues.
1395 * Resizing must be done at end-of-dump processing.
1396 */
1397 mq_size += ha->max_req_queues *
1398 (req->length * sizeof(request_t));
1399 mq_size += ha->max_rsp_queues *
1400 (rsp->length * sizeof(response_t));
1401 }
2d70c103
NB		 1402 if (ha->tgt.atio_q_length)
1403 mq_size += ha->tgt.atio_q_length * sizeof(request_t);
df613b96 1404 /* Allocate memory for Fibre Channel Event Buffer. */
6246b8a1 1405 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha))
436a7b11 1406 goto try_eft;
df613b96
AV		 1407
1408 tc = dma_alloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
1409 GFP_KERNEL);
1410 if (!tc) {
7c3df132
SK		 1411 ql_log(ql_log_warn, vha, 0x00be,
1412 "Unable to allocate (%d KB) for FCE.\n",
1413 FCE_SIZE / 1024);
17d98630 1414 goto try_eft;
df613b96
AV		 1415 }
1416
1417 memset(tc, 0, FCE_SIZE);
e315cd28 1418 rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS,
df613b96
AV		 1419 ha->fce_mb, &ha->fce_bufs);
1420 if (rval) {
7c3df132
SK		 1421 ql_log(ql_log_warn, vha, 0x00bf,
1422 "Unable to initialize FCE (%d).\n", rval);
df613b96
AV		 1423 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc,
1424 tc_dma);
1425 ha->flags.fce_enabled = 0;
17d98630 1426 goto try_eft;
df613b96 1427 }
cfb0919c 1428 ql_dbg(ql_dbg_init, vha, 0x00c0,
7c3df132 1429 "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024);
df613b96 1430
7d9dade3 1431 fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE;
df613b96
AV		 1432 ha->flags.fce_enabled = 1;
1433 ha->fce_dma = tc_dma;
1434 ha->fce = tc;
436a7b11
AV		 1435try_eft:
1436 /* Allocate memory for Extended Trace Buffer. */
1437 tc = dma_alloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
1438 GFP_KERNEL);
1439 if (!tc) {
7c3df132
SK		 1440 ql_log(ql_log_warn, vha, 0x00c1,
1441 "Unable to allocate (%d KB) for EFT.\n",
1442 EFT_SIZE / 1024);
436a7b11
AV		 1443 goto cont_alloc;
1444 }
1445
1446 memset(tc, 0, EFT_SIZE);
e315cd28 1447 rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
436a7b11 1448 if (rval) {
7c3df132
SK		 1449 ql_log(ql_log_warn, vha, 0x00c2,
1450 "Unable to initialize EFT (%d).\n", rval);
436a7b11
AV		 1451 dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc,
1452 tc_dma);
1453 goto cont_alloc;
1454 }
cfb0919c 1455 ql_dbg(ql_dbg_init, vha, 0x00c3,
7c3df132 1456 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
436a7b11
AV		 1457
1458 eft_size = EFT_SIZE;
1459 ha->eft_dma = tc_dma;
1460 ha->eft = tc;
d4e3e04d 1461 }
a7a167bf 1462cont_alloc:
73208dfd
AC		 1463 req_q_size = req->length * sizeof(request_t);
1464 rsp_q_size = rsp->length * sizeof(response_t);
a7a167bf
AV		 1465
1466 dump_size = offsetof(struct qla2xxx_fw_dump, isp);
2afa19a9 1467 dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size;
bb99de67
AV		 1468 ha->chain_offset = dump_size;
1469 dump_size += mq_size + fce_size;
d4e3e04d
AV		 1470
1471 ha->fw_dump = vmalloc(dump_size);
a7a167bf 1472 if (!ha->fw_dump) {
7c3df132
SK		 1473 ql_log(ql_log_warn, vha, 0x00c4,
1474 "Unable to allocate (%d KB) for firmware dump.\n",
1475 dump_size / 1024);
a7a167bf 1476
e30d1756
MI		 1477 if (ha->fce) {
1478 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
1479 ha->fce_dma);
1480 ha->fce = NULL;
1481 ha->fce_dma = 0;
1482 }
1483
a7a167bf
AV		 1484 if (ha->eft) {
1485 dma_free_coherent(&ha->pdev->dev, eft_size, ha->eft,
1486 ha->eft_dma);
1487 ha->eft = NULL;
1488 ha->eft_dma = 0;
1489 }
1490 return;
1491 }
cfb0919c 1492 ql_dbg(ql_dbg_init, vha, 0x00c5,
7c3df132 1493 "Allocated (%d KB) for firmware dump.\n", dump_size / 1024);
a7a167bf
AV		 1494
1495 ha->fw_dump_len = dump_size;
1496 ha->fw_dump->signature[0] = 'Q';
1497 ha->fw_dump->signature[1] = 'L';
1498 ha->fw_dump->signature[2] = 'G';
1499 ha->fw_dump->signature[3] = 'C';
1500 ha->fw_dump->version = __constant_htonl(1);
1501
1502 ha->fw_dump->fixed_size = htonl(fixed_size);
1503 ha->fw_dump->mem_size = htonl(mem_size);
1504 ha->fw_dump->req_q_size = htonl(req_q_size);
1505 ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
1506
1507 ha->fw_dump->eft_size = htonl(eft_size);
1508 ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma));
1509 ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma));
1510
1511 ha->fw_dump->header_size =
1512 htonl(offsetof(struct qla2xxx_fw_dump, isp));
0107109e
AV		 1513}
1514
18e7555a
AV		 1515static int
1516qla81xx_mpi_sync(scsi_qla_host_t *vha)
1517{
1518#define MPS_MASK 0xe0
1519 int rval;
1520 uint16_t dc;
1521 uint32_t dw;
18e7555a
AV		 1522
1523 if (!IS_QLA81XX(vha->hw))
1524 return QLA_SUCCESS;
1525
1526 rval = qla2x00_write_ram_word(vha, 0x7c00, 1);
1527 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1528 ql_log(ql_log_warn, vha, 0x0105,
1529 "Unable to acquire semaphore.\n");
18e7555a
AV		 1530 goto done;
1531 }
1532
1533 pci_read_config_word(vha->hw->pdev, 0x54, &dc);
1534 rval = qla2x00_read_ram_word(vha, 0x7a15, &dw);
1535 if (rval != QLA_SUCCESS) {
7c3df132 1536 ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n");
18e7555a
AV		 1537 goto done_release;
1538 }
1539
1540 dc &= MPS_MASK;
1541 if (dc == (dw & MPS_MASK))
1542 goto done_release;
1543
1544 dw &= ~MPS_MASK;
1545 dw |= dc;
1546 rval = qla2x00_write_ram_word(vha, 0x7a15, dw);
1547 if (rval != QLA_SUCCESS) {
7c3df132 1548 ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n");
18e7555a
AV		 1549 }
1550
1551done_release:
1552 rval = qla2x00_write_ram_word(vha, 0x7c00, 0);
1553 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1554 ql_log(ql_log_warn, vha, 0x006d,
1555 "Unable to release semaphore.\n");
18e7555a
AV		 1556 }
1557
1558done:
1559 return rval;
1560}
1561
8d93f550
CD		 1562int
1563qla2x00_alloc_outstanding_cmds(struct qla_hw_data *ha, struct req_que *req)
1564{
1565 /* Don't try to reallocate the array */
1566 if (req->outstanding_cmds)
1567 return QLA_SUCCESS;
1568
1569 if (!IS_FWI2_CAPABLE(ha) || (ha->mqiobase &&
1570 (ql2xmultique_tag || ql2xmaxqueues > 1)))
1571 req->num_outstanding_cmds = DEFAULT_OUTSTANDING_COMMANDS;
1572 else {
1573 if (ha->fw_xcb_count <= ha->fw_iocb_count)
1574 req->num_outstanding_cmds = ha->fw_xcb_count;
1575 else
1576 req->num_outstanding_cmds = ha->fw_iocb_count;
1577 }
1578
1579 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
1580 req->num_outstanding_cmds, GFP_KERNEL);
1581
1582 if (!req->outstanding_cmds) {
1583 /*
1584 * Try to allocate a minimal size just so we can get through
1585 * initialization.
1586 */
1587 req->num_outstanding_cmds = MIN_OUTSTANDING_COMMANDS;
1588 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
1589 req->num_outstanding_cmds, GFP_KERNEL);
1590
1591 if (!req->outstanding_cmds) {
1592 ql_log(ql_log_fatal, NULL, 0x0126,
1593 "Failed to allocate memory for "
1594 "outstanding_cmds for req_que %p.\n", req);
1595 req->num_outstanding_cmds = 0;
1596 return QLA_FUNCTION_FAILED;
1597 }
1598 }
1599
1600 return QLA_SUCCESS;
1601}
1602
1da177e4
LT		 1603/**
1604 * qla2x00_setup_chip() - Load and start RISC firmware.
1605 * @ha: HA context
1606 *
1607 * Returns 0 on success.
1608 */
1609static int
e315cd28 1610qla2x00_setup_chip(scsi_qla_host_t *vha)
1da177e4 1611{
0107109e
AV		 1612 int rval;
1613 uint32_t srisc_address = 0;
e315cd28 1614 struct qla_hw_data *ha = vha->hw;
3db0652e
AV		 1615 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1616 unsigned long flags;
dda772e8 1617 uint16_t fw_major_version;
3db0652e 1618
a9083016
GM		 1619 if (IS_QLA82XX(ha)) {
1620 rval = ha->isp_ops->load_risc(vha, &srisc_address);
14e303d9
AV		 1621 if (rval == QLA_SUCCESS) {
1622 qla2x00_stop_firmware(vha);
a9083016 1623 goto enable_82xx_npiv;
14e303d9 1624 } else
b963752f 1625 goto failed;
a9083016
GM		 1626 }
1627
3db0652e
AV		 1628 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1629 /* Disable SRAM, Instruction RAM and GP RAM parity. */
1630 spin_lock_irqsave(&ha->hardware_lock, flags);
1631 WRT_REG_WORD(&reg->hccr, (HCCR_ENABLE_PARITY + 0x0));
1632 RD_REG_WORD(&reg->hccr);
1633 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1634 }
1da177e4 1635
18e7555a
AV		 1636 qla81xx_mpi_sync(vha);
1637
1da177e4 1638 /* Load firmware sequences */
e315cd28 1639 rval = ha->isp_ops->load_risc(vha, &srisc_address);
0107109e 1640 if (rval == QLA_SUCCESS) {
7c3df132
SK		 1641 ql_dbg(ql_dbg_init, vha, 0x00c9,
1642 "Verifying Checksum of loaded RISC code.\n");
1da177e4 1643
e315cd28 1644 rval = qla2x00_verify_checksum(vha, srisc_address);
1da177e4
LT		 1645 if (rval == QLA_SUCCESS) {
1646 /* Start firmware execution. */
7c3df132
SK		 1647 ql_dbg(ql_dbg_init, vha, 0x00ca,
1648 "Starting firmware.\n");
1da177e4 1649
e315cd28 1650 rval = qla2x00_execute_fw(vha, srisc_address);
1da177e4 1651 /* Retrieve firmware information. */
dda772e8 1652 if (rval == QLA_SUCCESS) {
a9083016 1653enable_82xx_npiv:
dda772e8 1654 fw_major_version = ha->fw_major_version;
3173167f
GM		 1655 if (IS_QLA82XX(ha))
1656 qla82xx_check_md_needed(vha);
6246b8a1
GM		 1657 else
1658 rval = qla2x00_get_fw_version(vha);
ca9e9c3e
AV		 1659 if (rval != QLA_SUCCESS)
1660 goto failed;
2c3dfe3f 1661 ha->flags.npiv_supported = 0;
e315cd28 1662 if (IS_QLA2XXX_MIDTYPE(ha) &&
946fb891 1663 (ha->fw_attributes & BIT_2)) {
2c3dfe3f 1664 ha->flags.npiv_supported = 1;
4d0ea247
SJ		 1665 if ((!ha->max_npiv_vports) ||
1666 ((ha->max_npiv_vports + 1) %
eb66dc60 1667 MIN_MULTI_ID_FABRIC))
4d0ea247 1668 ha->max_npiv_vports =
eb66dc60 1669 MIN_MULTI_ID_FABRIC - 1;
4d0ea247 1670 }
24a08138 1671 qla2x00_get_resource_cnts(vha, NULL,
8d93f550 1672 &ha->fw_xcb_count, NULL, &ha->fw_iocb_count,
f3a0a77e 1673 &ha->max_npiv_vports, NULL);
d743de66 1674
8d93f550
CD		 1675 /*
1676 * Allocate the array of outstanding commands
1677 * now that we know the firmware resources.
1678 */
1679 rval = qla2x00_alloc_outstanding_cmds(ha,
1680 vha->req);
1681 if (rval != QLA_SUCCESS)
1682 goto failed;
1683
be5ea3cf
SK		 1684 if (!fw_major_version && ql2xallocfwdump
1685 && !IS_QLA82XX(ha))
08de2844 1686 qla2x00_alloc_fw_dump(vha);
1da177e4
LT		 1687 }
1688 } else {
7c3df132
SK		 1689 ql_log(ql_log_fatal, vha, 0x00cd,
1690 "ISP Firmware failed checksum.\n");
1691 goto failed;
1da177e4 1692 }
c74d88a4
AV		 1693 } else
1694 goto failed;
1da177e4 1695
3db0652e
AV		 1696 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1697 /* Enable proper parity. */
1698 spin_lock_irqsave(&ha->hardware_lock, flags);
1699 if (IS_QLA2300(ha))
1700 /* SRAM parity */
1701 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x1);
1702 else
1703 /* SRAM, Instruction RAM and GP RAM parity */
1704 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x7);
1705 RD_REG_WORD(&reg->hccr);
1706 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1707 }
1708
6246b8a1
GM		 1709 if (IS_QLA83XX(ha))
1710 goto skip_fac_check;
1711
1d2874de
JC		 1712 if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
1713 uint32_t size;
1714
1715 rval = qla81xx_fac_get_sector_size(vha, &size);
1716 if (rval == QLA_SUCCESS) {
1717 ha->flags.fac_supported = 1;
1718 ha->fdt_block_size = size << 2;
1719 } else {
7c3df132 1720 ql_log(ql_log_warn, vha, 0x00ce,
1d2874de
JC		 1721 "Unsupported FAC firmware (%d.%02d.%02d).\n",
1722 ha->fw_major_version, ha->fw_minor_version,
1723 ha->fw_subminor_version);
6246b8a1
GM		 1724skip_fac_check:
1725 if (IS_QLA83XX(ha)) {
1726 ha->flags.fac_supported = 0;
1727 rval = QLA_SUCCESS;
1728 }
1d2874de
JC		 1729 }
1730 }
ca9e9c3e 1731failed:
1da177e4 1732 if (rval) {
7c3df132
SK		 1733 ql_log(ql_log_fatal, vha, 0x00cf,
1734 "Setup chip ****FAILED****.\n");
1da177e4
LT		 1735 }
1736
1737 return (rval);
1738}
1739
1740/**
1741 * qla2x00_init_response_q_entries() - Initializes response queue entries.
1742 * @ha: HA context
1743 *
1744 * Beginning of request ring has initialization control block already built
1745 * by nvram config routine.
1746 *
1747 * Returns 0 on success.
1748 */
73208dfd
AC		 1749void
1750qla2x00_init_response_q_entries(struct rsp_que *rsp)
1da177e4
LT		 1751{
1752 uint16_t cnt;
1753 response_t *pkt;
1754
2afa19a9
AC		 1755 rsp->ring_ptr = rsp->ring;
1756 rsp->ring_index = 0;
1757 rsp->status_srb = NULL;
e315cd28
AC		 1758 pkt = rsp->ring_ptr;
1759 for (cnt = 0; cnt < rsp->length; cnt++) {
1da177e4
LT		 1760 pkt->signature = RESPONSE_PROCESSED;
1761 pkt++;
1762 }
1da177e4
LT		 1763}
1764
1765/**
1766 * qla2x00_update_fw_options() - Read and process firmware options.
1767 * @ha: HA context
1768 *
1769 * Returns 0 on success.
1770 */
abbd8870 1771void
e315cd28 1772qla2x00_update_fw_options(scsi_qla_host_t *vha)
1da177e4
LT		 1773{
1774 uint16_t swing, emphasis, tx_sens, rx_sens;
e315cd28 1775 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 1776
1777 memset(ha->fw_options, 0, sizeof(ha->fw_options));
e315cd28 1778 qla2x00_get_fw_options(vha, ha->fw_options);
1da177e4
LT		 1779
1780 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1781 return;
1782
1783 /* Serial Link options. */
7c3df132
SK		 1784 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
1785 "Serial link options.\n");
1786 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
1787 (uint8_t *)&ha->fw_seriallink_options,
1788 sizeof(ha->fw_seriallink_options));
1da177e4
LT		 1789
1790 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1791 if (ha->fw_seriallink_options[3] & BIT_2) {
1792 ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING;
1793
1794 /* 1G settings */
1795 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
1796 emphasis = (ha->fw_seriallink_options[2] &
1797 (BIT_4 | BIT_3)) >> 3;
1798 tx_sens = ha->fw_seriallink_options[0] &
fa2a1ce5 1799 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 1800 rx_sens = (ha->fw_seriallink_options[0] &
1801 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
1802 ha->fw_options[10] = (emphasis << 14) | (swing << 8);
1803 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
1804 if (rx_sens == 0x0)
1805 rx_sens = 0x3;
1806 ha->fw_options[10] |= (tx_sens << 4) | rx_sens;
1807 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
1808 ha->fw_options[10] |= BIT_5 |
1809 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
1810 (tx_sens & (BIT_1 | BIT_0));
1811
1812 /* 2G settings */
1813 swing = (ha->fw_seriallink_options[2] &
1814 (BIT_7 | BIT_6 | BIT_5)) >> 5;
1815 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
1816 tx_sens = ha->fw_seriallink_options[1] &
fa2a1ce5 1817 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 1818 rx_sens = (ha->fw_seriallink_options[1] &
1819 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
1820 ha->fw_options[11] = (emphasis << 14) | (swing << 8);
1821 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
1822 if (rx_sens == 0x0)
1823 rx_sens = 0x3;
1824 ha->fw_options[11] |= (tx_sens << 4) | rx_sens;
1825 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
1826 ha->fw_options[11] |= BIT_5 |
1827 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
1828 (tx_sens & (BIT_1 | BIT_0));
1829 }
1830
1831 /* FCP2 options. */
1832 /* Return command IOCBs without waiting for an ABTS to complete. */
1833 ha->fw_options[3] |= BIT_13;
1834
1835 /* LED scheme. */
1836 if (ha->flags.enable_led_scheme)
1837 ha->fw_options[2] |= BIT_12;
1838
48c02fde
AV		 1839 /* Detect ISP6312. */
1840 if (IS_QLA6312(ha))
1841 ha->fw_options[2] |= BIT_13;
1842
1da177e4 1843 /* Update firmware options. */
e315cd28 1844 qla2x00_set_fw_options(vha, ha->fw_options);
1da177e4
LT		 1845}
1846
0107109e 1847void
e315cd28 1848qla24xx_update_fw_options(scsi_qla_host_t *vha)
0107109e
AV		 1849{
1850 int rval;
e315cd28 1851 struct qla_hw_data *ha = vha->hw;
0107109e 1852
a9083016
GM		 1853 if (IS_QLA82XX(ha))
1854 return;
1855
0107109e 1856 /* Update Serial Link options. */
f94097ed 1857 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0)
0107109e
AV		 1858 return;
1859
e315cd28 1860 rval = qla2x00_set_serdes_params(vha,
f94097ed
AV		 1861 le16_to_cpu(ha->fw_seriallink_options24[1]),
1862 le16_to_cpu(ha->fw_seriallink_options24[2]),
1863 le16_to_cpu(ha->fw_seriallink_options24[3]));
0107109e 1864 if (rval != QLA_SUCCESS) {
7c3df132 1865 ql_log(ql_log_warn, vha, 0x0104,
0107109e
AV		 1866 "Unable to update Serial Link options (%x).\n", rval);
1867 }
1868}
1869
abbd8870 1870void
e315cd28 1871qla2x00_config_rings(struct scsi_qla_host *vha)
abbd8870 1872{
e315cd28 1873 struct qla_hw_data *ha = vha->hw;
3d71644c 1874 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
73208dfd
AC		 1875 struct req_que *req = ha->req_q_map[0];
1876 struct rsp_que *rsp = ha->rsp_q_map[0];
abbd8870
AV		 1877
1878 /* Setup ring parameters in initialization control block. */
1879 ha->init_cb->request_q_outpointer = __constant_cpu_to_le16(0);
1880 ha->init_cb->response_q_inpointer = __constant_cpu_to_le16(0);
e315cd28
AC		 1881 ha->init_cb->request_q_length = cpu_to_le16(req->length);
1882 ha->init_cb->response_q_length = cpu_to_le16(rsp->length);
1883 ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
1884 ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
1885 ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
1886 ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
abbd8870
AV		 1887
1888 WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0);
1889 WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0);
1890 WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0);
1891 WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0);
1892 RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */
1893}
1894
0107109e 1895void
e315cd28 1896qla24xx_config_rings(struct scsi_qla_host *vha)
0107109e 1897{
e315cd28 1898 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 1899 device_reg_t __iomem *reg = ISP_QUE_REG(ha, 0);
1900 struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
1901 struct qla_msix_entry *msix;
0107109e 1902 struct init_cb_24xx *icb;
73208dfd
AC		 1903 uint16_t rid = 0;
1904 struct req_que *req = ha->req_q_map[0];
1905 struct rsp_que *rsp = ha->rsp_q_map[0];
0107109e 1906
6246b8a1 1907 /* Setup ring parameters in initialization control block. */
0107109e
AV		 1908 icb = (struct init_cb_24xx *)ha->init_cb;
1909 icb->request_q_outpointer = __constant_cpu_to_le16(0);
1910 icb->response_q_inpointer = __constant_cpu_to_le16(0);
e315cd28
AC		 1911 icb->request_q_length = cpu_to_le16(req->length);
1912 icb->response_q_length = cpu_to_le16(rsp->length);
1913 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
1914 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
1915 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
1916 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
0107109e 1917
2d70c103
NB		 1918 /* Setup ATIO queue dma pointers for target mode */
1919 icb->atio_q_inpointer = __constant_cpu_to_le16(0);
1920 icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length);
1921 icb->atio_q_address[0] = cpu_to_le32(LSD(ha->tgt.atio_dma));
1922 icb->atio_q_address[1] = cpu_to_le32(MSD(ha->tgt.atio_dma));
1923
6246b8a1 1924 if (ha->mqenable || IS_QLA83XX(ha)) {
73208dfd
AC		 1925 icb->qos = __constant_cpu_to_le16(QLA_DEFAULT_QUE_QOS);
1926 icb->rid = __constant_cpu_to_le16(rid);
1927 if (ha->flags.msix_enabled) {
1928 msix = &ha->msix_entries[1];
7c3df132
SK		 1929 ql_dbg(ql_dbg_init, vha, 0x00fd,
1930 "Registering vector 0x%x for base que.\n",
1931 msix->entry);
73208dfd
AC		 1932 icb->msix = cpu_to_le16(msix->entry);
1933 }
1934 /* Use alternate PCI bus number */
1935 if (MSB(rid))
1936 icb->firmware_options_2 |=
1937 __constant_cpu_to_le32(BIT_19);
1938 /* Use alternate PCI devfn */
1939 if (LSB(rid))
1940 icb->firmware_options_2 |=
1941 __constant_cpu_to_le32(BIT_18);
1942
3155754a 1943 /* Use Disable MSIX Handshake mode for capable adapters */
6246b8a1
GM		 1944 if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) &&
1945 (ha->flags.msix_enabled)) {
3155754a
AC		 1946 icb->firmware_options_2 &=
1947 __constant_cpu_to_le32(~BIT_22);
1948 ha->flags.disable_msix_handshake = 1;
7c3df132
SK		 1949 ql_dbg(ql_dbg_init, vha, 0x00fe,
1950 "MSIX Handshake Disable Mode turned on.\n");
3155754a
AC		 1951 } else {
1952 icb->firmware_options_2 |=
1953 __constant_cpu_to_le32(BIT_22);
1954 }
73208dfd 1955 icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_23);
73208dfd
AC		 1956
1957 WRT_REG_DWORD(&reg->isp25mq.req_q_in, 0);
1958 WRT_REG_DWORD(&reg->isp25mq.req_q_out, 0);
1959 WRT_REG_DWORD(&reg->isp25mq.rsp_q_in, 0);
1960 WRT_REG_DWORD(&reg->isp25mq.rsp_q_out, 0);
1961 } else {
1962 WRT_REG_DWORD(&reg->isp24.req_q_in, 0);
1963 WRT_REG_DWORD(&reg->isp24.req_q_out, 0);
1964 WRT_REG_DWORD(&reg->isp24.rsp_q_in, 0);
1965 WRT_REG_DWORD(&reg->isp24.rsp_q_out, 0);
1966 }
aa230bc5 1967 qlt_24xx_config_rings(vha);
2d70c103 1968
73208dfd
AC		 1969 /* PCI posting */
1970 RD_REG_DWORD(&ioreg->hccr);
0107109e
AV		 1971}
1972
1da177e4
LT		 1973/**
1974 * qla2x00_init_rings() - Initializes firmware.
1975 * @ha: HA context
1976 *
1977 * Beginning of request ring has initialization control block already built
1978 * by nvram config routine.
1979 *
1980 * Returns 0 on success.
1981 */
1982static int
e315cd28 1983qla2x00_init_rings(scsi_qla_host_t *vha)
1da177e4
LT		 1984{
1985 int rval;
1986 unsigned long flags = 0;
29bdccbe 1987 int cnt, que;
e315cd28 1988 struct qla_hw_data *ha = vha->hw;
29bdccbe
AC		 1989 struct req_que *req;
1990 struct rsp_que *rsp;
2c3dfe3f
SJ		 1991 struct mid_init_cb_24xx *mid_init_cb =
1992 (struct mid_init_cb_24xx *) ha->init_cb;
1da177e4
LT		 1993
1994 spin_lock_irqsave(&ha->hardware_lock, flags);
1995
1996 /* Clear outstanding commands array. */
2afa19a9 1997 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe
AC		 1998 req = ha->req_q_map[que];
1999 if (!req)
2000 continue;
8d93f550 2001 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++)
29bdccbe 2002 req->outstanding_cmds[cnt] = NULL;
1da177e4 2003
2afa19a9 2004 req->current_outstanding_cmd = 1;
1da177e4 2005
29bdccbe
AC		 2006 /* Initialize firmware. */
2007 req->ring_ptr = req->ring;
2008 req->ring_index = 0;
2009 req->cnt = req->length;
2010 }
1da177e4 2011
2afa19a9 2012 for (que = 0; que < ha->max_rsp_queues; que++) {
29bdccbe
AC		 2013 rsp = ha->rsp_q_map[que];
2014 if (!rsp)
2015 continue;
29bdccbe
AC		 2016 /* Initialize response queue entries */
2017 qla2x00_init_response_q_entries(rsp);
2018 }
1da177e4 2019
2d70c103
NB		 2020 ha->tgt.atio_ring_ptr = ha->tgt.atio_ring;
2021 ha->tgt.atio_ring_index = 0;
2022 /* Initialize ATIO queue entries */
2023 qlt_init_atio_q_entries(vha);
2024
e315cd28 2025 ha->isp_ops->config_rings(vha);
1da177e4
LT		 2026
2027 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2028
2029 /* Update any ISP specific firmware options before initialization. */
e315cd28 2030 ha->isp_ops->update_fw_options(vha);
1da177e4 2031
7c3df132 2032 ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n");
2c3dfe3f 2033
605aa2bc 2034 if (ha->flags.npiv_supported) {
45980cc2 2035 if (ha->operating_mode == LOOP && !IS_CNA_CAPABLE(ha))
605aa2bc 2036 ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
c48339de 2037 mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
605aa2bc
LC		 2038 }
2039
24a08138
AV		 2040 if (IS_FWI2_CAPABLE(ha)) {
2041 mid_init_cb->options = __constant_cpu_to_le16(BIT_1);
2042 mid_init_cb->init_cb.execution_throttle =
2043 cpu_to_le16(ha->fw_xcb_count);
2044 }
2c3dfe3f 2045
e315cd28 2046 rval = qla2x00_init_firmware(vha, ha->init_cb_size);
1da177e4 2047 if (rval) {
7c3df132
SK		 2048 ql_log(ql_log_fatal, vha, 0x00d2,
2049 "Init Firmware **** FAILED ****.\n");
1da177e4 2050 } else {
7c3df132
SK		 2051 ql_dbg(ql_dbg_init, vha, 0x00d3,
2052 "Init Firmware -- success.\n");
1da177e4
LT		 2053 }
2054
2055 return (rval);
2056}
2057
2058/**
2059 * qla2x00_fw_ready() - Waits for firmware ready.
2060 * @ha: HA context
2061 *
2062 * Returns 0 on success.
2063 */
2064static int
e315cd28 2065qla2x00_fw_ready(scsi_qla_host_t *vha)
1da177e4
LT		 2066{
2067 int rval;
4d4df193 2068 unsigned long wtime, mtime, cs84xx_time;
1da177e4
LT		 2069 uint16_t min_wait; /* Minimum wait time if loop is down */
2070 uint16_t wait_time; /* Wait time if loop is coming ready */
656e8912 2071 uint16_t state[5];
e315cd28 2072 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2073
2074 rval = QLA_SUCCESS;
2075
2076 /* 20 seconds for loop down. */
fa2a1ce5 2077 min_wait = 20;
1da177e4
LT		 2078
2079 /*
2080 * Firmware should take at most one RATOV to login, plus 5 seconds for
2081 * our own processing.
2082 */
2083 if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) {
2084 wait_time = min_wait;
2085 }
2086
2087 /* Min wait time if loop down */
2088 mtime = jiffies + (min_wait * HZ);
2089
2090 /* wait time before firmware ready */
2091 wtime = jiffies + (wait_time * HZ);
2092
2093 /* Wait for ISP to finish LIP */
e315cd28 2094 if (!vha->flags.init_done)
7c3df132
SK		 2095 ql_log(ql_log_info, vha, 0x801e,
2096 "Waiting for LIP to complete.\n");
1da177e4
LT		 2097
2098 do {
5b939038 2099 memset(state, -1, sizeof(state));
e315cd28 2100 rval = qla2x00_get_firmware_state(vha, state);
1da177e4 2101 if (rval == QLA_SUCCESS) {
4d4df193 2102 if (state[0] < FSTATE_LOSS_OF_SYNC) {
e315cd28 2103 vha->device_flags &= ~DFLG_NO_CABLE;
1da177e4 2104 }
4d4df193 2105 if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) {
7c3df132
SK		 2106 ql_dbg(ql_dbg_taskm, vha, 0x801f,
2107 "fw_state=%x 84xx=%x.\n", state[0],
2108 state[2]);
4d4df193
HK		 2109 if ((state[2] & FSTATE_LOGGED_IN) &&
2110 (state[2] & FSTATE_WAITING_FOR_VERIFY)) {
7c3df132
SK		 2111 ql_dbg(ql_dbg_taskm, vha, 0x8028,
2112 "Sending verify iocb.\n");
4d4df193
HK		 2113
2114 cs84xx_time = jiffies;
e315cd28 2115 rval = qla84xx_init_chip(vha);
7c3df132
SK		 2116 if (rval != QLA_SUCCESS) {
2117 ql_log(ql_log_warn,
cfb0919c 2118 vha, 0x8007,
7c3df132 2119 "Init chip failed.\n");
4d4df193 2120 break;
7c3df132 2121 }
4d4df193
HK		 2122
2123 /* Add time taken to initialize. */
2124 cs84xx_time = jiffies - cs84xx_time;
2125 wtime += cs84xx_time;
2126 mtime += cs84xx_time;
cfb0919c 2127 ql_dbg(ql_dbg_taskm, vha, 0x8008,
7c3df132
SK		 2128 "Increasing wait time by %ld. "
2129 "New time %ld.\n", cs84xx_time,
2130 wtime);
4d4df193
HK		 2131 }
2132 } else if (state[0] == FSTATE_READY) {
7c3df132
SK		 2133 ql_dbg(ql_dbg_taskm, vha, 0x8037,
2134 "F/W Ready - OK.\n");
1da177e4 2135
e315cd28 2136 qla2x00_get_retry_cnt(vha, &ha->retry_count,
1da177e4
LT		 2137 &ha->login_timeout, &ha->r_a_tov);
2138
2139 rval = QLA_SUCCESS;
2140 break;
2141 }
2142
2143 rval = QLA_FUNCTION_FAILED;
2144
e315cd28 2145 if (atomic_read(&vha->loop_down_timer) &&
4d4df193 2146 state[0] != FSTATE_READY) {
1da177e4 2147 /* Loop down. Timeout on min_wait for states
fa2a1ce5
AV		 2148 * other than Wait for Login.
2149 */
1da177e4 2150 if (time_after_eq(jiffies, mtime)) {
7c3df132 2151 ql_log(ql_log_info, vha, 0x8038,
1da177e4
LT		 2152 "Cable is unplugged...\n");
2153
e315cd28 2154 vha->device_flags |= DFLG_NO_CABLE;
1da177e4
LT		 2155 break;
2156 }
2157 }
2158 } else {
2159 /* Mailbox cmd failed. Timeout on min_wait. */
cdbb0a4f 2160 if (time_after_eq(jiffies, mtime) ||
7190575f 2161 ha->flags.isp82xx_fw_hung)
1da177e4
LT		 2162 break;
2163 }
2164
2165 if (time_after_eq(jiffies, wtime))
2166 break;
2167
2168 /* Delay for a while */
2169 msleep(500);
1da177e4
LT		 2170 } while (1);
2171
7c3df132
SK		 2172 ql_dbg(ql_dbg_taskm, vha, 0x803a,
2173 "fw_state=%x (%x, %x, %x, %x) " "curr time=%lx.\n", state[0],
2174 state[1], state[2], state[3], state[4], jiffies);
1da177e4 2175
cfb0919c 2176 if (rval && !(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132
SK		 2177 ql_log(ql_log_warn, vha, 0x803b,
2178 "Firmware ready **** FAILED ****.\n");
1da177e4
LT		 2179 }
2180
2181 return (rval);
2182}
2183
2184/*
2185* qla2x00_configure_hba
2186* Setup adapter context.
2187*
2188* Input:
2189* ha = adapter state pointer.
2190*
2191* Returns:
2192* 0 = success
2193*
2194* Context:
2195* Kernel context.
2196*/
2197static int
e315cd28 2198qla2x00_configure_hba(scsi_qla_host_t *vha)
1da177e4
LT		 2199{
2200 int rval;
2201 uint16_t loop_id;
2202 uint16_t topo;
2c3dfe3f 2203 uint16_t sw_cap;
1da177e4
LT		 2204 uint8_t al_pa;
2205 uint8_t area;
2206 uint8_t domain;
2207 char connect_type[22];
e315cd28 2208 struct qla_hw_data *ha = vha->hw;
f24b5cb8 2209 unsigned long flags;
61e1b269 2210 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 2211
2212 /* Get host addresses. */
e315cd28 2213 rval = qla2x00_get_adapter_id(vha,
2c3dfe3f 2214 &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
1da177e4 2215 if (rval != QLA_SUCCESS) {
e315cd28 2216 if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
6246b8a1 2217 IS_CNA_CAPABLE(ha) ||
33135aa2 2218 (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
7c3df132
SK		 2219 ql_dbg(ql_dbg_disc, vha, 0x2008,
2220 "Loop is in a transition state.\n");
33135aa2 2221 } else {
7c3df132
SK		 2222 ql_log(ql_log_warn, vha, 0x2009,
2223 "Unable to get host loop ID.\n");
61e1b269
JC		 2224 if (IS_FWI2_CAPABLE(ha) && (vha == base_vha) &&
2225 (rval == QLA_COMMAND_ERROR && loop_id == 0x1b)) {
2226 ql_log(ql_log_warn, vha, 0x1151,
2227 "Doing link init.\n");
2228 if (qla24xx_link_initialize(vha) == QLA_SUCCESS)
2229 return rval;
2230 }
e315cd28 2231 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
33135aa2 2232 }
1da177e4
LT		 2233 return (rval);
2234 }
2235
2236 if (topo == 4) {
7c3df132
SK		 2237 ql_log(ql_log_info, vha, 0x200a,
2238 "Cannot get topology - retrying.\n");
1da177e4
LT		 2239 return (QLA_FUNCTION_FAILED);
2240 }
2241
e315cd28 2242 vha->loop_id = loop_id;
1da177e4
LT		 2243
2244 /* initialize */
2245 ha->min_external_loopid = SNS_FIRST_LOOP_ID;
2246 ha->operating_mode = LOOP;
2c3dfe3f 2247 ha->switch_cap = 0;
1da177e4
LT		 2248
2249 switch (topo) {
2250 case 0:
7c3df132 2251 ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n");
1da177e4
LT		 2252 ha->current_topology = ISP_CFG_NL;
2253 strcpy(connect_type, "(Loop)");
2254 break;
2255
2256 case 1:
7c3df132 2257 ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n");
2c3dfe3f 2258 ha->switch_cap = sw_cap;
1da177e4
LT		 2259 ha->current_topology = ISP_CFG_FL;
2260 strcpy(connect_type, "(FL_Port)");
2261 break;
2262
2263 case 2:
7c3df132 2264 ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n");
1da177e4
LT		 2265 ha->operating_mode = P2P;
2266 ha->current_topology = ISP_CFG_N;
2267 strcpy(connect_type, "(N_Port-to-N_Port)");
2268 break;
2269
2270 case 3:
7c3df132 2271 ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n");
2c3dfe3f 2272 ha->switch_cap = sw_cap;
1da177e4
LT		 2273 ha->operating_mode = P2P;
2274 ha->current_topology = ISP_CFG_F;
2275 strcpy(connect_type, "(F_Port)");
2276 break;
2277
2278 default:
7c3df132
SK		 2279 ql_dbg(ql_dbg_disc, vha, 0x200f,
2280 "HBA in unknown topology %x, using NL.\n", topo);
1da177e4
LT		 2281 ha->current_topology = ISP_CFG_NL;
2282 strcpy(connect_type, "(Loop)");
2283 break;
2284 }
2285
2286 /* Save Host port and loop ID. */
2287 /* byte order - Big Endian */
e315cd28
AC		 2288 vha->d_id.b.domain = domain;
2289 vha->d_id.b.area = area;
2290 vha->d_id.b.al_pa = al_pa;
1da177e4 2291
f24b5cb8 2292 spin_lock_irqsave(&ha->vport_slock, flags);
2d70c103 2293 qlt_update_vp_map(vha, SET_AL_PA);
f24b5cb8 2294 spin_unlock_irqrestore(&ha->vport_slock, flags);
2d70c103 2295
e315cd28 2296 if (!vha->flags.init_done)
7c3df132
SK		 2297 ql_log(ql_log_info, vha, 0x2010,
2298 "Topology - %s, Host Loop address 0x%x.\n",
e315cd28 2299 connect_type, vha->loop_id);
1da177e4
LT		 2300
2301 if (rval) {
7c3df132
SK		 2302 ql_log(ql_log_warn, vha, 0x2011,
2303 "%s FAILED\n", __func__);
1da177e4 2304 } else {
7c3df132
SK		 2305 ql_dbg(ql_dbg_disc, vha, 0x2012,
2306 "%s success\n", __func__);
1da177e4
LT		 2307 }
2308
2309 return(rval);
2310}
2311
a9083016 2312inline void
e315cd28
AC		 2313qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
2314 char *def)
9bb9fcf2
AV		 2315{
2316 char *st, *en;
2317 uint16_t index;
e315cd28 2318 struct qla_hw_data *ha = vha->hw;
ab671149 2319 int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
6246b8a1 2320 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha);
9bb9fcf2
AV		 2321
2322 if (memcmp(model, BINZERO, len) != 0) {
2323 strncpy(ha->model_number, model, len);
2324 st = en = ha->model_number;
2325 en += len - 1;
2326 while (en > st) {
2327 if (*en != 0x20 && *en != 0x00)
2328 break;
2329 *en-- = '\0';
2330 }
2331
2332 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 2333 if (use_tbl &&
2334 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2 2335 index < QLA_MODEL_NAMES)
1ee27146
JC		 2336 strncpy(ha->model_desc,
2337 qla2x00_model_name[index * 2 + 1],
2338 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 2339 } else {
2340 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 2341 if (use_tbl &&
2342 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2
AV		 2343 index < QLA_MODEL_NAMES) {
2344 strcpy(ha->model_number,
2345 qla2x00_model_name[index * 2]);
1ee27146
JC		 2346 strncpy(ha->model_desc,
2347 qla2x00_model_name[index * 2 + 1],
2348 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 2349 } else {
2350 strcpy(ha->model_number, def);
2351 }
2352 }
1ee27146 2353 if (IS_FWI2_CAPABLE(ha))
e315cd28 2354 qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc,
1ee27146 2355 sizeof(ha->model_desc));
9bb9fcf2
AV		 2356}
2357
4e08df3f
DM		 2358/* On sparc systems, obtain port and node WWN from firmware
2359 * properties.
2360 */
e315cd28 2361static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv)
4e08df3f
DM		 2362{
2363#ifdef CONFIG_SPARC
e315cd28 2364 struct qla_hw_data *ha = vha->hw;
4e08df3f 2365 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 2366 struct device_node *dp = pci_device_to_OF_node(pdev);
2367 const u8 *val;
4e08df3f
DM		 2368 int len;
2369
2370 val = of_get_property(dp, "port-wwn", &len);
2371 if (val && len >= WWN_SIZE)
2372 memcpy(nv->port_name, val, WWN_SIZE);
2373
2374 val = of_get_property(dp, "node-wwn", &len);
2375 if (val && len >= WWN_SIZE)
2376 memcpy(nv->node_name, val, WWN_SIZE);
2377#endif
2378}
2379
1da177e4
LT		 2380/*
2381* NVRAM configuration for ISP 2xxx
2382*
2383* Input:
2384* ha = adapter block pointer.
2385*
2386* Output:
2387* initialization control block in response_ring
2388* host adapters parameters in host adapter block
2389*
2390* Returns:
2391* 0 = success.
2392*/
abbd8870 2393int
e315cd28 2394qla2x00_nvram_config(scsi_qla_host_t *vha)
1da177e4 2395{
4e08df3f 2396 int rval;
0107109e
AV		 2397 uint8_t chksum = 0;
2398 uint16_t cnt;
2399 uint8_t *dptr1, *dptr2;
e315cd28 2400 struct qla_hw_data *ha = vha->hw;
0107109e 2401 init_cb_t *icb = ha->init_cb;
281afe19
SJ		 2402 nvram_t *nv = ha->nvram;
2403 uint8_t *ptr = ha->nvram;
3d71644c 2404 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 2405
4e08df3f
DM		 2406 rval = QLA_SUCCESS;
2407
1da177e4 2408 /* Determine NVRAM starting address. */
0107109e 2409 ha->nvram_size = sizeof(nvram_t);
1da177e4
LT		 2410 ha->nvram_base = 0;
2411 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
2412 if ((RD_REG_WORD(&reg->ctrl_status) >> 14) == 1)
2413 ha->nvram_base = 0x80;
2414
2415 /* Get NVRAM data and calculate checksum. */
e315cd28 2416 ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size);
0107109e
AV		 2417 for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++)
2418 chksum += *ptr++;
1da177e4 2419
7c3df132
SK		 2420 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
2421 "Contents of NVRAM.\n");
2422 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
2423 (uint8_t *)nv, ha->nvram_size);
1da177e4
LT		 2424
2425 /* Bad NVRAM data, set defaults parameters. */
2426 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' ||
2427 nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) {
2428 /* Reset NVRAM data. */
7c3df132 2429 ql_log(ql_log_warn, vha, 0x0064,
9e336520 2430 "Inconsistent NVRAM "
7c3df132
SK		 2431 "detected: checksum=0x%x id=%c version=0x%x.\n",
2432 chksum, nv->id[0], nv->nvram_version);
2433 ql_log(ql_log_warn, vha, 0x0065,
2434 "Falling back to "
2435 "functioning (yet invalid -- WWPN) defaults.\n");
4e08df3f
DM		 2436
2437 /*
2438 * Set default initialization control block.
2439 */
2440 memset(nv, 0, ha->nvram_size);
2441 nv->parameter_block_version = ICB_VERSION;
2442
2443 if (IS_QLA23XX(ha)) {
2444 nv->firmware_options[0] = BIT_2 | BIT_1;
2445 nv->firmware_options[1] = BIT_7 | BIT_5;
2446 nv->add_firmware_options[0] = BIT_5;
2447 nv->add_firmware_options[1] = BIT_5 | BIT_4;
2448 nv->frame_payload_size = __constant_cpu_to_le16(2048);
2449 nv->special_options[1] = BIT_7;
2450 } else if (IS_QLA2200(ha)) {
2451 nv->firmware_options[0] = BIT_2 | BIT_1;
2452 nv->firmware_options[1] = BIT_7 | BIT_5;
2453 nv->add_firmware_options[0] = BIT_5;
2454 nv->add_firmware_options[1] = BIT_5 | BIT_4;
2455 nv->frame_payload_size = __constant_cpu_to_le16(1024);
2456 } else if (IS_QLA2100(ha)) {
2457 nv->firmware_options[0] = BIT_3 | BIT_1;
2458 nv->firmware_options[1] = BIT_5;
2459 nv->frame_payload_size = __constant_cpu_to_le16(1024);
2460 }
2461
2462 nv->max_iocb_allocation = __constant_cpu_to_le16(256);
2463 nv->execution_throttle = __constant_cpu_to_le16(16);
2464 nv->retry_count = 8;
2465 nv->retry_delay = 1;
2466
2467 nv->port_name[0] = 33;
2468 nv->port_name[3] = 224;
2469 nv->port_name[4] = 139;
2470
e315cd28 2471 qla2xxx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 2472
2473 nv->login_timeout = 4;
2474
2475 /*
2476 * Set default host adapter parameters
2477 */
2478 nv->host_p[1] = BIT_2;
2479 nv->reset_delay = 5;
2480 nv->port_down_retry_count = 8;
2481 nv->max_luns_per_target = __constant_cpu_to_le16(8);
2482 nv->link_down_timeout = 60;
2483
2484 rval = 1;
1da177e4
LT		 2485 }
2486
2487#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
2488 /*
2489 * The SN2 does not provide BIOS emulation which means you can't change
2490 * potentially bogus BIOS settings. Force the use of default settings
2491 * for link rate and frame size. Hope that the rest of the settings
2492 * are valid.
2493 */
2494 if (ia64_platform_is("sn2")) {
2495 nv->frame_payload_size = __constant_cpu_to_le16(2048);
2496 if (IS_QLA23XX(ha))
2497 nv->special_options[1] = BIT_7;
2498 }
2499#endif
2500
2501 /* Reset Initialization control block */
0107109e 2502 memset(icb, 0, ha->init_cb_size);
1da177e4
LT		 2503
2504 /*
2505 * Setup driver NVRAM options.
2506 */
2507 nv->firmware_options[0] |= (BIT_6 | BIT_1);
2508 nv->firmware_options[0] &= ~(BIT_5 | BIT_4);
2509 nv->firmware_options[1] |= (BIT_5 | BIT_0);
2510 nv->firmware_options[1] &= ~BIT_4;
2511
2512 if (IS_QLA23XX(ha)) {
2513 nv->firmware_options[0] |= BIT_2;
2514 nv->firmware_options[0] &= ~BIT_3;
2d70c103 2515 nv->special_options[0] &= ~BIT_6;
0107109e 2516 nv->add_firmware_options[1] |= BIT_5 | BIT_4;
1da177e4
LT		 2517
2518 if (IS_QLA2300(ha)) {
2519 if (ha->fb_rev == FPM_2310) {
2520 strcpy(ha->model_number, "QLA2310");
2521 } else {
2522 strcpy(ha->model_number, "QLA2300");
2523 }
2524 } else {
e315cd28 2525 qla2x00_set_model_info(vha, nv->model_number,
9bb9fcf2 2526 sizeof(nv->model_number), "QLA23xx");
1da177e4
LT		 2527 }
2528 } else if (IS_QLA2200(ha)) {
2529 nv->firmware_options[0] |= BIT_2;
2530 /*
2531 * 'Point-to-point preferred, else loop' is not a safe
2532 * connection mode setting.
2533 */
2534 if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
2535 (BIT_5 | BIT_4)) {
2536 /* Force 'loop preferred, else point-to-point'. */
2537 nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
2538 nv->add_firmware_options[0] |= BIT_5;
2539 }
2540 strcpy(ha->model_number, "QLA22xx");
2541 } else /*if (IS_QLA2100(ha))*/ {
2542 strcpy(ha->model_number, "QLA2100");
2543 }
2544
2545 /*
2546 * Copy over NVRAM RISC parameter block to initialization control block.
2547 */
2548 dptr1 = (uint8_t *)icb;
2549 dptr2 = (uint8_t *)&nv->parameter_block_version;
2550 cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;
2551 while (cnt--)
2552 *dptr1++ = *dptr2++;
2553
2554 /* Copy 2nd half. */
2555 dptr1 = (uint8_t *)icb->add_firmware_options;
2556 cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;
2557 while (cnt--)
2558 *dptr1++ = *dptr2++;
2559
5341e868
AV		 2560 /* Use alternate WWN? */
2561 if (nv->host_p[1] & BIT_7) {
2562 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
2563 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
2564 }
2565
1da177e4
LT		 2566 /* Prepare nodename */
2567 if ((icb->firmware_options[1] & BIT_6) == 0) {
2568 /*
2569 * Firmware will apply the following mask if the nodename was
2570 * not provided.
2571 */
2572 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
2573 icb->node_name[0] &= 0xF0;
2574 }
2575
2576 /*
2577 * Set host adapter parameters.
2578 */
3ce8866c
SK		 2579
2580 /*
2581 * BIT_7 in the host-parameters section allows for modification to
2582 * internal driver logging.
2583 */
0181944f 2584 if (nv->host_p[0] & BIT_7)
cfb0919c 2585 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
1da177e4
LT		 2586 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
2587 /* Always load RISC code on non ISP2[12]00 chips. */
2588 if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
2589 ha->flags.disable_risc_code_load = 0;
2590 ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0);
2591 ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
2592 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
06c22bd1 2593 ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
d4c760c2 2594 ha->flags.disable_serdes = 0;
1da177e4
LT		 2595
2596 ha->operating_mode =
2597 (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
2598
2599 memcpy(ha->fw_seriallink_options, nv->seriallink_options,
2600 sizeof(ha->fw_seriallink_options));
2601
2602 /* save HBA serial number */
2603 ha->serial0 = icb->port_name[5];
2604 ha->serial1 = icb->port_name[6];
2605 ha->serial2 = icb->port_name[7];
e315cd28
AC		 2606 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
2607 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
1da177e4
LT		 2608
2609 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
2610
2611 ha->retry_count = nv->retry_count;
2612
2613 /* Set minimum login_timeout to 4 seconds. */
5b91490e 2614 if (nv->login_timeout != ql2xlogintimeout)
1da177e4
LT		 2615 nv->login_timeout = ql2xlogintimeout;
2616 if (nv->login_timeout < 4)
2617 nv->login_timeout = 4;
2618 ha->login_timeout = nv->login_timeout;
2619 icb->login_timeout = nv->login_timeout;
2620
00a537b8
AV		 2621 /* Set minimum RATOV to 100 tenths of a second. */
2622 ha->r_a_tov = 100;
1da177e4 2623
1da177e4
LT		 2624 ha->loop_reset_delay = nv->reset_delay;
2625
1da177e4
LT		 2626 /* Link Down Timeout = 0:
2627 *
2628 * When Port Down timer expires we will start returning
2629 * I/O's to OS with "DID_NO_CONNECT".
2630 *
2631 * Link Down Timeout != 0:
2632 *
2633 * The driver waits for the link to come up after link down
2634 * before returning I/Os to OS with "DID_NO_CONNECT".
fa2a1ce5 2635 */
1da177e4
LT		 2636 if (nv->link_down_timeout == 0) {
2637 ha->loop_down_abort_time =
354d6b21 2638 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
1da177e4
LT		 2639 } else {
2640 ha->link_down_timeout = nv->link_down_timeout;
2641 ha->loop_down_abort_time =
2642 (LOOP_DOWN_TIME - ha->link_down_timeout);
fa2a1ce5 2643 }
1da177e4 2644
1da177e4
LT		 2645 /*
2646 * Need enough time to try and get the port back.
2647 */
2648 ha->port_down_retry_count = nv->port_down_retry_count;
2649 if (qlport_down_retry)
2650 ha->port_down_retry_count = qlport_down_retry;
2651 /* Set login_retry_count */
2652 ha->login_retry_count = nv->retry_count;
2653 if (ha->port_down_retry_count == nv->port_down_retry_count &&
2654 ha->port_down_retry_count > 3)
2655 ha->login_retry_count = ha->port_down_retry_count;
2656 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
2657 ha->login_retry_count = ha->port_down_retry_count;
2658 if (ql2xloginretrycount)
2659 ha->login_retry_count = ql2xloginretrycount;
2660
1da177e4
LT		 2661 icb->lun_enables = __constant_cpu_to_le16(0);
2662 icb->command_resource_count = 0;
2663 icb->immediate_notify_resource_count = 0;
2664 icb->timeout = __constant_cpu_to_le16(0);
2665
2666 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
2667 /* Enable RIO */
2668 icb->firmware_options[0] &= ~BIT_3;
2669 icb->add_firmware_options[0] &=
2670 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
2671 icb->add_firmware_options[0] |= BIT_2;
2672 icb->response_accumulation_timer = 3;
2673 icb->interrupt_delay_timer = 5;
2674
e315cd28 2675 vha->flags.process_response_queue = 1;
1da177e4 2676 } else {
4fdfefe5 2677 /* Enable ZIO. */
e315cd28 2678 if (!vha->flags.init_done) {
4fdfefe5
AV		 2679 ha->zio_mode = icb->add_firmware_options[0] &
2680 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
2681 ha->zio_timer = icb->interrupt_delay_timer ?
2682 icb->interrupt_delay_timer: 2;
2683 }
1da177e4
LT		 2684 icb->add_firmware_options[0] &=
2685 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
e315cd28 2686 vha->flags.process_response_queue = 0;
4fdfefe5 2687 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d
AV		 2688 ha->zio_mode = QLA_ZIO_MODE_6;
2689
7c3df132 2690 ql_log(ql_log_info, vha, 0x0068,
4fdfefe5
AV		 2691 "ZIO mode %d enabled; timer delay (%d us).\n",
2692 ha->zio_mode, ha->zio_timer * 100);
1da177e4 2693
4fdfefe5
AV		 2694 icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;
2695 icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;
e315cd28 2696 vha->flags.process_response_queue = 1;
1da177e4
LT		 2697 }
2698 }
2699
4e08df3f 2700 if (rval) {
7c3df132
SK		 2701 ql_log(ql_log_warn, vha, 0x0069,
2702 "NVRAM configuration failed.\n");
4e08df3f
DM		 2703 }
2704 return (rval);
1da177e4
LT		 2705}
2706
19a7b4ae
JSEC		 2707static void
2708qla2x00_rport_del(void *data)
2709{
2710 fc_port_t *fcport = data;
d97994dc 2711 struct fc_rport *rport;
2d70c103 2712 scsi_qla_host_t *vha = fcport->vha;
044d78e1 2713 unsigned long flags;
d97994dc 2714
044d78e1 2715 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
ac280b67 2716 rport = fcport->drport ? fcport->drport: fcport->rport;
d97994dc 2717 fcport->drport = NULL;
044d78e1 2718 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
2d70c103 2719 if (rport) {
d97994dc 2720 fc_remote_port_delete(rport);
2d70c103
NB		 2721 /*
2722 * Release the target mode FC NEXUS in qla_target.c code
2723 * if target mod is enabled.
2724 */
2725 qlt_fc_port_deleted(vha, fcport);
2726 }
19a7b4ae
JSEC		 2727}
2728
1da177e4
LT		 2729/**
2730 * qla2x00_alloc_fcport() - Allocate a generic fcport.
2731 * @ha: HA context
2732 * @flags: allocation flags
2733 *
2734 * Returns a pointer to the allocated fcport, or NULL, if none available.
2735 */
9a069e19 2736fc_port_t *
e315cd28 2737qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags)
1da177e4
LT		 2738{
2739 fc_port_t *fcport;
2740
bbfbbbc1
MK		 2741 fcport = kzalloc(sizeof(fc_port_t), flags);
2742 if (!fcport)
2743 return NULL;
1da177e4
LT		 2744
2745 /* Setup fcport template structure. */
e315cd28 2746 fcport->vha = vha;
1da177e4
LT		 2747 fcport->port_type = FCT_UNKNOWN;
2748 fcport->loop_id = FC_NO_LOOP_ID;
ec426e10 2749 qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
ad3e0eda 2750 fcport->supported_classes = FC_COS_UNSPECIFIED;
1da177e4 2751
bbfbbbc1 2752 return fcport;
1da177e4
LT		 2753}
2754
2755/*
2756 * qla2x00_configure_loop
2757 * Updates Fibre Channel Device Database with what is actually on loop.
2758 *
2759 * Input:
2760 * ha = adapter block pointer.
2761 *
2762 * Returns:
2763 * 0 = success.
2764 * 1 = error.
2765 * 2 = database was full and device was not configured.
2766 */
2767static int
e315cd28 2768qla2x00_configure_loop(scsi_qla_host_t *vha)
1da177e4
LT		 2769{
2770 int rval;
2771 unsigned long flags, save_flags;
e315cd28 2772 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2773 rval = QLA_SUCCESS;
2774
2775 /* Get Initiator ID */
e315cd28
AC		 2776 if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) {
2777 rval = qla2x00_configure_hba(vha);
1da177e4 2778 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2779 ql_dbg(ql_dbg_disc, vha, 0x2013,
2780 "Unable to configure HBA.\n");
1da177e4
LT		 2781 return (rval);
2782 }
2783 }
2784
e315cd28 2785 save_flags = flags = vha->dpc_flags;
7c3df132
SK		 2786 ql_dbg(ql_dbg_disc, vha, 0x2014,
2787 "Configure loop -- dpc flags = 0x%lx.\n", flags);
1da177e4
LT		 2788
2789 /*
2790 * If we have both an RSCN and PORT UPDATE pending then handle them
2791 * both at the same time.
2792 */
e315cd28
AC		 2793 clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2794 clear_bit(RSCN_UPDATE, &vha->dpc_flags);
1da177e4 2795
3064ff39
MH		 2796 qla2x00_get_data_rate(vha);
2797
1da177e4
LT		 2798 /* Determine what we need to do */
2799 if (ha->current_topology == ISP_CFG_FL &&
2800 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
2801
1da177e4
LT		 2802 set_bit(RSCN_UPDATE, &flags);
2803
2804 } else if (ha->current_topology == ISP_CFG_F &&
2805 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
2806
1da177e4
LT		 2807 set_bit(RSCN_UPDATE, &flags);
2808 clear_bit(LOCAL_LOOP_UPDATE, &flags);
21333b48
AV		 2809
2810 } else if (ha->current_topology == ISP_CFG_N) {
2811 clear_bit(RSCN_UPDATE, &flags);
1da177e4 2812
e315cd28 2813 } else if (!vha->flags.online ||
1da177e4
LT		 2814 (test_bit(ABORT_ISP_ACTIVE, &flags))) {
2815
1da177e4
LT		 2816 set_bit(RSCN_UPDATE, &flags);
2817 set_bit(LOCAL_LOOP_UPDATE, &flags);
2818 }
2819
2820 if (test_bit(LOCAL_LOOP_UPDATE, &flags)) {
7c3df132
SK		 2821 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
2822 ql_dbg(ql_dbg_disc, vha, 0x2015,
2823 "Loop resync needed, failing.\n");
1da177e4 2824 rval = QLA_FUNCTION_FAILED;
642ef983 2825 } else
e315cd28 2826 rval = qla2x00_configure_local_loop(vha);
1da177e4
LT		 2827 }
2828
2829 if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
7c3df132
SK		 2830 if (LOOP_TRANSITION(vha)) {
2831 ql_dbg(ql_dbg_disc, vha, 0x201e,
2832 "Needs RSCN update and loop transition.\n");
1da177e4 2833 rval = QLA_FUNCTION_FAILED;
7c3df132 2834 }
e315cd28
AC		 2835 else
2836 rval = qla2x00_configure_fabric(vha);
1da177e4
LT		 2837 }
2838
2839 if (rval == QLA_SUCCESS) {
e315cd28
AC		 2840 if (atomic_read(&vha->loop_down_timer) ||
2841 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4
LT		 2842 rval = QLA_FUNCTION_FAILED;
2843 } else {
e315cd28 2844 atomic_set(&vha->loop_state, LOOP_READY);
7c3df132
SK		 2845 ql_dbg(ql_dbg_disc, vha, 0x2069,
2846 "LOOP READY.\n");
1da177e4
LT		 2847 }
2848 }
2849
2850 if (rval) {
7c3df132
SK		 2851 ql_dbg(ql_dbg_disc, vha, 0x206a,
2852 "%s *** FAILED ***.\n", __func__);
1da177e4 2853 } else {
7c3df132
SK		 2854 ql_dbg(ql_dbg_disc, vha, 0x206b,
2855 "%s: exiting normally.\n", __func__);
1da177e4
LT		 2856 }
2857
cc3ef7bc 2858 /* Restore state if a resync event occurred during processing */
e315cd28 2859 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4 2860 if (test_bit(LOCAL_LOOP_UPDATE, &save_flags))
e315cd28 2861 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
f4658b6c 2862 if (test_bit(RSCN_UPDATE, &save_flags)) {
e315cd28 2863 set_bit(RSCN_UPDATE, &vha->dpc_flags);
f4658b6c 2864 }
1da177e4
LT		 2865 }
2866
2867 return (rval);
2868}
2869
2870
2871
2872/*
2873 * qla2x00_configure_local_loop
2874 * Updates Fibre Channel Device Database with local loop devices.
2875 *
2876 * Input:
2877 * ha = adapter block pointer.
2878 *
2879 * Returns:
2880 * 0 = success.
2881 */
2882static int
e315cd28 2883qla2x00_configure_local_loop(scsi_qla_host_t *vha)
1da177e4
LT		 2884{
2885 int rval, rval2;
2886 int found_devs;
2887 int found;
2888 fc_port_t *fcport, *new_fcport;
2889
2890 uint16_t index;
2891 uint16_t entries;
2892 char *id_iter;
2893 uint16_t loop_id;
2894 uint8_t domain, area, al_pa;
e315cd28 2895 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2896
2897 found_devs = 0;
2898 new_fcport = NULL;
642ef983 2899 entries = MAX_FIBRE_DEVICES_LOOP;
1da177e4 2900
1da177e4 2901 /* Get list of logged in devices. */
642ef983 2902 memset(ha->gid_list, 0, qla2x00_gid_list_size(ha));
e315cd28 2903 rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma,
1da177e4
LT		 2904 &entries);
2905 if (rval != QLA_SUCCESS)
2906 goto cleanup_allocation;
2907
7c3df132
SK		 2908 ql_dbg(ql_dbg_disc, vha, 0x2017,
2909 "Entries in ID list (%d).\n", entries);
2910 ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
2911 (uint8_t *)ha->gid_list,
2912 entries * sizeof(struct gid_list_info));
1da177e4
LT		 2913
2914 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 2915 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 2916 if (new_fcport == NULL) {
7c3df132
SK		 2917 ql_log(ql_log_warn, vha, 0x2018,
2918 "Memory allocation failed for fcport.\n");
1da177e4
LT		 2919 rval = QLA_MEMORY_ALLOC_FAILED;
2920 goto cleanup_allocation;
2921 }
2922 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
2923
2924 /*
2925 * Mark local devices that were present with FCF_DEVICE_LOST for now.
2926 */
e315cd28 2927 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 2928 if (atomic_read(&fcport->state) == FCS_ONLINE &&
2929 fcport->port_type != FCT_BROADCAST &&
2930 (fcport->flags & FCF_FABRIC_DEVICE) == 0) {
2931
7c3df132
SK		 2932 ql_dbg(ql_dbg_disc, vha, 0x2019,
2933 "Marking port lost loop_id=0x%04x.\n",
2934 fcport->loop_id);
1da177e4 2935
ec426e10 2936 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 2937 }
2938 }
2939
2940 /* Add devices to port list. */
2941 id_iter = (char *)ha->gid_list;
2942 for (index = 0; index < entries; index++) {
2943 domain = ((struct gid_list_info *)id_iter)->domain;
2944 area = ((struct gid_list_info *)id_iter)->area;
2945 al_pa = ((struct gid_list_info *)id_iter)->al_pa;
abbd8870 2946 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1da177e4
LT		 2947 loop_id = (uint16_t)
2948 ((struct gid_list_info *)id_iter)->loop_id_2100;
abbd8870 2949 else
1da177e4
LT		 2950 loop_id = le16_to_cpu(
2951 ((struct gid_list_info *)id_iter)->loop_id);
abbd8870 2952 id_iter += ha->gid_list_info_size;
1da177e4
LT		 2953
2954 /* Bypass reserved domain fields. */
2955 if ((domain & 0xf0) == 0xf0)
2956 continue;
2957
2958 /* Bypass if not same domain and area of adapter. */
f7d289f6 2959 if (area && domain &&
e315cd28 2960 (area != vha->d_id.b.area || domain != vha->d_id.b.domain))
1da177e4
LT		 2961 continue;
2962
2963 /* Bypass invalid local loop ID. */
2964 if (loop_id > LAST_LOCAL_LOOP_ID)
2965 continue;
2966
370d550e
AE		 2967 memset(new_fcport, 0, sizeof(fc_port_t));
2968
1da177e4
LT		 2969 /* Fill in member data. */
2970 new_fcport->d_id.b.domain = domain;
2971 new_fcport->d_id.b.area = area;
2972 new_fcport->d_id.b.al_pa = al_pa;
2973 new_fcport->loop_id = loop_id;
e315cd28 2974 rval2 = qla2x00_get_port_database(vha, new_fcport, 0);
1da177e4 2975 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 2976 ql_dbg(ql_dbg_disc, vha, 0x201a,
2977 "Failed to retrieve fcport information "
2978 "-- get_port_database=%x, loop_id=0x%04x.\n",
2979 rval2, new_fcport->loop_id);
2980 ql_dbg(ql_dbg_disc, vha, 0x201b,
2981 "Scheduling resync.\n");
e315cd28 2982 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4
LT		 2983 continue;
2984 }
2985
2986 /* Check for matching device in port list. */
2987 found = 0;
2988 fcport = NULL;
e315cd28 2989 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 2990 if (memcmp(new_fcport->port_name, fcport->port_name,
2991 WWN_SIZE))
2992 continue;
2993
ddb9b126 2994 fcport->flags &= ~FCF_FABRIC_DEVICE;
1da177e4
LT		 2995 fcport->loop_id = new_fcport->loop_id;
2996 fcport->port_type = new_fcport->port_type;
2997 fcport->d_id.b24 = new_fcport->d_id.b24;
2998 memcpy(fcport->node_name, new_fcport->node_name,
2999 WWN_SIZE);
3000
3001 found++;
3002 break;
3003 }
3004
3005 if (!found) {
3006 /* New device, add to fcports list. */
e315cd28 3007 list_add_tail(&new_fcport->list, &vha->vp_fcports);
1da177e4
LT		 3008
3009 /* Allocate a new replacement fcport. */
3010 fcport = new_fcport;
e315cd28 3011 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3012 if (new_fcport == NULL) {
7c3df132
SK		 3013 ql_log(ql_log_warn, vha, 0x201c,
3014 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 3015 rval = QLA_MEMORY_ALLOC_FAILED;
3016 goto cleanup_allocation;
3017 }
3018 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
3019 }
3020
d8b45213 3021 /* Base iIDMA settings on HBA port speed. */
a3cbdfad 3022 fcport->fp_speed = ha->link_data_rate;
d8b45213 3023
e315cd28 3024 qla2x00_update_fcport(vha, fcport);
1da177e4
LT		 3025
3026 found_devs++;
3027 }
3028
3029cleanup_allocation:
c9475cb0 3030 kfree(new_fcport);
1da177e4
LT		 3031
3032 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3033 ql_dbg(ql_dbg_disc, vha, 0x201d,
3034 "Configure local loop error exit: rval=%x.\n", rval);
1da177e4
LT		 3035 }
3036
1da177e4
LT		 3037 return (rval);
3038}
3039
d8b45213 3040static void
e315cd28 3041qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
d8b45213 3042{
d8b45213 3043 int rval;
1bb39548 3044 uint16_t mb[4];
e315cd28 3045 struct qla_hw_data *ha = vha->hw;
d8b45213 3046
c76f2c01 3047 if (!IS_IIDMA_CAPABLE(ha))
d8b45213
AV		 3048 return;
3049
c9afb9a2
GM		 3050 if (atomic_read(&fcport->state) != FCS_ONLINE)
3051 return;
3052
39bd9622
AV		 3053 if (fcport->fp_speed == PORT_SPEED_UNKNOWN ||
3054 fcport->fp_speed > ha->link_data_rate)
d8b45213
AV		 3055 return;
3056
e315cd28 3057 rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed,
a3cbdfad 3058 mb);
d8b45213 3059 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3060 ql_dbg(ql_dbg_disc, vha, 0x2004,
3061 "Unable to adjust iIDMA "
3062 "%02x%02x%02x%02x%02x%02x%02x%02x -- %04x %x %04x "
3063 "%04x.\n", fcport->port_name[0], fcport->port_name[1],
d8b45213
AV		 3064 fcport->port_name[2], fcport->port_name[3],
3065 fcport->port_name[4], fcport->port_name[5],
3066 fcport->port_name[6], fcport->port_name[7], rval,
7c3df132 3067 fcport->fp_speed, mb[0], mb[1]);
d8b45213 3068 } else {
7c3df132
SK		 3069 ql_dbg(ql_dbg_disc, vha, 0x2005,
3070 "iIDMA adjusted to %s GB/s "
d0297c9a
JC		 3071 "on %02x%02x%02x%02x%02x%02x%02x%02x.\n",
3072 qla2x00_get_link_speed_str(ha, fcport->fp_speed),
7c3df132
SK		 3073 fcport->port_name[0], fcport->port_name[1],
3074 fcport->port_name[2], fcport->port_name[3],
3075 fcport->port_name[4], fcport->port_name[5],
3076 fcport->port_name[6], fcport->port_name[7]);
d8b45213
AV		 3077 }
3078}
3079
23be331d 3080static void
e315cd28 3081qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport)
8482e118
AV		 3082{
3083 struct fc_rport_identifiers rport_ids;
bdf79621 3084 struct fc_rport *rport;
044d78e1 3085 unsigned long flags;
8482e118 3086
ac280b67 3087 qla2x00_rport_del(fcport);
8482e118 3088
f8b02a85
AV		 3089 rport_ids.node_name = wwn_to_u64(fcport->node_name);
3090 rport_ids.port_name = wwn_to_u64(fcport->port_name);
8482e118
AV		 3091 rport_ids.port_id = fcport->d_id.b.domain << 16 |
3092 fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa;
77d74143 3093 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
e315cd28 3094 fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids);
77d74143 3095 if (!rport) {
7c3df132
SK		 3096 ql_log(ql_log_warn, vha, 0x2006,
3097 "Unable to allocate fc remote port.\n");
77d74143
AV		 3098 return;
3099 }
2d70c103
NB		 3100 /*
3101 * Create target mode FC NEXUS in qla_target.c if target mode is
3102 * enabled..
3103 */
3104 qlt_fc_port_added(vha, fcport);
3105
044d78e1 3106 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
19a7b4ae 3107 *((fc_port_t **)rport->dd_data) = fcport;
044d78e1 3108 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
d97994dc 3109
ad3e0eda 3110 rport->supported_classes = fcport->supported_classes;
77d74143 3111
8482e118
AV		 3112 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
3113 if (fcport->port_type == FCT_INITIATOR)
3114 rport_ids.roles |= FC_RPORT_ROLE_FCP_INITIATOR;
3115 if (fcport->port_type == FCT_TARGET)
3116 rport_ids.roles |= FC_RPORT_ROLE_FCP_TARGET;
77d74143 3117 fc_remote_port_rolechg(rport, rport_ids.roles);
1da177e4
LT		 3118}
3119
23be331d
AB		 3120/*
3121 * qla2x00_update_fcport
3122 * Updates device on list.
3123 *
3124 * Input:
3125 * ha = adapter block pointer.
3126 * fcport = port structure pointer.
3127 *
3128 * Return:
3129 * 0 - Success
3130 * BIT_0 - error
3131 *
3132 * Context:
3133 * Kernel context.
3134 */
3135void
e315cd28 3136qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
23be331d 3137{
e315cd28 3138 fcport->vha = vha;
23be331d 3139 fcport->login_retry = 0;
5ff1d584 3140 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
23be331d 3141
1f93da52 3142 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
e315cd28 3143 qla2x00_iidma_fcport(vha, fcport);
21090cbe 3144 qla24xx_update_fcport_fcp_prio(vha, fcport);
e315cd28 3145 qla2x00_reg_remote_port(vha, fcport);
23be331d
AB		 3146}
3147
1da177e4
LT		 3148/*
3149 * qla2x00_configure_fabric
3150 * Setup SNS devices with loop ID's.
3151 *
3152 * Input:
3153 * ha = adapter block pointer.
3154 *
3155 * Returns:
3156 * 0 = success.
3157 * BIT_0 = error
3158 */
3159static int
e315cd28 3160qla2x00_configure_fabric(scsi_qla_host_t *vha)
1da177e4 3161{
b3b02e6e 3162 int rval;
e452ceb6 3163 fc_port_t *fcport, *fcptemp;
1da177e4
LT		 3164 uint16_t next_loopid;
3165 uint16_t mb[MAILBOX_REGISTER_COUNT];
0107109e 3166 uint16_t loop_id;
1da177e4 3167 LIST_HEAD(new_fcports);
e315cd28
AC		 3168 struct qla_hw_data *ha = vha->hw;
3169 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 3170
3171 /* If FL port exists, then SNS is present */
e428924c 3172 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 3173 loop_id = NPH_F_PORT;
3174 else
3175 loop_id = SNS_FL_PORT;
e315cd28 3176 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1);
1da177e4 3177 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3178 ql_dbg(ql_dbg_disc, vha, 0x201f,
3179 "MBX_GET_PORT_NAME failed, No FL Port.\n");
1da177e4 3180
e315cd28 3181 vha->device_flags &= ~SWITCH_FOUND;
1da177e4
LT		 3182 return (QLA_SUCCESS);
3183 }
e315cd28 3184 vha->device_flags |= SWITCH_FOUND;
1da177e4 3185
1da177e4 3186 do {
cca5335c
AV		 3187 /* FDMI support. */
3188 if (ql2xfdmienable &&
e315cd28
AC		 3189 test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags))
3190 qla2x00_fdmi_register(vha);
cca5335c 3191
1da177e4 3192 /* Ensure we are logged into the SNS. */
e428924c 3193 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 3194 loop_id = NPH_SNS;
3195 else
3196 loop_id = SIMPLE_NAME_SERVER;
0b91d116
CD		 3197 rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff,
3198 0xfc, mb, BIT_1|BIT_0);
3199 if (rval != QLA_SUCCESS) {
3200 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
e452ceb6 3201 return rval;
0b91d116 3202 }
1da177e4 3203 if (mb[0] != MBS_COMMAND_COMPLETE) {
7c3df132
SK		 3204 ql_dbg(ql_dbg_disc, vha, 0x2042,
3205 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x "
3206 "mb[6]=%x mb[7]=%x.\n", loop_id, mb[0], mb[1],
3207 mb[2], mb[6], mb[7]);
1da177e4
LT		 3208 return (QLA_SUCCESS);
3209 }
3210
e315cd28
AC		 3211 if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) {
3212 if (qla2x00_rft_id(vha)) {
1da177e4 3213 /* EMPTY */
7c3df132
SK		 3214 ql_dbg(ql_dbg_disc, vha, 0x2045,
3215 "Register FC-4 TYPE failed.\n");
1da177e4 3216 }
e315cd28 3217 if (qla2x00_rff_id(vha)) {
1da177e4 3218 /* EMPTY */
7c3df132
SK		 3219 ql_dbg(ql_dbg_disc, vha, 0x2049,
3220 "Register FC-4 Features failed.\n");
1da177e4 3221 }
e315cd28 3222 if (qla2x00_rnn_id(vha)) {
1da177e4 3223 /* EMPTY */
7c3df132
SK		 3224 ql_dbg(ql_dbg_disc, vha, 0x204f,
3225 "Register Node Name failed.\n");
e315cd28 3226 } else if (qla2x00_rsnn_nn(vha)) {
1da177e4 3227 /* EMPTY */
7c3df132
SK		 3228 ql_dbg(ql_dbg_disc, vha, 0x2053,
3229 "Register Symobilic Node Name failed.\n");
1da177e4
LT		 3230 }
3231 }
3232
827210ba
JC		 3233#define QLA_FCPORT_SCAN 1
3234#define QLA_FCPORT_FOUND 2
3235
3236 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3237 fcport->scan_state = QLA_FCPORT_SCAN;
3238 }
3239
e315cd28 3240 rval = qla2x00_find_all_fabric_devs(vha, &new_fcports);
1da177e4
LT		 3241 if (rval != QLA_SUCCESS)
3242 break;
3243
e452ceb6
JC		 3244 /*
3245 * Logout all previous fabric devices marked lost, except
3246 * FCP2 devices.
3247 */
e315cd28
AC		 3248 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3249 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
1da177e4
LT		 3250 break;
3251
3252 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0)
3253 continue;
3254
827210ba 3255 if (fcport->scan_state == QLA_FCPORT_SCAN &&
b3b02e6e 3256 atomic_read(&fcport->state) == FCS_ONLINE) {
e315cd28 3257 qla2x00_mark_device_lost(vha, fcport,
d97994dc 3258 ql2xplogiabsentdevice, 0);
1da177e4 3259 if (fcport->loop_id != FC_NO_LOOP_ID &&
f08b7251 3260 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
1da177e4
LT		 3261 fcport->port_type != FCT_INITIATOR &&
3262 fcport->port_type != FCT_BROADCAST) {
e315cd28 3263 ha->isp_ops->fabric_logout(vha,
1c7c6357
AV		 3264 fcport->loop_id,
3265 fcport->d_id.b.domain,
3266 fcport->d_id.b.area,
3267 fcport->d_id.b.al_pa);
e452ceb6 3268 fcport->loop_id = FC_NO_LOOP_ID;
1da177e4
LT		 3269 }
3270 }
e452ceb6 3271 }
1da177e4 3272
e452ceb6
JC		 3273 /* Starting free loop ID. */
3274 next_loopid = ha->min_external_loopid;
3275
3276 /*
3277 * Scan through our port list and login entries that need to be
3278 * logged in.
3279 */
3280 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3281 if (atomic_read(&vha->loop_down_timer) ||
3282 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3283 break;
3284
3285 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0 ||
3286 (fcport->flags & FCF_LOGIN_NEEDED) == 0)
3287 continue;
3288
3289 if (fcport->loop_id == FC_NO_LOOP_ID) {
3290 fcport->loop_id = next_loopid;
3291 rval = qla2x00_find_new_loop_id(
3292 base_vha, fcport);
3293 if (rval != QLA_SUCCESS) {
3294 /* Ran out of IDs to use */
3295 break;
1da177e4
LT		 3296 }
3297 }
e452ceb6
JC		 3298 /* Login and update database */
3299 qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
3300 }
3301
3302 /* Exit if out of loop IDs. */
3303 if (rval != QLA_SUCCESS) {
3304 break;
3305 }
3306
3307 /*
3308 * Login and add the new devices to our port list.
3309 */
3310 list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) {
3311 if (atomic_read(&vha->loop_down_timer) ||
3312 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3313 break;
3314
3315 /* Find a new loop ID to use. */
3316 fcport->loop_id = next_loopid;
3317 rval = qla2x00_find_new_loop_id(base_vha, fcport);
3318 if (rval != QLA_SUCCESS) {
3319 /* Ran out of IDs to use */
3320 break;
3321 }
1da177e4 3322
bdf79621 3323 /* Login and update database */
e315cd28 3324 qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
e452ceb6
JC		 3325
3326 list_move_tail(&fcport->list, &vha->vp_fcports);
1da177e4
LT		 3327 }
3328 } while (0);
3329
e452ceb6
JC		 3330 /* Free all new device structures not processed. */
3331 list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) {
3332 list_del(&fcport->list);
3333 kfree(fcport);
3334 }
3335
1da177e4 3336 if (rval) {
7c3df132
SK		 3337 ql_dbg(ql_dbg_disc, vha, 0x2068,
3338 "Configure fabric error exit rval=%d.\n", rval);
1da177e4
LT		 3339 }
3340
3341 return (rval);
3342}
3343
1da177e4
LT		 3344/*
3345 * qla2x00_find_all_fabric_devs
3346 *
3347 * Input:
3348 * ha = adapter block pointer.
3349 * dev = database device entry pointer.
3350 *
3351 * Returns:
3352 * 0 = success.
3353 *
3354 * Context:
3355 * Kernel context.
3356 */
3357static int
e315cd28
AC		 3358qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha,
3359 struct list_head *new_fcports)
1da177e4
LT		 3360{
3361 int rval;
3362 uint16_t loop_id;
3363 fc_port_t *fcport, *new_fcport, *fcptemp;
3364 int found;
3365
3366 sw_info_t *swl;
3367 int swl_idx;
3368 int first_dev, last_dev;
1516ef44 3369 port_id_t wrap = {}, nxt_d_id;
e315cd28 3370 struct qla_hw_data *ha = vha->hw;
bb4cf5b7 3371 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 3372
3373 rval = QLA_SUCCESS;
3374
3375 /* Try GID_PT to get device list, else GAN. */
7a67735b 3376 if (!ha->swl)
642ef983 3377 ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t),
7a67735b
AV		 3378 GFP_KERNEL);
3379 swl = ha->swl;
bbfbbbc1 3380 if (!swl) {
1da177e4 3381 /*EMPTY*/
7c3df132
SK		 3382 ql_dbg(ql_dbg_disc, vha, 0x2054,
3383 "GID_PT allocations failed, fallback on GA_NXT.\n");
1da177e4 3384 } else {
642ef983 3385 memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t));
e315cd28 3386 if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) {
1da177e4 3387 swl = NULL;
e315cd28 3388 } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 3389 swl = NULL;
e315cd28 3390 } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 3391 swl = NULL;
e5896bd5 3392 } else if (ql2xiidmaenable &&
e315cd28
AC		 3393 qla2x00_gfpn_id(vha, swl) == QLA_SUCCESS) {
3394 qla2x00_gpsc(vha, swl);
1da177e4 3395 }
e8c72ba5
CD		 3396
3397 /* If other queries succeeded probe for FC-4 type */
3398 if (swl)
3399 qla2x00_gff_id(vha, swl);
1da177e4
LT		 3400 }
3401 swl_idx = 0;
3402
3403 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 3404 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3405 if (new_fcport == NULL) {
7c3df132
SK		 3406 ql_log(ql_log_warn, vha, 0x205e,
3407 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 3408 return (QLA_MEMORY_ALLOC_FAILED);
3409 }
3410 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
1da177e4
LT		 3411 /* Set start port ID scan at adapter ID. */
3412 first_dev = 1;
3413 last_dev = 0;
3414
3415 /* Starting free loop ID. */
e315cd28
AC		 3416 loop_id = ha->min_external_loopid;
3417 for (; loop_id <= ha->max_loop_id; loop_id++) {
3418 if (qla2x00_is_reserved_id(vha, loop_id))
1da177e4
LT		 3419 continue;
3420
3a6478df
GM		 3421 if (ha->current_topology == ISP_CFG_FL &&
3422 (atomic_read(&vha->loop_down_timer) ||
3423 LOOP_TRANSITION(vha))) {
bb2d52b2
AV		 3424 atomic_set(&vha->loop_down_timer, 0);
3425 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
3426 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
1da177e4 3427 break;
bb2d52b2 3428 }
1da177e4
LT		 3429
3430 if (swl != NULL) {
3431 if (last_dev) {
3432 wrap.b24 = new_fcport->d_id.b24;
3433 } else {
3434 new_fcport->d_id.b24 = swl[swl_idx].d_id.b24;
3435 memcpy(new_fcport->node_name,
3436 swl[swl_idx].node_name, WWN_SIZE);
3437 memcpy(new_fcport->port_name,
3438 swl[swl_idx].port_name, WWN_SIZE);
d8b45213
AV		 3439 memcpy(new_fcport->fabric_port_name,
3440 swl[swl_idx].fabric_port_name, WWN_SIZE);
3441 new_fcport->fp_speed = swl[swl_idx].fp_speed;
e8c72ba5 3442 new_fcport->fc4_type = swl[swl_idx].fc4_type;
1da177e4
LT		 3443
3444 if (swl[swl_idx].d_id.b.rsvd_1 != 0) {
3445 last_dev = 1;
3446 }
3447 swl_idx++;
3448 }
3449 } else {
3450 /* Send GA_NXT to the switch */
e315cd28 3451 rval = qla2x00_ga_nxt(vha, new_fcport);
1da177e4 3452 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3453 ql_log(ql_log_warn, vha, 0x2064,
3454 "SNS scan failed -- assuming "
3455 "zero-entry result.\n");
1da177e4
LT		 3456 list_for_each_entry_safe(fcport, fcptemp,
3457 new_fcports, list) {
3458 list_del(&fcport->list);
3459 kfree(fcport);
3460 }
3461 rval = QLA_SUCCESS;
3462 break;
3463 }
3464 }
3465
3466 /* If wrap on switch device list, exit. */
3467 if (first_dev) {
3468 wrap.b24 = new_fcport->d_id.b24;
3469 first_dev = 0;
3470 } else if (new_fcport->d_id.b24 == wrap.b24) {
7c3df132
SK		 3471 ql_dbg(ql_dbg_disc, vha, 0x2065,
3472 "Device wrap (%02x%02x%02x).\n",
3473 new_fcport->d_id.b.domain,
3474 new_fcport->d_id.b.area,
3475 new_fcport->d_id.b.al_pa);
1da177e4
LT		 3476 break;
3477 }
3478
2c3dfe3f 3479 /* Bypass if same physical adapter. */
e315cd28 3480 if (new_fcport->d_id.b24 == base_vha->d_id.b24)
1da177e4
LT		 3481 continue;
3482
2c3dfe3f 3483 /* Bypass virtual ports of the same host. */
bb4cf5b7
CD		 3484 if (qla2x00_is_a_vp_did(vha, new_fcport->d_id.b24))
3485 continue;
2c3dfe3f 3486
f7d289f6
AV		 3487 /* Bypass if same domain and area of adapter. */
3488 if (((new_fcport->d_id.b24 & 0xffff00) ==
e315cd28 3489 (vha->d_id.b24 & 0xffff00)) && ha->current_topology ==
f7d289f6
AV		 3490 ISP_CFG_FL)
3491 continue;
3492
1da177e4
LT		 3493 /* Bypass reserved domain fields. */
3494 if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0)
3495 continue;
3496
e8c72ba5 3497 /* Bypass ports whose FCP-4 type is not FCP_SCSI */
4da26e16
CD		 3498 if (ql2xgffidenable &&
3499 (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI &&
3500 new_fcport->fc4_type != FC4_TYPE_UNKNOWN))
e8c72ba5
CD		 3501 continue;
3502
1da177e4
LT		 3503 /* Locate matching device in database. */
3504 found = 0;
e315cd28 3505 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 3506 if (memcmp(new_fcport->port_name, fcport->port_name,
3507 WWN_SIZE))
3508 continue;
3509
827210ba 3510 fcport->scan_state = QLA_FCPORT_FOUND;
b3b02e6e 3511
1da177e4
LT		 3512 found++;
3513
d8b45213
AV		 3514 /* Update port state. */
3515 memcpy(fcport->fabric_port_name,
3516 new_fcport->fabric_port_name, WWN_SIZE);
3517 fcport->fp_speed = new_fcport->fp_speed;
3518
1da177e4
LT		 3519 /*
3520 * If address the same and state FCS_ONLINE, nothing
3521 * changed.
3522 */
3523 if (fcport->d_id.b24 == new_fcport->d_id.b24 &&
3524 atomic_read(&fcport->state) == FCS_ONLINE) {
3525 break;
3526 }
3527
3528 /*
3529 * If device was not a fabric device before.
3530 */
3531 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) {
3532 fcport->d_id.b24 = new_fcport->d_id.b24;
5f16b331 3533 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 3534 fcport->flags |= (FCF_FABRIC_DEVICE |
3535 FCF_LOGIN_NEEDED);
1da177e4
LT		 3536 break;
3537 }
3538
3539 /*
3540 * Port ID changed or device was marked to be updated;
3541 * Log it out if still logged in and mark it for
3542 * relogin later.
3543 */
3544 fcport->d_id.b24 = new_fcport->d_id.b24;
3545 fcport->flags |= FCF_LOGIN_NEEDED;
3546 if (fcport->loop_id != FC_NO_LOOP_ID &&
f08b7251 3547 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
0eba25df 3548 (fcport->flags & FCF_ASYNC_SENT) == 0 &&
1da177e4
LT		 3549 fcport->port_type != FCT_INITIATOR &&
3550 fcport->port_type != FCT_BROADCAST) {
e315cd28 3551 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3552 fcport->d_id.b.domain, fcport->d_id.b.area,
3553 fcport->d_id.b.al_pa);
5f16b331 3554 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 3555 }
3556
3557 break;
3558 }
3559
3560 if (found)
3561 continue;
1da177e4
LT		 3562 /* If device was not in our fcports list, then add it. */
3563 list_add_tail(&new_fcport->list, new_fcports);
3564
3565 /* Allocate a new replacement fcport. */
3566 nxt_d_id.b24 = new_fcport->d_id.b24;
e315cd28 3567 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3568 if (new_fcport == NULL) {
7c3df132
SK		 3569 ql_log(ql_log_warn, vha, 0x2066,
3570 "Memory allocation failed for fcport.\n");
1da177e4
LT		 3571 return (QLA_MEMORY_ALLOC_FAILED);
3572 }
3573 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
3574 new_fcport->d_id.b24 = nxt_d_id.b24;
3575 }
3576
c9475cb0 3577 kfree(new_fcport);
1da177e4 3578
1da177e4
LT		 3579 return (rval);
3580}
3581
3582/*
3583 * qla2x00_find_new_loop_id
3584 * Scan through our port list and find a new usable loop ID.
3585 *
3586 * Input:
3587 * ha: adapter state pointer.
3588 * dev: port structure pointer.
3589 *
3590 * Returns:
3591 * qla2x00 local function return status code.
3592 *
3593 * Context:
3594 * Kernel context.
3595 */
03bcfb57 3596int
e315cd28 3597qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
1da177e4
LT		 3598{
3599 int rval;
e315cd28 3600 struct qla_hw_data *ha = vha->hw;
feafb7b1 3601 unsigned long flags = 0;
1da177e4
LT		 3602
3603 rval = QLA_SUCCESS;
3604
5f16b331 3605 spin_lock_irqsave(&ha->vport_slock, flags);
1da177e4 3606
5f16b331
CD		 3607 dev->loop_id = find_first_zero_bit(ha->loop_id_map,
3608 LOOPID_MAP_SIZE);
3609 if (dev->loop_id >= LOOPID_MAP_SIZE ||
3610 qla2x00_is_reserved_id(vha, dev->loop_id)) {
3611 dev->loop_id = FC_NO_LOOP_ID;
3612 rval = QLA_FUNCTION_FAILED;
3613 } else
3614 set_bit(dev->loop_id, ha->loop_id_map);
1da177e4 3615
5f16b331 3616 spin_unlock_irqrestore(&ha->vport_slock, flags);
1da177e4 3617
5f16b331
CD		 3618 if (rval == QLA_SUCCESS)
3619 ql_dbg(ql_dbg_disc, dev->vha, 0x2086,
3620 "Assigning new loopid=%x, portid=%x.\n",
3621 dev->loop_id, dev->d_id.b24);
3622 else
3623 ql_log(ql_log_warn, dev->vha, 0x2087,
3624 "No loop_id's available, portid=%x.\n",
3625 dev->d_id.b24);
1da177e4
LT		 3626
3627 return (rval);
3628}
3629
1da177e4
LT		 3630/*
3631 * qla2x00_fabric_dev_login
3632 * Login fabric target device and update FC port database.
3633 *
3634 * Input:
3635 * ha: adapter state pointer.
3636 * fcport: port structure list pointer.
3637 * next_loopid: contains value of a new loop ID that can be used
3638 * by the next login attempt.
3639 *
3640 * Returns:
3641 * qla2x00 local function return status code.
3642 *
3643 * Context:
3644 * Kernel context.
3645 */
3646static int
e315cd28 3647qla2x00_fabric_dev_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 3648 uint16_t *next_loopid)
3649{
3650 int rval;
3651 int retry;
0107109e 3652 uint8_t opts;
e315cd28 3653 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3654
3655 rval = QLA_SUCCESS;
3656 retry = 0;
3657
ac280b67 3658 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584
AV		 3659 if (fcport->flags & FCF_ASYNC_SENT)
3660 return rval;
3661 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 3662 rval = qla2x00_post_async_login_work(vha, fcport, NULL);
3663 if (!rval)
3664 return rval;
3665 }
3666
5ff1d584 3667 fcport->flags &= ~FCF_ASYNC_SENT;
e315cd28 3668 rval = qla2x00_fabric_login(vha, fcport, next_loopid);
1da177e4 3669 if (rval == QLA_SUCCESS) {
f08b7251 3670 /* Send an ADISC to FCP2 devices.*/
0107109e 3671 opts = 0;
f08b7251 3672 if (fcport->flags & FCF_FCP2_DEVICE)
0107109e 3673 opts |= BIT_1;
e315cd28 3674 rval = qla2x00_get_port_database(vha, fcport, opts);
1da177e4 3675 if (rval != QLA_SUCCESS) {
e315cd28 3676 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3677 fcport->d_id.b.domain, fcport->d_id.b.area,
3678 fcport->d_id.b.al_pa);
e315cd28 3679 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4 3680 } else {
e315cd28 3681 qla2x00_update_fcport(vha, fcport);
1da177e4 3682 }
0b91d116
CD		 3683 } else {
3684 /* Retry Login. */
3685 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 3686 }
3687
3688 return (rval);
3689}
3690
3691/*
3692 * qla2x00_fabric_login
3693 * Issue fabric login command.
3694 *
3695 * Input:
3696 * ha = adapter block pointer.
3697 * device = pointer to FC device type structure.
3698 *
3699 * Returns:
3700 * 0 - Login successfully
3701 * 1 - Login failed
3702 * 2 - Initiator device
3703 * 3 - Fatal error
3704 */
3705int
e315cd28 3706qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 3707 uint16_t *next_loopid)
3708{
3709 int rval;
3710 int retry;
3711 uint16_t tmp_loopid;
3712 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 3713 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3714
3715 retry = 0;
3716 tmp_loopid = 0;
3717
3718 for (;;) {
7c3df132
SK		 3719 ql_dbg(ql_dbg_disc, vha, 0x2000,
3720 "Trying Fabric Login w/loop id 0x%04x for port "
3721 "%02x%02x%02x.\n",
3722 fcport->loop_id, fcport->d_id.b.domain,
3723 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 3724
3725 /* Login fcport on switch. */
0b91d116 3726 rval = ha->isp_ops->fabric_login(vha, fcport->loop_id,
1da177e4
LT		 3727 fcport->d_id.b.domain, fcport->d_id.b.area,
3728 fcport->d_id.b.al_pa, mb, BIT_0);
0b91d116
CD		 3729 if (rval != QLA_SUCCESS) {
3730 return rval;
3731 }
1da177e4
LT		 3732 if (mb[0] == MBS_PORT_ID_USED) {
3733 /*
3734 * Device has another loop ID. The firmware team
0107109e
AV		 3735 * recommends the driver perform an implicit login with
3736 * the specified ID again. The ID we just used is save
3737 * here so we return with an ID that can be tried by
3738 * the next login.
1da177e4
LT		 3739 */
3740 retry++;
3741 tmp_loopid = fcport->loop_id;
3742 fcport->loop_id = mb[1];
3743
7c3df132
SK		 3744 ql_dbg(ql_dbg_disc, vha, 0x2001,
3745 "Fabric Login: port in use - next loop "
3746 "id=0x%04x, port id= %02x%02x%02x.\n",
1da177e4 3747 fcport->loop_id, fcport->d_id.b.domain,
7c3df132 3748 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 3749
3750 } else if (mb[0] == MBS_COMMAND_COMPLETE) {
3751 /*
3752 * Login succeeded.
3753 */
3754 if (retry) {
3755 /* A retry occurred before. */
3756 *next_loopid = tmp_loopid;
3757 } else {
3758 /*
3759 * No retry occurred before. Just increment the
3760 * ID value for next login.
3761 */
3762 *next_loopid = (fcport->loop_id + 1);
3763 }
3764
3765 if (mb[1] & BIT_0) {
3766 fcport->port_type = FCT_INITIATOR;
3767 } else {
3768 fcport->port_type = FCT_TARGET;
3769 if (mb[1] & BIT_1) {
8474f3a0 3770 fcport->flags |= FCF_FCP2_DEVICE;
1da177e4
LT		 3771 }
3772 }
3773
ad3e0eda
AV		 3774 if (mb[10] & BIT_0)
3775 fcport->supported_classes |= FC_COS_CLASS2;
3776 if (mb[10] & BIT_1)
3777 fcport->supported_classes |= FC_COS_CLASS3;
3778
2d70c103
NB		 3779 if (IS_FWI2_CAPABLE(ha)) {
3780 if (mb[10] & BIT_7)
3781 fcport->flags |=
3782 FCF_CONF_COMP_SUPPORTED;
3783 }
3784
1da177e4
LT		 3785 rval = QLA_SUCCESS;
3786 break;
3787 } else if (mb[0] == MBS_LOOP_ID_USED) {
3788 /*
3789 * Loop ID already used, try next loop ID.
3790 */
3791 fcport->loop_id++;
e315cd28 3792 rval = qla2x00_find_new_loop_id(vha, fcport);
1da177e4
LT		 3793 if (rval != QLA_SUCCESS) {
3794 /* Ran out of loop IDs to use */
3795 break;
3796 }
3797 } else if (mb[0] == MBS_COMMAND_ERROR) {
3798 /*
3799 * Firmware possibly timed out during login. If NO
3800 * retries are left to do then the device is declared
3801 * dead.
3802 */
3803 *next_loopid = fcport->loop_id;
e315cd28 3804 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3805 fcport->d_id.b.domain, fcport->d_id.b.area,
3806 fcport->d_id.b.al_pa);
e315cd28 3807 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 3808
3809 rval = 1;
3810 break;
3811 } else {
3812 /*
3813 * unrecoverable / not handled error
3814 */
7c3df132
SK		 3815 ql_dbg(ql_dbg_disc, vha, 0x2002,
3816 "Failed=%x port_id=%02x%02x%02x loop_id=%x "
3817 "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain,
3818 fcport->d_id.b.area, fcport->d_id.b.al_pa,
3819 fcport->loop_id, jiffies);
1da177e4
LT		 3820
3821 *next_loopid = fcport->loop_id;
e315cd28 3822 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3823 fcport->d_id.b.domain, fcport->d_id.b.area,
3824 fcport->d_id.b.al_pa);
5f16b331 3825 qla2x00_clear_loop_id(fcport);
0eedfcf0 3826 fcport->login_retry = 0;
1da177e4
LT		 3827
3828 rval = 3;
3829 break;
3830 }
3831 }
3832
3833 return (rval);
3834}
3835
3836/*
3837 * qla2x00_local_device_login
3838 * Issue local device login command.
3839 *
3840 * Input:
3841 * ha = adapter block pointer.
3842 * loop_id = loop id of device to login to.
3843 *
3844 * Returns (Where's the #define!!!!):
3845 * 0 - Login successfully
3846 * 1 - Login failed
3847 * 3 - Fatal error
3848 */
3849int
e315cd28 3850qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport)
1da177e4
LT		 3851{
3852 int rval;
3853 uint16_t mb[MAILBOX_REGISTER_COUNT];
3854
3855 memset(mb, 0, sizeof(mb));
e315cd28 3856 rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0);
1da177e4
LT		 3857 if (rval == QLA_SUCCESS) {
3858 /* Interrogate mailbox registers for any errors */
3859 if (mb[0] == MBS_COMMAND_ERROR)
3860 rval = 1;
3861 else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR)
3862 /* device not in PCB table */
3863 rval = 3;
3864 }
3865
3866 return (rval);
3867}
3868
3869/*
3870 * qla2x00_loop_resync
3871 * Resync with fibre channel devices.
3872 *
3873 * Input:
3874 * ha = adapter block pointer.
3875 *
3876 * Returns:
3877 * 0 = success
3878 */
3879int
e315cd28 3880qla2x00_loop_resync(scsi_qla_host_t *vha)
1da177e4 3881{
73208dfd 3882 int rval = QLA_SUCCESS;
1da177e4 3883 uint32_t wait_time;
67c2e93a
AC		 3884 struct req_que *req;
3885 struct rsp_que *rsp;
3886
7163ea81 3887 if (vha->hw->flags.cpu_affinity_enabled)
67c2e93a
AC		 3888 req = vha->hw->req_q_map[0];
3889 else
3890 req = vha->req;
3891 rsp = req->rsp;
1da177e4 3892
e315cd28
AC		 3893 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
3894 if (vha->flags.online) {
3895 if (!(rval = qla2x00_fw_ready(vha))) {
1da177e4
LT		 3896 /* Wait at most MAX_TARGET RSCNs for a stable link. */
3897 wait_time = 256;
3898 do {
0107109e 3899 /* Issue a marker after FW becomes ready. */
73208dfd
AC		 3900 qla2x00_marker(vha, req, rsp, 0, 0,
3901 MK_SYNC_ALL);
e315cd28 3902 vha->marker_needed = 0;
1da177e4
LT		 3903
3904 /* Remap devices on Loop. */
e315cd28 3905 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4 3906
e315cd28 3907 qla2x00_configure_loop(vha);
1da177e4 3908 wait_time--;
e315cd28
AC		 3909 } while (!atomic_read(&vha->loop_down_timer) &&
3910 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
3911 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
3912 &vha->dpc_flags)));
1da177e4 3913 }
1da177e4
LT		 3914 }
3915
e315cd28 3916 if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
1da177e4 3917 return (QLA_FUNCTION_FAILED);
1da177e4 3918
e315cd28 3919 if (rval)
7c3df132
SK		 3920 ql_dbg(ql_dbg_disc, vha, 0x206c,
3921 "%s *** FAILED ***.\n", __func__);
1da177e4
LT		 3922
3923 return (rval);
3924}
3925
579d12b5
SK		 3926/*
3927* qla2x00_perform_loop_resync
3928* Description: This function will set the appropriate flags and call
3929* qla2x00_loop_resync. If successful loop will be resynced
3930* Arguments : scsi_qla_host_t pointer
3931* returm : Success or Failure
3932*/
3933
3934int qla2x00_perform_loop_resync(scsi_qla_host_t *ha)
3935{
3936 int32_t rval = 0;
3937
3938 if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) {
3939 /*Configure the flags so that resync happens properly*/
3940 atomic_set(&ha->loop_down_timer, 0);
3941 if (!(ha->device_flags & DFLG_NO_CABLE)) {
3942 atomic_set(&ha->loop_state, LOOP_UP);
3943 set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags);
3944 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
3945 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
3946
3947 rval = qla2x00_loop_resync(ha);
3948 } else
3949 atomic_set(&ha->loop_state, LOOP_DEAD);
3950
3951 clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags);
3952 }
3953
3954 return rval;
3955}
3956
d97994dc 3957void
67becc00 3958qla2x00_update_fcports(scsi_qla_host_t *base_vha)
d97994dc
AV		 3959{
3960 fc_port_t *fcport;
feafb7b1
AE		 3961 struct scsi_qla_host *vha;
3962 struct qla_hw_data *ha = base_vha->hw;
3963 unsigned long flags;
d97994dc 3964
feafb7b1 3965 spin_lock_irqsave(&ha->vport_slock, flags);
d97994dc 3966 /* Go with deferred removal of rport references. */
feafb7b1
AE		 3967 list_for_each_entry(vha, &base_vha->hw->vp_list, list) {
3968 atomic_inc(&vha->vref_count);
3969 list_for_each_entry(fcport, &vha->vp_fcports, list) {
8ae598d0 3970 if (fcport->drport &&
feafb7b1
AE		 3971 atomic_read(&fcport->state) != FCS_UNCONFIGURED) {
3972 spin_unlock_irqrestore(&ha->vport_slock, flags);
3973
67becc00 3974 qla2x00_rport_del(fcport);
feafb7b1
AE		 3975
3976 spin_lock_irqsave(&ha->vport_slock, flags);
3977 }
3978 }
3979 atomic_dec(&vha->vref_count);
3980 }
3981 spin_unlock_irqrestore(&ha->vport_slock, flags);
d97994dc
AV		 3982}
3983
7d613ac6
SV		 3984/* Assumes idc_lock always held on entry */
3985void
3986qla83xx_reset_ownership(scsi_qla_host_t *vha)
3987{
3988 struct qla_hw_data *ha = vha->hw;
3989 uint32_t drv_presence, drv_presence_mask;
3990 uint32_t dev_part_info1, dev_part_info2, class_type;
3991 uint32_t class_type_mask = 0x3;
3992 uint16_t fcoe_other_function = 0xffff, i;
3993
3994 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
3995
3996 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1);
3997 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2);
3998 for (i = 0; i < 8; i++) {
3999 class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask);
4000 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
4001 (i != ha->portnum)) {
4002 fcoe_other_function = i;
4003 break;
4004 }
4005 }
4006 if (fcoe_other_function == 0xffff) {
4007 for (i = 0; i < 8; i++) {
4008 class_type = ((dev_part_info2 >> (i * 4)) &
4009 class_type_mask);
4010 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
4011 ((i + 8) != ha->portnum)) {
4012 fcoe_other_function = i + 8;
4013 break;
4014 }
4015 }
4016 }
4017 /*
4018 * Prepare drv-presence mask based on fcoe functions present.
4019 * However consider only valid physical fcoe function numbers (0-15).
4020 */
4021 drv_presence_mask = ~((1 << (ha->portnum)) |
4022 ((fcoe_other_function == 0xffff) ?
4023 0 : (1 << (fcoe_other_function))));
4024
4025 /* We are the reset owner iff:
4026 * - No other protocol drivers present.
4027 * - This is the lowest among fcoe functions. */
4028 if (!(drv_presence & drv_presence_mask) &&
4029 (ha->portnum < fcoe_other_function)) {
4030 ql_dbg(ql_dbg_p3p, vha, 0xb07f,
4031 "This host is Reset owner.\n");
4032 ha->flags.nic_core_reset_owner = 1;
4033 }
4034}
4035
fa492630 4036static int
7d613ac6
SV		 4037__qla83xx_set_drv_ack(scsi_qla_host_t *vha)
4038{
4039 int rval = QLA_SUCCESS;
4040 struct qla_hw_data *ha = vha->hw;
4041 uint32_t drv_ack;
4042
4043 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4044 if (rval == QLA_SUCCESS) {
4045 drv_ack |= (1 << ha->portnum);
4046 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
4047 }
4048
4049 return rval;
4050}
4051
fa492630 4052static int
7d613ac6
SV		 4053__qla83xx_clear_drv_ack(scsi_qla_host_t *vha)
4054{
4055 int rval = QLA_SUCCESS;
4056 struct qla_hw_data *ha = vha->hw;
4057 uint32_t drv_ack;
4058
4059 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4060 if (rval == QLA_SUCCESS) {
4061 drv_ack &= ~(1 << ha->portnum);
4062 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
4063 }
4064
4065 return rval;
4066}
4067
fa492630 4068static const char *
7d613ac6
SV		 4069qla83xx_dev_state_to_string(uint32_t dev_state)
4070{
4071 switch (dev_state) {
4072 case QLA8XXX_DEV_COLD:
4073 return "COLD/RE-INIT";
4074 case QLA8XXX_DEV_INITIALIZING:
4075 return "INITIALIZING";
4076 case QLA8XXX_DEV_READY:
4077 return "READY";
4078 case QLA8XXX_DEV_NEED_RESET:
4079 return "NEED RESET";
4080 case QLA8XXX_DEV_NEED_QUIESCENT:
4081 return "NEED QUIESCENT";
4082 case QLA8XXX_DEV_FAILED:
4083 return "FAILED";
4084 case QLA8XXX_DEV_QUIESCENT:
4085 return "QUIESCENT";
4086 default:
4087 return "Unknown";
4088 }
4089}
4090
4091/* Assumes idc-lock always held on entry */
4092void
4093qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type)
4094{
4095 struct qla_hw_data *ha = vha->hw;
4096 uint32_t idc_audit_reg = 0, duration_secs = 0;
4097
4098 switch (audit_type) {
4099 case IDC_AUDIT_TIMESTAMP:
4100 ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000);
4101 idc_audit_reg = (ha->portnum) |
4102 (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8);
4103 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
4104 break;
4105
4106 case IDC_AUDIT_COMPLETION:
4107 duration_secs = ((jiffies_to_msecs(jiffies) -
4108 jiffies_to_msecs(ha->idc_audit_ts)) / 1000);
4109 idc_audit_reg = (ha->portnum) |
4110 (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8);
4111 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
4112 break;
4113
4114 default:
4115 ql_log(ql_log_warn, vha, 0xb078,
4116 "Invalid audit type specified.\n");
4117 break;
4118 }
4119}
4120
4121/* Assumes idc_lock always held on entry */
fa492630 4122static int
7d613ac6
SV		 4123qla83xx_initiating_reset(scsi_qla_host_t *vha)
4124{
4125 struct qla_hw_data *ha = vha->hw;
4126 uint32_t idc_control, dev_state;
4127
4128 __qla83xx_get_idc_control(vha, &idc_control);
4129 if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) {
4130 ql_log(ql_log_info, vha, 0xb080,
4131 "NIC Core reset has been disabled. idc-control=0x%x\n",
4132 idc_control);
4133 return QLA_FUNCTION_FAILED;
4134 }
4135
4136 /* Set NEED-RESET iff in READY state and we are the reset-owner */
4137 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4138 if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) {
4139 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
4140 QLA8XXX_DEV_NEED_RESET);
4141 ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n");
4142 qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP);
4143 } else {
4144 const char *state = qla83xx_dev_state_to_string(dev_state);
4145 ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n", state);
4146
4147 /* SV: XXX: Is timeout required here? */
4148 /* Wait for IDC state change READY -> NEED_RESET */
4149 while (dev_state == QLA8XXX_DEV_READY) {
4150 qla83xx_idc_unlock(vha, 0);
4151 msleep(200);
4152 qla83xx_idc_lock(vha, 0);
4153 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4154 }
4155 }
4156
4157 /* Send IDC ack by writing to drv-ack register */
4158 __qla83xx_set_drv_ack(vha);
4159
4160 return QLA_SUCCESS;
4161}
4162
4163int
4164__qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control)
4165{
4166 return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
4167}
4168
7d613ac6
SV		 4169int
4170__qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control)
4171{
4172 return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
4173}
4174
fa492630 4175static int
7d613ac6
SV		 4176qla83xx_check_driver_presence(scsi_qla_host_t *vha)
4177{
4178 uint32_t drv_presence = 0;
4179 struct qla_hw_data *ha = vha->hw;
4180
4181 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4182 if (drv_presence & (1 << ha->portnum))
4183 return QLA_SUCCESS;
4184 else
4185 return QLA_TEST_FAILED;
4186}
4187
4188int
4189qla83xx_nic_core_reset(scsi_qla_host_t *vha)
4190{
4191 int rval = QLA_SUCCESS;
4192 struct qla_hw_data *ha = vha->hw;
4193
4194 ql_dbg(ql_dbg_p3p, vha, 0xb058,
4195 "Entered %s().\n", __func__);
4196
4197 if (vha->device_flags & DFLG_DEV_FAILED) {
4198 ql_log(ql_log_warn, vha, 0xb059,
4199 "Device in unrecoverable FAILED state.\n");
4200 return QLA_FUNCTION_FAILED;
4201 }
4202
4203 qla83xx_idc_lock(vha, 0);
4204
4205 if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) {
4206 ql_log(ql_log_warn, vha, 0xb05a,
4207 "Function=0x%x has been removed from IDC participation.\n",
4208 ha->portnum);
4209 rval = QLA_FUNCTION_FAILED;
4210 goto exit;
4211 }
4212
4213 qla83xx_reset_ownership(vha);
4214
4215 rval = qla83xx_initiating_reset(vha);
4216
4217 /*
4218 * Perform reset if we are the reset-owner,
4219 * else wait till IDC state changes to READY/FAILED.
4220 */
4221 if (rval == QLA_SUCCESS) {
4222 rval = qla83xx_idc_state_handler(vha);
4223
4224 if (rval == QLA_SUCCESS)
4225 ha->flags.nic_core_hung = 0;
4226 __qla83xx_clear_drv_ack(vha);
4227 }
4228
4229exit:
4230 qla83xx_idc_unlock(vha, 0);
4231
4232 ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__);
4233
4234 return rval;
4235}
4236
81178772
SK		 4237int
4238qla2xxx_mctp_dump(scsi_qla_host_t *vha)
4239{
4240 struct qla_hw_data *ha = vha->hw;
4241 int rval = QLA_FUNCTION_FAILED;
4242
4243 if (!IS_MCTP_CAPABLE(ha)) {
4244 /* This message can be removed from the final version */
4245 ql_log(ql_log_info, vha, 0x506d,
4246 "This board is not MCTP capable\n");
4247 return rval;
4248 }
4249
4250 if (!ha->mctp_dump) {
4251 ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev,
4252 MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL);
4253
4254 if (!ha->mctp_dump) {
4255 ql_log(ql_log_warn, vha, 0x506e,
4256 "Failed to allocate memory for mctp dump\n");
4257 return rval;
4258 }
4259 }
4260
4261#define MCTP_DUMP_STR_ADDR 0x00000000
4262 rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma,
4263 MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4);
4264 if (rval != QLA_SUCCESS) {
4265 ql_log(ql_log_warn, vha, 0x506f,
4266 "Failed to capture mctp dump\n");
4267 } else {
4268 ql_log(ql_log_info, vha, 0x5070,
4269 "Mctp dump capture for host (%ld/%p).\n",
4270 vha->host_no, ha->mctp_dump);
4271 ha->mctp_dumped = 1;
4272 }
4273
409ee0fe 4274 if (!ha->flags.nic_core_reset_hdlr_active && !ha->portnum) {
81178772
SK		 4275 ha->flags.nic_core_reset_hdlr_active = 1;
4276 rval = qla83xx_restart_nic_firmware(vha);
4277 if (rval)
4278 /* NIC Core reset failed. */
4279 ql_log(ql_log_warn, vha, 0x5071,
4280 "Failed to restart nic firmware\n");
4281 else
4282 ql_dbg(ql_dbg_p3p, vha, 0xb084,
4283 "Restarted NIC firmware successfully.\n");
4284 ha->flags.nic_core_reset_hdlr_active = 0;
4285 }
4286
4287 return rval;
4288
4289}
4290
579d12b5 4291/*
8fcd6b8b 4292* qla2x00_quiesce_io
579d12b5
SK		 4293* Description: This function will block the new I/Os
4294* Its not aborting any I/Os as context
4295* is not destroyed during quiescence
4296* Arguments: scsi_qla_host_t
4297* return : void
4298*/
4299void
8fcd6b8b 4300qla2x00_quiesce_io(scsi_qla_host_t *vha)
579d12b5
SK		 4301{
4302 struct qla_hw_data *ha = vha->hw;
4303 struct scsi_qla_host *vp;
4304
8fcd6b8b
CD		 4305 ql_dbg(ql_dbg_dpc, vha, 0x401d,
4306 "Quiescing I/O - ha=%p.\n", ha);
579d12b5
SK		 4307
4308 atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME);
4309 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
4310 atomic_set(&vha->loop_state, LOOP_DOWN);
4311 qla2x00_mark_all_devices_lost(vha, 0);
4312 list_for_each_entry(vp, &ha->vp_list, list)
8fcd6b8b 4313 qla2x00_mark_all_devices_lost(vp, 0);
579d12b5
SK		 4314 } else {
4315 if (!atomic_read(&vha->loop_down_timer))
4316 atomic_set(&vha->loop_down_timer,
4317 LOOP_DOWN_TIME);
4318 }
4319 /* Wait for pending cmds to complete */
4320 qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST);
4321}
4322
a9083016
GM		 4323void
4324qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
4325{
4326 struct qla_hw_data *ha = vha->hw;
579d12b5 4327 struct scsi_qla_host *vp;
feafb7b1 4328 unsigned long flags;
6aef87be 4329 fc_port_t *fcport;
a9083016 4330
e46ef004
SK		 4331 /* For ISP82XX, driver waits for completion of the commands.
4332 * online flag should be set.
4333 */
4334 if (!IS_QLA82XX(ha))
4335 vha->flags.online = 0;
a9083016
GM		 4336 ha->flags.chip_reset_done = 0;
4337 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2be21fa2 4338 vha->qla_stats.total_isp_aborts++;
a9083016 4339
7c3df132
SK		 4340 ql_log(ql_log_info, vha, 0x00af,
4341 "Performing ISP error recovery - ha=%p.\n", ha);
a9083016 4342
e46ef004
SK		 4343 /* For ISP82XX, reset_chip is just disabling interrupts.
4344 * Driver waits for the completion of the commands.
4345 * the interrupts need to be enabled.
4346 */
a9083016
GM		 4347 if (!IS_QLA82XX(ha))
4348 ha->isp_ops->reset_chip(vha);
4349
4350 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
4351 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
4352 atomic_set(&vha->loop_state, LOOP_DOWN);
4353 qla2x00_mark_all_devices_lost(vha, 0);
feafb7b1
AE		 4354
4355 spin_lock_irqsave(&ha->vport_slock, flags);
579d12b5 4356 list_for_each_entry(vp, &ha->vp_list, list) {
feafb7b1
AE		 4357 atomic_inc(&vp->vref_count);
4358 spin_unlock_irqrestore(&ha->vport_slock, flags);
4359
a9083016 4360 qla2x00_mark_all_devices_lost(vp, 0);
feafb7b1
AE		 4361
4362 spin_lock_irqsave(&ha->vport_slock, flags);
4363 atomic_dec(&vp->vref_count);
4364 }
4365 spin_unlock_irqrestore(&ha->vport_slock, flags);
a9083016
GM		 4366 } else {
4367 if (!atomic_read(&vha->loop_down_timer))
4368 atomic_set(&vha->loop_down_timer,
4369 LOOP_DOWN_TIME);
4370 }
4371
6aef87be
AV		 4372 /* Clear all async request states across all VPs. */
4373 list_for_each_entry(fcport, &vha->vp_fcports, list)
4374 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
4375 spin_lock_irqsave(&ha->vport_slock, flags);
4376 list_for_each_entry(vp, &ha->vp_list, list) {
4377 atomic_inc(&vp->vref_count);
4378 spin_unlock_irqrestore(&ha->vport_slock, flags);
4379
4380 list_for_each_entry(fcport, &vp->vp_fcports, list)
4381 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
4382
4383 spin_lock_irqsave(&ha->vport_slock, flags);
4384 atomic_dec(&vp->vref_count);
4385 }
4386 spin_unlock_irqrestore(&ha->vport_slock, flags);
4387
bddd2d65
LC		 4388 if (!ha->flags.eeh_busy) {
4389 /* Make sure for ISP 82XX IO DMA is complete */
4390 if (IS_QLA82XX(ha)) {
7190575f 4391 qla82xx_chip_reset_cleanup(vha);
7c3df132
SK		 4392 ql_log(ql_log_info, vha, 0x00b4,
4393 "Done chip reset cleanup.\n");
a9083016 4394
e46ef004
SK		 4395 /* Done waiting for pending commands.
4396 * Reset the online flag.
4397 */
4398 vha->flags.online = 0;
4d78c973 4399 }
a9083016 4400
bddd2d65
LC		 4401 /* Requeue all commands in outstanding command list. */
4402 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
4403 }
a9083016
GM		 4404}
4405
1da177e4
LT		 4406/*
4407* qla2x00_abort_isp
4408* Resets ISP and aborts all outstanding commands.
4409*
4410* Input:
4411* ha = adapter block pointer.
4412*
4413* Returns:
4414* 0 = success
4415*/
4416int
e315cd28 4417qla2x00_abort_isp(scsi_qla_host_t *vha)
1da177e4 4418{
476e8978 4419 int rval;
1da177e4 4420 uint8_t status = 0;
e315cd28
AC		 4421 struct qla_hw_data *ha = vha->hw;
4422 struct scsi_qla_host *vp;
73208dfd 4423 struct req_que *req = ha->req_q_map[0];
feafb7b1 4424 unsigned long flags;
1da177e4 4425
e315cd28 4426 if (vha->flags.online) {
a9083016 4427 qla2x00_abort_isp_cleanup(vha);
1da177e4 4428
a6171297
SV		 4429 if (IS_QLA8031(ha)) {
4430 ql_dbg(ql_dbg_p3p, vha, 0xb05c,
4431 "Clearing fcoe driver presence.\n");
4432 if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS)
4433 ql_dbg(ql_dbg_p3p, vha, 0xb073,
4434 "Error while clearing DRV-Presence.\n");
4435 }
4436
85880801
AV		 4437 if (unlikely(pci_channel_offline(ha->pdev) &&
4438 ha->flags.pci_channel_io_perm_failure)) {
4439 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
4440 status = 0;
4441 return status;
4442 }
4443
73208dfd 4444 ha->isp_ops->get_flash_version(vha, req->ring);
30c47662 4445
e315cd28 4446 ha->isp_ops->nvram_config(vha);
1da177e4 4447
e315cd28
AC		 4448 if (!qla2x00_restart_isp(vha)) {
4449 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4 4450
e315cd28 4451 if (!atomic_read(&vha->loop_down_timer)) {
1da177e4
LT		 4452 /*
4453 * Issue marker command only when we are going
4454 * to start the I/O .
4455 */
e315cd28 4456 vha->marker_needed = 1;
1da177e4
LT		 4457 }
4458
e315cd28 4459 vha->flags.online = 1;
1da177e4 4460
fd34f556 4461 ha->isp_ops->enable_intrs(ha);
1da177e4 4462
fa2a1ce5 4463 ha->isp_abort_cnt = 0;
e315cd28 4464 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
476e8978 4465
6246b8a1
GM		 4466 if (IS_QLA81XX(ha) || IS_QLA8031(ha))
4467 qla2x00_get_fw_version(vha);
df613b96
AV		 4468 if (ha->fce) {
4469 ha->flags.fce_enabled = 1;
4470 memset(ha->fce, 0,
4471 fce_calc_size(ha->fce_bufs));
e315cd28 4472 rval = qla2x00_enable_fce_trace(vha,
df613b96
AV		 4473 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
4474 &ha->fce_bufs);
4475 if (rval) {
7c3df132 4476 ql_log(ql_log_warn, vha, 0x8033,
df613b96
AV		 4477 "Unable to reinitialize FCE "
4478 "(%d).\n", rval);
4479 ha->flags.fce_enabled = 0;
4480 }
4481 }
436a7b11
AV		 4482
4483 if (ha->eft) {
4484 memset(ha->eft, 0, EFT_SIZE);
e315cd28 4485 rval = qla2x00_enable_eft_trace(vha,
436a7b11
AV		 4486 ha->eft_dma, EFT_NUM_BUFFERS);
4487 if (rval) {
7c3df132 4488 ql_log(ql_log_warn, vha, 0x8034,
436a7b11
AV		 4489 "Unable to reinitialize EFT "
4490 "(%d).\n", rval);
4491 }
4492 }
1da177e4 4493 } else { /* failed the ISP abort */
e315cd28
AC		 4494 vha->flags.online = 1;
4495 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
1da177e4 4496 if (ha->isp_abort_cnt == 0) {
7c3df132
SK		 4497 ql_log(ql_log_fatal, vha, 0x8035,
4498 "ISP error recover failed - "
4499 "board disabled.\n");
fa2a1ce5 4500 /*
1da177e4
LT		 4501 * The next call disables the board
4502 * completely.
4503 */
e315cd28
AC		 4504 ha->isp_ops->reset_adapter(vha);
4505 vha->flags.online = 0;
1da177e4 4506 clear_bit(ISP_ABORT_RETRY,
e315cd28 4507 &vha->dpc_flags);
1da177e4
LT		 4508 status = 0;
4509 } else { /* schedule another ISP abort */
4510 ha->isp_abort_cnt--;
7c3df132
SK		 4511 ql_dbg(ql_dbg_taskm, vha, 0x8020,
4512 "ISP abort - retry remaining %d.\n",
4513 ha->isp_abort_cnt);
1da177e4
LT		 4514 status = 1;
4515 }
4516 } else {
4517 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
7c3df132
SK		 4518 ql_dbg(ql_dbg_taskm, vha, 0x8021,
4519 "ISP error recovery - retrying (%d) "
4520 "more times.\n", ha->isp_abort_cnt);
e315cd28 4521 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
1da177e4
LT		 4522 status = 1;
4523 }
4524 }
fa2a1ce5 4525
1da177e4
LT		 4526 }
4527
e315cd28 4528 if (!status) {
7c3df132 4529 ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__);
feafb7b1
AE		 4530
4531 spin_lock_irqsave(&ha->vport_slock, flags);
4532 list_for_each_entry(vp, &ha->vp_list, list) {
4533 if (vp->vp_idx) {
4534 atomic_inc(&vp->vref_count);
4535 spin_unlock_irqrestore(&ha->vport_slock, flags);
4536
e315cd28 4537 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 4538
4539 spin_lock_irqsave(&ha->vport_slock, flags);
4540 atomic_dec(&vp->vref_count);
4541 }
e315cd28 4542 }
feafb7b1
AE		 4543 spin_unlock_irqrestore(&ha->vport_slock, flags);
4544
7d613ac6
SV		 4545 if (IS_QLA8031(ha)) {
4546 ql_dbg(ql_dbg_p3p, vha, 0xb05d,
4547 "Setting back fcoe driver presence.\n");
4548 if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS)
4549 ql_dbg(ql_dbg_p3p, vha, 0xb074,
4550 "Error while setting DRV-Presence.\n");
4551 }
e315cd28 4552 } else {
d8424f68
JP		 4553 ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n",
4554 __func__);
1da177e4
LT		 4555 }
4556
4557 return(status);
4558}
4559
4560/*
4561* qla2x00_restart_isp
4562* restarts the ISP after a reset
4563*
4564* Input:
4565* ha = adapter block pointer.
4566*
4567* Returns:
4568* 0 = success
4569*/
4570static int
e315cd28 4571qla2x00_restart_isp(scsi_qla_host_t *vha)
1da177e4 4572{
c6b2fca8 4573 int status = 0;
1da177e4 4574 uint32_t wait_time;
e315cd28 4575 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 4576 struct req_que *req = ha->req_q_map[0];
4577 struct rsp_que *rsp = ha->rsp_q_map[0];
2d70c103 4578 unsigned long flags;
1da177e4
LT		 4579
4580 /* If firmware needs to be loaded */
e315cd28
AC		 4581 if (qla2x00_isp_firmware(vha)) {
4582 vha->flags.online = 0;
4583 status = ha->isp_ops->chip_diag(vha);
4584 if (!status)
4585 status = qla2x00_setup_chip(vha);
1da177e4
LT		 4586 }
4587
e315cd28
AC		 4588 if (!status && !(status = qla2x00_init_rings(vha))) {
4589 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
2533cf67 4590 ha->flags.chip_reset_done = 1;
73208dfd
AC		 4591 /* Initialize the queues in use */
4592 qla25xx_init_queues(ha);
4593
e315cd28
AC		 4594 status = qla2x00_fw_ready(vha);
4595 if (!status) {
7c3df132
SK		 4596 ql_dbg(ql_dbg_taskm, vha, 0x8031,
4597 "Start configure loop status = %d.\n", status);
0107109e
AV		 4598
4599 /* Issue a marker after FW becomes ready. */
73208dfd 4600 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
0107109e 4601
e315cd28 4602 vha->flags.online = 1;
2d70c103
NB		 4603
4604 /*
4605 * Process any ATIO queue entries that came in
4606 * while we weren't online.
4607 */
4608 spin_lock_irqsave(&ha->hardware_lock, flags);
4609 if (qla_tgt_mode_enabled(vha))
4610 qlt_24xx_process_atio_queue(vha);
4611 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4612
1da177e4
LT		 4613 /* Wait at most MAX_TARGET RSCNs for a stable link. */
4614 wait_time = 256;
4615 do {
e315cd28
AC		 4616 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
4617 qla2x00_configure_loop(vha);
1da177e4 4618 wait_time--;
e315cd28
AC		 4619 } while (!atomic_read(&vha->loop_down_timer) &&
4620 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
4621 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
4622 &vha->dpc_flags)));
1da177e4
LT		 4623 }
4624
4625 /* if no cable then assume it's good */
e315cd28 4626 if ((vha->device_flags & DFLG_NO_CABLE))
1da177e4
LT		 4627 status = 0;
4628
7c3df132
SK		 4629 ql_dbg(ql_dbg_taskm, vha, 0x8032,
4630 "Configure loop done, status = 0x%x.\n", status);
1da177e4
LT		 4631 }
4632 return (status);
4633}
4634
73208dfd
AC		 4635static int
4636qla25xx_init_queues(struct qla_hw_data *ha)
4637{
4638 struct rsp_que *rsp = NULL;
4639 struct req_que *req = NULL;
4640 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
4641 int ret = -1;
4642 int i;
4643
2afa19a9 4644 for (i = 1; i < ha->max_rsp_queues; i++) {
73208dfd
AC		 4645 rsp = ha->rsp_q_map[i];
4646 if (rsp) {
4647 rsp->options &= ~BIT_0;
618a7523 4648 ret = qla25xx_init_rsp_que(base_vha, rsp);
73208dfd 4649 if (ret != QLA_SUCCESS)
7c3df132
SK		 4650 ql_dbg(ql_dbg_init, base_vha, 0x00ff,
4651 "%s Rsp que: %d init failed.\n",
4652 __func__, rsp->id);
73208dfd 4653 else
7c3df132
SK		 4654 ql_dbg(ql_dbg_init, base_vha, 0x0100,
4655 "%s Rsp que: %d inited.\n",
4656 __func__, rsp->id);
73208dfd 4657 }
2afa19a9
AC		 4658 }
4659 for (i = 1; i < ha->max_req_queues; i++) {
73208dfd
AC		 4660 req = ha->req_q_map[i];
4661 if (req) {
29bdccbe 4662 /* Clear outstanding commands array. */
73208dfd 4663 req->options &= ~BIT_0;
618a7523 4664 ret = qla25xx_init_req_que(base_vha, req);
73208dfd 4665 if (ret != QLA_SUCCESS)
7c3df132
SK		 4666 ql_dbg(ql_dbg_init, base_vha, 0x0101,
4667 "%s Req que: %d init failed.\n",
4668 __func__, req->id);
73208dfd 4669 else
7c3df132
SK		 4670 ql_dbg(ql_dbg_init, base_vha, 0x0102,
4671 "%s Req que: %d inited.\n",
4672 __func__, req->id);
73208dfd
AC		 4673 }
4674 }
4675 return ret;
4676}
4677
1da177e4
LT		 4678/*
4679* qla2x00_reset_adapter
4680* Reset adapter.
4681*
4682* Input:
4683* ha = adapter block pointer.
4684*/
abbd8870 4685void
e315cd28 4686qla2x00_reset_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 4687{
4688 unsigned long flags = 0;
e315cd28 4689 struct qla_hw_data *ha = vha->hw;
3d71644c 4690 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 4691
e315cd28 4692 vha->flags.online = 0;
fd34f556 4693 ha->isp_ops->disable_intrs(ha);
1da177e4 4694
1da177e4
LT		 4695 spin_lock_irqsave(&ha->hardware_lock, flags);
4696 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
4697 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
4698 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
4699 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
4700 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4701}
0107109e
AV		 4702
4703void
e315cd28 4704qla24xx_reset_adapter(scsi_qla_host_t *vha)
0107109e
AV		 4705{
4706 unsigned long flags = 0;
e315cd28 4707 struct qla_hw_data *ha = vha->hw;
0107109e
AV		 4708 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
4709
a9083016
GM		 4710 if (IS_QLA82XX(ha))
4711 return;
4712
e315cd28 4713 vha->flags.online = 0;
fd34f556 4714 ha->isp_ops->disable_intrs(ha);
0107109e
AV		 4715
4716 spin_lock_irqsave(&ha->hardware_lock, flags);
4717 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
4718 RD_REG_DWORD(&reg->hccr);
4719 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
4720 RD_REG_DWORD(&reg->hccr);
4721 spin_unlock_irqrestore(&ha->hardware_lock, flags);
09ff36d3
AV		 4722
4723 if (IS_NOPOLLING_TYPE(ha))
4724 ha->isp_ops->enable_intrs(ha);
0107109e
AV		 4725}
4726
4e08df3f
DM		 4727/* On sparc systems, obtain port and node WWN from firmware
4728 * properties.
4729 */
e315cd28
AC		 4730static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha,
4731 struct nvram_24xx *nv)
4e08df3f
DM		 4732{
4733#ifdef CONFIG_SPARC
e315cd28 4734 struct qla_hw_data *ha = vha->hw;
4e08df3f 4735 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 4736 struct device_node *dp = pci_device_to_OF_node(pdev);
4737 const u8 *val;
4e08df3f
DM		 4738 int len;
4739
4740 val = of_get_property(dp, "port-wwn", &len);
4741 if (val && len >= WWN_SIZE)
4742 memcpy(nv->port_name, val, WWN_SIZE);
4743
4744 val = of_get_property(dp, "node-wwn", &len);
4745 if (val && len >= WWN_SIZE)
4746 memcpy(nv->node_name, val, WWN_SIZE);
4747#endif
4748}
4749
0107109e 4750int
e315cd28 4751qla24xx_nvram_config(scsi_qla_host_t *vha)
0107109e 4752{
4e08df3f 4753 int rval;
0107109e
AV		 4754 struct init_cb_24xx *icb;
4755 struct nvram_24xx *nv;
4756 uint32_t *dptr;
4757 uint8_t *dptr1, *dptr2;
4758 uint32_t chksum;
4759 uint16_t cnt;
e315cd28 4760 struct qla_hw_data *ha = vha->hw;
0107109e 4761
4e08df3f 4762 rval = QLA_SUCCESS;
0107109e 4763 icb = (struct init_cb_24xx *)ha->init_cb;
281afe19 4764 nv = ha->nvram;
0107109e
AV		 4765
4766 /* Determine NVRAM starting address. */
e5b68a61
AC		 4767 if (ha->flags.port0) {
4768 ha->nvram_base = FA_NVRAM_FUNC0_ADDR;
4769 ha->vpd_base = FA_NVRAM_VPD0_ADDR;
4770 } else {
0107109e 4771 ha->nvram_base = FA_NVRAM_FUNC1_ADDR;
6f641790
AV		 4772 ha->vpd_base = FA_NVRAM_VPD1_ADDR;
4773 }
e5b68a61
AC		 4774 ha->nvram_size = sizeof(struct nvram_24xx);
4775 ha->vpd_size = FA_NVRAM_VPD_SIZE;
a9083016
GM		 4776 if (IS_QLA82XX(ha))
4777 ha->vpd_size = FA_VPD_SIZE_82XX;
0107109e 4778
281afe19
SJ		 4779 /* Get VPD data into cache */
4780 ha->vpd = ha->nvram + VPD_OFFSET;
e315cd28 4781 ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd,
281afe19
SJ		 4782 ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
4783
4784 /* Get NVRAM data into cache and calculate checksum. */
0107109e 4785 dptr = (uint32_t *)nv;
e315cd28 4786 ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base,
0107109e
AV		 4787 ha->nvram_size);
4788 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
4789 chksum += le32_to_cpu(*dptr++);
4790
7c3df132
SK		 4791 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
4792 "Contents of NVRAM\n");
4793 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
4794 (uint8_t *)nv, ha->nvram_size);
0107109e
AV		 4795
4796 /* Bad NVRAM data, set defaults parameters. */
4797 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
4798 || nv->id[3] != ' ' ||
4799 nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
4800 /* Reset NVRAM data. */
7c3df132 4801 ql_log(ql_log_warn, vha, 0x006b,
9e336520 4802 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132
SK		 4803 "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version);
4804 ql_log(ql_log_warn, vha, 0x006c,
4805 "Falling back to functioning (yet invalid -- WWPN) "
4806 "defaults.\n");
4e08df3f
DM		 4807
4808 /*
4809 * Set default initialization control block.
4810 */
4811 memset(nv, 0, ha->nvram_size);
4812 nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
4813 nv->version = __constant_cpu_to_le16(ICB_VERSION);
4814 nv->frame_payload_size = __constant_cpu_to_le16(2048);
4815 nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
4816 nv->exchange_count = __constant_cpu_to_le16(0);
4817 nv->hard_address = __constant_cpu_to_le16(124);
4818 nv->port_name[0] = 0x21;
e5b68a61 4819 nv->port_name[1] = 0x00 + ha->port_no;
4e08df3f
DM		 4820 nv->port_name[2] = 0x00;
4821 nv->port_name[3] = 0xe0;
4822 nv->port_name[4] = 0x8b;
4823 nv->port_name[5] = 0x1c;
4824 nv->port_name[6] = 0x55;
4825 nv->port_name[7] = 0x86;
4826 nv->node_name[0] = 0x20;
4827 nv->node_name[1] = 0x00;
4828 nv->node_name[2] = 0x00;
4829 nv->node_name[3] = 0xe0;
4830 nv->node_name[4] = 0x8b;
4831 nv->node_name[5] = 0x1c;
4832 nv->node_name[6] = 0x55;
4833 nv->node_name[7] = 0x86;
e315cd28 4834 qla24xx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 4835 nv->login_retry_count = __constant_cpu_to_le16(8);
4836 nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
4837 nv->login_timeout = __constant_cpu_to_le16(0);
4838 nv->firmware_options_1 =
4839 __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
4840 nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
4841 nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
4842 nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
4843 nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
4844 nv->efi_parameters = __constant_cpu_to_le32(0);
4845 nv->reset_delay = 5;
4846 nv->max_luns_per_target = __constant_cpu_to_le16(128);
4847 nv->port_down_retry_count = __constant_cpu_to_le16(30);
4848 nv->link_down_timeout = __constant_cpu_to_le16(30);
4849
4850 rval = 1;
0107109e
AV		 4851 }
4852
2d70c103
NB		 4853 if (!qla_ini_mode_enabled(vha)) {
4854 /* Don't enable full login after initial LIP */
4855 nv->firmware_options_1 &= __constant_cpu_to_le32(~BIT_13);
4856 /* Don't enable LIP full login for initiator */
4857 nv->host_p &= __constant_cpu_to_le32(~BIT_10);
4858 }
4859
4860 qlt_24xx_config_nvram_stage1(vha, nv);
4861
0107109e 4862 /* Reset Initialization control block */
e315cd28 4863 memset(icb, 0, ha->init_cb_size);
0107109e
AV		 4864
4865 /* Copy 1st segment. */
4866 dptr1 = (uint8_t *)icb;
4867 dptr2 = (uint8_t *)&nv->version;
4868 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
4869 while (cnt--)
4870 *dptr1++ = *dptr2++;
4871
4872 icb->login_retry_count = nv->login_retry_count;
3ea66e28 4873 icb->link_down_on_nos = nv->link_down_on_nos;
0107109e
AV		 4874
4875 /* Copy 2nd segment. */
4876 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
4877 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
4878 cnt = (uint8_t *)&icb->reserved_3 -
4879 (uint8_t *)&icb->interrupt_delay_timer;
4880 while (cnt--)
4881 *dptr1++ = *dptr2++;
4882
4883 /*
4884 * Setup driver NVRAM options.
4885 */
e315cd28 4886 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
9bb9fcf2 4887 "QLA2462");
0107109e 4888
2d70c103
NB		 4889 qlt_24xx_config_nvram_stage2(vha, icb);
4890
5341e868 4891 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
2d70c103 4892 /* Use alternate WWN? */
5341e868
AV		 4893 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
4894 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
4895 }
4896
0107109e 4897 /* Prepare nodename */
fd0e7e4d 4898 if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
0107109e
AV		 4899 /*
4900 * Firmware will apply the following mask if the nodename was
4901 * not provided.
4902 */
4903 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
4904 icb->node_name[0] &= 0xF0;
4905 }
4906
4907 /* Set host adapter parameters. */
4908 ha->flags.disable_risc_code_load = 0;
0c8c39af
AV		 4909 ha->flags.enable_lip_reset = 0;
4910 ha->flags.enable_lip_full_login =
4911 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
4912 ha->flags.enable_target_reset =
4913 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
0107109e 4914 ha->flags.enable_led_scheme = 0;
d4c760c2 4915 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
0107109e 4916
fd0e7e4d
AV		 4917 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
4918 (BIT_6 | BIT_5 | BIT_4)) >> 4;
0107109e
AV		 4919
4920 memcpy(ha->fw_seriallink_options24, nv->seriallink_options,
4921 sizeof(ha->fw_seriallink_options24));
4922
4923 /* save HBA serial number */
4924 ha->serial0 = icb->port_name[5];
4925 ha->serial1 = icb->port_name[6];
4926 ha->serial2 = icb->port_name[7];
e315cd28
AC		 4927 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
4928 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
0107109e 4929
bc8fb3cb
AV		 4930 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
4931
0107109e
AV		 4932 ha->retry_count = le16_to_cpu(nv->login_retry_count);
4933
4934 /* Set minimum login_timeout to 4 seconds. */
4935 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
4936 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
4937 if (le16_to_cpu(nv->login_timeout) < 4)
4938 nv->login_timeout = __constant_cpu_to_le16(4);
4939 ha->login_timeout = le16_to_cpu(nv->login_timeout);
c6852c4c 4940 icb->login_timeout = nv->login_timeout;
0107109e 4941
00a537b8
AV		 4942 /* Set minimum RATOV to 100 tenths of a second. */
4943 ha->r_a_tov = 100;
0107109e
AV		 4944
4945 ha->loop_reset_delay = nv->reset_delay;
4946
4947 /* Link Down Timeout = 0:
4948 *
4949 * When Port Down timer expires we will start returning
4950 * I/O's to OS with "DID_NO_CONNECT".
4951 *
4952 * Link Down Timeout != 0:
4953 *
4954 * The driver waits for the link to come up after link down
4955 * before returning I/Os to OS with "DID_NO_CONNECT".
4956 */
4957 if (le16_to_cpu(nv->link_down_timeout) == 0) {
4958 ha->loop_down_abort_time =
4959 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
4960 } else {
4961 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
4962 ha->loop_down_abort_time =
4963 (LOOP_DOWN_TIME - ha->link_down_timeout);
4964 }
4965
4966 /* Need enough time to try and get the port back. */
4967 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
4968 if (qlport_down_retry)
4969 ha->port_down_retry_count = qlport_down_retry;
4970
4971 /* Set login_retry_count */
4972 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
4973 if (ha->port_down_retry_count ==
4974 le16_to_cpu(nv->port_down_retry_count) &&
4975 ha->port_down_retry_count > 3)
4976 ha->login_retry_count = ha->port_down_retry_count;
4977 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
4978 ha->login_retry_count = ha->port_down_retry_count;
4979 if (ql2xloginretrycount)
4980 ha->login_retry_count = ql2xloginretrycount;
4981
4fdfefe5 4982 /* Enable ZIO. */
e315cd28 4983 if (!vha->flags.init_done) {
4fdfefe5
AV		 4984 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
4985 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
4986 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
4987 le16_to_cpu(icb->interrupt_delay_timer): 2;
4988 }
4989 icb->firmware_options_2 &= __constant_cpu_to_le32(
4990 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
e315cd28 4991 vha->flags.process_response_queue = 0;
4fdfefe5 4992 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d
AV		 4993 ha->zio_mode = QLA_ZIO_MODE_6;
4994
7c3df132 4995 ql_log(ql_log_info, vha, 0x006f,
4fdfefe5
AV		 4996 "ZIO mode %d enabled; timer delay (%d us).\n",
4997 ha->zio_mode, ha->zio_timer * 100);
4998
4999 icb->firmware_options_2 |= cpu_to_le32(
5000 (uint32_t)ha->zio_mode);
5001 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
e315cd28 5002 vha->flags.process_response_queue = 1;
4fdfefe5
AV		 5003 }
5004
4e08df3f 5005 if (rval) {
7c3df132
SK		 5006 ql_log(ql_log_warn, vha, 0x0070,
5007 "NVRAM configuration failed.\n");
4e08df3f
DM		 5008 }
5009 return (rval);
0107109e
AV		 5010}
5011
413975a0 5012static int
cbc8eb67
AV		 5013qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
5014 uint32_t faddr)
d1c61909 5015{
73208dfd 5016 int rval = QLA_SUCCESS;
d1c61909 5017 int segments, fragment;
d1c61909
AV		 5018 uint32_t *dcode, dlen;
5019 uint32_t risc_addr;
5020 uint32_t risc_size;
5021 uint32_t i;
e315cd28 5022 struct qla_hw_data *ha = vha->hw;
73208dfd 5023 struct req_que *req = ha->req_q_map[0];
eaac30be 5024
7c3df132 5025 ql_dbg(ql_dbg_init, vha, 0x008b,
cfb0919c 5026 "FW: Loading firmware from flash (%x).\n", faddr);
eaac30be 5027
d1c61909
AV		 5028 rval = QLA_SUCCESS;
5029
5030 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 5031 dcode = (uint32_t *)req->ring;
d1c61909
AV		 5032 *srisc_addr = 0;
5033
5034 /* Validate firmware image by checking version. */
e315cd28 5035 qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
d1c61909
AV		 5036 for (i = 0; i < 4; i++)
5037 dcode[i] = be32_to_cpu(dcode[i]);
5038 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
5039 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
5040 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
5041 dcode[3] == 0)) {
7c3df132
SK		 5042 ql_log(ql_log_fatal, vha, 0x008c,
5043 "Unable to verify the integrity of flash firmware "
5044 "image.\n");
5045 ql_log(ql_log_fatal, vha, 0x008d,
5046 "Firmware data: %08x %08x %08x %08x.\n",
5047 dcode[0], dcode[1], dcode[2], dcode[3]);
d1c61909
AV		 5048
5049 return QLA_FUNCTION_FAILED;
5050 }
5051
5052 while (segments && rval == QLA_SUCCESS) {
5053 /* Read segment's load information. */
e315cd28 5054 qla24xx_read_flash_data(vha, dcode, faddr, 4);
d1c61909
AV		 5055
5056 risc_addr = be32_to_cpu(dcode[2]);
5057 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
5058 risc_size = be32_to_cpu(dcode[3]);
5059
5060 fragment = 0;
5061 while (risc_size > 0 && rval == QLA_SUCCESS) {
5062 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
5063 if (dlen > risc_size)
5064 dlen = risc_size;
5065
7c3df132
SK		 5066 ql_dbg(ql_dbg_init, vha, 0x008e,
5067 "Loading risc segment@ risc addr %x "
5068 "number of dwords 0x%x offset 0x%x.\n",
5069 risc_addr, dlen, faddr);
d1c61909 5070
e315cd28 5071 qla24xx_read_flash_data(vha, dcode, faddr, dlen);
d1c61909
AV		 5072 for (i = 0; i < dlen; i++)
5073 dcode[i] = swab32(dcode[i]);
5074
73208dfd 5075 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
d1c61909
AV		 5076 dlen);
5077 if (rval) {
7c3df132
SK		 5078 ql_log(ql_log_fatal, vha, 0x008f,
5079 "Failed to load segment %d of firmware.\n",
5080 fragment);
d1c61909
AV		 5081 break;
5082 }
5083
5084 faddr += dlen;
5085 risc_addr += dlen;
5086 risc_size -= dlen;
5087 fragment++;
5088 }
5089
5090 /* Next segment. */
5091 segments--;
5092 }
5093
5094 return rval;
5095}
5096
e9454a88 5097#define QLA_FW_URL "http://ldriver.qlogic.com/firmware/"
d1c61909 5098
0107109e 5099int
e315cd28 5100qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5433383e
AV		 5101{
5102 int rval;
5103 int i, fragment;
5104 uint16_t *wcode, *fwcode;
5105 uint32_t risc_addr, risc_size, fwclen, wlen, *seg;
5106 struct fw_blob *blob;
e315cd28 5107 struct qla_hw_data *ha = vha->hw;
73208dfd 5108 struct req_que *req = ha->req_q_map[0];
5433383e
AV		 5109
5110 /* Load firmware blob. */
e315cd28 5111 blob = qla2x00_request_firmware(vha);
5433383e 5112 if (!blob) {
7c3df132
SK		 5113 ql_log(ql_log_info, vha, 0x0083,
5114 "Fimware image unavailable.\n");
5115 ql_log(ql_log_info, vha, 0x0084,
5116 "Firmware images can be retrieved from: "QLA_FW_URL ".\n");
5433383e
AV		 5117 return QLA_FUNCTION_FAILED;
5118 }
5119
5120 rval = QLA_SUCCESS;
5121
73208dfd 5122 wcode = (uint16_t *)req->ring;
5433383e
AV		 5123 *srisc_addr = 0;
5124 fwcode = (uint16_t *)blob->fw->data;
5125 fwclen = 0;
5126
5127 /* Validate firmware image by checking version. */
5128 if (blob->fw->size < 8 * sizeof(uint16_t)) {
7c3df132
SK		 5129 ql_log(ql_log_fatal, vha, 0x0085,
5130 "Unable to verify integrity of firmware image (%Zd).\n",
5433383e
AV		 5131 blob->fw->size);
5132 goto fail_fw_integrity;
5133 }
5134 for (i = 0; i < 4; i++)
5135 wcode[i] = be16_to_cpu(fwcode[i + 4]);
5136 if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff &&
5137 wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 &&
5138 wcode[2] == 0 && wcode[3] == 0)) {
7c3df132
SK		 5139 ql_log(ql_log_fatal, vha, 0x0086,
5140 "Unable to verify integrity of firmware image.\n");
5141 ql_log(ql_log_fatal, vha, 0x0087,
5142 "Firmware data: %04x %04x %04x %04x.\n",
5143 wcode[0], wcode[1], wcode[2], wcode[3]);
5433383e
AV		 5144 goto fail_fw_integrity;
5145 }
5146
5147 seg = blob->segs;
5148 while (*seg && rval == QLA_SUCCESS) {
5149 risc_addr = *seg;
5150 *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr;
5151 risc_size = be16_to_cpu(fwcode[3]);
5152
5153 /* Validate firmware image size. */
5154 fwclen += risc_size * sizeof(uint16_t);
5155 if (blob->fw->size < fwclen) {
7c3df132 5156 ql_log(ql_log_fatal, vha, 0x0088,
5433383e 5157 "Unable to verify integrity of firmware image "
7c3df132 5158 "(%Zd).\n", blob->fw->size);
5433383e
AV		 5159 goto fail_fw_integrity;
5160 }
5161
5162 fragment = 0;
5163 while (risc_size > 0 && rval == QLA_SUCCESS) {
5164 wlen = (uint16_t)(ha->fw_transfer_size >> 1);
5165 if (wlen > risc_size)
5166 wlen = risc_size;
7c3df132
SK		 5167 ql_dbg(ql_dbg_init, vha, 0x0089,
5168 "Loading risc segment@ risc addr %x number of "
5169 "words 0x%x.\n", risc_addr, wlen);
5433383e
AV		 5170
5171 for (i = 0; i < wlen; i++)
5172 wcode[i] = swab16(fwcode[i]);
5173
73208dfd 5174 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
5433383e
AV		 5175 wlen);
5176 if (rval) {
7c3df132
SK		 5177 ql_log(ql_log_fatal, vha, 0x008a,
5178 "Failed to load segment %d of firmware.\n",
5179 fragment);
5433383e
AV		 5180 break;
5181 }
5182
5183 fwcode += wlen;
5184 risc_addr += wlen;
5185 risc_size -= wlen;
5186 fragment++;
5187 }
5188
5189 /* Next segment. */
5190 seg++;
5191 }
5192 return rval;
5193
5194fail_fw_integrity:
5195 return QLA_FUNCTION_FAILED;
5196}
5197
eaac30be
AV		 5198static int
5199qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
0107109e
AV		 5200{
5201 int rval;
5202 int segments, fragment;
5203 uint32_t *dcode, dlen;
5204 uint32_t risc_addr;
5205 uint32_t risc_size;
5206 uint32_t i;
5433383e 5207 struct fw_blob *blob;
0107109e 5208 uint32_t *fwcode, fwclen;
e315cd28 5209 struct qla_hw_data *ha = vha->hw;
73208dfd 5210 struct req_que *req = ha->req_q_map[0];
0107109e 5211
5433383e 5212 /* Load firmware blob. */
e315cd28 5213 blob = qla2x00_request_firmware(vha);
5433383e 5214 if (!blob) {
7c3df132
SK		 5215 ql_log(ql_log_warn, vha, 0x0090,
5216 "Fimware image unavailable.\n");
5217 ql_log(ql_log_warn, vha, 0x0091,
5218 "Firmware images can be retrieved from: "
5219 QLA_FW_URL ".\n");
d1c61909 5220
eaac30be 5221 return QLA_FUNCTION_FAILED;
0107109e
AV		 5222 }
5223
cfb0919c
CD		 5224 ql_dbg(ql_dbg_init, vha, 0x0092,
5225 "FW: Loading via request-firmware.\n");
eaac30be 5226
0107109e
AV		 5227 rval = QLA_SUCCESS;
5228
5229 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 5230 dcode = (uint32_t *)req->ring;
0107109e 5231 *srisc_addr = 0;
5433383e 5232 fwcode = (uint32_t *)blob->fw->data;
0107109e
AV		 5233 fwclen = 0;
5234
5235 /* Validate firmware image by checking version. */
5433383e 5236 if (blob->fw->size < 8 * sizeof(uint32_t)) {
7c3df132
SK		 5237 ql_log(ql_log_fatal, vha, 0x0093,
5238 "Unable to verify integrity of firmware image (%Zd).\n",
5433383e 5239 blob->fw->size);
0107109e
AV		 5240 goto fail_fw_integrity;
5241 }
5242 for (i = 0; i < 4; i++)
5243 dcode[i] = be32_to_cpu(fwcode[i + 4]);
5244 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
5245 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
5246 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
5247 dcode[3] == 0)) {
7c3df132
SK		 5248 ql_log(ql_log_fatal, vha, 0x0094,
5249 "Unable to verify integrity of firmware image (%Zd).\n",
5250 blob->fw->size);
5251 ql_log(ql_log_fatal, vha, 0x0095,
5252 "Firmware data: %08x %08x %08x %08x.\n",
5253 dcode[0], dcode[1], dcode[2], dcode[3]);
0107109e
AV		 5254 goto fail_fw_integrity;
5255 }
5256
5257 while (segments && rval == QLA_SUCCESS) {
5258 risc_addr = be32_to_cpu(fwcode[2]);
5259 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
5260 risc_size = be32_to_cpu(fwcode[3]);
5261
5262 /* Validate firmware image size. */
5263 fwclen += risc_size * sizeof(uint32_t);
5433383e 5264 if (blob->fw->size < fwclen) {
7c3df132 5265 ql_log(ql_log_fatal, vha, 0x0096,
5433383e 5266 "Unable to verify integrity of firmware image "
7c3df132 5267 "(%Zd).\n", blob->fw->size);
5433383e 5268
0107109e
AV		 5269 goto fail_fw_integrity;
5270 }
5271
5272 fragment = 0;
5273 while (risc_size > 0 && rval == QLA_SUCCESS) {
5274 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
5275 if (dlen > risc_size)
5276 dlen = risc_size;
5277
7c3df132
SK		 5278 ql_dbg(ql_dbg_init, vha, 0x0097,
5279 "Loading risc segment@ risc addr %x "
5280 "number of dwords 0x%x.\n", risc_addr, dlen);
0107109e
AV		 5281
5282 for (i = 0; i < dlen; i++)
5283 dcode[i] = swab32(fwcode[i]);
5284
73208dfd 5285 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
590f98e5 5286 dlen);
0107109e 5287 if (rval) {
7c3df132
SK		 5288 ql_log(ql_log_fatal, vha, 0x0098,
5289 "Failed to load segment %d of firmware.\n",
5290 fragment);
0107109e
AV		 5291 break;
5292 }
5293
5294 fwcode += dlen;
5295 risc_addr += dlen;
5296 risc_size -= dlen;
5297 fragment++;
5298 }
5299
5300 /* Next segment. */
5301 segments--;
5302 }
0107109e
AV		 5303 return rval;
5304
5305fail_fw_integrity:
0107109e 5306 return QLA_FUNCTION_FAILED;
0107109e 5307}
18c6c127 5308
eaac30be
AV		 5309int
5310qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5311{
5312 int rval;
5313
e337d907
AV		 5314 if (ql2xfwloadbin == 1)
5315 return qla81xx_load_risc(vha, srisc_addr);
5316
eaac30be
AV		 5317 /*
5318 * FW Load priority:
5319 * 1) Firmware via request-firmware interface (.bin file).
5320 * 2) Firmware residing in flash.
5321 */
5322 rval = qla24xx_load_risc_blob(vha, srisc_addr);
5323 if (rval == QLA_SUCCESS)
5324 return rval;
5325
cbc8eb67
AV		 5326 return qla24xx_load_risc_flash(vha, srisc_addr,
5327 vha->hw->flt_region_fw);
eaac30be
AV		 5328}
5329
5330int
5331qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5332{
5333 int rval;
cbc8eb67 5334 struct qla_hw_data *ha = vha->hw;
eaac30be 5335
e337d907 5336 if (ql2xfwloadbin == 2)
cbc8eb67 5337 goto try_blob_fw;
e337d907 5338
eaac30be
AV		 5339 /*
5340 * FW Load priority:
5341 * 1) Firmware residing in flash.
5342 * 2) Firmware via request-firmware interface (.bin file).
cbc8eb67 5343 * 3) Golden-Firmware residing in flash -- limited operation.
eaac30be 5344 */
cbc8eb67 5345 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
eaac30be
AV		 5346 if (rval == QLA_SUCCESS)
5347 return rval;
5348
cbc8eb67
AV		 5349try_blob_fw:
5350 rval = qla24xx_load_risc_blob(vha, srisc_addr);
5351 if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw)
5352 return rval;
5353
7c3df132
SK		 5354 ql_log(ql_log_info, vha, 0x0099,
5355 "Attempting to fallback to golden firmware.\n");
cbc8eb67
AV		 5356 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
5357 if (rval != QLA_SUCCESS)
5358 return rval;
5359
7c3df132 5360 ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n");
cbc8eb67 5361 ha->flags.running_gold_fw = 1;
cbc8eb67 5362 return rval;
eaac30be
AV		 5363}
5364
18c6c127 5365void
e315cd28 5366qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha)
18c6c127
AV		 5367{
5368 int ret, retries;
e315cd28 5369 struct qla_hw_data *ha = vha->hw;
18c6c127 5370
85880801
AV		 5371 if (ha->flags.pci_channel_io_perm_failure)
5372 return;
e428924c 5373 if (!IS_FWI2_CAPABLE(ha))
18c6c127 5374 return;
75edf81d
AV		 5375 if (!ha->fw_major_version)
5376 return;
18c6c127 5377
e315cd28 5378 ret = qla2x00_stop_firmware(vha);
7c7f1f29 5379 for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&
b469a7cb 5380 ret != QLA_INVALID_COMMAND && retries ; retries--) {
e315cd28
AC		 5381 ha->isp_ops->reset_chip(vha);
5382 if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS)
18c6c127 5383 continue;
e315cd28 5384 if (qla2x00_setup_chip(vha) != QLA_SUCCESS)
18c6c127 5385 continue;
7c3df132
SK		 5386 ql_log(ql_log_info, vha, 0x8015,
5387 "Attempting retry of stop-firmware command.\n");
e315cd28 5388 ret = qla2x00_stop_firmware(vha);
18c6c127
AV		 5389 }
5390}
2c3dfe3f
SJ		 5391
5392int
e315cd28 5393qla24xx_configure_vhba(scsi_qla_host_t *vha)
2c3dfe3f
SJ		 5394{
5395 int rval = QLA_SUCCESS;
0b91d116 5396 int rval2;
2c3dfe3f 5397 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28
AC		 5398 struct qla_hw_data *ha = vha->hw;
5399 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
67c2e93a
AC		 5400 struct req_que *req;
5401 struct rsp_que *rsp;
2c3dfe3f 5402
e315cd28 5403 if (!vha->vp_idx)
2c3dfe3f
SJ		 5404 return -EINVAL;
5405
e315cd28 5406 rval = qla2x00_fw_ready(base_vha);
7163ea81 5407 if (ha->flags.cpu_affinity_enabled)
67c2e93a
AC		 5408 req = ha->req_q_map[0];
5409 else
5410 req = vha->req;
5411 rsp = req->rsp;
5412
2c3dfe3f 5413 if (rval == QLA_SUCCESS) {
e315cd28 5414 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
73208dfd 5415 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
2c3dfe3f
SJ		 5416 }
5417
e315cd28 5418 vha->flags.management_server_logged_in = 0;
2c3dfe3f
SJ		 5419
5420 /* Login to SNS first */
0b91d116
CD		 5421 rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb,
5422 BIT_1);
5423 if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
5424 if (rval2 == QLA_MEMORY_ALLOC_FAILED)
5425 ql_dbg(ql_dbg_init, vha, 0x0120,
5426 "Failed SNS login: loop_id=%x, rval2=%d\n",
5427 NPH_SNS, rval2);
5428 else
5429 ql_dbg(ql_dbg_init, vha, 0x0103,
5430 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x "
5431 "mb[2]=%x mb[6]=%x mb[7]=%x.\n",
5432 NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]);
2c3dfe3f
SJ		 5433 return (QLA_FUNCTION_FAILED);
5434 }
5435
e315cd28
AC		 5436 atomic_set(&vha->loop_down_timer, 0);
5437 atomic_set(&vha->loop_state, LOOP_UP);
5438 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5439 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
5440 rval = qla2x00_loop_resync(base_vha);
2c3dfe3f
SJ		 5441
5442 return rval;
5443}
4d4df193
HK		 5444
5445/* 84XX Support **************************************************************/
5446
5447static LIST_HEAD(qla_cs84xx_list);
5448static DEFINE_MUTEX(qla_cs84xx_mutex);
5449
5450static struct qla_chip_state_84xx *
e315cd28 5451qla84xx_get_chip(struct scsi_qla_host *vha)
4d4df193
HK		 5452{
5453 struct qla_chip_state_84xx *cs84xx;
e315cd28 5454 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5455
5456 mutex_lock(&qla_cs84xx_mutex);
5457
5458 /* Find any shared 84xx chip. */
5459 list_for_each_entry(cs84xx, &qla_cs84xx_list, list) {
5460 if (cs84xx->bus == ha->pdev->bus) {
5461 kref_get(&cs84xx->kref);
5462 goto done;
5463 }
5464 }
5465
5466 cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL);
5467 if (!cs84xx)
5468 goto done;
5469
5470 kref_init(&cs84xx->kref);
5471 spin_lock_init(&cs84xx->access_lock);
5472 mutex_init(&cs84xx->fw_update_mutex);
5473 cs84xx->bus = ha->pdev->bus;
5474
5475 list_add_tail(&cs84xx->list, &qla_cs84xx_list);
5476done:
5477 mutex_unlock(&qla_cs84xx_mutex);
5478 return cs84xx;
5479}
5480
5481static void
5482__qla84xx_chip_release(struct kref *kref)
5483{
5484 struct qla_chip_state_84xx *cs84xx =
5485 container_of(kref, struct qla_chip_state_84xx, kref);
5486
5487 mutex_lock(&qla_cs84xx_mutex);
5488 list_del(&cs84xx->list);
5489 mutex_unlock(&qla_cs84xx_mutex);
5490 kfree(cs84xx);
5491}
5492
5493void
e315cd28 5494qla84xx_put_chip(struct scsi_qla_host *vha)
4d4df193 5495{
e315cd28 5496 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5497 if (ha->cs84xx)
5498 kref_put(&ha->cs84xx->kref, __qla84xx_chip_release);
5499}
5500
5501static int
e315cd28 5502qla84xx_init_chip(scsi_qla_host_t *vha)
4d4df193
HK		 5503{
5504 int rval;
5505 uint16_t status[2];
e315cd28 5506 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5507
5508 mutex_lock(&ha->cs84xx->fw_update_mutex);
5509
e315cd28 5510 rval = qla84xx_verify_chip(vha, status);
4d4df193
HK		 5511
5512 mutex_unlock(&ha->cs84xx->fw_update_mutex);
5513
5514 return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED:
5515 QLA_SUCCESS;
5516}
3a03eb79
AV		 5517
5518/* 81XX Support **************************************************************/
5519
5520int
5521qla81xx_nvram_config(scsi_qla_host_t *vha)
5522{
5523 int rval;
5524 struct init_cb_81xx *icb;
5525 struct nvram_81xx *nv;
5526 uint32_t *dptr;
5527 uint8_t *dptr1, *dptr2;
5528 uint32_t chksum;
5529 uint16_t cnt;
5530 struct qla_hw_data *ha = vha->hw;
5531
5532 rval = QLA_SUCCESS;
5533 icb = (struct init_cb_81xx *)ha->init_cb;
5534 nv = ha->nvram;
5535
5536 /* Determine NVRAM starting address. */
5537 ha->nvram_size = sizeof(struct nvram_81xx);
3a03eb79 5538 ha->vpd_size = FA_NVRAM_VPD_SIZE;
3a03eb79
AV		 5539
5540 /* Get VPD data into cache */
5541 ha->vpd = ha->nvram + VPD_OFFSET;
3d79038f
AV		 5542 ha->isp_ops->read_optrom(vha, ha->vpd, ha->flt_region_vpd << 2,
5543 ha->vpd_size);
3a03eb79
AV		 5544
5545 /* Get NVRAM data into cache and calculate checksum. */
3d79038f 5546 ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2,
3a03eb79 5547 ha->nvram_size);
3d79038f 5548 dptr = (uint32_t *)nv;
3a03eb79
AV		 5549 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
5550 chksum += le32_to_cpu(*dptr++);
5551
7c3df132
SK		 5552 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
5553 "Contents of NVRAM:\n");
5554 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
5555 (uint8_t *)nv, ha->nvram_size);
3a03eb79
AV		 5556
5557 /* Bad NVRAM data, set defaults parameters. */
5558 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
5559 || nv->id[3] != ' ' ||
5560 nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
5561 /* Reset NVRAM data. */
7c3df132 5562 ql_log(ql_log_info, vha, 0x0073,
9e336520 5563 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132 5564 "version=0x%x.\n", chksum, nv->id[0],
3a03eb79 5565 le16_to_cpu(nv->nvram_version));
7c3df132
SK		 5566 ql_log(ql_log_info, vha, 0x0074,
5567 "Falling back to functioning (yet invalid -- WWPN) "
5568 "defaults.\n");
3a03eb79
AV		 5569
5570 /*
5571 * Set default initialization control block.
5572 */
5573 memset(nv, 0, ha->nvram_size);
5574 nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
5575 nv->version = __constant_cpu_to_le16(ICB_VERSION);
5576 nv->frame_payload_size = __constant_cpu_to_le16(2048);
5577 nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
5578 nv->exchange_count = __constant_cpu_to_le16(0);
5579 nv->port_name[0] = 0x21;
e5b68a61 5580 nv->port_name[1] = 0x00 + ha->port_no;
3a03eb79
AV		 5581 nv->port_name[2] = 0x00;
5582 nv->port_name[3] = 0xe0;
5583 nv->port_name[4] = 0x8b;
5584 nv->port_name[5] = 0x1c;
5585 nv->port_name[6] = 0x55;
5586 nv->port_name[7] = 0x86;
5587 nv->node_name[0] = 0x20;
5588 nv->node_name[1] = 0x00;
5589 nv->node_name[2] = 0x00;
5590 nv->node_name[3] = 0xe0;
5591 nv->node_name[4] = 0x8b;
5592 nv->node_name[5] = 0x1c;
5593 nv->node_name[6] = 0x55;
5594 nv->node_name[7] = 0x86;
5595 nv->login_retry_count = __constant_cpu_to_le16(8);
5596 nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
5597 nv->login_timeout = __constant_cpu_to_le16(0);
5598 nv->firmware_options_1 =
5599 __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
5600 nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
5601 nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
5602 nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
5603 nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
5604 nv->efi_parameters = __constant_cpu_to_le32(0);
5605 nv->reset_delay = 5;
5606 nv->max_luns_per_target = __constant_cpu_to_le16(128);
5607 nv->port_down_retry_count = __constant_cpu_to_le16(30);
6246b8a1 5608 nv->link_down_timeout = __constant_cpu_to_le16(180);
eeebcc92 5609 nv->enode_mac[0] = 0x00;
6246b8a1
GM		 5610 nv->enode_mac[1] = 0xC0;
5611 nv->enode_mac[2] = 0xDD;
3a03eb79
AV		 5612 nv->enode_mac[3] = 0x04;
5613 nv->enode_mac[4] = 0x05;
e5b68a61 5614 nv->enode_mac[5] = 0x06 + ha->port_no;
3a03eb79
AV		 5615
5616 rval = 1;
5617 }
5618
9e522cd8
AE		 5619 if (IS_T10_PI_CAPABLE(ha))
5620 nv->frame_payload_size &= ~7;
5621
aa230bc5
AE		 5622 qlt_81xx_config_nvram_stage1(vha, nv);
5623
3a03eb79 5624 /* Reset Initialization control block */
773120e4 5625 memset(icb, 0, ha->init_cb_size);
3a03eb79
AV		 5626
5627 /* Copy 1st segment. */
5628 dptr1 = (uint8_t *)icb;
5629 dptr2 = (uint8_t *)&nv->version;
5630 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
5631 while (cnt--)
5632 *dptr1++ = *dptr2++;
5633
5634 icb->login_retry_count = nv->login_retry_count;
5635
5636 /* Copy 2nd segment. */
5637 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
5638 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
5639 cnt = (uint8_t *)&icb->reserved_5 -
5640 (uint8_t *)&icb->interrupt_delay_timer;
5641 while (cnt--)
5642 *dptr1++ = *dptr2++;
5643
5644 memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac));
5645 /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */
5646 if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) {
69e5f1ea
AV		 5647 icb->enode_mac[0] = 0x00;
5648 icb->enode_mac[1] = 0xC0;
5649 icb->enode_mac[2] = 0xDD;
3a03eb79
AV		 5650 icb->enode_mac[3] = 0x04;
5651 icb->enode_mac[4] = 0x05;
e5b68a61 5652 icb->enode_mac[5] = 0x06 + ha->port_no;
3a03eb79
AV		 5653 }
5654
b64b0e8f
AV		 5655 /* Use extended-initialization control block. */
5656 memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb));
5657
3a03eb79
AV		 5658 /*
5659 * Setup driver NVRAM options.
5660 */
5661 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
a9083016 5662 "QLE8XXX");
3a03eb79 5663
aa230bc5
AE		 5664 qlt_81xx_config_nvram_stage2(vha, icb);
5665
3a03eb79
AV		 5666 /* Use alternate WWN? */
5667 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
5668 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
5669 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
5670 }
5671
5672 /* Prepare nodename */
5673 if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
5674 /*
5675 * Firmware will apply the following mask if the nodename was
5676 * not provided.
5677 */
5678 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
5679 icb->node_name[0] &= 0xF0;
5680 }
5681
5682 /* Set host adapter parameters. */
5683 ha->flags.disable_risc_code_load = 0;
5684 ha->flags.enable_lip_reset = 0;
5685 ha->flags.enable_lip_full_login =
5686 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
5687 ha->flags.enable_target_reset =
5688 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
5689 ha->flags.enable_led_scheme = 0;
5690 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
5691
5692 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
5693 (BIT_6 | BIT_5 | BIT_4)) >> 4;
5694
5695 /* save HBA serial number */
5696 ha->serial0 = icb->port_name[5];
5697 ha->serial1 = icb->port_name[6];
5698 ha->serial2 = icb->port_name[7];
5699 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
5700 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
5701
5702 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
5703
5704 ha->retry_count = le16_to_cpu(nv->login_retry_count);
5705
5706 /* Set minimum login_timeout to 4 seconds. */
5707 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
5708 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
5709 if (le16_to_cpu(nv->login_timeout) < 4)
5710 nv->login_timeout = __constant_cpu_to_le16(4);
5711 ha->login_timeout = le16_to_cpu(nv->login_timeout);
5712 icb->login_timeout = nv->login_timeout;
5713
5714 /* Set minimum RATOV to 100 tenths of a second. */
5715 ha->r_a_tov = 100;
5716
5717 ha->loop_reset_delay = nv->reset_delay;
5718
5719 /* Link Down Timeout = 0:
5720 *
5721 * When Port Down timer expires we will start returning
5722 * I/O's to OS with "DID_NO_CONNECT".
5723 *
5724 * Link Down Timeout != 0:
5725 *
5726 * The driver waits for the link to come up after link down
5727 * before returning I/Os to OS with "DID_NO_CONNECT".
5728 */
5729 if (le16_to_cpu(nv->link_down_timeout) == 0) {
5730 ha->loop_down_abort_time =
5731 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
5732 } else {
5733 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
5734 ha->loop_down_abort_time =
5735 (LOOP_DOWN_TIME - ha->link_down_timeout);
5736 }
5737
5738 /* Need enough time to try and get the port back. */
5739 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
5740 if (qlport_down_retry)
5741 ha->port_down_retry_count = qlport_down_retry;
5742
5743 /* Set login_retry_count */
5744 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
5745 if (ha->port_down_retry_count ==
5746 le16_to_cpu(nv->port_down_retry_count) &&
5747 ha->port_down_retry_count > 3)
5748 ha->login_retry_count = ha->port_down_retry_count;
5749 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
5750 ha->login_retry_count = ha->port_down_retry_count;
5751 if (ql2xloginretrycount)
5752 ha->login_retry_count = ql2xloginretrycount;
5753
6246b8a1
GM		 5754 /* if not running MSI-X we need handshaking on interrupts */
5755 if (!vha->hw->flags.msix_enabled && IS_QLA83XX(ha))
5756 icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_22);
5757
3a03eb79
AV		 5758 /* Enable ZIO. */
5759 if (!vha->flags.init_done) {
5760 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
5761 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
5762 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
5763 le16_to_cpu(icb->interrupt_delay_timer): 2;
5764 }
5765 icb->firmware_options_2 &= __constant_cpu_to_le32(
5766 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
5767 vha->flags.process_response_queue = 0;
5768 if (ha->zio_mode != QLA_ZIO_DISABLED) {
5769 ha->zio_mode = QLA_ZIO_MODE_6;
5770
7c3df132 5771 ql_log(ql_log_info, vha, 0x0075,
3a03eb79 5772 "ZIO mode %d enabled; timer delay (%d us).\n",
7c3df132
SK		 5773 ha->zio_mode,
5774 ha->zio_timer * 100);
3a03eb79
AV		 5775
5776 icb->firmware_options_2 |= cpu_to_le32(
5777 (uint32_t)ha->zio_mode);
5778 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
5779 vha->flags.process_response_queue = 1;
5780 }
5781
5782 if (rval) {
7c3df132
SK		 5783 ql_log(ql_log_warn, vha, 0x0076,
5784 "NVRAM configuration failed.\n");
3a03eb79
AV		 5785 }
5786 return (rval);
5787}
5788
a9083016
GM		 5789int
5790qla82xx_restart_isp(scsi_qla_host_t *vha)
5791{
5792 int status, rval;
5793 uint32_t wait_time;
5794 struct qla_hw_data *ha = vha->hw;
5795 struct req_que *req = ha->req_q_map[0];
5796 struct rsp_que *rsp = ha->rsp_q_map[0];
5797 struct scsi_qla_host *vp;
feafb7b1 5798 unsigned long flags;
a9083016
GM		 5799
5800 status = qla2x00_init_rings(vha);
5801 if (!status) {
5802 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
5803 ha->flags.chip_reset_done = 1;
5804
5805 status = qla2x00_fw_ready(vha);
5806 if (!status) {
7c3df132
SK		 5807 ql_log(ql_log_info, vha, 0x803c,
5808 "Start configure loop, status =%d.\n", status);
a9083016
GM		 5809
5810 /* Issue a marker after FW becomes ready. */
5811 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
5812
5813 vha->flags.online = 1;
5814 /* Wait at most MAX_TARGET RSCNs for a stable link. */
5815 wait_time = 256;
5816 do {
5817 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5818 qla2x00_configure_loop(vha);
5819 wait_time--;
5820 } while (!atomic_read(&vha->loop_down_timer) &&
5821 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) &&
5822 wait_time &&
5823 (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)));
5824 }
5825
5826 /* if no cable then assume it's good */
5827 if ((vha->device_flags & DFLG_NO_CABLE))
5828 status = 0;
5829
cfb0919c 5830 ql_log(ql_log_info, vha, 0x8000,
7c3df132 5831 "Configure loop done, status = 0x%x.\n", status);
a9083016
GM		 5832 }
5833
5834 if (!status) {
5835 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
5836
5837 if (!atomic_read(&vha->loop_down_timer)) {
5838 /*
5839 * Issue marker command only when we are going
5840 * to start the I/O .
5841 */
5842 vha->marker_needed = 1;
5843 }
5844
5845 vha->flags.online = 1;
5846
5847 ha->isp_ops->enable_intrs(ha);
5848
5849 ha->isp_abort_cnt = 0;
5850 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
5851
53296788 5852 /* Update the firmware version */
3173167f 5853 status = qla82xx_check_md_needed(vha);
53296788 5854
a9083016
GM		 5855 if (ha->fce) {
5856 ha->flags.fce_enabled = 1;
5857 memset(ha->fce, 0,
5858 fce_calc_size(ha->fce_bufs));
5859 rval = qla2x00_enable_fce_trace(vha,
5860 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
5861 &ha->fce_bufs);
5862 if (rval) {
cfb0919c 5863 ql_log(ql_log_warn, vha, 0x8001,
7c3df132
SK		 5864 "Unable to reinitialize FCE (%d).\n",
5865 rval);
a9083016
GM		 5866 ha->flags.fce_enabled = 0;
5867 }
5868 }
5869
5870 if (ha->eft) {
5871 memset(ha->eft, 0, EFT_SIZE);
5872 rval = qla2x00_enable_eft_trace(vha,
5873 ha->eft_dma, EFT_NUM_BUFFERS);
5874 if (rval) {
cfb0919c 5875 ql_log(ql_log_warn, vha, 0x8010,
7c3df132
SK		 5876 "Unable to reinitialize EFT (%d).\n",
5877 rval);
a9083016
GM		 5878 }
5879 }
a9083016
GM		 5880 }
5881
5882 if (!status) {
cfb0919c 5883 ql_dbg(ql_dbg_taskm, vha, 0x8011,
7c3df132 5884 "qla82xx_restart_isp succeeded.\n");
feafb7b1
AE		 5885
5886 spin_lock_irqsave(&ha->vport_slock, flags);
5887 list_for_each_entry(vp, &ha->vp_list, list) {
5888 if (vp->vp_idx) {
5889 atomic_inc(&vp->vref_count);
5890 spin_unlock_irqrestore(&ha->vport_slock, flags);
5891
a9083016 5892 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 5893
5894 spin_lock_irqsave(&ha->vport_slock, flags);
5895 atomic_dec(&vp->vref_count);
5896 }
a9083016 5897 }
feafb7b1
AE		 5898 spin_unlock_irqrestore(&ha->vport_slock, flags);
5899
a9083016 5900 } else {
cfb0919c 5901 ql_log(ql_log_warn, vha, 0x8016,
7c3df132 5902 "qla82xx_restart_isp **** FAILED ****.\n");
a9083016
GM		 5903 }
5904
5905 return status;
5906}
5907
3a03eb79 5908void
ae97c91e 5909qla81xx_update_fw_options(scsi_qla_host_t *vha)
3a03eb79 5910{
ae97c91e
AV		 5911 struct qla_hw_data *ha = vha->hw;
5912
5913 if (!ql2xetsenable)
5914 return;
5915
5916 /* Enable ETS Burst. */
5917 memset(ha->fw_options, 0, sizeof(ha->fw_options));
5918 ha->fw_options[2] |= BIT_9;
5919 qla2x00_set_fw_options(vha, ha->fw_options);
3a03eb79 5920}
09ff701a
SR		 5921
5922/*
5923 * qla24xx_get_fcp_prio
5924 * Gets the fcp cmd priority value for the logged in port.
5925 * Looks for a match of the port descriptors within
5926 * each of the fcp prio config entries. If a match is found,
5927 * the tag (priority) value is returned.
5928 *
5929 * Input:
21090cbe 5930 * vha = scsi host structure pointer.
09ff701a
SR		 5931 * fcport = port structure pointer.
5932 *
5933 * Return:
6c452a45 5934 * non-zero (if found)
f28a0a96 5935 * -1 (if not found)
09ff701a
SR		 5936 *
5937 * Context:
5938 * Kernel context
5939 */
f28a0a96 5940static int
09ff701a
SR		 5941qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
5942{
5943 int i, entries;
5944 uint8_t pid_match, wwn_match;
f28a0a96 5945 int priority;
09ff701a
SR		 5946 uint32_t pid1, pid2;
5947 uint64_t wwn1, wwn2;
5948 struct qla_fcp_prio_entry *pri_entry;
5949 struct qla_hw_data *ha = vha->hw;
5950
5951 if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled)
f28a0a96 5952 return -1;
09ff701a 5953
f28a0a96 5954 priority = -1;
09ff701a
SR		 5955 entries = ha->fcp_prio_cfg->num_entries;
5956 pri_entry = &ha->fcp_prio_cfg->entry[0];
5957
5958 for (i = 0; i < entries; i++) {
5959 pid_match = wwn_match = 0;
5960
5961 if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) {
5962 pri_entry++;
5963 continue;
5964 }
5965
5966 /* check source pid for a match */
5967 if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) {
5968 pid1 = pri_entry->src_pid & INVALID_PORT_ID;
5969 pid2 = vha->d_id.b24 & INVALID_PORT_ID;
5970 if (pid1 == INVALID_PORT_ID)
5971 pid_match++;
5972 else if (pid1 == pid2)
5973 pid_match++;
5974 }
5975
5976 /* check destination pid for a match */
5977 if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) {
5978 pid1 = pri_entry->dst_pid & INVALID_PORT_ID;
5979 pid2 = fcport->d_id.b24 & INVALID_PORT_ID;
5980 if (pid1 == INVALID_PORT_ID)
5981 pid_match++;
5982 else if (pid1 == pid2)
5983 pid_match++;
5984 }
5985
5986 /* check source WWN for a match */
5987 if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) {
5988 wwn1 = wwn_to_u64(vha->port_name);
5989 wwn2 = wwn_to_u64(pri_entry->src_wwpn);
5990 if (wwn2 == (uint64_t)-1)
5991 wwn_match++;
5992 else if (wwn1 == wwn2)
5993 wwn_match++;
5994 }
5995
5996 /* check destination WWN for a match */
5997 if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) {
5998 wwn1 = wwn_to_u64(fcport->port_name);
5999 wwn2 = wwn_to_u64(pri_entry->dst_wwpn);
6000 if (wwn2 == (uint64_t)-1)
6001 wwn_match++;
6002 else if (wwn1 == wwn2)
6003 wwn_match++;
6004 }
6005
6006 if (pid_match == 2 || wwn_match == 2) {
6007 /* Found a matching entry */
6008 if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID)
6009 priority = pri_entry->tag;
6010 break;
6011 }
6012
6013 pri_entry++;
6014 }
6015
6016 return priority;
6017}
6018
6019/*
6020 * qla24xx_update_fcport_fcp_prio
6021 * Activates fcp priority for the logged in fc port
6022 *
6023 * Input:
21090cbe 6024 * vha = scsi host structure pointer.
09ff701a
SR		 6025 * fcp = port structure pointer.
6026 *
6027 * Return:
6028 * QLA_SUCCESS or QLA_FUNCTION_FAILED
6029 *
6030 * Context:
6031 * Kernel context.
6032 */
6033int
21090cbe 6034qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
09ff701a
SR		 6035{
6036 int ret;
f28a0a96 6037 int priority;
09ff701a
SR		 6038 uint16_t mb[5];
6039
21090cbe
MI		 6040 if (fcport->port_type != FCT_TARGET ||
6041 fcport->loop_id == FC_NO_LOOP_ID)
09ff701a
SR		 6042 return QLA_FUNCTION_FAILED;
6043
21090cbe 6044 priority = qla24xx_get_fcp_prio(vha, fcport);
f28a0a96
AV		 6045 if (priority < 0)
6046 return QLA_FUNCTION_FAILED;
6047
a00f6296
SK		 6048 if (IS_QLA82XX(vha->hw)) {
6049 fcport->fcp_prio = priority & 0xf;
6050 return QLA_SUCCESS;
6051 }
6052
21090cbe 6053 ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb);
cfb0919c
CD		 6054 if (ret == QLA_SUCCESS) {
6055 if (fcport->fcp_prio != priority)
6056 ql_dbg(ql_dbg_user, vha, 0x709e,
6057 "Updated FCP_CMND priority - value=%d loop_id=%d "
6058 "port_id=%02x%02x%02x.\n", priority,
6059 fcport->loop_id, fcport->d_id.b.domain,
6060 fcport->d_id.b.area, fcport->d_id.b.al_pa);
a00f6296 6061 fcport->fcp_prio = priority & 0xf;
cfb0919c 6062 } else
7c3df132 6063 ql_dbg(ql_dbg_user, vha, 0x704f,
cfb0919c
CD		 6064 "Unable to update FCP_CMND priority - ret=0x%x for "
6065 "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id,
6066 fcport->d_id.b.domain, fcport->d_id.b.area,
6067 fcport->d_id.b.al_pa);
09ff701a
SR		 6068 return ret;
6069}
6070
6071/*
6072 * qla24xx_update_all_fcp_prio
6073 * Activates fcp priority for all the logged in ports
6074 *
6075 * Input:
6076 * ha = adapter block pointer.
6077 *
6078 * Return:
6079 * QLA_SUCCESS or QLA_FUNCTION_FAILED
6080 *
6081 * Context:
6082 * Kernel context.
6083 */
6084int
6085qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha)
6086{
6087 int ret;
6088 fc_port_t *fcport;
6089
6090 ret = QLA_FUNCTION_FAILED;
6091 /* We need to set priority for all logged in ports */
6092 list_for_each_entry(fcport, &vha->vp_fcports, list)
6093 ret = qla24xx_update_fcport_fcp_prio(vha, fcport);
6094
6095 return ret;
6096}
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