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qla2xxx: Fix crash due to wrong casting of reg for ISP27XX.
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / qla2xxx / qla_init.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
73208dfd 8#include "qla_gbl.h"
1da177e4
LT		 9
10#include <linux/delay.h>
5a0e3ad6 11#include <linux/slab.h>
0107109e 12#include <linux/vmalloc.h>
1da177e4
LT		 13
14#include "qla_devtbl.h"
15
4e08df3f
DM		 16#ifdef CONFIG_SPARC
17#include <asm/prom.h>
4e08df3f
DM		 18#endif
19
2d70c103
NB		 20#include <target/target_core_base.h>
21#include "qla_target.h"
22
1da177e4
LT		 23/*
24* QLogic ISP2x00 Hardware Support Function Prototypes.
25*/
1da177e4 26static int qla2x00_isp_firmware(scsi_qla_host_t *);
1da177e4 27static int qla2x00_setup_chip(scsi_qla_host_t *);
1da177e4
LT		 28static int qla2x00_fw_ready(scsi_qla_host_t *);
29static int qla2x00_configure_hba(scsi_qla_host_t *);
1da177e4
LT		 30static int qla2x00_configure_loop(scsi_qla_host_t *);
31static int qla2x00_configure_local_loop(scsi_qla_host_t *);
1da177e4
LT		 32static int qla2x00_configure_fabric(scsi_qla_host_t *);
33static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *, struct list_head *);
1da177e4
LT		 34static int qla2x00_fabric_dev_login(scsi_qla_host_t *, fc_port_t *,
35 uint16_t *);
1da177e4
LT		 36
37static int qla2x00_restart_isp(scsi_qla_host_t *);
1da177e4 38
4d4df193
HK		 39static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *);
40static int qla84xx_init_chip(scsi_qla_host_t *);
73208dfd 41static int qla25xx_init_queues(struct qla_hw_data *);
4d4df193 42
ac280b67
AV		 43/* SRB Extensions ---------------------------------------------------------- */
44
9ba56b95
GM		 45void
46qla2x00_sp_timeout(unsigned long __data)
ac280b67
AV		 47{
48 srb_t *sp = (srb_t *)__data;
4916392b 49 struct srb_iocb *iocb;
ac280b67
AV		 50 fc_port_t *fcport = sp->fcport;
51 struct qla_hw_data *ha = fcport->vha->hw;
52 struct req_que *req;
53 unsigned long flags;
54
55 spin_lock_irqsave(&ha->hardware_lock, flags);
56 req = ha->req_q_map[0];
57 req->outstanding_cmds[sp->handle] = NULL;
9ba56b95 58 iocb = &sp->u.iocb_cmd;
4916392b 59 iocb->timeout(sp);
9ba56b95 60 sp->free(fcport->vha, sp);
6ac52608 61 spin_unlock_irqrestore(&ha->hardware_lock, flags);
ac280b67
AV		 62}
63
9ba56b95
GM		 64void
65qla2x00_sp_free(void *data, void *ptr)
ac280b67 66{
9ba56b95
GM		 67 srb_t *sp = (srb_t *)ptr;
68 struct srb_iocb *iocb = &sp->u.iocb_cmd;
69 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
ac280b67 70
4d97cc53 71 del_timer(&iocb->timer);
b00ee7d7 72 qla2x00_rel_sp(vha, sp);
ac280b67
AV		 73}
74
ac280b67
AV		 75/* Asynchronous Login/Logout Routines -------------------------------------- */
76
a9b6f722 77unsigned long
5b91490e
AV		 78qla2x00_get_async_timeout(struct scsi_qla_host *vha)
79{
80 unsigned long tmo;
81 struct qla_hw_data *ha = vha->hw;
82
83 /* Firmware should use switch negotiated r_a_tov for timeout. */
84 tmo = ha->r_a_tov / 10 * 2;
8ae6d9c7
GM		 85 if (IS_QLAFX00(ha)) {
86 tmo = FX00_DEF_RATOV * 2;
87 } else if (!IS_FWI2_CAPABLE(ha)) {
5b91490e
AV		 88 /*
89 * Except for earlier ISPs where the timeout is seeded from the
90 * initialization control block.
91 */
92 tmo = ha->login_timeout;
93 }
94 return tmo;
95}
ac280b67
AV		 96
97static void
9ba56b95 98qla2x00_async_iocb_timeout(void *data)
ac280b67 99{
9ba56b95 100 srb_t *sp = (srb_t *)data;
ac280b67 101 fc_port_t *fcport = sp->fcport;
ac280b67 102
7c3df132 103 ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
cfb0919c 104 "Async-%s timeout - hdl=%x portid=%02x%02x%02x.\n",
9ba56b95 105 sp->name, sp->handle, fcport->d_id.b.domain, fcport->d_id.b.area,
7c3df132 106 fcport->d_id.b.al_pa);
ac280b67 107
5ff1d584 108 fcport->flags &= ~FCF_ASYNC_SENT;
9ba56b95
GM		 109 if (sp->type == SRB_LOGIN_CMD) {
110 struct srb_iocb *lio = &sp->u.iocb_cmd;
ac280b67 111 qla2x00_post_async_logout_work(fcport->vha, fcport, NULL);
6ac52608
AV		 112 /* Retry as needed. */
113 lio->u.logio.data[0] = MBS_COMMAND_ERROR;
114 lio->u.logio.data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
115 QLA_LOGIO_LOGIN_RETRIED : 0;
116 qla2x00_post_async_login_done_work(fcport->vha, fcport,
117 lio->u.logio.data);
118 }
ac280b67
AV		 119}
120
99b0bec7 121static void
9ba56b95 122qla2x00_async_login_sp_done(void *data, void *ptr, int res)
99b0bec7 123{
9ba56b95
GM		 124 srb_t *sp = (srb_t *)ptr;
125 struct srb_iocb *lio = &sp->u.iocb_cmd;
126 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
127
128 if (!test_bit(UNLOADING, &vha->dpc_flags))
129 qla2x00_post_async_login_done_work(sp->fcport->vha, sp->fcport,
130 lio->u.logio.data);
131 sp->free(sp->fcport->vha, sp);
99b0bec7
AV		 132}
133
ac280b67
AV		 134int
135qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport,
136 uint16_t *data)
137{
ac280b67 138 srb_t *sp;
4916392b 139 struct srb_iocb *lio;
ac280b67
AV		 140 int rval;
141
142 rval = QLA_FUNCTION_FAILED;
9ba56b95 143 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 144 if (!sp)
145 goto done;
146
9ba56b95
GM		 147 sp->type = SRB_LOGIN_CMD;
148 sp->name = "login";
149 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
150
151 lio = &sp->u.iocb_cmd;
3822263e 152 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 153 sp->done = qla2x00_async_login_sp_done;
4916392b 154 lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI;
ac280b67 155 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 156 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
ac280b67
AV		 157 rval = qla2x00_start_sp(sp);
158 if (rval != QLA_SUCCESS)
159 goto done_free_sp;
160
7c3df132 161 ql_dbg(ql_dbg_disc, vha, 0x2072,
cfb0919c
CD		 162 "Async-login - hdl=%x, loopid=%x portid=%02x%02x%02x "
163 "retries=%d.\n", sp->handle, fcport->loop_id,
164 fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
165 fcport->login_retry);
ac280b67
AV		 166 return rval;
167
168done_free_sp:
9ba56b95 169 sp->free(fcport->vha, sp);
ac280b67
AV		 170done:
171 return rval;
172}
173
99b0bec7 174static void
9ba56b95 175qla2x00_async_logout_sp_done(void *data, void *ptr, int res)
99b0bec7 176{
9ba56b95
GM		 177 srb_t *sp = (srb_t *)ptr;
178 struct srb_iocb *lio = &sp->u.iocb_cmd;
179 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
180
181 if (!test_bit(UNLOADING, &vha->dpc_flags))
182 qla2x00_post_async_logout_done_work(sp->fcport->vha, sp->fcport,
183 lio->u.logio.data);
184 sp->free(sp->fcport->vha, sp);
99b0bec7
AV		 185}
186
ac280b67
AV		 187int
188qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport)
189{
ac280b67 190 srb_t *sp;
4916392b 191 struct srb_iocb *lio;
ac280b67
AV		 192 int rval;
193
194 rval = QLA_FUNCTION_FAILED;
9ba56b95 195 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 196 if (!sp)
197 goto done;
198
9ba56b95
GM		 199 sp->type = SRB_LOGOUT_CMD;
200 sp->name = "logout";
201 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
202
203 lio = &sp->u.iocb_cmd;
3822263e 204 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 205 sp->done = qla2x00_async_logout_sp_done;
ac280b67
AV		 206 rval = qla2x00_start_sp(sp);
207 if (rval != QLA_SUCCESS)
208 goto done_free_sp;
209
7c3df132 210 ql_dbg(ql_dbg_disc, vha, 0x2070,
cfb0919c
CD		 211 "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
212 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
213 fcport->d_id.b.area, fcport->d_id.b.al_pa);
ac280b67
AV		 214 return rval;
215
216done_free_sp:
9ba56b95 217 sp->free(fcport->vha, sp);
ac280b67
AV		 218done:
219 return rval;
220}
221
5ff1d584 222static void
9ba56b95 223qla2x00_async_adisc_sp_done(void *data, void *ptr, int res)
5ff1d584 224{
9ba56b95
GM		 225 srb_t *sp = (srb_t *)ptr;
226 struct srb_iocb *lio = &sp->u.iocb_cmd;
227 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
228
229 if (!test_bit(UNLOADING, &vha->dpc_flags))
230 qla2x00_post_async_adisc_done_work(sp->fcport->vha, sp->fcport,
231 lio->u.logio.data);
232 sp->free(sp->fcport->vha, sp);
5ff1d584
AV		 233}
234
235int
236qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport,
237 uint16_t *data)
238{
5ff1d584 239 srb_t *sp;
4916392b 240 struct srb_iocb *lio;
5ff1d584
AV		 241 int rval;
242
243 rval = QLA_FUNCTION_FAILED;
9ba56b95 244 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
5ff1d584
AV		 245 if (!sp)
246 goto done;
247
9ba56b95
GM		 248 sp->type = SRB_ADISC_CMD;
249 sp->name = "adisc";
250 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
251
252 lio = &sp->u.iocb_cmd;
3822263e 253 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 254 sp->done = qla2x00_async_adisc_sp_done;
5ff1d584 255 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 256 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
5ff1d584
AV		 257 rval = qla2x00_start_sp(sp);
258 if (rval != QLA_SUCCESS)
259 goto done_free_sp;
260
7c3df132 261 ql_dbg(ql_dbg_disc, vha, 0x206f,
cfb0919c
CD		 262 "Async-adisc - hdl=%x loopid=%x portid=%02x%02x%02x.\n",
263 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
264 fcport->d_id.b.area, fcport->d_id.b.al_pa);
5ff1d584
AV		 265 return rval;
266
267done_free_sp:
9ba56b95 268 sp->free(fcport->vha, sp);
5ff1d584
AV		 269done:
270 return rval;
271}
272
3822263e 273static void
faef62d1 274qla2x00_tmf_iocb_timeout(void *data)
3822263e 275{
faef62d1
AB		 276 srb_t *sp = (srb_t *)data;
277 struct srb_iocb *tmf = &sp->u.iocb_cmd;
3822263e 278
faef62d1
AB		 279 tmf->u.tmf.comp_status = CS_TIMEOUT;
280 complete(&tmf->u.tmf.comp);
281}
9ba56b95 282
faef62d1
AB		 283static void
284qla2x00_tmf_sp_done(void *data, void *ptr, int res)
285{
286 srb_t *sp = (srb_t *)ptr;
287 struct srb_iocb *tmf = &sp->u.iocb_cmd;
288 complete(&tmf->u.tmf.comp);
3822263e
MI		 289}
290
291int
faef62d1 292qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t flags, uint32_t lun,
3822263e
MI		 293 uint32_t tag)
294{
295 struct scsi_qla_host *vha = fcport->vha;
faef62d1 296 struct srb_iocb *tm_iocb;
3822263e 297 srb_t *sp;
faef62d1 298 int rval = QLA_FUNCTION_FAILED;
3822263e 299
9ba56b95 300 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
3822263e
MI		 301 if (!sp)
302 goto done;
303
faef62d1 304 tm_iocb = &sp->u.iocb_cmd;
9ba56b95
GM		 305 sp->type = SRB_TM_CMD;
306 sp->name = "tmf";
faef62d1
AB		 307 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
308 tm_iocb->u.tmf.flags = flags;
309 tm_iocb->u.tmf.lun = lun;
310 tm_iocb->u.tmf.data = tag;
311 sp->done = qla2x00_tmf_sp_done;
312 tm_iocb->timeout = qla2x00_tmf_iocb_timeout;
313 init_completion(&tm_iocb->u.tmf.comp);
3822263e
MI		 314
315 rval = qla2x00_start_sp(sp);
316 if (rval != QLA_SUCCESS)
317 goto done_free_sp;
318
7c3df132 319 ql_dbg(ql_dbg_taskm, vha, 0x802f,
cfb0919c
CD		 320 "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
321 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
322 fcport->d_id.b.area, fcport->d_id.b.al_pa);
faef62d1
AB		 323
324 wait_for_completion(&tm_iocb->u.tmf.comp);
325
326 rval = tm_iocb->u.tmf.comp_status == CS_COMPLETE ?
327 QLA_SUCCESS : QLA_FUNCTION_FAILED;
328
329 if ((rval != QLA_SUCCESS) || tm_iocb->u.tmf.data) {
330 ql_dbg(ql_dbg_taskm, vha, 0x8030,
331 "TM IOCB failed (%x).\n", rval);
332 }
333
334 if (!test_bit(UNLOADING, &vha->dpc_flags) && !IS_QLAFX00(vha->hw)) {
335 flags = tm_iocb->u.tmf.flags;
336 lun = (uint16_t)tm_iocb->u.tmf.lun;
337
338 /* Issue Marker IOCB */
339 qla2x00_marker(vha, vha->hw->req_q_map[0],
340 vha->hw->rsp_q_map[0], sp->fcport->loop_id, lun,
341 flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
342 }
3822263e
MI		 343
344done_free_sp:
faef62d1 345 sp->free(vha, sp);
3822263e
MI		 346done:
347 return rval;
348}
349
4440e46d
AB		 350static void
351qla24xx_abort_iocb_timeout(void *data)
352{
353 srb_t *sp = (srb_t *)data;
354 struct srb_iocb *abt = &sp->u.iocb_cmd;
355
356 abt->u.abt.comp_status = CS_TIMEOUT;
357 complete(&abt->u.abt.comp);
358}
359
360static void
361qla24xx_abort_sp_done(void *data, void *ptr, int res)
362{
363 srb_t *sp = (srb_t *)ptr;
364 struct srb_iocb *abt = &sp->u.iocb_cmd;
365
366 complete(&abt->u.abt.comp);
367}
368
369static int
370qla24xx_async_abort_cmd(srb_t *cmd_sp)
371{
372 scsi_qla_host_t *vha = cmd_sp->fcport->vha;
373 fc_port_t *fcport = cmd_sp->fcport;
374 struct srb_iocb *abt_iocb;
375 srb_t *sp;
376 int rval = QLA_FUNCTION_FAILED;
377
378 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
379 if (!sp)
380 goto done;
381
382 abt_iocb = &sp->u.iocb_cmd;
383 sp->type = SRB_ABT_CMD;
384 sp->name = "abort";
385 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
386 abt_iocb->u.abt.cmd_hndl = cmd_sp->handle;
387 sp->done = qla24xx_abort_sp_done;
388 abt_iocb->timeout = qla24xx_abort_iocb_timeout;
389 init_completion(&abt_iocb->u.abt.comp);
390
391 rval = qla2x00_start_sp(sp);
392 if (rval != QLA_SUCCESS)
393 goto done_free_sp;
394
395 ql_dbg(ql_dbg_async, vha, 0x507c,
396 "Abort command issued - hdl=%x, target_id=%x\n",
397 cmd_sp->handle, fcport->tgt_id);
398
399 wait_for_completion(&abt_iocb->u.abt.comp);
400
401 rval = abt_iocb->u.abt.comp_status == CS_COMPLETE ?
402 QLA_SUCCESS : QLA_FUNCTION_FAILED;
403
404done_free_sp:
405 sp->free(vha, sp);
406done:
407 return rval;
408}
409
410int
411qla24xx_async_abort_command(srb_t *sp)
412{
413 unsigned long flags = 0;
414
415 uint32_t handle;
416 fc_port_t *fcport = sp->fcport;
417 struct scsi_qla_host *vha = fcport->vha;
418 struct qla_hw_data *ha = vha->hw;
419 struct req_que *req = vha->req;
420
421 spin_lock_irqsave(&ha->hardware_lock, flags);
422 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
423 if (req->outstanding_cmds[handle] == sp)
424 break;
425 }
426 spin_unlock_irqrestore(&ha->hardware_lock, flags);
427 if (handle == req->num_outstanding_cmds) {
428 /* Command not found. */
429 return QLA_FUNCTION_FAILED;
430 }
431 if (sp->type == SRB_FXIOCB_DCMD)
432 return qlafx00_fx_disc(vha, &vha->hw->mr.fcport,
433 FXDISC_ABORT_IOCTL);
434
435 return qla24xx_async_abort_cmd(sp);
436}
437
4916392b 438void
ac280b67
AV		 439qla2x00_async_login_done(struct scsi_qla_host *vha, fc_port_t *fcport,
440 uint16_t *data)
441{
442 int rval;
ac280b67
AV		 443
444 switch (data[0]) {
445 case MBS_COMMAND_COMPLETE:
a4f92a32
AV		 446 /*
447 * Driver must validate login state - If PRLI not complete,
448 * force a relogin attempt via implicit LOGO, PLOGI, and PRLI
449 * requests.
450 */
451 rval = qla2x00_get_port_database(vha, fcport, 0);
0eba25df
AE		 452 if (rval == QLA_NOT_LOGGED_IN) {
453 fcport->flags &= ~FCF_ASYNC_SENT;
454 fcport->flags |= FCF_LOGIN_NEEDED;
455 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
456 break;
457 }
458
a4f92a32
AV		 459 if (rval != QLA_SUCCESS) {
460 qla2x00_post_async_logout_work(vha, fcport, NULL);
461 qla2x00_post_async_login_work(vha, fcport, NULL);
462 break;
463 }
99b0bec7 464 if (fcport->flags & FCF_FCP2_DEVICE) {
5ff1d584
AV		 465 qla2x00_post_async_adisc_work(vha, fcport, data);
466 break;
99b0bec7
AV		 467 }
468 qla2x00_update_fcport(vha, fcport);
ac280b67
AV		 469 break;
470 case MBS_COMMAND_ERROR:
5ff1d584 471 fcport->flags &= ~FCF_ASYNC_SENT;
ac280b67
AV		 472 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
473 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
474 else
80d79440 475 qla2x00_mark_device_lost(vha, fcport, 1, 0);
ac280b67
AV		 476 break;
477 case MBS_PORT_ID_USED:
478 fcport->loop_id = data[1];
6ac52608 479 qla2x00_post_async_logout_work(vha, fcport, NULL);
ac280b67
AV		 480 qla2x00_post_async_login_work(vha, fcport, NULL);
481 break;
482 case MBS_LOOP_ID_USED:
483 fcport->loop_id++;
484 rval = qla2x00_find_new_loop_id(vha, fcport);
485 if (rval != QLA_SUCCESS) {
5ff1d584 486 fcport->flags &= ~FCF_ASYNC_SENT;
80d79440 487 qla2x00_mark_device_lost(vha, fcport, 1, 0);
ac280b67
AV		 488 break;
489 }
490 qla2x00_post_async_login_work(vha, fcport, NULL);
491 break;
492 }
4916392b 493 return;
ac280b67
AV		 494}
495
4916392b 496void
ac280b67
AV		 497qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport,
498 uint16_t *data)
499{
500 qla2x00_mark_device_lost(vha, fcport, 1, 0);
4916392b 501 return;
ac280b67
AV		 502}
503
4916392b 504void
5ff1d584
AV		 505qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport,
506 uint16_t *data)
507{
508 if (data[0] == MBS_COMMAND_COMPLETE) {
509 qla2x00_update_fcport(vha, fcport);
510
4916392b 511 return;
5ff1d584
AV		 512 }
513
514 /* Retry login. */
515 fcport->flags &= ~FCF_ASYNC_SENT;
516 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
517 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
518 else
80d79440 519 qla2x00_mark_device_lost(vha, fcport, 1, 0);
5ff1d584 520
4916392b 521 return;
5ff1d584
AV		 522}
523
1da177e4
LT		 524/****************************************************************************/
525/* QLogic ISP2x00 Hardware Support Functions. */
526/****************************************************************************/
527
fa492630 528static int
7d613ac6
SV		 529qla83xx_nic_core_fw_load(scsi_qla_host_t *vha)
530{
531 int rval = QLA_SUCCESS;
532 struct qla_hw_data *ha = vha->hw;
533 uint32_t idc_major_ver, idc_minor_ver;
711aa7f7 534 uint16_t config[4];
7d613ac6
SV		 535
536 qla83xx_idc_lock(vha, 0);
537
538 /* SV: TODO: Assign initialization timeout from
539 * flash-info / other param
540 */
541 ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT;
542 ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT;
543
544 /* Set our fcoe function presence */
545 if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) {
546 ql_dbg(ql_dbg_p3p, vha, 0xb077,
547 "Error while setting DRV-Presence.\n");
548 rval = QLA_FUNCTION_FAILED;
549 goto exit;
550 }
551
552 /* Decide the reset ownership */
553 qla83xx_reset_ownership(vha);
554
555 /*
556 * On first protocol driver load:
557 * Init-Owner: Set IDC-Major-Version and Clear IDC-Lock-Recovery
558 * register.
559 * Others: Check compatibility with current IDC Major version.
560 */
561 qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver);
562 if (ha->flags.nic_core_reset_owner) {
563 /* Set IDC Major version */
564 idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION;
565 qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver);
566
567 /* Clearing IDC-Lock-Recovery register */
568 qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0);
569 } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) {
570 /*
571 * Clear further IDC participation if we are not compatible with
572 * the current IDC Major Version.
573 */
574 ql_log(ql_log_warn, vha, 0xb07d,
575 "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n",
576 idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION);
577 __qla83xx_clear_drv_presence(vha);
578 rval = QLA_FUNCTION_FAILED;
579 goto exit;
580 }
581 /* Each function sets its supported Minor version. */
582 qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver);
583 idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2));
584 qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver);
585
711aa7f7
SK		 586 if (ha->flags.nic_core_reset_owner) {
587 memset(config, 0, sizeof(config));
588 if (!qla81xx_get_port_config(vha, config))
589 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
590 QLA8XXX_DEV_READY);
591 }
592
7d613ac6
SV		 593 rval = qla83xx_idc_state_handler(vha);
594
595exit:
596 qla83xx_idc_unlock(vha, 0);
597
598 return rval;
599}
600
1da177e4
LT		 601/*
602* qla2x00_initialize_adapter
603* Initialize board.
604*
605* Input:
606* ha = adapter block pointer.
607*
608* Returns:
609* 0 = success
610*/
611int
e315cd28 612qla2x00_initialize_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 613{
614 int rval;
e315cd28 615 struct qla_hw_data *ha = vha->hw;
73208dfd 616 struct req_que *req = ha->req_q_map[0];
2533cf67 617
1da177e4 618 /* Clear adapter flags. */
e315cd28 619 vha->flags.online = 0;
2533cf67 620 ha->flags.chip_reset_done = 0;
e315cd28 621 vha->flags.reset_active = 0;
85880801
AV		 622 ha->flags.pci_channel_io_perm_failure = 0;
623 ha->flags.eeh_busy = 0;
fabbb8df 624 vha->qla_stats.jiffies_at_last_reset = get_jiffies_64();
e315cd28
AC		 625 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
626 atomic_set(&vha->loop_state, LOOP_DOWN);
627 vha->device_flags = DFLG_NO_CABLE;
628 vha->dpc_flags = 0;
629 vha->flags.management_server_logged_in = 0;
630 vha->marker_needed = 0;
1da177e4
LT		 631 ha->isp_abort_cnt = 0;
632 ha->beacon_blink_led = 0;
633
73208dfd
AC		 634 set_bit(0, ha->req_qid_map);
635 set_bit(0, ha->rsp_qid_map);
636
cfb0919c 637 ql_dbg(ql_dbg_init, vha, 0x0040,
7c3df132 638 "Configuring PCI space...\n");
e315cd28 639 rval = ha->isp_ops->pci_config(vha);
1da177e4 640 if (rval) {
7c3df132
SK		 641 ql_log(ql_log_warn, vha, 0x0044,
642 "Unable to configure PCI space.\n");
1da177e4
LT		 643 return (rval);
644 }
645
e315cd28 646 ha->isp_ops->reset_chip(vha);
1da177e4 647
e315cd28 648 rval = qla2xxx_get_flash_info(vha);
c00d8994 649 if (rval) {
7c3df132
SK		 650 ql_log(ql_log_fatal, vha, 0x004f,
651 "Unable to validate FLASH data.\n");
7ec0effd
AD		 652 return rval;
653 }
654
655 if (IS_QLA8044(ha)) {
656 qla8044_read_reset_template(vha);
657
658 /* NOTE: If ql2xdontresethba==1, set IDC_CTRL DONTRESET_BIT0.
659 * If DONRESET_BIT0 is set, drivers should not set dev_state
660 * to NEED_RESET. But if NEED_RESET is set, drivers should
661 * should honor the reset. */
662 if (ql2xdontresethba == 1)
663 qla8044_set_idc_dontreset(vha);
c00d8994
AV		 664 }
665
73208dfd 666 ha->isp_ops->get_flash_version(vha, req->ring);
cfb0919c 667 ql_dbg(ql_dbg_init, vha, 0x0061,
7c3df132 668 "Configure NVRAM parameters...\n");
0107109e 669
e315cd28 670 ha->isp_ops->nvram_config(vha);
1da177e4 671
d4c760c2
AV		 672 if (ha->flags.disable_serdes) {
673 /* Mask HBA via NVRAM settings? */
7c3df132 674 ql_log(ql_log_info, vha, 0x0077,
7b833558 675 "Masking HBA WWPN %8phN (via NVRAM).\n", vha->port_name);
d4c760c2
AV		 676 return QLA_FUNCTION_FAILED;
677 }
678
cfb0919c 679 ql_dbg(ql_dbg_init, vha, 0x0078,
7c3df132 680 "Verifying loaded RISC code...\n");
1da177e4 681
e315cd28
AC		 682 if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) {
683 rval = ha->isp_ops->chip_diag(vha);
d19044c3
AV		 684 if (rval)
685 return (rval);
e315cd28 686 rval = qla2x00_setup_chip(vha);
d19044c3
AV		 687 if (rval)
688 return (rval);
1da177e4 689 }
a9083016 690
4d4df193 691 if (IS_QLA84XX(ha)) {
e315cd28 692 ha->cs84xx = qla84xx_get_chip(vha);
4d4df193 693 if (!ha->cs84xx) {
7c3df132 694 ql_log(ql_log_warn, vha, 0x00d0,
4d4df193
HK		 695 "Unable to configure ISP84XX.\n");
696 return QLA_FUNCTION_FAILED;
697 }
698 }
2d70c103
NB		 699
700 if (qla_ini_mode_enabled(vha))
701 rval = qla2x00_init_rings(vha);
702
2533cf67 703 ha->flags.chip_reset_done = 1;
1da177e4 704
9a069e19 705 if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) {
6c452a45 706 /* Issue verify 84xx FW IOCB to complete 84xx initialization */
9a069e19
GM		 707 rval = qla84xx_init_chip(vha);
708 if (rval != QLA_SUCCESS) {
7c3df132
SK		 709 ql_log(ql_log_warn, vha, 0x00d4,
710 "Unable to initialize ISP84XX.\n");
9a069e19
GM		 711 qla84xx_put_chip(vha);
712 }
713 }
714
7d613ac6
SV		 715 /* Load the NIC Core f/w if we are the first protocol driver. */
716 if (IS_QLA8031(ha)) {
717 rval = qla83xx_nic_core_fw_load(vha);
718 if (rval)
719 ql_log(ql_log_warn, vha, 0x0124,
720 "Error in initializing NIC Core f/w.\n");
721 }
722
2f0f3f4f
MI		 723 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
724 qla24xx_read_fcp_prio_cfg(vha);
09ff701a 725
c46e65c7
JC		 726 if (IS_P3P_TYPE(ha))
727 qla82xx_set_driver_version(vha, QLA2XXX_VERSION);
728 else
729 qla25xx_set_driver_version(vha, QLA2XXX_VERSION);
730
1da177e4
LT		 731 return (rval);
732}
733
734/**
abbd8870 735 * qla2100_pci_config() - Setup ISP21xx PCI configuration registers.
1da177e4
LT		 736 * @ha: HA context
737 *
738 * Returns 0 on success.
739 */
abbd8870 740int
e315cd28 741qla2100_pci_config(scsi_qla_host_t *vha)
1da177e4 742{
a157b101 743 uint16_t w;
abbd8870 744 unsigned long flags;
e315cd28 745 struct qla_hw_data *ha = vha->hw;
3d71644c 746 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 747
1da177e4 748 pci_set_master(ha->pdev);
af6177d8 749 pci_try_set_mwi(ha->pdev);
1da177e4 750
1da177e4 751 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 752 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
abbd8870
AV		 753 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
754
737faece 755 pci_disable_rom(ha->pdev);
1da177e4
LT		 756
757 /* Get PCI bus information. */
758 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 759 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
1da177e4
LT		 760 spin_unlock_irqrestore(&ha->hardware_lock, flags);
761
abbd8870
AV		 762 return QLA_SUCCESS;
763}
1da177e4 764
abbd8870
AV		 765/**
766 * qla2300_pci_config() - Setup ISP23xx PCI configuration registers.
767 * @ha: HA context
768 *
769 * Returns 0 on success.
770 */
771int
e315cd28 772qla2300_pci_config(scsi_qla_host_t *vha)
abbd8870 773{
a157b101 774 uint16_t w;
abbd8870
AV		 775 unsigned long flags = 0;
776 uint32_t cnt;
e315cd28 777 struct qla_hw_data *ha = vha->hw;
3d71644c 778 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 779
abbd8870 780 pci_set_master(ha->pdev);
af6177d8 781 pci_try_set_mwi(ha->pdev);
1da177e4 782
abbd8870 783 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 784 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
1da177e4 785
abbd8870
AV		 786 if (IS_QLA2322(ha) || IS_QLA6322(ha))
787 w &= ~PCI_COMMAND_INTX_DISABLE;
a157b101 788 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1da177e4 789
abbd8870
AV		 790 /*
791 * If this is a 2300 card and not 2312, reset the
792 * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately,
793 * the 2310 also reports itself as a 2300 so we need to get the
794 * fb revision level -- a 6 indicates it really is a 2300 and
795 * not a 2310.
796 */
797 if (IS_QLA2300(ha)) {
798 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 799
abbd8870 800 /* Pause RISC. */
3d71644c 801 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
abbd8870 802 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 803 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
abbd8870 804 break;
1da177e4 805
abbd8870
AV		 806 udelay(10);
807 }
1da177e4 808
abbd8870 809 /* Select FPM registers. */
3d71644c
AV		 810 WRT_REG_WORD(&reg->ctrl_status, 0x20);
811 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 812
813 /* Get the fb rev level */
3d71644c 814 ha->fb_rev = RD_FB_CMD_REG(ha, reg);
abbd8870
AV		 815
816 if (ha->fb_rev == FPM_2300)
a157b101 817 pci_clear_mwi(ha->pdev);
abbd8870
AV		 818
819 /* Deselect FPM registers. */
3d71644c
AV		 820 WRT_REG_WORD(&reg->ctrl_status, 0x0);
821 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 822
823 /* Release RISC module. */
3d71644c 824 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
abbd8870 825 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 826 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0)
abbd8870
AV		 827 break;
828
829 udelay(10);
1da177e4 830 }
1da177e4 831
abbd8870
AV		 832 spin_unlock_irqrestore(&ha->hardware_lock, flags);
833 }
1da177e4 834
abbd8870
AV		 835 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
836
737faece 837 pci_disable_rom(ha->pdev);
1da177e4 838
abbd8870
AV		 839 /* Get PCI bus information. */
840 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 841 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 842 spin_unlock_irqrestore(&ha->hardware_lock, flags);
843
844 return QLA_SUCCESS;
1da177e4
LT		 845}
846
0107109e
AV		 847/**
848 * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers.
849 * @ha: HA context
850 *
851 * Returns 0 on success.
852 */
853int
e315cd28 854qla24xx_pci_config(scsi_qla_host_t *vha)
0107109e 855{
a157b101 856 uint16_t w;
0107109e 857 unsigned long flags = 0;
e315cd28 858 struct qla_hw_data *ha = vha->hw;
0107109e 859 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
0107109e
AV		 860
861 pci_set_master(ha->pdev);
af6177d8 862 pci_try_set_mwi(ha->pdev);
0107109e
AV		 863
864 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 865 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
0107109e
AV		 866 w &= ~PCI_COMMAND_INTX_DISABLE;
867 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
868
869 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
870
871 /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */
f85ec187
AV		 872 if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
873 pcix_set_mmrbc(ha->pdev, 2048);
0107109e
AV		 874
875 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 876 if (pci_is_pcie(ha->pdev))
5ffd3a52 877 pcie_set_readrq(ha->pdev, 4096);
0107109e 878
737faece 879 pci_disable_rom(ha->pdev);
0107109e 880
44c10138 881 ha->chip_revision = ha->pdev->revision;
a8488abe 882
0107109e
AV		 883 /* Get PCI bus information. */
884 spin_lock_irqsave(&ha->hardware_lock, flags);
885 ha->pci_attr = RD_REG_DWORD(&reg->ctrl_status);
886 spin_unlock_irqrestore(&ha->hardware_lock, flags);
887
888 return QLA_SUCCESS;
889}
890
c3a2f0df
AV		 891/**
892 * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers.
893 * @ha: HA context
894 *
895 * Returns 0 on success.
896 */
897int
e315cd28 898qla25xx_pci_config(scsi_qla_host_t *vha)
c3a2f0df
AV		 899{
900 uint16_t w;
e315cd28 901 struct qla_hw_data *ha = vha->hw;
c3a2f0df
AV		 902
903 pci_set_master(ha->pdev);
904 pci_try_set_mwi(ha->pdev);
905
906 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
907 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
908 w &= ~PCI_COMMAND_INTX_DISABLE;
909 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
910
911 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 912 if (pci_is_pcie(ha->pdev))
5ffd3a52 913 pcie_set_readrq(ha->pdev, 4096);
c3a2f0df 914
737faece 915 pci_disable_rom(ha->pdev);
c3a2f0df
AV		 916
917 ha->chip_revision = ha->pdev->revision;
918
919 return QLA_SUCCESS;
920}
921
1da177e4
LT		 922/**
923 * qla2x00_isp_firmware() - Choose firmware image.
924 * @ha: HA context
925 *
926 * Returns 0 on success.
927 */
928static int
e315cd28 929qla2x00_isp_firmware(scsi_qla_host_t *vha)
1da177e4
LT		 930{
931 int rval;
42e421b1
AV		 932 uint16_t loop_id, topo, sw_cap;
933 uint8_t domain, area, al_pa;
e315cd28 934 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 935
936 /* Assume loading risc code */
fa2a1ce5 937 rval = QLA_FUNCTION_FAILED;
1da177e4
LT		 938
939 if (ha->flags.disable_risc_code_load) {
7c3df132 940 ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n");
1da177e4
LT		 941
942 /* Verify checksum of loaded RISC code. */
e315cd28 943 rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address);
42e421b1
AV		 944 if (rval == QLA_SUCCESS) {
945 /* And, verify we are not in ROM code. */
e315cd28 946 rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa,
42e421b1
AV		 947 &area, &domain, &topo, &sw_cap);
948 }
1da177e4
LT		 949 }
950
7c3df132
SK		 951 if (rval)
952 ql_dbg(ql_dbg_init, vha, 0x007a,
953 "**** Load RISC code ****.\n");
1da177e4
LT		 954
955 return (rval);
956}
957
958/**
959 * qla2x00_reset_chip() - Reset ISP chip.
960 * @ha: HA context
961 *
962 * Returns 0 on success.
963 */
abbd8870 964void
e315cd28 965qla2x00_reset_chip(scsi_qla_host_t *vha)
1da177e4
LT		 966{
967 unsigned long flags = 0;
e315cd28 968 struct qla_hw_data *ha = vha->hw;
3d71644c 969 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 970 uint32_t cnt;
1da177e4
LT		 971 uint16_t cmd;
972
85880801
AV		 973 if (unlikely(pci_channel_offline(ha->pdev)))
974 return;
975
fd34f556 976 ha->isp_ops->disable_intrs(ha);
1da177e4
LT		 977
978 spin_lock_irqsave(&ha->hardware_lock, flags);
979
980 /* Turn off master enable */
981 cmd = 0;
982 pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd);
983 cmd &= ~PCI_COMMAND_MASTER;
984 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
985
986 if (!IS_QLA2100(ha)) {
987 /* Pause RISC. */
988 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
989 if (IS_QLA2200(ha) || IS_QLA2300(ha)) {
990 for (cnt = 0; cnt < 30000; cnt++) {
991 if ((RD_REG_WORD(&reg->hccr) &
992 HCCR_RISC_PAUSE) != 0)
993 break;
994 udelay(100);
995 }
996 } else {
997 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
998 udelay(10);
999 }
1000
1001 /* Select FPM registers. */
1002 WRT_REG_WORD(&reg->ctrl_status, 0x20);
1003 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1004
1005 /* FPM Soft Reset. */
1006 WRT_REG_WORD(&reg->fpm_diag_config, 0x100);
1007 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
1008
1009 /* Toggle Fpm Reset. */
1010 if (!IS_QLA2200(ha)) {
1011 WRT_REG_WORD(&reg->fpm_diag_config, 0x0);
1012 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
1013 }
1014
1015 /* Select frame buffer registers. */
1016 WRT_REG_WORD(&reg->ctrl_status, 0x10);
1017 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1018
1019 /* Reset frame buffer FIFOs. */
1020 if (IS_QLA2200(ha)) {
1021 WRT_FB_CMD_REG(ha, reg, 0xa000);
1022 RD_FB_CMD_REG(ha, reg); /* PCI Posting. */
1023 } else {
1024 WRT_FB_CMD_REG(ha, reg, 0x00fc);
1025
1026 /* Read back fb_cmd until zero or 3 seconds max */
1027 for (cnt = 0; cnt < 3000; cnt++) {
1028 if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0)
1029 break;
1030 udelay(100);
1031 }
1032 }
1033
1034 /* Select RISC module registers. */
1035 WRT_REG_WORD(&reg->ctrl_status, 0);
1036 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1037
1038 /* Reset RISC processor. */
1039 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
1040 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1041
1042 /* Release RISC processor. */
1043 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
1044 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1045 }
1046
1047 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
1048 WRT_REG_WORD(&reg->hccr, HCCR_CLR_HOST_INT);
1049
1050 /* Reset ISP chip. */
1051 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1052
1053 /* Wait for RISC to recover from reset. */
1054 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1055 /*
1056 * It is necessary to for a delay here since the card doesn't
1057 * respond to PCI reads during a reset. On some architectures
1058 * this will result in an MCA.
1059 */
1060 udelay(20);
1061 for (cnt = 30000; cnt; cnt--) {
1062 if ((RD_REG_WORD(&reg->ctrl_status) &
1063 CSR_ISP_SOFT_RESET) == 0)
1064 break;
1065 udelay(100);
1066 }
1067 } else
1068 udelay(10);
1069
1070 /* Reset RISC processor. */
1071 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
1072
1073 WRT_REG_WORD(&reg->semaphore, 0);
1074
1075 /* Release RISC processor. */
1076 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
1077 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1078
1079 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1080 for (cnt = 0; cnt < 30000; cnt++) {
ffb39f03 1081 if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY)
1da177e4 1082 break;
1da177e4
LT		 1083
1084 udelay(100);
1085 }
1086 } else
1087 udelay(100);
1088
1089 /* Turn on master enable */
1090 cmd |= PCI_COMMAND_MASTER;
1091 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
1092
1093 /* Disable RISC pause on FPM parity error. */
1094 if (!IS_QLA2100(ha)) {
1095 WRT_REG_WORD(&reg->hccr, HCCR_DISABLE_PARITY_PAUSE);
1096 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1097 }
1098
1099 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1100}
1101
b1d46989
MI		 1102/**
1103 * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC.
1104 *
1105 * Returns 0 on success.
1106 */
fa492630 1107static int
b1d46989
MI		 1108qla81xx_reset_mpi(scsi_qla_host_t *vha)
1109{
1110 uint16_t mb[4] = {0x1010, 0, 1, 0};
1111
6246b8a1
GM		 1112 if (!IS_QLA81XX(vha->hw))
1113 return QLA_SUCCESS;
1114
b1d46989
MI		 1115 return qla81xx_write_mpi_register(vha, mb);
1116}
1117
0107109e 1118/**
88c26663 1119 * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC.
0107109e
AV		 1120 * @ha: HA context
1121 *
1122 * Returns 0 on success.
1123 */
88c26663 1124static inline void
e315cd28 1125qla24xx_reset_risc(scsi_qla_host_t *vha)
0107109e
AV		 1126{
1127 unsigned long flags = 0;
e315cd28 1128 struct qla_hw_data *ha = vha->hw;
0107109e
AV		 1129 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1130 uint32_t cnt, d2;
335a1cc9 1131 uint16_t wd;
b1d46989 1132 static int abts_cnt; /* ISP abort retry counts */
0107109e 1133
0107109e
AV		 1134 spin_lock_irqsave(&ha->hardware_lock, flags);
1135
1136 /* Reset RISC. */
1137 WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
1138 for (cnt = 0; cnt < 30000; cnt++) {
1139 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
1140 break;
1141
1142 udelay(10);
1143 }
1144
1145 WRT_REG_DWORD(&reg->ctrl_status,
1146 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
335a1cc9 1147 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
88c26663 1148
335a1cc9 1149 udelay(100);
88c26663 1150 /* Wait for firmware to complete NVRAM accesses. */
88c26663
AV		 1151 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1152 for (cnt = 10000 ; cnt && d2; cnt--) {
1153 udelay(5);
1154 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1155 barrier();
1156 }
1157
335a1cc9 1158 /* Wait for soft-reset to complete. */
0107109e
AV		 1159 d2 = RD_REG_DWORD(&reg->ctrl_status);
1160 for (cnt = 6000000 ; cnt && (d2 & CSRX_ISP_SOFT_RESET); cnt--) {
1161 udelay(5);
1162 d2 = RD_REG_DWORD(&reg->ctrl_status);
1163 barrier();
1164 }
1165
b1d46989
MI		 1166 /* If required, do an MPI FW reset now */
1167 if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
1168 if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
1169 if (++abts_cnt < 5) {
1170 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1171 set_bit(MPI_RESET_NEEDED, &vha->dpc_flags);
1172 } else {
1173 /*
1174 * We exhausted the ISP abort retries. We have to
1175 * set the board offline.
1176 */
1177 abts_cnt = 0;
1178 vha->flags.online = 0;
1179 }
1180 }
1181 }
1182
0107109e
AV		 1183 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
1184 RD_REG_DWORD(&reg->hccr);
1185
1186 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
1187 RD_REG_DWORD(&reg->hccr);
1188
1189 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
1190 RD_REG_DWORD(&reg->hccr);
1191
1192 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1193 for (cnt = 6000000 ; cnt && d2; cnt--) {
1194 udelay(5);
1195 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1196 barrier();
1197 }
1198
1199 spin_unlock_irqrestore(&ha->hardware_lock, flags);
124f85e6
AV		 1200
1201 if (IS_NOPOLLING_TYPE(ha))
1202 ha->isp_ops->enable_intrs(ha);
0107109e
AV		 1203}
1204
4ea2c9c7
JC		 1205static void
1206qla25xx_read_risc_sema_reg(scsi_qla_host_t *vha, uint32_t *data)
1207{
1208 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
1209
1210 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
1211 *data = RD_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET);
1212
1213}
1214
1215static void
1216qla25xx_write_risc_sema_reg(scsi_qla_host_t *vha, uint32_t data)
1217{
1218 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
1219
1220 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
1221 WRT_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET, data);
1222}
1223
1224static void
1225qla25xx_manipulate_risc_semaphore(scsi_qla_host_t *vha)
1226{
1227 struct qla_hw_data *ha = vha->hw;
1228 uint32_t wd32 = 0;
1229 uint delta_msec = 100;
1230 uint elapsed_msec = 0;
1231 uint timeout_msec;
1232 ulong n;
1233
1234 if (!IS_QLA25XX(ha) && !IS_QLA2031(ha))
1235 return;
1236
1237attempt:
1238 timeout_msec = TIMEOUT_SEMAPHORE;
1239 n = timeout_msec / delta_msec;
1240 while (n--) {
1241 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_SET);
1242 qla25xx_read_risc_sema_reg(vha, &wd32);
1243 if (wd32 & RISC_SEMAPHORE)
1244 break;
1245 msleep(delta_msec);
1246 elapsed_msec += delta_msec;
1247 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
1248 goto force;
1249 }
1250
1251 if (!(wd32 & RISC_SEMAPHORE))
1252 goto force;
1253
1254 if (!(wd32 & RISC_SEMAPHORE_FORCE))
1255 goto acquired;
1256
1257 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_CLR);
1258 timeout_msec = TIMEOUT_SEMAPHORE_FORCE;
1259 n = timeout_msec / delta_msec;
1260 while (n--) {
1261 qla25xx_read_risc_sema_reg(vha, &wd32);
1262 if (!(wd32 & RISC_SEMAPHORE_FORCE))
1263 break;
1264 msleep(delta_msec);
1265 elapsed_msec += delta_msec;
1266 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
1267 goto force;
1268 }
1269
1270 if (wd32 & RISC_SEMAPHORE_FORCE)
1271 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_CLR);
1272
1273 goto attempt;
1274
1275force:
1276 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_SET);
1277
1278acquired:
1279 return;
1280}
1281
88c26663
AV		 1282/**
1283 * qla24xx_reset_chip() - Reset ISP24xx chip.
1284 * @ha: HA context
1285 *
1286 * Returns 0 on success.
1287 */
1288void
e315cd28 1289qla24xx_reset_chip(scsi_qla_host_t *vha)
88c26663 1290{
e315cd28 1291 struct qla_hw_data *ha = vha->hw;
85880801
AV		 1292
1293 if (pci_channel_offline(ha->pdev) &&
1294 ha->flags.pci_channel_io_perm_failure) {
1295 return;
1296 }
1297
fd34f556 1298 ha->isp_ops->disable_intrs(ha);
88c26663 1299
4ea2c9c7
JC		 1300 qla25xx_manipulate_risc_semaphore(vha);
1301
88c26663 1302 /* Perform RISC reset. */
e315cd28 1303 qla24xx_reset_risc(vha);
88c26663
AV		 1304}
1305
1da177e4
LT		 1306/**
1307 * qla2x00_chip_diag() - Test chip for proper operation.
1308 * @ha: HA context
1309 *
1310 * Returns 0 on success.
1311 */
abbd8870 1312int
e315cd28 1313qla2x00_chip_diag(scsi_qla_host_t *vha)
1da177e4
LT		 1314{
1315 int rval;
e315cd28 1316 struct qla_hw_data *ha = vha->hw;
3d71644c 1317 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 1318 unsigned long flags = 0;
1319 uint16_t data;
1320 uint32_t cnt;
1321 uint16_t mb[5];
73208dfd 1322 struct req_que *req = ha->req_q_map[0];
1da177e4
LT		 1323
1324 /* Assume a failed state */
1325 rval = QLA_FUNCTION_FAILED;
1326
7c3df132
SK		 1327 ql_dbg(ql_dbg_init, vha, 0x007b,
1328 "Testing device at %lx.\n", (u_long)&reg->flash_address);
1da177e4
LT		 1329
1330 spin_lock_irqsave(&ha->hardware_lock, flags);
1331
1332 /* Reset ISP chip. */
1333 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1334
1335 /*
1336 * We need to have a delay here since the card will not respond while
1337 * in reset causing an MCA on some architectures.
1338 */
1339 udelay(20);
1340 data = qla2x00_debounce_register(&reg->ctrl_status);
1341 for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {
1342 udelay(5);
1343 data = RD_REG_WORD(&reg->ctrl_status);
1344 barrier();
1345 }
1346
1347 if (!cnt)
1348 goto chip_diag_failed;
1349
7c3df132
SK		 1350 ql_dbg(ql_dbg_init, vha, 0x007c,
1351 "Reset register cleared by chip reset.\n");
1da177e4
LT		 1352
1353 /* Reset RISC processor. */
1354 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
1355 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
1356
1357 /* Workaround for QLA2312 PCI parity error */
1358 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1359 data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0));
1360 for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) {
1361 udelay(5);
1362 data = RD_MAILBOX_REG(ha, reg, 0);
fa2a1ce5 1363 barrier();
1da177e4
LT		 1364 }
1365 } else
1366 udelay(10);
1367
1368 if (!cnt)
1369 goto chip_diag_failed;
1370
1371 /* Check product ID of chip */
7c3df132 1372 ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product Id of chip.\n");
1da177e4
LT		 1373
1374 mb[1] = RD_MAILBOX_REG(ha, reg, 1);
1375 mb[2] = RD_MAILBOX_REG(ha, reg, 2);
1376 mb[3] = RD_MAILBOX_REG(ha, reg, 3);
1377 mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4));
1378 if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) ||
1379 mb[3] != PROD_ID_3) {
7c3df132
SK		 1380 ql_log(ql_log_warn, vha, 0x0062,
1381 "Wrong product ID = 0x%x,0x%x,0x%x.\n",
1382 mb[1], mb[2], mb[3]);
1da177e4
LT		 1383
1384 goto chip_diag_failed;
1385 }
1386 ha->product_id[0] = mb[1];
1387 ha->product_id[1] = mb[2];
1388 ha->product_id[2] = mb[3];
1389 ha->product_id[3] = mb[4];
1390
1391 /* Adjust fw RISC transfer size */
73208dfd 1392 if (req->length > 1024)
1da177e4
LT		 1393 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024;
1394 else
1395 ha->fw_transfer_size = REQUEST_ENTRY_SIZE *
73208dfd 1396 req->length;
1da177e4
LT		 1397
1398 if (IS_QLA2200(ha) &&
1399 RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) {
1400 /* Limit firmware transfer size with a 2200A */
7c3df132 1401 ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n");
1da177e4 1402
ea5b6382 1403 ha->device_type |= DT_ISP2200A;
1da177e4
LT		 1404 ha->fw_transfer_size = 128;
1405 }
1406
1407 /* Wrap Incoming Mailboxes Test. */
1408 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1409
7c3df132 1410 ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n");
e315cd28 1411 rval = qla2x00_mbx_reg_test(vha);
7c3df132
SK		 1412 if (rval)
1413 ql_log(ql_log_warn, vha, 0x0080,
1414 "Failed mailbox send register test.\n");
1415 else
1da177e4
LT		 1416 /* Flag a successful rval */
1417 rval = QLA_SUCCESS;
1da177e4
LT		 1418 spin_lock_irqsave(&ha->hardware_lock, flags);
1419
1420chip_diag_failed:
1421 if (rval)
7c3df132
SK		 1422 ql_log(ql_log_info, vha, 0x0081,
1423 "Chip diagnostics **** FAILED ****.\n");
1da177e4
LT		 1424
1425 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1426
1427 return (rval);
1428}
1429
0107109e
AV		 1430/**
1431 * qla24xx_chip_diag() - Test ISP24xx for proper operation.
1432 * @ha: HA context
1433 *
1434 * Returns 0 on success.
1435 */
1436int
e315cd28 1437qla24xx_chip_diag(scsi_qla_host_t *vha)
0107109e
AV		 1438{
1439 int rval;
e315cd28 1440 struct qla_hw_data *ha = vha->hw;
73208dfd 1441 struct req_que *req = ha->req_q_map[0];
0107109e 1442
7ec0effd 1443 if (IS_P3P_TYPE(ha))
a9083016
GM		 1444 return QLA_SUCCESS;
1445
73208dfd 1446 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
0107109e 1447
e315cd28 1448 rval = qla2x00_mbx_reg_test(vha);
0107109e 1449 if (rval) {
7c3df132
SK		 1450 ql_log(ql_log_warn, vha, 0x0082,
1451 "Failed mailbox send register test.\n");
0107109e
AV		 1452 } else {
1453 /* Flag a successful rval */
1454 rval = QLA_SUCCESS;
1455 }
1456
1457 return rval;
1458}
1459
a7a167bf 1460void
e315cd28 1461qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
0107109e 1462{
a7a167bf
AV		 1463 int rval;
1464 uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
73208dfd 1465 eft_size, fce_size, mq_size;
df613b96
AV		 1466 dma_addr_t tc_dma;
1467 void *tc;
e315cd28 1468 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 1469 struct req_que *req = ha->req_q_map[0];
1470 struct rsp_que *rsp = ha->rsp_q_map[0];
a7a167bf
AV		 1471
1472 if (ha->fw_dump) {
7c3df132
SK		 1473 ql_dbg(ql_dbg_init, vha, 0x00bd,
1474 "Firmware dump already allocated.\n");
a7a167bf
AV		 1475 return;
1476 }
d4e3e04d 1477
0107109e 1478 ha->fw_dumped = 0;
61f098dd 1479 ha->fw_dump_cap_flags = 0;
f73cb695
CD		 1480 dump_size = fixed_size = mem_size = eft_size = fce_size = mq_size = 0;
1481 req_q_size = rsp_q_size = 0;
1482
1483 if (IS_QLA27XX(ha))
1484 goto try_fce;
1485
d4e3e04d 1486 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
a7a167bf 1487 fixed_size = sizeof(struct qla2100_fw_dump);
d4e3e04d 1488 } else if (IS_QLA23XX(ha)) {
a7a167bf
AV		 1489 fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
1490 mem_size = (ha->fw_memory_size - 0x11000 + 1) *
1491 sizeof(uint16_t);
e428924c 1492 } else if (IS_FWI2_CAPABLE(ha)) {
6246b8a1
GM		 1493 if (IS_QLA83XX(ha))
1494 fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem);
1495 else if (IS_QLA81XX(ha))
3a03eb79
AV		 1496 fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
1497 else if (IS_QLA25XX(ha))
1498 fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
1499 else
1500 fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
f73cb695 1501
a7a167bf
AV		 1502 mem_size = (ha->fw_memory_size - 0x100000 + 1) *
1503 sizeof(uint32_t);
050c9bb1 1504 if (ha->mqenable) {
6246b8a1
GM		 1505 if (!IS_QLA83XX(ha))
1506 mq_size = sizeof(struct qla2xxx_mq_chain);
050c9bb1
GM		 1507 /*
1508 * Allocate maximum buffer size for all queues.
1509 * Resizing must be done at end-of-dump processing.
1510 */
1511 mq_size += ha->max_req_queues *
1512 (req->length * sizeof(request_t));
1513 mq_size += ha->max_rsp_queues *
1514 (rsp->length * sizeof(response_t));
1515 }
00876ae8 1516 if (ha->tgt.atio_ring)
2d70c103 1517 mq_size += ha->tgt.atio_q_length * sizeof(request_t);
df613b96 1518 /* Allocate memory for Fibre Channel Event Buffer. */
f73cb695
CD		 1519 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
1520 !IS_QLA27XX(ha))
436a7b11 1521 goto try_eft;
df613b96 1522
f73cb695
CD		 1523try_fce:
1524 if (ha->fce)
1525 dma_free_coherent(&ha->pdev->dev,
1526 FCE_SIZE, ha->fce, ha->fce_dma);
1527
1528 /* Allocate memory for Fibre Channel Event Buffer. */
0ea85b50
JP		 1529 tc = dma_zalloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
1530 GFP_KERNEL);
df613b96 1531 if (!tc) {
7c3df132
SK		 1532 ql_log(ql_log_warn, vha, 0x00be,
1533 "Unable to allocate (%d KB) for FCE.\n",
1534 FCE_SIZE / 1024);
17d98630 1535 goto try_eft;
df613b96
AV		 1536 }
1537
e315cd28 1538 rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS,
df613b96
AV		 1539 ha->fce_mb, &ha->fce_bufs);
1540 if (rval) {
7c3df132
SK		 1541 ql_log(ql_log_warn, vha, 0x00bf,
1542 "Unable to initialize FCE (%d).\n", rval);
df613b96
AV		 1543 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc,
1544 tc_dma);
1545 ha->flags.fce_enabled = 0;
17d98630 1546 goto try_eft;
df613b96 1547 }
cfb0919c 1548 ql_dbg(ql_dbg_init, vha, 0x00c0,
7c3df132 1549 "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024);
df613b96 1550
7d9dade3 1551 fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE;
df613b96
AV		 1552 ha->flags.fce_enabled = 1;
1553 ha->fce_dma = tc_dma;
1554 ha->fce = tc;
f73cb695 1555
436a7b11 1556try_eft:
f73cb695
CD		 1557 if (ha->eft)
1558 dma_free_coherent(&ha->pdev->dev,
1559 EFT_SIZE, ha->eft, ha->eft_dma);
1560
436a7b11 1561 /* Allocate memory for Extended Trace Buffer. */
0ea85b50
JP		 1562 tc = dma_zalloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
1563 GFP_KERNEL);
436a7b11 1564 if (!tc) {
7c3df132
SK		 1565 ql_log(ql_log_warn, vha, 0x00c1,
1566 "Unable to allocate (%d KB) for EFT.\n",
1567 EFT_SIZE / 1024);
436a7b11
AV		 1568 goto cont_alloc;
1569 }
1570
e315cd28 1571 rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
436a7b11 1572 if (rval) {
7c3df132
SK		 1573 ql_log(ql_log_warn, vha, 0x00c2,
1574 "Unable to initialize EFT (%d).\n", rval);
436a7b11
AV		 1575 dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc,
1576 tc_dma);
1577 goto cont_alloc;
1578 }
cfb0919c 1579 ql_dbg(ql_dbg_init, vha, 0x00c3,
7c3df132 1580 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
436a7b11
AV		 1581
1582 eft_size = EFT_SIZE;
1583 ha->eft_dma = tc_dma;
1584 ha->eft = tc;
d4e3e04d 1585 }
f73cb695 1586
a7a167bf 1587cont_alloc:
f73cb695
CD		 1588 if (IS_QLA27XX(ha)) {
1589 if (!ha->fw_dump_template) {
1590 ql_log(ql_log_warn, vha, 0x00ba,
1591 "Failed missing fwdump template\n");
1592 return;
1593 }
1594 dump_size = qla27xx_fwdt_calculate_dump_size(vha);
1595 ql_dbg(ql_dbg_init, vha, 0x00fa,
1596 "-> allocating fwdump (%x bytes)...\n", dump_size);
1597 goto allocate;
1598 }
1599
73208dfd
AC		 1600 req_q_size = req->length * sizeof(request_t);
1601 rsp_q_size = rsp->length * sizeof(response_t);
a7a167bf 1602 dump_size = offsetof(struct qla2xxx_fw_dump, isp);
2afa19a9 1603 dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size;
bb99de67
AV		 1604 ha->chain_offset = dump_size;
1605 dump_size += mq_size + fce_size;
d4e3e04d 1606
f73cb695 1607allocate:
d4e3e04d 1608 ha->fw_dump = vmalloc(dump_size);
a7a167bf 1609 if (!ha->fw_dump) {
7c3df132
SK		 1610 ql_log(ql_log_warn, vha, 0x00c4,
1611 "Unable to allocate (%d KB) for firmware dump.\n",
1612 dump_size / 1024);
a7a167bf 1613
e30d1756
MI		 1614 if (ha->fce) {
1615 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
1616 ha->fce_dma);
1617 ha->fce = NULL;
1618 ha->fce_dma = 0;
1619 }
1620
a7a167bf
AV		 1621 if (ha->eft) {
1622 dma_free_coherent(&ha->pdev->dev, eft_size, ha->eft,
1623 ha->eft_dma);
1624 ha->eft = NULL;
1625 ha->eft_dma = 0;
1626 }
1627 return;
1628 }
f73cb695 1629 ha->fw_dump_len = dump_size;
cfb0919c 1630 ql_dbg(ql_dbg_init, vha, 0x00c5,
7c3df132 1631 "Allocated (%d KB) for firmware dump.\n", dump_size / 1024);
a7a167bf 1632
f73cb695
CD		 1633 if (IS_QLA27XX(ha))
1634 return;
1635
a7a167bf
AV		 1636 ha->fw_dump->signature[0] = 'Q';
1637 ha->fw_dump->signature[1] = 'L';
1638 ha->fw_dump->signature[2] = 'G';
1639 ha->fw_dump->signature[3] = 'C';
1640 ha->fw_dump->version = __constant_htonl(1);
1641
1642 ha->fw_dump->fixed_size = htonl(fixed_size);
1643 ha->fw_dump->mem_size = htonl(mem_size);
1644 ha->fw_dump->req_q_size = htonl(req_q_size);
1645 ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
1646
1647 ha->fw_dump->eft_size = htonl(eft_size);
1648 ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma));
1649 ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma));
1650
1651 ha->fw_dump->header_size =
1652 htonl(offsetof(struct qla2xxx_fw_dump, isp));
0107109e
AV		 1653}
1654
18e7555a
AV		 1655static int
1656qla81xx_mpi_sync(scsi_qla_host_t *vha)
1657{
1658#define MPS_MASK 0xe0
1659 int rval;
1660 uint16_t dc;
1661 uint32_t dw;
18e7555a
AV		 1662
1663 if (!IS_QLA81XX(vha->hw))
1664 return QLA_SUCCESS;
1665
1666 rval = qla2x00_write_ram_word(vha, 0x7c00, 1);
1667 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1668 ql_log(ql_log_warn, vha, 0x0105,
1669 "Unable to acquire semaphore.\n");
18e7555a
AV		 1670 goto done;
1671 }
1672
1673 pci_read_config_word(vha->hw->pdev, 0x54, &dc);
1674 rval = qla2x00_read_ram_word(vha, 0x7a15, &dw);
1675 if (rval != QLA_SUCCESS) {
7c3df132 1676 ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n");
18e7555a
AV		 1677 goto done_release;
1678 }
1679
1680 dc &= MPS_MASK;
1681 if (dc == (dw & MPS_MASK))
1682 goto done_release;
1683
1684 dw &= ~MPS_MASK;
1685 dw |= dc;
1686 rval = qla2x00_write_ram_word(vha, 0x7a15, dw);
1687 if (rval != QLA_SUCCESS) {
7c3df132 1688 ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n");
18e7555a
AV		 1689 }
1690
1691done_release:
1692 rval = qla2x00_write_ram_word(vha, 0x7c00, 0);
1693 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1694 ql_log(ql_log_warn, vha, 0x006d,
1695 "Unable to release semaphore.\n");
18e7555a
AV		 1696 }
1697
1698done:
1699 return rval;
1700}
1701
8d93f550
CD		 1702int
1703qla2x00_alloc_outstanding_cmds(struct qla_hw_data *ha, struct req_que *req)
1704{
1705 /* Don't try to reallocate the array */
1706 if (req->outstanding_cmds)
1707 return QLA_SUCCESS;
1708
1709 if (!IS_FWI2_CAPABLE(ha) || (ha->mqiobase &&
1710 (ql2xmultique_tag || ql2xmaxqueues > 1)))
1711 req->num_outstanding_cmds = DEFAULT_OUTSTANDING_COMMANDS;
1712 else {
1713 if (ha->fw_xcb_count <= ha->fw_iocb_count)
1714 req->num_outstanding_cmds = ha->fw_xcb_count;
1715 else
1716 req->num_outstanding_cmds = ha->fw_iocb_count;
1717 }
1718
1719 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
1720 req->num_outstanding_cmds, GFP_KERNEL);
1721
1722 if (!req->outstanding_cmds) {
1723 /*
1724 * Try to allocate a minimal size just so we can get through
1725 * initialization.
1726 */
1727 req->num_outstanding_cmds = MIN_OUTSTANDING_COMMANDS;
1728 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
1729 req->num_outstanding_cmds, GFP_KERNEL);
1730
1731 if (!req->outstanding_cmds) {
1732 ql_log(ql_log_fatal, NULL, 0x0126,
1733 "Failed to allocate memory for "
1734 "outstanding_cmds for req_que %p.\n", req);
1735 req->num_outstanding_cmds = 0;
1736 return QLA_FUNCTION_FAILED;
1737 }
1738 }
1739
1740 return QLA_SUCCESS;
1741}
1742
1da177e4
LT		 1743/**
1744 * qla2x00_setup_chip() - Load and start RISC firmware.
1745 * @ha: HA context
1746 *
1747 * Returns 0 on success.
1748 */
1749static int
e315cd28 1750qla2x00_setup_chip(scsi_qla_host_t *vha)
1da177e4 1751{
0107109e
AV		 1752 int rval;
1753 uint32_t srisc_address = 0;
e315cd28 1754 struct qla_hw_data *ha = vha->hw;
3db0652e
AV		 1755 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1756 unsigned long flags;
dda772e8 1757 uint16_t fw_major_version;
3db0652e 1758
7ec0effd 1759 if (IS_P3P_TYPE(ha)) {
a9083016 1760 rval = ha->isp_ops->load_risc(vha, &srisc_address);
14e303d9
AV		 1761 if (rval == QLA_SUCCESS) {
1762 qla2x00_stop_firmware(vha);
a9083016 1763 goto enable_82xx_npiv;
14e303d9 1764 } else
b963752f 1765 goto failed;
a9083016
GM		 1766 }
1767
3db0652e
AV		 1768 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1769 /* Disable SRAM, Instruction RAM and GP RAM parity. */
1770 spin_lock_irqsave(&ha->hardware_lock, flags);
1771 WRT_REG_WORD(&reg->hccr, (HCCR_ENABLE_PARITY + 0x0));
1772 RD_REG_WORD(&reg->hccr);
1773 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1774 }
1da177e4 1775
18e7555a
AV		 1776 qla81xx_mpi_sync(vha);
1777
1da177e4 1778 /* Load firmware sequences */
e315cd28 1779 rval = ha->isp_ops->load_risc(vha, &srisc_address);
0107109e 1780 if (rval == QLA_SUCCESS) {
7c3df132
SK		 1781 ql_dbg(ql_dbg_init, vha, 0x00c9,
1782 "Verifying Checksum of loaded RISC code.\n");
1da177e4 1783
e315cd28 1784 rval = qla2x00_verify_checksum(vha, srisc_address);
1da177e4
LT		 1785 if (rval == QLA_SUCCESS) {
1786 /* Start firmware execution. */
7c3df132
SK		 1787 ql_dbg(ql_dbg_init, vha, 0x00ca,
1788 "Starting firmware.\n");
1da177e4 1789
e315cd28 1790 rval = qla2x00_execute_fw(vha, srisc_address);
1da177e4 1791 /* Retrieve firmware information. */
dda772e8 1792 if (rval == QLA_SUCCESS) {
a9083016 1793enable_82xx_npiv:
dda772e8 1794 fw_major_version = ha->fw_major_version;
7ec0effd 1795 if (IS_P3P_TYPE(ha))
3173167f 1796 qla82xx_check_md_needed(vha);
6246b8a1
GM		 1797 else
1798 rval = qla2x00_get_fw_version(vha);
ca9e9c3e
AV		 1799 if (rval != QLA_SUCCESS)
1800 goto failed;
2c3dfe3f 1801 ha->flags.npiv_supported = 0;
e315cd28 1802 if (IS_QLA2XXX_MIDTYPE(ha) &&
946fb891 1803 (ha->fw_attributes & BIT_2)) {
2c3dfe3f 1804 ha->flags.npiv_supported = 1;
4d0ea247
SJ		 1805 if ((!ha->max_npiv_vports) ||
1806 ((ha->max_npiv_vports + 1) %
eb66dc60 1807 MIN_MULTI_ID_FABRIC))
4d0ea247 1808 ha->max_npiv_vports =
eb66dc60 1809 MIN_MULTI_ID_FABRIC - 1;
4d0ea247 1810 }
24a08138 1811 qla2x00_get_resource_cnts(vha, NULL,
8d93f550 1812 &ha->fw_xcb_count, NULL, &ha->fw_iocb_count,
f3a0a77e 1813 &ha->max_npiv_vports, NULL);
d743de66 1814
8d93f550
CD		 1815 /*
1816 * Allocate the array of outstanding commands
1817 * now that we know the firmware resources.
1818 */
1819 rval = qla2x00_alloc_outstanding_cmds(ha,
1820 vha->req);
1821 if (rval != QLA_SUCCESS)
1822 goto failed;
1823
be5ea3cf 1824 if (!fw_major_version && ql2xallocfwdump
7ec0effd 1825 && !(IS_P3P_TYPE(ha)))
08de2844 1826 qla2x00_alloc_fw_dump(vha);
3b6e5b9d
CD		 1827 } else {
1828 goto failed;
1da177e4
LT		 1829 }
1830 } else {
7c3df132
SK		 1831 ql_log(ql_log_fatal, vha, 0x00cd,
1832 "ISP Firmware failed checksum.\n");
1833 goto failed;
1da177e4 1834 }
c74d88a4
AV		 1835 } else
1836 goto failed;
1da177e4 1837
3db0652e
AV		 1838 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1839 /* Enable proper parity. */
1840 spin_lock_irqsave(&ha->hardware_lock, flags);
1841 if (IS_QLA2300(ha))
1842 /* SRAM parity */
1843 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x1);
1844 else
1845 /* SRAM, Instruction RAM and GP RAM parity */
1846 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x7);
1847 RD_REG_WORD(&reg->hccr);
1848 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1849 }
1850
f3982d89
CD		 1851 if (IS_QLA27XX(ha))
1852 ha->flags.fac_supported = 1;
1853 else if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
1d2874de
JC		 1854 uint32_t size;
1855
1856 rval = qla81xx_fac_get_sector_size(vha, &size);
1857 if (rval == QLA_SUCCESS) {
1858 ha->flags.fac_supported = 1;
1859 ha->fdt_block_size = size << 2;
1860 } else {
7c3df132 1861 ql_log(ql_log_warn, vha, 0x00ce,
1d2874de
JC		 1862 "Unsupported FAC firmware (%d.%02d.%02d).\n",
1863 ha->fw_major_version, ha->fw_minor_version,
1864 ha->fw_subminor_version);
1ca60e3b 1865
f73cb695 1866 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
6246b8a1
GM		 1867 ha->flags.fac_supported = 0;
1868 rval = QLA_SUCCESS;
1869 }
1d2874de
JC		 1870 }
1871 }
ca9e9c3e 1872failed:
1da177e4 1873 if (rval) {
7c3df132
SK		 1874 ql_log(ql_log_fatal, vha, 0x00cf,
1875 "Setup chip ****FAILED****.\n");
1da177e4
LT		 1876 }
1877
1878 return (rval);
1879}
1880
1881/**
1882 * qla2x00_init_response_q_entries() - Initializes response queue entries.
1883 * @ha: HA context
1884 *
1885 * Beginning of request ring has initialization control block already built
1886 * by nvram config routine.
1887 *
1888 * Returns 0 on success.
1889 */
73208dfd
AC		 1890void
1891qla2x00_init_response_q_entries(struct rsp_que *rsp)
1da177e4
LT		 1892{
1893 uint16_t cnt;
1894 response_t *pkt;
1895
2afa19a9
AC		 1896 rsp->ring_ptr = rsp->ring;
1897 rsp->ring_index = 0;
1898 rsp->status_srb = NULL;
e315cd28
AC		 1899 pkt = rsp->ring_ptr;
1900 for (cnt = 0; cnt < rsp->length; cnt++) {
1da177e4
LT		 1901 pkt->signature = RESPONSE_PROCESSED;
1902 pkt++;
1903 }
1da177e4
LT		 1904}
1905
1906/**
1907 * qla2x00_update_fw_options() - Read and process firmware options.
1908 * @ha: HA context
1909 *
1910 * Returns 0 on success.
1911 */
abbd8870 1912void
e315cd28 1913qla2x00_update_fw_options(scsi_qla_host_t *vha)
1da177e4
LT		 1914{
1915 uint16_t swing, emphasis, tx_sens, rx_sens;
e315cd28 1916 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 1917
1918 memset(ha->fw_options, 0, sizeof(ha->fw_options));
e315cd28 1919 qla2x00_get_fw_options(vha, ha->fw_options);
1da177e4
LT		 1920
1921 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1922 return;
1923
1924 /* Serial Link options. */
7c3df132
SK		 1925 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
1926 "Serial link options.\n");
1927 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
1928 (uint8_t *)&ha->fw_seriallink_options,
1929 sizeof(ha->fw_seriallink_options));
1da177e4
LT		 1930
1931 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1932 if (ha->fw_seriallink_options[3] & BIT_2) {
1933 ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING;
1934
1935 /* 1G settings */
1936 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
1937 emphasis = (ha->fw_seriallink_options[2] &
1938 (BIT_4 | BIT_3)) >> 3;
1939 tx_sens = ha->fw_seriallink_options[0] &
fa2a1ce5 1940 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 1941 rx_sens = (ha->fw_seriallink_options[0] &
1942 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
1943 ha->fw_options[10] = (emphasis << 14) | (swing << 8);
1944 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
1945 if (rx_sens == 0x0)
1946 rx_sens = 0x3;
1947 ha->fw_options[10] |= (tx_sens << 4) | rx_sens;
1948 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
1949 ha->fw_options[10] |= BIT_5 |
1950 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
1951 (tx_sens & (BIT_1 | BIT_0));
1952
1953 /* 2G settings */
1954 swing = (ha->fw_seriallink_options[2] &
1955 (BIT_7 | BIT_6 | BIT_5)) >> 5;
1956 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
1957 tx_sens = ha->fw_seriallink_options[1] &
fa2a1ce5 1958 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 1959 rx_sens = (ha->fw_seriallink_options[1] &
1960 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
1961 ha->fw_options[11] = (emphasis << 14) | (swing << 8);
1962 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
1963 if (rx_sens == 0x0)
1964 rx_sens = 0x3;
1965 ha->fw_options[11] |= (tx_sens << 4) | rx_sens;
1966 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
1967 ha->fw_options[11] |= BIT_5 |
1968 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
1969 (tx_sens & (BIT_1 | BIT_0));
1970 }
1971
1972 /* FCP2 options. */
1973 /* Return command IOCBs without waiting for an ABTS to complete. */
1974 ha->fw_options[3] |= BIT_13;
1975
1976 /* LED scheme. */
1977 if (ha->flags.enable_led_scheme)
1978 ha->fw_options[2] |= BIT_12;
1979
48c02fde
AV		 1980 /* Detect ISP6312. */
1981 if (IS_QLA6312(ha))
1982 ha->fw_options[2] |= BIT_13;
1983
1da177e4 1984 /* Update firmware options. */
e315cd28 1985 qla2x00_set_fw_options(vha, ha->fw_options);
1da177e4
LT		 1986}
1987
0107109e 1988void
e315cd28 1989qla24xx_update_fw_options(scsi_qla_host_t *vha)
0107109e
AV		 1990{
1991 int rval;
e315cd28 1992 struct qla_hw_data *ha = vha->hw;
0107109e 1993
7ec0effd 1994 if (IS_P3P_TYPE(ha))
a9083016
GM		 1995 return;
1996
0107109e 1997 /* Update Serial Link options. */
f94097ed 1998 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0)
0107109e
AV		 1999 return;
2000
e315cd28 2001 rval = qla2x00_set_serdes_params(vha,
f94097ed
AV		 2002 le16_to_cpu(ha->fw_seriallink_options24[1]),
2003 le16_to_cpu(ha->fw_seriallink_options24[2]),
2004 le16_to_cpu(ha->fw_seriallink_options24[3]));
0107109e 2005 if (rval != QLA_SUCCESS) {
7c3df132 2006 ql_log(ql_log_warn, vha, 0x0104,
0107109e
AV		 2007 "Unable to update Serial Link options (%x).\n", rval);
2008 }
2009}
2010
abbd8870 2011void
e315cd28 2012qla2x00_config_rings(struct scsi_qla_host *vha)
abbd8870 2013{
e315cd28 2014 struct qla_hw_data *ha = vha->hw;
3d71644c 2015 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
73208dfd
AC		 2016 struct req_que *req = ha->req_q_map[0];
2017 struct rsp_que *rsp = ha->rsp_q_map[0];
abbd8870
AV		 2018
2019 /* Setup ring parameters in initialization control block. */
2020 ha->init_cb->request_q_outpointer = __constant_cpu_to_le16(0);
2021 ha->init_cb->response_q_inpointer = __constant_cpu_to_le16(0);
e315cd28
AC		 2022 ha->init_cb->request_q_length = cpu_to_le16(req->length);
2023 ha->init_cb->response_q_length = cpu_to_le16(rsp->length);
2024 ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
2025 ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
2026 ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
2027 ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
abbd8870
AV		 2028
2029 WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0);
2030 WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0);
2031 WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0);
2032 WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0);
2033 RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */
2034}
2035
0107109e 2036void
e315cd28 2037qla24xx_config_rings(struct scsi_qla_host *vha)
0107109e 2038{
e315cd28 2039 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 2040 device_reg_t __iomem *reg = ISP_QUE_REG(ha, 0);
2041 struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
2042 struct qla_msix_entry *msix;
0107109e 2043 struct init_cb_24xx *icb;
73208dfd
AC		 2044 uint16_t rid = 0;
2045 struct req_que *req = ha->req_q_map[0];
2046 struct rsp_que *rsp = ha->rsp_q_map[0];
0107109e 2047
6246b8a1 2048 /* Setup ring parameters in initialization control block. */
0107109e
AV		 2049 icb = (struct init_cb_24xx *)ha->init_cb;
2050 icb->request_q_outpointer = __constant_cpu_to_le16(0);
2051 icb->response_q_inpointer = __constant_cpu_to_le16(0);
e315cd28
AC		 2052 icb->request_q_length = cpu_to_le16(req->length);
2053 icb->response_q_length = cpu_to_le16(rsp->length);
2054 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
2055 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
2056 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
2057 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
0107109e 2058
2d70c103
NB		 2059 /* Setup ATIO queue dma pointers for target mode */
2060 icb->atio_q_inpointer = __constant_cpu_to_le16(0);
2061 icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length);
2062 icb->atio_q_address[0] = cpu_to_le32(LSD(ha->tgt.atio_dma));
2063 icb->atio_q_address[1] = cpu_to_le32(MSD(ha->tgt.atio_dma));
2064
7c6300e3
JC		 2065 if (IS_SHADOW_REG_CAPABLE(ha))
2066 icb->firmware_options_2 |=
2067 __constant_cpu_to_le32(BIT_30|BIT_29);
2068
f73cb695 2069 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
73208dfd
AC		 2070 icb->qos = __constant_cpu_to_le16(QLA_DEFAULT_QUE_QOS);
2071 icb->rid = __constant_cpu_to_le16(rid);
2072 if (ha->flags.msix_enabled) {
2073 msix = &ha->msix_entries[1];
7c3df132
SK		 2074 ql_dbg(ql_dbg_init, vha, 0x00fd,
2075 "Registering vector 0x%x for base que.\n",
2076 msix->entry);
73208dfd
AC		 2077 icb->msix = cpu_to_le16(msix->entry);
2078 }
2079 /* Use alternate PCI bus number */
2080 if (MSB(rid))
2081 icb->firmware_options_2 |=
2082 __constant_cpu_to_le32(BIT_19);
2083 /* Use alternate PCI devfn */
2084 if (LSB(rid))
2085 icb->firmware_options_2 |=
2086 __constant_cpu_to_le32(BIT_18);
2087
3155754a 2088 /* Use Disable MSIX Handshake mode for capable adapters */
6246b8a1
GM		 2089 if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) &&
2090 (ha->flags.msix_enabled)) {
3155754a
AC		 2091 icb->firmware_options_2 &=
2092 __constant_cpu_to_le32(~BIT_22);
2093 ha->flags.disable_msix_handshake = 1;
7c3df132
SK		 2094 ql_dbg(ql_dbg_init, vha, 0x00fe,
2095 "MSIX Handshake Disable Mode turned on.\n");
3155754a
AC		 2096 } else {
2097 icb->firmware_options_2 |=
2098 __constant_cpu_to_le32(BIT_22);
2099 }
73208dfd 2100 icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_23);
73208dfd
AC		 2101
2102 WRT_REG_DWORD(&reg->isp25mq.req_q_in, 0);
2103 WRT_REG_DWORD(&reg->isp25mq.req_q_out, 0);
2104 WRT_REG_DWORD(&reg->isp25mq.rsp_q_in, 0);
2105 WRT_REG_DWORD(&reg->isp25mq.rsp_q_out, 0);
2106 } else {
2107 WRT_REG_DWORD(&reg->isp24.req_q_in, 0);
2108 WRT_REG_DWORD(&reg->isp24.req_q_out, 0);
2109 WRT_REG_DWORD(&reg->isp24.rsp_q_in, 0);
2110 WRT_REG_DWORD(&reg->isp24.rsp_q_out, 0);
2111 }
aa230bc5 2112 qlt_24xx_config_rings(vha);
2d70c103 2113
73208dfd
AC		 2114 /* PCI posting */
2115 RD_REG_DWORD(&ioreg->hccr);
0107109e
AV		 2116}
2117
1da177e4
LT		 2118/**
2119 * qla2x00_init_rings() - Initializes firmware.
2120 * @ha: HA context
2121 *
2122 * Beginning of request ring has initialization control block already built
2123 * by nvram config routine.
2124 *
2125 * Returns 0 on success.
2126 */
8ae6d9c7 2127int
e315cd28 2128qla2x00_init_rings(scsi_qla_host_t *vha)
1da177e4
LT		 2129{
2130 int rval;
2131 unsigned long flags = 0;
29bdccbe 2132 int cnt, que;
e315cd28 2133 struct qla_hw_data *ha = vha->hw;
29bdccbe
AC		 2134 struct req_que *req;
2135 struct rsp_que *rsp;
2c3dfe3f
SJ		 2136 struct mid_init_cb_24xx *mid_init_cb =
2137 (struct mid_init_cb_24xx *) ha->init_cb;
1da177e4
LT		 2138
2139 spin_lock_irqsave(&ha->hardware_lock, flags);
2140
2141 /* Clear outstanding commands array. */
2afa19a9 2142 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe
AC		 2143 req = ha->req_q_map[que];
2144 if (!req)
2145 continue;
7c6300e3
JC		 2146 req->out_ptr = (void *)(req->ring + req->length);
2147 *req->out_ptr = 0;
8d93f550 2148 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++)
29bdccbe 2149 req->outstanding_cmds[cnt] = NULL;
1da177e4 2150
2afa19a9 2151 req->current_outstanding_cmd = 1;
1da177e4 2152
29bdccbe
AC		 2153 /* Initialize firmware. */
2154 req->ring_ptr = req->ring;
2155 req->ring_index = 0;
2156 req->cnt = req->length;
2157 }
1da177e4 2158
2afa19a9 2159 for (que = 0; que < ha->max_rsp_queues; que++) {
29bdccbe
AC		 2160 rsp = ha->rsp_q_map[que];
2161 if (!rsp)
2162 continue;
7c6300e3
JC		 2163 rsp->in_ptr = (void *)(rsp->ring + rsp->length);
2164 *rsp->in_ptr = 0;
29bdccbe 2165 /* Initialize response queue entries */
8ae6d9c7
GM		 2166 if (IS_QLAFX00(ha))
2167 qlafx00_init_response_q_entries(rsp);
2168 else
2169 qla2x00_init_response_q_entries(rsp);
29bdccbe 2170 }
1da177e4 2171
2d70c103
NB		 2172 ha->tgt.atio_ring_ptr = ha->tgt.atio_ring;
2173 ha->tgt.atio_ring_index = 0;
2174 /* Initialize ATIO queue entries */
2175 qlt_init_atio_q_entries(vha);
2176
e315cd28 2177 ha->isp_ops->config_rings(vha);
1da177e4
LT		 2178
2179 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2180
8ae6d9c7
GM		 2181 ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n");
2182
2183 if (IS_QLAFX00(ha)) {
2184 rval = qlafx00_init_firmware(vha, ha->init_cb_size);
2185 goto next_check;
2186 }
2187
1da177e4 2188 /* Update any ISP specific firmware options before initialization. */
e315cd28 2189 ha->isp_ops->update_fw_options(vha);
1da177e4 2190
605aa2bc 2191 if (ha->flags.npiv_supported) {
45980cc2 2192 if (ha->operating_mode == LOOP && !IS_CNA_CAPABLE(ha))
605aa2bc 2193 ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
c48339de 2194 mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
605aa2bc
LC		 2195 }
2196
24a08138
AV		 2197 if (IS_FWI2_CAPABLE(ha)) {
2198 mid_init_cb->options = __constant_cpu_to_le16(BIT_1);
2199 mid_init_cb->init_cb.execution_throttle =
2200 cpu_to_le16(ha->fw_xcb_count);
25232cc9
HM		 2201 /* D-Port Status */
2202 if (IS_DPORT_CAPABLE(ha))
2203 mid_init_cb->init_cb.firmware_options_1 |=
2204 cpu_to_le16(BIT_7);
2486c627
HM		 2205 /* Enable FA-WWPN */
2206 ha->flags.fawwpn_enabled =
2207 (mid_init_cb->init_cb.firmware_options_1 & BIT_6) ? 1 : 0;
2208 ql_dbg(ql_dbg_init, vha, 0x0141, "FA-WWPN Support: %s.\n",
2209 (ha->flags.fawwpn_enabled) ? "enabled" : "disabled");
24a08138 2210 }
2c3dfe3f 2211
e315cd28 2212 rval = qla2x00_init_firmware(vha, ha->init_cb_size);
8ae6d9c7 2213next_check:
1da177e4 2214 if (rval) {
7c3df132
SK		 2215 ql_log(ql_log_fatal, vha, 0x00d2,
2216 "Init Firmware **** FAILED ****.\n");
1da177e4 2217 } else {
7c3df132
SK		 2218 ql_dbg(ql_dbg_init, vha, 0x00d3,
2219 "Init Firmware -- success.\n");
1da177e4
LT		 2220 }
2221
2222 return (rval);
2223}
2224
2225/**
2226 * qla2x00_fw_ready() - Waits for firmware ready.
2227 * @ha: HA context
2228 *
2229 * Returns 0 on success.
2230 */
2231static int
e315cd28 2232qla2x00_fw_ready(scsi_qla_host_t *vha)
1da177e4
LT		 2233{
2234 int rval;
4d4df193 2235 unsigned long wtime, mtime, cs84xx_time;
1da177e4
LT		 2236 uint16_t min_wait; /* Minimum wait time if loop is down */
2237 uint16_t wait_time; /* Wait time if loop is coming ready */
b5a340dd 2238 uint16_t state[6];
e315cd28 2239 struct qla_hw_data *ha = vha->hw;
1da177e4 2240
8ae6d9c7
GM		 2241 if (IS_QLAFX00(vha->hw))
2242 return qlafx00_fw_ready(vha);
2243
1da177e4
LT		 2244 rval = QLA_SUCCESS;
2245
2246 /* 20 seconds for loop down. */
fa2a1ce5 2247 min_wait = 20;
1da177e4
LT		 2248
2249 /*
2250 * Firmware should take at most one RATOV to login, plus 5 seconds for
2251 * our own processing.
2252 */
2253 if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) {
2254 wait_time = min_wait;
2255 }
2256
2257 /* Min wait time if loop down */
2258 mtime = jiffies + (min_wait * HZ);
2259
2260 /* wait time before firmware ready */
2261 wtime = jiffies + (wait_time * HZ);
2262
2263 /* Wait for ISP to finish LIP */
e315cd28 2264 if (!vha->flags.init_done)
7c3df132
SK		 2265 ql_log(ql_log_info, vha, 0x801e,
2266 "Waiting for LIP to complete.\n");
1da177e4
LT		 2267
2268 do {
5b939038 2269 memset(state, -1, sizeof(state));
e315cd28 2270 rval = qla2x00_get_firmware_state(vha, state);
1da177e4 2271 if (rval == QLA_SUCCESS) {
4d4df193 2272 if (state[0] < FSTATE_LOSS_OF_SYNC) {
e315cd28 2273 vha->device_flags &= ~DFLG_NO_CABLE;
1da177e4 2274 }
4d4df193 2275 if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) {
7c3df132
SK		 2276 ql_dbg(ql_dbg_taskm, vha, 0x801f,
2277 "fw_state=%x 84xx=%x.\n", state[0],
2278 state[2]);
4d4df193
HK		 2279 if ((state[2] & FSTATE_LOGGED_IN) &&
2280 (state[2] & FSTATE_WAITING_FOR_VERIFY)) {
7c3df132
SK		 2281 ql_dbg(ql_dbg_taskm, vha, 0x8028,
2282 "Sending verify iocb.\n");
4d4df193
HK		 2283
2284 cs84xx_time = jiffies;
e315cd28 2285 rval = qla84xx_init_chip(vha);
7c3df132
SK		 2286 if (rval != QLA_SUCCESS) {
2287 ql_log(ql_log_warn,
cfb0919c 2288 vha, 0x8007,
7c3df132 2289 "Init chip failed.\n");
4d4df193 2290 break;
7c3df132 2291 }
4d4df193
HK		 2292
2293 /* Add time taken to initialize. */
2294 cs84xx_time = jiffies - cs84xx_time;
2295 wtime += cs84xx_time;
2296 mtime += cs84xx_time;
cfb0919c 2297 ql_dbg(ql_dbg_taskm, vha, 0x8008,
7c3df132
SK		 2298 "Increasing wait time by %ld. "
2299 "New time %ld.\n", cs84xx_time,
2300 wtime);
4d4df193
HK		 2301 }
2302 } else if (state[0] == FSTATE_READY) {
7c3df132
SK		 2303 ql_dbg(ql_dbg_taskm, vha, 0x8037,
2304 "F/W Ready - OK.\n");
1da177e4 2305
e315cd28 2306 qla2x00_get_retry_cnt(vha, &ha->retry_count,
1da177e4
LT		 2307 &ha->login_timeout, &ha->r_a_tov);
2308
2309 rval = QLA_SUCCESS;
2310 break;
2311 }
2312
2313 rval = QLA_FUNCTION_FAILED;
2314
e315cd28 2315 if (atomic_read(&vha->loop_down_timer) &&
4d4df193 2316 state[0] != FSTATE_READY) {
1da177e4 2317 /* Loop down. Timeout on min_wait for states
fa2a1ce5
AV		 2318 * other than Wait for Login.
2319 */
1da177e4 2320 if (time_after_eq(jiffies, mtime)) {
7c3df132 2321 ql_log(ql_log_info, vha, 0x8038,
1da177e4
LT		 2322 "Cable is unplugged...\n");
2323
e315cd28 2324 vha->device_flags |= DFLG_NO_CABLE;
1da177e4
LT		 2325 break;
2326 }
2327 }
2328 } else {
2329 /* Mailbox cmd failed. Timeout on min_wait. */
cdbb0a4f 2330 if (time_after_eq(jiffies, mtime) ||
7190575f 2331 ha->flags.isp82xx_fw_hung)
1da177e4
LT		 2332 break;
2333 }
2334
2335 if (time_after_eq(jiffies, wtime))
2336 break;
2337
2338 /* Delay for a while */
2339 msleep(500);
1da177e4
LT		 2340 } while (1);
2341
7c3df132 2342 ql_dbg(ql_dbg_taskm, vha, 0x803a,
b5a340dd
JC		 2343 "fw_state=%x (%x, %x, %x, %x %x) curr time=%lx.\n", state[0],
2344 state[1], state[2], state[3], state[4], state[5], jiffies);
1da177e4 2345
cfb0919c 2346 if (rval && !(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132
SK		 2347 ql_log(ql_log_warn, vha, 0x803b,
2348 "Firmware ready **** FAILED ****.\n");
1da177e4
LT		 2349 }
2350
2351 return (rval);
2352}
2353
2354/*
2355* qla2x00_configure_hba
2356* Setup adapter context.
2357*
2358* Input:
2359* ha = adapter state pointer.
2360*
2361* Returns:
2362* 0 = success
2363*
2364* Context:
2365* Kernel context.
2366*/
2367static int
e315cd28 2368qla2x00_configure_hba(scsi_qla_host_t *vha)
1da177e4
LT		 2369{
2370 int rval;
2371 uint16_t loop_id;
2372 uint16_t topo;
2c3dfe3f 2373 uint16_t sw_cap;
1da177e4
LT		 2374 uint8_t al_pa;
2375 uint8_t area;
2376 uint8_t domain;
2377 char connect_type[22];
e315cd28 2378 struct qla_hw_data *ha = vha->hw;
f24b5cb8 2379 unsigned long flags;
61e1b269 2380 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 2381
2382 /* Get host addresses. */
e315cd28 2383 rval = qla2x00_get_adapter_id(vha,
2c3dfe3f 2384 &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
1da177e4 2385 if (rval != QLA_SUCCESS) {
e315cd28 2386 if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
6246b8a1 2387 IS_CNA_CAPABLE(ha) ||
33135aa2 2388 (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
7c3df132
SK		 2389 ql_dbg(ql_dbg_disc, vha, 0x2008,
2390 "Loop is in a transition state.\n");
33135aa2 2391 } else {
7c3df132
SK		 2392 ql_log(ql_log_warn, vha, 0x2009,
2393 "Unable to get host loop ID.\n");
61e1b269
JC		 2394 if (IS_FWI2_CAPABLE(ha) && (vha == base_vha) &&
2395 (rval == QLA_COMMAND_ERROR && loop_id == 0x1b)) {
2396 ql_log(ql_log_warn, vha, 0x1151,
2397 "Doing link init.\n");
2398 if (qla24xx_link_initialize(vha) == QLA_SUCCESS)
2399 return rval;
2400 }
e315cd28 2401 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
33135aa2 2402 }
1da177e4
LT		 2403 return (rval);
2404 }
2405
2406 if (topo == 4) {
7c3df132
SK		 2407 ql_log(ql_log_info, vha, 0x200a,
2408 "Cannot get topology - retrying.\n");
1da177e4
LT		 2409 return (QLA_FUNCTION_FAILED);
2410 }
2411
e315cd28 2412 vha->loop_id = loop_id;
1da177e4
LT		 2413
2414 /* initialize */
2415 ha->min_external_loopid = SNS_FIRST_LOOP_ID;
2416 ha->operating_mode = LOOP;
2c3dfe3f 2417 ha->switch_cap = 0;
1da177e4
LT		 2418
2419 switch (topo) {
2420 case 0:
7c3df132 2421 ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n");
1da177e4
LT		 2422 ha->current_topology = ISP_CFG_NL;
2423 strcpy(connect_type, "(Loop)");
2424 break;
2425
2426 case 1:
7c3df132 2427 ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n");
2c3dfe3f 2428 ha->switch_cap = sw_cap;
1da177e4
LT		 2429 ha->current_topology = ISP_CFG_FL;
2430 strcpy(connect_type, "(FL_Port)");
2431 break;
2432
2433 case 2:
7c3df132 2434 ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n");
1da177e4
LT		 2435 ha->operating_mode = P2P;
2436 ha->current_topology = ISP_CFG_N;
2437 strcpy(connect_type, "(N_Port-to-N_Port)");
2438 break;
2439
2440 case 3:
7c3df132 2441 ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n");
2c3dfe3f 2442 ha->switch_cap = sw_cap;
1da177e4
LT		 2443 ha->operating_mode = P2P;
2444 ha->current_topology = ISP_CFG_F;
2445 strcpy(connect_type, "(F_Port)");
2446 break;
2447
2448 default:
7c3df132
SK		 2449 ql_dbg(ql_dbg_disc, vha, 0x200f,
2450 "HBA in unknown topology %x, using NL.\n", topo);
1da177e4
LT		 2451 ha->current_topology = ISP_CFG_NL;
2452 strcpy(connect_type, "(Loop)");
2453 break;
2454 }
2455
2456 /* Save Host port and loop ID. */
2457 /* byte order - Big Endian */
e315cd28
AC		 2458 vha->d_id.b.domain = domain;
2459 vha->d_id.b.area = area;
2460 vha->d_id.b.al_pa = al_pa;
1da177e4 2461
f24b5cb8 2462 spin_lock_irqsave(&ha->vport_slock, flags);
2d70c103 2463 qlt_update_vp_map(vha, SET_AL_PA);
f24b5cb8 2464 spin_unlock_irqrestore(&ha->vport_slock, flags);
2d70c103 2465
e315cd28 2466 if (!vha->flags.init_done)
7c3df132
SK		 2467 ql_log(ql_log_info, vha, 0x2010,
2468 "Topology - %s, Host Loop address 0x%x.\n",
e315cd28 2469 connect_type, vha->loop_id);
1da177e4 2470
1da177e4
LT		 2471 return(rval);
2472}
2473
a9083016 2474inline void
e315cd28
AC		 2475qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
2476 char *def)
9bb9fcf2
AV		 2477{
2478 char *st, *en;
2479 uint16_t index;
e315cd28 2480 struct qla_hw_data *ha = vha->hw;
ab671149 2481 int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
6246b8a1 2482 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha);
9bb9fcf2
AV		 2483
2484 if (memcmp(model, BINZERO, len) != 0) {
2485 strncpy(ha->model_number, model, len);
2486 st = en = ha->model_number;
2487 en += len - 1;
2488 while (en > st) {
2489 if (*en != 0x20 && *en != 0x00)
2490 break;
2491 *en-- = '\0';
2492 }
2493
2494 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 2495 if (use_tbl &&
2496 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2 2497 index < QLA_MODEL_NAMES)
1ee27146
JC		 2498 strncpy(ha->model_desc,
2499 qla2x00_model_name[index * 2 + 1],
2500 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 2501 } else {
2502 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 2503 if (use_tbl &&
2504 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2
AV		 2505 index < QLA_MODEL_NAMES) {
2506 strcpy(ha->model_number,
2507 qla2x00_model_name[index * 2]);
1ee27146
JC		 2508 strncpy(ha->model_desc,
2509 qla2x00_model_name[index * 2 + 1],
2510 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 2511 } else {
2512 strcpy(ha->model_number, def);
2513 }
2514 }
1ee27146 2515 if (IS_FWI2_CAPABLE(ha))
e315cd28 2516 qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc,
1ee27146 2517 sizeof(ha->model_desc));
9bb9fcf2
AV		 2518}
2519
4e08df3f
DM		 2520/* On sparc systems, obtain port and node WWN from firmware
2521 * properties.
2522 */
e315cd28 2523static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv)
4e08df3f
DM		 2524{
2525#ifdef CONFIG_SPARC
e315cd28 2526 struct qla_hw_data *ha = vha->hw;
4e08df3f 2527 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 2528 struct device_node *dp = pci_device_to_OF_node(pdev);
2529 const u8 *val;
4e08df3f
DM		 2530 int len;
2531
2532 val = of_get_property(dp, "port-wwn", &len);
2533 if (val && len >= WWN_SIZE)
2534 memcpy(nv->port_name, val, WWN_SIZE);
2535
2536 val = of_get_property(dp, "node-wwn", &len);
2537 if (val && len >= WWN_SIZE)
2538 memcpy(nv->node_name, val, WWN_SIZE);
2539#endif
2540}
2541
1da177e4
LT		 2542/*
2543* NVRAM configuration for ISP 2xxx
2544*
2545* Input:
2546* ha = adapter block pointer.
2547*
2548* Output:
2549* initialization control block in response_ring
2550* host adapters parameters in host adapter block
2551*
2552* Returns:
2553* 0 = success.
2554*/
abbd8870 2555int
e315cd28 2556qla2x00_nvram_config(scsi_qla_host_t *vha)
1da177e4 2557{
4e08df3f 2558 int rval;
0107109e
AV		 2559 uint8_t chksum = 0;
2560 uint16_t cnt;
2561 uint8_t *dptr1, *dptr2;
e315cd28 2562 struct qla_hw_data *ha = vha->hw;
0107109e 2563 init_cb_t *icb = ha->init_cb;
281afe19
SJ		 2564 nvram_t *nv = ha->nvram;
2565 uint8_t *ptr = ha->nvram;
3d71644c 2566 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 2567
4e08df3f
DM		 2568 rval = QLA_SUCCESS;
2569
1da177e4 2570 /* Determine NVRAM starting address. */
0107109e 2571 ha->nvram_size = sizeof(nvram_t);
1da177e4
LT		 2572 ha->nvram_base = 0;
2573 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
2574 if ((RD_REG_WORD(&reg->ctrl_status) >> 14) == 1)
2575 ha->nvram_base = 0x80;
2576
2577 /* Get NVRAM data and calculate checksum. */
e315cd28 2578 ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size);
0107109e
AV		 2579 for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++)
2580 chksum += *ptr++;
1da177e4 2581
7c3df132
SK		 2582 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
2583 "Contents of NVRAM.\n");
2584 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
2585 (uint8_t *)nv, ha->nvram_size);
1da177e4
LT		 2586
2587 /* Bad NVRAM data, set defaults parameters. */
2588 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' ||
2589 nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) {
2590 /* Reset NVRAM data. */
7c3df132 2591 ql_log(ql_log_warn, vha, 0x0064,
9e336520 2592 "Inconsistent NVRAM "
7c3df132
SK		 2593 "detected: checksum=0x%x id=%c version=0x%x.\n",
2594 chksum, nv->id[0], nv->nvram_version);
2595 ql_log(ql_log_warn, vha, 0x0065,
2596 "Falling back to "
2597 "functioning (yet invalid -- WWPN) defaults.\n");
4e08df3f
DM		 2598
2599 /*
2600 * Set default initialization control block.
2601 */
2602 memset(nv, 0, ha->nvram_size);
2603 nv->parameter_block_version = ICB_VERSION;
2604
2605 if (IS_QLA23XX(ha)) {
2606 nv->firmware_options[0] = BIT_2 | BIT_1;
2607 nv->firmware_options[1] = BIT_7 | BIT_5;
2608 nv->add_firmware_options[0] = BIT_5;
2609 nv->add_firmware_options[1] = BIT_5 | BIT_4;
98aee70d 2610 nv->frame_payload_size = 2048;
4e08df3f
DM		 2611 nv->special_options[1] = BIT_7;
2612 } else if (IS_QLA2200(ha)) {
2613 nv->firmware_options[0] = BIT_2 | BIT_1;
2614 nv->firmware_options[1] = BIT_7 | BIT_5;
2615 nv->add_firmware_options[0] = BIT_5;
2616 nv->add_firmware_options[1] = BIT_5 | BIT_4;
98aee70d 2617 nv->frame_payload_size = 1024;
4e08df3f
DM		 2618 } else if (IS_QLA2100(ha)) {
2619 nv->firmware_options[0] = BIT_3 | BIT_1;
2620 nv->firmware_options[1] = BIT_5;
98aee70d 2621 nv->frame_payload_size = 1024;
4e08df3f
DM		 2622 }
2623
2624 nv->max_iocb_allocation = __constant_cpu_to_le16(256);
2625 nv->execution_throttle = __constant_cpu_to_le16(16);
2626 nv->retry_count = 8;
2627 nv->retry_delay = 1;
2628
2629 nv->port_name[0] = 33;
2630 nv->port_name[3] = 224;
2631 nv->port_name[4] = 139;
2632
e315cd28 2633 qla2xxx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 2634
2635 nv->login_timeout = 4;
2636
2637 /*
2638 * Set default host adapter parameters
2639 */
2640 nv->host_p[1] = BIT_2;
2641 nv->reset_delay = 5;
2642 nv->port_down_retry_count = 8;
2643 nv->max_luns_per_target = __constant_cpu_to_le16(8);
2644 nv->link_down_timeout = 60;
2645
2646 rval = 1;
1da177e4
LT		 2647 }
2648
2649#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
2650 /*
2651 * The SN2 does not provide BIOS emulation which means you can't change
2652 * potentially bogus BIOS settings. Force the use of default settings
2653 * for link rate and frame size. Hope that the rest of the settings
2654 * are valid.
2655 */
2656 if (ia64_platform_is("sn2")) {
98aee70d 2657 nv->frame_payload_size = 2048;
1da177e4
LT		 2658 if (IS_QLA23XX(ha))
2659 nv->special_options[1] = BIT_7;
2660 }
2661#endif
2662
2663 /* Reset Initialization control block */
0107109e 2664 memset(icb, 0, ha->init_cb_size);
1da177e4
LT		 2665
2666 /*
2667 * Setup driver NVRAM options.
2668 */
2669 nv->firmware_options[0] |= (BIT_6 | BIT_1);
2670 nv->firmware_options[0] &= ~(BIT_5 | BIT_4);
2671 nv->firmware_options[1] |= (BIT_5 | BIT_0);
2672 nv->firmware_options[1] &= ~BIT_4;
2673
2674 if (IS_QLA23XX(ha)) {
2675 nv->firmware_options[0] |= BIT_2;
2676 nv->firmware_options[0] &= ~BIT_3;
2d70c103 2677 nv->special_options[0] &= ~BIT_6;
0107109e 2678 nv->add_firmware_options[1] |= BIT_5 | BIT_4;
1da177e4
LT		 2679
2680 if (IS_QLA2300(ha)) {
2681 if (ha->fb_rev == FPM_2310) {
2682 strcpy(ha->model_number, "QLA2310");
2683 } else {
2684 strcpy(ha->model_number, "QLA2300");
2685 }
2686 } else {
e315cd28 2687 qla2x00_set_model_info(vha, nv->model_number,
9bb9fcf2 2688 sizeof(nv->model_number), "QLA23xx");
1da177e4
LT		 2689 }
2690 } else if (IS_QLA2200(ha)) {
2691 nv->firmware_options[0] |= BIT_2;
2692 /*
2693 * 'Point-to-point preferred, else loop' is not a safe
2694 * connection mode setting.
2695 */
2696 if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
2697 (BIT_5 | BIT_4)) {
2698 /* Force 'loop preferred, else point-to-point'. */
2699 nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
2700 nv->add_firmware_options[0] |= BIT_5;
2701 }
2702 strcpy(ha->model_number, "QLA22xx");
2703 } else /*if (IS_QLA2100(ha))*/ {
2704 strcpy(ha->model_number, "QLA2100");
2705 }
2706
2707 /*
2708 * Copy over NVRAM RISC parameter block to initialization control block.
2709 */
2710 dptr1 = (uint8_t *)icb;
2711 dptr2 = (uint8_t *)&nv->parameter_block_version;
2712 cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;
2713 while (cnt--)
2714 *dptr1++ = *dptr2++;
2715
2716 /* Copy 2nd half. */
2717 dptr1 = (uint8_t *)icb->add_firmware_options;
2718 cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;
2719 while (cnt--)
2720 *dptr1++ = *dptr2++;
2721
5341e868
AV		 2722 /* Use alternate WWN? */
2723 if (nv->host_p[1] & BIT_7) {
2724 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
2725 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
2726 }
2727
1da177e4
LT		 2728 /* Prepare nodename */
2729 if ((icb->firmware_options[1] & BIT_6) == 0) {
2730 /*
2731 * Firmware will apply the following mask if the nodename was
2732 * not provided.
2733 */
2734 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
2735 icb->node_name[0] &= 0xF0;
2736 }
2737
2738 /*
2739 * Set host adapter parameters.
2740 */
3ce8866c
SK		 2741
2742 /*
2743 * BIT_7 in the host-parameters section allows for modification to
2744 * internal driver logging.
2745 */
0181944f 2746 if (nv->host_p[0] & BIT_7)
cfb0919c 2747 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
1da177e4
LT		 2748 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
2749 /* Always load RISC code on non ISP2[12]00 chips. */
2750 if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
2751 ha->flags.disable_risc_code_load = 0;
2752 ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0);
2753 ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
2754 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
06c22bd1 2755 ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
d4c760c2 2756 ha->flags.disable_serdes = 0;
1da177e4
LT		 2757
2758 ha->operating_mode =
2759 (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
2760
2761 memcpy(ha->fw_seriallink_options, nv->seriallink_options,
2762 sizeof(ha->fw_seriallink_options));
2763
2764 /* save HBA serial number */
2765 ha->serial0 = icb->port_name[5];
2766 ha->serial1 = icb->port_name[6];
2767 ha->serial2 = icb->port_name[7];
e315cd28
AC		 2768 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
2769 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
1da177e4
LT		 2770
2771 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
2772
2773 ha->retry_count = nv->retry_count;
2774
2775 /* Set minimum login_timeout to 4 seconds. */
5b91490e 2776 if (nv->login_timeout != ql2xlogintimeout)
1da177e4
LT		 2777 nv->login_timeout = ql2xlogintimeout;
2778 if (nv->login_timeout < 4)
2779 nv->login_timeout = 4;
2780 ha->login_timeout = nv->login_timeout;
2781 icb->login_timeout = nv->login_timeout;
2782
00a537b8
AV		 2783 /* Set minimum RATOV to 100 tenths of a second. */
2784 ha->r_a_tov = 100;
1da177e4 2785
1da177e4
LT		 2786 ha->loop_reset_delay = nv->reset_delay;
2787
1da177e4
LT		 2788 /* Link Down Timeout = 0:
2789 *
2790 * When Port Down timer expires we will start returning
2791 * I/O's to OS with "DID_NO_CONNECT".
2792 *
2793 * Link Down Timeout != 0:
2794 *
2795 * The driver waits for the link to come up after link down
2796 * before returning I/Os to OS with "DID_NO_CONNECT".
fa2a1ce5 2797 */
1da177e4
LT		 2798 if (nv->link_down_timeout == 0) {
2799 ha->loop_down_abort_time =
354d6b21 2800 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
1da177e4
LT		 2801 } else {
2802 ha->link_down_timeout = nv->link_down_timeout;
2803 ha->loop_down_abort_time =
2804 (LOOP_DOWN_TIME - ha->link_down_timeout);
fa2a1ce5 2805 }
1da177e4 2806
1da177e4
LT		 2807 /*
2808 * Need enough time to try and get the port back.
2809 */
2810 ha->port_down_retry_count = nv->port_down_retry_count;
2811 if (qlport_down_retry)
2812 ha->port_down_retry_count = qlport_down_retry;
2813 /* Set login_retry_count */
2814 ha->login_retry_count = nv->retry_count;
2815 if (ha->port_down_retry_count == nv->port_down_retry_count &&
2816 ha->port_down_retry_count > 3)
2817 ha->login_retry_count = ha->port_down_retry_count;
2818 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
2819 ha->login_retry_count = ha->port_down_retry_count;
2820 if (ql2xloginretrycount)
2821 ha->login_retry_count = ql2xloginretrycount;
2822
1da177e4
LT		 2823 icb->lun_enables = __constant_cpu_to_le16(0);
2824 icb->command_resource_count = 0;
2825 icb->immediate_notify_resource_count = 0;
2826 icb->timeout = __constant_cpu_to_le16(0);
2827
2828 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
2829 /* Enable RIO */
2830 icb->firmware_options[0] &= ~BIT_3;
2831 icb->add_firmware_options[0] &=
2832 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
2833 icb->add_firmware_options[0] |= BIT_2;
2834 icb->response_accumulation_timer = 3;
2835 icb->interrupt_delay_timer = 5;
2836
e315cd28 2837 vha->flags.process_response_queue = 1;
1da177e4 2838 } else {
4fdfefe5 2839 /* Enable ZIO. */
e315cd28 2840 if (!vha->flags.init_done) {
4fdfefe5
AV		 2841 ha->zio_mode = icb->add_firmware_options[0] &
2842 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
2843 ha->zio_timer = icb->interrupt_delay_timer ?
2844 icb->interrupt_delay_timer: 2;
2845 }
1da177e4
LT		 2846 icb->add_firmware_options[0] &=
2847 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
e315cd28 2848 vha->flags.process_response_queue = 0;
4fdfefe5 2849 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d
AV		 2850 ha->zio_mode = QLA_ZIO_MODE_6;
2851
7c3df132 2852 ql_log(ql_log_info, vha, 0x0068,
4fdfefe5
AV		 2853 "ZIO mode %d enabled; timer delay (%d us).\n",
2854 ha->zio_mode, ha->zio_timer * 100);
1da177e4 2855
4fdfefe5
AV		 2856 icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;
2857 icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;
e315cd28 2858 vha->flags.process_response_queue = 1;
1da177e4
LT		 2859 }
2860 }
2861
4e08df3f 2862 if (rval) {
7c3df132
SK		 2863 ql_log(ql_log_warn, vha, 0x0069,
2864 "NVRAM configuration failed.\n");
4e08df3f
DM		 2865 }
2866 return (rval);
1da177e4
LT		 2867}
2868
19a7b4ae
JSEC		 2869static void
2870qla2x00_rport_del(void *data)
2871{
2872 fc_port_t *fcport = data;
d97994dc 2873 struct fc_rport *rport;
2d70c103 2874 scsi_qla_host_t *vha = fcport->vha;
044d78e1 2875 unsigned long flags;
d97994dc 2876
044d78e1 2877 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
ac280b67 2878 rport = fcport->drport ? fcport->drport: fcport->rport;
d97994dc 2879 fcport->drport = NULL;
044d78e1 2880 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
2d70c103 2881 if (rport) {
d97994dc 2882 fc_remote_port_delete(rport);
2d70c103
NB		 2883 /*
2884 * Release the target mode FC NEXUS in qla_target.c code
2885 * if target mod is enabled.
2886 */
2887 qlt_fc_port_deleted(vha, fcport);
2888 }
19a7b4ae
JSEC		 2889}
2890
1da177e4
LT		 2891/**
2892 * qla2x00_alloc_fcport() - Allocate a generic fcport.
2893 * @ha: HA context
2894 * @flags: allocation flags
2895 *
2896 * Returns a pointer to the allocated fcport, or NULL, if none available.
2897 */
9a069e19 2898fc_port_t *
e315cd28 2899qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags)
1da177e4
LT		 2900{
2901 fc_port_t *fcport;
2902
bbfbbbc1
MK		 2903 fcport = kzalloc(sizeof(fc_port_t), flags);
2904 if (!fcport)
2905 return NULL;
1da177e4
LT		 2906
2907 /* Setup fcport template structure. */
e315cd28 2908 fcport->vha = vha;
1da177e4
LT		 2909 fcport->port_type = FCT_UNKNOWN;
2910 fcport->loop_id = FC_NO_LOOP_ID;
ec426e10 2911 qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
ad3e0eda 2912 fcport->supported_classes = FC_COS_UNSPECIFIED;
1da177e4 2913
bbfbbbc1 2914 return fcport;
1da177e4
LT		 2915}
2916
2917/*
2918 * qla2x00_configure_loop
2919 * Updates Fibre Channel Device Database with what is actually on loop.
2920 *
2921 * Input:
2922 * ha = adapter block pointer.
2923 *
2924 * Returns:
2925 * 0 = success.
2926 * 1 = error.
2927 * 2 = database was full and device was not configured.
2928 */
2929static int
e315cd28 2930qla2x00_configure_loop(scsi_qla_host_t *vha)
1da177e4
LT		 2931{
2932 int rval;
2933 unsigned long flags, save_flags;
e315cd28 2934 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2935 rval = QLA_SUCCESS;
2936
2937 /* Get Initiator ID */
e315cd28
AC		 2938 if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) {
2939 rval = qla2x00_configure_hba(vha);
1da177e4 2940 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2941 ql_dbg(ql_dbg_disc, vha, 0x2013,
2942 "Unable to configure HBA.\n");
1da177e4
LT		 2943 return (rval);
2944 }
2945 }
2946
e315cd28 2947 save_flags = flags = vha->dpc_flags;
7c3df132
SK		 2948 ql_dbg(ql_dbg_disc, vha, 0x2014,
2949 "Configure loop -- dpc flags = 0x%lx.\n", flags);
1da177e4
LT		 2950
2951 /*
2952 * If we have both an RSCN and PORT UPDATE pending then handle them
2953 * both at the same time.
2954 */
e315cd28
AC		 2955 clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2956 clear_bit(RSCN_UPDATE, &vha->dpc_flags);
1da177e4 2957
3064ff39
MH		 2958 qla2x00_get_data_rate(vha);
2959
1da177e4
LT		 2960 /* Determine what we need to do */
2961 if (ha->current_topology == ISP_CFG_FL &&
2962 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
2963
1da177e4
LT		 2964 set_bit(RSCN_UPDATE, &flags);
2965
2966 } else if (ha->current_topology == ISP_CFG_F &&
2967 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
2968
1da177e4
LT		 2969 set_bit(RSCN_UPDATE, &flags);
2970 clear_bit(LOCAL_LOOP_UPDATE, &flags);
21333b48
AV		 2971
2972 } else if (ha->current_topology == ISP_CFG_N) {
2973 clear_bit(RSCN_UPDATE, &flags);
1da177e4 2974
e315cd28 2975 } else if (!vha->flags.online ||
1da177e4
LT		 2976 (test_bit(ABORT_ISP_ACTIVE, &flags))) {
2977
1da177e4
LT		 2978 set_bit(RSCN_UPDATE, &flags);
2979 set_bit(LOCAL_LOOP_UPDATE, &flags);
2980 }
2981
2982 if (test_bit(LOCAL_LOOP_UPDATE, &flags)) {
7c3df132
SK		 2983 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
2984 ql_dbg(ql_dbg_disc, vha, 0x2015,
2985 "Loop resync needed, failing.\n");
1da177e4 2986 rval = QLA_FUNCTION_FAILED;
642ef983 2987 } else
e315cd28 2988 rval = qla2x00_configure_local_loop(vha);
1da177e4
LT		 2989 }
2990
2991 if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
7c3df132
SK		 2992 if (LOOP_TRANSITION(vha)) {
2993 ql_dbg(ql_dbg_disc, vha, 0x201e,
2994 "Needs RSCN update and loop transition.\n");
1da177e4 2995 rval = QLA_FUNCTION_FAILED;
7c3df132 2996 }
e315cd28
AC		 2997 else
2998 rval = qla2x00_configure_fabric(vha);
1da177e4
LT		 2999 }
3000
3001 if (rval == QLA_SUCCESS) {
e315cd28
AC		 3002 if (atomic_read(&vha->loop_down_timer) ||
3003 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4
LT		 3004 rval = QLA_FUNCTION_FAILED;
3005 } else {
e315cd28 3006 atomic_set(&vha->loop_state, LOOP_READY);
7c3df132
SK		 3007 ql_dbg(ql_dbg_disc, vha, 0x2069,
3008 "LOOP READY.\n");
1da177e4
LT		 3009 }
3010 }
3011
3012 if (rval) {
7c3df132
SK		 3013 ql_dbg(ql_dbg_disc, vha, 0x206a,
3014 "%s *** FAILED ***.\n", __func__);
1da177e4 3015 } else {
7c3df132
SK		 3016 ql_dbg(ql_dbg_disc, vha, 0x206b,
3017 "%s: exiting normally.\n", __func__);
1da177e4
LT		 3018 }
3019
cc3ef7bc 3020 /* Restore state if a resync event occurred during processing */
e315cd28 3021 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4 3022 if (test_bit(LOCAL_LOOP_UPDATE, &save_flags))
e315cd28 3023 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
f4658b6c 3024 if (test_bit(RSCN_UPDATE, &save_flags)) {
e315cd28 3025 set_bit(RSCN_UPDATE, &vha->dpc_flags);
f4658b6c 3026 }
1da177e4
LT		 3027 }
3028
3029 return (rval);
3030}
3031
3032
3033
3034/*
3035 * qla2x00_configure_local_loop
3036 * Updates Fibre Channel Device Database with local loop devices.
3037 *
3038 * Input:
3039 * ha = adapter block pointer.
3040 *
3041 * Returns:
3042 * 0 = success.
3043 */
3044static int
e315cd28 3045qla2x00_configure_local_loop(scsi_qla_host_t *vha)
1da177e4
LT		 3046{
3047 int rval, rval2;
3048 int found_devs;
3049 int found;
3050 fc_port_t *fcport, *new_fcport;
3051
3052 uint16_t index;
3053 uint16_t entries;
3054 char *id_iter;
3055 uint16_t loop_id;
3056 uint8_t domain, area, al_pa;
e315cd28 3057 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3058
3059 found_devs = 0;
3060 new_fcport = NULL;
642ef983 3061 entries = MAX_FIBRE_DEVICES_LOOP;
1da177e4 3062
1da177e4 3063 /* Get list of logged in devices. */
642ef983 3064 memset(ha->gid_list, 0, qla2x00_gid_list_size(ha));
e315cd28 3065 rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma,
1da177e4
LT		 3066 &entries);
3067 if (rval != QLA_SUCCESS)
3068 goto cleanup_allocation;
3069
7c3df132
SK		 3070 ql_dbg(ql_dbg_disc, vha, 0x2017,
3071 "Entries in ID list (%d).\n", entries);
3072 ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
3073 (uint8_t *)ha->gid_list,
3074 entries * sizeof(struct gid_list_info));
1da177e4
LT		 3075
3076 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 3077 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3078 if (new_fcport == NULL) {
7c3df132
SK		 3079 ql_log(ql_log_warn, vha, 0x2018,
3080 "Memory allocation failed for fcport.\n");
1da177e4
LT		 3081 rval = QLA_MEMORY_ALLOC_FAILED;
3082 goto cleanup_allocation;
3083 }
3084 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
3085
3086 /*
3087 * Mark local devices that were present with FCF_DEVICE_LOST for now.
3088 */
e315cd28 3089 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 3090 if (atomic_read(&fcport->state) == FCS_ONLINE &&
3091 fcport->port_type != FCT_BROADCAST &&
3092 (fcport->flags & FCF_FABRIC_DEVICE) == 0) {
3093
7c3df132
SK		 3094 ql_dbg(ql_dbg_disc, vha, 0x2019,
3095 "Marking port lost loop_id=0x%04x.\n",
3096 fcport->loop_id);
1da177e4 3097
ec426e10 3098 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3099 }
3100 }
3101
3102 /* Add devices to port list. */
3103 id_iter = (char *)ha->gid_list;
3104 for (index = 0; index < entries; index++) {
3105 domain = ((struct gid_list_info *)id_iter)->domain;
3106 area = ((struct gid_list_info *)id_iter)->area;
3107 al_pa = ((struct gid_list_info *)id_iter)->al_pa;
abbd8870 3108 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1da177e4
LT		 3109 loop_id = (uint16_t)
3110 ((struct gid_list_info *)id_iter)->loop_id_2100;
abbd8870 3111 else
1da177e4
LT		 3112 loop_id = le16_to_cpu(
3113 ((struct gid_list_info *)id_iter)->loop_id);
abbd8870 3114 id_iter += ha->gid_list_info_size;
1da177e4
LT		 3115
3116 /* Bypass reserved domain fields. */
3117 if ((domain & 0xf0) == 0xf0)
3118 continue;
3119
3120 /* Bypass if not same domain and area of adapter. */
f7d289f6 3121 if (area && domain &&
e315cd28 3122 (area != vha->d_id.b.area || domain != vha->d_id.b.domain))
1da177e4
LT		 3123 continue;
3124
3125 /* Bypass invalid local loop ID. */
3126 if (loop_id > LAST_LOCAL_LOOP_ID)
3127 continue;
3128
370d550e
AE		 3129 memset(new_fcport, 0, sizeof(fc_port_t));
3130
1da177e4
LT		 3131 /* Fill in member data. */
3132 new_fcport->d_id.b.domain = domain;
3133 new_fcport->d_id.b.area = area;
3134 new_fcport->d_id.b.al_pa = al_pa;
3135 new_fcport->loop_id = loop_id;
e315cd28 3136 rval2 = qla2x00_get_port_database(vha, new_fcport, 0);
1da177e4 3137 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 3138 ql_dbg(ql_dbg_disc, vha, 0x201a,
3139 "Failed to retrieve fcport information "
3140 "-- get_port_database=%x, loop_id=0x%04x.\n",
3141 rval2, new_fcport->loop_id);
3142 ql_dbg(ql_dbg_disc, vha, 0x201b,
3143 "Scheduling resync.\n");
e315cd28 3144 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4
LT		 3145 continue;
3146 }
3147
3148 /* Check for matching device in port list. */
3149 found = 0;
3150 fcport = NULL;
e315cd28 3151 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 3152 if (memcmp(new_fcport->port_name, fcport->port_name,
3153 WWN_SIZE))
3154 continue;
3155
ddb9b126 3156 fcport->flags &= ~FCF_FABRIC_DEVICE;
1da177e4
LT		 3157 fcport->loop_id = new_fcport->loop_id;
3158 fcport->port_type = new_fcport->port_type;
3159 fcport->d_id.b24 = new_fcport->d_id.b24;
3160 memcpy(fcport->node_name, new_fcport->node_name,
3161 WWN_SIZE);
3162
3163 found++;
3164 break;
3165 }
3166
3167 if (!found) {
3168 /* New device, add to fcports list. */
e315cd28 3169 list_add_tail(&new_fcport->list, &vha->vp_fcports);
1da177e4
LT		 3170
3171 /* Allocate a new replacement fcport. */
3172 fcport = new_fcport;
e315cd28 3173 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3174 if (new_fcport == NULL) {
7c3df132
SK		 3175 ql_log(ql_log_warn, vha, 0x201c,
3176 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 3177 rval = QLA_MEMORY_ALLOC_FAILED;
3178 goto cleanup_allocation;
3179 }
3180 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
3181 }
3182
d8b45213 3183 /* Base iIDMA settings on HBA port speed. */
a3cbdfad 3184 fcport->fp_speed = ha->link_data_rate;
d8b45213 3185
e315cd28 3186 qla2x00_update_fcport(vha, fcport);
1da177e4
LT		 3187
3188 found_devs++;
3189 }
3190
3191cleanup_allocation:
c9475cb0 3192 kfree(new_fcport);
1da177e4
LT		 3193
3194 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3195 ql_dbg(ql_dbg_disc, vha, 0x201d,
3196 "Configure local loop error exit: rval=%x.\n", rval);
1da177e4
LT		 3197 }
3198
1da177e4
LT		 3199 return (rval);
3200}
3201
d8b45213 3202static void
e315cd28 3203qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
d8b45213 3204{
d8b45213 3205 int rval;
93f2bd67 3206 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 3207 struct qla_hw_data *ha = vha->hw;
d8b45213 3208
c76f2c01 3209 if (!IS_IIDMA_CAPABLE(ha))
d8b45213
AV		 3210 return;
3211
c9afb9a2
GM		 3212 if (atomic_read(&fcport->state) != FCS_ONLINE)
3213 return;
3214
39bd9622
AV		 3215 if (fcport->fp_speed == PORT_SPEED_UNKNOWN ||
3216 fcport->fp_speed > ha->link_data_rate)
d8b45213
AV		 3217 return;
3218
e315cd28 3219 rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed,
a3cbdfad 3220 mb);
d8b45213 3221 if (rval != QLA_SUCCESS) {
7c3df132 3222 ql_dbg(ql_dbg_disc, vha, 0x2004,
7b833558
OK		 3223 "Unable to adjust iIDMA %8phN -- %04x %x %04x %04x.\n",
3224 fcport->port_name, rval, fcport->fp_speed, mb[0], mb[1]);
d8b45213 3225 } else {
7c3df132 3226 ql_dbg(ql_dbg_disc, vha, 0x2005,
7b833558 3227 "iIDMA adjusted to %s GB/s on %8phN.\n",
d0297c9a 3228 qla2x00_get_link_speed_str(ha, fcport->fp_speed),
7b833558 3229 fcport->port_name);
d8b45213
AV		 3230 }
3231}
3232
23be331d 3233static void
e315cd28 3234qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport)
8482e118
AV		 3235{
3236 struct fc_rport_identifiers rport_ids;
bdf79621 3237 struct fc_rport *rport;
044d78e1 3238 unsigned long flags;
8482e118 3239
f8b02a85
AV		 3240 rport_ids.node_name = wwn_to_u64(fcport->node_name);
3241 rport_ids.port_name = wwn_to_u64(fcport->port_name);
8482e118
AV		 3242 rport_ids.port_id = fcport->d_id.b.domain << 16 |
3243 fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa;
77d74143 3244 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
e315cd28 3245 fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids);
77d74143 3246 if (!rport) {
7c3df132
SK		 3247 ql_log(ql_log_warn, vha, 0x2006,
3248 "Unable to allocate fc remote port.\n");
77d74143
AV		 3249 return;
3250 }
2d70c103
NB		 3251 /*
3252 * Create target mode FC NEXUS in qla_target.c if target mode is
3253 * enabled..
3254 */
3255 qlt_fc_port_added(vha, fcport);
3256
044d78e1 3257 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
19a7b4ae 3258 *((fc_port_t **)rport->dd_data) = fcport;
044d78e1 3259 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
d97994dc 3260
ad3e0eda 3261 rport->supported_classes = fcport->supported_classes;
77d74143 3262
8482e118
AV		 3263 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
3264 if (fcport->port_type == FCT_INITIATOR)
3265 rport_ids.roles |= FC_RPORT_ROLE_FCP_INITIATOR;
3266 if (fcport->port_type == FCT_TARGET)
3267 rport_ids.roles |= FC_RPORT_ROLE_FCP_TARGET;
77d74143 3268 fc_remote_port_rolechg(rport, rport_ids.roles);
1da177e4
LT		 3269}
3270
23be331d
AB		 3271/*
3272 * qla2x00_update_fcport
3273 * Updates device on list.
3274 *
3275 * Input:
3276 * ha = adapter block pointer.
3277 * fcport = port structure pointer.
3278 *
3279 * Return:
3280 * 0 - Success
3281 * BIT_0 - error
3282 *
3283 * Context:
3284 * Kernel context.
3285 */
3286void
e315cd28 3287qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
23be331d 3288{
e315cd28 3289 fcport->vha = vha;
8ae6d9c7
GM		 3290
3291 if (IS_QLAFX00(vha->hw)) {
3292 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
3293 qla2x00_reg_remote_port(vha, fcport);
3294 return;
3295 }
23be331d 3296 fcport->login_retry = 0;
5ff1d584 3297 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
23be331d 3298
1f93da52 3299 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
e315cd28 3300 qla2x00_iidma_fcport(vha, fcport);
21090cbe 3301 qla24xx_update_fcport_fcp_prio(vha, fcport);
e315cd28 3302 qla2x00_reg_remote_port(vha, fcport);
23be331d
AB		 3303}
3304
1da177e4
LT		 3305/*
3306 * qla2x00_configure_fabric
3307 * Setup SNS devices with loop ID's.
3308 *
3309 * Input:
3310 * ha = adapter block pointer.
3311 *
3312 * Returns:
3313 * 0 = success.
3314 * BIT_0 = error
3315 */
3316static int
e315cd28 3317qla2x00_configure_fabric(scsi_qla_host_t *vha)
1da177e4 3318{
b3b02e6e 3319 int rval;
e452ceb6 3320 fc_port_t *fcport, *fcptemp;
1da177e4
LT		 3321 uint16_t next_loopid;
3322 uint16_t mb[MAILBOX_REGISTER_COUNT];
0107109e 3323 uint16_t loop_id;
1da177e4 3324 LIST_HEAD(new_fcports);
e315cd28
AC		 3325 struct qla_hw_data *ha = vha->hw;
3326 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 3327
3328 /* If FL port exists, then SNS is present */
e428924c 3329 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 3330 loop_id = NPH_F_PORT;
3331 else
3332 loop_id = SNS_FL_PORT;
e315cd28 3333 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1);
1da177e4 3334 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3335 ql_dbg(ql_dbg_disc, vha, 0x201f,
3336 "MBX_GET_PORT_NAME failed, No FL Port.\n");
1da177e4 3337
e315cd28 3338 vha->device_flags &= ~SWITCH_FOUND;
1da177e4
LT		 3339 return (QLA_SUCCESS);
3340 }
e315cd28 3341 vha->device_flags |= SWITCH_FOUND;
1da177e4 3342
1da177e4 3343 do {
cca5335c
AV		 3344 /* FDMI support. */
3345 if (ql2xfdmienable &&
e315cd28
AC		 3346 test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags))
3347 qla2x00_fdmi_register(vha);
cca5335c 3348
1da177e4 3349 /* Ensure we are logged into the SNS. */
e428924c 3350 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 3351 loop_id = NPH_SNS;
3352 else
3353 loop_id = SIMPLE_NAME_SERVER;
0b91d116
CD		 3354 rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff,
3355 0xfc, mb, BIT_1|BIT_0);
3356 if (rval != QLA_SUCCESS) {
3357 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
e452ceb6 3358 return rval;
0b91d116 3359 }
1da177e4 3360 if (mb[0] != MBS_COMMAND_COMPLETE) {
7c3df132
SK		 3361 ql_dbg(ql_dbg_disc, vha, 0x2042,
3362 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x "
3363 "mb[6]=%x mb[7]=%x.\n", loop_id, mb[0], mb[1],
3364 mb[2], mb[6], mb[7]);
1da177e4
LT		 3365 return (QLA_SUCCESS);
3366 }
3367
e315cd28
AC		 3368 if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) {
3369 if (qla2x00_rft_id(vha)) {
1da177e4 3370 /* EMPTY */
7c3df132
SK		 3371 ql_dbg(ql_dbg_disc, vha, 0x2045,
3372 "Register FC-4 TYPE failed.\n");
1da177e4 3373 }
e315cd28 3374 if (qla2x00_rff_id(vha)) {
1da177e4 3375 /* EMPTY */
7c3df132
SK		 3376 ql_dbg(ql_dbg_disc, vha, 0x2049,
3377 "Register FC-4 Features failed.\n");
1da177e4 3378 }
e315cd28 3379 if (qla2x00_rnn_id(vha)) {
1da177e4 3380 /* EMPTY */
7c3df132
SK		 3381 ql_dbg(ql_dbg_disc, vha, 0x204f,
3382 "Register Node Name failed.\n");
e315cd28 3383 } else if (qla2x00_rsnn_nn(vha)) {
1da177e4 3384 /* EMPTY */
7c3df132
SK		 3385 ql_dbg(ql_dbg_disc, vha, 0x2053,
3386 "Register Symobilic Node Name failed.\n");
1da177e4
LT		 3387 }
3388 }
3389
827210ba
JC		 3390#define QLA_FCPORT_SCAN 1
3391#define QLA_FCPORT_FOUND 2
3392
3393 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3394 fcport->scan_state = QLA_FCPORT_SCAN;
3395 }
3396
e315cd28 3397 rval = qla2x00_find_all_fabric_devs(vha, &new_fcports);
1da177e4
LT		 3398 if (rval != QLA_SUCCESS)
3399 break;
3400
e452ceb6
JC		 3401 /*
3402 * Logout all previous fabric devices marked lost, except
3403 * FCP2 devices.
3404 */
e315cd28
AC		 3405 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3406 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
1da177e4
LT		 3407 break;
3408
3409 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0)
3410 continue;
3411
827210ba 3412 if (fcport->scan_state == QLA_FCPORT_SCAN &&
b3b02e6e 3413 atomic_read(&fcport->state) == FCS_ONLINE) {
e315cd28 3414 qla2x00_mark_device_lost(vha, fcport,
d97994dc 3415 ql2xplogiabsentdevice, 0);
1da177e4 3416 if (fcport->loop_id != FC_NO_LOOP_ID &&
f08b7251 3417 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
1da177e4
LT		 3418 fcport->port_type != FCT_INITIATOR &&
3419 fcport->port_type != FCT_BROADCAST) {
e315cd28 3420 ha->isp_ops->fabric_logout(vha,
1c7c6357
AV		 3421 fcport->loop_id,
3422 fcport->d_id.b.domain,
3423 fcport->d_id.b.area,
3424 fcport->d_id.b.al_pa);
1a5c69bf 3425 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 3426 }
3427 }
e452ceb6 3428 }
1da177e4 3429
e452ceb6
JC		 3430 /* Starting free loop ID. */
3431 next_loopid = ha->min_external_loopid;
3432
3433 /*
3434 * Scan through our port list and login entries that need to be
3435 * logged in.
3436 */
3437 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3438 if (atomic_read(&vha->loop_down_timer) ||
3439 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3440 break;
3441
3442 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0 ||
3443 (fcport->flags & FCF_LOGIN_NEEDED) == 0)
3444 continue;
3445
3446 if (fcport->loop_id == FC_NO_LOOP_ID) {
3447 fcport->loop_id = next_loopid;
3448 rval = qla2x00_find_new_loop_id(
3449 base_vha, fcport);
3450 if (rval != QLA_SUCCESS) {
3451 /* Ran out of IDs to use */
3452 break;
1da177e4
LT		 3453 }
3454 }
e452ceb6
JC		 3455 /* Login and update database */
3456 qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
3457 }
3458
3459 /* Exit if out of loop IDs. */
3460 if (rval != QLA_SUCCESS) {
3461 break;
3462 }
3463
3464 /*
3465 * Login and add the new devices to our port list.
3466 */
3467 list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) {
3468 if (atomic_read(&vha->loop_down_timer) ||
3469 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3470 break;
3471
3472 /* Find a new loop ID to use. */
3473 fcport->loop_id = next_loopid;
3474 rval = qla2x00_find_new_loop_id(base_vha, fcport);
3475 if (rval != QLA_SUCCESS) {
3476 /* Ran out of IDs to use */
3477 break;
3478 }
1da177e4 3479
bdf79621 3480 /* Login and update database */
e315cd28 3481 qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
e452ceb6
JC		 3482
3483 list_move_tail(&fcport->list, &vha->vp_fcports);
1da177e4
LT		 3484 }
3485 } while (0);
3486
e452ceb6
JC		 3487 /* Free all new device structures not processed. */
3488 list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) {
3489 list_del(&fcport->list);
3490 kfree(fcport);
3491 }
3492
1da177e4 3493 if (rval) {
7c3df132
SK		 3494 ql_dbg(ql_dbg_disc, vha, 0x2068,
3495 "Configure fabric error exit rval=%d.\n", rval);
1da177e4
LT		 3496 }
3497
3498 return (rval);
3499}
3500
1da177e4
LT		 3501/*
3502 * qla2x00_find_all_fabric_devs
3503 *
3504 * Input:
3505 * ha = adapter block pointer.
3506 * dev = database device entry pointer.
3507 *
3508 * Returns:
3509 * 0 = success.
3510 *
3511 * Context:
3512 * Kernel context.
3513 */
3514static int
e315cd28
AC		 3515qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha,
3516 struct list_head *new_fcports)
1da177e4
LT		 3517{
3518 int rval;
3519 uint16_t loop_id;
3520 fc_port_t *fcport, *new_fcport, *fcptemp;
3521 int found;
3522
3523 sw_info_t *swl;
3524 int swl_idx;
3525 int first_dev, last_dev;
1516ef44 3526 port_id_t wrap = {}, nxt_d_id;
e315cd28 3527 struct qla_hw_data *ha = vha->hw;
bb4cf5b7 3528 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 3529
3530 rval = QLA_SUCCESS;
3531
3532 /* Try GID_PT to get device list, else GAN. */
7a67735b 3533 if (!ha->swl)
642ef983 3534 ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t),
7a67735b
AV		 3535 GFP_KERNEL);
3536 swl = ha->swl;
bbfbbbc1 3537 if (!swl) {
1da177e4 3538 /*EMPTY*/
7c3df132
SK		 3539 ql_dbg(ql_dbg_disc, vha, 0x2054,
3540 "GID_PT allocations failed, fallback on GA_NXT.\n");
1da177e4 3541 } else {
642ef983 3542 memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t));
e315cd28 3543 if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) {
1da177e4 3544 swl = NULL;
e315cd28 3545 } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 3546 swl = NULL;
e315cd28 3547 } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 3548 swl = NULL;
e5896bd5 3549 } else if (ql2xiidmaenable &&
e315cd28
AC		 3550 qla2x00_gfpn_id(vha, swl) == QLA_SUCCESS) {
3551 qla2x00_gpsc(vha, swl);
1da177e4 3552 }
e8c72ba5
CD		 3553
3554 /* If other queries succeeded probe for FC-4 type */
3555 if (swl)
3556 qla2x00_gff_id(vha, swl);
1da177e4
LT		 3557 }
3558 swl_idx = 0;
3559
3560 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 3561 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3562 if (new_fcport == NULL) {
7c3df132
SK		 3563 ql_log(ql_log_warn, vha, 0x205e,
3564 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 3565 return (QLA_MEMORY_ALLOC_FAILED);
3566 }
3567 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
1da177e4
LT		 3568 /* Set start port ID scan at adapter ID. */
3569 first_dev = 1;
3570 last_dev = 0;
3571
3572 /* Starting free loop ID. */
e315cd28
AC		 3573 loop_id = ha->min_external_loopid;
3574 for (; loop_id <= ha->max_loop_id; loop_id++) {
3575 if (qla2x00_is_reserved_id(vha, loop_id))
1da177e4
LT		 3576 continue;
3577
3a6478df
GM		 3578 if (ha->current_topology == ISP_CFG_FL &&
3579 (atomic_read(&vha->loop_down_timer) ||
3580 LOOP_TRANSITION(vha))) {
bb2d52b2
AV		 3581 atomic_set(&vha->loop_down_timer, 0);
3582 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
3583 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
1da177e4 3584 break;
bb2d52b2 3585 }
1da177e4
LT		 3586
3587 if (swl != NULL) {
3588 if (last_dev) {
3589 wrap.b24 = new_fcport->d_id.b24;
3590 } else {
3591 new_fcport->d_id.b24 = swl[swl_idx].d_id.b24;
3592 memcpy(new_fcport->node_name,
3593 swl[swl_idx].node_name, WWN_SIZE);
3594 memcpy(new_fcport->port_name,
3595 swl[swl_idx].port_name, WWN_SIZE);
d8b45213
AV		 3596 memcpy(new_fcport->fabric_port_name,
3597 swl[swl_idx].fabric_port_name, WWN_SIZE);
3598 new_fcport->fp_speed = swl[swl_idx].fp_speed;
e8c72ba5 3599 new_fcport->fc4_type = swl[swl_idx].fc4_type;
1da177e4
LT		 3600
3601 if (swl[swl_idx].d_id.b.rsvd_1 != 0) {
3602 last_dev = 1;
3603 }
3604 swl_idx++;
3605 }
3606 } else {
3607 /* Send GA_NXT to the switch */
e315cd28 3608 rval = qla2x00_ga_nxt(vha, new_fcport);
1da177e4 3609 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3610 ql_log(ql_log_warn, vha, 0x2064,
3611 "SNS scan failed -- assuming "
3612 "zero-entry result.\n");
1da177e4
LT		 3613 list_for_each_entry_safe(fcport, fcptemp,
3614 new_fcports, list) {
3615 list_del(&fcport->list);
3616 kfree(fcport);
3617 }
3618 rval = QLA_SUCCESS;
3619 break;
3620 }
3621 }
3622
3623 /* If wrap on switch device list, exit. */
3624 if (first_dev) {
3625 wrap.b24 = new_fcport->d_id.b24;
3626 first_dev = 0;
3627 } else if (new_fcport->d_id.b24 == wrap.b24) {
7c3df132
SK		 3628 ql_dbg(ql_dbg_disc, vha, 0x2065,
3629 "Device wrap (%02x%02x%02x).\n",
3630 new_fcport->d_id.b.domain,
3631 new_fcport->d_id.b.area,
3632 new_fcport->d_id.b.al_pa);
1da177e4
LT		 3633 break;
3634 }
3635
2c3dfe3f 3636 /* Bypass if same physical adapter. */
e315cd28 3637 if (new_fcport->d_id.b24 == base_vha->d_id.b24)
1da177e4
LT		 3638 continue;
3639
2c3dfe3f 3640 /* Bypass virtual ports of the same host. */
bb4cf5b7
CD		 3641 if (qla2x00_is_a_vp_did(vha, new_fcport->d_id.b24))
3642 continue;
2c3dfe3f 3643
f7d289f6
AV		 3644 /* Bypass if same domain and area of adapter. */
3645 if (((new_fcport->d_id.b24 & 0xffff00) ==
e315cd28 3646 (vha->d_id.b24 & 0xffff00)) && ha->current_topology ==
f7d289f6
AV		 3647 ISP_CFG_FL)
3648 continue;
3649
1da177e4
LT		 3650 /* Bypass reserved domain fields. */
3651 if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0)
3652 continue;
3653
e8c72ba5 3654 /* Bypass ports whose FCP-4 type is not FCP_SCSI */
4da26e16
CD		 3655 if (ql2xgffidenable &&
3656 (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI &&
3657 new_fcport->fc4_type != FC4_TYPE_UNKNOWN))
e8c72ba5
CD		 3658 continue;
3659
1da177e4
LT		 3660 /* Locate matching device in database. */
3661 found = 0;
e315cd28 3662 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 3663 if (memcmp(new_fcport->port_name, fcport->port_name,
3664 WWN_SIZE))
3665 continue;
3666
827210ba 3667 fcport->scan_state = QLA_FCPORT_FOUND;
b3b02e6e 3668
1da177e4
LT		 3669 found++;
3670
d8b45213
AV		 3671 /* Update port state. */
3672 memcpy(fcport->fabric_port_name,
3673 new_fcport->fabric_port_name, WWN_SIZE);
3674 fcport->fp_speed = new_fcport->fp_speed;
3675
1da177e4
LT		 3676 /*
3677 * If address the same and state FCS_ONLINE, nothing
3678 * changed.
3679 */
3680 if (fcport->d_id.b24 == new_fcport->d_id.b24 &&
3681 atomic_read(&fcport->state) == FCS_ONLINE) {
3682 break;
3683 }
3684
3685 /*
3686 * If device was not a fabric device before.
3687 */
3688 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) {
3689 fcport->d_id.b24 = new_fcport->d_id.b24;
5f16b331 3690 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 3691 fcport->flags |= (FCF_FABRIC_DEVICE |
3692 FCF_LOGIN_NEEDED);
1da177e4
LT		 3693 break;
3694 }
3695
3696 /*
3697 * Port ID changed or device was marked to be updated;
3698 * Log it out if still logged in and mark it for
3699 * relogin later.
3700 */
3701 fcport->d_id.b24 = new_fcport->d_id.b24;
3702 fcport->flags |= FCF_LOGIN_NEEDED;
3703 if (fcport->loop_id != FC_NO_LOOP_ID &&
f08b7251 3704 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
0eba25df 3705 (fcport->flags & FCF_ASYNC_SENT) == 0 &&
1da177e4
LT		 3706 fcport->port_type != FCT_INITIATOR &&
3707 fcport->port_type != FCT_BROADCAST) {
e315cd28 3708 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3709 fcport->d_id.b.domain, fcport->d_id.b.area,
3710 fcport->d_id.b.al_pa);
5f16b331 3711 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 3712 }
3713
3714 break;
3715 }
3716
3717 if (found)
3718 continue;
1da177e4
LT		 3719 /* If device was not in our fcports list, then add it. */
3720 list_add_tail(&new_fcport->list, new_fcports);
3721
3722 /* Allocate a new replacement fcport. */
3723 nxt_d_id.b24 = new_fcport->d_id.b24;
e315cd28 3724 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3725 if (new_fcport == NULL) {
7c3df132
SK		 3726 ql_log(ql_log_warn, vha, 0x2066,
3727 "Memory allocation failed for fcport.\n");
1da177e4
LT		 3728 return (QLA_MEMORY_ALLOC_FAILED);
3729 }
3730 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
3731 new_fcport->d_id.b24 = nxt_d_id.b24;
3732 }
3733
c9475cb0 3734 kfree(new_fcport);
1da177e4 3735
1da177e4
LT		 3736 return (rval);
3737}
3738
3739/*
3740 * qla2x00_find_new_loop_id
3741 * Scan through our port list and find a new usable loop ID.
3742 *
3743 * Input:
3744 * ha: adapter state pointer.
3745 * dev: port structure pointer.
3746 *
3747 * Returns:
3748 * qla2x00 local function return status code.
3749 *
3750 * Context:
3751 * Kernel context.
3752 */
03bcfb57 3753int
e315cd28 3754qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
1da177e4
LT		 3755{
3756 int rval;
e315cd28 3757 struct qla_hw_data *ha = vha->hw;
feafb7b1 3758 unsigned long flags = 0;
1da177e4
LT		 3759
3760 rval = QLA_SUCCESS;
3761
5f16b331 3762 spin_lock_irqsave(&ha->vport_slock, flags);
1da177e4 3763
5f16b331
CD		 3764 dev->loop_id = find_first_zero_bit(ha->loop_id_map,
3765 LOOPID_MAP_SIZE);
3766 if (dev->loop_id >= LOOPID_MAP_SIZE ||
3767 qla2x00_is_reserved_id(vha, dev->loop_id)) {
3768 dev->loop_id = FC_NO_LOOP_ID;
3769 rval = QLA_FUNCTION_FAILED;
3770 } else
3771 set_bit(dev->loop_id, ha->loop_id_map);
1da177e4 3772
5f16b331 3773 spin_unlock_irqrestore(&ha->vport_slock, flags);
1da177e4 3774
5f16b331
CD		 3775 if (rval == QLA_SUCCESS)
3776 ql_dbg(ql_dbg_disc, dev->vha, 0x2086,
3777 "Assigning new loopid=%x, portid=%x.\n",
3778 dev->loop_id, dev->d_id.b24);
3779 else
3780 ql_log(ql_log_warn, dev->vha, 0x2087,
3781 "No loop_id's available, portid=%x.\n",
3782 dev->d_id.b24);
1da177e4
LT		 3783
3784 return (rval);
3785}
3786
1da177e4
LT		 3787/*
3788 * qla2x00_fabric_dev_login
3789 * Login fabric target device and update FC port database.
3790 *
3791 * Input:
3792 * ha: adapter state pointer.
3793 * fcport: port structure list pointer.
3794 * next_loopid: contains value of a new loop ID that can be used
3795 * by the next login attempt.
3796 *
3797 * Returns:
3798 * qla2x00 local function return status code.
3799 *
3800 * Context:
3801 * Kernel context.
3802 */
3803static int
e315cd28 3804qla2x00_fabric_dev_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 3805 uint16_t *next_loopid)
3806{
3807 int rval;
3808 int retry;
0107109e 3809 uint8_t opts;
e315cd28 3810 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3811
3812 rval = QLA_SUCCESS;
3813 retry = 0;
3814
ac280b67 3815 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584
AV		 3816 if (fcport->flags & FCF_ASYNC_SENT)
3817 return rval;
3818 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 3819 rval = qla2x00_post_async_login_work(vha, fcport, NULL);
3820 if (!rval)
3821 return rval;
3822 }
3823
5ff1d584 3824 fcport->flags &= ~FCF_ASYNC_SENT;
e315cd28 3825 rval = qla2x00_fabric_login(vha, fcport, next_loopid);
1da177e4 3826 if (rval == QLA_SUCCESS) {
f08b7251 3827 /* Send an ADISC to FCP2 devices.*/
0107109e 3828 opts = 0;
f08b7251 3829 if (fcport->flags & FCF_FCP2_DEVICE)
0107109e 3830 opts |= BIT_1;
e315cd28 3831 rval = qla2x00_get_port_database(vha, fcport, opts);
1da177e4 3832 if (rval != QLA_SUCCESS) {
e315cd28 3833 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3834 fcport->d_id.b.domain, fcport->d_id.b.area,
3835 fcport->d_id.b.al_pa);
e315cd28 3836 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4 3837 } else {
e315cd28 3838 qla2x00_update_fcport(vha, fcport);
1da177e4 3839 }
0b91d116
CD		 3840 } else {
3841 /* Retry Login. */
3842 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 3843 }
3844
3845 return (rval);
3846}
3847
3848/*
3849 * qla2x00_fabric_login
3850 * Issue fabric login command.
3851 *
3852 * Input:
3853 * ha = adapter block pointer.
3854 * device = pointer to FC device type structure.
3855 *
3856 * Returns:
3857 * 0 - Login successfully
3858 * 1 - Login failed
3859 * 2 - Initiator device
3860 * 3 - Fatal error
3861 */
3862int
e315cd28 3863qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 3864 uint16_t *next_loopid)
3865{
3866 int rval;
3867 int retry;
3868 uint16_t tmp_loopid;
3869 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 3870 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3871
3872 retry = 0;
3873 tmp_loopid = 0;
3874
3875 for (;;) {
7c3df132
SK		 3876 ql_dbg(ql_dbg_disc, vha, 0x2000,
3877 "Trying Fabric Login w/loop id 0x%04x for port "
3878 "%02x%02x%02x.\n",
3879 fcport->loop_id, fcport->d_id.b.domain,
3880 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 3881
3882 /* Login fcport on switch. */
0b91d116 3883 rval = ha->isp_ops->fabric_login(vha, fcport->loop_id,
1da177e4
LT		 3884 fcport->d_id.b.domain, fcport->d_id.b.area,
3885 fcport->d_id.b.al_pa, mb, BIT_0);
0b91d116
CD		 3886 if (rval != QLA_SUCCESS) {
3887 return rval;
3888 }
1da177e4
LT		 3889 if (mb[0] == MBS_PORT_ID_USED) {
3890 /*
3891 * Device has another loop ID. The firmware team
0107109e
AV		 3892 * recommends the driver perform an implicit login with
3893 * the specified ID again. The ID we just used is save
3894 * here so we return with an ID that can be tried by
3895 * the next login.
1da177e4
LT		 3896 */
3897 retry++;
3898 tmp_loopid = fcport->loop_id;
3899 fcport->loop_id = mb[1];
3900
7c3df132
SK		 3901 ql_dbg(ql_dbg_disc, vha, 0x2001,
3902 "Fabric Login: port in use - next loop "
3903 "id=0x%04x, port id= %02x%02x%02x.\n",
1da177e4 3904 fcport->loop_id, fcport->d_id.b.domain,
7c3df132 3905 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 3906
3907 } else if (mb[0] == MBS_COMMAND_COMPLETE) {
3908 /*
3909 * Login succeeded.
3910 */
3911 if (retry) {
3912 /* A retry occurred before. */
3913 *next_loopid = tmp_loopid;
3914 } else {
3915 /*
3916 * No retry occurred before. Just increment the
3917 * ID value for next login.
3918 */
3919 *next_loopid = (fcport->loop_id + 1);
3920 }
3921
3922 if (mb[1] & BIT_0) {
3923 fcport->port_type = FCT_INITIATOR;
3924 } else {
3925 fcport->port_type = FCT_TARGET;
3926 if (mb[1] & BIT_1) {
8474f3a0 3927 fcport->flags |= FCF_FCP2_DEVICE;
1da177e4
LT		 3928 }
3929 }
3930
ad3e0eda
AV		 3931 if (mb[10] & BIT_0)
3932 fcport->supported_classes |= FC_COS_CLASS2;
3933 if (mb[10] & BIT_1)
3934 fcport->supported_classes |= FC_COS_CLASS3;
3935
2d70c103
NB		 3936 if (IS_FWI2_CAPABLE(ha)) {
3937 if (mb[10] & BIT_7)
3938 fcport->flags |=
3939 FCF_CONF_COMP_SUPPORTED;
3940 }
3941
1da177e4
LT		 3942 rval = QLA_SUCCESS;
3943 break;
3944 } else if (mb[0] == MBS_LOOP_ID_USED) {
3945 /*
3946 * Loop ID already used, try next loop ID.
3947 */
3948 fcport->loop_id++;
e315cd28 3949 rval = qla2x00_find_new_loop_id(vha, fcport);
1da177e4
LT		 3950 if (rval != QLA_SUCCESS) {
3951 /* Ran out of loop IDs to use */
3952 break;
3953 }
3954 } else if (mb[0] == MBS_COMMAND_ERROR) {
3955 /*
3956 * Firmware possibly timed out during login. If NO
3957 * retries are left to do then the device is declared
3958 * dead.
3959 */
3960 *next_loopid = fcport->loop_id;
e315cd28 3961 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3962 fcport->d_id.b.domain, fcport->d_id.b.area,
3963 fcport->d_id.b.al_pa);
e315cd28 3964 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 3965
3966 rval = 1;
3967 break;
3968 } else {
3969 /*
3970 * unrecoverable / not handled error
3971 */
7c3df132
SK		 3972 ql_dbg(ql_dbg_disc, vha, 0x2002,
3973 "Failed=%x port_id=%02x%02x%02x loop_id=%x "
3974 "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain,
3975 fcport->d_id.b.area, fcport->d_id.b.al_pa,
3976 fcport->loop_id, jiffies);
1da177e4
LT		 3977
3978 *next_loopid = fcport->loop_id;
e315cd28 3979 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3980 fcport->d_id.b.domain, fcport->d_id.b.area,
3981 fcport->d_id.b.al_pa);
5f16b331 3982 qla2x00_clear_loop_id(fcport);
0eedfcf0 3983 fcport->login_retry = 0;
1da177e4
LT		 3984
3985 rval = 3;
3986 break;
3987 }
3988 }
3989
3990 return (rval);
3991}
3992
3993/*
3994 * qla2x00_local_device_login
3995 * Issue local device login command.
3996 *
3997 * Input:
3998 * ha = adapter block pointer.
3999 * loop_id = loop id of device to login to.
4000 *
4001 * Returns (Where's the #define!!!!):
4002 * 0 - Login successfully
4003 * 1 - Login failed
4004 * 3 - Fatal error
4005 */
4006int
e315cd28 4007qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport)
1da177e4
LT		 4008{
4009 int rval;
4010 uint16_t mb[MAILBOX_REGISTER_COUNT];
4011
4012 memset(mb, 0, sizeof(mb));
e315cd28 4013 rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0);
1da177e4
LT		 4014 if (rval == QLA_SUCCESS) {
4015 /* Interrogate mailbox registers for any errors */
4016 if (mb[0] == MBS_COMMAND_ERROR)
4017 rval = 1;
4018 else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR)
4019 /* device not in PCB table */
4020 rval = 3;
4021 }
4022
4023 return (rval);
4024}
4025
4026/*
4027 * qla2x00_loop_resync
4028 * Resync with fibre channel devices.
4029 *
4030 * Input:
4031 * ha = adapter block pointer.
4032 *
4033 * Returns:
4034 * 0 = success
4035 */
4036int
e315cd28 4037qla2x00_loop_resync(scsi_qla_host_t *vha)
1da177e4 4038{
73208dfd 4039 int rval = QLA_SUCCESS;
1da177e4 4040 uint32_t wait_time;
67c2e93a
AC		 4041 struct req_que *req;
4042 struct rsp_que *rsp;
4043
7163ea81 4044 if (vha->hw->flags.cpu_affinity_enabled)
67c2e93a
AC		 4045 req = vha->hw->req_q_map[0];
4046 else
4047 req = vha->req;
4048 rsp = req->rsp;
1da177e4 4049
e315cd28
AC		 4050 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
4051 if (vha->flags.online) {
4052 if (!(rval = qla2x00_fw_ready(vha))) {
1da177e4
LT		 4053 /* Wait at most MAX_TARGET RSCNs for a stable link. */
4054 wait_time = 256;
4055 do {
8ae6d9c7
GM		 4056 if (!IS_QLAFX00(vha->hw)) {
4057 /*
4058 * Issue a marker after FW becomes
4059 * ready.
4060 */
4061 qla2x00_marker(vha, req, rsp, 0, 0,
4062 MK_SYNC_ALL);
4063 vha->marker_needed = 0;
4064 }
1da177e4
LT		 4065
4066 /* Remap devices on Loop. */
e315cd28 4067 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4 4068
8ae6d9c7
GM		 4069 if (IS_QLAFX00(vha->hw))
4070 qlafx00_configure_devices(vha);
4071 else
4072 qla2x00_configure_loop(vha);
4073
1da177e4 4074 wait_time--;
e315cd28
AC		 4075 } while (!atomic_read(&vha->loop_down_timer) &&
4076 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
4077 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
4078 &vha->dpc_flags)));
1da177e4 4079 }
1da177e4
LT		 4080 }
4081
e315cd28 4082 if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
1da177e4 4083 return (QLA_FUNCTION_FAILED);
1da177e4 4084
e315cd28 4085 if (rval)
7c3df132
SK		 4086 ql_dbg(ql_dbg_disc, vha, 0x206c,
4087 "%s *** FAILED ***.\n", __func__);
1da177e4
LT		 4088
4089 return (rval);
4090}
4091
579d12b5
SK		 4092/*
4093* qla2x00_perform_loop_resync
4094* Description: This function will set the appropriate flags and call
4095* qla2x00_loop_resync. If successful loop will be resynced
4096* Arguments : scsi_qla_host_t pointer
4097* returm : Success or Failure
4098*/
4099
4100int qla2x00_perform_loop_resync(scsi_qla_host_t *ha)
4101{
4102 int32_t rval = 0;
4103
4104 if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) {
4105 /*Configure the flags so that resync happens properly*/
4106 atomic_set(&ha->loop_down_timer, 0);
4107 if (!(ha->device_flags & DFLG_NO_CABLE)) {
4108 atomic_set(&ha->loop_state, LOOP_UP);
4109 set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags);
4110 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
4111 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
4112
4113 rval = qla2x00_loop_resync(ha);
4114 } else
4115 atomic_set(&ha->loop_state, LOOP_DEAD);
4116
4117 clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags);
4118 }
4119
4120 return rval;
4121}
4122
d97994dc 4123void
67becc00 4124qla2x00_update_fcports(scsi_qla_host_t *base_vha)
d97994dc
AV		 4125{
4126 fc_port_t *fcport;
feafb7b1
AE		 4127 struct scsi_qla_host *vha;
4128 struct qla_hw_data *ha = base_vha->hw;
4129 unsigned long flags;
d97994dc 4130
feafb7b1 4131 spin_lock_irqsave(&ha->vport_slock, flags);
d97994dc 4132 /* Go with deferred removal of rport references. */
feafb7b1
AE		 4133 list_for_each_entry(vha, &base_vha->hw->vp_list, list) {
4134 atomic_inc(&vha->vref_count);
4135 list_for_each_entry(fcport, &vha->vp_fcports, list) {
8ae598d0 4136 if (fcport->drport &&
feafb7b1
AE		 4137 atomic_read(&fcport->state) != FCS_UNCONFIGURED) {
4138 spin_unlock_irqrestore(&ha->vport_slock, flags);
67becc00 4139 qla2x00_rport_del(fcport);
feafb7b1
AE		 4140 spin_lock_irqsave(&ha->vport_slock, flags);
4141 }
4142 }
4143 atomic_dec(&vha->vref_count);
4144 }
4145 spin_unlock_irqrestore(&ha->vport_slock, flags);
d97994dc
AV		 4146}
4147
7d613ac6
SV		 4148/* Assumes idc_lock always held on entry */
4149void
4150qla83xx_reset_ownership(scsi_qla_host_t *vha)
4151{
4152 struct qla_hw_data *ha = vha->hw;
4153 uint32_t drv_presence, drv_presence_mask;
4154 uint32_t dev_part_info1, dev_part_info2, class_type;
4155 uint32_t class_type_mask = 0x3;
4156 uint16_t fcoe_other_function = 0xffff, i;
4157
7ec0effd
AD		 4158 if (IS_QLA8044(ha)) {
4159 drv_presence = qla8044_rd_direct(vha,
4160 QLA8044_CRB_DRV_ACTIVE_INDEX);
4161 dev_part_info1 = qla8044_rd_direct(vha,
4162 QLA8044_CRB_DEV_PART_INFO_INDEX);
4163 dev_part_info2 = qla8044_rd_direct(vha,
4164 QLA8044_CRB_DEV_PART_INFO2);
4165 } else {
4166 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4167 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1);
4168 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2);
4169 }
7d613ac6
SV		 4170 for (i = 0; i < 8; i++) {
4171 class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask);
4172 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
4173 (i != ha->portnum)) {
4174 fcoe_other_function = i;
4175 break;
4176 }
4177 }
4178 if (fcoe_other_function == 0xffff) {
4179 for (i = 0; i < 8; i++) {
4180 class_type = ((dev_part_info2 >> (i * 4)) &
4181 class_type_mask);
4182 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
4183 ((i + 8) != ha->portnum)) {
4184 fcoe_other_function = i + 8;
4185 break;
4186 }
4187 }
4188 }
4189 /*
4190 * Prepare drv-presence mask based on fcoe functions present.
4191 * However consider only valid physical fcoe function numbers (0-15).
4192 */
4193 drv_presence_mask = ~((1 << (ha->portnum)) |
4194 ((fcoe_other_function == 0xffff) ?
4195 0 : (1 << (fcoe_other_function))));
4196
4197 /* We are the reset owner iff:
4198 * - No other protocol drivers present.
4199 * - This is the lowest among fcoe functions. */
4200 if (!(drv_presence & drv_presence_mask) &&
4201 (ha->portnum < fcoe_other_function)) {
4202 ql_dbg(ql_dbg_p3p, vha, 0xb07f,
4203 "This host is Reset owner.\n");
4204 ha->flags.nic_core_reset_owner = 1;
4205 }
4206}
4207
fa492630 4208static int
7d613ac6
SV		 4209__qla83xx_set_drv_ack(scsi_qla_host_t *vha)
4210{
4211 int rval = QLA_SUCCESS;
4212 struct qla_hw_data *ha = vha->hw;
4213 uint32_t drv_ack;
4214
4215 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4216 if (rval == QLA_SUCCESS) {
4217 drv_ack |= (1 << ha->portnum);
4218 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
4219 }
4220
4221 return rval;
4222}
4223
fa492630 4224static int
7d613ac6
SV		 4225__qla83xx_clear_drv_ack(scsi_qla_host_t *vha)
4226{
4227 int rval = QLA_SUCCESS;
4228 struct qla_hw_data *ha = vha->hw;
4229 uint32_t drv_ack;
4230
4231 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4232 if (rval == QLA_SUCCESS) {
4233 drv_ack &= ~(1 << ha->portnum);
4234 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
4235 }
4236
4237 return rval;
4238}
4239
fa492630 4240static const char *
7d613ac6
SV		 4241qla83xx_dev_state_to_string(uint32_t dev_state)
4242{
4243 switch (dev_state) {
4244 case QLA8XXX_DEV_COLD:
4245 return "COLD/RE-INIT";
4246 case QLA8XXX_DEV_INITIALIZING:
4247 return "INITIALIZING";
4248 case QLA8XXX_DEV_READY:
4249 return "READY";
4250 case QLA8XXX_DEV_NEED_RESET:
4251 return "NEED RESET";
4252 case QLA8XXX_DEV_NEED_QUIESCENT:
4253 return "NEED QUIESCENT";
4254 case QLA8XXX_DEV_FAILED:
4255 return "FAILED";
4256 case QLA8XXX_DEV_QUIESCENT:
4257 return "QUIESCENT";
4258 default:
4259 return "Unknown";
4260 }
4261}
4262
4263/* Assumes idc-lock always held on entry */
4264void
4265qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type)
4266{
4267 struct qla_hw_data *ha = vha->hw;
4268 uint32_t idc_audit_reg = 0, duration_secs = 0;
4269
4270 switch (audit_type) {
4271 case IDC_AUDIT_TIMESTAMP:
4272 ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000);
4273 idc_audit_reg = (ha->portnum) |
4274 (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8);
4275 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
4276 break;
4277
4278 case IDC_AUDIT_COMPLETION:
4279 duration_secs = ((jiffies_to_msecs(jiffies) -
4280 jiffies_to_msecs(ha->idc_audit_ts)) / 1000);
4281 idc_audit_reg = (ha->portnum) |
4282 (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8);
4283 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
4284 break;
4285
4286 default:
4287 ql_log(ql_log_warn, vha, 0xb078,
4288 "Invalid audit type specified.\n");
4289 break;
4290 }
4291}
4292
4293/* Assumes idc_lock always held on entry */
fa492630 4294static int
7d613ac6
SV		 4295qla83xx_initiating_reset(scsi_qla_host_t *vha)
4296{
4297 struct qla_hw_data *ha = vha->hw;
4298 uint32_t idc_control, dev_state;
4299
4300 __qla83xx_get_idc_control(vha, &idc_control);
4301 if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) {
4302 ql_log(ql_log_info, vha, 0xb080,
4303 "NIC Core reset has been disabled. idc-control=0x%x\n",
4304 idc_control);
4305 return QLA_FUNCTION_FAILED;
4306 }
4307
4308 /* Set NEED-RESET iff in READY state and we are the reset-owner */
4309 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4310 if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) {
4311 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
4312 QLA8XXX_DEV_NEED_RESET);
4313 ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n");
4314 qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP);
4315 } else {
4316 const char *state = qla83xx_dev_state_to_string(dev_state);
4317 ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n", state);
4318
4319 /* SV: XXX: Is timeout required here? */
4320 /* Wait for IDC state change READY -> NEED_RESET */
4321 while (dev_state == QLA8XXX_DEV_READY) {
4322 qla83xx_idc_unlock(vha, 0);
4323 msleep(200);
4324 qla83xx_idc_lock(vha, 0);
4325 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4326 }
4327 }
4328
4329 /* Send IDC ack by writing to drv-ack register */
4330 __qla83xx_set_drv_ack(vha);
4331
4332 return QLA_SUCCESS;
4333}
4334
4335int
4336__qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control)
4337{
4338 return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
4339}
4340
7d613ac6
SV		 4341int
4342__qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control)
4343{
4344 return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
4345}
4346
fa492630 4347static int
7d613ac6
SV		 4348qla83xx_check_driver_presence(scsi_qla_host_t *vha)
4349{
4350 uint32_t drv_presence = 0;
4351 struct qla_hw_data *ha = vha->hw;
4352
4353 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4354 if (drv_presence & (1 << ha->portnum))
4355 return QLA_SUCCESS;
4356 else
4357 return QLA_TEST_FAILED;
4358}
4359
4360int
4361qla83xx_nic_core_reset(scsi_qla_host_t *vha)
4362{
4363 int rval = QLA_SUCCESS;
4364 struct qla_hw_data *ha = vha->hw;
4365
4366 ql_dbg(ql_dbg_p3p, vha, 0xb058,
4367 "Entered %s().\n", __func__);
4368
4369 if (vha->device_flags & DFLG_DEV_FAILED) {
4370 ql_log(ql_log_warn, vha, 0xb059,
4371 "Device in unrecoverable FAILED state.\n");
4372 return QLA_FUNCTION_FAILED;
4373 }
4374
4375 qla83xx_idc_lock(vha, 0);
4376
4377 if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) {
4378 ql_log(ql_log_warn, vha, 0xb05a,
4379 "Function=0x%x has been removed from IDC participation.\n",
4380 ha->portnum);
4381 rval = QLA_FUNCTION_FAILED;
4382 goto exit;
4383 }
4384
4385 qla83xx_reset_ownership(vha);
4386
4387 rval = qla83xx_initiating_reset(vha);
4388
4389 /*
4390 * Perform reset if we are the reset-owner,
4391 * else wait till IDC state changes to READY/FAILED.
4392 */
4393 if (rval == QLA_SUCCESS) {
4394 rval = qla83xx_idc_state_handler(vha);
4395
4396 if (rval == QLA_SUCCESS)
4397 ha->flags.nic_core_hung = 0;
4398 __qla83xx_clear_drv_ack(vha);
4399 }
4400
4401exit:
4402 qla83xx_idc_unlock(vha, 0);
4403
4404 ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__);
4405
4406 return rval;
4407}
4408
81178772
SK		 4409int
4410qla2xxx_mctp_dump(scsi_qla_host_t *vha)
4411{
4412 struct qla_hw_data *ha = vha->hw;
4413 int rval = QLA_FUNCTION_FAILED;
4414
4415 if (!IS_MCTP_CAPABLE(ha)) {
4416 /* This message can be removed from the final version */
4417 ql_log(ql_log_info, vha, 0x506d,
4418 "This board is not MCTP capable\n");
4419 return rval;
4420 }
4421
4422 if (!ha->mctp_dump) {
4423 ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev,
4424 MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL);
4425
4426 if (!ha->mctp_dump) {
4427 ql_log(ql_log_warn, vha, 0x506e,
4428 "Failed to allocate memory for mctp dump\n");
4429 return rval;
4430 }
4431 }
4432
4433#define MCTP_DUMP_STR_ADDR 0x00000000
4434 rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma,
4435 MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4);
4436 if (rval != QLA_SUCCESS) {
4437 ql_log(ql_log_warn, vha, 0x506f,
4438 "Failed to capture mctp dump\n");
4439 } else {
4440 ql_log(ql_log_info, vha, 0x5070,
4441 "Mctp dump capture for host (%ld/%p).\n",
4442 vha->host_no, ha->mctp_dump);
4443 ha->mctp_dumped = 1;
4444 }
4445
409ee0fe 4446 if (!ha->flags.nic_core_reset_hdlr_active && !ha->portnum) {
81178772
SK		 4447 ha->flags.nic_core_reset_hdlr_active = 1;
4448 rval = qla83xx_restart_nic_firmware(vha);
4449 if (rval)
4450 /* NIC Core reset failed. */
4451 ql_log(ql_log_warn, vha, 0x5071,
4452 "Failed to restart nic firmware\n");
4453 else
4454 ql_dbg(ql_dbg_p3p, vha, 0xb084,
4455 "Restarted NIC firmware successfully.\n");
4456 ha->flags.nic_core_reset_hdlr_active = 0;
4457 }
4458
4459 return rval;
4460
4461}
4462
579d12b5 4463/*
8fcd6b8b 4464* qla2x00_quiesce_io
579d12b5
SK		 4465* Description: This function will block the new I/Os
4466* Its not aborting any I/Os as context
4467* is not destroyed during quiescence
4468* Arguments: scsi_qla_host_t
4469* return : void
4470*/
4471void
8fcd6b8b 4472qla2x00_quiesce_io(scsi_qla_host_t *vha)
579d12b5
SK		 4473{
4474 struct qla_hw_data *ha = vha->hw;
4475 struct scsi_qla_host *vp;
4476
8fcd6b8b
CD		 4477 ql_dbg(ql_dbg_dpc, vha, 0x401d,
4478 "Quiescing I/O - ha=%p.\n", ha);
579d12b5
SK		 4479
4480 atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME);
4481 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
4482 atomic_set(&vha->loop_state, LOOP_DOWN);
4483 qla2x00_mark_all_devices_lost(vha, 0);
4484 list_for_each_entry(vp, &ha->vp_list, list)
8fcd6b8b 4485 qla2x00_mark_all_devices_lost(vp, 0);
579d12b5
SK		 4486 } else {
4487 if (!atomic_read(&vha->loop_down_timer))
4488 atomic_set(&vha->loop_down_timer,
4489 LOOP_DOWN_TIME);
4490 }
4491 /* Wait for pending cmds to complete */
4492 qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST);
4493}
4494
a9083016
GM		 4495void
4496qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
4497{
4498 struct qla_hw_data *ha = vha->hw;
579d12b5 4499 struct scsi_qla_host *vp;
feafb7b1 4500 unsigned long flags;
6aef87be 4501 fc_port_t *fcport;
a9083016 4502
e46ef004
SK		 4503 /* For ISP82XX, driver waits for completion of the commands.
4504 * online flag should be set.
4505 */
7ec0effd 4506 if (!(IS_P3P_TYPE(ha)))
e46ef004 4507 vha->flags.online = 0;
a9083016
GM		 4508 ha->flags.chip_reset_done = 0;
4509 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2be21fa2 4510 vha->qla_stats.total_isp_aborts++;
a9083016 4511
7c3df132
SK		 4512 ql_log(ql_log_info, vha, 0x00af,
4513 "Performing ISP error recovery - ha=%p.\n", ha);
a9083016 4514
e46ef004
SK		 4515 /* For ISP82XX, reset_chip is just disabling interrupts.
4516 * Driver waits for the completion of the commands.
4517 * the interrupts need to be enabled.
4518 */
7ec0effd 4519 if (!(IS_P3P_TYPE(ha)))
a9083016
GM		 4520 ha->isp_ops->reset_chip(vha);
4521
4522 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
4523 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
4524 atomic_set(&vha->loop_state, LOOP_DOWN);
4525 qla2x00_mark_all_devices_lost(vha, 0);
feafb7b1
AE		 4526
4527 spin_lock_irqsave(&ha->vport_slock, flags);
579d12b5 4528 list_for_each_entry(vp, &ha->vp_list, list) {
feafb7b1
AE		 4529 atomic_inc(&vp->vref_count);
4530 spin_unlock_irqrestore(&ha->vport_slock, flags);
4531
a9083016 4532 qla2x00_mark_all_devices_lost(vp, 0);
feafb7b1
AE		 4533
4534 spin_lock_irqsave(&ha->vport_slock, flags);
4535 atomic_dec(&vp->vref_count);
4536 }
4537 spin_unlock_irqrestore(&ha->vport_slock, flags);
a9083016
GM		 4538 } else {
4539 if (!atomic_read(&vha->loop_down_timer))
4540 atomic_set(&vha->loop_down_timer,
4541 LOOP_DOWN_TIME);
4542 }
4543
6aef87be
AV		 4544 /* Clear all async request states across all VPs. */
4545 list_for_each_entry(fcport, &vha->vp_fcports, list)
4546 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
4547 spin_lock_irqsave(&ha->vport_slock, flags);
4548 list_for_each_entry(vp, &ha->vp_list, list) {
4549 atomic_inc(&vp->vref_count);
4550 spin_unlock_irqrestore(&ha->vport_slock, flags);
4551
4552 list_for_each_entry(fcport, &vp->vp_fcports, list)
4553 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
4554
4555 spin_lock_irqsave(&ha->vport_slock, flags);
4556 atomic_dec(&vp->vref_count);
4557 }
4558 spin_unlock_irqrestore(&ha->vport_slock, flags);
4559
bddd2d65
LC		 4560 if (!ha->flags.eeh_busy) {
4561 /* Make sure for ISP 82XX IO DMA is complete */
7ec0effd 4562 if (IS_P3P_TYPE(ha)) {
7190575f 4563 qla82xx_chip_reset_cleanup(vha);
7c3df132
SK		 4564 ql_log(ql_log_info, vha, 0x00b4,
4565 "Done chip reset cleanup.\n");
a9083016 4566
e46ef004
SK		 4567 /* Done waiting for pending commands.
4568 * Reset the online flag.
4569 */
4570 vha->flags.online = 0;
4d78c973 4571 }
a9083016 4572
bddd2d65
LC		 4573 /* Requeue all commands in outstanding command list. */
4574 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
4575 }
b6a029e1
AE		 4576
4577 ha->chip_reset++;
4578 /* memory barrier */
4579 wmb();
a9083016
GM		 4580}
4581
1da177e4
LT		 4582/*
4583* qla2x00_abort_isp
4584* Resets ISP and aborts all outstanding commands.
4585*
4586* Input:
4587* ha = adapter block pointer.
4588*
4589* Returns:
4590* 0 = success
4591*/
4592int
e315cd28 4593qla2x00_abort_isp(scsi_qla_host_t *vha)
1da177e4 4594{
476e8978 4595 int rval;
1da177e4 4596 uint8_t status = 0;
e315cd28
AC		 4597 struct qla_hw_data *ha = vha->hw;
4598 struct scsi_qla_host *vp;
73208dfd 4599 struct req_que *req = ha->req_q_map[0];
feafb7b1 4600 unsigned long flags;
1da177e4 4601
e315cd28 4602 if (vha->flags.online) {
a9083016 4603 qla2x00_abort_isp_cleanup(vha);
1da177e4 4604
a6171297
SV		 4605 if (IS_QLA8031(ha)) {
4606 ql_dbg(ql_dbg_p3p, vha, 0xb05c,
4607 "Clearing fcoe driver presence.\n");
4608 if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS)
4609 ql_dbg(ql_dbg_p3p, vha, 0xb073,
4610 "Error while clearing DRV-Presence.\n");
4611 }
4612
85880801
AV		 4613 if (unlikely(pci_channel_offline(ha->pdev) &&
4614 ha->flags.pci_channel_io_perm_failure)) {
4615 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
4616 status = 0;
4617 return status;
4618 }
4619
73208dfd 4620 ha->isp_ops->get_flash_version(vha, req->ring);
30c47662 4621
e315cd28 4622 ha->isp_ops->nvram_config(vha);
1da177e4 4623
e315cd28
AC		 4624 if (!qla2x00_restart_isp(vha)) {
4625 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4 4626
e315cd28 4627 if (!atomic_read(&vha->loop_down_timer)) {
1da177e4
LT		 4628 /*
4629 * Issue marker command only when we are going
4630 * to start the I/O .
4631 */
e315cd28 4632 vha->marker_needed = 1;
1da177e4
LT		 4633 }
4634
e315cd28 4635 vha->flags.online = 1;
1da177e4 4636
fd34f556 4637 ha->isp_ops->enable_intrs(ha);
1da177e4 4638
fa2a1ce5 4639 ha->isp_abort_cnt = 0;
e315cd28 4640 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
476e8978 4641
6246b8a1
GM		 4642 if (IS_QLA81XX(ha) || IS_QLA8031(ha))
4643 qla2x00_get_fw_version(vha);
df613b96
AV		 4644 if (ha->fce) {
4645 ha->flags.fce_enabled = 1;
4646 memset(ha->fce, 0,
4647 fce_calc_size(ha->fce_bufs));
e315cd28 4648 rval = qla2x00_enable_fce_trace(vha,
df613b96
AV		 4649 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
4650 &ha->fce_bufs);
4651 if (rval) {
7c3df132 4652 ql_log(ql_log_warn, vha, 0x8033,
df613b96
AV		 4653 "Unable to reinitialize FCE "
4654 "(%d).\n", rval);
4655 ha->flags.fce_enabled = 0;
4656 }
4657 }
436a7b11
AV		 4658
4659 if (ha->eft) {
4660 memset(ha->eft, 0, EFT_SIZE);
e315cd28 4661 rval = qla2x00_enable_eft_trace(vha,
436a7b11
AV		 4662 ha->eft_dma, EFT_NUM_BUFFERS);
4663 if (rval) {
7c3df132 4664 ql_log(ql_log_warn, vha, 0x8034,
436a7b11
AV		 4665 "Unable to reinitialize EFT "
4666 "(%d).\n", rval);
4667 }
4668 }
1da177e4 4669 } else { /* failed the ISP abort */
e315cd28
AC		 4670 vha->flags.online = 1;
4671 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
1da177e4 4672 if (ha->isp_abort_cnt == 0) {
7c3df132
SK		 4673 ql_log(ql_log_fatal, vha, 0x8035,
4674 "ISP error recover failed - "
4675 "board disabled.\n");
fa2a1ce5 4676 /*
1da177e4
LT		 4677 * The next call disables the board
4678 * completely.
4679 */
e315cd28
AC		 4680 ha->isp_ops->reset_adapter(vha);
4681 vha->flags.online = 0;
1da177e4 4682 clear_bit(ISP_ABORT_RETRY,
e315cd28 4683 &vha->dpc_flags);
1da177e4
LT		 4684 status = 0;
4685 } else { /* schedule another ISP abort */
4686 ha->isp_abort_cnt--;
7c3df132
SK		 4687 ql_dbg(ql_dbg_taskm, vha, 0x8020,
4688 "ISP abort - retry remaining %d.\n",
4689 ha->isp_abort_cnt);
1da177e4
LT		 4690 status = 1;
4691 }
4692 } else {
4693 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
7c3df132
SK		 4694 ql_dbg(ql_dbg_taskm, vha, 0x8021,
4695 "ISP error recovery - retrying (%d) "
4696 "more times.\n", ha->isp_abort_cnt);
e315cd28 4697 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
1da177e4
LT		 4698 status = 1;
4699 }
4700 }
fa2a1ce5 4701
1da177e4
LT		 4702 }
4703
e315cd28 4704 if (!status) {
7c3df132 4705 ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__);
feafb7b1
AE		 4706
4707 spin_lock_irqsave(&ha->vport_slock, flags);
4708 list_for_each_entry(vp, &ha->vp_list, list) {
4709 if (vp->vp_idx) {
4710 atomic_inc(&vp->vref_count);
4711 spin_unlock_irqrestore(&ha->vport_slock, flags);
4712
e315cd28 4713 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 4714
4715 spin_lock_irqsave(&ha->vport_slock, flags);
4716 atomic_dec(&vp->vref_count);
4717 }
e315cd28 4718 }
feafb7b1
AE		 4719 spin_unlock_irqrestore(&ha->vport_slock, flags);
4720
7d613ac6
SV		 4721 if (IS_QLA8031(ha)) {
4722 ql_dbg(ql_dbg_p3p, vha, 0xb05d,
4723 "Setting back fcoe driver presence.\n");
4724 if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS)
4725 ql_dbg(ql_dbg_p3p, vha, 0xb074,
4726 "Error while setting DRV-Presence.\n");
4727 }
e315cd28 4728 } else {
d8424f68
JP		 4729 ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n",
4730 __func__);
1da177e4
LT		 4731 }
4732
4733 return(status);
4734}
4735
4736/*
4737* qla2x00_restart_isp
4738* restarts the ISP after a reset
4739*
4740* Input:
4741* ha = adapter block pointer.
4742*
4743* Returns:
4744* 0 = success
4745*/
4746static int
e315cd28 4747qla2x00_restart_isp(scsi_qla_host_t *vha)
1da177e4 4748{
c6b2fca8 4749 int status = 0;
e315cd28 4750 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 4751 struct req_que *req = ha->req_q_map[0];
4752 struct rsp_que *rsp = ha->rsp_q_map[0];
2d70c103 4753 unsigned long flags;
1da177e4
LT		 4754
4755 /* If firmware needs to be loaded */
e315cd28
AC		 4756 if (qla2x00_isp_firmware(vha)) {
4757 vha->flags.online = 0;
4758 status = ha->isp_ops->chip_diag(vha);
4759 if (!status)
4760 status = qla2x00_setup_chip(vha);
1da177e4
LT		 4761 }
4762
e315cd28
AC		 4763 if (!status && !(status = qla2x00_init_rings(vha))) {
4764 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
2533cf67 4765 ha->flags.chip_reset_done = 1;
7108b76e 4766
73208dfd
AC		 4767 /* Initialize the queues in use */
4768 qla25xx_init_queues(ha);
4769
e315cd28
AC		 4770 status = qla2x00_fw_ready(vha);
4771 if (!status) {
0107109e 4772 /* Issue a marker after FW becomes ready. */
73208dfd 4773 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
0107109e 4774
e315cd28 4775 vha->flags.online = 1;
2d70c103
NB		 4776
4777 /*
4778 * Process any ATIO queue entries that came in
4779 * while we weren't online.
4780 */
4781 spin_lock_irqsave(&ha->hardware_lock, flags);
4782 if (qla_tgt_mode_enabled(vha))
4783 qlt_24xx_process_atio_queue(vha);
4784 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4785
7108b76e 4786 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4
LT		 4787 }
4788
4789 /* if no cable then assume it's good */
e315cd28 4790 if ((vha->device_flags & DFLG_NO_CABLE))
1da177e4 4791 status = 0;
1da177e4
LT		 4792 }
4793 return (status);
4794}
4795
73208dfd
AC		 4796static int
4797qla25xx_init_queues(struct qla_hw_data *ha)
4798{
4799 struct rsp_que *rsp = NULL;
4800 struct req_que *req = NULL;
4801 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
4802 int ret = -1;
4803 int i;
4804
2afa19a9 4805 for (i = 1; i < ha->max_rsp_queues; i++) {
73208dfd
AC		 4806 rsp = ha->rsp_q_map[i];
4807 if (rsp) {
4808 rsp->options &= ~BIT_0;
618a7523 4809 ret = qla25xx_init_rsp_que(base_vha, rsp);
73208dfd 4810 if (ret != QLA_SUCCESS)
7c3df132
SK		 4811 ql_dbg(ql_dbg_init, base_vha, 0x00ff,
4812 "%s Rsp que: %d init failed.\n",
4813 __func__, rsp->id);
73208dfd 4814 else
7c3df132
SK		 4815 ql_dbg(ql_dbg_init, base_vha, 0x0100,
4816 "%s Rsp que: %d inited.\n",
4817 __func__, rsp->id);
73208dfd 4818 }
2afa19a9
AC		 4819 }
4820 for (i = 1; i < ha->max_req_queues; i++) {
73208dfd
AC		 4821 req = ha->req_q_map[i];
4822 if (req) {
29bdccbe 4823 /* Clear outstanding commands array. */
73208dfd 4824 req->options &= ~BIT_0;
618a7523 4825 ret = qla25xx_init_req_que(base_vha, req);
73208dfd 4826 if (ret != QLA_SUCCESS)
7c3df132
SK		 4827 ql_dbg(ql_dbg_init, base_vha, 0x0101,
4828 "%s Req que: %d init failed.\n",
4829 __func__, req->id);
73208dfd 4830 else
7c3df132
SK		 4831 ql_dbg(ql_dbg_init, base_vha, 0x0102,
4832 "%s Req que: %d inited.\n",
4833 __func__, req->id);
73208dfd
AC		 4834 }
4835 }
4836 return ret;
4837}
4838
1da177e4
LT		 4839/*
4840* qla2x00_reset_adapter
4841* Reset adapter.
4842*
4843* Input:
4844* ha = adapter block pointer.
4845*/
abbd8870 4846void
e315cd28 4847qla2x00_reset_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 4848{
4849 unsigned long flags = 0;
e315cd28 4850 struct qla_hw_data *ha = vha->hw;
3d71644c 4851 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 4852
e315cd28 4853 vha->flags.online = 0;
fd34f556 4854 ha->isp_ops->disable_intrs(ha);
1da177e4 4855
1da177e4
LT		 4856 spin_lock_irqsave(&ha->hardware_lock, flags);
4857 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
4858 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
4859 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
4860 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
4861 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4862}
0107109e
AV		 4863
4864void
e315cd28 4865qla24xx_reset_adapter(scsi_qla_host_t *vha)
0107109e
AV		 4866{
4867 unsigned long flags = 0;
e315cd28 4868 struct qla_hw_data *ha = vha->hw;
0107109e
AV		 4869 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
4870
7ec0effd 4871 if (IS_P3P_TYPE(ha))
a9083016
GM		 4872 return;
4873
e315cd28 4874 vha->flags.online = 0;
fd34f556 4875 ha->isp_ops->disable_intrs(ha);
0107109e
AV		 4876
4877 spin_lock_irqsave(&ha->hardware_lock, flags);
4878 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
4879 RD_REG_DWORD(&reg->hccr);
4880 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
4881 RD_REG_DWORD(&reg->hccr);
4882 spin_unlock_irqrestore(&ha->hardware_lock, flags);
09ff36d3
AV		 4883
4884 if (IS_NOPOLLING_TYPE(ha))
4885 ha->isp_ops->enable_intrs(ha);
0107109e
AV		 4886}
4887
4e08df3f
DM		 4888/* On sparc systems, obtain port and node WWN from firmware
4889 * properties.
4890 */
e315cd28
AC		 4891static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha,
4892 struct nvram_24xx *nv)
4e08df3f
DM		 4893{
4894#ifdef CONFIG_SPARC
e315cd28 4895 struct qla_hw_data *ha = vha->hw;
4e08df3f 4896 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 4897 struct device_node *dp = pci_device_to_OF_node(pdev);
4898 const u8 *val;
4e08df3f
DM		 4899 int len;
4900
4901 val = of_get_property(dp, "port-wwn", &len);
4902 if (val && len >= WWN_SIZE)
4903 memcpy(nv->port_name, val, WWN_SIZE);
4904
4905 val = of_get_property(dp, "node-wwn", &len);
4906 if (val && len >= WWN_SIZE)
4907 memcpy(nv->node_name, val, WWN_SIZE);
4908#endif
4909}
4910
0107109e 4911int
e315cd28 4912qla24xx_nvram_config(scsi_qla_host_t *vha)
0107109e 4913{
4e08df3f 4914 int rval;
0107109e
AV		 4915 struct init_cb_24xx *icb;
4916 struct nvram_24xx *nv;
4917 uint32_t *dptr;
4918 uint8_t *dptr1, *dptr2;
4919 uint32_t chksum;
4920 uint16_t cnt;
e315cd28 4921 struct qla_hw_data *ha = vha->hw;
0107109e 4922
4e08df3f 4923 rval = QLA_SUCCESS;
0107109e 4924 icb = (struct init_cb_24xx *)ha->init_cb;
281afe19 4925 nv = ha->nvram;
0107109e
AV		 4926
4927 /* Determine NVRAM starting address. */
f73cb695 4928 if (ha->port_no == 0) {
e5b68a61
AC		 4929 ha->nvram_base = FA_NVRAM_FUNC0_ADDR;
4930 ha->vpd_base = FA_NVRAM_VPD0_ADDR;
4931 } else {
0107109e 4932 ha->nvram_base = FA_NVRAM_FUNC1_ADDR;
6f641790
AV		 4933 ha->vpd_base = FA_NVRAM_VPD1_ADDR;
4934 }
f73cb695 4935
e5b68a61
AC		 4936 ha->nvram_size = sizeof(struct nvram_24xx);
4937 ha->vpd_size = FA_NVRAM_VPD_SIZE;
0107109e 4938
281afe19
SJ		 4939 /* Get VPD data into cache */
4940 ha->vpd = ha->nvram + VPD_OFFSET;
e315cd28 4941 ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd,
281afe19
SJ		 4942 ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
4943
4944 /* Get NVRAM data into cache and calculate checksum. */
0107109e 4945 dptr = (uint32_t *)nv;
e315cd28 4946 ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base,
0107109e
AV		 4947 ha->nvram_size);
4948 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
4949 chksum += le32_to_cpu(*dptr++);
4950
7c3df132
SK		 4951 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
4952 "Contents of NVRAM\n");
4953 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
4954 (uint8_t *)nv, ha->nvram_size);
0107109e
AV		 4955
4956 /* Bad NVRAM data, set defaults parameters. */
4957 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
4958 || nv->id[3] != ' ' ||
4959 nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
4960 /* Reset NVRAM data. */
7c3df132 4961 ql_log(ql_log_warn, vha, 0x006b,
9e336520 4962 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132
SK		 4963 "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version);
4964 ql_log(ql_log_warn, vha, 0x006c,
4965 "Falling back to functioning (yet invalid -- WWPN) "
4966 "defaults.\n");
4e08df3f
DM		 4967
4968 /*
4969 * Set default initialization control block.
4970 */
4971 memset(nv, 0, ha->nvram_size);
4972 nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
4973 nv->version = __constant_cpu_to_le16(ICB_VERSION);
98aee70d 4974 nv->frame_payload_size = 2048;
4e08df3f
DM		 4975 nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
4976 nv->exchange_count = __constant_cpu_to_le16(0);
4977 nv->hard_address = __constant_cpu_to_le16(124);
4978 nv->port_name[0] = 0x21;
f73cb695 4979 nv->port_name[1] = 0x00 + ha->port_no + 1;
4e08df3f
DM		 4980 nv->port_name[2] = 0x00;
4981 nv->port_name[3] = 0xe0;
4982 nv->port_name[4] = 0x8b;
4983 nv->port_name[5] = 0x1c;
4984 nv->port_name[6] = 0x55;
4985 nv->port_name[7] = 0x86;
4986 nv->node_name[0] = 0x20;
4987 nv->node_name[1] = 0x00;
4988 nv->node_name[2] = 0x00;
4989 nv->node_name[3] = 0xe0;
4990 nv->node_name[4] = 0x8b;
4991 nv->node_name[5] = 0x1c;
4992 nv->node_name[6] = 0x55;
4993 nv->node_name[7] = 0x86;
e315cd28 4994 qla24xx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 4995 nv->login_retry_count = __constant_cpu_to_le16(8);
4996 nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
4997 nv->login_timeout = __constant_cpu_to_le16(0);
4998 nv->firmware_options_1 =
4999 __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
5000 nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
5001 nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
5002 nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
5003 nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
5004 nv->efi_parameters = __constant_cpu_to_le32(0);
5005 nv->reset_delay = 5;
5006 nv->max_luns_per_target = __constant_cpu_to_le16(128);
5007 nv->port_down_retry_count = __constant_cpu_to_le16(30);
5008 nv->link_down_timeout = __constant_cpu_to_le16(30);
5009
5010 rval = 1;
0107109e
AV		 5011 }
5012
2d70c103
NB		 5013 if (!qla_ini_mode_enabled(vha)) {
5014 /* Don't enable full login after initial LIP */
5015 nv->firmware_options_1 &= __constant_cpu_to_le32(~BIT_13);
5016 /* Don't enable LIP full login for initiator */
5017 nv->host_p &= __constant_cpu_to_le32(~BIT_10);
5018 }
5019
5020 qlt_24xx_config_nvram_stage1(vha, nv);
5021
0107109e 5022 /* Reset Initialization control block */
e315cd28 5023 memset(icb, 0, ha->init_cb_size);
0107109e
AV		 5024
5025 /* Copy 1st segment. */
5026 dptr1 = (uint8_t *)icb;
5027 dptr2 = (uint8_t *)&nv->version;
5028 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
5029 while (cnt--)
5030 *dptr1++ = *dptr2++;
5031
5032 icb->login_retry_count = nv->login_retry_count;
3ea66e28 5033 icb->link_down_on_nos = nv->link_down_on_nos;
0107109e
AV		 5034
5035 /* Copy 2nd segment. */
5036 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
5037 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
5038 cnt = (uint8_t *)&icb->reserved_3 -
5039 (uint8_t *)&icb->interrupt_delay_timer;
5040 while (cnt--)
5041 *dptr1++ = *dptr2++;
5042
5043 /*
5044 * Setup driver NVRAM options.
5045 */
e315cd28 5046 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
9bb9fcf2 5047 "QLA2462");
0107109e 5048
2d70c103
NB		 5049 qlt_24xx_config_nvram_stage2(vha, icb);
5050
5341e868 5051 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
2d70c103 5052 /* Use alternate WWN? */
5341e868
AV		 5053 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
5054 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
5055 }
5056
0107109e 5057 /* Prepare nodename */
fd0e7e4d 5058 if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
0107109e
AV		 5059 /*
5060 * Firmware will apply the following mask if the nodename was
5061 * not provided.
5062 */
5063 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
5064 icb->node_name[0] &= 0xF0;
5065 }
5066
5067 /* Set host adapter parameters. */
5068 ha->flags.disable_risc_code_load = 0;
0c8c39af
AV		 5069 ha->flags.enable_lip_reset = 0;
5070 ha->flags.enable_lip_full_login =
5071 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
5072 ha->flags.enable_target_reset =
5073 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
0107109e 5074 ha->flags.enable_led_scheme = 0;
d4c760c2 5075 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
0107109e 5076
fd0e7e4d
AV		 5077 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
5078 (BIT_6 | BIT_5 | BIT_4)) >> 4;
0107109e
AV		 5079
5080 memcpy(ha->fw_seriallink_options24, nv->seriallink_options,
5081 sizeof(ha->fw_seriallink_options24));
5082
5083 /* save HBA serial number */
5084 ha->serial0 = icb->port_name[5];
5085 ha->serial1 = icb->port_name[6];
5086 ha->serial2 = icb->port_name[7];
e315cd28
AC		 5087 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
5088 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
0107109e 5089
bc8fb3cb
AV		 5090 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
5091
0107109e
AV		 5092 ha->retry_count = le16_to_cpu(nv->login_retry_count);
5093
5094 /* Set minimum login_timeout to 4 seconds. */
5095 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
5096 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
5097 if (le16_to_cpu(nv->login_timeout) < 4)
5098 nv->login_timeout = __constant_cpu_to_le16(4);
5099 ha->login_timeout = le16_to_cpu(nv->login_timeout);
c6852c4c 5100 icb->login_timeout = nv->login_timeout;
0107109e 5101
00a537b8
AV		 5102 /* Set minimum RATOV to 100 tenths of a second. */
5103 ha->r_a_tov = 100;
0107109e
AV		 5104
5105 ha->loop_reset_delay = nv->reset_delay;
5106
5107 /* Link Down Timeout = 0:
5108 *
5109 * When Port Down timer expires we will start returning
5110 * I/O's to OS with "DID_NO_CONNECT".
5111 *
5112 * Link Down Timeout != 0:
5113 *
5114 * The driver waits for the link to come up after link down
5115 * before returning I/Os to OS with "DID_NO_CONNECT".
5116 */
5117 if (le16_to_cpu(nv->link_down_timeout) == 0) {
5118 ha->loop_down_abort_time =
5119 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
5120 } else {
5121 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
5122 ha->loop_down_abort_time =
5123 (LOOP_DOWN_TIME - ha->link_down_timeout);
5124 }
5125
5126 /* Need enough time to try and get the port back. */
5127 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
5128 if (qlport_down_retry)
5129 ha->port_down_retry_count = qlport_down_retry;
5130
5131 /* Set login_retry_count */
5132 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
5133 if (ha->port_down_retry_count ==
5134 le16_to_cpu(nv->port_down_retry_count) &&
5135 ha->port_down_retry_count > 3)
5136 ha->login_retry_count = ha->port_down_retry_count;
5137 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
5138 ha->login_retry_count = ha->port_down_retry_count;
5139 if (ql2xloginretrycount)
5140 ha->login_retry_count = ql2xloginretrycount;
5141
4fdfefe5 5142 /* Enable ZIO. */
e315cd28 5143 if (!vha->flags.init_done) {
4fdfefe5
AV		 5144 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
5145 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
5146 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
5147 le16_to_cpu(icb->interrupt_delay_timer): 2;
5148 }
5149 icb->firmware_options_2 &= __constant_cpu_to_le32(
5150 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
e315cd28 5151 vha->flags.process_response_queue = 0;
4fdfefe5 5152 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d
AV		 5153 ha->zio_mode = QLA_ZIO_MODE_6;
5154
7c3df132 5155 ql_log(ql_log_info, vha, 0x006f,
4fdfefe5
AV		 5156 "ZIO mode %d enabled; timer delay (%d us).\n",
5157 ha->zio_mode, ha->zio_timer * 100);
5158
5159 icb->firmware_options_2 |= cpu_to_le32(
5160 (uint32_t)ha->zio_mode);
5161 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
e315cd28 5162 vha->flags.process_response_queue = 1;
4fdfefe5
AV		 5163 }
5164
4e08df3f 5165 if (rval) {
7c3df132
SK		 5166 ql_log(ql_log_warn, vha, 0x0070,
5167 "NVRAM configuration failed.\n");
4e08df3f
DM		 5168 }
5169 return (rval);
0107109e
AV		 5170}
5171
413975a0 5172static int
cbc8eb67
AV		 5173qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
5174 uint32_t faddr)
d1c61909 5175{
73208dfd 5176 int rval = QLA_SUCCESS;
d1c61909 5177 int segments, fragment;
d1c61909
AV		 5178 uint32_t *dcode, dlen;
5179 uint32_t risc_addr;
5180 uint32_t risc_size;
5181 uint32_t i;
e315cd28 5182 struct qla_hw_data *ha = vha->hw;
73208dfd 5183 struct req_que *req = ha->req_q_map[0];
eaac30be 5184
7c3df132 5185 ql_dbg(ql_dbg_init, vha, 0x008b,
cfb0919c 5186 "FW: Loading firmware from flash (%x).\n", faddr);
eaac30be 5187
d1c61909
AV		 5188 rval = QLA_SUCCESS;
5189
5190 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 5191 dcode = (uint32_t *)req->ring;
d1c61909
AV		 5192 *srisc_addr = 0;
5193
5194 /* Validate firmware image by checking version. */
e315cd28 5195 qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
d1c61909
AV		 5196 for (i = 0; i < 4; i++)
5197 dcode[i] = be32_to_cpu(dcode[i]);
5198 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
5199 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
5200 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
5201 dcode[3] == 0)) {
7c3df132
SK		 5202 ql_log(ql_log_fatal, vha, 0x008c,
5203 "Unable to verify the integrity of flash firmware "
5204 "image.\n");
5205 ql_log(ql_log_fatal, vha, 0x008d,
5206 "Firmware data: %08x %08x %08x %08x.\n",
5207 dcode[0], dcode[1], dcode[2], dcode[3]);
d1c61909
AV		 5208
5209 return QLA_FUNCTION_FAILED;
5210 }
5211
5212 while (segments && rval == QLA_SUCCESS) {
5213 /* Read segment's load information. */
e315cd28 5214 qla24xx_read_flash_data(vha, dcode, faddr, 4);
d1c61909
AV		 5215
5216 risc_addr = be32_to_cpu(dcode[2]);
5217 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
5218 risc_size = be32_to_cpu(dcode[3]);
5219
5220 fragment = 0;
5221 while (risc_size > 0 && rval == QLA_SUCCESS) {
5222 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
5223 if (dlen > risc_size)
5224 dlen = risc_size;
5225
7c3df132
SK		 5226 ql_dbg(ql_dbg_init, vha, 0x008e,
5227 "Loading risc segment@ risc addr %x "
5228 "number of dwords 0x%x offset 0x%x.\n",
5229 risc_addr, dlen, faddr);
d1c61909 5230
e315cd28 5231 qla24xx_read_flash_data(vha, dcode, faddr, dlen);
d1c61909
AV		 5232 for (i = 0; i < dlen; i++)
5233 dcode[i] = swab32(dcode[i]);
5234
73208dfd 5235 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
d1c61909
AV		 5236 dlen);
5237 if (rval) {
7c3df132
SK		 5238 ql_log(ql_log_fatal, vha, 0x008f,
5239 "Failed to load segment %d of firmware.\n",
5240 fragment);
f261f7af 5241 return QLA_FUNCTION_FAILED;
d1c61909
AV		 5242 }
5243
5244 faddr += dlen;
5245 risc_addr += dlen;
5246 risc_size -= dlen;
5247 fragment++;
5248 }
5249
5250 /* Next segment. */
5251 segments--;
5252 }
5253
f73cb695
CD		 5254 if (!IS_QLA27XX(ha))
5255 return rval;
5256
5257 if (ha->fw_dump_template)
5258 vfree(ha->fw_dump_template);
5259 ha->fw_dump_template = NULL;
5260 ha->fw_dump_template_len = 0;
5261
5262 ql_dbg(ql_dbg_init, vha, 0x0161,
5263 "Loading fwdump template from %x\n", faddr);
5264 qla24xx_read_flash_data(vha, dcode, faddr, 7);
5265 risc_size = be32_to_cpu(dcode[2]);
5266 ql_dbg(ql_dbg_init, vha, 0x0162,
5267 "-> array size %x dwords\n", risc_size);
5268 if (risc_size == 0 || risc_size == ~0)
5269 goto default_template;
5270
5271 dlen = (risc_size - 8) * sizeof(*dcode);
5272 ql_dbg(ql_dbg_init, vha, 0x0163,
5273 "-> template allocating %x bytes...\n", dlen);
5274 ha->fw_dump_template = vmalloc(dlen);
5275 if (!ha->fw_dump_template) {
5276 ql_log(ql_log_warn, vha, 0x0164,
5277 "Failed fwdump template allocate %x bytes.\n", risc_size);
5278 goto default_template;
5279 }
5280
5281 faddr += 7;
5282 risc_size -= 8;
5283 dcode = ha->fw_dump_template;
5284 qla24xx_read_flash_data(vha, dcode, faddr, risc_size);
5285 for (i = 0; i < risc_size; i++)
5286 dcode[i] = le32_to_cpu(dcode[i]);
5287
5288 if (!qla27xx_fwdt_template_valid(dcode)) {
5289 ql_log(ql_log_warn, vha, 0x0165,
5290 "Failed fwdump template validate\n");
5291 goto default_template;
5292 }
5293
5294 dlen = qla27xx_fwdt_template_size(dcode);
5295 ql_dbg(ql_dbg_init, vha, 0x0166,
5296 "-> template size %x bytes\n", dlen);
5297 if (dlen > risc_size * sizeof(*dcode)) {
5298 ql_log(ql_log_warn, vha, 0x0167,
97ea702b
CD		 5299 "Failed fwdump template exceeds array by %x bytes\n",
5300 (uint32_t)(dlen - risc_size * sizeof(*dcode)));
f73cb695
CD		 5301 goto default_template;
5302 }
5303 ha->fw_dump_template_len = dlen;
5304 return rval;
5305
5306default_template:
5307 ql_log(ql_log_warn, vha, 0x0168, "Using default fwdump template\n");
5308 if (ha->fw_dump_template)
5309 vfree(ha->fw_dump_template);
5310 ha->fw_dump_template = NULL;
5311 ha->fw_dump_template_len = 0;
5312
5313 dlen = qla27xx_fwdt_template_default_size();
5314 ql_dbg(ql_dbg_init, vha, 0x0169,
5315 "-> template allocating %x bytes...\n", dlen);
5316 ha->fw_dump_template = vmalloc(dlen);
5317 if (!ha->fw_dump_template) {
5318 ql_log(ql_log_warn, vha, 0x016a,
5319 "Failed fwdump template allocate %x bytes.\n", risc_size);
5320 goto failed_template;
5321 }
5322
5323 dcode = ha->fw_dump_template;
5324 risc_size = dlen / sizeof(*dcode);
5325 memcpy(dcode, qla27xx_fwdt_template_default(), dlen);
5326 for (i = 0; i < risc_size; i++)
5327 dcode[i] = be32_to_cpu(dcode[i]);
5328
5329 if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) {
5330 ql_log(ql_log_warn, vha, 0x016b,
5331 "Failed fwdump template validate\n");
5332 goto failed_template;
5333 }
5334
5335 dlen = qla27xx_fwdt_template_size(ha->fw_dump_template);
5336 ql_dbg(ql_dbg_init, vha, 0x016c,
5337 "-> template size %x bytes\n", dlen);
5338 ha->fw_dump_template_len = dlen;
5339 return rval;
5340
5341failed_template:
5342 ql_log(ql_log_warn, vha, 0x016d, "Failed default fwdump template\n");
5343 if (ha->fw_dump_template)
5344 vfree(ha->fw_dump_template);
5345 ha->fw_dump_template = NULL;
5346 ha->fw_dump_template_len = 0;
d1c61909
AV		 5347 return rval;
5348}
5349
e9454a88 5350#define QLA_FW_URL "http://ldriver.qlogic.com/firmware/"
d1c61909 5351
0107109e 5352int
e315cd28 5353qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5433383e
AV		 5354{
5355 int rval;
5356 int i, fragment;
5357 uint16_t *wcode, *fwcode;
5358 uint32_t risc_addr, risc_size, fwclen, wlen, *seg;
5359 struct fw_blob *blob;
e315cd28 5360 struct qla_hw_data *ha = vha->hw;
73208dfd 5361 struct req_que *req = ha->req_q_map[0];
5433383e
AV		 5362
5363 /* Load firmware blob. */
e315cd28 5364 blob = qla2x00_request_firmware(vha);
5433383e 5365 if (!blob) {
7c3df132
SK		 5366 ql_log(ql_log_info, vha, 0x0083,
5367 "Fimware image unavailable.\n");
5368 ql_log(ql_log_info, vha, 0x0084,
5369 "Firmware images can be retrieved from: "QLA_FW_URL ".\n");
5433383e
AV		 5370 return QLA_FUNCTION_FAILED;
5371 }
5372
5373 rval = QLA_SUCCESS;
5374
73208dfd 5375 wcode = (uint16_t *)req->ring;
5433383e
AV		 5376 *srisc_addr = 0;
5377 fwcode = (uint16_t *)blob->fw->data;
5378 fwclen = 0;
5379
5380 /* Validate firmware image by checking version. */
5381 if (blob->fw->size < 8 * sizeof(uint16_t)) {
7c3df132
SK		 5382 ql_log(ql_log_fatal, vha, 0x0085,
5383 "Unable to verify integrity of firmware image (%Zd).\n",
5433383e
AV		 5384 blob->fw->size);
5385 goto fail_fw_integrity;
5386 }
5387 for (i = 0; i < 4; i++)
5388 wcode[i] = be16_to_cpu(fwcode[i + 4]);
5389 if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff &&
5390 wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 &&
5391 wcode[2] == 0 && wcode[3] == 0)) {
7c3df132
SK		 5392 ql_log(ql_log_fatal, vha, 0x0086,
5393 "Unable to verify integrity of firmware image.\n");
5394 ql_log(ql_log_fatal, vha, 0x0087,
5395 "Firmware data: %04x %04x %04x %04x.\n",
5396 wcode[0], wcode[1], wcode[2], wcode[3]);
5433383e
AV		 5397 goto fail_fw_integrity;
5398 }
5399
5400 seg = blob->segs;
5401 while (*seg && rval == QLA_SUCCESS) {
5402 risc_addr = *seg;
5403 *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr;
5404 risc_size = be16_to_cpu(fwcode[3]);
5405
5406 /* Validate firmware image size. */
5407 fwclen += risc_size * sizeof(uint16_t);
5408 if (blob->fw->size < fwclen) {
7c3df132 5409 ql_log(ql_log_fatal, vha, 0x0088,
5433383e 5410 "Unable to verify integrity of firmware image "
7c3df132 5411 "(%Zd).\n", blob->fw->size);
5433383e
AV		 5412 goto fail_fw_integrity;
5413 }
5414
5415 fragment = 0;
5416 while (risc_size > 0 && rval == QLA_SUCCESS) {
5417 wlen = (uint16_t)(ha->fw_transfer_size >> 1);
5418 if (wlen > risc_size)
5419 wlen = risc_size;
7c3df132
SK		 5420 ql_dbg(ql_dbg_init, vha, 0x0089,
5421 "Loading risc segment@ risc addr %x number of "
5422 "words 0x%x.\n", risc_addr, wlen);
5433383e
AV		 5423
5424 for (i = 0; i < wlen; i++)
5425 wcode[i] = swab16(fwcode[i]);
5426
73208dfd 5427 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
5433383e
AV		 5428 wlen);
5429 if (rval) {
7c3df132
SK		 5430 ql_log(ql_log_fatal, vha, 0x008a,
5431 "Failed to load segment %d of firmware.\n",
5432 fragment);
5433383e
AV		 5433 break;
5434 }
5435
5436 fwcode += wlen;
5437 risc_addr += wlen;
5438 risc_size -= wlen;
5439 fragment++;
5440 }
5441
5442 /* Next segment. */
5443 seg++;
5444 }
5445 return rval;
5446
5447fail_fw_integrity:
5448 return QLA_FUNCTION_FAILED;
5449}
5450
eaac30be
AV		 5451static int
5452qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
0107109e
AV		 5453{
5454 int rval;
5455 int segments, fragment;
5456 uint32_t *dcode, dlen;
5457 uint32_t risc_addr;
5458 uint32_t risc_size;
5459 uint32_t i;
5433383e 5460 struct fw_blob *blob;
f73cb695
CD		 5461 const uint32_t *fwcode;
5462 uint32_t fwclen;
e315cd28 5463 struct qla_hw_data *ha = vha->hw;
73208dfd 5464 struct req_que *req = ha->req_q_map[0];
0107109e 5465
5433383e 5466 /* Load firmware blob. */
e315cd28 5467 blob = qla2x00_request_firmware(vha);
5433383e 5468 if (!blob) {
7c3df132
SK		 5469 ql_log(ql_log_warn, vha, 0x0090,
5470 "Fimware image unavailable.\n");
5471 ql_log(ql_log_warn, vha, 0x0091,
5472 "Firmware images can be retrieved from: "
5473 QLA_FW_URL ".\n");
d1c61909 5474
eaac30be 5475 return QLA_FUNCTION_FAILED;
0107109e
AV		 5476 }
5477
cfb0919c
CD		 5478 ql_dbg(ql_dbg_init, vha, 0x0092,
5479 "FW: Loading via request-firmware.\n");
eaac30be 5480
0107109e
AV		 5481 rval = QLA_SUCCESS;
5482
5483 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 5484 dcode = (uint32_t *)req->ring;
0107109e 5485 *srisc_addr = 0;
5433383e 5486 fwcode = (uint32_t *)blob->fw->data;
0107109e
AV		 5487 fwclen = 0;
5488
5489 /* Validate firmware image by checking version. */
5433383e 5490 if (blob->fw->size < 8 * sizeof(uint32_t)) {
7c3df132
SK		 5491 ql_log(ql_log_fatal, vha, 0x0093,
5492 "Unable to verify integrity of firmware image (%Zd).\n",
5433383e 5493 blob->fw->size);
f73cb695 5494 return QLA_FUNCTION_FAILED;
0107109e
AV		 5495 }
5496 for (i = 0; i < 4; i++)
5497 dcode[i] = be32_to_cpu(fwcode[i + 4]);
5498 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
5499 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
5500 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
5501 dcode[3] == 0)) {
7c3df132
SK		 5502 ql_log(ql_log_fatal, vha, 0x0094,
5503 "Unable to verify integrity of firmware image (%Zd).\n",
5504 blob->fw->size);
5505 ql_log(ql_log_fatal, vha, 0x0095,
5506 "Firmware data: %08x %08x %08x %08x.\n",
5507 dcode[0], dcode[1], dcode[2], dcode[3]);
f73cb695 5508 return QLA_FUNCTION_FAILED;
0107109e
AV		 5509 }
5510
5511 while (segments && rval == QLA_SUCCESS) {
5512 risc_addr = be32_to_cpu(fwcode[2]);
5513 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
5514 risc_size = be32_to_cpu(fwcode[3]);
5515
5516 /* Validate firmware image size. */
5517 fwclen += risc_size * sizeof(uint32_t);
5433383e 5518 if (blob->fw->size < fwclen) {
7c3df132 5519 ql_log(ql_log_fatal, vha, 0x0096,
5433383e 5520 "Unable to verify integrity of firmware image "
7c3df132 5521 "(%Zd).\n", blob->fw->size);
f73cb695 5522 return QLA_FUNCTION_FAILED;
0107109e
AV		 5523 }
5524
5525 fragment = 0;
5526 while (risc_size > 0 && rval == QLA_SUCCESS) {
5527 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
5528 if (dlen > risc_size)
5529 dlen = risc_size;
5530
7c3df132
SK		 5531 ql_dbg(ql_dbg_init, vha, 0x0097,
5532 "Loading risc segment@ risc addr %x "
5533 "number of dwords 0x%x.\n", risc_addr, dlen);
0107109e
AV		 5534
5535 for (i = 0; i < dlen; i++)
5536 dcode[i] = swab32(fwcode[i]);
5537
73208dfd 5538 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
590f98e5 5539 dlen);
0107109e 5540 if (rval) {
7c3df132
SK		 5541 ql_log(ql_log_fatal, vha, 0x0098,
5542 "Failed to load segment %d of firmware.\n",
5543 fragment);
f261f7af 5544 return QLA_FUNCTION_FAILED;
0107109e
AV		 5545 }
5546
5547 fwcode += dlen;
5548 risc_addr += dlen;
5549 risc_size -= dlen;
5550 fragment++;
5551 }
5552
5553 /* Next segment. */
5554 segments--;
5555 }
f73cb695
CD		 5556
5557 if (!IS_QLA27XX(ha))
5558 return rval;
5559
5560 if (ha->fw_dump_template)
5561 vfree(ha->fw_dump_template);
5562 ha->fw_dump_template = NULL;
5563 ha->fw_dump_template_len = 0;
5564
5565 ql_dbg(ql_dbg_init, vha, 0x171,
97ea702b
CD		 5566 "Loading fwdump template from %x\n",
5567 (uint32_t)((void *)fwcode - (void *)blob->fw->data));
f73cb695
CD		 5568 risc_size = be32_to_cpu(fwcode[2]);
5569 ql_dbg(ql_dbg_init, vha, 0x172,
5570 "-> array size %x dwords\n", risc_size);
5571 if (risc_size == 0 || risc_size == ~0)
5572 goto default_template;
5573
5574 dlen = (risc_size - 8) * sizeof(*fwcode);
5575 ql_dbg(ql_dbg_init, vha, 0x0173,
5576 "-> template allocating %x bytes...\n", dlen);
5577 ha->fw_dump_template = vmalloc(dlen);
5578 if (!ha->fw_dump_template) {
5579 ql_log(ql_log_warn, vha, 0x0174,
5580 "Failed fwdump template allocate %x bytes.\n", risc_size);
5581 goto default_template;
5582 }
5583
5584 fwcode += 7;
5585 risc_size -= 8;
5586 dcode = ha->fw_dump_template;
5587 for (i = 0; i < risc_size; i++)
5588 dcode[i] = le32_to_cpu(fwcode[i]);
5589
5590 if (!qla27xx_fwdt_template_valid(dcode)) {
5591 ql_log(ql_log_warn, vha, 0x0175,
5592 "Failed fwdump template validate\n");
5593 goto default_template;
5594 }
5595
5596 dlen = qla27xx_fwdt_template_size(dcode);
5597 ql_dbg(ql_dbg_init, vha, 0x0176,
5598 "-> template size %x bytes\n", dlen);
5599 if (dlen > risc_size * sizeof(*fwcode)) {
5600 ql_log(ql_log_warn, vha, 0x0177,
97ea702b
CD		 5601 "Failed fwdump template exceeds array by %x bytes\n",
5602 (uint32_t)(dlen - risc_size * sizeof(*fwcode)));
f73cb695
CD		 5603 goto default_template;
5604 }
5605 ha->fw_dump_template_len = dlen;
0107109e
AV		 5606 return rval;
5607
f73cb695
CD		 5608default_template:
5609 ql_log(ql_log_warn, vha, 0x0178, "Using default fwdump template\n");
5610 if (ha->fw_dump_template)
5611 vfree(ha->fw_dump_template);
5612 ha->fw_dump_template = NULL;
5613 ha->fw_dump_template_len = 0;
5614
5615 dlen = qla27xx_fwdt_template_default_size();
5616 ql_dbg(ql_dbg_init, vha, 0x0179,
5617 "-> template allocating %x bytes...\n", dlen);
5618 ha->fw_dump_template = vmalloc(dlen);
5619 if (!ha->fw_dump_template) {
5620 ql_log(ql_log_warn, vha, 0x017a,
5621 "Failed fwdump template allocate %x bytes.\n", risc_size);
5622 goto failed_template;
5623 }
5624
5625 dcode = ha->fw_dump_template;
5626 risc_size = dlen / sizeof(*fwcode);
5627 fwcode = qla27xx_fwdt_template_default();
5628 for (i = 0; i < risc_size; i++)
5629 dcode[i] = be32_to_cpu(fwcode[i]);
5630
5631 if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) {
5632 ql_log(ql_log_warn, vha, 0x017b,
5633 "Failed fwdump template validate\n");
5634 goto failed_template;
5635 }
5636
5637 dlen = qla27xx_fwdt_template_size(ha->fw_dump_template);
5638 ql_dbg(ql_dbg_init, vha, 0x017c,
5639 "-> template size %x bytes\n", dlen);
5640 ha->fw_dump_template_len = dlen;
5641 return rval;
5642
5643failed_template:
5644 ql_log(ql_log_warn, vha, 0x017d, "Failed default fwdump template\n");
5645 if (ha->fw_dump_template)
5646 vfree(ha->fw_dump_template);
5647 ha->fw_dump_template = NULL;
5648 ha->fw_dump_template_len = 0;
5649 return rval;
0107109e 5650}
18c6c127 5651
eaac30be
AV		 5652int
5653qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5654{
5655 int rval;
5656
e337d907
AV		 5657 if (ql2xfwloadbin == 1)
5658 return qla81xx_load_risc(vha, srisc_addr);
5659
eaac30be
AV		 5660 /*
5661 * FW Load priority:
5662 * 1) Firmware via request-firmware interface (.bin file).
5663 * 2) Firmware residing in flash.
5664 */
5665 rval = qla24xx_load_risc_blob(vha, srisc_addr);
5666 if (rval == QLA_SUCCESS)
5667 return rval;
5668
cbc8eb67
AV		 5669 return qla24xx_load_risc_flash(vha, srisc_addr,
5670 vha->hw->flt_region_fw);
eaac30be
AV		 5671}
5672
5673int
5674qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5675{
5676 int rval;
cbc8eb67 5677 struct qla_hw_data *ha = vha->hw;
eaac30be 5678
e337d907 5679 if (ql2xfwloadbin == 2)
cbc8eb67 5680 goto try_blob_fw;
e337d907 5681
eaac30be
AV		 5682 /*
5683 * FW Load priority:
5684 * 1) Firmware residing in flash.
5685 * 2) Firmware via request-firmware interface (.bin file).
cbc8eb67 5686 * 3) Golden-Firmware residing in flash -- limited operation.
eaac30be 5687 */
cbc8eb67 5688 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
eaac30be
AV		 5689 if (rval == QLA_SUCCESS)
5690 return rval;
5691
cbc8eb67
AV		 5692try_blob_fw:
5693 rval = qla24xx_load_risc_blob(vha, srisc_addr);
5694 if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw)
5695 return rval;
5696
7c3df132
SK		 5697 ql_log(ql_log_info, vha, 0x0099,
5698 "Attempting to fallback to golden firmware.\n");
cbc8eb67
AV		 5699 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
5700 if (rval != QLA_SUCCESS)
5701 return rval;
5702
7c3df132 5703 ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n");
cbc8eb67 5704 ha->flags.running_gold_fw = 1;
cbc8eb67 5705 return rval;
eaac30be
AV		 5706}
5707
18c6c127 5708void
e315cd28 5709qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha)
18c6c127
AV		 5710{
5711 int ret, retries;
e315cd28 5712 struct qla_hw_data *ha = vha->hw;
18c6c127 5713
85880801
AV		 5714 if (ha->flags.pci_channel_io_perm_failure)
5715 return;
e428924c 5716 if (!IS_FWI2_CAPABLE(ha))
18c6c127 5717 return;
75edf81d
AV		 5718 if (!ha->fw_major_version)
5719 return;
18c6c127 5720
e315cd28 5721 ret = qla2x00_stop_firmware(vha);
7c7f1f29 5722 for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&
b469a7cb 5723 ret != QLA_INVALID_COMMAND && retries ; retries--) {
e315cd28
AC		 5724 ha->isp_ops->reset_chip(vha);
5725 if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS)
18c6c127 5726 continue;
e315cd28 5727 if (qla2x00_setup_chip(vha) != QLA_SUCCESS)
18c6c127 5728 continue;
7c3df132
SK		 5729 ql_log(ql_log_info, vha, 0x8015,
5730 "Attempting retry of stop-firmware command.\n");
e315cd28 5731 ret = qla2x00_stop_firmware(vha);
18c6c127
AV		 5732 }
5733}
2c3dfe3f
SJ		 5734
5735int
e315cd28 5736qla24xx_configure_vhba(scsi_qla_host_t *vha)
2c3dfe3f
SJ		 5737{
5738 int rval = QLA_SUCCESS;
0b91d116 5739 int rval2;
2c3dfe3f 5740 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28
AC		 5741 struct qla_hw_data *ha = vha->hw;
5742 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
67c2e93a
AC		 5743 struct req_que *req;
5744 struct rsp_que *rsp;
2c3dfe3f 5745
e315cd28 5746 if (!vha->vp_idx)
2c3dfe3f
SJ		 5747 return -EINVAL;
5748
e315cd28 5749 rval = qla2x00_fw_ready(base_vha);
7163ea81 5750 if (ha->flags.cpu_affinity_enabled)
67c2e93a
AC		 5751 req = ha->req_q_map[0];
5752 else
5753 req = vha->req;
5754 rsp = req->rsp;
5755
2c3dfe3f 5756 if (rval == QLA_SUCCESS) {
e315cd28 5757 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
73208dfd 5758 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
2c3dfe3f
SJ		 5759 }
5760
e315cd28 5761 vha->flags.management_server_logged_in = 0;
2c3dfe3f
SJ		 5762
5763 /* Login to SNS first */
0b91d116
CD		 5764 rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb,
5765 BIT_1);
5766 if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
5767 if (rval2 == QLA_MEMORY_ALLOC_FAILED)
5768 ql_dbg(ql_dbg_init, vha, 0x0120,
5769 "Failed SNS login: loop_id=%x, rval2=%d\n",
5770 NPH_SNS, rval2);
5771 else
5772 ql_dbg(ql_dbg_init, vha, 0x0103,
5773 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x "
5774 "mb[2]=%x mb[6]=%x mb[7]=%x.\n",
5775 NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]);
2c3dfe3f
SJ		 5776 return (QLA_FUNCTION_FAILED);
5777 }
5778
e315cd28
AC		 5779 atomic_set(&vha->loop_down_timer, 0);
5780 atomic_set(&vha->loop_state, LOOP_UP);
5781 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5782 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
5783 rval = qla2x00_loop_resync(base_vha);
2c3dfe3f
SJ		 5784
5785 return rval;
5786}
4d4df193
HK		 5787
5788/* 84XX Support **************************************************************/
5789
5790static LIST_HEAD(qla_cs84xx_list);
5791static DEFINE_MUTEX(qla_cs84xx_mutex);
5792
5793static struct qla_chip_state_84xx *
e315cd28 5794qla84xx_get_chip(struct scsi_qla_host *vha)
4d4df193
HK		 5795{
5796 struct qla_chip_state_84xx *cs84xx;
e315cd28 5797 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5798
5799 mutex_lock(&qla_cs84xx_mutex);
5800
5801 /* Find any shared 84xx chip. */
5802 list_for_each_entry(cs84xx, &qla_cs84xx_list, list) {
5803 if (cs84xx->bus == ha->pdev->bus) {
5804 kref_get(&cs84xx->kref);
5805 goto done;
5806 }
5807 }
5808
5809 cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL);
5810 if (!cs84xx)
5811 goto done;
5812
5813 kref_init(&cs84xx->kref);
5814 spin_lock_init(&cs84xx->access_lock);
5815 mutex_init(&cs84xx->fw_update_mutex);
5816 cs84xx->bus = ha->pdev->bus;
5817
5818 list_add_tail(&cs84xx->list, &qla_cs84xx_list);
5819done:
5820 mutex_unlock(&qla_cs84xx_mutex);
5821 return cs84xx;
5822}
5823
5824static void
5825__qla84xx_chip_release(struct kref *kref)
5826{
5827 struct qla_chip_state_84xx *cs84xx =
5828 container_of(kref, struct qla_chip_state_84xx, kref);
5829
5830 mutex_lock(&qla_cs84xx_mutex);
5831 list_del(&cs84xx->list);
5832 mutex_unlock(&qla_cs84xx_mutex);
5833 kfree(cs84xx);
5834}
5835
5836void
e315cd28 5837qla84xx_put_chip(struct scsi_qla_host *vha)
4d4df193 5838{
e315cd28 5839 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5840 if (ha->cs84xx)
5841 kref_put(&ha->cs84xx->kref, __qla84xx_chip_release);
5842}
5843
5844static int
e315cd28 5845qla84xx_init_chip(scsi_qla_host_t *vha)
4d4df193
HK		 5846{
5847 int rval;
5848 uint16_t status[2];
e315cd28 5849 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5850
5851 mutex_lock(&ha->cs84xx->fw_update_mutex);
5852
e315cd28 5853 rval = qla84xx_verify_chip(vha, status);
4d4df193
HK		 5854
5855 mutex_unlock(&ha->cs84xx->fw_update_mutex);
5856
5857 return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED:
5858 QLA_SUCCESS;
5859}
3a03eb79
AV		 5860
5861/* 81XX Support **************************************************************/
5862
5863int
5864qla81xx_nvram_config(scsi_qla_host_t *vha)
5865{
5866 int rval;
5867 struct init_cb_81xx *icb;
5868 struct nvram_81xx *nv;
5869 uint32_t *dptr;
5870 uint8_t *dptr1, *dptr2;
5871 uint32_t chksum;
5872 uint16_t cnt;
5873 struct qla_hw_data *ha = vha->hw;
5874
5875 rval = QLA_SUCCESS;
5876 icb = (struct init_cb_81xx *)ha->init_cb;
5877 nv = ha->nvram;
5878
5879 /* Determine NVRAM starting address. */
5880 ha->nvram_size = sizeof(struct nvram_81xx);
3a03eb79 5881 ha->vpd_size = FA_NVRAM_VPD_SIZE;
7ec0effd
AD		 5882 if (IS_P3P_TYPE(ha) || IS_QLA8031(ha))
5883 ha->vpd_size = FA_VPD_SIZE_82XX;
3a03eb79
AV		 5884
5885 /* Get VPD data into cache */
5886 ha->vpd = ha->nvram + VPD_OFFSET;
3d79038f
AV		 5887 ha->isp_ops->read_optrom(vha, ha->vpd, ha->flt_region_vpd << 2,
5888 ha->vpd_size);
3a03eb79
AV		 5889
5890 /* Get NVRAM data into cache and calculate checksum. */
3d79038f 5891 ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2,
3a03eb79 5892 ha->nvram_size);
3d79038f 5893 dptr = (uint32_t *)nv;
3a03eb79
AV		 5894 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
5895 chksum += le32_to_cpu(*dptr++);
5896
7c3df132
SK		 5897 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
5898 "Contents of NVRAM:\n");
5899 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
5900 (uint8_t *)nv, ha->nvram_size);
3a03eb79
AV		 5901
5902 /* Bad NVRAM data, set defaults parameters. */
5903 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
5904 || nv->id[3] != ' ' ||
5905 nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
5906 /* Reset NVRAM data. */
7c3df132 5907 ql_log(ql_log_info, vha, 0x0073,
9e336520 5908 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132 5909 "version=0x%x.\n", chksum, nv->id[0],
3a03eb79 5910 le16_to_cpu(nv->nvram_version));
7c3df132
SK		 5911 ql_log(ql_log_info, vha, 0x0074,
5912 "Falling back to functioning (yet invalid -- WWPN) "
5913 "defaults.\n");
3a03eb79
AV		 5914
5915 /*
5916 * Set default initialization control block.
5917 */
5918 memset(nv, 0, ha->nvram_size);
5919 nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
5920 nv->version = __constant_cpu_to_le16(ICB_VERSION);
98aee70d 5921 nv->frame_payload_size = 2048;
3a03eb79
AV		 5922 nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
5923 nv->exchange_count = __constant_cpu_to_le16(0);
5924 nv->port_name[0] = 0x21;
f73cb695 5925 nv->port_name[1] = 0x00 + ha->port_no + 1;
3a03eb79
AV		 5926 nv->port_name[2] = 0x00;
5927 nv->port_name[3] = 0xe0;
5928 nv->port_name[4] = 0x8b;
5929 nv->port_name[5] = 0x1c;
5930 nv->port_name[6] = 0x55;
5931 nv->port_name[7] = 0x86;
5932 nv->node_name[0] = 0x20;
5933 nv->node_name[1] = 0x00;
5934 nv->node_name[2] = 0x00;
5935 nv->node_name[3] = 0xe0;
5936 nv->node_name[4] = 0x8b;
5937 nv->node_name[5] = 0x1c;
5938 nv->node_name[6] = 0x55;
5939 nv->node_name[7] = 0x86;
5940 nv->login_retry_count = __constant_cpu_to_le16(8);
5941 nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
5942 nv->login_timeout = __constant_cpu_to_le16(0);
5943 nv->firmware_options_1 =
5944 __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
5945 nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
5946 nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
5947 nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
5948 nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
5949 nv->efi_parameters = __constant_cpu_to_le32(0);
5950 nv->reset_delay = 5;
5951 nv->max_luns_per_target = __constant_cpu_to_le16(128);
5952 nv->port_down_retry_count = __constant_cpu_to_le16(30);
6246b8a1 5953 nv->link_down_timeout = __constant_cpu_to_le16(180);
eeebcc92 5954 nv->enode_mac[0] = 0x00;
6246b8a1
GM		 5955 nv->enode_mac[1] = 0xC0;
5956 nv->enode_mac[2] = 0xDD;
3a03eb79
AV		 5957 nv->enode_mac[3] = 0x04;
5958 nv->enode_mac[4] = 0x05;
f73cb695 5959 nv->enode_mac[5] = 0x06 + ha->port_no + 1;
3a03eb79
AV		 5960
5961 rval = 1;
5962 }
5963
9e522cd8
AE		 5964 if (IS_T10_PI_CAPABLE(ha))
5965 nv->frame_payload_size &= ~7;
5966
aa230bc5
AE		 5967 qlt_81xx_config_nvram_stage1(vha, nv);
5968
3a03eb79 5969 /* Reset Initialization control block */
773120e4 5970 memset(icb, 0, ha->init_cb_size);
3a03eb79
AV		 5971
5972 /* Copy 1st segment. */
5973 dptr1 = (uint8_t *)icb;
5974 dptr2 = (uint8_t *)&nv->version;
5975 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
5976 while (cnt--)
5977 *dptr1++ = *dptr2++;
5978
5979 icb->login_retry_count = nv->login_retry_count;
5980
5981 /* Copy 2nd segment. */
5982 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
5983 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
5984 cnt = (uint8_t *)&icb->reserved_5 -
5985 (uint8_t *)&icb->interrupt_delay_timer;
5986 while (cnt--)
5987 *dptr1++ = *dptr2++;
5988
5989 memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac));
5990 /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */
5991 if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) {
69e5f1ea
AV		 5992 icb->enode_mac[0] = 0x00;
5993 icb->enode_mac[1] = 0xC0;
5994 icb->enode_mac[2] = 0xDD;
3a03eb79
AV		 5995 icb->enode_mac[3] = 0x04;
5996 icb->enode_mac[4] = 0x05;
f73cb695 5997 icb->enode_mac[5] = 0x06 + ha->port_no + 1;
3a03eb79
AV		 5998 }
5999
b64b0e8f
AV		 6000 /* Use extended-initialization control block. */
6001 memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb));
6002
3a03eb79
AV		 6003 /*
6004 * Setup driver NVRAM options.
6005 */
6006 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
a9083016 6007 "QLE8XXX");
3a03eb79 6008
aa230bc5
AE		 6009 qlt_81xx_config_nvram_stage2(vha, icb);
6010
3a03eb79
AV		 6011 /* Use alternate WWN? */
6012 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
6013 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
6014 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
6015 }
6016
6017 /* Prepare nodename */
6018 if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
6019 /*
6020 * Firmware will apply the following mask if the nodename was
6021 * not provided.
6022 */
6023 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
6024 icb->node_name[0] &= 0xF0;
6025 }
6026
6027 /* Set host adapter parameters. */
6028 ha->flags.disable_risc_code_load = 0;
6029 ha->flags.enable_lip_reset = 0;
6030 ha->flags.enable_lip_full_login =
6031 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
6032 ha->flags.enable_target_reset =
6033 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
6034 ha->flags.enable_led_scheme = 0;
6035 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
6036
6037 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
6038 (BIT_6 | BIT_5 | BIT_4)) >> 4;
6039
6040 /* save HBA serial number */
6041 ha->serial0 = icb->port_name[5];
6042 ha->serial1 = icb->port_name[6];
6043 ha->serial2 = icb->port_name[7];
6044 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
6045 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
6046
6047 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
6048
6049 ha->retry_count = le16_to_cpu(nv->login_retry_count);
6050
6051 /* Set minimum login_timeout to 4 seconds. */
6052 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
6053 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
6054 if (le16_to_cpu(nv->login_timeout) < 4)
6055 nv->login_timeout = __constant_cpu_to_le16(4);
6056 ha->login_timeout = le16_to_cpu(nv->login_timeout);
6057 icb->login_timeout = nv->login_timeout;
6058
6059 /* Set minimum RATOV to 100 tenths of a second. */
6060 ha->r_a_tov = 100;
6061
6062 ha->loop_reset_delay = nv->reset_delay;
6063
6064 /* Link Down Timeout = 0:
6065 *
7ec0effd 6066 * When Port Down timer expires we will start returning
3a03eb79
AV		 6067 * I/O's to OS with "DID_NO_CONNECT".
6068 *
6069 * Link Down Timeout != 0:
6070 *
6071 * The driver waits for the link to come up after link down
6072 * before returning I/Os to OS with "DID_NO_CONNECT".
6073 */
6074 if (le16_to_cpu(nv->link_down_timeout) == 0) {
6075 ha->loop_down_abort_time =
6076 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
6077 } else {
6078 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
6079 ha->loop_down_abort_time =
6080 (LOOP_DOWN_TIME - ha->link_down_timeout);
6081 }
6082
6083 /* Need enough time to try and get the port back. */
6084 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
6085 if (qlport_down_retry)
6086 ha->port_down_retry_count = qlport_down_retry;
6087
6088 /* Set login_retry_count */
6089 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
6090 if (ha->port_down_retry_count ==
6091 le16_to_cpu(nv->port_down_retry_count) &&
6092 ha->port_down_retry_count > 3)
6093 ha->login_retry_count = ha->port_down_retry_count;
6094 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
6095 ha->login_retry_count = ha->port_down_retry_count;
6096 if (ql2xloginretrycount)
6097 ha->login_retry_count = ql2xloginretrycount;
6098
6246b8a1 6099 /* if not running MSI-X we need handshaking on interrupts */
f73cb695 6100 if (!vha->hw->flags.msix_enabled && (IS_QLA83XX(ha) || IS_QLA27XX(ha)))
6246b8a1
GM		 6101 icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_22);
6102
3a03eb79
AV		 6103 /* Enable ZIO. */
6104 if (!vha->flags.init_done) {
6105 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
6106 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
6107 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
6108 le16_to_cpu(icb->interrupt_delay_timer): 2;
6109 }
6110 icb->firmware_options_2 &= __constant_cpu_to_le32(
6111 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
6112 vha->flags.process_response_queue = 0;
6113 if (ha->zio_mode != QLA_ZIO_DISABLED) {
6114 ha->zio_mode = QLA_ZIO_MODE_6;
6115
7c3df132 6116 ql_log(ql_log_info, vha, 0x0075,
3a03eb79 6117 "ZIO mode %d enabled; timer delay (%d us).\n",
7c3df132
SK		 6118 ha->zio_mode,
6119 ha->zio_timer * 100);
3a03eb79
AV		 6120
6121 icb->firmware_options_2 |= cpu_to_le32(
6122 (uint32_t)ha->zio_mode);
6123 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
6124 vha->flags.process_response_queue = 1;
6125 }
6126
6127 if (rval) {
7c3df132
SK		 6128 ql_log(ql_log_warn, vha, 0x0076,
6129 "NVRAM configuration failed.\n");
3a03eb79
AV		 6130 }
6131 return (rval);
6132}
6133
a9083016
GM		 6134int
6135qla82xx_restart_isp(scsi_qla_host_t *vha)
6136{
6137 int status, rval;
a9083016
GM		 6138 struct qla_hw_data *ha = vha->hw;
6139 struct req_que *req = ha->req_q_map[0];
6140 struct rsp_que *rsp = ha->rsp_q_map[0];
6141 struct scsi_qla_host *vp;
feafb7b1 6142 unsigned long flags;
a9083016
GM		 6143
6144 status = qla2x00_init_rings(vha);
6145 if (!status) {
6146 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
6147 ha->flags.chip_reset_done = 1;
6148
6149 status = qla2x00_fw_ready(vha);
6150 if (!status) {
a9083016
GM		 6151 /* Issue a marker after FW becomes ready. */
6152 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
a9083016 6153 vha->flags.online = 1;
7108b76e 6154 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
a9083016
GM		 6155 }
6156
6157 /* if no cable then assume it's good */
6158 if ((vha->device_flags & DFLG_NO_CABLE))
6159 status = 0;
a9083016
GM		 6160 }
6161
6162 if (!status) {
6163 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
6164
6165 if (!atomic_read(&vha->loop_down_timer)) {
6166 /*
6167 * Issue marker command only when we are going
6168 * to start the I/O .
6169 */
6170 vha->marker_needed = 1;
6171 }
6172
a9083016
GM		 6173 ha->isp_ops->enable_intrs(ha);
6174
6175 ha->isp_abort_cnt = 0;
6176 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
6177
53296788 6178 /* Update the firmware version */
3173167f 6179 status = qla82xx_check_md_needed(vha);
53296788 6180
a9083016
GM		 6181 if (ha->fce) {
6182 ha->flags.fce_enabled = 1;
6183 memset(ha->fce, 0,
6184 fce_calc_size(ha->fce_bufs));
6185 rval = qla2x00_enable_fce_trace(vha,
6186 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
6187 &ha->fce_bufs);
6188 if (rval) {
cfb0919c 6189 ql_log(ql_log_warn, vha, 0x8001,
7c3df132
SK		 6190 "Unable to reinitialize FCE (%d).\n",
6191 rval);
a9083016
GM		 6192 ha->flags.fce_enabled = 0;
6193 }
6194 }
6195
6196 if (ha->eft) {
6197 memset(ha->eft, 0, EFT_SIZE);
6198 rval = qla2x00_enable_eft_trace(vha,
6199 ha->eft_dma, EFT_NUM_BUFFERS);
6200 if (rval) {
cfb0919c 6201 ql_log(ql_log_warn, vha, 0x8010,
7c3df132
SK		 6202 "Unable to reinitialize EFT (%d).\n",
6203 rval);
a9083016
GM		 6204 }
6205 }
a9083016
GM		 6206 }
6207
6208 if (!status) {
cfb0919c 6209 ql_dbg(ql_dbg_taskm, vha, 0x8011,
7c3df132 6210 "qla82xx_restart_isp succeeded.\n");
feafb7b1
AE		 6211
6212 spin_lock_irqsave(&ha->vport_slock, flags);
6213 list_for_each_entry(vp, &ha->vp_list, list) {
6214 if (vp->vp_idx) {
6215 atomic_inc(&vp->vref_count);
6216 spin_unlock_irqrestore(&ha->vport_slock, flags);
6217
a9083016 6218 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 6219
6220 spin_lock_irqsave(&ha->vport_slock, flags);
6221 atomic_dec(&vp->vref_count);
6222 }
a9083016 6223 }
feafb7b1
AE		 6224 spin_unlock_irqrestore(&ha->vport_slock, flags);
6225
a9083016 6226 } else {
cfb0919c 6227 ql_log(ql_log_warn, vha, 0x8016,
7c3df132 6228 "qla82xx_restart_isp **** FAILED ****.\n");
a9083016
GM		 6229 }
6230
6231 return status;
6232}
6233
3a03eb79 6234void
ae97c91e 6235qla81xx_update_fw_options(scsi_qla_host_t *vha)
3a03eb79 6236{
ae97c91e
AV		 6237 struct qla_hw_data *ha = vha->hw;
6238
6239 if (!ql2xetsenable)
6240 return;
6241
6242 /* Enable ETS Burst. */
6243 memset(ha->fw_options, 0, sizeof(ha->fw_options));
6244 ha->fw_options[2] |= BIT_9;
6245 qla2x00_set_fw_options(vha, ha->fw_options);
3a03eb79 6246}
09ff701a
SR		 6247
6248/*
6249 * qla24xx_get_fcp_prio
6250 * Gets the fcp cmd priority value for the logged in port.
6251 * Looks for a match of the port descriptors within
6252 * each of the fcp prio config entries. If a match is found,
6253 * the tag (priority) value is returned.
6254 *
6255 * Input:
21090cbe 6256 * vha = scsi host structure pointer.
09ff701a
SR		 6257 * fcport = port structure pointer.
6258 *
6259 * Return:
6c452a45 6260 * non-zero (if found)
f28a0a96 6261 * -1 (if not found)
09ff701a
SR		 6262 *
6263 * Context:
6264 * Kernel context
6265 */
f28a0a96 6266static int
09ff701a
SR		 6267qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
6268{
6269 int i, entries;
6270 uint8_t pid_match, wwn_match;
f28a0a96 6271 int priority;
09ff701a
SR		 6272 uint32_t pid1, pid2;
6273 uint64_t wwn1, wwn2;
6274 struct qla_fcp_prio_entry *pri_entry;
6275 struct qla_hw_data *ha = vha->hw;
6276
6277 if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled)
f28a0a96 6278 return -1;
09ff701a 6279
f28a0a96 6280 priority = -1;
09ff701a
SR		 6281 entries = ha->fcp_prio_cfg->num_entries;
6282 pri_entry = &ha->fcp_prio_cfg->entry[0];
6283
6284 for (i = 0; i < entries; i++) {
6285 pid_match = wwn_match = 0;
6286
6287 if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) {
6288 pri_entry++;
6289 continue;
6290 }
6291
6292 /* check source pid for a match */
6293 if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) {
6294 pid1 = pri_entry->src_pid & INVALID_PORT_ID;
6295 pid2 = vha->d_id.b24 & INVALID_PORT_ID;
6296 if (pid1 == INVALID_PORT_ID)
6297 pid_match++;
6298 else if (pid1 == pid2)
6299 pid_match++;
6300 }
6301
6302 /* check destination pid for a match */
6303 if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) {
6304 pid1 = pri_entry->dst_pid & INVALID_PORT_ID;
6305 pid2 = fcport->d_id.b24 & INVALID_PORT_ID;
6306 if (pid1 == INVALID_PORT_ID)
6307 pid_match++;
6308 else if (pid1 == pid2)
6309 pid_match++;
6310 }
6311
6312 /* check source WWN for a match */
6313 if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) {
6314 wwn1 = wwn_to_u64(vha->port_name);
6315 wwn2 = wwn_to_u64(pri_entry->src_wwpn);
6316 if (wwn2 == (uint64_t)-1)
6317 wwn_match++;
6318 else if (wwn1 == wwn2)
6319 wwn_match++;
6320 }
6321
6322 /* check destination WWN for a match */
6323 if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) {
6324 wwn1 = wwn_to_u64(fcport->port_name);
6325 wwn2 = wwn_to_u64(pri_entry->dst_wwpn);
6326 if (wwn2 == (uint64_t)-1)
6327 wwn_match++;
6328 else if (wwn1 == wwn2)
6329 wwn_match++;
6330 }
6331
6332 if (pid_match == 2 || wwn_match == 2) {
6333 /* Found a matching entry */
6334 if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID)
6335 priority = pri_entry->tag;
6336 break;
6337 }
6338
6339 pri_entry++;
6340 }
6341
6342 return priority;
6343}
6344
6345/*
6346 * qla24xx_update_fcport_fcp_prio
6347 * Activates fcp priority for the logged in fc port
6348 *
6349 * Input:
21090cbe 6350 * vha = scsi host structure pointer.
09ff701a
SR		 6351 * fcp = port structure pointer.
6352 *
6353 * Return:
6354 * QLA_SUCCESS or QLA_FUNCTION_FAILED
6355 *
6356 * Context:
6357 * Kernel context.
6358 */
6359int
21090cbe 6360qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
09ff701a
SR		 6361{
6362 int ret;
f28a0a96 6363 int priority;
09ff701a
SR		 6364 uint16_t mb[5];
6365
21090cbe
MI		 6366 if (fcport->port_type != FCT_TARGET ||
6367 fcport->loop_id == FC_NO_LOOP_ID)
09ff701a
SR		 6368 return QLA_FUNCTION_FAILED;
6369
21090cbe 6370 priority = qla24xx_get_fcp_prio(vha, fcport);
f28a0a96
AV		 6371 if (priority < 0)
6372 return QLA_FUNCTION_FAILED;
6373
7ec0effd 6374 if (IS_P3P_TYPE(vha->hw)) {
a00f6296
SK		 6375 fcport->fcp_prio = priority & 0xf;
6376 return QLA_SUCCESS;
6377 }
6378
21090cbe 6379 ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb);
cfb0919c
CD		 6380 if (ret == QLA_SUCCESS) {
6381 if (fcport->fcp_prio != priority)
6382 ql_dbg(ql_dbg_user, vha, 0x709e,
6383 "Updated FCP_CMND priority - value=%d loop_id=%d "
6384 "port_id=%02x%02x%02x.\n", priority,
6385 fcport->loop_id, fcport->d_id.b.domain,
6386 fcport->d_id.b.area, fcport->d_id.b.al_pa);
a00f6296 6387 fcport->fcp_prio = priority & 0xf;
cfb0919c 6388 } else
7c3df132 6389 ql_dbg(ql_dbg_user, vha, 0x704f,
cfb0919c
CD		 6390 "Unable to update FCP_CMND priority - ret=0x%x for "
6391 "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id,
6392 fcport->d_id.b.domain, fcport->d_id.b.area,
6393 fcport->d_id.b.al_pa);
09ff701a
SR		 6394 return ret;
6395}
6396
6397/*
6398 * qla24xx_update_all_fcp_prio
6399 * Activates fcp priority for all the logged in ports
6400 *
6401 * Input:
6402 * ha = adapter block pointer.
6403 *
6404 * Return:
6405 * QLA_SUCCESS or QLA_FUNCTION_FAILED
6406 *
6407 * Context:
6408 * Kernel context.
6409 */
6410int
6411qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha)
6412{
6413 int ret;
6414 fc_port_t *fcport;
6415
6416 ret = QLA_FUNCTION_FAILED;
6417 /* We need to set priority for all logged in ports */
6418 list_for_each_entry(fcport, &vha->vp_fcports, list)
6419 ret = qla24xx_update_fcport_fcp_prio(vha, fcport);
6420
6421 return ret;
6422}
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