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qla2xxx: Free sysfs attributes for ISP27xx.
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / qla2xxx / qla_init.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
73208dfd 8#include "qla_gbl.h"
1da177e4
LT		 9
10#include <linux/delay.h>
5a0e3ad6 11#include <linux/slab.h>
0107109e 12#include <linux/vmalloc.h>
1da177e4
LT		 13
14#include "qla_devtbl.h"
15
4e08df3f
DM		 16#ifdef CONFIG_SPARC
17#include <asm/prom.h>
4e08df3f
DM		 18#endif
19
2d70c103
NB		 20#include <target/target_core_base.h>
21#include "qla_target.h"
22
1da177e4
LT		 23/*
24* QLogic ISP2x00 Hardware Support Function Prototypes.
25*/
1da177e4 26static int qla2x00_isp_firmware(scsi_qla_host_t *);
1da177e4 27static int qla2x00_setup_chip(scsi_qla_host_t *);
1da177e4
LT		 28static int qla2x00_fw_ready(scsi_qla_host_t *);
29static int qla2x00_configure_hba(scsi_qla_host_t *);
1da177e4
LT		 30static int qla2x00_configure_loop(scsi_qla_host_t *);
31static int qla2x00_configure_local_loop(scsi_qla_host_t *);
1da177e4
LT		 32static int qla2x00_configure_fabric(scsi_qla_host_t *);
33static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *, struct list_head *);
1da177e4
LT		 34static int qla2x00_fabric_dev_login(scsi_qla_host_t *, fc_port_t *,
35 uint16_t *);
1da177e4
LT		 36
37static int qla2x00_restart_isp(scsi_qla_host_t *);
1da177e4 38
4d4df193
HK		 39static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *);
40static int qla84xx_init_chip(scsi_qla_host_t *);
73208dfd 41static int qla25xx_init_queues(struct qla_hw_data *);
4d4df193 42
ac280b67
AV		 43/* SRB Extensions ---------------------------------------------------------- */
44
9ba56b95
GM		 45void
46qla2x00_sp_timeout(unsigned long __data)
ac280b67
AV		 47{
48 srb_t *sp = (srb_t *)__data;
4916392b 49 struct srb_iocb *iocb;
ac280b67
AV		 50 fc_port_t *fcport = sp->fcport;
51 struct qla_hw_data *ha = fcport->vha->hw;
52 struct req_que *req;
53 unsigned long flags;
54
55 spin_lock_irqsave(&ha->hardware_lock, flags);
56 req = ha->req_q_map[0];
57 req->outstanding_cmds[sp->handle] = NULL;
9ba56b95 58 iocb = &sp->u.iocb_cmd;
4916392b 59 iocb->timeout(sp);
9ba56b95 60 sp->free(fcport->vha, sp);
6ac52608 61 spin_unlock_irqrestore(&ha->hardware_lock, flags);
ac280b67
AV		 62}
63
9ba56b95
GM		 64void
65qla2x00_sp_free(void *data, void *ptr)
ac280b67 66{
9ba56b95
GM		 67 srb_t *sp = (srb_t *)ptr;
68 struct srb_iocb *iocb = &sp->u.iocb_cmd;
69 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
ac280b67 70
4d97cc53 71 del_timer(&iocb->timer);
b00ee7d7 72 qla2x00_rel_sp(vha, sp);
ac280b67
AV		 73}
74
ac280b67
AV		 75/* Asynchronous Login/Logout Routines -------------------------------------- */
76
a9b6f722 77unsigned long
5b91490e
AV		 78qla2x00_get_async_timeout(struct scsi_qla_host *vha)
79{
80 unsigned long tmo;
81 struct qla_hw_data *ha = vha->hw;
82
83 /* Firmware should use switch negotiated r_a_tov for timeout. */
84 tmo = ha->r_a_tov / 10 * 2;
8ae6d9c7
GM		 85 if (IS_QLAFX00(ha)) {
86 tmo = FX00_DEF_RATOV * 2;
87 } else if (!IS_FWI2_CAPABLE(ha)) {
5b91490e
AV		 88 /*
89 * Except for earlier ISPs where the timeout is seeded from the
90 * initialization control block.
91 */
92 tmo = ha->login_timeout;
93 }
94 return tmo;
95}
ac280b67
AV		 96
97static void
9ba56b95 98qla2x00_async_iocb_timeout(void *data)
ac280b67 99{
9ba56b95 100 srb_t *sp = (srb_t *)data;
ac280b67 101 fc_port_t *fcport = sp->fcport;
ac280b67 102
7c3df132 103 ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
cfb0919c 104 "Async-%s timeout - hdl=%x portid=%02x%02x%02x.\n",
9ba56b95 105 sp->name, sp->handle, fcport->d_id.b.domain, fcport->d_id.b.area,
7c3df132 106 fcport->d_id.b.al_pa);
ac280b67 107
5ff1d584 108 fcport->flags &= ~FCF_ASYNC_SENT;
9ba56b95
GM		 109 if (sp->type == SRB_LOGIN_CMD) {
110 struct srb_iocb *lio = &sp->u.iocb_cmd;
ac280b67 111 qla2x00_post_async_logout_work(fcport->vha, fcport, NULL);
6ac52608
AV		 112 /* Retry as needed. */
113 lio->u.logio.data[0] = MBS_COMMAND_ERROR;
114 lio->u.logio.data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
115 QLA_LOGIO_LOGIN_RETRIED : 0;
116 qla2x00_post_async_login_done_work(fcport->vha, fcport,
117 lio->u.logio.data);
118 }
ac280b67
AV		 119}
120
99b0bec7 121static void
9ba56b95 122qla2x00_async_login_sp_done(void *data, void *ptr, int res)
99b0bec7 123{
9ba56b95
GM		 124 srb_t *sp = (srb_t *)ptr;
125 struct srb_iocb *lio = &sp->u.iocb_cmd;
126 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
127
128 if (!test_bit(UNLOADING, &vha->dpc_flags))
129 qla2x00_post_async_login_done_work(sp->fcport->vha, sp->fcport,
130 lio->u.logio.data);
131 sp->free(sp->fcport->vha, sp);
99b0bec7
AV		 132}
133
ac280b67
AV		 134int
135qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport,
136 uint16_t *data)
137{
ac280b67 138 srb_t *sp;
4916392b 139 struct srb_iocb *lio;
ac280b67
AV		 140 int rval;
141
142 rval = QLA_FUNCTION_FAILED;
9ba56b95 143 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 144 if (!sp)
145 goto done;
146
9ba56b95
GM		 147 sp->type = SRB_LOGIN_CMD;
148 sp->name = "login";
149 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
150
151 lio = &sp->u.iocb_cmd;
3822263e 152 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 153 sp->done = qla2x00_async_login_sp_done;
4916392b 154 lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI;
ac280b67 155 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 156 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
ac280b67
AV		 157 rval = qla2x00_start_sp(sp);
158 if (rval != QLA_SUCCESS)
159 goto done_free_sp;
160
7c3df132 161 ql_dbg(ql_dbg_disc, vha, 0x2072,
cfb0919c
CD		 162 "Async-login - hdl=%x, loopid=%x portid=%02x%02x%02x "
163 "retries=%d.\n", sp->handle, fcport->loop_id,
164 fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
165 fcport->login_retry);
ac280b67
AV		 166 return rval;
167
168done_free_sp:
9ba56b95 169 sp->free(fcport->vha, sp);
ac280b67
AV		 170done:
171 return rval;
172}
173
99b0bec7 174static void
9ba56b95 175qla2x00_async_logout_sp_done(void *data, void *ptr, int res)
99b0bec7 176{
9ba56b95
GM		 177 srb_t *sp = (srb_t *)ptr;
178 struct srb_iocb *lio = &sp->u.iocb_cmd;
179 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
180
181 if (!test_bit(UNLOADING, &vha->dpc_flags))
182 qla2x00_post_async_logout_done_work(sp->fcport->vha, sp->fcport,
183 lio->u.logio.data);
184 sp->free(sp->fcport->vha, sp);
99b0bec7
AV		 185}
186
ac280b67
AV		 187int
188qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport)
189{
ac280b67 190 srb_t *sp;
4916392b 191 struct srb_iocb *lio;
ac280b67
AV		 192 int rval;
193
194 rval = QLA_FUNCTION_FAILED;
9ba56b95 195 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 196 if (!sp)
197 goto done;
198
9ba56b95
GM		 199 sp->type = SRB_LOGOUT_CMD;
200 sp->name = "logout";
201 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
202
203 lio = &sp->u.iocb_cmd;
3822263e 204 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 205 sp->done = qla2x00_async_logout_sp_done;
ac280b67
AV		 206 rval = qla2x00_start_sp(sp);
207 if (rval != QLA_SUCCESS)
208 goto done_free_sp;
209
7c3df132 210 ql_dbg(ql_dbg_disc, vha, 0x2070,
cfb0919c
CD		 211 "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
212 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
213 fcport->d_id.b.area, fcport->d_id.b.al_pa);
ac280b67
AV		 214 return rval;
215
216done_free_sp:
9ba56b95 217 sp->free(fcport->vha, sp);
ac280b67
AV		 218done:
219 return rval;
220}
221
5ff1d584 222static void
9ba56b95 223qla2x00_async_adisc_sp_done(void *data, void *ptr, int res)
5ff1d584 224{
9ba56b95
GM		 225 srb_t *sp = (srb_t *)ptr;
226 struct srb_iocb *lio = &sp->u.iocb_cmd;
227 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
228
229 if (!test_bit(UNLOADING, &vha->dpc_flags))
230 qla2x00_post_async_adisc_done_work(sp->fcport->vha, sp->fcport,
231 lio->u.logio.data);
232 sp->free(sp->fcport->vha, sp);
5ff1d584
AV		 233}
234
235int
236qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport,
237 uint16_t *data)
238{
5ff1d584 239 srb_t *sp;
4916392b 240 struct srb_iocb *lio;
5ff1d584
AV		 241 int rval;
242
243 rval = QLA_FUNCTION_FAILED;
9ba56b95 244 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
5ff1d584
AV		 245 if (!sp)
246 goto done;
247
9ba56b95
GM		 248 sp->type = SRB_ADISC_CMD;
249 sp->name = "adisc";
250 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
251
252 lio = &sp->u.iocb_cmd;
3822263e 253 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 254 sp->done = qla2x00_async_adisc_sp_done;
5ff1d584 255 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 256 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
5ff1d584
AV		 257 rval = qla2x00_start_sp(sp);
258 if (rval != QLA_SUCCESS)
259 goto done_free_sp;
260
7c3df132 261 ql_dbg(ql_dbg_disc, vha, 0x206f,
cfb0919c
CD		 262 "Async-adisc - hdl=%x loopid=%x portid=%02x%02x%02x.\n",
263 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
264 fcport->d_id.b.area, fcport->d_id.b.al_pa);
5ff1d584
AV		 265 return rval;
266
267done_free_sp:
9ba56b95 268 sp->free(fcport->vha, sp);
5ff1d584
AV		 269done:
270 return rval;
271}
272
3822263e 273static void
faef62d1 274qla2x00_tmf_iocb_timeout(void *data)
3822263e 275{
faef62d1
AB		 276 srb_t *sp = (srb_t *)data;
277 struct srb_iocb *tmf = &sp->u.iocb_cmd;
3822263e 278
faef62d1
AB		 279 tmf->u.tmf.comp_status = CS_TIMEOUT;
280 complete(&tmf->u.tmf.comp);
281}
9ba56b95 282
faef62d1
AB		 283static void
284qla2x00_tmf_sp_done(void *data, void *ptr, int res)
285{
286 srb_t *sp = (srb_t *)ptr;
287 struct srb_iocb *tmf = &sp->u.iocb_cmd;
288 complete(&tmf->u.tmf.comp);
3822263e
MI		 289}
290
291int
faef62d1 292qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t flags, uint32_t lun,
3822263e
MI		 293 uint32_t tag)
294{
295 struct scsi_qla_host *vha = fcport->vha;
faef62d1 296 struct srb_iocb *tm_iocb;
3822263e 297 srb_t *sp;
faef62d1 298 int rval = QLA_FUNCTION_FAILED;
3822263e 299
9ba56b95 300 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
3822263e
MI		 301 if (!sp)
302 goto done;
303
faef62d1 304 tm_iocb = &sp->u.iocb_cmd;
9ba56b95
GM		 305 sp->type = SRB_TM_CMD;
306 sp->name = "tmf";
faef62d1
AB		 307 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
308 tm_iocb->u.tmf.flags = flags;
309 tm_iocb->u.tmf.lun = lun;
310 tm_iocb->u.tmf.data = tag;
311 sp->done = qla2x00_tmf_sp_done;
312 tm_iocb->timeout = qla2x00_tmf_iocb_timeout;
313 init_completion(&tm_iocb->u.tmf.comp);
3822263e
MI		 314
315 rval = qla2x00_start_sp(sp);
316 if (rval != QLA_SUCCESS)
317 goto done_free_sp;
318
7c3df132 319 ql_dbg(ql_dbg_taskm, vha, 0x802f,
cfb0919c
CD		 320 "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
321 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
322 fcport->d_id.b.area, fcport->d_id.b.al_pa);
faef62d1
AB		 323
324 wait_for_completion(&tm_iocb->u.tmf.comp);
325
326 rval = tm_iocb->u.tmf.comp_status == CS_COMPLETE ?
327 QLA_SUCCESS : QLA_FUNCTION_FAILED;
328
329 if ((rval != QLA_SUCCESS) || tm_iocb->u.tmf.data) {
330 ql_dbg(ql_dbg_taskm, vha, 0x8030,
331 "TM IOCB failed (%x).\n", rval);
332 }
333
334 if (!test_bit(UNLOADING, &vha->dpc_flags) && !IS_QLAFX00(vha->hw)) {
335 flags = tm_iocb->u.tmf.flags;
336 lun = (uint16_t)tm_iocb->u.tmf.lun;
337
338 /* Issue Marker IOCB */
339 qla2x00_marker(vha, vha->hw->req_q_map[0],
340 vha->hw->rsp_q_map[0], sp->fcport->loop_id, lun,
341 flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
342 }
3822263e
MI		 343
344done_free_sp:
faef62d1 345 sp->free(vha, sp);
3822263e
MI		 346done:
347 return rval;
348}
349
4440e46d
AB		 350static void
351qla24xx_abort_iocb_timeout(void *data)
352{
353 srb_t *sp = (srb_t *)data;
354 struct srb_iocb *abt = &sp->u.iocb_cmd;
355
356 abt->u.abt.comp_status = CS_TIMEOUT;
357 complete(&abt->u.abt.comp);
358}
359
360static void
361qla24xx_abort_sp_done(void *data, void *ptr, int res)
362{
363 srb_t *sp = (srb_t *)ptr;
364 struct srb_iocb *abt = &sp->u.iocb_cmd;
365
366 complete(&abt->u.abt.comp);
367}
368
369static int
370qla24xx_async_abort_cmd(srb_t *cmd_sp)
371{
372 scsi_qla_host_t *vha = cmd_sp->fcport->vha;
373 fc_port_t *fcport = cmd_sp->fcport;
374 struct srb_iocb *abt_iocb;
375 srb_t *sp;
376 int rval = QLA_FUNCTION_FAILED;
377
378 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
379 if (!sp)
380 goto done;
381
382 abt_iocb = &sp->u.iocb_cmd;
383 sp->type = SRB_ABT_CMD;
384 sp->name = "abort";
385 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
386 abt_iocb->u.abt.cmd_hndl = cmd_sp->handle;
387 sp->done = qla24xx_abort_sp_done;
388 abt_iocb->timeout = qla24xx_abort_iocb_timeout;
389 init_completion(&abt_iocb->u.abt.comp);
390
391 rval = qla2x00_start_sp(sp);
392 if (rval != QLA_SUCCESS)
393 goto done_free_sp;
394
395 ql_dbg(ql_dbg_async, vha, 0x507c,
396 "Abort command issued - hdl=%x, target_id=%x\n",
397 cmd_sp->handle, fcport->tgt_id);
398
399 wait_for_completion(&abt_iocb->u.abt.comp);
400
401 rval = abt_iocb->u.abt.comp_status == CS_COMPLETE ?
402 QLA_SUCCESS : QLA_FUNCTION_FAILED;
403
404done_free_sp:
405 sp->free(vha, sp);
406done:
407 return rval;
408}
409
410int
411qla24xx_async_abort_command(srb_t *sp)
412{
413 unsigned long flags = 0;
414
415 uint32_t handle;
416 fc_port_t *fcport = sp->fcport;
417 struct scsi_qla_host *vha = fcport->vha;
418 struct qla_hw_data *ha = vha->hw;
419 struct req_que *req = vha->req;
420
421 spin_lock_irqsave(&ha->hardware_lock, flags);
422 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
423 if (req->outstanding_cmds[handle] == sp)
424 break;
425 }
426 spin_unlock_irqrestore(&ha->hardware_lock, flags);
427 if (handle == req->num_outstanding_cmds) {
428 /* Command not found. */
429 return QLA_FUNCTION_FAILED;
430 }
431 if (sp->type == SRB_FXIOCB_DCMD)
432 return qlafx00_fx_disc(vha, &vha->hw->mr.fcport,
433 FXDISC_ABORT_IOCTL);
434
435 return qla24xx_async_abort_cmd(sp);
436}
437
4916392b 438void
ac280b67
AV		 439qla2x00_async_login_done(struct scsi_qla_host *vha, fc_port_t *fcport,
440 uint16_t *data)
441{
442 int rval;
ac280b67
AV		 443
444 switch (data[0]) {
445 case MBS_COMMAND_COMPLETE:
a4f92a32
AV		 446 /*
447 * Driver must validate login state - If PRLI not complete,
448 * force a relogin attempt via implicit LOGO, PLOGI, and PRLI
449 * requests.
450 */
451 rval = qla2x00_get_port_database(vha, fcport, 0);
0eba25df
AE		 452 if (rval == QLA_NOT_LOGGED_IN) {
453 fcport->flags &= ~FCF_ASYNC_SENT;
454 fcport->flags |= FCF_LOGIN_NEEDED;
455 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
456 break;
457 }
458
a4f92a32
AV		 459 if (rval != QLA_SUCCESS) {
460 qla2x00_post_async_logout_work(vha, fcport, NULL);
461 qla2x00_post_async_login_work(vha, fcport, NULL);
462 break;
463 }
99b0bec7 464 if (fcport->flags & FCF_FCP2_DEVICE) {
5ff1d584
AV		 465 qla2x00_post_async_adisc_work(vha, fcport, data);
466 break;
99b0bec7
AV		 467 }
468 qla2x00_update_fcport(vha, fcport);
ac280b67
AV		 469 break;
470 case MBS_COMMAND_ERROR:
5ff1d584 471 fcport->flags &= ~FCF_ASYNC_SENT;
ac280b67
AV		 472 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
473 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
474 else
80d79440 475 qla2x00_mark_device_lost(vha, fcport, 1, 0);
ac280b67
AV		 476 break;
477 case MBS_PORT_ID_USED:
478 fcport->loop_id = data[1];
6ac52608 479 qla2x00_post_async_logout_work(vha, fcport, NULL);
ac280b67
AV		 480 qla2x00_post_async_login_work(vha, fcport, NULL);
481 break;
482 case MBS_LOOP_ID_USED:
483 fcport->loop_id++;
484 rval = qla2x00_find_new_loop_id(vha, fcport);
485 if (rval != QLA_SUCCESS) {
5ff1d584 486 fcport->flags &= ~FCF_ASYNC_SENT;
80d79440 487 qla2x00_mark_device_lost(vha, fcport, 1, 0);
ac280b67
AV		 488 break;
489 }
490 qla2x00_post_async_login_work(vha, fcport, NULL);
491 break;
492 }
4916392b 493 return;
ac280b67
AV		 494}
495
4916392b 496void
ac280b67
AV		 497qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport,
498 uint16_t *data)
499{
500 qla2x00_mark_device_lost(vha, fcport, 1, 0);
4916392b 501 return;
ac280b67
AV		 502}
503
4916392b 504void
5ff1d584
AV		 505qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport,
506 uint16_t *data)
507{
508 if (data[0] == MBS_COMMAND_COMPLETE) {
509 qla2x00_update_fcport(vha, fcport);
510
4916392b 511 return;
5ff1d584
AV		 512 }
513
514 /* Retry login. */
515 fcport->flags &= ~FCF_ASYNC_SENT;
516 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
517 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
518 else
80d79440 519 qla2x00_mark_device_lost(vha, fcport, 1, 0);
5ff1d584 520
4916392b 521 return;
5ff1d584
AV		 522}
523
1da177e4
LT		 524/****************************************************************************/
525/* QLogic ISP2x00 Hardware Support Functions. */
526/****************************************************************************/
527
fa492630 528static int
7d613ac6
SV		 529qla83xx_nic_core_fw_load(scsi_qla_host_t *vha)
530{
531 int rval = QLA_SUCCESS;
532 struct qla_hw_data *ha = vha->hw;
533 uint32_t idc_major_ver, idc_minor_ver;
711aa7f7 534 uint16_t config[4];
7d613ac6
SV		 535
536 qla83xx_idc_lock(vha, 0);
537
538 /* SV: TODO: Assign initialization timeout from
539 * flash-info / other param
540 */
541 ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT;
542 ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT;
543
544 /* Set our fcoe function presence */
545 if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) {
546 ql_dbg(ql_dbg_p3p, vha, 0xb077,
547 "Error while setting DRV-Presence.\n");
548 rval = QLA_FUNCTION_FAILED;
549 goto exit;
550 }
551
552 /* Decide the reset ownership */
553 qla83xx_reset_ownership(vha);
554
555 /*
556 * On first protocol driver load:
557 * Init-Owner: Set IDC-Major-Version and Clear IDC-Lock-Recovery
558 * register.
559 * Others: Check compatibility with current IDC Major version.
560 */
561 qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver);
562 if (ha->flags.nic_core_reset_owner) {
563 /* Set IDC Major version */
564 idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION;
565 qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver);
566
567 /* Clearing IDC-Lock-Recovery register */
568 qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0);
569 } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) {
570 /*
571 * Clear further IDC participation if we are not compatible with
572 * the current IDC Major Version.
573 */
574 ql_log(ql_log_warn, vha, 0xb07d,
575 "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n",
576 idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION);
577 __qla83xx_clear_drv_presence(vha);
578 rval = QLA_FUNCTION_FAILED;
579 goto exit;
580 }
581 /* Each function sets its supported Minor version. */
582 qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver);
583 idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2));
584 qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver);
585
711aa7f7
SK		 586 if (ha->flags.nic_core_reset_owner) {
587 memset(config, 0, sizeof(config));
588 if (!qla81xx_get_port_config(vha, config))
589 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
590 QLA8XXX_DEV_READY);
591 }
592
7d613ac6
SV		 593 rval = qla83xx_idc_state_handler(vha);
594
595exit:
596 qla83xx_idc_unlock(vha, 0);
597
598 return rval;
599}
600
1da177e4
LT		 601/*
602* qla2x00_initialize_adapter
603* Initialize board.
604*
605* Input:
606* ha = adapter block pointer.
607*
608* Returns:
609* 0 = success
610*/
611int
e315cd28 612qla2x00_initialize_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 613{
614 int rval;
e315cd28 615 struct qla_hw_data *ha = vha->hw;
73208dfd 616 struct req_que *req = ha->req_q_map[0];
2533cf67 617
1da177e4 618 /* Clear adapter flags. */
e315cd28 619 vha->flags.online = 0;
2533cf67 620 ha->flags.chip_reset_done = 0;
e315cd28 621 vha->flags.reset_active = 0;
85880801
AV		 622 ha->flags.pci_channel_io_perm_failure = 0;
623 ha->flags.eeh_busy = 0;
fabbb8df 624 vha->qla_stats.jiffies_at_last_reset = get_jiffies_64();
e315cd28
AC		 625 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
626 atomic_set(&vha->loop_state, LOOP_DOWN);
627 vha->device_flags = DFLG_NO_CABLE;
628 vha->dpc_flags = 0;
629 vha->flags.management_server_logged_in = 0;
630 vha->marker_needed = 0;
1da177e4
LT		 631 ha->isp_abort_cnt = 0;
632 ha->beacon_blink_led = 0;
633
73208dfd
AC		 634 set_bit(0, ha->req_qid_map);
635 set_bit(0, ha->rsp_qid_map);
636
cfb0919c 637 ql_dbg(ql_dbg_init, vha, 0x0040,
7c3df132 638 "Configuring PCI space...\n");
e315cd28 639 rval = ha->isp_ops->pci_config(vha);
1da177e4 640 if (rval) {
7c3df132
SK		 641 ql_log(ql_log_warn, vha, 0x0044,
642 "Unable to configure PCI space.\n");
1da177e4
LT		 643 return (rval);
644 }
645
e315cd28 646 ha->isp_ops->reset_chip(vha);
1da177e4 647
e315cd28 648 rval = qla2xxx_get_flash_info(vha);
c00d8994 649 if (rval) {
7c3df132
SK		 650 ql_log(ql_log_fatal, vha, 0x004f,
651 "Unable to validate FLASH data.\n");
7ec0effd
AD		 652 return rval;
653 }
654
655 if (IS_QLA8044(ha)) {
656 qla8044_read_reset_template(vha);
657
658 /* NOTE: If ql2xdontresethba==1, set IDC_CTRL DONTRESET_BIT0.
659 * If DONRESET_BIT0 is set, drivers should not set dev_state
660 * to NEED_RESET. But if NEED_RESET is set, drivers should
661 * should honor the reset. */
662 if (ql2xdontresethba == 1)
663 qla8044_set_idc_dontreset(vha);
c00d8994
AV		 664 }
665
73208dfd 666 ha->isp_ops->get_flash_version(vha, req->ring);
cfb0919c 667 ql_dbg(ql_dbg_init, vha, 0x0061,
7c3df132 668 "Configure NVRAM parameters...\n");
0107109e 669
e315cd28 670 ha->isp_ops->nvram_config(vha);
1da177e4 671
d4c760c2
AV		 672 if (ha->flags.disable_serdes) {
673 /* Mask HBA via NVRAM settings? */
7c3df132 674 ql_log(ql_log_info, vha, 0x0077,
7b833558 675 "Masking HBA WWPN %8phN (via NVRAM).\n", vha->port_name);
d4c760c2
AV		 676 return QLA_FUNCTION_FAILED;
677 }
678
cfb0919c 679 ql_dbg(ql_dbg_init, vha, 0x0078,
7c3df132 680 "Verifying loaded RISC code...\n");
1da177e4 681
e315cd28
AC		 682 if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) {
683 rval = ha->isp_ops->chip_diag(vha);
d19044c3
AV		 684 if (rval)
685 return (rval);
e315cd28 686 rval = qla2x00_setup_chip(vha);
d19044c3
AV		 687 if (rval)
688 return (rval);
1da177e4 689 }
a9083016 690
4d4df193 691 if (IS_QLA84XX(ha)) {
e315cd28 692 ha->cs84xx = qla84xx_get_chip(vha);
4d4df193 693 if (!ha->cs84xx) {
7c3df132 694 ql_log(ql_log_warn, vha, 0x00d0,
4d4df193
HK		 695 "Unable to configure ISP84XX.\n");
696 return QLA_FUNCTION_FAILED;
697 }
698 }
2d70c103
NB		 699
700 if (qla_ini_mode_enabled(vha))
701 rval = qla2x00_init_rings(vha);
702
2533cf67 703 ha->flags.chip_reset_done = 1;
1da177e4 704
9a069e19 705 if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) {
6c452a45 706 /* Issue verify 84xx FW IOCB to complete 84xx initialization */
9a069e19
GM		 707 rval = qla84xx_init_chip(vha);
708 if (rval != QLA_SUCCESS) {
7c3df132
SK		 709 ql_log(ql_log_warn, vha, 0x00d4,
710 "Unable to initialize ISP84XX.\n");
9a069e19
GM		 711 qla84xx_put_chip(vha);
712 }
713 }
714
7d613ac6
SV		 715 /* Load the NIC Core f/w if we are the first protocol driver. */
716 if (IS_QLA8031(ha)) {
717 rval = qla83xx_nic_core_fw_load(vha);
718 if (rval)
719 ql_log(ql_log_warn, vha, 0x0124,
720 "Error in initializing NIC Core f/w.\n");
721 }
722
2f0f3f4f
MI		 723 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
724 qla24xx_read_fcp_prio_cfg(vha);
09ff701a 725
c46e65c7
JC		 726 if (IS_P3P_TYPE(ha))
727 qla82xx_set_driver_version(vha, QLA2XXX_VERSION);
728 else
729 qla25xx_set_driver_version(vha, QLA2XXX_VERSION);
730
1da177e4
LT		 731 return (rval);
732}
733
734/**
abbd8870 735 * qla2100_pci_config() - Setup ISP21xx PCI configuration registers.
1da177e4
LT		 736 * @ha: HA context
737 *
738 * Returns 0 on success.
739 */
abbd8870 740int
e315cd28 741qla2100_pci_config(scsi_qla_host_t *vha)
1da177e4 742{
a157b101 743 uint16_t w;
abbd8870 744 unsigned long flags;
e315cd28 745 struct qla_hw_data *ha = vha->hw;
3d71644c 746 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 747
1da177e4 748 pci_set_master(ha->pdev);
af6177d8 749 pci_try_set_mwi(ha->pdev);
1da177e4 750
1da177e4 751 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 752 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
abbd8870
AV		 753 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
754
737faece 755 pci_disable_rom(ha->pdev);
1da177e4
LT		 756
757 /* Get PCI bus information. */
758 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 759 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
1da177e4
LT		 760 spin_unlock_irqrestore(&ha->hardware_lock, flags);
761
abbd8870
AV		 762 return QLA_SUCCESS;
763}
1da177e4 764
abbd8870
AV		 765/**
766 * qla2300_pci_config() - Setup ISP23xx PCI configuration registers.
767 * @ha: HA context
768 *
769 * Returns 0 on success.
770 */
771int
e315cd28 772qla2300_pci_config(scsi_qla_host_t *vha)
abbd8870 773{
a157b101 774 uint16_t w;
abbd8870
AV		 775 unsigned long flags = 0;
776 uint32_t cnt;
e315cd28 777 struct qla_hw_data *ha = vha->hw;
3d71644c 778 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 779
abbd8870 780 pci_set_master(ha->pdev);
af6177d8 781 pci_try_set_mwi(ha->pdev);
1da177e4 782
abbd8870 783 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 784 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
1da177e4 785
abbd8870
AV		 786 if (IS_QLA2322(ha) || IS_QLA6322(ha))
787 w &= ~PCI_COMMAND_INTX_DISABLE;
a157b101 788 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1da177e4 789
abbd8870
AV		 790 /*
791 * If this is a 2300 card and not 2312, reset the
792 * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately,
793 * the 2310 also reports itself as a 2300 so we need to get the
794 * fb revision level -- a 6 indicates it really is a 2300 and
795 * not a 2310.
796 */
797 if (IS_QLA2300(ha)) {
798 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 799
abbd8870 800 /* Pause RISC. */
3d71644c 801 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
abbd8870 802 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 803 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
abbd8870 804 break;
1da177e4 805
abbd8870
AV		 806 udelay(10);
807 }
1da177e4 808
abbd8870 809 /* Select FPM registers. */
3d71644c
AV		 810 WRT_REG_WORD(&reg->ctrl_status, 0x20);
811 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 812
813 /* Get the fb rev level */
3d71644c 814 ha->fb_rev = RD_FB_CMD_REG(ha, reg);
abbd8870
AV		 815
816 if (ha->fb_rev == FPM_2300)
a157b101 817 pci_clear_mwi(ha->pdev);
abbd8870
AV		 818
819 /* Deselect FPM registers. */
3d71644c
AV		 820 WRT_REG_WORD(&reg->ctrl_status, 0x0);
821 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 822
823 /* Release RISC module. */
3d71644c 824 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
abbd8870 825 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 826 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0)
abbd8870
AV		 827 break;
828
829 udelay(10);
1da177e4 830 }
1da177e4 831
abbd8870
AV		 832 spin_unlock_irqrestore(&ha->hardware_lock, flags);
833 }
1da177e4 834
abbd8870
AV		 835 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
836
737faece 837 pci_disable_rom(ha->pdev);
1da177e4 838
abbd8870
AV		 839 /* Get PCI bus information. */
840 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 841 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 842 spin_unlock_irqrestore(&ha->hardware_lock, flags);
843
844 return QLA_SUCCESS;
1da177e4
LT		 845}
846
0107109e
AV		 847/**
848 * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers.
849 * @ha: HA context
850 *
851 * Returns 0 on success.
852 */
853int
e315cd28 854qla24xx_pci_config(scsi_qla_host_t *vha)
0107109e 855{
a157b101 856 uint16_t w;
0107109e 857 unsigned long flags = 0;
e315cd28 858 struct qla_hw_data *ha = vha->hw;
0107109e 859 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
0107109e
AV		 860
861 pci_set_master(ha->pdev);
af6177d8 862 pci_try_set_mwi(ha->pdev);
0107109e
AV		 863
864 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 865 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
0107109e
AV		 866 w &= ~PCI_COMMAND_INTX_DISABLE;
867 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
868
869 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
870
871 /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */
f85ec187
AV		 872 if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
873 pcix_set_mmrbc(ha->pdev, 2048);
0107109e
AV		 874
875 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 876 if (pci_is_pcie(ha->pdev))
5ffd3a52 877 pcie_set_readrq(ha->pdev, 4096);
0107109e 878
737faece 879 pci_disable_rom(ha->pdev);
0107109e 880
44c10138 881 ha->chip_revision = ha->pdev->revision;
a8488abe 882
0107109e
AV		 883 /* Get PCI bus information. */
884 spin_lock_irqsave(&ha->hardware_lock, flags);
885 ha->pci_attr = RD_REG_DWORD(&reg->ctrl_status);
886 spin_unlock_irqrestore(&ha->hardware_lock, flags);
887
888 return QLA_SUCCESS;
889}
890
c3a2f0df
AV		 891/**
892 * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers.
893 * @ha: HA context
894 *
895 * Returns 0 on success.
896 */
897int
e315cd28 898qla25xx_pci_config(scsi_qla_host_t *vha)
c3a2f0df
AV		 899{
900 uint16_t w;
e315cd28 901 struct qla_hw_data *ha = vha->hw;
c3a2f0df
AV		 902
903 pci_set_master(ha->pdev);
904 pci_try_set_mwi(ha->pdev);
905
906 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
907 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
908 w &= ~PCI_COMMAND_INTX_DISABLE;
909 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
910
911 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 912 if (pci_is_pcie(ha->pdev))
5ffd3a52 913 pcie_set_readrq(ha->pdev, 4096);
c3a2f0df 914
737faece 915 pci_disable_rom(ha->pdev);
c3a2f0df
AV		 916
917 ha->chip_revision = ha->pdev->revision;
918
919 return QLA_SUCCESS;
920}
921
1da177e4
LT		 922/**
923 * qla2x00_isp_firmware() - Choose firmware image.
924 * @ha: HA context
925 *
926 * Returns 0 on success.
927 */
928static int
e315cd28 929qla2x00_isp_firmware(scsi_qla_host_t *vha)
1da177e4
LT		 930{
931 int rval;
42e421b1
AV		 932 uint16_t loop_id, topo, sw_cap;
933 uint8_t domain, area, al_pa;
e315cd28 934 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 935
936 /* Assume loading risc code */
fa2a1ce5 937 rval = QLA_FUNCTION_FAILED;
1da177e4
LT		 938
939 if (ha->flags.disable_risc_code_load) {
7c3df132 940 ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n");
1da177e4
LT		 941
942 /* Verify checksum of loaded RISC code. */
e315cd28 943 rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address);
42e421b1
AV		 944 if (rval == QLA_SUCCESS) {
945 /* And, verify we are not in ROM code. */
e315cd28 946 rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa,
42e421b1
AV		 947 &area, &domain, &topo, &sw_cap);
948 }
1da177e4
LT		 949 }
950
7c3df132
SK		 951 if (rval)
952 ql_dbg(ql_dbg_init, vha, 0x007a,
953 "**** Load RISC code ****.\n");
1da177e4
LT		 954
955 return (rval);
956}
957
958/**
959 * qla2x00_reset_chip() - Reset ISP chip.
960 * @ha: HA context
961 *
962 * Returns 0 on success.
963 */
abbd8870 964void
e315cd28 965qla2x00_reset_chip(scsi_qla_host_t *vha)
1da177e4
LT		 966{
967 unsigned long flags = 0;
e315cd28 968 struct qla_hw_data *ha = vha->hw;
3d71644c 969 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 970 uint32_t cnt;
1da177e4
LT		 971 uint16_t cmd;
972
85880801
AV		 973 if (unlikely(pci_channel_offline(ha->pdev)))
974 return;
975
fd34f556 976 ha->isp_ops->disable_intrs(ha);
1da177e4
LT		 977
978 spin_lock_irqsave(&ha->hardware_lock, flags);
979
980 /* Turn off master enable */
981 cmd = 0;
982 pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd);
983 cmd &= ~PCI_COMMAND_MASTER;
984 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
985
986 if (!IS_QLA2100(ha)) {
987 /* Pause RISC. */
988 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
989 if (IS_QLA2200(ha) || IS_QLA2300(ha)) {
990 for (cnt = 0; cnt < 30000; cnt++) {
991 if ((RD_REG_WORD(&reg->hccr) &
992 HCCR_RISC_PAUSE) != 0)
993 break;
994 udelay(100);
995 }
996 } else {
997 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
998 udelay(10);
999 }
1000
1001 /* Select FPM registers. */
1002 WRT_REG_WORD(&reg->ctrl_status, 0x20);
1003 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1004
1005 /* FPM Soft Reset. */
1006 WRT_REG_WORD(&reg->fpm_diag_config, 0x100);
1007 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
1008
1009 /* Toggle Fpm Reset. */
1010 if (!IS_QLA2200(ha)) {
1011 WRT_REG_WORD(&reg->fpm_diag_config, 0x0);
1012 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
1013 }
1014
1015 /* Select frame buffer registers. */
1016 WRT_REG_WORD(&reg->ctrl_status, 0x10);
1017 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1018
1019 /* Reset frame buffer FIFOs. */
1020 if (IS_QLA2200(ha)) {
1021 WRT_FB_CMD_REG(ha, reg, 0xa000);
1022 RD_FB_CMD_REG(ha, reg); /* PCI Posting. */
1023 } else {
1024 WRT_FB_CMD_REG(ha, reg, 0x00fc);
1025
1026 /* Read back fb_cmd until zero or 3 seconds max */
1027 for (cnt = 0; cnt < 3000; cnt++) {
1028 if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0)
1029 break;
1030 udelay(100);
1031 }
1032 }
1033
1034 /* Select RISC module registers. */
1035 WRT_REG_WORD(&reg->ctrl_status, 0);
1036 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1037
1038 /* Reset RISC processor. */
1039 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
1040 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1041
1042 /* Release RISC processor. */
1043 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
1044 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1045 }
1046
1047 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
1048 WRT_REG_WORD(&reg->hccr, HCCR_CLR_HOST_INT);
1049
1050 /* Reset ISP chip. */
1051 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1052
1053 /* Wait for RISC to recover from reset. */
1054 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1055 /*
1056 * It is necessary to for a delay here since the card doesn't
1057 * respond to PCI reads during a reset. On some architectures
1058 * this will result in an MCA.
1059 */
1060 udelay(20);
1061 for (cnt = 30000; cnt; cnt--) {
1062 if ((RD_REG_WORD(&reg->ctrl_status) &
1063 CSR_ISP_SOFT_RESET) == 0)
1064 break;
1065 udelay(100);
1066 }
1067 } else
1068 udelay(10);
1069
1070 /* Reset RISC processor. */
1071 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
1072
1073 WRT_REG_WORD(&reg->semaphore, 0);
1074
1075 /* Release RISC processor. */
1076 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
1077 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1078
1079 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1080 for (cnt = 0; cnt < 30000; cnt++) {
ffb39f03 1081 if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY)
1da177e4 1082 break;
1da177e4
LT		 1083
1084 udelay(100);
1085 }
1086 } else
1087 udelay(100);
1088
1089 /* Turn on master enable */
1090 cmd |= PCI_COMMAND_MASTER;
1091 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
1092
1093 /* Disable RISC pause on FPM parity error. */
1094 if (!IS_QLA2100(ha)) {
1095 WRT_REG_WORD(&reg->hccr, HCCR_DISABLE_PARITY_PAUSE);
1096 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1097 }
1098
1099 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1100}
1101
b1d46989
MI		 1102/**
1103 * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC.
1104 *
1105 * Returns 0 on success.
1106 */
fa492630 1107static int
b1d46989
MI		 1108qla81xx_reset_mpi(scsi_qla_host_t *vha)
1109{
1110 uint16_t mb[4] = {0x1010, 0, 1, 0};
1111
6246b8a1
GM		 1112 if (!IS_QLA81XX(vha->hw))
1113 return QLA_SUCCESS;
1114
b1d46989
MI		 1115 return qla81xx_write_mpi_register(vha, mb);
1116}
1117
0107109e 1118/**
88c26663 1119 * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC.
0107109e
AV		 1120 * @ha: HA context
1121 *
1122 * Returns 0 on success.
1123 */
88c26663 1124static inline void
e315cd28 1125qla24xx_reset_risc(scsi_qla_host_t *vha)
0107109e
AV		 1126{
1127 unsigned long flags = 0;
e315cd28 1128 struct qla_hw_data *ha = vha->hw;
0107109e
AV		 1129 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1130 uint32_t cnt, d2;
335a1cc9 1131 uint16_t wd;
b1d46989 1132 static int abts_cnt; /* ISP abort retry counts */
0107109e 1133
0107109e
AV		 1134 spin_lock_irqsave(&ha->hardware_lock, flags);
1135
1136 /* Reset RISC. */
1137 WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
1138 for (cnt = 0; cnt < 30000; cnt++) {
1139 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
1140 break;
1141
1142 udelay(10);
1143 }
1144
1145 WRT_REG_DWORD(&reg->ctrl_status,
1146 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
335a1cc9 1147 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
88c26663 1148
335a1cc9 1149 udelay(100);
88c26663 1150 /* Wait for firmware to complete NVRAM accesses. */
88c26663
AV		 1151 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1152 for (cnt = 10000 ; cnt && d2; cnt--) {
1153 udelay(5);
1154 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1155 barrier();
1156 }
1157
335a1cc9 1158 /* Wait for soft-reset to complete. */
0107109e
AV		 1159 d2 = RD_REG_DWORD(&reg->ctrl_status);
1160 for (cnt = 6000000 ; cnt && (d2 & CSRX_ISP_SOFT_RESET); cnt--) {
1161 udelay(5);
1162 d2 = RD_REG_DWORD(&reg->ctrl_status);
1163 barrier();
1164 }
1165
b1d46989
MI		 1166 /* If required, do an MPI FW reset now */
1167 if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
1168 if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
1169 if (++abts_cnt < 5) {
1170 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1171 set_bit(MPI_RESET_NEEDED, &vha->dpc_flags);
1172 } else {
1173 /*
1174 * We exhausted the ISP abort retries. We have to
1175 * set the board offline.
1176 */
1177 abts_cnt = 0;
1178 vha->flags.online = 0;
1179 }
1180 }
1181 }
1182
0107109e
AV		 1183 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
1184 RD_REG_DWORD(&reg->hccr);
1185
1186 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
1187 RD_REG_DWORD(&reg->hccr);
1188
1189 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
1190 RD_REG_DWORD(&reg->hccr);
1191
1192 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1193 for (cnt = 6000000 ; cnt && d2; cnt--) {
1194 udelay(5);
1195 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1196 barrier();
1197 }
1198
1199 spin_unlock_irqrestore(&ha->hardware_lock, flags);
124f85e6
AV		 1200
1201 if (IS_NOPOLLING_TYPE(ha))
1202 ha->isp_ops->enable_intrs(ha);
0107109e
AV		 1203}
1204
4ea2c9c7
JC		 1205static void
1206qla25xx_read_risc_sema_reg(scsi_qla_host_t *vha, uint32_t *data)
1207{
1208 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
1209
1210 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
1211 *data = RD_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET);
1212
1213}
1214
1215static void
1216qla25xx_write_risc_sema_reg(scsi_qla_host_t *vha, uint32_t data)
1217{
1218 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
1219
1220 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
1221 WRT_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET, data);
1222}
1223
1224static void
1225qla25xx_manipulate_risc_semaphore(scsi_qla_host_t *vha)
1226{
1227 struct qla_hw_data *ha = vha->hw;
1228 uint32_t wd32 = 0;
1229 uint delta_msec = 100;
1230 uint elapsed_msec = 0;
1231 uint timeout_msec;
1232 ulong n;
1233
1234 if (!IS_QLA25XX(ha) && !IS_QLA2031(ha))
1235 return;
1236
1237attempt:
1238 timeout_msec = TIMEOUT_SEMAPHORE;
1239 n = timeout_msec / delta_msec;
1240 while (n--) {
1241 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_SET);
1242 qla25xx_read_risc_sema_reg(vha, &wd32);
1243 if (wd32 & RISC_SEMAPHORE)
1244 break;
1245 msleep(delta_msec);
1246 elapsed_msec += delta_msec;
1247 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
1248 goto force;
1249 }
1250
1251 if (!(wd32 & RISC_SEMAPHORE))
1252 goto force;
1253
1254 if (!(wd32 & RISC_SEMAPHORE_FORCE))
1255 goto acquired;
1256
1257 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_CLR);
1258 timeout_msec = TIMEOUT_SEMAPHORE_FORCE;
1259 n = timeout_msec / delta_msec;
1260 while (n--) {
1261 qla25xx_read_risc_sema_reg(vha, &wd32);
1262 if (!(wd32 & RISC_SEMAPHORE_FORCE))
1263 break;
1264 msleep(delta_msec);
1265 elapsed_msec += delta_msec;
1266 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
1267 goto force;
1268 }
1269
1270 if (wd32 & RISC_SEMAPHORE_FORCE)
1271 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_CLR);
1272
1273 goto attempt;
1274
1275force:
1276 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_SET);
1277
1278acquired:
1279 return;
1280}
1281
88c26663
AV		 1282/**
1283 * qla24xx_reset_chip() - Reset ISP24xx chip.
1284 * @ha: HA context
1285 *
1286 * Returns 0 on success.
1287 */
1288void
e315cd28 1289qla24xx_reset_chip(scsi_qla_host_t *vha)
88c26663 1290{
e315cd28 1291 struct qla_hw_data *ha = vha->hw;
85880801
AV		 1292
1293 if (pci_channel_offline(ha->pdev) &&
1294 ha->flags.pci_channel_io_perm_failure) {
1295 return;
1296 }
1297
fd34f556 1298 ha->isp_ops->disable_intrs(ha);
88c26663 1299
4ea2c9c7
JC		 1300 qla25xx_manipulate_risc_semaphore(vha);
1301
88c26663 1302 /* Perform RISC reset. */
e315cd28 1303 qla24xx_reset_risc(vha);
88c26663
AV		 1304}
1305
1da177e4
LT		 1306/**
1307 * qla2x00_chip_diag() - Test chip for proper operation.
1308 * @ha: HA context
1309 *
1310 * Returns 0 on success.
1311 */
abbd8870 1312int
e315cd28 1313qla2x00_chip_diag(scsi_qla_host_t *vha)
1da177e4
LT		 1314{
1315 int rval;
e315cd28 1316 struct qla_hw_data *ha = vha->hw;
3d71644c 1317 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 1318 unsigned long flags = 0;
1319 uint16_t data;
1320 uint32_t cnt;
1321 uint16_t mb[5];
73208dfd 1322 struct req_que *req = ha->req_q_map[0];
1da177e4
LT		 1323
1324 /* Assume a failed state */
1325 rval = QLA_FUNCTION_FAILED;
1326
7c3df132
SK		 1327 ql_dbg(ql_dbg_init, vha, 0x007b,
1328 "Testing device at %lx.\n", (u_long)&reg->flash_address);
1da177e4
LT		 1329
1330 spin_lock_irqsave(&ha->hardware_lock, flags);
1331
1332 /* Reset ISP chip. */
1333 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1334
1335 /*
1336 * We need to have a delay here since the card will not respond while
1337 * in reset causing an MCA on some architectures.
1338 */
1339 udelay(20);
1340 data = qla2x00_debounce_register(&reg->ctrl_status);
1341 for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {
1342 udelay(5);
1343 data = RD_REG_WORD(&reg->ctrl_status);
1344 barrier();
1345 }
1346
1347 if (!cnt)
1348 goto chip_diag_failed;
1349
7c3df132
SK		 1350 ql_dbg(ql_dbg_init, vha, 0x007c,
1351 "Reset register cleared by chip reset.\n");
1da177e4
LT		 1352
1353 /* Reset RISC processor. */
1354 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
1355 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
1356
1357 /* Workaround for QLA2312 PCI parity error */
1358 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1359 data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0));
1360 for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) {
1361 udelay(5);
1362 data = RD_MAILBOX_REG(ha, reg, 0);
fa2a1ce5 1363 barrier();
1da177e4
LT		 1364 }
1365 } else
1366 udelay(10);
1367
1368 if (!cnt)
1369 goto chip_diag_failed;
1370
1371 /* Check product ID of chip */
7c3df132 1372 ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product Id of chip.\n");
1da177e4
LT		 1373
1374 mb[1] = RD_MAILBOX_REG(ha, reg, 1);
1375 mb[2] = RD_MAILBOX_REG(ha, reg, 2);
1376 mb[3] = RD_MAILBOX_REG(ha, reg, 3);
1377 mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4));
1378 if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) ||
1379 mb[3] != PROD_ID_3) {
7c3df132
SK		 1380 ql_log(ql_log_warn, vha, 0x0062,
1381 "Wrong product ID = 0x%x,0x%x,0x%x.\n",
1382 mb[1], mb[2], mb[3]);
1da177e4
LT		 1383
1384 goto chip_diag_failed;
1385 }
1386 ha->product_id[0] = mb[1];
1387 ha->product_id[1] = mb[2];
1388 ha->product_id[2] = mb[3];
1389 ha->product_id[3] = mb[4];
1390
1391 /* Adjust fw RISC transfer size */
73208dfd 1392 if (req->length > 1024)
1da177e4
LT		 1393 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024;
1394 else
1395 ha->fw_transfer_size = REQUEST_ENTRY_SIZE *
73208dfd 1396 req->length;
1da177e4
LT		 1397
1398 if (IS_QLA2200(ha) &&
1399 RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) {
1400 /* Limit firmware transfer size with a 2200A */
7c3df132 1401 ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n");
1da177e4 1402
ea5b6382 1403 ha->device_type |= DT_ISP2200A;
1da177e4
LT		 1404 ha->fw_transfer_size = 128;
1405 }
1406
1407 /* Wrap Incoming Mailboxes Test. */
1408 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1409
7c3df132 1410 ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n");
e315cd28 1411 rval = qla2x00_mbx_reg_test(vha);
7c3df132
SK		 1412 if (rval)
1413 ql_log(ql_log_warn, vha, 0x0080,
1414 "Failed mailbox send register test.\n");
1415 else
1da177e4
LT		 1416 /* Flag a successful rval */
1417 rval = QLA_SUCCESS;
1da177e4
LT		 1418 spin_lock_irqsave(&ha->hardware_lock, flags);
1419
1420chip_diag_failed:
1421 if (rval)
7c3df132
SK		 1422 ql_log(ql_log_info, vha, 0x0081,
1423 "Chip diagnostics **** FAILED ****.\n");
1da177e4
LT		 1424
1425 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1426
1427 return (rval);
1428}
1429
0107109e
AV		 1430/**
1431 * qla24xx_chip_diag() - Test ISP24xx for proper operation.
1432 * @ha: HA context
1433 *
1434 * Returns 0 on success.
1435 */
1436int
e315cd28 1437qla24xx_chip_diag(scsi_qla_host_t *vha)
0107109e
AV		 1438{
1439 int rval;
e315cd28 1440 struct qla_hw_data *ha = vha->hw;
73208dfd 1441 struct req_que *req = ha->req_q_map[0];
0107109e 1442
7ec0effd 1443 if (IS_P3P_TYPE(ha))
a9083016
GM		 1444 return QLA_SUCCESS;
1445
73208dfd 1446 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
0107109e 1447
e315cd28 1448 rval = qla2x00_mbx_reg_test(vha);
0107109e 1449 if (rval) {
7c3df132
SK		 1450 ql_log(ql_log_warn, vha, 0x0082,
1451 "Failed mailbox send register test.\n");
0107109e
AV		 1452 } else {
1453 /* Flag a successful rval */
1454 rval = QLA_SUCCESS;
1455 }
1456
1457 return rval;
1458}
1459
a7a167bf 1460void
e315cd28 1461qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
0107109e 1462{
a7a167bf
AV		 1463 int rval;
1464 uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
73208dfd 1465 eft_size, fce_size, mq_size;
df613b96
AV		 1466 dma_addr_t tc_dma;
1467 void *tc;
e315cd28 1468 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 1469 struct req_que *req = ha->req_q_map[0];
1470 struct rsp_que *rsp = ha->rsp_q_map[0];
a7a167bf
AV		 1471
1472 if (ha->fw_dump) {
7c3df132
SK		 1473 ql_dbg(ql_dbg_init, vha, 0x00bd,
1474 "Firmware dump already allocated.\n");
a7a167bf
AV		 1475 return;
1476 }
d4e3e04d 1477
0107109e 1478 ha->fw_dumped = 0;
61f098dd 1479 ha->fw_dump_cap_flags = 0;
f73cb695
CD		 1480 dump_size = fixed_size = mem_size = eft_size = fce_size = mq_size = 0;
1481 req_q_size = rsp_q_size = 0;
1482
1483 if (IS_QLA27XX(ha))
1484 goto try_fce;
1485
d4e3e04d 1486 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
a7a167bf 1487 fixed_size = sizeof(struct qla2100_fw_dump);
d4e3e04d 1488 } else if (IS_QLA23XX(ha)) {
a7a167bf
AV		 1489 fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
1490 mem_size = (ha->fw_memory_size - 0x11000 + 1) *
1491 sizeof(uint16_t);
e428924c 1492 } else if (IS_FWI2_CAPABLE(ha)) {
6246b8a1
GM		 1493 if (IS_QLA83XX(ha))
1494 fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem);
1495 else if (IS_QLA81XX(ha))
3a03eb79
AV		 1496 fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
1497 else if (IS_QLA25XX(ha))
1498 fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
1499 else
1500 fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
f73cb695 1501
a7a167bf
AV		 1502 mem_size = (ha->fw_memory_size - 0x100000 + 1) *
1503 sizeof(uint32_t);
050c9bb1 1504 if (ha->mqenable) {
6246b8a1
GM		 1505 if (!IS_QLA83XX(ha))
1506 mq_size = sizeof(struct qla2xxx_mq_chain);
050c9bb1
GM		 1507 /*
1508 * Allocate maximum buffer size for all queues.
1509 * Resizing must be done at end-of-dump processing.
1510 */
1511 mq_size += ha->max_req_queues *
1512 (req->length * sizeof(request_t));
1513 mq_size += ha->max_rsp_queues *
1514 (rsp->length * sizeof(response_t));
1515 }
00876ae8 1516 if (ha->tgt.atio_ring)
2d70c103 1517 mq_size += ha->tgt.atio_q_length * sizeof(request_t);
df613b96 1518 /* Allocate memory for Fibre Channel Event Buffer. */
f73cb695
CD		 1519 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
1520 !IS_QLA27XX(ha))
436a7b11 1521 goto try_eft;
df613b96 1522
f73cb695
CD		 1523try_fce:
1524 if (ha->fce)
1525 dma_free_coherent(&ha->pdev->dev,
1526 FCE_SIZE, ha->fce, ha->fce_dma);
1527
1528 /* Allocate memory for Fibre Channel Event Buffer. */
0ea85b50
JP		 1529 tc = dma_zalloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
1530 GFP_KERNEL);
df613b96 1531 if (!tc) {
7c3df132
SK		 1532 ql_log(ql_log_warn, vha, 0x00be,
1533 "Unable to allocate (%d KB) for FCE.\n",
1534 FCE_SIZE / 1024);
17d98630 1535 goto try_eft;
df613b96
AV		 1536 }
1537
e315cd28 1538 rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS,
df613b96
AV		 1539 ha->fce_mb, &ha->fce_bufs);
1540 if (rval) {
7c3df132
SK		 1541 ql_log(ql_log_warn, vha, 0x00bf,
1542 "Unable to initialize FCE (%d).\n", rval);
df613b96
AV		 1543 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc,
1544 tc_dma);
1545 ha->flags.fce_enabled = 0;
17d98630 1546 goto try_eft;
df613b96 1547 }
cfb0919c 1548 ql_dbg(ql_dbg_init, vha, 0x00c0,
7c3df132 1549 "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024);
df613b96 1550
7d9dade3 1551 fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE;
df613b96
AV		 1552 ha->flags.fce_enabled = 1;
1553 ha->fce_dma = tc_dma;
1554 ha->fce = tc;
f73cb695 1555
436a7b11 1556try_eft:
f73cb695
CD		 1557 if (ha->eft)
1558 dma_free_coherent(&ha->pdev->dev,
1559 EFT_SIZE, ha->eft, ha->eft_dma);
1560
436a7b11 1561 /* Allocate memory for Extended Trace Buffer. */
0ea85b50
JP		 1562 tc = dma_zalloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
1563 GFP_KERNEL);
436a7b11 1564 if (!tc) {
7c3df132
SK		 1565 ql_log(ql_log_warn, vha, 0x00c1,
1566 "Unable to allocate (%d KB) for EFT.\n",
1567 EFT_SIZE / 1024);
436a7b11
AV		 1568 goto cont_alloc;
1569 }
1570
e315cd28 1571 rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
436a7b11 1572 if (rval) {
7c3df132
SK		 1573 ql_log(ql_log_warn, vha, 0x00c2,
1574 "Unable to initialize EFT (%d).\n", rval);
436a7b11
AV		 1575 dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc,
1576 tc_dma);
1577 goto cont_alloc;
1578 }
cfb0919c 1579 ql_dbg(ql_dbg_init, vha, 0x00c3,
7c3df132 1580 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
436a7b11
AV		 1581
1582 eft_size = EFT_SIZE;
1583 ha->eft_dma = tc_dma;
1584 ha->eft = tc;
d4e3e04d 1585 }
f73cb695 1586
a7a167bf 1587cont_alloc:
f73cb695
CD		 1588 if (IS_QLA27XX(ha)) {
1589 if (!ha->fw_dump_template) {
1590 ql_log(ql_log_warn, vha, 0x00ba,
1591 "Failed missing fwdump template\n");
1592 return;
1593 }
1594 dump_size = qla27xx_fwdt_calculate_dump_size(vha);
1595 ql_dbg(ql_dbg_init, vha, 0x00fa,
1596 "-> allocating fwdump (%x bytes)...\n", dump_size);
1597 goto allocate;
1598 }
1599
73208dfd
AC		 1600 req_q_size = req->length * sizeof(request_t);
1601 rsp_q_size = rsp->length * sizeof(response_t);
a7a167bf 1602 dump_size = offsetof(struct qla2xxx_fw_dump, isp);
2afa19a9 1603 dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size;
bb99de67
AV		 1604 ha->chain_offset = dump_size;
1605 dump_size += mq_size + fce_size;
d4e3e04d 1606
f73cb695 1607allocate:
d4e3e04d 1608 ha->fw_dump = vmalloc(dump_size);
a7a167bf 1609 if (!ha->fw_dump) {
7c3df132
SK		 1610 ql_log(ql_log_warn, vha, 0x00c4,
1611 "Unable to allocate (%d KB) for firmware dump.\n",
1612 dump_size / 1024);
a7a167bf 1613
e30d1756
MI		 1614 if (ha->fce) {
1615 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
1616 ha->fce_dma);
1617 ha->fce = NULL;
1618 ha->fce_dma = 0;
1619 }
1620
a7a167bf
AV		 1621 if (ha->eft) {
1622 dma_free_coherent(&ha->pdev->dev, eft_size, ha->eft,
1623 ha->eft_dma);
1624 ha->eft = NULL;
1625 ha->eft_dma = 0;
1626 }
1627 return;
1628 }
f73cb695 1629 ha->fw_dump_len = dump_size;
cfb0919c 1630 ql_dbg(ql_dbg_init, vha, 0x00c5,
7c3df132 1631 "Allocated (%d KB) for firmware dump.\n", dump_size / 1024);
a7a167bf 1632
f73cb695
CD		 1633 if (IS_QLA27XX(ha))
1634 return;
1635
a7a167bf
AV		 1636 ha->fw_dump->signature[0] = 'Q';
1637 ha->fw_dump->signature[1] = 'L';
1638 ha->fw_dump->signature[2] = 'G';
1639 ha->fw_dump->signature[3] = 'C';
1640 ha->fw_dump->version = __constant_htonl(1);
1641
1642 ha->fw_dump->fixed_size = htonl(fixed_size);
1643 ha->fw_dump->mem_size = htonl(mem_size);
1644 ha->fw_dump->req_q_size = htonl(req_q_size);
1645 ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
1646
1647 ha->fw_dump->eft_size = htonl(eft_size);
1648 ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma));
1649 ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma));
1650
1651 ha->fw_dump->header_size =
1652 htonl(offsetof(struct qla2xxx_fw_dump, isp));
0107109e
AV		 1653}
1654
18e7555a
AV		 1655static int
1656qla81xx_mpi_sync(scsi_qla_host_t *vha)
1657{
1658#define MPS_MASK 0xe0
1659 int rval;
1660 uint16_t dc;
1661 uint32_t dw;
18e7555a
AV		 1662
1663 if (!IS_QLA81XX(vha->hw))
1664 return QLA_SUCCESS;
1665
1666 rval = qla2x00_write_ram_word(vha, 0x7c00, 1);
1667 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1668 ql_log(ql_log_warn, vha, 0x0105,
1669 "Unable to acquire semaphore.\n");
18e7555a
AV		 1670 goto done;
1671 }
1672
1673 pci_read_config_word(vha->hw->pdev, 0x54, &dc);
1674 rval = qla2x00_read_ram_word(vha, 0x7a15, &dw);
1675 if (rval != QLA_SUCCESS) {
7c3df132 1676 ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n");
18e7555a
AV		 1677 goto done_release;
1678 }
1679
1680 dc &= MPS_MASK;
1681 if (dc == (dw & MPS_MASK))
1682 goto done_release;
1683
1684 dw &= ~MPS_MASK;
1685 dw |= dc;
1686 rval = qla2x00_write_ram_word(vha, 0x7a15, dw);
1687 if (rval != QLA_SUCCESS) {
7c3df132 1688 ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n");
18e7555a
AV		 1689 }
1690
1691done_release:
1692 rval = qla2x00_write_ram_word(vha, 0x7c00, 0);
1693 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1694 ql_log(ql_log_warn, vha, 0x006d,
1695 "Unable to release semaphore.\n");
18e7555a
AV		 1696 }
1697
1698done:
1699 return rval;
1700}
1701
8d93f550
CD		 1702int
1703qla2x00_alloc_outstanding_cmds(struct qla_hw_data *ha, struct req_que *req)
1704{
1705 /* Don't try to reallocate the array */
1706 if (req->outstanding_cmds)
1707 return QLA_SUCCESS;
1708
1709 if (!IS_FWI2_CAPABLE(ha) || (ha->mqiobase &&
1710 (ql2xmultique_tag || ql2xmaxqueues > 1)))
1711 req->num_outstanding_cmds = DEFAULT_OUTSTANDING_COMMANDS;
1712 else {
1713 if (ha->fw_xcb_count <= ha->fw_iocb_count)
1714 req->num_outstanding_cmds = ha->fw_xcb_count;
1715 else
1716 req->num_outstanding_cmds = ha->fw_iocb_count;
1717 }
1718
1719 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
1720 req->num_outstanding_cmds, GFP_KERNEL);
1721
1722 if (!req->outstanding_cmds) {
1723 /*
1724 * Try to allocate a minimal size just so we can get through
1725 * initialization.
1726 */
1727 req->num_outstanding_cmds = MIN_OUTSTANDING_COMMANDS;
1728 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
1729 req->num_outstanding_cmds, GFP_KERNEL);
1730
1731 if (!req->outstanding_cmds) {
1732 ql_log(ql_log_fatal, NULL, 0x0126,
1733 "Failed to allocate memory for "
1734 "outstanding_cmds for req_que %p.\n", req);
1735 req->num_outstanding_cmds = 0;
1736 return QLA_FUNCTION_FAILED;
1737 }
1738 }
1739
1740 return QLA_SUCCESS;
1741}
1742
1da177e4
LT		 1743/**
1744 * qla2x00_setup_chip() - Load and start RISC firmware.
1745 * @ha: HA context
1746 *
1747 * Returns 0 on success.
1748 */
1749static int
e315cd28 1750qla2x00_setup_chip(scsi_qla_host_t *vha)
1da177e4 1751{
0107109e
AV		 1752 int rval;
1753 uint32_t srisc_address = 0;
e315cd28 1754 struct qla_hw_data *ha = vha->hw;
3db0652e
AV		 1755 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1756 unsigned long flags;
dda772e8 1757 uint16_t fw_major_version;
3db0652e 1758
7ec0effd 1759 if (IS_P3P_TYPE(ha)) {
a9083016 1760 rval = ha->isp_ops->load_risc(vha, &srisc_address);
14e303d9
AV		 1761 if (rval == QLA_SUCCESS) {
1762 qla2x00_stop_firmware(vha);
a9083016 1763 goto enable_82xx_npiv;
14e303d9 1764 } else
b963752f 1765 goto failed;
a9083016
GM		 1766 }
1767
3db0652e
AV		 1768 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1769 /* Disable SRAM, Instruction RAM and GP RAM parity. */
1770 spin_lock_irqsave(&ha->hardware_lock, flags);
1771 WRT_REG_WORD(&reg->hccr, (HCCR_ENABLE_PARITY + 0x0));
1772 RD_REG_WORD(&reg->hccr);
1773 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1774 }
1da177e4 1775
18e7555a
AV		 1776 qla81xx_mpi_sync(vha);
1777
1da177e4 1778 /* Load firmware sequences */
e315cd28 1779 rval = ha->isp_ops->load_risc(vha, &srisc_address);
0107109e 1780 if (rval == QLA_SUCCESS) {
7c3df132
SK		 1781 ql_dbg(ql_dbg_init, vha, 0x00c9,
1782 "Verifying Checksum of loaded RISC code.\n");
1da177e4 1783
e315cd28 1784 rval = qla2x00_verify_checksum(vha, srisc_address);
1da177e4
LT		 1785 if (rval == QLA_SUCCESS) {
1786 /* Start firmware execution. */
7c3df132
SK		 1787 ql_dbg(ql_dbg_init, vha, 0x00ca,
1788 "Starting firmware.\n");
1da177e4 1789
e315cd28 1790 rval = qla2x00_execute_fw(vha, srisc_address);
1da177e4 1791 /* Retrieve firmware information. */
dda772e8 1792 if (rval == QLA_SUCCESS) {
a9083016 1793enable_82xx_npiv:
dda772e8 1794 fw_major_version = ha->fw_major_version;
7ec0effd 1795 if (IS_P3P_TYPE(ha))
3173167f 1796 qla82xx_check_md_needed(vha);
6246b8a1
GM		 1797 else
1798 rval = qla2x00_get_fw_version(vha);
ca9e9c3e
AV		 1799 if (rval != QLA_SUCCESS)
1800 goto failed;
2c3dfe3f 1801 ha->flags.npiv_supported = 0;
e315cd28 1802 if (IS_QLA2XXX_MIDTYPE(ha) &&
946fb891 1803 (ha->fw_attributes & BIT_2)) {
2c3dfe3f 1804 ha->flags.npiv_supported = 1;
4d0ea247
SJ		 1805 if ((!ha->max_npiv_vports) ||
1806 ((ha->max_npiv_vports + 1) %
eb66dc60 1807 MIN_MULTI_ID_FABRIC))
4d0ea247 1808 ha->max_npiv_vports =
eb66dc60 1809 MIN_MULTI_ID_FABRIC - 1;
4d0ea247 1810 }
24a08138 1811 qla2x00_get_resource_cnts(vha, NULL,
8d93f550 1812 &ha->fw_xcb_count, NULL, &ha->fw_iocb_count,
f3a0a77e 1813 &ha->max_npiv_vports, NULL);
d743de66 1814
8d93f550
CD		 1815 /*
1816 * Allocate the array of outstanding commands
1817 * now that we know the firmware resources.
1818 */
1819 rval = qla2x00_alloc_outstanding_cmds(ha,
1820 vha->req);
1821 if (rval != QLA_SUCCESS)
1822 goto failed;
1823
be5ea3cf 1824 if (!fw_major_version && ql2xallocfwdump
7ec0effd 1825 && !(IS_P3P_TYPE(ha)))
08de2844 1826 qla2x00_alloc_fw_dump(vha);
3b6e5b9d
CD		 1827 } else {
1828 goto failed;
1da177e4
LT		 1829 }
1830 } else {
7c3df132
SK		 1831 ql_log(ql_log_fatal, vha, 0x00cd,
1832 "ISP Firmware failed checksum.\n");
1833 goto failed;
1da177e4 1834 }
c74d88a4
AV		 1835 } else
1836 goto failed;
1da177e4 1837
3db0652e
AV		 1838 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1839 /* Enable proper parity. */
1840 spin_lock_irqsave(&ha->hardware_lock, flags);
1841 if (IS_QLA2300(ha))
1842 /* SRAM parity */
1843 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x1);
1844 else
1845 /* SRAM, Instruction RAM and GP RAM parity */
1846 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x7);
1847 RD_REG_WORD(&reg->hccr);
1848 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1849 }
1850
1d2874de
JC		 1851 if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
1852 uint32_t size;
1853
1854 rval = qla81xx_fac_get_sector_size(vha, &size);
1855 if (rval == QLA_SUCCESS) {
1856 ha->flags.fac_supported = 1;
1857 ha->fdt_block_size = size << 2;
1858 } else {
7c3df132 1859 ql_log(ql_log_warn, vha, 0x00ce,
1d2874de
JC		 1860 "Unsupported FAC firmware (%d.%02d.%02d).\n",
1861 ha->fw_major_version, ha->fw_minor_version,
1862 ha->fw_subminor_version);
1ca60e3b 1863
f73cb695 1864 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
6246b8a1
GM		 1865 ha->flags.fac_supported = 0;
1866 rval = QLA_SUCCESS;
1867 }
1d2874de
JC		 1868 }
1869 }
ca9e9c3e 1870failed:
1da177e4 1871 if (rval) {
7c3df132
SK		 1872 ql_log(ql_log_fatal, vha, 0x00cf,
1873 "Setup chip ****FAILED****.\n");
1da177e4
LT		 1874 }
1875
1876 return (rval);
1877}
1878
1879/**
1880 * qla2x00_init_response_q_entries() - Initializes response queue entries.
1881 * @ha: HA context
1882 *
1883 * Beginning of request ring has initialization control block already built
1884 * by nvram config routine.
1885 *
1886 * Returns 0 on success.
1887 */
73208dfd
AC		 1888void
1889qla2x00_init_response_q_entries(struct rsp_que *rsp)
1da177e4
LT		 1890{
1891 uint16_t cnt;
1892 response_t *pkt;
1893
2afa19a9
AC		 1894 rsp->ring_ptr = rsp->ring;
1895 rsp->ring_index = 0;
1896 rsp->status_srb = NULL;
e315cd28
AC		 1897 pkt = rsp->ring_ptr;
1898 for (cnt = 0; cnt < rsp->length; cnt++) {
1da177e4
LT		 1899 pkt->signature = RESPONSE_PROCESSED;
1900 pkt++;
1901 }
1da177e4
LT		 1902}
1903
1904/**
1905 * qla2x00_update_fw_options() - Read and process firmware options.
1906 * @ha: HA context
1907 *
1908 * Returns 0 on success.
1909 */
abbd8870 1910void
e315cd28 1911qla2x00_update_fw_options(scsi_qla_host_t *vha)
1da177e4
LT		 1912{
1913 uint16_t swing, emphasis, tx_sens, rx_sens;
e315cd28 1914 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 1915
1916 memset(ha->fw_options, 0, sizeof(ha->fw_options));
e315cd28 1917 qla2x00_get_fw_options(vha, ha->fw_options);
1da177e4
LT		 1918
1919 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1920 return;
1921
1922 /* Serial Link options. */
7c3df132
SK		 1923 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
1924 "Serial link options.\n");
1925 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
1926 (uint8_t *)&ha->fw_seriallink_options,
1927 sizeof(ha->fw_seriallink_options));
1da177e4
LT		 1928
1929 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1930 if (ha->fw_seriallink_options[3] & BIT_2) {
1931 ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING;
1932
1933 /* 1G settings */
1934 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
1935 emphasis = (ha->fw_seriallink_options[2] &
1936 (BIT_4 | BIT_3)) >> 3;
1937 tx_sens = ha->fw_seriallink_options[0] &
fa2a1ce5 1938 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 1939 rx_sens = (ha->fw_seriallink_options[0] &
1940 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
1941 ha->fw_options[10] = (emphasis << 14) | (swing << 8);
1942 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
1943 if (rx_sens == 0x0)
1944 rx_sens = 0x3;
1945 ha->fw_options[10] |= (tx_sens << 4) | rx_sens;
1946 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
1947 ha->fw_options[10] |= BIT_5 |
1948 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
1949 (tx_sens & (BIT_1 | BIT_0));
1950
1951 /* 2G settings */
1952 swing = (ha->fw_seriallink_options[2] &
1953 (BIT_7 | BIT_6 | BIT_5)) >> 5;
1954 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
1955 tx_sens = ha->fw_seriallink_options[1] &
fa2a1ce5 1956 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 1957 rx_sens = (ha->fw_seriallink_options[1] &
1958 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
1959 ha->fw_options[11] = (emphasis << 14) | (swing << 8);
1960 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
1961 if (rx_sens == 0x0)
1962 rx_sens = 0x3;
1963 ha->fw_options[11] |= (tx_sens << 4) | rx_sens;
1964 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
1965 ha->fw_options[11] |= BIT_5 |
1966 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
1967 (tx_sens & (BIT_1 | BIT_0));
1968 }
1969
1970 /* FCP2 options. */
1971 /* Return command IOCBs without waiting for an ABTS to complete. */
1972 ha->fw_options[3] |= BIT_13;
1973
1974 /* LED scheme. */
1975 if (ha->flags.enable_led_scheme)
1976 ha->fw_options[2] |= BIT_12;
1977
48c02fde
AV		 1978 /* Detect ISP6312. */
1979 if (IS_QLA6312(ha))
1980 ha->fw_options[2] |= BIT_13;
1981
1da177e4 1982 /* Update firmware options. */
e315cd28 1983 qla2x00_set_fw_options(vha, ha->fw_options);
1da177e4
LT		 1984}
1985
0107109e 1986void
e315cd28 1987qla24xx_update_fw_options(scsi_qla_host_t *vha)
0107109e
AV		 1988{
1989 int rval;
e315cd28 1990 struct qla_hw_data *ha = vha->hw;
0107109e 1991
7ec0effd 1992 if (IS_P3P_TYPE(ha))
a9083016
GM		 1993 return;
1994
0107109e 1995 /* Update Serial Link options. */
f94097ed 1996 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0)
0107109e
AV		 1997 return;
1998
e315cd28 1999 rval = qla2x00_set_serdes_params(vha,
f94097ed
AV		 2000 le16_to_cpu(ha->fw_seriallink_options24[1]),
2001 le16_to_cpu(ha->fw_seriallink_options24[2]),
2002 le16_to_cpu(ha->fw_seriallink_options24[3]));
0107109e 2003 if (rval != QLA_SUCCESS) {
7c3df132 2004 ql_log(ql_log_warn, vha, 0x0104,
0107109e
AV		 2005 "Unable to update Serial Link options (%x).\n", rval);
2006 }
2007}
2008
abbd8870 2009void
e315cd28 2010qla2x00_config_rings(struct scsi_qla_host *vha)
abbd8870 2011{
e315cd28 2012 struct qla_hw_data *ha = vha->hw;
3d71644c 2013 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
73208dfd
AC		 2014 struct req_que *req = ha->req_q_map[0];
2015 struct rsp_que *rsp = ha->rsp_q_map[0];
abbd8870
AV		 2016
2017 /* Setup ring parameters in initialization control block. */
2018 ha->init_cb->request_q_outpointer = __constant_cpu_to_le16(0);
2019 ha->init_cb->response_q_inpointer = __constant_cpu_to_le16(0);
e315cd28
AC		 2020 ha->init_cb->request_q_length = cpu_to_le16(req->length);
2021 ha->init_cb->response_q_length = cpu_to_le16(rsp->length);
2022 ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
2023 ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
2024 ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
2025 ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
abbd8870
AV		 2026
2027 WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0);
2028 WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0);
2029 WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0);
2030 WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0);
2031 RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */
2032}
2033
0107109e 2034void
e315cd28 2035qla24xx_config_rings(struct scsi_qla_host *vha)
0107109e 2036{
e315cd28 2037 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 2038 device_reg_t __iomem *reg = ISP_QUE_REG(ha, 0);
2039 struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
2040 struct qla_msix_entry *msix;
0107109e 2041 struct init_cb_24xx *icb;
73208dfd
AC		 2042 uint16_t rid = 0;
2043 struct req_que *req = ha->req_q_map[0];
2044 struct rsp_que *rsp = ha->rsp_q_map[0];
0107109e 2045
6246b8a1 2046 /* Setup ring parameters in initialization control block. */
0107109e
AV		 2047 icb = (struct init_cb_24xx *)ha->init_cb;
2048 icb->request_q_outpointer = __constant_cpu_to_le16(0);
2049 icb->response_q_inpointer = __constant_cpu_to_le16(0);
e315cd28
AC		 2050 icb->request_q_length = cpu_to_le16(req->length);
2051 icb->response_q_length = cpu_to_le16(rsp->length);
2052 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
2053 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
2054 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
2055 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
0107109e 2056
2d70c103
NB		 2057 /* Setup ATIO queue dma pointers for target mode */
2058 icb->atio_q_inpointer = __constant_cpu_to_le16(0);
2059 icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length);
2060 icb->atio_q_address[0] = cpu_to_le32(LSD(ha->tgt.atio_dma));
2061 icb->atio_q_address[1] = cpu_to_le32(MSD(ha->tgt.atio_dma));
2062
7c6300e3
JC		 2063 if (IS_SHADOW_REG_CAPABLE(ha))
2064 icb->firmware_options_2 |=
2065 __constant_cpu_to_le32(BIT_30|BIT_29);
2066
f73cb695 2067 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
73208dfd
AC		 2068 icb->qos = __constant_cpu_to_le16(QLA_DEFAULT_QUE_QOS);
2069 icb->rid = __constant_cpu_to_le16(rid);
2070 if (ha->flags.msix_enabled) {
2071 msix = &ha->msix_entries[1];
7c3df132
SK		 2072 ql_dbg(ql_dbg_init, vha, 0x00fd,
2073 "Registering vector 0x%x for base que.\n",
2074 msix->entry);
73208dfd
AC		 2075 icb->msix = cpu_to_le16(msix->entry);
2076 }
2077 /* Use alternate PCI bus number */
2078 if (MSB(rid))
2079 icb->firmware_options_2 |=
2080 __constant_cpu_to_le32(BIT_19);
2081 /* Use alternate PCI devfn */
2082 if (LSB(rid))
2083 icb->firmware_options_2 |=
2084 __constant_cpu_to_le32(BIT_18);
2085
3155754a 2086 /* Use Disable MSIX Handshake mode for capable adapters */
6246b8a1
GM		 2087 if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) &&
2088 (ha->flags.msix_enabled)) {
3155754a
AC		 2089 icb->firmware_options_2 &=
2090 __constant_cpu_to_le32(~BIT_22);
2091 ha->flags.disable_msix_handshake = 1;
7c3df132
SK		 2092 ql_dbg(ql_dbg_init, vha, 0x00fe,
2093 "MSIX Handshake Disable Mode turned on.\n");
3155754a
AC		 2094 } else {
2095 icb->firmware_options_2 |=
2096 __constant_cpu_to_le32(BIT_22);
2097 }
73208dfd 2098 icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_23);
73208dfd
AC		 2099
2100 WRT_REG_DWORD(&reg->isp25mq.req_q_in, 0);
2101 WRT_REG_DWORD(&reg->isp25mq.req_q_out, 0);
2102 WRT_REG_DWORD(&reg->isp25mq.rsp_q_in, 0);
2103 WRT_REG_DWORD(&reg->isp25mq.rsp_q_out, 0);
2104 } else {
2105 WRT_REG_DWORD(&reg->isp24.req_q_in, 0);
2106 WRT_REG_DWORD(&reg->isp24.req_q_out, 0);
2107 WRT_REG_DWORD(&reg->isp24.rsp_q_in, 0);
2108 WRT_REG_DWORD(&reg->isp24.rsp_q_out, 0);
2109 }
aa230bc5 2110 qlt_24xx_config_rings(vha);
2d70c103 2111
73208dfd
AC		 2112 /* PCI posting */
2113 RD_REG_DWORD(&ioreg->hccr);
0107109e
AV		 2114}
2115
1da177e4
LT		 2116/**
2117 * qla2x00_init_rings() - Initializes firmware.
2118 * @ha: HA context
2119 *
2120 * Beginning of request ring has initialization control block already built
2121 * by nvram config routine.
2122 *
2123 * Returns 0 on success.
2124 */
8ae6d9c7 2125int
e315cd28 2126qla2x00_init_rings(scsi_qla_host_t *vha)
1da177e4
LT		 2127{
2128 int rval;
2129 unsigned long flags = 0;
29bdccbe 2130 int cnt, que;
e315cd28 2131 struct qla_hw_data *ha = vha->hw;
29bdccbe
AC		 2132 struct req_que *req;
2133 struct rsp_que *rsp;
2c3dfe3f
SJ		 2134 struct mid_init_cb_24xx *mid_init_cb =
2135 (struct mid_init_cb_24xx *) ha->init_cb;
1da177e4
LT		 2136
2137 spin_lock_irqsave(&ha->hardware_lock, flags);
2138
2139 /* Clear outstanding commands array. */
2afa19a9 2140 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe
AC		 2141 req = ha->req_q_map[que];
2142 if (!req)
2143 continue;
7c6300e3
JC		 2144 req->out_ptr = (void *)(req->ring + req->length);
2145 *req->out_ptr = 0;
8d93f550 2146 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++)
29bdccbe 2147 req->outstanding_cmds[cnt] = NULL;
1da177e4 2148
2afa19a9 2149 req->current_outstanding_cmd = 1;
1da177e4 2150
29bdccbe
AC		 2151 /* Initialize firmware. */
2152 req->ring_ptr = req->ring;
2153 req->ring_index = 0;
2154 req->cnt = req->length;
2155 }
1da177e4 2156
2afa19a9 2157 for (que = 0; que < ha->max_rsp_queues; que++) {
29bdccbe
AC		 2158 rsp = ha->rsp_q_map[que];
2159 if (!rsp)
2160 continue;
7c6300e3
JC		 2161 rsp->in_ptr = (void *)(rsp->ring + rsp->length);
2162 *rsp->in_ptr = 0;
29bdccbe 2163 /* Initialize response queue entries */
8ae6d9c7
GM		 2164 if (IS_QLAFX00(ha))
2165 qlafx00_init_response_q_entries(rsp);
2166 else
2167 qla2x00_init_response_q_entries(rsp);
29bdccbe 2168 }
1da177e4 2169
2d70c103
NB		 2170 ha->tgt.atio_ring_ptr = ha->tgt.atio_ring;
2171 ha->tgt.atio_ring_index = 0;
2172 /* Initialize ATIO queue entries */
2173 qlt_init_atio_q_entries(vha);
2174
e315cd28 2175 ha->isp_ops->config_rings(vha);
1da177e4
LT		 2176
2177 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2178
8ae6d9c7
GM		 2179 ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n");
2180
2181 if (IS_QLAFX00(ha)) {
2182 rval = qlafx00_init_firmware(vha, ha->init_cb_size);
2183 goto next_check;
2184 }
2185
1da177e4 2186 /* Update any ISP specific firmware options before initialization. */
e315cd28 2187 ha->isp_ops->update_fw_options(vha);
1da177e4 2188
605aa2bc 2189 if (ha->flags.npiv_supported) {
45980cc2 2190 if (ha->operating_mode == LOOP && !IS_CNA_CAPABLE(ha))
605aa2bc 2191 ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
c48339de 2192 mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
605aa2bc
LC		 2193 }
2194
24a08138
AV		 2195 if (IS_FWI2_CAPABLE(ha)) {
2196 mid_init_cb->options = __constant_cpu_to_le16(BIT_1);
2197 mid_init_cb->init_cb.execution_throttle =
2198 cpu_to_le16(ha->fw_xcb_count);
25232cc9
HM		 2199 /* D-Port Status */
2200 if (IS_DPORT_CAPABLE(ha))
2201 mid_init_cb->init_cb.firmware_options_1 |=
2202 cpu_to_le16(BIT_7);
24a08138 2203 }
2c3dfe3f 2204
e315cd28 2205 rval = qla2x00_init_firmware(vha, ha->init_cb_size);
8ae6d9c7 2206next_check:
1da177e4 2207 if (rval) {
7c3df132
SK		 2208 ql_log(ql_log_fatal, vha, 0x00d2,
2209 "Init Firmware **** FAILED ****.\n");
1da177e4 2210 } else {
7c3df132
SK		 2211 ql_dbg(ql_dbg_init, vha, 0x00d3,
2212 "Init Firmware -- success.\n");
1da177e4
LT		 2213 }
2214
2215 return (rval);
2216}
2217
2218/**
2219 * qla2x00_fw_ready() - Waits for firmware ready.
2220 * @ha: HA context
2221 *
2222 * Returns 0 on success.
2223 */
2224static int
e315cd28 2225qla2x00_fw_ready(scsi_qla_host_t *vha)
1da177e4
LT		 2226{
2227 int rval;
4d4df193 2228 unsigned long wtime, mtime, cs84xx_time;
1da177e4
LT		 2229 uint16_t min_wait; /* Minimum wait time if loop is down */
2230 uint16_t wait_time; /* Wait time if loop is coming ready */
b5a340dd 2231 uint16_t state[6];
e315cd28 2232 struct qla_hw_data *ha = vha->hw;
1da177e4 2233
8ae6d9c7
GM		 2234 if (IS_QLAFX00(vha->hw))
2235 return qlafx00_fw_ready(vha);
2236
1da177e4
LT		 2237 rval = QLA_SUCCESS;
2238
2239 /* 20 seconds for loop down. */
fa2a1ce5 2240 min_wait = 20;
1da177e4
LT		 2241
2242 /*
2243 * Firmware should take at most one RATOV to login, plus 5 seconds for
2244 * our own processing.
2245 */
2246 if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) {
2247 wait_time = min_wait;
2248 }
2249
2250 /* Min wait time if loop down */
2251 mtime = jiffies + (min_wait * HZ);
2252
2253 /* wait time before firmware ready */
2254 wtime = jiffies + (wait_time * HZ);
2255
2256 /* Wait for ISP to finish LIP */
e315cd28 2257 if (!vha->flags.init_done)
7c3df132
SK		 2258 ql_log(ql_log_info, vha, 0x801e,
2259 "Waiting for LIP to complete.\n");
1da177e4
LT		 2260
2261 do {
5b939038 2262 memset(state, -1, sizeof(state));
e315cd28 2263 rval = qla2x00_get_firmware_state(vha, state);
1da177e4 2264 if (rval == QLA_SUCCESS) {
4d4df193 2265 if (state[0] < FSTATE_LOSS_OF_SYNC) {
e315cd28 2266 vha->device_flags &= ~DFLG_NO_CABLE;
1da177e4 2267 }
4d4df193 2268 if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) {
7c3df132
SK		 2269 ql_dbg(ql_dbg_taskm, vha, 0x801f,
2270 "fw_state=%x 84xx=%x.\n", state[0],
2271 state[2]);
4d4df193
HK		 2272 if ((state[2] & FSTATE_LOGGED_IN) &&
2273 (state[2] & FSTATE_WAITING_FOR_VERIFY)) {
7c3df132
SK		 2274 ql_dbg(ql_dbg_taskm, vha, 0x8028,
2275 "Sending verify iocb.\n");
4d4df193
HK		 2276
2277 cs84xx_time = jiffies;
e315cd28 2278 rval = qla84xx_init_chip(vha);
7c3df132
SK		 2279 if (rval != QLA_SUCCESS) {
2280 ql_log(ql_log_warn,
cfb0919c 2281 vha, 0x8007,
7c3df132 2282 "Init chip failed.\n");
4d4df193 2283 break;
7c3df132 2284 }
4d4df193
HK		 2285
2286 /* Add time taken to initialize. */
2287 cs84xx_time = jiffies - cs84xx_time;
2288 wtime += cs84xx_time;
2289 mtime += cs84xx_time;
cfb0919c 2290 ql_dbg(ql_dbg_taskm, vha, 0x8008,
7c3df132
SK		 2291 "Increasing wait time by %ld. "
2292 "New time %ld.\n", cs84xx_time,
2293 wtime);
4d4df193
HK		 2294 }
2295 } else if (state[0] == FSTATE_READY) {
7c3df132
SK		 2296 ql_dbg(ql_dbg_taskm, vha, 0x8037,
2297 "F/W Ready - OK.\n");
1da177e4 2298
e315cd28 2299 qla2x00_get_retry_cnt(vha, &ha->retry_count,
1da177e4
LT		 2300 &ha->login_timeout, &ha->r_a_tov);
2301
2302 rval = QLA_SUCCESS;
2303 break;
2304 }
2305
2306 rval = QLA_FUNCTION_FAILED;
2307
e315cd28 2308 if (atomic_read(&vha->loop_down_timer) &&
4d4df193 2309 state[0] != FSTATE_READY) {
1da177e4 2310 /* Loop down. Timeout on min_wait for states
fa2a1ce5
AV		 2311 * other than Wait for Login.
2312 */
1da177e4 2313 if (time_after_eq(jiffies, mtime)) {
7c3df132 2314 ql_log(ql_log_info, vha, 0x8038,
1da177e4
LT		 2315 "Cable is unplugged...\n");
2316
e315cd28 2317 vha->device_flags |= DFLG_NO_CABLE;
1da177e4
LT		 2318 break;
2319 }
2320 }
2321 } else {
2322 /* Mailbox cmd failed. Timeout on min_wait. */
cdbb0a4f 2323 if (time_after_eq(jiffies, mtime) ||
7190575f 2324 ha->flags.isp82xx_fw_hung)
1da177e4
LT		 2325 break;
2326 }
2327
2328 if (time_after_eq(jiffies, wtime))
2329 break;
2330
2331 /* Delay for a while */
2332 msleep(500);
1da177e4
LT		 2333 } while (1);
2334
7c3df132 2335 ql_dbg(ql_dbg_taskm, vha, 0x803a,
b5a340dd
JC		 2336 "fw_state=%x (%x, %x, %x, %x %x) curr time=%lx.\n", state[0],
2337 state[1], state[2], state[3], state[4], state[5], jiffies);
1da177e4 2338
cfb0919c 2339 if (rval && !(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132
SK		 2340 ql_log(ql_log_warn, vha, 0x803b,
2341 "Firmware ready **** FAILED ****.\n");
1da177e4
LT		 2342 }
2343
2344 return (rval);
2345}
2346
2347/*
2348* qla2x00_configure_hba
2349* Setup adapter context.
2350*
2351* Input:
2352* ha = adapter state pointer.
2353*
2354* Returns:
2355* 0 = success
2356*
2357* Context:
2358* Kernel context.
2359*/
2360static int
e315cd28 2361qla2x00_configure_hba(scsi_qla_host_t *vha)
1da177e4
LT		 2362{
2363 int rval;
2364 uint16_t loop_id;
2365 uint16_t topo;
2c3dfe3f 2366 uint16_t sw_cap;
1da177e4
LT		 2367 uint8_t al_pa;
2368 uint8_t area;
2369 uint8_t domain;
2370 char connect_type[22];
e315cd28 2371 struct qla_hw_data *ha = vha->hw;
f24b5cb8 2372 unsigned long flags;
61e1b269 2373 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 2374
2375 /* Get host addresses. */
e315cd28 2376 rval = qla2x00_get_adapter_id(vha,
2c3dfe3f 2377 &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
1da177e4 2378 if (rval != QLA_SUCCESS) {
e315cd28 2379 if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
6246b8a1 2380 IS_CNA_CAPABLE(ha) ||
33135aa2 2381 (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
7c3df132
SK		 2382 ql_dbg(ql_dbg_disc, vha, 0x2008,
2383 "Loop is in a transition state.\n");
33135aa2 2384 } else {
7c3df132
SK		 2385 ql_log(ql_log_warn, vha, 0x2009,
2386 "Unable to get host loop ID.\n");
61e1b269
JC		 2387 if (IS_FWI2_CAPABLE(ha) && (vha == base_vha) &&
2388 (rval == QLA_COMMAND_ERROR && loop_id == 0x1b)) {
2389 ql_log(ql_log_warn, vha, 0x1151,
2390 "Doing link init.\n");
2391 if (qla24xx_link_initialize(vha) == QLA_SUCCESS)
2392 return rval;
2393 }
e315cd28 2394 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
33135aa2 2395 }
1da177e4
LT		 2396 return (rval);
2397 }
2398
2399 if (topo == 4) {
7c3df132
SK		 2400 ql_log(ql_log_info, vha, 0x200a,
2401 "Cannot get topology - retrying.\n");
1da177e4
LT		 2402 return (QLA_FUNCTION_FAILED);
2403 }
2404
e315cd28 2405 vha->loop_id = loop_id;
1da177e4
LT		 2406
2407 /* initialize */
2408 ha->min_external_loopid = SNS_FIRST_LOOP_ID;
2409 ha->operating_mode = LOOP;
2c3dfe3f 2410 ha->switch_cap = 0;
1da177e4
LT		 2411
2412 switch (topo) {
2413 case 0:
7c3df132 2414 ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n");
1da177e4
LT		 2415 ha->current_topology = ISP_CFG_NL;
2416 strcpy(connect_type, "(Loop)");
2417 break;
2418
2419 case 1:
7c3df132 2420 ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n");
2c3dfe3f 2421 ha->switch_cap = sw_cap;
1da177e4
LT		 2422 ha->current_topology = ISP_CFG_FL;
2423 strcpy(connect_type, "(FL_Port)");
2424 break;
2425
2426 case 2:
7c3df132 2427 ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n");
1da177e4
LT		 2428 ha->operating_mode = P2P;
2429 ha->current_topology = ISP_CFG_N;
2430 strcpy(connect_type, "(N_Port-to-N_Port)");
2431 break;
2432
2433 case 3:
7c3df132 2434 ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n");
2c3dfe3f 2435 ha->switch_cap = sw_cap;
1da177e4
LT		 2436 ha->operating_mode = P2P;
2437 ha->current_topology = ISP_CFG_F;
2438 strcpy(connect_type, "(F_Port)");
2439 break;
2440
2441 default:
7c3df132
SK		 2442 ql_dbg(ql_dbg_disc, vha, 0x200f,
2443 "HBA in unknown topology %x, using NL.\n", topo);
1da177e4
LT		 2444 ha->current_topology = ISP_CFG_NL;
2445 strcpy(connect_type, "(Loop)");
2446 break;
2447 }
2448
2449 /* Save Host port and loop ID. */
2450 /* byte order - Big Endian */
e315cd28
AC		 2451 vha->d_id.b.domain = domain;
2452 vha->d_id.b.area = area;
2453 vha->d_id.b.al_pa = al_pa;
1da177e4 2454
f24b5cb8 2455 spin_lock_irqsave(&ha->vport_slock, flags);
2d70c103 2456 qlt_update_vp_map(vha, SET_AL_PA);
f24b5cb8 2457 spin_unlock_irqrestore(&ha->vport_slock, flags);
2d70c103 2458
e315cd28 2459 if (!vha->flags.init_done)
7c3df132
SK		 2460 ql_log(ql_log_info, vha, 0x2010,
2461 "Topology - %s, Host Loop address 0x%x.\n",
e315cd28 2462 connect_type, vha->loop_id);
1da177e4 2463
1da177e4
LT		 2464 return(rval);
2465}
2466
a9083016 2467inline void
e315cd28
AC		 2468qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
2469 char *def)
9bb9fcf2
AV		 2470{
2471 char *st, *en;
2472 uint16_t index;
e315cd28 2473 struct qla_hw_data *ha = vha->hw;
ab671149 2474 int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
6246b8a1 2475 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha);
9bb9fcf2
AV		 2476
2477 if (memcmp(model, BINZERO, len) != 0) {
2478 strncpy(ha->model_number, model, len);
2479 st = en = ha->model_number;
2480 en += len - 1;
2481 while (en > st) {
2482 if (*en != 0x20 && *en != 0x00)
2483 break;
2484 *en-- = '\0';
2485 }
2486
2487 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 2488 if (use_tbl &&
2489 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2 2490 index < QLA_MODEL_NAMES)
1ee27146
JC		 2491 strncpy(ha->model_desc,
2492 qla2x00_model_name[index * 2 + 1],
2493 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 2494 } else {
2495 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 2496 if (use_tbl &&
2497 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2
AV		 2498 index < QLA_MODEL_NAMES) {
2499 strcpy(ha->model_number,
2500 qla2x00_model_name[index * 2]);
1ee27146
JC		 2501 strncpy(ha->model_desc,
2502 qla2x00_model_name[index * 2 + 1],
2503 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 2504 } else {
2505 strcpy(ha->model_number, def);
2506 }
2507 }
1ee27146 2508 if (IS_FWI2_CAPABLE(ha))
e315cd28 2509 qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc,
1ee27146 2510 sizeof(ha->model_desc));
9bb9fcf2
AV		 2511}
2512
4e08df3f
DM		 2513/* On sparc systems, obtain port and node WWN from firmware
2514 * properties.
2515 */
e315cd28 2516static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv)
4e08df3f
DM		 2517{
2518#ifdef CONFIG_SPARC
e315cd28 2519 struct qla_hw_data *ha = vha->hw;
4e08df3f 2520 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 2521 struct device_node *dp = pci_device_to_OF_node(pdev);
2522 const u8 *val;
4e08df3f
DM		 2523 int len;
2524
2525 val = of_get_property(dp, "port-wwn", &len);
2526 if (val && len >= WWN_SIZE)
2527 memcpy(nv->port_name, val, WWN_SIZE);
2528
2529 val = of_get_property(dp, "node-wwn", &len);
2530 if (val && len >= WWN_SIZE)
2531 memcpy(nv->node_name, val, WWN_SIZE);
2532#endif
2533}
2534
1da177e4
LT		 2535/*
2536* NVRAM configuration for ISP 2xxx
2537*
2538* Input:
2539* ha = adapter block pointer.
2540*
2541* Output:
2542* initialization control block in response_ring
2543* host adapters parameters in host adapter block
2544*
2545* Returns:
2546* 0 = success.
2547*/
abbd8870 2548int
e315cd28 2549qla2x00_nvram_config(scsi_qla_host_t *vha)
1da177e4 2550{
4e08df3f 2551 int rval;
0107109e
AV		 2552 uint8_t chksum = 0;
2553 uint16_t cnt;
2554 uint8_t *dptr1, *dptr2;
e315cd28 2555 struct qla_hw_data *ha = vha->hw;
0107109e 2556 init_cb_t *icb = ha->init_cb;
281afe19
SJ		 2557 nvram_t *nv = ha->nvram;
2558 uint8_t *ptr = ha->nvram;
3d71644c 2559 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 2560
4e08df3f
DM		 2561 rval = QLA_SUCCESS;
2562
1da177e4 2563 /* Determine NVRAM starting address. */
0107109e 2564 ha->nvram_size = sizeof(nvram_t);
1da177e4
LT		 2565 ha->nvram_base = 0;
2566 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
2567 if ((RD_REG_WORD(&reg->ctrl_status) >> 14) == 1)
2568 ha->nvram_base = 0x80;
2569
2570 /* Get NVRAM data and calculate checksum. */
e315cd28 2571 ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size);
0107109e
AV		 2572 for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++)
2573 chksum += *ptr++;
1da177e4 2574
7c3df132
SK		 2575 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
2576 "Contents of NVRAM.\n");
2577 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
2578 (uint8_t *)nv, ha->nvram_size);
1da177e4
LT		 2579
2580 /* Bad NVRAM data, set defaults parameters. */
2581 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' ||
2582 nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) {
2583 /* Reset NVRAM data. */
7c3df132 2584 ql_log(ql_log_warn, vha, 0x0064,
9e336520 2585 "Inconsistent NVRAM "
7c3df132
SK		 2586 "detected: checksum=0x%x id=%c version=0x%x.\n",
2587 chksum, nv->id[0], nv->nvram_version);
2588 ql_log(ql_log_warn, vha, 0x0065,
2589 "Falling back to "
2590 "functioning (yet invalid -- WWPN) defaults.\n");
4e08df3f
DM		 2591
2592 /*
2593 * Set default initialization control block.
2594 */
2595 memset(nv, 0, ha->nvram_size);
2596 nv->parameter_block_version = ICB_VERSION;
2597
2598 if (IS_QLA23XX(ha)) {
2599 nv->firmware_options[0] = BIT_2 | BIT_1;
2600 nv->firmware_options[1] = BIT_7 | BIT_5;
2601 nv->add_firmware_options[0] = BIT_5;
2602 nv->add_firmware_options[1] = BIT_5 | BIT_4;
98aee70d 2603 nv->frame_payload_size = 2048;
4e08df3f
DM		 2604 nv->special_options[1] = BIT_7;
2605 } else if (IS_QLA2200(ha)) {
2606 nv->firmware_options[0] = BIT_2 | BIT_1;
2607 nv->firmware_options[1] = BIT_7 | BIT_5;
2608 nv->add_firmware_options[0] = BIT_5;
2609 nv->add_firmware_options[1] = BIT_5 | BIT_4;
98aee70d 2610 nv->frame_payload_size = 1024;
4e08df3f
DM		 2611 } else if (IS_QLA2100(ha)) {
2612 nv->firmware_options[0] = BIT_3 | BIT_1;
2613 nv->firmware_options[1] = BIT_5;
98aee70d 2614 nv->frame_payload_size = 1024;
4e08df3f
DM		 2615 }
2616
2617 nv->max_iocb_allocation = __constant_cpu_to_le16(256);
2618 nv->execution_throttle = __constant_cpu_to_le16(16);
2619 nv->retry_count = 8;
2620 nv->retry_delay = 1;
2621
2622 nv->port_name[0] = 33;
2623 nv->port_name[3] = 224;
2624 nv->port_name[4] = 139;
2625
e315cd28 2626 qla2xxx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 2627
2628 nv->login_timeout = 4;
2629
2630 /*
2631 * Set default host adapter parameters
2632 */
2633 nv->host_p[1] = BIT_2;
2634 nv->reset_delay = 5;
2635 nv->port_down_retry_count = 8;
2636 nv->max_luns_per_target = __constant_cpu_to_le16(8);
2637 nv->link_down_timeout = 60;
2638
2639 rval = 1;
1da177e4
LT		 2640 }
2641
2642#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
2643 /*
2644 * The SN2 does not provide BIOS emulation which means you can't change
2645 * potentially bogus BIOS settings. Force the use of default settings
2646 * for link rate and frame size. Hope that the rest of the settings
2647 * are valid.
2648 */
2649 if (ia64_platform_is("sn2")) {
98aee70d 2650 nv->frame_payload_size = 2048;
1da177e4
LT		 2651 if (IS_QLA23XX(ha))
2652 nv->special_options[1] = BIT_7;
2653 }
2654#endif
2655
2656 /* Reset Initialization control block */
0107109e 2657 memset(icb, 0, ha->init_cb_size);
1da177e4
LT		 2658
2659 /*
2660 * Setup driver NVRAM options.
2661 */
2662 nv->firmware_options[0] |= (BIT_6 | BIT_1);
2663 nv->firmware_options[0] &= ~(BIT_5 | BIT_4);
2664 nv->firmware_options[1] |= (BIT_5 | BIT_0);
2665 nv->firmware_options[1] &= ~BIT_4;
2666
2667 if (IS_QLA23XX(ha)) {
2668 nv->firmware_options[0] |= BIT_2;
2669 nv->firmware_options[0] &= ~BIT_3;
2d70c103 2670 nv->special_options[0] &= ~BIT_6;
0107109e 2671 nv->add_firmware_options[1] |= BIT_5 | BIT_4;
1da177e4
LT		 2672
2673 if (IS_QLA2300(ha)) {
2674 if (ha->fb_rev == FPM_2310) {
2675 strcpy(ha->model_number, "QLA2310");
2676 } else {
2677 strcpy(ha->model_number, "QLA2300");
2678 }
2679 } else {
e315cd28 2680 qla2x00_set_model_info(vha, nv->model_number,
9bb9fcf2 2681 sizeof(nv->model_number), "QLA23xx");
1da177e4
LT		 2682 }
2683 } else if (IS_QLA2200(ha)) {
2684 nv->firmware_options[0] |= BIT_2;
2685 /*
2686 * 'Point-to-point preferred, else loop' is not a safe
2687 * connection mode setting.
2688 */
2689 if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
2690 (BIT_5 | BIT_4)) {
2691 /* Force 'loop preferred, else point-to-point'. */
2692 nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
2693 nv->add_firmware_options[0] |= BIT_5;
2694 }
2695 strcpy(ha->model_number, "QLA22xx");
2696 } else /*if (IS_QLA2100(ha))*/ {
2697 strcpy(ha->model_number, "QLA2100");
2698 }
2699
2700 /*
2701 * Copy over NVRAM RISC parameter block to initialization control block.
2702 */
2703 dptr1 = (uint8_t *)icb;
2704 dptr2 = (uint8_t *)&nv->parameter_block_version;
2705 cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;
2706 while (cnt--)
2707 *dptr1++ = *dptr2++;
2708
2709 /* Copy 2nd half. */
2710 dptr1 = (uint8_t *)icb->add_firmware_options;
2711 cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;
2712 while (cnt--)
2713 *dptr1++ = *dptr2++;
2714
5341e868
AV		 2715 /* Use alternate WWN? */
2716 if (nv->host_p[1] & BIT_7) {
2717 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
2718 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
2719 }
2720
1da177e4
LT		 2721 /* Prepare nodename */
2722 if ((icb->firmware_options[1] & BIT_6) == 0) {
2723 /*
2724 * Firmware will apply the following mask if the nodename was
2725 * not provided.
2726 */
2727 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
2728 icb->node_name[0] &= 0xF0;
2729 }
2730
2731 /*
2732 * Set host adapter parameters.
2733 */
3ce8866c
SK		 2734
2735 /*
2736 * BIT_7 in the host-parameters section allows for modification to
2737 * internal driver logging.
2738 */
0181944f 2739 if (nv->host_p[0] & BIT_7)
cfb0919c 2740 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
1da177e4
LT		 2741 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
2742 /* Always load RISC code on non ISP2[12]00 chips. */
2743 if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
2744 ha->flags.disable_risc_code_load = 0;
2745 ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0);
2746 ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
2747 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
06c22bd1 2748 ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
d4c760c2 2749 ha->flags.disable_serdes = 0;
1da177e4
LT		 2750
2751 ha->operating_mode =
2752 (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
2753
2754 memcpy(ha->fw_seriallink_options, nv->seriallink_options,
2755 sizeof(ha->fw_seriallink_options));
2756
2757 /* save HBA serial number */
2758 ha->serial0 = icb->port_name[5];
2759 ha->serial1 = icb->port_name[6];
2760 ha->serial2 = icb->port_name[7];
e315cd28
AC		 2761 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
2762 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
1da177e4
LT		 2763
2764 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
2765
2766 ha->retry_count = nv->retry_count;
2767
2768 /* Set minimum login_timeout to 4 seconds. */
5b91490e 2769 if (nv->login_timeout != ql2xlogintimeout)
1da177e4
LT		 2770 nv->login_timeout = ql2xlogintimeout;
2771 if (nv->login_timeout < 4)
2772 nv->login_timeout = 4;
2773 ha->login_timeout = nv->login_timeout;
2774 icb->login_timeout = nv->login_timeout;
2775
00a537b8
AV		 2776 /* Set minimum RATOV to 100 tenths of a second. */
2777 ha->r_a_tov = 100;
1da177e4 2778
1da177e4
LT		 2779 ha->loop_reset_delay = nv->reset_delay;
2780
1da177e4
LT		 2781 /* Link Down Timeout = 0:
2782 *
2783 * When Port Down timer expires we will start returning
2784 * I/O's to OS with "DID_NO_CONNECT".
2785 *
2786 * Link Down Timeout != 0:
2787 *
2788 * The driver waits for the link to come up after link down
2789 * before returning I/Os to OS with "DID_NO_CONNECT".
fa2a1ce5 2790 */
1da177e4
LT		 2791 if (nv->link_down_timeout == 0) {
2792 ha->loop_down_abort_time =
354d6b21 2793 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
1da177e4
LT		 2794 } else {
2795 ha->link_down_timeout = nv->link_down_timeout;
2796 ha->loop_down_abort_time =
2797 (LOOP_DOWN_TIME - ha->link_down_timeout);
fa2a1ce5 2798 }
1da177e4 2799
1da177e4
LT		 2800 /*
2801 * Need enough time to try and get the port back.
2802 */
2803 ha->port_down_retry_count = nv->port_down_retry_count;
2804 if (qlport_down_retry)
2805 ha->port_down_retry_count = qlport_down_retry;
2806 /* Set login_retry_count */
2807 ha->login_retry_count = nv->retry_count;
2808 if (ha->port_down_retry_count == nv->port_down_retry_count &&
2809 ha->port_down_retry_count > 3)
2810 ha->login_retry_count = ha->port_down_retry_count;
2811 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
2812 ha->login_retry_count = ha->port_down_retry_count;
2813 if (ql2xloginretrycount)
2814 ha->login_retry_count = ql2xloginretrycount;
2815
1da177e4
LT		 2816 icb->lun_enables = __constant_cpu_to_le16(0);
2817 icb->command_resource_count = 0;
2818 icb->immediate_notify_resource_count = 0;
2819 icb->timeout = __constant_cpu_to_le16(0);
2820
2821 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
2822 /* Enable RIO */
2823 icb->firmware_options[0] &= ~BIT_3;
2824 icb->add_firmware_options[0] &=
2825 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
2826 icb->add_firmware_options[0] |= BIT_2;
2827 icb->response_accumulation_timer = 3;
2828 icb->interrupt_delay_timer = 5;
2829
e315cd28 2830 vha->flags.process_response_queue = 1;
1da177e4 2831 } else {
4fdfefe5 2832 /* Enable ZIO. */
e315cd28 2833 if (!vha->flags.init_done) {
4fdfefe5
AV		 2834 ha->zio_mode = icb->add_firmware_options[0] &
2835 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
2836 ha->zio_timer = icb->interrupt_delay_timer ?
2837 icb->interrupt_delay_timer: 2;
2838 }
1da177e4
LT		 2839 icb->add_firmware_options[0] &=
2840 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
e315cd28 2841 vha->flags.process_response_queue = 0;
4fdfefe5 2842 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d
AV		 2843 ha->zio_mode = QLA_ZIO_MODE_6;
2844
7c3df132 2845 ql_log(ql_log_info, vha, 0x0068,
4fdfefe5
AV		 2846 "ZIO mode %d enabled; timer delay (%d us).\n",
2847 ha->zio_mode, ha->zio_timer * 100);
1da177e4 2848
4fdfefe5
AV		 2849 icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;
2850 icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;
e315cd28 2851 vha->flags.process_response_queue = 1;
1da177e4
LT		 2852 }
2853 }
2854
4e08df3f 2855 if (rval) {
7c3df132
SK		 2856 ql_log(ql_log_warn, vha, 0x0069,
2857 "NVRAM configuration failed.\n");
4e08df3f
DM		 2858 }
2859 return (rval);
1da177e4
LT		 2860}
2861
19a7b4ae
JSEC		 2862static void
2863qla2x00_rport_del(void *data)
2864{
2865 fc_port_t *fcport = data;
d97994dc 2866 struct fc_rport *rport;
2d70c103 2867 scsi_qla_host_t *vha = fcport->vha;
044d78e1 2868 unsigned long flags;
d97994dc 2869
044d78e1 2870 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
ac280b67 2871 rport = fcport->drport ? fcport->drport: fcport->rport;
d97994dc 2872 fcport->drport = NULL;
044d78e1 2873 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
2d70c103 2874 if (rport) {
d97994dc 2875 fc_remote_port_delete(rport);
2d70c103
NB		 2876 /*
2877 * Release the target mode FC NEXUS in qla_target.c code
2878 * if target mod is enabled.
2879 */
2880 qlt_fc_port_deleted(vha, fcport);
2881 }
19a7b4ae
JSEC		 2882}
2883
1da177e4
LT		 2884/**
2885 * qla2x00_alloc_fcport() - Allocate a generic fcport.
2886 * @ha: HA context
2887 * @flags: allocation flags
2888 *
2889 * Returns a pointer to the allocated fcport, or NULL, if none available.
2890 */
9a069e19 2891fc_port_t *
e315cd28 2892qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags)
1da177e4
LT		 2893{
2894 fc_port_t *fcport;
2895
bbfbbbc1
MK		 2896 fcport = kzalloc(sizeof(fc_port_t), flags);
2897 if (!fcport)
2898 return NULL;
1da177e4
LT		 2899
2900 /* Setup fcport template structure. */
e315cd28 2901 fcport->vha = vha;
1da177e4
LT		 2902 fcport->port_type = FCT_UNKNOWN;
2903 fcport->loop_id = FC_NO_LOOP_ID;
ec426e10 2904 qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
ad3e0eda 2905 fcport->supported_classes = FC_COS_UNSPECIFIED;
1da177e4 2906
bbfbbbc1 2907 return fcport;
1da177e4
LT		 2908}
2909
2910/*
2911 * qla2x00_configure_loop
2912 * Updates Fibre Channel Device Database with what is actually on loop.
2913 *
2914 * Input:
2915 * ha = adapter block pointer.
2916 *
2917 * Returns:
2918 * 0 = success.
2919 * 1 = error.
2920 * 2 = database was full and device was not configured.
2921 */
2922static int
e315cd28 2923qla2x00_configure_loop(scsi_qla_host_t *vha)
1da177e4
LT		 2924{
2925 int rval;
2926 unsigned long flags, save_flags;
e315cd28 2927 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2928 rval = QLA_SUCCESS;
2929
2930 /* Get Initiator ID */
e315cd28
AC		 2931 if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) {
2932 rval = qla2x00_configure_hba(vha);
1da177e4 2933 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2934 ql_dbg(ql_dbg_disc, vha, 0x2013,
2935 "Unable to configure HBA.\n");
1da177e4
LT		 2936 return (rval);
2937 }
2938 }
2939
e315cd28 2940 save_flags = flags = vha->dpc_flags;
7c3df132
SK		 2941 ql_dbg(ql_dbg_disc, vha, 0x2014,
2942 "Configure loop -- dpc flags = 0x%lx.\n", flags);
1da177e4
LT		 2943
2944 /*
2945 * If we have both an RSCN and PORT UPDATE pending then handle them
2946 * both at the same time.
2947 */
e315cd28
AC		 2948 clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2949 clear_bit(RSCN_UPDATE, &vha->dpc_flags);
1da177e4 2950
3064ff39
MH		 2951 qla2x00_get_data_rate(vha);
2952
1da177e4
LT		 2953 /* Determine what we need to do */
2954 if (ha->current_topology == ISP_CFG_FL &&
2955 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
2956
1da177e4
LT		 2957 set_bit(RSCN_UPDATE, &flags);
2958
2959 } else if (ha->current_topology == ISP_CFG_F &&
2960 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
2961
1da177e4
LT		 2962 set_bit(RSCN_UPDATE, &flags);
2963 clear_bit(LOCAL_LOOP_UPDATE, &flags);
21333b48
AV		 2964
2965 } else if (ha->current_topology == ISP_CFG_N) {
2966 clear_bit(RSCN_UPDATE, &flags);
1da177e4 2967
e315cd28 2968 } else if (!vha->flags.online ||
1da177e4
LT		 2969 (test_bit(ABORT_ISP_ACTIVE, &flags))) {
2970
1da177e4
LT		 2971 set_bit(RSCN_UPDATE, &flags);
2972 set_bit(LOCAL_LOOP_UPDATE, &flags);
2973 }
2974
2975 if (test_bit(LOCAL_LOOP_UPDATE, &flags)) {
7c3df132
SK		 2976 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
2977 ql_dbg(ql_dbg_disc, vha, 0x2015,
2978 "Loop resync needed, failing.\n");
1da177e4 2979 rval = QLA_FUNCTION_FAILED;
642ef983 2980 } else
e315cd28 2981 rval = qla2x00_configure_local_loop(vha);
1da177e4
LT		 2982 }
2983
2984 if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
7c3df132
SK		 2985 if (LOOP_TRANSITION(vha)) {
2986 ql_dbg(ql_dbg_disc, vha, 0x201e,
2987 "Needs RSCN update and loop transition.\n");
1da177e4 2988 rval = QLA_FUNCTION_FAILED;
7c3df132 2989 }
e315cd28
AC		 2990 else
2991 rval = qla2x00_configure_fabric(vha);
1da177e4
LT		 2992 }
2993
2994 if (rval == QLA_SUCCESS) {
e315cd28
AC		 2995 if (atomic_read(&vha->loop_down_timer) ||
2996 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4
LT		 2997 rval = QLA_FUNCTION_FAILED;
2998 } else {
e315cd28 2999 atomic_set(&vha->loop_state, LOOP_READY);
7c3df132
SK		 3000 ql_dbg(ql_dbg_disc, vha, 0x2069,
3001 "LOOP READY.\n");
1da177e4
LT		 3002 }
3003 }
3004
3005 if (rval) {
7c3df132
SK		 3006 ql_dbg(ql_dbg_disc, vha, 0x206a,
3007 "%s *** FAILED ***.\n", __func__);
1da177e4 3008 } else {
7c3df132
SK		 3009 ql_dbg(ql_dbg_disc, vha, 0x206b,
3010 "%s: exiting normally.\n", __func__);
1da177e4
LT		 3011 }
3012
cc3ef7bc 3013 /* Restore state if a resync event occurred during processing */
e315cd28 3014 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4 3015 if (test_bit(LOCAL_LOOP_UPDATE, &save_flags))
e315cd28 3016 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
f4658b6c 3017 if (test_bit(RSCN_UPDATE, &save_flags)) {
e315cd28 3018 set_bit(RSCN_UPDATE, &vha->dpc_flags);
f4658b6c 3019 }
1da177e4
LT		 3020 }
3021
3022 return (rval);
3023}
3024
3025
3026
3027/*
3028 * qla2x00_configure_local_loop
3029 * Updates Fibre Channel Device Database with local loop devices.
3030 *
3031 * Input:
3032 * ha = adapter block pointer.
3033 *
3034 * Returns:
3035 * 0 = success.
3036 */
3037static int
e315cd28 3038qla2x00_configure_local_loop(scsi_qla_host_t *vha)
1da177e4
LT		 3039{
3040 int rval, rval2;
3041 int found_devs;
3042 int found;
3043 fc_port_t *fcport, *new_fcport;
3044
3045 uint16_t index;
3046 uint16_t entries;
3047 char *id_iter;
3048 uint16_t loop_id;
3049 uint8_t domain, area, al_pa;
e315cd28 3050 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3051
3052 found_devs = 0;
3053 new_fcport = NULL;
642ef983 3054 entries = MAX_FIBRE_DEVICES_LOOP;
1da177e4 3055
1da177e4 3056 /* Get list of logged in devices. */
642ef983 3057 memset(ha->gid_list, 0, qla2x00_gid_list_size(ha));
e315cd28 3058 rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma,
1da177e4
LT		 3059 &entries);
3060 if (rval != QLA_SUCCESS)
3061 goto cleanup_allocation;
3062
7c3df132
SK		 3063 ql_dbg(ql_dbg_disc, vha, 0x2017,
3064 "Entries in ID list (%d).\n", entries);
3065 ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
3066 (uint8_t *)ha->gid_list,
3067 entries * sizeof(struct gid_list_info));
1da177e4
LT		 3068
3069 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 3070 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3071 if (new_fcport == NULL) {
7c3df132
SK		 3072 ql_log(ql_log_warn, vha, 0x2018,
3073 "Memory allocation failed for fcport.\n");
1da177e4
LT		 3074 rval = QLA_MEMORY_ALLOC_FAILED;
3075 goto cleanup_allocation;
3076 }
3077 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
3078
3079 /*
3080 * Mark local devices that were present with FCF_DEVICE_LOST for now.
3081 */
e315cd28 3082 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 3083 if (atomic_read(&fcport->state) == FCS_ONLINE &&
3084 fcport->port_type != FCT_BROADCAST &&
3085 (fcport->flags & FCF_FABRIC_DEVICE) == 0) {
3086
7c3df132
SK		 3087 ql_dbg(ql_dbg_disc, vha, 0x2019,
3088 "Marking port lost loop_id=0x%04x.\n",
3089 fcport->loop_id);
1da177e4 3090
ec426e10 3091 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3092 }
3093 }
3094
3095 /* Add devices to port list. */
3096 id_iter = (char *)ha->gid_list;
3097 for (index = 0; index < entries; index++) {
3098 domain = ((struct gid_list_info *)id_iter)->domain;
3099 area = ((struct gid_list_info *)id_iter)->area;
3100 al_pa = ((struct gid_list_info *)id_iter)->al_pa;
abbd8870 3101 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1da177e4
LT		 3102 loop_id = (uint16_t)
3103 ((struct gid_list_info *)id_iter)->loop_id_2100;
abbd8870 3104 else
1da177e4
LT		 3105 loop_id = le16_to_cpu(
3106 ((struct gid_list_info *)id_iter)->loop_id);
abbd8870 3107 id_iter += ha->gid_list_info_size;
1da177e4
LT		 3108
3109 /* Bypass reserved domain fields. */
3110 if ((domain & 0xf0) == 0xf0)
3111 continue;
3112
3113 /* Bypass if not same domain and area of adapter. */
f7d289f6 3114 if (area && domain &&
e315cd28 3115 (area != vha->d_id.b.area || domain != vha->d_id.b.domain))
1da177e4
LT		 3116 continue;
3117
3118 /* Bypass invalid local loop ID. */
3119 if (loop_id > LAST_LOCAL_LOOP_ID)
3120 continue;
3121
370d550e
AE		 3122 memset(new_fcport, 0, sizeof(fc_port_t));
3123
1da177e4
LT		 3124 /* Fill in member data. */
3125 new_fcport->d_id.b.domain = domain;
3126 new_fcport->d_id.b.area = area;
3127 new_fcport->d_id.b.al_pa = al_pa;
3128 new_fcport->loop_id = loop_id;
e315cd28 3129 rval2 = qla2x00_get_port_database(vha, new_fcport, 0);
1da177e4 3130 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 3131 ql_dbg(ql_dbg_disc, vha, 0x201a,
3132 "Failed to retrieve fcport information "
3133 "-- get_port_database=%x, loop_id=0x%04x.\n",
3134 rval2, new_fcport->loop_id);
3135 ql_dbg(ql_dbg_disc, vha, 0x201b,
3136 "Scheduling resync.\n");
e315cd28 3137 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4
LT		 3138 continue;
3139 }
3140
3141 /* Check for matching device in port list. */
3142 found = 0;
3143 fcport = NULL;
e315cd28 3144 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 3145 if (memcmp(new_fcport->port_name, fcport->port_name,
3146 WWN_SIZE))
3147 continue;
3148
ddb9b126 3149 fcport->flags &= ~FCF_FABRIC_DEVICE;
1da177e4
LT		 3150 fcport->loop_id = new_fcport->loop_id;
3151 fcport->port_type = new_fcport->port_type;
3152 fcport->d_id.b24 = new_fcport->d_id.b24;
3153 memcpy(fcport->node_name, new_fcport->node_name,
3154 WWN_SIZE);
3155
3156 found++;
3157 break;
3158 }
3159
3160 if (!found) {
3161 /* New device, add to fcports list. */
e315cd28 3162 list_add_tail(&new_fcport->list, &vha->vp_fcports);
1da177e4
LT		 3163
3164 /* Allocate a new replacement fcport. */
3165 fcport = new_fcport;
e315cd28 3166 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3167 if (new_fcport == NULL) {
7c3df132
SK		 3168 ql_log(ql_log_warn, vha, 0x201c,
3169 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 3170 rval = QLA_MEMORY_ALLOC_FAILED;
3171 goto cleanup_allocation;
3172 }
3173 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
3174 }
3175
d8b45213 3176 /* Base iIDMA settings on HBA port speed. */
a3cbdfad 3177 fcport->fp_speed = ha->link_data_rate;
d8b45213 3178
e315cd28 3179 qla2x00_update_fcport(vha, fcport);
1da177e4
LT		 3180
3181 found_devs++;
3182 }
3183
3184cleanup_allocation:
c9475cb0 3185 kfree(new_fcport);
1da177e4
LT		 3186
3187 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3188 ql_dbg(ql_dbg_disc, vha, 0x201d,
3189 "Configure local loop error exit: rval=%x.\n", rval);
1da177e4
LT		 3190 }
3191
1da177e4
LT		 3192 return (rval);
3193}
3194
d8b45213 3195static void
e315cd28 3196qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
d8b45213 3197{
d8b45213 3198 int rval;
93f2bd67 3199 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 3200 struct qla_hw_data *ha = vha->hw;
d8b45213 3201
c76f2c01 3202 if (!IS_IIDMA_CAPABLE(ha))
d8b45213
AV		 3203 return;
3204
c9afb9a2
GM		 3205 if (atomic_read(&fcport->state) != FCS_ONLINE)
3206 return;
3207
39bd9622
AV		 3208 if (fcport->fp_speed == PORT_SPEED_UNKNOWN ||
3209 fcport->fp_speed > ha->link_data_rate)
d8b45213
AV		 3210 return;
3211
e315cd28 3212 rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed,
a3cbdfad 3213 mb);
d8b45213 3214 if (rval != QLA_SUCCESS) {
7c3df132 3215 ql_dbg(ql_dbg_disc, vha, 0x2004,
7b833558
OK		 3216 "Unable to adjust iIDMA %8phN -- %04x %x %04x %04x.\n",
3217 fcport->port_name, rval, fcport->fp_speed, mb[0], mb[1]);
d8b45213 3218 } else {
7c3df132 3219 ql_dbg(ql_dbg_disc, vha, 0x2005,
7b833558 3220 "iIDMA adjusted to %s GB/s on %8phN.\n",
d0297c9a 3221 qla2x00_get_link_speed_str(ha, fcport->fp_speed),
7b833558 3222 fcport->port_name);
d8b45213
AV		 3223 }
3224}
3225
23be331d 3226static void
e315cd28 3227qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport)
8482e118
AV		 3228{
3229 struct fc_rport_identifiers rport_ids;
bdf79621 3230 struct fc_rport *rport;
044d78e1 3231 unsigned long flags;
8482e118 3232
ac280b67 3233 qla2x00_rport_del(fcport);
8482e118 3234
f8b02a85
AV		 3235 rport_ids.node_name = wwn_to_u64(fcport->node_name);
3236 rport_ids.port_name = wwn_to_u64(fcport->port_name);
8482e118
AV		 3237 rport_ids.port_id = fcport->d_id.b.domain << 16 |
3238 fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa;
77d74143 3239 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
e315cd28 3240 fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids);
77d74143 3241 if (!rport) {
7c3df132
SK		 3242 ql_log(ql_log_warn, vha, 0x2006,
3243 "Unable to allocate fc remote port.\n");
77d74143
AV		 3244 return;
3245 }
2d70c103
NB		 3246 /*
3247 * Create target mode FC NEXUS in qla_target.c if target mode is
3248 * enabled..
3249 */
3250 qlt_fc_port_added(vha, fcport);
3251
044d78e1 3252 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
19a7b4ae 3253 *((fc_port_t **)rport->dd_data) = fcport;
044d78e1 3254 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
d97994dc 3255
ad3e0eda 3256 rport->supported_classes = fcport->supported_classes;
77d74143 3257
8482e118
AV		 3258 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
3259 if (fcport->port_type == FCT_INITIATOR)
3260 rport_ids.roles |= FC_RPORT_ROLE_FCP_INITIATOR;
3261 if (fcport->port_type == FCT_TARGET)
3262 rport_ids.roles |= FC_RPORT_ROLE_FCP_TARGET;
77d74143 3263 fc_remote_port_rolechg(rport, rport_ids.roles);
1da177e4
LT		 3264}
3265
23be331d
AB		 3266/*
3267 * qla2x00_update_fcport
3268 * Updates device on list.
3269 *
3270 * Input:
3271 * ha = adapter block pointer.
3272 * fcport = port structure pointer.
3273 *
3274 * Return:
3275 * 0 - Success
3276 * BIT_0 - error
3277 *
3278 * Context:
3279 * Kernel context.
3280 */
3281void
e315cd28 3282qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
23be331d 3283{
e315cd28 3284 fcport->vha = vha;
8ae6d9c7
GM		 3285
3286 if (IS_QLAFX00(vha->hw)) {
3287 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
3288 qla2x00_reg_remote_port(vha, fcport);
3289 return;
3290 }
23be331d 3291 fcport->login_retry = 0;
5ff1d584 3292 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
23be331d 3293
1f93da52 3294 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
e315cd28 3295 qla2x00_iidma_fcport(vha, fcport);
21090cbe 3296 qla24xx_update_fcport_fcp_prio(vha, fcport);
e315cd28 3297 qla2x00_reg_remote_port(vha, fcport);
23be331d
AB		 3298}
3299
1da177e4
LT		 3300/*
3301 * qla2x00_configure_fabric
3302 * Setup SNS devices with loop ID's.
3303 *
3304 * Input:
3305 * ha = adapter block pointer.
3306 *
3307 * Returns:
3308 * 0 = success.
3309 * BIT_0 = error
3310 */
3311static int
e315cd28 3312qla2x00_configure_fabric(scsi_qla_host_t *vha)
1da177e4 3313{
b3b02e6e 3314 int rval;
e452ceb6 3315 fc_port_t *fcport, *fcptemp;
1da177e4
LT		 3316 uint16_t next_loopid;
3317 uint16_t mb[MAILBOX_REGISTER_COUNT];
0107109e 3318 uint16_t loop_id;
1da177e4 3319 LIST_HEAD(new_fcports);
e315cd28
AC		 3320 struct qla_hw_data *ha = vha->hw;
3321 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 3322
3323 /* If FL port exists, then SNS is present */
e428924c 3324 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 3325 loop_id = NPH_F_PORT;
3326 else
3327 loop_id = SNS_FL_PORT;
e315cd28 3328 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1);
1da177e4 3329 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3330 ql_dbg(ql_dbg_disc, vha, 0x201f,
3331 "MBX_GET_PORT_NAME failed, No FL Port.\n");
1da177e4 3332
e315cd28 3333 vha->device_flags &= ~SWITCH_FOUND;
1da177e4
LT		 3334 return (QLA_SUCCESS);
3335 }
e315cd28 3336 vha->device_flags |= SWITCH_FOUND;
1da177e4 3337
1da177e4 3338 do {
cca5335c
AV		 3339 /* FDMI support. */
3340 if (ql2xfdmienable &&
e315cd28
AC		 3341 test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags))
3342 qla2x00_fdmi_register(vha);
cca5335c 3343
1da177e4 3344 /* Ensure we are logged into the SNS. */
e428924c 3345 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 3346 loop_id = NPH_SNS;
3347 else
3348 loop_id = SIMPLE_NAME_SERVER;
0b91d116
CD		 3349 rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff,
3350 0xfc, mb, BIT_1|BIT_0);
3351 if (rval != QLA_SUCCESS) {
3352 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
e452ceb6 3353 return rval;
0b91d116 3354 }
1da177e4 3355 if (mb[0] != MBS_COMMAND_COMPLETE) {
7c3df132
SK		 3356 ql_dbg(ql_dbg_disc, vha, 0x2042,
3357 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x "
3358 "mb[6]=%x mb[7]=%x.\n", loop_id, mb[0], mb[1],
3359 mb[2], mb[6], mb[7]);
1da177e4
LT		 3360 return (QLA_SUCCESS);
3361 }
3362
e315cd28
AC		 3363 if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) {
3364 if (qla2x00_rft_id(vha)) {
1da177e4 3365 /* EMPTY */
7c3df132
SK		 3366 ql_dbg(ql_dbg_disc, vha, 0x2045,
3367 "Register FC-4 TYPE failed.\n");
1da177e4 3368 }
e315cd28 3369 if (qla2x00_rff_id(vha)) {
1da177e4 3370 /* EMPTY */
7c3df132
SK		 3371 ql_dbg(ql_dbg_disc, vha, 0x2049,
3372 "Register FC-4 Features failed.\n");
1da177e4 3373 }
e315cd28 3374 if (qla2x00_rnn_id(vha)) {
1da177e4 3375 /* EMPTY */
7c3df132
SK		 3376 ql_dbg(ql_dbg_disc, vha, 0x204f,
3377 "Register Node Name failed.\n");
e315cd28 3378 } else if (qla2x00_rsnn_nn(vha)) {
1da177e4 3379 /* EMPTY */
7c3df132
SK		 3380 ql_dbg(ql_dbg_disc, vha, 0x2053,
3381 "Register Symobilic Node Name failed.\n");
1da177e4
LT		 3382 }
3383 }
3384
827210ba
JC		 3385#define QLA_FCPORT_SCAN 1
3386#define QLA_FCPORT_FOUND 2
3387
3388 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3389 fcport->scan_state = QLA_FCPORT_SCAN;
3390 }
3391
e315cd28 3392 rval = qla2x00_find_all_fabric_devs(vha, &new_fcports);
1da177e4
LT		 3393 if (rval != QLA_SUCCESS)
3394 break;
3395
e452ceb6
JC		 3396 /*
3397 * Logout all previous fabric devices marked lost, except
3398 * FCP2 devices.
3399 */
e315cd28
AC		 3400 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3401 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
1da177e4
LT		 3402 break;
3403
3404 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0)
3405 continue;
3406
827210ba 3407 if (fcport->scan_state == QLA_FCPORT_SCAN &&
b3b02e6e 3408 atomic_read(&fcport->state) == FCS_ONLINE) {
e315cd28 3409 qla2x00_mark_device_lost(vha, fcport,
d97994dc 3410 ql2xplogiabsentdevice, 0);
1da177e4 3411 if (fcport->loop_id != FC_NO_LOOP_ID &&
f08b7251 3412 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
1da177e4
LT		 3413 fcport->port_type != FCT_INITIATOR &&
3414 fcport->port_type != FCT_BROADCAST) {
e315cd28 3415 ha->isp_ops->fabric_logout(vha,
1c7c6357
AV		 3416 fcport->loop_id,
3417 fcport->d_id.b.domain,
3418 fcport->d_id.b.area,
3419 fcport->d_id.b.al_pa);
1a5c69bf 3420 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 3421 }
3422 }
e452ceb6 3423 }
1da177e4 3424
e452ceb6
JC		 3425 /* Starting free loop ID. */
3426 next_loopid = ha->min_external_loopid;
3427
3428 /*
3429 * Scan through our port list and login entries that need to be
3430 * logged in.
3431 */
3432 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3433 if (atomic_read(&vha->loop_down_timer) ||
3434 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3435 break;
3436
3437 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0 ||
3438 (fcport->flags & FCF_LOGIN_NEEDED) == 0)
3439 continue;
3440
3441 if (fcport->loop_id == FC_NO_LOOP_ID) {
3442 fcport->loop_id = next_loopid;
3443 rval = qla2x00_find_new_loop_id(
3444 base_vha, fcport);
3445 if (rval != QLA_SUCCESS) {
3446 /* Ran out of IDs to use */
3447 break;
1da177e4
LT		 3448 }
3449 }
e452ceb6
JC		 3450 /* Login and update database */
3451 qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
3452 }
3453
3454 /* Exit if out of loop IDs. */
3455 if (rval != QLA_SUCCESS) {
3456 break;
3457 }
3458
3459 /*
3460 * Login and add the new devices to our port list.
3461 */
3462 list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) {
3463 if (atomic_read(&vha->loop_down_timer) ||
3464 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3465 break;
3466
3467 /* Find a new loop ID to use. */
3468 fcport->loop_id = next_loopid;
3469 rval = qla2x00_find_new_loop_id(base_vha, fcport);
3470 if (rval != QLA_SUCCESS) {
3471 /* Ran out of IDs to use */
3472 break;
3473 }
1da177e4 3474
bdf79621 3475 /* Login and update database */
e315cd28 3476 qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
e452ceb6
JC		 3477
3478 list_move_tail(&fcport->list, &vha->vp_fcports);
1da177e4
LT		 3479 }
3480 } while (0);
3481
e452ceb6
JC		 3482 /* Free all new device structures not processed. */
3483 list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) {
3484 list_del(&fcport->list);
3485 kfree(fcport);
3486 }
3487
1da177e4 3488 if (rval) {
7c3df132
SK		 3489 ql_dbg(ql_dbg_disc, vha, 0x2068,
3490 "Configure fabric error exit rval=%d.\n", rval);
1da177e4
LT		 3491 }
3492
3493 return (rval);
3494}
3495
1da177e4
LT		 3496/*
3497 * qla2x00_find_all_fabric_devs
3498 *
3499 * Input:
3500 * ha = adapter block pointer.
3501 * dev = database device entry pointer.
3502 *
3503 * Returns:
3504 * 0 = success.
3505 *
3506 * Context:
3507 * Kernel context.
3508 */
3509static int
e315cd28
AC		 3510qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha,
3511 struct list_head *new_fcports)
1da177e4
LT		 3512{
3513 int rval;
3514 uint16_t loop_id;
3515 fc_port_t *fcport, *new_fcport, *fcptemp;
3516 int found;
3517
3518 sw_info_t *swl;
3519 int swl_idx;
3520 int first_dev, last_dev;
1516ef44 3521 port_id_t wrap = {}, nxt_d_id;
e315cd28 3522 struct qla_hw_data *ha = vha->hw;
bb4cf5b7 3523 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 3524
3525 rval = QLA_SUCCESS;
3526
3527 /* Try GID_PT to get device list, else GAN. */
7a67735b 3528 if (!ha->swl)
642ef983 3529 ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t),
7a67735b
AV		 3530 GFP_KERNEL);
3531 swl = ha->swl;
bbfbbbc1 3532 if (!swl) {
1da177e4 3533 /*EMPTY*/
7c3df132
SK		 3534 ql_dbg(ql_dbg_disc, vha, 0x2054,
3535 "GID_PT allocations failed, fallback on GA_NXT.\n");
1da177e4 3536 } else {
642ef983 3537 memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t));
e315cd28 3538 if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) {
1da177e4 3539 swl = NULL;
e315cd28 3540 } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 3541 swl = NULL;
e315cd28 3542 } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 3543 swl = NULL;
e5896bd5 3544 } else if (ql2xiidmaenable &&
e315cd28
AC		 3545 qla2x00_gfpn_id(vha, swl) == QLA_SUCCESS) {
3546 qla2x00_gpsc(vha, swl);
1da177e4 3547 }
e8c72ba5
CD		 3548
3549 /* If other queries succeeded probe for FC-4 type */
3550 if (swl)
3551 qla2x00_gff_id(vha, swl);
1da177e4
LT		 3552 }
3553 swl_idx = 0;
3554
3555 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 3556 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3557 if (new_fcport == NULL) {
7c3df132
SK		 3558 ql_log(ql_log_warn, vha, 0x205e,
3559 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 3560 return (QLA_MEMORY_ALLOC_FAILED);
3561 }
3562 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
1da177e4
LT		 3563 /* Set start port ID scan at adapter ID. */
3564 first_dev = 1;
3565 last_dev = 0;
3566
3567 /* Starting free loop ID. */
e315cd28
AC		 3568 loop_id = ha->min_external_loopid;
3569 for (; loop_id <= ha->max_loop_id; loop_id++) {
3570 if (qla2x00_is_reserved_id(vha, loop_id))
1da177e4
LT		 3571 continue;
3572
3a6478df
GM		 3573 if (ha->current_topology == ISP_CFG_FL &&
3574 (atomic_read(&vha->loop_down_timer) ||
3575 LOOP_TRANSITION(vha))) {
bb2d52b2
AV		 3576 atomic_set(&vha->loop_down_timer, 0);
3577 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
3578 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
1da177e4 3579 break;
bb2d52b2 3580 }
1da177e4
LT		 3581
3582 if (swl != NULL) {
3583 if (last_dev) {
3584 wrap.b24 = new_fcport->d_id.b24;
3585 } else {
3586 new_fcport->d_id.b24 = swl[swl_idx].d_id.b24;
3587 memcpy(new_fcport->node_name,
3588 swl[swl_idx].node_name, WWN_SIZE);
3589 memcpy(new_fcport->port_name,
3590 swl[swl_idx].port_name, WWN_SIZE);
d8b45213
AV		 3591 memcpy(new_fcport->fabric_port_name,
3592 swl[swl_idx].fabric_port_name, WWN_SIZE);
3593 new_fcport->fp_speed = swl[swl_idx].fp_speed;
e8c72ba5 3594 new_fcport->fc4_type = swl[swl_idx].fc4_type;
1da177e4
LT		 3595
3596 if (swl[swl_idx].d_id.b.rsvd_1 != 0) {
3597 last_dev = 1;
3598 }
3599 swl_idx++;
3600 }
3601 } else {
3602 /* Send GA_NXT to the switch */
e315cd28 3603 rval = qla2x00_ga_nxt(vha, new_fcport);
1da177e4 3604 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3605 ql_log(ql_log_warn, vha, 0x2064,
3606 "SNS scan failed -- assuming "
3607 "zero-entry result.\n");
1da177e4
LT		 3608 list_for_each_entry_safe(fcport, fcptemp,
3609 new_fcports, list) {
3610 list_del(&fcport->list);
3611 kfree(fcport);
3612 }
3613 rval = QLA_SUCCESS;
3614 break;
3615 }
3616 }
3617
3618 /* If wrap on switch device list, exit. */
3619 if (first_dev) {
3620 wrap.b24 = new_fcport->d_id.b24;
3621 first_dev = 0;
3622 } else if (new_fcport->d_id.b24 == wrap.b24) {
7c3df132
SK		 3623 ql_dbg(ql_dbg_disc, vha, 0x2065,
3624 "Device wrap (%02x%02x%02x).\n",
3625 new_fcport->d_id.b.domain,
3626 new_fcport->d_id.b.area,
3627 new_fcport->d_id.b.al_pa);
1da177e4
LT		 3628 break;
3629 }
3630
2c3dfe3f 3631 /* Bypass if same physical adapter. */
e315cd28 3632 if (new_fcport->d_id.b24 == base_vha->d_id.b24)
1da177e4
LT		 3633 continue;
3634
2c3dfe3f 3635 /* Bypass virtual ports of the same host. */
bb4cf5b7
CD		 3636 if (qla2x00_is_a_vp_did(vha, new_fcport->d_id.b24))
3637 continue;
2c3dfe3f 3638
f7d289f6
AV		 3639 /* Bypass if same domain and area of adapter. */
3640 if (((new_fcport->d_id.b24 & 0xffff00) ==
e315cd28 3641 (vha->d_id.b24 & 0xffff00)) && ha->current_topology ==
f7d289f6
AV		 3642 ISP_CFG_FL)
3643 continue;
3644
1da177e4
LT		 3645 /* Bypass reserved domain fields. */
3646 if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0)
3647 continue;
3648
e8c72ba5 3649 /* Bypass ports whose FCP-4 type is not FCP_SCSI */
4da26e16
CD		 3650 if (ql2xgffidenable &&
3651 (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI &&
3652 new_fcport->fc4_type != FC4_TYPE_UNKNOWN))
e8c72ba5
CD		 3653 continue;
3654
1da177e4
LT		 3655 /* Locate matching device in database. */
3656 found = 0;
e315cd28 3657 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 3658 if (memcmp(new_fcport->port_name, fcport->port_name,
3659 WWN_SIZE))
3660 continue;
3661
827210ba 3662 fcport->scan_state = QLA_FCPORT_FOUND;
b3b02e6e 3663
1da177e4
LT		 3664 found++;
3665
d8b45213
AV		 3666 /* Update port state. */
3667 memcpy(fcport->fabric_port_name,
3668 new_fcport->fabric_port_name, WWN_SIZE);
3669 fcport->fp_speed = new_fcport->fp_speed;
3670
1da177e4
LT		 3671 /*
3672 * If address the same and state FCS_ONLINE, nothing
3673 * changed.
3674 */
3675 if (fcport->d_id.b24 == new_fcport->d_id.b24 &&
3676 atomic_read(&fcport->state) == FCS_ONLINE) {
3677 break;
3678 }
3679
3680 /*
3681 * If device was not a fabric device before.
3682 */
3683 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) {
3684 fcport->d_id.b24 = new_fcport->d_id.b24;
5f16b331 3685 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 3686 fcport->flags |= (FCF_FABRIC_DEVICE |
3687 FCF_LOGIN_NEEDED);
1da177e4
LT		 3688 break;
3689 }
3690
3691 /*
3692 * Port ID changed or device was marked to be updated;
3693 * Log it out if still logged in and mark it for
3694 * relogin later.
3695 */
3696 fcport->d_id.b24 = new_fcport->d_id.b24;
3697 fcport->flags |= FCF_LOGIN_NEEDED;
3698 if (fcport->loop_id != FC_NO_LOOP_ID &&
f08b7251 3699 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
0eba25df 3700 (fcport->flags & FCF_ASYNC_SENT) == 0 &&
1da177e4
LT		 3701 fcport->port_type != FCT_INITIATOR &&
3702 fcport->port_type != FCT_BROADCAST) {
e315cd28 3703 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3704 fcport->d_id.b.domain, fcport->d_id.b.area,
3705 fcport->d_id.b.al_pa);
5f16b331 3706 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 3707 }
3708
3709 break;
3710 }
3711
3712 if (found)
3713 continue;
1da177e4
LT		 3714 /* If device was not in our fcports list, then add it. */
3715 list_add_tail(&new_fcport->list, new_fcports);
3716
3717 /* Allocate a new replacement fcport. */
3718 nxt_d_id.b24 = new_fcport->d_id.b24;
e315cd28 3719 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3720 if (new_fcport == NULL) {
7c3df132
SK		 3721 ql_log(ql_log_warn, vha, 0x2066,
3722 "Memory allocation failed for fcport.\n");
1da177e4
LT		 3723 return (QLA_MEMORY_ALLOC_FAILED);
3724 }
3725 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
3726 new_fcport->d_id.b24 = nxt_d_id.b24;
3727 }
3728
c9475cb0 3729 kfree(new_fcport);
1da177e4 3730
1da177e4
LT		 3731 return (rval);
3732}
3733
3734/*
3735 * qla2x00_find_new_loop_id
3736 * Scan through our port list and find a new usable loop ID.
3737 *
3738 * Input:
3739 * ha: adapter state pointer.
3740 * dev: port structure pointer.
3741 *
3742 * Returns:
3743 * qla2x00 local function return status code.
3744 *
3745 * Context:
3746 * Kernel context.
3747 */
03bcfb57 3748int
e315cd28 3749qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
1da177e4
LT		 3750{
3751 int rval;
e315cd28 3752 struct qla_hw_data *ha = vha->hw;
feafb7b1 3753 unsigned long flags = 0;
1da177e4
LT		 3754
3755 rval = QLA_SUCCESS;
3756
5f16b331 3757 spin_lock_irqsave(&ha->vport_slock, flags);
1da177e4 3758
5f16b331
CD		 3759 dev->loop_id = find_first_zero_bit(ha->loop_id_map,
3760 LOOPID_MAP_SIZE);
3761 if (dev->loop_id >= LOOPID_MAP_SIZE ||
3762 qla2x00_is_reserved_id(vha, dev->loop_id)) {
3763 dev->loop_id = FC_NO_LOOP_ID;
3764 rval = QLA_FUNCTION_FAILED;
3765 } else
3766 set_bit(dev->loop_id, ha->loop_id_map);
1da177e4 3767
5f16b331 3768 spin_unlock_irqrestore(&ha->vport_slock, flags);
1da177e4 3769
5f16b331
CD		 3770 if (rval == QLA_SUCCESS)
3771 ql_dbg(ql_dbg_disc, dev->vha, 0x2086,
3772 "Assigning new loopid=%x, portid=%x.\n",
3773 dev->loop_id, dev->d_id.b24);
3774 else
3775 ql_log(ql_log_warn, dev->vha, 0x2087,
3776 "No loop_id's available, portid=%x.\n",
3777 dev->d_id.b24);
1da177e4
LT		 3778
3779 return (rval);
3780}
3781
1da177e4
LT		 3782/*
3783 * qla2x00_fabric_dev_login
3784 * Login fabric target device and update FC port database.
3785 *
3786 * Input:
3787 * ha: adapter state pointer.
3788 * fcport: port structure list pointer.
3789 * next_loopid: contains value of a new loop ID that can be used
3790 * by the next login attempt.
3791 *
3792 * Returns:
3793 * qla2x00 local function return status code.
3794 *
3795 * Context:
3796 * Kernel context.
3797 */
3798static int
e315cd28 3799qla2x00_fabric_dev_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 3800 uint16_t *next_loopid)
3801{
3802 int rval;
3803 int retry;
0107109e 3804 uint8_t opts;
e315cd28 3805 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3806
3807 rval = QLA_SUCCESS;
3808 retry = 0;
3809
ac280b67 3810 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584
AV		 3811 if (fcport->flags & FCF_ASYNC_SENT)
3812 return rval;
3813 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 3814 rval = qla2x00_post_async_login_work(vha, fcport, NULL);
3815 if (!rval)
3816 return rval;
3817 }
3818
5ff1d584 3819 fcport->flags &= ~FCF_ASYNC_SENT;
e315cd28 3820 rval = qla2x00_fabric_login(vha, fcport, next_loopid);
1da177e4 3821 if (rval == QLA_SUCCESS) {
f08b7251 3822 /* Send an ADISC to FCP2 devices.*/
0107109e 3823 opts = 0;
f08b7251 3824 if (fcport->flags & FCF_FCP2_DEVICE)
0107109e 3825 opts |= BIT_1;
e315cd28 3826 rval = qla2x00_get_port_database(vha, fcport, opts);
1da177e4 3827 if (rval != QLA_SUCCESS) {
e315cd28 3828 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3829 fcport->d_id.b.domain, fcport->d_id.b.area,
3830 fcport->d_id.b.al_pa);
e315cd28 3831 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4 3832 } else {
e315cd28 3833 qla2x00_update_fcport(vha, fcport);
1da177e4 3834 }
0b91d116
CD		 3835 } else {
3836 /* Retry Login. */
3837 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 3838 }
3839
3840 return (rval);
3841}
3842
3843/*
3844 * qla2x00_fabric_login
3845 * Issue fabric login command.
3846 *
3847 * Input:
3848 * ha = adapter block pointer.
3849 * device = pointer to FC device type structure.
3850 *
3851 * Returns:
3852 * 0 - Login successfully
3853 * 1 - Login failed
3854 * 2 - Initiator device
3855 * 3 - Fatal error
3856 */
3857int
e315cd28 3858qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 3859 uint16_t *next_loopid)
3860{
3861 int rval;
3862 int retry;
3863 uint16_t tmp_loopid;
3864 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 3865 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3866
3867 retry = 0;
3868 tmp_loopid = 0;
3869
3870 for (;;) {
7c3df132
SK		 3871 ql_dbg(ql_dbg_disc, vha, 0x2000,
3872 "Trying Fabric Login w/loop id 0x%04x for port "
3873 "%02x%02x%02x.\n",
3874 fcport->loop_id, fcport->d_id.b.domain,
3875 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 3876
3877 /* Login fcport on switch. */
0b91d116 3878 rval = ha->isp_ops->fabric_login(vha, fcport->loop_id,
1da177e4
LT		 3879 fcport->d_id.b.domain, fcport->d_id.b.area,
3880 fcport->d_id.b.al_pa, mb, BIT_0);
0b91d116
CD		 3881 if (rval != QLA_SUCCESS) {
3882 return rval;
3883 }
1da177e4
LT		 3884 if (mb[0] == MBS_PORT_ID_USED) {
3885 /*
3886 * Device has another loop ID. The firmware team
0107109e
AV		 3887 * recommends the driver perform an implicit login with
3888 * the specified ID again. The ID we just used is save
3889 * here so we return with an ID that can be tried by
3890 * the next login.
1da177e4
LT		 3891 */
3892 retry++;
3893 tmp_loopid = fcport->loop_id;
3894 fcport->loop_id = mb[1];
3895
7c3df132
SK		 3896 ql_dbg(ql_dbg_disc, vha, 0x2001,
3897 "Fabric Login: port in use - next loop "
3898 "id=0x%04x, port id= %02x%02x%02x.\n",
1da177e4 3899 fcport->loop_id, fcport->d_id.b.domain,
7c3df132 3900 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 3901
3902 } else if (mb[0] == MBS_COMMAND_COMPLETE) {
3903 /*
3904 * Login succeeded.
3905 */
3906 if (retry) {
3907 /* A retry occurred before. */
3908 *next_loopid = tmp_loopid;
3909 } else {
3910 /*
3911 * No retry occurred before. Just increment the
3912 * ID value for next login.
3913 */
3914 *next_loopid = (fcport->loop_id + 1);
3915 }
3916
3917 if (mb[1] & BIT_0) {
3918 fcport->port_type = FCT_INITIATOR;
3919 } else {
3920 fcport->port_type = FCT_TARGET;
3921 if (mb[1] & BIT_1) {
8474f3a0 3922 fcport->flags |= FCF_FCP2_DEVICE;
1da177e4
LT		 3923 }
3924 }
3925
ad3e0eda
AV		 3926 if (mb[10] & BIT_0)
3927 fcport->supported_classes |= FC_COS_CLASS2;
3928 if (mb[10] & BIT_1)
3929 fcport->supported_classes |= FC_COS_CLASS3;
3930
2d70c103
NB		 3931 if (IS_FWI2_CAPABLE(ha)) {
3932 if (mb[10] & BIT_7)
3933 fcport->flags |=
3934 FCF_CONF_COMP_SUPPORTED;
3935 }
3936
1da177e4
LT		 3937 rval = QLA_SUCCESS;
3938 break;
3939 } else if (mb[0] == MBS_LOOP_ID_USED) {
3940 /*
3941 * Loop ID already used, try next loop ID.
3942 */
3943 fcport->loop_id++;
e315cd28 3944 rval = qla2x00_find_new_loop_id(vha, fcport);
1da177e4
LT		 3945 if (rval != QLA_SUCCESS) {
3946 /* Ran out of loop IDs to use */
3947 break;
3948 }
3949 } else if (mb[0] == MBS_COMMAND_ERROR) {
3950 /*
3951 * Firmware possibly timed out during login. If NO
3952 * retries are left to do then the device is declared
3953 * dead.
3954 */
3955 *next_loopid = fcport->loop_id;
e315cd28 3956 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3957 fcport->d_id.b.domain, fcport->d_id.b.area,
3958 fcport->d_id.b.al_pa);
e315cd28 3959 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 3960
3961 rval = 1;
3962 break;
3963 } else {
3964 /*
3965 * unrecoverable / not handled error
3966 */
7c3df132
SK		 3967 ql_dbg(ql_dbg_disc, vha, 0x2002,
3968 "Failed=%x port_id=%02x%02x%02x loop_id=%x "
3969 "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain,
3970 fcport->d_id.b.area, fcport->d_id.b.al_pa,
3971 fcport->loop_id, jiffies);
1da177e4
LT		 3972
3973 *next_loopid = fcport->loop_id;
e315cd28 3974 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3975 fcport->d_id.b.domain, fcport->d_id.b.area,
3976 fcport->d_id.b.al_pa);
5f16b331 3977 qla2x00_clear_loop_id(fcport);
0eedfcf0 3978 fcport->login_retry = 0;
1da177e4
LT		 3979
3980 rval = 3;
3981 break;
3982 }
3983 }
3984
3985 return (rval);
3986}
3987
3988/*
3989 * qla2x00_local_device_login
3990 * Issue local device login command.
3991 *
3992 * Input:
3993 * ha = adapter block pointer.
3994 * loop_id = loop id of device to login to.
3995 *
3996 * Returns (Where's the #define!!!!):
3997 * 0 - Login successfully
3998 * 1 - Login failed
3999 * 3 - Fatal error
4000 */
4001int
e315cd28 4002qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport)
1da177e4
LT		 4003{
4004 int rval;
4005 uint16_t mb[MAILBOX_REGISTER_COUNT];
4006
4007 memset(mb, 0, sizeof(mb));
e315cd28 4008 rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0);
1da177e4
LT		 4009 if (rval == QLA_SUCCESS) {
4010 /* Interrogate mailbox registers for any errors */
4011 if (mb[0] == MBS_COMMAND_ERROR)
4012 rval = 1;
4013 else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR)
4014 /* device not in PCB table */
4015 rval = 3;
4016 }
4017
4018 return (rval);
4019}
4020
4021/*
4022 * qla2x00_loop_resync
4023 * Resync with fibre channel devices.
4024 *
4025 * Input:
4026 * ha = adapter block pointer.
4027 *
4028 * Returns:
4029 * 0 = success
4030 */
4031int
e315cd28 4032qla2x00_loop_resync(scsi_qla_host_t *vha)
1da177e4 4033{
73208dfd 4034 int rval = QLA_SUCCESS;
1da177e4 4035 uint32_t wait_time;
67c2e93a
AC		 4036 struct req_que *req;
4037 struct rsp_que *rsp;
4038
7163ea81 4039 if (vha->hw->flags.cpu_affinity_enabled)
67c2e93a
AC		 4040 req = vha->hw->req_q_map[0];
4041 else
4042 req = vha->req;
4043 rsp = req->rsp;
1da177e4 4044
e315cd28
AC		 4045 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
4046 if (vha->flags.online) {
4047 if (!(rval = qla2x00_fw_ready(vha))) {
1da177e4
LT		 4048 /* Wait at most MAX_TARGET RSCNs for a stable link. */
4049 wait_time = 256;
4050 do {
8ae6d9c7
GM		 4051 if (!IS_QLAFX00(vha->hw)) {
4052 /*
4053 * Issue a marker after FW becomes
4054 * ready.
4055 */
4056 qla2x00_marker(vha, req, rsp, 0, 0,
4057 MK_SYNC_ALL);
4058 vha->marker_needed = 0;
4059 }
1da177e4
LT		 4060
4061 /* Remap devices on Loop. */
e315cd28 4062 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4 4063
8ae6d9c7
GM		 4064 if (IS_QLAFX00(vha->hw))
4065 qlafx00_configure_devices(vha);
4066 else
4067 qla2x00_configure_loop(vha);
4068
1da177e4 4069 wait_time--;
e315cd28
AC		 4070 } while (!atomic_read(&vha->loop_down_timer) &&
4071 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
4072 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
4073 &vha->dpc_flags)));
1da177e4 4074 }
1da177e4
LT		 4075 }
4076
e315cd28 4077 if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
1da177e4 4078 return (QLA_FUNCTION_FAILED);
1da177e4 4079
e315cd28 4080 if (rval)
7c3df132
SK		 4081 ql_dbg(ql_dbg_disc, vha, 0x206c,
4082 "%s *** FAILED ***.\n", __func__);
1da177e4
LT		 4083
4084 return (rval);
4085}
4086
579d12b5
SK		 4087/*
4088* qla2x00_perform_loop_resync
4089* Description: This function will set the appropriate flags and call
4090* qla2x00_loop_resync. If successful loop will be resynced
4091* Arguments : scsi_qla_host_t pointer
4092* returm : Success or Failure
4093*/
4094
4095int qla2x00_perform_loop_resync(scsi_qla_host_t *ha)
4096{
4097 int32_t rval = 0;
4098
4099 if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) {
4100 /*Configure the flags so that resync happens properly*/
4101 atomic_set(&ha->loop_down_timer, 0);
4102 if (!(ha->device_flags & DFLG_NO_CABLE)) {
4103 atomic_set(&ha->loop_state, LOOP_UP);
4104 set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags);
4105 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
4106 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
4107
4108 rval = qla2x00_loop_resync(ha);
4109 } else
4110 atomic_set(&ha->loop_state, LOOP_DEAD);
4111
4112 clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags);
4113 }
4114
4115 return rval;
4116}
4117
d97994dc 4118void
67becc00 4119qla2x00_update_fcports(scsi_qla_host_t *base_vha)
d97994dc
AV		 4120{
4121 fc_port_t *fcport;
feafb7b1
AE		 4122 struct scsi_qla_host *vha;
4123 struct qla_hw_data *ha = base_vha->hw;
4124 unsigned long flags;
d97994dc 4125
feafb7b1 4126 spin_lock_irqsave(&ha->vport_slock, flags);
d97994dc 4127 /* Go with deferred removal of rport references. */
feafb7b1
AE		 4128 list_for_each_entry(vha, &base_vha->hw->vp_list, list) {
4129 atomic_inc(&vha->vref_count);
4130 list_for_each_entry(fcport, &vha->vp_fcports, list) {
8ae598d0 4131 if (fcport->drport &&
feafb7b1
AE		 4132 atomic_read(&fcport->state) != FCS_UNCONFIGURED) {
4133 spin_unlock_irqrestore(&ha->vport_slock, flags);
67becc00 4134 qla2x00_rport_del(fcport);
feafb7b1
AE		 4135 spin_lock_irqsave(&ha->vport_slock, flags);
4136 }
4137 }
4138 atomic_dec(&vha->vref_count);
4139 }
4140 spin_unlock_irqrestore(&ha->vport_slock, flags);
d97994dc
AV		 4141}
4142
7d613ac6
SV		 4143/* Assumes idc_lock always held on entry */
4144void
4145qla83xx_reset_ownership(scsi_qla_host_t *vha)
4146{
4147 struct qla_hw_data *ha = vha->hw;
4148 uint32_t drv_presence, drv_presence_mask;
4149 uint32_t dev_part_info1, dev_part_info2, class_type;
4150 uint32_t class_type_mask = 0x3;
4151 uint16_t fcoe_other_function = 0xffff, i;
4152
7ec0effd
AD		 4153 if (IS_QLA8044(ha)) {
4154 drv_presence = qla8044_rd_direct(vha,
4155 QLA8044_CRB_DRV_ACTIVE_INDEX);
4156 dev_part_info1 = qla8044_rd_direct(vha,
4157 QLA8044_CRB_DEV_PART_INFO_INDEX);
4158 dev_part_info2 = qla8044_rd_direct(vha,
4159 QLA8044_CRB_DEV_PART_INFO2);
4160 } else {
4161 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4162 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1);
4163 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2);
4164 }
7d613ac6
SV		 4165 for (i = 0; i < 8; i++) {
4166 class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask);
4167 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
4168 (i != ha->portnum)) {
4169 fcoe_other_function = i;
4170 break;
4171 }
4172 }
4173 if (fcoe_other_function == 0xffff) {
4174 for (i = 0; i < 8; i++) {
4175 class_type = ((dev_part_info2 >> (i * 4)) &
4176 class_type_mask);
4177 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
4178 ((i + 8) != ha->portnum)) {
4179 fcoe_other_function = i + 8;
4180 break;
4181 }
4182 }
4183 }
4184 /*
4185 * Prepare drv-presence mask based on fcoe functions present.
4186 * However consider only valid physical fcoe function numbers (0-15).
4187 */
4188 drv_presence_mask = ~((1 << (ha->portnum)) |
4189 ((fcoe_other_function == 0xffff) ?
4190 0 : (1 << (fcoe_other_function))));
4191
4192 /* We are the reset owner iff:
4193 * - No other protocol drivers present.
4194 * - This is the lowest among fcoe functions. */
4195 if (!(drv_presence & drv_presence_mask) &&
4196 (ha->portnum < fcoe_other_function)) {
4197 ql_dbg(ql_dbg_p3p, vha, 0xb07f,
4198 "This host is Reset owner.\n");
4199 ha->flags.nic_core_reset_owner = 1;
4200 }
4201}
4202
fa492630 4203static int
7d613ac6
SV		 4204__qla83xx_set_drv_ack(scsi_qla_host_t *vha)
4205{
4206 int rval = QLA_SUCCESS;
4207 struct qla_hw_data *ha = vha->hw;
4208 uint32_t drv_ack;
4209
4210 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4211 if (rval == QLA_SUCCESS) {
4212 drv_ack |= (1 << ha->portnum);
4213 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
4214 }
4215
4216 return rval;
4217}
4218
fa492630 4219static int
7d613ac6
SV		 4220__qla83xx_clear_drv_ack(scsi_qla_host_t *vha)
4221{
4222 int rval = QLA_SUCCESS;
4223 struct qla_hw_data *ha = vha->hw;
4224 uint32_t drv_ack;
4225
4226 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4227 if (rval == QLA_SUCCESS) {
4228 drv_ack &= ~(1 << ha->portnum);
4229 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
4230 }
4231
4232 return rval;
4233}
4234
fa492630 4235static const char *
7d613ac6
SV		 4236qla83xx_dev_state_to_string(uint32_t dev_state)
4237{
4238 switch (dev_state) {
4239 case QLA8XXX_DEV_COLD:
4240 return "COLD/RE-INIT";
4241 case QLA8XXX_DEV_INITIALIZING:
4242 return "INITIALIZING";
4243 case QLA8XXX_DEV_READY:
4244 return "READY";
4245 case QLA8XXX_DEV_NEED_RESET:
4246 return "NEED RESET";
4247 case QLA8XXX_DEV_NEED_QUIESCENT:
4248 return "NEED QUIESCENT";
4249 case QLA8XXX_DEV_FAILED:
4250 return "FAILED";
4251 case QLA8XXX_DEV_QUIESCENT:
4252 return "QUIESCENT";
4253 default:
4254 return "Unknown";
4255 }
4256}
4257
4258/* Assumes idc-lock always held on entry */
4259void
4260qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type)
4261{
4262 struct qla_hw_data *ha = vha->hw;
4263 uint32_t idc_audit_reg = 0, duration_secs = 0;
4264
4265 switch (audit_type) {
4266 case IDC_AUDIT_TIMESTAMP:
4267 ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000);
4268 idc_audit_reg = (ha->portnum) |
4269 (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8);
4270 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
4271 break;
4272
4273 case IDC_AUDIT_COMPLETION:
4274 duration_secs = ((jiffies_to_msecs(jiffies) -
4275 jiffies_to_msecs(ha->idc_audit_ts)) / 1000);
4276 idc_audit_reg = (ha->portnum) |
4277 (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8);
4278 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
4279 break;
4280
4281 default:
4282 ql_log(ql_log_warn, vha, 0xb078,
4283 "Invalid audit type specified.\n");
4284 break;
4285 }
4286}
4287
4288/* Assumes idc_lock always held on entry */
fa492630 4289static int
7d613ac6
SV		 4290qla83xx_initiating_reset(scsi_qla_host_t *vha)
4291{
4292 struct qla_hw_data *ha = vha->hw;
4293 uint32_t idc_control, dev_state;
4294
4295 __qla83xx_get_idc_control(vha, &idc_control);
4296 if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) {
4297 ql_log(ql_log_info, vha, 0xb080,
4298 "NIC Core reset has been disabled. idc-control=0x%x\n",
4299 idc_control);
4300 return QLA_FUNCTION_FAILED;
4301 }
4302
4303 /* Set NEED-RESET iff in READY state and we are the reset-owner */
4304 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4305 if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) {
4306 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
4307 QLA8XXX_DEV_NEED_RESET);
4308 ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n");
4309 qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP);
4310 } else {
4311 const char *state = qla83xx_dev_state_to_string(dev_state);
4312 ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n", state);
4313
4314 /* SV: XXX: Is timeout required here? */
4315 /* Wait for IDC state change READY -> NEED_RESET */
4316 while (dev_state == QLA8XXX_DEV_READY) {
4317 qla83xx_idc_unlock(vha, 0);
4318 msleep(200);
4319 qla83xx_idc_lock(vha, 0);
4320 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4321 }
4322 }
4323
4324 /* Send IDC ack by writing to drv-ack register */
4325 __qla83xx_set_drv_ack(vha);
4326
4327 return QLA_SUCCESS;
4328}
4329
4330int
4331__qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control)
4332{
4333 return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
4334}
4335
7d613ac6
SV		 4336int
4337__qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control)
4338{
4339 return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
4340}
4341
fa492630 4342static int
7d613ac6
SV		 4343qla83xx_check_driver_presence(scsi_qla_host_t *vha)
4344{
4345 uint32_t drv_presence = 0;
4346 struct qla_hw_data *ha = vha->hw;
4347
4348 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4349 if (drv_presence & (1 << ha->portnum))
4350 return QLA_SUCCESS;
4351 else
4352 return QLA_TEST_FAILED;
4353}
4354
4355int
4356qla83xx_nic_core_reset(scsi_qla_host_t *vha)
4357{
4358 int rval = QLA_SUCCESS;
4359 struct qla_hw_data *ha = vha->hw;
4360
4361 ql_dbg(ql_dbg_p3p, vha, 0xb058,
4362 "Entered %s().\n", __func__);
4363
4364 if (vha->device_flags & DFLG_DEV_FAILED) {
4365 ql_log(ql_log_warn, vha, 0xb059,
4366 "Device in unrecoverable FAILED state.\n");
4367 return QLA_FUNCTION_FAILED;
4368 }
4369
4370 qla83xx_idc_lock(vha, 0);
4371
4372 if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) {
4373 ql_log(ql_log_warn, vha, 0xb05a,
4374 "Function=0x%x has been removed from IDC participation.\n",
4375 ha->portnum);
4376 rval = QLA_FUNCTION_FAILED;
4377 goto exit;
4378 }
4379
4380 qla83xx_reset_ownership(vha);
4381
4382 rval = qla83xx_initiating_reset(vha);
4383
4384 /*
4385 * Perform reset if we are the reset-owner,
4386 * else wait till IDC state changes to READY/FAILED.
4387 */
4388 if (rval == QLA_SUCCESS) {
4389 rval = qla83xx_idc_state_handler(vha);
4390
4391 if (rval == QLA_SUCCESS)
4392 ha->flags.nic_core_hung = 0;
4393 __qla83xx_clear_drv_ack(vha);
4394 }
4395
4396exit:
4397 qla83xx_idc_unlock(vha, 0);
4398
4399 ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__);
4400
4401 return rval;
4402}
4403
81178772
SK		 4404int
4405qla2xxx_mctp_dump(scsi_qla_host_t *vha)
4406{
4407 struct qla_hw_data *ha = vha->hw;
4408 int rval = QLA_FUNCTION_FAILED;
4409
4410 if (!IS_MCTP_CAPABLE(ha)) {
4411 /* This message can be removed from the final version */
4412 ql_log(ql_log_info, vha, 0x506d,
4413 "This board is not MCTP capable\n");
4414 return rval;
4415 }
4416
4417 if (!ha->mctp_dump) {
4418 ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev,
4419 MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL);
4420
4421 if (!ha->mctp_dump) {
4422 ql_log(ql_log_warn, vha, 0x506e,
4423 "Failed to allocate memory for mctp dump\n");
4424 return rval;
4425 }
4426 }
4427
4428#define MCTP_DUMP_STR_ADDR 0x00000000
4429 rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma,
4430 MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4);
4431 if (rval != QLA_SUCCESS) {
4432 ql_log(ql_log_warn, vha, 0x506f,
4433 "Failed to capture mctp dump\n");
4434 } else {
4435 ql_log(ql_log_info, vha, 0x5070,
4436 "Mctp dump capture for host (%ld/%p).\n",
4437 vha->host_no, ha->mctp_dump);
4438 ha->mctp_dumped = 1;
4439 }
4440
409ee0fe 4441 if (!ha->flags.nic_core_reset_hdlr_active && !ha->portnum) {
81178772
SK		 4442 ha->flags.nic_core_reset_hdlr_active = 1;
4443 rval = qla83xx_restart_nic_firmware(vha);
4444 if (rval)
4445 /* NIC Core reset failed. */
4446 ql_log(ql_log_warn, vha, 0x5071,
4447 "Failed to restart nic firmware\n");
4448 else
4449 ql_dbg(ql_dbg_p3p, vha, 0xb084,
4450 "Restarted NIC firmware successfully.\n");
4451 ha->flags.nic_core_reset_hdlr_active = 0;
4452 }
4453
4454 return rval;
4455
4456}
4457
579d12b5 4458/*
8fcd6b8b 4459* qla2x00_quiesce_io
579d12b5
SK		 4460* Description: This function will block the new I/Os
4461* Its not aborting any I/Os as context
4462* is not destroyed during quiescence
4463* Arguments: scsi_qla_host_t
4464* return : void
4465*/
4466void
8fcd6b8b 4467qla2x00_quiesce_io(scsi_qla_host_t *vha)
579d12b5
SK		 4468{
4469 struct qla_hw_data *ha = vha->hw;
4470 struct scsi_qla_host *vp;
4471
8fcd6b8b
CD		 4472 ql_dbg(ql_dbg_dpc, vha, 0x401d,
4473 "Quiescing I/O - ha=%p.\n", ha);
579d12b5
SK		 4474
4475 atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME);
4476 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
4477 atomic_set(&vha->loop_state, LOOP_DOWN);
4478 qla2x00_mark_all_devices_lost(vha, 0);
4479 list_for_each_entry(vp, &ha->vp_list, list)
8fcd6b8b 4480 qla2x00_mark_all_devices_lost(vp, 0);
579d12b5
SK		 4481 } else {
4482 if (!atomic_read(&vha->loop_down_timer))
4483 atomic_set(&vha->loop_down_timer,
4484 LOOP_DOWN_TIME);
4485 }
4486 /* Wait for pending cmds to complete */
4487 qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST);
4488}
4489
a9083016
GM		 4490void
4491qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
4492{
4493 struct qla_hw_data *ha = vha->hw;
579d12b5 4494 struct scsi_qla_host *vp;
feafb7b1 4495 unsigned long flags;
6aef87be 4496 fc_port_t *fcport;
a9083016 4497
e46ef004
SK		 4498 /* For ISP82XX, driver waits for completion of the commands.
4499 * online flag should be set.
4500 */
7ec0effd 4501 if (!(IS_P3P_TYPE(ha)))
e46ef004 4502 vha->flags.online = 0;
a9083016
GM		 4503 ha->flags.chip_reset_done = 0;
4504 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2be21fa2 4505 vha->qla_stats.total_isp_aborts++;
a9083016 4506
7c3df132
SK		 4507 ql_log(ql_log_info, vha, 0x00af,
4508 "Performing ISP error recovery - ha=%p.\n", ha);
a9083016 4509
e46ef004
SK		 4510 /* For ISP82XX, reset_chip is just disabling interrupts.
4511 * Driver waits for the completion of the commands.
4512 * the interrupts need to be enabled.
4513 */
7ec0effd 4514 if (!(IS_P3P_TYPE(ha)))
a9083016
GM		 4515 ha->isp_ops->reset_chip(vha);
4516
4517 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
4518 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
4519 atomic_set(&vha->loop_state, LOOP_DOWN);
4520 qla2x00_mark_all_devices_lost(vha, 0);
feafb7b1
AE		 4521
4522 spin_lock_irqsave(&ha->vport_slock, flags);
579d12b5 4523 list_for_each_entry(vp, &ha->vp_list, list) {
feafb7b1
AE		 4524 atomic_inc(&vp->vref_count);
4525 spin_unlock_irqrestore(&ha->vport_slock, flags);
4526
a9083016 4527 qla2x00_mark_all_devices_lost(vp, 0);
feafb7b1
AE		 4528
4529 spin_lock_irqsave(&ha->vport_slock, flags);
4530 atomic_dec(&vp->vref_count);
4531 }
4532 spin_unlock_irqrestore(&ha->vport_slock, flags);
a9083016
GM		 4533 } else {
4534 if (!atomic_read(&vha->loop_down_timer))
4535 atomic_set(&vha->loop_down_timer,
4536 LOOP_DOWN_TIME);
4537 }
4538
6aef87be
AV		 4539 /* Clear all async request states across all VPs. */
4540 list_for_each_entry(fcport, &vha->vp_fcports, list)
4541 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
4542 spin_lock_irqsave(&ha->vport_slock, flags);
4543 list_for_each_entry(vp, &ha->vp_list, list) {
4544 atomic_inc(&vp->vref_count);
4545 spin_unlock_irqrestore(&ha->vport_slock, flags);
4546
4547 list_for_each_entry(fcport, &vp->vp_fcports, list)
4548 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
4549
4550 spin_lock_irqsave(&ha->vport_slock, flags);
4551 atomic_dec(&vp->vref_count);
4552 }
4553 spin_unlock_irqrestore(&ha->vport_slock, flags);
4554
bddd2d65
LC		 4555 if (!ha->flags.eeh_busy) {
4556 /* Make sure for ISP 82XX IO DMA is complete */
7ec0effd 4557 if (IS_P3P_TYPE(ha)) {
7190575f 4558 qla82xx_chip_reset_cleanup(vha);
7c3df132
SK		 4559 ql_log(ql_log_info, vha, 0x00b4,
4560 "Done chip reset cleanup.\n");
a9083016 4561
e46ef004
SK		 4562 /* Done waiting for pending commands.
4563 * Reset the online flag.
4564 */
4565 vha->flags.online = 0;
4d78c973 4566 }
a9083016 4567
bddd2d65
LC		 4568 /* Requeue all commands in outstanding command list. */
4569 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
4570 }
a9083016
GM		 4571}
4572
1da177e4
LT		 4573/*
4574* qla2x00_abort_isp
4575* Resets ISP and aborts all outstanding commands.
4576*
4577* Input:
4578* ha = adapter block pointer.
4579*
4580* Returns:
4581* 0 = success
4582*/
4583int
e315cd28 4584qla2x00_abort_isp(scsi_qla_host_t *vha)
1da177e4 4585{
476e8978 4586 int rval;
1da177e4 4587 uint8_t status = 0;
e315cd28
AC		 4588 struct qla_hw_data *ha = vha->hw;
4589 struct scsi_qla_host *vp;
73208dfd 4590 struct req_que *req = ha->req_q_map[0];
feafb7b1 4591 unsigned long flags;
1da177e4 4592
e315cd28 4593 if (vha->flags.online) {
a9083016 4594 qla2x00_abort_isp_cleanup(vha);
1da177e4 4595
a6171297
SV		 4596 if (IS_QLA8031(ha)) {
4597 ql_dbg(ql_dbg_p3p, vha, 0xb05c,
4598 "Clearing fcoe driver presence.\n");
4599 if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS)
4600 ql_dbg(ql_dbg_p3p, vha, 0xb073,
4601 "Error while clearing DRV-Presence.\n");
4602 }
4603
85880801
AV		 4604 if (unlikely(pci_channel_offline(ha->pdev) &&
4605 ha->flags.pci_channel_io_perm_failure)) {
4606 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
4607 status = 0;
4608 return status;
4609 }
4610
73208dfd 4611 ha->isp_ops->get_flash_version(vha, req->ring);
30c47662 4612
e315cd28 4613 ha->isp_ops->nvram_config(vha);
1da177e4 4614
e315cd28
AC		 4615 if (!qla2x00_restart_isp(vha)) {
4616 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4 4617
e315cd28 4618 if (!atomic_read(&vha->loop_down_timer)) {
1da177e4
LT		 4619 /*
4620 * Issue marker command only when we are going
4621 * to start the I/O .
4622 */
e315cd28 4623 vha->marker_needed = 1;
1da177e4
LT		 4624 }
4625
e315cd28 4626 vha->flags.online = 1;
1da177e4 4627
fd34f556 4628 ha->isp_ops->enable_intrs(ha);
1da177e4 4629
fa2a1ce5 4630 ha->isp_abort_cnt = 0;
e315cd28 4631 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
476e8978 4632
6246b8a1
GM		 4633 if (IS_QLA81XX(ha) || IS_QLA8031(ha))
4634 qla2x00_get_fw_version(vha);
df613b96
AV		 4635 if (ha->fce) {
4636 ha->flags.fce_enabled = 1;
4637 memset(ha->fce, 0,
4638 fce_calc_size(ha->fce_bufs));
e315cd28 4639 rval = qla2x00_enable_fce_trace(vha,
df613b96
AV		 4640 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
4641 &ha->fce_bufs);
4642 if (rval) {
7c3df132 4643 ql_log(ql_log_warn, vha, 0x8033,
df613b96
AV		 4644 "Unable to reinitialize FCE "
4645 "(%d).\n", rval);
4646 ha->flags.fce_enabled = 0;
4647 }
4648 }
436a7b11
AV		 4649
4650 if (ha->eft) {
4651 memset(ha->eft, 0, EFT_SIZE);
e315cd28 4652 rval = qla2x00_enable_eft_trace(vha,
436a7b11
AV		 4653 ha->eft_dma, EFT_NUM_BUFFERS);
4654 if (rval) {
7c3df132 4655 ql_log(ql_log_warn, vha, 0x8034,
436a7b11
AV		 4656 "Unable to reinitialize EFT "
4657 "(%d).\n", rval);
4658 }
4659 }
1da177e4 4660 } else { /* failed the ISP abort */
e315cd28
AC		 4661 vha->flags.online = 1;
4662 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
1da177e4 4663 if (ha->isp_abort_cnt == 0) {
7c3df132
SK		 4664 ql_log(ql_log_fatal, vha, 0x8035,
4665 "ISP error recover failed - "
4666 "board disabled.\n");
fa2a1ce5 4667 /*
1da177e4
LT		 4668 * The next call disables the board
4669 * completely.
4670 */
e315cd28
AC		 4671 ha->isp_ops->reset_adapter(vha);
4672 vha->flags.online = 0;
1da177e4 4673 clear_bit(ISP_ABORT_RETRY,
e315cd28 4674 &vha->dpc_flags);
1da177e4
LT		 4675 status = 0;
4676 } else { /* schedule another ISP abort */
4677 ha->isp_abort_cnt--;
7c3df132
SK		 4678 ql_dbg(ql_dbg_taskm, vha, 0x8020,
4679 "ISP abort - retry remaining %d.\n",
4680 ha->isp_abort_cnt);
1da177e4
LT		 4681 status = 1;
4682 }
4683 } else {
4684 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
7c3df132
SK		 4685 ql_dbg(ql_dbg_taskm, vha, 0x8021,
4686 "ISP error recovery - retrying (%d) "
4687 "more times.\n", ha->isp_abort_cnt);
e315cd28 4688 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
1da177e4
LT		 4689 status = 1;
4690 }
4691 }
fa2a1ce5 4692
1da177e4
LT		 4693 }
4694
e315cd28 4695 if (!status) {
7c3df132 4696 ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__);
feafb7b1
AE		 4697
4698 spin_lock_irqsave(&ha->vport_slock, flags);
4699 list_for_each_entry(vp, &ha->vp_list, list) {
4700 if (vp->vp_idx) {
4701 atomic_inc(&vp->vref_count);
4702 spin_unlock_irqrestore(&ha->vport_slock, flags);
4703
e315cd28 4704 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 4705
4706 spin_lock_irqsave(&ha->vport_slock, flags);
4707 atomic_dec(&vp->vref_count);
4708 }
e315cd28 4709 }
feafb7b1
AE		 4710 spin_unlock_irqrestore(&ha->vport_slock, flags);
4711
7d613ac6
SV		 4712 if (IS_QLA8031(ha)) {
4713 ql_dbg(ql_dbg_p3p, vha, 0xb05d,
4714 "Setting back fcoe driver presence.\n");
4715 if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS)
4716 ql_dbg(ql_dbg_p3p, vha, 0xb074,
4717 "Error while setting DRV-Presence.\n");
4718 }
e315cd28 4719 } else {
d8424f68
JP		 4720 ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n",
4721 __func__);
1da177e4
LT		 4722 }
4723
4724 return(status);
4725}
4726
4727/*
4728* qla2x00_restart_isp
4729* restarts the ISP after a reset
4730*
4731* Input:
4732* ha = adapter block pointer.
4733*
4734* Returns:
4735* 0 = success
4736*/
4737static int
e315cd28 4738qla2x00_restart_isp(scsi_qla_host_t *vha)
1da177e4 4739{
c6b2fca8 4740 int status = 0;
e315cd28 4741 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 4742 struct req_que *req = ha->req_q_map[0];
4743 struct rsp_que *rsp = ha->rsp_q_map[0];
2d70c103 4744 unsigned long flags;
1da177e4
LT		 4745
4746 /* If firmware needs to be loaded */
e315cd28
AC		 4747 if (qla2x00_isp_firmware(vha)) {
4748 vha->flags.online = 0;
4749 status = ha->isp_ops->chip_diag(vha);
4750 if (!status)
4751 status = qla2x00_setup_chip(vha);
1da177e4
LT		 4752 }
4753
e315cd28
AC		 4754 if (!status && !(status = qla2x00_init_rings(vha))) {
4755 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
2533cf67 4756 ha->flags.chip_reset_done = 1;
7108b76e 4757
73208dfd
AC		 4758 /* Initialize the queues in use */
4759 qla25xx_init_queues(ha);
4760
e315cd28
AC		 4761 status = qla2x00_fw_ready(vha);
4762 if (!status) {
0107109e 4763 /* Issue a marker after FW becomes ready. */
73208dfd 4764 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
0107109e 4765
e315cd28 4766 vha->flags.online = 1;
2d70c103
NB		 4767
4768 /*
4769 * Process any ATIO queue entries that came in
4770 * while we weren't online.
4771 */
4772 spin_lock_irqsave(&ha->hardware_lock, flags);
4773 if (qla_tgt_mode_enabled(vha))
4774 qlt_24xx_process_atio_queue(vha);
4775 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4776
7108b76e 4777 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4
LT		 4778 }
4779
4780 /* if no cable then assume it's good */
e315cd28 4781 if ((vha->device_flags & DFLG_NO_CABLE))
1da177e4 4782 status = 0;
1da177e4
LT		 4783 }
4784 return (status);
4785}
4786
73208dfd
AC		 4787static int
4788qla25xx_init_queues(struct qla_hw_data *ha)
4789{
4790 struct rsp_que *rsp = NULL;
4791 struct req_que *req = NULL;
4792 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
4793 int ret = -1;
4794 int i;
4795
2afa19a9 4796 for (i = 1; i < ha->max_rsp_queues; i++) {
73208dfd
AC		 4797 rsp = ha->rsp_q_map[i];
4798 if (rsp) {
4799 rsp->options &= ~BIT_0;
618a7523 4800 ret = qla25xx_init_rsp_que(base_vha, rsp);
73208dfd 4801 if (ret != QLA_SUCCESS)
7c3df132
SK		 4802 ql_dbg(ql_dbg_init, base_vha, 0x00ff,
4803 "%s Rsp que: %d init failed.\n",
4804 __func__, rsp->id);
73208dfd 4805 else
7c3df132
SK		 4806 ql_dbg(ql_dbg_init, base_vha, 0x0100,
4807 "%s Rsp que: %d inited.\n",
4808 __func__, rsp->id);
73208dfd 4809 }
2afa19a9
AC		 4810 }
4811 for (i = 1; i < ha->max_req_queues; i++) {
73208dfd
AC		 4812 req = ha->req_q_map[i];
4813 if (req) {
29bdccbe 4814 /* Clear outstanding commands array. */
73208dfd 4815 req->options &= ~BIT_0;
618a7523 4816 ret = qla25xx_init_req_que(base_vha, req);
73208dfd 4817 if (ret != QLA_SUCCESS)
7c3df132
SK		 4818 ql_dbg(ql_dbg_init, base_vha, 0x0101,
4819 "%s Req que: %d init failed.\n",
4820 __func__, req->id);
73208dfd 4821 else
7c3df132
SK		 4822 ql_dbg(ql_dbg_init, base_vha, 0x0102,
4823 "%s Req que: %d inited.\n",
4824 __func__, req->id);
73208dfd
AC		 4825 }
4826 }
4827 return ret;
4828}
4829
1da177e4
LT		 4830/*
4831* qla2x00_reset_adapter
4832* Reset adapter.
4833*
4834* Input:
4835* ha = adapter block pointer.
4836*/
abbd8870 4837void
e315cd28 4838qla2x00_reset_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 4839{
4840 unsigned long flags = 0;
e315cd28 4841 struct qla_hw_data *ha = vha->hw;
3d71644c 4842 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 4843
e315cd28 4844 vha->flags.online = 0;
fd34f556 4845 ha->isp_ops->disable_intrs(ha);
1da177e4 4846
1da177e4
LT		 4847 spin_lock_irqsave(&ha->hardware_lock, flags);
4848 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
4849 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
4850 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
4851 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
4852 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4853}
0107109e
AV		 4854
4855void
e315cd28 4856qla24xx_reset_adapter(scsi_qla_host_t *vha)
0107109e
AV		 4857{
4858 unsigned long flags = 0;
e315cd28 4859 struct qla_hw_data *ha = vha->hw;
0107109e
AV		 4860 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
4861
7ec0effd 4862 if (IS_P3P_TYPE(ha))
a9083016
GM		 4863 return;
4864
e315cd28 4865 vha->flags.online = 0;
fd34f556 4866 ha->isp_ops->disable_intrs(ha);
0107109e
AV		 4867
4868 spin_lock_irqsave(&ha->hardware_lock, flags);
4869 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
4870 RD_REG_DWORD(&reg->hccr);
4871 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
4872 RD_REG_DWORD(&reg->hccr);
4873 spin_unlock_irqrestore(&ha->hardware_lock, flags);
09ff36d3
AV		 4874
4875 if (IS_NOPOLLING_TYPE(ha))
4876 ha->isp_ops->enable_intrs(ha);
0107109e
AV		 4877}
4878
4e08df3f
DM		 4879/* On sparc systems, obtain port and node WWN from firmware
4880 * properties.
4881 */
e315cd28
AC		 4882static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha,
4883 struct nvram_24xx *nv)
4e08df3f
DM		 4884{
4885#ifdef CONFIG_SPARC
e315cd28 4886 struct qla_hw_data *ha = vha->hw;
4e08df3f 4887 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 4888 struct device_node *dp = pci_device_to_OF_node(pdev);
4889 const u8 *val;
4e08df3f
DM		 4890 int len;
4891
4892 val = of_get_property(dp, "port-wwn", &len);
4893 if (val && len >= WWN_SIZE)
4894 memcpy(nv->port_name, val, WWN_SIZE);
4895
4896 val = of_get_property(dp, "node-wwn", &len);
4897 if (val && len >= WWN_SIZE)
4898 memcpy(nv->node_name, val, WWN_SIZE);
4899#endif
4900}
4901
0107109e 4902int
e315cd28 4903qla24xx_nvram_config(scsi_qla_host_t *vha)
0107109e 4904{
4e08df3f 4905 int rval;
0107109e
AV		 4906 struct init_cb_24xx *icb;
4907 struct nvram_24xx *nv;
4908 uint32_t *dptr;
4909 uint8_t *dptr1, *dptr2;
4910 uint32_t chksum;
4911 uint16_t cnt;
e315cd28 4912 struct qla_hw_data *ha = vha->hw;
0107109e 4913
4e08df3f 4914 rval = QLA_SUCCESS;
0107109e 4915 icb = (struct init_cb_24xx *)ha->init_cb;
281afe19 4916 nv = ha->nvram;
0107109e
AV		 4917
4918 /* Determine NVRAM starting address. */
f73cb695 4919 if (ha->port_no == 0) {
e5b68a61
AC		 4920 ha->nvram_base = FA_NVRAM_FUNC0_ADDR;
4921 ha->vpd_base = FA_NVRAM_VPD0_ADDR;
4922 } else {
0107109e 4923 ha->nvram_base = FA_NVRAM_FUNC1_ADDR;
6f641790
AV		 4924 ha->vpd_base = FA_NVRAM_VPD1_ADDR;
4925 }
f73cb695 4926
e5b68a61
AC		 4927 ha->nvram_size = sizeof(struct nvram_24xx);
4928 ha->vpd_size = FA_NVRAM_VPD_SIZE;
0107109e 4929
281afe19
SJ		 4930 /* Get VPD data into cache */
4931 ha->vpd = ha->nvram + VPD_OFFSET;
e315cd28 4932 ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd,
281afe19
SJ		 4933 ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
4934
4935 /* Get NVRAM data into cache and calculate checksum. */
0107109e 4936 dptr = (uint32_t *)nv;
e315cd28 4937 ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base,
0107109e
AV		 4938 ha->nvram_size);
4939 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
4940 chksum += le32_to_cpu(*dptr++);
4941
7c3df132
SK		 4942 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
4943 "Contents of NVRAM\n");
4944 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
4945 (uint8_t *)nv, ha->nvram_size);
0107109e
AV		 4946
4947 /* Bad NVRAM data, set defaults parameters. */
4948 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
4949 || nv->id[3] != ' ' ||
4950 nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
4951 /* Reset NVRAM data. */
7c3df132 4952 ql_log(ql_log_warn, vha, 0x006b,
9e336520 4953 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132
SK		 4954 "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version);
4955 ql_log(ql_log_warn, vha, 0x006c,
4956 "Falling back to functioning (yet invalid -- WWPN) "
4957 "defaults.\n");
4e08df3f
DM		 4958
4959 /*
4960 * Set default initialization control block.
4961 */
4962 memset(nv, 0, ha->nvram_size);
4963 nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
4964 nv->version = __constant_cpu_to_le16(ICB_VERSION);
98aee70d 4965 nv->frame_payload_size = 2048;
4e08df3f
DM		 4966 nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
4967 nv->exchange_count = __constant_cpu_to_le16(0);
4968 nv->hard_address = __constant_cpu_to_le16(124);
4969 nv->port_name[0] = 0x21;
f73cb695 4970 nv->port_name[1] = 0x00 + ha->port_no + 1;
4e08df3f
DM		 4971 nv->port_name[2] = 0x00;
4972 nv->port_name[3] = 0xe0;
4973 nv->port_name[4] = 0x8b;
4974 nv->port_name[5] = 0x1c;
4975 nv->port_name[6] = 0x55;
4976 nv->port_name[7] = 0x86;
4977 nv->node_name[0] = 0x20;
4978 nv->node_name[1] = 0x00;
4979 nv->node_name[2] = 0x00;
4980 nv->node_name[3] = 0xe0;
4981 nv->node_name[4] = 0x8b;
4982 nv->node_name[5] = 0x1c;
4983 nv->node_name[6] = 0x55;
4984 nv->node_name[7] = 0x86;
e315cd28 4985 qla24xx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 4986 nv->login_retry_count = __constant_cpu_to_le16(8);
4987 nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
4988 nv->login_timeout = __constant_cpu_to_le16(0);
4989 nv->firmware_options_1 =
4990 __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
4991 nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
4992 nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
4993 nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
4994 nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
4995 nv->efi_parameters = __constant_cpu_to_le32(0);
4996 nv->reset_delay = 5;
4997 nv->max_luns_per_target = __constant_cpu_to_le16(128);
4998 nv->port_down_retry_count = __constant_cpu_to_le16(30);
4999 nv->link_down_timeout = __constant_cpu_to_le16(30);
5000
5001 rval = 1;
0107109e
AV		 5002 }
5003
2d70c103
NB		 5004 if (!qla_ini_mode_enabled(vha)) {
5005 /* Don't enable full login after initial LIP */
5006 nv->firmware_options_1 &= __constant_cpu_to_le32(~BIT_13);
5007 /* Don't enable LIP full login for initiator */
5008 nv->host_p &= __constant_cpu_to_le32(~BIT_10);
5009 }
5010
5011 qlt_24xx_config_nvram_stage1(vha, nv);
5012
0107109e 5013 /* Reset Initialization control block */
e315cd28 5014 memset(icb, 0, ha->init_cb_size);
0107109e
AV		 5015
5016 /* Copy 1st segment. */
5017 dptr1 = (uint8_t *)icb;
5018 dptr2 = (uint8_t *)&nv->version;
5019 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
5020 while (cnt--)
5021 *dptr1++ = *dptr2++;
5022
5023 icb->login_retry_count = nv->login_retry_count;
3ea66e28 5024 icb->link_down_on_nos = nv->link_down_on_nos;
0107109e
AV		 5025
5026 /* Copy 2nd segment. */
5027 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
5028 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
5029 cnt = (uint8_t *)&icb->reserved_3 -
5030 (uint8_t *)&icb->interrupt_delay_timer;
5031 while (cnt--)
5032 *dptr1++ = *dptr2++;
5033
5034 /*
5035 * Setup driver NVRAM options.
5036 */
e315cd28 5037 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
9bb9fcf2 5038 "QLA2462");
0107109e 5039
2d70c103
NB		 5040 qlt_24xx_config_nvram_stage2(vha, icb);
5041
5341e868 5042 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
2d70c103 5043 /* Use alternate WWN? */
5341e868
AV		 5044 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
5045 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
5046 }
5047
0107109e 5048 /* Prepare nodename */
fd0e7e4d 5049 if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
0107109e
AV		 5050 /*
5051 * Firmware will apply the following mask if the nodename was
5052 * not provided.
5053 */
5054 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
5055 icb->node_name[0] &= 0xF0;
5056 }
5057
5058 /* Set host adapter parameters. */
5059 ha->flags.disable_risc_code_load = 0;
0c8c39af
AV		 5060 ha->flags.enable_lip_reset = 0;
5061 ha->flags.enable_lip_full_login =
5062 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
5063 ha->flags.enable_target_reset =
5064 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
0107109e 5065 ha->flags.enable_led_scheme = 0;
d4c760c2 5066 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
0107109e 5067
fd0e7e4d
AV		 5068 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
5069 (BIT_6 | BIT_5 | BIT_4)) >> 4;
0107109e
AV		 5070
5071 memcpy(ha->fw_seriallink_options24, nv->seriallink_options,
5072 sizeof(ha->fw_seriallink_options24));
5073
5074 /* save HBA serial number */
5075 ha->serial0 = icb->port_name[5];
5076 ha->serial1 = icb->port_name[6];
5077 ha->serial2 = icb->port_name[7];
e315cd28
AC		 5078 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
5079 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
0107109e 5080
bc8fb3cb
AV		 5081 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
5082
0107109e
AV		 5083 ha->retry_count = le16_to_cpu(nv->login_retry_count);
5084
5085 /* Set minimum login_timeout to 4 seconds. */
5086 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
5087 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
5088 if (le16_to_cpu(nv->login_timeout) < 4)
5089 nv->login_timeout = __constant_cpu_to_le16(4);
5090 ha->login_timeout = le16_to_cpu(nv->login_timeout);
c6852c4c 5091 icb->login_timeout = nv->login_timeout;
0107109e 5092
00a537b8
AV		 5093 /* Set minimum RATOV to 100 tenths of a second. */
5094 ha->r_a_tov = 100;
0107109e
AV		 5095
5096 ha->loop_reset_delay = nv->reset_delay;
5097
5098 /* Link Down Timeout = 0:
5099 *
5100 * When Port Down timer expires we will start returning
5101 * I/O's to OS with "DID_NO_CONNECT".
5102 *
5103 * Link Down Timeout != 0:
5104 *
5105 * The driver waits for the link to come up after link down
5106 * before returning I/Os to OS with "DID_NO_CONNECT".
5107 */
5108 if (le16_to_cpu(nv->link_down_timeout) == 0) {
5109 ha->loop_down_abort_time =
5110 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
5111 } else {
5112 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
5113 ha->loop_down_abort_time =
5114 (LOOP_DOWN_TIME - ha->link_down_timeout);
5115 }
5116
5117 /* Need enough time to try and get the port back. */
5118 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
5119 if (qlport_down_retry)
5120 ha->port_down_retry_count = qlport_down_retry;
5121
5122 /* Set login_retry_count */
5123 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
5124 if (ha->port_down_retry_count ==
5125 le16_to_cpu(nv->port_down_retry_count) &&
5126 ha->port_down_retry_count > 3)
5127 ha->login_retry_count = ha->port_down_retry_count;
5128 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
5129 ha->login_retry_count = ha->port_down_retry_count;
5130 if (ql2xloginretrycount)
5131 ha->login_retry_count = ql2xloginretrycount;
5132
4fdfefe5 5133 /* Enable ZIO. */
e315cd28 5134 if (!vha->flags.init_done) {
4fdfefe5
AV		 5135 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
5136 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
5137 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
5138 le16_to_cpu(icb->interrupt_delay_timer): 2;
5139 }
5140 icb->firmware_options_2 &= __constant_cpu_to_le32(
5141 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
e315cd28 5142 vha->flags.process_response_queue = 0;
4fdfefe5 5143 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d
AV		 5144 ha->zio_mode = QLA_ZIO_MODE_6;
5145
7c3df132 5146 ql_log(ql_log_info, vha, 0x006f,
4fdfefe5
AV		 5147 "ZIO mode %d enabled; timer delay (%d us).\n",
5148 ha->zio_mode, ha->zio_timer * 100);
5149
5150 icb->firmware_options_2 |= cpu_to_le32(
5151 (uint32_t)ha->zio_mode);
5152 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
e315cd28 5153 vha->flags.process_response_queue = 1;
4fdfefe5
AV		 5154 }
5155
4e08df3f 5156 if (rval) {
7c3df132
SK		 5157 ql_log(ql_log_warn, vha, 0x0070,
5158 "NVRAM configuration failed.\n");
4e08df3f
DM		 5159 }
5160 return (rval);
0107109e
AV		 5161}
5162
413975a0 5163static int
cbc8eb67
AV		 5164qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
5165 uint32_t faddr)
d1c61909 5166{
73208dfd 5167 int rval = QLA_SUCCESS;
d1c61909 5168 int segments, fragment;
d1c61909
AV		 5169 uint32_t *dcode, dlen;
5170 uint32_t risc_addr;
5171 uint32_t risc_size;
5172 uint32_t i;
e315cd28 5173 struct qla_hw_data *ha = vha->hw;
73208dfd 5174 struct req_que *req = ha->req_q_map[0];
eaac30be 5175
7c3df132 5176 ql_dbg(ql_dbg_init, vha, 0x008b,
cfb0919c 5177 "FW: Loading firmware from flash (%x).\n", faddr);
eaac30be 5178
d1c61909
AV		 5179 rval = QLA_SUCCESS;
5180
5181 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 5182 dcode = (uint32_t *)req->ring;
d1c61909
AV		 5183 *srisc_addr = 0;
5184
5185 /* Validate firmware image by checking version. */
e315cd28 5186 qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
d1c61909
AV		 5187 for (i = 0; i < 4; i++)
5188 dcode[i] = be32_to_cpu(dcode[i]);
5189 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
5190 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
5191 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
5192 dcode[3] == 0)) {
7c3df132
SK		 5193 ql_log(ql_log_fatal, vha, 0x008c,
5194 "Unable to verify the integrity of flash firmware "
5195 "image.\n");
5196 ql_log(ql_log_fatal, vha, 0x008d,
5197 "Firmware data: %08x %08x %08x %08x.\n",
5198 dcode[0], dcode[1], dcode[2], dcode[3]);
d1c61909
AV		 5199
5200 return QLA_FUNCTION_FAILED;
5201 }
5202
5203 while (segments && rval == QLA_SUCCESS) {
5204 /* Read segment's load information. */
e315cd28 5205 qla24xx_read_flash_data(vha, dcode, faddr, 4);
d1c61909
AV		 5206
5207 risc_addr = be32_to_cpu(dcode[2]);
5208 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
5209 risc_size = be32_to_cpu(dcode[3]);
5210
5211 fragment = 0;
5212 while (risc_size > 0 && rval == QLA_SUCCESS) {
5213 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
5214 if (dlen > risc_size)
5215 dlen = risc_size;
5216
7c3df132
SK		 5217 ql_dbg(ql_dbg_init, vha, 0x008e,
5218 "Loading risc segment@ risc addr %x "
5219 "number of dwords 0x%x offset 0x%x.\n",
5220 risc_addr, dlen, faddr);
d1c61909 5221
e315cd28 5222 qla24xx_read_flash_data(vha, dcode, faddr, dlen);
d1c61909
AV		 5223 for (i = 0; i < dlen; i++)
5224 dcode[i] = swab32(dcode[i]);
5225
73208dfd 5226 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
d1c61909
AV		 5227 dlen);
5228 if (rval) {
7c3df132
SK		 5229 ql_log(ql_log_fatal, vha, 0x008f,
5230 "Failed to load segment %d of firmware.\n",
5231 fragment);
d1c61909
AV		 5232 break;
5233 }
5234
5235 faddr += dlen;
5236 risc_addr += dlen;
5237 risc_size -= dlen;
5238 fragment++;
5239 }
5240
5241 /* Next segment. */
5242 segments--;
5243 }
5244
f73cb695
CD		 5245 if (!IS_QLA27XX(ha))
5246 return rval;
5247
5248 if (ha->fw_dump_template)
5249 vfree(ha->fw_dump_template);
5250 ha->fw_dump_template = NULL;
5251 ha->fw_dump_template_len = 0;
5252
5253 ql_dbg(ql_dbg_init, vha, 0x0161,
5254 "Loading fwdump template from %x\n", faddr);
5255 qla24xx_read_flash_data(vha, dcode, faddr, 7);
5256 risc_size = be32_to_cpu(dcode[2]);
5257 ql_dbg(ql_dbg_init, vha, 0x0162,
5258 "-> array size %x dwords\n", risc_size);
5259 if (risc_size == 0 || risc_size == ~0)
5260 goto default_template;
5261
5262 dlen = (risc_size - 8) * sizeof(*dcode);
5263 ql_dbg(ql_dbg_init, vha, 0x0163,
5264 "-> template allocating %x bytes...\n", dlen);
5265 ha->fw_dump_template = vmalloc(dlen);
5266 if (!ha->fw_dump_template) {
5267 ql_log(ql_log_warn, vha, 0x0164,
5268 "Failed fwdump template allocate %x bytes.\n", risc_size);
5269 goto default_template;
5270 }
5271
5272 faddr += 7;
5273 risc_size -= 8;
5274 dcode = ha->fw_dump_template;
5275 qla24xx_read_flash_data(vha, dcode, faddr, risc_size);
5276 for (i = 0; i < risc_size; i++)
5277 dcode[i] = le32_to_cpu(dcode[i]);
5278
5279 if (!qla27xx_fwdt_template_valid(dcode)) {
5280 ql_log(ql_log_warn, vha, 0x0165,
5281 "Failed fwdump template validate\n");
5282 goto default_template;
5283 }
5284
5285 dlen = qla27xx_fwdt_template_size(dcode);
5286 ql_dbg(ql_dbg_init, vha, 0x0166,
5287 "-> template size %x bytes\n", dlen);
5288 if (dlen > risc_size * sizeof(*dcode)) {
5289 ql_log(ql_log_warn, vha, 0x0167,
97ea702b
CD		 5290 "Failed fwdump template exceeds array by %x bytes\n",
5291 (uint32_t)(dlen - risc_size * sizeof(*dcode)));
f73cb695
CD		 5292 goto default_template;
5293 }
5294 ha->fw_dump_template_len = dlen;
5295 return rval;
5296
5297default_template:
5298 ql_log(ql_log_warn, vha, 0x0168, "Using default fwdump template\n");
5299 if (ha->fw_dump_template)
5300 vfree(ha->fw_dump_template);
5301 ha->fw_dump_template = NULL;
5302 ha->fw_dump_template_len = 0;
5303
5304 dlen = qla27xx_fwdt_template_default_size();
5305 ql_dbg(ql_dbg_init, vha, 0x0169,
5306 "-> template allocating %x bytes...\n", dlen);
5307 ha->fw_dump_template = vmalloc(dlen);
5308 if (!ha->fw_dump_template) {
5309 ql_log(ql_log_warn, vha, 0x016a,
5310 "Failed fwdump template allocate %x bytes.\n", risc_size);
5311 goto failed_template;
5312 }
5313
5314 dcode = ha->fw_dump_template;
5315 risc_size = dlen / sizeof(*dcode);
5316 memcpy(dcode, qla27xx_fwdt_template_default(), dlen);
5317 for (i = 0; i < risc_size; i++)
5318 dcode[i] = be32_to_cpu(dcode[i]);
5319
5320 if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) {
5321 ql_log(ql_log_warn, vha, 0x016b,
5322 "Failed fwdump template validate\n");
5323 goto failed_template;
5324 }
5325
5326 dlen = qla27xx_fwdt_template_size(ha->fw_dump_template);
5327 ql_dbg(ql_dbg_init, vha, 0x016c,
5328 "-> template size %x bytes\n", dlen);
5329 ha->fw_dump_template_len = dlen;
5330 return rval;
5331
5332failed_template:
5333 ql_log(ql_log_warn, vha, 0x016d, "Failed default fwdump template\n");
5334 if (ha->fw_dump_template)
5335 vfree(ha->fw_dump_template);
5336 ha->fw_dump_template = NULL;
5337 ha->fw_dump_template_len = 0;
d1c61909
AV		 5338 return rval;
5339}
5340
e9454a88 5341#define QLA_FW_URL "http://ldriver.qlogic.com/firmware/"
d1c61909 5342
0107109e 5343int
e315cd28 5344qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5433383e
AV		 5345{
5346 int rval;
5347 int i, fragment;
5348 uint16_t *wcode, *fwcode;
5349 uint32_t risc_addr, risc_size, fwclen, wlen, *seg;
5350 struct fw_blob *blob;
e315cd28 5351 struct qla_hw_data *ha = vha->hw;
73208dfd 5352 struct req_que *req = ha->req_q_map[0];
5433383e
AV		 5353
5354 /* Load firmware blob. */
e315cd28 5355 blob = qla2x00_request_firmware(vha);
5433383e 5356 if (!blob) {
7c3df132
SK		 5357 ql_log(ql_log_info, vha, 0x0083,
5358 "Fimware image unavailable.\n");
5359 ql_log(ql_log_info, vha, 0x0084,
5360 "Firmware images can be retrieved from: "QLA_FW_URL ".\n");
5433383e
AV		 5361 return QLA_FUNCTION_FAILED;
5362 }
5363
5364 rval = QLA_SUCCESS;
5365
73208dfd 5366 wcode = (uint16_t *)req->ring;
5433383e
AV		 5367 *srisc_addr = 0;
5368 fwcode = (uint16_t *)blob->fw->data;
5369 fwclen = 0;
5370
5371 /* Validate firmware image by checking version. */
5372 if (blob->fw->size < 8 * sizeof(uint16_t)) {
7c3df132
SK		 5373 ql_log(ql_log_fatal, vha, 0x0085,
5374 "Unable to verify integrity of firmware image (%Zd).\n",
5433383e
AV		 5375 blob->fw->size);
5376 goto fail_fw_integrity;
5377 }
5378 for (i = 0; i < 4; i++)
5379 wcode[i] = be16_to_cpu(fwcode[i + 4]);
5380 if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff &&
5381 wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 &&
5382 wcode[2] == 0 && wcode[3] == 0)) {
7c3df132
SK		 5383 ql_log(ql_log_fatal, vha, 0x0086,
5384 "Unable to verify integrity of firmware image.\n");
5385 ql_log(ql_log_fatal, vha, 0x0087,
5386 "Firmware data: %04x %04x %04x %04x.\n",
5387 wcode[0], wcode[1], wcode[2], wcode[3]);
5433383e
AV		 5388 goto fail_fw_integrity;
5389 }
5390
5391 seg = blob->segs;
5392 while (*seg && rval == QLA_SUCCESS) {
5393 risc_addr = *seg;
5394 *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr;
5395 risc_size = be16_to_cpu(fwcode[3]);
5396
5397 /* Validate firmware image size. */
5398 fwclen += risc_size * sizeof(uint16_t);
5399 if (blob->fw->size < fwclen) {
7c3df132 5400 ql_log(ql_log_fatal, vha, 0x0088,
5433383e 5401 "Unable to verify integrity of firmware image "
7c3df132 5402 "(%Zd).\n", blob->fw->size);
5433383e
AV		 5403 goto fail_fw_integrity;
5404 }
5405
5406 fragment = 0;
5407 while (risc_size > 0 && rval == QLA_SUCCESS) {
5408 wlen = (uint16_t)(ha->fw_transfer_size >> 1);
5409 if (wlen > risc_size)
5410 wlen = risc_size;
7c3df132
SK		 5411 ql_dbg(ql_dbg_init, vha, 0x0089,
5412 "Loading risc segment@ risc addr %x number of "
5413 "words 0x%x.\n", risc_addr, wlen);
5433383e
AV		 5414
5415 for (i = 0; i < wlen; i++)
5416 wcode[i] = swab16(fwcode[i]);
5417
73208dfd 5418 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
5433383e
AV		 5419 wlen);
5420 if (rval) {
7c3df132
SK		 5421 ql_log(ql_log_fatal, vha, 0x008a,
5422 "Failed to load segment %d of firmware.\n",
5423 fragment);
5433383e
AV		 5424 break;
5425 }
5426
5427 fwcode += wlen;
5428 risc_addr += wlen;
5429 risc_size -= wlen;
5430 fragment++;
5431 }
5432
5433 /* Next segment. */
5434 seg++;
5435 }
5436 return rval;
5437
5438fail_fw_integrity:
5439 return QLA_FUNCTION_FAILED;
5440}
5441
eaac30be
AV		 5442static int
5443qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
0107109e
AV		 5444{
5445 int rval;
5446 int segments, fragment;
5447 uint32_t *dcode, dlen;
5448 uint32_t risc_addr;
5449 uint32_t risc_size;
5450 uint32_t i;
5433383e 5451 struct fw_blob *blob;
f73cb695
CD		 5452 const uint32_t *fwcode;
5453 uint32_t fwclen;
e315cd28 5454 struct qla_hw_data *ha = vha->hw;
73208dfd 5455 struct req_que *req = ha->req_q_map[0];
0107109e 5456
5433383e 5457 /* Load firmware blob. */
e315cd28 5458 blob = qla2x00_request_firmware(vha);
5433383e 5459 if (!blob) {
7c3df132
SK		 5460 ql_log(ql_log_warn, vha, 0x0090,
5461 "Fimware image unavailable.\n");
5462 ql_log(ql_log_warn, vha, 0x0091,
5463 "Firmware images can be retrieved from: "
5464 QLA_FW_URL ".\n");
d1c61909 5465
eaac30be 5466 return QLA_FUNCTION_FAILED;
0107109e
AV		 5467 }
5468
cfb0919c
CD		 5469 ql_dbg(ql_dbg_init, vha, 0x0092,
5470 "FW: Loading via request-firmware.\n");
eaac30be 5471
0107109e
AV		 5472 rval = QLA_SUCCESS;
5473
5474 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 5475 dcode = (uint32_t *)req->ring;
0107109e 5476 *srisc_addr = 0;
5433383e 5477 fwcode = (uint32_t *)blob->fw->data;
0107109e
AV		 5478 fwclen = 0;
5479
5480 /* Validate firmware image by checking version. */
5433383e 5481 if (blob->fw->size < 8 * sizeof(uint32_t)) {
7c3df132
SK		 5482 ql_log(ql_log_fatal, vha, 0x0093,
5483 "Unable to verify integrity of firmware image (%Zd).\n",
5433383e 5484 blob->fw->size);
f73cb695 5485 return QLA_FUNCTION_FAILED;
0107109e
AV		 5486 }
5487 for (i = 0; i < 4; i++)
5488 dcode[i] = be32_to_cpu(fwcode[i + 4]);
5489 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
5490 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
5491 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
5492 dcode[3] == 0)) {
7c3df132
SK		 5493 ql_log(ql_log_fatal, vha, 0x0094,
5494 "Unable to verify integrity of firmware image (%Zd).\n",
5495 blob->fw->size);
5496 ql_log(ql_log_fatal, vha, 0x0095,
5497 "Firmware data: %08x %08x %08x %08x.\n",
5498 dcode[0], dcode[1], dcode[2], dcode[3]);
f73cb695 5499 return QLA_FUNCTION_FAILED;
0107109e
AV		 5500 }
5501
5502 while (segments && rval == QLA_SUCCESS) {
5503 risc_addr = be32_to_cpu(fwcode[2]);
5504 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
5505 risc_size = be32_to_cpu(fwcode[3]);
5506
5507 /* Validate firmware image size. */
5508 fwclen += risc_size * sizeof(uint32_t);
5433383e 5509 if (blob->fw->size < fwclen) {
7c3df132 5510 ql_log(ql_log_fatal, vha, 0x0096,
5433383e 5511 "Unable to verify integrity of firmware image "
7c3df132 5512 "(%Zd).\n", blob->fw->size);
f73cb695 5513 return QLA_FUNCTION_FAILED;
0107109e
AV		 5514 }
5515
5516 fragment = 0;
5517 while (risc_size > 0 && rval == QLA_SUCCESS) {
5518 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
5519 if (dlen > risc_size)
5520 dlen = risc_size;
5521
7c3df132
SK		 5522 ql_dbg(ql_dbg_init, vha, 0x0097,
5523 "Loading risc segment@ risc addr %x "
5524 "number of dwords 0x%x.\n", risc_addr, dlen);
0107109e
AV		 5525
5526 for (i = 0; i < dlen; i++)
5527 dcode[i] = swab32(fwcode[i]);
5528
73208dfd 5529 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
590f98e5 5530 dlen);
0107109e 5531 if (rval) {
7c3df132
SK		 5532 ql_log(ql_log_fatal, vha, 0x0098,
5533 "Failed to load segment %d of firmware.\n",
5534 fragment);
0107109e
AV		 5535 break;
5536 }
5537
5538 fwcode += dlen;
5539 risc_addr += dlen;
5540 risc_size -= dlen;
5541 fragment++;
5542 }
5543
5544 /* Next segment. */
5545 segments--;
5546 }
f73cb695
CD		 5547
5548 if (!IS_QLA27XX(ha))
5549 return rval;
5550
5551 if (ha->fw_dump_template)
5552 vfree(ha->fw_dump_template);
5553 ha->fw_dump_template = NULL;
5554 ha->fw_dump_template_len = 0;
5555
5556 ql_dbg(ql_dbg_init, vha, 0x171,
97ea702b
CD		 5557 "Loading fwdump template from %x\n",
5558 (uint32_t)((void *)fwcode - (void *)blob->fw->data));
f73cb695
CD		 5559 risc_size = be32_to_cpu(fwcode[2]);
5560 ql_dbg(ql_dbg_init, vha, 0x172,
5561 "-> array size %x dwords\n", risc_size);
5562 if (risc_size == 0 || risc_size == ~0)
5563 goto default_template;
5564
5565 dlen = (risc_size - 8) * sizeof(*fwcode);
5566 ql_dbg(ql_dbg_init, vha, 0x0173,
5567 "-> template allocating %x bytes...\n", dlen);
5568 ha->fw_dump_template = vmalloc(dlen);
5569 if (!ha->fw_dump_template) {
5570 ql_log(ql_log_warn, vha, 0x0174,
5571 "Failed fwdump template allocate %x bytes.\n", risc_size);
5572 goto default_template;
5573 }
5574
5575 fwcode += 7;
5576 risc_size -= 8;
5577 dcode = ha->fw_dump_template;
5578 for (i = 0; i < risc_size; i++)
5579 dcode[i] = le32_to_cpu(fwcode[i]);
5580
5581 if (!qla27xx_fwdt_template_valid(dcode)) {
5582 ql_log(ql_log_warn, vha, 0x0175,
5583 "Failed fwdump template validate\n");
5584 goto default_template;
5585 }
5586
5587 dlen = qla27xx_fwdt_template_size(dcode);
5588 ql_dbg(ql_dbg_init, vha, 0x0176,
5589 "-> template size %x bytes\n", dlen);
5590 if (dlen > risc_size * sizeof(*fwcode)) {
5591 ql_log(ql_log_warn, vha, 0x0177,
97ea702b
CD		 5592 "Failed fwdump template exceeds array by %x bytes\n",
5593 (uint32_t)(dlen - risc_size * sizeof(*fwcode)));
f73cb695
CD		 5594 goto default_template;
5595 }
5596 ha->fw_dump_template_len = dlen;
0107109e
AV		 5597 return rval;
5598
f73cb695
CD		 5599default_template:
5600 ql_log(ql_log_warn, vha, 0x0178, "Using default fwdump template\n");
5601 if (ha->fw_dump_template)
5602 vfree(ha->fw_dump_template);
5603 ha->fw_dump_template = NULL;
5604 ha->fw_dump_template_len = 0;
5605
5606 dlen = qla27xx_fwdt_template_default_size();
5607 ql_dbg(ql_dbg_init, vha, 0x0179,
5608 "-> template allocating %x bytes...\n", dlen);
5609 ha->fw_dump_template = vmalloc(dlen);
5610 if (!ha->fw_dump_template) {
5611 ql_log(ql_log_warn, vha, 0x017a,
5612 "Failed fwdump template allocate %x bytes.\n", risc_size);
5613 goto failed_template;
5614 }
5615
5616 dcode = ha->fw_dump_template;
5617 risc_size = dlen / sizeof(*fwcode);
5618 fwcode = qla27xx_fwdt_template_default();
5619 for (i = 0; i < risc_size; i++)
5620 dcode[i] = be32_to_cpu(fwcode[i]);
5621
5622 if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) {
5623 ql_log(ql_log_warn, vha, 0x017b,
5624 "Failed fwdump template validate\n");
5625 goto failed_template;
5626 }
5627
5628 dlen = qla27xx_fwdt_template_size(ha->fw_dump_template);
5629 ql_dbg(ql_dbg_init, vha, 0x017c,
5630 "-> template size %x bytes\n", dlen);
5631 ha->fw_dump_template_len = dlen;
5632 return rval;
5633
5634failed_template:
5635 ql_log(ql_log_warn, vha, 0x017d, "Failed default fwdump template\n");
5636 if (ha->fw_dump_template)
5637 vfree(ha->fw_dump_template);
5638 ha->fw_dump_template = NULL;
5639 ha->fw_dump_template_len = 0;
5640 return rval;
0107109e 5641}
18c6c127 5642
eaac30be
AV		 5643int
5644qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5645{
5646 int rval;
5647
e337d907
AV		 5648 if (ql2xfwloadbin == 1)
5649 return qla81xx_load_risc(vha, srisc_addr);
5650
eaac30be
AV		 5651 /*
5652 * FW Load priority:
5653 * 1) Firmware via request-firmware interface (.bin file).
5654 * 2) Firmware residing in flash.
5655 */
5656 rval = qla24xx_load_risc_blob(vha, srisc_addr);
5657 if (rval == QLA_SUCCESS)
5658 return rval;
5659
cbc8eb67
AV		 5660 return qla24xx_load_risc_flash(vha, srisc_addr,
5661 vha->hw->flt_region_fw);
eaac30be
AV		 5662}
5663
5664int
5665qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5666{
5667 int rval;
cbc8eb67 5668 struct qla_hw_data *ha = vha->hw;
eaac30be 5669
e337d907 5670 if (ql2xfwloadbin == 2)
cbc8eb67 5671 goto try_blob_fw;
e337d907 5672
eaac30be
AV		 5673 /*
5674 * FW Load priority:
5675 * 1) Firmware residing in flash.
5676 * 2) Firmware via request-firmware interface (.bin file).
cbc8eb67 5677 * 3) Golden-Firmware residing in flash -- limited operation.
eaac30be 5678 */
cbc8eb67 5679 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
eaac30be
AV		 5680 if (rval == QLA_SUCCESS)
5681 return rval;
5682
cbc8eb67
AV		 5683try_blob_fw:
5684 rval = qla24xx_load_risc_blob(vha, srisc_addr);
5685 if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw)
5686 return rval;
5687
7c3df132
SK		 5688 ql_log(ql_log_info, vha, 0x0099,
5689 "Attempting to fallback to golden firmware.\n");
cbc8eb67
AV		 5690 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
5691 if (rval != QLA_SUCCESS)
5692 return rval;
5693
7c3df132 5694 ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n");
cbc8eb67 5695 ha->flags.running_gold_fw = 1;
cbc8eb67 5696 return rval;
eaac30be
AV		 5697}
5698
18c6c127 5699void
e315cd28 5700qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha)
18c6c127
AV		 5701{
5702 int ret, retries;
e315cd28 5703 struct qla_hw_data *ha = vha->hw;
18c6c127 5704
85880801
AV		 5705 if (ha->flags.pci_channel_io_perm_failure)
5706 return;
e428924c 5707 if (!IS_FWI2_CAPABLE(ha))
18c6c127 5708 return;
75edf81d
AV		 5709 if (!ha->fw_major_version)
5710 return;
18c6c127 5711
e315cd28 5712 ret = qla2x00_stop_firmware(vha);
7c7f1f29 5713 for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&
b469a7cb 5714 ret != QLA_INVALID_COMMAND && retries ; retries--) {
e315cd28
AC		 5715 ha->isp_ops->reset_chip(vha);
5716 if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS)
18c6c127 5717 continue;
e315cd28 5718 if (qla2x00_setup_chip(vha) != QLA_SUCCESS)
18c6c127 5719 continue;
7c3df132
SK		 5720 ql_log(ql_log_info, vha, 0x8015,
5721 "Attempting retry of stop-firmware command.\n");
e315cd28 5722 ret = qla2x00_stop_firmware(vha);
18c6c127
AV		 5723 }
5724}
2c3dfe3f
SJ		 5725
5726int
e315cd28 5727qla24xx_configure_vhba(scsi_qla_host_t *vha)
2c3dfe3f
SJ		 5728{
5729 int rval = QLA_SUCCESS;
0b91d116 5730 int rval2;
2c3dfe3f 5731 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28
AC		 5732 struct qla_hw_data *ha = vha->hw;
5733 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
67c2e93a
AC		 5734 struct req_que *req;
5735 struct rsp_que *rsp;
2c3dfe3f 5736
e315cd28 5737 if (!vha->vp_idx)
2c3dfe3f
SJ		 5738 return -EINVAL;
5739
e315cd28 5740 rval = qla2x00_fw_ready(base_vha);
7163ea81 5741 if (ha->flags.cpu_affinity_enabled)
67c2e93a
AC		 5742 req = ha->req_q_map[0];
5743 else
5744 req = vha->req;
5745 rsp = req->rsp;
5746
2c3dfe3f 5747 if (rval == QLA_SUCCESS) {
e315cd28 5748 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
73208dfd 5749 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
2c3dfe3f
SJ		 5750 }
5751
e315cd28 5752 vha->flags.management_server_logged_in = 0;
2c3dfe3f
SJ		 5753
5754 /* Login to SNS first */
0b91d116
CD		 5755 rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb,
5756 BIT_1);
5757 if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
5758 if (rval2 == QLA_MEMORY_ALLOC_FAILED)
5759 ql_dbg(ql_dbg_init, vha, 0x0120,
5760 "Failed SNS login: loop_id=%x, rval2=%d\n",
5761 NPH_SNS, rval2);
5762 else
5763 ql_dbg(ql_dbg_init, vha, 0x0103,
5764 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x "
5765 "mb[2]=%x mb[6]=%x mb[7]=%x.\n",
5766 NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]);
2c3dfe3f
SJ		 5767 return (QLA_FUNCTION_FAILED);
5768 }
5769
e315cd28
AC		 5770 atomic_set(&vha->loop_down_timer, 0);
5771 atomic_set(&vha->loop_state, LOOP_UP);
5772 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5773 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
5774 rval = qla2x00_loop_resync(base_vha);
2c3dfe3f
SJ		 5775
5776 return rval;
5777}
4d4df193
HK		 5778
5779/* 84XX Support **************************************************************/
5780
5781static LIST_HEAD(qla_cs84xx_list);
5782static DEFINE_MUTEX(qla_cs84xx_mutex);
5783
5784static struct qla_chip_state_84xx *
e315cd28 5785qla84xx_get_chip(struct scsi_qla_host *vha)
4d4df193
HK		 5786{
5787 struct qla_chip_state_84xx *cs84xx;
e315cd28 5788 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5789
5790 mutex_lock(&qla_cs84xx_mutex);
5791
5792 /* Find any shared 84xx chip. */
5793 list_for_each_entry(cs84xx, &qla_cs84xx_list, list) {
5794 if (cs84xx->bus == ha->pdev->bus) {
5795 kref_get(&cs84xx->kref);
5796 goto done;
5797 }
5798 }
5799
5800 cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL);
5801 if (!cs84xx)
5802 goto done;
5803
5804 kref_init(&cs84xx->kref);
5805 spin_lock_init(&cs84xx->access_lock);
5806 mutex_init(&cs84xx->fw_update_mutex);
5807 cs84xx->bus = ha->pdev->bus;
5808
5809 list_add_tail(&cs84xx->list, &qla_cs84xx_list);
5810done:
5811 mutex_unlock(&qla_cs84xx_mutex);
5812 return cs84xx;
5813}
5814
5815static void
5816__qla84xx_chip_release(struct kref *kref)
5817{
5818 struct qla_chip_state_84xx *cs84xx =
5819 container_of(kref, struct qla_chip_state_84xx, kref);
5820
5821 mutex_lock(&qla_cs84xx_mutex);
5822 list_del(&cs84xx->list);
5823 mutex_unlock(&qla_cs84xx_mutex);
5824 kfree(cs84xx);
5825}
5826
5827void
e315cd28 5828qla84xx_put_chip(struct scsi_qla_host *vha)
4d4df193 5829{
e315cd28 5830 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5831 if (ha->cs84xx)
5832 kref_put(&ha->cs84xx->kref, __qla84xx_chip_release);
5833}
5834
5835static int
e315cd28 5836qla84xx_init_chip(scsi_qla_host_t *vha)
4d4df193
HK		 5837{
5838 int rval;
5839 uint16_t status[2];
e315cd28 5840 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5841
5842 mutex_lock(&ha->cs84xx->fw_update_mutex);
5843
e315cd28 5844 rval = qla84xx_verify_chip(vha, status);
4d4df193
HK		 5845
5846 mutex_unlock(&ha->cs84xx->fw_update_mutex);
5847
5848 return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED:
5849 QLA_SUCCESS;
5850}
3a03eb79
AV		 5851
5852/* 81XX Support **************************************************************/
5853
5854int
5855qla81xx_nvram_config(scsi_qla_host_t *vha)
5856{
5857 int rval;
5858 struct init_cb_81xx *icb;
5859 struct nvram_81xx *nv;
5860 uint32_t *dptr;
5861 uint8_t *dptr1, *dptr2;
5862 uint32_t chksum;
5863 uint16_t cnt;
5864 struct qla_hw_data *ha = vha->hw;
5865
5866 rval = QLA_SUCCESS;
5867 icb = (struct init_cb_81xx *)ha->init_cb;
5868 nv = ha->nvram;
5869
5870 /* Determine NVRAM starting address. */
5871 ha->nvram_size = sizeof(struct nvram_81xx);
3a03eb79 5872 ha->vpd_size = FA_NVRAM_VPD_SIZE;
7ec0effd
AD		 5873 if (IS_P3P_TYPE(ha) || IS_QLA8031(ha))
5874 ha->vpd_size = FA_VPD_SIZE_82XX;
3a03eb79
AV		 5875
5876 /* Get VPD data into cache */
5877 ha->vpd = ha->nvram + VPD_OFFSET;
3d79038f
AV		 5878 ha->isp_ops->read_optrom(vha, ha->vpd, ha->flt_region_vpd << 2,
5879 ha->vpd_size);
3a03eb79
AV		 5880
5881 /* Get NVRAM data into cache and calculate checksum. */
3d79038f 5882 ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2,
3a03eb79 5883 ha->nvram_size);
3d79038f 5884 dptr = (uint32_t *)nv;
3a03eb79
AV		 5885 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
5886 chksum += le32_to_cpu(*dptr++);
5887
7c3df132
SK		 5888 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
5889 "Contents of NVRAM:\n");
5890 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
5891 (uint8_t *)nv, ha->nvram_size);
3a03eb79
AV		 5892
5893 /* Bad NVRAM data, set defaults parameters. */
5894 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
5895 || nv->id[3] != ' ' ||
5896 nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
5897 /* Reset NVRAM data. */
7c3df132 5898 ql_log(ql_log_info, vha, 0x0073,
9e336520 5899 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132 5900 "version=0x%x.\n", chksum, nv->id[0],
3a03eb79 5901 le16_to_cpu(nv->nvram_version));
7c3df132
SK		 5902 ql_log(ql_log_info, vha, 0x0074,
5903 "Falling back to functioning (yet invalid -- WWPN) "
5904 "defaults.\n");
3a03eb79
AV		 5905
5906 /*
5907 * Set default initialization control block.
5908 */
5909 memset(nv, 0, ha->nvram_size);
5910 nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
5911 nv->version = __constant_cpu_to_le16(ICB_VERSION);
98aee70d 5912 nv->frame_payload_size = 2048;
3a03eb79
AV		 5913 nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
5914 nv->exchange_count = __constant_cpu_to_le16(0);
5915 nv->port_name[0] = 0x21;
f73cb695 5916 nv->port_name[1] = 0x00 + ha->port_no + 1;
3a03eb79
AV		 5917 nv->port_name[2] = 0x00;
5918 nv->port_name[3] = 0xe0;
5919 nv->port_name[4] = 0x8b;
5920 nv->port_name[5] = 0x1c;
5921 nv->port_name[6] = 0x55;
5922 nv->port_name[7] = 0x86;
5923 nv->node_name[0] = 0x20;
5924 nv->node_name[1] = 0x00;
5925 nv->node_name[2] = 0x00;
5926 nv->node_name[3] = 0xe0;
5927 nv->node_name[4] = 0x8b;
5928 nv->node_name[5] = 0x1c;
5929 nv->node_name[6] = 0x55;
5930 nv->node_name[7] = 0x86;
5931 nv->login_retry_count = __constant_cpu_to_le16(8);
5932 nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
5933 nv->login_timeout = __constant_cpu_to_le16(0);
5934 nv->firmware_options_1 =
5935 __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
5936 nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
5937 nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
5938 nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
5939 nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
5940 nv->efi_parameters = __constant_cpu_to_le32(0);
5941 nv->reset_delay = 5;
5942 nv->max_luns_per_target = __constant_cpu_to_le16(128);
5943 nv->port_down_retry_count = __constant_cpu_to_le16(30);
6246b8a1 5944 nv->link_down_timeout = __constant_cpu_to_le16(180);
eeebcc92 5945 nv->enode_mac[0] = 0x00;
6246b8a1
GM		 5946 nv->enode_mac[1] = 0xC0;
5947 nv->enode_mac[2] = 0xDD;
3a03eb79
AV		 5948 nv->enode_mac[3] = 0x04;
5949 nv->enode_mac[4] = 0x05;
f73cb695 5950 nv->enode_mac[5] = 0x06 + ha->port_no + 1;
3a03eb79
AV		 5951
5952 rval = 1;
5953 }
5954
9e522cd8
AE		 5955 if (IS_T10_PI_CAPABLE(ha))
5956 nv->frame_payload_size &= ~7;
5957
aa230bc5
AE		 5958 qlt_81xx_config_nvram_stage1(vha, nv);
5959
3a03eb79 5960 /* Reset Initialization control block */
773120e4 5961 memset(icb, 0, ha->init_cb_size);
3a03eb79
AV		 5962
5963 /* Copy 1st segment. */
5964 dptr1 = (uint8_t *)icb;
5965 dptr2 = (uint8_t *)&nv->version;
5966 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
5967 while (cnt--)
5968 *dptr1++ = *dptr2++;
5969
5970 icb->login_retry_count = nv->login_retry_count;
5971
5972 /* Copy 2nd segment. */
5973 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
5974 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
5975 cnt = (uint8_t *)&icb->reserved_5 -
5976 (uint8_t *)&icb->interrupt_delay_timer;
5977 while (cnt--)
5978 *dptr1++ = *dptr2++;
5979
5980 memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac));
5981 /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */
5982 if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) {
69e5f1ea
AV		 5983 icb->enode_mac[0] = 0x00;
5984 icb->enode_mac[1] = 0xC0;
5985 icb->enode_mac[2] = 0xDD;
3a03eb79
AV		 5986 icb->enode_mac[3] = 0x04;
5987 icb->enode_mac[4] = 0x05;
f73cb695 5988 icb->enode_mac[5] = 0x06 + ha->port_no + 1;
3a03eb79
AV		 5989 }
5990
b64b0e8f
AV		 5991 /* Use extended-initialization control block. */
5992 memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb));
5993
3a03eb79
AV		 5994 /*
5995 * Setup driver NVRAM options.
5996 */
5997 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
a9083016 5998 "QLE8XXX");
3a03eb79 5999
aa230bc5
AE		 6000 qlt_81xx_config_nvram_stage2(vha, icb);
6001
3a03eb79
AV		 6002 /* Use alternate WWN? */
6003 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
6004 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
6005 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
6006 }
6007
6008 /* Prepare nodename */
6009 if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
6010 /*
6011 * Firmware will apply the following mask if the nodename was
6012 * not provided.
6013 */
6014 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
6015 icb->node_name[0] &= 0xF0;
6016 }
6017
6018 /* Set host adapter parameters. */
6019 ha->flags.disable_risc_code_load = 0;
6020 ha->flags.enable_lip_reset = 0;
6021 ha->flags.enable_lip_full_login =
6022 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
6023 ha->flags.enable_target_reset =
6024 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
6025 ha->flags.enable_led_scheme = 0;
6026 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
6027
6028 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
6029 (BIT_6 | BIT_5 | BIT_4)) >> 4;
6030
6031 /* save HBA serial number */
6032 ha->serial0 = icb->port_name[5];
6033 ha->serial1 = icb->port_name[6];
6034 ha->serial2 = icb->port_name[7];
6035 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
6036 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
6037
6038 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
6039
6040 ha->retry_count = le16_to_cpu(nv->login_retry_count);
6041
6042 /* Set minimum login_timeout to 4 seconds. */
6043 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
6044 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
6045 if (le16_to_cpu(nv->login_timeout) < 4)
6046 nv->login_timeout = __constant_cpu_to_le16(4);
6047 ha->login_timeout = le16_to_cpu(nv->login_timeout);
6048 icb->login_timeout = nv->login_timeout;
6049
6050 /* Set minimum RATOV to 100 tenths of a second. */
6051 ha->r_a_tov = 100;
6052
6053 ha->loop_reset_delay = nv->reset_delay;
6054
6055 /* Link Down Timeout = 0:
6056 *
7ec0effd 6057 * When Port Down timer expires we will start returning
3a03eb79
AV		 6058 * I/O's to OS with "DID_NO_CONNECT".
6059 *
6060 * Link Down Timeout != 0:
6061 *
6062 * The driver waits for the link to come up after link down
6063 * before returning I/Os to OS with "DID_NO_CONNECT".
6064 */
6065 if (le16_to_cpu(nv->link_down_timeout) == 0) {
6066 ha->loop_down_abort_time =
6067 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
6068 } else {
6069 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
6070 ha->loop_down_abort_time =
6071 (LOOP_DOWN_TIME - ha->link_down_timeout);
6072 }
6073
6074 /* Need enough time to try and get the port back. */
6075 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
6076 if (qlport_down_retry)
6077 ha->port_down_retry_count = qlport_down_retry;
6078
6079 /* Set login_retry_count */
6080 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
6081 if (ha->port_down_retry_count ==
6082 le16_to_cpu(nv->port_down_retry_count) &&
6083 ha->port_down_retry_count > 3)
6084 ha->login_retry_count = ha->port_down_retry_count;
6085 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
6086 ha->login_retry_count = ha->port_down_retry_count;
6087 if (ql2xloginretrycount)
6088 ha->login_retry_count = ql2xloginretrycount;
6089
6246b8a1 6090 /* if not running MSI-X we need handshaking on interrupts */
f73cb695 6091 if (!vha->hw->flags.msix_enabled && (IS_QLA83XX(ha) || IS_QLA27XX(ha)))
6246b8a1
GM		 6092 icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_22);
6093
3a03eb79
AV		 6094 /* Enable ZIO. */
6095 if (!vha->flags.init_done) {
6096 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
6097 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
6098 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
6099 le16_to_cpu(icb->interrupt_delay_timer): 2;
6100 }
6101 icb->firmware_options_2 &= __constant_cpu_to_le32(
6102 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
6103 vha->flags.process_response_queue = 0;
6104 if (ha->zio_mode != QLA_ZIO_DISABLED) {
6105 ha->zio_mode = QLA_ZIO_MODE_6;
6106
7c3df132 6107 ql_log(ql_log_info, vha, 0x0075,
3a03eb79 6108 "ZIO mode %d enabled; timer delay (%d us).\n",
7c3df132
SK		 6109 ha->zio_mode,
6110 ha->zio_timer * 100);
3a03eb79
AV		 6111
6112 icb->firmware_options_2 |= cpu_to_le32(
6113 (uint32_t)ha->zio_mode);
6114 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
6115 vha->flags.process_response_queue = 1;
6116 }
6117
6118 if (rval) {
7c3df132
SK		 6119 ql_log(ql_log_warn, vha, 0x0076,
6120 "NVRAM configuration failed.\n");
3a03eb79
AV		 6121 }
6122 return (rval);
6123}
6124
a9083016
GM		 6125int
6126qla82xx_restart_isp(scsi_qla_host_t *vha)
6127{
6128 int status, rval;
a9083016
GM		 6129 struct qla_hw_data *ha = vha->hw;
6130 struct req_que *req = ha->req_q_map[0];
6131 struct rsp_que *rsp = ha->rsp_q_map[0];
6132 struct scsi_qla_host *vp;
feafb7b1 6133 unsigned long flags;
a9083016
GM		 6134
6135 status = qla2x00_init_rings(vha);
6136 if (!status) {
6137 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
6138 ha->flags.chip_reset_done = 1;
6139
6140 status = qla2x00_fw_ready(vha);
6141 if (!status) {
a9083016
GM		 6142 /* Issue a marker after FW becomes ready. */
6143 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
a9083016 6144 vha->flags.online = 1;
7108b76e 6145 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
a9083016
GM		 6146 }
6147
6148 /* if no cable then assume it's good */
6149 if ((vha->device_flags & DFLG_NO_CABLE))
6150 status = 0;
a9083016
GM		 6151 }
6152
6153 if (!status) {
6154 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
6155
6156 if (!atomic_read(&vha->loop_down_timer)) {
6157 /*
6158 * Issue marker command only when we are going
6159 * to start the I/O .
6160 */
6161 vha->marker_needed = 1;
6162 }
6163
a9083016
GM		 6164 ha->isp_ops->enable_intrs(ha);
6165
6166 ha->isp_abort_cnt = 0;
6167 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
6168
53296788 6169 /* Update the firmware version */
3173167f 6170 status = qla82xx_check_md_needed(vha);
53296788 6171
a9083016
GM		 6172 if (ha->fce) {
6173 ha->flags.fce_enabled = 1;
6174 memset(ha->fce, 0,
6175 fce_calc_size(ha->fce_bufs));
6176 rval = qla2x00_enable_fce_trace(vha,
6177 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
6178 &ha->fce_bufs);
6179 if (rval) {
cfb0919c 6180 ql_log(ql_log_warn, vha, 0x8001,
7c3df132
SK		 6181 "Unable to reinitialize FCE (%d).\n",
6182 rval);
a9083016
GM		 6183 ha->flags.fce_enabled = 0;
6184 }
6185 }
6186
6187 if (ha->eft) {
6188 memset(ha->eft, 0, EFT_SIZE);
6189 rval = qla2x00_enable_eft_trace(vha,
6190 ha->eft_dma, EFT_NUM_BUFFERS);
6191 if (rval) {
cfb0919c 6192 ql_log(ql_log_warn, vha, 0x8010,
7c3df132
SK		 6193 "Unable to reinitialize EFT (%d).\n",
6194 rval);
a9083016
GM		 6195 }
6196 }
a9083016
GM		 6197 }
6198
6199 if (!status) {
cfb0919c 6200 ql_dbg(ql_dbg_taskm, vha, 0x8011,
7c3df132 6201 "qla82xx_restart_isp succeeded.\n");
feafb7b1
AE		 6202
6203 spin_lock_irqsave(&ha->vport_slock, flags);
6204 list_for_each_entry(vp, &ha->vp_list, list) {
6205 if (vp->vp_idx) {
6206 atomic_inc(&vp->vref_count);
6207 spin_unlock_irqrestore(&ha->vport_slock, flags);
6208
a9083016 6209 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 6210
6211 spin_lock_irqsave(&ha->vport_slock, flags);
6212 atomic_dec(&vp->vref_count);
6213 }
a9083016 6214 }
feafb7b1
AE		 6215 spin_unlock_irqrestore(&ha->vport_slock, flags);
6216
a9083016 6217 } else {
cfb0919c 6218 ql_log(ql_log_warn, vha, 0x8016,
7c3df132 6219 "qla82xx_restart_isp **** FAILED ****.\n");
a9083016
GM		 6220 }
6221
6222 return status;
6223}
6224
3a03eb79 6225void
ae97c91e 6226qla81xx_update_fw_options(scsi_qla_host_t *vha)
3a03eb79 6227{
ae97c91e
AV		 6228 struct qla_hw_data *ha = vha->hw;
6229
6230 if (!ql2xetsenable)
6231 return;
6232
6233 /* Enable ETS Burst. */
6234 memset(ha->fw_options, 0, sizeof(ha->fw_options));
6235 ha->fw_options[2] |= BIT_9;
6236 qla2x00_set_fw_options(vha, ha->fw_options);
3a03eb79 6237}
09ff701a
SR		 6238
6239/*
6240 * qla24xx_get_fcp_prio
6241 * Gets the fcp cmd priority value for the logged in port.
6242 * Looks for a match of the port descriptors within
6243 * each of the fcp prio config entries. If a match is found,
6244 * the tag (priority) value is returned.
6245 *
6246 * Input:
21090cbe 6247 * vha = scsi host structure pointer.
09ff701a
SR		 6248 * fcport = port structure pointer.
6249 *
6250 * Return:
6c452a45 6251 * non-zero (if found)
f28a0a96 6252 * -1 (if not found)
09ff701a
SR		 6253 *
6254 * Context:
6255 * Kernel context
6256 */
f28a0a96 6257static int
09ff701a
SR		 6258qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
6259{
6260 int i, entries;
6261 uint8_t pid_match, wwn_match;
f28a0a96 6262 int priority;
09ff701a
SR		 6263 uint32_t pid1, pid2;
6264 uint64_t wwn1, wwn2;
6265 struct qla_fcp_prio_entry *pri_entry;
6266 struct qla_hw_data *ha = vha->hw;
6267
6268 if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled)
f28a0a96 6269 return -1;
09ff701a 6270
f28a0a96 6271 priority = -1;
09ff701a
SR		 6272 entries = ha->fcp_prio_cfg->num_entries;
6273 pri_entry = &ha->fcp_prio_cfg->entry[0];
6274
6275 for (i = 0; i < entries; i++) {
6276 pid_match = wwn_match = 0;
6277
6278 if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) {
6279 pri_entry++;
6280 continue;
6281 }
6282
6283 /* check source pid for a match */
6284 if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) {
6285 pid1 = pri_entry->src_pid & INVALID_PORT_ID;
6286 pid2 = vha->d_id.b24 & INVALID_PORT_ID;
6287 if (pid1 == INVALID_PORT_ID)
6288 pid_match++;
6289 else if (pid1 == pid2)
6290 pid_match++;
6291 }
6292
6293 /* check destination pid for a match */
6294 if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) {
6295 pid1 = pri_entry->dst_pid & INVALID_PORT_ID;
6296 pid2 = fcport->d_id.b24 & INVALID_PORT_ID;
6297 if (pid1 == INVALID_PORT_ID)
6298 pid_match++;
6299 else if (pid1 == pid2)
6300 pid_match++;
6301 }
6302
6303 /* check source WWN for a match */
6304 if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) {
6305 wwn1 = wwn_to_u64(vha->port_name);
6306 wwn2 = wwn_to_u64(pri_entry->src_wwpn);
6307 if (wwn2 == (uint64_t)-1)
6308 wwn_match++;
6309 else if (wwn1 == wwn2)
6310 wwn_match++;
6311 }
6312
6313 /* check destination WWN for a match */
6314 if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) {
6315 wwn1 = wwn_to_u64(fcport->port_name);
6316 wwn2 = wwn_to_u64(pri_entry->dst_wwpn);
6317 if (wwn2 == (uint64_t)-1)
6318 wwn_match++;
6319 else if (wwn1 == wwn2)
6320 wwn_match++;
6321 }
6322
6323 if (pid_match == 2 || wwn_match == 2) {
6324 /* Found a matching entry */
6325 if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID)
6326 priority = pri_entry->tag;
6327 break;
6328 }
6329
6330 pri_entry++;
6331 }
6332
6333 return priority;
6334}
6335
6336/*
6337 * qla24xx_update_fcport_fcp_prio
6338 * Activates fcp priority for the logged in fc port
6339 *
6340 * Input:
21090cbe 6341 * vha = scsi host structure pointer.
09ff701a
SR		 6342 * fcp = port structure pointer.
6343 *
6344 * Return:
6345 * QLA_SUCCESS or QLA_FUNCTION_FAILED
6346 *
6347 * Context:
6348 * Kernel context.
6349 */
6350int
21090cbe 6351qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
09ff701a
SR		 6352{
6353 int ret;
f28a0a96 6354 int priority;
09ff701a
SR		 6355 uint16_t mb[5];
6356
21090cbe
MI		 6357 if (fcport->port_type != FCT_TARGET ||
6358 fcport->loop_id == FC_NO_LOOP_ID)
09ff701a
SR		 6359 return QLA_FUNCTION_FAILED;
6360
21090cbe 6361 priority = qla24xx_get_fcp_prio(vha, fcport);
f28a0a96
AV		 6362 if (priority < 0)
6363 return QLA_FUNCTION_FAILED;
6364
7ec0effd 6365 if (IS_P3P_TYPE(vha->hw)) {
a00f6296
SK		 6366 fcport->fcp_prio = priority & 0xf;
6367 return QLA_SUCCESS;
6368 }
6369
21090cbe 6370 ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb);
cfb0919c
CD		 6371 if (ret == QLA_SUCCESS) {
6372 if (fcport->fcp_prio != priority)
6373 ql_dbg(ql_dbg_user, vha, 0x709e,
6374 "Updated FCP_CMND priority - value=%d loop_id=%d "
6375 "port_id=%02x%02x%02x.\n", priority,
6376 fcport->loop_id, fcport->d_id.b.domain,
6377 fcport->d_id.b.area, fcport->d_id.b.al_pa);
a00f6296 6378 fcport->fcp_prio = priority & 0xf;
cfb0919c 6379 } else
7c3df132 6380 ql_dbg(ql_dbg_user, vha, 0x704f,
cfb0919c
CD		 6381 "Unable to update FCP_CMND priority - ret=0x%x for "
6382 "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id,
6383 fcport->d_id.b.domain, fcport->d_id.b.area,
6384 fcport->d_id.b.al_pa);
09ff701a
SR		 6385 return ret;
6386}
6387
6388/*
6389 * qla24xx_update_all_fcp_prio
6390 * Activates fcp priority for all the logged in ports
6391 *
6392 * Input:
6393 * ha = adapter block pointer.
6394 *
6395 * Return:
6396 * QLA_SUCCESS or QLA_FUNCTION_FAILED
6397 *
6398 * Context:
6399 * Kernel context.
6400 */
6401int
6402qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha)
6403{
6404 int ret;
6405 fc_port_t *fcport;
6406
6407 ret = QLA_FUNCTION_FAILED;
6408 /* We need to set priority for all logged in ports */
6409 list_for_each_entry(fcport, &vha->vp_fcports, list)
6410 ret = qla24xx_update_fcport_fcp_prio(vha, fcport);
6411
6412 return ret;
6413}
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