]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/scsi/qla2xxx/qla_init.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[SCSI] qla2xxx: Only enable link up on the correct interrupt event.
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / qla2xxx / qla_init.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
46152ceb 3 * Copyright (c) 2003-2012 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
73208dfd 8#include "qla_gbl.h"
1da177e4
LT		 9
10#include <linux/delay.h>
5a0e3ad6 11#include <linux/slab.h>
0107109e 12#include <linux/vmalloc.h>
1da177e4
LT		 13
14#include "qla_devtbl.h"
15
4e08df3f
DM		 16#ifdef CONFIG_SPARC
17#include <asm/prom.h>
4e08df3f
DM		 18#endif
19
2d70c103
NB		 20#include <target/target_core_base.h>
21#include "qla_target.h"
22
1da177e4
LT		 23/*
24* QLogic ISP2x00 Hardware Support Function Prototypes.
25*/
1da177e4 26static int qla2x00_isp_firmware(scsi_qla_host_t *);
1da177e4 27static int qla2x00_setup_chip(scsi_qla_host_t *);
1da177e4
LT		 28static int qla2x00_init_rings(scsi_qla_host_t *);
29static int qla2x00_fw_ready(scsi_qla_host_t *);
30static int qla2x00_configure_hba(scsi_qla_host_t *);
1da177e4
LT		 31static int qla2x00_configure_loop(scsi_qla_host_t *);
32static int qla2x00_configure_local_loop(scsi_qla_host_t *);
1da177e4
LT		 33static int qla2x00_configure_fabric(scsi_qla_host_t *);
34static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *, struct list_head *);
1da177e4
LT		 35static int qla2x00_fabric_dev_login(scsi_qla_host_t *, fc_port_t *,
36 uint16_t *);
1da177e4
LT		 37
38static int qla2x00_restart_isp(scsi_qla_host_t *);
1da177e4 39
4d4df193
HK		 40static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *);
41static int qla84xx_init_chip(scsi_qla_host_t *);
73208dfd 42static int qla25xx_init_queues(struct qla_hw_data *);
4d4df193 43
ac280b67
AV		 44/* SRB Extensions ---------------------------------------------------------- */
45
9ba56b95
GM		 46void
47qla2x00_sp_timeout(unsigned long __data)
ac280b67
AV		 48{
49 srb_t *sp = (srb_t *)__data;
4916392b 50 struct srb_iocb *iocb;
ac280b67
AV		 51 fc_port_t *fcport = sp->fcport;
52 struct qla_hw_data *ha = fcport->vha->hw;
53 struct req_que *req;
54 unsigned long flags;
55
56 spin_lock_irqsave(&ha->hardware_lock, flags);
57 req = ha->req_q_map[0];
58 req->outstanding_cmds[sp->handle] = NULL;
9ba56b95 59 iocb = &sp->u.iocb_cmd;
4916392b 60 iocb->timeout(sp);
9ba56b95 61 sp->free(fcport->vha, sp);
6ac52608 62 spin_unlock_irqrestore(&ha->hardware_lock, flags);
ac280b67
AV		 63}
64
9ba56b95
GM		 65void
66qla2x00_sp_free(void *data, void *ptr)
ac280b67 67{
9ba56b95
GM		 68 srb_t *sp = (srb_t *)ptr;
69 struct srb_iocb *iocb = &sp->u.iocb_cmd;
70 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
ac280b67 71
4d97cc53 72 del_timer(&iocb->timer);
9ba56b95 73 mempool_free(sp, vha->hw->srb_mempool);
feafb7b1
AE		 74
75 QLA_VHA_MARK_NOT_BUSY(vha);
ac280b67
AV		 76}
77
ac280b67
AV		 78/* Asynchronous Login/Logout Routines -------------------------------------- */
79
a9b6f722 80unsigned long
5b91490e
AV		 81qla2x00_get_async_timeout(struct scsi_qla_host *vha)
82{
83 unsigned long tmo;
84 struct qla_hw_data *ha = vha->hw;
85
86 /* Firmware should use switch negotiated r_a_tov for timeout. */
87 tmo = ha->r_a_tov / 10 * 2;
88 if (!IS_FWI2_CAPABLE(ha)) {
89 /*
90 * Except for earlier ISPs where the timeout is seeded from the
91 * initialization control block.
92 */
93 tmo = ha->login_timeout;
94 }
95 return tmo;
96}
ac280b67
AV		 97
98static void
9ba56b95 99qla2x00_async_iocb_timeout(void *data)
ac280b67 100{
9ba56b95 101 srb_t *sp = (srb_t *)data;
ac280b67 102 fc_port_t *fcport = sp->fcport;
ac280b67 103
7c3df132 104 ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
cfb0919c 105 "Async-%s timeout - hdl=%x portid=%02x%02x%02x.\n",
9ba56b95 106 sp->name, sp->handle, fcport->d_id.b.domain, fcport->d_id.b.area,
7c3df132 107 fcport->d_id.b.al_pa);
ac280b67 108
5ff1d584 109 fcport->flags &= ~FCF_ASYNC_SENT;
9ba56b95
GM		 110 if (sp->type == SRB_LOGIN_CMD) {
111 struct srb_iocb *lio = &sp->u.iocb_cmd;
ac280b67 112 qla2x00_post_async_logout_work(fcport->vha, fcport, NULL);
6ac52608
AV		 113 /* Retry as needed. */
114 lio->u.logio.data[0] = MBS_COMMAND_ERROR;
115 lio->u.logio.data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
116 QLA_LOGIO_LOGIN_RETRIED : 0;
117 qla2x00_post_async_login_done_work(fcport->vha, fcport,
118 lio->u.logio.data);
119 }
ac280b67
AV		 120}
121
99b0bec7 122static void
9ba56b95 123qla2x00_async_login_sp_done(void *data, void *ptr, int res)
99b0bec7 124{
9ba56b95
GM		 125 srb_t *sp = (srb_t *)ptr;
126 struct srb_iocb *lio = &sp->u.iocb_cmd;
127 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
128
129 if (!test_bit(UNLOADING, &vha->dpc_flags))
130 qla2x00_post_async_login_done_work(sp->fcport->vha, sp->fcport,
131 lio->u.logio.data);
132 sp->free(sp->fcport->vha, sp);
99b0bec7
AV		 133}
134
ac280b67
AV		 135int
136qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport,
137 uint16_t *data)
138{
ac280b67 139 srb_t *sp;
4916392b 140 struct srb_iocb *lio;
ac280b67
AV		 141 int rval;
142
143 rval = QLA_FUNCTION_FAILED;
9ba56b95 144 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 145 if (!sp)
146 goto done;
147
9ba56b95
GM		 148 sp->type = SRB_LOGIN_CMD;
149 sp->name = "login";
150 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
151
152 lio = &sp->u.iocb_cmd;
3822263e 153 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 154 sp->done = qla2x00_async_login_sp_done;
4916392b 155 lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI;
ac280b67 156 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 157 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
ac280b67
AV		 158 rval = qla2x00_start_sp(sp);
159 if (rval != QLA_SUCCESS)
160 goto done_free_sp;
161
7c3df132 162 ql_dbg(ql_dbg_disc, vha, 0x2072,
cfb0919c
CD		 163 "Async-login - hdl=%x, loopid=%x portid=%02x%02x%02x "
164 "retries=%d.\n", sp->handle, fcport->loop_id,
165 fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
166 fcport->login_retry);
ac280b67
AV		 167 return rval;
168
169done_free_sp:
9ba56b95 170 sp->free(fcport->vha, sp);
ac280b67
AV		 171done:
172 return rval;
173}
174
99b0bec7 175static void
9ba56b95 176qla2x00_async_logout_sp_done(void *data, void *ptr, int res)
99b0bec7 177{
9ba56b95
GM		 178 srb_t *sp = (srb_t *)ptr;
179 struct srb_iocb *lio = &sp->u.iocb_cmd;
180 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
181
182 if (!test_bit(UNLOADING, &vha->dpc_flags))
183 qla2x00_post_async_logout_done_work(sp->fcport->vha, sp->fcport,
184 lio->u.logio.data);
185 sp->free(sp->fcport->vha, sp);
99b0bec7
AV		 186}
187
ac280b67
AV		 188int
189qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport)
190{
ac280b67 191 srb_t *sp;
4916392b 192 struct srb_iocb *lio;
ac280b67
AV		 193 int rval;
194
195 rval = QLA_FUNCTION_FAILED;
9ba56b95 196 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 197 if (!sp)
198 goto done;
199
9ba56b95
GM		 200 sp->type = SRB_LOGOUT_CMD;
201 sp->name = "logout";
202 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
203
204 lio = &sp->u.iocb_cmd;
3822263e 205 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 206 sp->done = qla2x00_async_logout_sp_done;
ac280b67
AV		 207 rval = qla2x00_start_sp(sp);
208 if (rval != QLA_SUCCESS)
209 goto done_free_sp;
210
7c3df132 211 ql_dbg(ql_dbg_disc, vha, 0x2070,
cfb0919c
CD		 212 "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
213 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
214 fcport->d_id.b.area, fcport->d_id.b.al_pa);
ac280b67
AV		 215 return rval;
216
217done_free_sp:
9ba56b95 218 sp->free(fcport->vha, sp);
ac280b67
AV		 219done:
220 return rval;
221}
222
5ff1d584 223static void
9ba56b95 224qla2x00_async_adisc_sp_done(void *data, void *ptr, int res)
5ff1d584 225{
9ba56b95
GM		 226 srb_t *sp = (srb_t *)ptr;
227 struct srb_iocb *lio = &sp->u.iocb_cmd;
228 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
229
230 if (!test_bit(UNLOADING, &vha->dpc_flags))
231 qla2x00_post_async_adisc_done_work(sp->fcport->vha, sp->fcport,
232 lio->u.logio.data);
233 sp->free(sp->fcport->vha, sp);
5ff1d584
AV		 234}
235
236int
237qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport,
238 uint16_t *data)
239{
5ff1d584 240 srb_t *sp;
4916392b 241 struct srb_iocb *lio;
5ff1d584
AV		 242 int rval;
243
244 rval = QLA_FUNCTION_FAILED;
9ba56b95 245 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
5ff1d584
AV		 246 if (!sp)
247 goto done;
248
9ba56b95
GM		 249 sp->type = SRB_ADISC_CMD;
250 sp->name = "adisc";
251 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
252
253 lio = &sp->u.iocb_cmd;
3822263e 254 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 255 sp->done = qla2x00_async_adisc_sp_done;
5ff1d584 256 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 257 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
5ff1d584
AV		 258 rval = qla2x00_start_sp(sp);
259 if (rval != QLA_SUCCESS)
260 goto done_free_sp;
261
7c3df132 262 ql_dbg(ql_dbg_disc, vha, 0x206f,
cfb0919c
CD		 263 "Async-adisc - hdl=%x loopid=%x portid=%02x%02x%02x.\n",
264 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
265 fcport->d_id.b.area, fcport->d_id.b.al_pa);
5ff1d584
AV		 266 return rval;
267
268done_free_sp:
9ba56b95 269 sp->free(fcport->vha, sp);
5ff1d584
AV		 270done:
271 return rval;
272}
273
3822263e 274static void
9ba56b95 275qla2x00_async_tm_cmd_done(void *data, void *ptr, int res)
3822263e 276{
9ba56b95
GM		 277 srb_t *sp = (srb_t *)ptr;
278 struct srb_iocb *iocb = &sp->u.iocb_cmd;
279 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
280 uint32_t flags;
281 uint16_t lun;
282 int rval;
3822263e 283
9ba56b95
GM		 284 if (!test_bit(UNLOADING, &vha->dpc_flags)) {
285 flags = iocb->u.tmf.flags;
286 lun = (uint16_t)iocb->u.tmf.lun;
287
288 /* Issue Marker IOCB */
289 rval = qla2x00_marker(vha, vha->hw->req_q_map[0],
290 vha->hw->rsp_q_map[0], sp->fcport->loop_id, lun,
291 flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
292
293 if ((rval != QLA_SUCCESS) || iocb->u.tmf.data) {
294 ql_dbg(ql_dbg_taskm, vha, 0x8030,
295 "TM IOCB failed (%x).\n", rval);
296 }
297 }
298 sp->free(sp->fcport->vha, sp);
3822263e
MI		 299}
300
301int
9ba56b95 302qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t tm_flags, uint32_t lun,
3822263e
MI		 303 uint32_t tag)
304{
305 struct scsi_qla_host *vha = fcport->vha;
3822263e 306 srb_t *sp;
3822263e
MI		 307 struct srb_iocb *tcf;
308 int rval;
309
310 rval = QLA_FUNCTION_FAILED;
9ba56b95 311 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
3822263e
MI		 312 if (!sp)
313 goto done;
314
9ba56b95
GM		 315 sp->type = SRB_TM_CMD;
316 sp->name = "tmf";
317 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
318
319 tcf = &sp->u.iocb_cmd;
320 tcf->u.tmf.flags = tm_flags;
3822263e
MI		 321 tcf->u.tmf.lun = lun;
322 tcf->u.tmf.data = tag;
323 tcf->timeout = qla2x00_async_iocb_timeout;
9ba56b95 324 sp->done = qla2x00_async_tm_cmd_done;
3822263e
MI		 325
326 rval = qla2x00_start_sp(sp);
327 if (rval != QLA_SUCCESS)
328 goto done_free_sp;
329
7c3df132 330 ql_dbg(ql_dbg_taskm, vha, 0x802f,
cfb0919c
CD		 331 "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
332 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
333 fcport->d_id.b.area, fcport->d_id.b.al_pa);
3822263e
MI		 334 return rval;
335
336done_free_sp:
9ba56b95 337 sp->free(fcport->vha, sp);
3822263e
MI		 338done:
339 return rval;
340}
341
4916392b 342void
ac280b67
AV		 343qla2x00_async_login_done(struct scsi_qla_host *vha, fc_port_t *fcport,
344 uint16_t *data)
345{
346 int rval;
ac280b67
AV		 347
348 switch (data[0]) {
349 case MBS_COMMAND_COMPLETE:
a4f92a32
AV		 350 /*
351 * Driver must validate login state - If PRLI not complete,
352 * force a relogin attempt via implicit LOGO, PLOGI, and PRLI
353 * requests.
354 */
355 rval = qla2x00_get_port_database(vha, fcport, 0);
0eba25df
AE		 356 if (rval == QLA_NOT_LOGGED_IN) {
357 fcport->flags &= ~FCF_ASYNC_SENT;
358 fcport->flags |= FCF_LOGIN_NEEDED;
359 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
360 break;
361 }
362
a4f92a32
AV		 363 if (rval != QLA_SUCCESS) {
364 qla2x00_post_async_logout_work(vha, fcport, NULL);
365 qla2x00_post_async_login_work(vha, fcport, NULL);
366 break;
367 }
99b0bec7 368 if (fcport->flags & FCF_FCP2_DEVICE) {
5ff1d584
AV		 369 qla2x00_post_async_adisc_work(vha, fcport, data);
370 break;
99b0bec7
AV		 371 }
372 qla2x00_update_fcport(vha, fcport);
ac280b67
AV		 373 break;
374 case MBS_COMMAND_ERROR:
5ff1d584 375 fcport->flags &= ~FCF_ASYNC_SENT;
ac280b67
AV		 376 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
377 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
378 else
80d79440 379 qla2x00_mark_device_lost(vha, fcport, 1, 0);
ac280b67
AV		 380 break;
381 case MBS_PORT_ID_USED:
382 fcport->loop_id = data[1];
6ac52608 383 qla2x00_post_async_logout_work(vha, fcport, NULL);
ac280b67
AV		 384 qla2x00_post_async_login_work(vha, fcport, NULL);
385 break;
386 case MBS_LOOP_ID_USED:
387 fcport->loop_id++;
388 rval = qla2x00_find_new_loop_id(vha, fcport);
389 if (rval != QLA_SUCCESS) {
5ff1d584 390 fcport->flags &= ~FCF_ASYNC_SENT;
80d79440 391 qla2x00_mark_device_lost(vha, fcport, 1, 0);
ac280b67
AV		 392 break;
393 }
394 qla2x00_post_async_login_work(vha, fcport, NULL);
395 break;
396 }
4916392b 397 return;
ac280b67
AV		 398}
399
4916392b 400void
ac280b67
AV		 401qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport,
402 uint16_t *data)
403{
404 qla2x00_mark_device_lost(vha, fcport, 1, 0);
4916392b 405 return;
ac280b67
AV		 406}
407
4916392b 408void
5ff1d584
AV		 409qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport,
410 uint16_t *data)
411{
412 if (data[0] == MBS_COMMAND_COMPLETE) {
413 qla2x00_update_fcport(vha, fcport);
414
4916392b 415 return;
5ff1d584
AV		 416 }
417
418 /* Retry login. */
419 fcport->flags &= ~FCF_ASYNC_SENT;
420 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
421 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
422 else
80d79440 423 qla2x00_mark_device_lost(vha, fcport, 1, 0);
5ff1d584 424
4916392b 425 return;
5ff1d584
AV		 426}
427
1da177e4
LT		 428/****************************************************************************/
429/* QLogic ISP2x00 Hardware Support Functions. */
430/****************************************************************************/
431
7d613ac6
SV		 432int
433qla83xx_nic_core_fw_load(scsi_qla_host_t *vha)
434{
435 int rval = QLA_SUCCESS;
436 struct qla_hw_data *ha = vha->hw;
437 uint32_t idc_major_ver, idc_minor_ver;
438
439 qla83xx_idc_lock(vha, 0);
440
441 /* SV: TODO: Assign initialization timeout from
442 * flash-info / other param
443 */
444 ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT;
445 ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT;
446
447 /* Set our fcoe function presence */
448 if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) {
449 ql_dbg(ql_dbg_p3p, vha, 0xb077,
450 "Error while setting DRV-Presence.\n");
451 rval = QLA_FUNCTION_FAILED;
452 goto exit;
453 }
454
455 /* Decide the reset ownership */
456 qla83xx_reset_ownership(vha);
457
458 /*
459 * On first protocol driver load:
460 * Init-Owner: Set IDC-Major-Version and Clear IDC-Lock-Recovery
461 * register.
462 * Others: Check compatibility with current IDC Major version.
463 */
464 qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver);
465 if (ha->flags.nic_core_reset_owner) {
466 /* Set IDC Major version */
467 idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION;
468 qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver);
469
470 /* Clearing IDC-Lock-Recovery register */
471 qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0);
472 } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) {
473 /*
474 * Clear further IDC participation if we are not compatible with
475 * the current IDC Major Version.
476 */
477 ql_log(ql_log_warn, vha, 0xb07d,
478 "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n",
479 idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION);
480 __qla83xx_clear_drv_presence(vha);
481 rval = QLA_FUNCTION_FAILED;
482 goto exit;
483 }
484 /* Each function sets its supported Minor version. */
485 qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver);
486 idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2));
487 qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver);
488
489 rval = qla83xx_idc_state_handler(vha);
490
491exit:
492 qla83xx_idc_unlock(vha, 0);
493
494 return rval;
495}
496
1da177e4
LT		 497/*
498* qla2x00_initialize_adapter
499* Initialize board.
500*
501* Input:
502* ha = adapter block pointer.
503*
504* Returns:
505* 0 = success
506*/
507int
e315cd28 508qla2x00_initialize_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 509{
510 int rval;
e315cd28 511 struct qla_hw_data *ha = vha->hw;
73208dfd 512 struct req_que *req = ha->req_q_map[0];
2533cf67 513
1da177e4 514 /* Clear adapter flags. */
e315cd28 515 vha->flags.online = 0;
2533cf67 516 ha->flags.chip_reset_done = 0;
e315cd28 517 vha->flags.reset_active = 0;
85880801
AV		 518 ha->flags.pci_channel_io_perm_failure = 0;
519 ha->flags.eeh_busy = 0;
794a5691 520 ha->flags.thermal_supported = 1;
e315cd28
AC		 521 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
522 atomic_set(&vha->loop_state, LOOP_DOWN);
523 vha->device_flags = DFLG_NO_CABLE;
524 vha->dpc_flags = 0;
525 vha->flags.management_server_logged_in = 0;
526 vha->marker_needed = 0;
1da177e4
LT		 527 ha->isp_abort_cnt = 0;
528 ha->beacon_blink_led = 0;
529
73208dfd
AC		 530 set_bit(0, ha->req_qid_map);
531 set_bit(0, ha->rsp_qid_map);
532
cfb0919c 533 ql_dbg(ql_dbg_init, vha, 0x0040,
7c3df132 534 "Configuring PCI space...\n");
e315cd28 535 rval = ha->isp_ops->pci_config(vha);
1da177e4 536 if (rval) {
7c3df132
SK		 537 ql_log(ql_log_warn, vha, 0x0044,
538 "Unable to configure PCI space.\n");
1da177e4
LT		 539 return (rval);
540 }
541
e315cd28 542 ha->isp_ops->reset_chip(vha);
1da177e4 543
e315cd28 544 rval = qla2xxx_get_flash_info(vha);
c00d8994 545 if (rval) {
7c3df132
SK		 546 ql_log(ql_log_fatal, vha, 0x004f,
547 "Unable to validate FLASH data.\n");
c00d8994
AV		 548 return (rval);
549 }
550
73208dfd 551 ha->isp_ops->get_flash_version(vha, req->ring);
cfb0919c 552 ql_dbg(ql_dbg_init, vha, 0x0061,
7c3df132 553 "Configure NVRAM parameters...\n");
0107109e 554
e315cd28 555 ha->isp_ops->nvram_config(vha);
1da177e4 556
d4c760c2
AV		 557 if (ha->flags.disable_serdes) {
558 /* Mask HBA via NVRAM settings? */
7c3df132
SK		 559 ql_log(ql_log_info, vha, 0x0077,
560 "Masking HBA WWPN "
d4c760c2 561 "%02x%02x%02x%02x%02x%02x%02x%02x (via NVRAM).\n",
e315cd28
AC		 562 vha->port_name[0], vha->port_name[1],
563 vha->port_name[2], vha->port_name[3],
564 vha->port_name[4], vha->port_name[5],
565 vha->port_name[6], vha->port_name[7]);
d4c760c2
AV		 566 return QLA_FUNCTION_FAILED;
567 }
568
cfb0919c 569 ql_dbg(ql_dbg_init, vha, 0x0078,
7c3df132 570 "Verifying loaded RISC code...\n");
1da177e4 571
e315cd28
AC		 572 if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) {
573 rval = ha->isp_ops->chip_diag(vha);
d19044c3
AV		 574 if (rval)
575 return (rval);
e315cd28 576 rval = qla2x00_setup_chip(vha);
d19044c3
AV		 577 if (rval)
578 return (rval);
1da177e4 579 }
a9083016 580
4d4df193 581 if (IS_QLA84XX(ha)) {
e315cd28 582 ha->cs84xx = qla84xx_get_chip(vha);
4d4df193 583 if (!ha->cs84xx) {
7c3df132 584 ql_log(ql_log_warn, vha, 0x00d0,
4d4df193
HK		 585 "Unable to configure ISP84XX.\n");
586 return QLA_FUNCTION_FAILED;
587 }
588 }
2d70c103
NB		 589
590 if (qla_ini_mode_enabled(vha))
591 rval = qla2x00_init_rings(vha);
592
2533cf67 593 ha->flags.chip_reset_done = 1;
1da177e4 594
9a069e19 595 if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) {
6c452a45 596 /* Issue verify 84xx FW IOCB to complete 84xx initialization */
9a069e19
GM		 597 rval = qla84xx_init_chip(vha);
598 if (rval != QLA_SUCCESS) {
7c3df132
SK		 599 ql_log(ql_log_warn, vha, 0x00d4,
600 "Unable to initialize ISP84XX.\n");
9a069e19
GM		 601 qla84xx_put_chip(vha);
602 }
603 }
604
7d613ac6
SV		 605 /* Load the NIC Core f/w if we are the first protocol driver. */
606 if (IS_QLA8031(ha)) {
607 rval = qla83xx_nic_core_fw_load(vha);
608 if (rval)
609 ql_log(ql_log_warn, vha, 0x0124,
610 "Error in initializing NIC Core f/w.\n");
611 }
612
2f0f3f4f
MI		 613 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
614 qla24xx_read_fcp_prio_cfg(vha);
09ff701a 615
1da177e4
LT		 616 return (rval);
617}
618
619/**
abbd8870 620 * qla2100_pci_config() - Setup ISP21xx PCI configuration registers.
1da177e4
LT		 621 * @ha: HA context
622 *
623 * Returns 0 on success.
624 */
abbd8870 625int
e315cd28 626qla2100_pci_config(scsi_qla_host_t *vha)
1da177e4 627{
a157b101 628 uint16_t w;
abbd8870 629 unsigned long flags;
e315cd28 630 struct qla_hw_data *ha = vha->hw;
3d71644c 631 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 632
1da177e4 633 pci_set_master(ha->pdev);
af6177d8 634 pci_try_set_mwi(ha->pdev);
1da177e4 635
1da177e4 636 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 637 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
abbd8870
AV		 638 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
639
737faece 640 pci_disable_rom(ha->pdev);
1da177e4
LT		 641
642 /* Get PCI bus information. */
643 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 644 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
1da177e4
LT		 645 spin_unlock_irqrestore(&ha->hardware_lock, flags);
646
abbd8870
AV		 647 return QLA_SUCCESS;
648}
1da177e4 649
abbd8870
AV		 650/**
651 * qla2300_pci_config() - Setup ISP23xx PCI configuration registers.
652 * @ha: HA context
653 *
654 * Returns 0 on success.
655 */
656int
e315cd28 657qla2300_pci_config(scsi_qla_host_t *vha)
abbd8870 658{
a157b101 659 uint16_t w;
abbd8870
AV		 660 unsigned long flags = 0;
661 uint32_t cnt;
e315cd28 662 struct qla_hw_data *ha = vha->hw;
3d71644c 663 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 664
abbd8870 665 pci_set_master(ha->pdev);
af6177d8 666 pci_try_set_mwi(ha->pdev);
1da177e4 667
abbd8870 668 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 669 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
1da177e4 670
abbd8870
AV		 671 if (IS_QLA2322(ha) || IS_QLA6322(ha))
672 w &= ~PCI_COMMAND_INTX_DISABLE;
a157b101 673 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1da177e4 674
abbd8870
AV		 675 /*
676 * If this is a 2300 card and not 2312, reset the
677 * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately,
678 * the 2310 also reports itself as a 2300 so we need to get the
679 * fb revision level -- a 6 indicates it really is a 2300 and
680 * not a 2310.
681 */
682 if (IS_QLA2300(ha)) {
683 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 684
abbd8870 685 /* Pause RISC. */
3d71644c 686 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
abbd8870 687 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 688 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
abbd8870 689 break;
1da177e4 690
abbd8870
AV		 691 udelay(10);
692 }
1da177e4 693
abbd8870 694 /* Select FPM registers. */
3d71644c
AV		 695 WRT_REG_WORD(&reg->ctrl_status, 0x20);
696 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 697
698 /* Get the fb rev level */
3d71644c 699 ha->fb_rev = RD_FB_CMD_REG(ha, reg);
abbd8870
AV		 700
701 if (ha->fb_rev == FPM_2300)
a157b101 702 pci_clear_mwi(ha->pdev);
abbd8870
AV		 703
704 /* Deselect FPM registers. */
3d71644c
AV		 705 WRT_REG_WORD(&reg->ctrl_status, 0x0);
706 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 707
708 /* Release RISC module. */
3d71644c 709 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
abbd8870 710 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 711 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0)
abbd8870
AV		 712 break;
713
714 udelay(10);
1da177e4 715 }
1da177e4 716
abbd8870
AV		 717 spin_unlock_irqrestore(&ha->hardware_lock, flags);
718 }
1da177e4 719
abbd8870
AV		 720 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
721
737faece 722 pci_disable_rom(ha->pdev);
1da177e4 723
abbd8870
AV		 724 /* Get PCI bus information. */
725 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 726 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 727 spin_unlock_irqrestore(&ha->hardware_lock, flags);
728
729 return QLA_SUCCESS;
1da177e4
LT		 730}
731
0107109e
AV		 732/**
733 * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers.
734 * @ha: HA context
735 *
736 * Returns 0 on success.
737 */
738int
e315cd28 739qla24xx_pci_config(scsi_qla_host_t *vha)
0107109e 740{
a157b101 741 uint16_t w;
0107109e 742 unsigned long flags = 0;
e315cd28 743 struct qla_hw_data *ha = vha->hw;
0107109e 744 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
0107109e
AV		 745
746 pci_set_master(ha->pdev);
af6177d8 747 pci_try_set_mwi(ha->pdev);
0107109e
AV		 748
749 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 750 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
0107109e
AV		 751 w &= ~PCI_COMMAND_INTX_DISABLE;
752 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
753
754 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
755
756 /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */
f85ec187
AV		 757 if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
758 pcix_set_mmrbc(ha->pdev, 2048);
0107109e
AV		 759
760 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 761 if (pci_is_pcie(ha->pdev))
f85ec187 762 pcie_set_readrq(ha->pdev, 2048);
0107109e 763
737faece 764 pci_disable_rom(ha->pdev);
0107109e 765
44c10138 766 ha->chip_revision = ha->pdev->revision;
a8488abe 767
0107109e
AV		 768 /* Get PCI bus information. */
769 spin_lock_irqsave(&ha->hardware_lock, flags);
770 ha->pci_attr = RD_REG_DWORD(&reg->ctrl_status);
771 spin_unlock_irqrestore(&ha->hardware_lock, flags);
772
773 return QLA_SUCCESS;
774}
775
c3a2f0df
AV		 776/**
777 * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers.
778 * @ha: HA context
779 *
780 * Returns 0 on success.
781 */
782int
e315cd28 783qla25xx_pci_config(scsi_qla_host_t *vha)
c3a2f0df
AV		 784{
785 uint16_t w;
e315cd28 786 struct qla_hw_data *ha = vha->hw;
c3a2f0df
AV		 787
788 pci_set_master(ha->pdev);
789 pci_try_set_mwi(ha->pdev);
790
791 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
792 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
793 w &= ~PCI_COMMAND_INTX_DISABLE;
794 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
795
796 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 797 if (pci_is_pcie(ha->pdev))
c3a2f0df
AV		 798 pcie_set_readrq(ha->pdev, 2048);
799
737faece 800 pci_disable_rom(ha->pdev);
c3a2f0df
AV		 801
802 ha->chip_revision = ha->pdev->revision;
803
804 return QLA_SUCCESS;
805}
806
1da177e4
LT		 807/**
808 * qla2x00_isp_firmware() - Choose firmware image.
809 * @ha: HA context
810 *
811 * Returns 0 on success.
812 */
813static int
e315cd28 814qla2x00_isp_firmware(scsi_qla_host_t *vha)
1da177e4
LT		 815{
816 int rval;
42e421b1
AV		 817 uint16_t loop_id, topo, sw_cap;
818 uint8_t domain, area, al_pa;
e315cd28 819 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 820
821 /* Assume loading risc code */
fa2a1ce5 822 rval = QLA_FUNCTION_FAILED;
1da177e4
LT		 823
824 if (ha->flags.disable_risc_code_load) {
7c3df132 825 ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n");
1da177e4
LT		 826
827 /* Verify checksum of loaded RISC code. */
e315cd28 828 rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address);
42e421b1
AV		 829 if (rval == QLA_SUCCESS) {
830 /* And, verify we are not in ROM code. */
e315cd28 831 rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa,
42e421b1
AV		 832 &area, &domain, &topo, &sw_cap);
833 }
1da177e4
LT		 834 }
835
7c3df132
SK		 836 if (rval)
837 ql_dbg(ql_dbg_init, vha, 0x007a,
838 "**** Load RISC code ****.\n");
1da177e4
LT		 839
840 return (rval);
841}
842
843/**
844 * qla2x00_reset_chip() - Reset ISP chip.
845 * @ha: HA context
846 *
847 * Returns 0 on success.
848 */
abbd8870 849void
e315cd28 850qla2x00_reset_chip(scsi_qla_host_t *vha)
1da177e4
LT		 851{
852 unsigned long flags = 0;
e315cd28 853 struct qla_hw_data *ha = vha->hw;
3d71644c 854 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 855 uint32_t cnt;
1da177e4
LT		 856 uint16_t cmd;
857
85880801
AV		 858 if (unlikely(pci_channel_offline(ha->pdev)))
859 return;
860
fd34f556 861 ha->isp_ops->disable_intrs(ha);
1da177e4
LT		 862
863 spin_lock_irqsave(&ha->hardware_lock, flags);
864
865 /* Turn off master enable */
866 cmd = 0;
867 pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd);
868 cmd &= ~PCI_COMMAND_MASTER;
869 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
870
871 if (!IS_QLA2100(ha)) {
872 /* Pause RISC. */
873 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
874 if (IS_QLA2200(ha) || IS_QLA2300(ha)) {
875 for (cnt = 0; cnt < 30000; cnt++) {
876 if ((RD_REG_WORD(&reg->hccr) &
877 HCCR_RISC_PAUSE) != 0)
878 break;
879 udelay(100);
880 }
881 } else {
882 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
883 udelay(10);
884 }
885
886 /* Select FPM registers. */
887 WRT_REG_WORD(&reg->ctrl_status, 0x20);
888 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
889
890 /* FPM Soft Reset. */
891 WRT_REG_WORD(&reg->fpm_diag_config, 0x100);
892 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
893
894 /* Toggle Fpm Reset. */
895 if (!IS_QLA2200(ha)) {
896 WRT_REG_WORD(&reg->fpm_diag_config, 0x0);
897 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
898 }
899
900 /* Select frame buffer registers. */
901 WRT_REG_WORD(&reg->ctrl_status, 0x10);
902 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
903
904 /* Reset frame buffer FIFOs. */
905 if (IS_QLA2200(ha)) {
906 WRT_FB_CMD_REG(ha, reg, 0xa000);
907 RD_FB_CMD_REG(ha, reg); /* PCI Posting. */
908 } else {
909 WRT_FB_CMD_REG(ha, reg, 0x00fc);
910
911 /* Read back fb_cmd until zero or 3 seconds max */
912 for (cnt = 0; cnt < 3000; cnt++) {
913 if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0)
914 break;
915 udelay(100);
916 }
917 }
918
919 /* Select RISC module registers. */
920 WRT_REG_WORD(&reg->ctrl_status, 0);
921 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
922
923 /* Reset RISC processor. */
924 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
925 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
926
927 /* Release RISC processor. */
928 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
929 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
930 }
931
932 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
933 WRT_REG_WORD(&reg->hccr, HCCR_CLR_HOST_INT);
934
935 /* Reset ISP chip. */
936 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
937
938 /* Wait for RISC to recover from reset. */
939 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
940 /*
941 * It is necessary to for a delay here since the card doesn't
942 * respond to PCI reads during a reset. On some architectures
943 * this will result in an MCA.
944 */
945 udelay(20);
946 for (cnt = 30000; cnt; cnt--) {
947 if ((RD_REG_WORD(&reg->ctrl_status) &
948 CSR_ISP_SOFT_RESET) == 0)
949 break;
950 udelay(100);
951 }
952 } else
953 udelay(10);
954
955 /* Reset RISC processor. */
956 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
957
958 WRT_REG_WORD(&reg->semaphore, 0);
959
960 /* Release RISC processor. */
961 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
962 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
963
964 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
965 for (cnt = 0; cnt < 30000; cnt++) {
ffb39f03 966 if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY)
1da177e4 967 break;
1da177e4
LT		 968
969 udelay(100);
970 }
971 } else
972 udelay(100);
973
974 /* Turn on master enable */
975 cmd |= PCI_COMMAND_MASTER;
976 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
977
978 /* Disable RISC pause on FPM parity error. */
979 if (!IS_QLA2100(ha)) {
980 WRT_REG_WORD(&reg->hccr, HCCR_DISABLE_PARITY_PAUSE);
981 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
982 }
983
984 spin_unlock_irqrestore(&ha->hardware_lock, flags);
985}
986
b1d46989
MI		 987/**
988 * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC.
989 *
990 * Returns 0 on success.
991 */
992int
993qla81xx_reset_mpi(scsi_qla_host_t *vha)
994{
995 uint16_t mb[4] = {0x1010, 0, 1, 0};
996
6246b8a1
GM		 997 if (!IS_QLA81XX(vha->hw))
998 return QLA_SUCCESS;
999
b1d46989
MI		 1000 return qla81xx_write_mpi_register(vha, mb);
1001}
1002
0107109e 1003/**
88c26663 1004 * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC.
0107109e
AV		 1005 * @ha: HA context
1006 *
1007 * Returns 0 on success.
1008 */
88c26663 1009static inline void
e315cd28 1010qla24xx_reset_risc(scsi_qla_host_t *vha)
0107109e
AV		 1011{
1012 unsigned long flags = 0;
e315cd28 1013 struct qla_hw_data *ha = vha->hw;
0107109e
AV		 1014 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1015 uint32_t cnt, d2;
335a1cc9 1016 uint16_t wd;
b1d46989 1017 static int abts_cnt; /* ISP abort retry counts */
0107109e 1018
0107109e
AV		 1019 spin_lock_irqsave(&ha->hardware_lock, flags);
1020
1021 /* Reset RISC. */
1022 WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
1023 for (cnt = 0; cnt < 30000; cnt++) {
1024 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
1025 break;
1026
1027 udelay(10);
1028 }
1029
1030 WRT_REG_DWORD(&reg->ctrl_status,
1031 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
335a1cc9 1032 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
88c26663 1033
335a1cc9 1034 udelay(100);
88c26663 1035 /* Wait for firmware to complete NVRAM accesses. */
88c26663
AV		 1036 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1037 for (cnt = 10000 ; cnt && d2; cnt--) {
1038 udelay(5);
1039 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1040 barrier();
1041 }
1042
335a1cc9 1043 /* Wait for soft-reset to complete. */
0107109e
AV		 1044 d2 = RD_REG_DWORD(&reg->ctrl_status);
1045 for (cnt = 6000000 ; cnt && (d2 & CSRX_ISP_SOFT_RESET); cnt--) {
1046 udelay(5);
1047 d2 = RD_REG_DWORD(&reg->ctrl_status);
1048 barrier();
1049 }
1050
b1d46989
MI		 1051 /* If required, do an MPI FW reset now */
1052 if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
1053 if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
1054 if (++abts_cnt < 5) {
1055 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1056 set_bit(MPI_RESET_NEEDED, &vha->dpc_flags);
1057 } else {
1058 /*
1059 * We exhausted the ISP abort retries. We have to
1060 * set the board offline.
1061 */
1062 abts_cnt = 0;
1063 vha->flags.online = 0;
1064 }
1065 }
1066 }
1067
0107109e
AV		 1068 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
1069 RD_REG_DWORD(&reg->hccr);
1070
1071 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
1072 RD_REG_DWORD(&reg->hccr);
1073
1074 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
1075 RD_REG_DWORD(&reg->hccr);
1076
1077 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1078 for (cnt = 6000000 ; cnt && d2; cnt--) {
1079 udelay(5);
1080 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1081 barrier();
1082 }
1083
1084 spin_unlock_irqrestore(&ha->hardware_lock, flags);
124f85e6
AV		 1085
1086 if (IS_NOPOLLING_TYPE(ha))
1087 ha->isp_ops->enable_intrs(ha);
0107109e
AV		 1088}
1089
88c26663
AV		 1090/**
1091 * qla24xx_reset_chip() - Reset ISP24xx chip.
1092 * @ha: HA context
1093 *
1094 * Returns 0 on success.
1095 */
1096void
e315cd28 1097qla24xx_reset_chip(scsi_qla_host_t *vha)
88c26663 1098{
e315cd28 1099 struct qla_hw_data *ha = vha->hw;
85880801
AV		 1100
1101 if (pci_channel_offline(ha->pdev) &&
1102 ha->flags.pci_channel_io_perm_failure) {
1103 return;
1104 }
1105
fd34f556 1106 ha->isp_ops->disable_intrs(ha);
88c26663
AV		 1107
1108 /* Perform RISC reset. */
e315cd28 1109 qla24xx_reset_risc(vha);
88c26663
AV		 1110}
1111
1da177e4
LT		 1112/**
1113 * qla2x00_chip_diag() - Test chip for proper operation.
1114 * @ha: HA context
1115 *
1116 * Returns 0 on success.
1117 */
abbd8870 1118int
e315cd28 1119qla2x00_chip_diag(scsi_qla_host_t *vha)
1da177e4
LT		 1120{
1121 int rval;
e315cd28 1122 struct qla_hw_data *ha = vha->hw;
3d71644c 1123 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 1124 unsigned long flags = 0;
1125 uint16_t data;
1126 uint32_t cnt;
1127 uint16_t mb[5];
73208dfd 1128 struct req_que *req = ha->req_q_map[0];
1da177e4
LT		 1129
1130 /* Assume a failed state */
1131 rval = QLA_FUNCTION_FAILED;
1132
7c3df132
SK		 1133 ql_dbg(ql_dbg_init, vha, 0x007b,
1134 "Testing device at %lx.\n", (u_long)&reg->flash_address);
1da177e4
LT		 1135
1136 spin_lock_irqsave(&ha->hardware_lock, flags);
1137
1138 /* Reset ISP chip. */
1139 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1140
1141 /*
1142 * We need to have a delay here since the card will not respond while
1143 * in reset causing an MCA on some architectures.
1144 */
1145 udelay(20);
1146 data = qla2x00_debounce_register(&reg->ctrl_status);
1147 for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {
1148 udelay(5);
1149 data = RD_REG_WORD(&reg->ctrl_status);
1150 barrier();
1151 }
1152
1153 if (!cnt)
1154 goto chip_diag_failed;
1155
7c3df132
SK		 1156 ql_dbg(ql_dbg_init, vha, 0x007c,
1157 "Reset register cleared by chip reset.\n");
1da177e4
LT		 1158
1159 /* Reset RISC processor. */
1160 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
1161 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
1162
1163 /* Workaround for QLA2312 PCI parity error */
1164 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1165 data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0));
1166 for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) {
1167 udelay(5);
1168 data = RD_MAILBOX_REG(ha, reg, 0);
fa2a1ce5 1169 barrier();
1da177e4
LT		 1170 }
1171 } else
1172 udelay(10);
1173
1174 if (!cnt)
1175 goto chip_diag_failed;
1176
1177 /* Check product ID of chip */
7c3df132 1178 ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product Id of chip.\n");
1da177e4
LT		 1179
1180 mb[1] = RD_MAILBOX_REG(ha, reg, 1);
1181 mb[2] = RD_MAILBOX_REG(ha, reg, 2);
1182 mb[3] = RD_MAILBOX_REG(ha, reg, 3);
1183 mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4));
1184 if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) ||
1185 mb[3] != PROD_ID_3) {
7c3df132
SK		 1186 ql_log(ql_log_warn, vha, 0x0062,
1187 "Wrong product ID = 0x%x,0x%x,0x%x.\n",
1188 mb[1], mb[2], mb[3]);
1da177e4
LT		 1189
1190 goto chip_diag_failed;
1191 }
1192 ha->product_id[0] = mb[1];
1193 ha->product_id[1] = mb[2];
1194 ha->product_id[2] = mb[3];
1195 ha->product_id[3] = mb[4];
1196
1197 /* Adjust fw RISC transfer size */
73208dfd 1198 if (req->length > 1024)
1da177e4
LT		 1199 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024;
1200 else
1201 ha->fw_transfer_size = REQUEST_ENTRY_SIZE *
73208dfd 1202 req->length;
1da177e4
LT		 1203
1204 if (IS_QLA2200(ha) &&
1205 RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) {
1206 /* Limit firmware transfer size with a 2200A */
7c3df132 1207 ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n");
1da177e4 1208
ea5b6382 1209 ha->device_type |= DT_ISP2200A;
1da177e4
LT		 1210 ha->fw_transfer_size = 128;
1211 }
1212
1213 /* Wrap Incoming Mailboxes Test. */
1214 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1215
7c3df132 1216 ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n");
e315cd28 1217 rval = qla2x00_mbx_reg_test(vha);
7c3df132
SK		 1218 if (rval)
1219 ql_log(ql_log_warn, vha, 0x0080,
1220 "Failed mailbox send register test.\n");
1221 else
1da177e4
LT		 1222 /* Flag a successful rval */
1223 rval = QLA_SUCCESS;
1da177e4
LT		 1224 spin_lock_irqsave(&ha->hardware_lock, flags);
1225
1226chip_diag_failed:
1227 if (rval)
7c3df132
SK		 1228 ql_log(ql_log_info, vha, 0x0081,
1229 "Chip diagnostics **** FAILED ****.\n");
1da177e4
LT		 1230
1231 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1232
1233 return (rval);
1234}
1235
0107109e
AV		 1236/**
1237 * qla24xx_chip_diag() - Test ISP24xx for proper operation.
1238 * @ha: HA context
1239 *
1240 * Returns 0 on success.
1241 */
1242int
e315cd28 1243qla24xx_chip_diag(scsi_qla_host_t *vha)
0107109e
AV		 1244{
1245 int rval;
e315cd28 1246 struct qla_hw_data *ha = vha->hw;
73208dfd 1247 struct req_que *req = ha->req_q_map[0];
0107109e 1248
a9083016
GM		 1249 if (IS_QLA82XX(ha))
1250 return QLA_SUCCESS;
1251
73208dfd 1252 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
0107109e 1253
e315cd28 1254 rval = qla2x00_mbx_reg_test(vha);
0107109e 1255 if (rval) {
7c3df132
SK		 1256 ql_log(ql_log_warn, vha, 0x0082,
1257 "Failed mailbox send register test.\n");
0107109e
AV		 1258 } else {
1259 /* Flag a successful rval */
1260 rval = QLA_SUCCESS;
1261 }
1262
1263 return rval;
1264}
1265
a7a167bf 1266void
e315cd28 1267qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
0107109e 1268{
a7a167bf
AV		 1269 int rval;
1270 uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
73208dfd 1271 eft_size, fce_size, mq_size;
df613b96
AV		 1272 dma_addr_t tc_dma;
1273 void *tc;
e315cd28 1274 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 1275 struct req_que *req = ha->req_q_map[0];
1276 struct rsp_que *rsp = ha->rsp_q_map[0];
a7a167bf
AV		 1277
1278 if (ha->fw_dump) {
7c3df132
SK		 1279 ql_dbg(ql_dbg_init, vha, 0x00bd,
1280 "Firmware dump already allocated.\n");
a7a167bf
AV		 1281 return;
1282 }
d4e3e04d 1283
0107109e 1284 ha->fw_dumped = 0;
73208dfd 1285 fixed_size = mem_size = eft_size = fce_size = mq_size = 0;
d4e3e04d 1286 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
a7a167bf 1287 fixed_size = sizeof(struct qla2100_fw_dump);
d4e3e04d 1288 } else if (IS_QLA23XX(ha)) {
a7a167bf
AV		 1289 fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
1290 mem_size = (ha->fw_memory_size - 0x11000 + 1) *
1291 sizeof(uint16_t);
e428924c 1292 } else if (IS_FWI2_CAPABLE(ha)) {
6246b8a1
GM		 1293 if (IS_QLA83XX(ha))
1294 fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem);
1295 else if (IS_QLA81XX(ha))
3a03eb79
AV		 1296 fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
1297 else if (IS_QLA25XX(ha))
1298 fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
1299 else
1300 fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
a7a167bf
AV		 1301 mem_size = (ha->fw_memory_size - 0x100000 + 1) *
1302 sizeof(uint32_t);
050c9bb1 1303 if (ha->mqenable) {
6246b8a1
GM		 1304 if (!IS_QLA83XX(ha))
1305 mq_size = sizeof(struct qla2xxx_mq_chain);
050c9bb1
GM		 1306 /*
1307 * Allocate maximum buffer size for all queues.
1308 * Resizing must be done at end-of-dump processing.
1309 */
1310 mq_size += ha->max_req_queues *
1311 (req->length * sizeof(request_t));
1312 mq_size += ha->max_rsp_queues *
1313 (rsp->length * sizeof(response_t));
1314 }
2d70c103
NB		 1315 if (ha->tgt.atio_q_length)
1316 mq_size += ha->tgt.atio_q_length * sizeof(request_t);
df613b96 1317 /* Allocate memory for Fibre Channel Event Buffer. */
6246b8a1 1318 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha))
436a7b11 1319 goto try_eft;
df613b96
AV		 1320
1321 tc = dma_alloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
1322 GFP_KERNEL);
1323 if (!tc) {
7c3df132
SK		 1324 ql_log(ql_log_warn, vha, 0x00be,
1325 "Unable to allocate (%d KB) for FCE.\n",
1326 FCE_SIZE / 1024);
17d98630 1327 goto try_eft;
df613b96
AV		 1328 }
1329
1330 memset(tc, 0, FCE_SIZE);
e315cd28 1331 rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS,
df613b96
AV		 1332 ha->fce_mb, &ha->fce_bufs);
1333 if (rval) {
7c3df132
SK		 1334 ql_log(ql_log_warn, vha, 0x00bf,
1335 "Unable to initialize FCE (%d).\n", rval);
df613b96
AV		 1336 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc,
1337 tc_dma);
1338 ha->flags.fce_enabled = 0;
17d98630 1339 goto try_eft;
df613b96 1340 }
cfb0919c 1341 ql_dbg(ql_dbg_init, vha, 0x00c0,
7c3df132 1342 "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024);
df613b96 1343
7d9dade3 1344 fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE;
df613b96
AV		 1345 ha->flags.fce_enabled = 1;
1346 ha->fce_dma = tc_dma;
1347 ha->fce = tc;
436a7b11
AV		 1348try_eft:
1349 /* Allocate memory for Extended Trace Buffer. */
1350 tc = dma_alloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
1351 GFP_KERNEL);
1352 if (!tc) {
7c3df132
SK		 1353 ql_log(ql_log_warn, vha, 0x00c1,
1354 "Unable to allocate (%d KB) for EFT.\n",
1355 EFT_SIZE / 1024);
436a7b11
AV		 1356 goto cont_alloc;
1357 }
1358
1359 memset(tc, 0, EFT_SIZE);
e315cd28 1360 rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
436a7b11 1361 if (rval) {
7c3df132
SK		 1362 ql_log(ql_log_warn, vha, 0x00c2,
1363 "Unable to initialize EFT (%d).\n", rval);
436a7b11
AV		 1364 dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc,
1365 tc_dma);
1366 goto cont_alloc;
1367 }
cfb0919c 1368 ql_dbg(ql_dbg_init, vha, 0x00c3,
7c3df132 1369 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
436a7b11
AV		 1370
1371 eft_size = EFT_SIZE;
1372 ha->eft_dma = tc_dma;
1373 ha->eft = tc;
d4e3e04d 1374 }
a7a167bf 1375cont_alloc:
73208dfd
AC		 1376 req_q_size = req->length * sizeof(request_t);
1377 rsp_q_size = rsp->length * sizeof(response_t);
a7a167bf
AV		 1378
1379 dump_size = offsetof(struct qla2xxx_fw_dump, isp);
2afa19a9 1380 dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size;
bb99de67
AV		 1381 ha->chain_offset = dump_size;
1382 dump_size += mq_size + fce_size;
d4e3e04d
AV		 1383
1384 ha->fw_dump = vmalloc(dump_size);
a7a167bf 1385 if (!ha->fw_dump) {
7c3df132
SK		 1386 ql_log(ql_log_warn, vha, 0x00c4,
1387 "Unable to allocate (%d KB) for firmware dump.\n",
1388 dump_size / 1024);
a7a167bf 1389
e30d1756
MI		 1390 if (ha->fce) {
1391 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
1392 ha->fce_dma);
1393 ha->fce = NULL;
1394 ha->fce_dma = 0;
1395 }
1396
a7a167bf
AV		 1397 if (ha->eft) {
1398 dma_free_coherent(&ha->pdev->dev, eft_size, ha->eft,
1399 ha->eft_dma);
1400 ha->eft = NULL;
1401 ha->eft_dma = 0;
1402 }
1403 return;
1404 }
cfb0919c 1405 ql_dbg(ql_dbg_init, vha, 0x00c5,
7c3df132 1406 "Allocated (%d KB) for firmware dump.\n", dump_size / 1024);
a7a167bf
AV		 1407
1408 ha->fw_dump_len = dump_size;
1409 ha->fw_dump->signature[0] = 'Q';
1410 ha->fw_dump->signature[1] = 'L';
1411 ha->fw_dump->signature[2] = 'G';
1412 ha->fw_dump->signature[3] = 'C';
1413 ha->fw_dump->version = __constant_htonl(1);
1414
1415 ha->fw_dump->fixed_size = htonl(fixed_size);
1416 ha->fw_dump->mem_size = htonl(mem_size);
1417 ha->fw_dump->req_q_size = htonl(req_q_size);
1418 ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
1419
1420 ha->fw_dump->eft_size = htonl(eft_size);
1421 ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma));
1422 ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma));
1423
1424 ha->fw_dump->header_size =
1425 htonl(offsetof(struct qla2xxx_fw_dump, isp));
0107109e
AV		 1426}
1427
18e7555a
AV		 1428static int
1429qla81xx_mpi_sync(scsi_qla_host_t *vha)
1430{
1431#define MPS_MASK 0xe0
1432 int rval;
1433 uint16_t dc;
1434 uint32_t dw;
18e7555a
AV		 1435
1436 if (!IS_QLA81XX(vha->hw))
1437 return QLA_SUCCESS;
1438
1439 rval = qla2x00_write_ram_word(vha, 0x7c00, 1);
1440 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1441 ql_log(ql_log_warn, vha, 0x0105,
1442 "Unable to acquire semaphore.\n");
18e7555a
AV		 1443 goto done;
1444 }
1445
1446 pci_read_config_word(vha->hw->pdev, 0x54, &dc);
1447 rval = qla2x00_read_ram_word(vha, 0x7a15, &dw);
1448 if (rval != QLA_SUCCESS) {
7c3df132 1449 ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n");
18e7555a
AV		 1450 goto done_release;
1451 }
1452
1453 dc &= MPS_MASK;
1454 if (dc == (dw & MPS_MASK))
1455 goto done_release;
1456
1457 dw &= ~MPS_MASK;
1458 dw |= dc;
1459 rval = qla2x00_write_ram_word(vha, 0x7a15, dw);
1460 if (rval != QLA_SUCCESS) {
7c3df132 1461 ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n");
18e7555a
AV		 1462 }
1463
1464done_release:
1465 rval = qla2x00_write_ram_word(vha, 0x7c00, 0);
1466 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1467 ql_log(ql_log_warn, vha, 0x006d,
1468 "Unable to release semaphore.\n");
18e7555a
AV		 1469 }
1470
1471done:
1472 return rval;
1473}
1474
1da177e4
LT		 1475/**
1476 * qla2x00_setup_chip() - Load and start RISC firmware.
1477 * @ha: HA context
1478 *
1479 * Returns 0 on success.
1480 */
1481static int
e315cd28 1482qla2x00_setup_chip(scsi_qla_host_t *vha)
1da177e4 1483{
0107109e
AV		 1484 int rval;
1485 uint32_t srisc_address = 0;
e315cd28 1486 struct qla_hw_data *ha = vha->hw;
3db0652e
AV		 1487 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1488 unsigned long flags;
dda772e8 1489 uint16_t fw_major_version;
3db0652e 1490
a9083016
GM		 1491 if (IS_QLA82XX(ha)) {
1492 rval = ha->isp_ops->load_risc(vha, &srisc_address);
14e303d9
AV		 1493 if (rval == QLA_SUCCESS) {
1494 qla2x00_stop_firmware(vha);
a9083016 1495 goto enable_82xx_npiv;
14e303d9 1496 } else
b963752f 1497 goto failed;
a9083016
GM		 1498 }
1499
3db0652e
AV		 1500 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1501 /* Disable SRAM, Instruction RAM and GP RAM parity. */
1502 spin_lock_irqsave(&ha->hardware_lock, flags);
1503 WRT_REG_WORD(&reg->hccr, (HCCR_ENABLE_PARITY + 0x0));
1504 RD_REG_WORD(&reg->hccr);
1505 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1506 }
1da177e4 1507
18e7555a
AV		 1508 qla81xx_mpi_sync(vha);
1509
1da177e4 1510 /* Load firmware sequences */
e315cd28 1511 rval = ha->isp_ops->load_risc(vha, &srisc_address);
0107109e 1512 if (rval == QLA_SUCCESS) {
7c3df132
SK		 1513 ql_dbg(ql_dbg_init, vha, 0x00c9,
1514 "Verifying Checksum of loaded RISC code.\n");
1da177e4 1515
e315cd28 1516 rval = qla2x00_verify_checksum(vha, srisc_address);
1da177e4
LT		 1517 if (rval == QLA_SUCCESS) {
1518 /* Start firmware execution. */
7c3df132
SK		 1519 ql_dbg(ql_dbg_init, vha, 0x00ca,
1520 "Starting firmware.\n");
1da177e4 1521
e315cd28 1522 rval = qla2x00_execute_fw(vha, srisc_address);
1da177e4 1523 /* Retrieve firmware information. */
dda772e8 1524 if (rval == QLA_SUCCESS) {
a9083016 1525enable_82xx_npiv:
dda772e8 1526 fw_major_version = ha->fw_major_version;
3173167f
GM		 1527 if (IS_QLA82XX(ha))
1528 qla82xx_check_md_needed(vha);
6246b8a1
GM		 1529 else
1530 rval = qla2x00_get_fw_version(vha);
ca9e9c3e
AV		 1531 if (rval != QLA_SUCCESS)
1532 goto failed;
2c3dfe3f 1533 ha->flags.npiv_supported = 0;
e315cd28 1534 if (IS_QLA2XXX_MIDTYPE(ha) &&
946fb891 1535 (ha->fw_attributes & BIT_2)) {
2c3dfe3f 1536 ha->flags.npiv_supported = 1;
4d0ea247
SJ		 1537 if ((!ha->max_npiv_vports) ||
1538 ((ha->max_npiv_vports + 1) %
eb66dc60 1539 MIN_MULTI_ID_FABRIC))
4d0ea247 1540 ha->max_npiv_vports =
eb66dc60 1541 MIN_MULTI_ID_FABRIC - 1;
4d0ea247 1542 }
24a08138
AV		 1543 qla2x00_get_resource_cnts(vha, NULL,
1544 &ha->fw_xcb_count, NULL, NULL,
f3a0a77e 1545 &ha->max_npiv_vports, NULL);
d743de66 1546
be5ea3cf
SK		 1547 if (!fw_major_version && ql2xallocfwdump
1548 && !IS_QLA82XX(ha))
08de2844 1549 qla2x00_alloc_fw_dump(vha);
1da177e4
LT		 1550 }
1551 } else {
7c3df132
SK		 1552 ql_log(ql_log_fatal, vha, 0x00cd,
1553 "ISP Firmware failed checksum.\n");
1554 goto failed;
1da177e4
LT		 1555 }
1556 }
1557
3db0652e
AV		 1558 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1559 /* Enable proper parity. */
1560 spin_lock_irqsave(&ha->hardware_lock, flags);
1561 if (IS_QLA2300(ha))
1562 /* SRAM parity */
1563 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x1);
1564 else
1565 /* SRAM, Instruction RAM and GP RAM parity */
1566 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x7);
1567 RD_REG_WORD(&reg->hccr);
1568 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1569 }
1570
6246b8a1
GM		 1571 if (IS_QLA83XX(ha))
1572 goto skip_fac_check;
1573
1d2874de
JC		 1574 if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
1575 uint32_t size;
1576
1577 rval = qla81xx_fac_get_sector_size(vha, &size);
1578 if (rval == QLA_SUCCESS) {
1579 ha->flags.fac_supported = 1;
1580 ha->fdt_block_size = size << 2;
1581 } else {
7c3df132 1582 ql_log(ql_log_warn, vha, 0x00ce,
1d2874de
JC		 1583 "Unsupported FAC firmware (%d.%02d.%02d).\n",
1584 ha->fw_major_version, ha->fw_minor_version,
1585 ha->fw_subminor_version);
6246b8a1
GM		 1586skip_fac_check:
1587 if (IS_QLA83XX(ha)) {
1588 ha->flags.fac_supported = 0;
1589 rval = QLA_SUCCESS;
1590 }
1d2874de
JC		 1591 }
1592 }
ca9e9c3e 1593failed:
1da177e4 1594 if (rval) {
7c3df132
SK		 1595 ql_log(ql_log_fatal, vha, 0x00cf,
1596 "Setup chip ****FAILED****.\n");
1da177e4
LT		 1597 }
1598
1599 return (rval);
1600}
1601
1602/**
1603 * qla2x00_init_response_q_entries() - Initializes response queue entries.
1604 * @ha: HA context
1605 *
1606 * Beginning of request ring has initialization control block already built
1607 * by nvram config routine.
1608 *
1609 * Returns 0 on success.
1610 */
73208dfd
AC		 1611void
1612qla2x00_init_response_q_entries(struct rsp_que *rsp)
1da177e4
LT		 1613{
1614 uint16_t cnt;
1615 response_t *pkt;
1616
2afa19a9
AC		 1617 rsp->ring_ptr = rsp->ring;
1618 rsp->ring_index = 0;
1619 rsp->status_srb = NULL;
e315cd28
AC		 1620 pkt = rsp->ring_ptr;
1621 for (cnt = 0; cnt < rsp->length; cnt++) {
1da177e4
LT		 1622 pkt->signature = RESPONSE_PROCESSED;
1623 pkt++;
1624 }
1da177e4
LT		 1625}
1626
1627/**
1628 * qla2x00_update_fw_options() - Read and process firmware options.
1629 * @ha: HA context
1630 *
1631 * Returns 0 on success.
1632 */
abbd8870 1633void
e315cd28 1634qla2x00_update_fw_options(scsi_qla_host_t *vha)
1da177e4
LT		 1635{
1636 uint16_t swing, emphasis, tx_sens, rx_sens;
e315cd28 1637 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 1638
1639 memset(ha->fw_options, 0, sizeof(ha->fw_options));
e315cd28 1640 qla2x00_get_fw_options(vha, ha->fw_options);
1da177e4
LT		 1641
1642 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1643 return;
1644
1645 /* Serial Link options. */
7c3df132
SK		 1646 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
1647 "Serial link options.\n");
1648 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
1649 (uint8_t *)&ha->fw_seriallink_options,
1650 sizeof(ha->fw_seriallink_options));
1da177e4
LT		 1651
1652 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1653 if (ha->fw_seriallink_options[3] & BIT_2) {
1654 ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING;
1655
1656 /* 1G settings */
1657 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
1658 emphasis = (ha->fw_seriallink_options[2] &
1659 (BIT_4 | BIT_3)) >> 3;
1660 tx_sens = ha->fw_seriallink_options[0] &
fa2a1ce5 1661 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 1662 rx_sens = (ha->fw_seriallink_options[0] &
1663 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
1664 ha->fw_options[10] = (emphasis << 14) | (swing << 8);
1665 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
1666 if (rx_sens == 0x0)
1667 rx_sens = 0x3;
1668 ha->fw_options[10] |= (tx_sens << 4) | rx_sens;
1669 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
1670 ha->fw_options[10] |= BIT_5 |
1671 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
1672 (tx_sens & (BIT_1 | BIT_0));
1673
1674 /* 2G settings */
1675 swing = (ha->fw_seriallink_options[2] &
1676 (BIT_7 | BIT_6 | BIT_5)) >> 5;
1677 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
1678 tx_sens = ha->fw_seriallink_options[1] &
fa2a1ce5 1679 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 1680 rx_sens = (ha->fw_seriallink_options[1] &
1681 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
1682 ha->fw_options[11] = (emphasis << 14) | (swing << 8);
1683 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
1684 if (rx_sens == 0x0)
1685 rx_sens = 0x3;
1686 ha->fw_options[11] |= (tx_sens << 4) | rx_sens;
1687 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
1688 ha->fw_options[11] |= BIT_5 |
1689 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
1690 (tx_sens & (BIT_1 | BIT_0));
1691 }
1692
1693 /* FCP2 options. */
1694 /* Return command IOCBs without waiting for an ABTS to complete. */
1695 ha->fw_options[3] |= BIT_13;
1696
1697 /* LED scheme. */
1698 if (ha->flags.enable_led_scheme)
1699 ha->fw_options[2] |= BIT_12;
1700
48c02fde
AV		 1701 /* Detect ISP6312. */
1702 if (IS_QLA6312(ha))
1703 ha->fw_options[2] |= BIT_13;
1704
1da177e4 1705 /* Update firmware options. */
e315cd28 1706 qla2x00_set_fw_options(vha, ha->fw_options);
1da177e4
LT		 1707}
1708
0107109e 1709void
e315cd28 1710qla24xx_update_fw_options(scsi_qla_host_t *vha)
0107109e
AV		 1711{
1712 int rval;
e315cd28 1713 struct qla_hw_data *ha = vha->hw;
0107109e 1714
a9083016
GM		 1715 if (IS_QLA82XX(ha))
1716 return;
1717
0107109e 1718 /* Update Serial Link options. */
f94097ed 1719 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0)
0107109e
AV		 1720 return;
1721
e315cd28 1722 rval = qla2x00_set_serdes_params(vha,
f94097ed
AV		 1723 le16_to_cpu(ha->fw_seriallink_options24[1]),
1724 le16_to_cpu(ha->fw_seriallink_options24[2]),
1725 le16_to_cpu(ha->fw_seriallink_options24[3]));
0107109e 1726 if (rval != QLA_SUCCESS) {
7c3df132 1727 ql_log(ql_log_warn, vha, 0x0104,
0107109e
AV		 1728 "Unable to update Serial Link options (%x).\n", rval);
1729 }
1730}
1731
abbd8870 1732void
e315cd28 1733qla2x00_config_rings(struct scsi_qla_host *vha)
abbd8870 1734{
e315cd28 1735 struct qla_hw_data *ha = vha->hw;
3d71644c 1736 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
73208dfd
AC		 1737 struct req_que *req = ha->req_q_map[0];
1738 struct rsp_que *rsp = ha->rsp_q_map[0];
abbd8870
AV		 1739
1740 /* Setup ring parameters in initialization control block. */
1741 ha->init_cb->request_q_outpointer = __constant_cpu_to_le16(0);
1742 ha->init_cb->response_q_inpointer = __constant_cpu_to_le16(0);
e315cd28
AC		 1743 ha->init_cb->request_q_length = cpu_to_le16(req->length);
1744 ha->init_cb->response_q_length = cpu_to_le16(rsp->length);
1745 ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
1746 ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
1747 ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
1748 ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
abbd8870
AV		 1749
1750 WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0);
1751 WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0);
1752 WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0);
1753 WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0);
1754 RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */
1755}
1756
0107109e 1757void
e315cd28 1758qla24xx_config_rings(struct scsi_qla_host *vha)
0107109e 1759{
e315cd28 1760 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 1761 device_reg_t __iomem *reg = ISP_QUE_REG(ha, 0);
1762 struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
1763 struct qla_msix_entry *msix;
0107109e 1764 struct init_cb_24xx *icb;
73208dfd
AC		 1765 uint16_t rid = 0;
1766 struct req_que *req = ha->req_q_map[0];
1767 struct rsp_que *rsp = ha->rsp_q_map[0];
0107109e 1768
6246b8a1 1769 /* Setup ring parameters in initialization control block. */
0107109e
AV		 1770 icb = (struct init_cb_24xx *)ha->init_cb;
1771 icb->request_q_outpointer = __constant_cpu_to_le16(0);
1772 icb->response_q_inpointer = __constant_cpu_to_le16(0);
e315cd28
AC		 1773 icb->request_q_length = cpu_to_le16(req->length);
1774 icb->response_q_length = cpu_to_le16(rsp->length);
1775 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
1776 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
1777 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
1778 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
0107109e 1779
2d70c103
NB		 1780 /* Setup ATIO queue dma pointers for target mode */
1781 icb->atio_q_inpointer = __constant_cpu_to_le16(0);
1782 icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length);
1783 icb->atio_q_address[0] = cpu_to_le32(LSD(ha->tgt.atio_dma));
1784 icb->atio_q_address[1] = cpu_to_le32(MSD(ha->tgt.atio_dma));
1785
6246b8a1 1786 if (ha->mqenable || IS_QLA83XX(ha)) {
73208dfd
AC		 1787 icb->qos = __constant_cpu_to_le16(QLA_DEFAULT_QUE_QOS);
1788 icb->rid = __constant_cpu_to_le16(rid);
1789 if (ha->flags.msix_enabled) {
1790 msix = &ha->msix_entries[1];
7c3df132
SK		 1791 ql_dbg(ql_dbg_init, vha, 0x00fd,
1792 "Registering vector 0x%x for base que.\n",
1793 msix->entry);
73208dfd
AC		 1794 icb->msix = cpu_to_le16(msix->entry);
1795 }
1796 /* Use alternate PCI bus number */
1797 if (MSB(rid))
1798 icb->firmware_options_2 |=
1799 __constant_cpu_to_le32(BIT_19);
1800 /* Use alternate PCI devfn */
1801 if (LSB(rid))
1802 icb->firmware_options_2 |=
1803 __constant_cpu_to_le32(BIT_18);
1804
3155754a 1805 /* Use Disable MSIX Handshake mode for capable adapters */
6246b8a1
GM		 1806 if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) &&
1807 (ha->flags.msix_enabled)) {
3155754a
AC		 1808 icb->firmware_options_2 &=
1809 __constant_cpu_to_le32(~BIT_22);
1810 ha->flags.disable_msix_handshake = 1;
7c3df132
SK		 1811 ql_dbg(ql_dbg_init, vha, 0x00fe,
1812 "MSIX Handshake Disable Mode turned on.\n");
3155754a
AC		 1813 } else {
1814 icb->firmware_options_2 |=
1815 __constant_cpu_to_le32(BIT_22);
1816 }
73208dfd 1817 icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_23);
73208dfd
AC		 1818
1819 WRT_REG_DWORD(&reg->isp25mq.req_q_in, 0);
1820 WRT_REG_DWORD(&reg->isp25mq.req_q_out, 0);
1821 WRT_REG_DWORD(&reg->isp25mq.rsp_q_in, 0);
1822 WRT_REG_DWORD(&reg->isp25mq.rsp_q_out, 0);
1823 } else {
1824 WRT_REG_DWORD(&reg->isp24.req_q_in, 0);
1825 WRT_REG_DWORD(&reg->isp24.req_q_out, 0);
1826 WRT_REG_DWORD(&reg->isp24.rsp_q_in, 0);
1827 WRT_REG_DWORD(&reg->isp24.rsp_q_out, 0);
1828 }
2d70c103
NB		 1829 qlt_24xx_config_rings(vha, reg);
1830
73208dfd
AC		 1831 /* PCI posting */
1832 RD_REG_DWORD(&ioreg->hccr);
0107109e
AV		 1833}
1834
1da177e4
LT		 1835/**
1836 * qla2x00_init_rings() - Initializes firmware.
1837 * @ha: HA context
1838 *
1839 * Beginning of request ring has initialization control block already built
1840 * by nvram config routine.
1841 *
1842 * Returns 0 on success.
1843 */
1844static int
e315cd28 1845qla2x00_init_rings(scsi_qla_host_t *vha)
1da177e4
LT		 1846{
1847 int rval;
1848 unsigned long flags = 0;
29bdccbe 1849 int cnt, que;
e315cd28 1850 struct qla_hw_data *ha = vha->hw;
29bdccbe
AC		 1851 struct req_que *req;
1852 struct rsp_que *rsp;
2c3dfe3f
SJ		 1853 struct mid_init_cb_24xx *mid_init_cb =
1854 (struct mid_init_cb_24xx *) ha->init_cb;
1da177e4
LT		 1855
1856 spin_lock_irqsave(&ha->hardware_lock, flags);
1857
1858 /* Clear outstanding commands array. */
2afa19a9 1859 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe
AC		 1860 req = ha->req_q_map[que];
1861 if (!req)
1862 continue;
2afa19a9 1863 for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++)
29bdccbe 1864 req->outstanding_cmds[cnt] = NULL;
1da177e4 1865
2afa19a9 1866 req->current_outstanding_cmd = 1;
1da177e4 1867
29bdccbe
AC		 1868 /* Initialize firmware. */
1869 req->ring_ptr = req->ring;
1870 req->ring_index = 0;
1871 req->cnt = req->length;
1872 }
1da177e4 1873
2afa19a9 1874 for (que = 0; que < ha->max_rsp_queues; que++) {
29bdccbe
AC		 1875 rsp = ha->rsp_q_map[que];
1876 if (!rsp)
1877 continue;
29bdccbe
AC		 1878 /* Initialize response queue entries */
1879 qla2x00_init_response_q_entries(rsp);
1880 }
1da177e4 1881
542bce1f 1882 spin_lock(&ha->vport_slock);
feafb7b1 1883
542bce1f 1884 spin_unlock(&ha->vport_slock);
feafb7b1 1885
2d70c103
NB		 1886 ha->tgt.atio_ring_ptr = ha->tgt.atio_ring;
1887 ha->tgt.atio_ring_index = 0;
1888 /* Initialize ATIO queue entries */
1889 qlt_init_atio_q_entries(vha);
1890
e315cd28 1891 ha->isp_ops->config_rings(vha);
1da177e4
LT		 1892
1893 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1894
1895 /* Update any ISP specific firmware options before initialization. */
e315cd28 1896 ha->isp_ops->update_fw_options(vha);
1da177e4 1897
7c3df132 1898 ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n");
2c3dfe3f 1899
605aa2bc
LC		 1900 if (ha->flags.npiv_supported) {
1901 if (ha->operating_mode == LOOP)
1902 ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
c48339de 1903 mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
605aa2bc
LC		 1904 }
1905
24a08138
AV		 1906 if (IS_FWI2_CAPABLE(ha)) {
1907 mid_init_cb->options = __constant_cpu_to_le16(BIT_1);
1908 mid_init_cb->init_cb.execution_throttle =
1909 cpu_to_le16(ha->fw_xcb_count);
1910 }
2c3dfe3f 1911
e315cd28 1912 rval = qla2x00_init_firmware(vha, ha->init_cb_size);
1da177e4 1913 if (rval) {
7c3df132
SK		 1914 ql_log(ql_log_fatal, vha, 0x00d2,
1915 "Init Firmware **** FAILED ****.\n");
1da177e4 1916 } else {
7c3df132
SK		 1917 ql_dbg(ql_dbg_init, vha, 0x00d3,
1918 "Init Firmware -- success.\n");
1da177e4
LT		 1919 }
1920
1921 return (rval);
1922}
1923
1924/**
1925 * qla2x00_fw_ready() - Waits for firmware ready.
1926 * @ha: HA context
1927 *
1928 * Returns 0 on success.
1929 */
1930static int
e315cd28 1931qla2x00_fw_ready(scsi_qla_host_t *vha)
1da177e4
LT		 1932{
1933 int rval;
4d4df193 1934 unsigned long wtime, mtime, cs84xx_time;
1da177e4
LT		 1935 uint16_t min_wait; /* Minimum wait time if loop is down */
1936 uint16_t wait_time; /* Wait time if loop is coming ready */
656e8912 1937 uint16_t state[5];
e315cd28 1938 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 1939
1940 rval = QLA_SUCCESS;
1941
1942 /* 20 seconds for loop down. */
fa2a1ce5 1943 min_wait = 20;
1da177e4
LT		 1944
1945 /*
1946 * Firmware should take at most one RATOV to login, plus 5 seconds for
1947 * our own processing.
1948 */
1949 if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) {
1950 wait_time = min_wait;
1951 }
1952
1953 /* Min wait time if loop down */
1954 mtime = jiffies + (min_wait * HZ);
1955
1956 /* wait time before firmware ready */
1957 wtime = jiffies + (wait_time * HZ);
1958
1959 /* Wait for ISP to finish LIP */
e315cd28 1960 if (!vha->flags.init_done)
7c3df132
SK		 1961 ql_log(ql_log_info, vha, 0x801e,
1962 "Waiting for LIP to complete.\n");
1da177e4
LT		 1963
1964 do {
e315cd28 1965 rval = qla2x00_get_firmware_state(vha, state);
1da177e4 1966 if (rval == QLA_SUCCESS) {
4d4df193 1967 if (state[0] < FSTATE_LOSS_OF_SYNC) {
e315cd28 1968 vha->device_flags &= ~DFLG_NO_CABLE;
1da177e4 1969 }
4d4df193 1970 if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) {
7c3df132
SK		 1971 ql_dbg(ql_dbg_taskm, vha, 0x801f,
1972 "fw_state=%x 84xx=%x.\n", state[0],
1973 state[2]);
4d4df193
HK		 1974 if ((state[2] & FSTATE_LOGGED_IN) &&
1975 (state[2] & FSTATE_WAITING_FOR_VERIFY)) {
7c3df132
SK		 1976 ql_dbg(ql_dbg_taskm, vha, 0x8028,
1977 "Sending verify iocb.\n");
4d4df193
HK		 1978
1979 cs84xx_time = jiffies;
e315cd28 1980 rval = qla84xx_init_chip(vha);
7c3df132
SK		 1981 if (rval != QLA_SUCCESS) {
1982 ql_log(ql_log_warn,
cfb0919c 1983 vha, 0x8007,
7c3df132 1984 "Init chip failed.\n");
4d4df193 1985 break;
7c3df132 1986 }
4d4df193
HK		 1987
1988 /* Add time taken to initialize. */
1989 cs84xx_time = jiffies - cs84xx_time;
1990 wtime += cs84xx_time;
1991 mtime += cs84xx_time;
cfb0919c 1992 ql_dbg(ql_dbg_taskm, vha, 0x8008,
7c3df132
SK		 1993 "Increasing wait time by %ld. "
1994 "New time %ld.\n", cs84xx_time,
1995 wtime);
4d4df193
HK		 1996 }
1997 } else if (state[0] == FSTATE_READY) {
7c3df132
SK		 1998 ql_dbg(ql_dbg_taskm, vha, 0x8037,
1999 "F/W Ready - OK.\n");
1da177e4 2000
e315cd28 2001 qla2x00_get_retry_cnt(vha, &ha->retry_count,
1da177e4
LT		 2002 &ha->login_timeout, &ha->r_a_tov);
2003
2004 rval = QLA_SUCCESS;
2005 break;
2006 }
2007
2008 rval = QLA_FUNCTION_FAILED;
2009
e315cd28 2010 if (atomic_read(&vha->loop_down_timer) &&
4d4df193 2011 state[0] != FSTATE_READY) {
1da177e4 2012 /* Loop down. Timeout on min_wait for states
fa2a1ce5
AV		 2013 * other than Wait for Login.
2014 */
1da177e4 2015 if (time_after_eq(jiffies, mtime)) {
7c3df132 2016 ql_log(ql_log_info, vha, 0x8038,
1da177e4
LT		 2017 "Cable is unplugged...\n");
2018
e315cd28 2019 vha->device_flags |= DFLG_NO_CABLE;
1da177e4
LT		 2020 break;
2021 }
2022 }
2023 } else {
2024 /* Mailbox cmd failed. Timeout on min_wait. */
cdbb0a4f 2025 if (time_after_eq(jiffies, mtime) ||
7190575f 2026 ha->flags.isp82xx_fw_hung)
1da177e4
LT		 2027 break;
2028 }
2029
2030 if (time_after_eq(jiffies, wtime))
2031 break;
2032
2033 /* Delay for a while */
2034 msleep(500);
1da177e4
LT		 2035 } while (1);
2036
7c3df132
SK		 2037 ql_dbg(ql_dbg_taskm, vha, 0x803a,
2038 "fw_state=%x (%x, %x, %x, %x) " "curr time=%lx.\n", state[0],
2039 state[1], state[2], state[3], state[4], jiffies);
1da177e4 2040
cfb0919c 2041 if (rval && !(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132
SK		 2042 ql_log(ql_log_warn, vha, 0x803b,
2043 "Firmware ready **** FAILED ****.\n");
1da177e4
LT		 2044 }
2045
2046 return (rval);
2047}
2048
2049/*
2050* qla2x00_configure_hba
2051* Setup adapter context.
2052*
2053* Input:
2054* ha = adapter state pointer.
2055*
2056* Returns:
2057* 0 = success
2058*
2059* Context:
2060* Kernel context.
2061*/
2062static int
e315cd28 2063qla2x00_configure_hba(scsi_qla_host_t *vha)
1da177e4
LT		 2064{
2065 int rval;
2066 uint16_t loop_id;
2067 uint16_t topo;
2c3dfe3f 2068 uint16_t sw_cap;
1da177e4
LT		 2069 uint8_t al_pa;
2070 uint8_t area;
2071 uint8_t domain;
2072 char connect_type[22];
e315cd28 2073 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2074
2075 /* Get host addresses. */
e315cd28 2076 rval = qla2x00_get_adapter_id(vha,
2c3dfe3f 2077 &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
1da177e4 2078 if (rval != QLA_SUCCESS) {
e315cd28 2079 if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
6246b8a1 2080 IS_CNA_CAPABLE(ha) ||
33135aa2 2081 (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
7c3df132
SK		 2082 ql_dbg(ql_dbg_disc, vha, 0x2008,
2083 "Loop is in a transition state.\n");
33135aa2 2084 } else {
7c3df132
SK		 2085 ql_log(ql_log_warn, vha, 0x2009,
2086 "Unable to get host loop ID.\n");
e315cd28 2087 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
33135aa2 2088 }
1da177e4
LT		 2089 return (rval);
2090 }
2091
2092 if (topo == 4) {
7c3df132
SK		 2093 ql_log(ql_log_info, vha, 0x200a,
2094 "Cannot get topology - retrying.\n");
1da177e4
LT		 2095 return (QLA_FUNCTION_FAILED);
2096 }
2097
e315cd28 2098 vha->loop_id = loop_id;
1da177e4
LT		 2099
2100 /* initialize */
2101 ha->min_external_loopid = SNS_FIRST_LOOP_ID;
2102 ha->operating_mode = LOOP;
2c3dfe3f 2103 ha->switch_cap = 0;
1da177e4
LT		 2104
2105 switch (topo) {
2106 case 0:
7c3df132 2107 ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n");
1da177e4
LT		 2108 ha->current_topology = ISP_CFG_NL;
2109 strcpy(connect_type, "(Loop)");
2110 break;
2111
2112 case 1:
7c3df132 2113 ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n");
2c3dfe3f 2114 ha->switch_cap = sw_cap;
1da177e4
LT		 2115 ha->current_topology = ISP_CFG_FL;
2116 strcpy(connect_type, "(FL_Port)");
2117 break;
2118
2119 case 2:
7c3df132 2120 ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n");
1da177e4
LT		 2121 ha->operating_mode = P2P;
2122 ha->current_topology = ISP_CFG_N;
2123 strcpy(connect_type, "(N_Port-to-N_Port)");
2124 break;
2125
2126 case 3:
7c3df132 2127 ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n");
2c3dfe3f 2128 ha->switch_cap = sw_cap;
1da177e4
LT		 2129 ha->operating_mode = P2P;
2130 ha->current_topology = ISP_CFG_F;
2131 strcpy(connect_type, "(F_Port)");
2132 break;
2133
2134 default:
7c3df132
SK		 2135 ql_dbg(ql_dbg_disc, vha, 0x200f,
2136 "HBA in unknown topology %x, using NL.\n", topo);
1da177e4
LT		 2137 ha->current_topology = ISP_CFG_NL;
2138 strcpy(connect_type, "(Loop)");
2139 break;
2140 }
2141
2142 /* Save Host port and loop ID. */
2143 /* byte order - Big Endian */
e315cd28
AC		 2144 vha->d_id.b.domain = domain;
2145 vha->d_id.b.area = area;
2146 vha->d_id.b.al_pa = al_pa;
1da177e4 2147
2d70c103
NB		 2148 spin_lock(&ha->vport_slock);
2149 qlt_update_vp_map(vha, SET_AL_PA);
2150 spin_unlock(&ha->vport_slock);
2151
e315cd28 2152 if (!vha->flags.init_done)
7c3df132
SK		 2153 ql_log(ql_log_info, vha, 0x2010,
2154 "Topology - %s, Host Loop address 0x%x.\n",
e315cd28 2155 connect_type, vha->loop_id);
1da177e4
LT		 2156
2157 if (rval) {
7c3df132
SK		 2158 ql_log(ql_log_warn, vha, 0x2011,
2159 "%s FAILED\n", __func__);
1da177e4 2160 } else {
7c3df132
SK		 2161 ql_dbg(ql_dbg_disc, vha, 0x2012,
2162 "%s success\n", __func__);
1da177e4
LT		 2163 }
2164
2165 return(rval);
2166}
2167
a9083016 2168inline void
e315cd28
AC		 2169qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
2170 char *def)
9bb9fcf2
AV		 2171{
2172 char *st, *en;
2173 uint16_t index;
e315cd28 2174 struct qla_hw_data *ha = vha->hw;
ab671149 2175 int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
6246b8a1 2176 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha);
9bb9fcf2
AV		 2177
2178 if (memcmp(model, BINZERO, len) != 0) {
2179 strncpy(ha->model_number, model, len);
2180 st = en = ha->model_number;
2181 en += len - 1;
2182 while (en > st) {
2183 if (*en != 0x20 && *en != 0x00)
2184 break;
2185 *en-- = '\0';
2186 }
2187
2188 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 2189 if (use_tbl &&
2190 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2 2191 index < QLA_MODEL_NAMES)
1ee27146
JC		 2192 strncpy(ha->model_desc,
2193 qla2x00_model_name[index * 2 + 1],
2194 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 2195 } else {
2196 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 2197 if (use_tbl &&
2198 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2
AV		 2199 index < QLA_MODEL_NAMES) {
2200 strcpy(ha->model_number,
2201 qla2x00_model_name[index * 2]);
1ee27146
JC		 2202 strncpy(ha->model_desc,
2203 qla2x00_model_name[index * 2 + 1],
2204 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 2205 } else {
2206 strcpy(ha->model_number, def);
2207 }
2208 }
1ee27146 2209 if (IS_FWI2_CAPABLE(ha))
e315cd28 2210 qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc,
1ee27146 2211 sizeof(ha->model_desc));
9bb9fcf2
AV		 2212}
2213
4e08df3f
DM		 2214/* On sparc systems, obtain port and node WWN from firmware
2215 * properties.
2216 */
e315cd28 2217static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv)
4e08df3f
DM		 2218{
2219#ifdef CONFIG_SPARC
e315cd28 2220 struct qla_hw_data *ha = vha->hw;
4e08df3f 2221 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 2222 struct device_node *dp = pci_device_to_OF_node(pdev);
2223 const u8 *val;
4e08df3f
DM		 2224 int len;
2225
2226 val = of_get_property(dp, "port-wwn", &len);
2227 if (val && len >= WWN_SIZE)
2228 memcpy(nv->port_name, val, WWN_SIZE);
2229
2230 val = of_get_property(dp, "node-wwn", &len);
2231 if (val && len >= WWN_SIZE)
2232 memcpy(nv->node_name, val, WWN_SIZE);
2233#endif
2234}
2235
1da177e4
LT		 2236/*
2237* NVRAM configuration for ISP 2xxx
2238*
2239* Input:
2240* ha = adapter block pointer.
2241*
2242* Output:
2243* initialization control block in response_ring
2244* host adapters parameters in host adapter block
2245*
2246* Returns:
2247* 0 = success.
2248*/
abbd8870 2249int
e315cd28 2250qla2x00_nvram_config(scsi_qla_host_t *vha)
1da177e4 2251{
4e08df3f 2252 int rval;
0107109e
AV		 2253 uint8_t chksum = 0;
2254 uint16_t cnt;
2255 uint8_t *dptr1, *dptr2;
e315cd28 2256 struct qla_hw_data *ha = vha->hw;
0107109e 2257 init_cb_t *icb = ha->init_cb;
281afe19
SJ		 2258 nvram_t *nv = ha->nvram;
2259 uint8_t *ptr = ha->nvram;
3d71644c 2260 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 2261
4e08df3f
DM		 2262 rval = QLA_SUCCESS;
2263
1da177e4 2264 /* Determine NVRAM starting address. */
0107109e 2265 ha->nvram_size = sizeof(nvram_t);
1da177e4
LT		 2266 ha->nvram_base = 0;
2267 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
2268 if ((RD_REG_WORD(&reg->ctrl_status) >> 14) == 1)
2269 ha->nvram_base = 0x80;
2270
2271 /* Get NVRAM data and calculate checksum. */
e315cd28 2272 ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size);
0107109e
AV		 2273 for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++)
2274 chksum += *ptr++;
1da177e4 2275
7c3df132
SK		 2276 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
2277 "Contents of NVRAM.\n");
2278 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
2279 (uint8_t *)nv, ha->nvram_size);
1da177e4
LT		 2280
2281 /* Bad NVRAM data, set defaults parameters. */
2282 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' ||
2283 nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) {
2284 /* Reset NVRAM data. */
7c3df132 2285 ql_log(ql_log_warn, vha, 0x0064,
9e336520 2286 "Inconsistent NVRAM "
7c3df132
SK		 2287 "detected: checksum=0x%x id=%c version=0x%x.\n",
2288 chksum, nv->id[0], nv->nvram_version);
2289 ql_log(ql_log_warn, vha, 0x0065,
2290 "Falling back to "
2291 "functioning (yet invalid -- WWPN) defaults.\n");
4e08df3f
DM		 2292
2293 /*
2294 * Set default initialization control block.
2295 */
2296 memset(nv, 0, ha->nvram_size);
2297 nv->parameter_block_version = ICB_VERSION;
2298
2299 if (IS_QLA23XX(ha)) {
2300 nv->firmware_options[0] = BIT_2 | BIT_1;
2301 nv->firmware_options[1] = BIT_7 | BIT_5;
2302 nv->add_firmware_options[0] = BIT_5;
2303 nv->add_firmware_options[1] = BIT_5 | BIT_4;
2304 nv->frame_payload_size = __constant_cpu_to_le16(2048);
2305 nv->special_options[1] = BIT_7;
2306 } else if (IS_QLA2200(ha)) {
2307 nv->firmware_options[0] = BIT_2 | BIT_1;
2308 nv->firmware_options[1] = BIT_7 | BIT_5;
2309 nv->add_firmware_options[0] = BIT_5;
2310 nv->add_firmware_options[1] = BIT_5 | BIT_4;
2311 nv->frame_payload_size = __constant_cpu_to_le16(1024);
2312 } else if (IS_QLA2100(ha)) {
2313 nv->firmware_options[0] = BIT_3 | BIT_1;
2314 nv->firmware_options[1] = BIT_5;
2315 nv->frame_payload_size = __constant_cpu_to_le16(1024);
2316 }
2317
2318 nv->max_iocb_allocation = __constant_cpu_to_le16(256);
2319 nv->execution_throttle = __constant_cpu_to_le16(16);
2320 nv->retry_count = 8;
2321 nv->retry_delay = 1;
2322
2323 nv->port_name[0] = 33;
2324 nv->port_name[3] = 224;
2325 nv->port_name[4] = 139;
2326
e315cd28 2327 qla2xxx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 2328
2329 nv->login_timeout = 4;
2330
2331 /*
2332 * Set default host adapter parameters
2333 */
2334 nv->host_p[1] = BIT_2;
2335 nv->reset_delay = 5;
2336 nv->port_down_retry_count = 8;
2337 nv->max_luns_per_target = __constant_cpu_to_le16(8);
2338 nv->link_down_timeout = 60;
2339
2340 rval = 1;
1da177e4
LT		 2341 }
2342
2343#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
2344 /*
2345 * The SN2 does not provide BIOS emulation which means you can't change
2346 * potentially bogus BIOS settings. Force the use of default settings
2347 * for link rate and frame size. Hope that the rest of the settings
2348 * are valid.
2349 */
2350 if (ia64_platform_is("sn2")) {
2351 nv->frame_payload_size = __constant_cpu_to_le16(2048);
2352 if (IS_QLA23XX(ha))
2353 nv->special_options[1] = BIT_7;
2354 }
2355#endif
2356
2357 /* Reset Initialization control block */
0107109e 2358 memset(icb, 0, ha->init_cb_size);
1da177e4
LT		 2359
2360 /*
2361 * Setup driver NVRAM options.
2362 */
2363 nv->firmware_options[0] |= (BIT_6 | BIT_1);
2364 nv->firmware_options[0] &= ~(BIT_5 | BIT_4);
2365 nv->firmware_options[1] |= (BIT_5 | BIT_0);
2366 nv->firmware_options[1] &= ~BIT_4;
2367
2368 if (IS_QLA23XX(ha)) {
2369 nv->firmware_options[0] |= BIT_2;
2370 nv->firmware_options[0] &= ~BIT_3;
2d70c103 2371 nv->special_options[0] &= ~BIT_6;
0107109e 2372 nv->add_firmware_options[1] |= BIT_5 | BIT_4;
1da177e4
LT		 2373
2374 if (IS_QLA2300(ha)) {
2375 if (ha->fb_rev == FPM_2310) {
2376 strcpy(ha->model_number, "QLA2310");
2377 } else {
2378 strcpy(ha->model_number, "QLA2300");
2379 }
2380 } else {
e315cd28 2381 qla2x00_set_model_info(vha, nv->model_number,
9bb9fcf2 2382 sizeof(nv->model_number), "QLA23xx");
1da177e4
LT		 2383 }
2384 } else if (IS_QLA2200(ha)) {
2385 nv->firmware_options[0] |= BIT_2;
2386 /*
2387 * 'Point-to-point preferred, else loop' is not a safe
2388 * connection mode setting.
2389 */
2390 if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
2391 (BIT_5 | BIT_4)) {
2392 /* Force 'loop preferred, else point-to-point'. */
2393 nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
2394 nv->add_firmware_options[0] |= BIT_5;
2395 }
2396 strcpy(ha->model_number, "QLA22xx");
2397 } else /*if (IS_QLA2100(ha))*/ {
2398 strcpy(ha->model_number, "QLA2100");
2399 }
2400
2401 /*
2402 * Copy over NVRAM RISC parameter block to initialization control block.
2403 */
2404 dptr1 = (uint8_t *)icb;
2405 dptr2 = (uint8_t *)&nv->parameter_block_version;
2406 cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;
2407 while (cnt--)
2408 *dptr1++ = *dptr2++;
2409
2410 /* Copy 2nd half. */
2411 dptr1 = (uint8_t *)icb->add_firmware_options;
2412 cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;
2413 while (cnt--)
2414 *dptr1++ = *dptr2++;
2415
5341e868
AV		 2416 /* Use alternate WWN? */
2417 if (nv->host_p[1] & BIT_7) {
2418 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
2419 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
2420 }
2421
1da177e4
LT		 2422 /* Prepare nodename */
2423 if ((icb->firmware_options[1] & BIT_6) == 0) {
2424 /*
2425 * Firmware will apply the following mask if the nodename was
2426 * not provided.
2427 */
2428 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
2429 icb->node_name[0] &= 0xF0;
2430 }
2431
2432 /*
2433 * Set host adapter parameters.
2434 */
3ce8866c
SK		 2435
2436 /*
2437 * BIT_7 in the host-parameters section allows for modification to
2438 * internal driver logging.
2439 */
0181944f 2440 if (nv->host_p[0] & BIT_7)
cfb0919c 2441 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
1da177e4
LT		 2442 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
2443 /* Always load RISC code on non ISP2[12]00 chips. */
2444 if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
2445 ha->flags.disable_risc_code_load = 0;
2446 ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0);
2447 ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
2448 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
06c22bd1 2449 ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
d4c760c2 2450 ha->flags.disable_serdes = 0;
1da177e4
LT		 2451
2452 ha->operating_mode =
2453 (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
2454
2455 memcpy(ha->fw_seriallink_options, nv->seriallink_options,
2456 sizeof(ha->fw_seriallink_options));
2457
2458 /* save HBA serial number */
2459 ha->serial0 = icb->port_name[5];
2460 ha->serial1 = icb->port_name[6];
2461 ha->serial2 = icb->port_name[7];
e315cd28
AC		 2462 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
2463 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
1da177e4
LT		 2464
2465 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
2466
2467 ha->retry_count = nv->retry_count;
2468
2469 /* Set minimum login_timeout to 4 seconds. */
5b91490e 2470 if (nv->login_timeout != ql2xlogintimeout)
1da177e4
LT		 2471 nv->login_timeout = ql2xlogintimeout;
2472 if (nv->login_timeout < 4)
2473 nv->login_timeout = 4;
2474 ha->login_timeout = nv->login_timeout;
2475 icb->login_timeout = nv->login_timeout;
2476
00a537b8
AV		 2477 /* Set minimum RATOV to 100 tenths of a second. */
2478 ha->r_a_tov = 100;
1da177e4 2479
1da177e4
LT		 2480 ha->loop_reset_delay = nv->reset_delay;
2481
1da177e4
LT		 2482 /* Link Down Timeout = 0:
2483 *
2484 * When Port Down timer expires we will start returning
2485 * I/O's to OS with "DID_NO_CONNECT".
2486 *
2487 * Link Down Timeout != 0:
2488 *
2489 * The driver waits for the link to come up after link down
2490 * before returning I/Os to OS with "DID_NO_CONNECT".
fa2a1ce5 2491 */
1da177e4
LT		 2492 if (nv->link_down_timeout == 0) {
2493 ha->loop_down_abort_time =
354d6b21 2494 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
1da177e4
LT		 2495 } else {
2496 ha->link_down_timeout = nv->link_down_timeout;
2497 ha->loop_down_abort_time =
2498 (LOOP_DOWN_TIME - ha->link_down_timeout);
fa2a1ce5 2499 }
1da177e4 2500
1da177e4
LT		 2501 /*
2502 * Need enough time to try and get the port back.
2503 */
2504 ha->port_down_retry_count = nv->port_down_retry_count;
2505 if (qlport_down_retry)
2506 ha->port_down_retry_count = qlport_down_retry;
2507 /* Set login_retry_count */
2508 ha->login_retry_count = nv->retry_count;
2509 if (ha->port_down_retry_count == nv->port_down_retry_count &&
2510 ha->port_down_retry_count > 3)
2511 ha->login_retry_count = ha->port_down_retry_count;
2512 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
2513 ha->login_retry_count = ha->port_down_retry_count;
2514 if (ql2xloginretrycount)
2515 ha->login_retry_count = ql2xloginretrycount;
2516
1da177e4
LT		 2517 icb->lun_enables = __constant_cpu_to_le16(0);
2518 icb->command_resource_count = 0;
2519 icb->immediate_notify_resource_count = 0;
2520 icb->timeout = __constant_cpu_to_le16(0);
2521
2522 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
2523 /* Enable RIO */
2524 icb->firmware_options[0] &= ~BIT_3;
2525 icb->add_firmware_options[0] &=
2526 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
2527 icb->add_firmware_options[0] |= BIT_2;
2528 icb->response_accumulation_timer = 3;
2529 icb->interrupt_delay_timer = 5;
2530
e315cd28 2531 vha->flags.process_response_queue = 1;
1da177e4 2532 } else {
4fdfefe5 2533 /* Enable ZIO. */
e315cd28 2534 if (!vha->flags.init_done) {
4fdfefe5
AV		 2535 ha->zio_mode = icb->add_firmware_options[0] &
2536 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
2537 ha->zio_timer = icb->interrupt_delay_timer ?
2538 icb->interrupt_delay_timer: 2;
2539 }
1da177e4
LT		 2540 icb->add_firmware_options[0] &=
2541 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
e315cd28 2542 vha->flags.process_response_queue = 0;
4fdfefe5 2543 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d
AV		 2544 ha->zio_mode = QLA_ZIO_MODE_6;
2545
7c3df132 2546 ql_log(ql_log_info, vha, 0x0068,
4fdfefe5
AV		 2547 "ZIO mode %d enabled; timer delay (%d us).\n",
2548 ha->zio_mode, ha->zio_timer * 100);
1da177e4 2549
4fdfefe5
AV		 2550 icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;
2551 icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;
e315cd28 2552 vha->flags.process_response_queue = 1;
1da177e4
LT		 2553 }
2554 }
2555
4e08df3f 2556 if (rval) {
7c3df132
SK		 2557 ql_log(ql_log_warn, vha, 0x0069,
2558 "NVRAM configuration failed.\n");
4e08df3f
DM		 2559 }
2560 return (rval);
1da177e4
LT		 2561}
2562
19a7b4ae
JSEC		 2563static void
2564qla2x00_rport_del(void *data)
2565{
2566 fc_port_t *fcport = data;
d97994dc 2567 struct fc_rport *rport;
2d70c103 2568 scsi_qla_host_t *vha = fcport->vha;
044d78e1 2569 unsigned long flags;
d97994dc 2570
044d78e1 2571 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
ac280b67 2572 rport = fcport->drport ? fcport->drport: fcport->rport;
d97994dc 2573 fcport->drport = NULL;
044d78e1 2574 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
2d70c103 2575 if (rport) {
d97994dc 2576 fc_remote_port_delete(rport);
2d70c103
NB		 2577 /*
2578 * Release the target mode FC NEXUS in qla_target.c code
2579 * if target mod is enabled.
2580 */
2581 qlt_fc_port_deleted(vha, fcport);
2582 }
19a7b4ae
JSEC		 2583}
2584
1da177e4
LT		 2585/**
2586 * qla2x00_alloc_fcport() - Allocate a generic fcport.
2587 * @ha: HA context
2588 * @flags: allocation flags
2589 *
2590 * Returns a pointer to the allocated fcport, or NULL, if none available.
2591 */
9a069e19 2592fc_port_t *
e315cd28 2593qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags)
1da177e4
LT		 2594{
2595 fc_port_t *fcport;
2596
bbfbbbc1
MK		 2597 fcport = kzalloc(sizeof(fc_port_t), flags);
2598 if (!fcport)
2599 return NULL;
1da177e4
LT		 2600
2601 /* Setup fcport template structure. */
e315cd28 2602 fcport->vha = vha;
1da177e4
LT		 2603 fcport->port_type = FCT_UNKNOWN;
2604 fcport->loop_id = FC_NO_LOOP_ID;
ec426e10 2605 qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
ad3e0eda 2606 fcport->supported_classes = FC_COS_UNSPECIFIED;
c0822b63 2607 fcport->scan_state = QLA_FCPORT_SCAN_NONE;
1da177e4 2608
bbfbbbc1 2609 return fcport;
1da177e4
LT		 2610}
2611
2612/*
2613 * qla2x00_configure_loop
2614 * Updates Fibre Channel Device Database with what is actually on loop.
2615 *
2616 * Input:
2617 * ha = adapter block pointer.
2618 *
2619 * Returns:
2620 * 0 = success.
2621 * 1 = error.
2622 * 2 = database was full and device was not configured.
2623 */
2624static int
e315cd28 2625qla2x00_configure_loop(scsi_qla_host_t *vha)
1da177e4
LT		 2626{
2627 int rval;
2628 unsigned long flags, save_flags;
e315cd28 2629 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2630 rval = QLA_SUCCESS;
2631
2632 /* Get Initiator ID */
e315cd28
AC		 2633 if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) {
2634 rval = qla2x00_configure_hba(vha);
1da177e4 2635 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2636 ql_dbg(ql_dbg_disc, vha, 0x2013,
2637 "Unable to configure HBA.\n");
1da177e4
LT		 2638 return (rval);
2639 }
2640 }
2641
e315cd28 2642 save_flags = flags = vha->dpc_flags;
7c3df132
SK		 2643 ql_dbg(ql_dbg_disc, vha, 0x2014,
2644 "Configure loop -- dpc flags = 0x%lx.\n", flags);
1da177e4
LT		 2645
2646 /*
2647 * If we have both an RSCN and PORT UPDATE pending then handle them
2648 * both at the same time.
2649 */
e315cd28
AC		 2650 clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2651 clear_bit(RSCN_UPDATE, &vha->dpc_flags);
1da177e4 2652
3064ff39
MH		 2653 qla2x00_get_data_rate(vha);
2654
1da177e4
LT		 2655 /* Determine what we need to do */
2656 if (ha->current_topology == ISP_CFG_FL &&
2657 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
2658
1da177e4
LT		 2659 set_bit(RSCN_UPDATE, &flags);
2660
2661 } else if (ha->current_topology == ISP_CFG_F &&
2662 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
2663
1da177e4
LT		 2664 set_bit(RSCN_UPDATE, &flags);
2665 clear_bit(LOCAL_LOOP_UPDATE, &flags);
21333b48
AV		 2666
2667 } else if (ha->current_topology == ISP_CFG_N) {
2668 clear_bit(RSCN_UPDATE, &flags);
1da177e4 2669
e315cd28 2670 } else if (!vha->flags.online ||
1da177e4
LT		 2671 (test_bit(ABORT_ISP_ACTIVE, &flags))) {
2672
1da177e4
LT		 2673 set_bit(RSCN_UPDATE, &flags);
2674 set_bit(LOCAL_LOOP_UPDATE, &flags);
2675 }
2676
2677 if (test_bit(LOCAL_LOOP_UPDATE, &flags)) {
7c3df132
SK		 2678 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
2679 ql_dbg(ql_dbg_disc, vha, 0x2015,
2680 "Loop resync needed, failing.\n");
1da177e4 2681 rval = QLA_FUNCTION_FAILED;
642ef983 2682 } else
e315cd28 2683 rval = qla2x00_configure_local_loop(vha);
1da177e4
LT		 2684 }
2685
2686 if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
7c3df132
SK		 2687 if (LOOP_TRANSITION(vha)) {
2688 ql_dbg(ql_dbg_disc, vha, 0x201e,
2689 "Needs RSCN update and loop transition.\n");
1da177e4 2690 rval = QLA_FUNCTION_FAILED;
7c3df132 2691 }
e315cd28
AC		 2692 else
2693 rval = qla2x00_configure_fabric(vha);
1da177e4
LT		 2694 }
2695
2696 if (rval == QLA_SUCCESS) {
e315cd28
AC		 2697 if (atomic_read(&vha->loop_down_timer) ||
2698 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4
LT		 2699 rval = QLA_FUNCTION_FAILED;
2700 } else {
e315cd28 2701 atomic_set(&vha->loop_state, LOOP_READY);
7c3df132
SK		 2702 ql_dbg(ql_dbg_disc, vha, 0x2069,
2703 "LOOP READY.\n");
1da177e4
LT		 2704 }
2705 }
2706
2707 if (rval) {
7c3df132
SK		 2708 ql_dbg(ql_dbg_disc, vha, 0x206a,
2709 "%s *** FAILED ***.\n", __func__);
1da177e4 2710 } else {
7c3df132
SK		 2711 ql_dbg(ql_dbg_disc, vha, 0x206b,
2712 "%s: exiting normally.\n", __func__);
1da177e4
LT		 2713 }
2714
cc3ef7bc 2715 /* Restore state if a resync event occurred during processing */
e315cd28 2716 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4 2717 if (test_bit(LOCAL_LOOP_UPDATE, &save_flags))
e315cd28 2718 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
f4658b6c 2719 if (test_bit(RSCN_UPDATE, &save_flags)) {
e315cd28 2720 set_bit(RSCN_UPDATE, &vha->dpc_flags);
f4658b6c 2721 }
1da177e4
LT		 2722 }
2723
2724 return (rval);
2725}
2726
2727
2728
2729/*
2730 * qla2x00_configure_local_loop
2731 * Updates Fibre Channel Device Database with local loop devices.
2732 *
2733 * Input:
2734 * ha = adapter block pointer.
2735 *
2736 * Returns:
2737 * 0 = success.
2738 */
2739static int
e315cd28 2740qla2x00_configure_local_loop(scsi_qla_host_t *vha)
1da177e4
LT		 2741{
2742 int rval, rval2;
2743 int found_devs;
2744 int found;
2745 fc_port_t *fcport, *new_fcport;
2746
2747 uint16_t index;
2748 uint16_t entries;
2749 char *id_iter;
2750 uint16_t loop_id;
2751 uint8_t domain, area, al_pa;
e315cd28 2752 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2753
2754 found_devs = 0;
2755 new_fcport = NULL;
642ef983 2756 entries = MAX_FIBRE_DEVICES_LOOP;
1da177e4 2757
7c3df132
SK		 2758 ql_dbg(ql_dbg_disc, vha, 0x2016,
2759 "Getting FCAL position map.\n");
2760 if (ql2xextended_error_logging & ql_dbg_disc)
2761 qla2x00_get_fcal_position_map(vha, NULL);
1da177e4
LT		 2762
2763 /* Get list of logged in devices. */
642ef983 2764 memset(ha->gid_list, 0, qla2x00_gid_list_size(ha));
e315cd28 2765 rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma,
1da177e4
LT		 2766 &entries);
2767 if (rval != QLA_SUCCESS)
2768 goto cleanup_allocation;
2769
7c3df132
SK		 2770 ql_dbg(ql_dbg_disc, vha, 0x2017,
2771 "Entries in ID list (%d).\n", entries);
2772 ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
2773 (uint8_t *)ha->gid_list,
2774 entries * sizeof(struct gid_list_info));
1da177e4
LT		 2775
2776 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 2777 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 2778 if (new_fcport == NULL) {
7c3df132
SK		 2779 ql_log(ql_log_warn, vha, 0x2018,
2780 "Memory allocation failed for fcport.\n");
1da177e4
LT		 2781 rval = QLA_MEMORY_ALLOC_FAILED;
2782 goto cleanup_allocation;
2783 }
2784 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
2785
2786 /*
2787 * Mark local devices that were present with FCF_DEVICE_LOST for now.
2788 */
e315cd28 2789 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 2790 if (atomic_read(&fcport->state) == FCS_ONLINE &&
2791 fcport->port_type != FCT_BROADCAST &&
2792 (fcport->flags & FCF_FABRIC_DEVICE) == 0) {
2793
7c3df132
SK		 2794 ql_dbg(ql_dbg_disc, vha, 0x2019,
2795 "Marking port lost loop_id=0x%04x.\n",
2796 fcport->loop_id);
1da177e4 2797
ec426e10 2798 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 2799 }
2800 }
2801
2802 /* Add devices to port list. */
2803 id_iter = (char *)ha->gid_list;
2804 for (index = 0; index < entries; index++) {
2805 domain = ((struct gid_list_info *)id_iter)->domain;
2806 area = ((struct gid_list_info *)id_iter)->area;
2807 al_pa = ((struct gid_list_info *)id_iter)->al_pa;
abbd8870 2808 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1da177e4
LT		 2809 loop_id = (uint16_t)
2810 ((struct gid_list_info *)id_iter)->loop_id_2100;
abbd8870 2811 else
1da177e4
LT		 2812 loop_id = le16_to_cpu(
2813 ((struct gid_list_info *)id_iter)->loop_id);
abbd8870 2814 id_iter += ha->gid_list_info_size;
1da177e4
LT		 2815
2816 /* Bypass reserved domain fields. */
2817 if ((domain & 0xf0) == 0xf0)
2818 continue;
2819
2820 /* Bypass if not same domain and area of adapter. */
f7d289f6 2821 if (area && domain &&
e315cd28 2822 (area != vha->d_id.b.area || domain != vha->d_id.b.domain))
1da177e4
LT		 2823 continue;
2824
2825 /* Bypass invalid local loop ID. */
2826 if (loop_id > LAST_LOCAL_LOOP_ID)
2827 continue;
2828
2829 /* Fill in member data. */
2830 new_fcport->d_id.b.domain = domain;
2831 new_fcport->d_id.b.area = area;
2832 new_fcport->d_id.b.al_pa = al_pa;
2833 new_fcport->loop_id = loop_id;
e315cd28 2834 rval2 = qla2x00_get_port_database(vha, new_fcport, 0);
1da177e4 2835 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 2836 ql_dbg(ql_dbg_disc, vha, 0x201a,
2837 "Failed to retrieve fcport information "
2838 "-- get_port_database=%x, loop_id=0x%04x.\n",
2839 rval2, new_fcport->loop_id);
2840 ql_dbg(ql_dbg_disc, vha, 0x201b,
2841 "Scheduling resync.\n");
e315cd28 2842 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4
LT		 2843 continue;
2844 }
2845
2846 /* Check for matching device in port list. */
2847 found = 0;
2848 fcport = NULL;
e315cd28 2849 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 2850 if (memcmp(new_fcport->port_name, fcport->port_name,
2851 WWN_SIZE))
2852 continue;
2853
ddb9b126 2854 fcport->flags &= ~FCF_FABRIC_DEVICE;
1da177e4
LT		 2855 fcport->loop_id = new_fcport->loop_id;
2856 fcport->port_type = new_fcport->port_type;
2857 fcport->d_id.b24 = new_fcport->d_id.b24;
2858 memcpy(fcport->node_name, new_fcport->node_name,
2859 WWN_SIZE);
2860
2861 found++;
2862 break;
2863 }
2864
2865 if (!found) {
2866 /* New device, add to fcports list. */
e315cd28 2867 list_add_tail(&new_fcport->list, &vha->vp_fcports);
1da177e4
LT		 2868
2869 /* Allocate a new replacement fcport. */
2870 fcport = new_fcport;
e315cd28 2871 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 2872 if (new_fcport == NULL) {
7c3df132
SK		 2873 ql_log(ql_log_warn, vha, 0x201c,
2874 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 2875 rval = QLA_MEMORY_ALLOC_FAILED;
2876 goto cleanup_allocation;
2877 }
2878 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
2879 }
2880
d8b45213 2881 /* Base iIDMA settings on HBA port speed. */
a3cbdfad 2882 fcport->fp_speed = ha->link_data_rate;
d8b45213 2883
e315cd28 2884 qla2x00_update_fcport(vha, fcport);
1da177e4
LT		 2885
2886 found_devs++;
2887 }
2888
2889cleanup_allocation:
c9475cb0 2890 kfree(new_fcport);
1da177e4
LT		 2891
2892 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2893 ql_dbg(ql_dbg_disc, vha, 0x201d,
2894 "Configure local loop error exit: rval=%x.\n", rval);
1da177e4
LT		 2895 }
2896
1da177e4
LT		 2897 return (rval);
2898}
2899
d8b45213 2900static void
e315cd28 2901qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
d8b45213 2902{
9f8fddee 2903 char *link_speed;
d8b45213 2904 int rval;
1bb39548 2905 uint16_t mb[4];
e315cd28 2906 struct qla_hw_data *ha = vha->hw;
d8b45213 2907
c76f2c01 2908 if (!IS_IIDMA_CAPABLE(ha))
d8b45213
AV		 2909 return;
2910
c9afb9a2
GM		 2911 if (atomic_read(&fcport->state) != FCS_ONLINE)
2912 return;
2913
39bd9622
AV		 2914 if (fcport->fp_speed == PORT_SPEED_UNKNOWN ||
2915 fcport->fp_speed > ha->link_data_rate)
d8b45213
AV		 2916 return;
2917
e315cd28 2918 rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed,
a3cbdfad 2919 mb);
d8b45213 2920 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2921 ql_dbg(ql_dbg_disc, vha, 0x2004,
2922 "Unable to adjust iIDMA "
2923 "%02x%02x%02x%02x%02x%02x%02x%02x -- %04x %x %04x "
2924 "%04x.\n", fcport->port_name[0], fcport->port_name[1],
d8b45213
AV		 2925 fcport->port_name[2], fcport->port_name[3],
2926 fcport->port_name[4], fcport->port_name[5],
2927 fcport->port_name[6], fcport->port_name[7], rval,
7c3df132 2928 fcport->fp_speed, mb[0], mb[1]);
d8b45213 2929 } else {
daae62a3 2930 link_speed = qla2x00_get_link_speed_str(ha);
7c3df132
SK		 2931 ql_dbg(ql_dbg_disc, vha, 0x2005,
2932 "iIDMA adjusted to %s GB/s "
2933 "on %02x%02x%02x%02x%02x%02x%02x%02x.\n", link_speed,
2934 fcport->port_name[0], fcport->port_name[1],
2935 fcport->port_name[2], fcport->port_name[3],
2936 fcport->port_name[4], fcport->port_name[5],
2937 fcport->port_name[6], fcport->port_name[7]);
d8b45213
AV		 2938 }
2939}
2940
23be331d 2941static void
e315cd28 2942qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport)
8482e118
AV		 2943{
2944 struct fc_rport_identifiers rport_ids;
bdf79621 2945 struct fc_rport *rport;
044d78e1 2946 unsigned long flags;
8482e118 2947
ac280b67 2948 qla2x00_rport_del(fcport);
8482e118 2949
f8b02a85
AV		 2950 rport_ids.node_name = wwn_to_u64(fcport->node_name);
2951 rport_ids.port_name = wwn_to_u64(fcport->port_name);
8482e118
AV		 2952 rport_ids.port_id = fcport->d_id.b.domain << 16 |
2953 fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa;
77d74143 2954 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
e315cd28 2955 fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids);
77d74143 2956 if (!rport) {
7c3df132
SK		 2957 ql_log(ql_log_warn, vha, 0x2006,
2958 "Unable to allocate fc remote port.\n");
77d74143
AV		 2959 return;
2960 }
2d70c103
NB		 2961 /*
2962 * Create target mode FC NEXUS in qla_target.c if target mode is
2963 * enabled..
2964 */
2965 qlt_fc_port_added(vha, fcport);
2966
044d78e1 2967 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
19a7b4ae 2968 *((fc_port_t **)rport->dd_data) = fcport;
044d78e1 2969 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
d97994dc 2970
ad3e0eda 2971 rport->supported_classes = fcport->supported_classes;
77d74143 2972
8482e118
AV		 2973 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
2974 if (fcport->port_type == FCT_INITIATOR)
2975 rport_ids.roles |= FC_RPORT_ROLE_FCP_INITIATOR;
2976 if (fcport->port_type == FCT_TARGET)
2977 rport_ids.roles |= FC_RPORT_ROLE_FCP_TARGET;
77d74143 2978 fc_remote_port_rolechg(rport, rport_ids.roles);
1da177e4
LT		 2979}
2980
23be331d
AB		 2981/*
2982 * qla2x00_update_fcport
2983 * Updates device on list.
2984 *
2985 * Input:
2986 * ha = adapter block pointer.
2987 * fcport = port structure pointer.
2988 *
2989 * Return:
2990 * 0 - Success
2991 * BIT_0 - error
2992 *
2993 * Context:
2994 * Kernel context.
2995 */
2996void
e315cd28 2997qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
23be331d 2998{
e315cd28 2999 fcport->vha = vha;
23be331d 3000 fcport->login_retry = 0;
5ff1d584 3001 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
23be331d 3002
e315cd28 3003 qla2x00_iidma_fcport(vha, fcport);
21090cbe 3004 qla24xx_update_fcport_fcp_prio(vha, fcport);
e315cd28 3005 qla2x00_reg_remote_port(vha, fcport);
ec426e10 3006 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
23be331d
AB		 3007}
3008
1da177e4
LT		 3009/*
3010 * qla2x00_configure_fabric
3011 * Setup SNS devices with loop ID's.
3012 *
3013 * Input:
3014 * ha = adapter block pointer.
3015 *
3016 * Returns:
3017 * 0 = success.
3018 * BIT_0 = error
3019 */
3020static int
e315cd28 3021qla2x00_configure_fabric(scsi_qla_host_t *vha)
1da177e4 3022{
b3b02e6e 3023 int rval;
4dc77c36 3024 fc_port_t *fcport;
1da177e4
LT		 3025 uint16_t next_loopid;
3026 uint16_t mb[MAILBOX_REGISTER_COUNT];
0107109e 3027 uint16_t loop_id;
1da177e4 3028 LIST_HEAD(new_fcports);
e315cd28
AC		 3029 struct qla_hw_data *ha = vha->hw;
3030 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 3031
3032 /* If FL port exists, then SNS is present */
e428924c 3033 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 3034 loop_id = NPH_F_PORT;
3035 else
3036 loop_id = SNS_FL_PORT;
e315cd28 3037 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1);
1da177e4 3038 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3039 ql_dbg(ql_dbg_disc, vha, 0x201f,
3040 "MBX_GET_PORT_NAME failed, No FL Port.\n");
1da177e4 3041
e315cd28 3042 vha->device_flags &= ~SWITCH_FOUND;
1da177e4
LT		 3043 return (QLA_SUCCESS);
3044 }
e315cd28 3045 vha->device_flags |= SWITCH_FOUND;
1da177e4 3046
1da177e4 3047 do {
cca5335c
AV		 3048 /* FDMI support. */
3049 if (ql2xfdmienable &&
e315cd28
AC		 3050 test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags))
3051 qla2x00_fdmi_register(vha);
cca5335c 3052
1da177e4 3053 /* Ensure we are logged into the SNS. */
e428924c 3054 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 3055 loop_id = NPH_SNS;
3056 else
3057 loop_id = SIMPLE_NAME_SERVER;
0b91d116
CD		 3058 rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff,
3059 0xfc, mb, BIT_1|BIT_0);
3060 if (rval != QLA_SUCCESS) {
3061 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
4dc77c36 3062 break;
0b91d116 3063 }
1da177e4 3064 if (mb[0] != MBS_COMMAND_COMPLETE) {
7c3df132
SK		 3065 ql_dbg(ql_dbg_disc, vha, 0x2042,
3066 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x "
3067 "mb[6]=%x mb[7]=%x.\n", loop_id, mb[0], mb[1],
3068 mb[2], mb[6], mb[7]);
1da177e4
LT		 3069 return (QLA_SUCCESS);
3070 }
3071
e315cd28
AC		 3072 if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) {
3073 if (qla2x00_rft_id(vha)) {
1da177e4 3074 /* EMPTY */
7c3df132
SK		 3075 ql_dbg(ql_dbg_disc, vha, 0x2045,
3076 "Register FC-4 TYPE failed.\n");
1da177e4 3077 }
e315cd28 3078 if (qla2x00_rff_id(vha)) {
1da177e4 3079 /* EMPTY */
7c3df132
SK		 3080 ql_dbg(ql_dbg_disc, vha, 0x2049,
3081 "Register FC-4 Features failed.\n");
1da177e4 3082 }
e315cd28 3083 if (qla2x00_rnn_id(vha)) {
1da177e4 3084 /* EMPTY */
7c3df132
SK		 3085 ql_dbg(ql_dbg_disc, vha, 0x204f,
3086 "Register Node Name failed.\n");
e315cd28 3087 } else if (qla2x00_rsnn_nn(vha)) {
1da177e4 3088 /* EMPTY */
7c3df132
SK		 3089 ql_dbg(ql_dbg_disc, vha, 0x2053,
3090 "Register Symobilic Node Name failed.\n");
1da177e4
LT		 3091 }
3092 }
3093
e315cd28 3094 rval = qla2x00_find_all_fabric_devs(vha, &new_fcports);
1da177e4
LT		 3095 if (rval != QLA_SUCCESS)
3096 break;
3097
4dc77c36
JC		 3098 /* Add new ports to existing port list */
3099 list_splice_tail_init(&new_fcports, &vha->vp_fcports);
3100
3101 /* Starting free loop ID. */
3102 next_loopid = ha->min_external_loopid;
3103
e315cd28
AC		 3104 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3105 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
1da177e4
LT		 3106 break;
3107
3108 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0)
3109 continue;
3110
4dc77c36 3111 /* Logout lost/gone fabric devices (non-FCP2) */
c0822b63 3112 if (fcport->scan_state != QLA_FCPORT_SCAN_FOUND &&
b3b02e6e 3113 atomic_read(&fcport->state) == FCS_ONLINE) {
e315cd28 3114 qla2x00_mark_device_lost(vha, fcport,
d97994dc 3115 ql2xplogiabsentdevice, 0);
1da177e4 3116 if (fcport->loop_id != FC_NO_LOOP_ID &&
f08b7251 3117 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
1da177e4
LT		 3118 fcport->port_type != FCT_INITIATOR &&
3119 fcport->port_type != FCT_BROADCAST) {
e315cd28 3120 ha->isp_ops->fabric_logout(vha,
1c7c6357
AV		 3121 fcport->loop_id,
3122 fcport->d_id.b.domain,
3123 fcport->d_id.b.area,
3124 fcport->d_id.b.al_pa);
1da177e4 3125 }
c0822b63 3126 continue;
1da177e4 3127 }
c0822b63 3128 fcport->scan_state = QLA_FCPORT_SCAN_NONE;
1da177e4 3129
4dc77c36
JC		 3130 /* Login fabric devices that need a login */
3131 if ((fcport->flags & FCF_LOGIN_NEEDED) != 0 &&
3132 atomic_read(&vha->loop_down_timer) == 0) {
3133 if (fcport->loop_id == FC_NO_LOOP_ID) {
3134 fcport->loop_id = next_loopid;
3135 rval = qla2x00_find_new_loop_id(
3136 base_vha, fcport);
3137 if (rval != QLA_SUCCESS) {
3138 /* Ran out of IDs to use */
3139 continue;
3140 }
1da177e4
LT		 3141 }
3142 }
1da177e4 3143
bdf79621 3144 /* Login and update database */
e315cd28 3145 qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
1da177e4
LT		 3146 }
3147 } while (0);
3148
1da177e4 3149 if (rval) {
7c3df132
SK		 3150 ql_dbg(ql_dbg_disc, vha, 0x2068,
3151 "Configure fabric error exit rval=%d.\n", rval);
1da177e4
LT		 3152 }
3153
3154 return (rval);
3155}
3156
1da177e4
LT		 3157/*
3158 * qla2x00_find_all_fabric_devs
3159 *
3160 * Input:
3161 * ha = adapter block pointer.
3162 * dev = database device entry pointer.
3163 *
3164 * Returns:
3165 * 0 = success.
3166 *
3167 * Context:
3168 * Kernel context.
3169 */
3170static int
e315cd28
AC		 3171qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha,
3172 struct list_head *new_fcports)
1da177e4
LT		 3173{
3174 int rval;
3175 uint16_t loop_id;
3176 fc_port_t *fcport, *new_fcport, *fcptemp;
3177 int found;
3178
3179 sw_info_t *swl;
3180 int swl_idx;
3181 int first_dev, last_dev;
1516ef44 3182 port_id_t wrap = {}, nxt_d_id;
e315cd28
AC		 3183 struct qla_hw_data *ha = vha->hw;
3184 struct scsi_qla_host *vp, *base_vha = pci_get_drvdata(ha->pdev);
ee546b6e 3185 struct scsi_qla_host *tvp;
1da177e4
LT		 3186
3187 rval = QLA_SUCCESS;
3188
3189 /* Try GID_PT to get device list, else GAN. */
7a67735b 3190 if (!ha->swl)
642ef983 3191 ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t),
7a67735b
AV		 3192 GFP_KERNEL);
3193 swl = ha->swl;
bbfbbbc1 3194 if (!swl) {
1da177e4 3195 /*EMPTY*/
7c3df132
SK		 3196 ql_dbg(ql_dbg_disc, vha, 0x2054,
3197 "GID_PT allocations failed, fallback on GA_NXT.\n");
1da177e4 3198 } else {
642ef983 3199 memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t));
e315cd28 3200 if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) {
1da177e4 3201 swl = NULL;
e315cd28 3202 } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 3203 swl = NULL;
e315cd28 3204 } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 3205 swl = NULL;
e5896bd5 3206 } else if (ql2xiidmaenable &&
e315cd28
AC		 3207 qla2x00_gfpn_id(vha, swl) == QLA_SUCCESS) {
3208 qla2x00_gpsc(vha, swl);
1da177e4 3209 }
e8c72ba5
CD		 3210
3211 /* If other queries succeeded probe for FC-4 type */
3212 if (swl)
3213 qla2x00_gff_id(vha, swl);
1da177e4
LT		 3214 }
3215 swl_idx = 0;
3216
3217 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 3218 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3219 if (new_fcport == NULL) {
7c3df132
SK		 3220 ql_log(ql_log_warn, vha, 0x205e,
3221 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 3222 return (QLA_MEMORY_ALLOC_FAILED);
3223 }
3224 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
1da177e4
LT		 3225 /* Set start port ID scan at adapter ID. */
3226 first_dev = 1;
3227 last_dev = 0;
3228
3229 /* Starting free loop ID. */
e315cd28
AC		 3230 loop_id = ha->min_external_loopid;
3231 for (; loop_id <= ha->max_loop_id; loop_id++) {
3232 if (qla2x00_is_reserved_id(vha, loop_id))
1da177e4
LT		 3233 continue;
3234
3a6478df
GM		 3235 if (ha->current_topology == ISP_CFG_FL &&
3236 (atomic_read(&vha->loop_down_timer) ||
3237 LOOP_TRANSITION(vha))) {
bb2d52b2
AV		 3238 atomic_set(&vha->loop_down_timer, 0);
3239 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
3240 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
1da177e4 3241 break;
bb2d52b2 3242 }
1da177e4
LT		 3243
3244 if (swl != NULL) {
3245 if (last_dev) {
3246 wrap.b24 = new_fcport->d_id.b24;
3247 } else {
3248 new_fcport->d_id.b24 = swl[swl_idx].d_id.b24;
3249 memcpy(new_fcport->node_name,
3250 swl[swl_idx].node_name, WWN_SIZE);
3251 memcpy(new_fcport->port_name,
3252 swl[swl_idx].port_name, WWN_SIZE);
d8b45213
AV		 3253 memcpy(new_fcport->fabric_port_name,
3254 swl[swl_idx].fabric_port_name, WWN_SIZE);
3255 new_fcport->fp_speed = swl[swl_idx].fp_speed;
e8c72ba5 3256 new_fcport->fc4_type = swl[swl_idx].fc4_type;
1da177e4
LT		 3257
3258 if (swl[swl_idx].d_id.b.rsvd_1 != 0) {
3259 last_dev = 1;
3260 }
3261 swl_idx++;
3262 }
3263 } else {
3264 /* Send GA_NXT to the switch */
e315cd28 3265 rval = qla2x00_ga_nxt(vha, new_fcport);
1da177e4 3266 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3267 ql_log(ql_log_warn, vha, 0x2064,
3268 "SNS scan failed -- assuming "
3269 "zero-entry result.\n");
1da177e4
LT		 3270 list_for_each_entry_safe(fcport, fcptemp,
3271 new_fcports, list) {
3272 list_del(&fcport->list);
3273 kfree(fcport);
3274 }
3275 rval = QLA_SUCCESS;
3276 break;
3277 }
3278 }
3279
3280 /* If wrap on switch device list, exit. */
3281 if (first_dev) {
3282 wrap.b24 = new_fcport->d_id.b24;
3283 first_dev = 0;
3284 } else if (new_fcport->d_id.b24 == wrap.b24) {
7c3df132
SK		 3285 ql_dbg(ql_dbg_disc, vha, 0x2065,
3286 "Device wrap (%02x%02x%02x).\n",
3287 new_fcport->d_id.b.domain,
3288 new_fcport->d_id.b.area,
3289 new_fcport->d_id.b.al_pa);
1da177e4
LT		 3290 break;
3291 }
3292
2c3dfe3f 3293 /* Bypass if same physical adapter. */
e315cd28 3294 if (new_fcport->d_id.b24 == base_vha->d_id.b24)
1da177e4
LT		 3295 continue;
3296
2c3dfe3f 3297 /* Bypass virtual ports of the same host. */
e315cd28
AC		 3298 found = 0;
3299 if (ha->num_vhosts) {
feafb7b1
AE		 3300 unsigned long flags;
3301
3302 spin_lock_irqsave(&ha->vport_slock, flags);
ee546b6e 3303 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
e315cd28
AC		 3304 if (new_fcport->d_id.b24 == vp->d_id.b24) {
3305 found = 1;
2c3dfe3f 3306 break;
e315cd28 3307 }
2c3dfe3f 3308 }
feafb7b1
AE		 3309 spin_unlock_irqrestore(&ha->vport_slock, flags);
3310
e315cd28 3311 if (found)
2c3dfe3f
SJ		 3312 continue;
3313 }
3314
f7d289f6
AV		 3315 /* Bypass if same domain and area of adapter. */
3316 if (((new_fcport->d_id.b24 & 0xffff00) ==
e315cd28 3317 (vha->d_id.b24 & 0xffff00)) && ha->current_topology ==
f7d289f6
AV		 3318 ISP_CFG_FL)
3319 continue;
3320
1da177e4
LT		 3321 /* Bypass reserved domain fields. */
3322 if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0)
3323 continue;
3324
e8c72ba5 3325 /* Bypass ports whose FCP-4 type is not FCP_SCSI */
4da26e16
CD		 3326 if (ql2xgffidenable &&
3327 (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI &&
3328 new_fcport->fc4_type != FC4_TYPE_UNKNOWN))
e8c72ba5
CD		 3329 continue;
3330
1da177e4
LT		 3331 /* Locate matching device in database. */
3332 found = 0;
e315cd28 3333 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 3334 if (memcmp(new_fcport->port_name, fcport->port_name,
3335 WWN_SIZE))
3336 continue;
3337
c0822b63 3338 fcport->scan_state = QLA_FCPORT_SCAN_FOUND;
b3b02e6e 3339
1da177e4
LT		 3340 found++;
3341
d8b45213
AV		 3342 /* Update port state. */
3343 memcpy(fcport->fabric_port_name,
3344 new_fcport->fabric_port_name, WWN_SIZE);
3345 fcport->fp_speed = new_fcport->fp_speed;
3346
1da177e4
LT		 3347 /*
3348 * If address the same and state FCS_ONLINE, nothing
3349 * changed.
3350 */
3351 if (fcport->d_id.b24 == new_fcport->d_id.b24 &&
3352 atomic_read(&fcport->state) == FCS_ONLINE) {
3353 break;
3354 }
3355
3356 /*
3357 * If device was not a fabric device before.
3358 */
3359 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) {
3360 fcport->d_id.b24 = new_fcport->d_id.b24;
5f16b331 3361 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 3362 fcport->flags |= (FCF_FABRIC_DEVICE |
3363 FCF_LOGIN_NEEDED);
1da177e4
LT		 3364 break;
3365 }
3366
3367 /*
3368 * Port ID changed or device was marked to be updated;
3369 * Log it out if still logged in and mark it for
3370 * relogin later.
3371 */
3372 fcport->d_id.b24 = new_fcport->d_id.b24;
3373 fcport->flags |= FCF_LOGIN_NEEDED;
3374 if (fcport->loop_id != FC_NO_LOOP_ID &&
f08b7251 3375 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
0eba25df 3376 (fcport->flags & FCF_ASYNC_SENT) == 0 &&
1da177e4
LT		 3377 fcport->port_type != FCT_INITIATOR &&
3378 fcport->port_type != FCT_BROADCAST) {
e315cd28 3379 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3380 fcport->d_id.b.domain, fcport->d_id.b.area,
3381 fcport->d_id.b.al_pa);
5f16b331 3382 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 3383 }
3384
3385 break;
3386 }
3387
3388 if (found)
3389 continue;
1da177e4
LT		 3390 /* If device was not in our fcports list, then add it. */
3391 list_add_tail(&new_fcport->list, new_fcports);
3392
3393 /* Allocate a new replacement fcport. */
3394 nxt_d_id.b24 = new_fcport->d_id.b24;
e315cd28 3395 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3396 if (new_fcport == NULL) {
7c3df132
SK		 3397 ql_log(ql_log_warn, vha, 0x2066,
3398 "Memory allocation failed for fcport.\n");
1da177e4
LT		 3399 return (QLA_MEMORY_ALLOC_FAILED);
3400 }
3401 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
3402 new_fcport->d_id.b24 = nxt_d_id.b24;
3403 }
3404
c9475cb0 3405 kfree(new_fcport);
1da177e4 3406
1da177e4
LT		 3407 return (rval);
3408}
3409
3410/*
3411 * qla2x00_find_new_loop_id
3412 * Scan through our port list and find a new usable loop ID.
3413 *
3414 * Input:
3415 * ha: adapter state pointer.
3416 * dev: port structure pointer.
3417 *
3418 * Returns:
3419 * qla2x00 local function return status code.
3420 *
3421 * Context:
3422 * Kernel context.
3423 */
03bcfb57 3424int
e315cd28 3425qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
1da177e4
LT		 3426{
3427 int rval;
e315cd28 3428 struct qla_hw_data *ha = vha->hw;
feafb7b1 3429 unsigned long flags = 0;
1da177e4
LT		 3430
3431 rval = QLA_SUCCESS;
3432
5f16b331 3433 spin_lock_irqsave(&ha->vport_slock, flags);
1da177e4 3434
5f16b331
CD		 3435 dev->loop_id = find_first_zero_bit(ha->loop_id_map,
3436 LOOPID_MAP_SIZE);
3437 if (dev->loop_id >= LOOPID_MAP_SIZE ||
3438 qla2x00_is_reserved_id(vha, dev->loop_id)) {
3439 dev->loop_id = FC_NO_LOOP_ID;
3440 rval = QLA_FUNCTION_FAILED;
3441 } else
3442 set_bit(dev->loop_id, ha->loop_id_map);
1da177e4 3443
5f16b331 3444 spin_unlock_irqrestore(&ha->vport_slock, flags);
1da177e4 3445
5f16b331
CD		 3446 if (rval == QLA_SUCCESS)
3447 ql_dbg(ql_dbg_disc, dev->vha, 0x2086,
3448 "Assigning new loopid=%x, portid=%x.\n",
3449 dev->loop_id, dev->d_id.b24);
3450 else
3451 ql_log(ql_log_warn, dev->vha, 0x2087,
3452 "No loop_id's available, portid=%x.\n",
3453 dev->d_id.b24);
1da177e4
LT		 3454
3455 return (rval);
3456}
3457
1da177e4
LT		 3458/*
3459 * qla2x00_fabric_dev_login
3460 * Login fabric target device and update FC port database.
3461 *
3462 * Input:
3463 * ha: adapter state pointer.
3464 * fcport: port structure list pointer.
3465 * next_loopid: contains value of a new loop ID that can be used
3466 * by the next login attempt.
3467 *
3468 * Returns:
3469 * qla2x00 local function return status code.
3470 *
3471 * Context:
3472 * Kernel context.
3473 */
3474static int
e315cd28 3475qla2x00_fabric_dev_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 3476 uint16_t *next_loopid)
3477{
3478 int rval;
3479 int retry;
0107109e 3480 uint8_t opts;
e315cd28 3481 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3482
3483 rval = QLA_SUCCESS;
3484 retry = 0;
3485
ac280b67 3486 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584
AV		 3487 if (fcport->flags & FCF_ASYNC_SENT)
3488 return rval;
3489 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 3490 rval = qla2x00_post_async_login_work(vha, fcport, NULL);
3491 if (!rval)
3492 return rval;
3493 }
3494
5ff1d584 3495 fcport->flags &= ~FCF_ASYNC_SENT;
e315cd28 3496 rval = qla2x00_fabric_login(vha, fcport, next_loopid);
1da177e4 3497 if (rval == QLA_SUCCESS) {
f08b7251 3498 /* Send an ADISC to FCP2 devices.*/
0107109e 3499 opts = 0;
f08b7251 3500 if (fcport->flags & FCF_FCP2_DEVICE)
0107109e 3501 opts |= BIT_1;
e315cd28 3502 rval = qla2x00_get_port_database(vha, fcport, opts);
1da177e4 3503 if (rval != QLA_SUCCESS) {
e315cd28 3504 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3505 fcport->d_id.b.domain, fcport->d_id.b.area,
3506 fcport->d_id.b.al_pa);
e315cd28 3507 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4 3508 } else {
e315cd28 3509 qla2x00_update_fcport(vha, fcport);
1da177e4 3510 }
0b91d116
CD		 3511 } else {
3512 /* Retry Login. */
3513 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 3514 }
3515
3516 return (rval);
3517}
3518
3519/*
3520 * qla2x00_fabric_login
3521 * Issue fabric login command.
3522 *
3523 * Input:
3524 * ha = adapter block pointer.
3525 * device = pointer to FC device type structure.
3526 *
3527 * Returns:
3528 * 0 - Login successfully
3529 * 1 - Login failed
3530 * 2 - Initiator device
3531 * 3 - Fatal error
3532 */
3533int
e315cd28 3534qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 3535 uint16_t *next_loopid)
3536{
3537 int rval;
3538 int retry;
3539 uint16_t tmp_loopid;
3540 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 3541 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3542
3543 retry = 0;
3544 tmp_loopid = 0;
3545
3546 for (;;) {
7c3df132
SK		 3547 ql_dbg(ql_dbg_disc, vha, 0x2000,
3548 "Trying Fabric Login w/loop id 0x%04x for port "
3549 "%02x%02x%02x.\n",
3550 fcport->loop_id, fcport->d_id.b.domain,
3551 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 3552
3553 /* Login fcport on switch. */
0b91d116 3554 rval = ha->isp_ops->fabric_login(vha, fcport->loop_id,
1da177e4
LT		 3555 fcport->d_id.b.domain, fcport->d_id.b.area,
3556 fcport->d_id.b.al_pa, mb, BIT_0);
0b91d116
CD		 3557 if (rval != QLA_SUCCESS) {
3558 return rval;
3559 }
1da177e4
LT		 3560 if (mb[0] == MBS_PORT_ID_USED) {
3561 /*
3562 * Device has another loop ID. The firmware team
0107109e
AV		 3563 * recommends the driver perform an implicit login with
3564 * the specified ID again. The ID we just used is save
3565 * here so we return with an ID that can be tried by
3566 * the next login.
1da177e4
LT		 3567 */
3568 retry++;
3569 tmp_loopid = fcport->loop_id;
3570 fcport->loop_id = mb[1];
3571
7c3df132
SK		 3572 ql_dbg(ql_dbg_disc, vha, 0x2001,
3573 "Fabric Login: port in use - next loop "
3574 "id=0x%04x, port id= %02x%02x%02x.\n",
1da177e4 3575 fcport->loop_id, fcport->d_id.b.domain,
7c3df132 3576 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 3577
3578 } else if (mb[0] == MBS_COMMAND_COMPLETE) {
3579 /*
3580 * Login succeeded.
3581 */
3582 if (retry) {
3583 /* A retry occurred before. */
3584 *next_loopid = tmp_loopid;
3585 } else {
3586 /*
3587 * No retry occurred before. Just increment the
3588 * ID value for next login.
3589 */
3590 *next_loopid = (fcport->loop_id + 1);
3591 }
3592
3593 if (mb[1] & BIT_0) {
3594 fcport->port_type = FCT_INITIATOR;
3595 } else {
3596 fcport->port_type = FCT_TARGET;
3597 if (mb[1] & BIT_1) {
8474f3a0 3598 fcport->flags |= FCF_FCP2_DEVICE;
1da177e4
LT		 3599 }
3600 }
3601
ad3e0eda
AV		 3602 if (mb[10] & BIT_0)
3603 fcport->supported_classes |= FC_COS_CLASS2;
3604 if (mb[10] & BIT_1)
3605 fcport->supported_classes |= FC_COS_CLASS3;
3606
2d70c103
NB		 3607 if (IS_FWI2_CAPABLE(ha)) {
3608 if (mb[10] & BIT_7)
3609 fcport->flags |=
3610 FCF_CONF_COMP_SUPPORTED;
3611 }
3612
1da177e4
LT		 3613 rval = QLA_SUCCESS;
3614 break;
3615 } else if (mb[0] == MBS_LOOP_ID_USED) {
3616 /*
3617 * Loop ID already used, try next loop ID.
3618 */
3619 fcport->loop_id++;
e315cd28 3620 rval = qla2x00_find_new_loop_id(vha, fcport);
1da177e4
LT		 3621 if (rval != QLA_SUCCESS) {
3622 /* Ran out of loop IDs to use */
3623 break;
3624 }
3625 } else if (mb[0] == MBS_COMMAND_ERROR) {
3626 /*
3627 * Firmware possibly timed out during login. If NO
3628 * retries are left to do then the device is declared
3629 * dead.
3630 */
3631 *next_loopid = fcport->loop_id;
e315cd28 3632 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3633 fcport->d_id.b.domain, fcport->d_id.b.area,
3634 fcport->d_id.b.al_pa);
e315cd28 3635 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 3636
3637 rval = 1;
3638 break;
3639 } else {
3640 /*
3641 * unrecoverable / not handled error
3642 */
7c3df132
SK		 3643 ql_dbg(ql_dbg_disc, vha, 0x2002,
3644 "Failed=%x port_id=%02x%02x%02x loop_id=%x "
3645 "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain,
3646 fcport->d_id.b.area, fcport->d_id.b.al_pa,
3647 fcport->loop_id, jiffies);
1da177e4
LT		 3648
3649 *next_loopid = fcport->loop_id;
e315cd28 3650 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3651 fcport->d_id.b.domain, fcport->d_id.b.area,
3652 fcport->d_id.b.al_pa);
5f16b331 3653 qla2x00_clear_loop_id(fcport);
0eedfcf0 3654 fcport->login_retry = 0;
1da177e4
LT		 3655
3656 rval = 3;
3657 break;
3658 }
3659 }
3660
3661 return (rval);
3662}
3663
3664/*
3665 * qla2x00_local_device_login
3666 * Issue local device login command.
3667 *
3668 * Input:
3669 * ha = adapter block pointer.
3670 * loop_id = loop id of device to login to.
3671 *
3672 * Returns (Where's the #define!!!!):
3673 * 0 - Login successfully
3674 * 1 - Login failed
3675 * 3 - Fatal error
3676 */
3677int
e315cd28 3678qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport)
1da177e4
LT		 3679{
3680 int rval;
3681 uint16_t mb[MAILBOX_REGISTER_COUNT];
3682
3683 memset(mb, 0, sizeof(mb));
e315cd28 3684 rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0);
1da177e4
LT		 3685 if (rval == QLA_SUCCESS) {
3686 /* Interrogate mailbox registers for any errors */
3687 if (mb[0] == MBS_COMMAND_ERROR)
3688 rval = 1;
3689 else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR)
3690 /* device not in PCB table */
3691 rval = 3;
3692 }
3693
3694 return (rval);
3695}
3696
3697/*
3698 * qla2x00_loop_resync
3699 * Resync with fibre channel devices.
3700 *
3701 * Input:
3702 * ha = adapter block pointer.
3703 *
3704 * Returns:
3705 * 0 = success
3706 */
3707int
e315cd28 3708qla2x00_loop_resync(scsi_qla_host_t *vha)
1da177e4 3709{
73208dfd 3710 int rval = QLA_SUCCESS;
1da177e4 3711 uint32_t wait_time;
67c2e93a
AC		 3712 struct req_que *req;
3713 struct rsp_que *rsp;
3714
7163ea81 3715 if (vha->hw->flags.cpu_affinity_enabled)
67c2e93a
AC		 3716 req = vha->hw->req_q_map[0];
3717 else
3718 req = vha->req;
3719 rsp = req->rsp;
1da177e4 3720
e315cd28
AC		 3721 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
3722 if (vha->flags.online) {
3723 if (!(rval = qla2x00_fw_ready(vha))) {
1da177e4
LT		 3724 /* Wait at most MAX_TARGET RSCNs for a stable link. */
3725 wait_time = 256;
3726 do {
0107109e 3727 /* Issue a marker after FW becomes ready. */
73208dfd
AC		 3728 qla2x00_marker(vha, req, rsp, 0, 0,
3729 MK_SYNC_ALL);
e315cd28 3730 vha->marker_needed = 0;
1da177e4
LT		 3731
3732 /* Remap devices on Loop. */
e315cd28 3733 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4 3734
e315cd28 3735 qla2x00_configure_loop(vha);
1da177e4 3736 wait_time--;
e315cd28
AC		 3737 } while (!atomic_read(&vha->loop_down_timer) &&
3738 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
3739 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
3740 &vha->dpc_flags)));
1da177e4 3741 }
1da177e4
LT		 3742 }
3743
e315cd28 3744 if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
1da177e4 3745 return (QLA_FUNCTION_FAILED);
1da177e4 3746
e315cd28 3747 if (rval)
7c3df132
SK		 3748 ql_dbg(ql_dbg_disc, vha, 0x206c,
3749 "%s *** FAILED ***.\n", __func__);
1da177e4
LT		 3750
3751 return (rval);
3752}
3753
579d12b5
SK		 3754/*
3755* qla2x00_perform_loop_resync
3756* Description: This function will set the appropriate flags and call
3757* qla2x00_loop_resync. If successful loop will be resynced
3758* Arguments : scsi_qla_host_t pointer
3759* returm : Success or Failure
3760*/
3761
3762int qla2x00_perform_loop_resync(scsi_qla_host_t *ha)
3763{
3764 int32_t rval = 0;
3765
3766 if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) {
3767 /*Configure the flags so that resync happens properly*/
3768 atomic_set(&ha->loop_down_timer, 0);
3769 if (!(ha->device_flags & DFLG_NO_CABLE)) {
3770 atomic_set(&ha->loop_state, LOOP_UP);
3771 set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags);
3772 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
3773 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
3774
3775 rval = qla2x00_loop_resync(ha);
3776 } else
3777 atomic_set(&ha->loop_state, LOOP_DEAD);
3778
3779 clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags);
3780 }
3781
3782 return rval;
3783}
3784
d97994dc 3785void
67becc00 3786qla2x00_update_fcports(scsi_qla_host_t *base_vha)
d97994dc
AV		 3787{
3788 fc_port_t *fcport;
feafb7b1
AE		 3789 struct scsi_qla_host *vha;
3790 struct qla_hw_data *ha = base_vha->hw;
3791 unsigned long flags;
d97994dc 3792
feafb7b1 3793 spin_lock_irqsave(&ha->vport_slock, flags);
d97994dc 3794 /* Go with deferred removal of rport references. */
feafb7b1
AE		 3795 list_for_each_entry(vha, &base_vha->hw->vp_list, list) {
3796 atomic_inc(&vha->vref_count);
3797 list_for_each_entry(fcport, &vha->vp_fcports, list) {
8ae598d0 3798 if (fcport->drport &&
feafb7b1
AE		 3799 atomic_read(&fcport->state) != FCS_UNCONFIGURED) {
3800 spin_unlock_irqrestore(&ha->vport_slock, flags);
3801
67becc00 3802 qla2x00_rport_del(fcport);
feafb7b1
AE		 3803
3804 spin_lock_irqsave(&ha->vport_slock, flags);
3805 }
3806 }
3807 atomic_dec(&vha->vref_count);
3808 }
3809 spin_unlock_irqrestore(&ha->vport_slock, flags);
d97994dc
AV		 3810}
3811
7d613ac6
SV		 3812/* Assumes idc_lock always held on entry */
3813void
3814qla83xx_reset_ownership(scsi_qla_host_t *vha)
3815{
3816 struct qla_hw_data *ha = vha->hw;
3817 uint32_t drv_presence, drv_presence_mask;
3818 uint32_t dev_part_info1, dev_part_info2, class_type;
3819 uint32_t class_type_mask = 0x3;
3820 uint16_t fcoe_other_function = 0xffff, i;
3821
3822 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
3823
3824 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1);
3825 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2);
3826 for (i = 0; i < 8; i++) {
3827 class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask);
3828 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
3829 (i != ha->portnum)) {
3830 fcoe_other_function = i;
3831 break;
3832 }
3833 }
3834 if (fcoe_other_function == 0xffff) {
3835 for (i = 0; i < 8; i++) {
3836 class_type = ((dev_part_info2 >> (i * 4)) &
3837 class_type_mask);
3838 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
3839 ((i + 8) != ha->portnum)) {
3840 fcoe_other_function = i + 8;
3841 break;
3842 }
3843 }
3844 }
3845 /*
3846 * Prepare drv-presence mask based on fcoe functions present.
3847 * However consider only valid physical fcoe function numbers (0-15).
3848 */
3849 drv_presence_mask = ~((1 << (ha->portnum)) |
3850 ((fcoe_other_function == 0xffff) ?
3851 0 : (1 << (fcoe_other_function))));
3852
3853 /* We are the reset owner iff:
3854 * - No other protocol drivers present.
3855 * - This is the lowest among fcoe functions. */
3856 if (!(drv_presence & drv_presence_mask) &&
3857 (ha->portnum < fcoe_other_function)) {
3858 ql_dbg(ql_dbg_p3p, vha, 0xb07f,
3859 "This host is Reset owner.\n");
3860 ha->flags.nic_core_reset_owner = 1;
3861 }
3862}
3863
3864int
3865__qla83xx_set_drv_ack(scsi_qla_host_t *vha)
3866{
3867 int rval = QLA_SUCCESS;
3868 struct qla_hw_data *ha = vha->hw;
3869 uint32_t drv_ack;
3870
3871 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
3872 if (rval == QLA_SUCCESS) {
3873 drv_ack |= (1 << ha->portnum);
3874 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
3875 }
3876
3877 return rval;
3878}
3879
3880int
3881qla83xx_set_drv_ack(scsi_qla_host_t *vha)
3882{
3883 int rval = QLA_SUCCESS;
3884
3885 qla83xx_idc_lock(vha, 0);
3886 rval = __qla83xx_set_drv_ack(vha);
3887 qla83xx_idc_unlock(vha, 0);
3888
3889 return rval;
3890}
3891
3892int
3893__qla83xx_clear_drv_ack(scsi_qla_host_t *vha)
3894{
3895 int rval = QLA_SUCCESS;
3896 struct qla_hw_data *ha = vha->hw;
3897 uint32_t drv_ack;
3898
3899 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
3900 if (rval == QLA_SUCCESS) {
3901 drv_ack &= ~(1 << ha->portnum);
3902 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
3903 }
3904
3905 return rval;
3906}
3907
3908int
3909qla83xx_clear_drv_ack(scsi_qla_host_t *vha)
3910{
3911 int rval = QLA_SUCCESS;
3912
3913 qla83xx_idc_lock(vha, 0);
3914 rval = __qla83xx_clear_drv_ack(vha);
3915 qla83xx_idc_unlock(vha, 0);
3916
3917 return rval;
3918}
3919
3920const char *
3921qla83xx_dev_state_to_string(uint32_t dev_state)
3922{
3923 switch (dev_state) {
3924 case QLA8XXX_DEV_COLD:
3925 return "COLD/RE-INIT";
3926 case QLA8XXX_DEV_INITIALIZING:
3927 return "INITIALIZING";
3928 case QLA8XXX_DEV_READY:
3929 return "READY";
3930 case QLA8XXX_DEV_NEED_RESET:
3931 return "NEED RESET";
3932 case QLA8XXX_DEV_NEED_QUIESCENT:
3933 return "NEED QUIESCENT";
3934 case QLA8XXX_DEV_FAILED:
3935 return "FAILED";
3936 case QLA8XXX_DEV_QUIESCENT:
3937 return "QUIESCENT";
3938 default:
3939 return "Unknown";
3940 }
3941}
3942
3943/* Assumes idc-lock always held on entry */
3944void
3945qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type)
3946{
3947 struct qla_hw_data *ha = vha->hw;
3948 uint32_t idc_audit_reg = 0, duration_secs = 0;
3949
3950 switch (audit_type) {
3951 case IDC_AUDIT_TIMESTAMP:
3952 ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000);
3953 idc_audit_reg = (ha->portnum) |
3954 (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8);
3955 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
3956 break;
3957
3958 case IDC_AUDIT_COMPLETION:
3959 duration_secs = ((jiffies_to_msecs(jiffies) -
3960 jiffies_to_msecs(ha->idc_audit_ts)) / 1000);
3961 idc_audit_reg = (ha->portnum) |
3962 (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8);
3963 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
3964 break;
3965
3966 default:
3967 ql_log(ql_log_warn, vha, 0xb078,
3968 "Invalid audit type specified.\n");
3969 break;
3970 }
3971}
3972
3973/* Assumes idc_lock always held on entry */
3974int
3975qla83xx_initiating_reset(scsi_qla_host_t *vha)
3976{
3977 struct qla_hw_data *ha = vha->hw;
3978 uint32_t idc_control, dev_state;
3979
3980 __qla83xx_get_idc_control(vha, &idc_control);
3981 if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) {
3982 ql_log(ql_log_info, vha, 0xb080,
3983 "NIC Core reset has been disabled. idc-control=0x%x\n",
3984 idc_control);
3985 return QLA_FUNCTION_FAILED;
3986 }
3987
3988 /* Set NEED-RESET iff in READY state and we are the reset-owner */
3989 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
3990 if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) {
3991 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
3992 QLA8XXX_DEV_NEED_RESET);
3993 ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n");
3994 qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP);
3995 } else {
3996 const char *state = qla83xx_dev_state_to_string(dev_state);
3997 ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n", state);
3998
3999 /* SV: XXX: Is timeout required here? */
4000 /* Wait for IDC state change READY -> NEED_RESET */
4001 while (dev_state == QLA8XXX_DEV_READY) {
4002 qla83xx_idc_unlock(vha, 0);
4003 msleep(200);
4004 qla83xx_idc_lock(vha, 0);
4005 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4006 }
4007 }
4008
4009 /* Send IDC ack by writing to drv-ack register */
4010 __qla83xx_set_drv_ack(vha);
4011
4012 return QLA_SUCCESS;
4013}
4014
4015int
4016__qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control)
4017{
4018 return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
4019}
4020
4021int
4022qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control)
4023{
4024 int rval = QLA_SUCCESS;
4025
4026 qla83xx_idc_lock(vha, 0);
4027 rval = __qla83xx_set_idc_control(vha, idc_control);
4028 qla83xx_idc_unlock(vha, 0);
4029
4030 return rval;
4031}
4032
4033int
4034__qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control)
4035{
4036 return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
4037}
4038
4039int
4040qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control)
4041{
4042 int rval = QLA_SUCCESS;
4043
4044 qla83xx_idc_lock(vha, 0);
4045 rval = __qla83xx_get_idc_control(vha, idc_control);
4046 qla83xx_idc_unlock(vha, 0);
4047
4048 return rval;
4049}
4050
4051int
4052qla83xx_check_driver_presence(scsi_qla_host_t *vha)
4053{
4054 uint32_t drv_presence = 0;
4055 struct qla_hw_data *ha = vha->hw;
4056
4057 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4058 if (drv_presence & (1 << ha->portnum))
4059 return QLA_SUCCESS;
4060 else
4061 return QLA_TEST_FAILED;
4062}
4063
4064int
4065qla83xx_nic_core_reset(scsi_qla_host_t *vha)
4066{
4067 int rval = QLA_SUCCESS;
4068 struct qla_hw_data *ha = vha->hw;
4069
4070 ql_dbg(ql_dbg_p3p, vha, 0xb058,
4071 "Entered %s().\n", __func__);
4072
4073 if (vha->device_flags & DFLG_DEV_FAILED) {
4074 ql_log(ql_log_warn, vha, 0xb059,
4075 "Device in unrecoverable FAILED state.\n");
4076 return QLA_FUNCTION_FAILED;
4077 }
4078
4079 qla83xx_idc_lock(vha, 0);
4080
4081 if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) {
4082 ql_log(ql_log_warn, vha, 0xb05a,
4083 "Function=0x%x has been removed from IDC participation.\n",
4084 ha->portnum);
4085 rval = QLA_FUNCTION_FAILED;
4086 goto exit;
4087 }
4088
4089 qla83xx_reset_ownership(vha);
4090
4091 rval = qla83xx_initiating_reset(vha);
4092
4093 /*
4094 * Perform reset if we are the reset-owner,
4095 * else wait till IDC state changes to READY/FAILED.
4096 */
4097 if (rval == QLA_SUCCESS) {
4098 rval = qla83xx_idc_state_handler(vha);
4099
4100 if (rval == QLA_SUCCESS)
4101 ha->flags.nic_core_hung = 0;
4102 __qla83xx_clear_drv_ack(vha);
4103 }
4104
4105exit:
4106 qla83xx_idc_unlock(vha, 0);
4107
4108 ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__);
4109
4110 return rval;
4111}
4112
81178772
SK		 4113int
4114qla2xxx_mctp_dump(scsi_qla_host_t *vha)
4115{
4116 struct qla_hw_data *ha = vha->hw;
4117 int rval = QLA_FUNCTION_FAILED;
4118
4119 if (!IS_MCTP_CAPABLE(ha)) {
4120 /* This message can be removed from the final version */
4121 ql_log(ql_log_info, vha, 0x506d,
4122 "This board is not MCTP capable\n");
4123 return rval;
4124 }
4125
4126 if (!ha->mctp_dump) {
4127 ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev,
4128 MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL);
4129
4130 if (!ha->mctp_dump) {
4131 ql_log(ql_log_warn, vha, 0x506e,
4132 "Failed to allocate memory for mctp dump\n");
4133 return rval;
4134 }
4135 }
4136
4137#define MCTP_DUMP_STR_ADDR 0x00000000
4138 rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma,
4139 MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4);
4140 if (rval != QLA_SUCCESS) {
4141 ql_log(ql_log_warn, vha, 0x506f,
4142 "Failed to capture mctp dump\n");
4143 } else {
4144 ql_log(ql_log_info, vha, 0x5070,
4145 "Mctp dump capture for host (%ld/%p).\n",
4146 vha->host_no, ha->mctp_dump);
4147 ha->mctp_dumped = 1;
4148 }
4149
4150 if (!ha->flags.nic_core_reset_hdlr_active) {
4151 ha->flags.nic_core_reset_hdlr_active = 1;
4152 rval = qla83xx_restart_nic_firmware(vha);
4153 if (rval)
4154 /* NIC Core reset failed. */
4155 ql_log(ql_log_warn, vha, 0x5071,
4156 "Failed to restart nic firmware\n");
4157 else
4158 ql_dbg(ql_dbg_p3p, vha, 0xb084,
4159 "Restarted NIC firmware successfully.\n");
4160 ha->flags.nic_core_reset_hdlr_active = 0;
4161 }
4162
4163 return rval;
4164
4165}
4166
579d12b5 4167/*
8fcd6b8b 4168* qla2x00_quiesce_io
579d12b5
SK		 4169* Description: This function will block the new I/Os
4170* Its not aborting any I/Os as context
4171* is not destroyed during quiescence
4172* Arguments: scsi_qla_host_t
4173* return : void
4174*/
4175void
8fcd6b8b 4176qla2x00_quiesce_io(scsi_qla_host_t *vha)
579d12b5
SK		 4177{
4178 struct qla_hw_data *ha = vha->hw;
4179 struct scsi_qla_host *vp;
4180
8fcd6b8b
CD		 4181 ql_dbg(ql_dbg_dpc, vha, 0x401d,
4182 "Quiescing I/O - ha=%p.\n", ha);
579d12b5
SK		 4183
4184 atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME);
4185 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
4186 atomic_set(&vha->loop_state, LOOP_DOWN);
4187 qla2x00_mark_all_devices_lost(vha, 0);
4188 list_for_each_entry(vp, &ha->vp_list, list)
8fcd6b8b 4189 qla2x00_mark_all_devices_lost(vp, 0);
579d12b5
SK		 4190 } else {
4191 if (!atomic_read(&vha->loop_down_timer))
4192 atomic_set(&vha->loop_down_timer,
4193 LOOP_DOWN_TIME);
4194 }
4195 /* Wait for pending cmds to complete */
4196 qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST);
4197}
4198
a9083016
GM		 4199void
4200qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
4201{
4202 struct qla_hw_data *ha = vha->hw;
579d12b5 4203 struct scsi_qla_host *vp;
feafb7b1 4204 unsigned long flags;
6aef87be 4205 fc_port_t *fcport;
a9083016 4206
e46ef004
SK		 4207 /* For ISP82XX, driver waits for completion of the commands.
4208 * online flag should be set.
4209 */
4210 if (!IS_QLA82XX(ha))
4211 vha->flags.online = 0;
a9083016
GM		 4212 ha->flags.chip_reset_done = 0;
4213 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2be21fa2 4214 vha->qla_stats.total_isp_aborts++;
a9083016 4215
7c3df132
SK		 4216 ql_log(ql_log_info, vha, 0x00af,
4217 "Performing ISP error recovery - ha=%p.\n", ha);
a9083016 4218
e46ef004
SK		 4219 /* For ISP82XX, reset_chip is just disabling interrupts.
4220 * Driver waits for the completion of the commands.
4221 * the interrupts need to be enabled.
4222 */
a9083016
GM		 4223 if (!IS_QLA82XX(ha))
4224 ha->isp_ops->reset_chip(vha);
4225
4226 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
4227 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
4228 atomic_set(&vha->loop_state, LOOP_DOWN);
4229 qla2x00_mark_all_devices_lost(vha, 0);
feafb7b1
AE		 4230
4231 spin_lock_irqsave(&ha->vport_slock, flags);
579d12b5 4232 list_for_each_entry(vp, &ha->vp_list, list) {
feafb7b1
AE		 4233 atomic_inc(&vp->vref_count);
4234 spin_unlock_irqrestore(&ha->vport_slock, flags);
4235
a9083016 4236 qla2x00_mark_all_devices_lost(vp, 0);
feafb7b1
AE		 4237
4238 spin_lock_irqsave(&ha->vport_slock, flags);
4239 atomic_dec(&vp->vref_count);
4240 }
4241 spin_unlock_irqrestore(&ha->vport_slock, flags);
a9083016
GM		 4242 } else {
4243 if (!atomic_read(&vha->loop_down_timer))
4244 atomic_set(&vha->loop_down_timer,
4245 LOOP_DOWN_TIME);
4246 }
4247
6aef87be
AV		 4248 /* Clear all async request states across all VPs. */
4249 list_for_each_entry(fcport, &vha->vp_fcports, list)
4250 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
4251 spin_lock_irqsave(&ha->vport_slock, flags);
4252 list_for_each_entry(vp, &ha->vp_list, list) {
4253 atomic_inc(&vp->vref_count);
4254 spin_unlock_irqrestore(&ha->vport_slock, flags);
4255
4256 list_for_each_entry(fcport, &vp->vp_fcports, list)
4257 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
4258
4259 spin_lock_irqsave(&ha->vport_slock, flags);
4260 atomic_dec(&vp->vref_count);
4261 }
4262 spin_unlock_irqrestore(&ha->vport_slock, flags);
4263
bddd2d65
LC		 4264 if (!ha->flags.eeh_busy) {
4265 /* Make sure for ISP 82XX IO DMA is complete */
4266 if (IS_QLA82XX(ha)) {
7190575f 4267 qla82xx_chip_reset_cleanup(vha);
7c3df132
SK		 4268 ql_log(ql_log_info, vha, 0x00b4,
4269 "Done chip reset cleanup.\n");
a9083016 4270
e46ef004
SK		 4271 /* Done waiting for pending commands.
4272 * Reset the online flag.
4273 */
4274 vha->flags.online = 0;
4d78c973 4275 }
a9083016 4276
bddd2d65
LC		 4277 /* Requeue all commands in outstanding command list. */
4278 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
4279 }
a9083016
GM		 4280}
4281
1da177e4
LT		 4282/*
4283* qla2x00_abort_isp
4284* Resets ISP and aborts all outstanding commands.
4285*
4286* Input:
4287* ha = adapter block pointer.
4288*
4289* Returns:
4290* 0 = success
4291*/
4292int
e315cd28 4293qla2x00_abort_isp(scsi_qla_host_t *vha)
1da177e4 4294{
476e8978 4295 int rval;
1da177e4 4296 uint8_t status = 0;
e315cd28
AC		 4297 struct qla_hw_data *ha = vha->hw;
4298 struct scsi_qla_host *vp;
73208dfd 4299 struct req_que *req = ha->req_q_map[0];
feafb7b1 4300 unsigned long flags;
1da177e4 4301
7d613ac6
SV		 4302 if (IS_QLA8031(ha)) {
4303 ql_dbg(ql_dbg_p3p, vha, 0xb05c,
4304 "Clearing fcoe driver presence.\n");
4305 if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS)
4306 ql_dbg(ql_dbg_p3p, vha, 0xb073,
4307 "Erro while clearing DRV-Presence.\n");
4308 }
4309
e315cd28 4310 if (vha->flags.online) {
a9083016 4311 qla2x00_abort_isp_cleanup(vha);
1da177e4 4312
85880801
AV		 4313 if (unlikely(pci_channel_offline(ha->pdev) &&
4314 ha->flags.pci_channel_io_perm_failure)) {
4315 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
4316 status = 0;
4317 return status;
4318 }
4319
73208dfd 4320 ha->isp_ops->get_flash_version(vha, req->ring);
30c47662 4321
e315cd28 4322 ha->isp_ops->nvram_config(vha);
1da177e4 4323
e315cd28
AC		 4324 if (!qla2x00_restart_isp(vha)) {
4325 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4 4326
e315cd28 4327 if (!atomic_read(&vha->loop_down_timer)) {
1da177e4
LT		 4328 /*
4329 * Issue marker command only when we are going
4330 * to start the I/O .
4331 */
e315cd28 4332 vha->marker_needed = 1;
1da177e4
LT		 4333 }
4334
e315cd28 4335 vha->flags.online = 1;
1da177e4 4336
fd34f556 4337 ha->isp_ops->enable_intrs(ha);
1da177e4 4338
fa2a1ce5 4339 ha->isp_abort_cnt = 0;
e315cd28 4340 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
476e8978 4341
6246b8a1
GM		 4342 if (IS_QLA81XX(ha) || IS_QLA8031(ha))
4343 qla2x00_get_fw_version(vha);
df613b96
AV		 4344 if (ha->fce) {
4345 ha->flags.fce_enabled = 1;
4346 memset(ha->fce, 0,
4347 fce_calc_size(ha->fce_bufs));
e315cd28 4348 rval = qla2x00_enable_fce_trace(vha,
df613b96
AV		 4349 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
4350 &ha->fce_bufs);
4351 if (rval) {
7c3df132 4352 ql_log(ql_log_warn, vha, 0x8033,
df613b96
AV		 4353 "Unable to reinitialize FCE "
4354 "(%d).\n", rval);
4355 ha->flags.fce_enabled = 0;
4356 }
4357 }
436a7b11
AV		 4358
4359 if (ha->eft) {
4360 memset(ha->eft, 0, EFT_SIZE);
e315cd28 4361 rval = qla2x00_enable_eft_trace(vha,
436a7b11
AV		 4362 ha->eft_dma, EFT_NUM_BUFFERS);
4363 if (rval) {
7c3df132 4364 ql_log(ql_log_warn, vha, 0x8034,
436a7b11
AV		 4365 "Unable to reinitialize EFT "
4366 "(%d).\n", rval);
4367 }
4368 }
1da177e4 4369 } else { /* failed the ISP abort */
e315cd28
AC		 4370 vha->flags.online = 1;
4371 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
1da177e4 4372 if (ha->isp_abort_cnt == 0) {
7c3df132
SK		 4373 ql_log(ql_log_fatal, vha, 0x8035,
4374 "ISP error recover failed - "
4375 "board disabled.\n");
fa2a1ce5 4376 /*
1da177e4
LT		 4377 * The next call disables the board
4378 * completely.
4379 */
e315cd28
AC		 4380 ha->isp_ops->reset_adapter(vha);
4381 vha->flags.online = 0;
1da177e4 4382 clear_bit(ISP_ABORT_RETRY,
e315cd28 4383 &vha->dpc_flags);
1da177e4
LT		 4384 status = 0;
4385 } else { /* schedule another ISP abort */
4386 ha->isp_abort_cnt--;
7c3df132
SK		 4387 ql_dbg(ql_dbg_taskm, vha, 0x8020,
4388 "ISP abort - retry remaining %d.\n",
4389 ha->isp_abort_cnt);
1da177e4
LT		 4390 status = 1;
4391 }
4392 } else {
4393 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
7c3df132
SK		 4394 ql_dbg(ql_dbg_taskm, vha, 0x8021,
4395 "ISP error recovery - retrying (%d) "
4396 "more times.\n", ha->isp_abort_cnt);
e315cd28 4397 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
1da177e4
LT		 4398 status = 1;
4399 }
4400 }
fa2a1ce5 4401
1da177e4
LT		 4402 }
4403
e315cd28 4404 if (!status) {
7c3df132 4405 ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__);
feafb7b1
AE		 4406
4407 spin_lock_irqsave(&ha->vport_slock, flags);
4408 list_for_each_entry(vp, &ha->vp_list, list) {
4409 if (vp->vp_idx) {
4410 atomic_inc(&vp->vref_count);
4411 spin_unlock_irqrestore(&ha->vport_slock, flags);
4412
e315cd28 4413 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 4414
4415 spin_lock_irqsave(&ha->vport_slock, flags);
4416 atomic_dec(&vp->vref_count);
4417 }
e315cd28 4418 }
feafb7b1
AE		 4419 spin_unlock_irqrestore(&ha->vport_slock, flags);
4420
7d613ac6
SV		 4421 if (IS_QLA8031(ha)) {
4422 ql_dbg(ql_dbg_p3p, vha, 0xb05d,
4423 "Setting back fcoe driver presence.\n");
4424 if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS)
4425 ql_dbg(ql_dbg_p3p, vha, 0xb074,
4426 "Error while setting DRV-Presence.\n");
4427 }
e315cd28 4428 } else {
d8424f68
JP		 4429 ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n",
4430 __func__);
1da177e4
LT		 4431 }
4432
4433 return(status);
4434}
4435
4436/*
4437* qla2x00_restart_isp
4438* restarts the ISP after a reset
4439*
4440* Input:
4441* ha = adapter block pointer.
4442*
4443* Returns:
4444* 0 = success
4445*/
4446static int
e315cd28 4447qla2x00_restart_isp(scsi_qla_host_t *vha)
1da177e4 4448{
c6b2fca8 4449 int status = 0;
1da177e4 4450 uint32_t wait_time;
e315cd28 4451 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 4452 struct req_que *req = ha->req_q_map[0];
4453 struct rsp_que *rsp = ha->rsp_q_map[0];
2d70c103 4454 unsigned long flags;
1da177e4
LT		 4455
4456 /* If firmware needs to be loaded */
e315cd28
AC		 4457 if (qla2x00_isp_firmware(vha)) {
4458 vha->flags.online = 0;
4459 status = ha->isp_ops->chip_diag(vha);
4460 if (!status)
4461 status = qla2x00_setup_chip(vha);
1da177e4
LT		 4462 }
4463
e315cd28
AC		 4464 if (!status && !(status = qla2x00_init_rings(vha))) {
4465 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
2533cf67 4466 ha->flags.chip_reset_done = 1;
73208dfd
AC		 4467 /* Initialize the queues in use */
4468 qla25xx_init_queues(ha);
4469
e315cd28
AC		 4470 status = qla2x00_fw_ready(vha);
4471 if (!status) {
7c3df132
SK		 4472 ql_dbg(ql_dbg_taskm, vha, 0x8031,
4473 "Start configure loop status = %d.\n", status);
0107109e
AV		 4474
4475 /* Issue a marker after FW becomes ready. */
73208dfd 4476 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
0107109e 4477
e315cd28 4478 vha->flags.online = 1;
2d70c103
NB		 4479
4480 /*
4481 * Process any ATIO queue entries that came in
4482 * while we weren't online.
4483 */
4484 spin_lock_irqsave(&ha->hardware_lock, flags);
4485 if (qla_tgt_mode_enabled(vha))
4486 qlt_24xx_process_atio_queue(vha);
4487 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4488
1da177e4
LT		 4489 /* Wait at most MAX_TARGET RSCNs for a stable link. */
4490 wait_time = 256;
4491 do {
e315cd28
AC		 4492 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
4493 qla2x00_configure_loop(vha);
1da177e4 4494 wait_time--;
e315cd28
AC		 4495 } while (!atomic_read(&vha->loop_down_timer) &&
4496 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
4497 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
4498 &vha->dpc_flags)));
1da177e4
LT		 4499 }
4500
4501 /* if no cable then assume it's good */
e315cd28 4502 if ((vha->device_flags & DFLG_NO_CABLE))
1da177e4
LT		 4503 status = 0;
4504
7c3df132
SK		 4505 ql_dbg(ql_dbg_taskm, vha, 0x8032,
4506 "Configure loop done, status = 0x%x.\n", status);
1da177e4
LT		 4507 }
4508 return (status);
4509}
4510
73208dfd
AC		 4511static int
4512qla25xx_init_queues(struct qla_hw_data *ha)
4513{
4514 struct rsp_que *rsp = NULL;
4515 struct req_que *req = NULL;
4516 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
4517 int ret = -1;
4518 int i;
4519
2afa19a9 4520 for (i = 1; i < ha->max_rsp_queues; i++) {
73208dfd
AC		 4521 rsp = ha->rsp_q_map[i];
4522 if (rsp) {
4523 rsp->options &= ~BIT_0;
618a7523 4524 ret = qla25xx_init_rsp_que(base_vha, rsp);
73208dfd 4525 if (ret != QLA_SUCCESS)
7c3df132
SK		 4526 ql_dbg(ql_dbg_init, base_vha, 0x00ff,
4527 "%s Rsp que: %d init failed.\n",
4528 __func__, rsp->id);
73208dfd 4529 else
7c3df132
SK		 4530 ql_dbg(ql_dbg_init, base_vha, 0x0100,
4531 "%s Rsp que: %d inited.\n",
4532 __func__, rsp->id);
73208dfd 4533 }
2afa19a9
AC		 4534 }
4535 for (i = 1; i < ha->max_req_queues; i++) {
73208dfd
AC		 4536 req = ha->req_q_map[i];
4537 if (req) {
29bdccbe 4538 /* Clear outstanding commands array. */
73208dfd 4539 req->options &= ~BIT_0;
618a7523 4540 ret = qla25xx_init_req_que(base_vha, req);
73208dfd 4541 if (ret != QLA_SUCCESS)
7c3df132
SK		 4542 ql_dbg(ql_dbg_init, base_vha, 0x0101,
4543 "%s Req que: %d init failed.\n",
4544 __func__, req->id);
73208dfd 4545 else
7c3df132
SK		 4546 ql_dbg(ql_dbg_init, base_vha, 0x0102,
4547 "%s Req que: %d inited.\n",
4548 __func__, req->id);
73208dfd
AC		 4549 }
4550 }
4551 return ret;
4552}
4553
1da177e4
LT		 4554/*
4555* qla2x00_reset_adapter
4556* Reset adapter.
4557*
4558* Input:
4559* ha = adapter block pointer.
4560*/
abbd8870 4561void
e315cd28 4562qla2x00_reset_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 4563{
4564 unsigned long flags = 0;
e315cd28 4565 struct qla_hw_data *ha = vha->hw;
3d71644c 4566 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 4567
e315cd28 4568 vha->flags.online = 0;
fd34f556 4569 ha->isp_ops->disable_intrs(ha);
1da177e4 4570
1da177e4
LT		 4571 spin_lock_irqsave(&ha->hardware_lock, flags);
4572 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
4573 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
4574 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
4575 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
4576 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4577}
0107109e
AV		 4578
4579void
e315cd28 4580qla24xx_reset_adapter(scsi_qla_host_t *vha)
0107109e
AV		 4581{
4582 unsigned long flags = 0;
e315cd28 4583 struct qla_hw_data *ha = vha->hw;
0107109e
AV		 4584 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
4585
a9083016
GM		 4586 if (IS_QLA82XX(ha))
4587 return;
4588
e315cd28 4589 vha->flags.online = 0;
fd34f556 4590 ha->isp_ops->disable_intrs(ha);
0107109e
AV		 4591
4592 spin_lock_irqsave(&ha->hardware_lock, flags);
4593 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
4594 RD_REG_DWORD(&reg->hccr);
4595 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
4596 RD_REG_DWORD(&reg->hccr);
4597 spin_unlock_irqrestore(&ha->hardware_lock, flags);
09ff36d3
AV		 4598
4599 if (IS_NOPOLLING_TYPE(ha))
4600 ha->isp_ops->enable_intrs(ha);
0107109e
AV		 4601}
4602
4e08df3f
DM		 4603/* On sparc systems, obtain port and node WWN from firmware
4604 * properties.
4605 */
e315cd28
AC		 4606static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha,
4607 struct nvram_24xx *nv)
4e08df3f
DM		 4608{
4609#ifdef CONFIG_SPARC
e315cd28 4610 struct qla_hw_data *ha = vha->hw;
4e08df3f 4611 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 4612 struct device_node *dp = pci_device_to_OF_node(pdev);
4613 const u8 *val;
4e08df3f
DM		 4614 int len;
4615
4616 val = of_get_property(dp, "port-wwn", &len);
4617 if (val && len >= WWN_SIZE)
4618 memcpy(nv->port_name, val, WWN_SIZE);
4619
4620 val = of_get_property(dp, "node-wwn", &len);
4621 if (val && len >= WWN_SIZE)
4622 memcpy(nv->node_name, val, WWN_SIZE);
4623#endif
4624}
4625
0107109e 4626int
e315cd28 4627qla24xx_nvram_config(scsi_qla_host_t *vha)
0107109e 4628{
4e08df3f 4629 int rval;
0107109e
AV		 4630 struct init_cb_24xx *icb;
4631 struct nvram_24xx *nv;
4632 uint32_t *dptr;
4633 uint8_t *dptr1, *dptr2;
4634 uint32_t chksum;
4635 uint16_t cnt;
e315cd28 4636 struct qla_hw_data *ha = vha->hw;
0107109e 4637
4e08df3f 4638 rval = QLA_SUCCESS;
0107109e 4639 icb = (struct init_cb_24xx *)ha->init_cb;
281afe19 4640 nv = ha->nvram;
0107109e
AV		 4641
4642 /* Determine NVRAM starting address. */
e5b68a61
AC		 4643 if (ha->flags.port0) {
4644 ha->nvram_base = FA_NVRAM_FUNC0_ADDR;
4645 ha->vpd_base = FA_NVRAM_VPD0_ADDR;
4646 } else {
0107109e 4647 ha->nvram_base = FA_NVRAM_FUNC1_ADDR;
6f641790
AV		 4648 ha->vpd_base = FA_NVRAM_VPD1_ADDR;
4649 }
e5b68a61
AC		 4650 ha->nvram_size = sizeof(struct nvram_24xx);
4651 ha->vpd_size = FA_NVRAM_VPD_SIZE;
a9083016
GM		 4652 if (IS_QLA82XX(ha))
4653 ha->vpd_size = FA_VPD_SIZE_82XX;
0107109e 4654
281afe19
SJ		 4655 /* Get VPD data into cache */
4656 ha->vpd = ha->nvram + VPD_OFFSET;
e315cd28 4657 ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd,
281afe19
SJ		 4658 ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
4659
4660 /* Get NVRAM data into cache and calculate checksum. */
0107109e 4661 dptr = (uint32_t *)nv;
e315cd28 4662 ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base,
0107109e
AV		 4663 ha->nvram_size);
4664 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
4665 chksum += le32_to_cpu(*dptr++);
4666
7c3df132
SK		 4667 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
4668 "Contents of NVRAM\n");
4669 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
4670 (uint8_t *)nv, ha->nvram_size);
0107109e
AV		 4671
4672 /* Bad NVRAM data, set defaults parameters. */
4673 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
4674 || nv->id[3] != ' ' ||
4675 nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
4676 /* Reset NVRAM data. */
7c3df132 4677 ql_log(ql_log_warn, vha, 0x006b,
9e336520 4678 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132
SK		 4679 "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version);
4680 ql_log(ql_log_warn, vha, 0x006c,
4681 "Falling back to functioning (yet invalid -- WWPN) "
4682 "defaults.\n");
4e08df3f
DM		 4683
4684 /*
4685 * Set default initialization control block.
4686 */
4687 memset(nv, 0, ha->nvram_size);
4688 nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
4689 nv->version = __constant_cpu_to_le16(ICB_VERSION);
4690 nv->frame_payload_size = __constant_cpu_to_le16(2048);
4691 nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
4692 nv->exchange_count = __constant_cpu_to_le16(0);
4693 nv->hard_address = __constant_cpu_to_le16(124);
4694 nv->port_name[0] = 0x21;
e5b68a61 4695 nv->port_name[1] = 0x00 + ha->port_no;
4e08df3f
DM		 4696 nv->port_name[2] = 0x00;
4697 nv->port_name[3] = 0xe0;
4698 nv->port_name[4] = 0x8b;
4699 nv->port_name[5] = 0x1c;
4700 nv->port_name[6] = 0x55;
4701 nv->port_name[7] = 0x86;
4702 nv->node_name[0] = 0x20;
4703 nv->node_name[1] = 0x00;
4704 nv->node_name[2] = 0x00;
4705 nv->node_name[3] = 0xe0;
4706 nv->node_name[4] = 0x8b;
4707 nv->node_name[5] = 0x1c;
4708 nv->node_name[6] = 0x55;
4709 nv->node_name[7] = 0x86;
e315cd28 4710 qla24xx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 4711 nv->login_retry_count = __constant_cpu_to_le16(8);
4712 nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
4713 nv->login_timeout = __constant_cpu_to_le16(0);
4714 nv->firmware_options_1 =
4715 __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
4716 nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
4717 nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
4718 nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
4719 nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
4720 nv->efi_parameters = __constant_cpu_to_le32(0);
4721 nv->reset_delay = 5;
4722 nv->max_luns_per_target = __constant_cpu_to_le16(128);
4723 nv->port_down_retry_count = __constant_cpu_to_le16(30);
4724 nv->link_down_timeout = __constant_cpu_to_le16(30);
4725
4726 rval = 1;
0107109e
AV		 4727 }
4728
2d70c103
NB		 4729 if (!qla_ini_mode_enabled(vha)) {
4730 /* Don't enable full login after initial LIP */
4731 nv->firmware_options_1 &= __constant_cpu_to_le32(~BIT_13);
4732 /* Don't enable LIP full login for initiator */
4733 nv->host_p &= __constant_cpu_to_le32(~BIT_10);
4734 }
4735
4736 qlt_24xx_config_nvram_stage1(vha, nv);
4737
0107109e 4738 /* Reset Initialization control block */
e315cd28 4739 memset(icb, 0, ha->init_cb_size);
0107109e
AV		 4740
4741 /* Copy 1st segment. */
4742 dptr1 = (uint8_t *)icb;
4743 dptr2 = (uint8_t *)&nv->version;
4744 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
4745 while (cnt--)
4746 *dptr1++ = *dptr2++;
4747
4748 icb->login_retry_count = nv->login_retry_count;
3ea66e28 4749 icb->link_down_on_nos = nv->link_down_on_nos;
0107109e
AV		 4750
4751 /* Copy 2nd segment. */
4752 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
4753 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
4754 cnt = (uint8_t *)&icb->reserved_3 -
4755 (uint8_t *)&icb->interrupt_delay_timer;
4756 while (cnt--)
4757 *dptr1++ = *dptr2++;
4758
4759 /*
4760 * Setup driver NVRAM options.
4761 */
e315cd28 4762 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
9bb9fcf2 4763 "QLA2462");
0107109e 4764
2d70c103
NB		 4765 qlt_24xx_config_nvram_stage2(vha, icb);
4766
5341e868 4767 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
2d70c103 4768 /* Use alternate WWN? */
5341e868
AV		 4769 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
4770 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
4771 }
4772
0107109e 4773 /* Prepare nodename */
fd0e7e4d 4774 if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
0107109e
AV		 4775 /*
4776 * Firmware will apply the following mask if the nodename was
4777 * not provided.
4778 */
4779 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
4780 icb->node_name[0] &= 0xF0;
4781 }
4782
4783 /* Set host adapter parameters. */
4784 ha->flags.disable_risc_code_load = 0;
0c8c39af
AV		 4785 ha->flags.enable_lip_reset = 0;
4786 ha->flags.enable_lip_full_login =
4787 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
4788 ha->flags.enable_target_reset =
4789 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
0107109e 4790 ha->flags.enable_led_scheme = 0;
d4c760c2 4791 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
0107109e 4792
fd0e7e4d
AV		 4793 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
4794 (BIT_6 | BIT_5 | BIT_4)) >> 4;
0107109e
AV		 4795
4796 memcpy(ha->fw_seriallink_options24, nv->seriallink_options,
4797 sizeof(ha->fw_seriallink_options24));
4798
4799 /* save HBA serial number */
4800 ha->serial0 = icb->port_name[5];
4801 ha->serial1 = icb->port_name[6];
4802 ha->serial2 = icb->port_name[7];
e315cd28
AC		 4803 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
4804 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
0107109e 4805
bc8fb3cb
AV		 4806 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
4807
0107109e
AV		 4808 ha->retry_count = le16_to_cpu(nv->login_retry_count);
4809
4810 /* Set minimum login_timeout to 4 seconds. */
4811 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
4812 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
4813 if (le16_to_cpu(nv->login_timeout) < 4)
4814 nv->login_timeout = __constant_cpu_to_le16(4);
4815 ha->login_timeout = le16_to_cpu(nv->login_timeout);
c6852c4c 4816 icb->login_timeout = nv->login_timeout;
0107109e 4817
00a537b8
AV		 4818 /* Set minimum RATOV to 100 tenths of a second. */
4819 ha->r_a_tov = 100;
0107109e
AV		 4820
4821 ha->loop_reset_delay = nv->reset_delay;
4822
4823 /* Link Down Timeout = 0:
4824 *
4825 * When Port Down timer expires we will start returning
4826 * I/O's to OS with "DID_NO_CONNECT".
4827 *
4828 * Link Down Timeout != 0:
4829 *
4830 * The driver waits for the link to come up after link down
4831 * before returning I/Os to OS with "DID_NO_CONNECT".
4832 */
4833 if (le16_to_cpu(nv->link_down_timeout) == 0) {
4834 ha->loop_down_abort_time =
4835 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
4836 } else {
4837 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
4838 ha->loop_down_abort_time =
4839 (LOOP_DOWN_TIME - ha->link_down_timeout);
4840 }
4841
4842 /* Need enough time to try and get the port back. */
4843 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
4844 if (qlport_down_retry)
4845 ha->port_down_retry_count = qlport_down_retry;
4846
4847 /* Set login_retry_count */
4848 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
4849 if (ha->port_down_retry_count ==
4850 le16_to_cpu(nv->port_down_retry_count) &&
4851 ha->port_down_retry_count > 3)
4852 ha->login_retry_count = ha->port_down_retry_count;
4853 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
4854 ha->login_retry_count = ha->port_down_retry_count;
4855 if (ql2xloginretrycount)
4856 ha->login_retry_count = ql2xloginretrycount;
4857
4fdfefe5 4858 /* Enable ZIO. */
e315cd28 4859 if (!vha->flags.init_done) {
4fdfefe5
AV		 4860 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
4861 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
4862 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
4863 le16_to_cpu(icb->interrupt_delay_timer): 2;
4864 }
4865 icb->firmware_options_2 &= __constant_cpu_to_le32(
4866 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
e315cd28 4867 vha->flags.process_response_queue = 0;
4fdfefe5 4868 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d
AV		 4869 ha->zio_mode = QLA_ZIO_MODE_6;
4870
7c3df132 4871 ql_log(ql_log_info, vha, 0x006f,
4fdfefe5
AV		 4872 "ZIO mode %d enabled; timer delay (%d us).\n",
4873 ha->zio_mode, ha->zio_timer * 100);
4874
4875 icb->firmware_options_2 |= cpu_to_le32(
4876 (uint32_t)ha->zio_mode);
4877 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
e315cd28 4878 vha->flags.process_response_queue = 1;
4fdfefe5
AV		 4879 }
4880
4e08df3f 4881 if (rval) {
7c3df132
SK		 4882 ql_log(ql_log_warn, vha, 0x0070,
4883 "NVRAM configuration failed.\n");
4e08df3f
DM		 4884 }
4885 return (rval);
0107109e
AV		 4886}
4887
413975a0 4888static int
cbc8eb67
AV		 4889qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
4890 uint32_t faddr)
d1c61909 4891{
73208dfd 4892 int rval = QLA_SUCCESS;
d1c61909 4893 int segments, fragment;
d1c61909
AV		 4894 uint32_t *dcode, dlen;
4895 uint32_t risc_addr;
4896 uint32_t risc_size;
4897 uint32_t i;
e315cd28 4898 struct qla_hw_data *ha = vha->hw;
73208dfd 4899 struct req_que *req = ha->req_q_map[0];
eaac30be 4900
7c3df132 4901 ql_dbg(ql_dbg_init, vha, 0x008b,
cfb0919c 4902 "FW: Loading firmware from flash (%x).\n", faddr);
eaac30be 4903
d1c61909
AV		 4904 rval = QLA_SUCCESS;
4905
4906 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 4907 dcode = (uint32_t *)req->ring;
d1c61909
AV		 4908 *srisc_addr = 0;
4909
4910 /* Validate firmware image by checking version. */
e315cd28 4911 qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
d1c61909
AV		 4912 for (i = 0; i < 4; i++)
4913 dcode[i] = be32_to_cpu(dcode[i]);
4914 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
4915 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
4916 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
4917 dcode[3] == 0)) {
7c3df132
SK		 4918 ql_log(ql_log_fatal, vha, 0x008c,
4919 "Unable to verify the integrity of flash firmware "
4920 "image.\n");
4921 ql_log(ql_log_fatal, vha, 0x008d,
4922 "Firmware data: %08x %08x %08x %08x.\n",
4923 dcode[0], dcode[1], dcode[2], dcode[3]);
d1c61909
AV		 4924
4925 return QLA_FUNCTION_FAILED;
4926 }
4927
4928 while (segments && rval == QLA_SUCCESS) {
4929 /* Read segment's load information. */
e315cd28 4930 qla24xx_read_flash_data(vha, dcode, faddr, 4);
d1c61909
AV		 4931
4932 risc_addr = be32_to_cpu(dcode[2]);
4933 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
4934 risc_size = be32_to_cpu(dcode[3]);
4935
4936 fragment = 0;
4937 while (risc_size > 0 && rval == QLA_SUCCESS) {
4938 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
4939 if (dlen > risc_size)
4940 dlen = risc_size;
4941
7c3df132
SK		 4942 ql_dbg(ql_dbg_init, vha, 0x008e,
4943 "Loading risc segment@ risc addr %x "
4944 "number of dwords 0x%x offset 0x%x.\n",
4945 risc_addr, dlen, faddr);
d1c61909 4946
e315cd28 4947 qla24xx_read_flash_data(vha, dcode, faddr, dlen);
d1c61909
AV		 4948 for (i = 0; i < dlen; i++)
4949 dcode[i] = swab32(dcode[i]);
4950
73208dfd 4951 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
d1c61909
AV		 4952 dlen);
4953 if (rval) {
7c3df132
SK		 4954 ql_log(ql_log_fatal, vha, 0x008f,
4955 "Failed to load segment %d of firmware.\n",
4956 fragment);
d1c61909
AV		 4957 break;
4958 }
4959
4960 faddr += dlen;
4961 risc_addr += dlen;
4962 risc_size -= dlen;
4963 fragment++;
4964 }
4965
4966 /* Next segment. */
4967 segments--;
4968 }
4969
4970 return rval;
4971}
4972
d1c61909
AV		 4973#define QLA_FW_URL "ftp://ftp.qlogic.com/outgoing/linux/firmware/"
4974
0107109e 4975int
e315cd28 4976qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5433383e
AV		 4977{
4978 int rval;
4979 int i, fragment;
4980 uint16_t *wcode, *fwcode;
4981 uint32_t risc_addr, risc_size, fwclen, wlen, *seg;
4982 struct fw_blob *blob;
e315cd28 4983 struct qla_hw_data *ha = vha->hw;
73208dfd 4984 struct req_que *req = ha->req_q_map[0];
5433383e
AV		 4985
4986 /* Load firmware blob. */
e315cd28 4987 blob = qla2x00_request_firmware(vha);
5433383e 4988 if (!blob) {
7c3df132
SK		 4989 ql_log(ql_log_info, vha, 0x0083,
4990 "Fimware image unavailable.\n");
4991 ql_log(ql_log_info, vha, 0x0084,
4992 "Firmware images can be retrieved from: "QLA_FW_URL ".\n");
5433383e
AV		 4993 return QLA_FUNCTION_FAILED;
4994 }
4995
4996 rval = QLA_SUCCESS;
4997
73208dfd 4998 wcode = (uint16_t *)req->ring;
5433383e
AV		 4999 *srisc_addr = 0;
5000 fwcode = (uint16_t *)blob->fw->data;
5001 fwclen = 0;
5002
5003 /* Validate firmware image by checking version. */
5004 if (blob->fw->size < 8 * sizeof(uint16_t)) {
7c3df132
SK		 5005 ql_log(ql_log_fatal, vha, 0x0085,
5006 "Unable to verify integrity of firmware image (%Zd).\n",
5433383e
AV		 5007 blob->fw->size);
5008 goto fail_fw_integrity;
5009 }
5010 for (i = 0; i < 4; i++)
5011 wcode[i] = be16_to_cpu(fwcode[i + 4]);
5012 if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff &&
5013 wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 &&
5014 wcode[2] == 0 && wcode[3] == 0)) {
7c3df132
SK		 5015 ql_log(ql_log_fatal, vha, 0x0086,
5016 "Unable to verify integrity of firmware image.\n");
5017 ql_log(ql_log_fatal, vha, 0x0087,
5018 "Firmware data: %04x %04x %04x %04x.\n",
5019 wcode[0], wcode[1], wcode[2], wcode[3]);
5433383e
AV		 5020 goto fail_fw_integrity;
5021 }
5022
5023 seg = blob->segs;
5024 while (*seg && rval == QLA_SUCCESS) {
5025 risc_addr = *seg;
5026 *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr;
5027 risc_size = be16_to_cpu(fwcode[3]);
5028
5029 /* Validate firmware image size. */
5030 fwclen += risc_size * sizeof(uint16_t);
5031 if (blob->fw->size < fwclen) {
7c3df132 5032 ql_log(ql_log_fatal, vha, 0x0088,
5433383e 5033 "Unable to verify integrity of firmware image "
7c3df132 5034 "(%Zd).\n", blob->fw->size);
5433383e
AV		 5035 goto fail_fw_integrity;
5036 }
5037
5038 fragment = 0;
5039 while (risc_size > 0 && rval == QLA_SUCCESS) {
5040 wlen = (uint16_t)(ha->fw_transfer_size >> 1);
5041 if (wlen > risc_size)
5042 wlen = risc_size;
7c3df132
SK		 5043 ql_dbg(ql_dbg_init, vha, 0x0089,
5044 "Loading risc segment@ risc addr %x number of "
5045 "words 0x%x.\n", risc_addr, wlen);
5433383e
AV		 5046
5047 for (i = 0; i < wlen; i++)
5048 wcode[i] = swab16(fwcode[i]);
5049
73208dfd 5050 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
5433383e
AV		 5051 wlen);
5052 if (rval) {
7c3df132
SK		 5053 ql_log(ql_log_fatal, vha, 0x008a,
5054 "Failed to load segment %d of firmware.\n",
5055 fragment);
5433383e
AV		 5056 break;
5057 }
5058
5059 fwcode += wlen;
5060 risc_addr += wlen;
5061 risc_size -= wlen;
5062 fragment++;
5063 }
5064
5065 /* Next segment. */
5066 seg++;
5067 }
5068 return rval;
5069
5070fail_fw_integrity:
5071 return QLA_FUNCTION_FAILED;
5072}
5073
eaac30be
AV		 5074static int
5075qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
0107109e
AV		 5076{
5077 int rval;
5078 int segments, fragment;
5079 uint32_t *dcode, dlen;
5080 uint32_t risc_addr;
5081 uint32_t risc_size;
5082 uint32_t i;
5433383e 5083 struct fw_blob *blob;
0107109e 5084 uint32_t *fwcode, fwclen;
e315cd28 5085 struct qla_hw_data *ha = vha->hw;
73208dfd 5086 struct req_que *req = ha->req_q_map[0];
0107109e 5087
5433383e 5088 /* Load firmware blob. */
e315cd28 5089 blob = qla2x00_request_firmware(vha);
5433383e 5090 if (!blob) {
7c3df132
SK		 5091 ql_log(ql_log_warn, vha, 0x0090,
5092 "Fimware image unavailable.\n");
5093 ql_log(ql_log_warn, vha, 0x0091,
5094 "Firmware images can be retrieved from: "
5095 QLA_FW_URL ".\n");
d1c61909 5096
eaac30be 5097 return QLA_FUNCTION_FAILED;
0107109e
AV		 5098 }
5099
cfb0919c
CD		 5100 ql_dbg(ql_dbg_init, vha, 0x0092,
5101 "FW: Loading via request-firmware.\n");
eaac30be 5102
0107109e
AV		 5103 rval = QLA_SUCCESS;
5104
5105 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 5106 dcode = (uint32_t *)req->ring;
0107109e 5107 *srisc_addr = 0;
5433383e 5108 fwcode = (uint32_t *)blob->fw->data;
0107109e
AV		 5109 fwclen = 0;
5110
5111 /* Validate firmware image by checking version. */
5433383e 5112 if (blob->fw->size < 8 * sizeof(uint32_t)) {
7c3df132
SK		 5113 ql_log(ql_log_fatal, vha, 0x0093,
5114 "Unable to verify integrity of firmware image (%Zd).\n",
5433383e 5115 blob->fw->size);
0107109e
AV		 5116 goto fail_fw_integrity;
5117 }
5118 for (i = 0; i < 4; i++)
5119 dcode[i] = be32_to_cpu(fwcode[i + 4]);
5120 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
5121 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
5122 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
5123 dcode[3] == 0)) {
7c3df132
SK		 5124 ql_log(ql_log_fatal, vha, 0x0094,
5125 "Unable to verify integrity of firmware image (%Zd).\n",
5126 blob->fw->size);
5127 ql_log(ql_log_fatal, vha, 0x0095,
5128 "Firmware data: %08x %08x %08x %08x.\n",
5129 dcode[0], dcode[1], dcode[2], dcode[3]);
0107109e
AV		 5130 goto fail_fw_integrity;
5131 }
5132
5133 while (segments && rval == QLA_SUCCESS) {
5134 risc_addr = be32_to_cpu(fwcode[2]);
5135 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
5136 risc_size = be32_to_cpu(fwcode[3]);
5137
5138 /* Validate firmware image size. */
5139 fwclen += risc_size * sizeof(uint32_t);
5433383e 5140 if (blob->fw->size < fwclen) {
7c3df132 5141 ql_log(ql_log_fatal, vha, 0x0096,
5433383e 5142 "Unable to verify integrity of firmware image "
7c3df132 5143 "(%Zd).\n", blob->fw->size);
5433383e 5144
0107109e
AV		 5145 goto fail_fw_integrity;
5146 }
5147
5148 fragment = 0;
5149 while (risc_size > 0 && rval == QLA_SUCCESS) {
5150 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
5151 if (dlen > risc_size)
5152 dlen = risc_size;
5153
7c3df132
SK		 5154 ql_dbg(ql_dbg_init, vha, 0x0097,
5155 "Loading risc segment@ risc addr %x "
5156 "number of dwords 0x%x.\n", risc_addr, dlen);
0107109e
AV		 5157
5158 for (i = 0; i < dlen; i++)
5159 dcode[i] = swab32(fwcode[i]);
5160
73208dfd 5161 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
590f98e5 5162 dlen);
0107109e 5163 if (rval) {
7c3df132
SK		 5164 ql_log(ql_log_fatal, vha, 0x0098,
5165 "Failed to load segment %d of firmware.\n",
5166 fragment);
0107109e
AV		 5167 break;
5168 }
5169
5170 fwcode += dlen;
5171 risc_addr += dlen;
5172 risc_size -= dlen;
5173 fragment++;
5174 }
5175
5176 /* Next segment. */
5177 segments--;
5178 }
0107109e
AV		 5179 return rval;
5180
5181fail_fw_integrity:
0107109e 5182 return QLA_FUNCTION_FAILED;
0107109e 5183}
18c6c127 5184
eaac30be
AV		 5185int
5186qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5187{
5188 int rval;
5189
e337d907
AV		 5190 if (ql2xfwloadbin == 1)
5191 return qla81xx_load_risc(vha, srisc_addr);
5192
eaac30be
AV		 5193 /*
5194 * FW Load priority:
5195 * 1) Firmware via request-firmware interface (.bin file).
5196 * 2) Firmware residing in flash.
5197 */
5198 rval = qla24xx_load_risc_blob(vha, srisc_addr);
5199 if (rval == QLA_SUCCESS)
5200 return rval;
5201
cbc8eb67
AV		 5202 return qla24xx_load_risc_flash(vha, srisc_addr,
5203 vha->hw->flt_region_fw);
eaac30be
AV		 5204}
5205
5206int
5207qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5208{
5209 int rval;
cbc8eb67 5210 struct qla_hw_data *ha = vha->hw;
eaac30be 5211
e337d907 5212 if (ql2xfwloadbin == 2)
cbc8eb67 5213 goto try_blob_fw;
e337d907 5214
eaac30be
AV		 5215 /*
5216 * FW Load priority:
5217 * 1) Firmware residing in flash.
5218 * 2) Firmware via request-firmware interface (.bin file).
cbc8eb67 5219 * 3) Golden-Firmware residing in flash -- limited operation.
eaac30be 5220 */
cbc8eb67 5221 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
eaac30be
AV		 5222 if (rval == QLA_SUCCESS)
5223 return rval;
5224
cbc8eb67
AV		 5225try_blob_fw:
5226 rval = qla24xx_load_risc_blob(vha, srisc_addr);
5227 if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw)
5228 return rval;
5229
7c3df132
SK		 5230 ql_log(ql_log_info, vha, 0x0099,
5231 "Attempting to fallback to golden firmware.\n");
cbc8eb67
AV		 5232 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
5233 if (rval != QLA_SUCCESS)
5234 return rval;
5235
7c3df132 5236 ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n");
cbc8eb67 5237 ha->flags.running_gold_fw = 1;
cbc8eb67 5238 return rval;
eaac30be
AV		 5239}
5240
18c6c127 5241void
e315cd28 5242qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha)
18c6c127
AV		 5243{
5244 int ret, retries;
e315cd28 5245 struct qla_hw_data *ha = vha->hw;
18c6c127 5246
85880801
AV		 5247 if (ha->flags.pci_channel_io_perm_failure)
5248 return;
e428924c 5249 if (!IS_FWI2_CAPABLE(ha))
18c6c127 5250 return;
75edf81d
AV		 5251 if (!ha->fw_major_version)
5252 return;
18c6c127 5253
e315cd28 5254 ret = qla2x00_stop_firmware(vha);
7c7f1f29 5255 for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&
b469a7cb 5256 ret != QLA_INVALID_COMMAND && retries ; retries--) {
e315cd28
AC		 5257 ha->isp_ops->reset_chip(vha);
5258 if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS)
18c6c127 5259 continue;
e315cd28 5260 if (qla2x00_setup_chip(vha) != QLA_SUCCESS)
18c6c127 5261 continue;
7c3df132
SK		 5262 ql_log(ql_log_info, vha, 0x8015,
5263 "Attempting retry of stop-firmware command.\n");
e315cd28 5264 ret = qla2x00_stop_firmware(vha);
18c6c127
AV		 5265 }
5266}
2c3dfe3f
SJ		 5267
5268int
e315cd28 5269qla24xx_configure_vhba(scsi_qla_host_t *vha)
2c3dfe3f
SJ		 5270{
5271 int rval = QLA_SUCCESS;
0b91d116 5272 int rval2;
2c3dfe3f 5273 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28
AC		 5274 struct qla_hw_data *ha = vha->hw;
5275 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
67c2e93a
AC		 5276 struct req_que *req;
5277 struct rsp_que *rsp;
2c3dfe3f 5278
e315cd28 5279 if (!vha->vp_idx)
2c3dfe3f
SJ		 5280 return -EINVAL;
5281
e315cd28 5282 rval = qla2x00_fw_ready(base_vha);
7163ea81 5283 if (ha->flags.cpu_affinity_enabled)
67c2e93a
AC		 5284 req = ha->req_q_map[0];
5285 else
5286 req = vha->req;
5287 rsp = req->rsp;
5288
2c3dfe3f 5289 if (rval == QLA_SUCCESS) {
e315cd28 5290 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
73208dfd 5291 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
2c3dfe3f
SJ		 5292 }
5293
e315cd28 5294 vha->flags.management_server_logged_in = 0;
2c3dfe3f
SJ		 5295
5296 /* Login to SNS first */
0b91d116
CD		 5297 rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb,
5298 BIT_1);
5299 if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
5300 if (rval2 == QLA_MEMORY_ALLOC_FAILED)
5301 ql_dbg(ql_dbg_init, vha, 0x0120,
5302 "Failed SNS login: loop_id=%x, rval2=%d\n",
5303 NPH_SNS, rval2);
5304 else
5305 ql_dbg(ql_dbg_init, vha, 0x0103,
5306 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x "
5307 "mb[2]=%x mb[6]=%x mb[7]=%x.\n",
5308 NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]);
2c3dfe3f
SJ		 5309 return (QLA_FUNCTION_FAILED);
5310 }
5311
e315cd28
AC		 5312 atomic_set(&vha->loop_down_timer, 0);
5313 atomic_set(&vha->loop_state, LOOP_UP);
5314 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5315 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
5316 rval = qla2x00_loop_resync(base_vha);
2c3dfe3f
SJ		 5317
5318 return rval;
5319}
4d4df193
HK		 5320
5321/* 84XX Support **************************************************************/
5322
5323static LIST_HEAD(qla_cs84xx_list);
5324static DEFINE_MUTEX(qla_cs84xx_mutex);
5325
5326static struct qla_chip_state_84xx *
e315cd28 5327qla84xx_get_chip(struct scsi_qla_host *vha)
4d4df193
HK		 5328{
5329 struct qla_chip_state_84xx *cs84xx;
e315cd28 5330 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5331
5332 mutex_lock(&qla_cs84xx_mutex);
5333
5334 /* Find any shared 84xx chip. */
5335 list_for_each_entry(cs84xx, &qla_cs84xx_list, list) {
5336 if (cs84xx->bus == ha->pdev->bus) {
5337 kref_get(&cs84xx->kref);
5338 goto done;
5339 }
5340 }
5341
5342 cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL);
5343 if (!cs84xx)
5344 goto done;
5345
5346 kref_init(&cs84xx->kref);
5347 spin_lock_init(&cs84xx->access_lock);
5348 mutex_init(&cs84xx->fw_update_mutex);
5349 cs84xx->bus = ha->pdev->bus;
5350
5351 list_add_tail(&cs84xx->list, &qla_cs84xx_list);
5352done:
5353 mutex_unlock(&qla_cs84xx_mutex);
5354 return cs84xx;
5355}
5356
5357static void
5358__qla84xx_chip_release(struct kref *kref)
5359{
5360 struct qla_chip_state_84xx *cs84xx =
5361 container_of(kref, struct qla_chip_state_84xx, kref);
5362
5363 mutex_lock(&qla_cs84xx_mutex);
5364 list_del(&cs84xx->list);
5365 mutex_unlock(&qla_cs84xx_mutex);
5366 kfree(cs84xx);
5367}
5368
5369void
e315cd28 5370qla84xx_put_chip(struct scsi_qla_host *vha)
4d4df193 5371{
e315cd28 5372 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5373 if (ha->cs84xx)
5374 kref_put(&ha->cs84xx->kref, __qla84xx_chip_release);
5375}
5376
5377static int
e315cd28 5378qla84xx_init_chip(scsi_qla_host_t *vha)
4d4df193
HK		 5379{
5380 int rval;
5381 uint16_t status[2];
e315cd28 5382 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5383
5384 mutex_lock(&ha->cs84xx->fw_update_mutex);
5385
e315cd28 5386 rval = qla84xx_verify_chip(vha, status);
4d4df193
HK		 5387
5388 mutex_unlock(&ha->cs84xx->fw_update_mutex);
5389
5390 return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED:
5391 QLA_SUCCESS;
5392}
3a03eb79
AV		 5393
5394/* 81XX Support **************************************************************/
5395
5396int
5397qla81xx_nvram_config(scsi_qla_host_t *vha)
5398{
5399 int rval;
5400 struct init_cb_81xx *icb;
5401 struct nvram_81xx *nv;
5402 uint32_t *dptr;
5403 uint8_t *dptr1, *dptr2;
5404 uint32_t chksum;
5405 uint16_t cnt;
5406 struct qla_hw_data *ha = vha->hw;
5407
5408 rval = QLA_SUCCESS;
5409 icb = (struct init_cb_81xx *)ha->init_cb;
5410 nv = ha->nvram;
5411
5412 /* Determine NVRAM starting address. */
5413 ha->nvram_size = sizeof(struct nvram_81xx);
3a03eb79 5414 ha->vpd_size = FA_NVRAM_VPD_SIZE;
3a03eb79
AV		 5415
5416 /* Get VPD data into cache */
5417 ha->vpd = ha->nvram + VPD_OFFSET;
3d79038f
AV		 5418 ha->isp_ops->read_optrom(vha, ha->vpd, ha->flt_region_vpd << 2,
5419 ha->vpd_size);
3a03eb79
AV		 5420
5421 /* Get NVRAM data into cache and calculate checksum. */
3d79038f 5422 ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2,
3a03eb79 5423 ha->nvram_size);
3d79038f 5424 dptr = (uint32_t *)nv;
3a03eb79
AV		 5425 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
5426 chksum += le32_to_cpu(*dptr++);
5427
7c3df132
SK		 5428 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
5429 "Contents of NVRAM:\n");
5430 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
5431 (uint8_t *)nv, ha->nvram_size);
3a03eb79
AV		 5432
5433 /* Bad NVRAM data, set defaults parameters. */
5434 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
5435 || nv->id[3] != ' ' ||
5436 nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
5437 /* Reset NVRAM data. */
7c3df132 5438 ql_log(ql_log_info, vha, 0x0073,
9e336520 5439 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132 5440 "version=0x%x.\n", chksum, nv->id[0],
3a03eb79 5441 le16_to_cpu(nv->nvram_version));
7c3df132
SK		 5442 ql_log(ql_log_info, vha, 0x0074,
5443 "Falling back to functioning (yet invalid -- WWPN) "
5444 "defaults.\n");
3a03eb79
AV		 5445
5446 /*
5447 * Set default initialization control block.
5448 */
5449 memset(nv, 0, ha->nvram_size);
5450 nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
5451 nv->version = __constant_cpu_to_le16(ICB_VERSION);
5452 nv->frame_payload_size = __constant_cpu_to_le16(2048);
5453 nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
5454 nv->exchange_count = __constant_cpu_to_le16(0);
5455 nv->port_name[0] = 0x21;
e5b68a61 5456 nv->port_name[1] = 0x00 + ha->port_no;
3a03eb79
AV		 5457 nv->port_name[2] = 0x00;
5458 nv->port_name[3] = 0xe0;
5459 nv->port_name[4] = 0x8b;
5460 nv->port_name[5] = 0x1c;
5461 nv->port_name[6] = 0x55;
5462 nv->port_name[7] = 0x86;
5463 nv->node_name[0] = 0x20;
5464 nv->node_name[1] = 0x00;
5465 nv->node_name[2] = 0x00;
5466 nv->node_name[3] = 0xe0;
5467 nv->node_name[4] = 0x8b;
5468 nv->node_name[5] = 0x1c;
5469 nv->node_name[6] = 0x55;
5470 nv->node_name[7] = 0x86;
5471 nv->login_retry_count = __constant_cpu_to_le16(8);
5472 nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
5473 nv->login_timeout = __constant_cpu_to_le16(0);
5474 nv->firmware_options_1 =
5475 __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
5476 nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
5477 nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
5478 nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
5479 nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
5480 nv->efi_parameters = __constant_cpu_to_le32(0);
5481 nv->reset_delay = 5;
5482 nv->max_luns_per_target = __constant_cpu_to_le16(128);
5483 nv->port_down_retry_count = __constant_cpu_to_le16(30);
6246b8a1 5484 nv->link_down_timeout = __constant_cpu_to_le16(180);
eeebcc92 5485 nv->enode_mac[0] = 0x00;
6246b8a1
GM		 5486 nv->enode_mac[1] = 0xC0;
5487 nv->enode_mac[2] = 0xDD;
3a03eb79
AV		 5488 nv->enode_mac[3] = 0x04;
5489 nv->enode_mac[4] = 0x05;
e5b68a61 5490 nv->enode_mac[5] = 0x06 + ha->port_no;
3a03eb79
AV		 5491
5492 rval = 1;
5493 }
5494
5495 /* Reset Initialization control block */
773120e4 5496 memset(icb, 0, ha->init_cb_size);
3a03eb79
AV		 5497
5498 /* Copy 1st segment. */
5499 dptr1 = (uint8_t *)icb;
5500 dptr2 = (uint8_t *)&nv->version;
5501 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
5502 while (cnt--)
5503 *dptr1++ = *dptr2++;
5504
5505 icb->login_retry_count = nv->login_retry_count;
5506
5507 /* Copy 2nd segment. */
5508 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
5509 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
5510 cnt = (uint8_t *)&icb->reserved_5 -
5511 (uint8_t *)&icb->interrupt_delay_timer;
5512 while (cnt--)
5513 *dptr1++ = *dptr2++;
5514
5515 memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac));
5516 /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */
5517 if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) {
69e5f1ea
AV		 5518 icb->enode_mac[0] = 0x00;
5519 icb->enode_mac[1] = 0xC0;
5520 icb->enode_mac[2] = 0xDD;
3a03eb79
AV		 5521 icb->enode_mac[3] = 0x04;
5522 icb->enode_mac[4] = 0x05;
e5b68a61 5523 icb->enode_mac[5] = 0x06 + ha->port_no;
3a03eb79
AV		 5524 }
5525
b64b0e8f
AV		 5526 /* Use extended-initialization control block. */
5527 memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb));
5528
3a03eb79
AV		 5529 /*
5530 * Setup driver NVRAM options.
5531 */
5532 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
a9083016 5533 "QLE8XXX");
3a03eb79
AV		 5534
5535 /* Use alternate WWN? */
5536 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
5537 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
5538 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
5539 }
5540
5541 /* Prepare nodename */
5542 if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
5543 /*
5544 * Firmware will apply the following mask if the nodename was
5545 * not provided.
5546 */
5547 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
5548 icb->node_name[0] &= 0xF0;
5549 }
5550
5551 /* Set host adapter parameters. */
5552 ha->flags.disable_risc_code_load = 0;
5553 ha->flags.enable_lip_reset = 0;
5554 ha->flags.enable_lip_full_login =
5555 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
5556 ha->flags.enable_target_reset =
5557 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
5558 ha->flags.enable_led_scheme = 0;
5559 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
5560
5561 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
5562 (BIT_6 | BIT_5 | BIT_4)) >> 4;
5563
5564 /* save HBA serial number */
5565 ha->serial0 = icb->port_name[5];
5566 ha->serial1 = icb->port_name[6];
5567 ha->serial2 = icb->port_name[7];
5568 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
5569 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
5570
5571 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
5572
5573 ha->retry_count = le16_to_cpu(nv->login_retry_count);
5574
5575 /* Set minimum login_timeout to 4 seconds. */
5576 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
5577 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
5578 if (le16_to_cpu(nv->login_timeout) < 4)
5579 nv->login_timeout = __constant_cpu_to_le16(4);
5580 ha->login_timeout = le16_to_cpu(nv->login_timeout);
5581 icb->login_timeout = nv->login_timeout;
5582
5583 /* Set minimum RATOV to 100 tenths of a second. */
5584 ha->r_a_tov = 100;
5585
5586 ha->loop_reset_delay = nv->reset_delay;
5587
5588 /* Link Down Timeout = 0:
5589 *
5590 * When Port Down timer expires we will start returning
5591 * I/O's to OS with "DID_NO_CONNECT".
5592 *
5593 * Link Down Timeout != 0:
5594 *
5595 * The driver waits for the link to come up after link down
5596 * before returning I/Os to OS with "DID_NO_CONNECT".
5597 */
5598 if (le16_to_cpu(nv->link_down_timeout) == 0) {
5599 ha->loop_down_abort_time =
5600 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
5601 } else {
5602 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
5603 ha->loop_down_abort_time =
5604 (LOOP_DOWN_TIME - ha->link_down_timeout);
5605 }
5606
5607 /* Need enough time to try and get the port back. */
5608 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
5609 if (qlport_down_retry)
5610 ha->port_down_retry_count = qlport_down_retry;
5611
5612 /* Set login_retry_count */
5613 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
5614 if (ha->port_down_retry_count ==
5615 le16_to_cpu(nv->port_down_retry_count) &&
5616 ha->port_down_retry_count > 3)
5617 ha->login_retry_count = ha->port_down_retry_count;
5618 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
5619 ha->login_retry_count = ha->port_down_retry_count;
5620 if (ql2xloginretrycount)
5621 ha->login_retry_count = ql2xloginretrycount;
5622
6246b8a1
GM		 5623 /* if not running MSI-X we need handshaking on interrupts */
5624 if (!vha->hw->flags.msix_enabled && IS_QLA83XX(ha))
5625 icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_22);
5626
3a03eb79
AV		 5627 /* Enable ZIO. */
5628 if (!vha->flags.init_done) {
5629 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
5630 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
5631 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
5632 le16_to_cpu(icb->interrupt_delay_timer): 2;
5633 }
5634 icb->firmware_options_2 &= __constant_cpu_to_le32(
5635 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
5636 vha->flags.process_response_queue = 0;
5637 if (ha->zio_mode != QLA_ZIO_DISABLED) {
5638 ha->zio_mode = QLA_ZIO_MODE_6;
5639
7c3df132 5640 ql_log(ql_log_info, vha, 0x0075,
3a03eb79 5641 "ZIO mode %d enabled; timer delay (%d us).\n",
7c3df132
SK		 5642 ha->zio_mode,
5643 ha->zio_timer * 100);
3a03eb79
AV		 5644
5645 icb->firmware_options_2 |= cpu_to_le32(
5646 (uint32_t)ha->zio_mode);
5647 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
5648 vha->flags.process_response_queue = 1;
5649 }
5650
5651 if (rval) {
7c3df132
SK		 5652 ql_log(ql_log_warn, vha, 0x0076,
5653 "NVRAM configuration failed.\n");
3a03eb79
AV		 5654 }
5655 return (rval);
5656}
5657
a9083016
GM		 5658int
5659qla82xx_restart_isp(scsi_qla_host_t *vha)
5660{
5661 int status, rval;
5662 uint32_t wait_time;
5663 struct qla_hw_data *ha = vha->hw;
5664 struct req_que *req = ha->req_q_map[0];
5665 struct rsp_que *rsp = ha->rsp_q_map[0];
5666 struct scsi_qla_host *vp;
feafb7b1 5667 unsigned long flags;
a9083016
GM		 5668
5669 status = qla2x00_init_rings(vha);
5670 if (!status) {
5671 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
5672 ha->flags.chip_reset_done = 1;
5673
5674 status = qla2x00_fw_ready(vha);
5675 if (!status) {
7c3df132
SK		 5676 ql_log(ql_log_info, vha, 0x803c,
5677 "Start configure loop, status =%d.\n", status);
a9083016
GM		 5678
5679 /* Issue a marker after FW becomes ready. */
5680 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
5681
5682 vha->flags.online = 1;
5683 /* Wait at most MAX_TARGET RSCNs for a stable link. */
5684 wait_time = 256;
5685 do {
5686 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5687 qla2x00_configure_loop(vha);
5688 wait_time--;
5689 } while (!atomic_read(&vha->loop_down_timer) &&
5690 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) &&
5691 wait_time &&
5692 (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)));
5693 }
5694
5695 /* if no cable then assume it's good */
5696 if ((vha->device_flags & DFLG_NO_CABLE))
5697 status = 0;
5698
cfb0919c 5699 ql_log(ql_log_info, vha, 0x8000,
7c3df132 5700 "Configure loop done, status = 0x%x.\n", status);
a9083016
GM		 5701 }
5702
5703 if (!status) {
5704 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
5705
5706 if (!atomic_read(&vha->loop_down_timer)) {
5707 /*
5708 * Issue marker command only when we are going
5709 * to start the I/O .
5710 */
5711 vha->marker_needed = 1;
5712 }
5713
5714 vha->flags.online = 1;
5715
5716 ha->isp_ops->enable_intrs(ha);
5717
5718 ha->isp_abort_cnt = 0;
5719 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
5720
53296788 5721 /* Update the firmware version */
3173167f 5722 status = qla82xx_check_md_needed(vha);
53296788 5723
a9083016
GM		 5724 if (ha->fce) {
5725 ha->flags.fce_enabled = 1;
5726 memset(ha->fce, 0,
5727 fce_calc_size(ha->fce_bufs));
5728 rval = qla2x00_enable_fce_trace(vha,
5729 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
5730 &ha->fce_bufs);
5731 if (rval) {
cfb0919c 5732 ql_log(ql_log_warn, vha, 0x8001,
7c3df132
SK		 5733 "Unable to reinitialize FCE (%d).\n",
5734 rval);
a9083016
GM		 5735 ha->flags.fce_enabled = 0;
5736 }
5737 }
5738
5739 if (ha->eft) {
5740 memset(ha->eft, 0, EFT_SIZE);
5741 rval = qla2x00_enable_eft_trace(vha,
5742 ha->eft_dma, EFT_NUM_BUFFERS);
5743 if (rval) {
cfb0919c 5744 ql_log(ql_log_warn, vha, 0x8010,
7c3df132
SK		 5745 "Unable to reinitialize EFT (%d).\n",
5746 rval);
a9083016
GM		 5747 }
5748 }
a9083016
GM		 5749 }
5750
5751 if (!status) {
cfb0919c 5752 ql_dbg(ql_dbg_taskm, vha, 0x8011,
7c3df132 5753 "qla82xx_restart_isp succeeded.\n");
feafb7b1
AE		 5754
5755 spin_lock_irqsave(&ha->vport_slock, flags);
5756 list_for_each_entry(vp, &ha->vp_list, list) {
5757 if (vp->vp_idx) {
5758 atomic_inc(&vp->vref_count);
5759 spin_unlock_irqrestore(&ha->vport_slock, flags);
5760
a9083016 5761 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 5762
5763 spin_lock_irqsave(&ha->vport_slock, flags);
5764 atomic_dec(&vp->vref_count);
5765 }
a9083016 5766 }
feafb7b1
AE		 5767 spin_unlock_irqrestore(&ha->vport_slock, flags);
5768
a9083016 5769 } else {
cfb0919c 5770 ql_log(ql_log_warn, vha, 0x8016,
7c3df132 5771 "qla82xx_restart_isp **** FAILED ****.\n");
a9083016
GM		 5772 }
5773
5774 return status;
5775}
5776
3a03eb79 5777void
ae97c91e 5778qla81xx_update_fw_options(scsi_qla_host_t *vha)
3a03eb79 5779{
ae97c91e
AV		 5780 struct qla_hw_data *ha = vha->hw;
5781
5782 if (!ql2xetsenable)
5783 return;
5784
5785 /* Enable ETS Burst. */
5786 memset(ha->fw_options, 0, sizeof(ha->fw_options));
5787 ha->fw_options[2] |= BIT_9;
5788 qla2x00_set_fw_options(vha, ha->fw_options);
3a03eb79 5789}
09ff701a
SR		 5790
5791/*
5792 * qla24xx_get_fcp_prio
5793 * Gets the fcp cmd priority value for the logged in port.
5794 * Looks for a match of the port descriptors within
5795 * each of the fcp prio config entries. If a match is found,
5796 * the tag (priority) value is returned.
5797 *
5798 * Input:
21090cbe 5799 * vha = scsi host structure pointer.
09ff701a
SR		 5800 * fcport = port structure pointer.
5801 *
5802 * Return:
6c452a45 5803 * non-zero (if found)
f28a0a96 5804 * -1 (if not found)
09ff701a
SR		 5805 *
5806 * Context:
5807 * Kernel context
5808 */
f28a0a96 5809static int
09ff701a
SR		 5810qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
5811{
5812 int i, entries;
5813 uint8_t pid_match, wwn_match;
f28a0a96 5814 int priority;
09ff701a
SR		 5815 uint32_t pid1, pid2;
5816 uint64_t wwn1, wwn2;
5817 struct qla_fcp_prio_entry *pri_entry;
5818 struct qla_hw_data *ha = vha->hw;
5819
5820 if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled)
f28a0a96 5821 return -1;
09ff701a 5822
f28a0a96 5823 priority = -1;
09ff701a
SR		 5824 entries = ha->fcp_prio_cfg->num_entries;
5825 pri_entry = &ha->fcp_prio_cfg->entry[0];
5826
5827 for (i = 0; i < entries; i++) {
5828 pid_match = wwn_match = 0;
5829
5830 if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) {
5831 pri_entry++;
5832 continue;
5833 }
5834
5835 /* check source pid for a match */
5836 if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) {
5837 pid1 = pri_entry->src_pid & INVALID_PORT_ID;
5838 pid2 = vha->d_id.b24 & INVALID_PORT_ID;
5839 if (pid1 == INVALID_PORT_ID)
5840 pid_match++;
5841 else if (pid1 == pid2)
5842 pid_match++;
5843 }
5844
5845 /* check destination pid for a match */
5846 if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) {
5847 pid1 = pri_entry->dst_pid & INVALID_PORT_ID;
5848 pid2 = fcport->d_id.b24 & INVALID_PORT_ID;
5849 if (pid1 == INVALID_PORT_ID)
5850 pid_match++;
5851 else if (pid1 == pid2)
5852 pid_match++;
5853 }
5854
5855 /* check source WWN for a match */
5856 if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) {
5857 wwn1 = wwn_to_u64(vha->port_name);
5858 wwn2 = wwn_to_u64(pri_entry->src_wwpn);
5859 if (wwn2 == (uint64_t)-1)
5860 wwn_match++;
5861 else if (wwn1 == wwn2)
5862 wwn_match++;
5863 }
5864
5865 /* check destination WWN for a match */
5866 if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) {
5867 wwn1 = wwn_to_u64(fcport->port_name);
5868 wwn2 = wwn_to_u64(pri_entry->dst_wwpn);
5869 if (wwn2 == (uint64_t)-1)
5870 wwn_match++;
5871 else if (wwn1 == wwn2)
5872 wwn_match++;
5873 }
5874
5875 if (pid_match == 2 || wwn_match == 2) {
5876 /* Found a matching entry */
5877 if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID)
5878 priority = pri_entry->tag;
5879 break;
5880 }
5881
5882 pri_entry++;
5883 }
5884
5885 return priority;
5886}
5887
5888/*
5889 * qla24xx_update_fcport_fcp_prio
5890 * Activates fcp priority for the logged in fc port
5891 *
5892 * Input:
21090cbe 5893 * vha = scsi host structure pointer.
09ff701a
SR		 5894 * fcp = port structure pointer.
5895 *
5896 * Return:
5897 * QLA_SUCCESS or QLA_FUNCTION_FAILED
5898 *
5899 * Context:
5900 * Kernel context.
5901 */
5902int
21090cbe 5903qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
09ff701a
SR		 5904{
5905 int ret;
f28a0a96 5906 int priority;
09ff701a
SR		 5907 uint16_t mb[5];
5908
21090cbe
MI		 5909 if (fcport->port_type != FCT_TARGET ||
5910 fcport->loop_id == FC_NO_LOOP_ID)
09ff701a
SR		 5911 return QLA_FUNCTION_FAILED;
5912
21090cbe 5913 priority = qla24xx_get_fcp_prio(vha, fcport);
f28a0a96
AV		 5914 if (priority < 0)
5915 return QLA_FUNCTION_FAILED;
5916
a00f6296
SK		 5917 if (IS_QLA82XX(vha->hw)) {
5918 fcport->fcp_prio = priority & 0xf;
5919 return QLA_SUCCESS;
5920 }
5921
21090cbe 5922 ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb);
cfb0919c
CD		 5923 if (ret == QLA_SUCCESS) {
5924 if (fcport->fcp_prio != priority)
5925 ql_dbg(ql_dbg_user, vha, 0x709e,
5926 "Updated FCP_CMND priority - value=%d loop_id=%d "
5927 "port_id=%02x%02x%02x.\n", priority,
5928 fcport->loop_id, fcport->d_id.b.domain,
5929 fcport->d_id.b.area, fcport->d_id.b.al_pa);
a00f6296 5930 fcport->fcp_prio = priority & 0xf;
cfb0919c 5931 } else
7c3df132 5932 ql_dbg(ql_dbg_user, vha, 0x704f,
cfb0919c
CD		 5933 "Unable to update FCP_CMND priority - ret=0x%x for "
5934 "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id,
5935 fcport->d_id.b.domain, fcport->d_id.b.area,
5936 fcport->d_id.b.al_pa);
09ff701a
SR		 5937 return ret;
5938}
5939
5940/*
5941 * qla24xx_update_all_fcp_prio
5942 * Activates fcp priority for all the logged in ports
5943 *
5944 * Input:
5945 * ha = adapter block pointer.
5946 *
5947 * Return:
5948 * QLA_SUCCESS or QLA_FUNCTION_FAILED
5949 *
5950 * Context:
5951 * Kernel context.
5952 */
5953int
5954qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha)
5955{
5956 int ret;
5957 fc_port_t *fcport;
5958
5959 ret = QLA_FUNCTION_FAILED;
5960 /* We need to set priority for all logged in ports */
5961 list_for_each_entry(fcport, &vha->vp_fcports, list)
5962 ret = qla24xx_update_fcport_fcp_prio(vha, fcport);
5963
5964 return ret;
5965}
ubuntu-bionic-kernel mirror