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[SCSI] qla2xxx: Ignore driver ack bit if corresponding presence bit is not set.
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / qla2xxx / qla_init.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
46152ceb 3 * Copyright (c) 2003-2012 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
73208dfd 8#include "qla_gbl.h"
1da177e4
LT		 9
10#include <linux/delay.h>
5a0e3ad6 11#include <linux/slab.h>
0107109e 12#include <linux/vmalloc.h>
1da177e4
LT		 13
14#include "qla_devtbl.h"
15
4e08df3f
DM		 16#ifdef CONFIG_SPARC
17#include <asm/prom.h>
4e08df3f
DM		 18#endif
19
2d70c103
NB		 20#include <target/target_core_base.h>
21#include "qla_target.h"
22
1da177e4
LT		 23/*
24* QLogic ISP2x00 Hardware Support Function Prototypes.
25*/
1da177e4 26static int qla2x00_isp_firmware(scsi_qla_host_t *);
1da177e4 27static int qla2x00_setup_chip(scsi_qla_host_t *);
1da177e4
LT		 28static int qla2x00_init_rings(scsi_qla_host_t *);
29static int qla2x00_fw_ready(scsi_qla_host_t *);
30static int qla2x00_configure_hba(scsi_qla_host_t *);
1da177e4
LT		 31static int qla2x00_configure_loop(scsi_qla_host_t *);
32static int qla2x00_configure_local_loop(scsi_qla_host_t *);
1da177e4
LT		 33static int qla2x00_configure_fabric(scsi_qla_host_t *);
34static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *, struct list_head *);
1da177e4
LT		 35static int qla2x00_fabric_dev_login(scsi_qla_host_t *, fc_port_t *,
36 uint16_t *);
1da177e4
LT		 37
38static int qla2x00_restart_isp(scsi_qla_host_t *);
1da177e4 39
4d4df193
HK		 40static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *);
41static int qla84xx_init_chip(scsi_qla_host_t *);
73208dfd 42static int qla25xx_init_queues(struct qla_hw_data *);
4d4df193 43
ac280b67
AV		 44/* SRB Extensions ---------------------------------------------------------- */
45
9ba56b95
GM		 46void
47qla2x00_sp_timeout(unsigned long __data)
ac280b67
AV		 48{
49 srb_t *sp = (srb_t *)__data;
4916392b 50 struct srb_iocb *iocb;
ac280b67
AV		 51 fc_port_t *fcport = sp->fcport;
52 struct qla_hw_data *ha = fcport->vha->hw;
53 struct req_que *req;
54 unsigned long flags;
55
56 spin_lock_irqsave(&ha->hardware_lock, flags);
57 req = ha->req_q_map[0];
58 req->outstanding_cmds[sp->handle] = NULL;
9ba56b95 59 iocb = &sp->u.iocb_cmd;
4916392b 60 iocb->timeout(sp);
9ba56b95 61 sp->free(fcport->vha, sp);
6ac52608 62 spin_unlock_irqrestore(&ha->hardware_lock, flags);
ac280b67
AV		 63}
64
9ba56b95
GM		 65void
66qla2x00_sp_free(void *data, void *ptr)
ac280b67 67{
9ba56b95
GM		 68 srb_t *sp = (srb_t *)ptr;
69 struct srb_iocb *iocb = &sp->u.iocb_cmd;
70 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
ac280b67 71
4d97cc53 72 del_timer(&iocb->timer);
9ba56b95 73 mempool_free(sp, vha->hw->srb_mempool);
feafb7b1
AE		 74
75 QLA_VHA_MARK_NOT_BUSY(vha);
ac280b67
AV		 76}
77
ac280b67
AV		 78/* Asynchronous Login/Logout Routines -------------------------------------- */
79
a9b6f722 80unsigned long
5b91490e
AV		 81qla2x00_get_async_timeout(struct scsi_qla_host *vha)
82{
83 unsigned long tmo;
84 struct qla_hw_data *ha = vha->hw;
85
86 /* Firmware should use switch negotiated r_a_tov for timeout. */
87 tmo = ha->r_a_tov / 10 * 2;
88 if (!IS_FWI2_CAPABLE(ha)) {
89 /*
90 * Except for earlier ISPs where the timeout is seeded from the
91 * initialization control block.
92 */
93 tmo = ha->login_timeout;
94 }
95 return tmo;
96}
ac280b67
AV		 97
98static void
9ba56b95 99qla2x00_async_iocb_timeout(void *data)
ac280b67 100{
9ba56b95 101 srb_t *sp = (srb_t *)data;
ac280b67 102 fc_port_t *fcport = sp->fcport;
ac280b67 103
7c3df132 104 ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
cfb0919c 105 "Async-%s timeout - hdl=%x portid=%02x%02x%02x.\n",
9ba56b95 106 sp->name, sp->handle, fcport->d_id.b.domain, fcport->d_id.b.area,
7c3df132 107 fcport->d_id.b.al_pa);
ac280b67 108
5ff1d584 109 fcport->flags &= ~FCF_ASYNC_SENT;
9ba56b95
GM		 110 if (sp->type == SRB_LOGIN_CMD) {
111 struct srb_iocb *lio = &sp->u.iocb_cmd;
ac280b67 112 qla2x00_post_async_logout_work(fcport->vha, fcport, NULL);
6ac52608
AV		 113 /* Retry as needed. */
114 lio->u.logio.data[0] = MBS_COMMAND_ERROR;
115 lio->u.logio.data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
116 QLA_LOGIO_LOGIN_RETRIED : 0;
117 qla2x00_post_async_login_done_work(fcport->vha, fcport,
118 lio->u.logio.data);
119 }
ac280b67
AV		 120}
121
99b0bec7 122static void
9ba56b95 123qla2x00_async_login_sp_done(void *data, void *ptr, int res)
99b0bec7 124{
9ba56b95
GM		 125 srb_t *sp = (srb_t *)ptr;
126 struct srb_iocb *lio = &sp->u.iocb_cmd;
127 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
128
129 if (!test_bit(UNLOADING, &vha->dpc_flags))
130 qla2x00_post_async_login_done_work(sp->fcport->vha, sp->fcport,
131 lio->u.logio.data);
132 sp->free(sp->fcport->vha, sp);
99b0bec7
AV		 133}
134
ac280b67
AV		 135int
136qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport,
137 uint16_t *data)
138{
ac280b67 139 srb_t *sp;
4916392b 140 struct srb_iocb *lio;
ac280b67
AV		 141 int rval;
142
143 rval = QLA_FUNCTION_FAILED;
9ba56b95 144 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 145 if (!sp)
146 goto done;
147
9ba56b95
GM		 148 sp->type = SRB_LOGIN_CMD;
149 sp->name = "login";
150 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
151
152 lio = &sp->u.iocb_cmd;
3822263e 153 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 154 sp->done = qla2x00_async_login_sp_done;
4916392b 155 lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI;
ac280b67 156 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 157 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
ac280b67
AV		 158 rval = qla2x00_start_sp(sp);
159 if (rval != QLA_SUCCESS)
160 goto done_free_sp;
161
7c3df132 162 ql_dbg(ql_dbg_disc, vha, 0x2072,
cfb0919c
CD		 163 "Async-login - hdl=%x, loopid=%x portid=%02x%02x%02x "
164 "retries=%d.\n", sp->handle, fcport->loop_id,
165 fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
166 fcport->login_retry);
ac280b67
AV		 167 return rval;
168
169done_free_sp:
9ba56b95 170 sp->free(fcport->vha, sp);
ac280b67
AV		 171done:
172 return rval;
173}
174
99b0bec7 175static void
9ba56b95 176qla2x00_async_logout_sp_done(void *data, void *ptr, int res)
99b0bec7 177{
9ba56b95
GM		 178 srb_t *sp = (srb_t *)ptr;
179 struct srb_iocb *lio = &sp->u.iocb_cmd;
180 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
181
182 if (!test_bit(UNLOADING, &vha->dpc_flags))
183 qla2x00_post_async_logout_done_work(sp->fcport->vha, sp->fcport,
184 lio->u.logio.data);
185 sp->free(sp->fcport->vha, sp);
99b0bec7
AV		 186}
187
ac280b67
AV		 188int
189qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport)
190{
ac280b67 191 srb_t *sp;
4916392b 192 struct srb_iocb *lio;
ac280b67
AV		 193 int rval;
194
195 rval = QLA_FUNCTION_FAILED;
9ba56b95 196 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 197 if (!sp)
198 goto done;
199
9ba56b95
GM		 200 sp->type = SRB_LOGOUT_CMD;
201 sp->name = "logout";
202 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
203
204 lio = &sp->u.iocb_cmd;
3822263e 205 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 206 sp->done = qla2x00_async_logout_sp_done;
ac280b67
AV		 207 rval = qla2x00_start_sp(sp);
208 if (rval != QLA_SUCCESS)
209 goto done_free_sp;
210
7c3df132 211 ql_dbg(ql_dbg_disc, vha, 0x2070,
cfb0919c
CD		 212 "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
213 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
214 fcport->d_id.b.area, fcport->d_id.b.al_pa);
ac280b67
AV		 215 return rval;
216
217done_free_sp:
9ba56b95 218 sp->free(fcport->vha, sp);
ac280b67
AV		 219done:
220 return rval;
221}
222
5ff1d584 223static void
9ba56b95 224qla2x00_async_adisc_sp_done(void *data, void *ptr, int res)
5ff1d584 225{
9ba56b95
GM		 226 srb_t *sp = (srb_t *)ptr;
227 struct srb_iocb *lio = &sp->u.iocb_cmd;
228 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
229
230 if (!test_bit(UNLOADING, &vha->dpc_flags))
231 qla2x00_post_async_adisc_done_work(sp->fcport->vha, sp->fcport,
232 lio->u.logio.data);
233 sp->free(sp->fcport->vha, sp);
5ff1d584
AV		 234}
235
236int
237qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport,
238 uint16_t *data)
239{
5ff1d584 240 srb_t *sp;
4916392b 241 struct srb_iocb *lio;
5ff1d584
AV		 242 int rval;
243
244 rval = QLA_FUNCTION_FAILED;
9ba56b95 245 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
5ff1d584
AV		 246 if (!sp)
247 goto done;
248
9ba56b95
GM		 249 sp->type = SRB_ADISC_CMD;
250 sp->name = "adisc";
251 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
252
253 lio = &sp->u.iocb_cmd;
3822263e 254 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 255 sp->done = qla2x00_async_adisc_sp_done;
5ff1d584 256 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 257 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
5ff1d584
AV		 258 rval = qla2x00_start_sp(sp);
259 if (rval != QLA_SUCCESS)
260 goto done_free_sp;
261
7c3df132 262 ql_dbg(ql_dbg_disc, vha, 0x206f,
cfb0919c
CD		 263 "Async-adisc - hdl=%x loopid=%x portid=%02x%02x%02x.\n",
264 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
265 fcport->d_id.b.area, fcport->d_id.b.al_pa);
5ff1d584
AV		 266 return rval;
267
268done_free_sp:
9ba56b95 269 sp->free(fcport->vha, sp);
5ff1d584
AV		 270done:
271 return rval;
272}
273
3822263e 274static void
9ba56b95 275qla2x00_async_tm_cmd_done(void *data, void *ptr, int res)
3822263e 276{
9ba56b95
GM		 277 srb_t *sp = (srb_t *)ptr;
278 struct srb_iocb *iocb = &sp->u.iocb_cmd;
279 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
280 uint32_t flags;
281 uint16_t lun;
282 int rval;
3822263e 283
9ba56b95
GM		 284 if (!test_bit(UNLOADING, &vha->dpc_flags)) {
285 flags = iocb->u.tmf.flags;
286 lun = (uint16_t)iocb->u.tmf.lun;
287
288 /* Issue Marker IOCB */
289 rval = qla2x00_marker(vha, vha->hw->req_q_map[0],
290 vha->hw->rsp_q_map[0], sp->fcport->loop_id, lun,
291 flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
292
293 if ((rval != QLA_SUCCESS) || iocb->u.tmf.data) {
294 ql_dbg(ql_dbg_taskm, vha, 0x8030,
295 "TM IOCB failed (%x).\n", rval);
296 }
297 }
298 sp->free(sp->fcport->vha, sp);
3822263e
MI		 299}
300
301int
9ba56b95 302qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t tm_flags, uint32_t lun,
3822263e
MI		 303 uint32_t tag)
304{
305 struct scsi_qla_host *vha = fcport->vha;
3822263e 306 srb_t *sp;
3822263e
MI		 307 struct srb_iocb *tcf;
308 int rval;
309
310 rval = QLA_FUNCTION_FAILED;
9ba56b95 311 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
3822263e
MI		 312 if (!sp)
313 goto done;
314
9ba56b95
GM		 315 sp->type = SRB_TM_CMD;
316 sp->name = "tmf";
317 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
318
319 tcf = &sp->u.iocb_cmd;
320 tcf->u.tmf.flags = tm_flags;
3822263e
MI		 321 tcf->u.tmf.lun = lun;
322 tcf->u.tmf.data = tag;
323 tcf->timeout = qla2x00_async_iocb_timeout;
9ba56b95 324 sp->done = qla2x00_async_tm_cmd_done;
3822263e
MI		 325
326 rval = qla2x00_start_sp(sp);
327 if (rval != QLA_SUCCESS)
328 goto done_free_sp;
329
7c3df132 330 ql_dbg(ql_dbg_taskm, vha, 0x802f,
cfb0919c
CD		 331 "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
332 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
333 fcport->d_id.b.area, fcport->d_id.b.al_pa);
3822263e
MI		 334 return rval;
335
336done_free_sp:
9ba56b95 337 sp->free(fcport->vha, sp);
3822263e
MI		 338done:
339 return rval;
340}
341
4916392b 342void
ac280b67
AV		 343qla2x00_async_login_done(struct scsi_qla_host *vha, fc_port_t *fcport,
344 uint16_t *data)
345{
346 int rval;
ac280b67
AV		 347
348 switch (data[0]) {
349 case MBS_COMMAND_COMPLETE:
a4f92a32
AV		 350 /*
351 * Driver must validate login state - If PRLI not complete,
352 * force a relogin attempt via implicit LOGO, PLOGI, and PRLI
353 * requests.
354 */
355 rval = qla2x00_get_port_database(vha, fcport, 0);
0eba25df
AE		 356 if (rval == QLA_NOT_LOGGED_IN) {
357 fcport->flags &= ~FCF_ASYNC_SENT;
358 fcport->flags |= FCF_LOGIN_NEEDED;
359 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
360 break;
361 }
362
a4f92a32
AV		 363 if (rval != QLA_SUCCESS) {
364 qla2x00_post_async_logout_work(vha, fcport, NULL);
365 qla2x00_post_async_login_work(vha, fcport, NULL);
366 break;
367 }
99b0bec7 368 if (fcport->flags & FCF_FCP2_DEVICE) {
5ff1d584
AV		 369 qla2x00_post_async_adisc_work(vha, fcport, data);
370 break;
99b0bec7
AV		 371 }
372 qla2x00_update_fcport(vha, fcport);
ac280b67
AV		 373 break;
374 case MBS_COMMAND_ERROR:
5ff1d584 375 fcport->flags &= ~FCF_ASYNC_SENT;
ac280b67
AV		 376 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
377 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
378 else
80d79440 379 qla2x00_mark_device_lost(vha, fcport, 1, 0);
ac280b67
AV		 380 break;
381 case MBS_PORT_ID_USED:
382 fcport->loop_id = data[1];
6ac52608 383 qla2x00_post_async_logout_work(vha, fcport, NULL);
ac280b67
AV		 384 qla2x00_post_async_login_work(vha, fcport, NULL);
385 break;
386 case MBS_LOOP_ID_USED:
387 fcport->loop_id++;
388 rval = qla2x00_find_new_loop_id(vha, fcport);
389 if (rval != QLA_SUCCESS) {
5ff1d584 390 fcport->flags &= ~FCF_ASYNC_SENT;
80d79440 391 qla2x00_mark_device_lost(vha, fcport, 1, 0);
ac280b67
AV		 392 break;
393 }
394 qla2x00_post_async_login_work(vha, fcport, NULL);
395 break;
396 }
4916392b 397 return;
ac280b67
AV		 398}
399
4916392b 400void
ac280b67
AV		 401qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport,
402 uint16_t *data)
403{
404 qla2x00_mark_device_lost(vha, fcport, 1, 0);
4916392b 405 return;
ac280b67
AV		 406}
407
4916392b 408void
5ff1d584
AV		 409qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport,
410 uint16_t *data)
411{
412 if (data[0] == MBS_COMMAND_COMPLETE) {
413 qla2x00_update_fcport(vha, fcport);
414
4916392b 415 return;
5ff1d584
AV		 416 }
417
418 /* Retry login. */
419 fcport->flags &= ~FCF_ASYNC_SENT;
420 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
421 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
422 else
80d79440 423 qla2x00_mark_device_lost(vha, fcport, 1, 0);
5ff1d584 424
4916392b 425 return;
5ff1d584
AV		 426}
427
1da177e4
LT		 428/****************************************************************************/
429/* QLogic ISP2x00 Hardware Support Functions. */
430/****************************************************************************/
431
fa492630 432static int
7d613ac6
SV		 433qla83xx_nic_core_fw_load(scsi_qla_host_t *vha)
434{
435 int rval = QLA_SUCCESS;
436 struct qla_hw_data *ha = vha->hw;
437 uint32_t idc_major_ver, idc_minor_ver;
711aa7f7 438 uint16_t config[4];
7d613ac6
SV		 439
440 qla83xx_idc_lock(vha, 0);
441
442 /* SV: TODO: Assign initialization timeout from
443 * flash-info / other param
444 */
445 ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT;
446 ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT;
447
448 /* Set our fcoe function presence */
449 if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) {
450 ql_dbg(ql_dbg_p3p, vha, 0xb077,
451 "Error while setting DRV-Presence.\n");
452 rval = QLA_FUNCTION_FAILED;
453 goto exit;
454 }
455
456 /* Decide the reset ownership */
457 qla83xx_reset_ownership(vha);
458
459 /*
460 * On first protocol driver load:
461 * Init-Owner: Set IDC-Major-Version and Clear IDC-Lock-Recovery
462 * register.
463 * Others: Check compatibility with current IDC Major version.
464 */
465 qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver);
466 if (ha->flags.nic_core_reset_owner) {
467 /* Set IDC Major version */
468 idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION;
469 qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver);
470
471 /* Clearing IDC-Lock-Recovery register */
472 qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0);
473 } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) {
474 /*
475 * Clear further IDC participation if we are not compatible with
476 * the current IDC Major Version.
477 */
478 ql_log(ql_log_warn, vha, 0xb07d,
479 "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n",
480 idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION);
481 __qla83xx_clear_drv_presence(vha);
482 rval = QLA_FUNCTION_FAILED;
483 goto exit;
484 }
485 /* Each function sets its supported Minor version. */
486 qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver);
487 idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2));
488 qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver);
489
711aa7f7
SK		 490 if (ha->flags.nic_core_reset_owner) {
491 memset(config, 0, sizeof(config));
492 if (!qla81xx_get_port_config(vha, config))
493 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
494 QLA8XXX_DEV_READY);
495 }
496
7d613ac6
SV		 497 rval = qla83xx_idc_state_handler(vha);
498
499exit:
500 qla83xx_idc_unlock(vha, 0);
501
502 return rval;
503}
504
1da177e4
LT		 505/*
506* qla2x00_initialize_adapter
507* Initialize board.
508*
509* Input:
510* ha = adapter block pointer.
511*
512* Returns:
513* 0 = success
514*/
515int
e315cd28 516qla2x00_initialize_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 517{
518 int rval;
e315cd28 519 struct qla_hw_data *ha = vha->hw;
73208dfd 520 struct req_que *req = ha->req_q_map[0];
2533cf67 521
1da177e4 522 /* Clear adapter flags. */
e315cd28 523 vha->flags.online = 0;
2533cf67 524 ha->flags.chip_reset_done = 0;
e315cd28 525 vha->flags.reset_active = 0;
85880801
AV		 526 ha->flags.pci_channel_io_perm_failure = 0;
527 ha->flags.eeh_busy = 0;
794a5691 528 ha->flags.thermal_supported = 1;
e315cd28
AC		 529 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
530 atomic_set(&vha->loop_state, LOOP_DOWN);
531 vha->device_flags = DFLG_NO_CABLE;
532 vha->dpc_flags = 0;
533 vha->flags.management_server_logged_in = 0;
534 vha->marker_needed = 0;
1da177e4
LT		 535 ha->isp_abort_cnt = 0;
536 ha->beacon_blink_led = 0;
537
73208dfd
AC		 538 set_bit(0, ha->req_qid_map);
539 set_bit(0, ha->rsp_qid_map);
540
cfb0919c 541 ql_dbg(ql_dbg_init, vha, 0x0040,
7c3df132 542 "Configuring PCI space...\n");
e315cd28 543 rval = ha->isp_ops->pci_config(vha);
1da177e4 544 if (rval) {
7c3df132
SK		 545 ql_log(ql_log_warn, vha, 0x0044,
546 "Unable to configure PCI space.\n");
1da177e4
LT		 547 return (rval);
548 }
549
e315cd28 550 ha->isp_ops->reset_chip(vha);
1da177e4 551
e315cd28 552 rval = qla2xxx_get_flash_info(vha);
c00d8994 553 if (rval) {
7c3df132
SK		 554 ql_log(ql_log_fatal, vha, 0x004f,
555 "Unable to validate FLASH data.\n");
c00d8994
AV		 556 return (rval);
557 }
558
73208dfd 559 ha->isp_ops->get_flash_version(vha, req->ring);
cfb0919c 560 ql_dbg(ql_dbg_init, vha, 0x0061,
7c3df132 561 "Configure NVRAM parameters...\n");
0107109e 562
e315cd28 563 ha->isp_ops->nvram_config(vha);
1da177e4 564
d4c760c2
AV		 565 if (ha->flags.disable_serdes) {
566 /* Mask HBA via NVRAM settings? */
7c3df132
SK		 567 ql_log(ql_log_info, vha, 0x0077,
568 "Masking HBA WWPN "
d4c760c2 569 "%02x%02x%02x%02x%02x%02x%02x%02x (via NVRAM).\n",
e315cd28
AC		 570 vha->port_name[0], vha->port_name[1],
571 vha->port_name[2], vha->port_name[3],
572 vha->port_name[4], vha->port_name[5],
573 vha->port_name[6], vha->port_name[7]);
d4c760c2
AV		 574 return QLA_FUNCTION_FAILED;
575 }
576
cfb0919c 577 ql_dbg(ql_dbg_init, vha, 0x0078,
7c3df132 578 "Verifying loaded RISC code...\n");
1da177e4 579
e315cd28
AC		 580 if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) {
581 rval = ha->isp_ops->chip_diag(vha);
d19044c3
AV		 582 if (rval)
583 return (rval);
e315cd28 584 rval = qla2x00_setup_chip(vha);
d19044c3
AV		 585 if (rval)
586 return (rval);
1da177e4 587 }
a9083016 588
4d4df193 589 if (IS_QLA84XX(ha)) {
e315cd28 590 ha->cs84xx = qla84xx_get_chip(vha);
4d4df193 591 if (!ha->cs84xx) {
7c3df132 592 ql_log(ql_log_warn, vha, 0x00d0,
4d4df193
HK		 593 "Unable to configure ISP84XX.\n");
594 return QLA_FUNCTION_FAILED;
595 }
596 }
2d70c103
NB		 597
598 if (qla_ini_mode_enabled(vha))
599 rval = qla2x00_init_rings(vha);
600
2533cf67 601 ha->flags.chip_reset_done = 1;
1da177e4 602
9a069e19 603 if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) {
6c452a45 604 /* Issue verify 84xx FW IOCB to complete 84xx initialization */
9a069e19
GM		 605 rval = qla84xx_init_chip(vha);
606 if (rval != QLA_SUCCESS) {
7c3df132
SK		 607 ql_log(ql_log_warn, vha, 0x00d4,
608 "Unable to initialize ISP84XX.\n");
9a069e19
GM		 609 qla84xx_put_chip(vha);
610 }
611 }
612
7d613ac6
SV		 613 /* Load the NIC Core f/w if we are the first protocol driver. */
614 if (IS_QLA8031(ha)) {
615 rval = qla83xx_nic_core_fw_load(vha);
616 if (rval)
617 ql_log(ql_log_warn, vha, 0x0124,
618 "Error in initializing NIC Core f/w.\n");
619 }
620
2f0f3f4f
MI		 621 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
622 qla24xx_read_fcp_prio_cfg(vha);
09ff701a 623
1da177e4
LT		 624 return (rval);
625}
626
627/**
abbd8870 628 * qla2100_pci_config() - Setup ISP21xx PCI configuration registers.
1da177e4
LT		 629 * @ha: HA context
630 *
631 * Returns 0 on success.
632 */
abbd8870 633int
e315cd28 634qla2100_pci_config(scsi_qla_host_t *vha)
1da177e4 635{
a157b101 636 uint16_t w;
abbd8870 637 unsigned long flags;
e315cd28 638 struct qla_hw_data *ha = vha->hw;
3d71644c 639 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 640
1da177e4 641 pci_set_master(ha->pdev);
af6177d8 642 pci_try_set_mwi(ha->pdev);
1da177e4 643
1da177e4 644 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 645 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
abbd8870
AV		 646 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
647
737faece 648 pci_disable_rom(ha->pdev);
1da177e4
LT		 649
650 /* Get PCI bus information. */
651 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 652 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
1da177e4
LT		 653 spin_unlock_irqrestore(&ha->hardware_lock, flags);
654
abbd8870
AV		 655 return QLA_SUCCESS;
656}
1da177e4 657
abbd8870
AV		 658/**
659 * qla2300_pci_config() - Setup ISP23xx PCI configuration registers.
660 * @ha: HA context
661 *
662 * Returns 0 on success.
663 */
664int
e315cd28 665qla2300_pci_config(scsi_qla_host_t *vha)
abbd8870 666{
a157b101 667 uint16_t w;
abbd8870
AV		 668 unsigned long flags = 0;
669 uint32_t cnt;
e315cd28 670 struct qla_hw_data *ha = vha->hw;
3d71644c 671 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 672
abbd8870 673 pci_set_master(ha->pdev);
af6177d8 674 pci_try_set_mwi(ha->pdev);
1da177e4 675
abbd8870 676 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 677 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
1da177e4 678
abbd8870
AV		 679 if (IS_QLA2322(ha) || IS_QLA6322(ha))
680 w &= ~PCI_COMMAND_INTX_DISABLE;
a157b101 681 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1da177e4 682
abbd8870
AV		 683 /*
684 * If this is a 2300 card and not 2312, reset the
685 * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately,
686 * the 2310 also reports itself as a 2300 so we need to get the
687 * fb revision level -- a 6 indicates it really is a 2300 and
688 * not a 2310.
689 */
690 if (IS_QLA2300(ha)) {
691 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 692
abbd8870 693 /* Pause RISC. */
3d71644c 694 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
abbd8870 695 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 696 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
abbd8870 697 break;
1da177e4 698
abbd8870
AV		 699 udelay(10);
700 }
1da177e4 701
abbd8870 702 /* Select FPM registers. */
3d71644c
AV		 703 WRT_REG_WORD(&reg->ctrl_status, 0x20);
704 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 705
706 /* Get the fb rev level */
3d71644c 707 ha->fb_rev = RD_FB_CMD_REG(ha, reg);
abbd8870
AV		 708
709 if (ha->fb_rev == FPM_2300)
a157b101 710 pci_clear_mwi(ha->pdev);
abbd8870
AV		 711
712 /* Deselect FPM registers. */
3d71644c
AV		 713 WRT_REG_WORD(&reg->ctrl_status, 0x0);
714 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 715
716 /* Release RISC module. */
3d71644c 717 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
abbd8870 718 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 719 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0)
abbd8870
AV		 720 break;
721
722 udelay(10);
1da177e4 723 }
1da177e4 724
abbd8870
AV		 725 spin_unlock_irqrestore(&ha->hardware_lock, flags);
726 }
1da177e4 727
abbd8870
AV		 728 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
729
737faece 730 pci_disable_rom(ha->pdev);
1da177e4 731
abbd8870
AV		 732 /* Get PCI bus information. */
733 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 734 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 735 spin_unlock_irqrestore(&ha->hardware_lock, flags);
736
737 return QLA_SUCCESS;
1da177e4
LT		 738}
739
0107109e
AV		 740/**
741 * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers.
742 * @ha: HA context
743 *
744 * Returns 0 on success.
745 */
746int
e315cd28 747qla24xx_pci_config(scsi_qla_host_t *vha)
0107109e 748{
a157b101 749 uint16_t w;
0107109e 750 unsigned long flags = 0;
e315cd28 751 struct qla_hw_data *ha = vha->hw;
0107109e 752 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
0107109e
AV		 753
754 pci_set_master(ha->pdev);
af6177d8 755 pci_try_set_mwi(ha->pdev);
0107109e
AV		 756
757 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 758 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
0107109e
AV		 759 w &= ~PCI_COMMAND_INTX_DISABLE;
760 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
761
762 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
763
764 /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */
f85ec187
AV		 765 if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
766 pcix_set_mmrbc(ha->pdev, 2048);
0107109e
AV		 767
768 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 769 if (pci_is_pcie(ha->pdev))
5ffd3a52 770 pcie_set_readrq(ha->pdev, 4096);
0107109e 771
737faece 772 pci_disable_rom(ha->pdev);
0107109e 773
44c10138 774 ha->chip_revision = ha->pdev->revision;
a8488abe 775
0107109e
AV		 776 /* Get PCI bus information. */
777 spin_lock_irqsave(&ha->hardware_lock, flags);
778 ha->pci_attr = RD_REG_DWORD(&reg->ctrl_status);
779 spin_unlock_irqrestore(&ha->hardware_lock, flags);
780
781 return QLA_SUCCESS;
782}
783
c3a2f0df
AV		 784/**
785 * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers.
786 * @ha: HA context
787 *
788 * Returns 0 on success.
789 */
790int
e315cd28 791qla25xx_pci_config(scsi_qla_host_t *vha)
c3a2f0df
AV		 792{
793 uint16_t w;
e315cd28 794 struct qla_hw_data *ha = vha->hw;
c3a2f0df
AV		 795
796 pci_set_master(ha->pdev);
797 pci_try_set_mwi(ha->pdev);
798
799 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
800 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
801 w &= ~PCI_COMMAND_INTX_DISABLE;
802 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
803
804 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 805 if (pci_is_pcie(ha->pdev))
5ffd3a52 806 pcie_set_readrq(ha->pdev, 4096);
c3a2f0df 807
737faece 808 pci_disable_rom(ha->pdev);
c3a2f0df
AV		 809
810 ha->chip_revision = ha->pdev->revision;
811
812 return QLA_SUCCESS;
813}
814
1da177e4
LT		 815/**
816 * qla2x00_isp_firmware() - Choose firmware image.
817 * @ha: HA context
818 *
819 * Returns 0 on success.
820 */
821static int
e315cd28 822qla2x00_isp_firmware(scsi_qla_host_t *vha)
1da177e4
LT		 823{
824 int rval;
42e421b1
AV		 825 uint16_t loop_id, topo, sw_cap;
826 uint8_t domain, area, al_pa;
e315cd28 827 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 828
829 /* Assume loading risc code */
fa2a1ce5 830 rval = QLA_FUNCTION_FAILED;
1da177e4
LT		 831
832 if (ha->flags.disable_risc_code_load) {
7c3df132 833 ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n");
1da177e4
LT		 834
835 /* Verify checksum of loaded RISC code. */
e315cd28 836 rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address);
42e421b1
AV		 837 if (rval == QLA_SUCCESS) {
838 /* And, verify we are not in ROM code. */
e315cd28 839 rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa,
42e421b1
AV		 840 &area, &domain, &topo, &sw_cap);
841 }
1da177e4
LT		 842 }
843
7c3df132
SK		 844 if (rval)
845 ql_dbg(ql_dbg_init, vha, 0x007a,
846 "**** Load RISC code ****.\n");
1da177e4
LT		 847
848 return (rval);
849}
850
851/**
852 * qla2x00_reset_chip() - Reset ISP chip.
853 * @ha: HA context
854 *
855 * Returns 0 on success.
856 */
abbd8870 857void
e315cd28 858qla2x00_reset_chip(scsi_qla_host_t *vha)
1da177e4
LT		 859{
860 unsigned long flags = 0;
e315cd28 861 struct qla_hw_data *ha = vha->hw;
3d71644c 862 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 863 uint32_t cnt;
1da177e4
LT		 864 uint16_t cmd;
865
85880801
AV		 866 if (unlikely(pci_channel_offline(ha->pdev)))
867 return;
868
fd34f556 869 ha->isp_ops->disable_intrs(ha);
1da177e4
LT		 870
871 spin_lock_irqsave(&ha->hardware_lock, flags);
872
873 /* Turn off master enable */
874 cmd = 0;
875 pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd);
876 cmd &= ~PCI_COMMAND_MASTER;
877 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
878
879 if (!IS_QLA2100(ha)) {
880 /* Pause RISC. */
881 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
882 if (IS_QLA2200(ha) || IS_QLA2300(ha)) {
883 for (cnt = 0; cnt < 30000; cnt++) {
884 if ((RD_REG_WORD(&reg->hccr) &
885 HCCR_RISC_PAUSE) != 0)
886 break;
887 udelay(100);
888 }
889 } else {
890 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
891 udelay(10);
892 }
893
894 /* Select FPM registers. */
895 WRT_REG_WORD(&reg->ctrl_status, 0x20);
896 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
897
898 /* FPM Soft Reset. */
899 WRT_REG_WORD(&reg->fpm_diag_config, 0x100);
900 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
901
902 /* Toggle Fpm Reset. */
903 if (!IS_QLA2200(ha)) {
904 WRT_REG_WORD(&reg->fpm_diag_config, 0x0);
905 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
906 }
907
908 /* Select frame buffer registers. */
909 WRT_REG_WORD(&reg->ctrl_status, 0x10);
910 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
911
912 /* Reset frame buffer FIFOs. */
913 if (IS_QLA2200(ha)) {
914 WRT_FB_CMD_REG(ha, reg, 0xa000);
915 RD_FB_CMD_REG(ha, reg); /* PCI Posting. */
916 } else {
917 WRT_FB_CMD_REG(ha, reg, 0x00fc);
918
919 /* Read back fb_cmd until zero or 3 seconds max */
920 for (cnt = 0; cnt < 3000; cnt++) {
921 if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0)
922 break;
923 udelay(100);
924 }
925 }
926
927 /* Select RISC module registers. */
928 WRT_REG_WORD(&reg->ctrl_status, 0);
929 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
930
931 /* Reset RISC processor. */
932 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
933 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
934
935 /* Release RISC processor. */
936 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
937 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
938 }
939
940 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
941 WRT_REG_WORD(&reg->hccr, HCCR_CLR_HOST_INT);
942
943 /* Reset ISP chip. */
944 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
945
946 /* Wait for RISC to recover from reset. */
947 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
948 /*
949 * It is necessary to for a delay here since the card doesn't
950 * respond to PCI reads during a reset. On some architectures
951 * this will result in an MCA.
952 */
953 udelay(20);
954 for (cnt = 30000; cnt; cnt--) {
955 if ((RD_REG_WORD(&reg->ctrl_status) &
956 CSR_ISP_SOFT_RESET) == 0)
957 break;
958 udelay(100);
959 }
960 } else
961 udelay(10);
962
963 /* Reset RISC processor. */
964 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
965
966 WRT_REG_WORD(&reg->semaphore, 0);
967
968 /* Release RISC processor. */
969 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
970 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
971
972 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
973 for (cnt = 0; cnt < 30000; cnt++) {
ffb39f03 974 if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY)
1da177e4 975 break;
1da177e4
LT		 976
977 udelay(100);
978 }
979 } else
980 udelay(100);
981
982 /* Turn on master enable */
983 cmd |= PCI_COMMAND_MASTER;
984 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
985
986 /* Disable RISC pause on FPM parity error. */
987 if (!IS_QLA2100(ha)) {
988 WRT_REG_WORD(&reg->hccr, HCCR_DISABLE_PARITY_PAUSE);
989 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
990 }
991
992 spin_unlock_irqrestore(&ha->hardware_lock, flags);
993}
994
b1d46989
MI		 995/**
996 * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC.
997 *
998 * Returns 0 on success.
999 */
fa492630 1000static int
b1d46989
MI		 1001qla81xx_reset_mpi(scsi_qla_host_t *vha)
1002{
1003 uint16_t mb[4] = {0x1010, 0, 1, 0};
1004
6246b8a1
GM		 1005 if (!IS_QLA81XX(vha->hw))
1006 return QLA_SUCCESS;
1007
b1d46989
MI		 1008 return qla81xx_write_mpi_register(vha, mb);
1009}
1010
0107109e 1011/**
88c26663 1012 * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC.
0107109e
AV		 1013 * @ha: HA context
1014 *
1015 * Returns 0 on success.
1016 */
88c26663 1017static inline void
e315cd28 1018qla24xx_reset_risc(scsi_qla_host_t *vha)
0107109e
AV		 1019{
1020 unsigned long flags = 0;
e315cd28 1021 struct qla_hw_data *ha = vha->hw;
0107109e
AV		 1022 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1023 uint32_t cnt, d2;
335a1cc9 1024 uint16_t wd;
b1d46989 1025 static int abts_cnt; /* ISP abort retry counts */
0107109e 1026
0107109e
AV		 1027 spin_lock_irqsave(&ha->hardware_lock, flags);
1028
1029 /* Reset RISC. */
1030 WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
1031 for (cnt = 0; cnt < 30000; cnt++) {
1032 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
1033 break;
1034
1035 udelay(10);
1036 }
1037
1038 WRT_REG_DWORD(&reg->ctrl_status,
1039 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
335a1cc9 1040 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
88c26663 1041
335a1cc9 1042 udelay(100);
88c26663 1043 /* Wait for firmware to complete NVRAM accesses. */
88c26663
AV		 1044 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1045 for (cnt = 10000 ; cnt && d2; cnt--) {
1046 udelay(5);
1047 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1048 barrier();
1049 }
1050
335a1cc9 1051 /* Wait for soft-reset to complete. */
0107109e
AV		 1052 d2 = RD_REG_DWORD(&reg->ctrl_status);
1053 for (cnt = 6000000 ; cnt && (d2 & CSRX_ISP_SOFT_RESET); cnt--) {
1054 udelay(5);
1055 d2 = RD_REG_DWORD(&reg->ctrl_status);
1056 barrier();
1057 }
1058
b1d46989
MI		 1059 /* If required, do an MPI FW reset now */
1060 if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
1061 if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
1062 if (++abts_cnt < 5) {
1063 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1064 set_bit(MPI_RESET_NEEDED, &vha->dpc_flags);
1065 } else {
1066 /*
1067 * We exhausted the ISP abort retries. We have to
1068 * set the board offline.
1069 */
1070 abts_cnt = 0;
1071 vha->flags.online = 0;
1072 }
1073 }
1074 }
1075
0107109e
AV		 1076 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
1077 RD_REG_DWORD(&reg->hccr);
1078
1079 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
1080 RD_REG_DWORD(&reg->hccr);
1081
1082 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
1083 RD_REG_DWORD(&reg->hccr);
1084
1085 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1086 for (cnt = 6000000 ; cnt && d2; cnt--) {
1087 udelay(5);
1088 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1089 barrier();
1090 }
1091
1092 spin_unlock_irqrestore(&ha->hardware_lock, flags);
124f85e6
AV		 1093
1094 if (IS_NOPOLLING_TYPE(ha))
1095 ha->isp_ops->enable_intrs(ha);
0107109e
AV		 1096}
1097
88c26663
AV		 1098/**
1099 * qla24xx_reset_chip() - Reset ISP24xx chip.
1100 * @ha: HA context
1101 *
1102 * Returns 0 on success.
1103 */
1104void
e315cd28 1105qla24xx_reset_chip(scsi_qla_host_t *vha)
88c26663 1106{
e315cd28 1107 struct qla_hw_data *ha = vha->hw;
85880801
AV		 1108
1109 if (pci_channel_offline(ha->pdev) &&
1110 ha->flags.pci_channel_io_perm_failure) {
1111 return;
1112 }
1113
fd34f556 1114 ha->isp_ops->disable_intrs(ha);
88c26663
AV		 1115
1116 /* Perform RISC reset. */
e315cd28 1117 qla24xx_reset_risc(vha);
88c26663
AV		 1118}
1119
1da177e4
LT		 1120/**
1121 * qla2x00_chip_diag() - Test chip for proper operation.
1122 * @ha: HA context
1123 *
1124 * Returns 0 on success.
1125 */
abbd8870 1126int
e315cd28 1127qla2x00_chip_diag(scsi_qla_host_t *vha)
1da177e4
LT		 1128{
1129 int rval;
e315cd28 1130 struct qla_hw_data *ha = vha->hw;
3d71644c 1131 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 1132 unsigned long flags = 0;
1133 uint16_t data;
1134 uint32_t cnt;
1135 uint16_t mb[5];
73208dfd 1136 struct req_que *req = ha->req_q_map[0];
1da177e4
LT		 1137
1138 /* Assume a failed state */
1139 rval = QLA_FUNCTION_FAILED;
1140
7c3df132
SK		 1141 ql_dbg(ql_dbg_init, vha, 0x007b,
1142 "Testing device at %lx.\n", (u_long)&reg->flash_address);
1da177e4
LT		 1143
1144 spin_lock_irqsave(&ha->hardware_lock, flags);
1145
1146 /* Reset ISP chip. */
1147 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1148
1149 /*
1150 * We need to have a delay here since the card will not respond while
1151 * in reset causing an MCA on some architectures.
1152 */
1153 udelay(20);
1154 data = qla2x00_debounce_register(&reg->ctrl_status);
1155 for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {
1156 udelay(5);
1157 data = RD_REG_WORD(&reg->ctrl_status);
1158 barrier();
1159 }
1160
1161 if (!cnt)
1162 goto chip_diag_failed;
1163
7c3df132
SK		 1164 ql_dbg(ql_dbg_init, vha, 0x007c,
1165 "Reset register cleared by chip reset.\n");
1da177e4
LT		 1166
1167 /* Reset RISC processor. */
1168 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
1169 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
1170
1171 /* Workaround for QLA2312 PCI parity error */
1172 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1173 data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0));
1174 for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) {
1175 udelay(5);
1176 data = RD_MAILBOX_REG(ha, reg, 0);
fa2a1ce5 1177 barrier();
1da177e4
LT		 1178 }
1179 } else
1180 udelay(10);
1181
1182 if (!cnt)
1183 goto chip_diag_failed;
1184
1185 /* Check product ID of chip */
7c3df132 1186 ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product Id of chip.\n");
1da177e4
LT		 1187
1188 mb[1] = RD_MAILBOX_REG(ha, reg, 1);
1189 mb[2] = RD_MAILBOX_REG(ha, reg, 2);
1190 mb[3] = RD_MAILBOX_REG(ha, reg, 3);
1191 mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4));
1192 if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) ||
1193 mb[3] != PROD_ID_3) {
7c3df132
SK		 1194 ql_log(ql_log_warn, vha, 0x0062,
1195 "Wrong product ID = 0x%x,0x%x,0x%x.\n",
1196 mb[1], mb[2], mb[3]);
1da177e4
LT		 1197
1198 goto chip_diag_failed;
1199 }
1200 ha->product_id[0] = mb[1];
1201 ha->product_id[1] = mb[2];
1202 ha->product_id[2] = mb[3];
1203 ha->product_id[3] = mb[4];
1204
1205 /* Adjust fw RISC transfer size */
73208dfd 1206 if (req->length > 1024)
1da177e4
LT		 1207 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024;
1208 else
1209 ha->fw_transfer_size = REQUEST_ENTRY_SIZE *
73208dfd 1210 req->length;
1da177e4
LT		 1211
1212 if (IS_QLA2200(ha) &&
1213 RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) {
1214 /* Limit firmware transfer size with a 2200A */
7c3df132 1215 ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n");
1da177e4 1216
ea5b6382 1217 ha->device_type |= DT_ISP2200A;
1da177e4
LT		 1218 ha->fw_transfer_size = 128;
1219 }
1220
1221 /* Wrap Incoming Mailboxes Test. */
1222 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1223
7c3df132 1224 ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n");
e315cd28 1225 rval = qla2x00_mbx_reg_test(vha);
7c3df132
SK		 1226 if (rval)
1227 ql_log(ql_log_warn, vha, 0x0080,
1228 "Failed mailbox send register test.\n");
1229 else
1da177e4
LT		 1230 /* Flag a successful rval */
1231 rval = QLA_SUCCESS;
1da177e4
LT		 1232 spin_lock_irqsave(&ha->hardware_lock, flags);
1233
1234chip_diag_failed:
1235 if (rval)
7c3df132
SK		 1236 ql_log(ql_log_info, vha, 0x0081,
1237 "Chip diagnostics **** FAILED ****.\n");
1da177e4
LT		 1238
1239 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1240
1241 return (rval);
1242}
1243
0107109e
AV		 1244/**
1245 * qla24xx_chip_diag() - Test ISP24xx for proper operation.
1246 * @ha: HA context
1247 *
1248 * Returns 0 on success.
1249 */
1250int
e315cd28 1251qla24xx_chip_diag(scsi_qla_host_t *vha)
0107109e
AV		 1252{
1253 int rval;
e315cd28 1254 struct qla_hw_data *ha = vha->hw;
73208dfd 1255 struct req_que *req = ha->req_q_map[0];
0107109e 1256
a9083016
GM		 1257 if (IS_QLA82XX(ha))
1258 return QLA_SUCCESS;
1259
73208dfd 1260 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
0107109e 1261
e315cd28 1262 rval = qla2x00_mbx_reg_test(vha);
0107109e 1263 if (rval) {
7c3df132
SK		 1264 ql_log(ql_log_warn, vha, 0x0082,
1265 "Failed mailbox send register test.\n");
0107109e
AV		 1266 } else {
1267 /* Flag a successful rval */
1268 rval = QLA_SUCCESS;
1269 }
1270
1271 return rval;
1272}
1273
a7a167bf 1274void
e315cd28 1275qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
0107109e 1276{
a7a167bf
AV		 1277 int rval;
1278 uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
73208dfd 1279 eft_size, fce_size, mq_size;
df613b96
AV		 1280 dma_addr_t tc_dma;
1281 void *tc;
e315cd28 1282 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 1283 struct req_que *req = ha->req_q_map[0];
1284 struct rsp_que *rsp = ha->rsp_q_map[0];
a7a167bf
AV		 1285
1286 if (ha->fw_dump) {
7c3df132
SK		 1287 ql_dbg(ql_dbg_init, vha, 0x00bd,
1288 "Firmware dump already allocated.\n");
a7a167bf
AV		 1289 return;
1290 }
d4e3e04d 1291
0107109e 1292 ha->fw_dumped = 0;
73208dfd 1293 fixed_size = mem_size = eft_size = fce_size = mq_size = 0;
d4e3e04d 1294 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
a7a167bf 1295 fixed_size = sizeof(struct qla2100_fw_dump);
d4e3e04d 1296 } else if (IS_QLA23XX(ha)) {
a7a167bf
AV		 1297 fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
1298 mem_size = (ha->fw_memory_size - 0x11000 + 1) *
1299 sizeof(uint16_t);
e428924c 1300 } else if (IS_FWI2_CAPABLE(ha)) {
6246b8a1
GM		 1301 if (IS_QLA83XX(ha))
1302 fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem);
1303 else if (IS_QLA81XX(ha))
3a03eb79
AV		 1304 fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
1305 else if (IS_QLA25XX(ha))
1306 fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
1307 else
1308 fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
a7a167bf
AV		 1309 mem_size = (ha->fw_memory_size - 0x100000 + 1) *
1310 sizeof(uint32_t);
050c9bb1 1311 if (ha->mqenable) {
6246b8a1
GM		 1312 if (!IS_QLA83XX(ha))
1313 mq_size = sizeof(struct qla2xxx_mq_chain);
050c9bb1
GM		 1314 /*
1315 * Allocate maximum buffer size for all queues.
1316 * Resizing must be done at end-of-dump processing.
1317 */
1318 mq_size += ha->max_req_queues *
1319 (req->length * sizeof(request_t));
1320 mq_size += ha->max_rsp_queues *
1321 (rsp->length * sizeof(response_t));
1322 }
2d70c103
NB		 1323 if (ha->tgt.atio_q_length)
1324 mq_size += ha->tgt.atio_q_length * sizeof(request_t);
df613b96 1325 /* Allocate memory for Fibre Channel Event Buffer. */
6246b8a1 1326 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha))
436a7b11 1327 goto try_eft;
df613b96
AV		 1328
1329 tc = dma_alloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
1330 GFP_KERNEL);
1331 if (!tc) {
7c3df132
SK		 1332 ql_log(ql_log_warn, vha, 0x00be,
1333 "Unable to allocate (%d KB) for FCE.\n",
1334 FCE_SIZE / 1024);
17d98630 1335 goto try_eft;
df613b96
AV		 1336 }
1337
1338 memset(tc, 0, FCE_SIZE);
e315cd28 1339 rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS,
df613b96
AV		 1340 ha->fce_mb, &ha->fce_bufs);
1341 if (rval) {
7c3df132
SK		 1342 ql_log(ql_log_warn, vha, 0x00bf,
1343 "Unable to initialize FCE (%d).\n", rval);
df613b96
AV		 1344 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc,
1345 tc_dma);
1346 ha->flags.fce_enabled = 0;
17d98630 1347 goto try_eft;
df613b96 1348 }
cfb0919c 1349 ql_dbg(ql_dbg_init, vha, 0x00c0,
7c3df132 1350 "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024);
df613b96 1351
7d9dade3 1352 fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE;
df613b96
AV		 1353 ha->flags.fce_enabled = 1;
1354 ha->fce_dma = tc_dma;
1355 ha->fce = tc;
436a7b11
AV		 1356try_eft:
1357 /* Allocate memory for Extended Trace Buffer. */
1358 tc = dma_alloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
1359 GFP_KERNEL);
1360 if (!tc) {
7c3df132
SK		 1361 ql_log(ql_log_warn, vha, 0x00c1,
1362 "Unable to allocate (%d KB) for EFT.\n",
1363 EFT_SIZE / 1024);
436a7b11
AV		 1364 goto cont_alloc;
1365 }
1366
1367 memset(tc, 0, EFT_SIZE);
e315cd28 1368 rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
436a7b11 1369 if (rval) {
7c3df132
SK		 1370 ql_log(ql_log_warn, vha, 0x00c2,
1371 "Unable to initialize EFT (%d).\n", rval);
436a7b11
AV		 1372 dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc,
1373 tc_dma);
1374 goto cont_alloc;
1375 }
cfb0919c 1376 ql_dbg(ql_dbg_init, vha, 0x00c3,
7c3df132 1377 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
436a7b11
AV		 1378
1379 eft_size = EFT_SIZE;
1380 ha->eft_dma = tc_dma;
1381 ha->eft = tc;
d4e3e04d 1382 }
a7a167bf 1383cont_alloc:
73208dfd
AC		 1384 req_q_size = req->length * sizeof(request_t);
1385 rsp_q_size = rsp->length * sizeof(response_t);
a7a167bf
AV		 1386
1387 dump_size = offsetof(struct qla2xxx_fw_dump, isp);
2afa19a9 1388 dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size;
bb99de67
AV		 1389 ha->chain_offset = dump_size;
1390 dump_size += mq_size + fce_size;
d4e3e04d
AV		 1391
1392 ha->fw_dump = vmalloc(dump_size);
a7a167bf 1393 if (!ha->fw_dump) {
7c3df132
SK		 1394 ql_log(ql_log_warn, vha, 0x00c4,
1395 "Unable to allocate (%d KB) for firmware dump.\n",
1396 dump_size / 1024);
a7a167bf 1397
e30d1756
MI		 1398 if (ha->fce) {
1399 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
1400 ha->fce_dma);
1401 ha->fce = NULL;
1402 ha->fce_dma = 0;
1403 }
1404
a7a167bf
AV		 1405 if (ha->eft) {
1406 dma_free_coherent(&ha->pdev->dev, eft_size, ha->eft,
1407 ha->eft_dma);
1408 ha->eft = NULL;
1409 ha->eft_dma = 0;
1410 }
1411 return;
1412 }
cfb0919c 1413 ql_dbg(ql_dbg_init, vha, 0x00c5,
7c3df132 1414 "Allocated (%d KB) for firmware dump.\n", dump_size / 1024);
a7a167bf
AV		 1415
1416 ha->fw_dump_len = dump_size;
1417 ha->fw_dump->signature[0] = 'Q';
1418 ha->fw_dump->signature[1] = 'L';
1419 ha->fw_dump->signature[2] = 'G';
1420 ha->fw_dump->signature[3] = 'C';
1421 ha->fw_dump->version = __constant_htonl(1);
1422
1423 ha->fw_dump->fixed_size = htonl(fixed_size);
1424 ha->fw_dump->mem_size = htonl(mem_size);
1425 ha->fw_dump->req_q_size = htonl(req_q_size);
1426 ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
1427
1428 ha->fw_dump->eft_size = htonl(eft_size);
1429 ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma));
1430 ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma));
1431
1432 ha->fw_dump->header_size =
1433 htonl(offsetof(struct qla2xxx_fw_dump, isp));
0107109e
AV		 1434}
1435
18e7555a
AV		 1436static int
1437qla81xx_mpi_sync(scsi_qla_host_t *vha)
1438{
1439#define MPS_MASK 0xe0
1440 int rval;
1441 uint16_t dc;
1442 uint32_t dw;
18e7555a
AV		 1443
1444 if (!IS_QLA81XX(vha->hw))
1445 return QLA_SUCCESS;
1446
1447 rval = qla2x00_write_ram_word(vha, 0x7c00, 1);
1448 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1449 ql_log(ql_log_warn, vha, 0x0105,
1450 "Unable to acquire semaphore.\n");
18e7555a
AV		 1451 goto done;
1452 }
1453
1454 pci_read_config_word(vha->hw->pdev, 0x54, &dc);
1455 rval = qla2x00_read_ram_word(vha, 0x7a15, &dw);
1456 if (rval != QLA_SUCCESS) {
7c3df132 1457 ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n");
18e7555a
AV		 1458 goto done_release;
1459 }
1460
1461 dc &= MPS_MASK;
1462 if (dc == (dw & MPS_MASK))
1463 goto done_release;
1464
1465 dw &= ~MPS_MASK;
1466 dw |= dc;
1467 rval = qla2x00_write_ram_word(vha, 0x7a15, dw);
1468 if (rval != QLA_SUCCESS) {
7c3df132 1469 ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n");
18e7555a
AV		 1470 }
1471
1472done_release:
1473 rval = qla2x00_write_ram_word(vha, 0x7c00, 0);
1474 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1475 ql_log(ql_log_warn, vha, 0x006d,
1476 "Unable to release semaphore.\n");
18e7555a
AV		 1477 }
1478
1479done:
1480 return rval;
1481}
1482
1da177e4
LT		 1483/**
1484 * qla2x00_setup_chip() - Load and start RISC firmware.
1485 * @ha: HA context
1486 *
1487 * Returns 0 on success.
1488 */
1489static int
e315cd28 1490qla2x00_setup_chip(scsi_qla_host_t *vha)
1da177e4 1491{
0107109e
AV		 1492 int rval;
1493 uint32_t srisc_address = 0;
e315cd28 1494 struct qla_hw_data *ha = vha->hw;
3db0652e
AV		 1495 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1496 unsigned long flags;
dda772e8 1497 uint16_t fw_major_version;
3db0652e 1498
a9083016
GM		 1499 if (IS_QLA82XX(ha)) {
1500 rval = ha->isp_ops->load_risc(vha, &srisc_address);
14e303d9
AV		 1501 if (rval == QLA_SUCCESS) {
1502 qla2x00_stop_firmware(vha);
a9083016 1503 goto enable_82xx_npiv;
14e303d9 1504 } else
b963752f 1505 goto failed;
a9083016
GM		 1506 }
1507
3db0652e
AV		 1508 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1509 /* Disable SRAM, Instruction RAM and GP RAM parity. */
1510 spin_lock_irqsave(&ha->hardware_lock, flags);
1511 WRT_REG_WORD(&reg->hccr, (HCCR_ENABLE_PARITY + 0x0));
1512 RD_REG_WORD(&reg->hccr);
1513 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1514 }
1da177e4 1515
18e7555a
AV		 1516 qla81xx_mpi_sync(vha);
1517
1da177e4 1518 /* Load firmware sequences */
e315cd28 1519 rval = ha->isp_ops->load_risc(vha, &srisc_address);
0107109e 1520 if (rval == QLA_SUCCESS) {
7c3df132
SK		 1521 ql_dbg(ql_dbg_init, vha, 0x00c9,
1522 "Verifying Checksum of loaded RISC code.\n");
1da177e4 1523
e315cd28 1524 rval = qla2x00_verify_checksum(vha, srisc_address);
1da177e4
LT		 1525 if (rval == QLA_SUCCESS) {
1526 /* Start firmware execution. */
7c3df132
SK		 1527 ql_dbg(ql_dbg_init, vha, 0x00ca,
1528 "Starting firmware.\n");
1da177e4 1529
e315cd28 1530 rval = qla2x00_execute_fw(vha, srisc_address);
1da177e4 1531 /* Retrieve firmware information. */
dda772e8 1532 if (rval == QLA_SUCCESS) {
a9083016 1533enable_82xx_npiv:
dda772e8 1534 fw_major_version = ha->fw_major_version;
3173167f
GM		 1535 if (IS_QLA82XX(ha))
1536 qla82xx_check_md_needed(vha);
6246b8a1
GM		 1537 else
1538 rval = qla2x00_get_fw_version(vha);
ca9e9c3e
AV		 1539 if (rval != QLA_SUCCESS)
1540 goto failed;
2c3dfe3f 1541 ha->flags.npiv_supported = 0;
e315cd28 1542 if (IS_QLA2XXX_MIDTYPE(ha) &&
946fb891 1543 (ha->fw_attributes & BIT_2)) {
2c3dfe3f 1544 ha->flags.npiv_supported = 1;
4d0ea247
SJ		 1545 if ((!ha->max_npiv_vports) ||
1546 ((ha->max_npiv_vports + 1) %
eb66dc60 1547 MIN_MULTI_ID_FABRIC))
4d0ea247 1548 ha->max_npiv_vports =
eb66dc60 1549 MIN_MULTI_ID_FABRIC - 1;
4d0ea247 1550 }
24a08138
AV		 1551 qla2x00_get_resource_cnts(vha, NULL,
1552 &ha->fw_xcb_count, NULL, NULL,
f3a0a77e 1553 &ha->max_npiv_vports, NULL);
d743de66 1554
be5ea3cf
SK		 1555 if (!fw_major_version && ql2xallocfwdump
1556 && !IS_QLA82XX(ha))
08de2844 1557 qla2x00_alloc_fw_dump(vha);
1da177e4
LT		 1558 }
1559 } else {
7c3df132
SK		 1560 ql_log(ql_log_fatal, vha, 0x00cd,
1561 "ISP Firmware failed checksum.\n");
1562 goto failed;
1da177e4 1563 }
c74d88a4
AV		 1564 } else
1565 goto failed;
1da177e4 1566
3db0652e
AV		 1567 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1568 /* Enable proper parity. */
1569 spin_lock_irqsave(&ha->hardware_lock, flags);
1570 if (IS_QLA2300(ha))
1571 /* SRAM parity */
1572 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x1);
1573 else
1574 /* SRAM, Instruction RAM and GP RAM parity */
1575 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x7);
1576 RD_REG_WORD(&reg->hccr);
1577 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1578 }
1579
6246b8a1
GM		 1580 if (IS_QLA83XX(ha))
1581 goto skip_fac_check;
1582
1d2874de
JC		 1583 if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
1584 uint32_t size;
1585
1586 rval = qla81xx_fac_get_sector_size(vha, &size);
1587 if (rval == QLA_SUCCESS) {
1588 ha->flags.fac_supported = 1;
1589 ha->fdt_block_size = size << 2;
1590 } else {
7c3df132 1591 ql_log(ql_log_warn, vha, 0x00ce,
1d2874de
JC		 1592 "Unsupported FAC firmware (%d.%02d.%02d).\n",
1593 ha->fw_major_version, ha->fw_minor_version,
1594 ha->fw_subminor_version);
6246b8a1
GM		 1595skip_fac_check:
1596 if (IS_QLA83XX(ha)) {
1597 ha->flags.fac_supported = 0;
1598 rval = QLA_SUCCESS;
1599 }
1d2874de
JC		 1600 }
1601 }
ca9e9c3e 1602failed:
1da177e4 1603 if (rval) {
7c3df132
SK		 1604 ql_log(ql_log_fatal, vha, 0x00cf,
1605 "Setup chip ****FAILED****.\n");
1da177e4
LT		 1606 }
1607
1608 return (rval);
1609}
1610
1611/**
1612 * qla2x00_init_response_q_entries() - Initializes response queue entries.
1613 * @ha: HA context
1614 *
1615 * Beginning of request ring has initialization control block already built
1616 * by nvram config routine.
1617 *
1618 * Returns 0 on success.
1619 */
73208dfd
AC		 1620void
1621qla2x00_init_response_q_entries(struct rsp_que *rsp)
1da177e4
LT		 1622{
1623 uint16_t cnt;
1624 response_t *pkt;
1625
2afa19a9
AC		 1626 rsp->ring_ptr = rsp->ring;
1627 rsp->ring_index = 0;
1628 rsp->status_srb = NULL;
e315cd28
AC		 1629 pkt = rsp->ring_ptr;
1630 for (cnt = 0; cnt < rsp->length; cnt++) {
1da177e4
LT		 1631 pkt->signature = RESPONSE_PROCESSED;
1632 pkt++;
1633 }
1da177e4
LT		 1634}
1635
1636/**
1637 * qla2x00_update_fw_options() - Read and process firmware options.
1638 * @ha: HA context
1639 *
1640 * Returns 0 on success.
1641 */
abbd8870 1642void
e315cd28 1643qla2x00_update_fw_options(scsi_qla_host_t *vha)
1da177e4
LT		 1644{
1645 uint16_t swing, emphasis, tx_sens, rx_sens;
e315cd28 1646 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 1647
1648 memset(ha->fw_options, 0, sizeof(ha->fw_options));
e315cd28 1649 qla2x00_get_fw_options(vha, ha->fw_options);
1da177e4
LT		 1650
1651 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1652 return;
1653
1654 /* Serial Link options. */
7c3df132
SK		 1655 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
1656 "Serial link options.\n");
1657 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
1658 (uint8_t *)&ha->fw_seriallink_options,
1659 sizeof(ha->fw_seriallink_options));
1da177e4
LT		 1660
1661 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1662 if (ha->fw_seriallink_options[3] & BIT_2) {
1663 ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING;
1664
1665 /* 1G settings */
1666 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
1667 emphasis = (ha->fw_seriallink_options[2] &
1668 (BIT_4 | BIT_3)) >> 3;
1669 tx_sens = ha->fw_seriallink_options[0] &
fa2a1ce5 1670 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 1671 rx_sens = (ha->fw_seriallink_options[0] &
1672 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
1673 ha->fw_options[10] = (emphasis << 14) | (swing << 8);
1674 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
1675 if (rx_sens == 0x0)
1676 rx_sens = 0x3;
1677 ha->fw_options[10] |= (tx_sens << 4) | rx_sens;
1678 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
1679 ha->fw_options[10] |= BIT_5 |
1680 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
1681 (tx_sens & (BIT_1 | BIT_0));
1682
1683 /* 2G settings */
1684 swing = (ha->fw_seriallink_options[2] &
1685 (BIT_7 | BIT_6 | BIT_5)) >> 5;
1686 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
1687 tx_sens = ha->fw_seriallink_options[1] &
fa2a1ce5 1688 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 1689 rx_sens = (ha->fw_seriallink_options[1] &
1690 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
1691 ha->fw_options[11] = (emphasis << 14) | (swing << 8);
1692 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
1693 if (rx_sens == 0x0)
1694 rx_sens = 0x3;
1695 ha->fw_options[11] |= (tx_sens << 4) | rx_sens;
1696 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
1697 ha->fw_options[11] |= BIT_5 |
1698 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
1699 (tx_sens & (BIT_1 | BIT_0));
1700 }
1701
1702 /* FCP2 options. */
1703 /* Return command IOCBs without waiting for an ABTS to complete. */
1704 ha->fw_options[3] |= BIT_13;
1705
1706 /* LED scheme. */
1707 if (ha->flags.enable_led_scheme)
1708 ha->fw_options[2] |= BIT_12;
1709
48c02fde
AV		 1710 /* Detect ISP6312. */
1711 if (IS_QLA6312(ha))
1712 ha->fw_options[2] |= BIT_13;
1713
1da177e4 1714 /* Update firmware options. */
e315cd28 1715 qla2x00_set_fw_options(vha, ha->fw_options);
1da177e4
LT		 1716}
1717
0107109e 1718void
e315cd28 1719qla24xx_update_fw_options(scsi_qla_host_t *vha)
0107109e
AV		 1720{
1721 int rval;
e315cd28 1722 struct qla_hw_data *ha = vha->hw;
0107109e 1723
a9083016
GM		 1724 if (IS_QLA82XX(ha))
1725 return;
1726
0107109e 1727 /* Update Serial Link options. */
f94097ed 1728 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0)
0107109e
AV		 1729 return;
1730
e315cd28 1731 rval = qla2x00_set_serdes_params(vha,
f94097ed
AV		 1732 le16_to_cpu(ha->fw_seriallink_options24[1]),
1733 le16_to_cpu(ha->fw_seriallink_options24[2]),
1734 le16_to_cpu(ha->fw_seriallink_options24[3]));
0107109e 1735 if (rval != QLA_SUCCESS) {
7c3df132 1736 ql_log(ql_log_warn, vha, 0x0104,
0107109e
AV		 1737 "Unable to update Serial Link options (%x).\n", rval);
1738 }
1739}
1740
abbd8870 1741void
e315cd28 1742qla2x00_config_rings(struct scsi_qla_host *vha)
abbd8870 1743{
e315cd28 1744 struct qla_hw_data *ha = vha->hw;
3d71644c 1745 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
73208dfd
AC		 1746 struct req_que *req = ha->req_q_map[0];
1747 struct rsp_que *rsp = ha->rsp_q_map[0];
abbd8870
AV		 1748
1749 /* Setup ring parameters in initialization control block. */
1750 ha->init_cb->request_q_outpointer = __constant_cpu_to_le16(0);
1751 ha->init_cb->response_q_inpointer = __constant_cpu_to_le16(0);
e315cd28
AC		 1752 ha->init_cb->request_q_length = cpu_to_le16(req->length);
1753 ha->init_cb->response_q_length = cpu_to_le16(rsp->length);
1754 ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
1755 ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
1756 ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
1757 ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
abbd8870
AV		 1758
1759 WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0);
1760 WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0);
1761 WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0);
1762 WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0);
1763 RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */
1764}
1765
0107109e 1766void
e315cd28 1767qla24xx_config_rings(struct scsi_qla_host *vha)
0107109e 1768{
e315cd28 1769 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 1770 device_reg_t __iomem *reg = ISP_QUE_REG(ha, 0);
1771 struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
1772 struct qla_msix_entry *msix;
0107109e 1773 struct init_cb_24xx *icb;
73208dfd
AC		 1774 uint16_t rid = 0;
1775 struct req_que *req = ha->req_q_map[0];
1776 struct rsp_que *rsp = ha->rsp_q_map[0];
0107109e 1777
6246b8a1 1778 /* Setup ring parameters in initialization control block. */
0107109e
AV		 1779 icb = (struct init_cb_24xx *)ha->init_cb;
1780 icb->request_q_outpointer = __constant_cpu_to_le16(0);
1781 icb->response_q_inpointer = __constant_cpu_to_le16(0);
e315cd28
AC		 1782 icb->request_q_length = cpu_to_le16(req->length);
1783 icb->response_q_length = cpu_to_le16(rsp->length);
1784 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
1785 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
1786 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
1787 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
0107109e 1788
2d70c103
NB		 1789 /* Setup ATIO queue dma pointers for target mode */
1790 icb->atio_q_inpointer = __constant_cpu_to_le16(0);
1791 icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length);
1792 icb->atio_q_address[0] = cpu_to_le32(LSD(ha->tgt.atio_dma));
1793 icb->atio_q_address[1] = cpu_to_le32(MSD(ha->tgt.atio_dma));
1794
6246b8a1 1795 if (ha->mqenable || IS_QLA83XX(ha)) {
73208dfd
AC		 1796 icb->qos = __constant_cpu_to_le16(QLA_DEFAULT_QUE_QOS);
1797 icb->rid = __constant_cpu_to_le16(rid);
1798 if (ha->flags.msix_enabled) {
1799 msix = &ha->msix_entries[1];
7c3df132
SK		 1800 ql_dbg(ql_dbg_init, vha, 0x00fd,
1801 "Registering vector 0x%x for base que.\n",
1802 msix->entry);
73208dfd
AC		 1803 icb->msix = cpu_to_le16(msix->entry);
1804 }
1805 /* Use alternate PCI bus number */
1806 if (MSB(rid))
1807 icb->firmware_options_2 |=
1808 __constant_cpu_to_le32(BIT_19);
1809 /* Use alternate PCI devfn */
1810 if (LSB(rid))
1811 icb->firmware_options_2 |=
1812 __constant_cpu_to_le32(BIT_18);
1813
3155754a 1814 /* Use Disable MSIX Handshake mode for capable adapters */
6246b8a1
GM		 1815 if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) &&
1816 (ha->flags.msix_enabled)) {
3155754a
AC		 1817 icb->firmware_options_2 &=
1818 __constant_cpu_to_le32(~BIT_22);
1819 ha->flags.disable_msix_handshake = 1;
7c3df132
SK		 1820 ql_dbg(ql_dbg_init, vha, 0x00fe,
1821 "MSIX Handshake Disable Mode turned on.\n");
3155754a
AC		 1822 } else {
1823 icb->firmware_options_2 |=
1824 __constant_cpu_to_le32(BIT_22);
1825 }
73208dfd 1826 icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_23);
73208dfd
AC		 1827
1828 WRT_REG_DWORD(&reg->isp25mq.req_q_in, 0);
1829 WRT_REG_DWORD(&reg->isp25mq.req_q_out, 0);
1830 WRT_REG_DWORD(&reg->isp25mq.rsp_q_in, 0);
1831 WRT_REG_DWORD(&reg->isp25mq.rsp_q_out, 0);
1832 } else {
1833 WRT_REG_DWORD(&reg->isp24.req_q_in, 0);
1834 WRT_REG_DWORD(&reg->isp24.req_q_out, 0);
1835 WRT_REG_DWORD(&reg->isp24.rsp_q_in, 0);
1836 WRT_REG_DWORD(&reg->isp24.rsp_q_out, 0);
1837 }
2d70c103
NB		 1838 qlt_24xx_config_rings(vha, reg);
1839
73208dfd
AC		 1840 /* PCI posting */
1841 RD_REG_DWORD(&ioreg->hccr);
0107109e
AV		 1842}
1843
1da177e4
LT		 1844/**
1845 * qla2x00_init_rings() - Initializes firmware.
1846 * @ha: HA context
1847 *
1848 * Beginning of request ring has initialization control block already built
1849 * by nvram config routine.
1850 *
1851 * Returns 0 on success.
1852 */
1853static int
e315cd28 1854qla2x00_init_rings(scsi_qla_host_t *vha)
1da177e4
LT		 1855{
1856 int rval;
1857 unsigned long flags = 0;
29bdccbe 1858 int cnt, que;
e315cd28 1859 struct qla_hw_data *ha = vha->hw;
29bdccbe
AC		 1860 struct req_que *req;
1861 struct rsp_que *rsp;
2c3dfe3f
SJ		 1862 struct mid_init_cb_24xx *mid_init_cb =
1863 (struct mid_init_cb_24xx *) ha->init_cb;
1da177e4
LT		 1864
1865 spin_lock_irqsave(&ha->hardware_lock, flags);
1866
1867 /* Clear outstanding commands array. */
2afa19a9 1868 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe
AC		 1869 req = ha->req_q_map[que];
1870 if (!req)
1871 continue;
2afa19a9 1872 for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++)
29bdccbe 1873 req->outstanding_cmds[cnt] = NULL;
1da177e4 1874
2afa19a9 1875 req->current_outstanding_cmd = 1;
1da177e4 1876
29bdccbe
AC		 1877 /* Initialize firmware. */
1878 req->ring_ptr = req->ring;
1879 req->ring_index = 0;
1880 req->cnt = req->length;
1881 }
1da177e4 1882
2afa19a9 1883 for (que = 0; que < ha->max_rsp_queues; que++) {
29bdccbe
AC		 1884 rsp = ha->rsp_q_map[que];
1885 if (!rsp)
1886 continue;
29bdccbe
AC		 1887 /* Initialize response queue entries */
1888 qla2x00_init_response_q_entries(rsp);
1889 }
1da177e4 1890
2d70c103
NB		 1891 ha->tgt.atio_ring_ptr = ha->tgt.atio_ring;
1892 ha->tgt.atio_ring_index = 0;
1893 /* Initialize ATIO queue entries */
1894 qlt_init_atio_q_entries(vha);
1895
e315cd28 1896 ha->isp_ops->config_rings(vha);
1da177e4
LT		 1897
1898 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1899
1900 /* Update any ISP specific firmware options before initialization. */
e315cd28 1901 ha->isp_ops->update_fw_options(vha);
1da177e4 1902
7c3df132 1903 ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n");
2c3dfe3f 1904
605aa2bc 1905 if (ha->flags.npiv_supported) {
45980cc2 1906 if (ha->operating_mode == LOOP && !IS_CNA_CAPABLE(ha))
605aa2bc 1907 ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
c48339de 1908 mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
605aa2bc
LC		 1909 }
1910
24a08138
AV		 1911 if (IS_FWI2_CAPABLE(ha)) {
1912 mid_init_cb->options = __constant_cpu_to_le16(BIT_1);
1913 mid_init_cb->init_cb.execution_throttle =
1914 cpu_to_le16(ha->fw_xcb_count);
1915 }
2c3dfe3f 1916
e315cd28 1917 rval = qla2x00_init_firmware(vha, ha->init_cb_size);
1da177e4 1918 if (rval) {
7c3df132
SK		 1919 ql_log(ql_log_fatal, vha, 0x00d2,
1920 "Init Firmware **** FAILED ****.\n");
1da177e4 1921 } else {
7c3df132
SK		 1922 ql_dbg(ql_dbg_init, vha, 0x00d3,
1923 "Init Firmware -- success.\n");
1da177e4
LT		 1924 }
1925
1926 return (rval);
1927}
1928
1929/**
1930 * qla2x00_fw_ready() - Waits for firmware ready.
1931 * @ha: HA context
1932 *
1933 * Returns 0 on success.
1934 */
1935static int
e315cd28 1936qla2x00_fw_ready(scsi_qla_host_t *vha)
1da177e4
LT		 1937{
1938 int rval;
4d4df193 1939 unsigned long wtime, mtime, cs84xx_time;
1da177e4
LT		 1940 uint16_t min_wait; /* Minimum wait time if loop is down */
1941 uint16_t wait_time; /* Wait time if loop is coming ready */
656e8912 1942 uint16_t state[5];
e315cd28 1943 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 1944
1945 rval = QLA_SUCCESS;
1946
1947 /* 20 seconds for loop down. */
fa2a1ce5 1948 min_wait = 20;
1da177e4
LT		 1949
1950 /*
1951 * Firmware should take at most one RATOV to login, plus 5 seconds for
1952 * our own processing.
1953 */
1954 if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) {
1955 wait_time = min_wait;
1956 }
1957
1958 /* Min wait time if loop down */
1959 mtime = jiffies + (min_wait * HZ);
1960
1961 /* wait time before firmware ready */
1962 wtime = jiffies + (wait_time * HZ);
1963
1964 /* Wait for ISP to finish LIP */
e315cd28 1965 if (!vha->flags.init_done)
7c3df132
SK		 1966 ql_log(ql_log_info, vha, 0x801e,
1967 "Waiting for LIP to complete.\n");
1da177e4
LT		 1968
1969 do {
5b939038 1970 memset(state, -1, sizeof(state));
e315cd28 1971 rval = qla2x00_get_firmware_state(vha, state);
1da177e4 1972 if (rval == QLA_SUCCESS) {
4d4df193 1973 if (state[0] < FSTATE_LOSS_OF_SYNC) {
e315cd28 1974 vha->device_flags &= ~DFLG_NO_CABLE;
1da177e4 1975 }
4d4df193 1976 if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) {
7c3df132
SK		 1977 ql_dbg(ql_dbg_taskm, vha, 0x801f,
1978 "fw_state=%x 84xx=%x.\n", state[0],
1979 state[2]);
4d4df193
HK		 1980 if ((state[2] & FSTATE_LOGGED_IN) &&
1981 (state[2] & FSTATE_WAITING_FOR_VERIFY)) {
7c3df132
SK		 1982 ql_dbg(ql_dbg_taskm, vha, 0x8028,
1983 "Sending verify iocb.\n");
4d4df193
HK		 1984
1985 cs84xx_time = jiffies;
e315cd28 1986 rval = qla84xx_init_chip(vha);
7c3df132
SK		 1987 if (rval != QLA_SUCCESS) {
1988 ql_log(ql_log_warn,
cfb0919c 1989 vha, 0x8007,
7c3df132 1990 "Init chip failed.\n");
4d4df193 1991 break;
7c3df132 1992 }
4d4df193
HK		 1993
1994 /* Add time taken to initialize. */
1995 cs84xx_time = jiffies - cs84xx_time;
1996 wtime += cs84xx_time;
1997 mtime += cs84xx_time;
cfb0919c 1998 ql_dbg(ql_dbg_taskm, vha, 0x8008,
7c3df132
SK		 1999 "Increasing wait time by %ld. "
2000 "New time %ld.\n", cs84xx_time,
2001 wtime);
4d4df193
HK		 2002 }
2003 } else if (state[0] == FSTATE_READY) {
7c3df132
SK		 2004 ql_dbg(ql_dbg_taskm, vha, 0x8037,
2005 "F/W Ready - OK.\n");
1da177e4 2006
e315cd28 2007 qla2x00_get_retry_cnt(vha, &ha->retry_count,
1da177e4
LT		 2008 &ha->login_timeout, &ha->r_a_tov);
2009
2010 rval = QLA_SUCCESS;
2011 break;
2012 }
2013
2014 rval = QLA_FUNCTION_FAILED;
2015
e315cd28 2016 if (atomic_read(&vha->loop_down_timer) &&
4d4df193 2017 state[0] != FSTATE_READY) {
1da177e4 2018 /* Loop down. Timeout on min_wait for states
fa2a1ce5
AV		 2019 * other than Wait for Login.
2020 */
1da177e4 2021 if (time_after_eq(jiffies, mtime)) {
7c3df132 2022 ql_log(ql_log_info, vha, 0x8038,
1da177e4
LT		 2023 "Cable is unplugged...\n");
2024
e315cd28 2025 vha->device_flags |= DFLG_NO_CABLE;
1da177e4
LT		 2026 break;
2027 }
2028 }
2029 } else {
2030 /* Mailbox cmd failed. Timeout on min_wait. */
cdbb0a4f 2031 if (time_after_eq(jiffies, mtime) ||
7190575f 2032 ha->flags.isp82xx_fw_hung)
1da177e4
LT		 2033 break;
2034 }
2035
2036 if (time_after_eq(jiffies, wtime))
2037 break;
2038
2039 /* Delay for a while */
2040 msleep(500);
1da177e4
LT		 2041 } while (1);
2042
7c3df132
SK		 2043 ql_dbg(ql_dbg_taskm, vha, 0x803a,
2044 "fw_state=%x (%x, %x, %x, %x) " "curr time=%lx.\n", state[0],
2045 state[1], state[2], state[3], state[4], jiffies);
1da177e4 2046
cfb0919c 2047 if (rval && !(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132
SK		 2048 ql_log(ql_log_warn, vha, 0x803b,
2049 "Firmware ready **** FAILED ****.\n");
1da177e4
LT		 2050 }
2051
2052 return (rval);
2053}
2054
2055/*
2056* qla2x00_configure_hba
2057* Setup adapter context.
2058*
2059* Input:
2060* ha = adapter state pointer.
2061*
2062* Returns:
2063* 0 = success
2064*
2065* Context:
2066* Kernel context.
2067*/
2068static int
e315cd28 2069qla2x00_configure_hba(scsi_qla_host_t *vha)
1da177e4
LT		 2070{
2071 int rval;
2072 uint16_t loop_id;
2073 uint16_t topo;
2c3dfe3f 2074 uint16_t sw_cap;
1da177e4
LT		 2075 uint8_t al_pa;
2076 uint8_t area;
2077 uint8_t domain;
2078 char connect_type[22];
e315cd28 2079 struct qla_hw_data *ha = vha->hw;
f24b5cb8 2080 unsigned long flags;
1da177e4
LT		 2081
2082 /* Get host addresses. */
e315cd28 2083 rval = qla2x00_get_adapter_id(vha,
2c3dfe3f 2084 &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
1da177e4 2085 if (rval != QLA_SUCCESS) {
e315cd28 2086 if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
6246b8a1 2087 IS_CNA_CAPABLE(ha) ||
33135aa2 2088 (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
7c3df132
SK		 2089 ql_dbg(ql_dbg_disc, vha, 0x2008,
2090 "Loop is in a transition state.\n");
33135aa2 2091 } else {
7c3df132
SK		 2092 ql_log(ql_log_warn, vha, 0x2009,
2093 "Unable to get host loop ID.\n");
e315cd28 2094 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
33135aa2 2095 }
1da177e4
LT		 2096 return (rval);
2097 }
2098
2099 if (topo == 4) {
7c3df132
SK		 2100 ql_log(ql_log_info, vha, 0x200a,
2101 "Cannot get topology - retrying.\n");
1da177e4
LT		 2102 return (QLA_FUNCTION_FAILED);
2103 }
2104
e315cd28 2105 vha->loop_id = loop_id;
1da177e4
LT		 2106
2107 /* initialize */
2108 ha->min_external_loopid = SNS_FIRST_LOOP_ID;
2109 ha->operating_mode = LOOP;
2c3dfe3f 2110 ha->switch_cap = 0;
1da177e4
LT		 2111
2112 switch (topo) {
2113 case 0:
7c3df132 2114 ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n");
1da177e4
LT		 2115 ha->current_topology = ISP_CFG_NL;
2116 strcpy(connect_type, "(Loop)");
2117 break;
2118
2119 case 1:
7c3df132 2120 ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n");
2c3dfe3f 2121 ha->switch_cap = sw_cap;
1da177e4
LT		 2122 ha->current_topology = ISP_CFG_FL;
2123 strcpy(connect_type, "(FL_Port)");
2124 break;
2125
2126 case 2:
7c3df132 2127 ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n");
1da177e4
LT		 2128 ha->operating_mode = P2P;
2129 ha->current_topology = ISP_CFG_N;
2130 strcpy(connect_type, "(N_Port-to-N_Port)");
2131 break;
2132
2133 case 3:
7c3df132 2134 ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n");
2c3dfe3f 2135 ha->switch_cap = sw_cap;
1da177e4
LT		 2136 ha->operating_mode = P2P;
2137 ha->current_topology = ISP_CFG_F;
2138 strcpy(connect_type, "(F_Port)");
2139 break;
2140
2141 default:
7c3df132
SK		 2142 ql_dbg(ql_dbg_disc, vha, 0x200f,
2143 "HBA in unknown topology %x, using NL.\n", topo);
1da177e4
LT		 2144 ha->current_topology = ISP_CFG_NL;
2145 strcpy(connect_type, "(Loop)");
2146 break;
2147 }
2148
2149 /* Save Host port and loop ID. */
2150 /* byte order - Big Endian */
e315cd28
AC		 2151 vha->d_id.b.domain = domain;
2152 vha->d_id.b.area = area;
2153 vha->d_id.b.al_pa = al_pa;
1da177e4 2154
f24b5cb8 2155 spin_lock_irqsave(&ha->vport_slock, flags);
2d70c103 2156 qlt_update_vp_map(vha, SET_AL_PA);
f24b5cb8 2157 spin_unlock_irqrestore(&ha->vport_slock, flags);
2d70c103 2158
e315cd28 2159 if (!vha->flags.init_done)
7c3df132
SK		 2160 ql_log(ql_log_info, vha, 0x2010,
2161 "Topology - %s, Host Loop address 0x%x.\n",
e315cd28 2162 connect_type, vha->loop_id);
1da177e4
LT		 2163
2164 if (rval) {
7c3df132
SK		 2165 ql_log(ql_log_warn, vha, 0x2011,
2166 "%s FAILED\n", __func__);
1da177e4 2167 } else {
7c3df132
SK		 2168 ql_dbg(ql_dbg_disc, vha, 0x2012,
2169 "%s success\n", __func__);
1da177e4
LT		 2170 }
2171
2172 return(rval);
2173}
2174
a9083016 2175inline void
e315cd28
AC		 2176qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
2177 char *def)
9bb9fcf2
AV		 2178{
2179 char *st, *en;
2180 uint16_t index;
e315cd28 2181 struct qla_hw_data *ha = vha->hw;
ab671149 2182 int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
6246b8a1 2183 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha);
9bb9fcf2
AV		 2184
2185 if (memcmp(model, BINZERO, len) != 0) {
2186 strncpy(ha->model_number, model, len);
2187 st = en = ha->model_number;
2188 en += len - 1;
2189 while (en > st) {
2190 if (*en != 0x20 && *en != 0x00)
2191 break;
2192 *en-- = '\0';
2193 }
2194
2195 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 2196 if (use_tbl &&
2197 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2 2198 index < QLA_MODEL_NAMES)
1ee27146
JC		 2199 strncpy(ha->model_desc,
2200 qla2x00_model_name[index * 2 + 1],
2201 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 2202 } else {
2203 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 2204 if (use_tbl &&
2205 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2
AV		 2206 index < QLA_MODEL_NAMES) {
2207 strcpy(ha->model_number,
2208 qla2x00_model_name[index * 2]);
1ee27146
JC		 2209 strncpy(ha->model_desc,
2210 qla2x00_model_name[index * 2 + 1],
2211 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 2212 } else {
2213 strcpy(ha->model_number, def);
2214 }
2215 }
1ee27146 2216 if (IS_FWI2_CAPABLE(ha))
e315cd28 2217 qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc,
1ee27146 2218 sizeof(ha->model_desc));
9bb9fcf2
AV		 2219}
2220
4e08df3f
DM		 2221/* On sparc systems, obtain port and node WWN from firmware
2222 * properties.
2223 */
e315cd28 2224static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv)
4e08df3f
DM		 2225{
2226#ifdef CONFIG_SPARC
e315cd28 2227 struct qla_hw_data *ha = vha->hw;
4e08df3f 2228 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 2229 struct device_node *dp = pci_device_to_OF_node(pdev);
2230 const u8 *val;
4e08df3f
DM		 2231 int len;
2232
2233 val = of_get_property(dp, "port-wwn", &len);
2234 if (val && len >= WWN_SIZE)
2235 memcpy(nv->port_name, val, WWN_SIZE);
2236
2237 val = of_get_property(dp, "node-wwn", &len);
2238 if (val && len >= WWN_SIZE)
2239 memcpy(nv->node_name, val, WWN_SIZE);
2240#endif
2241}
2242
1da177e4
LT		 2243/*
2244* NVRAM configuration for ISP 2xxx
2245*
2246* Input:
2247* ha = adapter block pointer.
2248*
2249* Output:
2250* initialization control block in response_ring
2251* host adapters parameters in host adapter block
2252*
2253* Returns:
2254* 0 = success.
2255*/
abbd8870 2256int
e315cd28 2257qla2x00_nvram_config(scsi_qla_host_t *vha)
1da177e4 2258{
4e08df3f 2259 int rval;
0107109e
AV		 2260 uint8_t chksum = 0;
2261 uint16_t cnt;
2262 uint8_t *dptr1, *dptr2;
e315cd28 2263 struct qla_hw_data *ha = vha->hw;
0107109e 2264 init_cb_t *icb = ha->init_cb;
281afe19
SJ		 2265 nvram_t *nv = ha->nvram;
2266 uint8_t *ptr = ha->nvram;
3d71644c 2267 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 2268
4e08df3f
DM		 2269 rval = QLA_SUCCESS;
2270
1da177e4 2271 /* Determine NVRAM starting address. */
0107109e 2272 ha->nvram_size = sizeof(nvram_t);
1da177e4
LT		 2273 ha->nvram_base = 0;
2274 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
2275 if ((RD_REG_WORD(&reg->ctrl_status) >> 14) == 1)
2276 ha->nvram_base = 0x80;
2277
2278 /* Get NVRAM data and calculate checksum. */
e315cd28 2279 ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size);
0107109e
AV		 2280 for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++)
2281 chksum += *ptr++;
1da177e4 2282
7c3df132
SK		 2283 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
2284 "Contents of NVRAM.\n");
2285 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
2286 (uint8_t *)nv, ha->nvram_size);
1da177e4
LT		 2287
2288 /* Bad NVRAM data, set defaults parameters. */
2289 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' ||
2290 nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) {
2291 /* Reset NVRAM data. */
7c3df132 2292 ql_log(ql_log_warn, vha, 0x0064,
9e336520 2293 "Inconsistent NVRAM "
7c3df132
SK		 2294 "detected: checksum=0x%x id=%c version=0x%x.\n",
2295 chksum, nv->id[0], nv->nvram_version);
2296 ql_log(ql_log_warn, vha, 0x0065,
2297 "Falling back to "
2298 "functioning (yet invalid -- WWPN) defaults.\n");
4e08df3f
DM		 2299
2300 /*
2301 * Set default initialization control block.
2302 */
2303 memset(nv, 0, ha->nvram_size);
2304 nv->parameter_block_version = ICB_VERSION;
2305
2306 if (IS_QLA23XX(ha)) {
2307 nv->firmware_options[0] = BIT_2 | BIT_1;
2308 nv->firmware_options[1] = BIT_7 | BIT_5;
2309 nv->add_firmware_options[0] = BIT_5;
2310 nv->add_firmware_options[1] = BIT_5 | BIT_4;
2311 nv->frame_payload_size = __constant_cpu_to_le16(2048);
2312 nv->special_options[1] = BIT_7;
2313 } else if (IS_QLA2200(ha)) {
2314 nv->firmware_options[0] = BIT_2 | BIT_1;
2315 nv->firmware_options[1] = BIT_7 | BIT_5;
2316 nv->add_firmware_options[0] = BIT_5;
2317 nv->add_firmware_options[1] = BIT_5 | BIT_4;
2318 nv->frame_payload_size = __constant_cpu_to_le16(1024);
2319 } else if (IS_QLA2100(ha)) {
2320 nv->firmware_options[0] = BIT_3 | BIT_1;
2321 nv->firmware_options[1] = BIT_5;
2322 nv->frame_payload_size = __constant_cpu_to_le16(1024);
2323 }
2324
2325 nv->max_iocb_allocation = __constant_cpu_to_le16(256);
2326 nv->execution_throttle = __constant_cpu_to_le16(16);
2327 nv->retry_count = 8;
2328 nv->retry_delay = 1;
2329
2330 nv->port_name[0] = 33;
2331 nv->port_name[3] = 224;
2332 nv->port_name[4] = 139;
2333
e315cd28 2334 qla2xxx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 2335
2336 nv->login_timeout = 4;
2337
2338 /*
2339 * Set default host adapter parameters
2340 */
2341 nv->host_p[1] = BIT_2;
2342 nv->reset_delay = 5;
2343 nv->port_down_retry_count = 8;
2344 nv->max_luns_per_target = __constant_cpu_to_le16(8);
2345 nv->link_down_timeout = 60;
2346
2347 rval = 1;
1da177e4
LT		 2348 }
2349
2350#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
2351 /*
2352 * The SN2 does not provide BIOS emulation which means you can't change
2353 * potentially bogus BIOS settings. Force the use of default settings
2354 * for link rate and frame size. Hope that the rest of the settings
2355 * are valid.
2356 */
2357 if (ia64_platform_is("sn2")) {
2358 nv->frame_payload_size = __constant_cpu_to_le16(2048);
2359 if (IS_QLA23XX(ha))
2360 nv->special_options[1] = BIT_7;
2361 }
2362#endif
2363
2364 /* Reset Initialization control block */
0107109e 2365 memset(icb, 0, ha->init_cb_size);
1da177e4
LT		 2366
2367 /*
2368 * Setup driver NVRAM options.
2369 */
2370 nv->firmware_options[0] |= (BIT_6 | BIT_1);
2371 nv->firmware_options[0] &= ~(BIT_5 | BIT_4);
2372 nv->firmware_options[1] |= (BIT_5 | BIT_0);
2373 nv->firmware_options[1] &= ~BIT_4;
2374
2375 if (IS_QLA23XX(ha)) {
2376 nv->firmware_options[0] |= BIT_2;
2377 nv->firmware_options[0] &= ~BIT_3;
2d70c103 2378 nv->special_options[0] &= ~BIT_6;
0107109e 2379 nv->add_firmware_options[1] |= BIT_5 | BIT_4;
1da177e4
LT		 2380
2381 if (IS_QLA2300(ha)) {
2382 if (ha->fb_rev == FPM_2310) {
2383 strcpy(ha->model_number, "QLA2310");
2384 } else {
2385 strcpy(ha->model_number, "QLA2300");
2386 }
2387 } else {
e315cd28 2388 qla2x00_set_model_info(vha, nv->model_number,
9bb9fcf2 2389 sizeof(nv->model_number), "QLA23xx");
1da177e4
LT		 2390 }
2391 } else if (IS_QLA2200(ha)) {
2392 nv->firmware_options[0] |= BIT_2;
2393 /*
2394 * 'Point-to-point preferred, else loop' is not a safe
2395 * connection mode setting.
2396 */
2397 if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
2398 (BIT_5 | BIT_4)) {
2399 /* Force 'loop preferred, else point-to-point'. */
2400 nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
2401 nv->add_firmware_options[0] |= BIT_5;
2402 }
2403 strcpy(ha->model_number, "QLA22xx");
2404 } else /*if (IS_QLA2100(ha))*/ {
2405 strcpy(ha->model_number, "QLA2100");
2406 }
2407
2408 /*
2409 * Copy over NVRAM RISC parameter block to initialization control block.
2410 */
2411 dptr1 = (uint8_t *)icb;
2412 dptr2 = (uint8_t *)&nv->parameter_block_version;
2413 cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;
2414 while (cnt--)
2415 *dptr1++ = *dptr2++;
2416
2417 /* Copy 2nd half. */
2418 dptr1 = (uint8_t *)icb->add_firmware_options;
2419 cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;
2420 while (cnt--)
2421 *dptr1++ = *dptr2++;
2422
5341e868
AV		 2423 /* Use alternate WWN? */
2424 if (nv->host_p[1] & BIT_7) {
2425 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
2426 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
2427 }
2428
1da177e4
LT		 2429 /* Prepare nodename */
2430 if ((icb->firmware_options[1] & BIT_6) == 0) {
2431 /*
2432 * Firmware will apply the following mask if the nodename was
2433 * not provided.
2434 */
2435 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
2436 icb->node_name[0] &= 0xF0;
2437 }
2438
2439 /*
2440 * Set host adapter parameters.
2441 */
3ce8866c
SK		 2442
2443 /*
2444 * BIT_7 in the host-parameters section allows for modification to
2445 * internal driver logging.
2446 */
0181944f 2447 if (nv->host_p[0] & BIT_7)
cfb0919c 2448 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
1da177e4
LT		 2449 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
2450 /* Always load RISC code on non ISP2[12]00 chips. */
2451 if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
2452 ha->flags.disable_risc_code_load = 0;
2453 ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0);
2454 ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
2455 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
06c22bd1 2456 ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
d4c760c2 2457 ha->flags.disable_serdes = 0;
1da177e4
LT		 2458
2459 ha->operating_mode =
2460 (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
2461
2462 memcpy(ha->fw_seriallink_options, nv->seriallink_options,
2463 sizeof(ha->fw_seriallink_options));
2464
2465 /* save HBA serial number */
2466 ha->serial0 = icb->port_name[5];
2467 ha->serial1 = icb->port_name[6];
2468 ha->serial2 = icb->port_name[7];
e315cd28
AC		 2469 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
2470 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
1da177e4
LT		 2471
2472 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
2473
2474 ha->retry_count = nv->retry_count;
2475
2476 /* Set minimum login_timeout to 4 seconds. */
5b91490e 2477 if (nv->login_timeout != ql2xlogintimeout)
1da177e4
LT		 2478 nv->login_timeout = ql2xlogintimeout;
2479 if (nv->login_timeout < 4)
2480 nv->login_timeout = 4;
2481 ha->login_timeout = nv->login_timeout;
2482 icb->login_timeout = nv->login_timeout;
2483
00a537b8
AV		 2484 /* Set minimum RATOV to 100 tenths of a second. */
2485 ha->r_a_tov = 100;
1da177e4 2486
1da177e4
LT		 2487 ha->loop_reset_delay = nv->reset_delay;
2488
1da177e4
LT		 2489 /* Link Down Timeout = 0:
2490 *
2491 * When Port Down timer expires we will start returning
2492 * I/O's to OS with "DID_NO_CONNECT".
2493 *
2494 * Link Down Timeout != 0:
2495 *
2496 * The driver waits for the link to come up after link down
2497 * before returning I/Os to OS with "DID_NO_CONNECT".
fa2a1ce5 2498 */
1da177e4
LT		 2499 if (nv->link_down_timeout == 0) {
2500 ha->loop_down_abort_time =
354d6b21 2501 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
1da177e4
LT		 2502 } else {
2503 ha->link_down_timeout = nv->link_down_timeout;
2504 ha->loop_down_abort_time =
2505 (LOOP_DOWN_TIME - ha->link_down_timeout);
fa2a1ce5 2506 }
1da177e4 2507
1da177e4
LT		 2508 /*
2509 * Need enough time to try and get the port back.
2510 */
2511 ha->port_down_retry_count = nv->port_down_retry_count;
2512 if (qlport_down_retry)
2513 ha->port_down_retry_count = qlport_down_retry;
2514 /* Set login_retry_count */
2515 ha->login_retry_count = nv->retry_count;
2516 if (ha->port_down_retry_count == nv->port_down_retry_count &&
2517 ha->port_down_retry_count > 3)
2518 ha->login_retry_count = ha->port_down_retry_count;
2519 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
2520 ha->login_retry_count = ha->port_down_retry_count;
2521 if (ql2xloginretrycount)
2522 ha->login_retry_count = ql2xloginretrycount;
2523
1da177e4
LT		 2524 icb->lun_enables = __constant_cpu_to_le16(0);
2525 icb->command_resource_count = 0;
2526 icb->immediate_notify_resource_count = 0;
2527 icb->timeout = __constant_cpu_to_le16(0);
2528
2529 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
2530 /* Enable RIO */
2531 icb->firmware_options[0] &= ~BIT_3;
2532 icb->add_firmware_options[0] &=
2533 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
2534 icb->add_firmware_options[0] |= BIT_2;
2535 icb->response_accumulation_timer = 3;
2536 icb->interrupt_delay_timer = 5;
2537
e315cd28 2538 vha->flags.process_response_queue = 1;
1da177e4 2539 } else {
4fdfefe5 2540 /* Enable ZIO. */
e315cd28 2541 if (!vha->flags.init_done) {
4fdfefe5
AV		 2542 ha->zio_mode = icb->add_firmware_options[0] &
2543 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
2544 ha->zio_timer = icb->interrupt_delay_timer ?
2545 icb->interrupt_delay_timer: 2;
2546 }
1da177e4
LT		 2547 icb->add_firmware_options[0] &=
2548 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
e315cd28 2549 vha->flags.process_response_queue = 0;
4fdfefe5 2550 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d
AV		 2551 ha->zio_mode = QLA_ZIO_MODE_6;
2552
7c3df132 2553 ql_log(ql_log_info, vha, 0x0068,
4fdfefe5
AV		 2554 "ZIO mode %d enabled; timer delay (%d us).\n",
2555 ha->zio_mode, ha->zio_timer * 100);
1da177e4 2556
4fdfefe5
AV		 2557 icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;
2558 icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;
e315cd28 2559 vha->flags.process_response_queue = 1;
1da177e4
LT		 2560 }
2561 }
2562
4e08df3f 2563 if (rval) {
7c3df132
SK		 2564 ql_log(ql_log_warn, vha, 0x0069,
2565 "NVRAM configuration failed.\n");
4e08df3f
DM		 2566 }
2567 return (rval);
1da177e4
LT		 2568}
2569
19a7b4ae
JSEC		 2570static void
2571qla2x00_rport_del(void *data)
2572{
2573 fc_port_t *fcport = data;
d97994dc 2574 struct fc_rport *rport;
2d70c103 2575 scsi_qla_host_t *vha = fcport->vha;
044d78e1 2576 unsigned long flags;
d97994dc 2577
044d78e1 2578 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
ac280b67 2579 rport = fcport->drport ? fcport->drport: fcport->rport;
d97994dc 2580 fcport->drport = NULL;
044d78e1 2581 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
2d70c103 2582 if (rport) {
d97994dc 2583 fc_remote_port_delete(rport);
2d70c103
NB		 2584 /*
2585 * Release the target mode FC NEXUS in qla_target.c code
2586 * if target mod is enabled.
2587 */
2588 qlt_fc_port_deleted(vha, fcport);
2589 }
19a7b4ae
JSEC		 2590}
2591
1da177e4
LT		 2592/**
2593 * qla2x00_alloc_fcport() - Allocate a generic fcport.
2594 * @ha: HA context
2595 * @flags: allocation flags
2596 *
2597 * Returns a pointer to the allocated fcport, or NULL, if none available.
2598 */
9a069e19 2599fc_port_t *
e315cd28 2600qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags)
1da177e4
LT		 2601{
2602 fc_port_t *fcport;
2603
bbfbbbc1
MK		 2604 fcport = kzalloc(sizeof(fc_port_t), flags);
2605 if (!fcport)
2606 return NULL;
1da177e4
LT		 2607
2608 /* Setup fcport template structure. */
e315cd28 2609 fcport->vha = vha;
1da177e4
LT		 2610 fcport->port_type = FCT_UNKNOWN;
2611 fcport->loop_id = FC_NO_LOOP_ID;
ec426e10 2612 qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
ad3e0eda 2613 fcport->supported_classes = FC_COS_UNSPECIFIED;
c0822b63 2614 fcport->scan_state = QLA_FCPORT_SCAN_NONE;
1da177e4 2615
bbfbbbc1 2616 return fcport;
1da177e4
LT		 2617}
2618
2619/*
2620 * qla2x00_configure_loop
2621 * Updates Fibre Channel Device Database with what is actually on loop.
2622 *
2623 * Input:
2624 * ha = adapter block pointer.
2625 *
2626 * Returns:
2627 * 0 = success.
2628 * 1 = error.
2629 * 2 = database was full and device was not configured.
2630 */
2631static int
e315cd28 2632qla2x00_configure_loop(scsi_qla_host_t *vha)
1da177e4
LT		 2633{
2634 int rval;
2635 unsigned long flags, save_flags;
e315cd28 2636 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2637 rval = QLA_SUCCESS;
2638
2639 /* Get Initiator ID */
e315cd28
AC		 2640 if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) {
2641 rval = qla2x00_configure_hba(vha);
1da177e4 2642 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2643 ql_dbg(ql_dbg_disc, vha, 0x2013,
2644 "Unable to configure HBA.\n");
1da177e4
LT		 2645 return (rval);
2646 }
2647 }
2648
e315cd28 2649 save_flags = flags = vha->dpc_flags;
7c3df132
SK		 2650 ql_dbg(ql_dbg_disc, vha, 0x2014,
2651 "Configure loop -- dpc flags = 0x%lx.\n", flags);
1da177e4
LT		 2652
2653 /*
2654 * If we have both an RSCN and PORT UPDATE pending then handle them
2655 * both at the same time.
2656 */
e315cd28
AC		 2657 clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2658 clear_bit(RSCN_UPDATE, &vha->dpc_flags);
1da177e4 2659
3064ff39
MH		 2660 qla2x00_get_data_rate(vha);
2661
1da177e4
LT		 2662 /* Determine what we need to do */
2663 if (ha->current_topology == ISP_CFG_FL &&
2664 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
2665
1da177e4
LT		 2666 set_bit(RSCN_UPDATE, &flags);
2667
2668 } else if (ha->current_topology == ISP_CFG_F &&
2669 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
2670
1da177e4
LT		 2671 set_bit(RSCN_UPDATE, &flags);
2672 clear_bit(LOCAL_LOOP_UPDATE, &flags);
21333b48
AV		 2673
2674 } else if (ha->current_topology == ISP_CFG_N) {
2675 clear_bit(RSCN_UPDATE, &flags);
1da177e4 2676
e315cd28 2677 } else if (!vha->flags.online ||
1da177e4
LT		 2678 (test_bit(ABORT_ISP_ACTIVE, &flags))) {
2679
1da177e4
LT		 2680 set_bit(RSCN_UPDATE, &flags);
2681 set_bit(LOCAL_LOOP_UPDATE, &flags);
2682 }
2683
2684 if (test_bit(LOCAL_LOOP_UPDATE, &flags)) {
7c3df132
SK		 2685 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
2686 ql_dbg(ql_dbg_disc, vha, 0x2015,
2687 "Loop resync needed, failing.\n");
1da177e4 2688 rval = QLA_FUNCTION_FAILED;
642ef983 2689 } else
e315cd28 2690 rval = qla2x00_configure_local_loop(vha);
1da177e4
LT		 2691 }
2692
2693 if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
7c3df132
SK		 2694 if (LOOP_TRANSITION(vha)) {
2695 ql_dbg(ql_dbg_disc, vha, 0x201e,
2696 "Needs RSCN update and loop transition.\n");
1da177e4 2697 rval = QLA_FUNCTION_FAILED;
7c3df132 2698 }
e315cd28
AC		 2699 else
2700 rval = qla2x00_configure_fabric(vha);
1da177e4
LT		 2701 }
2702
2703 if (rval == QLA_SUCCESS) {
e315cd28
AC		 2704 if (atomic_read(&vha->loop_down_timer) ||
2705 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4
LT		 2706 rval = QLA_FUNCTION_FAILED;
2707 } else {
e315cd28 2708 atomic_set(&vha->loop_state, LOOP_READY);
7c3df132
SK		 2709 ql_dbg(ql_dbg_disc, vha, 0x2069,
2710 "LOOP READY.\n");
1da177e4
LT		 2711 }
2712 }
2713
2714 if (rval) {
7c3df132
SK		 2715 ql_dbg(ql_dbg_disc, vha, 0x206a,
2716 "%s *** FAILED ***.\n", __func__);
1da177e4 2717 } else {
7c3df132
SK		 2718 ql_dbg(ql_dbg_disc, vha, 0x206b,
2719 "%s: exiting normally.\n", __func__);
1da177e4
LT		 2720 }
2721
cc3ef7bc 2722 /* Restore state if a resync event occurred during processing */
e315cd28 2723 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4 2724 if (test_bit(LOCAL_LOOP_UPDATE, &save_flags))
e315cd28 2725 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
f4658b6c 2726 if (test_bit(RSCN_UPDATE, &save_flags)) {
e315cd28 2727 set_bit(RSCN_UPDATE, &vha->dpc_flags);
f4658b6c 2728 }
1da177e4
LT		 2729 }
2730
2731 return (rval);
2732}
2733
2734
2735
2736/*
2737 * qla2x00_configure_local_loop
2738 * Updates Fibre Channel Device Database with local loop devices.
2739 *
2740 * Input:
2741 * ha = adapter block pointer.
2742 *
2743 * Returns:
2744 * 0 = success.
2745 */
2746static int
e315cd28 2747qla2x00_configure_local_loop(scsi_qla_host_t *vha)
1da177e4
LT		 2748{
2749 int rval, rval2;
2750 int found_devs;
2751 int found;
2752 fc_port_t *fcport, *new_fcport;
2753
2754 uint16_t index;
2755 uint16_t entries;
2756 char *id_iter;
2757 uint16_t loop_id;
2758 uint8_t domain, area, al_pa;
e315cd28 2759 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2760
2761 found_devs = 0;
2762 new_fcport = NULL;
642ef983 2763 entries = MAX_FIBRE_DEVICES_LOOP;
1da177e4 2764
1da177e4 2765 /* Get list of logged in devices. */
642ef983 2766 memset(ha->gid_list, 0, qla2x00_gid_list_size(ha));
e315cd28 2767 rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma,
1da177e4
LT		 2768 &entries);
2769 if (rval != QLA_SUCCESS)
2770 goto cleanup_allocation;
2771
7c3df132
SK		 2772 ql_dbg(ql_dbg_disc, vha, 0x2017,
2773 "Entries in ID list (%d).\n", entries);
2774 ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
2775 (uint8_t *)ha->gid_list,
2776 entries * sizeof(struct gid_list_info));
1da177e4
LT		 2777
2778 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 2779 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 2780 if (new_fcport == NULL) {
7c3df132
SK		 2781 ql_log(ql_log_warn, vha, 0x2018,
2782 "Memory allocation failed for fcport.\n");
1da177e4
LT		 2783 rval = QLA_MEMORY_ALLOC_FAILED;
2784 goto cleanup_allocation;
2785 }
2786 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
2787
2788 /*
2789 * Mark local devices that were present with FCF_DEVICE_LOST for now.
2790 */
e315cd28 2791 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 2792 if (atomic_read(&fcport->state) == FCS_ONLINE &&
2793 fcport->port_type != FCT_BROADCAST &&
2794 (fcport->flags & FCF_FABRIC_DEVICE) == 0) {
2795
7c3df132
SK		 2796 ql_dbg(ql_dbg_disc, vha, 0x2019,
2797 "Marking port lost loop_id=0x%04x.\n",
2798 fcport->loop_id);
1da177e4 2799
ec426e10 2800 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 2801 }
2802 }
2803
2804 /* Add devices to port list. */
2805 id_iter = (char *)ha->gid_list;
2806 for (index = 0; index < entries; index++) {
2807 domain = ((struct gid_list_info *)id_iter)->domain;
2808 area = ((struct gid_list_info *)id_iter)->area;
2809 al_pa = ((struct gid_list_info *)id_iter)->al_pa;
abbd8870 2810 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1da177e4
LT		 2811 loop_id = (uint16_t)
2812 ((struct gid_list_info *)id_iter)->loop_id_2100;
abbd8870 2813 else
1da177e4
LT		 2814 loop_id = le16_to_cpu(
2815 ((struct gid_list_info *)id_iter)->loop_id);
abbd8870 2816 id_iter += ha->gid_list_info_size;
1da177e4
LT		 2817
2818 /* Bypass reserved domain fields. */
2819 if ((domain & 0xf0) == 0xf0)
2820 continue;
2821
2822 /* Bypass if not same domain and area of adapter. */
f7d289f6 2823 if (area && domain &&
e315cd28 2824 (area != vha->d_id.b.area || domain != vha->d_id.b.domain))
1da177e4
LT		 2825 continue;
2826
2827 /* Bypass invalid local loop ID. */
2828 if (loop_id > LAST_LOCAL_LOOP_ID)
2829 continue;
2830
370d550e
AE		 2831 memset(new_fcport, 0, sizeof(fc_port_t));
2832
1da177e4
LT		 2833 /* Fill in member data. */
2834 new_fcport->d_id.b.domain = domain;
2835 new_fcport->d_id.b.area = area;
2836 new_fcport->d_id.b.al_pa = al_pa;
2837 new_fcport->loop_id = loop_id;
e315cd28 2838 rval2 = qla2x00_get_port_database(vha, new_fcport, 0);
1da177e4 2839 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 2840 ql_dbg(ql_dbg_disc, vha, 0x201a,
2841 "Failed to retrieve fcport information "
2842 "-- get_port_database=%x, loop_id=0x%04x.\n",
2843 rval2, new_fcport->loop_id);
2844 ql_dbg(ql_dbg_disc, vha, 0x201b,
2845 "Scheduling resync.\n");
e315cd28 2846 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4
LT		 2847 continue;
2848 }
2849
2850 /* Check for matching device in port list. */
2851 found = 0;
2852 fcport = NULL;
e315cd28 2853 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 2854 if (memcmp(new_fcport->port_name, fcport->port_name,
2855 WWN_SIZE))
2856 continue;
2857
ddb9b126 2858 fcport->flags &= ~FCF_FABRIC_DEVICE;
1da177e4
LT		 2859 fcport->loop_id = new_fcport->loop_id;
2860 fcport->port_type = new_fcport->port_type;
2861 fcport->d_id.b24 = new_fcport->d_id.b24;
2862 memcpy(fcport->node_name, new_fcport->node_name,
2863 WWN_SIZE);
2864
2865 found++;
2866 break;
2867 }
2868
2869 if (!found) {
2870 /* New device, add to fcports list. */
e315cd28 2871 list_add_tail(&new_fcport->list, &vha->vp_fcports);
1da177e4
LT		 2872
2873 /* Allocate a new replacement fcport. */
2874 fcport = new_fcport;
e315cd28 2875 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 2876 if (new_fcport == NULL) {
7c3df132
SK		 2877 ql_log(ql_log_warn, vha, 0x201c,
2878 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 2879 rval = QLA_MEMORY_ALLOC_FAILED;
2880 goto cleanup_allocation;
2881 }
2882 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
2883 }
2884
d8b45213 2885 /* Base iIDMA settings on HBA port speed. */
a3cbdfad 2886 fcport->fp_speed = ha->link_data_rate;
d8b45213 2887
e315cd28 2888 qla2x00_update_fcport(vha, fcport);
1da177e4
LT		 2889
2890 found_devs++;
2891 }
2892
2893cleanup_allocation:
c9475cb0 2894 kfree(new_fcport);
1da177e4
LT		 2895
2896 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2897 ql_dbg(ql_dbg_disc, vha, 0x201d,
2898 "Configure local loop error exit: rval=%x.\n", rval);
1da177e4
LT		 2899 }
2900
1da177e4
LT		 2901 return (rval);
2902}
2903
d8b45213 2904static void
e315cd28 2905qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
d8b45213 2906{
9f8fddee 2907 char *link_speed;
d8b45213 2908 int rval;
1bb39548 2909 uint16_t mb[4];
e315cd28 2910 struct qla_hw_data *ha = vha->hw;
d8b45213 2911
c76f2c01 2912 if (!IS_IIDMA_CAPABLE(ha))
d8b45213
AV		 2913 return;
2914
c9afb9a2
GM		 2915 if (atomic_read(&fcport->state) != FCS_ONLINE)
2916 return;
2917
39bd9622
AV		 2918 if (fcport->fp_speed == PORT_SPEED_UNKNOWN ||
2919 fcport->fp_speed > ha->link_data_rate)
d8b45213
AV		 2920 return;
2921
e315cd28 2922 rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed,
a3cbdfad 2923 mb);
d8b45213 2924 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2925 ql_dbg(ql_dbg_disc, vha, 0x2004,
2926 "Unable to adjust iIDMA "
2927 "%02x%02x%02x%02x%02x%02x%02x%02x -- %04x %x %04x "
2928 "%04x.\n", fcport->port_name[0], fcport->port_name[1],
d8b45213
AV		 2929 fcport->port_name[2], fcport->port_name[3],
2930 fcport->port_name[4], fcport->port_name[5],
2931 fcport->port_name[6], fcport->port_name[7], rval,
7c3df132 2932 fcport->fp_speed, mb[0], mb[1]);
d8b45213 2933 } else {
daae62a3 2934 link_speed = qla2x00_get_link_speed_str(ha);
7c3df132
SK		 2935 ql_dbg(ql_dbg_disc, vha, 0x2005,
2936 "iIDMA adjusted to %s GB/s "
2937 "on %02x%02x%02x%02x%02x%02x%02x%02x.\n", link_speed,
2938 fcport->port_name[0], fcport->port_name[1],
2939 fcport->port_name[2], fcport->port_name[3],
2940 fcport->port_name[4], fcport->port_name[5],
2941 fcport->port_name[6], fcport->port_name[7]);
d8b45213
AV		 2942 }
2943}
2944
23be331d 2945static void
e315cd28 2946qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport)
8482e118
AV		 2947{
2948 struct fc_rport_identifiers rport_ids;
bdf79621 2949 struct fc_rport *rport;
044d78e1 2950 unsigned long flags;
8482e118 2951
ac280b67 2952 qla2x00_rport_del(fcport);
8482e118 2953
f8b02a85
AV		 2954 rport_ids.node_name = wwn_to_u64(fcport->node_name);
2955 rport_ids.port_name = wwn_to_u64(fcport->port_name);
8482e118
AV		 2956 rport_ids.port_id = fcport->d_id.b.domain << 16 |
2957 fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa;
77d74143 2958 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
e315cd28 2959 fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids);
77d74143 2960 if (!rport) {
7c3df132
SK		 2961 ql_log(ql_log_warn, vha, 0x2006,
2962 "Unable to allocate fc remote port.\n");
77d74143
AV		 2963 return;
2964 }
2d70c103
NB		 2965 /*
2966 * Create target mode FC NEXUS in qla_target.c if target mode is
2967 * enabled..
2968 */
2969 qlt_fc_port_added(vha, fcport);
2970
044d78e1 2971 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
19a7b4ae 2972 *((fc_port_t **)rport->dd_data) = fcport;
044d78e1 2973 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
d97994dc 2974
ad3e0eda 2975 rport->supported_classes = fcport->supported_classes;
77d74143 2976
8482e118
AV		 2977 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
2978 if (fcport->port_type == FCT_INITIATOR)
2979 rport_ids.roles |= FC_RPORT_ROLE_FCP_INITIATOR;
2980 if (fcport->port_type == FCT_TARGET)
2981 rport_ids.roles |= FC_RPORT_ROLE_FCP_TARGET;
77d74143 2982 fc_remote_port_rolechg(rport, rport_ids.roles);
1da177e4
LT		 2983}
2984
23be331d
AB		 2985/*
2986 * qla2x00_update_fcport
2987 * Updates device on list.
2988 *
2989 * Input:
2990 * ha = adapter block pointer.
2991 * fcport = port structure pointer.
2992 *
2993 * Return:
2994 * 0 - Success
2995 * BIT_0 - error
2996 *
2997 * Context:
2998 * Kernel context.
2999 */
3000void
e315cd28 3001qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
23be331d 3002{
e315cd28 3003 fcport->vha = vha;
23be331d 3004 fcport->login_retry = 0;
5ff1d584 3005 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
23be331d 3006
e315cd28 3007 qla2x00_iidma_fcport(vha, fcport);
21090cbe 3008 qla24xx_update_fcport_fcp_prio(vha, fcport);
e315cd28 3009 qla2x00_reg_remote_port(vha, fcport);
ec426e10 3010 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
23be331d
AB		 3011}
3012
1da177e4
LT		 3013/*
3014 * qla2x00_configure_fabric
3015 * Setup SNS devices with loop ID's.
3016 *
3017 * Input:
3018 * ha = adapter block pointer.
3019 *
3020 * Returns:
3021 * 0 = success.
3022 * BIT_0 = error
3023 */
3024static int
e315cd28 3025qla2x00_configure_fabric(scsi_qla_host_t *vha)
1da177e4 3026{
b3b02e6e 3027 int rval;
4dc77c36 3028 fc_port_t *fcport;
1da177e4
LT		 3029 uint16_t next_loopid;
3030 uint16_t mb[MAILBOX_REGISTER_COUNT];
0107109e 3031 uint16_t loop_id;
1da177e4 3032 LIST_HEAD(new_fcports);
e315cd28
AC		 3033 struct qla_hw_data *ha = vha->hw;
3034 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 3035
3036 /* If FL port exists, then SNS is present */
e428924c 3037 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 3038 loop_id = NPH_F_PORT;
3039 else
3040 loop_id = SNS_FL_PORT;
e315cd28 3041 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1);
1da177e4 3042 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3043 ql_dbg(ql_dbg_disc, vha, 0x201f,
3044 "MBX_GET_PORT_NAME failed, No FL Port.\n");
1da177e4 3045
e315cd28 3046 vha->device_flags &= ~SWITCH_FOUND;
1da177e4
LT		 3047 return (QLA_SUCCESS);
3048 }
e315cd28 3049 vha->device_flags |= SWITCH_FOUND;
1da177e4 3050
1da177e4 3051 do {
cca5335c
AV		 3052 /* FDMI support. */
3053 if (ql2xfdmienable &&
e315cd28
AC		 3054 test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags))
3055 qla2x00_fdmi_register(vha);
cca5335c 3056
1da177e4 3057 /* Ensure we are logged into the SNS. */
e428924c 3058 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 3059 loop_id = NPH_SNS;
3060 else
3061 loop_id = SIMPLE_NAME_SERVER;
0b91d116
CD		 3062 rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff,
3063 0xfc, mb, BIT_1|BIT_0);
3064 if (rval != QLA_SUCCESS) {
3065 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
4dc77c36 3066 break;
0b91d116 3067 }
1da177e4 3068 if (mb[0] != MBS_COMMAND_COMPLETE) {
7c3df132
SK		 3069 ql_dbg(ql_dbg_disc, vha, 0x2042,
3070 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x "
3071 "mb[6]=%x mb[7]=%x.\n", loop_id, mb[0], mb[1],
3072 mb[2], mb[6], mb[7]);
1da177e4
LT		 3073 return (QLA_SUCCESS);
3074 }
3075
e315cd28
AC		 3076 if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) {
3077 if (qla2x00_rft_id(vha)) {
1da177e4 3078 /* EMPTY */
7c3df132
SK		 3079 ql_dbg(ql_dbg_disc, vha, 0x2045,
3080 "Register FC-4 TYPE failed.\n");
1da177e4 3081 }
e315cd28 3082 if (qla2x00_rff_id(vha)) {
1da177e4 3083 /* EMPTY */
7c3df132
SK		 3084 ql_dbg(ql_dbg_disc, vha, 0x2049,
3085 "Register FC-4 Features failed.\n");
1da177e4 3086 }
e315cd28 3087 if (qla2x00_rnn_id(vha)) {
1da177e4 3088 /* EMPTY */
7c3df132
SK		 3089 ql_dbg(ql_dbg_disc, vha, 0x204f,
3090 "Register Node Name failed.\n");
e315cd28 3091 } else if (qla2x00_rsnn_nn(vha)) {
1da177e4 3092 /* EMPTY */
7c3df132
SK		 3093 ql_dbg(ql_dbg_disc, vha, 0x2053,
3094 "Register Symobilic Node Name failed.\n");
1da177e4
LT		 3095 }
3096 }
3097
e315cd28 3098 rval = qla2x00_find_all_fabric_devs(vha, &new_fcports);
1da177e4
LT		 3099 if (rval != QLA_SUCCESS)
3100 break;
3101
4dc77c36
JC		 3102 /* Add new ports to existing port list */
3103 list_splice_tail_init(&new_fcports, &vha->vp_fcports);
3104
3105 /* Starting free loop ID. */
3106 next_loopid = ha->min_external_loopid;
3107
e315cd28
AC		 3108 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3109 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
1da177e4
LT		 3110 break;
3111
3112 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0)
3113 continue;
3114
4dc77c36 3115 /* Logout lost/gone fabric devices (non-FCP2) */
c0822b63 3116 if (fcport->scan_state != QLA_FCPORT_SCAN_FOUND &&
b3b02e6e 3117 atomic_read(&fcport->state) == FCS_ONLINE) {
e315cd28 3118 qla2x00_mark_device_lost(vha, fcport,
d97994dc 3119 ql2xplogiabsentdevice, 0);
1da177e4 3120 if (fcport->loop_id != FC_NO_LOOP_ID &&
f08b7251 3121 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
1da177e4
LT		 3122 fcport->port_type != FCT_INITIATOR &&
3123 fcport->port_type != FCT_BROADCAST) {
e315cd28 3124 ha->isp_ops->fabric_logout(vha,
1c7c6357
AV		 3125 fcport->loop_id,
3126 fcport->d_id.b.domain,
3127 fcport->d_id.b.area,
3128 fcport->d_id.b.al_pa);
1da177e4 3129 }
c0822b63 3130 continue;
1da177e4 3131 }
c0822b63 3132 fcport->scan_state = QLA_FCPORT_SCAN_NONE;
1da177e4 3133
4dc77c36
JC		 3134 /* Login fabric devices that need a login */
3135 if ((fcport->flags & FCF_LOGIN_NEEDED) != 0 &&
3136 atomic_read(&vha->loop_down_timer) == 0) {
3137 if (fcport->loop_id == FC_NO_LOOP_ID) {
3138 fcport->loop_id = next_loopid;
3139 rval = qla2x00_find_new_loop_id(
3140 base_vha, fcport);
3141 if (rval != QLA_SUCCESS) {
3142 /* Ran out of IDs to use */
3143 continue;
3144 }
1da177e4
LT		 3145 }
3146 }
1da177e4 3147
bdf79621 3148 /* Login and update database */
e315cd28 3149 qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
1da177e4
LT		 3150 }
3151 } while (0);
3152
1da177e4 3153 if (rval) {
7c3df132
SK		 3154 ql_dbg(ql_dbg_disc, vha, 0x2068,
3155 "Configure fabric error exit rval=%d.\n", rval);
1da177e4
LT		 3156 }
3157
3158 return (rval);
3159}
3160
1da177e4
LT		 3161/*
3162 * qla2x00_find_all_fabric_devs
3163 *
3164 * Input:
3165 * ha = adapter block pointer.
3166 * dev = database device entry pointer.
3167 *
3168 * Returns:
3169 * 0 = success.
3170 *
3171 * Context:
3172 * Kernel context.
3173 */
3174static int
e315cd28
AC		 3175qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha,
3176 struct list_head *new_fcports)
1da177e4
LT		 3177{
3178 int rval;
3179 uint16_t loop_id;
3180 fc_port_t *fcport, *new_fcport, *fcptemp;
3181 int found;
3182
3183 sw_info_t *swl;
3184 int swl_idx;
3185 int first_dev, last_dev;
1516ef44 3186 port_id_t wrap = {}, nxt_d_id;
e315cd28
AC		 3187 struct qla_hw_data *ha = vha->hw;
3188 struct scsi_qla_host *vp, *base_vha = pci_get_drvdata(ha->pdev);
ee546b6e 3189 struct scsi_qla_host *tvp;
1da177e4
LT		 3190
3191 rval = QLA_SUCCESS;
3192
3193 /* Try GID_PT to get device list, else GAN. */
7a67735b 3194 if (!ha->swl)
642ef983 3195 ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t),
7a67735b
AV		 3196 GFP_KERNEL);
3197 swl = ha->swl;
bbfbbbc1 3198 if (!swl) {
1da177e4 3199 /*EMPTY*/
7c3df132
SK		 3200 ql_dbg(ql_dbg_disc, vha, 0x2054,
3201 "GID_PT allocations failed, fallback on GA_NXT.\n");
1da177e4 3202 } else {
642ef983 3203 memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t));
e315cd28 3204 if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) {
1da177e4 3205 swl = NULL;
e315cd28 3206 } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 3207 swl = NULL;
e315cd28 3208 } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 3209 swl = NULL;
e5896bd5 3210 } else if (ql2xiidmaenable &&
e315cd28
AC		 3211 qla2x00_gfpn_id(vha, swl) == QLA_SUCCESS) {
3212 qla2x00_gpsc(vha, swl);
1da177e4 3213 }
e8c72ba5
CD		 3214
3215 /* If other queries succeeded probe for FC-4 type */
3216 if (swl)
3217 qla2x00_gff_id(vha, swl);
1da177e4
LT		 3218 }
3219 swl_idx = 0;
3220
3221 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 3222 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3223 if (new_fcport == NULL) {
7c3df132
SK		 3224 ql_log(ql_log_warn, vha, 0x205e,
3225 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 3226 return (QLA_MEMORY_ALLOC_FAILED);
3227 }
3228 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
1da177e4
LT		 3229 /* Set start port ID scan at adapter ID. */
3230 first_dev = 1;
3231 last_dev = 0;
3232
3233 /* Starting free loop ID. */
e315cd28
AC		 3234 loop_id = ha->min_external_loopid;
3235 for (; loop_id <= ha->max_loop_id; loop_id++) {
3236 if (qla2x00_is_reserved_id(vha, loop_id))
1da177e4
LT		 3237 continue;
3238
3a6478df
GM		 3239 if (ha->current_topology == ISP_CFG_FL &&
3240 (atomic_read(&vha->loop_down_timer) ||
3241 LOOP_TRANSITION(vha))) {
bb2d52b2
AV		 3242 atomic_set(&vha->loop_down_timer, 0);
3243 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
3244 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
1da177e4 3245 break;
bb2d52b2 3246 }
1da177e4
LT		 3247
3248 if (swl != NULL) {
3249 if (last_dev) {
3250 wrap.b24 = new_fcport->d_id.b24;
3251 } else {
3252 new_fcport->d_id.b24 = swl[swl_idx].d_id.b24;
3253 memcpy(new_fcport->node_name,
3254 swl[swl_idx].node_name, WWN_SIZE);
3255 memcpy(new_fcport->port_name,
3256 swl[swl_idx].port_name, WWN_SIZE);
d8b45213
AV		 3257 memcpy(new_fcport->fabric_port_name,
3258 swl[swl_idx].fabric_port_name, WWN_SIZE);
3259 new_fcport->fp_speed = swl[swl_idx].fp_speed;
e8c72ba5 3260 new_fcport->fc4_type = swl[swl_idx].fc4_type;
1da177e4
LT		 3261
3262 if (swl[swl_idx].d_id.b.rsvd_1 != 0) {
3263 last_dev = 1;
3264 }
3265 swl_idx++;
3266 }
3267 } else {
3268 /* Send GA_NXT to the switch */
e315cd28 3269 rval = qla2x00_ga_nxt(vha, new_fcport);
1da177e4 3270 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3271 ql_log(ql_log_warn, vha, 0x2064,
3272 "SNS scan failed -- assuming "
3273 "zero-entry result.\n");
1da177e4
LT		 3274 list_for_each_entry_safe(fcport, fcptemp,
3275 new_fcports, list) {
3276 list_del(&fcport->list);
3277 kfree(fcport);
3278 }
3279 rval = QLA_SUCCESS;
3280 break;
3281 }
3282 }
3283
3284 /* If wrap on switch device list, exit. */
3285 if (first_dev) {
3286 wrap.b24 = new_fcport->d_id.b24;
3287 first_dev = 0;
3288 } else if (new_fcport->d_id.b24 == wrap.b24) {
7c3df132
SK		 3289 ql_dbg(ql_dbg_disc, vha, 0x2065,
3290 "Device wrap (%02x%02x%02x).\n",
3291 new_fcport->d_id.b.domain,
3292 new_fcport->d_id.b.area,
3293 new_fcport->d_id.b.al_pa);
1da177e4
LT		 3294 break;
3295 }
3296
2c3dfe3f 3297 /* Bypass if same physical adapter. */
e315cd28 3298 if (new_fcport->d_id.b24 == base_vha->d_id.b24)
1da177e4
LT		 3299 continue;
3300
2c3dfe3f 3301 /* Bypass virtual ports of the same host. */
e315cd28
AC		 3302 found = 0;
3303 if (ha->num_vhosts) {
feafb7b1
AE		 3304 unsigned long flags;
3305
3306 spin_lock_irqsave(&ha->vport_slock, flags);
ee546b6e 3307 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
e315cd28
AC		 3308 if (new_fcport->d_id.b24 == vp->d_id.b24) {
3309 found = 1;
2c3dfe3f 3310 break;
e315cd28 3311 }
2c3dfe3f 3312 }
feafb7b1
AE		 3313 spin_unlock_irqrestore(&ha->vport_slock, flags);
3314
e315cd28 3315 if (found)
2c3dfe3f
SJ		 3316 continue;
3317 }
3318
f7d289f6
AV		 3319 /* Bypass if same domain and area of adapter. */
3320 if (((new_fcport->d_id.b24 & 0xffff00) ==
e315cd28 3321 (vha->d_id.b24 & 0xffff00)) && ha->current_topology ==
f7d289f6
AV		 3322 ISP_CFG_FL)
3323 continue;
3324
1da177e4
LT		 3325 /* Bypass reserved domain fields. */
3326 if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0)
3327 continue;
3328
e8c72ba5 3329 /* Bypass ports whose FCP-4 type is not FCP_SCSI */
4da26e16
CD		 3330 if (ql2xgffidenable &&
3331 (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI &&
3332 new_fcport->fc4_type != FC4_TYPE_UNKNOWN))
e8c72ba5
CD		 3333 continue;
3334
1da177e4
LT		 3335 /* Locate matching device in database. */
3336 found = 0;
e315cd28 3337 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 3338 if (memcmp(new_fcport->port_name, fcport->port_name,
3339 WWN_SIZE))
3340 continue;
3341
c0822b63 3342 fcport->scan_state = QLA_FCPORT_SCAN_FOUND;
b3b02e6e 3343
1da177e4
LT		 3344 found++;
3345
d8b45213
AV		 3346 /* Update port state. */
3347 memcpy(fcport->fabric_port_name,
3348 new_fcport->fabric_port_name, WWN_SIZE);
3349 fcport->fp_speed = new_fcport->fp_speed;
3350
1da177e4
LT		 3351 /*
3352 * If address the same and state FCS_ONLINE, nothing
3353 * changed.
3354 */
3355 if (fcport->d_id.b24 == new_fcport->d_id.b24 &&
3356 atomic_read(&fcport->state) == FCS_ONLINE) {
3357 break;
3358 }
3359
3360 /*
3361 * If device was not a fabric device before.
3362 */
3363 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) {
3364 fcport->d_id.b24 = new_fcport->d_id.b24;
5f16b331 3365 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 3366 fcport->flags |= (FCF_FABRIC_DEVICE |
3367 FCF_LOGIN_NEEDED);
1da177e4
LT		 3368 break;
3369 }
3370
3371 /*
3372 * Port ID changed or device was marked to be updated;
3373 * Log it out if still logged in and mark it for
3374 * relogin later.
3375 */
3376 fcport->d_id.b24 = new_fcport->d_id.b24;
3377 fcport->flags |= FCF_LOGIN_NEEDED;
3378 if (fcport->loop_id != FC_NO_LOOP_ID &&
f08b7251 3379 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
0eba25df 3380 (fcport->flags & FCF_ASYNC_SENT) == 0 &&
1da177e4
LT		 3381 fcport->port_type != FCT_INITIATOR &&
3382 fcport->port_type != FCT_BROADCAST) {
e315cd28 3383 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3384 fcport->d_id.b.domain, fcport->d_id.b.area,
3385 fcport->d_id.b.al_pa);
5f16b331 3386 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 3387 }
3388
3389 break;
3390 }
3391
3392 if (found)
3393 continue;
1da177e4
LT		 3394 /* If device was not in our fcports list, then add it. */
3395 list_add_tail(&new_fcport->list, new_fcports);
3396
3397 /* Allocate a new replacement fcport. */
3398 nxt_d_id.b24 = new_fcport->d_id.b24;
e315cd28 3399 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3400 if (new_fcport == NULL) {
7c3df132
SK		 3401 ql_log(ql_log_warn, vha, 0x2066,
3402 "Memory allocation failed for fcport.\n");
1da177e4
LT		 3403 return (QLA_MEMORY_ALLOC_FAILED);
3404 }
3405 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
3406 new_fcport->d_id.b24 = nxt_d_id.b24;
3407 }
3408
c9475cb0 3409 kfree(new_fcport);
1da177e4 3410
1da177e4
LT		 3411 return (rval);
3412}
3413
3414/*
3415 * qla2x00_find_new_loop_id
3416 * Scan through our port list and find a new usable loop ID.
3417 *
3418 * Input:
3419 * ha: adapter state pointer.
3420 * dev: port structure pointer.
3421 *
3422 * Returns:
3423 * qla2x00 local function return status code.
3424 *
3425 * Context:
3426 * Kernel context.
3427 */
03bcfb57 3428int
e315cd28 3429qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
1da177e4
LT		 3430{
3431 int rval;
e315cd28 3432 struct qla_hw_data *ha = vha->hw;
feafb7b1 3433 unsigned long flags = 0;
1da177e4
LT		 3434
3435 rval = QLA_SUCCESS;
3436
5f16b331 3437 spin_lock_irqsave(&ha->vport_slock, flags);
1da177e4 3438
5f16b331
CD		 3439 dev->loop_id = find_first_zero_bit(ha->loop_id_map,
3440 LOOPID_MAP_SIZE);
3441 if (dev->loop_id >= LOOPID_MAP_SIZE ||
3442 qla2x00_is_reserved_id(vha, dev->loop_id)) {
3443 dev->loop_id = FC_NO_LOOP_ID;
3444 rval = QLA_FUNCTION_FAILED;
3445 } else
3446 set_bit(dev->loop_id, ha->loop_id_map);
1da177e4 3447
5f16b331 3448 spin_unlock_irqrestore(&ha->vport_slock, flags);
1da177e4 3449
5f16b331
CD		 3450 if (rval == QLA_SUCCESS)
3451 ql_dbg(ql_dbg_disc, dev->vha, 0x2086,
3452 "Assigning new loopid=%x, portid=%x.\n",
3453 dev->loop_id, dev->d_id.b24);
3454 else
3455 ql_log(ql_log_warn, dev->vha, 0x2087,
3456 "No loop_id's available, portid=%x.\n",
3457 dev->d_id.b24);
1da177e4
LT		 3458
3459 return (rval);
3460}
3461
1da177e4
LT		 3462/*
3463 * qla2x00_fabric_dev_login
3464 * Login fabric target device and update FC port database.
3465 *
3466 * Input:
3467 * ha: adapter state pointer.
3468 * fcport: port structure list pointer.
3469 * next_loopid: contains value of a new loop ID that can be used
3470 * by the next login attempt.
3471 *
3472 * Returns:
3473 * qla2x00 local function return status code.
3474 *
3475 * Context:
3476 * Kernel context.
3477 */
3478static int
e315cd28 3479qla2x00_fabric_dev_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 3480 uint16_t *next_loopid)
3481{
3482 int rval;
3483 int retry;
0107109e 3484 uint8_t opts;
e315cd28 3485 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3486
3487 rval = QLA_SUCCESS;
3488 retry = 0;
3489
ac280b67 3490 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584
AV		 3491 if (fcport->flags & FCF_ASYNC_SENT)
3492 return rval;
3493 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 3494 rval = qla2x00_post_async_login_work(vha, fcport, NULL);
3495 if (!rval)
3496 return rval;
3497 }
3498
5ff1d584 3499 fcport->flags &= ~FCF_ASYNC_SENT;
e315cd28 3500 rval = qla2x00_fabric_login(vha, fcport, next_loopid);
1da177e4 3501 if (rval == QLA_SUCCESS) {
f08b7251 3502 /* Send an ADISC to FCP2 devices.*/
0107109e 3503 opts = 0;
f08b7251 3504 if (fcport->flags & FCF_FCP2_DEVICE)
0107109e 3505 opts |= BIT_1;
e315cd28 3506 rval = qla2x00_get_port_database(vha, fcport, opts);
1da177e4 3507 if (rval != QLA_SUCCESS) {
e315cd28 3508 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3509 fcport->d_id.b.domain, fcport->d_id.b.area,
3510 fcport->d_id.b.al_pa);
e315cd28 3511 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4 3512 } else {
e315cd28 3513 qla2x00_update_fcport(vha, fcport);
1da177e4 3514 }
0b91d116
CD		 3515 } else {
3516 /* Retry Login. */
3517 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 3518 }
3519
3520 return (rval);
3521}
3522
3523/*
3524 * qla2x00_fabric_login
3525 * Issue fabric login command.
3526 *
3527 * Input:
3528 * ha = adapter block pointer.
3529 * device = pointer to FC device type structure.
3530 *
3531 * Returns:
3532 * 0 - Login successfully
3533 * 1 - Login failed
3534 * 2 - Initiator device
3535 * 3 - Fatal error
3536 */
3537int
e315cd28 3538qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 3539 uint16_t *next_loopid)
3540{
3541 int rval;
3542 int retry;
3543 uint16_t tmp_loopid;
3544 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 3545 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3546
3547 retry = 0;
3548 tmp_loopid = 0;
3549
3550 for (;;) {
7c3df132
SK		 3551 ql_dbg(ql_dbg_disc, vha, 0x2000,
3552 "Trying Fabric Login w/loop id 0x%04x for port "
3553 "%02x%02x%02x.\n",
3554 fcport->loop_id, fcport->d_id.b.domain,
3555 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 3556
3557 /* Login fcport on switch. */
0b91d116 3558 rval = ha->isp_ops->fabric_login(vha, fcport->loop_id,
1da177e4
LT		 3559 fcport->d_id.b.domain, fcport->d_id.b.area,
3560 fcport->d_id.b.al_pa, mb, BIT_0);
0b91d116
CD		 3561 if (rval != QLA_SUCCESS) {
3562 return rval;
3563 }
1da177e4
LT		 3564 if (mb[0] == MBS_PORT_ID_USED) {
3565 /*
3566 * Device has another loop ID. The firmware team
0107109e
AV		 3567 * recommends the driver perform an implicit login with
3568 * the specified ID again. The ID we just used is save
3569 * here so we return with an ID that can be tried by
3570 * the next login.
1da177e4
LT		 3571 */
3572 retry++;
3573 tmp_loopid = fcport->loop_id;
3574 fcport->loop_id = mb[1];
3575
7c3df132
SK		 3576 ql_dbg(ql_dbg_disc, vha, 0x2001,
3577 "Fabric Login: port in use - next loop "
3578 "id=0x%04x, port id= %02x%02x%02x.\n",
1da177e4 3579 fcport->loop_id, fcport->d_id.b.domain,
7c3df132 3580 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 3581
3582 } else if (mb[0] == MBS_COMMAND_COMPLETE) {
3583 /*
3584 * Login succeeded.
3585 */
3586 if (retry) {
3587 /* A retry occurred before. */
3588 *next_loopid = tmp_loopid;
3589 } else {
3590 /*
3591 * No retry occurred before. Just increment the
3592 * ID value for next login.
3593 */
3594 *next_loopid = (fcport->loop_id + 1);
3595 }
3596
3597 if (mb[1] & BIT_0) {
3598 fcport->port_type = FCT_INITIATOR;
3599 } else {
3600 fcport->port_type = FCT_TARGET;
3601 if (mb[1] & BIT_1) {
8474f3a0 3602 fcport->flags |= FCF_FCP2_DEVICE;
1da177e4
LT		 3603 }
3604 }
3605
ad3e0eda
AV		 3606 if (mb[10] & BIT_0)
3607 fcport->supported_classes |= FC_COS_CLASS2;
3608 if (mb[10] & BIT_1)
3609 fcport->supported_classes |= FC_COS_CLASS3;
3610
2d70c103
NB		 3611 if (IS_FWI2_CAPABLE(ha)) {
3612 if (mb[10] & BIT_7)
3613 fcport->flags |=
3614 FCF_CONF_COMP_SUPPORTED;
3615 }
3616
1da177e4
LT		 3617 rval = QLA_SUCCESS;
3618 break;
3619 } else if (mb[0] == MBS_LOOP_ID_USED) {
3620 /*
3621 * Loop ID already used, try next loop ID.
3622 */
3623 fcport->loop_id++;
e315cd28 3624 rval = qla2x00_find_new_loop_id(vha, fcport);
1da177e4
LT		 3625 if (rval != QLA_SUCCESS) {
3626 /* Ran out of loop IDs to use */
3627 break;
3628 }
3629 } else if (mb[0] == MBS_COMMAND_ERROR) {
3630 /*
3631 * Firmware possibly timed out during login. If NO
3632 * retries are left to do then the device is declared
3633 * dead.
3634 */
3635 *next_loopid = fcport->loop_id;
e315cd28 3636 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3637 fcport->d_id.b.domain, fcport->d_id.b.area,
3638 fcport->d_id.b.al_pa);
e315cd28 3639 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 3640
3641 rval = 1;
3642 break;
3643 } else {
3644 /*
3645 * unrecoverable / not handled error
3646 */
7c3df132
SK		 3647 ql_dbg(ql_dbg_disc, vha, 0x2002,
3648 "Failed=%x port_id=%02x%02x%02x loop_id=%x "
3649 "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain,
3650 fcport->d_id.b.area, fcport->d_id.b.al_pa,
3651 fcport->loop_id, jiffies);
1da177e4
LT		 3652
3653 *next_loopid = fcport->loop_id;
e315cd28 3654 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3655 fcport->d_id.b.domain, fcport->d_id.b.area,
3656 fcport->d_id.b.al_pa);
5f16b331 3657 qla2x00_clear_loop_id(fcport);
0eedfcf0 3658 fcport->login_retry = 0;
1da177e4
LT		 3659
3660 rval = 3;
3661 break;
3662 }
3663 }
3664
3665 return (rval);
3666}
3667
3668/*
3669 * qla2x00_local_device_login
3670 * Issue local device login command.
3671 *
3672 * Input:
3673 * ha = adapter block pointer.
3674 * loop_id = loop id of device to login to.
3675 *
3676 * Returns (Where's the #define!!!!):
3677 * 0 - Login successfully
3678 * 1 - Login failed
3679 * 3 - Fatal error
3680 */
3681int
e315cd28 3682qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport)
1da177e4
LT		 3683{
3684 int rval;
3685 uint16_t mb[MAILBOX_REGISTER_COUNT];
3686
3687 memset(mb, 0, sizeof(mb));
e315cd28 3688 rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0);
1da177e4
LT		 3689 if (rval == QLA_SUCCESS) {
3690 /* Interrogate mailbox registers for any errors */
3691 if (mb[0] == MBS_COMMAND_ERROR)
3692 rval = 1;
3693 else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR)
3694 /* device not in PCB table */
3695 rval = 3;
3696 }
3697
3698 return (rval);
3699}
3700
3701/*
3702 * qla2x00_loop_resync
3703 * Resync with fibre channel devices.
3704 *
3705 * Input:
3706 * ha = adapter block pointer.
3707 *
3708 * Returns:
3709 * 0 = success
3710 */
3711int
e315cd28 3712qla2x00_loop_resync(scsi_qla_host_t *vha)
1da177e4 3713{
73208dfd 3714 int rval = QLA_SUCCESS;
1da177e4 3715 uint32_t wait_time;
67c2e93a
AC		 3716 struct req_que *req;
3717 struct rsp_que *rsp;
3718
7163ea81 3719 if (vha->hw->flags.cpu_affinity_enabled)
67c2e93a
AC		 3720 req = vha->hw->req_q_map[0];
3721 else
3722 req = vha->req;
3723 rsp = req->rsp;
1da177e4 3724
e315cd28
AC		 3725 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
3726 if (vha->flags.online) {
3727 if (!(rval = qla2x00_fw_ready(vha))) {
1da177e4
LT		 3728 /* Wait at most MAX_TARGET RSCNs for a stable link. */
3729 wait_time = 256;
3730 do {
0107109e 3731 /* Issue a marker after FW becomes ready. */
73208dfd
AC		 3732 qla2x00_marker(vha, req, rsp, 0, 0,
3733 MK_SYNC_ALL);
e315cd28 3734 vha->marker_needed = 0;
1da177e4
LT		 3735
3736 /* Remap devices on Loop. */
e315cd28 3737 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4 3738
e315cd28 3739 qla2x00_configure_loop(vha);
1da177e4 3740 wait_time--;
e315cd28
AC		 3741 } while (!atomic_read(&vha->loop_down_timer) &&
3742 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
3743 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
3744 &vha->dpc_flags)));
1da177e4 3745 }
1da177e4
LT		 3746 }
3747
e315cd28 3748 if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
1da177e4 3749 return (QLA_FUNCTION_FAILED);
1da177e4 3750
e315cd28 3751 if (rval)
7c3df132
SK		 3752 ql_dbg(ql_dbg_disc, vha, 0x206c,
3753 "%s *** FAILED ***.\n", __func__);
1da177e4
LT		 3754
3755 return (rval);
3756}
3757
579d12b5
SK		 3758/*
3759* qla2x00_perform_loop_resync
3760* Description: This function will set the appropriate flags and call
3761* qla2x00_loop_resync. If successful loop will be resynced
3762* Arguments : scsi_qla_host_t pointer
3763* returm : Success or Failure
3764*/
3765
3766int qla2x00_perform_loop_resync(scsi_qla_host_t *ha)
3767{
3768 int32_t rval = 0;
3769
3770 if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) {
3771 /*Configure the flags so that resync happens properly*/
3772 atomic_set(&ha->loop_down_timer, 0);
3773 if (!(ha->device_flags & DFLG_NO_CABLE)) {
3774 atomic_set(&ha->loop_state, LOOP_UP);
3775 set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags);
3776 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
3777 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
3778
3779 rval = qla2x00_loop_resync(ha);
3780 } else
3781 atomic_set(&ha->loop_state, LOOP_DEAD);
3782
3783 clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags);
3784 }
3785
3786 return rval;
3787}
3788
d97994dc 3789void
67becc00 3790qla2x00_update_fcports(scsi_qla_host_t *base_vha)
d97994dc
AV		 3791{
3792 fc_port_t *fcport;
feafb7b1
AE		 3793 struct scsi_qla_host *vha;
3794 struct qla_hw_data *ha = base_vha->hw;
3795 unsigned long flags;
d97994dc 3796
feafb7b1 3797 spin_lock_irqsave(&ha->vport_slock, flags);
d97994dc 3798 /* Go with deferred removal of rport references. */
feafb7b1
AE		 3799 list_for_each_entry(vha, &base_vha->hw->vp_list, list) {
3800 atomic_inc(&vha->vref_count);
3801 list_for_each_entry(fcport, &vha->vp_fcports, list) {
8ae598d0 3802 if (fcport->drport &&
feafb7b1
AE		 3803 atomic_read(&fcport->state) != FCS_UNCONFIGURED) {
3804 spin_unlock_irqrestore(&ha->vport_slock, flags);
3805
67becc00 3806 qla2x00_rport_del(fcport);
feafb7b1
AE		 3807
3808 spin_lock_irqsave(&ha->vport_slock, flags);
3809 }
3810 }
3811 atomic_dec(&vha->vref_count);
3812 }
3813 spin_unlock_irqrestore(&ha->vport_slock, flags);
d97994dc
AV		 3814}
3815
7d613ac6
SV		 3816/* Assumes idc_lock always held on entry */
3817void
3818qla83xx_reset_ownership(scsi_qla_host_t *vha)
3819{
3820 struct qla_hw_data *ha = vha->hw;
3821 uint32_t drv_presence, drv_presence_mask;
3822 uint32_t dev_part_info1, dev_part_info2, class_type;
3823 uint32_t class_type_mask = 0x3;
3824 uint16_t fcoe_other_function = 0xffff, i;
3825
3826 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
3827
3828 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1);
3829 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2);
3830 for (i = 0; i < 8; i++) {
3831 class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask);
3832 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
3833 (i != ha->portnum)) {
3834 fcoe_other_function = i;
3835 break;
3836 }
3837 }
3838 if (fcoe_other_function == 0xffff) {
3839 for (i = 0; i < 8; i++) {
3840 class_type = ((dev_part_info2 >> (i * 4)) &
3841 class_type_mask);
3842 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
3843 ((i + 8) != ha->portnum)) {
3844 fcoe_other_function = i + 8;
3845 break;
3846 }
3847 }
3848 }
3849 /*
3850 * Prepare drv-presence mask based on fcoe functions present.
3851 * However consider only valid physical fcoe function numbers (0-15).
3852 */
3853 drv_presence_mask = ~((1 << (ha->portnum)) |
3854 ((fcoe_other_function == 0xffff) ?
3855 0 : (1 << (fcoe_other_function))));
3856
3857 /* We are the reset owner iff:
3858 * - No other protocol drivers present.
3859 * - This is the lowest among fcoe functions. */
3860 if (!(drv_presence & drv_presence_mask) &&
3861 (ha->portnum < fcoe_other_function)) {
3862 ql_dbg(ql_dbg_p3p, vha, 0xb07f,
3863 "This host is Reset owner.\n");
3864 ha->flags.nic_core_reset_owner = 1;
3865 }
3866}
3867
fa492630 3868static int
7d613ac6
SV		 3869__qla83xx_set_drv_ack(scsi_qla_host_t *vha)
3870{
3871 int rval = QLA_SUCCESS;
3872 struct qla_hw_data *ha = vha->hw;
3873 uint32_t drv_ack;
3874
3875 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
3876 if (rval == QLA_SUCCESS) {
3877 drv_ack |= (1 << ha->portnum);
3878 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
3879 }
3880
3881 return rval;
3882}
3883
fa492630 3884static int
7d613ac6
SV		 3885__qla83xx_clear_drv_ack(scsi_qla_host_t *vha)
3886{
3887 int rval = QLA_SUCCESS;
3888 struct qla_hw_data *ha = vha->hw;
3889 uint32_t drv_ack;
3890
3891 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
3892 if (rval == QLA_SUCCESS) {
3893 drv_ack &= ~(1 << ha->portnum);
3894 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
3895 }
3896
3897 return rval;
3898}
3899
fa492630 3900static const char *
7d613ac6
SV		 3901qla83xx_dev_state_to_string(uint32_t dev_state)
3902{
3903 switch (dev_state) {
3904 case QLA8XXX_DEV_COLD:
3905 return "COLD/RE-INIT";
3906 case QLA8XXX_DEV_INITIALIZING:
3907 return "INITIALIZING";
3908 case QLA8XXX_DEV_READY:
3909 return "READY";
3910 case QLA8XXX_DEV_NEED_RESET:
3911 return "NEED RESET";
3912 case QLA8XXX_DEV_NEED_QUIESCENT:
3913 return "NEED QUIESCENT";
3914 case QLA8XXX_DEV_FAILED:
3915 return "FAILED";
3916 case QLA8XXX_DEV_QUIESCENT:
3917 return "QUIESCENT";
3918 default:
3919 return "Unknown";
3920 }
3921}
3922
3923/* Assumes idc-lock always held on entry */
3924void
3925qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type)
3926{
3927 struct qla_hw_data *ha = vha->hw;
3928 uint32_t idc_audit_reg = 0, duration_secs = 0;
3929
3930 switch (audit_type) {
3931 case IDC_AUDIT_TIMESTAMP:
3932 ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000);
3933 idc_audit_reg = (ha->portnum) |
3934 (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8);
3935 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
3936 break;
3937
3938 case IDC_AUDIT_COMPLETION:
3939 duration_secs = ((jiffies_to_msecs(jiffies) -
3940 jiffies_to_msecs(ha->idc_audit_ts)) / 1000);
3941 idc_audit_reg = (ha->portnum) |
3942 (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8);
3943 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
3944 break;
3945
3946 default:
3947 ql_log(ql_log_warn, vha, 0xb078,
3948 "Invalid audit type specified.\n");
3949 break;
3950 }
3951}
3952
3953/* Assumes idc_lock always held on entry */
fa492630 3954static int
7d613ac6
SV		 3955qla83xx_initiating_reset(scsi_qla_host_t *vha)
3956{
3957 struct qla_hw_data *ha = vha->hw;
3958 uint32_t idc_control, dev_state;
3959
3960 __qla83xx_get_idc_control(vha, &idc_control);
3961 if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) {
3962 ql_log(ql_log_info, vha, 0xb080,
3963 "NIC Core reset has been disabled. idc-control=0x%x\n",
3964 idc_control);
3965 return QLA_FUNCTION_FAILED;
3966 }
3967
3968 /* Set NEED-RESET iff in READY state and we are the reset-owner */
3969 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
3970 if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) {
3971 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
3972 QLA8XXX_DEV_NEED_RESET);
3973 ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n");
3974 qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP);
3975 } else {
3976 const char *state = qla83xx_dev_state_to_string(dev_state);
3977 ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n", state);
3978
3979 /* SV: XXX: Is timeout required here? */
3980 /* Wait for IDC state change READY -> NEED_RESET */
3981 while (dev_state == QLA8XXX_DEV_READY) {
3982 qla83xx_idc_unlock(vha, 0);
3983 msleep(200);
3984 qla83xx_idc_lock(vha, 0);
3985 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
3986 }
3987 }
3988
3989 /* Send IDC ack by writing to drv-ack register */
3990 __qla83xx_set_drv_ack(vha);
3991
3992 return QLA_SUCCESS;
3993}
3994
3995int
3996__qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control)
3997{
3998 return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
3999}
4000
7d613ac6
SV		 4001int
4002__qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control)
4003{
4004 return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
4005}
4006
fa492630 4007static int
7d613ac6
SV		 4008qla83xx_check_driver_presence(scsi_qla_host_t *vha)
4009{
4010 uint32_t drv_presence = 0;
4011 struct qla_hw_data *ha = vha->hw;
4012
4013 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4014 if (drv_presence & (1 << ha->portnum))
4015 return QLA_SUCCESS;
4016 else
4017 return QLA_TEST_FAILED;
4018}
4019
4020int
4021qla83xx_nic_core_reset(scsi_qla_host_t *vha)
4022{
4023 int rval = QLA_SUCCESS;
4024 struct qla_hw_data *ha = vha->hw;
4025
4026 ql_dbg(ql_dbg_p3p, vha, 0xb058,
4027 "Entered %s().\n", __func__);
4028
4029 if (vha->device_flags & DFLG_DEV_FAILED) {
4030 ql_log(ql_log_warn, vha, 0xb059,
4031 "Device in unrecoverable FAILED state.\n");
4032 return QLA_FUNCTION_FAILED;
4033 }
4034
4035 qla83xx_idc_lock(vha, 0);
4036
4037 if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) {
4038 ql_log(ql_log_warn, vha, 0xb05a,
4039 "Function=0x%x has been removed from IDC participation.\n",
4040 ha->portnum);
4041 rval = QLA_FUNCTION_FAILED;
4042 goto exit;
4043 }
4044
4045 qla83xx_reset_ownership(vha);
4046
4047 rval = qla83xx_initiating_reset(vha);
4048
4049 /*
4050 * Perform reset if we are the reset-owner,
4051 * else wait till IDC state changes to READY/FAILED.
4052 */
4053 if (rval == QLA_SUCCESS) {
4054 rval = qla83xx_idc_state_handler(vha);
4055
4056 if (rval == QLA_SUCCESS)
4057 ha->flags.nic_core_hung = 0;
4058 __qla83xx_clear_drv_ack(vha);
4059 }
4060
4061exit:
4062 qla83xx_idc_unlock(vha, 0);
4063
4064 ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__);
4065
4066 return rval;
4067}
4068
81178772
SK		 4069int
4070qla2xxx_mctp_dump(scsi_qla_host_t *vha)
4071{
4072 struct qla_hw_data *ha = vha->hw;
4073 int rval = QLA_FUNCTION_FAILED;
4074
4075 if (!IS_MCTP_CAPABLE(ha)) {
4076 /* This message can be removed from the final version */
4077 ql_log(ql_log_info, vha, 0x506d,
4078 "This board is not MCTP capable\n");
4079 return rval;
4080 }
4081
4082 if (!ha->mctp_dump) {
4083 ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev,
4084 MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL);
4085
4086 if (!ha->mctp_dump) {
4087 ql_log(ql_log_warn, vha, 0x506e,
4088 "Failed to allocate memory for mctp dump\n");
4089 return rval;
4090 }
4091 }
4092
4093#define MCTP_DUMP_STR_ADDR 0x00000000
4094 rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma,
4095 MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4);
4096 if (rval != QLA_SUCCESS) {
4097 ql_log(ql_log_warn, vha, 0x506f,
4098 "Failed to capture mctp dump\n");
4099 } else {
4100 ql_log(ql_log_info, vha, 0x5070,
4101 "Mctp dump capture for host (%ld/%p).\n",
4102 vha->host_no, ha->mctp_dump);
4103 ha->mctp_dumped = 1;
4104 }
4105
409ee0fe 4106 if (!ha->flags.nic_core_reset_hdlr_active && !ha->portnum) {
81178772
SK		 4107 ha->flags.nic_core_reset_hdlr_active = 1;
4108 rval = qla83xx_restart_nic_firmware(vha);
4109 if (rval)
4110 /* NIC Core reset failed. */
4111 ql_log(ql_log_warn, vha, 0x5071,
4112 "Failed to restart nic firmware\n");
4113 else
4114 ql_dbg(ql_dbg_p3p, vha, 0xb084,
4115 "Restarted NIC firmware successfully.\n");
4116 ha->flags.nic_core_reset_hdlr_active = 0;
4117 }
4118
4119 return rval;
4120
4121}
4122
579d12b5 4123/*
8fcd6b8b 4124* qla2x00_quiesce_io
579d12b5
SK		 4125* Description: This function will block the new I/Os
4126* Its not aborting any I/Os as context
4127* is not destroyed during quiescence
4128* Arguments: scsi_qla_host_t
4129* return : void
4130*/
4131void
8fcd6b8b 4132qla2x00_quiesce_io(scsi_qla_host_t *vha)
579d12b5
SK		 4133{
4134 struct qla_hw_data *ha = vha->hw;
4135 struct scsi_qla_host *vp;
4136
8fcd6b8b
CD		 4137 ql_dbg(ql_dbg_dpc, vha, 0x401d,
4138 "Quiescing I/O - ha=%p.\n", ha);
579d12b5
SK		 4139
4140 atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME);
4141 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
4142 atomic_set(&vha->loop_state, LOOP_DOWN);
4143 qla2x00_mark_all_devices_lost(vha, 0);
4144 list_for_each_entry(vp, &ha->vp_list, list)
8fcd6b8b 4145 qla2x00_mark_all_devices_lost(vp, 0);
579d12b5
SK		 4146 } else {
4147 if (!atomic_read(&vha->loop_down_timer))
4148 atomic_set(&vha->loop_down_timer,
4149 LOOP_DOWN_TIME);
4150 }
4151 /* Wait for pending cmds to complete */
4152 qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST);
4153}
4154
a9083016
GM		 4155void
4156qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
4157{
4158 struct qla_hw_data *ha = vha->hw;
579d12b5 4159 struct scsi_qla_host *vp;
feafb7b1 4160 unsigned long flags;
6aef87be 4161 fc_port_t *fcport;
a9083016 4162
e46ef004
SK		 4163 /* For ISP82XX, driver waits for completion of the commands.
4164 * online flag should be set.
4165 */
4166 if (!IS_QLA82XX(ha))
4167 vha->flags.online = 0;
a9083016
GM		 4168 ha->flags.chip_reset_done = 0;
4169 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2be21fa2 4170 vha->qla_stats.total_isp_aborts++;
a9083016 4171
7c3df132
SK		 4172 ql_log(ql_log_info, vha, 0x00af,
4173 "Performing ISP error recovery - ha=%p.\n", ha);
a9083016 4174
e46ef004
SK		 4175 /* For ISP82XX, reset_chip is just disabling interrupts.
4176 * Driver waits for the completion of the commands.
4177 * the interrupts need to be enabled.
4178 */
a9083016
GM		 4179 if (!IS_QLA82XX(ha))
4180 ha->isp_ops->reset_chip(vha);
4181
4182 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
4183 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
4184 atomic_set(&vha->loop_state, LOOP_DOWN);
4185 qla2x00_mark_all_devices_lost(vha, 0);
feafb7b1
AE		 4186
4187 spin_lock_irqsave(&ha->vport_slock, flags);
579d12b5 4188 list_for_each_entry(vp, &ha->vp_list, list) {
feafb7b1
AE		 4189 atomic_inc(&vp->vref_count);
4190 spin_unlock_irqrestore(&ha->vport_slock, flags);
4191
a9083016 4192 qla2x00_mark_all_devices_lost(vp, 0);
feafb7b1
AE		 4193
4194 spin_lock_irqsave(&ha->vport_slock, flags);
4195 atomic_dec(&vp->vref_count);
4196 }
4197 spin_unlock_irqrestore(&ha->vport_slock, flags);
a9083016
GM		 4198 } else {
4199 if (!atomic_read(&vha->loop_down_timer))
4200 atomic_set(&vha->loop_down_timer,
4201 LOOP_DOWN_TIME);
4202 }
4203
6aef87be
AV		 4204 /* Clear all async request states across all VPs. */
4205 list_for_each_entry(fcport, &vha->vp_fcports, list)
4206 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
4207 spin_lock_irqsave(&ha->vport_slock, flags);
4208 list_for_each_entry(vp, &ha->vp_list, list) {
4209 atomic_inc(&vp->vref_count);
4210 spin_unlock_irqrestore(&ha->vport_slock, flags);
4211
4212 list_for_each_entry(fcport, &vp->vp_fcports, list)
4213 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
4214
4215 spin_lock_irqsave(&ha->vport_slock, flags);
4216 atomic_dec(&vp->vref_count);
4217 }
4218 spin_unlock_irqrestore(&ha->vport_slock, flags);
4219
bddd2d65
LC		 4220 if (!ha->flags.eeh_busy) {
4221 /* Make sure for ISP 82XX IO DMA is complete */
4222 if (IS_QLA82XX(ha)) {
7190575f 4223 qla82xx_chip_reset_cleanup(vha);
7c3df132
SK		 4224 ql_log(ql_log_info, vha, 0x00b4,
4225 "Done chip reset cleanup.\n");
a9083016 4226
e46ef004
SK		 4227 /* Done waiting for pending commands.
4228 * Reset the online flag.
4229 */
4230 vha->flags.online = 0;
4d78c973 4231 }
a9083016 4232
bddd2d65
LC		 4233 /* Requeue all commands in outstanding command list. */
4234 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
4235 }
a9083016
GM		 4236}
4237
1da177e4
LT		 4238/*
4239* qla2x00_abort_isp
4240* Resets ISP and aborts all outstanding commands.
4241*
4242* Input:
4243* ha = adapter block pointer.
4244*
4245* Returns:
4246* 0 = success
4247*/
4248int
e315cd28 4249qla2x00_abort_isp(scsi_qla_host_t *vha)
1da177e4 4250{
476e8978 4251 int rval;
1da177e4 4252 uint8_t status = 0;
e315cd28
AC		 4253 struct qla_hw_data *ha = vha->hw;
4254 struct scsi_qla_host *vp;
73208dfd 4255 struct req_que *req = ha->req_q_map[0];
feafb7b1 4256 unsigned long flags;
1da177e4 4257
e315cd28 4258 if (vha->flags.online) {
a9083016 4259 qla2x00_abort_isp_cleanup(vha);
1da177e4 4260
a6171297
SV		 4261 if (IS_QLA8031(ha)) {
4262 ql_dbg(ql_dbg_p3p, vha, 0xb05c,
4263 "Clearing fcoe driver presence.\n");
4264 if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS)
4265 ql_dbg(ql_dbg_p3p, vha, 0xb073,
4266 "Error while clearing DRV-Presence.\n");
4267 }
4268
85880801
AV		 4269 if (unlikely(pci_channel_offline(ha->pdev) &&
4270 ha->flags.pci_channel_io_perm_failure)) {
4271 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
4272 status = 0;
4273 return status;
4274 }
4275
73208dfd 4276 ha->isp_ops->get_flash_version(vha, req->ring);
30c47662 4277
e315cd28 4278 ha->isp_ops->nvram_config(vha);
1da177e4 4279
e315cd28
AC		 4280 if (!qla2x00_restart_isp(vha)) {
4281 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4 4282
e315cd28 4283 if (!atomic_read(&vha->loop_down_timer)) {
1da177e4
LT		 4284 /*
4285 * Issue marker command only when we are going
4286 * to start the I/O .
4287 */
e315cd28 4288 vha->marker_needed = 1;
1da177e4
LT		 4289 }
4290
e315cd28 4291 vha->flags.online = 1;
1da177e4 4292
fd34f556 4293 ha->isp_ops->enable_intrs(ha);
1da177e4 4294
fa2a1ce5 4295 ha->isp_abort_cnt = 0;
e315cd28 4296 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
476e8978 4297
6246b8a1
GM		 4298 if (IS_QLA81XX(ha) || IS_QLA8031(ha))
4299 qla2x00_get_fw_version(vha);
df613b96
AV		 4300 if (ha->fce) {
4301 ha->flags.fce_enabled = 1;
4302 memset(ha->fce, 0,
4303 fce_calc_size(ha->fce_bufs));
e315cd28 4304 rval = qla2x00_enable_fce_trace(vha,
df613b96
AV		 4305 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
4306 &ha->fce_bufs);
4307 if (rval) {
7c3df132 4308 ql_log(ql_log_warn, vha, 0x8033,
df613b96
AV		 4309 "Unable to reinitialize FCE "
4310 "(%d).\n", rval);
4311 ha->flags.fce_enabled = 0;
4312 }
4313 }
436a7b11
AV		 4314
4315 if (ha->eft) {
4316 memset(ha->eft, 0, EFT_SIZE);
e315cd28 4317 rval = qla2x00_enable_eft_trace(vha,
436a7b11
AV		 4318 ha->eft_dma, EFT_NUM_BUFFERS);
4319 if (rval) {
7c3df132 4320 ql_log(ql_log_warn, vha, 0x8034,
436a7b11
AV		 4321 "Unable to reinitialize EFT "
4322 "(%d).\n", rval);
4323 }
4324 }
1da177e4 4325 } else { /* failed the ISP abort */
e315cd28
AC		 4326 vha->flags.online = 1;
4327 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
1da177e4 4328 if (ha->isp_abort_cnt == 0) {
7c3df132
SK		 4329 ql_log(ql_log_fatal, vha, 0x8035,
4330 "ISP error recover failed - "
4331 "board disabled.\n");
fa2a1ce5 4332 /*
1da177e4
LT		 4333 * The next call disables the board
4334 * completely.
4335 */
e315cd28
AC		 4336 ha->isp_ops->reset_adapter(vha);
4337 vha->flags.online = 0;
1da177e4 4338 clear_bit(ISP_ABORT_RETRY,
e315cd28 4339 &vha->dpc_flags);
1da177e4
LT		 4340 status = 0;
4341 } else { /* schedule another ISP abort */
4342 ha->isp_abort_cnt--;
7c3df132
SK		 4343 ql_dbg(ql_dbg_taskm, vha, 0x8020,
4344 "ISP abort - retry remaining %d.\n",
4345 ha->isp_abort_cnt);
1da177e4
LT		 4346 status = 1;
4347 }
4348 } else {
4349 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
7c3df132
SK		 4350 ql_dbg(ql_dbg_taskm, vha, 0x8021,
4351 "ISP error recovery - retrying (%d) "
4352 "more times.\n", ha->isp_abort_cnt);
e315cd28 4353 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
1da177e4
LT		 4354 status = 1;
4355 }
4356 }
fa2a1ce5 4357
1da177e4
LT		 4358 }
4359
e315cd28 4360 if (!status) {
7c3df132 4361 ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__);
feafb7b1
AE		 4362
4363 spin_lock_irqsave(&ha->vport_slock, flags);
4364 list_for_each_entry(vp, &ha->vp_list, list) {
4365 if (vp->vp_idx) {
4366 atomic_inc(&vp->vref_count);
4367 spin_unlock_irqrestore(&ha->vport_slock, flags);
4368
e315cd28 4369 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 4370
4371 spin_lock_irqsave(&ha->vport_slock, flags);
4372 atomic_dec(&vp->vref_count);
4373 }
e315cd28 4374 }
feafb7b1
AE		 4375 spin_unlock_irqrestore(&ha->vport_slock, flags);
4376
7d613ac6
SV		 4377 if (IS_QLA8031(ha)) {
4378 ql_dbg(ql_dbg_p3p, vha, 0xb05d,
4379 "Setting back fcoe driver presence.\n");
4380 if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS)
4381 ql_dbg(ql_dbg_p3p, vha, 0xb074,
4382 "Error while setting DRV-Presence.\n");
4383 }
e315cd28 4384 } else {
d8424f68
JP		 4385 ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n",
4386 __func__);
1da177e4
LT		 4387 }
4388
4389 return(status);
4390}
4391
4392/*
4393* qla2x00_restart_isp
4394* restarts the ISP after a reset
4395*
4396* Input:
4397* ha = adapter block pointer.
4398*
4399* Returns:
4400* 0 = success
4401*/
4402static int
e315cd28 4403qla2x00_restart_isp(scsi_qla_host_t *vha)
1da177e4 4404{
c6b2fca8 4405 int status = 0;
1da177e4 4406 uint32_t wait_time;
e315cd28 4407 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 4408 struct req_que *req = ha->req_q_map[0];
4409 struct rsp_que *rsp = ha->rsp_q_map[0];
2d70c103 4410 unsigned long flags;
1da177e4
LT		 4411
4412 /* If firmware needs to be loaded */
e315cd28
AC		 4413 if (qla2x00_isp_firmware(vha)) {
4414 vha->flags.online = 0;
4415 status = ha->isp_ops->chip_diag(vha);
4416 if (!status)
4417 status = qla2x00_setup_chip(vha);
1da177e4
LT		 4418 }
4419
e315cd28
AC		 4420 if (!status && !(status = qla2x00_init_rings(vha))) {
4421 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
2533cf67 4422 ha->flags.chip_reset_done = 1;
73208dfd
AC		 4423 /* Initialize the queues in use */
4424 qla25xx_init_queues(ha);
4425
e315cd28
AC		 4426 status = qla2x00_fw_ready(vha);
4427 if (!status) {
7c3df132
SK		 4428 ql_dbg(ql_dbg_taskm, vha, 0x8031,
4429 "Start configure loop status = %d.\n", status);
0107109e
AV		 4430
4431 /* Issue a marker after FW becomes ready. */
73208dfd 4432 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
0107109e 4433
e315cd28 4434 vha->flags.online = 1;
2d70c103
NB		 4435
4436 /*
4437 * Process any ATIO queue entries that came in
4438 * while we weren't online.
4439 */
4440 spin_lock_irqsave(&ha->hardware_lock, flags);
4441 if (qla_tgt_mode_enabled(vha))
4442 qlt_24xx_process_atio_queue(vha);
4443 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4444
1da177e4
LT		 4445 /* Wait at most MAX_TARGET RSCNs for a stable link. */
4446 wait_time = 256;
4447 do {
e315cd28
AC		 4448 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
4449 qla2x00_configure_loop(vha);
1da177e4 4450 wait_time--;
e315cd28
AC		 4451 } while (!atomic_read(&vha->loop_down_timer) &&
4452 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
4453 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
4454 &vha->dpc_flags)));
1da177e4
LT		 4455 }
4456
4457 /* if no cable then assume it's good */
e315cd28 4458 if ((vha->device_flags & DFLG_NO_CABLE))
1da177e4
LT		 4459 status = 0;
4460
7c3df132
SK		 4461 ql_dbg(ql_dbg_taskm, vha, 0x8032,
4462 "Configure loop done, status = 0x%x.\n", status);
1da177e4
LT		 4463 }
4464 return (status);
4465}
4466
73208dfd
AC		 4467static int
4468qla25xx_init_queues(struct qla_hw_data *ha)
4469{
4470 struct rsp_que *rsp = NULL;
4471 struct req_que *req = NULL;
4472 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
4473 int ret = -1;
4474 int i;
4475
2afa19a9 4476 for (i = 1; i < ha->max_rsp_queues; i++) {
73208dfd
AC		 4477 rsp = ha->rsp_q_map[i];
4478 if (rsp) {
4479 rsp->options &= ~BIT_0;
618a7523 4480 ret = qla25xx_init_rsp_que(base_vha, rsp);
73208dfd 4481 if (ret != QLA_SUCCESS)
7c3df132
SK		 4482 ql_dbg(ql_dbg_init, base_vha, 0x00ff,
4483 "%s Rsp que: %d init failed.\n",
4484 __func__, rsp->id);
73208dfd 4485 else
7c3df132
SK		 4486 ql_dbg(ql_dbg_init, base_vha, 0x0100,
4487 "%s Rsp que: %d inited.\n",
4488 __func__, rsp->id);
73208dfd 4489 }
2afa19a9
AC		 4490 }
4491 for (i = 1; i < ha->max_req_queues; i++) {
73208dfd
AC		 4492 req = ha->req_q_map[i];
4493 if (req) {
29bdccbe 4494 /* Clear outstanding commands array. */
73208dfd 4495 req->options &= ~BIT_0;
618a7523 4496 ret = qla25xx_init_req_que(base_vha, req);
73208dfd 4497 if (ret != QLA_SUCCESS)
7c3df132
SK		 4498 ql_dbg(ql_dbg_init, base_vha, 0x0101,
4499 "%s Req que: %d init failed.\n",
4500 __func__, req->id);
73208dfd 4501 else
7c3df132
SK		 4502 ql_dbg(ql_dbg_init, base_vha, 0x0102,
4503 "%s Req que: %d inited.\n",
4504 __func__, req->id);
73208dfd
AC		 4505 }
4506 }
4507 return ret;
4508}
4509
1da177e4
LT		 4510/*
4511* qla2x00_reset_adapter
4512* Reset adapter.
4513*
4514* Input:
4515* ha = adapter block pointer.
4516*/
abbd8870 4517void
e315cd28 4518qla2x00_reset_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 4519{
4520 unsigned long flags = 0;
e315cd28 4521 struct qla_hw_data *ha = vha->hw;
3d71644c 4522 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 4523
e315cd28 4524 vha->flags.online = 0;
fd34f556 4525 ha->isp_ops->disable_intrs(ha);
1da177e4 4526
1da177e4
LT		 4527 spin_lock_irqsave(&ha->hardware_lock, flags);
4528 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
4529 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
4530 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
4531 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
4532 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4533}
0107109e
AV		 4534
4535void
e315cd28 4536qla24xx_reset_adapter(scsi_qla_host_t *vha)
0107109e
AV		 4537{
4538 unsigned long flags = 0;
e315cd28 4539 struct qla_hw_data *ha = vha->hw;
0107109e
AV		 4540 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
4541
a9083016
GM		 4542 if (IS_QLA82XX(ha))
4543 return;
4544
e315cd28 4545 vha->flags.online = 0;
fd34f556 4546 ha->isp_ops->disable_intrs(ha);
0107109e
AV		 4547
4548 spin_lock_irqsave(&ha->hardware_lock, flags);
4549 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
4550 RD_REG_DWORD(&reg->hccr);
4551 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
4552 RD_REG_DWORD(&reg->hccr);
4553 spin_unlock_irqrestore(&ha->hardware_lock, flags);
09ff36d3
AV		 4554
4555 if (IS_NOPOLLING_TYPE(ha))
4556 ha->isp_ops->enable_intrs(ha);
0107109e
AV		 4557}
4558
4e08df3f
DM		 4559/* On sparc systems, obtain port and node WWN from firmware
4560 * properties.
4561 */
e315cd28
AC		 4562static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha,
4563 struct nvram_24xx *nv)
4e08df3f
DM		 4564{
4565#ifdef CONFIG_SPARC
e315cd28 4566 struct qla_hw_data *ha = vha->hw;
4e08df3f 4567 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 4568 struct device_node *dp = pci_device_to_OF_node(pdev);
4569 const u8 *val;
4e08df3f
DM		 4570 int len;
4571
4572 val = of_get_property(dp, "port-wwn", &len);
4573 if (val && len >= WWN_SIZE)
4574 memcpy(nv->port_name, val, WWN_SIZE);
4575
4576 val = of_get_property(dp, "node-wwn", &len);
4577 if (val && len >= WWN_SIZE)
4578 memcpy(nv->node_name, val, WWN_SIZE);
4579#endif
4580}
4581
0107109e 4582int
e315cd28 4583qla24xx_nvram_config(scsi_qla_host_t *vha)
0107109e 4584{
4e08df3f 4585 int rval;
0107109e
AV		 4586 struct init_cb_24xx *icb;
4587 struct nvram_24xx *nv;
4588 uint32_t *dptr;
4589 uint8_t *dptr1, *dptr2;
4590 uint32_t chksum;
4591 uint16_t cnt;
e315cd28 4592 struct qla_hw_data *ha = vha->hw;
0107109e 4593
4e08df3f 4594 rval = QLA_SUCCESS;
0107109e 4595 icb = (struct init_cb_24xx *)ha->init_cb;
281afe19 4596 nv = ha->nvram;
0107109e
AV		 4597
4598 /* Determine NVRAM starting address. */
e5b68a61
AC		 4599 if (ha->flags.port0) {
4600 ha->nvram_base = FA_NVRAM_FUNC0_ADDR;
4601 ha->vpd_base = FA_NVRAM_VPD0_ADDR;
4602 } else {
0107109e 4603 ha->nvram_base = FA_NVRAM_FUNC1_ADDR;
6f641790
AV		 4604 ha->vpd_base = FA_NVRAM_VPD1_ADDR;
4605 }
e5b68a61
AC		 4606 ha->nvram_size = sizeof(struct nvram_24xx);
4607 ha->vpd_size = FA_NVRAM_VPD_SIZE;
a9083016
GM		 4608 if (IS_QLA82XX(ha))
4609 ha->vpd_size = FA_VPD_SIZE_82XX;
0107109e 4610
281afe19
SJ		 4611 /* Get VPD data into cache */
4612 ha->vpd = ha->nvram + VPD_OFFSET;
e315cd28 4613 ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd,
281afe19
SJ		 4614 ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
4615
4616 /* Get NVRAM data into cache and calculate checksum. */
0107109e 4617 dptr = (uint32_t *)nv;
e315cd28 4618 ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base,
0107109e
AV		 4619 ha->nvram_size);
4620 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
4621 chksum += le32_to_cpu(*dptr++);
4622
7c3df132
SK		 4623 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
4624 "Contents of NVRAM\n");
4625 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
4626 (uint8_t *)nv, ha->nvram_size);
0107109e
AV		 4627
4628 /* Bad NVRAM data, set defaults parameters. */
4629 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
4630 || nv->id[3] != ' ' ||
4631 nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
4632 /* Reset NVRAM data. */
7c3df132 4633 ql_log(ql_log_warn, vha, 0x006b,
9e336520 4634 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132
SK		 4635 "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version);
4636 ql_log(ql_log_warn, vha, 0x006c,
4637 "Falling back to functioning (yet invalid -- WWPN) "
4638 "defaults.\n");
4e08df3f
DM		 4639
4640 /*
4641 * Set default initialization control block.
4642 */
4643 memset(nv, 0, ha->nvram_size);
4644 nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
4645 nv->version = __constant_cpu_to_le16(ICB_VERSION);
4646 nv->frame_payload_size = __constant_cpu_to_le16(2048);
4647 nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
4648 nv->exchange_count = __constant_cpu_to_le16(0);
4649 nv->hard_address = __constant_cpu_to_le16(124);
4650 nv->port_name[0] = 0x21;
e5b68a61 4651 nv->port_name[1] = 0x00 + ha->port_no;
4e08df3f
DM		 4652 nv->port_name[2] = 0x00;
4653 nv->port_name[3] = 0xe0;
4654 nv->port_name[4] = 0x8b;
4655 nv->port_name[5] = 0x1c;
4656 nv->port_name[6] = 0x55;
4657 nv->port_name[7] = 0x86;
4658 nv->node_name[0] = 0x20;
4659 nv->node_name[1] = 0x00;
4660 nv->node_name[2] = 0x00;
4661 nv->node_name[3] = 0xe0;
4662 nv->node_name[4] = 0x8b;
4663 nv->node_name[5] = 0x1c;
4664 nv->node_name[6] = 0x55;
4665 nv->node_name[7] = 0x86;
e315cd28 4666 qla24xx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 4667 nv->login_retry_count = __constant_cpu_to_le16(8);
4668 nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
4669 nv->login_timeout = __constant_cpu_to_le16(0);
4670 nv->firmware_options_1 =
4671 __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
4672 nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
4673 nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
4674 nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
4675 nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
4676 nv->efi_parameters = __constant_cpu_to_le32(0);
4677 nv->reset_delay = 5;
4678 nv->max_luns_per_target = __constant_cpu_to_le16(128);
4679 nv->port_down_retry_count = __constant_cpu_to_le16(30);
4680 nv->link_down_timeout = __constant_cpu_to_le16(30);
4681
4682 rval = 1;
0107109e
AV		 4683 }
4684
2d70c103
NB		 4685 if (!qla_ini_mode_enabled(vha)) {
4686 /* Don't enable full login after initial LIP */
4687 nv->firmware_options_1 &= __constant_cpu_to_le32(~BIT_13);
4688 /* Don't enable LIP full login for initiator */
4689 nv->host_p &= __constant_cpu_to_le32(~BIT_10);
4690 }
4691
4692 qlt_24xx_config_nvram_stage1(vha, nv);
4693
0107109e 4694 /* Reset Initialization control block */
e315cd28 4695 memset(icb, 0, ha->init_cb_size);
0107109e
AV		 4696
4697 /* Copy 1st segment. */
4698 dptr1 = (uint8_t *)icb;
4699 dptr2 = (uint8_t *)&nv->version;
4700 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
4701 while (cnt--)
4702 *dptr1++ = *dptr2++;
4703
4704 icb->login_retry_count = nv->login_retry_count;
3ea66e28 4705 icb->link_down_on_nos = nv->link_down_on_nos;
0107109e
AV		 4706
4707 /* Copy 2nd segment. */
4708 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
4709 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
4710 cnt = (uint8_t *)&icb->reserved_3 -
4711 (uint8_t *)&icb->interrupt_delay_timer;
4712 while (cnt--)
4713 *dptr1++ = *dptr2++;
4714
4715 /*
4716 * Setup driver NVRAM options.
4717 */
e315cd28 4718 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
9bb9fcf2 4719 "QLA2462");
0107109e 4720
2d70c103
NB		 4721 qlt_24xx_config_nvram_stage2(vha, icb);
4722
5341e868 4723 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
2d70c103 4724 /* Use alternate WWN? */
5341e868
AV		 4725 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
4726 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
4727 }
4728
0107109e 4729 /* Prepare nodename */
fd0e7e4d 4730 if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
0107109e
AV		 4731 /*
4732 * Firmware will apply the following mask if the nodename was
4733 * not provided.
4734 */
4735 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
4736 icb->node_name[0] &= 0xF0;
4737 }
4738
4739 /* Set host adapter parameters. */
4740 ha->flags.disable_risc_code_load = 0;
0c8c39af
AV		 4741 ha->flags.enable_lip_reset = 0;
4742 ha->flags.enable_lip_full_login =
4743 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
4744 ha->flags.enable_target_reset =
4745 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
0107109e 4746 ha->flags.enable_led_scheme = 0;
d4c760c2 4747 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
0107109e 4748
fd0e7e4d
AV		 4749 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
4750 (BIT_6 | BIT_5 | BIT_4)) >> 4;
0107109e
AV		 4751
4752 memcpy(ha->fw_seriallink_options24, nv->seriallink_options,
4753 sizeof(ha->fw_seriallink_options24));
4754
4755 /* save HBA serial number */
4756 ha->serial0 = icb->port_name[5];
4757 ha->serial1 = icb->port_name[6];
4758 ha->serial2 = icb->port_name[7];
e315cd28
AC		 4759 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
4760 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
0107109e 4761
bc8fb3cb
AV		 4762 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
4763
0107109e
AV		 4764 ha->retry_count = le16_to_cpu(nv->login_retry_count);
4765
4766 /* Set minimum login_timeout to 4 seconds. */
4767 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
4768 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
4769 if (le16_to_cpu(nv->login_timeout) < 4)
4770 nv->login_timeout = __constant_cpu_to_le16(4);
4771 ha->login_timeout = le16_to_cpu(nv->login_timeout);
c6852c4c 4772 icb->login_timeout = nv->login_timeout;
0107109e 4773
00a537b8
AV		 4774 /* Set minimum RATOV to 100 tenths of a second. */
4775 ha->r_a_tov = 100;
0107109e
AV		 4776
4777 ha->loop_reset_delay = nv->reset_delay;
4778
4779 /* Link Down Timeout = 0:
4780 *
4781 * When Port Down timer expires we will start returning
4782 * I/O's to OS with "DID_NO_CONNECT".
4783 *
4784 * Link Down Timeout != 0:
4785 *
4786 * The driver waits for the link to come up after link down
4787 * before returning I/Os to OS with "DID_NO_CONNECT".
4788 */
4789 if (le16_to_cpu(nv->link_down_timeout) == 0) {
4790 ha->loop_down_abort_time =
4791 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
4792 } else {
4793 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
4794 ha->loop_down_abort_time =
4795 (LOOP_DOWN_TIME - ha->link_down_timeout);
4796 }
4797
4798 /* Need enough time to try and get the port back. */
4799 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
4800 if (qlport_down_retry)
4801 ha->port_down_retry_count = qlport_down_retry;
4802
4803 /* Set login_retry_count */
4804 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
4805 if (ha->port_down_retry_count ==
4806 le16_to_cpu(nv->port_down_retry_count) &&
4807 ha->port_down_retry_count > 3)
4808 ha->login_retry_count = ha->port_down_retry_count;
4809 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
4810 ha->login_retry_count = ha->port_down_retry_count;
4811 if (ql2xloginretrycount)
4812 ha->login_retry_count = ql2xloginretrycount;
4813
4fdfefe5 4814 /* Enable ZIO. */
e315cd28 4815 if (!vha->flags.init_done) {
4fdfefe5
AV		 4816 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
4817 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
4818 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
4819 le16_to_cpu(icb->interrupt_delay_timer): 2;
4820 }
4821 icb->firmware_options_2 &= __constant_cpu_to_le32(
4822 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
e315cd28 4823 vha->flags.process_response_queue = 0;
4fdfefe5 4824 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d
AV		 4825 ha->zio_mode = QLA_ZIO_MODE_6;
4826
7c3df132 4827 ql_log(ql_log_info, vha, 0x006f,
4fdfefe5
AV		 4828 "ZIO mode %d enabled; timer delay (%d us).\n",
4829 ha->zio_mode, ha->zio_timer * 100);
4830
4831 icb->firmware_options_2 |= cpu_to_le32(
4832 (uint32_t)ha->zio_mode);
4833 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
e315cd28 4834 vha->flags.process_response_queue = 1;
4fdfefe5
AV		 4835 }
4836
4e08df3f 4837 if (rval) {
7c3df132
SK		 4838 ql_log(ql_log_warn, vha, 0x0070,
4839 "NVRAM configuration failed.\n");
4e08df3f
DM		 4840 }
4841 return (rval);
0107109e
AV		 4842}
4843
413975a0 4844static int
cbc8eb67
AV		 4845qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
4846 uint32_t faddr)
d1c61909 4847{
73208dfd 4848 int rval = QLA_SUCCESS;
d1c61909 4849 int segments, fragment;
d1c61909
AV		 4850 uint32_t *dcode, dlen;
4851 uint32_t risc_addr;
4852 uint32_t risc_size;
4853 uint32_t i;
e315cd28 4854 struct qla_hw_data *ha = vha->hw;
73208dfd 4855 struct req_que *req = ha->req_q_map[0];
eaac30be 4856
7c3df132 4857 ql_dbg(ql_dbg_init, vha, 0x008b,
cfb0919c 4858 "FW: Loading firmware from flash (%x).\n", faddr);
eaac30be 4859
d1c61909
AV		 4860 rval = QLA_SUCCESS;
4861
4862 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 4863 dcode = (uint32_t *)req->ring;
d1c61909
AV		 4864 *srisc_addr = 0;
4865
4866 /* Validate firmware image by checking version. */
e315cd28 4867 qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
d1c61909
AV		 4868 for (i = 0; i < 4; i++)
4869 dcode[i] = be32_to_cpu(dcode[i]);
4870 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
4871 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
4872 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
4873 dcode[3] == 0)) {
7c3df132
SK		 4874 ql_log(ql_log_fatal, vha, 0x008c,
4875 "Unable to verify the integrity of flash firmware "
4876 "image.\n");
4877 ql_log(ql_log_fatal, vha, 0x008d,
4878 "Firmware data: %08x %08x %08x %08x.\n",
4879 dcode[0], dcode[1], dcode[2], dcode[3]);
d1c61909
AV		 4880
4881 return QLA_FUNCTION_FAILED;
4882 }
4883
4884 while (segments && rval == QLA_SUCCESS) {
4885 /* Read segment's load information. */
e315cd28 4886 qla24xx_read_flash_data(vha, dcode, faddr, 4);
d1c61909
AV		 4887
4888 risc_addr = be32_to_cpu(dcode[2]);
4889 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
4890 risc_size = be32_to_cpu(dcode[3]);
4891
4892 fragment = 0;
4893 while (risc_size > 0 && rval == QLA_SUCCESS) {
4894 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
4895 if (dlen > risc_size)
4896 dlen = risc_size;
4897
7c3df132
SK		 4898 ql_dbg(ql_dbg_init, vha, 0x008e,
4899 "Loading risc segment@ risc addr %x "
4900 "number of dwords 0x%x offset 0x%x.\n",
4901 risc_addr, dlen, faddr);
d1c61909 4902
e315cd28 4903 qla24xx_read_flash_data(vha, dcode, faddr, dlen);
d1c61909
AV		 4904 for (i = 0; i < dlen; i++)
4905 dcode[i] = swab32(dcode[i]);
4906
73208dfd 4907 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
d1c61909
AV		 4908 dlen);
4909 if (rval) {
7c3df132
SK		 4910 ql_log(ql_log_fatal, vha, 0x008f,
4911 "Failed to load segment %d of firmware.\n",
4912 fragment);
d1c61909
AV		 4913 break;
4914 }
4915
4916 faddr += dlen;
4917 risc_addr += dlen;
4918 risc_size -= dlen;
4919 fragment++;
4920 }
4921
4922 /* Next segment. */
4923 segments--;
4924 }
4925
4926 return rval;
4927}
4928
d1c61909
AV		 4929#define QLA_FW_URL "ftp://ftp.qlogic.com/outgoing/linux/firmware/"
4930
0107109e 4931int
e315cd28 4932qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5433383e
AV		 4933{
4934 int rval;
4935 int i, fragment;
4936 uint16_t *wcode, *fwcode;
4937 uint32_t risc_addr, risc_size, fwclen, wlen, *seg;
4938 struct fw_blob *blob;
e315cd28 4939 struct qla_hw_data *ha = vha->hw;
73208dfd 4940 struct req_que *req = ha->req_q_map[0];
5433383e
AV		 4941
4942 /* Load firmware blob. */
e315cd28 4943 blob = qla2x00_request_firmware(vha);
5433383e 4944 if (!blob) {
7c3df132
SK		 4945 ql_log(ql_log_info, vha, 0x0083,
4946 "Fimware image unavailable.\n");
4947 ql_log(ql_log_info, vha, 0x0084,
4948 "Firmware images can be retrieved from: "QLA_FW_URL ".\n");
5433383e
AV		 4949 return QLA_FUNCTION_FAILED;
4950 }
4951
4952 rval = QLA_SUCCESS;
4953
73208dfd 4954 wcode = (uint16_t *)req->ring;
5433383e
AV		 4955 *srisc_addr = 0;
4956 fwcode = (uint16_t *)blob->fw->data;
4957 fwclen = 0;
4958
4959 /* Validate firmware image by checking version. */
4960 if (blob->fw->size < 8 * sizeof(uint16_t)) {
7c3df132
SK		 4961 ql_log(ql_log_fatal, vha, 0x0085,
4962 "Unable to verify integrity of firmware image (%Zd).\n",
5433383e
AV		 4963 blob->fw->size);
4964 goto fail_fw_integrity;
4965 }
4966 for (i = 0; i < 4; i++)
4967 wcode[i] = be16_to_cpu(fwcode[i + 4]);
4968 if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff &&
4969 wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 &&
4970 wcode[2] == 0 && wcode[3] == 0)) {
7c3df132
SK		 4971 ql_log(ql_log_fatal, vha, 0x0086,
4972 "Unable to verify integrity of firmware image.\n");
4973 ql_log(ql_log_fatal, vha, 0x0087,
4974 "Firmware data: %04x %04x %04x %04x.\n",
4975 wcode[0], wcode[1], wcode[2], wcode[3]);
5433383e
AV		 4976 goto fail_fw_integrity;
4977 }
4978
4979 seg = blob->segs;
4980 while (*seg && rval == QLA_SUCCESS) {
4981 risc_addr = *seg;
4982 *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr;
4983 risc_size = be16_to_cpu(fwcode[3]);
4984
4985 /* Validate firmware image size. */
4986 fwclen += risc_size * sizeof(uint16_t);
4987 if (blob->fw->size < fwclen) {
7c3df132 4988 ql_log(ql_log_fatal, vha, 0x0088,
5433383e 4989 "Unable to verify integrity of firmware image "
7c3df132 4990 "(%Zd).\n", blob->fw->size);
5433383e
AV		 4991 goto fail_fw_integrity;
4992 }
4993
4994 fragment = 0;
4995 while (risc_size > 0 && rval == QLA_SUCCESS) {
4996 wlen = (uint16_t)(ha->fw_transfer_size >> 1);
4997 if (wlen > risc_size)
4998 wlen = risc_size;
7c3df132
SK		 4999 ql_dbg(ql_dbg_init, vha, 0x0089,
5000 "Loading risc segment@ risc addr %x number of "
5001 "words 0x%x.\n", risc_addr, wlen);
5433383e
AV		 5002
5003 for (i = 0; i < wlen; i++)
5004 wcode[i] = swab16(fwcode[i]);
5005
73208dfd 5006 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
5433383e
AV		 5007 wlen);
5008 if (rval) {
7c3df132
SK		 5009 ql_log(ql_log_fatal, vha, 0x008a,
5010 "Failed to load segment %d of firmware.\n",
5011 fragment);
5433383e
AV		 5012 break;
5013 }
5014
5015 fwcode += wlen;
5016 risc_addr += wlen;
5017 risc_size -= wlen;
5018 fragment++;
5019 }
5020
5021 /* Next segment. */
5022 seg++;
5023 }
5024 return rval;
5025
5026fail_fw_integrity:
5027 return QLA_FUNCTION_FAILED;
5028}
5029
eaac30be
AV		 5030static int
5031qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
0107109e
AV		 5032{
5033 int rval;
5034 int segments, fragment;
5035 uint32_t *dcode, dlen;
5036 uint32_t risc_addr;
5037 uint32_t risc_size;
5038 uint32_t i;
5433383e 5039 struct fw_blob *blob;
0107109e 5040 uint32_t *fwcode, fwclen;
e315cd28 5041 struct qla_hw_data *ha = vha->hw;
73208dfd 5042 struct req_que *req = ha->req_q_map[0];
0107109e 5043
5433383e 5044 /* Load firmware blob. */
e315cd28 5045 blob = qla2x00_request_firmware(vha);
5433383e 5046 if (!blob) {
7c3df132
SK		 5047 ql_log(ql_log_warn, vha, 0x0090,
5048 "Fimware image unavailable.\n");
5049 ql_log(ql_log_warn, vha, 0x0091,
5050 "Firmware images can be retrieved from: "
5051 QLA_FW_URL ".\n");
d1c61909 5052
eaac30be 5053 return QLA_FUNCTION_FAILED;
0107109e
AV		 5054 }
5055
cfb0919c
CD		 5056 ql_dbg(ql_dbg_init, vha, 0x0092,
5057 "FW: Loading via request-firmware.\n");
eaac30be 5058
0107109e
AV		 5059 rval = QLA_SUCCESS;
5060
5061 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 5062 dcode = (uint32_t *)req->ring;
0107109e 5063 *srisc_addr = 0;
5433383e 5064 fwcode = (uint32_t *)blob->fw->data;
0107109e
AV		 5065 fwclen = 0;
5066
5067 /* Validate firmware image by checking version. */
5433383e 5068 if (blob->fw->size < 8 * sizeof(uint32_t)) {
7c3df132
SK		 5069 ql_log(ql_log_fatal, vha, 0x0093,
5070 "Unable to verify integrity of firmware image (%Zd).\n",
5433383e 5071 blob->fw->size);
0107109e
AV		 5072 goto fail_fw_integrity;
5073 }
5074 for (i = 0; i < 4; i++)
5075 dcode[i] = be32_to_cpu(fwcode[i + 4]);
5076 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
5077 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
5078 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
5079 dcode[3] == 0)) {
7c3df132
SK		 5080 ql_log(ql_log_fatal, vha, 0x0094,
5081 "Unable to verify integrity of firmware image (%Zd).\n",
5082 blob->fw->size);
5083 ql_log(ql_log_fatal, vha, 0x0095,
5084 "Firmware data: %08x %08x %08x %08x.\n",
5085 dcode[0], dcode[1], dcode[2], dcode[3]);
0107109e
AV		 5086 goto fail_fw_integrity;
5087 }
5088
5089 while (segments && rval == QLA_SUCCESS) {
5090 risc_addr = be32_to_cpu(fwcode[2]);
5091 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
5092 risc_size = be32_to_cpu(fwcode[3]);
5093
5094 /* Validate firmware image size. */
5095 fwclen += risc_size * sizeof(uint32_t);
5433383e 5096 if (blob->fw->size < fwclen) {
7c3df132 5097 ql_log(ql_log_fatal, vha, 0x0096,
5433383e 5098 "Unable to verify integrity of firmware image "
7c3df132 5099 "(%Zd).\n", blob->fw->size);
5433383e 5100
0107109e
AV		 5101 goto fail_fw_integrity;
5102 }
5103
5104 fragment = 0;
5105 while (risc_size > 0 && rval == QLA_SUCCESS) {
5106 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
5107 if (dlen > risc_size)
5108 dlen = risc_size;
5109
7c3df132
SK		 5110 ql_dbg(ql_dbg_init, vha, 0x0097,
5111 "Loading risc segment@ risc addr %x "
5112 "number of dwords 0x%x.\n", risc_addr, dlen);
0107109e
AV		 5113
5114 for (i = 0; i < dlen; i++)
5115 dcode[i] = swab32(fwcode[i]);
5116
73208dfd 5117 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
590f98e5 5118 dlen);
0107109e 5119 if (rval) {
7c3df132
SK		 5120 ql_log(ql_log_fatal, vha, 0x0098,
5121 "Failed to load segment %d of firmware.\n",
5122 fragment);
0107109e
AV		 5123 break;
5124 }
5125
5126 fwcode += dlen;
5127 risc_addr += dlen;
5128 risc_size -= dlen;
5129 fragment++;
5130 }
5131
5132 /* Next segment. */
5133 segments--;
5134 }
0107109e
AV		 5135 return rval;
5136
5137fail_fw_integrity:
0107109e 5138 return QLA_FUNCTION_FAILED;
0107109e 5139}
18c6c127 5140
eaac30be
AV		 5141int
5142qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5143{
5144 int rval;
5145
e337d907
AV		 5146 if (ql2xfwloadbin == 1)
5147 return qla81xx_load_risc(vha, srisc_addr);
5148
eaac30be
AV		 5149 /*
5150 * FW Load priority:
5151 * 1) Firmware via request-firmware interface (.bin file).
5152 * 2) Firmware residing in flash.
5153 */
5154 rval = qla24xx_load_risc_blob(vha, srisc_addr);
5155 if (rval == QLA_SUCCESS)
5156 return rval;
5157
cbc8eb67
AV		 5158 return qla24xx_load_risc_flash(vha, srisc_addr,
5159 vha->hw->flt_region_fw);
eaac30be
AV		 5160}
5161
5162int
5163qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5164{
5165 int rval;
cbc8eb67 5166 struct qla_hw_data *ha = vha->hw;
eaac30be 5167
e337d907 5168 if (ql2xfwloadbin == 2)
cbc8eb67 5169 goto try_blob_fw;
e337d907 5170
eaac30be
AV		 5171 /*
5172 * FW Load priority:
5173 * 1) Firmware residing in flash.
5174 * 2) Firmware via request-firmware interface (.bin file).
cbc8eb67 5175 * 3) Golden-Firmware residing in flash -- limited operation.
eaac30be 5176 */
cbc8eb67 5177 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
eaac30be
AV		 5178 if (rval == QLA_SUCCESS)
5179 return rval;
5180
cbc8eb67
AV		 5181try_blob_fw:
5182 rval = qla24xx_load_risc_blob(vha, srisc_addr);
5183 if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw)
5184 return rval;
5185
7c3df132
SK		 5186 ql_log(ql_log_info, vha, 0x0099,
5187 "Attempting to fallback to golden firmware.\n");
cbc8eb67
AV		 5188 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
5189 if (rval != QLA_SUCCESS)
5190 return rval;
5191
7c3df132 5192 ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n");
cbc8eb67 5193 ha->flags.running_gold_fw = 1;
cbc8eb67 5194 return rval;
eaac30be
AV		 5195}
5196
18c6c127 5197void
e315cd28 5198qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha)
18c6c127
AV		 5199{
5200 int ret, retries;
e315cd28 5201 struct qla_hw_data *ha = vha->hw;
18c6c127 5202
85880801
AV		 5203 if (ha->flags.pci_channel_io_perm_failure)
5204 return;
e428924c 5205 if (!IS_FWI2_CAPABLE(ha))
18c6c127 5206 return;
75edf81d
AV		 5207 if (!ha->fw_major_version)
5208 return;
18c6c127 5209
e315cd28 5210 ret = qla2x00_stop_firmware(vha);
7c7f1f29 5211 for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&
b469a7cb 5212 ret != QLA_INVALID_COMMAND && retries ; retries--) {
e315cd28
AC		 5213 ha->isp_ops->reset_chip(vha);
5214 if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS)
18c6c127 5215 continue;
e315cd28 5216 if (qla2x00_setup_chip(vha) != QLA_SUCCESS)
18c6c127 5217 continue;
7c3df132
SK		 5218 ql_log(ql_log_info, vha, 0x8015,
5219 "Attempting retry of stop-firmware command.\n");
e315cd28 5220 ret = qla2x00_stop_firmware(vha);
18c6c127
AV		 5221 }
5222}
2c3dfe3f
SJ		 5223
5224int
e315cd28 5225qla24xx_configure_vhba(scsi_qla_host_t *vha)
2c3dfe3f
SJ		 5226{
5227 int rval = QLA_SUCCESS;
0b91d116 5228 int rval2;
2c3dfe3f 5229 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28
AC		 5230 struct qla_hw_data *ha = vha->hw;
5231 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
67c2e93a
AC		 5232 struct req_que *req;
5233 struct rsp_que *rsp;
2c3dfe3f 5234
e315cd28 5235 if (!vha->vp_idx)
2c3dfe3f
SJ		 5236 return -EINVAL;
5237
e315cd28 5238 rval = qla2x00_fw_ready(base_vha);
7163ea81 5239 if (ha->flags.cpu_affinity_enabled)
67c2e93a
AC		 5240 req = ha->req_q_map[0];
5241 else
5242 req = vha->req;
5243 rsp = req->rsp;
5244
2c3dfe3f 5245 if (rval == QLA_SUCCESS) {
e315cd28 5246 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
73208dfd 5247 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
2c3dfe3f
SJ		 5248 }
5249
e315cd28 5250 vha->flags.management_server_logged_in = 0;
2c3dfe3f
SJ		 5251
5252 /* Login to SNS first */
0b91d116
CD		 5253 rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb,
5254 BIT_1);
5255 if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
5256 if (rval2 == QLA_MEMORY_ALLOC_FAILED)
5257 ql_dbg(ql_dbg_init, vha, 0x0120,
5258 "Failed SNS login: loop_id=%x, rval2=%d\n",
5259 NPH_SNS, rval2);
5260 else
5261 ql_dbg(ql_dbg_init, vha, 0x0103,
5262 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x "
5263 "mb[2]=%x mb[6]=%x mb[7]=%x.\n",
5264 NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]);
2c3dfe3f
SJ		 5265 return (QLA_FUNCTION_FAILED);
5266 }
5267
e315cd28
AC		 5268 atomic_set(&vha->loop_down_timer, 0);
5269 atomic_set(&vha->loop_state, LOOP_UP);
5270 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5271 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
5272 rval = qla2x00_loop_resync(base_vha);
2c3dfe3f
SJ		 5273
5274 return rval;
5275}
4d4df193
HK		 5276
5277/* 84XX Support **************************************************************/
5278
5279static LIST_HEAD(qla_cs84xx_list);
5280static DEFINE_MUTEX(qla_cs84xx_mutex);
5281
5282static struct qla_chip_state_84xx *
e315cd28 5283qla84xx_get_chip(struct scsi_qla_host *vha)
4d4df193
HK		 5284{
5285 struct qla_chip_state_84xx *cs84xx;
e315cd28 5286 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5287
5288 mutex_lock(&qla_cs84xx_mutex);
5289
5290 /* Find any shared 84xx chip. */
5291 list_for_each_entry(cs84xx, &qla_cs84xx_list, list) {
5292 if (cs84xx->bus == ha->pdev->bus) {
5293 kref_get(&cs84xx->kref);
5294 goto done;
5295 }
5296 }
5297
5298 cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL);
5299 if (!cs84xx)
5300 goto done;
5301
5302 kref_init(&cs84xx->kref);
5303 spin_lock_init(&cs84xx->access_lock);
5304 mutex_init(&cs84xx->fw_update_mutex);
5305 cs84xx->bus = ha->pdev->bus;
5306
5307 list_add_tail(&cs84xx->list, &qla_cs84xx_list);
5308done:
5309 mutex_unlock(&qla_cs84xx_mutex);
5310 return cs84xx;
5311}
5312
5313static void
5314__qla84xx_chip_release(struct kref *kref)
5315{
5316 struct qla_chip_state_84xx *cs84xx =
5317 container_of(kref, struct qla_chip_state_84xx, kref);
5318
5319 mutex_lock(&qla_cs84xx_mutex);
5320 list_del(&cs84xx->list);
5321 mutex_unlock(&qla_cs84xx_mutex);
5322 kfree(cs84xx);
5323}
5324
5325void
e315cd28 5326qla84xx_put_chip(struct scsi_qla_host *vha)
4d4df193 5327{
e315cd28 5328 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5329 if (ha->cs84xx)
5330 kref_put(&ha->cs84xx->kref, __qla84xx_chip_release);
5331}
5332
5333static int
e315cd28 5334qla84xx_init_chip(scsi_qla_host_t *vha)
4d4df193
HK		 5335{
5336 int rval;
5337 uint16_t status[2];
e315cd28 5338 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5339
5340 mutex_lock(&ha->cs84xx->fw_update_mutex);
5341
e315cd28 5342 rval = qla84xx_verify_chip(vha, status);
4d4df193
HK		 5343
5344 mutex_unlock(&ha->cs84xx->fw_update_mutex);
5345
5346 return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED:
5347 QLA_SUCCESS;
5348}
3a03eb79
AV		 5349
5350/* 81XX Support **************************************************************/
5351
5352int
5353qla81xx_nvram_config(scsi_qla_host_t *vha)
5354{
5355 int rval;
5356 struct init_cb_81xx *icb;
5357 struct nvram_81xx *nv;
5358 uint32_t *dptr;
5359 uint8_t *dptr1, *dptr2;
5360 uint32_t chksum;
5361 uint16_t cnt;
5362 struct qla_hw_data *ha = vha->hw;
5363
5364 rval = QLA_SUCCESS;
5365 icb = (struct init_cb_81xx *)ha->init_cb;
5366 nv = ha->nvram;
5367
5368 /* Determine NVRAM starting address. */
5369 ha->nvram_size = sizeof(struct nvram_81xx);
3a03eb79 5370 ha->vpd_size = FA_NVRAM_VPD_SIZE;
3a03eb79
AV		 5371
5372 /* Get VPD data into cache */
5373 ha->vpd = ha->nvram + VPD_OFFSET;
3d79038f
AV		 5374 ha->isp_ops->read_optrom(vha, ha->vpd, ha->flt_region_vpd << 2,
5375 ha->vpd_size);
3a03eb79
AV		 5376
5377 /* Get NVRAM data into cache and calculate checksum. */
3d79038f 5378 ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2,
3a03eb79 5379 ha->nvram_size);
3d79038f 5380 dptr = (uint32_t *)nv;
3a03eb79
AV		 5381 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
5382 chksum += le32_to_cpu(*dptr++);
5383
7c3df132
SK		 5384 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
5385 "Contents of NVRAM:\n");
5386 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
5387 (uint8_t *)nv, ha->nvram_size);
3a03eb79
AV		 5388
5389 /* Bad NVRAM data, set defaults parameters. */
5390 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
5391 || nv->id[3] != ' ' ||
5392 nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
5393 /* Reset NVRAM data. */
7c3df132 5394 ql_log(ql_log_info, vha, 0x0073,
9e336520 5395 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132 5396 "version=0x%x.\n", chksum, nv->id[0],
3a03eb79 5397 le16_to_cpu(nv->nvram_version));
7c3df132
SK		 5398 ql_log(ql_log_info, vha, 0x0074,
5399 "Falling back to functioning (yet invalid -- WWPN) "
5400 "defaults.\n");
3a03eb79
AV		 5401
5402 /*
5403 * Set default initialization control block.
5404 */
5405 memset(nv, 0, ha->nvram_size);
5406 nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
5407 nv->version = __constant_cpu_to_le16(ICB_VERSION);
5408 nv->frame_payload_size = __constant_cpu_to_le16(2048);
5409 nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
5410 nv->exchange_count = __constant_cpu_to_le16(0);
5411 nv->port_name[0] = 0x21;
e5b68a61 5412 nv->port_name[1] = 0x00 + ha->port_no;
3a03eb79
AV		 5413 nv->port_name[2] = 0x00;
5414 nv->port_name[3] = 0xe0;
5415 nv->port_name[4] = 0x8b;
5416 nv->port_name[5] = 0x1c;
5417 nv->port_name[6] = 0x55;
5418 nv->port_name[7] = 0x86;
5419 nv->node_name[0] = 0x20;
5420 nv->node_name[1] = 0x00;
5421 nv->node_name[2] = 0x00;
5422 nv->node_name[3] = 0xe0;
5423 nv->node_name[4] = 0x8b;
5424 nv->node_name[5] = 0x1c;
5425 nv->node_name[6] = 0x55;
5426 nv->node_name[7] = 0x86;
5427 nv->login_retry_count = __constant_cpu_to_le16(8);
5428 nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
5429 nv->login_timeout = __constant_cpu_to_le16(0);
5430 nv->firmware_options_1 =
5431 __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
5432 nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
5433 nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
5434 nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
5435 nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
5436 nv->efi_parameters = __constant_cpu_to_le32(0);
5437 nv->reset_delay = 5;
5438 nv->max_luns_per_target = __constant_cpu_to_le16(128);
5439 nv->port_down_retry_count = __constant_cpu_to_le16(30);
6246b8a1 5440 nv->link_down_timeout = __constant_cpu_to_le16(180);
eeebcc92 5441 nv->enode_mac[0] = 0x00;
6246b8a1
GM		 5442 nv->enode_mac[1] = 0xC0;
5443 nv->enode_mac[2] = 0xDD;
3a03eb79
AV		 5444 nv->enode_mac[3] = 0x04;
5445 nv->enode_mac[4] = 0x05;
e5b68a61 5446 nv->enode_mac[5] = 0x06 + ha->port_no;
3a03eb79
AV		 5447
5448 rval = 1;
5449 }
5450
9e522cd8
AE		 5451 if (IS_T10_PI_CAPABLE(ha))
5452 nv->frame_payload_size &= ~7;
5453
3a03eb79 5454 /* Reset Initialization control block */
773120e4 5455 memset(icb, 0, ha->init_cb_size);
3a03eb79
AV		 5456
5457 /* Copy 1st segment. */
5458 dptr1 = (uint8_t *)icb;
5459 dptr2 = (uint8_t *)&nv->version;
5460 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
5461 while (cnt--)
5462 *dptr1++ = *dptr2++;
5463
5464 icb->login_retry_count = nv->login_retry_count;
5465
5466 /* Copy 2nd segment. */
5467 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
5468 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
5469 cnt = (uint8_t *)&icb->reserved_5 -
5470 (uint8_t *)&icb->interrupt_delay_timer;
5471 while (cnt--)
5472 *dptr1++ = *dptr2++;
5473
5474 memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac));
5475 /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */
5476 if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) {
69e5f1ea
AV		 5477 icb->enode_mac[0] = 0x00;
5478 icb->enode_mac[1] = 0xC0;
5479 icb->enode_mac[2] = 0xDD;
3a03eb79
AV		 5480 icb->enode_mac[3] = 0x04;
5481 icb->enode_mac[4] = 0x05;
e5b68a61 5482 icb->enode_mac[5] = 0x06 + ha->port_no;
3a03eb79
AV		 5483 }
5484
b64b0e8f
AV		 5485 /* Use extended-initialization control block. */
5486 memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb));
5487
3a03eb79
AV		 5488 /*
5489 * Setup driver NVRAM options.
5490 */
5491 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
a9083016 5492 "QLE8XXX");
3a03eb79
AV		 5493
5494 /* Use alternate WWN? */
5495 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
5496 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
5497 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
5498 }
5499
5500 /* Prepare nodename */
5501 if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
5502 /*
5503 * Firmware will apply the following mask if the nodename was
5504 * not provided.
5505 */
5506 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
5507 icb->node_name[0] &= 0xF0;
5508 }
5509
5510 /* Set host adapter parameters. */
5511 ha->flags.disable_risc_code_load = 0;
5512 ha->flags.enable_lip_reset = 0;
5513 ha->flags.enable_lip_full_login =
5514 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
5515 ha->flags.enable_target_reset =
5516 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
5517 ha->flags.enable_led_scheme = 0;
5518 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
5519
5520 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
5521 (BIT_6 | BIT_5 | BIT_4)) >> 4;
5522
5523 /* save HBA serial number */
5524 ha->serial0 = icb->port_name[5];
5525 ha->serial1 = icb->port_name[6];
5526 ha->serial2 = icb->port_name[7];
5527 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
5528 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
5529
5530 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
5531
5532 ha->retry_count = le16_to_cpu(nv->login_retry_count);
5533
5534 /* Set minimum login_timeout to 4 seconds. */
5535 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
5536 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
5537 if (le16_to_cpu(nv->login_timeout) < 4)
5538 nv->login_timeout = __constant_cpu_to_le16(4);
5539 ha->login_timeout = le16_to_cpu(nv->login_timeout);
5540 icb->login_timeout = nv->login_timeout;
5541
5542 /* Set minimum RATOV to 100 tenths of a second. */
5543 ha->r_a_tov = 100;
5544
5545 ha->loop_reset_delay = nv->reset_delay;
5546
5547 /* Link Down Timeout = 0:
5548 *
5549 * When Port Down timer expires we will start returning
5550 * I/O's to OS with "DID_NO_CONNECT".
5551 *
5552 * Link Down Timeout != 0:
5553 *
5554 * The driver waits for the link to come up after link down
5555 * before returning I/Os to OS with "DID_NO_CONNECT".
5556 */
5557 if (le16_to_cpu(nv->link_down_timeout) == 0) {
5558 ha->loop_down_abort_time =
5559 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
5560 } else {
5561 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
5562 ha->loop_down_abort_time =
5563 (LOOP_DOWN_TIME - ha->link_down_timeout);
5564 }
5565
5566 /* Need enough time to try and get the port back. */
5567 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
5568 if (qlport_down_retry)
5569 ha->port_down_retry_count = qlport_down_retry;
5570
5571 /* Set login_retry_count */
5572 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
5573 if (ha->port_down_retry_count ==
5574 le16_to_cpu(nv->port_down_retry_count) &&
5575 ha->port_down_retry_count > 3)
5576 ha->login_retry_count = ha->port_down_retry_count;
5577 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
5578 ha->login_retry_count = ha->port_down_retry_count;
5579 if (ql2xloginretrycount)
5580 ha->login_retry_count = ql2xloginretrycount;
5581
6246b8a1
GM		 5582 /* if not running MSI-X we need handshaking on interrupts */
5583 if (!vha->hw->flags.msix_enabled && IS_QLA83XX(ha))
5584 icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_22);
5585
3a03eb79
AV		 5586 /* Enable ZIO. */
5587 if (!vha->flags.init_done) {
5588 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
5589 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
5590 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
5591 le16_to_cpu(icb->interrupt_delay_timer): 2;
5592 }
5593 icb->firmware_options_2 &= __constant_cpu_to_le32(
5594 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
5595 vha->flags.process_response_queue = 0;
5596 if (ha->zio_mode != QLA_ZIO_DISABLED) {
5597 ha->zio_mode = QLA_ZIO_MODE_6;
5598
7c3df132 5599 ql_log(ql_log_info, vha, 0x0075,
3a03eb79 5600 "ZIO mode %d enabled; timer delay (%d us).\n",
7c3df132
SK		 5601 ha->zio_mode,
5602 ha->zio_timer * 100);
3a03eb79
AV		 5603
5604 icb->firmware_options_2 |= cpu_to_le32(
5605 (uint32_t)ha->zio_mode);
5606 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
5607 vha->flags.process_response_queue = 1;
5608 }
5609
5610 if (rval) {
7c3df132
SK		 5611 ql_log(ql_log_warn, vha, 0x0076,
5612 "NVRAM configuration failed.\n");
3a03eb79
AV		 5613 }
5614 return (rval);
5615}
5616
a9083016
GM		 5617int
5618qla82xx_restart_isp(scsi_qla_host_t *vha)
5619{
5620 int status, rval;
5621 uint32_t wait_time;
5622 struct qla_hw_data *ha = vha->hw;
5623 struct req_que *req = ha->req_q_map[0];
5624 struct rsp_que *rsp = ha->rsp_q_map[0];
5625 struct scsi_qla_host *vp;
feafb7b1 5626 unsigned long flags;
a9083016
GM		 5627
5628 status = qla2x00_init_rings(vha);
5629 if (!status) {
5630 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
5631 ha->flags.chip_reset_done = 1;
5632
5633 status = qla2x00_fw_ready(vha);
5634 if (!status) {
7c3df132
SK		 5635 ql_log(ql_log_info, vha, 0x803c,
5636 "Start configure loop, status =%d.\n", status);
a9083016
GM		 5637
5638 /* Issue a marker after FW becomes ready. */
5639 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
5640
5641 vha->flags.online = 1;
5642 /* Wait at most MAX_TARGET RSCNs for a stable link. */
5643 wait_time = 256;
5644 do {
5645 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5646 qla2x00_configure_loop(vha);
5647 wait_time--;
5648 } while (!atomic_read(&vha->loop_down_timer) &&
5649 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) &&
5650 wait_time &&
5651 (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)));
5652 }
5653
5654 /* if no cable then assume it's good */
5655 if ((vha->device_flags & DFLG_NO_CABLE))
5656 status = 0;
5657
cfb0919c 5658 ql_log(ql_log_info, vha, 0x8000,
7c3df132 5659 "Configure loop done, status = 0x%x.\n", status);
a9083016
GM		 5660 }
5661
5662 if (!status) {
5663 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
5664
5665 if (!atomic_read(&vha->loop_down_timer)) {
5666 /*
5667 * Issue marker command only when we are going
5668 * to start the I/O .
5669 */
5670 vha->marker_needed = 1;
5671 }
5672
5673 vha->flags.online = 1;
5674
5675 ha->isp_ops->enable_intrs(ha);
5676
5677 ha->isp_abort_cnt = 0;
5678 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
5679
53296788 5680 /* Update the firmware version */
3173167f 5681 status = qla82xx_check_md_needed(vha);
53296788 5682
a9083016
GM		 5683 if (ha->fce) {
5684 ha->flags.fce_enabled = 1;
5685 memset(ha->fce, 0,
5686 fce_calc_size(ha->fce_bufs));
5687 rval = qla2x00_enable_fce_trace(vha,
5688 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
5689 &ha->fce_bufs);
5690 if (rval) {
cfb0919c 5691 ql_log(ql_log_warn, vha, 0x8001,
7c3df132
SK		 5692 "Unable to reinitialize FCE (%d).\n",
5693 rval);
a9083016
GM		 5694 ha->flags.fce_enabled = 0;
5695 }
5696 }
5697
5698 if (ha->eft) {
5699 memset(ha->eft, 0, EFT_SIZE);
5700 rval = qla2x00_enable_eft_trace(vha,
5701 ha->eft_dma, EFT_NUM_BUFFERS);
5702 if (rval) {
cfb0919c 5703 ql_log(ql_log_warn, vha, 0x8010,
7c3df132
SK		 5704 "Unable to reinitialize EFT (%d).\n",
5705 rval);
a9083016
GM		 5706 }
5707 }
a9083016
GM		 5708 }
5709
5710 if (!status) {
cfb0919c 5711 ql_dbg(ql_dbg_taskm, vha, 0x8011,
7c3df132 5712 "qla82xx_restart_isp succeeded.\n");
feafb7b1
AE		 5713
5714 spin_lock_irqsave(&ha->vport_slock, flags);
5715 list_for_each_entry(vp, &ha->vp_list, list) {
5716 if (vp->vp_idx) {
5717 atomic_inc(&vp->vref_count);
5718 spin_unlock_irqrestore(&ha->vport_slock, flags);
5719
a9083016 5720 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 5721
5722 spin_lock_irqsave(&ha->vport_slock, flags);
5723 atomic_dec(&vp->vref_count);
5724 }
a9083016 5725 }
feafb7b1
AE		 5726 spin_unlock_irqrestore(&ha->vport_slock, flags);
5727
a9083016 5728 } else {
cfb0919c 5729 ql_log(ql_log_warn, vha, 0x8016,
7c3df132 5730 "qla82xx_restart_isp **** FAILED ****.\n");
a9083016
GM		 5731 }
5732
5733 return status;
5734}
5735
3a03eb79 5736void
ae97c91e 5737qla81xx_update_fw_options(scsi_qla_host_t *vha)
3a03eb79 5738{
ae97c91e
AV		 5739 struct qla_hw_data *ha = vha->hw;
5740
5741 if (!ql2xetsenable)
5742 return;
5743
5744 /* Enable ETS Burst. */
5745 memset(ha->fw_options, 0, sizeof(ha->fw_options));
5746 ha->fw_options[2] |= BIT_9;
5747 qla2x00_set_fw_options(vha, ha->fw_options);
3a03eb79 5748}
09ff701a
SR		 5749
5750/*
5751 * qla24xx_get_fcp_prio
5752 * Gets the fcp cmd priority value for the logged in port.
5753 * Looks for a match of the port descriptors within
5754 * each of the fcp prio config entries. If a match is found,
5755 * the tag (priority) value is returned.
5756 *
5757 * Input:
21090cbe 5758 * vha = scsi host structure pointer.
09ff701a
SR		 5759 * fcport = port structure pointer.
5760 *
5761 * Return:
6c452a45 5762 * non-zero (if found)
f28a0a96 5763 * -1 (if not found)
09ff701a
SR		 5764 *
5765 * Context:
5766 * Kernel context
5767 */
f28a0a96 5768static int
09ff701a
SR		 5769qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
5770{
5771 int i, entries;
5772 uint8_t pid_match, wwn_match;
f28a0a96 5773 int priority;
09ff701a
SR		 5774 uint32_t pid1, pid2;
5775 uint64_t wwn1, wwn2;
5776 struct qla_fcp_prio_entry *pri_entry;
5777 struct qla_hw_data *ha = vha->hw;
5778
5779 if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled)
f28a0a96 5780 return -1;
09ff701a 5781
f28a0a96 5782 priority = -1;
09ff701a
SR		 5783 entries = ha->fcp_prio_cfg->num_entries;
5784 pri_entry = &ha->fcp_prio_cfg->entry[0];
5785
5786 for (i = 0; i < entries; i++) {
5787 pid_match = wwn_match = 0;
5788
5789 if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) {
5790 pri_entry++;
5791 continue;
5792 }
5793
5794 /* check source pid for a match */
5795 if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) {
5796 pid1 = pri_entry->src_pid & INVALID_PORT_ID;
5797 pid2 = vha->d_id.b24 & INVALID_PORT_ID;
5798 if (pid1 == INVALID_PORT_ID)
5799 pid_match++;
5800 else if (pid1 == pid2)
5801 pid_match++;
5802 }
5803
5804 /* check destination pid for a match */
5805 if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) {
5806 pid1 = pri_entry->dst_pid & INVALID_PORT_ID;
5807 pid2 = fcport->d_id.b24 & INVALID_PORT_ID;
5808 if (pid1 == INVALID_PORT_ID)
5809 pid_match++;
5810 else if (pid1 == pid2)
5811 pid_match++;
5812 }
5813
5814 /* check source WWN for a match */
5815 if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) {
5816 wwn1 = wwn_to_u64(vha->port_name);
5817 wwn2 = wwn_to_u64(pri_entry->src_wwpn);
5818 if (wwn2 == (uint64_t)-1)
5819 wwn_match++;
5820 else if (wwn1 == wwn2)
5821 wwn_match++;
5822 }
5823
5824 /* check destination WWN for a match */
5825 if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) {
5826 wwn1 = wwn_to_u64(fcport->port_name);
5827 wwn2 = wwn_to_u64(pri_entry->dst_wwpn);
5828 if (wwn2 == (uint64_t)-1)
5829 wwn_match++;
5830 else if (wwn1 == wwn2)
5831 wwn_match++;
5832 }
5833
5834 if (pid_match == 2 || wwn_match == 2) {
5835 /* Found a matching entry */
5836 if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID)
5837 priority = pri_entry->tag;
5838 break;
5839 }
5840
5841 pri_entry++;
5842 }
5843
5844 return priority;
5845}
5846
5847/*
5848 * qla24xx_update_fcport_fcp_prio
5849 * Activates fcp priority for the logged in fc port
5850 *
5851 * Input:
21090cbe 5852 * vha = scsi host structure pointer.
09ff701a
SR		 5853 * fcp = port structure pointer.
5854 *
5855 * Return:
5856 * QLA_SUCCESS or QLA_FUNCTION_FAILED
5857 *
5858 * Context:
5859 * Kernel context.
5860 */
5861int
21090cbe 5862qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
09ff701a
SR		 5863{
5864 int ret;
f28a0a96 5865 int priority;
09ff701a
SR		 5866 uint16_t mb[5];
5867
21090cbe
MI		 5868 if (fcport->port_type != FCT_TARGET ||
5869 fcport->loop_id == FC_NO_LOOP_ID)
09ff701a
SR		 5870 return QLA_FUNCTION_FAILED;
5871
21090cbe 5872 priority = qla24xx_get_fcp_prio(vha, fcport);
f28a0a96
AV		 5873 if (priority < 0)
5874 return QLA_FUNCTION_FAILED;
5875
a00f6296
SK		 5876 if (IS_QLA82XX(vha->hw)) {
5877 fcport->fcp_prio = priority & 0xf;
5878 return QLA_SUCCESS;
5879 }
5880
21090cbe 5881 ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb);
cfb0919c
CD		 5882 if (ret == QLA_SUCCESS) {
5883 if (fcport->fcp_prio != priority)
5884 ql_dbg(ql_dbg_user, vha, 0x709e,
5885 "Updated FCP_CMND priority - value=%d loop_id=%d "
5886 "port_id=%02x%02x%02x.\n", priority,
5887 fcport->loop_id, fcport->d_id.b.domain,
5888 fcport->d_id.b.area, fcport->d_id.b.al_pa);
a00f6296 5889 fcport->fcp_prio = priority & 0xf;
cfb0919c 5890 } else
7c3df132 5891 ql_dbg(ql_dbg_user, vha, 0x704f,
cfb0919c
CD		 5892 "Unable to update FCP_CMND priority - ret=0x%x for "
5893 "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id,
5894 fcport->d_id.b.domain, fcport->d_id.b.area,
5895 fcport->d_id.b.al_pa);
09ff701a
SR		 5896 return ret;
5897}
5898
5899/*
5900 * qla24xx_update_all_fcp_prio
5901 * Activates fcp priority for all the logged in ports
5902 *
5903 * Input:
5904 * ha = adapter block pointer.
5905 *
5906 * Return:
5907 * QLA_SUCCESS or QLA_FUNCTION_FAILED
5908 *
5909 * Context:
5910 * Kernel context.
5911 */
5912int
5913qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha)
5914{
5915 int ret;
5916 fc_port_t *fcport;
5917
5918 ret = QLA_FUNCTION_FAILED;
5919 /* We need to set priority for all logged in ports */
5920 list_for_each_entry(fcport, &vha->vp_fcports, list)
5921 ret = qla24xx_update_fcport_fcp_prio(vha, fcport);
5922
5923 return ret;
5924}
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