]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/scsi/qla2xxx/qla_init.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[SCSI] qla2xxx: Remove QL_DEBUG_LEVEL_17 defines from qla_nx.c.
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / qla2xxx / qla_init.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
1e63395c 3 * Copyright (c) 2003-2013 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
73208dfd 8#include "qla_gbl.h"
1da177e4
LT		 9
10#include <linux/delay.h>
5a0e3ad6 11#include <linux/slab.h>
0107109e 12#include <linux/vmalloc.h>
1da177e4
LT		 13
14#include "qla_devtbl.h"
15
4e08df3f
DM		 16#ifdef CONFIG_SPARC
17#include <asm/prom.h>
4e08df3f
DM		 18#endif
19
2d70c103
NB		 20#include <target/target_core_base.h>
21#include "qla_target.h"
22
1da177e4
LT		 23/*
24* QLogic ISP2x00 Hardware Support Function Prototypes.
25*/
1da177e4 26static int qla2x00_isp_firmware(scsi_qla_host_t *);
1da177e4 27static int qla2x00_setup_chip(scsi_qla_host_t *);
1da177e4
LT		 28static int qla2x00_fw_ready(scsi_qla_host_t *);
29static int qla2x00_configure_hba(scsi_qla_host_t *);
1da177e4
LT		 30static int qla2x00_configure_loop(scsi_qla_host_t *);
31static int qla2x00_configure_local_loop(scsi_qla_host_t *);
1da177e4
LT		 32static int qla2x00_configure_fabric(scsi_qla_host_t *);
33static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *, struct list_head *);
1da177e4
LT		 34static int qla2x00_fabric_dev_login(scsi_qla_host_t *, fc_port_t *,
35 uint16_t *);
1da177e4
LT		 36
37static int qla2x00_restart_isp(scsi_qla_host_t *);
1da177e4 38
4d4df193
HK		 39static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *);
40static int qla84xx_init_chip(scsi_qla_host_t *);
73208dfd 41static int qla25xx_init_queues(struct qla_hw_data *);
4d4df193 42
ac280b67
AV		 43/* SRB Extensions ---------------------------------------------------------- */
44
9ba56b95
GM		 45void
46qla2x00_sp_timeout(unsigned long __data)
ac280b67
AV		 47{
48 srb_t *sp = (srb_t *)__data;
4916392b 49 struct srb_iocb *iocb;
ac280b67
AV		 50 fc_port_t *fcport = sp->fcport;
51 struct qla_hw_data *ha = fcport->vha->hw;
52 struct req_que *req;
53 unsigned long flags;
54
55 spin_lock_irqsave(&ha->hardware_lock, flags);
56 req = ha->req_q_map[0];
57 req->outstanding_cmds[sp->handle] = NULL;
9ba56b95 58 iocb = &sp->u.iocb_cmd;
4916392b 59 iocb->timeout(sp);
9ba56b95 60 sp->free(fcport->vha, sp);
6ac52608 61 spin_unlock_irqrestore(&ha->hardware_lock, flags);
ac280b67
AV		 62}
63
9ba56b95
GM		 64void
65qla2x00_sp_free(void *data, void *ptr)
ac280b67 66{
9ba56b95
GM		 67 srb_t *sp = (srb_t *)ptr;
68 struct srb_iocb *iocb = &sp->u.iocb_cmd;
69 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
ac280b67 70
4d97cc53 71 del_timer(&iocb->timer);
b00ee7d7 72 qla2x00_rel_sp(vha, sp);
ac280b67
AV		 73}
74
ac280b67
AV		 75/* Asynchronous Login/Logout Routines -------------------------------------- */
76
a9b6f722 77unsigned long
5b91490e
AV		 78qla2x00_get_async_timeout(struct scsi_qla_host *vha)
79{
80 unsigned long tmo;
81 struct qla_hw_data *ha = vha->hw;
82
83 /* Firmware should use switch negotiated r_a_tov for timeout. */
84 tmo = ha->r_a_tov / 10 * 2;
8ae6d9c7
GM		 85 if (IS_QLAFX00(ha)) {
86 tmo = FX00_DEF_RATOV * 2;
87 } else if (!IS_FWI2_CAPABLE(ha)) {
5b91490e
AV		 88 /*
89 * Except for earlier ISPs where the timeout is seeded from the
90 * initialization control block.
91 */
92 tmo = ha->login_timeout;
93 }
94 return tmo;
95}
ac280b67
AV		 96
97static void
9ba56b95 98qla2x00_async_iocb_timeout(void *data)
ac280b67 99{
9ba56b95 100 srb_t *sp = (srb_t *)data;
ac280b67 101 fc_port_t *fcport = sp->fcport;
ac280b67 102
7c3df132 103 ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
cfb0919c 104 "Async-%s timeout - hdl=%x portid=%02x%02x%02x.\n",
9ba56b95 105 sp->name, sp->handle, fcport->d_id.b.domain, fcport->d_id.b.area,
7c3df132 106 fcport->d_id.b.al_pa);
ac280b67 107
5ff1d584 108 fcport->flags &= ~FCF_ASYNC_SENT;
9ba56b95
GM		 109 if (sp->type == SRB_LOGIN_CMD) {
110 struct srb_iocb *lio = &sp->u.iocb_cmd;
ac280b67 111 qla2x00_post_async_logout_work(fcport->vha, fcport, NULL);
6ac52608
AV		 112 /* Retry as needed. */
113 lio->u.logio.data[0] = MBS_COMMAND_ERROR;
114 lio->u.logio.data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
115 QLA_LOGIO_LOGIN_RETRIED : 0;
116 qla2x00_post_async_login_done_work(fcport->vha, fcport,
117 lio->u.logio.data);
118 }
ac280b67
AV		 119}
120
99b0bec7 121static void
9ba56b95 122qla2x00_async_login_sp_done(void *data, void *ptr, int res)
99b0bec7 123{
9ba56b95
GM		 124 srb_t *sp = (srb_t *)ptr;
125 struct srb_iocb *lio = &sp->u.iocb_cmd;
126 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
127
128 if (!test_bit(UNLOADING, &vha->dpc_flags))
129 qla2x00_post_async_login_done_work(sp->fcport->vha, sp->fcport,
130 lio->u.logio.data);
131 sp->free(sp->fcport->vha, sp);
99b0bec7
AV		 132}
133
ac280b67
AV		 134int
135qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport,
136 uint16_t *data)
137{
ac280b67 138 srb_t *sp;
4916392b 139 struct srb_iocb *lio;
ac280b67
AV		 140 int rval;
141
142 rval = QLA_FUNCTION_FAILED;
9ba56b95 143 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 144 if (!sp)
145 goto done;
146
9ba56b95
GM		 147 sp->type = SRB_LOGIN_CMD;
148 sp->name = "login";
149 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
150
151 lio = &sp->u.iocb_cmd;
3822263e 152 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 153 sp->done = qla2x00_async_login_sp_done;
4916392b 154 lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI;
ac280b67 155 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 156 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
ac280b67
AV		 157 rval = qla2x00_start_sp(sp);
158 if (rval != QLA_SUCCESS)
159 goto done_free_sp;
160
7c3df132 161 ql_dbg(ql_dbg_disc, vha, 0x2072,
cfb0919c
CD		 162 "Async-login - hdl=%x, loopid=%x portid=%02x%02x%02x "
163 "retries=%d.\n", sp->handle, fcport->loop_id,
164 fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
165 fcport->login_retry);
ac280b67
AV		 166 return rval;
167
168done_free_sp:
9ba56b95 169 sp->free(fcport->vha, sp);
ac280b67
AV		 170done:
171 return rval;
172}
173
99b0bec7 174static void
9ba56b95 175qla2x00_async_logout_sp_done(void *data, void *ptr, int res)
99b0bec7 176{
9ba56b95
GM		 177 srb_t *sp = (srb_t *)ptr;
178 struct srb_iocb *lio = &sp->u.iocb_cmd;
179 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
180
181 if (!test_bit(UNLOADING, &vha->dpc_flags))
182 qla2x00_post_async_logout_done_work(sp->fcport->vha, sp->fcport,
183 lio->u.logio.data);
184 sp->free(sp->fcport->vha, sp);
99b0bec7
AV		 185}
186
ac280b67
AV		 187int
188qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport)
189{
ac280b67 190 srb_t *sp;
4916392b 191 struct srb_iocb *lio;
ac280b67
AV		 192 int rval;
193
194 rval = QLA_FUNCTION_FAILED;
9ba56b95 195 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 196 if (!sp)
197 goto done;
198
9ba56b95
GM		 199 sp->type = SRB_LOGOUT_CMD;
200 sp->name = "logout";
201 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
202
203 lio = &sp->u.iocb_cmd;
3822263e 204 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 205 sp->done = qla2x00_async_logout_sp_done;
ac280b67
AV		 206 rval = qla2x00_start_sp(sp);
207 if (rval != QLA_SUCCESS)
208 goto done_free_sp;
209
7c3df132 210 ql_dbg(ql_dbg_disc, vha, 0x2070,
cfb0919c
CD		 211 "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
212 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
213 fcport->d_id.b.area, fcport->d_id.b.al_pa);
ac280b67
AV		 214 return rval;
215
216done_free_sp:
9ba56b95 217 sp->free(fcport->vha, sp);
ac280b67
AV		 218done:
219 return rval;
220}
221
5ff1d584 222static void
9ba56b95 223qla2x00_async_adisc_sp_done(void *data, void *ptr, int res)
5ff1d584 224{
9ba56b95
GM		 225 srb_t *sp = (srb_t *)ptr;
226 struct srb_iocb *lio = &sp->u.iocb_cmd;
227 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
228
229 if (!test_bit(UNLOADING, &vha->dpc_flags))
230 qla2x00_post_async_adisc_done_work(sp->fcport->vha, sp->fcport,
231 lio->u.logio.data);
232 sp->free(sp->fcport->vha, sp);
5ff1d584
AV		 233}
234
235int
236qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport,
237 uint16_t *data)
238{
5ff1d584 239 srb_t *sp;
4916392b 240 struct srb_iocb *lio;
5ff1d584
AV		 241 int rval;
242
243 rval = QLA_FUNCTION_FAILED;
9ba56b95 244 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
5ff1d584
AV		 245 if (!sp)
246 goto done;
247
9ba56b95
GM		 248 sp->type = SRB_ADISC_CMD;
249 sp->name = "adisc";
250 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
251
252 lio = &sp->u.iocb_cmd;
3822263e 253 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 254 sp->done = qla2x00_async_adisc_sp_done;
5ff1d584 255 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 256 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
5ff1d584
AV		 257 rval = qla2x00_start_sp(sp);
258 if (rval != QLA_SUCCESS)
259 goto done_free_sp;
260
7c3df132 261 ql_dbg(ql_dbg_disc, vha, 0x206f,
cfb0919c
CD		 262 "Async-adisc - hdl=%x loopid=%x portid=%02x%02x%02x.\n",
263 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
264 fcport->d_id.b.area, fcport->d_id.b.al_pa);
5ff1d584
AV		 265 return rval;
266
267done_free_sp:
9ba56b95 268 sp->free(fcport->vha, sp);
5ff1d584
AV		 269done:
270 return rval;
271}
272
3822263e 273static void
9ba56b95 274qla2x00_async_tm_cmd_done(void *data, void *ptr, int res)
3822263e 275{
9ba56b95
GM		 276 srb_t *sp = (srb_t *)ptr;
277 struct srb_iocb *iocb = &sp->u.iocb_cmd;
278 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
279 uint32_t flags;
280 uint16_t lun;
281 int rval;
3822263e 282
9ba56b95
GM		 283 if (!test_bit(UNLOADING, &vha->dpc_flags)) {
284 flags = iocb->u.tmf.flags;
285 lun = (uint16_t)iocb->u.tmf.lun;
286
287 /* Issue Marker IOCB */
288 rval = qla2x00_marker(vha, vha->hw->req_q_map[0],
289 vha->hw->rsp_q_map[0], sp->fcport->loop_id, lun,
290 flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
291
292 if ((rval != QLA_SUCCESS) || iocb->u.tmf.data) {
293 ql_dbg(ql_dbg_taskm, vha, 0x8030,
294 "TM IOCB failed (%x).\n", rval);
295 }
296 }
297 sp->free(sp->fcport->vha, sp);
3822263e
MI		 298}
299
300int
9ba56b95 301qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t tm_flags, uint32_t lun,
3822263e
MI		 302 uint32_t tag)
303{
304 struct scsi_qla_host *vha = fcport->vha;
3822263e 305 srb_t *sp;
3822263e
MI		 306 struct srb_iocb *tcf;
307 int rval;
308
309 rval = QLA_FUNCTION_FAILED;
9ba56b95 310 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
3822263e
MI		 311 if (!sp)
312 goto done;
313
9ba56b95
GM		 314 sp->type = SRB_TM_CMD;
315 sp->name = "tmf";
316 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
317
318 tcf = &sp->u.iocb_cmd;
319 tcf->u.tmf.flags = tm_flags;
3822263e
MI		 320 tcf->u.tmf.lun = lun;
321 tcf->u.tmf.data = tag;
322 tcf->timeout = qla2x00_async_iocb_timeout;
9ba56b95 323 sp->done = qla2x00_async_tm_cmd_done;
3822263e
MI		 324
325 rval = qla2x00_start_sp(sp);
326 if (rval != QLA_SUCCESS)
327 goto done_free_sp;
328
7c3df132 329 ql_dbg(ql_dbg_taskm, vha, 0x802f,
cfb0919c
CD		 330 "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
331 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
332 fcport->d_id.b.area, fcport->d_id.b.al_pa);
3822263e
MI		 333 return rval;
334
335done_free_sp:
9ba56b95 336 sp->free(fcport->vha, sp);
3822263e
MI		 337done:
338 return rval;
339}
340
4916392b 341void
ac280b67
AV		 342qla2x00_async_login_done(struct scsi_qla_host *vha, fc_port_t *fcport,
343 uint16_t *data)
344{
345 int rval;
ac280b67
AV		 346
347 switch (data[0]) {
348 case MBS_COMMAND_COMPLETE:
a4f92a32
AV		 349 /*
350 * Driver must validate login state - If PRLI not complete,
351 * force a relogin attempt via implicit LOGO, PLOGI, and PRLI
352 * requests.
353 */
354 rval = qla2x00_get_port_database(vha, fcport, 0);
0eba25df
AE		 355 if (rval == QLA_NOT_LOGGED_IN) {
356 fcport->flags &= ~FCF_ASYNC_SENT;
357 fcport->flags |= FCF_LOGIN_NEEDED;
358 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
359 break;
360 }
361
a4f92a32
AV		 362 if (rval != QLA_SUCCESS) {
363 qla2x00_post_async_logout_work(vha, fcport, NULL);
364 qla2x00_post_async_login_work(vha, fcport, NULL);
365 break;
366 }
99b0bec7 367 if (fcport->flags & FCF_FCP2_DEVICE) {
5ff1d584
AV		 368 qla2x00_post_async_adisc_work(vha, fcport, data);
369 break;
99b0bec7
AV		 370 }
371 qla2x00_update_fcport(vha, fcport);
ac280b67
AV		 372 break;
373 case MBS_COMMAND_ERROR:
5ff1d584 374 fcport->flags &= ~FCF_ASYNC_SENT;
ac280b67
AV		 375 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
376 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
377 else
80d79440 378 qla2x00_mark_device_lost(vha, fcport, 1, 0);
ac280b67
AV		 379 break;
380 case MBS_PORT_ID_USED:
381 fcport->loop_id = data[1];
6ac52608 382 qla2x00_post_async_logout_work(vha, fcport, NULL);
ac280b67
AV		 383 qla2x00_post_async_login_work(vha, fcport, NULL);
384 break;
385 case MBS_LOOP_ID_USED:
386 fcport->loop_id++;
387 rval = qla2x00_find_new_loop_id(vha, fcport);
388 if (rval != QLA_SUCCESS) {
5ff1d584 389 fcport->flags &= ~FCF_ASYNC_SENT;
80d79440 390 qla2x00_mark_device_lost(vha, fcport, 1, 0);
ac280b67
AV		 391 break;
392 }
393 qla2x00_post_async_login_work(vha, fcport, NULL);
394 break;
395 }
4916392b 396 return;
ac280b67
AV		 397}
398
4916392b 399void
ac280b67
AV		 400qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport,
401 uint16_t *data)
402{
403 qla2x00_mark_device_lost(vha, fcport, 1, 0);
4916392b 404 return;
ac280b67
AV		 405}
406
4916392b 407void
5ff1d584
AV		 408qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport,
409 uint16_t *data)
410{
411 if (data[0] == MBS_COMMAND_COMPLETE) {
412 qla2x00_update_fcport(vha, fcport);
413
4916392b 414 return;
5ff1d584
AV		 415 }
416
417 /* Retry login. */
418 fcport->flags &= ~FCF_ASYNC_SENT;
419 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
420 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
421 else
80d79440 422 qla2x00_mark_device_lost(vha, fcport, 1, 0);
5ff1d584 423
4916392b 424 return;
5ff1d584
AV		 425}
426
1da177e4
LT		 427/****************************************************************************/
428/* QLogic ISP2x00 Hardware Support Functions. */
429/****************************************************************************/
430
fa492630 431static int
7d613ac6
SV		 432qla83xx_nic_core_fw_load(scsi_qla_host_t *vha)
433{
434 int rval = QLA_SUCCESS;
435 struct qla_hw_data *ha = vha->hw;
436 uint32_t idc_major_ver, idc_minor_ver;
711aa7f7 437 uint16_t config[4];
7d613ac6
SV		 438
439 qla83xx_idc_lock(vha, 0);
440
441 /* SV: TODO: Assign initialization timeout from
442 * flash-info / other param
443 */
444 ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT;
445 ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT;
446
447 /* Set our fcoe function presence */
448 if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) {
449 ql_dbg(ql_dbg_p3p, vha, 0xb077,
450 "Error while setting DRV-Presence.\n");
451 rval = QLA_FUNCTION_FAILED;
452 goto exit;
453 }
454
455 /* Decide the reset ownership */
456 qla83xx_reset_ownership(vha);
457
458 /*
459 * On first protocol driver load:
460 * Init-Owner: Set IDC-Major-Version and Clear IDC-Lock-Recovery
461 * register.
462 * Others: Check compatibility with current IDC Major version.
463 */
464 qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver);
465 if (ha->flags.nic_core_reset_owner) {
466 /* Set IDC Major version */
467 idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION;
468 qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver);
469
470 /* Clearing IDC-Lock-Recovery register */
471 qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0);
472 } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) {
473 /*
474 * Clear further IDC participation if we are not compatible with
475 * the current IDC Major Version.
476 */
477 ql_log(ql_log_warn, vha, 0xb07d,
478 "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n",
479 idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION);
480 __qla83xx_clear_drv_presence(vha);
481 rval = QLA_FUNCTION_FAILED;
482 goto exit;
483 }
484 /* Each function sets its supported Minor version. */
485 qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver);
486 idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2));
487 qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver);
488
711aa7f7
SK		 489 if (ha->flags.nic_core_reset_owner) {
490 memset(config, 0, sizeof(config));
491 if (!qla81xx_get_port_config(vha, config))
492 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
493 QLA8XXX_DEV_READY);
494 }
495
7d613ac6
SV		 496 rval = qla83xx_idc_state_handler(vha);
497
498exit:
499 qla83xx_idc_unlock(vha, 0);
500
501 return rval;
502}
503
1da177e4
LT		 504/*
505* qla2x00_initialize_adapter
506* Initialize board.
507*
508* Input:
509* ha = adapter block pointer.
510*
511* Returns:
512* 0 = success
513*/
514int
e315cd28 515qla2x00_initialize_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 516{
517 int rval;
e315cd28 518 struct qla_hw_data *ha = vha->hw;
73208dfd 519 struct req_que *req = ha->req_q_map[0];
2533cf67 520
1da177e4 521 /* Clear adapter flags. */
e315cd28 522 vha->flags.online = 0;
2533cf67 523 ha->flags.chip_reset_done = 0;
e315cd28 524 vha->flags.reset_active = 0;
85880801
AV		 525 ha->flags.pci_channel_io_perm_failure = 0;
526 ha->flags.eeh_busy = 0;
fe52f6e1 527 ha->thermal_support = THERMAL_SUPPORT_I2C|THERMAL_SUPPORT_ISP;
e315cd28
AC		 528 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
529 atomic_set(&vha->loop_state, LOOP_DOWN);
530 vha->device_flags = DFLG_NO_CABLE;
531 vha->dpc_flags = 0;
532 vha->flags.management_server_logged_in = 0;
533 vha->marker_needed = 0;
1da177e4
LT		 534 ha->isp_abort_cnt = 0;
535 ha->beacon_blink_led = 0;
536
73208dfd
AC		 537 set_bit(0, ha->req_qid_map);
538 set_bit(0, ha->rsp_qid_map);
539
cfb0919c 540 ql_dbg(ql_dbg_init, vha, 0x0040,
7c3df132 541 "Configuring PCI space...\n");
e315cd28 542 rval = ha->isp_ops->pci_config(vha);
1da177e4 543 if (rval) {
7c3df132
SK		 544 ql_log(ql_log_warn, vha, 0x0044,
545 "Unable to configure PCI space.\n");
1da177e4
LT		 546 return (rval);
547 }
548
e315cd28 549 ha->isp_ops->reset_chip(vha);
1da177e4 550
e315cd28 551 rval = qla2xxx_get_flash_info(vha);
c00d8994 552 if (rval) {
7c3df132
SK		 553 ql_log(ql_log_fatal, vha, 0x004f,
554 "Unable to validate FLASH data.\n");
7ec0effd
AD		 555 return rval;
556 }
557
558 if (IS_QLA8044(ha)) {
559 qla8044_read_reset_template(vha);
560
561 /* NOTE: If ql2xdontresethba==1, set IDC_CTRL DONTRESET_BIT0.
562 * If DONRESET_BIT0 is set, drivers should not set dev_state
563 * to NEED_RESET. But if NEED_RESET is set, drivers should
564 * should honor the reset. */
565 if (ql2xdontresethba == 1)
566 qla8044_set_idc_dontreset(vha);
c00d8994
AV		 567 }
568
73208dfd 569 ha->isp_ops->get_flash_version(vha, req->ring);
cfb0919c 570 ql_dbg(ql_dbg_init, vha, 0x0061,
7c3df132 571 "Configure NVRAM parameters...\n");
0107109e 572
e315cd28 573 ha->isp_ops->nvram_config(vha);
1da177e4 574
d4c760c2
AV		 575 if (ha->flags.disable_serdes) {
576 /* Mask HBA via NVRAM settings? */
7c3df132 577 ql_log(ql_log_info, vha, 0x0077,
7b833558 578 "Masking HBA WWPN %8phN (via NVRAM).\n", vha->port_name);
d4c760c2
AV		 579 return QLA_FUNCTION_FAILED;
580 }
581
cfb0919c 582 ql_dbg(ql_dbg_init, vha, 0x0078,
7c3df132 583 "Verifying loaded RISC code...\n");
1da177e4 584
e315cd28
AC		 585 if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) {
586 rval = ha->isp_ops->chip_diag(vha);
d19044c3
AV		 587 if (rval)
588 return (rval);
e315cd28 589 rval = qla2x00_setup_chip(vha);
d19044c3
AV		 590 if (rval)
591 return (rval);
1da177e4 592 }
a9083016 593
4d4df193 594 if (IS_QLA84XX(ha)) {
e315cd28 595 ha->cs84xx = qla84xx_get_chip(vha);
4d4df193 596 if (!ha->cs84xx) {
7c3df132 597 ql_log(ql_log_warn, vha, 0x00d0,
4d4df193
HK		 598 "Unable to configure ISP84XX.\n");
599 return QLA_FUNCTION_FAILED;
600 }
601 }
2d70c103
NB		 602
603 if (qla_ini_mode_enabled(vha))
604 rval = qla2x00_init_rings(vha);
605
2533cf67 606 ha->flags.chip_reset_done = 1;
1da177e4 607
9a069e19 608 if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) {
6c452a45 609 /* Issue verify 84xx FW IOCB to complete 84xx initialization */
9a069e19
GM		 610 rval = qla84xx_init_chip(vha);
611 if (rval != QLA_SUCCESS) {
7c3df132
SK		 612 ql_log(ql_log_warn, vha, 0x00d4,
613 "Unable to initialize ISP84XX.\n");
9a069e19
GM		 614 qla84xx_put_chip(vha);
615 }
616 }
617
7d613ac6
SV		 618 /* Load the NIC Core f/w if we are the first protocol driver. */
619 if (IS_QLA8031(ha)) {
620 rval = qla83xx_nic_core_fw_load(vha);
621 if (rval)
622 ql_log(ql_log_warn, vha, 0x0124,
623 "Error in initializing NIC Core f/w.\n");
624 }
625
2f0f3f4f
MI		 626 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
627 qla24xx_read_fcp_prio_cfg(vha);
09ff701a 628
1da177e4
LT		 629 return (rval);
630}
631
632/**
abbd8870 633 * qla2100_pci_config() - Setup ISP21xx PCI configuration registers.
1da177e4
LT		 634 * @ha: HA context
635 *
636 * Returns 0 on success.
637 */
abbd8870 638int
e315cd28 639qla2100_pci_config(scsi_qla_host_t *vha)
1da177e4 640{
a157b101 641 uint16_t w;
abbd8870 642 unsigned long flags;
e315cd28 643 struct qla_hw_data *ha = vha->hw;
3d71644c 644 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 645
1da177e4 646 pci_set_master(ha->pdev);
af6177d8 647 pci_try_set_mwi(ha->pdev);
1da177e4 648
1da177e4 649 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 650 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
abbd8870
AV		 651 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
652
737faece 653 pci_disable_rom(ha->pdev);
1da177e4
LT		 654
655 /* Get PCI bus information. */
656 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 657 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
1da177e4
LT		 658 spin_unlock_irqrestore(&ha->hardware_lock, flags);
659
abbd8870
AV		 660 return QLA_SUCCESS;
661}
1da177e4 662
abbd8870
AV		 663/**
664 * qla2300_pci_config() - Setup ISP23xx PCI configuration registers.
665 * @ha: HA context
666 *
667 * Returns 0 on success.
668 */
669int
e315cd28 670qla2300_pci_config(scsi_qla_host_t *vha)
abbd8870 671{
a157b101 672 uint16_t w;
abbd8870
AV		 673 unsigned long flags = 0;
674 uint32_t cnt;
e315cd28 675 struct qla_hw_data *ha = vha->hw;
3d71644c 676 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 677
abbd8870 678 pci_set_master(ha->pdev);
af6177d8 679 pci_try_set_mwi(ha->pdev);
1da177e4 680
abbd8870 681 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 682 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
1da177e4 683
abbd8870
AV		 684 if (IS_QLA2322(ha) || IS_QLA6322(ha))
685 w &= ~PCI_COMMAND_INTX_DISABLE;
a157b101 686 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1da177e4 687
abbd8870
AV		 688 /*
689 * If this is a 2300 card and not 2312, reset the
690 * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately,
691 * the 2310 also reports itself as a 2300 so we need to get the
692 * fb revision level -- a 6 indicates it really is a 2300 and
693 * not a 2310.
694 */
695 if (IS_QLA2300(ha)) {
696 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 697
abbd8870 698 /* Pause RISC. */
3d71644c 699 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
abbd8870 700 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 701 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
abbd8870 702 break;
1da177e4 703
abbd8870
AV		 704 udelay(10);
705 }
1da177e4 706
abbd8870 707 /* Select FPM registers. */
3d71644c
AV		 708 WRT_REG_WORD(&reg->ctrl_status, 0x20);
709 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 710
711 /* Get the fb rev level */
3d71644c 712 ha->fb_rev = RD_FB_CMD_REG(ha, reg);
abbd8870
AV		 713
714 if (ha->fb_rev == FPM_2300)
a157b101 715 pci_clear_mwi(ha->pdev);
abbd8870
AV		 716
717 /* Deselect FPM registers. */
3d71644c
AV		 718 WRT_REG_WORD(&reg->ctrl_status, 0x0);
719 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 720
721 /* Release RISC module. */
3d71644c 722 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
abbd8870 723 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 724 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0)
abbd8870
AV		 725 break;
726
727 udelay(10);
1da177e4 728 }
1da177e4 729
abbd8870
AV		 730 spin_unlock_irqrestore(&ha->hardware_lock, flags);
731 }
1da177e4 732
abbd8870
AV		 733 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
734
737faece 735 pci_disable_rom(ha->pdev);
1da177e4 736
abbd8870
AV		 737 /* Get PCI bus information. */
738 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 739 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 740 spin_unlock_irqrestore(&ha->hardware_lock, flags);
741
742 return QLA_SUCCESS;
1da177e4
LT		 743}
744
0107109e
AV		 745/**
746 * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers.
747 * @ha: HA context
748 *
749 * Returns 0 on success.
750 */
751int
e315cd28 752qla24xx_pci_config(scsi_qla_host_t *vha)
0107109e 753{
a157b101 754 uint16_t w;
0107109e 755 unsigned long flags = 0;
e315cd28 756 struct qla_hw_data *ha = vha->hw;
0107109e 757 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
0107109e
AV		 758
759 pci_set_master(ha->pdev);
af6177d8 760 pci_try_set_mwi(ha->pdev);
0107109e
AV		 761
762 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 763 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
0107109e
AV		 764 w &= ~PCI_COMMAND_INTX_DISABLE;
765 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
766
767 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
768
769 /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */
f85ec187
AV		 770 if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
771 pcix_set_mmrbc(ha->pdev, 2048);
0107109e
AV		 772
773 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 774 if (pci_is_pcie(ha->pdev))
5ffd3a52 775 pcie_set_readrq(ha->pdev, 4096);
0107109e 776
737faece 777 pci_disable_rom(ha->pdev);
0107109e 778
44c10138 779 ha->chip_revision = ha->pdev->revision;
a8488abe 780
0107109e
AV		 781 /* Get PCI bus information. */
782 spin_lock_irqsave(&ha->hardware_lock, flags);
783 ha->pci_attr = RD_REG_DWORD(&reg->ctrl_status);
784 spin_unlock_irqrestore(&ha->hardware_lock, flags);
785
786 return QLA_SUCCESS;
787}
788
c3a2f0df
AV		 789/**
790 * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers.
791 * @ha: HA context
792 *
793 * Returns 0 on success.
794 */
795int
e315cd28 796qla25xx_pci_config(scsi_qla_host_t *vha)
c3a2f0df
AV		 797{
798 uint16_t w;
e315cd28 799 struct qla_hw_data *ha = vha->hw;
c3a2f0df
AV		 800
801 pci_set_master(ha->pdev);
802 pci_try_set_mwi(ha->pdev);
803
804 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
805 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
806 w &= ~PCI_COMMAND_INTX_DISABLE;
807 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
808
809 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 810 if (pci_is_pcie(ha->pdev))
5ffd3a52 811 pcie_set_readrq(ha->pdev, 4096);
c3a2f0df 812
737faece 813 pci_disable_rom(ha->pdev);
c3a2f0df
AV		 814
815 ha->chip_revision = ha->pdev->revision;
816
817 return QLA_SUCCESS;
818}
819
1da177e4
LT		 820/**
821 * qla2x00_isp_firmware() - Choose firmware image.
822 * @ha: HA context
823 *
824 * Returns 0 on success.
825 */
826static int
e315cd28 827qla2x00_isp_firmware(scsi_qla_host_t *vha)
1da177e4
LT		 828{
829 int rval;
42e421b1
AV		 830 uint16_t loop_id, topo, sw_cap;
831 uint8_t domain, area, al_pa;
e315cd28 832 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 833
834 /* Assume loading risc code */
fa2a1ce5 835 rval = QLA_FUNCTION_FAILED;
1da177e4
LT		 836
837 if (ha->flags.disable_risc_code_load) {
7c3df132 838 ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n");
1da177e4
LT		 839
840 /* Verify checksum of loaded RISC code. */
e315cd28 841 rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address);
42e421b1
AV		 842 if (rval == QLA_SUCCESS) {
843 /* And, verify we are not in ROM code. */
e315cd28 844 rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa,
42e421b1
AV		 845 &area, &domain, &topo, &sw_cap);
846 }
1da177e4
LT		 847 }
848
7c3df132
SK		 849 if (rval)
850 ql_dbg(ql_dbg_init, vha, 0x007a,
851 "**** Load RISC code ****.\n");
1da177e4
LT		 852
853 return (rval);
854}
855
856/**
857 * qla2x00_reset_chip() - Reset ISP chip.
858 * @ha: HA context
859 *
860 * Returns 0 on success.
861 */
abbd8870 862void
e315cd28 863qla2x00_reset_chip(scsi_qla_host_t *vha)
1da177e4
LT		 864{
865 unsigned long flags = 0;
e315cd28 866 struct qla_hw_data *ha = vha->hw;
3d71644c 867 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 868 uint32_t cnt;
1da177e4
LT		 869 uint16_t cmd;
870
85880801
AV		 871 if (unlikely(pci_channel_offline(ha->pdev)))
872 return;
873
fd34f556 874 ha->isp_ops->disable_intrs(ha);
1da177e4
LT		 875
876 spin_lock_irqsave(&ha->hardware_lock, flags);
877
878 /* Turn off master enable */
879 cmd = 0;
880 pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd);
881 cmd &= ~PCI_COMMAND_MASTER;
882 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
883
884 if (!IS_QLA2100(ha)) {
885 /* Pause RISC. */
886 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
887 if (IS_QLA2200(ha) || IS_QLA2300(ha)) {
888 for (cnt = 0; cnt < 30000; cnt++) {
889 if ((RD_REG_WORD(&reg->hccr) &
890 HCCR_RISC_PAUSE) != 0)
891 break;
892 udelay(100);
893 }
894 } else {
895 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
896 udelay(10);
897 }
898
899 /* Select FPM registers. */
900 WRT_REG_WORD(&reg->ctrl_status, 0x20);
901 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
902
903 /* FPM Soft Reset. */
904 WRT_REG_WORD(&reg->fpm_diag_config, 0x100);
905 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
906
907 /* Toggle Fpm Reset. */
908 if (!IS_QLA2200(ha)) {
909 WRT_REG_WORD(&reg->fpm_diag_config, 0x0);
910 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
911 }
912
913 /* Select frame buffer registers. */
914 WRT_REG_WORD(&reg->ctrl_status, 0x10);
915 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
916
917 /* Reset frame buffer FIFOs. */
918 if (IS_QLA2200(ha)) {
919 WRT_FB_CMD_REG(ha, reg, 0xa000);
920 RD_FB_CMD_REG(ha, reg); /* PCI Posting. */
921 } else {
922 WRT_FB_CMD_REG(ha, reg, 0x00fc);
923
924 /* Read back fb_cmd until zero or 3 seconds max */
925 for (cnt = 0; cnt < 3000; cnt++) {
926 if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0)
927 break;
928 udelay(100);
929 }
930 }
931
932 /* Select RISC module registers. */
933 WRT_REG_WORD(&reg->ctrl_status, 0);
934 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
935
936 /* Reset RISC processor. */
937 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
938 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
939
940 /* Release RISC processor. */
941 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
942 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
943 }
944
945 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
946 WRT_REG_WORD(&reg->hccr, HCCR_CLR_HOST_INT);
947
948 /* Reset ISP chip. */
949 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
950
951 /* Wait for RISC to recover from reset. */
952 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
953 /*
954 * It is necessary to for a delay here since the card doesn't
955 * respond to PCI reads during a reset. On some architectures
956 * this will result in an MCA.
957 */
958 udelay(20);
959 for (cnt = 30000; cnt; cnt--) {
960 if ((RD_REG_WORD(&reg->ctrl_status) &
961 CSR_ISP_SOFT_RESET) == 0)
962 break;
963 udelay(100);
964 }
965 } else
966 udelay(10);
967
968 /* Reset RISC processor. */
969 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
970
971 WRT_REG_WORD(&reg->semaphore, 0);
972
973 /* Release RISC processor. */
974 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
975 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
976
977 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
978 for (cnt = 0; cnt < 30000; cnt++) {
ffb39f03 979 if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY)
1da177e4 980 break;
1da177e4
LT		 981
982 udelay(100);
983 }
984 } else
985 udelay(100);
986
987 /* Turn on master enable */
988 cmd |= PCI_COMMAND_MASTER;
989 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
990
991 /* Disable RISC pause on FPM parity error. */
992 if (!IS_QLA2100(ha)) {
993 WRT_REG_WORD(&reg->hccr, HCCR_DISABLE_PARITY_PAUSE);
994 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
995 }
996
997 spin_unlock_irqrestore(&ha->hardware_lock, flags);
998}
999
b1d46989
MI		 1000/**
1001 * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC.
1002 *
1003 * Returns 0 on success.
1004 */
fa492630 1005static int
b1d46989
MI		 1006qla81xx_reset_mpi(scsi_qla_host_t *vha)
1007{
1008 uint16_t mb[4] = {0x1010, 0, 1, 0};
1009
6246b8a1
GM		 1010 if (!IS_QLA81XX(vha->hw))
1011 return QLA_SUCCESS;
1012
b1d46989
MI		 1013 return qla81xx_write_mpi_register(vha, mb);
1014}
1015
0107109e 1016/**
88c26663 1017 * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC.
0107109e
AV		 1018 * @ha: HA context
1019 *
1020 * Returns 0 on success.
1021 */
88c26663 1022static inline void
e315cd28 1023qla24xx_reset_risc(scsi_qla_host_t *vha)
0107109e
AV		 1024{
1025 unsigned long flags = 0;
e315cd28 1026 struct qla_hw_data *ha = vha->hw;
0107109e
AV		 1027 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1028 uint32_t cnt, d2;
335a1cc9 1029 uint16_t wd;
b1d46989 1030 static int abts_cnt; /* ISP abort retry counts */
0107109e 1031
0107109e
AV		 1032 spin_lock_irqsave(&ha->hardware_lock, flags);
1033
1034 /* Reset RISC. */
1035 WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
1036 for (cnt = 0; cnt < 30000; cnt++) {
1037 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
1038 break;
1039
1040 udelay(10);
1041 }
1042
1043 WRT_REG_DWORD(&reg->ctrl_status,
1044 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
335a1cc9 1045 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
88c26663 1046
335a1cc9 1047 udelay(100);
88c26663 1048 /* Wait for firmware to complete NVRAM accesses. */
88c26663
AV		 1049 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1050 for (cnt = 10000 ; cnt && d2; cnt--) {
1051 udelay(5);
1052 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1053 barrier();
1054 }
1055
335a1cc9 1056 /* Wait for soft-reset to complete. */
0107109e
AV		 1057 d2 = RD_REG_DWORD(&reg->ctrl_status);
1058 for (cnt = 6000000 ; cnt && (d2 & CSRX_ISP_SOFT_RESET); cnt--) {
1059 udelay(5);
1060 d2 = RD_REG_DWORD(&reg->ctrl_status);
1061 barrier();
1062 }
1063
b1d46989
MI		 1064 /* If required, do an MPI FW reset now */
1065 if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
1066 if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
1067 if (++abts_cnt < 5) {
1068 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1069 set_bit(MPI_RESET_NEEDED, &vha->dpc_flags);
1070 } else {
1071 /*
1072 * We exhausted the ISP abort retries. We have to
1073 * set the board offline.
1074 */
1075 abts_cnt = 0;
1076 vha->flags.online = 0;
1077 }
1078 }
1079 }
1080
0107109e
AV		 1081 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
1082 RD_REG_DWORD(&reg->hccr);
1083
1084 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
1085 RD_REG_DWORD(&reg->hccr);
1086
1087 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
1088 RD_REG_DWORD(&reg->hccr);
1089
1090 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1091 for (cnt = 6000000 ; cnt && d2; cnt--) {
1092 udelay(5);
1093 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1094 barrier();
1095 }
1096
1097 spin_unlock_irqrestore(&ha->hardware_lock, flags);
124f85e6
AV		 1098
1099 if (IS_NOPOLLING_TYPE(ha))
1100 ha->isp_ops->enable_intrs(ha);
0107109e
AV		 1101}
1102
4ea2c9c7
JC		 1103static void
1104qla25xx_read_risc_sema_reg(scsi_qla_host_t *vha, uint32_t *data)
1105{
1106 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
1107
1108 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
1109 *data = RD_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET);
1110
1111}
1112
1113static void
1114qla25xx_write_risc_sema_reg(scsi_qla_host_t *vha, uint32_t data)
1115{
1116 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
1117
1118 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
1119 WRT_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET, data);
1120}
1121
1122static void
1123qla25xx_manipulate_risc_semaphore(scsi_qla_host_t *vha)
1124{
1125 struct qla_hw_data *ha = vha->hw;
1126 uint32_t wd32 = 0;
1127 uint delta_msec = 100;
1128 uint elapsed_msec = 0;
1129 uint timeout_msec;
1130 ulong n;
1131
1132 if (!IS_QLA25XX(ha) && !IS_QLA2031(ha))
1133 return;
1134
1135attempt:
1136 timeout_msec = TIMEOUT_SEMAPHORE;
1137 n = timeout_msec / delta_msec;
1138 while (n--) {
1139 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_SET);
1140 qla25xx_read_risc_sema_reg(vha, &wd32);
1141 if (wd32 & RISC_SEMAPHORE)
1142 break;
1143 msleep(delta_msec);
1144 elapsed_msec += delta_msec;
1145 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
1146 goto force;
1147 }
1148
1149 if (!(wd32 & RISC_SEMAPHORE))
1150 goto force;
1151
1152 if (!(wd32 & RISC_SEMAPHORE_FORCE))
1153 goto acquired;
1154
1155 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_CLR);
1156 timeout_msec = TIMEOUT_SEMAPHORE_FORCE;
1157 n = timeout_msec / delta_msec;
1158 while (n--) {
1159 qla25xx_read_risc_sema_reg(vha, &wd32);
1160 if (!(wd32 & RISC_SEMAPHORE_FORCE))
1161 break;
1162 msleep(delta_msec);
1163 elapsed_msec += delta_msec;
1164 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
1165 goto force;
1166 }
1167
1168 if (wd32 & RISC_SEMAPHORE_FORCE)
1169 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_CLR);
1170
1171 goto attempt;
1172
1173force:
1174 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_SET);
1175
1176acquired:
1177 return;
1178}
1179
88c26663
AV		 1180/**
1181 * qla24xx_reset_chip() - Reset ISP24xx chip.
1182 * @ha: HA context
1183 *
1184 * Returns 0 on success.
1185 */
1186void
e315cd28 1187qla24xx_reset_chip(scsi_qla_host_t *vha)
88c26663 1188{
e315cd28 1189 struct qla_hw_data *ha = vha->hw;
85880801
AV		 1190
1191 if (pci_channel_offline(ha->pdev) &&
1192 ha->flags.pci_channel_io_perm_failure) {
1193 return;
1194 }
1195
fd34f556 1196 ha->isp_ops->disable_intrs(ha);
88c26663 1197
4ea2c9c7
JC		 1198 qla25xx_manipulate_risc_semaphore(vha);
1199
88c26663 1200 /* Perform RISC reset. */
e315cd28 1201 qla24xx_reset_risc(vha);
88c26663
AV		 1202}
1203
1da177e4
LT		 1204/**
1205 * qla2x00_chip_diag() - Test chip for proper operation.
1206 * @ha: HA context
1207 *
1208 * Returns 0 on success.
1209 */
abbd8870 1210int
e315cd28 1211qla2x00_chip_diag(scsi_qla_host_t *vha)
1da177e4
LT		 1212{
1213 int rval;
e315cd28 1214 struct qla_hw_data *ha = vha->hw;
3d71644c 1215 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 1216 unsigned long flags = 0;
1217 uint16_t data;
1218 uint32_t cnt;
1219 uint16_t mb[5];
73208dfd 1220 struct req_que *req = ha->req_q_map[0];
1da177e4
LT		 1221
1222 /* Assume a failed state */
1223 rval = QLA_FUNCTION_FAILED;
1224
7c3df132
SK		 1225 ql_dbg(ql_dbg_init, vha, 0x007b,
1226 "Testing device at %lx.\n", (u_long)&reg->flash_address);
1da177e4
LT		 1227
1228 spin_lock_irqsave(&ha->hardware_lock, flags);
1229
1230 /* Reset ISP chip. */
1231 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1232
1233 /*
1234 * We need to have a delay here since the card will not respond while
1235 * in reset causing an MCA on some architectures.
1236 */
1237 udelay(20);
1238 data = qla2x00_debounce_register(&reg->ctrl_status);
1239 for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {
1240 udelay(5);
1241 data = RD_REG_WORD(&reg->ctrl_status);
1242 barrier();
1243 }
1244
1245 if (!cnt)
1246 goto chip_diag_failed;
1247
7c3df132
SK		 1248 ql_dbg(ql_dbg_init, vha, 0x007c,
1249 "Reset register cleared by chip reset.\n");
1da177e4
LT		 1250
1251 /* Reset RISC processor. */
1252 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
1253 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
1254
1255 /* Workaround for QLA2312 PCI parity error */
1256 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1257 data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0));
1258 for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) {
1259 udelay(5);
1260 data = RD_MAILBOX_REG(ha, reg, 0);
fa2a1ce5 1261 barrier();
1da177e4
LT		 1262 }
1263 } else
1264 udelay(10);
1265
1266 if (!cnt)
1267 goto chip_diag_failed;
1268
1269 /* Check product ID of chip */
7c3df132 1270 ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product Id of chip.\n");
1da177e4
LT		 1271
1272 mb[1] = RD_MAILBOX_REG(ha, reg, 1);
1273 mb[2] = RD_MAILBOX_REG(ha, reg, 2);
1274 mb[3] = RD_MAILBOX_REG(ha, reg, 3);
1275 mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4));
1276 if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) ||
1277 mb[3] != PROD_ID_3) {
7c3df132
SK		 1278 ql_log(ql_log_warn, vha, 0x0062,
1279 "Wrong product ID = 0x%x,0x%x,0x%x.\n",
1280 mb[1], mb[2], mb[3]);
1da177e4
LT		 1281
1282 goto chip_diag_failed;
1283 }
1284 ha->product_id[0] = mb[1];
1285 ha->product_id[1] = mb[2];
1286 ha->product_id[2] = mb[3];
1287 ha->product_id[3] = mb[4];
1288
1289 /* Adjust fw RISC transfer size */
73208dfd 1290 if (req->length > 1024)
1da177e4
LT		 1291 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024;
1292 else
1293 ha->fw_transfer_size = REQUEST_ENTRY_SIZE *
73208dfd 1294 req->length;
1da177e4
LT		 1295
1296 if (IS_QLA2200(ha) &&
1297 RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) {
1298 /* Limit firmware transfer size with a 2200A */
7c3df132 1299 ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n");
1da177e4 1300
ea5b6382 1301 ha->device_type |= DT_ISP2200A;
1da177e4
LT		 1302 ha->fw_transfer_size = 128;
1303 }
1304
1305 /* Wrap Incoming Mailboxes Test. */
1306 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1307
7c3df132 1308 ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n");
e315cd28 1309 rval = qla2x00_mbx_reg_test(vha);
7c3df132
SK		 1310 if (rval)
1311 ql_log(ql_log_warn, vha, 0x0080,
1312 "Failed mailbox send register test.\n");
1313 else
1da177e4
LT		 1314 /* Flag a successful rval */
1315 rval = QLA_SUCCESS;
1da177e4
LT		 1316 spin_lock_irqsave(&ha->hardware_lock, flags);
1317
1318chip_diag_failed:
1319 if (rval)
7c3df132
SK		 1320 ql_log(ql_log_info, vha, 0x0081,
1321 "Chip diagnostics **** FAILED ****.\n");
1da177e4
LT		 1322
1323 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1324
1325 return (rval);
1326}
1327
0107109e
AV		 1328/**
1329 * qla24xx_chip_diag() - Test ISP24xx for proper operation.
1330 * @ha: HA context
1331 *
1332 * Returns 0 on success.
1333 */
1334int
e315cd28 1335qla24xx_chip_diag(scsi_qla_host_t *vha)
0107109e
AV		 1336{
1337 int rval;
e315cd28 1338 struct qla_hw_data *ha = vha->hw;
73208dfd 1339 struct req_que *req = ha->req_q_map[0];
0107109e 1340
7ec0effd 1341 if (IS_P3P_TYPE(ha))
a9083016
GM		 1342 return QLA_SUCCESS;
1343
73208dfd 1344 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
0107109e 1345
e315cd28 1346 rval = qla2x00_mbx_reg_test(vha);
0107109e 1347 if (rval) {
7c3df132
SK		 1348 ql_log(ql_log_warn, vha, 0x0082,
1349 "Failed mailbox send register test.\n");
0107109e
AV		 1350 } else {
1351 /* Flag a successful rval */
1352 rval = QLA_SUCCESS;
1353 }
1354
1355 return rval;
1356}
1357
a7a167bf 1358void
e315cd28 1359qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
0107109e 1360{
a7a167bf
AV		 1361 int rval;
1362 uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
73208dfd 1363 eft_size, fce_size, mq_size;
df613b96
AV		 1364 dma_addr_t tc_dma;
1365 void *tc;
e315cd28 1366 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 1367 struct req_que *req = ha->req_q_map[0];
1368 struct rsp_que *rsp = ha->rsp_q_map[0];
a7a167bf
AV		 1369
1370 if (ha->fw_dump) {
7c3df132
SK		 1371 ql_dbg(ql_dbg_init, vha, 0x00bd,
1372 "Firmware dump already allocated.\n");
a7a167bf
AV		 1373 return;
1374 }
d4e3e04d 1375
0107109e 1376 ha->fw_dumped = 0;
73208dfd 1377 fixed_size = mem_size = eft_size = fce_size = mq_size = 0;
d4e3e04d 1378 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
a7a167bf 1379 fixed_size = sizeof(struct qla2100_fw_dump);
d4e3e04d 1380 } else if (IS_QLA23XX(ha)) {
a7a167bf
AV		 1381 fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
1382 mem_size = (ha->fw_memory_size - 0x11000 + 1) *
1383 sizeof(uint16_t);
e428924c 1384 } else if (IS_FWI2_CAPABLE(ha)) {
6246b8a1
GM		 1385 if (IS_QLA83XX(ha))
1386 fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem);
1387 else if (IS_QLA81XX(ha))
3a03eb79
AV		 1388 fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
1389 else if (IS_QLA25XX(ha))
1390 fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
1391 else
1392 fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
a7a167bf
AV		 1393 mem_size = (ha->fw_memory_size - 0x100000 + 1) *
1394 sizeof(uint32_t);
050c9bb1 1395 if (ha->mqenable) {
6246b8a1
GM		 1396 if (!IS_QLA83XX(ha))
1397 mq_size = sizeof(struct qla2xxx_mq_chain);
050c9bb1
GM		 1398 /*
1399 * Allocate maximum buffer size for all queues.
1400 * Resizing must be done at end-of-dump processing.
1401 */
1402 mq_size += ha->max_req_queues *
1403 (req->length * sizeof(request_t));
1404 mq_size += ha->max_rsp_queues *
1405 (rsp->length * sizeof(response_t));
1406 }
00876ae8 1407 if (ha->tgt.atio_ring)
2d70c103 1408 mq_size += ha->tgt.atio_q_length * sizeof(request_t);
df613b96 1409 /* Allocate memory for Fibre Channel Event Buffer. */
6246b8a1 1410 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha))
436a7b11 1411 goto try_eft;
df613b96
AV		 1412
1413 tc = dma_alloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
1414 GFP_KERNEL);
1415 if (!tc) {
7c3df132
SK		 1416 ql_log(ql_log_warn, vha, 0x00be,
1417 "Unable to allocate (%d KB) for FCE.\n",
1418 FCE_SIZE / 1024);
17d98630 1419 goto try_eft;
df613b96
AV		 1420 }
1421
1422 memset(tc, 0, FCE_SIZE);
e315cd28 1423 rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS,
df613b96
AV		 1424 ha->fce_mb, &ha->fce_bufs);
1425 if (rval) {
7c3df132
SK		 1426 ql_log(ql_log_warn, vha, 0x00bf,
1427 "Unable to initialize FCE (%d).\n", rval);
df613b96
AV		 1428 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc,
1429 tc_dma);
1430 ha->flags.fce_enabled = 0;
17d98630 1431 goto try_eft;
df613b96 1432 }
cfb0919c 1433 ql_dbg(ql_dbg_init, vha, 0x00c0,
7c3df132 1434 "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024);
df613b96 1435
7d9dade3 1436 fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE;
df613b96
AV		 1437 ha->flags.fce_enabled = 1;
1438 ha->fce_dma = tc_dma;
1439 ha->fce = tc;
436a7b11
AV		 1440try_eft:
1441 /* Allocate memory for Extended Trace Buffer. */
1442 tc = dma_alloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
1443 GFP_KERNEL);
1444 if (!tc) {
7c3df132
SK		 1445 ql_log(ql_log_warn, vha, 0x00c1,
1446 "Unable to allocate (%d KB) for EFT.\n",
1447 EFT_SIZE / 1024);
436a7b11
AV		 1448 goto cont_alloc;
1449 }
1450
1451 memset(tc, 0, EFT_SIZE);
e315cd28 1452 rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
436a7b11 1453 if (rval) {
7c3df132
SK		 1454 ql_log(ql_log_warn, vha, 0x00c2,
1455 "Unable to initialize EFT (%d).\n", rval);
436a7b11
AV		 1456 dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc,
1457 tc_dma);
1458 goto cont_alloc;
1459 }
cfb0919c 1460 ql_dbg(ql_dbg_init, vha, 0x00c3,
7c3df132 1461 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
436a7b11
AV		 1462
1463 eft_size = EFT_SIZE;
1464 ha->eft_dma = tc_dma;
1465 ha->eft = tc;
d4e3e04d 1466 }
a7a167bf 1467cont_alloc:
73208dfd
AC		 1468 req_q_size = req->length * sizeof(request_t);
1469 rsp_q_size = rsp->length * sizeof(response_t);
a7a167bf
AV		 1470
1471 dump_size = offsetof(struct qla2xxx_fw_dump, isp);
2afa19a9 1472 dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size;
bb99de67
AV		 1473 ha->chain_offset = dump_size;
1474 dump_size += mq_size + fce_size;
d4e3e04d
AV		 1475
1476 ha->fw_dump = vmalloc(dump_size);
a7a167bf 1477 if (!ha->fw_dump) {
7c3df132
SK		 1478 ql_log(ql_log_warn, vha, 0x00c4,
1479 "Unable to allocate (%d KB) for firmware dump.\n",
1480 dump_size / 1024);
a7a167bf 1481
e30d1756
MI		 1482 if (ha->fce) {
1483 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
1484 ha->fce_dma);
1485 ha->fce = NULL;
1486 ha->fce_dma = 0;
1487 }
1488
a7a167bf
AV		 1489 if (ha->eft) {
1490 dma_free_coherent(&ha->pdev->dev, eft_size, ha->eft,
1491 ha->eft_dma);
1492 ha->eft = NULL;
1493 ha->eft_dma = 0;
1494 }
1495 return;
1496 }
cfb0919c 1497 ql_dbg(ql_dbg_init, vha, 0x00c5,
7c3df132 1498 "Allocated (%d KB) for firmware dump.\n", dump_size / 1024);
a7a167bf
AV		 1499
1500 ha->fw_dump_len = dump_size;
1501 ha->fw_dump->signature[0] = 'Q';
1502 ha->fw_dump->signature[1] = 'L';
1503 ha->fw_dump->signature[2] = 'G';
1504 ha->fw_dump->signature[3] = 'C';
1505 ha->fw_dump->version = __constant_htonl(1);
1506
1507 ha->fw_dump->fixed_size = htonl(fixed_size);
1508 ha->fw_dump->mem_size = htonl(mem_size);
1509 ha->fw_dump->req_q_size = htonl(req_q_size);
1510 ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
1511
1512 ha->fw_dump->eft_size = htonl(eft_size);
1513 ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma));
1514 ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma));
1515
1516 ha->fw_dump->header_size =
1517 htonl(offsetof(struct qla2xxx_fw_dump, isp));
0107109e
AV		 1518}
1519
18e7555a
AV		 1520static int
1521qla81xx_mpi_sync(scsi_qla_host_t *vha)
1522{
1523#define MPS_MASK 0xe0
1524 int rval;
1525 uint16_t dc;
1526 uint32_t dw;
18e7555a
AV		 1527
1528 if (!IS_QLA81XX(vha->hw))
1529 return QLA_SUCCESS;
1530
1531 rval = qla2x00_write_ram_word(vha, 0x7c00, 1);
1532 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1533 ql_log(ql_log_warn, vha, 0x0105,
1534 "Unable to acquire semaphore.\n");
18e7555a
AV		 1535 goto done;
1536 }
1537
1538 pci_read_config_word(vha->hw->pdev, 0x54, &dc);
1539 rval = qla2x00_read_ram_word(vha, 0x7a15, &dw);
1540 if (rval != QLA_SUCCESS) {
7c3df132 1541 ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n");
18e7555a
AV		 1542 goto done_release;
1543 }
1544
1545 dc &= MPS_MASK;
1546 if (dc == (dw & MPS_MASK))
1547 goto done_release;
1548
1549 dw &= ~MPS_MASK;
1550 dw |= dc;
1551 rval = qla2x00_write_ram_word(vha, 0x7a15, dw);
1552 if (rval != QLA_SUCCESS) {
7c3df132 1553 ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n");
18e7555a
AV		 1554 }
1555
1556done_release:
1557 rval = qla2x00_write_ram_word(vha, 0x7c00, 0);
1558 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1559 ql_log(ql_log_warn, vha, 0x006d,
1560 "Unable to release semaphore.\n");
18e7555a
AV		 1561 }
1562
1563done:
1564 return rval;
1565}
1566
8d93f550
CD		 1567int
1568qla2x00_alloc_outstanding_cmds(struct qla_hw_data *ha, struct req_que *req)
1569{
1570 /* Don't try to reallocate the array */
1571 if (req->outstanding_cmds)
1572 return QLA_SUCCESS;
1573
1574 if (!IS_FWI2_CAPABLE(ha) || (ha->mqiobase &&
1575 (ql2xmultique_tag || ql2xmaxqueues > 1)))
1576 req->num_outstanding_cmds = DEFAULT_OUTSTANDING_COMMANDS;
1577 else {
1578 if (ha->fw_xcb_count <= ha->fw_iocb_count)
1579 req->num_outstanding_cmds = ha->fw_xcb_count;
1580 else
1581 req->num_outstanding_cmds = ha->fw_iocb_count;
1582 }
1583
1584 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
1585 req->num_outstanding_cmds, GFP_KERNEL);
1586
1587 if (!req->outstanding_cmds) {
1588 /*
1589 * Try to allocate a minimal size just so we can get through
1590 * initialization.
1591 */
1592 req->num_outstanding_cmds = MIN_OUTSTANDING_COMMANDS;
1593 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
1594 req->num_outstanding_cmds, GFP_KERNEL);
1595
1596 if (!req->outstanding_cmds) {
1597 ql_log(ql_log_fatal, NULL, 0x0126,
1598 "Failed to allocate memory for "
1599 "outstanding_cmds for req_que %p.\n", req);
1600 req->num_outstanding_cmds = 0;
1601 return QLA_FUNCTION_FAILED;
1602 }
1603 }
1604
1605 return QLA_SUCCESS;
1606}
1607
1da177e4
LT		 1608/**
1609 * qla2x00_setup_chip() - Load and start RISC firmware.
1610 * @ha: HA context
1611 *
1612 * Returns 0 on success.
1613 */
1614static int
e315cd28 1615qla2x00_setup_chip(scsi_qla_host_t *vha)
1da177e4 1616{
0107109e
AV		 1617 int rval;
1618 uint32_t srisc_address = 0;
e315cd28 1619 struct qla_hw_data *ha = vha->hw;
3db0652e
AV		 1620 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1621 unsigned long flags;
dda772e8 1622 uint16_t fw_major_version;
3db0652e 1623
7ec0effd 1624 if (IS_P3P_TYPE(ha)) {
a9083016 1625 rval = ha->isp_ops->load_risc(vha, &srisc_address);
14e303d9
AV		 1626 if (rval == QLA_SUCCESS) {
1627 qla2x00_stop_firmware(vha);
a9083016 1628 goto enable_82xx_npiv;
14e303d9 1629 } else
b963752f 1630 goto failed;
a9083016
GM		 1631 }
1632
3db0652e
AV		 1633 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1634 /* Disable SRAM, Instruction RAM and GP RAM parity. */
1635 spin_lock_irqsave(&ha->hardware_lock, flags);
1636 WRT_REG_WORD(&reg->hccr, (HCCR_ENABLE_PARITY + 0x0));
1637 RD_REG_WORD(&reg->hccr);
1638 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1639 }
1da177e4 1640
18e7555a
AV		 1641 qla81xx_mpi_sync(vha);
1642
1da177e4 1643 /* Load firmware sequences */
e315cd28 1644 rval = ha->isp_ops->load_risc(vha, &srisc_address);
0107109e 1645 if (rval == QLA_SUCCESS) {
7c3df132
SK		 1646 ql_dbg(ql_dbg_init, vha, 0x00c9,
1647 "Verifying Checksum of loaded RISC code.\n");
1da177e4 1648
e315cd28 1649 rval = qla2x00_verify_checksum(vha, srisc_address);
1da177e4
LT		 1650 if (rval == QLA_SUCCESS) {
1651 /* Start firmware execution. */
7c3df132
SK		 1652 ql_dbg(ql_dbg_init, vha, 0x00ca,
1653 "Starting firmware.\n");
1da177e4 1654
e315cd28 1655 rval = qla2x00_execute_fw(vha, srisc_address);
1da177e4 1656 /* Retrieve firmware information. */
dda772e8 1657 if (rval == QLA_SUCCESS) {
a9083016 1658enable_82xx_npiv:
dda772e8 1659 fw_major_version = ha->fw_major_version;
7ec0effd 1660 if (IS_P3P_TYPE(ha))
3173167f 1661 qla82xx_check_md_needed(vha);
6246b8a1
GM		 1662 else
1663 rval = qla2x00_get_fw_version(vha);
ca9e9c3e
AV		 1664 if (rval != QLA_SUCCESS)
1665 goto failed;
2c3dfe3f 1666 ha->flags.npiv_supported = 0;
e315cd28 1667 if (IS_QLA2XXX_MIDTYPE(ha) &&
946fb891 1668 (ha->fw_attributes & BIT_2)) {
2c3dfe3f 1669 ha->flags.npiv_supported = 1;
4d0ea247
SJ		 1670 if ((!ha->max_npiv_vports) ||
1671 ((ha->max_npiv_vports + 1) %
eb66dc60 1672 MIN_MULTI_ID_FABRIC))
4d0ea247 1673 ha->max_npiv_vports =
eb66dc60 1674 MIN_MULTI_ID_FABRIC - 1;
4d0ea247 1675 }
24a08138 1676 qla2x00_get_resource_cnts(vha, NULL,
8d93f550 1677 &ha->fw_xcb_count, NULL, &ha->fw_iocb_count,
f3a0a77e 1678 &ha->max_npiv_vports, NULL);
d743de66 1679
8d93f550
CD		 1680 /*
1681 * Allocate the array of outstanding commands
1682 * now that we know the firmware resources.
1683 */
1684 rval = qla2x00_alloc_outstanding_cmds(ha,
1685 vha->req);
1686 if (rval != QLA_SUCCESS)
1687 goto failed;
1688
be5ea3cf 1689 if (!fw_major_version && ql2xallocfwdump
7ec0effd 1690 && !(IS_P3P_TYPE(ha)))
08de2844 1691 qla2x00_alloc_fw_dump(vha);
1da177e4
LT		 1692 }
1693 } else {
7c3df132
SK		 1694 ql_log(ql_log_fatal, vha, 0x00cd,
1695 "ISP Firmware failed checksum.\n");
1696 goto failed;
1da177e4 1697 }
c74d88a4
AV		 1698 } else
1699 goto failed;
1da177e4 1700
3db0652e
AV		 1701 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1702 /* Enable proper parity. */
1703 spin_lock_irqsave(&ha->hardware_lock, flags);
1704 if (IS_QLA2300(ha))
1705 /* SRAM parity */
1706 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x1);
1707 else
1708 /* SRAM, Instruction RAM and GP RAM parity */
1709 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x7);
1710 RD_REG_WORD(&reg->hccr);
1711 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1712 }
1713
6246b8a1
GM		 1714 if (IS_QLA83XX(ha))
1715 goto skip_fac_check;
1716
1d2874de
JC		 1717 if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
1718 uint32_t size;
1719
1720 rval = qla81xx_fac_get_sector_size(vha, &size);
1721 if (rval == QLA_SUCCESS) {
1722 ha->flags.fac_supported = 1;
1723 ha->fdt_block_size = size << 2;
1724 } else {
7c3df132 1725 ql_log(ql_log_warn, vha, 0x00ce,
1d2874de
JC		 1726 "Unsupported FAC firmware (%d.%02d.%02d).\n",
1727 ha->fw_major_version, ha->fw_minor_version,
1728 ha->fw_subminor_version);
6246b8a1
GM		 1729skip_fac_check:
1730 if (IS_QLA83XX(ha)) {
1731 ha->flags.fac_supported = 0;
1732 rval = QLA_SUCCESS;
1733 }
1d2874de
JC		 1734 }
1735 }
ca9e9c3e 1736failed:
1da177e4 1737 if (rval) {
7c3df132
SK		 1738 ql_log(ql_log_fatal, vha, 0x00cf,
1739 "Setup chip ****FAILED****.\n");
1da177e4
LT		 1740 }
1741
1742 return (rval);
1743}
1744
1745/**
1746 * qla2x00_init_response_q_entries() - Initializes response queue entries.
1747 * @ha: HA context
1748 *
1749 * Beginning of request ring has initialization control block already built
1750 * by nvram config routine.
1751 *
1752 * Returns 0 on success.
1753 */
73208dfd
AC		 1754void
1755qla2x00_init_response_q_entries(struct rsp_que *rsp)
1da177e4
LT		 1756{
1757 uint16_t cnt;
1758 response_t *pkt;
1759
2afa19a9
AC		 1760 rsp->ring_ptr = rsp->ring;
1761 rsp->ring_index = 0;
1762 rsp->status_srb = NULL;
e315cd28
AC		 1763 pkt = rsp->ring_ptr;
1764 for (cnt = 0; cnt < rsp->length; cnt++) {
1da177e4
LT		 1765 pkt->signature = RESPONSE_PROCESSED;
1766 pkt++;
1767 }
1da177e4
LT		 1768}
1769
1770/**
1771 * qla2x00_update_fw_options() - Read and process firmware options.
1772 * @ha: HA context
1773 *
1774 * Returns 0 on success.
1775 */
abbd8870 1776void
e315cd28 1777qla2x00_update_fw_options(scsi_qla_host_t *vha)
1da177e4
LT		 1778{
1779 uint16_t swing, emphasis, tx_sens, rx_sens;
e315cd28 1780 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 1781
1782 memset(ha->fw_options, 0, sizeof(ha->fw_options));
e315cd28 1783 qla2x00_get_fw_options(vha, ha->fw_options);
1da177e4
LT		 1784
1785 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1786 return;
1787
1788 /* Serial Link options. */
7c3df132
SK		 1789 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
1790 "Serial link options.\n");
1791 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
1792 (uint8_t *)&ha->fw_seriallink_options,
1793 sizeof(ha->fw_seriallink_options));
1da177e4
LT		 1794
1795 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1796 if (ha->fw_seriallink_options[3] & BIT_2) {
1797 ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING;
1798
1799 /* 1G settings */
1800 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
1801 emphasis = (ha->fw_seriallink_options[2] &
1802 (BIT_4 | BIT_3)) >> 3;
1803 tx_sens = ha->fw_seriallink_options[0] &
fa2a1ce5 1804 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 1805 rx_sens = (ha->fw_seriallink_options[0] &
1806 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
1807 ha->fw_options[10] = (emphasis << 14) | (swing << 8);
1808 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
1809 if (rx_sens == 0x0)
1810 rx_sens = 0x3;
1811 ha->fw_options[10] |= (tx_sens << 4) | rx_sens;
1812 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
1813 ha->fw_options[10] |= BIT_5 |
1814 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
1815 (tx_sens & (BIT_1 | BIT_0));
1816
1817 /* 2G settings */
1818 swing = (ha->fw_seriallink_options[2] &
1819 (BIT_7 | BIT_6 | BIT_5)) >> 5;
1820 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
1821 tx_sens = ha->fw_seriallink_options[1] &
fa2a1ce5 1822 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 1823 rx_sens = (ha->fw_seriallink_options[1] &
1824 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
1825 ha->fw_options[11] = (emphasis << 14) | (swing << 8);
1826 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
1827 if (rx_sens == 0x0)
1828 rx_sens = 0x3;
1829 ha->fw_options[11] |= (tx_sens << 4) | rx_sens;
1830 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
1831 ha->fw_options[11] |= BIT_5 |
1832 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
1833 (tx_sens & (BIT_1 | BIT_0));
1834 }
1835
1836 /* FCP2 options. */
1837 /* Return command IOCBs without waiting for an ABTS to complete. */
1838 ha->fw_options[3] |= BIT_13;
1839
1840 /* LED scheme. */
1841 if (ha->flags.enable_led_scheme)
1842 ha->fw_options[2] |= BIT_12;
1843
48c02fde
AV		 1844 /* Detect ISP6312. */
1845 if (IS_QLA6312(ha))
1846 ha->fw_options[2] |= BIT_13;
1847
1da177e4 1848 /* Update firmware options. */
e315cd28 1849 qla2x00_set_fw_options(vha, ha->fw_options);
1da177e4
LT		 1850}
1851
0107109e 1852void
e315cd28 1853qla24xx_update_fw_options(scsi_qla_host_t *vha)
0107109e
AV		 1854{
1855 int rval;
e315cd28 1856 struct qla_hw_data *ha = vha->hw;
0107109e 1857
7ec0effd 1858 if (IS_P3P_TYPE(ha))
a9083016
GM		 1859 return;
1860
0107109e 1861 /* Update Serial Link options. */
f94097ed 1862 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0)
0107109e
AV		 1863 return;
1864
e315cd28 1865 rval = qla2x00_set_serdes_params(vha,
f94097ed
AV		 1866 le16_to_cpu(ha->fw_seriallink_options24[1]),
1867 le16_to_cpu(ha->fw_seriallink_options24[2]),
1868 le16_to_cpu(ha->fw_seriallink_options24[3]));
0107109e 1869 if (rval != QLA_SUCCESS) {
7c3df132 1870 ql_log(ql_log_warn, vha, 0x0104,
0107109e
AV		 1871 "Unable to update Serial Link options (%x).\n", rval);
1872 }
1873}
1874
abbd8870 1875void
e315cd28 1876qla2x00_config_rings(struct scsi_qla_host *vha)
abbd8870 1877{
e315cd28 1878 struct qla_hw_data *ha = vha->hw;
3d71644c 1879 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
73208dfd
AC		 1880 struct req_que *req = ha->req_q_map[0];
1881 struct rsp_que *rsp = ha->rsp_q_map[0];
abbd8870
AV		 1882
1883 /* Setup ring parameters in initialization control block. */
1884 ha->init_cb->request_q_outpointer = __constant_cpu_to_le16(0);
1885 ha->init_cb->response_q_inpointer = __constant_cpu_to_le16(0);
e315cd28
AC		 1886 ha->init_cb->request_q_length = cpu_to_le16(req->length);
1887 ha->init_cb->response_q_length = cpu_to_le16(rsp->length);
1888 ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
1889 ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
1890 ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
1891 ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
abbd8870
AV		 1892
1893 WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0);
1894 WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0);
1895 WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0);
1896 WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0);
1897 RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */
1898}
1899
0107109e 1900void
e315cd28 1901qla24xx_config_rings(struct scsi_qla_host *vha)
0107109e 1902{
e315cd28 1903 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 1904 device_reg_t __iomem *reg = ISP_QUE_REG(ha, 0);
1905 struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
1906 struct qla_msix_entry *msix;
0107109e 1907 struct init_cb_24xx *icb;
73208dfd
AC		 1908 uint16_t rid = 0;
1909 struct req_que *req = ha->req_q_map[0];
1910 struct rsp_que *rsp = ha->rsp_q_map[0];
0107109e 1911
6246b8a1 1912 /* Setup ring parameters in initialization control block. */
0107109e
AV		 1913 icb = (struct init_cb_24xx *)ha->init_cb;
1914 icb->request_q_outpointer = __constant_cpu_to_le16(0);
1915 icb->response_q_inpointer = __constant_cpu_to_le16(0);
e315cd28
AC		 1916 icb->request_q_length = cpu_to_le16(req->length);
1917 icb->response_q_length = cpu_to_le16(rsp->length);
1918 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
1919 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
1920 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
1921 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
0107109e 1922
2d70c103
NB		 1923 /* Setup ATIO queue dma pointers for target mode */
1924 icb->atio_q_inpointer = __constant_cpu_to_le16(0);
1925 icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length);
1926 icb->atio_q_address[0] = cpu_to_le32(LSD(ha->tgt.atio_dma));
1927 icb->atio_q_address[1] = cpu_to_le32(MSD(ha->tgt.atio_dma));
1928
6246b8a1 1929 if (ha->mqenable || IS_QLA83XX(ha)) {
73208dfd
AC		 1930 icb->qos = __constant_cpu_to_le16(QLA_DEFAULT_QUE_QOS);
1931 icb->rid = __constant_cpu_to_le16(rid);
1932 if (ha->flags.msix_enabled) {
1933 msix = &ha->msix_entries[1];
7c3df132
SK		 1934 ql_dbg(ql_dbg_init, vha, 0x00fd,
1935 "Registering vector 0x%x for base que.\n",
1936 msix->entry);
73208dfd
AC		 1937 icb->msix = cpu_to_le16(msix->entry);
1938 }
1939 /* Use alternate PCI bus number */
1940 if (MSB(rid))
1941 icb->firmware_options_2 |=
1942 __constant_cpu_to_le32(BIT_19);
1943 /* Use alternate PCI devfn */
1944 if (LSB(rid))
1945 icb->firmware_options_2 |=
1946 __constant_cpu_to_le32(BIT_18);
1947
3155754a 1948 /* Use Disable MSIX Handshake mode for capable adapters */
6246b8a1
GM		 1949 if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) &&
1950 (ha->flags.msix_enabled)) {
3155754a
AC		 1951 icb->firmware_options_2 &=
1952 __constant_cpu_to_le32(~BIT_22);
1953 ha->flags.disable_msix_handshake = 1;
7c3df132
SK		 1954 ql_dbg(ql_dbg_init, vha, 0x00fe,
1955 "MSIX Handshake Disable Mode turned on.\n");
3155754a
AC		 1956 } else {
1957 icb->firmware_options_2 |=
1958 __constant_cpu_to_le32(BIT_22);
1959 }
73208dfd 1960 icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_23);
73208dfd
AC		 1961
1962 WRT_REG_DWORD(&reg->isp25mq.req_q_in, 0);
1963 WRT_REG_DWORD(&reg->isp25mq.req_q_out, 0);
1964 WRT_REG_DWORD(&reg->isp25mq.rsp_q_in, 0);
1965 WRT_REG_DWORD(&reg->isp25mq.rsp_q_out, 0);
1966 } else {
1967 WRT_REG_DWORD(&reg->isp24.req_q_in, 0);
1968 WRT_REG_DWORD(&reg->isp24.req_q_out, 0);
1969 WRT_REG_DWORD(&reg->isp24.rsp_q_in, 0);
1970 WRT_REG_DWORD(&reg->isp24.rsp_q_out, 0);
1971 }
aa230bc5 1972 qlt_24xx_config_rings(vha);
2d70c103 1973
73208dfd
AC		 1974 /* PCI posting */
1975 RD_REG_DWORD(&ioreg->hccr);
0107109e
AV		 1976}
1977
1da177e4
LT		 1978/**
1979 * qla2x00_init_rings() - Initializes firmware.
1980 * @ha: HA context
1981 *
1982 * Beginning of request ring has initialization control block already built
1983 * by nvram config routine.
1984 *
1985 * Returns 0 on success.
1986 */
8ae6d9c7 1987int
e315cd28 1988qla2x00_init_rings(scsi_qla_host_t *vha)
1da177e4
LT		 1989{
1990 int rval;
1991 unsigned long flags = 0;
29bdccbe 1992 int cnt, que;
e315cd28 1993 struct qla_hw_data *ha = vha->hw;
29bdccbe
AC		 1994 struct req_que *req;
1995 struct rsp_que *rsp;
2c3dfe3f
SJ		 1996 struct mid_init_cb_24xx *mid_init_cb =
1997 (struct mid_init_cb_24xx *) ha->init_cb;
1da177e4
LT		 1998
1999 spin_lock_irqsave(&ha->hardware_lock, flags);
2000
2001 /* Clear outstanding commands array. */
2afa19a9 2002 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe
AC		 2003 req = ha->req_q_map[que];
2004 if (!req)
2005 continue;
8d93f550 2006 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++)
29bdccbe 2007 req->outstanding_cmds[cnt] = NULL;
1da177e4 2008
2afa19a9 2009 req->current_outstanding_cmd = 1;
1da177e4 2010
29bdccbe
AC		 2011 /* Initialize firmware. */
2012 req->ring_ptr = req->ring;
2013 req->ring_index = 0;
2014 req->cnt = req->length;
2015 }
1da177e4 2016
2afa19a9 2017 for (que = 0; que < ha->max_rsp_queues; que++) {
29bdccbe
AC		 2018 rsp = ha->rsp_q_map[que];
2019 if (!rsp)
2020 continue;
29bdccbe 2021 /* Initialize response queue entries */
8ae6d9c7
GM		 2022 if (IS_QLAFX00(ha))
2023 qlafx00_init_response_q_entries(rsp);
2024 else
2025 qla2x00_init_response_q_entries(rsp);
29bdccbe 2026 }
1da177e4 2027
2d70c103
NB		 2028 ha->tgt.atio_ring_ptr = ha->tgt.atio_ring;
2029 ha->tgt.atio_ring_index = 0;
2030 /* Initialize ATIO queue entries */
2031 qlt_init_atio_q_entries(vha);
2032
e315cd28 2033 ha->isp_ops->config_rings(vha);
1da177e4
LT		 2034
2035 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2036
8ae6d9c7
GM		 2037 ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n");
2038
2039 if (IS_QLAFX00(ha)) {
2040 rval = qlafx00_init_firmware(vha, ha->init_cb_size);
2041 goto next_check;
2042 }
2043
1da177e4 2044 /* Update any ISP specific firmware options before initialization. */
e315cd28 2045 ha->isp_ops->update_fw_options(vha);
1da177e4 2046
605aa2bc 2047 if (ha->flags.npiv_supported) {
45980cc2 2048 if (ha->operating_mode == LOOP && !IS_CNA_CAPABLE(ha))
605aa2bc 2049 ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
c48339de 2050 mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
605aa2bc
LC		 2051 }
2052
24a08138
AV		 2053 if (IS_FWI2_CAPABLE(ha)) {
2054 mid_init_cb->options = __constant_cpu_to_le16(BIT_1);
2055 mid_init_cb->init_cb.execution_throttle =
2056 cpu_to_le16(ha->fw_xcb_count);
2057 }
2c3dfe3f 2058
e315cd28 2059 rval = qla2x00_init_firmware(vha, ha->init_cb_size);
8ae6d9c7 2060next_check:
1da177e4 2061 if (rval) {
7c3df132
SK		 2062 ql_log(ql_log_fatal, vha, 0x00d2,
2063 "Init Firmware **** FAILED ****.\n");
1da177e4 2064 } else {
7c3df132
SK		 2065 ql_dbg(ql_dbg_init, vha, 0x00d3,
2066 "Init Firmware -- success.\n");
1da177e4
LT		 2067 }
2068
2069 return (rval);
2070}
2071
2072/**
2073 * qla2x00_fw_ready() - Waits for firmware ready.
2074 * @ha: HA context
2075 *
2076 * Returns 0 on success.
2077 */
2078static int
e315cd28 2079qla2x00_fw_ready(scsi_qla_host_t *vha)
1da177e4
LT		 2080{
2081 int rval;
4d4df193 2082 unsigned long wtime, mtime, cs84xx_time;
1da177e4
LT		 2083 uint16_t min_wait; /* Minimum wait time if loop is down */
2084 uint16_t wait_time; /* Wait time if loop is coming ready */
656e8912 2085 uint16_t state[5];
e315cd28 2086 struct qla_hw_data *ha = vha->hw;
1da177e4 2087
8ae6d9c7
GM		 2088 if (IS_QLAFX00(vha->hw))
2089 return qlafx00_fw_ready(vha);
2090
1da177e4
LT		 2091 rval = QLA_SUCCESS;
2092
2093 /* 20 seconds for loop down. */
fa2a1ce5 2094 min_wait = 20;
1da177e4
LT		 2095
2096 /*
2097 * Firmware should take at most one RATOV to login, plus 5 seconds for
2098 * our own processing.
2099 */
2100 if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) {
2101 wait_time = min_wait;
2102 }
2103
2104 /* Min wait time if loop down */
2105 mtime = jiffies + (min_wait * HZ);
2106
2107 /* wait time before firmware ready */
2108 wtime = jiffies + (wait_time * HZ);
2109
2110 /* Wait for ISP to finish LIP */
e315cd28 2111 if (!vha->flags.init_done)
7c3df132
SK		 2112 ql_log(ql_log_info, vha, 0x801e,
2113 "Waiting for LIP to complete.\n");
1da177e4
LT		 2114
2115 do {
5b939038 2116 memset(state, -1, sizeof(state));
e315cd28 2117 rval = qla2x00_get_firmware_state(vha, state);
1da177e4 2118 if (rval == QLA_SUCCESS) {
4d4df193 2119 if (state[0] < FSTATE_LOSS_OF_SYNC) {
e315cd28 2120 vha->device_flags &= ~DFLG_NO_CABLE;
1da177e4 2121 }
4d4df193 2122 if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) {
7c3df132
SK		 2123 ql_dbg(ql_dbg_taskm, vha, 0x801f,
2124 "fw_state=%x 84xx=%x.\n", state[0],
2125 state[2]);
4d4df193
HK		 2126 if ((state[2] & FSTATE_LOGGED_IN) &&
2127 (state[2] & FSTATE_WAITING_FOR_VERIFY)) {
7c3df132
SK		 2128 ql_dbg(ql_dbg_taskm, vha, 0x8028,
2129 "Sending verify iocb.\n");
4d4df193
HK		 2130
2131 cs84xx_time = jiffies;
e315cd28 2132 rval = qla84xx_init_chip(vha);
7c3df132
SK		 2133 if (rval != QLA_SUCCESS) {
2134 ql_log(ql_log_warn,
cfb0919c 2135 vha, 0x8007,
7c3df132 2136 "Init chip failed.\n");
4d4df193 2137 break;
7c3df132 2138 }
4d4df193
HK		 2139
2140 /* Add time taken to initialize. */
2141 cs84xx_time = jiffies - cs84xx_time;
2142 wtime += cs84xx_time;
2143 mtime += cs84xx_time;
cfb0919c 2144 ql_dbg(ql_dbg_taskm, vha, 0x8008,
7c3df132
SK		 2145 "Increasing wait time by %ld. "
2146 "New time %ld.\n", cs84xx_time,
2147 wtime);
4d4df193
HK		 2148 }
2149 } else if (state[0] == FSTATE_READY) {
7c3df132
SK		 2150 ql_dbg(ql_dbg_taskm, vha, 0x8037,
2151 "F/W Ready - OK.\n");
1da177e4 2152
e315cd28 2153 qla2x00_get_retry_cnt(vha, &ha->retry_count,
1da177e4
LT		 2154 &ha->login_timeout, &ha->r_a_tov);
2155
2156 rval = QLA_SUCCESS;
2157 break;
2158 }
2159
2160 rval = QLA_FUNCTION_FAILED;
2161
e315cd28 2162 if (atomic_read(&vha->loop_down_timer) &&
4d4df193 2163 state[0] != FSTATE_READY) {
1da177e4 2164 /* Loop down. Timeout on min_wait for states
fa2a1ce5
AV		 2165 * other than Wait for Login.
2166 */
1da177e4 2167 if (time_after_eq(jiffies, mtime)) {
7c3df132 2168 ql_log(ql_log_info, vha, 0x8038,
1da177e4
LT		 2169 "Cable is unplugged...\n");
2170
e315cd28 2171 vha->device_flags |= DFLG_NO_CABLE;
1da177e4
LT		 2172 break;
2173 }
2174 }
2175 } else {
2176 /* Mailbox cmd failed. Timeout on min_wait. */
cdbb0a4f 2177 if (time_after_eq(jiffies, mtime) ||
7190575f 2178 ha->flags.isp82xx_fw_hung)
1da177e4
LT		 2179 break;
2180 }
2181
2182 if (time_after_eq(jiffies, wtime))
2183 break;
2184
2185 /* Delay for a while */
2186 msleep(500);
1da177e4
LT		 2187 } while (1);
2188
7c3df132
SK		 2189 ql_dbg(ql_dbg_taskm, vha, 0x803a,
2190 "fw_state=%x (%x, %x, %x, %x) " "curr time=%lx.\n", state[0],
2191 state[1], state[2], state[3], state[4], jiffies);
1da177e4 2192
cfb0919c 2193 if (rval && !(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132
SK		 2194 ql_log(ql_log_warn, vha, 0x803b,
2195 "Firmware ready **** FAILED ****.\n");
1da177e4
LT		 2196 }
2197
2198 return (rval);
2199}
2200
2201/*
2202* qla2x00_configure_hba
2203* Setup adapter context.
2204*
2205* Input:
2206* ha = adapter state pointer.
2207*
2208* Returns:
2209* 0 = success
2210*
2211* Context:
2212* Kernel context.
2213*/
2214static int
e315cd28 2215qla2x00_configure_hba(scsi_qla_host_t *vha)
1da177e4
LT		 2216{
2217 int rval;
2218 uint16_t loop_id;
2219 uint16_t topo;
2c3dfe3f 2220 uint16_t sw_cap;
1da177e4
LT		 2221 uint8_t al_pa;
2222 uint8_t area;
2223 uint8_t domain;
2224 char connect_type[22];
e315cd28 2225 struct qla_hw_data *ha = vha->hw;
f24b5cb8 2226 unsigned long flags;
61e1b269 2227 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 2228
2229 /* Get host addresses. */
e315cd28 2230 rval = qla2x00_get_adapter_id(vha,
2c3dfe3f 2231 &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
1da177e4 2232 if (rval != QLA_SUCCESS) {
e315cd28 2233 if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
6246b8a1 2234 IS_CNA_CAPABLE(ha) ||
33135aa2 2235 (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
7c3df132
SK		 2236 ql_dbg(ql_dbg_disc, vha, 0x2008,
2237 "Loop is in a transition state.\n");
33135aa2 2238 } else {
7c3df132
SK		 2239 ql_log(ql_log_warn, vha, 0x2009,
2240 "Unable to get host loop ID.\n");
61e1b269
JC		 2241 if (IS_FWI2_CAPABLE(ha) && (vha == base_vha) &&
2242 (rval == QLA_COMMAND_ERROR && loop_id == 0x1b)) {
2243 ql_log(ql_log_warn, vha, 0x1151,
2244 "Doing link init.\n");
2245 if (qla24xx_link_initialize(vha) == QLA_SUCCESS)
2246 return rval;
2247 }
e315cd28 2248 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
33135aa2 2249 }
1da177e4
LT		 2250 return (rval);
2251 }
2252
2253 if (topo == 4) {
7c3df132
SK		 2254 ql_log(ql_log_info, vha, 0x200a,
2255 "Cannot get topology - retrying.\n");
1da177e4
LT		 2256 return (QLA_FUNCTION_FAILED);
2257 }
2258
e315cd28 2259 vha->loop_id = loop_id;
1da177e4
LT		 2260
2261 /* initialize */
2262 ha->min_external_loopid = SNS_FIRST_LOOP_ID;
2263 ha->operating_mode = LOOP;
2c3dfe3f 2264 ha->switch_cap = 0;
1da177e4
LT		 2265
2266 switch (topo) {
2267 case 0:
7c3df132 2268 ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n");
1da177e4
LT		 2269 ha->current_topology = ISP_CFG_NL;
2270 strcpy(connect_type, "(Loop)");
2271 break;
2272
2273 case 1:
7c3df132 2274 ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n");
2c3dfe3f 2275 ha->switch_cap = sw_cap;
1da177e4
LT		 2276 ha->current_topology = ISP_CFG_FL;
2277 strcpy(connect_type, "(FL_Port)");
2278 break;
2279
2280 case 2:
7c3df132 2281 ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n");
1da177e4
LT		 2282 ha->operating_mode = P2P;
2283 ha->current_topology = ISP_CFG_N;
2284 strcpy(connect_type, "(N_Port-to-N_Port)");
2285 break;
2286
2287 case 3:
7c3df132 2288 ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n");
2c3dfe3f 2289 ha->switch_cap = sw_cap;
1da177e4
LT		 2290 ha->operating_mode = P2P;
2291 ha->current_topology = ISP_CFG_F;
2292 strcpy(connect_type, "(F_Port)");
2293 break;
2294
2295 default:
7c3df132
SK		 2296 ql_dbg(ql_dbg_disc, vha, 0x200f,
2297 "HBA in unknown topology %x, using NL.\n", topo);
1da177e4
LT		 2298 ha->current_topology = ISP_CFG_NL;
2299 strcpy(connect_type, "(Loop)");
2300 break;
2301 }
2302
2303 /* Save Host port and loop ID. */
2304 /* byte order - Big Endian */
e315cd28
AC		 2305 vha->d_id.b.domain = domain;
2306 vha->d_id.b.area = area;
2307 vha->d_id.b.al_pa = al_pa;
1da177e4 2308
f24b5cb8 2309 spin_lock_irqsave(&ha->vport_slock, flags);
2d70c103 2310 qlt_update_vp_map(vha, SET_AL_PA);
f24b5cb8 2311 spin_unlock_irqrestore(&ha->vport_slock, flags);
2d70c103 2312
e315cd28 2313 if (!vha->flags.init_done)
7c3df132
SK		 2314 ql_log(ql_log_info, vha, 0x2010,
2315 "Topology - %s, Host Loop address 0x%x.\n",
e315cd28 2316 connect_type, vha->loop_id);
1da177e4 2317
1da177e4
LT		 2318 return(rval);
2319}
2320
a9083016 2321inline void
e315cd28
AC		 2322qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
2323 char *def)
9bb9fcf2
AV		 2324{
2325 char *st, *en;
2326 uint16_t index;
e315cd28 2327 struct qla_hw_data *ha = vha->hw;
ab671149 2328 int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
6246b8a1 2329 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha);
9bb9fcf2
AV		 2330
2331 if (memcmp(model, BINZERO, len) != 0) {
2332 strncpy(ha->model_number, model, len);
2333 st = en = ha->model_number;
2334 en += len - 1;
2335 while (en > st) {
2336 if (*en != 0x20 && *en != 0x00)
2337 break;
2338 *en-- = '\0';
2339 }
2340
2341 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 2342 if (use_tbl &&
2343 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2 2344 index < QLA_MODEL_NAMES)
1ee27146
JC		 2345 strncpy(ha->model_desc,
2346 qla2x00_model_name[index * 2 + 1],
2347 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 2348 } else {
2349 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 2350 if (use_tbl &&
2351 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2
AV		 2352 index < QLA_MODEL_NAMES) {
2353 strcpy(ha->model_number,
2354 qla2x00_model_name[index * 2]);
1ee27146
JC		 2355 strncpy(ha->model_desc,
2356 qla2x00_model_name[index * 2 + 1],
2357 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 2358 } else {
2359 strcpy(ha->model_number, def);
2360 }
2361 }
1ee27146 2362 if (IS_FWI2_CAPABLE(ha))
e315cd28 2363 qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc,
1ee27146 2364 sizeof(ha->model_desc));
9bb9fcf2
AV		 2365}
2366
4e08df3f
DM		 2367/* On sparc systems, obtain port and node WWN from firmware
2368 * properties.
2369 */
e315cd28 2370static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv)
4e08df3f
DM		 2371{
2372#ifdef CONFIG_SPARC
e315cd28 2373 struct qla_hw_data *ha = vha->hw;
4e08df3f 2374 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 2375 struct device_node *dp = pci_device_to_OF_node(pdev);
2376 const u8 *val;
4e08df3f
DM		 2377 int len;
2378
2379 val = of_get_property(dp, "port-wwn", &len);
2380 if (val && len >= WWN_SIZE)
2381 memcpy(nv->port_name, val, WWN_SIZE);
2382
2383 val = of_get_property(dp, "node-wwn", &len);
2384 if (val && len >= WWN_SIZE)
2385 memcpy(nv->node_name, val, WWN_SIZE);
2386#endif
2387}
2388
1da177e4
LT		 2389/*
2390* NVRAM configuration for ISP 2xxx
2391*
2392* Input:
2393* ha = adapter block pointer.
2394*
2395* Output:
2396* initialization control block in response_ring
2397* host adapters parameters in host adapter block
2398*
2399* Returns:
2400* 0 = success.
2401*/
abbd8870 2402int
e315cd28 2403qla2x00_nvram_config(scsi_qla_host_t *vha)
1da177e4 2404{
4e08df3f 2405 int rval;
0107109e
AV		 2406 uint8_t chksum = 0;
2407 uint16_t cnt;
2408 uint8_t *dptr1, *dptr2;
e315cd28 2409 struct qla_hw_data *ha = vha->hw;
0107109e 2410 init_cb_t *icb = ha->init_cb;
281afe19
SJ		 2411 nvram_t *nv = ha->nvram;
2412 uint8_t *ptr = ha->nvram;
3d71644c 2413 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 2414
4e08df3f
DM		 2415 rval = QLA_SUCCESS;
2416
1da177e4 2417 /* Determine NVRAM starting address. */
0107109e 2418 ha->nvram_size = sizeof(nvram_t);
1da177e4
LT		 2419 ha->nvram_base = 0;
2420 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
2421 if ((RD_REG_WORD(&reg->ctrl_status) >> 14) == 1)
2422 ha->nvram_base = 0x80;
2423
2424 /* Get NVRAM data and calculate checksum. */
e315cd28 2425 ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size);
0107109e
AV		 2426 for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++)
2427 chksum += *ptr++;
1da177e4 2428
7c3df132
SK		 2429 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
2430 "Contents of NVRAM.\n");
2431 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
2432 (uint8_t *)nv, ha->nvram_size);
1da177e4
LT		 2433
2434 /* Bad NVRAM data, set defaults parameters. */
2435 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' ||
2436 nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) {
2437 /* Reset NVRAM data. */
7c3df132 2438 ql_log(ql_log_warn, vha, 0x0064,
9e336520 2439 "Inconsistent NVRAM "
7c3df132
SK		 2440 "detected: checksum=0x%x id=%c version=0x%x.\n",
2441 chksum, nv->id[0], nv->nvram_version);
2442 ql_log(ql_log_warn, vha, 0x0065,
2443 "Falling back to "
2444 "functioning (yet invalid -- WWPN) defaults.\n");
4e08df3f
DM		 2445
2446 /*
2447 * Set default initialization control block.
2448 */
2449 memset(nv, 0, ha->nvram_size);
2450 nv->parameter_block_version = ICB_VERSION;
2451
2452 if (IS_QLA23XX(ha)) {
2453 nv->firmware_options[0] = BIT_2 | BIT_1;
2454 nv->firmware_options[1] = BIT_7 | BIT_5;
2455 nv->add_firmware_options[0] = BIT_5;
2456 nv->add_firmware_options[1] = BIT_5 | BIT_4;
2457 nv->frame_payload_size = __constant_cpu_to_le16(2048);
2458 nv->special_options[1] = BIT_7;
2459 } else if (IS_QLA2200(ha)) {
2460 nv->firmware_options[0] = BIT_2 | BIT_1;
2461 nv->firmware_options[1] = BIT_7 | BIT_5;
2462 nv->add_firmware_options[0] = BIT_5;
2463 nv->add_firmware_options[1] = BIT_5 | BIT_4;
2464 nv->frame_payload_size = __constant_cpu_to_le16(1024);
2465 } else if (IS_QLA2100(ha)) {
2466 nv->firmware_options[0] = BIT_3 | BIT_1;
2467 nv->firmware_options[1] = BIT_5;
2468 nv->frame_payload_size = __constant_cpu_to_le16(1024);
2469 }
2470
2471 nv->max_iocb_allocation = __constant_cpu_to_le16(256);
2472 nv->execution_throttle = __constant_cpu_to_le16(16);
2473 nv->retry_count = 8;
2474 nv->retry_delay = 1;
2475
2476 nv->port_name[0] = 33;
2477 nv->port_name[3] = 224;
2478 nv->port_name[4] = 139;
2479
e315cd28 2480 qla2xxx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 2481
2482 nv->login_timeout = 4;
2483
2484 /*
2485 * Set default host adapter parameters
2486 */
2487 nv->host_p[1] = BIT_2;
2488 nv->reset_delay = 5;
2489 nv->port_down_retry_count = 8;
2490 nv->max_luns_per_target = __constant_cpu_to_le16(8);
2491 nv->link_down_timeout = 60;
2492
2493 rval = 1;
1da177e4
LT		 2494 }
2495
2496#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
2497 /*
2498 * The SN2 does not provide BIOS emulation which means you can't change
2499 * potentially bogus BIOS settings. Force the use of default settings
2500 * for link rate and frame size. Hope that the rest of the settings
2501 * are valid.
2502 */
2503 if (ia64_platform_is("sn2")) {
2504 nv->frame_payload_size = __constant_cpu_to_le16(2048);
2505 if (IS_QLA23XX(ha))
2506 nv->special_options[1] = BIT_7;
2507 }
2508#endif
2509
2510 /* Reset Initialization control block */
0107109e 2511 memset(icb, 0, ha->init_cb_size);
1da177e4
LT		 2512
2513 /*
2514 * Setup driver NVRAM options.
2515 */
2516 nv->firmware_options[0] |= (BIT_6 | BIT_1);
2517 nv->firmware_options[0] &= ~(BIT_5 | BIT_4);
2518 nv->firmware_options[1] |= (BIT_5 | BIT_0);
2519 nv->firmware_options[1] &= ~BIT_4;
2520
2521 if (IS_QLA23XX(ha)) {
2522 nv->firmware_options[0] |= BIT_2;
2523 nv->firmware_options[0] &= ~BIT_3;
2d70c103 2524 nv->special_options[0] &= ~BIT_6;
0107109e 2525 nv->add_firmware_options[1] |= BIT_5 | BIT_4;
1da177e4
LT		 2526
2527 if (IS_QLA2300(ha)) {
2528 if (ha->fb_rev == FPM_2310) {
2529 strcpy(ha->model_number, "QLA2310");
2530 } else {
2531 strcpy(ha->model_number, "QLA2300");
2532 }
2533 } else {
e315cd28 2534 qla2x00_set_model_info(vha, nv->model_number,
9bb9fcf2 2535 sizeof(nv->model_number), "QLA23xx");
1da177e4
LT		 2536 }
2537 } else if (IS_QLA2200(ha)) {
2538 nv->firmware_options[0] |= BIT_2;
2539 /*
2540 * 'Point-to-point preferred, else loop' is not a safe
2541 * connection mode setting.
2542 */
2543 if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
2544 (BIT_5 | BIT_4)) {
2545 /* Force 'loop preferred, else point-to-point'. */
2546 nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
2547 nv->add_firmware_options[0] |= BIT_5;
2548 }
2549 strcpy(ha->model_number, "QLA22xx");
2550 } else /*if (IS_QLA2100(ha))*/ {
2551 strcpy(ha->model_number, "QLA2100");
2552 }
2553
2554 /*
2555 * Copy over NVRAM RISC parameter block to initialization control block.
2556 */
2557 dptr1 = (uint8_t *)icb;
2558 dptr2 = (uint8_t *)&nv->parameter_block_version;
2559 cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;
2560 while (cnt--)
2561 *dptr1++ = *dptr2++;
2562
2563 /* Copy 2nd half. */
2564 dptr1 = (uint8_t *)icb->add_firmware_options;
2565 cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;
2566 while (cnt--)
2567 *dptr1++ = *dptr2++;
2568
5341e868
AV		 2569 /* Use alternate WWN? */
2570 if (nv->host_p[1] & BIT_7) {
2571 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
2572 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
2573 }
2574
1da177e4
LT		 2575 /* Prepare nodename */
2576 if ((icb->firmware_options[1] & BIT_6) == 0) {
2577 /*
2578 * Firmware will apply the following mask if the nodename was
2579 * not provided.
2580 */
2581 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
2582 icb->node_name[0] &= 0xF0;
2583 }
2584
2585 /*
2586 * Set host adapter parameters.
2587 */
3ce8866c
SK		 2588
2589 /*
2590 * BIT_7 in the host-parameters section allows for modification to
2591 * internal driver logging.
2592 */
0181944f 2593 if (nv->host_p[0] & BIT_7)
cfb0919c 2594 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
1da177e4
LT		 2595 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
2596 /* Always load RISC code on non ISP2[12]00 chips. */
2597 if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
2598 ha->flags.disable_risc_code_load = 0;
2599 ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0);
2600 ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
2601 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
06c22bd1 2602 ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
d4c760c2 2603 ha->flags.disable_serdes = 0;
1da177e4
LT		 2604
2605 ha->operating_mode =
2606 (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
2607
2608 memcpy(ha->fw_seriallink_options, nv->seriallink_options,
2609 sizeof(ha->fw_seriallink_options));
2610
2611 /* save HBA serial number */
2612 ha->serial0 = icb->port_name[5];
2613 ha->serial1 = icb->port_name[6];
2614 ha->serial2 = icb->port_name[7];
e315cd28
AC		 2615 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
2616 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
1da177e4
LT		 2617
2618 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
2619
2620 ha->retry_count = nv->retry_count;
2621
2622 /* Set minimum login_timeout to 4 seconds. */
5b91490e 2623 if (nv->login_timeout != ql2xlogintimeout)
1da177e4
LT		 2624 nv->login_timeout = ql2xlogintimeout;
2625 if (nv->login_timeout < 4)
2626 nv->login_timeout = 4;
2627 ha->login_timeout = nv->login_timeout;
2628 icb->login_timeout = nv->login_timeout;
2629
00a537b8
AV		 2630 /* Set minimum RATOV to 100 tenths of a second. */
2631 ha->r_a_tov = 100;
1da177e4 2632
1da177e4
LT		 2633 ha->loop_reset_delay = nv->reset_delay;
2634
1da177e4
LT		 2635 /* Link Down Timeout = 0:
2636 *
2637 * When Port Down timer expires we will start returning
2638 * I/O's to OS with "DID_NO_CONNECT".
2639 *
2640 * Link Down Timeout != 0:
2641 *
2642 * The driver waits for the link to come up after link down
2643 * before returning I/Os to OS with "DID_NO_CONNECT".
fa2a1ce5 2644 */
1da177e4
LT		 2645 if (nv->link_down_timeout == 0) {
2646 ha->loop_down_abort_time =
354d6b21 2647 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
1da177e4
LT		 2648 } else {
2649 ha->link_down_timeout = nv->link_down_timeout;
2650 ha->loop_down_abort_time =
2651 (LOOP_DOWN_TIME - ha->link_down_timeout);
fa2a1ce5 2652 }
1da177e4 2653
1da177e4
LT		 2654 /*
2655 * Need enough time to try and get the port back.
2656 */
2657 ha->port_down_retry_count = nv->port_down_retry_count;
2658 if (qlport_down_retry)
2659 ha->port_down_retry_count = qlport_down_retry;
2660 /* Set login_retry_count */
2661 ha->login_retry_count = nv->retry_count;
2662 if (ha->port_down_retry_count == nv->port_down_retry_count &&
2663 ha->port_down_retry_count > 3)
2664 ha->login_retry_count = ha->port_down_retry_count;
2665 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
2666 ha->login_retry_count = ha->port_down_retry_count;
2667 if (ql2xloginretrycount)
2668 ha->login_retry_count = ql2xloginretrycount;
2669
1da177e4
LT		 2670 icb->lun_enables = __constant_cpu_to_le16(0);
2671 icb->command_resource_count = 0;
2672 icb->immediate_notify_resource_count = 0;
2673 icb->timeout = __constant_cpu_to_le16(0);
2674
2675 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
2676 /* Enable RIO */
2677 icb->firmware_options[0] &= ~BIT_3;
2678 icb->add_firmware_options[0] &=
2679 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
2680 icb->add_firmware_options[0] |= BIT_2;
2681 icb->response_accumulation_timer = 3;
2682 icb->interrupt_delay_timer = 5;
2683
e315cd28 2684 vha->flags.process_response_queue = 1;
1da177e4 2685 } else {
4fdfefe5 2686 /* Enable ZIO. */
e315cd28 2687 if (!vha->flags.init_done) {
4fdfefe5
AV		 2688 ha->zio_mode = icb->add_firmware_options[0] &
2689 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
2690 ha->zio_timer = icb->interrupt_delay_timer ?
2691 icb->interrupt_delay_timer: 2;
2692 }
1da177e4
LT		 2693 icb->add_firmware_options[0] &=
2694 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
e315cd28 2695 vha->flags.process_response_queue = 0;
4fdfefe5 2696 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d
AV		 2697 ha->zio_mode = QLA_ZIO_MODE_6;
2698
7c3df132 2699 ql_log(ql_log_info, vha, 0x0068,
4fdfefe5
AV		 2700 "ZIO mode %d enabled; timer delay (%d us).\n",
2701 ha->zio_mode, ha->zio_timer * 100);
1da177e4 2702
4fdfefe5
AV		 2703 icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;
2704 icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;
e315cd28 2705 vha->flags.process_response_queue = 1;
1da177e4
LT		 2706 }
2707 }
2708
4e08df3f 2709 if (rval) {
7c3df132
SK		 2710 ql_log(ql_log_warn, vha, 0x0069,
2711 "NVRAM configuration failed.\n");
4e08df3f
DM		 2712 }
2713 return (rval);
1da177e4
LT		 2714}
2715
19a7b4ae
JSEC		 2716static void
2717qla2x00_rport_del(void *data)
2718{
2719 fc_port_t *fcport = data;
d97994dc 2720 struct fc_rport *rport;
2d70c103 2721 scsi_qla_host_t *vha = fcport->vha;
044d78e1 2722 unsigned long flags;
d97994dc 2723
044d78e1 2724 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
ac280b67 2725 rport = fcport->drport ? fcport->drport: fcport->rport;
d97994dc 2726 fcport->drport = NULL;
044d78e1 2727 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
2d70c103 2728 if (rport) {
d97994dc 2729 fc_remote_port_delete(rport);
2d70c103
NB		 2730 /*
2731 * Release the target mode FC NEXUS in qla_target.c code
2732 * if target mod is enabled.
2733 */
2734 qlt_fc_port_deleted(vha, fcport);
2735 }
19a7b4ae
JSEC		 2736}
2737
1da177e4
LT		 2738/**
2739 * qla2x00_alloc_fcport() - Allocate a generic fcport.
2740 * @ha: HA context
2741 * @flags: allocation flags
2742 *
2743 * Returns a pointer to the allocated fcport, or NULL, if none available.
2744 */
9a069e19 2745fc_port_t *
e315cd28 2746qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags)
1da177e4
LT		 2747{
2748 fc_port_t *fcport;
2749
bbfbbbc1
MK		 2750 fcport = kzalloc(sizeof(fc_port_t), flags);
2751 if (!fcport)
2752 return NULL;
1da177e4
LT		 2753
2754 /* Setup fcport template structure. */
e315cd28 2755 fcport->vha = vha;
1da177e4
LT		 2756 fcport->port_type = FCT_UNKNOWN;
2757 fcport->loop_id = FC_NO_LOOP_ID;
ec426e10 2758 qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
ad3e0eda 2759 fcport->supported_classes = FC_COS_UNSPECIFIED;
1da177e4 2760
bbfbbbc1 2761 return fcport;
1da177e4
LT		 2762}
2763
2764/*
2765 * qla2x00_configure_loop
2766 * Updates Fibre Channel Device Database with what is actually on loop.
2767 *
2768 * Input:
2769 * ha = adapter block pointer.
2770 *
2771 * Returns:
2772 * 0 = success.
2773 * 1 = error.
2774 * 2 = database was full and device was not configured.
2775 */
2776static int
e315cd28 2777qla2x00_configure_loop(scsi_qla_host_t *vha)
1da177e4
LT		 2778{
2779 int rval;
2780 unsigned long flags, save_flags;
e315cd28 2781 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2782 rval = QLA_SUCCESS;
2783
2784 /* Get Initiator ID */
e315cd28
AC		 2785 if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) {
2786 rval = qla2x00_configure_hba(vha);
1da177e4 2787 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2788 ql_dbg(ql_dbg_disc, vha, 0x2013,
2789 "Unable to configure HBA.\n");
1da177e4
LT		 2790 return (rval);
2791 }
2792 }
2793
e315cd28 2794 save_flags = flags = vha->dpc_flags;
7c3df132
SK		 2795 ql_dbg(ql_dbg_disc, vha, 0x2014,
2796 "Configure loop -- dpc flags = 0x%lx.\n", flags);
1da177e4
LT		 2797
2798 /*
2799 * If we have both an RSCN and PORT UPDATE pending then handle them
2800 * both at the same time.
2801 */
e315cd28
AC		 2802 clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2803 clear_bit(RSCN_UPDATE, &vha->dpc_flags);
1da177e4 2804
3064ff39
MH		 2805 qla2x00_get_data_rate(vha);
2806
1da177e4
LT		 2807 /* Determine what we need to do */
2808 if (ha->current_topology == ISP_CFG_FL &&
2809 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
2810
1da177e4
LT		 2811 set_bit(RSCN_UPDATE, &flags);
2812
2813 } else if (ha->current_topology == ISP_CFG_F &&
2814 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
2815
1da177e4
LT		 2816 set_bit(RSCN_UPDATE, &flags);
2817 clear_bit(LOCAL_LOOP_UPDATE, &flags);
21333b48
AV		 2818
2819 } else if (ha->current_topology == ISP_CFG_N) {
2820 clear_bit(RSCN_UPDATE, &flags);
1da177e4 2821
e315cd28 2822 } else if (!vha->flags.online ||
1da177e4
LT		 2823 (test_bit(ABORT_ISP_ACTIVE, &flags))) {
2824
1da177e4
LT		 2825 set_bit(RSCN_UPDATE, &flags);
2826 set_bit(LOCAL_LOOP_UPDATE, &flags);
2827 }
2828
2829 if (test_bit(LOCAL_LOOP_UPDATE, &flags)) {
7c3df132
SK		 2830 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
2831 ql_dbg(ql_dbg_disc, vha, 0x2015,
2832 "Loop resync needed, failing.\n");
1da177e4 2833 rval = QLA_FUNCTION_FAILED;
642ef983 2834 } else
e315cd28 2835 rval = qla2x00_configure_local_loop(vha);
1da177e4
LT		 2836 }
2837
2838 if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
7c3df132
SK		 2839 if (LOOP_TRANSITION(vha)) {
2840 ql_dbg(ql_dbg_disc, vha, 0x201e,
2841 "Needs RSCN update and loop transition.\n");
1da177e4 2842 rval = QLA_FUNCTION_FAILED;
7c3df132 2843 }
e315cd28
AC		 2844 else
2845 rval = qla2x00_configure_fabric(vha);
1da177e4
LT		 2846 }
2847
2848 if (rval == QLA_SUCCESS) {
e315cd28
AC		 2849 if (atomic_read(&vha->loop_down_timer) ||
2850 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4
LT		 2851 rval = QLA_FUNCTION_FAILED;
2852 } else {
e315cd28 2853 atomic_set(&vha->loop_state, LOOP_READY);
7c3df132
SK		 2854 ql_dbg(ql_dbg_disc, vha, 0x2069,
2855 "LOOP READY.\n");
1da177e4
LT		 2856 }
2857 }
2858
2859 if (rval) {
7c3df132
SK		 2860 ql_dbg(ql_dbg_disc, vha, 0x206a,
2861 "%s *** FAILED ***.\n", __func__);
1da177e4 2862 } else {
7c3df132
SK		 2863 ql_dbg(ql_dbg_disc, vha, 0x206b,
2864 "%s: exiting normally.\n", __func__);
1da177e4
LT		 2865 }
2866
cc3ef7bc 2867 /* Restore state if a resync event occurred during processing */
e315cd28 2868 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4 2869 if (test_bit(LOCAL_LOOP_UPDATE, &save_flags))
e315cd28 2870 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
f4658b6c 2871 if (test_bit(RSCN_UPDATE, &save_flags)) {
e315cd28 2872 set_bit(RSCN_UPDATE, &vha->dpc_flags);
f4658b6c 2873 }
1da177e4
LT		 2874 }
2875
2876 return (rval);
2877}
2878
2879
2880
2881/*
2882 * qla2x00_configure_local_loop
2883 * Updates Fibre Channel Device Database with local loop devices.
2884 *
2885 * Input:
2886 * ha = adapter block pointer.
2887 *
2888 * Returns:
2889 * 0 = success.
2890 */
2891static int
e315cd28 2892qla2x00_configure_local_loop(scsi_qla_host_t *vha)
1da177e4
LT		 2893{
2894 int rval, rval2;
2895 int found_devs;
2896 int found;
2897 fc_port_t *fcport, *new_fcport;
2898
2899 uint16_t index;
2900 uint16_t entries;
2901 char *id_iter;
2902 uint16_t loop_id;
2903 uint8_t domain, area, al_pa;
e315cd28 2904 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2905
2906 found_devs = 0;
2907 new_fcport = NULL;
642ef983 2908 entries = MAX_FIBRE_DEVICES_LOOP;
1da177e4 2909
1da177e4 2910 /* Get list of logged in devices. */
642ef983 2911 memset(ha->gid_list, 0, qla2x00_gid_list_size(ha));
e315cd28 2912 rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma,
1da177e4
LT		 2913 &entries);
2914 if (rval != QLA_SUCCESS)
2915 goto cleanup_allocation;
2916
7c3df132
SK		 2917 ql_dbg(ql_dbg_disc, vha, 0x2017,
2918 "Entries in ID list (%d).\n", entries);
2919 ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
2920 (uint8_t *)ha->gid_list,
2921 entries * sizeof(struct gid_list_info));
1da177e4
LT		 2922
2923 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 2924 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 2925 if (new_fcport == NULL) {
7c3df132
SK		 2926 ql_log(ql_log_warn, vha, 0x2018,
2927 "Memory allocation failed for fcport.\n");
1da177e4
LT		 2928 rval = QLA_MEMORY_ALLOC_FAILED;
2929 goto cleanup_allocation;
2930 }
2931 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
2932
2933 /*
2934 * Mark local devices that were present with FCF_DEVICE_LOST for now.
2935 */
e315cd28 2936 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 2937 if (atomic_read(&fcport->state) == FCS_ONLINE &&
2938 fcport->port_type != FCT_BROADCAST &&
2939 (fcport->flags & FCF_FABRIC_DEVICE) == 0) {
2940
7c3df132
SK		 2941 ql_dbg(ql_dbg_disc, vha, 0x2019,
2942 "Marking port lost loop_id=0x%04x.\n",
2943 fcport->loop_id);
1da177e4 2944
ec426e10 2945 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 2946 }
2947 }
2948
2949 /* Add devices to port list. */
2950 id_iter = (char *)ha->gid_list;
2951 for (index = 0; index < entries; index++) {
2952 domain = ((struct gid_list_info *)id_iter)->domain;
2953 area = ((struct gid_list_info *)id_iter)->area;
2954 al_pa = ((struct gid_list_info *)id_iter)->al_pa;
abbd8870 2955 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1da177e4
LT		 2956 loop_id = (uint16_t)
2957 ((struct gid_list_info *)id_iter)->loop_id_2100;
abbd8870 2958 else
1da177e4
LT		 2959 loop_id = le16_to_cpu(
2960 ((struct gid_list_info *)id_iter)->loop_id);
abbd8870 2961 id_iter += ha->gid_list_info_size;
1da177e4
LT		 2962
2963 /* Bypass reserved domain fields. */
2964 if ((domain & 0xf0) == 0xf0)
2965 continue;
2966
2967 /* Bypass if not same domain and area of adapter. */
f7d289f6 2968 if (area && domain &&
e315cd28 2969 (area != vha->d_id.b.area || domain != vha->d_id.b.domain))
1da177e4
LT		 2970 continue;
2971
2972 /* Bypass invalid local loop ID. */
2973 if (loop_id > LAST_LOCAL_LOOP_ID)
2974 continue;
2975
370d550e
AE		 2976 memset(new_fcport, 0, sizeof(fc_port_t));
2977
1da177e4
LT		 2978 /* Fill in member data. */
2979 new_fcport->d_id.b.domain = domain;
2980 new_fcport->d_id.b.area = area;
2981 new_fcport->d_id.b.al_pa = al_pa;
2982 new_fcport->loop_id = loop_id;
e315cd28 2983 rval2 = qla2x00_get_port_database(vha, new_fcport, 0);
1da177e4 2984 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 2985 ql_dbg(ql_dbg_disc, vha, 0x201a,
2986 "Failed to retrieve fcport information "
2987 "-- get_port_database=%x, loop_id=0x%04x.\n",
2988 rval2, new_fcport->loop_id);
2989 ql_dbg(ql_dbg_disc, vha, 0x201b,
2990 "Scheduling resync.\n");
e315cd28 2991 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4
LT		 2992 continue;
2993 }
2994
2995 /* Check for matching device in port list. */
2996 found = 0;
2997 fcport = NULL;
e315cd28 2998 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 2999 if (memcmp(new_fcport->port_name, fcport->port_name,
3000 WWN_SIZE))
3001 continue;
3002
ddb9b126 3003 fcport->flags &= ~FCF_FABRIC_DEVICE;
1da177e4
LT		 3004 fcport->loop_id = new_fcport->loop_id;
3005 fcport->port_type = new_fcport->port_type;
3006 fcport->d_id.b24 = new_fcport->d_id.b24;
3007 memcpy(fcport->node_name, new_fcport->node_name,
3008 WWN_SIZE);
3009
3010 found++;
3011 break;
3012 }
3013
3014 if (!found) {
3015 /* New device, add to fcports list. */
e315cd28 3016 list_add_tail(&new_fcport->list, &vha->vp_fcports);
1da177e4
LT		 3017
3018 /* Allocate a new replacement fcport. */
3019 fcport = new_fcport;
e315cd28 3020 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3021 if (new_fcport == NULL) {
7c3df132
SK		 3022 ql_log(ql_log_warn, vha, 0x201c,
3023 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 3024 rval = QLA_MEMORY_ALLOC_FAILED;
3025 goto cleanup_allocation;
3026 }
3027 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
3028 }
3029
d8b45213 3030 /* Base iIDMA settings on HBA port speed. */
a3cbdfad 3031 fcport->fp_speed = ha->link_data_rate;
d8b45213 3032
e315cd28 3033 qla2x00_update_fcport(vha, fcport);
1da177e4
LT		 3034
3035 found_devs++;
3036 }
3037
3038cleanup_allocation:
c9475cb0 3039 kfree(new_fcport);
1da177e4
LT		 3040
3041 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3042 ql_dbg(ql_dbg_disc, vha, 0x201d,
3043 "Configure local loop error exit: rval=%x.\n", rval);
1da177e4
LT		 3044 }
3045
1da177e4
LT		 3046 return (rval);
3047}
3048
d8b45213 3049static void
e315cd28 3050qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
d8b45213 3051{
d8b45213 3052 int rval;
1bb39548 3053 uint16_t mb[4];
e315cd28 3054 struct qla_hw_data *ha = vha->hw;
d8b45213 3055
c76f2c01 3056 if (!IS_IIDMA_CAPABLE(ha))
d8b45213
AV		 3057 return;
3058
c9afb9a2
GM		 3059 if (atomic_read(&fcport->state) != FCS_ONLINE)
3060 return;
3061
39bd9622
AV		 3062 if (fcport->fp_speed == PORT_SPEED_UNKNOWN ||
3063 fcport->fp_speed > ha->link_data_rate)
d8b45213
AV		 3064 return;
3065
e315cd28 3066 rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed,
a3cbdfad 3067 mb);
d8b45213 3068 if (rval != QLA_SUCCESS) {
7c3df132 3069 ql_dbg(ql_dbg_disc, vha, 0x2004,
7b833558
OK		 3070 "Unable to adjust iIDMA %8phN -- %04x %x %04x %04x.\n",
3071 fcport->port_name, rval, fcport->fp_speed, mb[0], mb[1]);
d8b45213 3072 } else {
7c3df132 3073 ql_dbg(ql_dbg_disc, vha, 0x2005,
7b833558 3074 "iIDMA adjusted to %s GB/s on %8phN.\n",
d0297c9a 3075 qla2x00_get_link_speed_str(ha, fcport->fp_speed),
7b833558 3076 fcport->port_name);
d8b45213
AV		 3077 }
3078}
3079
23be331d 3080static void
e315cd28 3081qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport)
8482e118
AV		 3082{
3083 struct fc_rport_identifiers rport_ids;
bdf79621 3084 struct fc_rport *rport;
044d78e1 3085 unsigned long flags;
8482e118 3086
ac280b67 3087 qla2x00_rport_del(fcport);
8482e118 3088
f8b02a85
AV		 3089 rport_ids.node_name = wwn_to_u64(fcport->node_name);
3090 rport_ids.port_name = wwn_to_u64(fcport->port_name);
8482e118
AV		 3091 rport_ids.port_id = fcport->d_id.b.domain << 16 |
3092 fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa;
77d74143 3093 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
e315cd28 3094 fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids);
77d74143 3095 if (!rport) {
7c3df132
SK		 3096 ql_log(ql_log_warn, vha, 0x2006,
3097 "Unable to allocate fc remote port.\n");
77d74143
AV		 3098 return;
3099 }
2d70c103
NB		 3100 /*
3101 * Create target mode FC NEXUS in qla_target.c if target mode is
3102 * enabled..
3103 */
3104 qlt_fc_port_added(vha, fcport);
3105
044d78e1 3106 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
19a7b4ae 3107 *((fc_port_t **)rport->dd_data) = fcport;
044d78e1 3108 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
d97994dc 3109
ad3e0eda 3110 rport->supported_classes = fcport->supported_classes;
77d74143 3111
8482e118
AV		 3112 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
3113 if (fcport->port_type == FCT_INITIATOR)
3114 rport_ids.roles |= FC_RPORT_ROLE_FCP_INITIATOR;
3115 if (fcport->port_type == FCT_TARGET)
3116 rport_ids.roles |= FC_RPORT_ROLE_FCP_TARGET;
77d74143 3117 fc_remote_port_rolechg(rport, rport_ids.roles);
1da177e4
LT		 3118}
3119
23be331d
AB		 3120/*
3121 * qla2x00_update_fcport
3122 * Updates device on list.
3123 *
3124 * Input:
3125 * ha = adapter block pointer.
3126 * fcport = port structure pointer.
3127 *
3128 * Return:
3129 * 0 - Success
3130 * BIT_0 - error
3131 *
3132 * Context:
3133 * Kernel context.
3134 */
3135void
e315cd28 3136qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
23be331d 3137{
e315cd28 3138 fcport->vha = vha;
8ae6d9c7
GM		 3139
3140 if (IS_QLAFX00(vha->hw)) {
3141 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
3142 qla2x00_reg_remote_port(vha, fcport);
3143 return;
3144 }
23be331d 3145 fcport->login_retry = 0;
5ff1d584 3146 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
23be331d 3147
1f93da52 3148 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
e315cd28 3149 qla2x00_iidma_fcport(vha, fcport);
21090cbe 3150 qla24xx_update_fcport_fcp_prio(vha, fcport);
e315cd28 3151 qla2x00_reg_remote_port(vha, fcport);
23be331d
AB		 3152}
3153
1da177e4
LT		 3154/*
3155 * qla2x00_configure_fabric
3156 * Setup SNS devices with loop ID's.
3157 *
3158 * Input:
3159 * ha = adapter block pointer.
3160 *
3161 * Returns:
3162 * 0 = success.
3163 * BIT_0 = error
3164 */
3165static int
e315cd28 3166qla2x00_configure_fabric(scsi_qla_host_t *vha)
1da177e4 3167{
b3b02e6e 3168 int rval;
e452ceb6 3169 fc_port_t *fcport, *fcptemp;
1da177e4
LT		 3170 uint16_t next_loopid;
3171 uint16_t mb[MAILBOX_REGISTER_COUNT];
0107109e 3172 uint16_t loop_id;
1da177e4 3173 LIST_HEAD(new_fcports);
e315cd28
AC		 3174 struct qla_hw_data *ha = vha->hw;
3175 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 3176
3177 /* If FL port exists, then SNS is present */
e428924c 3178 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 3179 loop_id = NPH_F_PORT;
3180 else
3181 loop_id = SNS_FL_PORT;
e315cd28 3182 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1);
1da177e4 3183 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3184 ql_dbg(ql_dbg_disc, vha, 0x201f,
3185 "MBX_GET_PORT_NAME failed, No FL Port.\n");
1da177e4 3186
e315cd28 3187 vha->device_flags &= ~SWITCH_FOUND;
1da177e4
LT		 3188 return (QLA_SUCCESS);
3189 }
e315cd28 3190 vha->device_flags |= SWITCH_FOUND;
1da177e4 3191
1da177e4 3192 do {
cca5335c
AV		 3193 /* FDMI support. */
3194 if (ql2xfdmienable &&
e315cd28
AC		 3195 test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags))
3196 qla2x00_fdmi_register(vha);
cca5335c 3197
1da177e4 3198 /* Ensure we are logged into the SNS. */
e428924c 3199 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 3200 loop_id = NPH_SNS;
3201 else
3202 loop_id = SIMPLE_NAME_SERVER;
0b91d116
CD		 3203 rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff,
3204 0xfc, mb, BIT_1|BIT_0);
3205 if (rval != QLA_SUCCESS) {
3206 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
e452ceb6 3207 return rval;
0b91d116 3208 }
1da177e4 3209 if (mb[0] != MBS_COMMAND_COMPLETE) {
7c3df132
SK		 3210 ql_dbg(ql_dbg_disc, vha, 0x2042,
3211 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x "
3212 "mb[6]=%x mb[7]=%x.\n", loop_id, mb[0], mb[1],
3213 mb[2], mb[6], mb[7]);
1da177e4
LT		 3214 return (QLA_SUCCESS);
3215 }
3216
e315cd28
AC		 3217 if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) {
3218 if (qla2x00_rft_id(vha)) {
1da177e4 3219 /* EMPTY */
7c3df132
SK		 3220 ql_dbg(ql_dbg_disc, vha, 0x2045,
3221 "Register FC-4 TYPE failed.\n");
1da177e4 3222 }
e315cd28 3223 if (qla2x00_rff_id(vha)) {
1da177e4 3224 /* EMPTY */
7c3df132
SK		 3225 ql_dbg(ql_dbg_disc, vha, 0x2049,
3226 "Register FC-4 Features failed.\n");
1da177e4 3227 }
e315cd28 3228 if (qla2x00_rnn_id(vha)) {
1da177e4 3229 /* EMPTY */
7c3df132
SK		 3230 ql_dbg(ql_dbg_disc, vha, 0x204f,
3231 "Register Node Name failed.\n");
e315cd28 3232 } else if (qla2x00_rsnn_nn(vha)) {
1da177e4 3233 /* EMPTY */
7c3df132
SK		 3234 ql_dbg(ql_dbg_disc, vha, 0x2053,
3235 "Register Symobilic Node Name failed.\n");
1da177e4
LT		 3236 }
3237 }
3238
827210ba
JC		 3239#define QLA_FCPORT_SCAN 1
3240#define QLA_FCPORT_FOUND 2
3241
3242 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3243 fcport->scan_state = QLA_FCPORT_SCAN;
3244 }
3245
e315cd28 3246 rval = qla2x00_find_all_fabric_devs(vha, &new_fcports);
1da177e4
LT		 3247 if (rval != QLA_SUCCESS)
3248 break;
3249
e452ceb6
JC		 3250 /*
3251 * Logout all previous fabric devices marked lost, except
3252 * FCP2 devices.
3253 */
e315cd28
AC		 3254 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3255 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
1da177e4
LT		 3256 break;
3257
3258 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0)
3259 continue;
3260
827210ba 3261 if (fcport->scan_state == QLA_FCPORT_SCAN &&
b3b02e6e 3262 atomic_read(&fcport->state) == FCS_ONLINE) {
e315cd28 3263 qla2x00_mark_device_lost(vha, fcport,
d97994dc 3264 ql2xplogiabsentdevice, 0);
1da177e4 3265 if (fcport->loop_id != FC_NO_LOOP_ID &&
f08b7251 3266 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
1da177e4
LT		 3267 fcport->port_type != FCT_INITIATOR &&
3268 fcport->port_type != FCT_BROADCAST) {
e315cd28 3269 ha->isp_ops->fabric_logout(vha,
1c7c6357
AV		 3270 fcport->loop_id,
3271 fcport->d_id.b.domain,
3272 fcport->d_id.b.area,
3273 fcport->d_id.b.al_pa);
e452ceb6 3274 fcport->loop_id = FC_NO_LOOP_ID;
1da177e4
LT		 3275 }
3276 }
e452ceb6 3277 }
1da177e4 3278
e452ceb6
JC		 3279 /* Starting free loop ID. */
3280 next_loopid = ha->min_external_loopid;
3281
3282 /*
3283 * Scan through our port list and login entries that need to be
3284 * logged in.
3285 */
3286 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3287 if (atomic_read(&vha->loop_down_timer) ||
3288 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3289 break;
3290
3291 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0 ||
3292 (fcport->flags & FCF_LOGIN_NEEDED) == 0)
3293 continue;
3294
3295 if (fcport->loop_id == FC_NO_LOOP_ID) {
3296 fcport->loop_id = next_loopid;
3297 rval = qla2x00_find_new_loop_id(
3298 base_vha, fcport);
3299 if (rval != QLA_SUCCESS) {
3300 /* Ran out of IDs to use */
3301 break;
1da177e4
LT		 3302 }
3303 }
e452ceb6
JC		 3304 /* Login and update database */
3305 qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
3306 }
3307
3308 /* Exit if out of loop IDs. */
3309 if (rval != QLA_SUCCESS) {
3310 break;
3311 }
3312
3313 /*
3314 * Login and add the new devices to our port list.
3315 */
3316 list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) {
3317 if (atomic_read(&vha->loop_down_timer) ||
3318 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3319 break;
3320
3321 /* Find a new loop ID to use. */
3322 fcport->loop_id = next_loopid;
3323 rval = qla2x00_find_new_loop_id(base_vha, fcport);
3324 if (rval != QLA_SUCCESS) {
3325 /* Ran out of IDs to use */
3326 break;
3327 }
1da177e4 3328
bdf79621 3329 /* Login and update database */
e315cd28 3330 qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
e452ceb6
JC		 3331
3332 list_move_tail(&fcport->list, &vha->vp_fcports);
1da177e4
LT		 3333 }
3334 } while (0);
3335
e452ceb6
JC		 3336 /* Free all new device structures not processed. */
3337 list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) {
3338 list_del(&fcport->list);
3339 kfree(fcport);
3340 }
3341
1da177e4 3342 if (rval) {
7c3df132
SK		 3343 ql_dbg(ql_dbg_disc, vha, 0x2068,
3344 "Configure fabric error exit rval=%d.\n", rval);
1da177e4
LT		 3345 }
3346
3347 return (rval);
3348}
3349
1da177e4
LT		 3350/*
3351 * qla2x00_find_all_fabric_devs
3352 *
3353 * Input:
3354 * ha = adapter block pointer.
3355 * dev = database device entry pointer.
3356 *
3357 * Returns:
3358 * 0 = success.
3359 *
3360 * Context:
3361 * Kernel context.
3362 */
3363static int
e315cd28
AC		 3364qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha,
3365 struct list_head *new_fcports)
1da177e4
LT		 3366{
3367 int rval;
3368 uint16_t loop_id;
3369 fc_port_t *fcport, *new_fcport, *fcptemp;
3370 int found;
3371
3372 sw_info_t *swl;
3373 int swl_idx;
3374 int first_dev, last_dev;
1516ef44 3375 port_id_t wrap = {}, nxt_d_id;
e315cd28 3376 struct qla_hw_data *ha = vha->hw;
bb4cf5b7 3377 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 3378
3379 rval = QLA_SUCCESS;
3380
3381 /* Try GID_PT to get device list, else GAN. */
7a67735b 3382 if (!ha->swl)
642ef983 3383 ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t),
7a67735b
AV		 3384 GFP_KERNEL);
3385 swl = ha->swl;
bbfbbbc1 3386 if (!swl) {
1da177e4 3387 /*EMPTY*/
7c3df132
SK		 3388 ql_dbg(ql_dbg_disc, vha, 0x2054,
3389 "GID_PT allocations failed, fallback on GA_NXT.\n");
1da177e4 3390 } else {
642ef983 3391 memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t));
e315cd28 3392 if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) {
1da177e4 3393 swl = NULL;
e315cd28 3394 } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 3395 swl = NULL;
e315cd28 3396 } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 3397 swl = NULL;
e5896bd5 3398 } else if (ql2xiidmaenable &&
e315cd28
AC		 3399 qla2x00_gfpn_id(vha, swl) == QLA_SUCCESS) {
3400 qla2x00_gpsc(vha, swl);
1da177e4 3401 }
e8c72ba5
CD		 3402
3403 /* If other queries succeeded probe for FC-4 type */
3404 if (swl)
3405 qla2x00_gff_id(vha, swl);
1da177e4
LT		 3406 }
3407 swl_idx = 0;
3408
3409 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 3410 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3411 if (new_fcport == NULL) {
7c3df132
SK		 3412 ql_log(ql_log_warn, vha, 0x205e,
3413 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 3414 return (QLA_MEMORY_ALLOC_FAILED);
3415 }
3416 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
1da177e4
LT		 3417 /* Set start port ID scan at adapter ID. */
3418 first_dev = 1;
3419 last_dev = 0;
3420
3421 /* Starting free loop ID. */
e315cd28
AC		 3422 loop_id = ha->min_external_loopid;
3423 for (; loop_id <= ha->max_loop_id; loop_id++) {
3424 if (qla2x00_is_reserved_id(vha, loop_id))
1da177e4
LT		 3425 continue;
3426
3a6478df
GM		 3427 if (ha->current_topology == ISP_CFG_FL &&
3428 (atomic_read(&vha->loop_down_timer) ||
3429 LOOP_TRANSITION(vha))) {
bb2d52b2
AV		 3430 atomic_set(&vha->loop_down_timer, 0);
3431 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
3432 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
1da177e4 3433 break;
bb2d52b2 3434 }
1da177e4
LT		 3435
3436 if (swl != NULL) {
3437 if (last_dev) {
3438 wrap.b24 = new_fcport->d_id.b24;
3439 } else {
3440 new_fcport->d_id.b24 = swl[swl_idx].d_id.b24;
3441 memcpy(new_fcport->node_name,
3442 swl[swl_idx].node_name, WWN_SIZE);
3443 memcpy(new_fcport->port_name,
3444 swl[swl_idx].port_name, WWN_SIZE);
d8b45213
AV		 3445 memcpy(new_fcport->fabric_port_name,
3446 swl[swl_idx].fabric_port_name, WWN_SIZE);
3447 new_fcport->fp_speed = swl[swl_idx].fp_speed;
e8c72ba5 3448 new_fcport->fc4_type = swl[swl_idx].fc4_type;
1da177e4
LT		 3449
3450 if (swl[swl_idx].d_id.b.rsvd_1 != 0) {
3451 last_dev = 1;
3452 }
3453 swl_idx++;
3454 }
3455 } else {
3456 /* Send GA_NXT to the switch */
e315cd28 3457 rval = qla2x00_ga_nxt(vha, new_fcport);
1da177e4 3458 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3459 ql_log(ql_log_warn, vha, 0x2064,
3460 "SNS scan failed -- assuming "
3461 "zero-entry result.\n");
1da177e4
LT		 3462 list_for_each_entry_safe(fcport, fcptemp,
3463 new_fcports, list) {
3464 list_del(&fcport->list);
3465 kfree(fcport);
3466 }
3467 rval = QLA_SUCCESS;
3468 break;
3469 }
3470 }
3471
3472 /* If wrap on switch device list, exit. */
3473 if (first_dev) {
3474 wrap.b24 = new_fcport->d_id.b24;
3475 first_dev = 0;
3476 } else if (new_fcport->d_id.b24 == wrap.b24) {
7c3df132
SK		 3477 ql_dbg(ql_dbg_disc, vha, 0x2065,
3478 "Device wrap (%02x%02x%02x).\n",
3479 new_fcport->d_id.b.domain,
3480 new_fcport->d_id.b.area,
3481 new_fcport->d_id.b.al_pa);
1da177e4
LT		 3482 break;
3483 }
3484
2c3dfe3f 3485 /* Bypass if same physical adapter. */
e315cd28 3486 if (new_fcport->d_id.b24 == base_vha->d_id.b24)
1da177e4
LT		 3487 continue;
3488
2c3dfe3f 3489 /* Bypass virtual ports of the same host. */
bb4cf5b7
CD		 3490 if (qla2x00_is_a_vp_did(vha, new_fcport->d_id.b24))
3491 continue;
2c3dfe3f 3492
f7d289f6
AV		 3493 /* Bypass if same domain and area of adapter. */
3494 if (((new_fcport->d_id.b24 & 0xffff00) ==
e315cd28 3495 (vha->d_id.b24 & 0xffff00)) && ha->current_topology ==
f7d289f6
AV		 3496 ISP_CFG_FL)
3497 continue;
3498
1da177e4
LT		 3499 /* Bypass reserved domain fields. */
3500 if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0)
3501 continue;
3502
e8c72ba5 3503 /* Bypass ports whose FCP-4 type is not FCP_SCSI */
4da26e16
CD		 3504 if (ql2xgffidenable &&
3505 (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI &&
3506 new_fcport->fc4_type != FC4_TYPE_UNKNOWN))
e8c72ba5
CD		 3507 continue;
3508
1da177e4
LT		 3509 /* Locate matching device in database. */
3510 found = 0;
e315cd28 3511 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 3512 if (memcmp(new_fcport->port_name, fcport->port_name,
3513 WWN_SIZE))
3514 continue;
3515
827210ba 3516 fcport->scan_state = QLA_FCPORT_FOUND;
b3b02e6e 3517
1da177e4
LT		 3518 found++;
3519
d8b45213
AV		 3520 /* Update port state. */
3521 memcpy(fcport->fabric_port_name,
3522 new_fcport->fabric_port_name, WWN_SIZE);
3523 fcport->fp_speed = new_fcport->fp_speed;
3524
1da177e4
LT		 3525 /*
3526 * If address the same and state FCS_ONLINE, nothing
3527 * changed.
3528 */
3529 if (fcport->d_id.b24 == new_fcport->d_id.b24 &&
3530 atomic_read(&fcport->state) == FCS_ONLINE) {
3531 break;
3532 }
3533
3534 /*
3535 * If device was not a fabric device before.
3536 */
3537 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) {
3538 fcport->d_id.b24 = new_fcport->d_id.b24;
5f16b331 3539 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 3540 fcport->flags |= (FCF_FABRIC_DEVICE |
3541 FCF_LOGIN_NEEDED);
1da177e4
LT		 3542 break;
3543 }
3544
3545 /*
3546 * Port ID changed or device was marked to be updated;
3547 * Log it out if still logged in and mark it for
3548 * relogin later.
3549 */
3550 fcport->d_id.b24 = new_fcport->d_id.b24;
3551 fcport->flags |= FCF_LOGIN_NEEDED;
3552 if (fcport->loop_id != FC_NO_LOOP_ID &&
f08b7251 3553 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
0eba25df 3554 (fcport->flags & FCF_ASYNC_SENT) == 0 &&
1da177e4
LT		 3555 fcport->port_type != FCT_INITIATOR &&
3556 fcport->port_type != FCT_BROADCAST) {
e315cd28 3557 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3558 fcport->d_id.b.domain, fcport->d_id.b.area,
3559 fcport->d_id.b.al_pa);
5f16b331 3560 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 3561 }
3562
3563 break;
3564 }
3565
3566 if (found)
3567 continue;
1da177e4
LT		 3568 /* If device was not in our fcports list, then add it. */
3569 list_add_tail(&new_fcport->list, new_fcports);
3570
3571 /* Allocate a new replacement fcport. */
3572 nxt_d_id.b24 = new_fcport->d_id.b24;
e315cd28 3573 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3574 if (new_fcport == NULL) {
7c3df132
SK		 3575 ql_log(ql_log_warn, vha, 0x2066,
3576 "Memory allocation failed for fcport.\n");
1da177e4
LT		 3577 return (QLA_MEMORY_ALLOC_FAILED);
3578 }
3579 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
3580 new_fcport->d_id.b24 = nxt_d_id.b24;
3581 }
3582
c9475cb0 3583 kfree(new_fcport);
1da177e4 3584
1da177e4
LT		 3585 return (rval);
3586}
3587
3588/*
3589 * qla2x00_find_new_loop_id
3590 * Scan through our port list and find a new usable loop ID.
3591 *
3592 * Input:
3593 * ha: adapter state pointer.
3594 * dev: port structure pointer.
3595 *
3596 * Returns:
3597 * qla2x00 local function return status code.
3598 *
3599 * Context:
3600 * Kernel context.
3601 */
03bcfb57 3602int
e315cd28 3603qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
1da177e4
LT		 3604{
3605 int rval;
e315cd28 3606 struct qla_hw_data *ha = vha->hw;
feafb7b1 3607 unsigned long flags = 0;
1da177e4
LT		 3608
3609 rval = QLA_SUCCESS;
3610
5f16b331 3611 spin_lock_irqsave(&ha->vport_slock, flags);
1da177e4 3612
5f16b331
CD		 3613 dev->loop_id = find_first_zero_bit(ha->loop_id_map,
3614 LOOPID_MAP_SIZE);
3615 if (dev->loop_id >= LOOPID_MAP_SIZE ||
3616 qla2x00_is_reserved_id(vha, dev->loop_id)) {
3617 dev->loop_id = FC_NO_LOOP_ID;
3618 rval = QLA_FUNCTION_FAILED;
3619 } else
3620 set_bit(dev->loop_id, ha->loop_id_map);
1da177e4 3621
5f16b331 3622 spin_unlock_irqrestore(&ha->vport_slock, flags);
1da177e4 3623
5f16b331
CD		 3624 if (rval == QLA_SUCCESS)
3625 ql_dbg(ql_dbg_disc, dev->vha, 0x2086,
3626 "Assigning new loopid=%x, portid=%x.\n",
3627 dev->loop_id, dev->d_id.b24);
3628 else
3629 ql_log(ql_log_warn, dev->vha, 0x2087,
3630 "No loop_id's available, portid=%x.\n",
3631 dev->d_id.b24);
1da177e4
LT		 3632
3633 return (rval);
3634}
3635
1da177e4
LT		 3636/*
3637 * qla2x00_fabric_dev_login
3638 * Login fabric target device and update FC port database.
3639 *
3640 * Input:
3641 * ha: adapter state pointer.
3642 * fcport: port structure list pointer.
3643 * next_loopid: contains value of a new loop ID that can be used
3644 * by the next login attempt.
3645 *
3646 * Returns:
3647 * qla2x00 local function return status code.
3648 *
3649 * Context:
3650 * Kernel context.
3651 */
3652static int
e315cd28 3653qla2x00_fabric_dev_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 3654 uint16_t *next_loopid)
3655{
3656 int rval;
3657 int retry;
0107109e 3658 uint8_t opts;
e315cd28 3659 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3660
3661 rval = QLA_SUCCESS;
3662 retry = 0;
3663
ac280b67 3664 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584
AV		 3665 if (fcport->flags & FCF_ASYNC_SENT)
3666 return rval;
3667 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 3668 rval = qla2x00_post_async_login_work(vha, fcport, NULL);
3669 if (!rval)
3670 return rval;
3671 }
3672
5ff1d584 3673 fcport->flags &= ~FCF_ASYNC_SENT;
e315cd28 3674 rval = qla2x00_fabric_login(vha, fcport, next_loopid);
1da177e4 3675 if (rval == QLA_SUCCESS) {
f08b7251 3676 /* Send an ADISC to FCP2 devices.*/
0107109e 3677 opts = 0;
f08b7251 3678 if (fcport->flags & FCF_FCP2_DEVICE)
0107109e 3679 opts |= BIT_1;
e315cd28 3680 rval = qla2x00_get_port_database(vha, fcport, opts);
1da177e4 3681 if (rval != QLA_SUCCESS) {
e315cd28 3682 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3683 fcport->d_id.b.domain, fcport->d_id.b.area,
3684 fcport->d_id.b.al_pa);
e315cd28 3685 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4 3686 } else {
e315cd28 3687 qla2x00_update_fcport(vha, fcport);
1da177e4 3688 }
0b91d116
CD		 3689 } else {
3690 /* Retry Login. */
3691 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 3692 }
3693
3694 return (rval);
3695}
3696
3697/*
3698 * qla2x00_fabric_login
3699 * Issue fabric login command.
3700 *
3701 * Input:
3702 * ha = adapter block pointer.
3703 * device = pointer to FC device type structure.
3704 *
3705 * Returns:
3706 * 0 - Login successfully
3707 * 1 - Login failed
3708 * 2 - Initiator device
3709 * 3 - Fatal error
3710 */
3711int
e315cd28 3712qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 3713 uint16_t *next_loopid)
3714{
3715 int rval;
3716 int retry;
3717 uint16_t tmp_loopid;
3718 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 3719 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3720
3721 retry = 0;
3722 tmp_loopid = 0;
3723
3724 for (;;) {
7c3df132
SK		 3725 ql_dbg(ql_dbg_disc, vha, 0x2000,
3726 "Trying Fabric Login w/loop id 0x%04x for port "
3727 "%02x%02x%02x.\n",
3728 fcport->loop_id, fcport->d_id.b.domain,
3729 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 3730
3731 /* Login fcport on switch. */
0b91d116 3732 rval = ha->isp_ops->fabric_login(vha, fcport->loop_id,
1da177e4
LT		 3733 fcport->d_id.b.domain, fcport->d_id.b.area,
3734 fcport->d_id.b.al_pa, mb, BIT_0);
0b91d116
CD		 3735 if (rval != QLA_SUCCESS) {
3736 return rval;
3737 }
1da177e4
LT		 3738 if (mb[0] == MBS_PORT_ID_USED) {
3739 /*
3740 * Device has another loop ID. The firmware team
0107109e
AV		 3741 * recommends the driver perform an implicit login with
3742 * the specified ID again. The ID we just used is save
3743 * here so we return with an ID that can be tried by
3744 * the next login.
1da177e4
LT		 3745 */
3746 retry++;
3747 tmp_loopid = fcport->loop_id;
3748 fcport->loop_id = mb[1];
3749
7c3df132
SK		 3750 ql_dbg(ql_dbg_disc, vha, 0x2001,
3751 "Fabric Login: port in use - next loop "
3752 "id=0x%04x, port id= %02x%02x%02x.\n",
1da177e4 3753 fcport->loop_id, fcport->d_id.b.domain,
7c3df132 3754 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 3755
3756 } else if (mb[0] == MBS_COMMAND_COMPLETE) {
3757 /*
3758 * Login succeeded.
3759 */
3760 if (retry) {
3761 /* A retry occurred before. */
3762 *next_loopid = tmp_loopid;
3763 } else {
3764 /*
3765 * No retry occurred before. Just increment the
3766 * ID value for next login.
3767 */
3768 *next_loopid = (fcport->loop_id + 1);
3769 }
3770
3771 if (mb[1] & BIT_0) {
3772 fcport->port_type = FCT_INITIATOR;
3773 } else {
3774 fcport->port_type = FCT_TARGET;
3775 if (mb[1] & BIT_1) {
8474f3a0 3776 fcport->flags |= FCF_FCP2_DEVICE;
1da177e4
LT		 3777 }
3778 }
3779
ad3e0eda
AV		 3780 if (mb[10] & BIT_0)
3781 fcport->supported_classes |= FC_COS_CLASS2;
3782 if (mb[10] & BIT_1)
3783 fcport->supported_classes |= FC_COS_CLASS3;
3784
2d70c103
NB		 3785 if (IS_FWI2_CAPABLE(ha)) {
3786 if (mb[10] & BIT_7)
3787 fcport->flags |=
3788 FCF_CONF_COMP_SUPPORTED;
3789 }
3790
1da177e4
LT		 3791 rval = QLA_SUCCESS;
3792 break;
3793 } else if (mb[0] == MBS_LOOP_ID_USED) {
3794 /*
3795 * Loop ID already used, try next loop ID.
3796 */
3797 fcport->loop_id++;
e315cd28 3798 rval = qla2x00_find_new_loop_id(vha, fcport);
1da177e4
LT		 3799 if (rval != QLA_SUCCESS) {
3800 /* Ran out of loop IDs to use */
3801 break;
3802 }
3803 } else if (mb[0] == MBS_COMMAND_ERROR) {
3804 /*
3805 * Firmware possibly timed out during login. If NO
3806 * retries are left to do then the device is declared
3807 * dead.
3808 */
3809 *next_loopid = fcport->loop_id;
e315cd28 3810 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3811 fcport->d_id.b.domain, fcport->d_id.b.area,
3812 fcport->d_id.b.al_pa);
e315cd28 3813 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 3814
3815 rval = 1;
3816 break;
3817 } else {
3818 /*
3819 * unrecoverable / not handled error
3820 */
7c3df132
SK		 3821 ql_dbg(ql_dbg_disc, vha, 0x2002,
3822 "Failed=%x port_id=%02x%02x%02x loop_id=%x "
3823 "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain,
3824 fcport->d_id.b.area, fcport->d_id.b.al_pa,
3825 fcport->loop_id, jiffies);
1da177e4
LT		 3826
3827 *next_loopid = fcport->loop_id;
e315cd28 3828 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3829 fcport->d_id.b.domain, fcport->d_id.b.area,
3830 fcport->d_id.b.al_pa);
5f16b331 3831 qla2x00_clear_loop_id(fcport);
0eedfcf0 3832 fcport->login_retry = 0;
1da177e4
LT		 3833
3834 rval = 3;
3835 break;
3836 }
3837 }
3838
3839 return (rval);
3840}
3841
3842/*
3843 * qla2x00_local_device_login
3844 * Issue local device login command.
3845 *
3846 * Input:
3847 * ha = adapter block pointer.
3848 * loop_id = loop id of device to login to.
3849 *
3850 * Returns (Where's the #define!!!!):
3851 * 0 - Login successfully
3852 * 1 - Login failed
3853 * 3 - Fatal error
3854 */
3855int
e315cd28 3856qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport)
1da177e4
LT		 3857{
3858 int rval;
3859 uint16_t mb[MAILBOX_REGISTER_COUNT];
3860
3861 memset(mb, 0, sizeof(mb));
e315cd28 3862 rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0);
1da177e4
LT		 3863 if (rval == QLA_SUCCESS) {
3864 /* Interrogate mailbox registers for any errors */
3865 if (mb[0] == MBS_COMMAND_ERROR)
3866 rval = 1;
3867 else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR)
3868 /* device not in PCB table */
3869 rval = 3;
3870 }
3871
3872 return (rval);
3873}
3874
3875/*
3876 * qla2x00_loop_resync
3877 * Resync with fibre channel devices.
3878 *
3879 * Input:
3880 * ha = adapter block pointer.
3881 *
3882 * Returns:
3883 * 0 = success
3884 */
3885int
e315cd28 3886qla2x00_loop_resync(scsi_qla_host_t *vha)
1da177e4 3887{
73208dfd 3888 int rval = QLA_SUCCESS;
1da177e4 3889 uint32_t wait_time;
67c2e93a
AC		 3890 struct req_que *req;
3891 struct rsp_que *rsp;
3892
7163ea81 3893 if (vha->hw->flags.cpu_affinity_enabled)
67c2e93a
AC		 3894 req = vha->hw->req_q_map[0];
3895 else
3896 req = vha->req;
3897 rsp = req->rsp;
1da177e4 3898
e315cd28
AC		 3899 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
3900 if (vha->flags.online) {
3901 if (!(rval = qla2x00_fw_ready(vha))) {
1da177e4
LT		 3902 /* Wait at most MAX_TARGET RSCNs for a stable link. */
3903 wait_time = 256;
3904 do {
8ae6d9c7
GM		 3905 if (!IS_QLAFX00(vha->hw)) {
3906 /*
3907 * Issue a marker after FW becomes
3908 * ready.
3909 */
3910 qla2x00_marker(vha, req, rsp, 0, 0,
3911 MK_SYNC_ALL);
3912 vha->marker_needed = 0;
3913 }
1da177e4
LT		 3914
3915 /* Remap devices on Loop. */
e315cd28 3916 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4 3917
8ae6d9c7
GM		 3918 if (IS_QLAFX00(vha->hw))
3919 qlafx00_configure_devices(vha);
3920 else
3921 qla2x00_configure_loop(vha);
3922
1da177e4 3923 wait_time--;
e315cd28
AC		 3924 } while (!atomic_read(&vha->loop_down_timer) &&
3925 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
3926 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
3927 &vha->dpc_flags)));
1da177e4 3928 }
1da177e4
LT		 3929 }
3930
e315cd28 3931 if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
1da177e4 3932 return (QLA_FUNCTION_FAILED);
1da177e4 3933
e315cd28 3934 if (rval)
7c3df132
SK		 3935 ql_dbg(ql_dbg_disc, vha, 0x206c,
3936 "%s *** FAILED ***.\n", __func__);
1da177e4
LT		 3937
3938 return (rval);
3939}
3940
579d12b5
SK		 3941/*
3942* qla2x00_perform_loop_resync
3943* Description: This function will set the appropriate flags and call
3944* qla2x00_loop_resync. If successful loop will be resynced
3945* Arguments : scsi_qla_host_t pointer
3946* returm : Success or Failure
3947*/
3948
3949int qla2x00_perform_loop_resync(scsi_qla_host_t *ha)
3950{
3951 int32_t rval = 0;
3952
3953 if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) {
3954 /*Configure the flags so that resync happens properly*/
3955 atomic_set(&ha->loop_down_timer, 0);
3956 if (!(ha->device_flags & DFLG_NO_CABLE)) {
3957 atomic_set(&ha->loop_state, LOOP_UP);
3958 set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags);
3959 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
3960 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
3961
3962 rval = qla2x00_loop_resync(ha);
3963 } else
3964 atomic_set(&ha->loop_state, LOOP_DEAD);
3965
3966 clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags);
3967 }
3968
3969 return rval;
3970}
3971
d97994dc 3972void
67becc00 3973qla2x00_update_fcports(scsi_qla_host_t *base_vha)
d97994dc
AV		 3974{
3975 fc_port_t *fcport;
feafb7b1
AE		 3976 struct scsi_qla_host *vha;
3977 struct qla_hw_data *ha = base_vha->hw;
3978 unsigned long flags;
d97994dc 3979
feafb7b1 3980 spin_lock_irqsave(&ha->vport_slock, flags);
d97994dc 3981 /* Go with deferred removal of rport references. */
feafb7b1
AE		 3982 list_for_each_entry(vha, &base_vha->hw->vp_list, list) {
3983 atomic_inc(&vha->vref_count);
3984 list_for_each_entry(fcport, &vha->vp_fcports, list) {
8ae598d0 3985 if (fcport->drport &&
feafb7b1
AE		 3986 atomic_read(&fcport->state) != FCS_UNCONFIGURED) {
3987 spin_unlock_irqrestore(&ha->vport_slock, flags);
67becc00 3988 qla2x00_rport_del(fcport);
feafb7b1
AE		 3989 spin_lock_irqsave(&ha->vport_slock, flags);
3990 }
3991 }
3992 atomic_dec(&vha->vref_count);
3993 }
3994 spin_unlock_irqrestore(&ha->vport_slock, flags);
d97994dc
AV		 3995}
3996
7d613ac6
SV		 3997/* Assumes idc_lock always held on entry */
3998void
3999qla83xx_reset_ownership(scsi_qla_host_t *vha)
4000{
4001 struct qla_hw_data *ha = vha->hw;
4002 uint32_t drv_presence, drv_presence_mask;
4003 uint32_t dev_part_info1, dev_part_info2, class_type;
4004 uint32_t class_type_mask = 0x3;
4005 uint16_t fcoe_other_function = 0xffff, i;
4006
7ec0effd
AD		 4007 if (IS_QLA8044(ha)) {
4008 drv_presence = qla8044_rd_direct(vha,
4009 QLA8044_CRB_DRV_ACTIVE_INDEX);
4010 dev_part_info1 = qla8044_rd_direct(vha,
4011 QLA8044_CRB_DEV_PART_INFO_INDEX);
4012 dev_part_info2 = qla8044_rd_direct(vha,
4013 QLA8044_CRB_DEV_PART_INFO2);
4014 } else {
4015 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4016 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1);
4017 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2);
4018 }
7d613ac6
SV		 4019 for (i = 0; i < 8; i++) {
4020 class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask);
4021 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
4022 (i != ha->portnum)) {
4023 fcoe_other_function = i;
4024 break;
4025 }
4026 }
4027 if (fcoe_other_function == 0xffff) {
4028 for (i = 0; i < 8; i++) {
4029 class_type = ((dev_part_info2 >> (i * 4)) &
4030 class_type_mask);
4031 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
4032 ((i + 8) != ha->portnum)) {
4033 fcoe_other_function = i + 8;
4034 break;
4035 }
4036 }
4037 }
4038 /*
4039 * Prepare drv-presence mask based on fcoe functions present.
4040 * However consider only valid physical fcoe function numbers (0-15).
4041 */
4042 drv_presence_mask = ~((1 << (ha->portnum)) |
4043 ((fcoe_other_function == 0xffff) ?
4044 0 : (1 << (fcoe_other_function))));
4045
4046 /* We are the reset owner iff:
4047 * - No other protocol drivers present.
4048 * - This is the lowest among fcoe functions. */
4049 if (!(drv_presence & drv_presence_mask) &&
4050 (ha->portnum < fcoe_other_function)) {
4051 ql_dbg(ql_dbg_p3p, vha, 0xb07f,
4052 "This host is Reset owner.\n");
4053 ha->flags.nic_core_reset_owner = 1;
4054 }
4055}
4056
fa492630 4057static int
7d613ac6
SV		 4058__qla83xx_set_drv_ack(scsi_qla_host_t *vha)
4059{
4060 int rval = QLA_SUCCESS;
4061 struct qla_hw_data *ha = vha->hw;
4062 uint32_t drv_ack;
4063
4064 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4065 if (rval == QLA_SUCCESS) {
4066 drv_ack |= (1 << ha->portnum);
4067 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
4068 }
4069
4070 return rval;
4071}
4072
fa492630 4073static int
7d613ac6
SV		 4074__qla83xx_clear_drv_ack(scsi_qla_host_t *vha)
4075{
4076 int rval = QLA_SUCCESS;
4077 struct qla_hw_data *ha = vha->hw;
4078 uint32_t drv_ack;
4079
4080 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4081 if (rval == QLA_SUCCESS) {
4082 drv_ack &= ~(1 << ha->portnum);
4083 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
4084 }
4085
4086 return rval;
4087}
4088
fa492630 4089static const char *
7d613ac6
SV		 4090qla83xx_dev_state_to_string(uint32_t dev_state)
4091{
4092 switch (dev_state) {
4093 case QLA8XXX_DEV_COLD:
4094 return "COLD/RE-INIT";
4095 case QLA8XXX_DEV_INITIALIZING:
4096 return "INITIALIZING";
4097 case QLA8XXX_DEV_READY:
4098 return "READY";
4099 case QLA8XXX_DEV_NEED_RESET:
4100 return "NEED RESET";
4101 case QLA8XXX_DEV_NEED_QUIESCENT:
4102 return "NEED QUIESCENT";
4103 case QLA8XXX_DEV_FAILED:
4104 return "FAILED";
4105 case QLA8XXX_DEV_QUIESCENT:
4106 return "QUIESCENT";
4107 default:
4108 return "Unknown";
4109 }
4110}
4111
4112/* Assumes idc-lock always held on entry */
4113void
4114qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type)
4115{
4116 struct qla_hw_data *ha = vha->hw;
4117 uint32_t idc_audit_reg = 0, duration_secs = 0;
4118
4119 switch (audit_type) {
4120 case IDC_AUDIT_TIMESTAMP:
4121 ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000);
4122 idc_audit_reg = (ha->portnum) |
4123 (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8);
4124 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
4125 break;
4126
4127 case IDC_AUDIT_COMPLETION:
4128 duration_secs = ((jiffies_to_msecs(jiffies) -
4129 jiffies_to_msecs(ha->idc_audit_ts)) / 1000);
4130 idc_audit_reg = (ha->portnum) |
4131 (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8);
4132 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
4133 break;
4134
4135 default:
4136 ql_log(ql_log_warn, vha, 0xb078,
4137 "Invalid audit type specified.\n");
4138 break;
4139 }
4140}
4141
4142/* Assumes idc_lock always held on entry */
fa492630 4143static int
7d613ac6
SV		 4144qla83xx_initiating_reset(scsi_qla_host_t *vha)
4145{
4146 struct qla_hw_data *ha = vha->hw;
4147 uint32_t idc_control, dev_state;
4148
4149 __qla83xx_get_idc_control(vha, &idc_control);
4150 if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) {
4151 ql_log(ql_log_info, vha, 0xb080,
4152 "NIC Core reset has been disabled. idc-control=0x%x\n",
4153 idc_control);
4154 return QLA_FUNCTION_FAILED;
4155 }
4156
4157 /* Set NEED-RESET iff in READY state and we are the reset-owner */
4158 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4159 if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) {
4160 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
4161 QLA8XXX_DEV_NEED_RESET);
4162 ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n");
4163 qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP);
4164 } else {
4165 const char *state = qla83xx_dev_state_to_string(dev_state);
4166 ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n", state);
4167
4168 /* SV: XXX: Is timeout required here? */
4169 /* Wait for IDC state change READY -> NEED_RESET */
4170 while (dev_state == QLA8XXX_DEV_READY) {
4171 qla83xx_idc_unlock(vha, 0);
4172 msleep(200);
4173 qla83xx_idc_lock(vha, 0);
4174 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4175 }
4176 }
4177
4178 /* Send IDC ack by writing to drv-ack register */
4179 __qla83xx_set_drv_ack(vha);
4180
4181 return QLA_SUCCESS;
4182}
4183
4184int
4185__qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control)
4186{
4187 return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
4188}
4189
7d613ac6
SV		 4190int
4191__qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control)
4192{
4193 return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
4194}
4195
fa492630 4196static int
7d613ac6
SV		 4197qla83xx_check_driver_presence(scsi_qla_host_t *vha)
4198{
4199 uint32_t drv_presence = 0;
4200 struct qla_hw_data *ha = vha->hw;
4201
4202 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4203 if (drv_presence & (1 << ha->portnum))
4204 return QLA_SUCCESS;
4205 else
4206 return QLA_TEST_FAILED;
4207}
4208
4209int
4210qla83xx_nic_core_reset(scsi_qla_host_t *vha)
4211{
4212 int rval = QLA_SUCCESS;
4213 struct qla_hw_data *ha = vha->hw;
4214
4215 ql_dbg(ql_dbg_p3p, vha, 0xb058,
4216 "Entered %s().\n", __func__);
4217
4218 if (vha->device_flags & DFLG_DEV_FAILED) {
4219 ql_log(ql_log_warn, vha, 0xb059,
4220 "Device in unrecoverable FAILED state.\n");
4221 return QLA_FUNCTION_FAILED;
4222 }
4223
4224 qla83xx_idc_lock(vha, 0);
4225
4226 if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) {
4227 ql_log(ql_log_warn, vha, 0xb05a,
4228 "Function=0x%x has been removed from IDC participation.\n",
4229 ha->portnum);
4230 rval = QLA_FUNCTION_FAILED;
4231 goto exit;
4232 }
4233
4234 qla83xx_reset_ownership(vha);
4235
4236 rval = qla83xx_initiating_reset(vha);
4237
4238 /*
4239 * Perform reset if we are the reset-owner,
4240 * else wait till IDC state changes to READY/FAILED.
4241 */
4242 if (rval == QLA_SUCCESS) {
4243 rval = qla83xx_idc_state_handler(vha);
4244
4245 if (rval == QLA_SUCCESS)
4246 ha->flags.nic_core_hung = 0;
4247 __qla83xx_clear_drv_ack(vha);
4248 }
4249
4250exit:
4251 qla83xx_idc_unlock(vha, 0);
4252
4253 ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__);
4254
4255 return rval;
4256}
4257
81178772
SK		 4258int
4259qla2xxx_mctp_dump(scsi_qla_host_t *vha)
4260{
4261 struct qla_hw_data *ha = vha->hw;
4262 int rval = QLA_FUNCTION_FAILED;
4263
4264 if (!IS_MCTP_CAPABLE(ha)) {
4265 /* This message can be removed from the final version */
4266 ql_log(ql_log_info, vha, 0x506d,
4267 "This board is not MCTP capable\n");
4268 return rval;
4269 }
4270
4271 if (!ha->mctp_dump) {
4272 ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev,
4273 MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL);
4274
4275 if (!ha->mctp_dump) {
4276 ql_log(ql_log_warn, vha, 0x506e,
4277 "Failed to allocate memory for mctp dump\n");
4278 return rval;
4279 }
4280 }
4281
4282#define MCTP_DUMP_STR_ADDR 0x00000000
4283 rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma,
4284 MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4);
4285 if (rval != QLA_SUCCESS) {
4286 ql_log(ql_log_warn, vha, 0x506f,
4287 "Failed to capture mctp dump\n");
4288 } else {
4289 ql_log(ql_log_info, vha, 0x5070,
4290 "Mctp dump capture for host (%ld/%p).\n",
4291 vha->host_no, ha->mctp_dump);
4292 ha->mctp_dumped = 1;
4293 }
4294
409ee0fe 4295 if (!ha->flags.nic_core_reset_hdlr_active && !ha->portnum) {
81178772
SK		 4296 ha->flags.nic_core_reset_hdlr_active = 1;
4297 rval = qla83xx_restart_nic_firmware(vha);
4298 if (rval)
4299 /* NIC Core reset failed. */
4300 ql_log(ql_log_warn, vha, 0x5071,
4301 "Failed to restart nic firmware\n");
4302 else
4303 ql_dbg(ql_dbg_p3p, vha, 0xb084,
4304 "Restarted NIC firmware successfully.\n");
4305 ha->flags.nic_core_reset_hdlr_active = 0;
4306 }
4307
4308 return rval;
4309
4310}
4311
579d12b5 4312/*
8fcd6b8b 4313* qla2x00_quiesce_io
579d12b5
SK		 4314* Description: This function will block the new I/Os
4315* Its not aborting any I/Os as context
4316* is not destroyed during quiescence
4317* Arguments: scsi_qla_host_t
4318* return : void
4319*/
4320void
8fcd6b8b 4321qla2x00_quiesce_io(scsi_qla_host_t *vha)
579d12b5
SK		 4322{
4323 struct qla_hw_data *ha = vha->hw;
4324 struct scsi_qla_host *vp;
4325
8fcd6b8b
CD		 4326 ql_dbg(ql_dbg_dpc, vha, 0x401d,
4327 "Quiescing I/O - ha=%p.\n", ha);
579d12b5
SK		 4328
4329 atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME);
4330 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
4331 atomic_set(&vha->loop_state, LOOP_DOWN);
4332 qla2x00_mark_all_devices_lost(vha, 0);
4333 list_for_each_entry(vp, &ha->vp_list, list)
8fcd6b8b 4334 qla2x00_mark_all_devices_lost(vp, 0);
579d12b5
SK		 4335 } else {
4336 if (!atomic_read(&vha->loop_down_timer))
4337 atomic_set(&vha->loop_down_timer,
4338 LOOP_DOWN_TIME);
4339 }
4340 /* Wait for pending cmds to complete */
4341 qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST);
4342}
4343
a9083016
GM		 4344void
4345qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
4346{
4347 struct qla_hw_data *ha = vha->hw;
579d12b5 4348 struct scsi_qla_host *vp;
feafb7b1 4349 unsigned long flags;
6aef87be 4350 fc_port_t *fcport;
a9083016 4351
e46ef004
SK		 4352 /* For ISP82XX, driver waits for completion of the commands.
4353 * online flag should be set.
4354 */
7ec0effd 4355 if (!(IS_P3P_TYPE(ha)))
e46ef004 4356 vha->flags.online = 0;
a9083016
GM		 4357 ha->flags.chip_reset_done = 0;
4358 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2be21fa2 4359 vha->qla_stats.total_isp_aborts++;
a9083016 4360
7c3df132
SK		 4361 ql_log(ql_log_info, vha, 0x00af,
4362 "Performing ISP error recovery - ha=%p.\n", ha);
a9083016 4363
e46ef004
SK		 4364 /* For ISP82XX, reset_chip is just disabling interrupts.
4365 * Driver waits for the completion of the commands.
4366 * the interrupts need to be enabled.
4367 */
7ec0effd 4368 if (!(IS_P3P_TYPE(ha)))
a9083016
GM		 4369 ha->isp_ops->reset_chip(vha);
4370
4371 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
4372 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
4373 atomic_set(&vha->loop_state, LOOP_DOWN);
4374 qla2x00_mark_all_devices_lost(vha, 0);
feafb7b1
AE		 4375
4376 spin_lock_irqsave(&ha->vport_slock, flags);
579d12b5 4377 list_for_each_entry(vp, &ha->vp_list, list) {
feafb7b1
AE		 4378 atomic_inc(&vp->vref_count);
4379 spin_unlock_irqrestore(&ha->vport_slock, flags);
4380
a9083016 4381 qla2x00_mark_all_devices_lost(vp, 0);
feafb7b1
AE		 4382
4383 spin_lock_irqsave(&ha->vport_slock, flags);
4384 atomic_dec(&vp->vref_count);
4385 }
4386 spin_unlock_irqrestore(&ha->vport_slock, flags);
a9083016
GM		 4387 } else {
4388 if (!atomic_read(&vha->loop_down_timer))
4389 atomic_set(&vha->loop_down_timer,
4390 LOOP_DOWN_TIME);
4391 }
4392
6aef87be
AV		 4393 /* Clear all async request states across all VPs. */
4394 list_for_each_entry(fcport, &vha->vp_fcports, list)
4395 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
4396 spin_lock_irqsave(&ha->vport_slock, flags);
4397 list_for_each_entry(vp, &ha->vp_list, list) {
4398 atomic_inc(&vp->vref_count);
4399 spin_unlock_irqrestore(&ha->vport_slock, flags);
4400
4401 list_for_each_entry(fcport, &vp->vp_fcports, list)
4402 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
4403
4404 spin_lock_irqsave(&ha->vport_slock, flags);
4405 atomic_dec(&vp->vref_count);
4406 }
4407 spin_unlock_irqrestore(&ha->vport_slock, flags);
4408
bddd2d65
LC		 4409 if (!ha->flags.eeh_busy) {
4410 /* Make sure for ISP 82XX IO DMA is complete */
7ec0effd 4411 if (IS_P3P_TYPE(ha)) {
7190575f 4412 qla82xx_chip_reset_cleanup(vha);
7c3df132
SK		 4413 ql_log(ql_log_info, vha, 0x00b4,
4414 "Done chip reset cleanup.\n");
a9083016 4415
e46ef004
SK		 4416 /* Done waiting for pending commands.
4417 * Reset the online flag.
4418 */
4419 vha->flags.online = 0;
4d78c973 4420 }
a9083016 4421
bddd2d65
LC		 4422 /* Requeue all commands in outstanding command list. */
4423 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
4424 }
a9083016
GM		 4425}
4426
1da177e4
LT		 4427/*
4428* qla2x00_abort_isp
4429* Resets ISP and aborts all outstanding commands.
4430*
4431* Input:
4432* ha = adapter block pointer.
4433*
4434* Returns:
4435* 0 = success
4436*/
4437int
e315cd28 4438qla2x00_abort_isp(scsi_qla_host_t *vha)
1da177e4 4439{
476e8978 4440 int rval;
1da177e4 4441 uint8_t status = 0;
e315cd28
AC		 4442 struct qla_hw_data *ha = vha->hw;
4443 struct scsi_qla_host *vp;
73208dfd 4444 struct req_que *req = ha->req_q_map[0];
feafb7b1 4445 unsigned long flags;
1da177e4 4446
e315cd28 4447 if (vha->flags.online) {
a9083016 4448 qla2x00_abort_isp_cleanup(vha);
1da177e4 4449
a6171297
SV		 4450 if (IS_QLA8031(ha)) {
4451 ql_dbg(ql_dbg_p3p, vha, 0xb05c,
4452 "Clearing fcoe driver presence.\n");
4453 if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS)
4454 ql_dbg(ql_dbg_p3p, vha, 0xb073,
4455 "Error while clearing DRV-Presence.\n");
4456 }
4457
85880801
AV		 4458 if (unlikely(pci_channel_offline(ha->pdev) &&
4459 ha->flags.pci_channel_io_perm_failure)) {
4460 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
4461 status = 0;
4462 return status;
4463 }
4464
73208dfd 4465 ha->isp_ops->get_flash_version(vha, req->ring);
30c47662 4466
e315cd28 4467 ha->isp_ops->nvram_config(vha);
1da177e4 4468
e315cd28
AC		 4469 if (!qla2x00_restart_isp(vha)) {
4470 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4 4471
e315cd28 4472 if (!atomic_read(&vha->loop_down_timer)) {
1da177e4
LT		 4473 /*
4474 * Issue marker command only when we are going
4475 * to start the I/O .
4476 */
e315cd28 4477 vha->marker_needed = 1;
1da177e4
LT		 4478 }
4479
e315cd28 4480 vha->flags.online = 1;
1da177e4 4481
fd34f556 4482 ha->isp_ops->enable_intrs(ha);
1da177e4 4483
fa2a1ce5 4484 ha->isp_abort_cnt = 0;
e315cd28 4485 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
476e8978 4486
6246b8a1
GM		 4487 if (IS_QLA81XX(ha) || IS_QLA8031(ha))
4488 qla2x00_get_fw_version(vha);
df613b96
AV		 4489 if (ha->fce) {
4490 ha->flags.fce_enabled = 1;
4491 memset(ha->fce, 0,
4492 fce_calc_size(ha->fce_bufs));
e315cd28 4493 rval = qla2x00_enable_fce_trace(vha,
df613b96
AV		 4494 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
4495 &ha->fce_bufs);
4496 if (rval) {
7c3df132 4497 ql_log(ql_log_warn, vha, 0x8033,
df613b96
AV		 4498 "Unable to reinitialize FCE "
4499 "(%d).\n", rval);
4500 ha->flags.fce_enabled = 0;
4501 }
4502 }
436a7b11
AV		 4503
4504 if (ha->eft) {
4505 memset(ha->eft, 0, EFT_SIZE);
e315cd28 4506 rval = qla2x00_enable_eft_trace(vha,
436a7b11
AV		 4507 ha->eft_dma, EFT_NUM_BUFFERS);
4508 if (rval) {
7c3df132 4509 ql_log(ql_log_warn, vha, 0x8034,
436a7b11
AV		 4510 "Unable to reinitialize EFT "
4511 "(%d).\n", rval);
4512 }
4513 }
1da177e4 4514 } else { /* failed the ISP abort */
e315cd28
AC		 4515 vha->flags.online = 1;
4516 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
1da177e4 4517 if (ha->isp_abort_cnt == 0) {
7c3df132
SK		 4518 ql_log(ql_log_fatal, vha, 0x8035,
4519 "ISP error recover failed - "
4520 "board disabled.\n");
fa2a1ce5 4521 /*
1da177e4
LT		 4522 * The next call disables the board
4523 * completely.
4524 */
e315cd28
AC		 4525 ha->isp_ops->reset_adapter(vha);
4526 vha->flags.online = 0;
1da177e4 4527 clear_bit(ISP_ABORT_RETRY,
e315cd28 4528 &vha->dpc_flags);
1da177e4
LT		 4529 status = 0;
4530 } else { /* schedule another ISP abort */
4531 ha->isp_abort_cnt--;
7c3df132
SK		 4532 ql_dbg(ql_dbg_taskm, vha, 0x8020,
4533 "ISP abort - retry remaining %d.\n",
4534 ha->isp_abort_cnt);
1da177e4
LT		 4535 status = 1;
4536 }
4537 } else {
4538 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
7c3df132
SK		 4539 ql_dbg(ql_dbg_taskm, vha, 0x8021,
4540 "ISP error recovery - retrying (%d) "
4541 "more times.\n", ha->isp_abort_cnt);
e315cd28 4542 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
1da177e4
LT		 4543 status = 1;
4544 }
4545 }
fa2a1ce5 4546
1da177e4
LT		 4547 }
4548
e315cd28 4549 if (!status) {
7c3df132 4550 ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__);
feafb7b1
AE		 4551
4552 spin_lock_irqsave(&ha->vport_slock, flags);
4553 list_for_each_entry(vp, &ha->vp_list, list) {
4554 if (vp->vp_idx) {
4555 atomic_inc(&vp->vref_count);
4556 spin_unlock_irqrestore(&ha->vport_slock, flags);
4557
e315cd28 4558 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 4559
4560 spin_lock_irqsave(&ha->vport_slock, flags);
4561 atomic_dec(&vp->vref_count);
4562 }
e315cd28 4563 }
feafb7b1
AE		 4564 spin_unlock_irqrestore(&ha->vport_slock, flags);
4565
7d613ac6
SV		 4566 if (IS_QLA8031(ha)) {
4567 ql_dbg(ql_dbg_p3p, vha, 0xb05d,
4568 "Setting back fcoe driver presence.\n");
4569 if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS)
4570 ql_dbg(ql_dbg_p3p, vha, 0xb074,
4571 "Error while setting DRV-Presence.\n");
4572 }
e315cd28 4573 } else {
d8424f68
JP		 4574 ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n",
4575 __func__);
1da177e4
LT		 4576 }
4577
4578 return(status);
4579}
4580
4581/*
4582* qla2x00_restart_isp
4583* restarts the ISP after a reset
4584*
4585* Input:
4586* ha = adapter block pointer.
4587*
4588* Returns:
4589* 0 = success
4590*/
4591static int
e315cd28 4592qla2x00_restart_isp(scsi_qla_host_t *vha)
1da177e4 4593{
c6b2fca8 4594 int status = 0;
1da177e4 4595 uint32_t wait_time;
e315cd28 4596 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 4597 struct req_que *req = ha->req_q_map[0];
4598 struct rsp_que *rsp = ha->rsp_q_map[0];
2d70c103 4599 unsigned long flags;
1da177e4
LT		 4600
4601 /* If firmware needs to be loaded */
e315cd28
AC		 4602 if (qla2x00_isp_firmware(vha)) {
4603 vha->flags.online = 0;
4604 status = ha->isp_ops->chip_diag(vha);
4605 if (!status)
4606 status = qla2x00_setup_chip(vha);
1da177e4
LT		 4607 }
4608
e315cd28
AC		 4609 if (!status && !(status = qla2x00_init_rings(vha))) {
4610 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
2533cf67 4611 ha->flags.chip_reset_done = 1;
73208dfd
AC		 4612 /* Initialize the queues in use */
4613 qla25xx_init_queues(ha);
4614
e315cd28
AC		 4615 status = qla2x00_fw_ready(vha);
4616 if (!status) {
7c3df132
SK		 4617 ql_dbg(ql_dbg_taskm, vha, 0x8031,
4618 "Start configure loop status = %d.\n", status);
0107109e
AV		 4619
4620 /* Issue a marker after FW becomes ready. */
73208dfd 4621 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
0107109e 4622
e315cd28 4623 vha->flags.online = 1;
2d70c103
NB		 4624
4625 /*
4626 * Process any ATIO queue entries that came in
4627 * while we weren't online.
4628 */
4629 spin_lock_irqsave(&ha->hardware_lock, flags);
4630 if (qla_tgt_mode_enabled(vha))
4631 qlt_24xx_process_atio_queue(vha);
4632 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4633
1da177e4
LT		 4634 /* Wait at most MAX_TARGET RSCNs for a stable link. */
4635 wait_time = 256;
4636 do {
e315cd28
AC		 4637 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
4638 qla2x00_configure_loop(vha);
1da177e4 4639 wait_time--;
e315cd28
AC		 4640 } while (!atomic_read(&vha->loop_down_timer) &&
4641 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
4642 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
4643 &vha->dpc_flags)));
1da177e4
LT		 4644 }
4645
4646 /* if no cable then assume it's good */
e315cd28 4647 if ((vha->device_flags & DFLG_NO_CABLE))
1da177e4
LT		 4648 status = 0;
4649
7c3df132
SK		 4650 ql_dbg(ql_dbg_taskm, vha, 0x8032,
4651 "Configure loop done, status = 0x%x.\n", status);
1da177e4
LT		 4652 }
4653 return (status);
4654}
4655
73208dfd
AC		 4656static int
4657qla25xx_init_queues(struct qla_hw_data *ha)
4658{
4659 struct rsp_que *rsp = NULL;
4660 struct req_que *req = NULL;
4661 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
4662 int ret = -1;
4663 int i;
4664
2afa19a9 4665 for (i = 1; i < ha->max_rsp_queues; i++) {
73208dfd
AC		 4666 rsp = ha->rsp_q_map[i];
4667 if (rsp) {
4668 rsp->options &= ~BIT_0;
618a7523 4669 ret = qla25xx_init_rsp_que(base_vha, rsp);
73208dfd 4670 if (ret != QLA_SUCCESS)
7c3df132
SK		 4671 ql_dbg(ql_dbg_init, base_vha, 0x00ff,
4672 "%s Rsp que: %d init failed.\n",
4673 __func__, rsp->id);
73208dfd 4674 else
7c3df132
SK		 4675 ql_dbg(ql_dbg_init, base_vha, 0x0100,
4676 "%s Rsp que: %d inited.\n",
4677 __func__, rsp->id);
73208dfd 4678 }
2afa19a9
AC		 4679 }
4680 for (i = 1; i < ha->max_req_queues; i++) {
73208dfd
AC		 4681 req = ha->req_q_map[i];
4682 if (req) {
29bdccbe 4683 /* Clear outstanding commands array. */
73208dfd 4684 req->options &= ~BIT_0;
618a7523 4685 ret = qla25xx_init_req_que(base_vha, req);
73208dfd 4686 if (ret != QLA_SUCCESS)
7c3df132
SK		 4687 ql_dbg(ql_dbg_init, base_vha, 0x0101,
4688 "%s Req que: %d init failed.\n",
4689 __func__, req->id);
73208dfd 4690 else
7c3df132
SK		 4691 ql_dbg(ql_dbg_init, base_vha, 0x0102,
4692 "%s Req que: %d inited.\n",
4693 __func__, req->id);
73208dfd
AC		 4694 }
4695 }
4696 return ret;
4697}
4698
1da177e4
LT		 4699/*
4700* qla2x00_reset_adapter
4701* Reset adapter.
4702*
4703* Input:
4704* ha = adapter block pointer.
4705*/
abbd8870 4706void
e315cd28 4707qla2x00_reset_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 4708{
4709 unsigned long flags = 0;
e315cd28 4710 struct qla_hw_data *ha = vha->hw;
3d71644c 4711 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 4712
e315cd28 4713 vha->flags.online = 0;
fd34f556 4714 ha->isp_ops->disable_intrs(ha);
1da177e4 4715
1da177e4
LT		 4716 spin_lock_irqsave(&ha->hardware_lock, flags);
4717 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
4718 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
4719 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
4720 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
4721 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4722}
0107109e
AV		 4723
4724void
e315cd28 4725qla24xx_reset_adapter(scsi_qla_host_t *vha)
0107109e
AV		 4726{
4727 unsigned long flags = 0;
e315cd28 4728 struct qla_hw_data *ha = vha->hw;
0107109e
AV		 4729 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
4730
7ec0effd 4731 if (IS_P3P_TYPE(ha))
a9083016
GM		 4732 return;
4733
e315cd28 4734 vha->flags.online = 0;
fd34f556 4735 ha->isp_ops->disable_intrs(ha);
0107109e
AV		 4736
4737 spin_lock_irqsave(&ha->hardware_lock, flags);
4738 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
4739 RD_REG_DWORD(&reg->hccr);
4740 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
4741 RD_REG_DWORD(&reg->hccr);
4742 spin_unlock_irqrestore(&ha->hardware_lock, flags);
09ff36d3
AV		 4743
4744 if (IS_NOPOLLING_TYPE(ha))
4745 ha->isp_ops->enable_intrs(ha);
0107109e
AV		 4746}
4747
4e08df3f
DM		 4748/* On sparc systems, obtain port and node WWN from firmware
4749 * properties.
4750 */
e315cd28
AC		 4751static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha,
4752 struct nvram_24xx *nv)
4e08df3f
DM		 4753{
4754#ifdef CONFIG_SPARC
e315cd28 4755 struct qla_hw_data *ha = vha->hw;
4e08df3f 4756 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 4757 struct device_node *dp = pci_device_to_OF_node(pdev);
4758 const u8 *val;
4e08df3f
DM		 4759 int len;
4760
4761 val = of_get_property(dp, "port-wwn", &len);
4762 if (val && len >= WWN_SIZE)
4763 memcpy(nv->port_name, val, WWN_SIZE);
4764
4765 val = of_get_property(dp, "node-wwn", &len);
4766 if (val && len >= WWN_SIZE)
4767 memcpy(nv->node_name, val, WWN_SIZE);
4768#endif
4769}
4770
0107109e 4771int
e315cd28 4772qla24xx_nvram_config(scsi_qla_host_t *vha)
0107109e 4773{
4e08df3f 4774 int rval;
0107109e
AV		 4775 struct init_cb_24xx *icb;
4776 struct nvram_24xx *nv;
4777 uint32_t *dptr;
4778 uint8_t *dptr1, *dptr2;
4779 uint32_t chksum;
4780 uint16_t cnt;
e315cd28 4781 struct qla_hw_data *ha = vha->hw;
0107109e 4782
4e08df3f 4783 rval = QLA_SUCCESS;
0107109e 4784 icb = (struct init_cb_24xx *)ha->init_cb;
281afe19 4785 nv = ha->nvram;
0107109e
AV		 4786
4787 /* Determine NVRAM starting address. */
e5b68a61
AC		 4788 if (ha->flags.port0) {
4789 ha->nvram_base = FA_NVRAM_FUNC0_ADDR;
4790 ha->vpd_base = FA_NVRAM_VPD0_ADDR;
4791 } else {
0107109e 4792 ha->nvram_base = FA_NVRAM_FUNC1_ADDR;
6f641790
AV		 4793 ha->vpd_base = FA_NVRAM_VPD1_ADDR;
4794 }
e5b68a61
AC		 4795 ha->nvram_size = sizeof(struct nvram_24xx);
4796 ha->vpd_size = FA_NVRAM_VPD_SIZE;
0107109e 4797
281afe19
SJ		 4798 /* Get VPD data into cache */
4799 ha->vpd = ha->nvram + VPD_OFFSET;
e315cd28 4800 ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd,
281afe19
SJ		 4801 ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
4802
4803 /* Get NVRAM data into cache and calculate checksum. */
0107109e 4804 dptr = (uint32_t *)nv;
e315cd28 4805 ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base,
0107109e
AV		 4806 ha->nvram_size);
4807 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
4808 chksum += le32_to_cpu(*dptr++);
4809
7c3df132
SK		 4810 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
4811 "Contents of NVRAM\n");
4812 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
4813 (uint8_t *)nv, ha->nvram_size);
0107109e
AV		 4814
4815 /* Bad NVRAM data, set defaults parameters. */
4816 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
4817 || nv->id[3] != ' ' ||
4818 nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
4819 /* Reset NVRAM data. */
7c3df132 4820 ql_log(ql_log_warn, vha, 0x006b,
9e336520 4821 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132
SK		 4822 "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version);
4823 ql_log(ql_log_warn, vha, 0x006c,
4824 "Falling back to functioning (yet invalid -- WWPN) "
4825 "defaults.\n");
4e08df3f
DM		 4826
4827 /*
4828 * Set default initialization control block.
4829 */
4830 memset(nv, 0, ha->nvram_size);
4831 nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
4832 nv->version = __constant_cpu_to_le16(ICB_VERSION);
4833 nv->frame_payload_size = __constant_cpu_to_le16(2048);
4834 nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
4835 nv->exchange_count = __constant_cpu_to_le16(0);
4836 nv->hard_address = __constant_cpu_to_le16(124);
4837 nv->port_name[0] = 0x21;
e5b68a61 4838 nv->port_name[1] = 0x00 + ha->port_no;
4e08df3f
DM		 4839 nv->port_name[2] = 0x00;
4840 nv->port_name[3] = 0xe0;
4841 nv->port_name[4] = 0x8b;
4842 nv->port_name[5] = 0x1c;
4843 nv->port_name[6] = 0x55;
4844 nv->port_name[7] = 0x86;
4845 nv->node_name[0] = 0x20;
4846 nv->node_name[1] = 0x00;
4847 nv->node_name[2] = 0x00;
4848 nv->node_name[3] = 0xe0;
4849 nv->node_name[4] = 0x8b;
4850 nv->node_name[5] = 0x1c;
4851 nv->node_name[6] = 0x55;
4852 nv->node_name[7] = 0x86;
e315cd28 4853 qla24xx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 4854 nv->login_retry_count = __constant_cpu_to_le16(8);
4855 nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
4856 nv->login_timeout = __constant_cpu_to_le16(0);
4857 nv->firmware_options_1 =
4858 __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
4859 nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
4860 nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
4861 nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
4862 nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
4863 nv->efi_parameters = __constant_cpu_to_le32(0);
4864 nv->reset_delay = 5;
4865 nv->max_luns_per_target = __constant_cpu_to_le16(128);
4866 nv->port_down_retry_count = __constant_cpu_to_le16(30);
4867 nv->link_down_timeout = __constant_cpu_to_le16(30);
4868
4869 rval = 1;
0107109e
AV		 4870 }
4871
2d70c103
NB		 4872 if (!qla_ini_mode_enabled(vha)) {
4873 /* Don't enable full login after initial LIP */
4874 nv->firmware_options_1 &= __constant_cpu_to_le32(~BIT_13);
4875 /* Don't enable LIP full login for initiator */
4876 nv->host_p &= __constant_cpu_to_le32(~BIT_10);
4877 }
4878
4879 qlt_24xx_config_nvram_stage1(vha, nv);
4880
0107109e 4881 /* Reset Initialization control block */
e315cd28 4882 memset(icb, 0, ha->init_cb_size);
0107109e
AV		 4883
4884 /* Copy 1st segment. */
4885 dptr1 = (uint8_t *)icb;
4886 dptr2 = (uint8_t *)&nv->version;
4887 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
4888 while (cnt--)
4889 *dptr1++ = *dptr2++;
4890
4891 icb->login_retry_count = nv->login_retry_count;
3ea66e28 4892 icb->link_down_on_nos = nv->link_down_on_nos;
0107109e
AV		 4893
4894 /* Copy 2nd segment. */
4895 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
4896 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
4897 cnt = (uint8_t *)&icb->reserved_3 -
4898 (uint8_t *)&icb->interrupt_delay_timer;
4899 while (cnt--)
4900 *dptr1++ = *dptr2++;
4901
4902 /*
4903 * Setup driver NVRAM options.
4904 */
e315cd28 4905 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
9bb9fcf2 4906 "QLA2462");
0107109e 4907
2d70c103
NB		 4908 qlt_24xx_config_nvram_stage2(vha, icb);
4909
5341e868 4910 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
2d70c103 4911 /* Use alternate WWN? */
5341e868
AV		 4912 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
4913 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
4914 }
4915
0107109e 4916 /* Prepare nodename */
fd0e7e4d 4917 if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
0107109e
AV		 4918 /*
4919 * Firmware will apply the following mask if the nodename was
4920 * not provided.
4921 */
4922 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
4923 icb->node_name[0] &= 0xF0;
4924 }
4925
4926 /* Set host adapter parameters. */
4927 ha->flags.disable_risc_code_load = 0;
0c8c39af
AV		 4928 ha->flags.enable_lip_reset = 0;
4929 ha->flags.enable_lip_full_login =
4930 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
4931 ha->flags.enable_target_reset =
4932 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
0107109e 4933 ha->flags.enable_led_scheme = 0;
d4c760c2 4934 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
0107109e 4935
fd0e7e4d
AV		 4936 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
4937 (BIT_6 | BIT_5 | BIT_4)) >> 4;
0107109e
AV		 4938
4939 memcpy(ha->fw_seriallink_options24, nv->seriallink_options,
4940 sizeof(ha->fw_seriallink_options24));
4941
4942 /* save HBA serial number */
4943 ha->serial0 = icb->port_name[5];
4944 ha->serial1 = icb->port_name[6];
4945 ha->serial2 = icb->port_name[7];
e315cd28
AC		 4946 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
4947 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
0107109e 4948
bc8fb3cb
AV		 4949 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
4950
0107109e
AV		 4951 ha->retry_count = le16_to_cpu(nv->login_retry_count);
4952
4953 /* Set minimum login_timeout to 4 seconds. */
4954 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
4955 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
4956 if (le16_to_cpu(nv->login_timeout) < 4)
4957 nv->login_timeout = __constant_cpu_to_le16(4);
4958 ha->login_timeout = le16_to_cpu(nv->login_timeout);
c6852c4c 4959 icb->login_timeout = nv->login_timeout;
0107109e 4960
00a537b8
AV		 4961 /* Set minimum RATOV to 100 tenths of a second. */
4962 ha->r_a_tov = 100;
0107109e
AV		 4963
4964 ha->loop_reset_delay = nv->reset_delay;
4965
4966 /* Link Down Timeout = 0:
4967 *
4968 * When Port Down timer expires we will start returning
4969 * I/O's to OS with "DID_NO_CONNECT".
4970 *
4971 * Link Down Timeout != 0:
4972 *
4973 * The driver waits for the link to come up after link down
4974 * before returning I/Os to OS with "DID_NO_CONNECT".
4975 */
4976 if (le16_to_cpu(nv->link_down_timeout) == 0) {
4977 ha->loop_down_abort_time =
4978 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
4979 } else {
4980 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
4981 ha->loop_down_abort_time =
4982 (LOOP_DOWN_TIME - ha->link_down_timeout);
4983 }
4984
4985 /* Need enough time to try and get the port back. */
4986 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
4987 if (qlport_down_retry)
4988 ha->port_down_retry_count = qlport_down_retry;
4989
4990 /* Set login_retry_count */
4991 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
4992 if (ha->port_down_retry_count ==
4993 le16_to_cpu(nv->port_down_retry_count) &&
4994 ha->port_down_retry_count > 3)
4995 ha->login_retry_count = ha->port_down_retry_count;
4996 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
4997 ha->login_retry_count = ha->port_down_retry_count;
4998 if (ql2xloginretrycount)
4999 ha->login_retry_count = ql2xloginretrycount;
5000
4fdfefe5 5001 /* Enable ZIO. */
e315cd28 5002 if (!vha->flags.init_done) {
4fdfefe5
AV		 5003 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
5004 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
5005 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
5006 le16_to_cpu(icb->interrupt_delay_timer): 2;
5007 }
5008 icb->firmware_options_2 &= __constant_cpu_to_le32(
5009 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
e315cd28 5010 vha->flags.process_response_queue = 0;
4fdfefe5 5011 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d
AV		 5012 ha->zio_mode = QLA_ZIO_MODE_6;
5013
7c3df132 5014 ql_log(ql_log_info, vha, 0x006f,
4fdfefe5
AV		 5015 "ZIO mode %d enabled; timer delay (%d us).\n",
5016 ha->zio_mode, ha->zio_timer * 100);
5017
5018 icb->firmware_options_2 |= cpu_to_le32(
5019 (uint32_t)ha->zio_mode);
5020 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
e315cd28 5021 vha->flags.process_response_queue = 1;
4fdfefe5
AV		 5022 }
5023
4e08df3f 5024 if (rval) {
7c3df132
SK		 5025 ql_log(ql_log_warn, vha, 0x0070,
5026 "NVRAM configuration failed.\n");
4e08df3f
DM		 5027 }
5028 return (rval);
0107109e
AV		 5029}
5030
413975a0 5031static int
cbc8eb67
AV		 5032qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
5033 uint32_t faddr)
d1c61909 5034{
73208dfd 5035 int rval = QLA_SUCCESS;
d1c61909 5036 int segments, fragment;
d1c61909
AV		 5037 uint32_t *dcode, dlen;
5038 uint32_t risc_addr;
5039 uint32_t risc_size;
5040 uint32_t i;
e315cd28 5041 struct qla_hw_data *ha = vha->hw;
73208dfd 5042 struct req_que *req = ha->req_q_map[0];
eaac30be 5043
7c3df132 5044 ql_dbg(ql_dbg_init, vha, 0x008b,
cfb0919c 5045 "FW: Loading firmware from flash (%x).\n", faddr);
eaac30be 5046
d1c61909
AV		 5047 rval = QLA_SUCCESS;
5048
5049 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 5050 dcode = (uint32_t *)req->ring;
d1c61909
AV		 5051 *srisc_addr = 0;
5052
5053 /* Validate firmware image by checking version. */
e315cd28 5054 qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
d1c61909
AV		 5055 for (i = 0; i < 4; i++)
5056 dcode[i] = be32_to_cpu(dcode[i]);
5057 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
5058 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
5059 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
5060 dcode[3] == 0)) {
7c3df132
SK		 5061 ql_log(ql_log_fatal, vha, 0x008c,
5062 "Unable to verify the integrity of flash firmware "
5063 "image.\n");
5064 ql_log(ql_log_fatal, vha, 0x008d,
5065 "Firmware data: %08x %08x %08x %08x.\n",
5066 dcode[0], dcode[1], dcode[2], dcode[3]);
d1c61909
AV		 5067
5068 return QLA_FUNCTION_FAILED;
5069 }
5070
5071 while (segments && rval == QLA_SUCCESS) {
5072 /* Read segment's load information. */
e315cd28 5073 qla24xx_read_flash_data(vha, dcode, faddr, 4);
d1c61909
AV		 5074
5075 risc_addr = be32_to_cpu(dcode[2]);
5076 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
5077 risc_size = be32_to_cpu(dcode[3]);
5078
5079 fragment = 0;
5080 while (risc_size > 0 && rval == QLA_SUCCESS) {
5081 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
5082 if (dlen > risc_size)
5083 dlen = risc_size;
5084
7c3df132
SK		 5085 ql_dbg(ql_dbg_init, vha, 0x008e,
5086 "Loading risc segment@ risc addr %x "
5087 "number of dwords 0x%x offset 0x%x.\n",
5088 risc_addr, dlen, faddr);
d1c61909 5089
e315cd28 5090 qla24xx_read_flash_data(vha, dcode, faddr, dlen);
d1c61909
AV		 5091 for (i = 0; i < dlen; i++)
5092 dcode[i] = swab32(dcode[i]);
5093
73208dfd 5094 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
d1c61909
AV		 5095 dlen);
5096 if (rval) {
7c3df132
SK		 5097 ql_log(ql_log_fatal, vha, 0x008f,
5098 "Failed to load segment %d of firmware.\n",
5099 fragment);
d1c61909
AV		 5100 break;
5101 }
5102
5103 faddr += dlen;
5104 risc_addr += dlen;
5105 risc_size -= dlen;
5106 fragment++;
5107 }
5108
5109 /* Next segment. */
5110 segments--;
5111 }
5112
5113 return rval;
5114}
5115
e9454a88 5116#define QLA_FW_URL "http://ldriver.qlogic.com/firmware/"
d1c61909 5117
0107109e 5118int
e315cd28 5119qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5433383e
AV		 5120{
5121 int rval;
5122 int i, fragment;
5123 uint16_t *wcode, *fwcode;
5124 uint32_t risc_addr, risc_size, fwclen, wlen, *seg;
5125 struct fw_blob *blob;
e315cd28 5126 struct qla_hw_data *ha = vha->hw;
73208dfd 5127 struct req_que *req = ha->req_q_map[0];
5433383e
AV		 5128
5129 /* Load firmware blob. */
e315cd28 5130 blob = qla2x00_request_firmware(vha);
5433383e 5131 if (!blob) {
7c3df132
SK		 5132 ql_log(ql_log_info, vha, 0x0083,
5133 "Fimware image unavailable.\n");
5134 ql_log(ql_log_info, vha, 0x0084,
5135 "Firmware images can be retrieved from: "QLA_FW_URL ".\n");
5433383e
AV		 5136 return QLA_FUNCTION_FAILED;
5137 }
5138
5139 rval = QLA_SUCCESS;
5140
73208dfd 5141 wcode = (uint16_t *)req->ring;
5433383e
AV		 5142 *srisc_addr = 0;
5143 fwcode = (uint16_t *)blob->fw->data;
5144 fwclen = 0;
5145
5146 /* Validate firmware image by checking version. */
5147 if (blob->fw->size < 8 * sizeof(uint16_t)) {
7c3df132
SK		 5148 ql_log(ql_log_fatal, vha, 0x0085,
5149 "Unable to verify integrity of firmware image (%Zd).\n",
5433383e
AV		 5150 blob->fw->size);
5151 goto fail_fw_integrity;
5152 }
5153 for (i = 0; i < 4; i++)
5154 wcode[i] = be16_to_cpu(fwcode[i + 4]);
5155 if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff &&
5156 wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 &&
5157 wcode[2] == 0 && wcode[3] == 0)) {
7c3df132
SK		 5158 ql_log(ql_log_fatal, vha, 0x0086,
5159 "Unable to verify integrity of firmware image.\n");
5160 ql_log(ql_log_fatal, vha, 0x0087,
5161 "Firmware data: %04x %04x %04x %04x.\n",
5162 wcode[0], wcode[1], wcode[2], wcode[3]);
5433383e
AV		 5163 goto fail_fw_integrity;
5164 }
5165
5166 seg = blob->segs;
5167 while (*seg && rval == QLA_SUCCESS) {
5168 risc_addr = *seg;
5169 *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr;
5170 risc_size = be16_to_cpu(fwcode[3]);
5171
5172 /* Validate firmware image size. */
5173 fwclen += risc_size * sizeof(uint16_t);
5174 if (blob->fw->size < fwclen) {
7c3df132 5175 ql_log(ql_log_fatal, vha, 0x0088,
5433383e 5176 "Unable to verify integrity of firmware image "
7c3df132 5177 "(%Zd).\n", blob->fw->size);
5433383e
AV		 5178 goto fail_fw_integrity;
5179 }
5180
5181 fragment = 0;
5182 while (risc_size > 0 && rval == QLA_SUCCESS) {
5183 wlen = (uint16_t)(ha->fw_transfer_size >> 1);
5184 if (wlen > risc_size)
5185 wlen = risc_size;
7c3df132
SK		 5186 ql_dbg(ql_dbg_init, vha, 0x0089,
5187 "Loading risc segment@ risc addr %x number of "
5188 "words 0x%x.\n", risc_addr, wlen);
5433383e
AV		 5189
5190 for (i = 0; i < wlen; i++)
5191 wcode[i] = swab16(fwcode[i]);
5192
73208dfd 5193 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
5433383e
AV		 5194 wlen);
5195 if (rval) {
7c3df132
SK		 5196 ql_log(ql_log_fatal, vha, 0x008a,
5197 "Failed to load segment %d of firmware.\n",
5198 fragment);
5433383e
AV		 5199 break;
5200 }
5201
5202 fwcode += wlen;
5203 risc_addr += wlen;
5204 risc_size -= wlen;
5205 fragment++;
5206 }
5207
5208 /* Next segment. */
5209 seg++;
5210 }
5211 return rval;
5212
5213fail_fw_integrity:
5214 return QLA_FUNCTION_FAILED;
5215}
5216
eaac30be
AV		 5217static int
5218qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
0107109e
AV		 5219{
5220 int rval;
5221 int segments, fragment;
5222 uint32_t *dcode, dlen;
5223 uint32_t risc_addr;
5224 uint32_t risc_size;
5225 uint32_t i;
5433383e 5226 struct fw_blob *blob;
0107109e 5227 uint32_t *fwcode, fwclen;
e315cd28 5228 struct qla_hw_data *ha = vha->hw;
73208dfd 5229 struct req_que *req = ha->req_q_map[0];
0107109e 5230
5433383e 5231 /* Load firmware blob. */
e315cd28 5232 blob = qla2x00_request_firmware(vha);
5433383e 5233 if (!blob) {
7c3df132
SK		 5234 ql_log(ql_log_warn, vha, 0x0090,
5235 "Fimware image unavailable.\n");
5236 ql_log(ql_log_warn, vha, 0x0091,
5237 "Firmware images can be retrieved from: "
5238 QLA_FW_URL ".\n");
d1c61909 5239
eaac30be 5240 return QLA_FUNCTION_FAILED;
0107109e
AV		 5241 }
5242
cfb0919c
CD		 5243 ql_dbg(ql_dbg_init, vha, 0x0092,
5244 "FW: Loading via request-firmware.\n");
eaac30be 5245
0107109e
AV		 5246 rval = QLA_SUCCESS;
5247
5248 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 5249 dcode = (uint32_t *)req->ring;
0107109e 5250 *srisc_addr = 0;
5433383e 5251 fwcode = (uint32_t *)blob->fw->data;
0107109e
AV		 5252 fwclen = 0;
5253
5254 /* Validate firmware image by checking version. */
5433383e 5255 if (blob->fw->size < 8 * sizeof(uint32_t)) {
7c3df132
SK		 5256 ql_log(ql_log_fatal, vha, 0x0093,
5257 "Unable to verify integrity of firmware image (%Zd).\n",
5433383e 5258 blob->fw->size);
0107109e
AV		 5259 goto fail_fw_integrity;
5260 }
5261 for (i = 0; i < 4; i++)
5262 dcode[i] = be32_to_cpu(fwcode[i + 4]);
5263 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
5264 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
5265 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
5266 dcode[3] == 0)) {
7c3df132
SK		 5267 ql_log(ql_log_fatal, vha, 0x0094,
5268 "Unable to verify integrity of firmware image (%Zd).\n",
5269 blob->fw->size);
5270 ql_log(ql_log_fatal, vha, 0x0095,
5271 "Firmware data: %08x %08x %08x %08x.\n",
5272 dcode[0], dcode[1], dcode[2], dcode[3]);
0107109e
AV		 5273 goto fail_fw_integrity;
5274 }
5275
5276 while (segments && rval == QLA_SUCCESS) {
5277 risc_addr = be32_to_cpu(fwcode[2]);
5278 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
5279 risc_size = be32_to_cpu(fwcode[3]);
5280
5281 /* Validate firmware image size. */
5282 fwclen += risc_size * sizeof(uint32_t);
5433383e 5283 if (blob->fw->size < fwclen) {
7c3df132 5284 ql_log(ql_log_fatal, vha, 0x0096,
5433383e 5285 "Unable to verify integrity of firmware image "
7c3df132 5286 "(%Zd).\n", blob->fw->size);
5433383e 5287
0107109e
AV		 5288 goto fail_fw_integrity;
5289 }
5290
5291 fragment = 0;
5292 while (risc_size > 0 && rval == QLA_SUCCESS) {
5293 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
5294 if (dlen > risc_size)
5295 dlen = risc_size;
5296
7c3df132
SK		 5297 ql_dbg(ql_dbg_init, vha, 0x0097,
5298 "Loading risc segment@ risc addr %x "
5299 "number of dwords 0x%x.\n", risc_addr, dlen);
0107109e
AV		 5300
5301 for (i = 0; i < dlen; i++)
5302 dcode[i] = swab32(fwcode[i]);
5303
73208dfd 5304 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
590f98e5 5305 dlen);
0107109e 5306 if (rval) {
7c3df132
SK		 5307 ql_log(ql_log_fatal, vha, 0x0098,
5308 "Failed to load segment %d of firmware.\n",
5309 fragment);
0107109e
AV		 5310 break;
5311 }
5312
5313 fwcode += dlen;
5314 risc_addr += dlen;
5315 risc_size -= dlen;
5316 fragment++;
5317 }
5318
5319 /* Next segment. */
5320 segments--;
5321 }
0107109e
AV		 5322 return rval;
5323
5324fail_fw_integrity:
0107109e 5325 return QLA_FUNCTION_FAILED;
0107109e 5326}
18c6c127 5327
eaac30be
AV		 5328int
5329qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5330{
5331 int rval;
5332
e337d907
AV		 5333 if (ql2xfwloadbin == 1)
5334 return qla81xx_load_risc(vha, srisc_addr);
5335
eaac30be
AV		 5336 /*
5337 * FW Load priority:
5338 * 1) Firmware via request-firmware interface (.bin file).
5339 * 2) Firmware residing in flash.
5340 */
5341 rval = qla24xx_load_risc_blob(vha, srisc_addr);
5342 if (rval == QLA_SUCCESS)
5343 return rval;
5344
cbc8eb67
AV		 5345 return qla24xx_load_risc_flash(vha, srisc_addr,
5346 vha->hw->flt_region_fw);
eaac30be
AV		 5347}
5348
5349int
5350qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5351{
5352 int rval;
cbc8eb67 5353 struct qla_hw_data *ha = vha->hw;
eaac30be 5354
e337d907 5355 if (ql2xfwloadbin == 2)
cbc8eb67 5356 goto try_blob_fw;
e337d907 5357
eaac30be
AV		 5358 /*
5359 * FW Load priority:
5360 * 1) Firmware residing in flash.
5361 * 2) Firmware via request-firmware interface (.bin file).
cbc8eb67 5362 * 3) Golden-Firmware residing in flash -- limited operation.
eaac30be 5363 */
cbc8eb67 5364 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
eaac30be
AV		 5365 if (rval == QLA_SUCCESS)
5366 return rval;
5367
cbc8eb67
AV		 5368try_blob_fw:
5369 rval = qla24xx_load_risc_blob(vha, srisc_addr);
5370 if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw)
5371 return rval;
5372
7c3df132
SK		 5373 ql_log(ql_log_info, vha, 0x0099,
5374 "Attempting to fallback to golden firmware.\n");
cbc8eb67
AV		 5375 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
5376 if (rval != QLA_SUCCESS)
5377 return rval;
5378
7c3df132 5379 ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n");
cbc8eb67 5380 ha->flags.running_gold_fw = 1;
cbc8eb67 5381 return rval;
eaac30be
AV		 5382}
5383
18c6c127 5384void
e315cd28 5385qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha)
18c6c127
AV		 5386{
5387 int ret, retries;
e315cd28 5388 struct qla_hw_data *ha = vha->hw;
18c6c127 5389
85880801
AV		 5390 if (ha->flags.pci_channel_io_perm_failure)
5391 return;
e428924c 5392 if (!IS_FWI2_CAPABLE(ha))
18c6c127 5393 return;
75edf81d
AV		 5394 if (!ha->fw_major_version)
5395 return;
18c6c127 5396
e315cd28 5397 ret = qla2x00_stop_firmware(vha);
7c7f1f29 5398 for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&
b469a7cb 5399 ret != QLA_INVALID_COMMAND && retries ; retries--) {
e315cd28
AC		 5400 ha->isp_ops->reset_chip(vha);
5401 if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS)
18c6c127 5402 continue;
e315cd28 5403 if (qla2x00_setup_chip(vha) != QLA_SUCCESS)
18c6c127 5404 continue;
7c3df132
SK		 5405 ql_log(ql_log_info, vha, 0x8015,
5406 "Attempting retry of stop-firmware command.\n");
e315cd28 5407 ret = qla2x00_stop_firmware(vha);
18c6c127
AV		 5408 }
5409}
2c3dfe3f
SJ		 5410
5411int
e315cd28 5412qla24xx_configure_vhba(scsi_qla_host_t *vha)
2c3dfe3f
SJ		 5413{
5414 int rval = QLA_SUCCESS;
0b91d116 5415 int rval2;
2c3dfe3f 5416 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28
AC		 5417 struct qla_hw_data *ha = vha->hw;
5418 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
67c2e93a
AC		 5419 struct req_que *req;
5420 struct rsp_que *rsp;
2c3dfe3f 5421
e315cd28 5422 if (!vha->vp_idx)
2c3dfe3f
SJ		 5423 return -EINVAL;
5424
e315cd28 5425 rval = qla2x00_fw_ready(base_vha);
7163ea81 5426 if (ha->flags.cpu_affinity_enabled)
67c2e93a
AC		 5427 req = ha->req_q_map[0];
5428 else
5429 req = vha->req;
5430 rsp = req->rsp;
5431
2c3dfe3f 5432 if (rval == QLA_SUCCESS) {
e315cd28 5433 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
73208dfd 5434 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
2c3dfe3f
SJ		 5435 }
5436
e315cd28 5437 vha->flags.management_server_logged_in = 0;
2c3dfe3f
SJ		 5438
5439 /* Login to SNS first */
0b91d116
CD		 5440 rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb,
5441 BIT_1);
5442 if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
5443 if (rval2 == QLA_MEMORY_ALLOC_FAILED)
5444 ql_dbg(ql_dbg_init, vha, 0x0120,
5445 "Failed SNS login: loop_id=%x, rval2=%d\n",
5446 NPH_SNS, rval2);
5447 else
5448 ql_dbg(ql_dbg_init, vha, 0x0103,
5449 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x "
5450 "mb[2]=%x mb[6]=%x mb[7]=%x.\n",
5451 NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]);
2c3dfe3f
SJ		 5452 return (QLA_FUNCTION_FAILED);
5453 }
5454
e315cd28
AC		 5455 atomic_set(&vha->loop_down_timer, 0);
5456 atomic_set(&vha->loop_state, LOOP_UP);
5457 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5458 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
5459 rval = qla2x00_loop_resync(base_vha);
2c3dfe3f
SJ		 5460
5461 return rval;
5462}
4d4df193
HK		 5463
5464/* 84XX Support **************************************************************/
5465
5466static LIST_HEAD(qla_cs84xx_list);
5467static DEFINE_MUTEX(qla_cs84xx_mutex);
5468
5469static struct qla_chip_state_84xx *
e315cd28 5470qla84xx_get_chip(struct scsi_qla_host *vha)
4d4df193
HK		 5471{
5472 struct qla_chip_state_84xx *cs84xx;
e315cd28 5473 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5474
5475 mutex_lock(&qla_cs84xx_mutex);
5476
5477 /* Find any shared 84xx chip. */
5478 list_for_each_entry(cs84xx, &qla_cs84xx_list, list) {
5479 if (cs84xx->bus == ha->pdev->bus) {
5480 kref_get(&cs84xx->kref);
5481 goto done;
5482 }
5483 }
5484
5485 cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL);
5486 if (!cs84xx)
5487 goto done;
5488
5489 kref_init(&cs84xx->kref);
5490 spin_lock_init(&cs84xx->access_lock);
5491 mutex_init(&cs84xx->fw_update_mutex);
5492 cs84xx->bus = ha->pdev->bus;
5493
5494 list_add_tail(&cs84xx->list, &qla_cs84xx_list);
5495done:
5496 mutex_unlock(&qla_cs84xx_mutex);
5497 return cs84xx;
5498}
5499
5500static void
5501__qla84xx_chip_release(struct kref *kref)
5502{
5503 struct qla_chip_state_84xx *cs84xx =
5504 container_of(kref, struct qla_chip_state_84xx, kref);
5505
5506 mutex_lock(&qla_cs84xx_mutex);
5507 list_del(&cs84xx->list);
5508 mutex_unlock(&qla_cs84xx_mutex);
5509 kfree(cs84xx);
5510}
5511
5512void
e315cd28 5513qla84xx_put_chip(struct scsi_qla_host *vha)
4d4df193 5514{
e315cd28 5515 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5516 if (ha->cs84xx)
5517 kref_put(&ha->cs84xx->kref, __qla84xx_chip_release);
5518}
5519
5520static int
e315cd28 5521qla84xx_init_chip(scsi_qla_host_t *vha)
4d4df193
HK		 5522{
5523 int rval;
5524 uint16_t status[2];
e315cd28 5525 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5526
5527 mutex_lock(&ha->cs84xx->fw_update_mutex);
5528
e315cd28 5529 rval = qla84xx_verify_chip(vha, status);
4d4df193
HK		 5530
5531 mutex_unlock(&ha->cs84xx->fw_update_mutex);
5532
5533 return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED:
5534 QLA_SUCCESS;
5535}
3a03eb79
AV		 5536
5537/* 81XX Support **************************************************************/
5538
5539int
5540qla81xx_nvram_config(scsi_qla_host_t *vha)
5541{
5542 int rval;
5543 struct init_cb_81xx *icb;
5544 struct nvram_81xx *nv;
5545 uint32_t *dptr;
5546 uint8_t *dptr1, *dptr2;
5547 uint32_t chksum;
5548 uint16_t cnt;
5549 struct qla_hw_data *ha = vha->hw;
5550
5551 rval = QLA_SUCCESS;
5552 icb = (struct init_cb_81xx *)ha->init_cb;
5553 nv = ha->nvram;
5554
5555 /* Determine NVRAM starting address. */
5556 ha->nvram_size = sizeof(struct nvram_81xx);
3a03eb79 5557 ha->vpd_size = FA_NVRAM_VPD_SIZE;
7ec0effd
AD		 5558 if (IS_P3P_TYPE(ha) || IS_QLA8031(ha))
5559 ha->vpd_size = FA_VPD_SIZE_82XX;
3a03eb79
AV		 5560
5561 /* Get VPD data into cache */
5562 ha->vpd = ha->nvram + VPD_OFFSET;
3d79038f
AV		 5563 ha->isp_ops->read_optrom(vha, ha->vpd, ha->flt_region_vpd << 2,
5564 ha->vpd_size);
3a03eb79
AV		 5565
5566 /* Get NVRAM data into cache and calculate checksum. */
3d79038f 5567 ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2,
3a03eb79 5568 ha->nvram_size);
3d79038f 5569 dptr = (uint32_t *)nv;
3a03eb79
AV		 5570 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
5571 chksum += le32_to_cpu(*dptr++);
5572
7c3df132
SK		 5573 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
5574 "Contents of NVRAM:\n");
5575 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
5576 (uint8_t *)nv, ha->nvram_size);
3a03eb79
AV		 5577
5578 /* Bad NVRAM data, set defaults parameters. */
5579 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
5580 || nv->id[3] != ' ' ||
5581 nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
5582 /* Reset NVRAM data. */
7c3df132 5583 ql_log(ql_log_info, vha, 0x0073,
9e336520 5584 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132 5585 "version=0x%x.\n", chksum, nv->id[0],
3a03eb79 5586 le16_to_cpu(nv->nvram_version));
7c3df132
SK		 5587 ql_log(ql_log_info, vha, 0x0074,
5588 "Falling back to functioning (yet invalid -- WWPN) "
5589 "defaults.\n");
3a03eb79
AV		 5590
5591 /*
5592 * Set default initialization control block.
5593 */
5594 memset(nv, 0, ha->nvram_size);
5595 nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
5596 nv->version = __constant_cpu_to_le16(ICB_VERSION);
5597 nv->frame_payload_size = __constant_cpu_to_le16(2048);
5598 nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
5599 nv->exchange_count = __constant_cpu_to_le16(0);
5600 nv->port_name[0] = 0x21;
e5b68a61 5601 nv->port_name[1] = 0x00 + ha->port_no;
3a03eb79
AV		 5602 nv->port_name[2] = 0x00;
5603 nv->port_name[3] = 0xe0;
5604 nv->port_name[4] = 0x8b;
5605 nv->port_name[5] = 0x1c;
5606 nv->port_name[6] = 0x55;
5607 nv->port_name[7] = 0x86;
5608 nv->node_name[0] = 0x20;
5609 nv->node_name[1] = 0x00;
5610 nv->node_name[2] = 0x00;
5611 nv->node_name[3] = 0xe0;
5612 nv->node_name[4] = 0x8b;
5613 nv->node_name[5] = 0x1c;
5614 nv->node_name[6] = 0x55;
5615 nv->node_name[7] = 0x86;
5616 nv->login_retry_count = __constant_cpu_to_le16(8);
5617 nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
5618 nv->login_timeout = __constant_cpu_to_le16(0);
5619 nv->firmware_options_1 =
5620 __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
5621 nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
5622 nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
5623 nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
5624 nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
5625 nv->efi_parameters = __constant_cpu_to_le32(0);
5626 nv->reset_delay = 5;
5627 nv->max_luns_per_target = __constant_cpu_to_le16(128);
5628 nv->port_down_retry_count = __constant_cpu_to_le16(30);
6246b8a1 5629 nv->link_down_timeout = __constant_cpu_to_le16(180);
eeebcc92 5630 nv->enode_mac[0] = 0x00;
6246b8a1
GM		 5631 nv->enode_mac[1] = 0xC0;
5632 nv->enode_mac[2] = 0xDD;
3a03eb79
AV		 5633 nv->enode_mac[3] = 0x04;
5634 nv->enode_mac[4] = 0x05;
e5b68a61 5635 nv->enode_mac[5] = 0x06 + ha->port_no;
3a03eb79
AV		 5636
5637 rval = 1;
5638 }
5639
9e522cd8
AE		 5640 if (IS_T10_PI_CAPABLE(ha))
5641 nv->frame_payload_size &= ~7;
5642
aa230bc5
AE		 5643 qlt_81xx_config_nvram_stage1(vha, nv);
5644
3a03eb79 5645 /* Reset Initialization control block */
773120e4 5646 memset(icb, 0, ha->init_cb_size);
3a03eb79
AV		 5647
5648 /* Copy 1st segment. */
5649 dptr1 = (uint8_t *)icb;
5650 dptr2 = (uint8_t *)&nv->version;
5651 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
5652 while (cnt--)
5653 *dptr1++ = *dptr2++;
5654
5655 icb->login_retry_count = nv->login_retry_count;
5656
5657 /* Copy 2nd segment. */
5658 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
5659 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
5660 cnt = (uint8_t *)&icb->reserved_5 -
5661 (uint8_t *)&icb->interrupt_delay_timer;
5662 while (cnt--)
5663 *dptr1++ = *dptr2++;
5664
5665 memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac));
5666 /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */
5667 if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) {
69e5f1ea
AV		 5668 icb->enode_mac[0] = 0x00;
5669 icb->enode_mac[1] = 0xC0;
5670 icb->enode_mac[2] = 0xDD;
3a03eb79
AV		 5671 icb->enode_mac[3] = 0x04;
5672 icb->enode_mac[4] = 0x05;
e5b68a61 5673 icb->enode_mac[5] = 0x06 + ha->port_no;
3a03eb79
AV		 5674 }
5675
b64b0e8f
AV		 5676 /* Use extended-initialization control block. */
5677 memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb));
5678
3a03eb79
AV		 5679 /*
5680 * Setup driver NVRAM options.
5681 */
5682 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
a9083016 5683 "QLE8XXX");
3a03eb79 5684
aa230bc5
AE		 5685 qlt_81xx_config_nvram_stage2(vha, icb);
5686
3a03eb79
AV		 5687 /* Use alternate WWN? */
5688 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
5689 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
5690 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
5691 }
5692
5693 /* Prepare nodename */
5694 if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
5695 /*
5696 * Firmware will apply the following mask if the nodename was
5697 * not provided.
5698 */
5699 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
5700 icb->node_name[0] &= 0xF0;
5701 }
5702
5703 /* Set host adapter parameters. */
5704 ha->flags.disable_risc_code_load = 0;
5705 ha->flags.enable_lip_reset = 0;
5706 ha->flags.enable_lip_full_login =
5707 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
5708 ha->flags.enable_target_reset =
5709 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
5710 ha->flags.enable_led_scheme = 0;
5711 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
5712
5713 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
5714 (BIT_6 | BIT_5 | BIT_4)) >> 4;
5715
5716 /* save HBA serial number */
5717 ha->serial0 = icb->port_name[5];
5718 ha->serial1 = icb->port_name[6];
5719 ha->serial2 = icb->port_name[7];
5720 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
5721 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
5722
5723 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
5724
5725 ha->retry_count = le16_to_cpu(nv->login_retry_count);
5726
5727 /* Set minimum login_timeout to 4 seconds. */
5728 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
5729 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
5730 if (le16_to_cpu(nv->login_timeout) < 4)
5731 nv->login_timeout = __constant_cpu_to_le16(4);
5732 ha->login_timeout = le16_to_cpu(nv->login_timeout);
5733 icb->login_timeout = nv->login_timeout;
5734
5735 /* Set minimum RATOV to 100 tenths of a second. */
5736 ha->r_a_tov = 100;
5737
5738 ha->loop_reset_delay = nv->reset_delay;
5739
5740 /* Link Down Timeout = 0:
5741 *
7ec0effd 5742 * When Port Down timer expires we will start returning
3a03eb79
AV		 5743 * I/O's to OS with "DID_NO_CONNECT".
5744 *
5745 * Link Down Timeout != 0:
5746 *
5747 * The driver waits for the link to come up after link down
5748 * before returning I/Os to OS with "DID_NO_CONNECT".
5749 */
5750 if (le16_to_cpu(nv->link_down_timeout) == 0) {
5751 ha->loop_down_abort_time =
5752 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
5753 } else {
5754 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
5755 ha->loop_down_abort_time =
5756 (LOOP_DOWN_TIME - ha->link_down_timeout);
5757 }
5758
5759 /* Need enough time to try and get the port back. */
5760 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
5761 if (qlport_down_retry)
5762 ha->port_down_retry_count = qlport_down_retry;
5763
5764 /* Set login_retry_count */
5765 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
5766 if (ha->port_down_retry_count ==
5767 le16_to_cpu(nv->port_down_retry_count) &&
5768 ha->port_down_retry_count > 3)
5769 ha->login_retry_count = ha->port_down_retry_count;
5770 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
5771 ha->login_retry_count = ha->port_down_retry_count;
5772 if (ql2xloginretrycount)
5773 ha->login_retry_count = ql2xloginretrycount;
5774
6246b8a1
GM		 5775 /* if not running MSI-X we need handshaking on interrupts */
5776 if (!vha->hw->flags.msix_enabled && IS_QLA83XX(ha))
5777 icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_22);
5778
3a03eb79
AV		 5779 /* Enable ZIO. */
5780 if (!vha->flags.init_done) {
5781 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
5782 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
5783 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
5784 le16_to_cpu(icb->interrupt_delay_timer): 2;
5785 }
5786 icb->firmware_options_2 &= __constant_cpu_to_le32(
5787 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
5788 vha->flags.process_response_queue = 0;
5789 if (ha->zio_mode != QLA_ZIO_DISABLED) {
5790 ha->zio_mode = QLA_ZIO_MODE_6;
5791
7c3df132 5792 ql_log(ql_log_info, vha, 0x0075,
3a03eb79 5793 "ZIO mode %d enabled; timer delay (%d us).\n",
7c3df132
SK		 5794 ha->zio_mode,
5795 ha->zio_timer * 100);
3a03eb79
AV		 5796
5797 icb->firmware_options_2 |= cpu_to_le32(
5798 (uint32_t)ha->zio_mode);
5799 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
5800 vha->flags.process_response_queue = 1;
5801 }
5802
5803 if (rval) {
7c3df132
SK		 5804 ql_log(ql_log_warn, vha, 0x0076,
5805 "NVRAM configuration failed.\n");
3a03eb79
AV		 5806 }
5807 return (rval);
5808}
5809
a9083016
GM		 5810int
5811qla82xx_restart_isp(scsi_qla_host_t *vha)
5812{
5813 int status, rval;
5814 uint32_t wait_time;
5815 struct qla_hw_data *ha = vha->hw;
5816 struct req_que *req = ha->req_q_map[0];
5817 struct rsp_que *rsp = ha->rsp_q_map[0];
5818 struct scsi_qla_host *vp;
feafb7b1 5819 unsigned long flags;
a9083016
GM		 5820
5821 status = qla2x00_init_rings(vha);
5822 if (!status) {
5823 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
5824 ha->flags.chip_reset_done = 1;
5825
5826 status = qla2x00_fw_ready(vha);
5827 if (!status) {
7c3df132
SK		 5828 ql_log(ql_log_info, vha, 0x803c,
5829 "Start configure loop, status =%d.\n", status);
a9083016
GM		 5830
5831 /* Issue a marker after FW becomes ready. */
5832 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
5833
5834 vha->flags.online = 1;
5835 /* Wait at most MAX_TARGET RSCNs for a stable link. */
5836 wait_time = 256;
5837 do {
5838 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5839 qla2x00_configure_loop(vha);
5840 wait_time--;
5841 } while (!atomic_read(&vha->loop_down_timer) &&
5842 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) &&
5843 wait_time &&
5844 (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)));
5845 }
5846
5847 /* if no cable then assume it's good */
5848 if ((vha->device_flags & DFLG_NO_CABLE))
5849 status = 0;
5850
cfb0919c 5851 ql_log(ql_log_info, vha, 0x8000,
7c3df132 5852 "Configure loop done, status = 0x%x.\n", status);
a9083016
GM		 5853 }
5854
5855 if (!status) {
5856 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
5857
5858 if (!atomic_read(&vha->loop_down_timer)) {
5859 /*
5860 * Issue marker command only when we are going
5861 * to start the I/O .
5862 */
5863 vha->marker_needed = 1;
5864 }
5865
5866 vha->flags.online = 1;
5867
5868 ha->isp_ops->enable_intrs(ha);
5869
5870 ha->isp_abort_cnt = 0;
5871 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
5872
53296788 5873 /* Update the firmware version */
3173167f 5874 status = qla82xx_check_md_needed(vha);
53296788 5875
a9083016
GM		 5876 if (ha->fce) {
5877 ha->flags.fce_enabled = 1;
5878 memset(ha->fce, 0,
5879 fce_calc_size(ha->fce_bufs));
5880 rval = qla2x00_enable_fce_trace(vha,
5881 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
5882 &ha->fce_bufs);
5883 if (rval) {
cfb0919c 5884 ql_log(ql_log_warn, vha, 0x8001,
7c3df132
SK		 5885 "Unable to reinitialize FCE (%d).\n",
5886 rval);
a9083016
GM		 5887 ha->flags.fce_enabled = 0;
5888 }
5889 }
5890
5891 if (ha->eft) {
5892 memset(ha->eft, 0, EFT_SIZE);
5893 rval = qla2x00_enable_eft_trace(vha,
5894 ha->eft_dma, EFT_NUM_BUFFERS);
5895 if (rval) {
cfb0919c 5896 ql_log(ql_log_warn, vha, 0x8010,
7c3df132
SK		 5897 "Unable to reinitialize EFT (%d).\n",
5898 rval);
a9083016
GM		 5899 }
5900 }
a9083016
GM		 5901 }
5902
5903 if (!status) {
cfb0919c 5904 ql_dbg(ql_dbg_taskm, vha, 0x8011,
7c3df132 5905 "qla82xx_restart_isp succeeded.\n");
feafb7b1
AE		 5906
5907 spin_lock_irqsave(&ha->vport_slock, flags);
5908 list_for_each_entry(vp, &ha->vp_list, list) {
5909 if (vp->vp_idx) {
5910 atomic_inc(&vp->vref_count);
5911 spin_unlock_irqrestore(&ha->vport_slock, flags);
5912
a9083016 5913 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 5914
5915 spin_lock_irqsave(&ha->vport_slock, flags);
5916 atomic_dec(&vp->vref_count);
5917 }
a9083016 5918 }
feafb7b1
AE		 5919 spin_unlock_irqrestore(&ha->vport_slock, flags);
5920
a9083016 5921 } else {
cfb0919c 5922 ql_log(ql_log_warn, vha, 0x8016,
7c3df132 5923 "qla82xx_restart_isp **** FAILED ****.\n");
a9083016
GM		 5924 }
5925
5926 return status;
5927}
5928
3a03eb79 5929void
ae97c91e 5930qla81xx_update_fw_options(scsi_qla_host_t *vha)
3a03eb79 5931{
ae97c91e
AV		 5932 struct qla_hw_data *ha = vha->hw;
5933
5934 if (!ql2xetsenable)
5935 return;
5936
5937 /* Enable ETS Burst. */
5938 memset(ha->fw_options, 0, sizeof(ha->fw_options));
5939 ha->fw_options[2] |= BIT_9;
5940 qla2x00_set_fw_options(vha, ha->fw_options);
3a03eb79 5941}
09ff701a
SR		 5942
5943/*
5944 * qla24xx_get_fcp_prio
5945 * Gets the fcp cmd priority value for the logged in port.
5946 * Looks for a match of the port descriptors within
5947 * each of the fcp prio config entries. If a match is found,
5948 * the tag (priority) value is returned.
5949 *
5950 * Input:
21090cbe 5951 * vha = scsi host structure pointer.
09ff701a
SR		 5952 * fcport = port structure pointer.
5953 *
5954 * Return:
6c452a45 5955 * non-zero (if found)
f28a0a96 5956 * -1 (if not found)
09ff701a
SR		 5957 *
5958 * Context:
5959 * Kernel context
5960 */
f28a0a96 5961static int
09ff701a
SR		 5962qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
5963{
5964 int i, entries;
5965 uint8_t pid_match, wwn_match;
f28a0a96 5966 int priority;
09ff701a
SR		 5967 uint32_t pid1, pid2;
5968 uint64_t wwn1, wwn2;
5969 struct qla_fcp_prio_entry *pri_entry;
5970 struct qla_hw_data *ha = vha->hw;
5971
5972 if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled)
f28a0a96 5973 return -1;
09ff701a 5974
f28a0a96 5975 priority = -1;
09ff701a
SR		 5976 entries = ha->fcp_prio_cfg->num_entries;
5977 pri_entry = &ha->fcp_prio_cfg->entry[0];
5978
5979 for (i = 0; i < entries; i++) {
5980 pid_match = wwn_match = 0;
5981
5982 if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) {
5983 pri_entry++;
5984 continue;
5985 }
5986
5987 /* check source pid for a match */
5988 if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) {
5989 pid1 = pri_entry->src_pid & INVALID_PORT_ID;
5990 pid2 = vha->d_id.b24 & INVALID_PORT_ID;
5991 if (pid1 == INVALID_PORT_ID)
5992 pid_match++;
5993 else if (pid1 == pid2)
5994 pid_match++;
5995 }
5996
5997 /* check destination pid for a match */
5998 if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) {
5999 pid1 = pri_entry->dst_pid & INVALID_PORT_ID;
6000 pid2 = fcport->d_id.b24 & INVALID_PORT_ID;
6001 if (pid1 == INVALID_PORT_ID)
6002 pid_match++;
6003 else if (pid1 == pid2)
6004 pid_match++;
6005 }
6006
6007 /* check source WWN for a match */
6008 if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) {
6009 wwn1 = wwn_to_u64(vha->port_name);
6010 wwn2 = wwn_to_u64(pri_entry->src_wwpn);
6011 if (wwn2 == (uint64_t)-1)
6012 wwn_match++;
6013 else if (wwn1 == wwn2)
6014 wwn_match++;
6015 }
6016
6017 /* check destination WWN for a match */
6018 if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) {
6019 wwn1 = wwn_to_u64(fcport->port_name);
6020 wwn2 = wwn_to_u64(pri_entry->dst_wwpn);
6021 if (wwn2 == (uint64_t)-1)
6022 wwn_match++;
6023 else if (wwn1 == wwn2)
6024 wwn_match++;
6025 }
6026
6027 if (pid_match == 2 || wwn_match == 2) {
6028 /* Found a matching entry */
6029 if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID)
6030 priority = pri_entry->tag;
6031 break;
6032 }
6033
6034 pri_entry++;
6035 }
6036
6037 return priority;
6038}
6039
6040/*
6041 * qla24xx_update_fcport_fcp_prio
6042 * Activates fcp priority for the logged in fc port
6043 *
6044 * Input:
21090cbe 6045 * vha = scsi host structure pointer.
09ff701a
SR		 6046 * fcp = port structure pointer.
6047 *
6048 * Return:
6049 * QLA_SUCCESS or QLA_FUNCTION_FAILED
6050 *
6051 * Context:
6052 * Kernel context.
6053 */
6054int
21090cbe 6055qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
09ff701a
SR		 6056{
6057 int ret;
f28a0a96 6058 int priority;
09ff701a
SR		 6059 uint16_t mb[5];
6060
21090cbe
MI		 6061 if (fcport->port_type != FCT_TARGET ||
6062 fcport->loop_id == FC_NO_LOOP_ID)
09ff701a
SR		 6063 return QLA_FUNCTION_FAILED;
6064
21090cbe 6065 priority = qla24xx_get_fcp_prio(vha, fcport);
f28a0a96
AV		 6066 if (priority < 0)
6067 return QLA_FUNCTION_FAILED;
6068
7ec0effd 6069 if (IS_P3P_TYPE(vha->hw)) {
a00f6296
SK		 6070 fcport->fcp_prio = priority & 0xf;
6071 return QLA_SUCCESS;
6072 }
6073
21090cbe 6074 ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb);
cfb0919c
CD		 6075 if (ret == QLA_SUCCESS) {
6076 if (fcport->fcp_prio != priority)
6077 ql_dbg(ql_dbg_user, vha, 0x709e,
6078 "Updated FCP_CMND priority - value=%d loop_id=%d "
6079 "port_id=%02x%02x%02x.\n", priority,
6080 fcport->loop_id, fcport->d_id.b.domain,
6081 fcport->d_id.b.area, fcport->d_id.b.al_pa);
a00f6296 6082 fcport->fcp_prio = priority & 0xf;
cfb0919c 6083 } else
7c3df132 6084 ql_dbg(ql_dbg_user, vha, 0x704f,
cfb0919c
CD		 6085 "Unable to update FCP_CMND priority - ret=0x%x for "
6086 "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id,
6087 fcport->d_id.b.domain, fcport->d_id.b.area,
6088 fcport->d_id.b.al_pa);
09ff701a
SR		 6089 return ret;
6090}
6091
6092/*
6093 * qla24xx_update_all_fcp_prio
6094 * Activates fcp priority for all the logged in ports
6095 *
6096 * Input:
6097 * ha = adapter block pointer.
6098 *
6099 * Return:
6100 * QLA_SUCCESS or QLA_FUNCTION_FAILED
6101 *
6102 * Context:
6103 * Kernel context.
6104 */
6105int
6106qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha)
6107{
6108 int ret;
6109 fc_port_t *fcport;
6110
6111 ret = QLA_FUNCTION_FAILED;
6112 /* We need to set priority for all logged in ports */
6113 list_for_each_entry(fcport, &vha->vp_fcports, list)
6114 ret = qla24xx_update_fcport_fcp_prio(vha, fcport);
6115
6116 return ret;
6117}
ubuntu-bionic-kernel mirror