]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/scsi/qla2xxx/qla_init.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
qla2xxx: Remove __constant_ prefix
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / qla2xxx / qla_init.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
73208dfd 8#include "qla_gbl.h"
1da177e4
LT		 9
10#include <linux/delay.h>
5a0e3ad6 11#include <linux/slab.h>
0107109e 12#include <linux/vmalloc.h>
1da177e4
LT		 13
14#include "qla_devtbl.h"
15
4e08df3f
DM		 16#ifdef CONFIG_SPARC
17#include <asm/prom.h>
4e08df3f
DM		 18#endif
19
2d70c103
NB		 20#include <target/target_core_base.h>
21#include "qla_target.h"
22
1da177e4
LT		 23/*
24* QLogic ISP2x00 Hardware Support Function Prototypes.
25*/
1da177e4 26static int qla2x00_isp_firmware(scsi_qla_host_t *);
1da177e4 27static int qla2x00_setup_chip(scsi_qla_host_t *);
1da177e4
LT		 28static int qla2x00_fw_ready(scsi_qla_host_t *);
29static int qla2x00_configure_hba(scsi_qla_host_t *);
1da177e4
LT		 30static int qla2x00_configure_loop(scsi_qla_host_t *);
31static int qla2x00_configure_local_loop(scsi_qla_host_t *);
1da177e4
LT		 32static int qla2x00_configure_fabric(scsi_qla_host_t *);
33static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *, struct list_head *);
1da177e4
LT		 34static int qla2x00_fabric_dev_login(scsi_qla_host_t *, fc_port_t *,
35 uint16_t *);
1da177e4
LT		 36
37static int qla2x00_restart_isp(scsi_qla_host_t *);
1da177e4 38
4d4df193
HK		 39static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *);
40static int qla84xx_init_chip(scsi_qla_host_t *);
73208dfd 41static int qla25xx_init_queues(struct qla_hw_data *);
4d4df193 42
ac280b67
AV		 43/* SRB Extensions ---------------------------------------------------------- */
44
9ba56b95
GM		 45void
46qla2x00_sp_timeout(unsigned long __data)
ac280b67
AV		 47{
48 srb_t *sp = (srb_t *)__data;
4916392b 49 struct srb_iocb *iocb;
ac280b67
AV		 50 fc_port_t *fcport = sp->fcport;
51 struct qla_hw_data *ha = fcport->vha->hw;
52 struct req_que *req;
53 unsigned long flags;
54
55 spin_lock_irqsave(&ha->hardware_lock, flags);
56 req = ha->req_q_map[0];
57 req->outstanding_cmds[sp->handle] = NULL;
9ba56b95 58 iocb = &sp->u.iocb_cmd;
4916392b 59 iocb->timeout(sp);
9ba56b95 60 sp->free(fcport->vha, sp);
6ac52608 61 spin_unlock_irqrestore(&ha->hardware_lock, flags);
ac280b67
AV		 62}
63
9ba56b95
GM		 64void
65qla2x00_sp_free(void *data, void *ptr)
ac280b67 66{
9ba56b95
GM		 67 srb_t *sp = (srb_t *)ptr;
68 struct srb_iocb *iocb = &sp->u.iocb_cmd;
69 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
ac280b67 70
4d97cc53 71 del_timer(&iocb->timer);
b00ee7d7 72 qla2x00_rel_sp(vha, sp);
ac280b67
AV		 73}
74
ac280b67
AV		 75/* Asynchronous Login/Logout Routines -------------------------------------- */
76
a9b6f722 77unsigned long
5b91490e
AV		 78qla2x00_get_async_timeout(struct scsi_qla_host *vha)
79{
80 unsigned long tmo;
81 struct qla_hw_data *ha = vha->hw;
82
83 /* Firmware should use switch negotiated r_a_tov for timeout. */
84 tmo = ha->r_a_tov / 10 * 2;
8ae6d9c7
GM		 85 if (IS_QLAFX00(ha)) {
86 tmo = FX00_DEF_RATOV * 2;
87 } else if (!IS_FWI2_CAPABLE(ha)) {
5b91490e
AV		 88 /*
89 * Except for earlier ISPs where the timeout is seeded from the
90 * initialization control block.
91 */
92 tmo = ha->login_timeout;
93 }
94 return tmo;
95}
ac280b67
AV		 96
97static void
9ba56b95 98qla2x00_async_iocb_timeout(void *data)
ac280b67 99{
9ba56b95 100 srb_t *sp = (srb_t *)data;
ac280b67 101 fc_port_t *fcport = sp->fcport;
ac280b67 102
7c3df132 103 ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
cfb0919c 104 "Async-%s timeout - hdl=%x portid=%02x%02x%02x.\n",
9ba56b95 105 sp->name, sp->handle, fcport->d_id.b.domain, fcport->d_id.b.area,
7c3df132 106 fcport->d_id.b.al_pa);
ac280b67 107
5ff1d584 108 fcport->flags &= ~FCF_ASYNC_SENT;
9ba56b95
GM		 109 if (sp->type == SRB_LOGIN_CMD) {
110 struct srb_iocb *lio = &sp->u.iocb_cmd;
ac280b67 111 qla2x00_post_async_logout_work(fcport->vha, fcport, NULL);
6ac52608
AV		 112 /* Retry as needed. */
113 lio->u.logio.data[0] = MBS_COMMAND_ERROR;
114 lio->u.logio.data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
115 QLA_LOGIO_LOGIN_RETRIED : 0;
116 qla2x00_post_async_login_done_work(fcport->vha, fcport,
117 lio->u.logio.data);
118 }
ac280b67
AV		 119}
120
99b0bec7 121static void
9ba56b95 122qla2x00_async_login_sp_done(void *data, void *ptr, int res)
99b0bec7 123{
9ba56b95
GM		 124 srb_t *sp = (srb_t *)ptr;
125 struct srb_iocb *lio = &sp->u.iocb_cmd;
126 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
127
128 if (!test_bit(UNLOADING, &vha->dpc_flags))
129 qla2x00_post_async_login_done_work(sp->fcport->vha, sp->fcport,
130 lio->u.logio.data);
131 sp->free(sp->fcport->vha, sp);
99b0bec7
AV		 132}
133
ac280b67
AV		 134int
135qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport,
136 uint16_t *data)
137{
ac280b67 138 srb_t *sp;
4916392b 139 struct srb_iocb *lio;
ac280b67
AV		 140 int rval;
141
142 rval = QLA_FUNCTION_FAILED;
9ba56b95 143 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 144 if (!sp)
145 goto done;
146
9ba56b95
GM		 147 sp->type = SRB_LOGIN_CMD;
148 sp->name = "login";
149 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
150
151 lio = &sp->u.iocb_cmd;
3822263e 152 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 153 sp->done = qla2x00_async_login_sp_done;
4916392b 154 lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI;
ac280b67 155 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 156 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
ac280b67
AV		 157 rval = qla2x00_start_sp(sp);
158 if (rval != QLA_SUCCESS)
159 goto done_free_sp;
160
7c3df132 161 ql_dbg(ql_dbg_disc, vha, 0x2072,
cfb0919c
CD		 162 "Async-login - hdl=%x, loopid=%x portid=%02x%02x%02x "
163 "retries=%d.\n", sp->handle, fcport->loop_id,
164 fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
165 fcport->login_retry);
ac280b67
AV		 166 return rval;
167
168done_free_sp:
9ba56b95 169 sp->free(fcport->vha, sp);
ac280b67
AV		 170done:
171 return rval;
172}
173
99b0bec7 174static void
9ba56b95 175qla2x00_async_logout_sp_done(void *data, void *ptr, int res)
99b0bec7 176{
9ba56b95
GM		 177 srb_t *sp = (srb_t *)ptr;
178 struct srb_iocb *lio = &sp->u.iocb_cmd;
179 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
180
181 if (!test_bit(UNLOADING, &vha->dpc_flags))
182 qla2x00_post_async_logout_done_work(sp->fcport->vha, sp->fcport,
183 lio->u.logio.data);
184 sp->free(sp->fcport->vha, sp);
99b0bec7
AV		 185}
186
ac280b67
AV		 187int
188qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport)
189{
ac280b67 190 srb_t *sp;
4916392b 191 struct srb_iocb *lio;
ac280b67
AV		 192 int rval;
193
194 rval = QLA_FUNCTION_FAILED;
9ba56b95 195 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 196 if (!sp)
197 goto done;
198
9ba56b95
GM		 199 sp->type = SRB_LOGOUT_CMD;
200 sp->name = "logout";
201 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
202
203 lio = &sp->u.iocb_cmd;
3822263e 204 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 205 sp->done = qla2x00_async_logout_sp_done;
ac280b67
AV		 206 rval = qla2x00_start_sp(sp);
207 if (rval != QLA_SUCCESS)
208 goto done_free_sp;
209
7c3df132 210 ql_dbg(ql_dbg_disc, vha, 0x2070,
cfb0919c
CD		 211 "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
212 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
213 fcport->d_id.b.area, fcport->d_id.b.al_pa);
ac280b67
AV		 214 return rval;
215
216done_free_sp:
9ba56b95 217 sp->free(fcport->vha, sp);
ac280b67
AV		 218done:
219 return rval;
220}
221
5ff1d584 222static void
9ba56b95 223qla2x00_async_adisc_sp_done(void *data, void *ptr, int res)
5ff1d584 224{
9ba56b95
GM		 225 srb_t *sp = (srb_t *)ptr;
226 struct srb_iocb *lio = &sp->u.iocb_cmd;
227 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
228
229 if (!test_bit(UNLOADING, &vha->dpc_flags))
230 qla2x00_post_async_adisc_done_work(sp->fcport->vha, sp->fcport,
231 lio->u.logio.data);
232 sp->free(sp->fcport->vha, sp);
5ff1d584
AV		 233}
234
235int
236qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport,
237 uint16_t *data)
238{
5ff1d584 239 srb_t *sp;
4916392b 240 struct srb_iocb *lio;
5ff1d584
AV		 241 int rval;
242
243 rval = QLA_FUNCTION_FAILED;
9ba56b95 244 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
5ff1d584
AV		 245 if (!sp)
246 goto done;
247
9ba56b95
GM		 248 sp->type = SRB_ADISC_CMD;
249 sp->name = "adisc";
250 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
251
252 lio = &sp->u.iocb_cmd;
3822263e 253 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 254 sp->done = qla2x00_async_adisc_sp_done;
5ff1d584 255 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 256 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
5ff1d584
AV		 257 rval = qla2x00_start_sp(sp);
258 if (rval != QLA_SUCCESS)
259 goto done_free_sp;
260
7c3df132 261 ql_dbg(ql_dbg_disc, vha, 0x206f,
cfb0919c
CD		 262 "Async-adisc - hdl=%x loopid=%x portid=%02x%02x%02x.\n",
263 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
264 fcport->d_id.b.area, fcport->d_id.b.al_pa);
5ff1d584
AV		 265 return rval;
266
267done_free_sp:
9ba56b95 268 sp->free(fcport->vha, sp);
5ff1d584
AV		 269done:
270 return rval;
271}
272
3822263e 273static void
faef62d1 274qla2x00_tmf_iocb_timeout(void *data)
3822263e 275{
faef62d1
AB		 276 srb_t *sp = (srb_t *)data;
277 struct srb_iocb *tmf = &sp->u.iocb_cmd;
3822263e 278
faef62d1
AB		 279 tmf->u.tmf.comp_status = CS_TIMEOUT;
280 complete(&tmf->u.tmf.comp);
281}
9ba56b95 282
faef62d1
AB		 283static void
284qla2x00_tmf_sp_done(void *data, void *ptr, int res)
285{
286 srb_t *sp = (srb_t *)ptr;
287 struct srb_iocb *tmf = &sp->u.iocb_cmd;
288 complete(&tmf->u.tmf.comp);
3822263e
MI		 289}
290
291int
faef62d1 292qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t flags, uint32_t lun,
3822263e
MI		 293 uint32_t tag)
294{
295 struct scsi_qla_host *vha = fcport->vha;
faef62d1 296 struct srb_iocb *tm_iocb;
3822263e 297 srb_t *sp;
faef62d1 298 int rval = QLA_FUNCTION_FAILED;
3822263e 299
9ba56b95 300 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
3822263e
MI		 301 if (!sp)
302 goto done;
303
faef62d1 304 tm_iocb = &sp->u.iocb_cmd;
9ba56b95
GM		 305 sp->type = SRB_TM_CMD;
306 sp->name = "tmf";
faef62d1
AB		 307 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
308 tm_iocb->u.tmf.flags = flags;
309 tm_iocb->u.tmf.lun = lun;
310 tm_iocb->u.tmf.data = tag;
311 sp->done = qla2x00_tmf_sp_done;
312 tm_iocb->timeout = qla2x00_tmf_iocb_timeout;
313 init_completion(&tm_iocb->u.tmf.comp);
3822263e
MI		 314
315 rval = qla2x00_start_sp(sp);
316 if (rval != QLA_SUCCESS)
317 goto done_free_sp;
318
7c3df132 319 ql_dbg(ql_dbg_taskm, vha, 0x802f,
cfb0919c
CD		 320 "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
321 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
322 fcport->d_id.b.area, fcport->d_id.b.al_pa);
faef62d1
AB		 323
324 wait_for_completion(&tm_iocb->u.tmf.comp);
325
326 rval = tm_iocb->u.tmf.comp_status == CS_COMPLETE ?
327 QLA_SUCCESS : QLA_FUNCTION_FAILED;
328
329 if ((rval != QLA_SUCCESS) || tm_iocb->u.tmf.data) {
330 ql_dbg(ql_dbg_taskm, vha, 0x8030,
331 "TM IOCB failed (%x).\n", rval);
332 }
333
334 if (!test_bit(UNLOADING, &vha->dpc_flags) && !IS_QLAFX00(vha->hw)) {
335 flags = tm_iocb->u.tmf.flags;
336 lun = (uint16_t)tm_iocb->u.tmf.lun;
337
338 /* Issue Marker IOCB */
339 qla2x00_marker(vha, vha->hw->req_q_map[0],
340 vha->hw->rsp_q_map[0], sp->fcport->loop_id, lun,
341 flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
342 }
3822263e
MI		 343
344done_free_sp:
faef62d1 345 sp->free(vha, sp);
3822263e
MI		 346done:
347 return rval;
348}
349
4440e46d
AB		 350static void
351qla24xx_abort_iocb_timeout(void *data)
352{
353 srb_t *sp = (srb_t *)data;
354 struct srb_iocb *abt = &sp->u.iocb_cmd;
355
356 abt->u.abt.comp_status = CS_TIMEOUT;
357 complete(&abt->u.abt.comp);
358}
359
360static void
361qla24xx_abort_sp_done(void *data, void *ptr, int res)
362{
363 srb_t *sp = (srb_t *)ptr;
364 struct srb_iocb *abt = &sp->u.iocb_cmd;
365
366 complete(&abt->u.abt.comp);
367}
368
369static int
370qla24xx_async_abort_cmd(srb_t *cmd_sp)
371{
372 scsi_qla_host_t *vha = cmd_sp->fcport->vha;
373 fc_port_t *fcport = cmd_sp->fcport;
374 struct srb_iocb *abt_iocb;
375 srb_t *sp;
376 int rval = QLA_FUNCTION_FAILED;
377
378 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
379 if (!sp)
380 goto done;
381
382 abt_iocb = &sp->u.iocb_cmd;
383 sp->type = SRB_ABT_CMD;
384 sp->name = "abort";
385 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
386 abt_iocb->u.abt.cmd_hndl = cmd_sp->handle;
387 sp->done = qla24xx_abort_sp_done;
388 abt_iocb->timeout = qla24xx_abort_iocb_timeout;
389 init_completion(&abt_iocb->u.abt.comp);
390
391 rval = qla2x00_start_sp(sp);
392 if (rval != QLA_SUCCESS)
393 goto done_free_sp;
394
395 ql_dbg(ql_dbg_async, vha, 0x507c,
396 "Abort command issued - hdl=%x, target_id=%x\n",
397 cmd_sp->handle, fcport->tgt_id);
398
399 wait_for_completion(&abt_iocb->u.abt.comp);
400
401 rval = abt_iocb->u.abt.comp_status == CS_COMPLETE ?
402 QLA_SUCCESS : QLA_FUNCTION_FAILED;
403
404done_free_sp:
405 sp->free(vha, sp);
406done:
407 return rval;
408}
409
410int
411qla24xx_async_abort_command(srb_t *sp)
412{
413 unsigned long flags = 0;
414
415 uint32_t handle;
416 fc_port_t *fcport = sp->fcport;
417 struct scsi_qla_host *vha = fcport->vha;
418 struct qla_hw_data *ha = vha->hw;
419 struct req_que *req = vha->req;
420
421 spin_lock_irqsave(&ha->hardware_lock, flags);
422 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
423 if (req->outstanding_cmds[handle] == sp)
424 break;
425 }
426 spin_unlock_irqrestore(&ha->hardware_lock, flags);
427 if (handle == req->num_outstanding_cmds) {
428 /* Command not found. */
429 return QLA_FUNCTION_FAILED;
430 }
431 if (sp->type == SRB_FXIOCB_DCMD)
432 return qlafx00_fx_disc(vha, &vha->hw->mr.fcport,
433 FXDISC_ABORT_IOCTL);
434
435 return qla24xx_async_abort_cmd(sp);
436}
437
4916392b 438void
ac280b67
AV		 439qla2x00_async_login_done(struct scsi_qla_host *vha, fc_port_t *fcport,
440 uint16_t *data)
441{
442 int rval;
ac280b67
AV		 443
444 switch (data[0]) {
445 case MBS_COMMAND_COMPLETE:
a4f92a32
AV		 446 /*
447 * Driver must validate login state - If PRLI not complete,
448 * force a relogin attempt via implicit LOGO, PLOGI, and PRLI
449 * requests.
450 */
451 rval = qla2x00_get_port_database(vha, fcport, 0);
0eba25df
AE		 452 if (rval == QLA_NOT_LOGGED_IN) {
453 fcport->flags &= ~FCF_ASYNC_SENT;
454 fcport->flags |= FCF_LOGIN_NEEDED;
455 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
456 break;
457 }
458
a4f92a32
AV		 459 if (rval != QLA_SUCCESS) {
460 qla2x00_post_async_logout_work(vha, fcport, NULL);
461 qla2x00_post_async_login_work(vha, fcport, NULL);
462 break;
463 }
99b0bec7 464 if (fcport->flags & FCF_FCP2_DEVICE) {
5ff1d584
AV		 465 qla2x00_post_async_adisc_work(vha, fcport, data);
466 break;
99b0bec7
AV		 467 }
468 qla2x00_update_fcport(vha, fcport);
ac280b67
AV		 469 break;
470 case MBS_COMMAND_ERROR:
5ff1d584 471 fcport->flags &= ~FCF_ASYNC_SENT;
ac280b67
AV		 472 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
473 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
474 else
80d79440 475 qla2x00_mark_device_lost(vha, fcport, 1, 0);
ac280b67
AV		 476 break;
477 case MBS_PORT_ID_USED:
478 fcport->loop_id = data[1];
6ac52608 479 qla2x00_post_async_logout_work(vha, fcport, NULL);
ac280b67
AV		 480 qla2x00_post_async_login_work(vha, fcport, NULL);
481 break;
482 case MBS_LOOP_ID_USED:
483 fcport->loop_id++;
484 rval = qla2x00_find_new_loop_id(vha, fcport);
485 if (rval != QLA_SUCCESS) {
5ff1d584 486 fcport->flags &= ~FCF_ASYNC_SENT;
80d79440 487 qla2x00_mark_device_lost(vha, fcport, 1, 0);
ac280b67
AV		 488 break;
489 }
490 qla2x00_post_async_login_work(vha, fcport, NULL);
491 break;
492 }
4916392b 493 return;
ac280b67
AV		 494}
495
4916392b 496void
ac280b67
AV		 497qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport,
498 uint16_t *data)
499{
500 qla2x00_mark_device_lost(vha, fcport, 1, 0);
4916392b 501 return;
ac280b67
AV		 502}
503
4916392b 504void
5ff1d584
AV		 505qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport,
506 uint16_t *data)
507{
508 if (data[0] == MBS_COMMAND_COMPLETE) {
509 qla2x00_update_fcport(vha, fcport);
510
4916392b 511 return;
5ff1d584
AV		 512 }
513
514 /* Retry login. */
515 fcport->flags &= ~FCF_ASYNC_SENT;
516 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
517 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
518 else
80d79440 519 qla2x00_mark_device_lost(vha, fcport, 1, 0);
5ff1d584 520
4916392b 521 return;
5ff1d584
AV		 522}
523
1da177e4
LT		 524/****************************************************************************/
525/* QLogic ISP2x00 Hardware Support Functions. */
526/****************************************************************************/
527
fa492630 528static int
7d613ac6
SV		 529qla83xx_nic_core_fw_load(scsi_qla_host_t *vha)
530{
531 int rval = QLA_SUCCESS;
532 struct qla_hw_data *ha = vha->hw;
533 uint32_t idc_major_ver, idc_minor_ver;
711aa7f7 534 uint16_t config[4];
7d613ac6
SV		 535
536 qla83xx_idc_lock(vha, 0);
537
538 /* SV: TODO: Assign initialization timeout from
539 * flash-info / other param
540 */
541 ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT;
542 ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT;
543
544 /* Set our fcoe function presence */
545 if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) {
546 ql_dbg(ql_dbg_p3p, vha, 0xb077,
547 "Error while setting DRV-Presence.\n");
548 rval = QLA_FUNCTION_FAILED;
549 goto exit;
550 }
551
552 /* Decide the reset ownership */
553 qla83xx_reset_ownership(vha);
554
555 /*
556 * On first protocol driver load:
557 * Init-Owner: Set IDC-Major-Version and Clear IDC-Lock-Recovery
558 * register.
559 * Others: Check compatibility with current IDC Major version.
560 */
561 qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver);
562 if (ha->flags.nic_core_reset_owner) {
563 /* Set IDC Major version */
564 idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION;
565 qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver);
566
567 /* Clearing IDC-Lock-Recovery register */
568 qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0);
569 } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) {
570 /*
571 * Clear further IDC participation if we are not compatible with
572 * the current IDC Major Version.
573 */
574 ql_log(ql_log_warn, vha, 0xb07d,
575 "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n",
576 idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION);
577 __qla83xx_clear_drv_presence(vha);
578 rval = QLA_FUNCTION_FAILED;
579 goto exit;
580 }
581 /* Each function sets its supported Minor version. */
582 qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver);
583 idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2));
584 qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver);
585
711aa7f7
SK		 586 if (ha->flags.nic_core_reset_owner) {
587 memset(config, 0, sizeof(config));
588 if (!qla81xx_get_port_config(vha, config))
589 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
590 QLA8XXX_DEV_READY);
591 }
592
7d613ac6
SV		 593 rval = qla83xx_idc_state_handler(vha);
594
595exit:
596 qla83xx_idc_unlock(vha, 0);
597
598 return rval;
599}
600
1da177e4
LT		 601/*
602* qla2x00_initialize_adapter
603* Initialize board.
604*
605* Input:
606* ha = adapter block pointer.
607*
608* Returns:
609* 0 = success
610*/
611int
e315cd28 612qla2x00_initialize_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 613{
614 int rval;
e315cd28 615 struct qla_hw_data *ha = vha->hw;
73208dfd 616 struct req_que *req = ha->req_q_map[0];
2533cf67 617
1da177e4 618 /* Clear adapter flags. */
e315cd28 619 vha->flags.online = 0;
2533cf67 620 ha->flags.chip_reset_done = 0;
e315cd28 621 vha->flags.reset_active = 0;
85880801
AV		 622 ha->flags.pci_channel_io_perm_failure = 0;
623 ha->flags.eeh_busy = 0;
fabbb8df 624 vha->qla_stats.jiffies_at_last_reset = get_jiffies_64();
e315cd28
AC		 625 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
626 atomic_set(&vha->loop_state, LOOP_DOWN);
627 vha->device_flags = DFLG_NO_CABLE;
628 vha->dpc_flags = 0;
629 vha->flags.management_server_logged_in = 0;
630 vha->marker_needed = 0;
1da177e4
LT		 631 ha->isp_abort_cnt = 0;
632 ha->beacon_blink_led = 0;
633
73208dfd
AC		 634 set_bit(0, ha->req_qid_map);
635 set_bit(0, ha->rsp_qid_map);
636
cfb0919c 637 ql_dbg(ql_dbg_init, vha, 0x0040,
7c3df132 638 "Configuring PCI space...\n");
e315cd28 639 rval = ha->isp_ops->pci_config(vha);
1da177e4 640 if (rval) {
7c3df132
SK		 641 ql_log(ql_log_warn, vha, 0x0044,
642 "Unable to configure PCI space.\n");
1da177e4
LT		 643 return (rval);
644 }
645
e315cd28 646 ha->isp_ops->reset_chip(vha);
1da177e4 647
e315cd28 648 rval = qla2xxx_get_flash_info(vha);
c00d8994 649 if (rval) {
7c3df132
SK		 650 ql_log(ql_log_fatal, vha, 0x004f,
651 "Unable to validate FLASH data.\n");
7ec0effd
AD		 652 return rval;
653 }
654
655 if (IS_QLA8044(ha)) {
656 qla8044_read_reset_template(vha);
657
658 /* NOTE: If ql2xdontresethba==1, set IDC_CTRL DONTRESET_BIT0.
659 * If DONRESET_BIT0 is set, drivers should not set dev_state
660 * to NEED_RESET. But if NEED_RESET is set, drivers should
661 * should honor the reset. */
662 if (ql2xdontresethba == 1)
663 qla8044_set_idc_dontreset(vha);
c00d8994
AV		 664 }
665
73208dfd 666 ha->isp_ops->get_flash_version(vha, req->ring);
cfb0919c 667 ql_dbg(ql_dbg_init, vha, 0x0061,
7c3df132 668 "Configure NVRAM parameters...\n");
0107109e 669
e315cd28 670 ha->isp_ops->nvram_config(vha);
1da177e4 671
d4c760c2
AV		 672 if (ha->flags.disable_serdes) {
673 /* Mask HBA via NVRAM settings? */
7c3df132 674 ql_log(ql_log_info, vha, 0x0077,
7b833558 675 "Masking HBA WWPN %8phN (via NVRAM).\n", vha->port_name);
d4c760c2
AV		 676 return QLA_FUNCTION_FAILED;
677 }
678
cfb0919c 679 ql_dbg(ql_dbg_init, vha, 0x0078,
7c3df132 680 "Verifying loaded RISC code...\n");
1da177e4 681
e315cd28
AC		 682 if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) {
683 rval = ha->isp_ops->chip_diag(vha);
d19044c3
AV		 684 if (rval)
685 return (rval);
e315cd28 686 rval = qla2x00_setup_chip(vha);
d19044c3
AV		 687 if (rval)
688 return (rval);
1da177e4 689 }
a9083016 690
4d4df193 691 if (IS_QLA84XX(ha)) {
e315cd28 692 ha->cs84xx = qla84xx_get_chip(vha);
4d4df193 693 if (!ha->cs84xx) {
7c3df132 694 ql_log(ql_log_warn, vha, 0x00d0,
4d4df193
HK		 695 "Unable to configure ISP84XX.\n");
696 return QLA_FUNCTION_FAILED;
697 }
698 }
2d70c103
NB		 699
700 if (qla_ini_mode_enabled(vha))
701 rval = qla2x00_init_rings(vha);
702
2533cf67 703 ha->flags.chip_reset_done = 1;
1da177e4 704
9a069e19 705 if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) {
6c452a45 706 /* Issue verify 84xx FW IOCB to complete 84xx initialization */
9a069e19
GM		 707 rval = qla84xx_init_chip(vha);
708 if (rval != QLA_SUCCESS) {
7c3df132
SK		 709 ql_log(ql_log_warn, vha, 0x00d4,
710 "Unable to initialize ISP84XX.\n");
8d2b21db 711 qla84xx_put_chip(vha);
9a069e19
GM		 712 }
713 }
714
7d613ac6
SV		 715 /* Load the NIC Core f/w if we are the first protocol driver. */
716 if (IS_QLA8031(ha)) {
717 rval = qla83xx_nic_core_fw_load(vha);
718 if (rval)
719 ql_log(ql_log_warn, vha, 0x0124,
720 "Error in initializing NIC Core f/w.\n");
721 }
722
2f0f3f4f
MI		 723 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
724 qla24xx_read_fcp_prio_cfg(vha);
09ff701a 725
c46e65c7
JC		 726 if (IS_P3P_TYPE(ha))
727 qla82xx_set_driver_version(vha, QLA2XXX_VERSION);
728 else
729 qla25xx_set_driver_version(vha, QLA2XXX_VERSION);
730
1da177e4
LT		 731 return (rval);
732}
733
734/**
abbd8870 735 * qla2100_pci_config() - Setup ISP21xx PCI configuration registers.
1da177e4
LT		 736 * @ha: HA context
737 *
738 * Returns 0 on success.
739 */
abbd8870 740int
e315cd28 741qla2100_pci_config(scsi_qla_host_t *vha)
1da177e4 742{
a157b101 743 uint16_t w;
abbd8870 744 unsigned long flags;
e315cd28 745 struct qla_hw_data *ha = vha->hw;
3d71644c 746 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 747
1da177e4 748 pci_set_master(ha->pdev);
af6177d8 749 pci_try_set_mwi(ha->pdev);
1da177e4 750
1da177e4 751 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 752 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
abbd8870
AV		 753 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
754
737faece 755 pci_disable_rom(ha->pdev);
1da177e4
LT		 756
757 /* Get PCI bus information. */
758 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 759 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
1da177e4
LT		 760 spin_unlock_irqrestore(&ha->hardware_lock, flags);
761
abbd8870
AV		 762 return QLA_SUCCESS;
763}
1da177e4 764
abbd8870
AV		 765/**
766 * qla2300_pci_config() - Setup ISP23xx PCI configuration registers.
767 * @ha: HA context
768 *
769 * Returns 0 on success.
770 */
771int
e315cd28 772qla2300_pci_config(scsi_qla_host_t *vha)
abbd8870 773{
a157b101 774 uint16_t w;
abbd8870
AV		 775 unsigned long flags = 0;
776 uint32_t cnt;
e315cd28 777 struct qla_hw_data *ha = vha->hw;
3d71644c 778 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 779
abbd8870 780 pci_set_master(ha->pdev);
af6177d8 781 pci_try_set_mwi(ha->pdev);
1da177e4 782
abbd8870 783 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 784 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
1da177e4 785
abbd8870
AV		 786 if (IS_QLA2322(ha) || IS_QLA6322(ha))
787 w &= ~PCI_COMMAND_INTX_DISABLE;
a157b101 788 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1da177e4 789
abbd8870
AV		 790 /*
791 * If this is a 2300 card and not 2312, reset the
792 * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately,
793 * the 2310 also reports itself as a 2300 so we need to get the
794 * fb revision level -- a 6 indicates it really is a 2300 and
795 * not a 2310.
796 */
797 if (IS_QLA2300(ha)) {
798 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 799
abbd8870 800 /* Pause RISC. */
3d71644c 801 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
abbd8870 802 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 803 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
abbd8870 804 break;
1da177e4 805
abbd8870
AV		 806 udelay(10);
807 }
1da177e4 808
abbd8870 809 /* Select FPM registers. */
3d71644c
AV		 810 WRT_REG_WORD(&reg->ctrl_status, 0x20);
811 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 812
813 /* Get the fb rev level */
3d71644c 814 ha->fb_rev = RD_FB_CMD_REG(ha, reg);
abbd8870
AV		 815
816 if (ha->fb_rev == FPM_2300)
a157b101 817 pci_clear_mwi(ha->pdev);
abbd8870
AV		 818
819 /* Deselect FPM registers. */
3d71644c
AV		 820 WRT_REG_WORD(&reg->ctrl_status, 0x0);
821 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 822
823 /* Release RISC module. */
3d71644c 824 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
abbd8870 825 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 826 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0)
abbd8870
AV		 827 break;
828
829 udelay(10);
1da177e4 830 }
1da177e4 831
abbd8870
AV		 832 spin_unlock_irqrestore(&ha->hardware_lock, flags);
833 }
1da177e4 834
abbd8870
AV		 835 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
836
737faece 837 pci_disable_rom(ha->pdev);
1da177e4 838
abbd8870
AV		 839 /* Get PCI bus information. */
840 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 841 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 842 spin_unlock_irqrestore(&ha->hardware_lock, flags);
843
844 return QLA_SUCCESS;
1da177e4
LT		 845}
846
0107109e
AV		 847/**
848 * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers.
849 * @ha: HA context
850 *
851 * Returns 0 on success.
852 */
853int
e315cd28 854qla24xx_pci_config(scsi_qla_host_t *vha)
0107109e 855{
a157b101 856 uint16_t w;
0107109e 857 unsigned long flags = 0;
e315cd28 858 struct qla_hw_data *ha = vha->hw;
0107109e 859 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
0107109e
AV		 860
861 pci_set_master(ha->pdev);
af6177d8 862 pci_try_set_mwi(ha->pdev);
0107109e
AV		 863
864 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 865 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
0107109e
AV		 866 w &= ~PCI_COMMAND_INTX_DISABLE;
867 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
868
869 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
870
871 /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */
f85ec187
AV		 872 if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
873 pcix_set_mmrbc(ha->pdev, 2048);
0107109e
AV		 874
875 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 876 if (pci_is_pcie(ha->pdev))
5ffd3a52 877 pcie_set_readrq(ha->pdev, 4096);
0107109e 878
737faece 879 pci_disable_rom(ha->pdev);
0107109e 880
44c10138 881 ha->chip_revision = ha->pdev->revision;
a8488abe 882
0107109e
AV		 883 /* Get PCI bus information. */
884 spin_lock_irqsave(&ha->hardware_lock, flags);
885 ha->pci_attr = RD_REG_DWORD(&reg->ctrl_status);
886 spin_unlock_irqrestore(&ha->hardware_lock, flags);
887
888 return QLA_SUCCESS;
889}
890
c3a2f0df
AV		 891/**
892 * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers.
893 * @ha: HA context
894 *
895 * Returns 0 on success.
896 */
897int
e315cd28 898qla25xx_pci_config(scsi_qla_host_t *vha)
c3a2f0df
AV		 899{
900 uint16_t w;
e315cd28 901 struct qla_hw_data *ha = vha->hw;
c3a2f0df
AV		 902
903 pci_set_master(ha->pdev);
904 pci_try_set_mwi(ha->pdev);
905
906 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
907 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
908 w &= ~PCI_COMMAND_INTX_DISABLE;
909 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
910
911 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 912 if (pci_is_pcie(ha->pdev))
5ffd3a52 913 pcie_set_readrq(ha->pdev, 4096);
c3a2f0df 914
737faece 915 pci_disable_rom(ha->pdev);
c3a2f0df
AV		 916
917 ha->chip_revision = ha->pdev->revision;
918
919 return QLA_SUCCESS;
920}
921
1da177e4
LT		 922/**
923 * qla2x00_isp_firmware() - Choose firmware image.
924 * @ha: HA context
925 *
926 * Returns 0 on success.
927 */
928static int
e315cd28 929qla2x00_isp_firmware(scsi_qla_host_t *vha)
1da177e4
LT		 930{
931 int rval;
42e421b1
AV		 932 uint16_t loop_id, topo, sw_cap;
933 uint8_t domain, area, al_pa;
e315cd28 934 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 935
936 /* Assume loading risc code */
fa2a1ce5 937 rval = QLA_FUNCTION_FAILED;
1da177e4
LT		 938
939 if (ha->flags.disable_risc_code_load) {
7c3df132 940 ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n");
1da177e4
LT		 941
942 /* Verify checksum of loaded RISC code. */
e315cd28 943 rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address);
42e421b1
AV		 944 if (rval == QLA_SUCCESS) {
945 /* And, verify we are not in ROM code. */
e315cd28 946 rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa,
42e421b1
AV		 947 &area, &domain, &topo, &sw_cap);
948 }
1da177e4
LT		 949 }
950
7c3df132
SK		 951 if (rval)
952 ql_dbg(ql_dbg_init, vha, 0x007a,
953 "**** Load RISC code ****.\n");
1da177e4
LT		 954
955 return (rval);
956}
957
958/**
959 * qla2x00_reset_chip() - Reset ISP chip.
960 * @ha: HA context
961 *
962 * Returns 0 on success.
963 */
abbd8870 964void
e315cd28 965qla2x00_reset_chip(scsi_qla_host_t *vha)
1da177e4
LT		 966{
967 unsigned long flags = 0;
e315cd28 968 struct qla_hw_data *ha = vha->hw;
3d71644c 969 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 970 uint32_t cnt;
1da177e4
LT		 971 uint16_t cmd;
972
85880801
AV		 973 if (unlikely(pci_channel_offline(ha->pdev)))
974 return;
975
fd34f556 976 ha->isp_ops->disable_intrs(ha);
1da177e4
LT		 977
978 spin_lock_irqsave(&ha->hardware_lock, flags);
979
980 /* Turn off master enable */
981 cmd = 0;
982 pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd);
983 cmd &= ~PCI_COMMAND_MASTER;
984 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
985
986 if (!IS_QLA2100(ha)) {
987 /* Pause RISC. */
988 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
989 if (IS_QLA2200(ha) || IS_QLA2300(ha)) {
990 for (cnt = 0; cnt < 30000; cnt++) {
991 if ((RD_REG_WORD(&reg->hccr) &
992 HCCR_RISC_PAUSE) != 0)
993 break;
994 udelay(100);
995 }
996 } else {
997 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
998 udelay(10);
999 }
1000
1001 /* Select FPM registers. */
1002 WRT_REG_WORD(&reg->ctrl_status, 0x20);
1003 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1004
1005 /* FPM Soft Reset. */
1006 WRT_REG_WORD(&reg->fpm_diag_config, 0x100);
1007 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
1008
1009 /* Toggle Fpm Reset. */
1010 if (!IS_QLA2200(ha)) {
1011 WRT_REG_WORD(&reg->fpm_diag_config, 0x0);
1012 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
1013 }
1014
1015 /* Select frame buffer registers. */
1016 WRT_REG_WORD(&reg->ctrl_status, 0x10);
1017 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1018
1019 /* Reset frame buffer FIFOs. */
1020 if (IS_QLA2200(ha)) {
1021 WRT_FB_CMD_REG(ha, reg, 0xa000);
1022 RD_FB_CMD_REG(ha, reg); /* PCI Posting. */
1023 } else {
1024 WRT_FB_CMD_REG(ha, reg, 0x00fc);
1025
1026 /* Read back fb_cmd until zero or 3 seconds max */
1027 for (cnt = 0; cnt < 3000; cnt++) {
1028 if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0)
1029 break;
1030 udelay(100);
1031 }
1032 }
1033
1034 /* Select RISC module registers. */
1035 WRT_REG_WORD(&reg->ctrl_status, 0);
1036 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1037
1038 /* Reset RISC processor. */
1039 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
1040 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1041
1042 /* Release RISC processor. */
1043 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
1044 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1045 }
1046
1047 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
1048 WRT_REG_WORD(&reg->hccr, HCCR_CLR_HOST_INT);
1049
1050 /* Reset ISP chip. */
1051 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1052
1053 /* Wait for RISC to recover from reset. */
1054 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1055 /*
1056 * It is necessary to for a delay here since the card doesn't
1057 * respond to PCI reads during a reset. On some architectures
1058 * this will result in an MCA.
1059 */
1060 udelay(20);
1061 for (cnt = 30000; cnt; cnt--) {
1062 if ((RD_REG_WORD(&reg->ctrl_status) &
1063 CSR_ISP_SOFT_RESET) == 0)
1064 break;
1065 udelay(100);
1066 }
1067 } else
1068 udelay(10);
1069
1070 /* Reset RISC processor. */
1071 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
1072
1073 WRT_REG_WORD(&reg->semaphore, 0);
1074
1075 /* Release RISC processor. */
1076 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
1077 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1078
1079 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1080 for (cnt = 0; cnt < 30000; cnt++) {
ffb39f03 1081 if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY)
1da177e4 1082 break;
1da177e4
LT		 1083
1084 udelay(100);
1085 }
1086 } else
1087 udelay(100);
1088
1089 /* Turn on master enable */
1090 cmd |= PCI_COMMAND_MASTER;
1091 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
1092
1093 /* Disable RISC pause on FPM parity error. */
1094 if (!IS_QLA2100(ha)) {
1095 WRT_REG_WORD(&reg->hccr, HCCR_DISABLE_PARITY_PAUSE);
1096 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1097 }
1098
1099 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1100}
1101
b1d46989
MI		 1102/**
1103 * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC.
1104 *
1105 * Returns 0 on success.
1106 */
fa492630 1107static int
b1d46989
MI		 1108qla81xx_reset_mpi(scsi_qla_host_t *vha)
1109{
1110 uint16_t mb[4] = {0x1010, 0, 1, 0};
1111
6246b8a1
GM		 1112 if (!IS_QLA81XX(vha->hw))
1113 return QLA_SUCCESS;
1114
b1d46989
MI		 1115 return qla81xx_write_mpi_register(vha, mb);
1116}
1117
0107109e 1118/**
88c26663 1119 * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC.
0107109e
AV		 1120 * @ha: HA context
1121 *
1122 * Returns 0 on success.
1123 */
d14e72fb 1124static inline int
e315cd28 1125qla24xx_reset_risc(scsi_qla_host_t *vha)
0107109e
AV		 1126{
1127 unsigned long flags = 0;
e315cd28 1128 struct qla_hw_data *ha = vha->hw;
0107109e 1129 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
52c82823 1130 uint32_t cnt;
335a1cc9 1131 uint16_t wd;
b1d46989 1132 static int abts_cnt; /* ISP abort retry counts */
d14e72fb 1133 int rval = QLA_SUCCESS;
0107109e 1134
0107109e
AV		 1135 spin_lock_irqsave(&ha->hardware_lock, flags);
1136
1137 /* Reset RISC. */
1138 WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
1139 for (cnt = 0; cnt < 30000; cnt++) {
1140 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
1141 break;
1142
1143 udelay(10);
1144 }
1145
d14e72fb
HM		 1146 if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE))
1147 set_bit(DMA_SHUTDOWN_CMPL, &ha->fw_dump_cap_flags);
1148
1149 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017e,
1150 "HCCR: 0x%x, Control Status %x, DMA active status:0x%x\n",
1151 RD_REG_DWORD(&reg->hccr),
1152 RD_REG_DWORD(&reg->ctrl_status),
1153 (RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE));
1154
0107109e
AV		 1155 WRT_REG_DWORD(&reg->ctrl_status,
1156 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
335a1cc9 1157 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
88c26663 1158
335a1cc9 1159 udelay(100);
d14e72fb 1160
88c26663 1161 /* Wait for firmware to complete NVRAM accesses. */
52c82823 1162 RD_REG_WORD(&reg->mailbox0);
d14e72fb
HM		 1163 for (cnt = 10000; RD_REG_WORD(&reg->mailbox0) != 0 &&
1164 rval == QLA_SUCCESS; cnt--) {
88c26663 1165 barrier();
d14e72fb
HM		 1166 if (cnt)
1167 udelay(5);
1168 else
1169 rval = QLA_FUNCTION_TIMEOUT;
88c26663
AV		 1170 }
1171
d14e72fb
HM		 1172 if (rval == QLA_SUCCESS)
1173 set_bit(ISP_MBX_RDY, &ha->fw_dump_cap_flags);
1174
1175 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017f,
1176 "HCCR: 0x%x, MailBox0 Status 0x%x\n",
1177 RD_REG_DWORD(&reg->hccr),
1178 RD_REG_DWORD(&reg->mailbox0));
1179
335a1cc9 1180 /* Wait for soft-reset to complete. */
52c82823 1181 RD_REG_DWORD(&reg->ctrl_status);
d14e72fb 1182 for (cnt = 0; cnt < 6000000; cnt++) {
0107109e 1183 barrier();
d14e72fb
HM		 1184 if ((RD_REG_DWORD(&reg->ctrl_status) &
1185 CSRX_ISP_SOFT_RESET) == 0)
1186 break;
1187
1188 udelay(5);
0107109e 1189 }
d14e72fb
HM		 1190 if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_ISP_SOFT_RESET))
1191 set_bit(ISP_SOFT_RESET_CMPL, &ha->fw_dump_cap_flags);
1192
1193 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015d,
1194 "HCCR: 0x%x, Soft Reset status: 0x%x\n",
1195 RD_REG_DWORD(&reg->hccr),
1196 RD_REG_DWORD(&reg->ctrl_status));
0107109e 1197
b1d46989
MI		 1198 /* If required, do an MPI FW reset now */
1199 if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
1200 if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
1201 if (++abts_cnt < 5) {
1202 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1203 set_bit(MPI_RESET_NEEDED, &vha->dpc_flags);
1204 } else {
1205 /*
1206 * We exhausted the ISP abort retries. We have to
1207 * set the board offline.
1208 */
1209 abts_cnt = 0;
1210 vha->flags.online = 0;
1211 }
1212 }
1213 }
1214
0107109e
AV		 1215 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
1216 RD_REG_DWORD(&reg->hccr);
1217
1218 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
1219 RD_REG_DWORD(&reg->hccr);
1220
1221 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
1222 RD_REG_DWORD(&reg->hccr);
1223
52c82823 1224 RD_REG_WORD(&reg->mailbox0);
d14e72fb
HM		 1225 for (cnt = 6000000; RD_REG_WORD(&reg->mailbox0) != 0 &&
1226 rval == QLA_SUCCESS; cnt--) {
0107109e 1227 barrier();
d14e72fb
HM		 1228 if (cnt)
1229 udelay(5);
1230 else
1231 rval = QLA_FUNCTION_TIMEOUT;
0107109e 1232 }
d14e72fb
HM		 1233 if (rval == QLA_SUCCESS)
1234 set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags);
1235
1236 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015e,
1237 "Host Risc 0x%x, mailbox0 0x%x\n",
1238 RD_REG_DWORD(&reg->hccr),
1239 RD_REG_WORD(&reg->mailbox0));
0107109e
AV		 1240
1241 spin_unlock_irqrestore(&ha->hardware_lock, flags);
124f85e6 1242
d14e72fb
HM		 1243 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015f,
1244 "Driver in %s mode\n",
1245 IS_NOPOLLING_TYPE(ha) ? "Interrupt" : "Polling");
1246
124f85e6
AV		 1247 if (IS_NOPOLLING_TYPE(ha))
1248 ha->isp_ops->enable_intrs(ha);
d14e72fb
HM		 1249
1250 return rval;
0107109e
AV		 1251}
1252
4ea2c9c7
JC		 1253static void
1254qla25xx_read_risc_sema_reg(scsi_qla_host_t *vha, uint32_t *data)
1255{
1256 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
1257
1258 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
1259 *data = RD_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET);
1260
1261}
1262
1263static void
1264qla25xx_write_risc_sema_reg(scsi_qla_host_t *vha, uint32_t data)
1265{
1266 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
1267
1268 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
1269 WRT_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET, data);
1270}
1271
1272static void
1273qla25xx_manipulate_risc_semaphore(scsi_qla_host_t *vha)
1274{
1275 struct qla_hw_data *ha = vha->hw;
1276 uint32_t wd32 = 0;
1277 uint delta_msec = 100;
1278 uint elapsed_msec = 0;
1279 uint timeout_msec;
1280 ulong n;
1281
1282 if (!IS_QLA25XX(ha) && !IS_QLA2031(ha))
1283 return;
1284
1285attempt:
1286 timeout_msec = TIMEOUT_SEMAPHORE;
1287 n = timeout_msec / delta_msec;
1288 while (n--) {
1289 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_SET);
1290 qla25xx_read_risc_sema_reg(vha, &wd32);
1291 if (wd32 & RISC_SEMAPHORE)
1292 break;
1293 msleep(delta_msec);
1294 elapsed_msec += delta_msec;
1295 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
1296 goto force;
1297 }
1298
1299 if (!(wd32 & RISC_SEMAPHORE))
1300 goto force;
1301
1302 if (!(wd32 & RISC_SEMAPHORE_FORCE))
1303 goto acquired;
1304
1305 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_CLR);
1306 timeout_msec = TIMEOUT_SEMAPHORE_FORCE;
1307 n = timeout_msec / delta_msec;
1308 while (n--) {
1309 qla25xx_read_risc_sema_reg(vha, &wd32);
1310 if (!(wd32 & RISC_SEMAPHORE_FORCE))
1311 break;
1312 msleep(delta_msec);
1313 elapsed_msec += delta_msec;
1314 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
1315 goto force;
1316 }
1317
1318 if (wd32 & RISC_SEMAPHORE_FORCE)
1319 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_CLR);
1320
1321 goto attempt;
1322
1323force:
1324 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_SET);
1325
1326acquired:
1327 return;
1328}
1329
88c26663
AV		 1330/**
1331 * qla24xx_reset_chip() - Reset ISP24xx chip.
1332 * @ha: HA context
1333 *
1334 * Returns 0 on success.
1335 */
1336void
e315cd28 1337qla24xx_reset_chip(scsi_qla_host_t *vha)
88c26663 1338{
e315cd28 1339 struct qla_hw_data *ha = vha->hw;
85880801
AV		 1340
1341 if (pci_channel_offline(ha->pdev) &&
1342 ha->flags.pci_channel_io_perm_failure) {
1343 return;
1344 }
1345
fd34f556 1346 ha->isp_ops->disable_intrs(ha);
88c26663 1347
4ea2c9c7
JC		 1348 qla25xx_manipulate_risc_semaphore(vha);
1349
88c26663 1350 /* Perform RISC reset. */
e315cd28 1351 qla24xx_reset_risc(vha);
88c26663
AV		 1352}
1353
1da177e4
LT		 1354/**
1355 * qla2x00_chip_diag() - Test chip for proper operation.
1356 * @ha: HA context
1357 *
1358 * Returns 0 on success.
1359 */
abbd8870 1360int
e315cd28 1361qla2x00_chip_diag(scsi_qla_host_t *vha)
1da177e4
LT		 1362{
1363 int rval;
e315cd28 1364 struct qla_hw_data *ha = vha->hw;
3d71644c 1365 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 1366 unsigned long flags = 0;
1367 uint16_t data;
1368 uint32_t cnt;
1369 uint16_t mb[5];
73208dfd 1370 struct req_que *req = ha->req_q_map[0];
1da177e4
LT		 1371
1372 /* Assume a failed state */
1373 rval = QLA_FUNCTION_FAILED;
1374
7c3df132
SK		 1375 ql_dbg(ql_dbg_init, vha, 0x007b,
1376 "Testing device at %lx.\n", (u_long)&reg->flash_address);
1da177e4
LT		 1377
1378 spin_lock_irqsave(&ha->hardware_lock, flags);
1379
1380 /* Reset ISP chip. */
1381 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1382
1383 /*
1384 * We need to have a delay here since the card will not respond while
1385 * in reset causing an MCA on some architectures.
1386 */
1387 udelay(20);
1388 data = qla2x00_debounce_register(&reg->ctrl_status);
1389 for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {
1390 udelay(5);
1391 data = RD_REG_WORD(&reg->ctrl_status);
1392 barrier();
1393 }
1394
1395 if (!cnt)
1396 goto chip_diag_failed;
1397
7c3df132
SK		 1398 ql_dbg(ql_dbg_init, vha, 0x007c,
1399 "Reset register cleared by chip reset.\n");
1da177e4
LT		 1400
1401 /* Reset RISC processor. */
1402 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
1403 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
1404
1405 /* Workaround for QLA2312 PCI parity error */
1406 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1407 data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0));
1408 for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) {
1409 udelay(5);
1410 data = RD_MAILBOX_REG(ha, reg, 0);
fa2a1ce5 1411 barrier();
1da177e4
LT		 1412 }
1413 } else
1414 udelay(10);
1415
1416 if (!cnt)
1417 goto chip_diag_failed;
1418
1419 /* Check product ID of chip */
7c3df132 1420 ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product Id of chip.\n");
1da177e4
LT		 1421
1422 mb[1] = RD_MAILBOX_REG(ha, reg, 1);
1423 mb[2] = RD_MAILBOX_REG(ha, reg, 2);
1424 mb[3] = RD_MAILBOX_REG(ha, reg, 3);
1425 mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4));
1426 if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) ||
1427 mb[3] != PROD_ID_3) {
7c3df132
SK		 1428 ql_log(ql_log_warn, vha, 0x0062,
1429 "Wrong product ID = 0x%x,0x%x,0x%x.\n",
1430 mb[1], mb[2], mb[3]);
1da177e4
LT		 1431
1432 goto chip_diag_failed;
1433 }
1434 ha->product_id[0] = mb[1];
1435 ha->product_id[1] = mb[2];
1436 ha->product_id[2] = mb[3];
1437 ha->product_id[3] = mb[4];
1438
1439 /* Adjust fw RISC transfer size */
73208dfd 1440 if (req->length > 1024)
1da177e4
LT		 1441 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024;
1442 else
1443 ha->fw_transfer_size = REQUEST_ENTRY_SIZE *
73208dfd 1444 req->length;
1da177e4
LT		 1445
1446 if (IS_QLA2200(ha) &&
1447 RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) {
1448 /* Limit firmware transfer size with a 2200A */
7c3df132 1449 ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n");
1da177e4 1450
ea5b6382 1451 ha->device_type |= DT_ISP2200A;
1da177e4
LT		 1452 ha->fw_transfer_size = 128;
1453 }
1454
1455 /* Wrap Incoming Mailboxes Test. */
1456 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1457
7c3df132 1458 ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n");
e315cd28 1459 rval = qla2x00_mbx_reg_test(vha);
7c3df132
SK		 1460 if (rval)
1461 ql_log(ql_log_warn, vha, 0x0080,
1462 "Failed mailbox send register test.\n");
1463 else
1da177e4
LT		 1464 /* Flag a successful rval */
1465 rval = QLA_SUCCESS;
1da177e4
LT		 1466 spin_lock_irqsave(&ha->hardware_lock, flags);
1467
1468chip_diag_failed:
1469 if (rval)
7c3df132
SK		 1470 ql_log(ql_log_info, vha, 0x0081,
1471 "Chip diagnostics **** FAILED ****.\n");
1da177e4
LT		 1472
1473 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1474
1475 return (rval);
1476}
1477
0107109e
AV		 1478/**
1479 * qla24xx_chip_diag() - Test ISP24xx for proper operation.
1480 * @ha: HA context
1481 *
1482 * Returns 0 on success.
1483 */
1484int
e315cd28 1485qla24xx_chip_diag(scsi_qla_host_t *vha)
0107109e
AV		 1486{
1487 int rval;
e315cd28 1488 struct qla_hw_data *ha = vha->hw;
73208dfd 1489 struct req_que *req = ha->req_q_map[0];
0107109e 1490
7ec0effd 1491 if (IS_P3P_TYPE(ha))
a9083016
GM		 1492 return QLA_SUCCESS;
1493
73208dfd 1494 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
0107109e 1495
e315cd28 1496 rval = qla2x00_mbx_reg_test(vha);
0107109e 1497 if (rval) {
7c3df132
SK		 1498 ql_log(ql_log_warn, vha, 0x0082,
1499 "Failed mailbox send register test.\n");
0107109e
AV		 1500 } else {
1501 /* Flag a successful rval */
1502 rval = QLA_SUCCESS;
1503 }
1504
1505 return rval;
1506}
1507
a7a167bf 1508void
e315cd28 1509qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
0107109e 1510{
a7a167bf
AV		 1511 int rval;
1512 uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
73208dfd 1513 eft_size, fce_size, mq_size;
df613b96
AV		 1514 dma_addr_t tc_dma;
1515 void *tc;
e315cd28 1516 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 1517 struct req_que *req = ha->req_q_map[0];
1518 struct rsp_que *rsp = ha->rsp_q_map[0];
a7a167bf
AV		 1519
1520 if (ha->fw_dump) {
7c3df132
SK		 1521 ql_dbg(ql_dbg_init, vha, 0x00bd,
1522 "Firmware dump already allocated.\n");
a7a167bf
AV		 1523 return;
1524 }
d4e3e04d 1525
0107109e 1526 ha->fw_dumped = 0;
61f098dd 1527 ha->fw_dump_cap_flags = 0;
f73cb695
CD		 1528 dump_size = fixed_size = mem_size = eft_size = fce_size = mq_size = 0;
1529 req_q_size = rsp_q_size = 0;
1530
1531 if (IS_QLA27XX(ha))
1532 goto try_fce;
1533
d4e3e04d 1534 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
a7a167bf 1535 fixed_size = sizeof(struct qla2100_fw_dump);
d4e3e04d 1536 } else if (IS_QLA23XX(ha)) {
a7a167bf
AV		 1537 fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
1538 mem_size = (ha->fw_memory_size - 0x11000 + 1) *
1539 sizeof(uint16_t);
e428924c 1540 } else if (IS_FWI2_CAPABLE(ha)) {
6246b8a1
GM		 1541 if (IS_QLA83XX(ha))
1542 fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem);
1543 else if (IS_QLA81XX(ha))
3a03eb79
AV		 1544 fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
1545 else if (IS_QLA25XX(ha))
1546 fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
1547 else
1548 fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
f73cb695 1549
a7a167bf
AV		 1550 mem_size = (ha->fw_memory_size - 0x100000 + 1) *
1551 sizeof(uint32_t);
050c9bb1 1552 if (ha->mqenable) {
6246b8a1
GM		 1553 if (!IS_QLA83XX(ha))
1554 mq_size = sizeof(struct qla2xxx_mq_chain);
050c9bb1
GM		 1555 /*
1556 * Allocate maximum buffer size for all queues.
1557 * Resizing must be done at end-of-dump processing.
1558 */
1559 mq_size += ha->max_req_queues *
1560 (req->length * sizeof(request_t));
1561 mq_size += ha->max_rsp_queues *
1562 (rsp->length * sizeof(response_t));
1563 }
00876ae8 1564 if (ha->tgt.atio_ring)
2d70c103 1565 mq_size += ha->tgt.atio_q_length * sizeof(request_t);
df613b96 1566 /* Allocate memory for Fibre Channel Event Buffer. */
f73cb695
CD		 1567 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
1568 !IS_QLA27XX(ha))
436a7b11 1569 goto try_eft;
df613b96 1570
f73cb695
CD		 1571try_fce:
1572 if (ha->fce)
1573 dma_free_coherent(&ha->pdev->dev,
1574 FCE_SIZE, ha->fce, ha->fce_dma);
1575
1576 /* Allocate memory for Fibre Channel Event Buffer. */
0ea85b50
JP		 1577 tc = dma_zalloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
1578 GFP_KERNEL);
df613b96 1579 if (!tc) {
7c3df132
SK		 1580 ql_log(ql_log_warn, vha, 0x00be,
1581 "Unable to allocate (%d KB) for FCE.\n",
1582 FCE_SIZE / 1024);
17d98630 1583 goto try_eft;
df613b96
AV		 1584 }
1585
e315cd28 1586 rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS,
df613b96
AV		 1587 ha->fce_mb, &ha->fce_bufs);
1588 if (rval) {
7c3df132
SK		 1589 ql_log(ql_log_warn, vha, 0x00bf,
1590 "Unable to initialize FCE (%d).\n", rval);
df613b96
AV		 1591 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc,
1592 tc_dma);
1593 ha->flags.fce_enabled = 0;
17d98630 1594 goto try_eft;
df613b96 1595 }
cfb0919c 1596 ql_dbg(ql_dbg_init, vha, 0x00c0,
7c3df132 1597 "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024);
df613b96 1598
7d9dade3 1599 fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE;
df613b96
AV		 1600 ha->flags.fce_enabled = 1;
1601 ha->fce_dma = tc_dma;
1602 ha->fce = tc;
f73cb695 1603
436a7b11 1604try_eft:
f73cb695
CD		 1605 if (ha->eft)
1606 dma_free_coherent(&ha->pdev->dev,
1607 EFT_SIZE, ha->eft, ha->eft_dma);
1608
436a7b11 1609 /* Allocate memory for Extended Trace Buffer. */
0ea85b50
JP		 1610 tc = dma_zalloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
1611 GFP_KERNEL);
436a7b11 1612 if (!tc) {
7c3df132
SK		 1613 ql_log(ql_log_warn, vha, 0x00c1,
1614 "Unable to allocate (%d KB) for EFT.\n",
1615 EFT_SIZE / 1024);
436a7b11
AV		 1616 goto cont_alloc;
1617 }
1618
e315cd28 1619 rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
436a7b11 1620 if (rval) {
7c3df132
SK		 1621 ql_log(ql_log_warn, vha, 0x00c2,
1622 "Unable to initialize EFT (%d).\n", rval);
436a7b11
AV		 1623 dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc,
1624 tc_dma);
1625 goto cont_alloc;
1626 }
cfb0919c 1627 ql_dbg(ql_dbg_init, vha, 0x00c3,
7c3df132 1628 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
436a7b11
AV		 1629
1630 eft_size = EFT_SIZE;
1631 ha->eft_dma = tc_dma;
1632 ha->eft = tc;
d4e3e04d 1633 }
f73cb695 1634
a7a167bf 1635cont_alloc:
f73cb695
CD		 1636 if (IS_QLA27XX(ha)) {
1637 if (!ha->fw_dump_template) {
1638 ql_log(ql_log_warn, vha, 0x00ba,
1639 "Failed missing fwdump template\n");
1640 return;
1641 }
1642 dump_size = qla27xx_fwdt_calculate_dump_size(vha);
1643 ql_dbg(ql_dbg_init, vha, 0x00fa,
1644 "-> allocating fwdump (%x bytes)...\n", dump_size);
1645 goto allocate;
1646 }
1647
73208dfd
AC		 1648 req_q_size = req->length * sizeof(request_t);
1649 rsp_q_size = rsp->length * sizeof(response_t);
a7a167bf 1650 dump_size = offsetof(struct qla2xxx_fw_dump, isp);
2afa19a9 1651 dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size;
bb99de67
AV		 1652 ha->chain_offset = dump_size;
1653 dump_size += mq_size + fce_size;
d4e3e04d 1654
f73cb695 1655allocate:
d4e3e04d 1656 ha->fw_dump = vmalloc(dump_size);
a7a167bf 1657 if (!ha->fw_dump) {
7c3df132
SK		 1658 ql_log(ql_log_warn, vha, 0x00c4,
1659 "Unable to allocate (%d KB) for firmware dump.\n",
1660 dump_size / 1024);
a7a167bf 1661
e30d1756
MI		 1662 if (ha->fce) {
1663 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
1664 ha->fce_dma);
1665 ha->fce = NULL;
1666 ha->fce_dma = 0;
1667 }
1668
a7a167bf
AV		 1669 if (ha->eft) {
1670 dma_free_coherent(&ha->pdev->dev, eft_size, ha->eft,
1671 ha->eft_dma);
1672 ha->eft = NULL;
1673 ha->eft_dma = 0;
1674 }
1675 return;
1676 }
f73cb695 1677 ha->fw_dump_len = dump_size;
cfb0919c 1678 ql_dbg(ql_dbg_init, vha, 0x00c5,
7c3df132 1679 "Allocated (%d KB) for firmware dump.\n", dump_size / 1024);
a7a167bf 1680
f73cb695
CD		 1681 if (IS_QLA27XX(ha))
1682 return;
1683
a7a167bf
AV		 1684 ha->fw_dump->signature[0] = 'Q';
1685 ha->fw_dump->signature[1] = 'L';
1686 ha->fw_dump->signature[2] = 'G';
1687 ha->fw_dump->signature[3] = 'C';
ad950360 1688 ha->fw_dump->version = htonl(1);
a7a167bf
AV		 1689
1690 ha->fw_dump->fixed_size = htonl(fixed_size);
1691 ha->fw_dump->mem_size = htonl(mem_size);
1692 ha->fw_dump->req_q_size = htonl(req_q_size);
1693 ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
1694
1695 ha->fw_dump->eft_size = htonl(eft_size);
1696 ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma));
1697 ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma));
1698
1699 ha->fw_dump->header_size =
1700 htonl(offsetof(struct qla2xxx_fw_dump, isp));
0107109e
AV		 1701}
1702
18e7555a
AV		 1703static int
1704qla81xx_mpi_sync(scsi_qla_host_t *vha)
1705{
1706#define MPS_MASK 0xe0
1707 int rval;
1708 uint16_t dc;
1709 uint32_t dw;
18e7555a
AV		 1710
1711 if (!IS_QLA81XX(vha->hw))
1712 return QLA_SUCCESS;
1713
1714 rval = qla2x00_write_ram_word(vha, 0x7c00, 1);
1715 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1716 ql_log(ql_log_warn, vha, 0x0105,
1717 "Unable to acquire semaphore.\n");
18e7555a
AV		 1718 goto done;
1719 }
1720
1721 pci_read_config_word(vha->hw->pdev, 0x54, &dc);
1722 rval = qla2x00_read_ram_word(vha, 0x7a15, &dw);
1723 if (rval != QLA_SUCCESS) {
7c3df132 1724 ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n");
18e7555a
AV		 1725 goto done_release;
1726 }
1727
1728 dc &= MPS_MASK;
1729 if (dc == (dw & MPS_MASK))
1730 goto done_release;
1731
1732 dw &= ~MPS_MASK;
1733 dw |= dc;
1734 rval = qla2x00_write_ram_word(vha, 0x7a15, dw);
1735 if (rval != QLA_SUCCESS) {
7c3df132 1736 ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n");
18e7555a
AV		 1737 }
1738
1739done_release:
1740 rval = qla2x00_write_ram_word(vha, 0x7c00, 0);
1741 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1742 ql_log(ql_log_warn, vha, 0x006d,
1743 "Unable to release semaphore.\n");
18e7555a
AV		 1744 }
1745
1746done:
1747 return rval;
1748}
1749
8d93f550
CD		 1750int
1751qla2x00_alloc_outstanding_cmds(struct qla_hw_data *ha, struct req_que *req)
1752{
1753 /* Don't try to reallocate the array */
1754 if (req->outstanding_cmds)
1755 return QLA_SUCCESS;
1756
1757 if (!IS_FWI2_CAPABLE(ha) || (ha->mqiobase &&
1758 (ql2xmultique_tag || ql2xmaxqueues > 1)))
1759 req->num_outstanding_cmds = DEFAULT_OUTSTANDING_COMMANDS;
1760 else {
1761 if (ha->fw_xcb_count <= ha->fw_iocb_count)
1762 req->num_outstanding_cmds = ha->fw_xcb_count;
1763 else
1764 req->num_outstanding_cmds = ha->fw_iocb_count;
1765 }
1766
1767 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
1768 req->num_outstanding_cmds, GFP_KERNEL);
1769
1770 if (!req->outstanding_cmds) {
1771 /*
1772 * Try to allocate a minimal size just so we can get through
1773 * initialization.
1774 */
1775 req->num_outstanding_cmds = MIN_OUTSTANDING_COMMANDS;
1776 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
1777 req->num_outstanding_cmds, GFP_KERNEL);
1778
1779 if (!req->outstanding_cmds) {
1780 ql_log(ql_log_fatal, NULL, 0x0126,
1781 "Failed to allocate memory for "
1782 "outstanding_cmds for req_que %p.\n", req);
1783 req->num_outstanding_cmds = 0;
1784 return QLA_FUNCTION_FAILED;
1785 }
1786 }
1787
1788 return QLA_SUCCESS;
1789}
1790
1da177e4
LT		 1791/**
1792 * qla2x00_setup_chip() - Load and start RISC firmware.
1793 * @ha: HA context
1794 *
1795 * Returns 0 on success.
1796 */
1797static int
e315cd28 1798qla2x00_setup_chip(scsi_qla_host_t *vha)
1da177e4 1799{
0107109e
AV		 1800 int rval;
1801 uint32_t srisc_address = 0;
e315cd28 1802 struct qla_hw_data *ha = vha->hw;
3db0652e
AV		 1803 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1804 unsigned long flags;
dda772e8 1805 uint16_t fw_major_version;
3db0652e 1806
7ec0effd 1807 if (IS_P3P_TYPE(ha)) {
a9083016 1808 rval = ha->isp_ops->load_risc(vha, &srisc_address);
14e303d9
AV		 1809 if (rval == QLA_SUCCESS) {
1810 qla2x00_stop_firmware(vha);
a9083016 1811 goto enable_82xx_npiv;
14e303d9 1812 } else
b963752f 1813 goto failed;
a9083016
GM		 1814 }
1815
3db0652e
AV		 1816 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1817 /* Disable SRAM, Instruction RAM and GP RAM parity. */
1818 spin_lock_irqsave(&ha->hardware_lock, flags);
1819 WRT_REG_WORD(&reg->hccr, (HCCR_ENABLE_PARITY + 0x0));
1820 RD_REG_WORD(&reg->hccr);
1821 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1822 }
1da177e4 1823
18e7555a
AV		 1824 qla81xx_mpi_sync(vha);
1825
1da177e4 1826 /* Load firmware sequences */
e315cd28 1827 rval = ha->isp_ops->load_risc(vha, &srisc_address);
0107109e 1828 if (rval == QLA_SUCCESS) {
7c3df132
SK		 1829 ql_dbg(ql_dbg_init, vha, 0x00c9,
1830 "Verifying Checksum of loaded RISC code.\n");
1da177e4 1831
e315cd28 1832 rval = qla2x00_verify_checksum(vha, srisc_address);
1da177e4
LT		 1833 if (rval == QLA_SUCCESS) {
1834 /* Start firmware execution. */
7c3df132
SK		 1835 ql_dbg(ql_dbg_init, vha, 0x00ca,
1836 "Starting firmware.\n");
1da177e4 1837
e315cd28 1838 rval = qla2x00_execute_fw(vha, srisc_address);
1da177e4 1839 /* Retrieve firmware information. */
dda772e8 1840 if (rval == QLA_SUCCESS) {
a9083016 1841enable_82xx_npiv:
dda772e8 1842 fw_major_version = ha->fw_major_version;
7ec0effd 1843 if (IS_P3P_TYPE(ha))
3173167f 1844 qla82xx_check_md_needed(vha);
6246b8a1
GM		 1845 else
1846 rval = qla2x00_get_fw_version(vha);
ca9e9c3e
AV		 1847 if (rval != QLA_SUCCESS)
1848 goto failed;
2c3dfe3f 1849 ha->flags.npiv_supported = 0;
e315cd28 1850 if (IS_QLA2XXX_MIDTYPE(ha) &&
946fb891 1851 (ha->fw_attributes & BIT_2)) {
2c3dfe3f 1852 ha->flags.npiv_supported = 1;
4d0ea247
SJ		 1853 if ((!ha->max_npiv_vports) ||
1854 ((ha->max_npiv_vports + 1) %
eb66dc60 1855 MIN_MULTI_ID_FABRIC))
4d0ea247 1856 ha->max_npiv_vports =
eb66dc60 1857 MIN_MULTI_ID_FABRIC - 1;
4d0ea247 1858 }
24a08138 1859 qla2x00_get_resource_cnts(vha, NULL,
8d93f550 1860 &ha->fw_xcb_count, NULL, &ha->fw_iocb_count,
f3a0a77e 1861 &ha->max_npiv_vports, NULL);
d743de66 1862
8d93f550
CD		 1863 /*
1864 * Allocate the array of outstanding commands
1865 * now that we know the firmware resources.
1866 */
1867 rval = qla2x00_alloc_outstanding_cmds(ha,
1868 vha->req);
1869 if (rval != QLA_SUCCESS)
1870 goto failed;
1871
be5ea3cf 1872 if (!fw_major_version && ql2xallocfwdump
7ec0effd 1873 && !(IS_P3P_TYPE(ha)))
08de2844 1874 qla2x00_alloc_fw_dump(vha);
3b6e5b9d
CD		 1875 } else {
1876 goto failed;
1da177e4
LT		 1877 }
1878 } else {
7c3df132
SK		 1879 ql_log(ql_log_fatal, vha, 0x00cd,
1880 "ISP Firmware failed checksum.\n");
1881 goto failed;
1da177e4 1882 }
c74d88a4
AV		 1883 } else
1884 goto failed;
1da177e4 1885
3db0652e
AV		 1886 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1887 /* Enable proper parity. */
1888 spin_lock_irqsave(&ha->hardware_lock, flags);
1889 if (IS_QLA2300(ha))
1890 /* SRAM parity */
1891 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x1);
1892 else
1893 /* SRAM, Instruction RAM and GP RAM parity */
1894 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x7);
1895 RD_REG_WORD(&reg->hccr);
1896 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1897 }
1898
f3982d89
CD		 1899 if (IS_QLA27XX(ha))
1900 ha->flags.fac_supported = 1;
1901 else if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
1d2874de
JC		 1902 uint32_t size;
1903
1904 rval = qla81xx_fac_get_sector_size(vha, &size);
1905 if (rval == QLA_SUCCESS) {
1906 ha->flags.fac_supported = 1;
1907 ha->fdt_block_size = size << 2;
1908 } else {
7c3df132 1909 ql_log(ql_log_warn, vha, 0x00ce,
1d2874de
JC		 1910 "Unsupported FAC firmware (%d.%02d.%02d).\n",
1911 ha->fw_major_version, ha->fw_minor_version,
1912 ha->fw_subminor_version);
1ca60e3b 1913
f73cb695 1914 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
6246b8a1
GM		 1915 ha->flags.fac_supported = 0;
1916 rval = QLA_SUCCESS;
1917 }
1d2874de
JC		 1918 }
1919 }
ca9e9c3e 1920failed:
1da177e4 1921 if (rval) {
7c3df132
SK		 1922 ql_log(ql_log_fatal, vha, 0x00cf,
1923 "Setup chip ****FAILED****.\n");
1da177e4
LT		 1924 }
1925
1926 return (rval);
1927}
1928
1929/**
1930 * qla2x00_init_response_q_entries() - Initializes response queue entries.
1931 * @ha: HA context
1932 *
1933 * Beginning of request ring has initialization control block already built
1934 * by nvram config routine.
1935 *
1936 * Returns 0 on success.
1937 */
73208dfd
AC		 1938void
1939qla2x00_init_response_q_entries(struct rsp_que *rsp)
1da177e4
LT		 1940{
1941 uint16_t cnt;
1942 response_t *pkt;
1943
2afa19a9
AC		 1944 rsp->ring_ptr = rsp->ring;
1945 rsp->ring_index = 0;
1946 rsp->status_srb = NULL;
e315cd28
AC		 1947 pkt = rsp->ring_ptr;
1948 for (cnt = 0; cnt < rsp->length; cnt++) {
1da177e4
LT		 1949 pkt->signature = RESPONSE_PROCESSED;
1950 pkt++;
1951 }
1da177e4
LT		 1952}
1953
1954/**
1955 * qla2x00_update_fw_options() - Read and process firmware options.
1956 * @ha: HA context
1957 *
1958 * Returns 0 on success.
1959 */
abbd8870 1960void
e315cd28 1961qla2x00_update_fw_options(scsi_qla_host_t *vha)
1da177e4
LT		 1962{
1963 uint16_t swing, emphasis, tx_sens, rx_sens;
e315cd28 1964 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 1965
1966 memset(ha->fw_options, 0, sizeof(ha->fw_options));
e315cd28 1967 qla2x00_get_fw_options(vha, ha->fw_options);
1da177e4
LT		 1968
1969 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1970 return;
1971
1972 /* Serial Link options. */
7c3df132
SK		 1973 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
1974 "Serial link options.\n");
1975 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
1976 (uint8_t *)&ha->fw_seriallink_options,
1977 sizeof(ha->fw_seriallink_options));
1da177e4
LT		 1978
1979 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1980 if (ha->fw_seriallink_options[3] & BIT_2) {
1981 ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING;
1982
1983 /* 1G settings */
1984 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
1985 emphasis = (ha->fw_seriallink_options[2] &
1986 (BIT_4 | BIT_3)) >> 3;
1987 tx_sens = ha->fw_seriallink_options[0] &
fa2a1ce5 1988 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 1989 rx_sens = (ha->fw_seriallink_options[0] &
1990 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
1991 ha->fw_options[10] = (emphasis << 14) | (swing << 8);
1992 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
1993 if (rx_sens == 0x0)
1994 rx_sens = 0x3;
1995 ha->fw_options[10] |= (tx_sens << 4) | rx_sens;
1996 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
1997 ha->fw_options[10] |= BIT_5 |
1998 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
1999 (tx_sens & (BIT_1 | BIT_0));
2000
2001 /* 2G settings */
2002 swing = (ha->fw_seriallink_options[2] &
2003 (BIT_7 | BIT_6 | BIT_5)) >> 5;
2004 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
2005 tx_sens = ha->fw_seriallink_options[1] &
fa2a1ce5 2006 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 2007 rx_sens = (ha->fw_seriallink_options[1] &
2008 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
2009 ha->fw_options[11] = (emphasis << 14) | (swing << 8);
2010 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
2011 if (rx_sens == 0x0)
2012 rx_sens = 0x3;
2013 ha->fw_options[11] |= (tx_sens << 4) | rx_sens;
2014 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
2015 ha->fw_options[11] |= BIT_5 |
2016 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
2017 (tx_sens & (BIT_1 | BIT_0));
2018 }
2019
2020 /* FCP2 options. */
2021 /* Return command IOCBs without waiting for an ABTS to complete. */
2022 ha->fw_options[3] |= BIT_13;
2023
2024 /* LED scheme. */
2025 if (ha->flags.enable_led_scheme)
2026 ha->fw_options[2] |= BIT_12;
2027
48c02fde
AV		 2028 /* Detect ISP6312. */
2029 if (IS_QLA6312(ha))
2030 ha->fw_options[2] |= BIT_13;
2031
1da177e4 2032 /* Update firmware options. */
e315cd28 2033 qla2x00_set_fw_options(vha, ha->fw_options);
1da177e4
LT		 2034}
2035
0107109e 2036void
e315cd28 2037qla24xx_update_fw_options(scsi_qla_host_t *vha)
0107109e
AV		 2038{
2039 int rval;
e315cd28 2040 struct qla_hw_data *ha = vha->hw;
0107109e 2041
7ec0effd 2042 if (IS_P3P_TYPE(ha))
a9083016
GM		 2043 return;
2044
0107109e 2045 /* Update Serial Link options. */
f94097ed 2046 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0)
0107109e
AV		 2047 return;
2048
e315cd28 2049 rval = qla2x00_set_serdes_params(vha,
f94097ed
AV		 2050 le16_to_cpu(ha->fw_seriallink_options24[1]),
2051 le16_to_cpu(ha->fw_seriallink_options24[2]),
2052 le16_to_cpu(ha->fw_seriallink_options24[3]));
0107109e 2053 if (rval != QLA_SUCCESS) {
7c3df132 2054 ql_log(ql_log_warn, vha, 0x0104,
0107109e
AV		 2055 "Unable to update Serial Link options (%x).\n", rval);
2056 }
2057}
2058
abbd8870 2059void
e315cd28 2060qla2x00_config_rings(struct scsi_qla_host *vha)
abbd8870 2061{
e315cd28 2062 struct qla_hw_data *ha = vha->hw;
3d71644c 2063 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
73208dfd
AC		 2064 struct req_que *req = ha->req_q_map[0];
2065 struct rsp_que *rsp = ha->rsp_q_map[0];
abbd8870
AV		 2066
2067 /* Setup ring parameters in initialization control block. */
ad950360
BVA		 2068 ha->init_cb->request_q_outpointer = cpu_to_le16(0);
2069 ha->init_cb->response_q_inpointer = cpu_to_le16(0);
e315cd28
AC		 2070 ha->init_cb->request_q_length = cpu_to_le16(req->length);
2071 ha->init_cb->response_q_length = cpu_to_le16(rsp->length);
2072 ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
2073 ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
2074 ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
2075 ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
abbd8870
AV		 2076
2077 WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0);
2078 WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0);
2079 WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0);
2080 WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0);
2081 RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */
2082}
2083
0107109e 2084void
e315cd28 2085qla24xx_config_rings(struct scsi_qla_host *vha)
0107109e 2086{
e315cd28 2087 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 2088 device_reg_t __iomem *reg = ISP_QUE_REG(ha, 0);
2089 struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
2090 struct qla_msix_entry *msix;
0107109e 2091 struct init_cb_24xx *icb;
73208dfd
AC		 2092 uint16_t rid = 0;
2093 struct req_que *req = ha->req_q_map[0];
2094 struct rsp_que *rsp = ha->rsp_q_map[0];
0107109e 2095
6246b8a1 2096 /* Setup ring parameters in initialization control block. */
0107109e 2097 icb = (struct init_cb_24xx *)ha->init_cb;
ad950360
BVA		 2098 icb->request_q_outpointer = cpu_to_le16(0);
2099 icb->response_q_inpointer = cpu_to_le16(0);
e315cd28
AC		 2100 icb->request_q_length = cpu_to_le16(req->length);
2101 icb->response_q_length = cpu_to_le16(rsp->length);
2102 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
2103 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
2104 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
2105 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
0107109e 2106
2d70c103 2107 /* Setup ATIO queue dma pointers for target mode */
ad950360 2108 icb->atio_q_inpointer = cpu_to_le16(0);
2d70c103
NB		 2109 icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length);
2110 icb->atio_q_address[0] = cpu_to_le32(LSD(ha->tgt.atio_dma));
2111 icb->atio_q_address[1] = cpu_to_le32(MSD(ha->tgt.atio_dma));
2112
7c6300e3 2113 if (IS_SHADOW_REG_CAPABLE(ha))
ad950360 2114 icb->firmware_options_2 |= cpu_to_le32(BIT_30|BIT_29);
7c6300e3 2115
f73cb695 2116 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
ad950360
BVA		 2117 icb->qos = cpu_to_le16(QLA_DEFAULT_QUE_QOS);
2118 icb->rid = cpu_to_le16(rid);
73208dfd
AC		 2119 if (ha->flags.msix_enabled) {
2120 msix = &ha->msix_entries[1];
7c3df132
SK		 2121 ql_dbg(ql_dbg_init, vha, 0x00fd,
2122 "Registering vector 0x%x for base que.\n",
2123 msix->entry);
73208dfd
AC		 2124 icb->msix = cpu_to_le16(msix->entry);
2125 }
2126 /* Use alternate PCI bus number */
2127 if (MSB(rid))
ad950360 2128 icb->firmware_options_2 |= cpu_to_le32(BIT_19);
73208dfd
AC		 2129 /* Use alternate PCI devfn */
2130 if (LSB(rid))
ad950360 2131 icb->firmware_options_2 |= cpu_to_le32(BIT_18);
73208dfd 2132
3155754a 2133 /* Use Disable MSIX Handshake mode for capable adapters */
6246b8a1
GM		 2134 if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) &&
2135 (ha->flags.msix_enabled)) {
ad950360 2136 icb->firmware_options_2 &= cpu_to_le32(~BIT_22);
3155754a 2137 ha->flags.disable_msix_handshake = 1;
7c3df132
SK		 2138 ql_dbg(ql_dbg_init, vha, 0x00fe,
2139 "MSIX Handshake Disable Mode turned on.\n");
3155754a 2140 } else {
ad950360 2141 icb->firmware_options_2 |= cpu_to_le32(BIT_22);
3155754a 2142 }
ad950360 2143 icb->firmware_options_2 |= cpu_to_le32(BIT_23);
73208dfd
AC		 2144
2145 WRT_REG_DWORD(&reg->isp25mq.req_q_in, 0);
2146 WRT_REG_DWORD(&reg->isp25mq.req_q_out, 0);
2147 WRT_REG_DWORD(&reg->isp25mq.rsp_q_in, 0);
2148 WRT_REG_DWORD(&reg->isp25mq.rsp_q_out, 0);
2149 } else {
2150 WRT_REG_DWORD(&reg->isp24.req_q_in, 0);
2151 WRT_REG_DWORD(&reg->isp24.req_q_out, 0);
2152 WRT_REG_DWORD(&reg->isp24.rsp_q_in, 0);
2153 WRT_REG_DWORD(&reg->isp24.rsp_q_out, 0);
2154 }
aa230bc5 2155 qlt_24xx_config_rings(vha);
2d70c103 2156
73208dfd
AC		 2157 /* PCI posting */
2158 RD_REG_DWORD(&ioreg->hccr);
0107109e
AV		 2159}
2160
1da177e4
LT		 2161/**
2162 * qla2x00_init_rings() - Initializes firmware.
2163 * @ha: HA context
2164 *
2165 * Beginning of request ring has initialization control block already built
2166 * by nvram config routine.
2167 *
2168 * Returns 0 on success.
2169 */
8ae6d9c7 2170int
e315cd28 2171qla2x00_init_rings(scsi_qla_host_t *vha)
1da177e4
LT		 2172{
2173 int rval;
2174 unsigned long flags = 0;
29bdccbe 2175 int cnt, que;
e315cd28 2176 struct qla_hw_data *ha = vha->hw;
29bdccbe
AC		 2177 struct req_que *req;
2178 struct rsp_que *rsp;
2c3dfe3f
SJ		 2179 struct mid_init_cb_24xx *mid_init_cb =
2180 (struct mid_init_cb_24xx *) ha->init_cb;
1da177e4
LT		 2181
2182 spin_lock_irqsave(&ha->hardware_lock, flags);
2183
2184 /* Clear outstanding commands array. */
2afa19a9 2185 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe
AC		 2186 req = ha->req_q_map[que];
2187 if (!req)
2188 continue;
7c6300e3
JC		 2189 req->out_ptr = (void *)(req->ring + req->length);
2190 *req->out_ptr = 0;
8d93f550 2191 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++)
29bdccbe 2192 req->outstanding_cmds[cnt] = NULL;
1da177e4 2193
2afa19a9 2194 req->current_outstanding_cmd = 1;
1da177e4 2195
29bdccbe
AC		 2196 /* Initialize firmware. */
2197 req->ring_ptr = req->ring;
2198 req->ring_index = 0;
2199 req->cnt = req->length;
2200 }
1da177e4 2201
2afa19a9 2202 for (que = 0; que < ha->max_rsp_queues; que++) {
29bdccbe
AC		 2203 rsp = ha->rsp_q_map[que];
2204 if (!rsp)
2205 continue;
7c6300e3
JC		 2206 rsp->in_ptr = (void *)(rsp->ring + rsp->length);
2207 *rsp->in_ptr = 0;
29bdccbe 2208 /* Initialize response queue entries */
8ae6d9c7
GM		 2209 if (IS_QLAFX00(ha))
2210 qlafx00_init_response_q_entries(rsp);
2211 else
2212 qla2x00_init_response_q_entries(rsp);
29bdccbe 2213 }
1da177e4 2214
2d70c103
NB		 2215 ha->tgt.atio_ring_ptr = ha->tgt.atio_ring;
2216 ha->tgt.atio_ring_index = 0;
2217 /* Initialize ATIO queue entries */
2218 qlt_init_atio_q_entries(vha);
2219
e315cd28 2220 ha->isp_ops->config_rings(vha);
1da177e4
LT		 2221
2222 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2223
8ae6d9c7
GM		 2224 ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n");
2225
2226 if (IS_QLAFX00(ha)) {
2227 rval = qlafx00_init_firmware(vha, ha->init_cb_size);
2228 goto next_check;
2229 }
2230
1da177e4 2231 /* Update any ISP specific firmware options before initialization. */
e315cd28 2232 ha->isp_ops->update_fw_options(vha);
1da177e4 2233
605aa2bc 2234 if (ha->flags.npiv_supported) {
45980cc2 2235 if (ha->operating_mode == LOOP && !IS_CNA_CAPABLE(ha))
605aa2bc 2236 ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
c48339de 2237 mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
605aa2bc
LC		 2238 }
2239
24a08138 2240 if (IS_FWI2_CAPABLE(ha)) {
ad950360 2241 mid_init_cb->options = cpu_to_le16(BIT_1);
24a08138
AV		 2242 mid_init_cb->init_cb.execution_throttle =
2243 cpu_to_le16(ha->fw_xcb_count);
25232cc9
HM		 2244 /* D-Port Status */
2245 if (IS_DPORT_CAPABLE(ha))
2246 mid_init_cb->init_cb.firmware_options_1 |=
2247 cpu_to_le16(BIT_7);
2486c627
HM		 2248 /* Enable FA-WWPN */
2249 ha->flags.fawwpn_enabled =
2250 (mid_init_cb->init_cb.firmware_options_1 & BIT_6) ? 1 : 0;
2251 ql_dbg(ql_dbg_init, vha, 0x0141, "FA-WWPN Support: %s.\n",
2252 (ha->flags.fawwpn_enabled) ? "enabled" : "disabled");
24a08138 2253 }
2c3dfe3f 2254
e315cd28 2255 rval = qla2x00_init_firmware(vha, ha->init_cb_size);
8ae6d9c7 2256next_check:
1da177e4 2257 if (rval) {
7c3df132
SK		 2258 ql_log(ql_log_fatal, vha, 0x00d2,
2259 "Init Firmware **** FAILED ****.\n");
1da177e4 2260 } else {
7c3df132
SK		 2261 ql_dbg(ql_dbg_init, vha, 0x00d3,
2262 "Init Firmware -- success.\n");
1da177e4
LT		 2263 }
2264
2265 return (rval);
2266}
2267
2268/**
2269 * qla2x00_fw_ready() - Waits for firmware ready.
2270 * @ha: HA context
2271 *
2272 * Returns 0 on success.
2273 */
2274static int
e315cd28 2275qla2x00_fw_ready(scsi_qla_host_t *vha)
1da177e4
LT		 2276{
2277 int rval;
4d4df193 2278 unsigned long wtime, mtime, cs84xx_time;
1da177e4
LT		 2279 uint16_t min_wait; /* Minimum wait time if loop is down */
2280 uint16_t wait_time; /* Wait time if loop is coming ready */
b5a340dd 2281 uint16_t state[6];
e315cd28 2282 struct qla_hw_data *ha = vha->hw;
1da177e4 2283
8ae6d9c7
GM		 2284 if (IS_QLAFX00(vha->hw))
2285 return qlafx00_fw_ready(vha);
2286
1da177e4
LT		 2287 rval = QLA_SUCCESS;
2288
33461491
CD		 2289 /* Time to wait for loop down */
2290 if (IS_P3P_TYPE(ha))
2291 min_wait = 30;
2292 else
2293 min_wait = 20;
1da177e4
LT		 2294
2295 /*
2296 * Firmware should take at most one RATOV to login, plus 5 seconds for
2297 * our own processing.
2298 */
2299 if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) {
2300 wait_time = min_wait;
2301 }
2302
2303 /* Min wait time if loop down */
2304 mtime = jiffies + (min_wait * HZ);
2305
2306 /* wait time before firmware ready */
2307 wtime = jiffies + (wait_time * HZ);
2308
2309 /* Wait for ISP to finish LIP */
e315cd28 2310 if (!vha->flags.init_done)
7c3df132
SK		 2311 ql_log(ql_log_info, vha, 0x801e,
2312 "Waiting for LIP to complete.\n");
1da177e4
LT		 2313
2314 do {
5b939038 2315 memset(state, -1, sizeof(state));
e315cd28 2316 rval = qla2x00_get_firmware_state(vha, state);
1da177e4 2317 if (rval == QLA_SUCCESS) {
4d4df193 2318 if (state[0] < FSTATE_LOSS_OF_SYNC) {
e315cd28 2319 vha->device_flags &= ~DFLG_NO_CABLE;
1da177e4 2320 }
4d4df193 2321 if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) {
7c3df132
SK		 2322 ql_dbg(ql_dbg_taskm, vha, 0x801f,
2323 "fw_state=%x 84xx=%x.\n", state[0],
2324 state[2]);
4d4df193
HK		 2325 if ((state[2] & FSTATE_LOGGED_IN) &&
2326 (state[2] & FSTATE_WAITING_FOR_VERIFY)) {
7c3df132
SK		 2327 ql_dbg(ql_dbg_taskm, vha, 0x8028,
2328 "Sending verify iocb.\n");
4d4df193
HK		 2329
2330 cs84xx_time = jiffies;
e315cd28 2331 rval = qla84xx_init_chip(vha);
7c3df132
SK		 2332 if (rval != QLA_SUCCESS) {
2333 ql_log(ql_log_warn,
cfb0919c 2334 vha, 0x8007,
7c3df132 2335 "Init chip failed.\n");
4d4df193 2336 break;
7c3df132 2337 }
4d4df193
HK		 2338
2339 /* Add time taken to initialize. */
2340 cs84xx_time = jiffies - cs84xx_time;
2341 wtime += cs84xx_time;
2342 mtime += cs84xx_time;
cfb0919c 2343 ql_dbg(ql_dbg_taskm, vha, 0x8008,
7c3df132
SK		 2344 "Increasing wait time by %ld. "
2345 "New time %ld.\n", cs84xx_time,
2346 wtime);
4d4df193
HK		 2347 }
2348 } else if (state[0] == FSTATE_READY) {
7c3df132
SK		 2349 ql_dbg(ql_dbg_taskm, vha, 0x8037,
2350 "F/W Ready - OK.\n");
1da177e4 2351
e315cd28 2352 qla2x00_get_retry_cnt(vha, &ha->retry_count,
1da177e4
LT		 2353 &ha->login_timeout, &ha->r_a_tov);
2354
2355 rval = QLA_SUCCESS;
2356 break;
2357 }
2358
2359 rval = QLA_FUNCTION_FAILED;
2360
e315cd28 2361 if (atomic_read(&vha->loop_down_timer) &&
4d4df193 2362 state[0] != FSTATE_READY) {
1da177e4 2363 /* Loop down. Timeout on min_wait for states
fa2a1ce5
AV		 2364 * other than Wait for Login.
2365 */
1da177e4 2366 if (time_after_eq(jiffies, mtime)) {
7c3df132 2367 ql_log(ql_log_info, vha, 0x8038,
1da177e4
LT		 2368 "Cable is unplugged...\n");
2369
e315cd28 2370 vha->device_flags |= DFLG_NO_CABLE;
1da177e4
LT		 2371 break;
2372 }
2373 }
2374 } else {
2375 /* Mailbox cmd failed. Timeout on min_wait. */
cdbb0a4f 2376 if (time_after_eq(jiffies, mtime) ||
7190575f 2377 ha->flags.isp82xx_fw_hung)
1da177e4
LT		 2378 break;
2379 }
2380
2381 if (time_after_eq(jiffies, wtime))
2382 break;
2383
2384 /* Delay for a while */
2385 msleep(500);
1da177e4
LT		 2386 } while (1);
2387
7c3df132 2388 ql_dbg(ql_dbg_taskm, vha, 0x803a,
b5a340dd
JC		 2389 "fw_state=%x (%x, %x, %x, %x %x) curr time=%lx.\n", state[0],
2390 state[1], state[2], state[3], state[4], state[5], jiffies);
1da177e4 2391
cfb0919c 2392 if (rval && !(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132
SK		 2393 ql_log(ql_log_warn, vha, 0x803b,
2394 "Firmware ready **** FAILED ****.\n");
1da177e4
LT		 2395 }
2396
2397 return (rval);
2398}
2399
2400/*
2401* qla2x00_configure_hba
2402* Setup adapter context.
2403*
2404* Input:
2405* ha = adapter state pointer.
2406*
2407* Returns:
2408* 0 = success
2409*
2410* Context:
2411* Kernel context.
2412*/
2413static int
e315cd28 2414qla2x00_configure_hba(scsi_qla_host_t *vha)
1da177e4
LT		 2415{
2416 int rval;
2417 uint16_t loop_id;
2418 uint16_t topo;
2c3dfe3f 2419 uint16_t sw_cap;
1da177e4
LT		 2420 uint8_t al_pa;
2421 uint8_t area;
2422 uint8_t domain;
2423 char connect_type[22];
e315cd28 2424 struct qla_hw_data *ha = vha->hw;
f24b5cb8 2425 unsigned long flags;
61e1b269 2426 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 2427
2428 /* Get host addresses. */
e315cd28 2429 rval = qla2x00_get_adapter_id(vha,
2c3dfe3f 2430 &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
1da177e4 2431 if (rval != QLA_SUCCESS) {
e315cd28 2432 if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
6246b8a1 2433 IS_CNA_CAPABLE(ha) ||
33135aa2 2434 (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
7c3df132
SK		 2435 ql_dbg(ql_dbg_disc, vha, 0x2008,
2436 "Loop is in a transition state.\n");
33135aa2 2437 } else {
7c3df132
SK		 2438 ql_log(ql_log_warn, vha, 0x2009,
2439 "Unable to get host loop ID.\n");
61e1b269
JC		 2440 if (IS_FWI2_CAPABLE(ha) && (vha == base_vha) &&
2441 (rval == QLA_COMMAND_ERROR && loop_id == 0x1b)) {
2442 ql_log(ql_log_warn, vha, 0x1151,
2443 "Doing link init.\n");
2444 if (qla24xx_link_initialize(vha) == QLA_SUCCESS)
2445 return rval;
2446 }
e315cd28 2447 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
33135aa2 2448 }
1da177e4
LT		 2449 return (rval);
2450 }
2451
2452 if (topo == 4) {
7c3df132
SK		 2453 ql_log(ql_log_info, vha, 0x200a,
2454 "Cannot get topology - retrying.\n");
1da177e4
LT		 2455 return (QLA_FUNCTION_FAILED);
2456 }
2457
e315cd28 2458 vha->loop_id = loop_id;
1da177e4
LT		 2459
2460 /* initialize */
2461 ha->min_external_loopid = SNS_FIRST_LOOP_ID;
2462 ha->operating_mode = LOOP;
2c3dfe3f 2463 ha->switch_cap = 0;
1da177e4
LT		 2464
2465 switch (topo) {
2466 case 0:
7c3df132 2467 ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n");
1da177e4
LT		 2468 ha->current_topology = ISP_CFG_NL;
2469 strcpy(connect_type, "(Loop)");
2470 break;
2471
2472 case 1:
7c3df132 2473 ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n");
2c3dfe3f 2474 ha->switch_cap = sw_cap;
1da177e4
LT		 2475 ha->current_topology = ISP_CFG_FL;
2476 strcpy(connect_type, "(FL_Port)");
2477 break;
2478
2479 case 2:
7c3df132 2480 ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n");
1da177e4
LT		 2481 ha->operating_mode = P2P;
2482 ha->current_topology = ISP_CFG_N;
2483 strcpy(connect_type, "(N_Port-to-N_Port)");
2484 break;
2485
2486 case 3:
7c3df132 2487 ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n");
2c3dfe3f 2488 ha->switch_cap = sw_cap;
1da177e4
LT		 2489 ha->operating_mode = P2P;
2490 ha->current_topology = ISP_CFG_F;
2491 strcpy(connect_type, "(F_Port)");
2492 break;
2493
2494 default:
7c3df132
SK		 2495 ql_dbg(ql_dbg_disc, vha, 0x200f,
2496 "HBA in unknown topology %x, using NL.\n", topo);
1da177e4
LT		 2497 ha->current_topology = ISP_CFG_NL;
2498 strcpy(connect_type, "(Loop)");
2499 break;
2500 }
2501
2502 /* Save Host port and loop ID. */
2503 /* byte order - Big Endian */
e315cd28
AC		 2504 vha->d_id.b.domain = domain;
2505 vha->d_id.b.area = area;
2506 vha->d_id.b.al_pa = al_pa;
1da177e4 2507
f24b5cb8 2508 spin_lock_irqsave(&ha->vport_slock, flags);
2d70c103 2509 qlt_update_vp_map(vha, SET_AL_PA);
f24b5cb8 2510 spin_unlock_irqrestore(&ha->vport_slock, flags);
2d70c103 2511
e315cd28 2512 if (!vha->flags.init_done)
7c3df132
SK		 2513 ql_log(ql_log_info, vha, 0x2010,
2514 "Topology - %s, Host Loop address 0x%x.\n",
e315cd28 2515 connect_type, vha->loop_id);
1da177e4 2516
1da177e4
LT		 2517 return(rval);
2518}
2519
a9083016 2520inline void
e315cd28
AC		 2521qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
2522 char *def)
9bb9fcf2
AV		 2523{
2524 char *st, *en;
2525 uint16_t index;
e315cd28 2526 struct qla_hw_data *ha = vha->hw;
ab671149 2527 int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
6246b8a1 2528 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha);
9bb9fcf2
AV		 2529
2530 if (memcmp(model, BINZERO, len) != 0) {
2531 strncpy(ha->model_number, model, len);
2532 st = en = ha->model_number;
2533 en += len - 1;
2534 while (en > st) {
2535 if (*en != 0x20 && *en != 0x00)
2536 break;
2537 *en-- = '\0';
2538 }
2539
2540 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 2541 if (use_tbl &&
2542 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2 2543 index < QLA_MODEL_NAMES)
1ee27146
JC		 2544 strncpy(ha->model_desc,
2545 qla2x00_model_name[index * 2 + 1],
2546 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 2547 } else {
2548 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 2549 if (use_tbl &&
2550 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2
AV		 2551 index < QLA_MODEL_NAMES) {
2552 strcpy(ha->model_number,
2553 qla2x00_model_name[index * 2]);
1ee27146
JC		 2554 strncpy(ha->model_desc,
2555 qla2x00_model_name[index * 2 + 1],
2556 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 2557 } else {
2558 strcpy(ha->model_number, def);
2559 }
2560 }
1ee27146 2561 if (IS_FWI2_CAPABLE(ha))
e315cd28 2562 qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc,
1ee27146 2563 sizeof(ha->model_desc));
9bb9fcf2
AV		 2564}
2565
4e08df3f
DM		 2566/* On sparc systems, obtain port and node WWN from firmware
2567 * properties.
2568 */
e315cd28 2569static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv)
4e08df3f
DM		 2570{
2571#ifdef CONFIG_SPARC
e315cd28 2572 struct qla_hw_data *ha = vha->hw;
4e08df3f 2573 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 2574 struct device_node *dp = pci_device_to_OF_node(pdev);
2575 const u8 *val;
4e08df3f
DM		 2576 int len;
2577
2578 val = of_get_property(dp, "port-wwn", &len);
2579 if (val && len >= WWN_SIZE)
2580 memcpy(nv->port_name, val, WWN_SIZE);
2581
2582 val = of_get_property(dp, "node-wwn", &len);
2583 if (val && len >= WWN_SIZE)
2584 memcpy(nv->node_name, val, WWN_SIZE);
2585#endif
2586}
2587
1da177e4
LT		 2588/*
2589* NVRAM configuration for ISP 2xxx
2590*
2591* Input:
2592* ha = adapter block pointer.
2593*
2594* Output:
2595* initialization control block in response_ring
2596* host adapters parameters in host adapter block
2597*
2598* Returns:
2599* 0 = success.
2600*/
abbd8870 2601int
e315cd28 2602qla2x00_nvram_config(scsi_qla_host_t *vha)
1da177e4 2603{
4e08df3f 2604 int rval;
0107109e
AV		 2605 uint8_t chksum = 0;
2606 uint16_t cnt;
2607 uint8_t *dptr1, *dptr2;
e315cd28 2608 struct qla_hw_data *ha = vha->hw;
0107109e 2609 init_cb_t *icb = ha->init_cb;
281afe19
SJ		 2610 nvram_t *nv = ha->nvram;
2611 uint8_t *ptr = ha->nvram;
3d71644c 2612 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 2613
4e08df3f
DM		 2614 rval = QLA_SUCCESS;
2615
1da177e4 2616 /* Determine NVRAM starting address. */
0107109e 2617 ha->nvram_size = sizeof(nvram_t);
1da177e4
LT		 2618 ha->nvram_base = 0;
2619 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
2620 if ((RD_REG_WORD(&reg->ctrl_status) >> 14) == 1)
2621 ha->nvram_base = 0x80;
2622
2623 /* Get NVRAM data and calculate checksum. */
e315cd28 2624 ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size);
0107109e
AV		 2625 for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++)
2626 chksum += *ptr++;
1da177e4 2627
7c3df132
SK		 2628 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
2629 "Contents of NVRAM.\n");
2630 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
2631 (uint8_t *)nv, ha->nvram_size);
1da177e4
LT		 2632
2633 /* Bad NVRAM data, set defaults parameters. */
2634 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' ||
2635 nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) {
2636 /* Reset NVRAM data. */
7c3df132 2637 ql_log(ql_log_warn, vha, 0x0064,
9e336520 2638 "Inconsistent NVRAM "
7c3df132
SK		 2639 "detected: checksum=0x%x id=%c version=0x%x.\n",
2640 chksum, nv->id[0], nv->nvram_version);
2641 ql_log(ql_log_warn, vha, 0x0065,
2642 "Falling back to "
2643 "functioning (yet invalid -- WWPN) defaults.\n");
4e08df3f
DM		 2644
2645 /*
2646 * Set default initialization control block.
2647 */
2648 memset(nv, 0, ha->nvram_size);
2649 nv->parameter_block_version = ICB_VERSION;
2650
2651 if (IS_QLA23XX(ha)) {
2652 nv->firmware_options[0] = BIT_2 | BIT_1;
2653 nv->firmware_options[1] = BIT_7 | BIT_5;
2654 nv->add_firmware_options[0] = BIT_5;
2655 nv->add_firmware_options[1] = BIT_5 | BIT_4;
98aee70d 2656 nv->frame_payload_size = 2048;
4e08df3f
DM		 2657 nv->special_options[1] = BIT_7;
2658 } else if (IS_QLA2200(ha)) {
2659 nv->firmware_options[0] = BIT_2 | BIT_1;
2660 nv->firmware_options[1] = BIT_7 | BIT_5;
2661 nv->add_firmware_options[0] = BIT_5;
2662 nv->add_firmware_options[1] = BIT_5 | BIT_4;
98aee70d 2663 nv->frame_payload_size = 1024;
4e08df3f
DM		 2664 } else if (IS_QLA2100(ha)) {
2665 nv->firmware_options[0] = BIT_3 | BIT_1;
2666 nv->firmware_options[1] = BIT_5;
98aee70d 2667 nv->frame_payload_size = 1024;
4e08df3f
DM		 2668 }
2669
ad950360
BVA		 2670 nv->max_iocb_allocation = cpu_to_le16(256);
2671 nv->execution_throttle = cpu_to_le16(16);
4e08df3f
DM		 2672 nv->retry_count = 8;
2673 nv->retry_delay = 1;
2674
2675 nv->port_name[0] = 33;
2676 nv->port_name[3] = 224;
2677 nv->port_name[4] = 139;
2678
e315cd28 2679 qla2xxx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 2680
2681 nv->login_timeout = 4;
2682
2683 /*
2684 * Set default host adapter parameters
2685 */
2686 nv->host_p[1] = BIT_2;
2687 nv->reset_delay = 5;
2688 nv->port_down_retry_count = 8;
ad950360 2689 nv->max_luns_per_target = cpu_to_le16(8);
4e08df3f
DM		 2690 nv->link_down_timeout = 60;
2691
2692 rval = 1;
1da177e4
LT		 2693 }
2694
2695#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
2696 /*
2697 * The SN2 does not provide BIOS emulation which means you can't change
2698 * potentially bogus BIOS settings. Force the use of default settings
2699 * for link rate and frame size. Hope that the rest of the settings
2700 * are valid.
2701 */
2702 if (ia64_platform_is("sn2")) {
98aee70d 2703 nv->frame_payload_size = 2048;
1da177e4
LT		 2704 if (IS_QLA23XX(ha))
2705 nv->special_options[1] = BIT_7;
2706 }
2707#endif
2708
2709 /* Reset Initialization control block */
0107109e 2710 memset(icb, 0, ha->init_cb_size);
1da177e4
LT		 2711
2712 /*
2713 * Setup driver NVRAM options.
2714 */
2715 nv->firmware_options[0] |= (BIT_6 | BIT_1);
2716 nv->firmware_options[0] &= ~(BIT_5 | BIT_4);
2717 nv->firmware_options[1] |= (BIT_5 | BIT_0);
2718 nv->firmware_options[1] &= ~BIT_4;
2719
2720 if (IS_QLA23XX(ha)) {
2721 nv->firmware_options[0] |= BIT_2;
2722 nv->firmware_options[0] &= ~BIT_3;
2d70c103 2723 nv->special_options[0] &= ~BIT_6;
0107109e 2724 nv->add_firmware_options[1] |= BIT_5 | BIT_4;
1da177e4
LT		 2725
2726 if (IS_QLA2300(ha)) {
2727 if (ha->fb_rev == FPM_2310) {
2728 strcpy(ha->model_number, "QLA2310");
2729 } else {
2730 strcpy(ha->model_number, "QLA2300");
2731 }
2732 } else {
e315cd28 2733 qla2x00_set_model_info(vha, nv->model_number,
9bb9fcf2 2734 sizeof(nv->model_number), "QLA23xx");
1da177e4
LT		 2735 }
2736 } else if (IS_QLA2200(ha)) {
2737 nv->firmware_options[0] |= BIT_2;
2738 /*
2739 * 'Point-to-point preferred, else loop' is not a safe
2740 * connection mode setting.
2741 */
2742 if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
2743 (BIT_5 | BIT_4)) {
2744 /* Force 'loop preferred, else point-to-point'. */
2745 nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
2746 nv->add_firmware_options[0] |= BIT_5;
2747 }
2748 strcpy(ha->model_number, "QLA22xx");
2749 } else /*if (IS_QLA2100(ha))*/ {
2750 strcpy(ha->model_number, "QLA2100");
2751 }
2752
2753 /*
2754 * Copy over NVRAM RISC parameter block to initialization control block.
2755 */
2756 dptr1 = (uint8_t *)icb;
2757 dptr2 = (uint8_t *)&nv->parameter_block_version;
2758 cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;
2759 while (cnt--)
2760 *dptr1++ = *dptr2++;
2761
2762 /* Copy 2nd half. */
2763 dptr1 = (uint8_t *)icb->add_firmware_options;
2764 cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;
2765 while (cnt--)
2766 *dptr1++ = *dptr2++;
2767
5341e868
AV		 2768 /* Use alternate WWN? */
2769 if (nv->host_p[1] & BIT_7) {
2770 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
2771 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
2772 }
2773
1da177e4
LT		 2774 /* Prepare nodename */
2775 if ((icb->firmware_options[1] & BIT_6) == 0) {
2776 /*
2777 * Firmware will apply the following mask if the nodename was
2778 * not provided.
2779 */
2780 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
2781 icb->node_name[0] &= 0xF0;
2782 }
2783
2784 /*
2785 * Set host adapter parameters.
2786 */
3ce8866c
SK		 2787
2788 /*
2789 * BIT_7 in the host-parameters section allows for modification to
2790 * internal driver logging.
2791 */
0181944f 2792 if (nv->host_p[0] & BIT_7)
cfb0919c 2793 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
1da177e4
LT		 2794 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
2795 /* Always load RISC code on non ISP2[12]00 chips. */
2796 if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
2797 ha->flags.disable_risc_code_load = 0;
2798 ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0);
2799 ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
2800 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
06c22bd1 2801 ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
d4c760c2 2802 ha->flags.disable_serdes = 0;
1da177e4
LT		 2803
2804 ha->operating_mode =
2805 (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
2806
2807 memcpy(ha->fw_seriallink_options, nv->seriallink_options,
2808 sizeof(ha->fw_seriallink_options));
2809
2810 /* save HBA serial number */
2811 ha->serial0 = icb->port_name[5];
2812 ha->serial1 = icb->port_name[6];
2813 ha->serial2 = icb->port_name[7];
e315cd28
AC		 2814 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
2815 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
1da177e4 2816
ad950360 2817 icb->execution_throttle = cpu_to_le16(0xFFFF);
1da177e4
LT		 2818
2819 ha->retry_count = nv->retry_count;
2820
2821 /* Set minimum login_timeout to 4 seconds. */
5b91490e 2822 if (nv->login_timeout != ql2xlogintimeout)
1da177e4
LT		 2823 nv->login_timeout = ql2xlogintimeout;
2824 if (nv->login_timeout < 4)
2825 nv->login_timeout = 4;
2826 ha->login_timeout = nv->login_timeout;
2827 icb->login_timeout = nv->login_timeout;
2828
00a537b8
AV		 2829 /* Set minimum RATOV to 100 tenths of a second. */
2830 ha->r_a_tov = 100;
1da177e4 2831
1da177e4
LT		 2832 ha->loop_reset_delay = nv->reset_delay;
2833
1da177e4
LT		 2834 /* Link Down Timeout = 0:
2835 *
2836 * When Port Down timer expires we will start returning
2837 * I/O's to OS with "DID_NO_CONNECT".
2838 *
2839 * Link Down Timeout != 0:
2840 *
2841 * The driver waits for the link to come up after link down
2842 * before returning I/Os to OS with "DID_NO_CONNECT".
fa2a1ce5 2843 */
1da177e4
LT		 2844 if (nv->link_down_timeout == 0) {
2845 ha->loop_down_abort_time =
354d6b21 2846 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
1da177e4
LT		 2847 } else {
2848 ha->link_down_timeout = nv->link_down_timeout;
2849 ha->loop_down_abort_time =
2850 (LOOP_DOWN_TIME - ha->link_down_timeout);
fa2a1ce5 2851 }
1da177e4 2852
1da177e4
LT		 2853 /*
2854 * Need enough time to try and get the port back.
2855 */
2856 ha->port_down_retry_count = nv->port_down_retry_count;
2857 if (qlport_down_retry)
2858 ha->port_down_retry_count = qlport_down_retry;
2859 /* Set login_retry_count */
2860 ha->login_retry_count = nv->retry_count;
2861 if (ha->port_down_retry_count == nv->port_down_retry_count &&
2862 ha->port_down_retry_count > 3)
2863 ha->login_retry_count = ha->port_down_retry_count;
2864 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
2865 ha->login_retry_count = ha->port_down_retry_count;
2866 if (ql2xloginretrycount)
2867 ha->login_retry_count = ql2xloginretrycount;
2868
ad950360 2869 icb->lun_enables = cpu_to_le16(0);
1da177e4
LT		 2870 icb->command_resource_count = 0;
2871 icb->immediate_notify_resource_count = 0;
ad950360 2872 icb->timeout = cpu_to_le16(0);
1da177e4
LT		 2873
2874 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
2875 /* Enable RIO */
2876 icb->firmware_options[0] &= ~BIT_3;
2877 icb->add_firmware_options[0] &=
2878 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
2879 icb->add_firmware_options[0] |= BIT_2;
2880 icb->response_accumulation_timer = 3;
2881 icb->interrupt_delay_timer = 5;
2882
e315cd28 2883 vha->flags.process_response_queue = 1;
1da177e4 2884 } else {
4fdfefe5 2885 /* Enable ZIO. */
e315cd28 2886 if (!vha->flags.init_done) {
4fdfefe5
AV		 2887 ha->zio_mode = icb->add_firmware_options[0] &
2888 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
2889 ha->zio_timer = icb->interrupt_delay_timer ?
2890 icb->interrupt_delay_timer: 2;
2891 }
1da177e4
LT		 2892 icb->add_firmware_options[0] &=
2893 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
e315cd28 2894 vha->flags.process_response_queue = 0;
4fdfefe5 2895 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d
AV		 2896 ha->zio_mode = QLA_ZIO_MODE_6;
2897
7c3df132 2898 ql_log(ql_log_info, vha, 0x0068,
4fdfefe5
AV		 2899 "ZIO mode %d enabled; timer delay (%d us).\n",
2900 ha->zio_mode, ha->zio_timer * 100);
1da177e4 2901
4fdfefe5
AV		 2902 icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;
2903 icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;
e315cd28 2904 vha->flags.process_response_queue = 1;
1da177e4
LT		 2905 }
2906 }
2907
4e08df3f 2908 if (rval) {
7c3df132
SK		 2909 ql_log(ql_log_warn, vha, 0x0069,
2910 "NVRAM configuration failed.\n");
4e08df3f
DM		 2911 }
2912 return (rval);
1da177e4
LT		 2913}
2914
19a7b4ae
JSEC		 2915static void
2916qla2x00_rport_del(void *data)
2917{
2918 fc_port_t *fcport = data;
d97994dc 2919 struct fc_rport *rport;
2d70c103 2920 scsi_qla_host_t *vha = fcport->vha;
044d78e1 2921 unsigned long flags;
d97994dc 2922
044d78e1 2923 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
ac280b67 2924 rport = fcport->drport ? fcport->drport: fcport->rport;
d97994dc 2925 fcport->drport = NULL;
044d78e1 2926 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
2d70c103 2927 if (rport) {
d97994dc 2928 fc_remote_port_delete(rport);
2d70c103
NB		 2929 /*
2930 * Release the target mode FC NEXUS in qla_target.c code
2931 * if target mod is enabled.
2932 */
2933 qlt_fc_port_deleted(vha, fcport);
2934 }
19a7b4ae
JSEC		 2935}
2936
1da177e4
LT		 2937/**
2938 * qla2x00_alloc_fcport() - Allocate a generic fcport.
2939 * @ha: HA context
2940 * @flags: allocation flags
2941 *
2942 * Returns a pointer to the allocated fcport, or NULL, if none available.
2943 */
9a069e19 2944fc_port_t *
e315cd28 2945qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags)
1da177e4
LT		 2946{
2947 fc_port_t *fcport;
2948
bbfbbbc1
MK		 2949 fcport = kzalloc(sizeof(fc_port_t), flags);
2950 if (!fcport)
2951 return NULL;
1da177e4
LT		 2952
2953 /* Setup fcport template structure. */
e315cd28 2954 fcport->vha = vha;
1da177e4
LT		 2955 fcport->port_type = FCT_UNKNOWN;
2956 fcport->loop_id = FC_NO_LOOP_ID;
ec426e10 2957 qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
ad3e0eda 2958 fcport->supported_classes = FC_COS_UNSPECIFIED;
1da177e4 2959
bbfbbbc1 2960 return fcport;
1da177e4
LT		 2961}
2962
2963/*
2964 * qla2x00_configure_loop
2965 * Updates Fibre Channel Device Database with what is actually on loop.
2966 *
2967 * Input:
2968 * ha = adapter block pointer.
2969 *
2970 * Returns:
2971 * 0 = success.
2972 * 1 = error.
2973 * 2 = database was full and device was not configured.
2974 */
2975static int
e315cd28 2976qla2x00_configure_loop(scsi_qla_host_t *vha)
1da177e4
LT		 2977{
2978 int rval;
2979 unsigned long flags, save_flags;
e315cd28 2980 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2981 rval = QLA_SUCCESS;
2982
2983 /* Get Initiator ID */
e315cd28
AC		 2984 if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) {
2985 rval = qla2x00_configure_hba(vha);
1da177e4 2986 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2987 ql_dbg(ql_dbg_disc, vha, 0x2013,
2988 "Unable to configure HBA.\n");
1da177e4
LT		 2989 return (rval);
2990 }
2991 }
2992
e315cd28 2993 save_flags = flags = vha->dpc_flags;
7c3df132
SK		 2994 ql_dbg(ql_dbg_disc, vha, 0x2014,
2995 "Configure loop -- dpc flags = 0x%lx.\n", flags);
1da177e4
LT		 2996
2997 /*
2998 * If we have both an RSCN and PORT UPDATE pending then handle them
2999 * both at the same time.
3000 */
e315cd28
AC		 3001 clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
3002 clear_bit(RSCN_UPDATE, &vha->dpc_flags);
1da177e4 3003
3064ff39
MH		 3004 qla2x00_get_data_rate(vha);
3005
1da177e4
LT		 3006 /* Determine what we need to do */
3007 if (ha->current_topology == ISP_CFG_FL &&
3008 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
3009
1da177e4
LT		 3010 set_bit(RSCN_UPDATE, &flags);
3011
3012 } else if (ha->current_topology == ISP_CFG_F &&
3013 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
3014
1da177e4
LT		 3015 set_bit(RSCN_UPDATE, &flags);
3016 clear_bit(LOCAL_LOOP_UPDATE, &flags);
21333b48
AV		 3017
3018 } else if (ha->current_topology == ISP_CFG_N) {
3019 clear_bit(RSCN_UPDATE, &flags);
1da177e4 3020
e315cd28 3021 } else if (!vha->flags.online ||
1da177e4
LT		 3022 (test_bit(ABORT_ISP_ACTIVE, &flags))) {
3023
1da177e4
LT		 3024 set_bit(RSCN_UPDATE, &flags);
3025 set_bit(LOCAL_LOOP_UPDATE, &flags);
3026 }
3027
3028 if (test_bit(LOCAL_LOOP_UPDATE, &flags)) {
7c3df132
SK		 3029 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
3030 ql_dbg(ql_dbg_disc, vha, 0x2015,
3031 "Loop resync needed, failing.\n");
1da177e4 3032 rval = QLA_FUNCTION_FAILED;
642ef983 3033 } else
e315cd28 3034 rval = qla2x00_configure_local_loop(vha);
1da177e4
LT		 3035 }
3036
3037 if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
7c3df132
SK		 3038 if (LOOP_TRANSITION(vha)) {
3039 ql_dbg(ql_dbg_disc, vha, 0x201e,
3040 "Needs RSCN update and loop transition.\n");
1da177e4 3041 rval = QLA_FUNCTION_FAILED;
7c3df132 3042 }
e315cd28
AC		 3043 else
3044 rval = qla2x00_configure_fabric(vha);
1da177e4
LT		 3045 }
3046
3047 if (rval == QLA_SUCCESS) {
e315cd28
AC		 3048 if (atomic_read(&vha->loop_down_timer) ||
3049 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4
LT		 3050 rval = QLA_FUNCTION_FAILED;
3051 } else {
e315cd28 3052 atomic_set(&vha->loop_state, LOOP_READY);
7c3df132
SK		 3053 ql_dbg(ql_dbg_disc, vha, 0x2069,
3054 "LOOP READY.\n");
1da177e4
LT		 3055 }
3056 }
3057
3058 if (rval) {
7c3df132
SK		 3059 ql_dbg(ql_dbg_disc, vha, 0x206a,
3060 "%s *** FAILED ***.\n", __func__);
1da177e4 3061 } else {
7c3df132
SK		 3062 ql_dbg(ql_dbg_disc, vha, 0x206b,
3063 "%s: exiting normally.\n", __func__);
1da177e4
LT		 3064 }
3065
cc3ef7bc 3066 /* Restore state if a resync event occurred during processing */
e315cd28 3067 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4 3068 if (test_bit(LOCAL_LOOP_UPDATE, &save_flags))
e315cd28 3069 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
f4658b6c 3070 if (test_bit(RSCN_UPDATE, &save_flags)) {
e315cd28 3071 set_bit(RSCN_UPDATE, &vha->dpc_flags);
f4658b6c 3072 }
1da177e4
LT		 3073 }
3074
3075 return (rval);
3076}
3077
3078
3079
3080/*
3081 * qla2x00_configure_local_loop
3082 * Updates Fibre Channel Device Database with local loop devices.
3083 *
3084 * Input:
3085 * ha = adapter block pointer.
3086 *
3087 * Returns:
3088 * 0 = success.
3089 */
3090static int
e315cd28 3091qla2x00_configure_local_loop(scsi_qla_host_t *vha)
1da177e4
LT		 3092{
3093 int rval, rval2;
3094 int found_devs;
3095 int found;
3096 fc_port_t *fcport, *new_fcport;
3097
3098 uint16_t index;
3099 uint16_t entries;
3100 char *id_iter;
3101 uint16_t loop_id;
3102 uint8_t domain, area, al_pa;
e315cd28 3103 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3104
3105 found_devs = 0;
3106 new_fcport = NULL;
642ef983 3107 entries = MAX_FIBRE_DEVICES_LOOP;
1da177e4 3108
1da177e4 3109 /* Get list of logged in devices. */
642ef983 3110 memset(ha->gid_list, 0, qla2x00_gid_list_size(ha));
e315cd28 3111 rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma,
1da177e4
LT		 3112 &entries);
3113 if (rval != QLA_SUCCESS)
3114 goto cleanup_allocation;
3115
7c3df132
SK		 3116 ql_dbg(ql_dbg_disc, vha, 0x2017,
3117 "Entries in ID list (%d).\n", entries);
3118 ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
3119 (uint8_t *)ha->gid_list,
3120 entries * sizeof(struct gid_list_info));
1da177e4
LT		 3121
3122 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 3123 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3124 if (new_fcport == NULL) {
7c3df132
SK		 3125 ql_log(ql_log_warn, vha, 0x2018,
3126 "Memory allocation failed for fcport.\n");
1da177e4
LT		 3127 rval = QLA_MEMORY_ALLOC_FAILED;
3128 goto cleanup_allocation;
3129 }
3130 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
3131
3132 /*
3133 * Mark local devices that were present with FCF_DEVICE_LOST for now.
3134 */
e315cd28 3135 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 3136 if (atomic_read(&fcport->state) == FCS_ONLINE &&
3137 fcport->port_type != FCT_BROADCAST &&
3138 (fcport->flags & FCF_FABRIC_DEVICE) == 0) {
3139
7c3df132
SK		 3140 ql_dbg(ql_dbg_disc, vha, 0x2019,
3141 "Marking port lost loop_id=0x%04x.\n",
3142 fcport->loop_id);
1da177e4 3143
ec426e10 3144 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3145 }
3146 }
3147
3148 /* Add devices to port list. */
3149 id_iter = (char *)ha->gid_list;
3150 for (index = 0; index < entries; index++) {
3151 domain = ((struct gid_list_info *)id_iter)->domain;
3152 area = ((struct gid_list_info *)id_iter)->area;
3153 al_pa = ((struct gid_list_info *)id_iter)->al_pa;
abbd8870 3154 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1da177e4
LT		 3155 loop_id = (uint16_t)
3156 ((struct gid_list_info *)id_iter)->loop_id_2100;
abbd8870 3157 else
1da177e4
LT		 3158 loop_id = le16_to_cpu(
3159 ((struct gid_list_info *)id_iter)->loop_id);
abbd8870 3160 id_iter += ha->gid_list_info_size;
1da177e4
LT		 3161
3162 /* Bypass reserved domain fields. */
3163 if ((domain & 0xf0) == 0xf0)
3164 continue;
3165
3166 /* Bypass if not same domain and area of adapter. */
f7d289f6 3167 if (area && domain &&
e315cd28 3168 (area != vha->d_id.b.area || domain != vha->d_id.b.domain))
1da177e4
LT		 3169 continue;
3170
3171 /* Bypass invalid local loop ID. */
3172 if (loop_id > LAST_LOCAL_LOOP_ID)
3173 continue;
3174
370d550e
AE		 3175 memset(new_fcport, 0, sizeof(fc_port_t));
3176
1da177e4
LT		 3177 /* Fill in member data. */
3178 new_fcport->d_id.b.domain = domain;
3179 new_fcport->d_id.b.area = area;
3180 new_fcport->d_id.b.al_pa = al_pa;
3181 new_fcport->loop_id = loop_id;
e315cd28 3182 rval2 = qla2x00_get_port_database(vha, new_fcport, 0);
1da177e4 3183 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 3184 ql_dbg(ql_dbg_disc, vha, 0x201a,
3185 "Failed to retrieve fcport information "
3186 "-- get_port_database=%x, loop_id=0x%04x.\n",
3187 rval2, new_fcport->loop_id);
3188 ql_dbg(ql_dbg_disc, vha, 0x201b,
3189 "Scheduling resync.\n");
e315cd28 3190 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4
LT		 3191 continue;
3192 }
3193
3194 /* Check for matching device in port list. */
3195 found = 0;
3196 fcport = NULL;
e315cd28 3197 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 3198 if (memcmp(new_fcport->port_name, fcport->port_name,
3199 WWN_SIZE))
3200 continue;
3201
ddb9b126 3202 fcport->flags &= ~FCF_FABRIC_DEVICE;
1da177e4
LT		 3203 fcport->loop_id = new_fcport->loop_id;
3204 fcport->port_type = new_fcport->port_type;
3205 fcport->d_id.b24 = new_fcport->d_id.b24;
3206 memcpy(fcport->node_name, new_fcport->node_name,
3207 WWN_SIZE);
3208
3209 found++;
3210 break;
3211 }
3212
3213 if (!found) {
3214 /* New device, add to fcports list. */
e315cd28 3215 list_add_tail(&new_fcport->list, &vha->vp_fcports);
1da177e4
LT		 3216
3217 /* Allocate a new replacement fcport. */
3218 fcport = new_fcport;
e315cd28 3219 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3220 if (new_fcport == NULL) {
7c3df132
SK		 3221 ql_log(ql_log_warn, vha, 0x201c,
3222 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 3223 rval = QLA_MEMORY_ALLOC_FAILED;
3224 goto cleanup_allocation;
3225 }
3226 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
3227 }
3228
d8b45213 3229 /* Base iIDMA settings on HBA port speed. */
a3cbdfad 3230 fcport->fp_speed = ha->link_data_rate;
d8b45213 3231
e315cd28 3232 qla2x00_update_fcport(vha, fcport);
1da177e4
LT		 3233
3234 found_devs++;
3235 }
3236
3237cleanup_allocation:
c9475cb0 3238 kfree(new_fcport);
1da177e4
LT		 3239
3240 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3241 ql_dbg(ql_dbg_disc, vha, 0x201d,
3242 "Configure local loop error exit: rval=%x.\n", rval);
1da177e4
LT		 3243 }
3244
1da177e4
LT		 3245 return (rval);
3246}
3247
d8b45213 3248static void
e315cd28 3249qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
d8b45213 3250{
d8b45213 3251 int rval;
93f2bd67 3252 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 3253 struct qla_hw_data *ha = vha->hw;
d8b45213 3254
c76f2c01 3255 if (!IS_IIDMA_CAPABLE(ha))
d8b45213
AV		 3256 return;
3257
c9afb9a2
GM		 3258 if (atomic_read(&fcport->state) != FCS_ONLINE)
3259 return;
3260
39bd9622
AV		 3261 if (fcport->fp_speed == PORT_SPEED_UNKNOWN ||
3262 fcport->fp_speed > ha->link_data_rate)
d8b45213
AV		 3263 return;
3264
e315cd28 3265 rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed,
a3cbdfad 3266 mb);
d8b45213 3267 if (rval != QLA_SUCCESS) {
7c3df132 3268 ql_dbg(ql_dbg_disc, vha, 0x2004,
7b833558
OK		 3269 "Unable to adjust iIDMA %8phN -- %04x %x %04x %04x.\n",
3270 fcport->port_name, rval, fcport->fp_speed, mb[0], mb[1]);
d8b45213 3271 } else {
7c3df132 3272 ql_dbg(ql_dbg_disc, vha, 0x2005,
7b833558 3273 "iIDMA adjusted to %s GB/s on %8phN.\n",
d0297c9a 3274 qla2x00_get_link_speed_str(ha, fcport->fp_speed),
7b833558 3275 fcport->port_name);
d8b45213
AV		 3276 }
3277}
3278
23be331d 3279static void
e315cd28 3280qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport)
8482e118
AV		 3281{
3282 struct fc_rport_identifiers rport_ids;
bdf79621 3283 struct fc_rport *rport;
044d78e1 3284 unsigned long flags;
8482e118 3285
f8b02a85
AV		 3286 rport_ids.node_name = wwn_to_u64(fcport->node_name);
3287 rport_ids.port_name = wwn_to_u64(fcport->port_name);
8482e118
AV		 3288 rport_ids.port_id = fcport->d_id.b.domain << 16 |
3289 fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa;
77d74143 3290 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
e315cd28 3291 fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids);
77d74143 3292 if (!rport) {
7c3df132
SK		 3293 ql_log(ql_log_warn, vha, 0x2006,
3294 "Unable to allocate fc remote port.\n");
77d74143
AV		 3295 return;
3296 }
2d70c103
NB		 3297 /*
3298 * Create target mode FC NEXUS in qla_target.c if target mode is
3299 * enabled..
3300 */
3301 qlt_fc_port_added(vha, fcport);
3302
044d78e1 3303 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
19a7b4ae 3304 *((fc_port_t **)rport->dd_data) = fcport;
044d78e1 3305 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
d97994dc 3306
ad3e0eda 3307 rport->supported_classes = fcport->supported_classes;
77d74143 3308
8482e118
AV		 3309 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
3310 if (fcport->port_type == FCT_INITIATOR)
3311 rport_ids.roles |= FC_RPORT_ROLE_FCP_INITIATOR;
3312 if (fcport->port_type == FCT_TARGET)
3313 rport_ids.roles |= FC_RPORT_ROLE_FCP_TARGET;
77d74143 3314 fc_remote_port_rolechg(rport, rport_ids.roles);
1da177e4
LT		 3315}
3316
23be331d
AB		 3317/*
3318 * qla2x00_update_fcport
3319 * Updates device on list.
3320 *
3321 * Input:
3322 * ha = adapter block pointer.
3323 * fcport = port structure pointer.
3324 *
3325 * Return:
3326 * 0 - Success
3327 * BIT_0 - error
3328 *
3329 * Context:
3330 * Kernel context.
3331 */
3332void
e315cd28 3333qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
23be331d 3334{
e315cd28 3335 fcport->vha = vha;
8ae6d9c7
GM		 3336
3337 if (IS_QLAFX00(vha->hw)) {
3338 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
3339 qla2x00_reg_remote_port(vha, fcport);
3340 return;
3341 }
23be331d 3342 fcport->login_retry = 0;
5ff1d584 3343 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
23be331d 3344
1f93da52 3345 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
e315cd28 3346 qla2x00_iidma_fcport(vha, fcport);
21090cbe 3347 qla24xx_update_fcport_fcp_prio(vha, fcport);
e315cd28 3348 qla2x00_reg_remote_port(vha, fcport);
23be331d
AB		 3349}
3350
1da177e4
LT		 3351/*
3352 * qla2x00_configure_fabric
3353 * Setup SNS devices with loop ID's.
3354 *
3355 * Input:
3356 * ha = adapter block pointer.
3357 *
3358 * Returns:
3359 * 0 = success.
3360 * BIT_0 = error
3361 */
3362static int
e315cd28 3363qla2x00_configure_fabric(scsi_qla_host_t *vha)
1da177e4 3364{
b3b02e6e 3365 int rval;
e452ceb6 3366 fc_port_t *fcport, *fcptemp;
1da177e4
LT		 3367 uint16_t next_loopid;
3368 uint16_t mb[MAILBOX_REGISTER_COUNT];
0107109e 3369 uint16_t loop_id;
1da177e4 3370 LIST_HEAD(new_fcports);
e315cd28
AC		 3371 struct qla_hw_data *ha = vha->hw;
3372 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 3373
3374 /* If FL port exists, then SNS is present */
e428924c 3375 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 3376 loop_id = NPH_F_PORT;
3377 else
3378 loop_id = SNS_FL_PORT;
e315cd28 3379 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1);
1da177e4 3380 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3381 ql_dbg(ql_dbg_disc, vha, 0x201f,
3382 "MBX_GET_PORT_NAME failed, No FL Port.\n");
1da177e4 3383
e315cd28 3384 vha->device_flags &= ~SWITCH_FOUND;
1da177e4
LT		 3385 return (QLA_SUCCESS);
3386 }
e315cd28 3387 vha->device_flags |= SWITCH_FOUND;
1da177e4 3388
1da177e4 3389 do {
cca5335c
AV		 3390 /* FDMI support. */
3391 if (ql2xfdmienable &&
e315cd28
AC		 3392 test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags))
3393 qla2x00_fdmi_register(vha);
cca5335c 3394
1da177e4 3395 /* Ensure we are logged into the SNS. */
e428924c 3396 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 3397 loop_id = NPH_SNS;
3398 else
3399 loop_id = SIMPLE_NAME_SERVER;
0b91d116
CD		 3400 rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff,
3401 0xfc, mb, BIT_1|BIT_0);
3402 if (rval != QLA_SUCCESS) {
3403 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
e452ceb6 3404 return rval;
0b91d116 3405 }
1da177e4 3406 if (mb[0] != MBS_COMMAND_COMPLETE) {
7c3df132
SK		 3407 ql_dbg(ql_dbg_disc, vha, 0x2042,
3408 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x "
3409 "mb[6]=%x mb[7]=%x.\n", loop_id, mb[0], mb[1],
3410 mb[2], mb[6], mb[7]);
1da177e4
LT		 3411 return (QLA_SUCCESS);
3412 }
3413
e315cd28
AC		 3414 if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) {
3415 if (qla2x00_rft_id(vha)) {
1da177e4 3416 /* EMPTY */
7c3df132
SK		 3417 ql_dbg(ql_dbg_disc, vha, 0x2045,
3418 "Register FC-4 TYPE failed.\n");
1da177e4 3419 }
e315cd28 3420 if (qla2x00_rff_id(vha)) {
1da177e4 3421 /* EMPTY */
7c3df132
SK		 3422 ql_dbg(ql_dbg_disc, vha, 0x2049,
3423 "Register FC-4 Features failed.\n");
1da177e4 3424 }
e315cd28 3425 if (qla2x00_rnn_id(vha)) {
1da177e4 3426 /* EMPTY */
7c3df132
SK		 3427 ql_dbg(ql_dbg_disc, vha, 0x204f,
3428 "Register Node Name failed.\n");
e315cd28 3429 } else if (qla2x00_rsnn_nn(vha)) {
1da177e4 3430 /* EMPTY */
7c3df132
SK		 3431 ql_dbg(ql_dbg_disc, vha, 0x2053,
3432 "Register Symobilic Node Name failed.\n");
1da177e4
LT		 3433 }
3434 }
3435
827210ba
JC		 3436#define QLA_FCPORT_SCAN 1
3437#define QLA_FCPORT_FOUND 2
3438
3439 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3440 fcport->scan_state = QLA_FCPORT_SCAN;
3441 }
3442
e315cd28 3443 rval = qla2x00_find_all_fabric_devs(vha, &new_fcports);
1da177e4
LT		 3444 if (rval != QLA_SUCCESS)
3445 break;
3446
e452ceb6
JC		 3447 /*
3448 * Logout all previous fabric devices marked lost, except
3449 * FCP2 devices.
3450 */
e315cd28
AC		 3451 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3452 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
1da177e4
LT		 3453 break;
3454
3455 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0)
3456 continue;
3457
827210ba 3458 if (fcport->scan_state == QLA_FCPORT_SCAN &&
b3b02e6e 3459 atomic_read(&fcport->state) == FCS_ONLINE) {
e315cd28 3460 qla2x00_mark_device_lost(vha, fcport,
d97994dc 3461 ql2xplogiabsentdevice, 0);
1da177e4 3462 if (fcport->loop_id != FC_NO_LOOP_ID &&
f08b7251 3463 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
1da177e4
LT		 3464 fcport->port_type != FCT_INITIATOR &&
3465 fcport->port_type != FCT_BROADCAST) {
e315cd28 3466 ha->isp_ops->fabric_logout(vha,
1c7c6357
AV		 3467 fcport->loop_id,
3468 fcport->d_id.b.domain,
3469 fcport->d_id.b.area,
3470 fcport->d_id.b.al_pa);
1a5c69bf 3471 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 3472 }
3473 }
e452ceb6 3474 }
1da177e4 3475
e452ceb6
JC		 3476 /* Starting free loop ID. */
3477 next_loopid = ha->min_external_loopid;
3478
3479 /*
3480 * Scan through our port list and login entries that need to be
3481 * logged in.
3482 */
3483 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3484 if (atomic_read(&vha->loop_down_timer) ||
3485 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3486 break;
3487
3488 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0 ||
3489 (fcport->flags & FCF_LOGIN_NEEDED) == 0)
3490 continue;
3491
3492 if (fcport->loop_id == FC_NO_LOOP_ID) {
3493 fcport->loop_id = next_loopid;
3494 rval = qla2x00_find_new_loop_id(
3495 base_vha, fcport);
3496 if (rval != QLA_SUCCESS) {
3497 /* Ran out of IDs to use */
3498 break;
1da177e4
LT		 3499 }
3500 }
e452ceb6
JC		 3501 /* Login and update database */
3502 qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
3503 }
3504
3505 /* Exit if out of loop IDs. */
3506 if (rval != QLA_SUCCESS) {
3507 break;
3508 }
3509
3510 /*
3511 * Login and add the new devices to our port list.
3512 */
3513 list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) {
3514 if (atomic_read(&vha->loop_down_timer) ||
3515 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3516 break;
3517
3518 /* Find a new loop ID to use. */
3519 fcport->loop_id = next_loopid;
3520 rval = qla2x00_find_new_loop_id(base_vha, fcport);
3521 if (rval != QLA_SUCCESS) {
3522 /* Ran out of IDs to use */
3523 break;
3524 }
1da177e4 3525
bdf79621 3526 /* Login and update database */
e315cd28 3527 qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
e452ceb6
JC		 3528
3529 list_move_tail(&fcport->list, &vha->vp_fcports);
1da177e4
LT		 3530 }
3531 } while (0);
3532
e452ceb6
JC		 3533 /* Free all new device structures not processed. */
3534 list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) {
3535 list_del(&fcport->list);
3536 kfree(fcport);
3537 }
3538
1da177e4 3539 if (rval) {
7c3df132
SK		 3540 ql_dbg(ql_dbg_disc, vha, 0x2068,
3541 "Configure fabric error exit rval=%d.\n", rval);
1da177e4
LT		 3542 }
3543
3544 return (rval);
3545}
3546
1da177e4
LT		 3547/*
3548 * qla2x00_find_all_fabric_devs
3549 *
3550 * Input:
3551 * ha = adapter block pointer.
3552 * dev = database device entry pointer.
3553 *
3554 * Returns:
3555 * 0 = success.
3556 *
3557 * Context:
3558 * Kernel context.
3559 */
3560static int
e315cd28
AC		 3561qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha,
3562 struct list_head *new_fcports)
1da177e4
LT		 3563{
3564 int rval;
3565 uint16_t loop_id;
3566 fc_port_t *fcport, *new_fcport, *fcptemp;
3567 int found;
3568
3569 sw_info_t *swl;
3570 int swl_idx;
3571 int first_dev, last_dev;
1516ef44 3572 port_id_t wrap = {}, nxt_d_id;
e315cd28 3573 struct qla_hw_data *ha = vha->hw;
bb4cf5b7 3574 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 3575
3576 rval = QLA_SUCCESS;
3577
3578 /* Try GID_PT to get device list, else GAN. */
7a67735b 3579 if (!ha->swl)
642ef983 3580 ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t),
7a67735b
AV		 3581 GFP_KERNEL);
3582 swl = ha->swl;
bbfbbbc1 3583 if (!swl) {
1da177e4 3584 /*EMPTY*/
7c3df132
SK		 3585 ql_dbg(ql_dbg_disc, vha, 0x2054,
3586 "GID_PT allocations failed, fallback on GA_NXT.\n");
1da177e4 3587 } else {
642ef983 3588 memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t));
e315cd28 3589 if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) {
1da177e4 3590 swl = NULL;
e315cd28 3591 } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 3592 swl = NULL;
e315cd28 3593 } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 3594 swl = NULL;
e5896bd5 3595 } else if (ql2xiidmaenable &&
e315cd28
AC		 3596 qla2x00_gfpn_id(vha, swl) == QLA_SUCCESS) {
3597 qla2x00_gpsc(vha, swl);
1da177e4 3598 }
e8c72ba5
CD		 3599
3600 /* If other queries succeeded probe for FC-4 type */
3601 if (swl)
3602 qla2x00_gff_id(vha, swl);
1da177e4
LT		 3603 }
3604 swl_idx = 0;
3605
3606 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 3607 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3608 if (new_fcport == NULL) {
7c3df132
SK		 3609 ql_log(ql_log_warn, vha, 0x205e,
3610 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 3611 return (QLA_MEMORY_ALLOC_FAILED);
3612 }
3613 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
1da177e4
LT		 3614 /* Set start port ID scan at adapter ID. */
3615 first_dev = 1;
3616 last_dev = 0;
3617
3618 /* Starting free loop ID. */
e315cd28
AC		 3619 loop_id = ha->min_external_loopid;
3620 for (; loop_id <= ha->max_loop_id; loop_id++) {
3621 if (qla2x00_is_reserved_id(vha, loop_id))
1da177e4
LT		 3622 continue;
3623
3a6478df
GM		 3624 if (ha->current_topology == ISP_CFG_FL &&
3625 (atomic_read(&vha->loop_down_timer) ||
3626 LOOP_TRANSITION(vha))) {
bb2d52b2
AV		 3627 atomic_set(&vha->loop_down_timer, 0);
3628 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
3629 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
1da177e4 3630 break;
bb2d52b2 3631 }
1da177e4
LT		 3632
3633 if (swl != NULL) {
3634 if (last_dev) {
3635 wrap.b24 = new_fcport->d_id.b24;
3636 } else {
3637 new_fcport->d_id.b24 = swl[swl_idx].d_id.b24;
3638 memcpy(new_fcport->node_name,
3639 swl[swl_idx].node_name, WWN_SIZE);
3640 memcpy(new_fcport->port_name,
3641 swl[swl_idx].port_name, WWN_SIZE);
d8b45213
AV		 3642 memcpy(new_fcport->fabric_port_name,
3643 swl[swl_idx].fabric_port_name, WWN_SIZE);
3644 new_fcport->fp_speed = swl[swl_idx].fp_speed;
e8c72ba5 3645 new_fcport->fc4_type = swl[swl_idx].fc4_type;
1da177e4
LT		 3646
3647 if (swl[swl_idx].d_id.b.rsvd_1 != 0) {
3648 last_dev = 1;
3649 }
3650 swl_idx++;
3651 }
3652 } else {
3653 /* Send GA_NXT to the switch */
e315cd28 3654 rval = qla2x00_ga_nxt(vha, new_fcport);
1da177e4 3655 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3656 ql_log(ql_log_warn, vha, 0x2064,
3657 "SNS scan failed -- assuming "
3658 "zero-entry result.\n");
1da177e4
LT		 3659 list_for_each_entry_safe(fcport, fcptemp,
3660 new_fcports, list) {
3661 list_del(&fcport->list);
3662 kfree(fcport);
3663 }
3664 rval = QLA_SUCCESS;
3665 break;
3666 }
3667 }
3668
3669 /* If wrap on switch device list, exit. */
3670 if (first_dev) {
3671 wrap.b24 = new_fcport->d_id.b24;
3672 first_dev = 0;
3673 } else if (new_fcport->d_id.b24 == wrap.b24) {
7c3df132
SK		 3674 ql_dbg(ql_dbg_disc, vha, 0x2065,
3675 "Device wrap (%02x%02x%02x).\n",
3676 new_fcport->d_id.b.domain,
3677 new_fcport->d_id.b.area,
3678 new_fcport->d_id.b.al_pa);
1da177e4
LT		 3679 break;
3680 }
3681
2c3dfe3f 3682 /* Bypass if same physical adapter. */
e315cd28 3683 if (new_fcport->d_id.b24 == base_vha->d_id.b24)
1da177e4
LT		 3684 continue;
3685
2c3dfe3f 3686 /* Bypass virtual ports of the same host. */
bb4cf5b7
CD		 3687 if (qla2x00_is_a_vp_did(vha, new_fcport->d_id.b24))
3688 continue;
2c3dfe3f 3689
f7d289f6
AV		 3690 /* Bypass if same domain and area of adapter. */
3691 if (((new_fcport->d_id.b24 & 0xffff00) ==
e315cd28 3692 (vha->d_id.b24 & 0xffff00)) && ha->current_topology ==
f7d289f6
AV		 3693 ISP_CFG_FL)
3694 continue;
3695
1da177e4
LT		 3696 /* Bypass reserved domain fields. */
3697 if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0)
3698 continue;
3699
e8c72ba5 3700 /* Bypass ports whose FCP-4 type is not FCP_SCSI */
4da26e16
CD		 3701 if (ql2xgffidenable &&
3702 (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI &&
3703 new_fcport->fc4_type != FC4_TYPE_UNKNOWN))
e8c72ba5
CD		 3704 continue;
3705
1da177e4
LT		 3706 /* Locate matching device in database. */
3707 found = 0;
e315cd28 3708 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 3709 if (memcmp(new_fcport->port_name, fcport->port_name,
3710 WWN_SIZE))
3711 continue;
3712
827210ba 3713 fcport->scan_state = QLA_FCPORT_FOUND;
b3b02e6e 3714
1da177e4
LT		 3715 found++;
3716
d8b45213
AV		 3717 /* Update port state. */
3718 memcpy(fcport->fabric_port_name,
3719 new_fcport->fabric_port_name, WWN_SIZE);
3720 fcport->fp_speed = new_fcport->fp_speed;
3721
1da177e4
LT		 3722 /*
3723 * If address the same and state FCS_ONLINE, nothing
3724 * changed.
3725 */
3726 if (fcport->d_id.b24 == new_fcport->d_id.b24 &&
3727 atomic_read(&fcport->state) == FCS_ONLINE) {
3728 break;
3729 }
3730
3731 /*
3732 * If device was not a fabric device before.
3733 */
3734 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) {
3735 fcport->d_id.b24 = new_fcport->d_id.b24;
5f16b331 3736 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 3737 fcport->flags |= (FCF_FABRIC_DEVICE |
3738 FCF_LOGIN_NEEDED);
1da177e4
LT		 3739 break;
3740 }
3741
3742 /*
3743 * Port ID changed or device was marked to be updated;
3744 * Log it out if still logged in and mark it for
3745 * relogin later.
3746 */
3747 fcport->d_id.b24 = new_fcport->d_id.b24;
3748 fcport->flags |= FCF_LOGIN_NEEDED;
3749 if (fcport->loop_id != FC_NO_LOOP_ID &&
f08b7251 3750 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
0eba25df 3751 (fcport->flags & FCF_ASYNC_SENT) == 0 &&
1da177e4
LT		 3752 fcport->port_type != FCT_INITIATOR &&
3753 fcport->port_type != FCT_BROADCAST) {
e315cd28 3754 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3755 fcport->d_id.b.domain, fcport->d_id.b.area,
3756 fcport->d_id.b.al_pa);
5f16b331 3757 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 3758 }
3759
3760 break;
3761 }
3762
3763 if (found)
3764 continue;
1da177e4
LT		 3765 /* If device was not in our fcports list, then add it. */
3766 list_add_tail(&new_fcport->list, new_fcports);
3767
3768 /* Allocate a new replacement fcport. */
3769 nxt_d_id.b24 = new_fcport->d_id.b24;
e315cd28 3770 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3771 if (new_fcport == NULL) {
7c3df132
SK		 3772 ql_log(ql_log_warn, vha, 0x2066,
3773 "Memory allocation failed for fcport.\n");
1da177e4
LT		 3774 return (QLA_MEMORY_ALLOC_FAILED);
3775 }
3776 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
3777 new_fcport->d_id.b24 = nxt_d_id.b24;
3778 }
3779
c9475cb0 3780 kfree(new_fcport);
1da177e4 3781
1da177e4
LT		 3782 return (rval);
3783}
3784
3785/*
3786 * qla2x00_find_new_loop_id
3787 * Scan through our port list and find a new usable loop ID.
3788 *
3789 * Input:
3790 * ha: adapter state pointer.
3791 * dev: port structure pointer.
3792 *
3793 * Returns:
3794 * qla2x00 local function return status code.
3795 *
3796 * Context:
3797 * Kernel context.
3798 */
03bcfb57 3799int
e315cd28 3800qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
1da177e4
LT		 3801{
3802 int rval;
e315cd28 3803 struct qla_hw_data *ha = vha->hw;
feafb7b1 3804 unsigned long flags = 0;
1da177e4
LT		 3805
3806 rval = QLA_SUCCESS;
3807
5f16b331 3808 spin_lock_irqsave(&ha->vport_slock, flags);
1da177e4 3809
5f16b331
CD		 3810 dev->loop_id = find_first_zero_bit(ha->loop_id_map,
3811 LOOPID_MAP_SIZE);
3812 if (dev->loop_id >= LOOPID_MAP_SIZE ||
3813 qla2x00_is_reserved_id(vha, dev->loop_id)) {
3814 dev->loop_id = FC_NO_LOOP_ID;
3815 rval = QLA_FUNCTION_FAILED;
3816 } else
3817 set_bit(dev->loop_id, ha->loop_id_map);
1da177e4 3818
5f16b331 3819 spin_unlock_irqrestore(&ha->vport_slock, flags);
1da177e4 3820
5f16b331
CD		 3821 if (rval == QLA_SUCCESS)
3822 ql_dbg(ql_dbg_disc, dev->vha, 0x2086,
3823 "Assigning new loopid=%x, portid=%x.\n",
3824 dev->loop_id, dev->d_id.b24);
3825 else
3826 ql_log(ql_log_warn, dev->vha, 0x2087,
3827 "No loop_id's available, portid=%x.\n",
3828 dev->d_id.b24);
1da177e4
LT		 3829
3830 return (rval);
3831}
3832
1da177e4
LT		 3833/*
3834 * qla2x00_fabric_dev_login
3835 * Login fabric target device and update FC port database.
3836 *
3837 * Input:
3838 * ha: adapter state pointer.
3839 * fcport: port structure list pointer.
3840 * next_loopid: contains value of a new loop ID that can be used
3841 * by the next login attempt.
3842 *
3843 * Returns:
3844 * qla2x00 local function return status code.
3845 *
3846 * Context:
3847 * Kernel context.
3848 */
3849static int
e315cd28 3850qla2x00_fabric_dev_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 3851 uint16_t *next_loopid)
3852{
3853 int rval;
0107109e 3854 uint8_t opts;
e315cd28 3855 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3856
3857 rval = QLA_SUCCESS;
1da177e4 3858
ac280b67 3859 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584
AV		 3860 if (fcport->flags & FCF_ASYNC_SENT)
3861 return rval;
3862 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 3863 rval = qla2x00_post_async_login_work(vha, fcport, NULL);
3864 if (!rval)
3865 return rval;
3866 }
3867
5ff1d584 3868 fcport->flags &= ~FCF_ASYNC_SENT;
e315cd28 3869 rval = qla2x00_fabric_login(vha, fcport, next_loopid);
1da177e4 3870 if (rval == QLA_SUCCESS) {
f08b7251 3871 /* Send an ADISC to FCP2 devices.*/
0107109e 3872 opts = 0;
f08b7251 3873 if (fcport->flags & FCF_FCP2_DEVICE)
0107109e 3874 opts |= BIT_1;
e315cd28 3875 rval = qla2x00_get_port_database(vha, fcport, opts);
1da177e4 3876 if (rval != QLA_SUCCESS) {
e315cd28 3877 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3878 fcport->d_id.b.domain, fcport->d_id.b.area,
3879 fcport->d_id.b.al_pa);
e315cd28 3880 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4 3881 } else {
e315cd28 3882 qla2x00_update_fcport(vha, fcport);
1da177e4 3883 }
0b91d116
CD		 3884 } else {
3885 /* Retry Login. */
3886 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 3887 }
3888
3889 return (rval);
3890}
3891
3892/*
3893 * qla2x00_fabric_login
3894 * Issue fabric login command.
3895 *
3896 * Input:
3897 * ha = adapter block pointer.
3898 * device = pointer to FC device type structure.
3899 *
3900 * Returns:
3901 * 0 - Login successfully
3902 * 1 - Login failed
3903 * 2 - Initiator device
3904 * 3 - Fatal error
3905 */
3906int
e315cd28 3907qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 3908 uint16_t *next_loopid)
3909{
3910 int rval;
3911 int retry;
3912 uint16_t tmp_loopid;
3913 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 3914 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3915
3916 retry = 0;
3917 tmp_loopid = 0;
3918
3919 for (;;) {
7c3df132
SK		 3920 ql_dbg(ql_dbg_disc, vha, 0x2000,
3921 "Trying Fabric Login w/loop id 0x%04x for port "
3922 "%02x%02x%02x.\n",
3923 fcport->loop_id, fcport->d_id.b.domain,
3924 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 3925
3926 /* Login fcport on switch. */
0b91d116 3927 rval = ha->isp_ops->fabric_login(vha, fcport->loop_id,
1da177e4
LT		 3928 fcport->d_id.b.domain, fcport->d_id.b.area,
3929 fcport->d_id.b.al_pa, mb, BIT_0);
0b91d116
CD		 3930 if (rval != QLA_SUCCESS) {
3931 return rval;
3932 }
1da177e4
LT		 3933 if (mb[0] == MBS_PORT_ID_USED) {
3934 /*
3935 * Device has another loop ID. The firmware team
0107109e
AV		 3936 * recommends the driver perform an implicit login with
3937 * the specified ID again. The ID we just used is save
3938 * here so we return with an ID that can be tried by
3939 * the next login.
1da177e4
LT		 3940 */
3941 retry++;
3942 tmp_loopid = fcport->loop_id;
3943 fcport->loop_id = mb[1];
3944
7c3df132
SK		 3945 ql_dbg(ql_dbg_disc, vha, 0x2001,
3946 "Fabric Login: port in use - next loop "
3947 "id=0x%04x, port id= %02x%02x%02x.\n",
1da177e4 3948 fcport->loop_id, fcport->d_id.b.domain,
7c3df132 3949 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 3950
3951 } else if (mb[0] == MBS_COMMAND_COMPLETE) {
3952 /*
3953 * Login succeeded.
3954 */
3955 if (retry) {
3956 /* A retry occurred before. */
3957 *next_loopid = tmp_loopid;
3958 } else {
3959 /*
3960 * No retry occurred before. Just increment the
3961 * ID value for next login.
3962 */
3963 *next_loopid = (fcport->loop_id + 1);
3964 }
3965
3966 if (mb[1] & BIT_0) {
3967 fcport->port_type = FCT_INITIATOR;
3968 } else {
3969 fcport->port_type = FCT_TARGET;
3970 if (mb[1] & BIT_1) {
8474f3a0 3971 fcport->flags |= FCF_FCP2_DEVICE;
1da177e4
LT		 3972 }
3973 }
3974
ad3e0eda
AV		 3975 if (mb[10] & BIT_0)
3976 fcport->supported_classes |= FC_COS_CLASS2;
3977 if (mb[10] & BIT_1)
3978 fcport->supported_classes |= FC_COS_CLASS3;
3979
2d70c103
NB		 3980 if (IS_FWI2_CAPABLE(ha)) {
3981 if (mb[10] & BIT_7)
3982 fcport->flags |=
3983 FCF_CONF_COMP_SUPPORTED;
3984 }
3985
1da177e4
LT		 3986 rval = QLA_SUCCESS;
3987 break;
3988 } else if (mb[0] == MBS_LOOP_ID_USED) {
3989 /*
3990 * Loop ID already used, try next loop ID.
3991 */
3992 fcport->loop_id++;
e315cd28 3993 rval = qla2x00_find_new_loop_id(vha, fcport);
1da177e4
LT		 3994 if (rval != QLA_SUCCESS) {
3995 /* Ran out of loop IDs to use */
3996 break;
3997 }
3998 } else if (mb[0] == MBS_COMMAND_ERROR) {
3999 /*
4000 * Firmware possibly timed out during login. If NO
4001 * retries are left to do then the device is declared
4002 * dead.
4003 */
4004 *next_loopid = fcport->loop_id;
e315cd28 4005 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 4006 fcport->d_id.b.domain, fcport->d_id.b.area,
4007 fcport->d_id.b.al_pa);
e315cd28 4008 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 4009
4010 rval = 1;
4011 break;
4012 } else {
4013 /*
4014 * unrecoverable / not handled error
4015 */
7c3df132
SK		 4016 ql_dbg(ql_dbg_disc, vha, 0x2002,
4017 "Failed=%x port_id=%02x%02x%02x loop_id=%x "
4018 "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain,
4019 fcport->d_id.b.area, fcport->d_id.b.al_pa,
4020 fcport->loop_id, jiffies);
1da177e4
LT		 4021
4022 *next_loopid = fcport->loop_id;
e315cd28 4023 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 4024 fcport->d_id.b.domain, fcport->d_id.b.area,
4025 fcport->d_id.b.al_pa);
5f16b331 4026 qla2x00_clear_loop_id(fcport);
0eedfcf0 4027 fcport->login_retry = 0;
1da177e4
LT		 4028
4029 rval = 3;
4030 break;
4031 }
4032 }
4033
4034 return (rval);
4035}
4036
4037/*
4038 * qla2x00_local_device_login
4039 * Issue local device login command.
4040 *
4041 * Input:
4042 * ha = adapter block pointer.
4043 * loop_id = loop id of device to login to.
4044 *
4045 * Returns (Where's the #define!!!!):
4046 * 0 - Login successfully
4047 * 1 - Login failed
4048 * 3 - Fatal error
4049 */
4050int
e315cd28 4051qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport)
1da177e4
LT		 4052{
4053 int rval;
4054 uint16_t mb[MAILBOX_REGISTER_COUNT];
4055
4056 memset(mb, 0, sizeof(mb));
e315cd28 4057 rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0);
1da177e4
LT		 4058 if (rval == QLA_SUCCESS) {
4059 /* Interrogate mailbox registers for any errors */
4060 if (mb[0] == MBS_COMMAND_ERROR)
4061 rval = 1;
4062 else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR)
4063 /* device not in PCB table */
4064 rval = 3;
4065 }
4066
4067 return (rval);
4068}
4069
4070/*
4071 * qla2x00_loop_resync
4072 * Resync with fibre channel devices.
4073 *
4074 * Input:
4075 * ha = adapter block pointer.
4076 *
4077 * Returns:
4078 * 0 = success
4079 */
4080int
e315cd28 4081qla2x00_loop_resync(scsi_qla_host_t *vha)
1da177e4 4082{
73208dfd 4083 int rval = QLA_SUCCESS;
1da177e4 4084 uint32_t wait_time;
67c2e93a
AC		 4085 struct req_que *req;
4086 struct rsp_que *rsp;
4087
7163ea81 4088 if (vha->hw->flags.cpu_affinity_enabled)
67c2e93a
AC		 4089 req = vha->hw->req_q_map[0];
4090 else
4091 req = vha->req;
4092 rsp = req->rsp;
1da177e4 4093
e315cd28
AC		 4094 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
4095 if (vha->flags.online) {
4096 if (!(rval = qla2x00_fw_ready(vha))) {
1da177e4
LT		 4097 /* Wait at most MAX_TARGET RSCNs for a stable link. */
4098 wait_time = 256;
4099 do {
8ae6d9c7
GM		 4100 if (!IS_QLAFX00(vha->hw)) {
4101 /*
4102 * Issue a marker after FW becomes
4103 * ready.
4104 */
4105 qla2x00_marker(vha, req, rsp, 0, 0,
4106 MK_SYNC_ALL);
4107 vha->marker_needed = 0;
4108 }
1da177e4
LT		 4109
4110 /* Remap devices on Loop. */
e315cd28 4111 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4 4112
8ae6d9c7
GM		 4113 if (IS_QLAFX00(vha->hw))
4114 qlafx00_configure_devices(vha);
4115 else
4116 qla2x00_configure_loop(vha);
4117
1da177e4 4118 wait_time--;
e315cd28
AC		 4119 } while (!atomic_read(&vha->loop_down_timer) &&
4120 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
4121 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
4122 &vha->dpc_flags)));
1da177e4 4123 }
1da177e4
LT		 4124 }
4125
e315cd28 4126 if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
1da177e4 4127 return (QLA_FUNCTION_FAILED);
1da177e4 4128
e315cd28 4129 if (rval)
7c3df132
SK		 4130 ql_dbg(ql_dbg_disc, vha, 0x206c,
4131 "%s *** FAILED ***.\n", __func__);
1da177e4
LT		 4132
4133 return (rval);
4134}
4135
579d12b5
SK		 4136/*
4137* qla2x00_perform_loop_resync
4138* Description: This function will set the appropriate flags and call
4139* qla2x00_loop_resync. If successful loop will be resynced
4140* Arguments : scsi_qla_host_t pointer
4141* returm : Success or Failure
4142*/
4143
4144int qla2x00_perform_loop_resync(scsi_qla_host_t *ha)
4145{
4146 int32_t rval = 0;
4147
4148 if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) {
4149 /*Configure the flags so that resync happens properly*/
4150 atomic_set(&ha->loop_down_timer, 0);
4151 if (!(ha->device_flags & DFLG_NO_CABLE)) {
4152 atomic_set(&ha->loop_state, LOOP_UP);
4153 set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags);
4154 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
4155 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
4156
4157 rval = qla2x00_loop_resync(ha);
4158 } else
4159 atomic_set(&ha->loop_state, LOOP_DEAD);
4160
4161 clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags);
4162 }
4163
4164 return rval;
4165}
4166
d97994dc 4167void
67becc00 4168qla2x00_update_fcports(scsi_qla_host_t *base_vha)
d97994dc
AV		 4169{
4170 fc_port_t *fcport;
feafb7b1
AE		 4171 struct scsi_qla_host *vha;
4172 struct qla_hw_data *ha = base_vha->hw;
4173 unsigned long flags;
d97994dc 4174
feafb7b1 4175 spin_lock_irqsave(&ha->vport_slock, flags);
d97994dc 4176 /* Go with deferred removal of rport references. */
feafb7b1
AE		 4177 list_for_each_entry(vha, &base_vha->hw->vp_list, list) {
4178 atomic_inc(&vha->vref_count);
4179 list_for_each_entry(fcport, &vha->vp_fcports, list) {
8ae598d0 4180 if (fcport->drport &&
feafb7b1
AE		 4181 atomic_read(&fcport->state) != FCS_UNCONFIGURED) {
4182 spin_unlock_irqrestore(&ha->vport_slock, flags);
67becc00 4183 qla2x00_rport_del(fcport);
feafb7b1
AE		 4184 spin_lock_irqsave(&ha->vport_slock, flags);
4185 }
4186 }
4187 atomic_dec(&vha->vref_count);
4188 }
4189 spin_unlock_irqrestore(&ha->vport_slock, flags);
d97994dc
AV		 4190}
4191
7d613ac6
SV		 4192/* Assumes idc_lock always held on entry */
4193void
4194qla83xx_reset_ownership(scsi_qla_host_t *vha)
4195{
4196 struct qla_hw_data *ha = vha->hw;
4197 uint32_t drv_presence, drv_presence_mask;
4198 uint32_t dev_part_info1, dev_part_info2, class_type;
4199 uint32_t class_type_mask = 0x3;
4200 uint16_t fcoe_other_function = 0xffff, i;
4201
7ec0effd
AD		 4202 if (IS_QLA8044(ha)) {
4203 drv_presence = qla8044_rd_direct(vha,
4204 QLA8044_CRB_DRV_ACTIVE_INDEX);
4205 dev_part_info1 = qla8044_rd_direct(vha,
4206 QLA8044_CRB_DEV_PART_INFO_INDEX);
4207 dev_part_info2 = qla8044_rd_direct(vha,
4208 QLA8044_CRB_DEV_PART_INFO2);
4209 } else {
4210 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4211 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1);
4212 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2);
4213 }
7d613ac6
SV		 4214 for (i = 0; i < 8; i++) {
4215 class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask);
4216 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
4217 (i != ha->portnum)) {
4218 fcoe_other_function = i;
4219 break;
4220 }
4221 }
4222 if (fcoe_other_function == 0xffff) {
4223 for (i = 0; i < 8; i++) {
4224 class_type = ((dev_part_info2 >> (i * 4)) &
4225 class_type_mask);
4226 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
4227 ((i + 8) != ha->portnum)) {
4228 fcoe_other_function = i + 8;
4229 break;
4230 }
4231 }
4232 }
4233 /*
4234 * Prepare drv-presence mask based on fcoe functions present.
4235 * However consider only valid physical fcoe function numbers (0-15).
4236 */
4237 drv_presence_mask = ~((1 << (ha->portnum)) |
4238 ((fcoe_other_function == 0xffff) ?
4239 0 : (1 << (fcoe_other_function))));
4240
4241 /* We are the reset owner iff:
4242 * - No other protocol drivers present.
4243 * - This is the lowest among fcoe functions. */
4244 if (!(drv_presence & drv_presence_mask) &&
4245 (ha->portnum < fcoe_other_function)) {
4246 ql_dbg(ql_dbg_p3p, vha, 0xb07f,
4247 "This host is Reset owner.\n");
4248 ha->flags.nic_core_reset_owner = 1;
4249 }
4250}
4251
fa492630 4252static int
7d613ac6
SV		 4253__qla83xx_set_drv_ack(scsi_qla_host_t *vha)
4254{
4255 int rval = QLA_SUCCESS;
4256 struct qla_hw_data *ha = vha->hw;
4257 uint32_t drv_ack;
4258
4259 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4260 if (rval == QLA_SUCCESS) {
4261 drv_ack |= (1 << ha->portnum);
4262 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
4263 }
4264
4265 return rval;
4266}
4267
fa492630 4268static int
7d613ac6
SV		 4269__qla83xx_clear_drv_ack(scsi_qla_host_t *vha)
4270{
4271 int rval = QLA_SUCCESS;
4272 struct qla_hw_data *ha = vha->hw;
4273 uint32_t drv_ack;
4274
4275 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4276 if (rval == QLA_SUCCESS) {
4277 drv_ack &= ~(1 << ha->portnum);
4278 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
4279 }
4280
4281 return rval;
4282}
4283
fa492630 4284static const char *
7d613ac6
SV		 4285qla83xx_dev_state_to_string(uint32_t dev_state)
4286{
4287 switch (dev_state) {
4288 case QLA8XXX_DEV_COLD:
4289 return "COLD/RE-INIT";
4290 case QLA8XXX_DEV_INITIALIZING:
4291 return "INITIALIZING";
4292 case QLA8XXX_DEV_READY:
4293 return "READY";
4294 case QLA8XXX_DEV_NEED_RESET:
4295 return "NEED RESET";
4296 case QLA8XXX_DEV_NEED_QUIESCENT:
4297 return "NEED QUIESCENT";
4298 case QLA8XXX_DEV_FAILED:
4299 return "FAILED";
4300 case QLA8XXX_DEV_QUIESCENT:
4301 return "QUIESCENT";
4302 default:
4303 return "Unknown";
4304 }
4305}
4306
4307/* Assumes idc-lock always held on entry */
4308void
4309qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type)
4310{
4311 struct qla_hw_data *ha = vha->hw;
4312 uint32_t idc_audit_reg = 0, duration_secs = 0;
4313
4314 switch (audit_type) {
4315 case IDC_AUDIT_TIMESTAMP:
4316 ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000);
4317 idc_audit_reg = (ha->portnum) |
4318 (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8);
4319 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
4320 break;
4321
4322 case IDC_AUDIT_COMPLETION:
4323 duration_secs = ((jiffies_to_msecs(jiffies) -
4324 jiffies_to_msecs(ha->idc_audit_ts)) / 1000);
4325 idc_audit_reg = (ha->portnum) |
4326 (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8);
4327 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
4328 break;
4329
4330 default:
4331 ql_log(ql_log_warn, vha, 0xb078,
4332 "Invalid audit type specified.\n");
4333 break;
4334 }
4335}
4336
4337/* Assumes idc_lock always held on entry */
fa492630 4338static int
7d613ac6
SV		 4339qla83xx_initiating_reset(scsi_qla_host_t *vha)
4340{
4341 struct qla_hw_data *ha = vha->hw;
4342 uint32_t idc_control, dev_state;
4343
4344 __qla83xx_get_idc_control(vha, &idc_control);
4345 if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) {
4346 ql_log(ql_log_info, vha, 0xb080,
4347 "NIC Core reset has been disabled. idc-control=0x%x\n",
4348 idc_control);
4349 return QLA_FUNCTION_FAILED;
4350 }
4351
4352 /* Set NEED-RESET iff in READY state and we are the reset-owner */
4353 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4354 if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) {
4355 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
4356 QLA8XXX_DEV_NEED_RESET);
4357 ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n");
4358 qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP);
4359 } else {
4360 const char *state = qla83xx_dev_state_to_string(dev_state);
4361 ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n", state);
4362
4363 /* SV: XXX: Is timeout required here? */
4364 /* Wait for IDC state change READY -> NEED_RESET */
4365 while (dev_state == QLA8XXX_DEV_READY) {
4366 qla83xx_idc_unlock(vha, 0);
4367 msleep(200);
4368 qla83xx_idc_lock(vha, 0);
4369 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4370 }
4371 }
4372
4373 /* Send IDC ack by writing to drv-ack register */
4374 __qla83xx_set_drv_ack(vha);
4375
4376 return QLA_SUCCESS;
4377}
4378
4379int
4380__qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control)
4381{
4382 return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
4383}
4384
7d613ac6
SV		 4385int
4386__qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control)
4387{
4388 return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
4389}
4390
fa492630 4391static int
7d613ac6
SV		 4392qla83xx_check_driver_presence(scsi_qla_host_t *vha)
4393{
4394 uint32_t drv_presence = 0;
4395 struct qla_hw_data *ha = vha->hw;
4396
4397 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4398 if (drv_presence & (1 << ha->portnum))
4399 return QLA_SUCCESS;
4400 else
4401 return QLA_TEST_FAILED;
4402}
4403
4404int
4405qla83xx_nic_core_reset(scsi_qla_host_t *vha)
4406{
4407 int rval = QLA_SUCCESS;
4408 struct qla_hw_data *ha = vha->hw;
4409
4410 ql_dbg(ql_dbg_p3p, vha, 0xb058,
4411 "Entered %s().\n", __func__);
4412
4413 if (vha->device_flags & DFLG_DEV_FAILED) {
4414 ql_log(ql_log_warn, vha, 0xb059,
4415 "Device in unrecoverable FAILED state.\n");
4416 return QLA_FUNCTION_FAILED;
4417 }
4418
4419 qla83xx_idc_lock(vha, 0);
4420
4421 if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) {
4422 ql_log(ql_log_warn, vha, 0xb05a,
4423 "Function=0x%x has been removed from IDC participation.\n",
4424 ha->portnum);
4425 rval = QLA_FUNCTION_FAILED;
4426 goto exit;
4427 }
4428
4429 qla83xx_reset_ownership(vha);
4430
4431 rval = qla83xx_initiating_reset(vha);
4432
4433 /*
4434 * Perform reset if we are the reset-owner,
4435 * else wait till IDC state changes to READY/FAILED.
4436 */
4437 if (rval == QLA_SUCCESS) {
4438 rval = qla83xx_idc_state_handler(vha);
4439
4440 if (rval == QLA_SUCCESS)
4441 ha->flags.nic_core_hung = 0;
4442 __qla83xx_clear_drv_ack(vha);
4443 }
4444
4445exit:
4446 qla83xx_idc_unlock(vha, 0);
4447
4448 ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__);
4449
4450 return rval;
4451}
4452
81178772
SK		 4453int
4454qla2xxx_mctp_dump(scsi_qla_host_t *vha)
4455{
4456 struct qla_hw_data *ha = vha->hw;
4457 int rval = QLA_FUNCTION_FAILED;
4458
4459 if (!IS_MCTP_CAPABLE(ha)) {
4460 /* This message can be removed from the final version */
4461 ql_log(ql_log_info, vha, 0x506d,
4462 "This board is not MCTP capable\n");
4463 return rval;
4464 }
4465
4466 if (!ha->mctp_dump) {
4467 ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev,
4468 MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL);
4469
4470 if (!ha->mctp_dump) {
4471 ql_log(ql_log_warn, vha, 0x506e,
4472 "Failed to allocate memory for mctp dump\n");
4473 return rval;
4474 }
4475 }
4476
4477#define MCTP_DUMP_STR_ADDR 0x00000000
4478 rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma,
4479 MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4);
4480 if (rval != QLA_SUCCESS) {
4481 ql_log(ql_log_warn, vha, 0x506f,
4482 "Failed to capture mctp dump\n");
4483 } else {
4484 ql_log(ql_log_info, vha, 0x5070,
4485 "Mctp dump capture for host (%ld/%p).\n",
4486 vha->host_no, ha->mctp_dump);
4487 ha->mctp_dumped = 1;
4488 }
4489
409ee0fe 4490 if (!ha->flags.nic_core_reset_hdlr_active && !ha->portnum) {
81178772
SK		 4491 ha->flags.nic_core_reset_hdlr_active = 1;
4492 rval = qla83xx_restart_nic_firmware(vha);
4493 if (rval)
4494 /* NIC Core reset failed. */
4495 ql_log(ql_log_warn, vha, 0x5071,
4496 "Failed to restart nic firmware\n");
4497 else
4498 ql_dbg(ql_dbg_p3p, vha, 0xb084,
4499 "Restarted NIC firmware successfully.\n");
4500 ha->flags.nic_core_reset_hdlr_active = 0;
4501 }
4502
4503 return rval;
4504
4505}
4506
579d12b5 4507/*
8fcd6b8b 4508* qla2x00_quiesce_io
579d12b5
SK		 4509* Description: This function will block the new I/Os
4510* Its not aborting any I/Os as context
4511* is not destroyed during quiescence
4512* Arguments: scsi_qla_host_t
4513* return : void
4514*/
4515void
8fcd6b8b 4516qla2x00_quiesce_io(scsi_qla_host_t *vha)
579d12b5
SK		 4517{
4518 struct qla_hw_data *ha = vha->hw;
4519 struct scsi_qla_host *vp;
4520
8fcd6b8b
CD		 4521 ql_dbg(ql_dbg_dpc, vha, 0x401d,
4522 "Quiescing I/O - ha=%p.\n", ha);
579d12b5
SK		 4523
4524 atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME);
4525 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
4526 atomic_set(&vha->loop_state, LOOP_DOWN);
4527 qla2x00_mark_all_devices_lost(vha, 0);
4528 list_for_each_entry(vp, &ha->vp_list, list)
8fcd6b8b 4529 qla2x00_mark_all_devices_lost(vp, 0);
579d12b5
SK		 4530 } else {
4531 if (!atomic_read(&vha->loop_down_timer))
4532 atomic_set(&vha->loop_down_timer,
4533 LOOP_DOWN_TIME);
4534 }
4535 /* Wait for pending cmds to complete */
4536 qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST);
4537}
4538
a9083016
GM		 4539void
4540qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
4541{
4542 struct qla_hw_data *ha = vha->hw;
579d12b5 4543 struct scsi_qla_host *vp;
feafb7b1 4544 unsigned long flags;
6aef87be 4545 fc_port_t *fcport;
a9083016 4546
e46ef004
SK		 4547 /* For ISP82XX, driver waits for completion of the commands.
4548 * online flag should be set.
4549 */
7ec0effd 4550 if (!(IS_P3P_TYPE(ha)))
e46ef004 4551 vha->flags.online = 0;
a9083016
GM		 4552 ha->flags.chip_reset_done = 0;
4553 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2be21fa2 4554 vha->qla_stats.total_isp_aborts++;
a9083016 4555
7c3df132
SK		 4556 ql_log(ql_log_info, vha, 0x00af,
4557 "Performing ISP error recovery - ha=%p.\n", ha);
a9083016 4558
e46ef004
SK		 4559 /* For ISP82XX, reset_chip is just disabling interrupts.
4560 * Driver waits for the completion of the commands.
4561 * the interrupts need to be enabled.
4562 */
7ec0effd 4563 if (!(IS_P3P_TYPE(ha)))
a9083016
GM		 4564 ha->isp_ops->reset_chip(vha);
4565
4566 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
4567 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
4568 atomic_set(&vha->loop_state, LOOP_DOWN);
4569 qla2x00_mark_all_devices_lost(vha, 0);
feafb7b1
AE		 4570
4571 spin_lock_irqsave(&ha->vport_slock, flags);
579d12b5 4572 list_for_each_entry(vp, &ha->vp_list, list) {
feafb7b1
AE		 4573 atomic_inc(&vp->vref_count);
4574 spin_unlock_irqrestore(&ha->vport_slock, flags);
4575
a9083016 4576 qla2x00_mark_all_devices_lost(vp, 0);
feafb7b1
AE		 4577
4578 spin_lock_irqsave(&ha->vport_slock, flags);
4579 atomic_dec(&vp->vref_count);
4580 }
4581 spin_unlock_irqrestore(&ha->vport_slock, flags);
a9083016
GM		 4582 } else {
4583 if (!atomic_read(&vha->loop_down_timer))
4584 atomic_set(&vha->loop_down_timer,
4585 LOOP_DOWN_TIME);
4586 }
4587
6aef87be
AV		 4588 /* Clear all async request states across all VPs. */
4589 list_for_each_entry(fcport, &vha->vp_fcports, list)
4590 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
4591 spin_lock_irqsave(&ha->vport_slock, flags);
4592 list_for_each_entry(vp, &ha->vp_list, list) {
4593 atomic_inc(&vp->vref_count);
4594 spin_unlock_irqrestore(&ha->vport_slock, flags);
4595
4596 list_for_each_entry(fcport, &vp->vp_fcports, list)
4597 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
4598
4599 spin_lock_irqsave(&ha->vport_slock, flags);
4600 atomic_dec(&vp->vref_count);
4601 }
4602 spin_unlock_irqrestore(&ha->vport_slock, flags);
4603
bddd2d65
LC		 4604 if (!ha->flags.eeh_busy) {
4605 /* Make sure for ISP 82XX IO DMA is complete */
7ec0effd 4606 if (IS_P3P_TYPE(ha)) {
7190575f 4607 qla82xx_chip_reset_cleanup(vha);
7c3df132
SK		 4608 ql_log(ql_log_info, vha, 0x00b4,
4609 "Done chip reset cleanup.\n");
a9083016 4610
e46ef004
SK		 4611 /* Done waiting for pending commands.
4612 * Reset the online flag.
4613 */
4614 vha->flags.online = 0;
4d78c973 4615 }
a9083016 4616
bddd2d65
LC		 4617 /* Requeue all commands in outstanding command list. */
4618 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
4619 }
b6a029e1
AE		 4620
4621 ha->chip_reset++;
4622 /* memory barrier */
4623 wmb();
a9083016
GM		 4624}
4625
1da177e4
LT		 4626/*
4627* qla2x00_abort_isp
4628* Resets ISP and aborts all outstanding commands.
4629*
4630* Input:
4631* ha = adapter block pointer.
4632*
4633* Returns:
4634* 0 = success
4635*/
4636int
e315cd28 4637qla2x00_abort_isp(scsi_qla_host_t *vha)
1da177e4 4638{
476e8978 4639 int rval;
1da177e4 4640 uint8_t status = 0;
e315cd28
AC		 4641 struct qla_hw_data *ha = vha->hw;
4642 struct scsi_qla_host *vp;
73208dfd 4643 struct req_que *req = ha->req_q_map[0];
feafb7b1 4644 unsigned long flags;
1da177e4 4645
e315cd28 4646 if (vha->flags.online) {
a9083016 4647 qla2x00_abort_isp_cleanup(vha);
1da177e4 4648
a6171297
SV		 4649 if (IS_QLA8031(ha)) {
4650 ql_dbg(ql_dbg_p3p, vha, 0xb05c,
4651 "Clearing fcoe driver presence.\n");
4652 if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS)
4653 ql_dbg(ql_dbg_p3p, vha, 0xb073,
4654 "Error while clearing DRV-Presence.\n");
4655 }
4656
85880801
AV		 4657 if (unlikely(pci_channel_offline(ha->pdev) &&
4658 ha->flags.pci_channel_io_perm_failure)) {
4659 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
4660 status = 0;
4661 return status;
4662 }
4663
73208dfd 4664 ha->isp_ops->get_flash_version(vha, req->ring);
30c47662 4665
e315cd28 4666 ha->isp_ops->nvram_config(vha);
1da177e4 4667
e315cd28
AC		 4668 if (!qla2x00_restart_isp(vha)) {
4669 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4 4670
e315cd28 4671 if (!atomic_read(&vha->loop_down_timer)) {
1da177e4
LT		 4672 /*
4673 * Issue marker command only when we are going
4674 * to start the I/O .
4675 */
e315cd28 4676 vha->marker_needed = 1;
1da177e4
LT		 4677 }
4678
e315cd28 4679 vha->flags.online = 1;
1da177e4 4680
fd34f556 4681 ha->isp_ops->enable_intrs(ha);
1da177e4 4682
fa2a1ce5 4683 ha->isp_abort_cnt = 0;
e315cd28 4684 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
476e8978 4685
6246b8a1
GM		 4686 if (IS_QLA81XX(ha) || IS_QLA8031(ha))
4687 qla2x00_get_fw_version(vha);
df613b96
AV		 4688 if (ha->fce) {
4689 ha->flags.fce_enabled = 1;
4690 memset(ha->fce, 0,
4691 fce_calc_size(ha->fce_bufs));
e315cd28 4692 rval = qla2x00_enable_fce_trace(vha,
df613b96
AV		 4693 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
4694 &ha->fce_bufs);
4695 if (rval) {
7c3df132 4696 ql_log(ql_log_warn, vha, 0x8033,
df613b96
AV		 4697 "Unable to reinitialize FCE "
4698 "(%d).\n", rval);
4699 ha->flags.fce_enabled = 0;
4700 }
4701 }
436a7b11
AV		 4702
4703 if (ha->eft) {
4704 memset(ha->eft, 0, EFT_SIZE);
e315cd28 4705 rval = qla2x00_enable_eft_trace(vha,
436a7b11
AV		 4706 ha->eft_dma, EFT_NUM_BUFFERS);
4707 if (rval) {
7c3df132 4708 ql_log(ql_log_warn, vha, 0x8034,
436a7b11
AV		 4709 "Unable to reinitialize EFT "
4710 "(%d).\n", rval);
4711 }
4712 }
1da177e4 4713 } else { /* failed the ISP abort */
e315cd28
AC		 4714 vha->flags.online = 1;
4715 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
1da177e4 4716 if (ha->isp_abort_cnt == 0) {
7c3df132
SK		 4717 ql_log(ql_log_fatal, vha, 0x8035,
4718 "ISP error recover failed - "
4719 "board disabled.\n");
fa2a1ce5 4720 /*
1da177e4
LT		 4721 * The next call disables the board
4722 * completely.
4723 */
e315cd28
AC		 4724 ha->isp_ops->reset_adapter(vha);
4725 vha->flags.online = 0;
1da177e4 4726 clear_bit(ISP_ABORT_RETRY,
e315cd28 4727 &vha->dpc_flags);
1da177e4
LT		 4728 status = 0;
4729 } else { /* schedule another ISP abort */
4730 ha->isp_abort_cnt--;
7c3df132
SK		 4731 ql_dbg(ql_dbg_taskm, vha, 0x8020,
4732 "ISP abort - retry remaining %d.\n",
4733 ha->isp_abort_cnt);
1da177e4
LT		 4734 status = 1;
4735 }
4736 } else {
4737 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
7c3df132
SK		 4738 ql_dbg(ql_dbg_taskm, vha, 0x8021,
4739 "ISP error recovery - retrying (%d) "
4740 "more times.\n", ha->isp_abort_cnt);
e315cd28 4741 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
1da177e4
LT		 4742 status = 1;
4743 }
4744 }
fa2a1ce5 4745
1da177e4
LT		 4746 }
4747
e315cd28 4748 if (!status) {
7c3df132 4749 ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__);
feafb7b1
AE		 4750
4751 spin_lock_irqsave(&ha->vport_slock, flags);
4752 list_for_each_entry(vp, &ha->vp_list, list) {
4753 if (vp->vp_idx) {
4754 atomic_inc(&vp->vref_count);
4755 spin_unlock_irqrestore(&ha->vport_slock, flags);
4756
e315cd28 4757 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 4758
4759 spin_lock_irqsave(&ha->vport_slock, flags);
4760 atomic_dec(&vp->vref_count);
4761 }
e315cd28 4762 }
feafb7b1
AE		 4763 spin_unlock_irqrestore(&ha->vport_slock, flags);
4764
7d613ac6
SV		 4765 if (IS_QLA8031(ha)) {
4766 ql_dbg(ql_dbg_p3p, vha, 0xb05d,
4767 "Setting back fcoe driver presence.\n");
4768 if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS)
4769 ql_dbg(ql_dbg_p3p, vha, 0xb074,
4770 "Error while setting DRV-Presence.\n");
4771 }
e315cd28 4772 } else {
d8424f68
JP		 4773 ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n",
4774 __func__);
1da177e4
LT		 4775 }
4776
4777 return(status);
4778}
4779
4780/*
4781* qla2x00_restart_isp
4782* restarts the ISP after a reset
4783*
4784* Input:
4785* ha = adapter block pointer.
4786*
4787* Returns:
4788* 0 = success
4789*/
4790static int
e315cd28 4791qla2x00_restart_isp(scsi_qla_host_t *vha)
1da177e4 4792{
c6b2fca8 4793 int status = 0;
e315cd28 4794 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 4795 struct req_que *req = ha->req_q_map[0];
4796 struct rsp_que *rsp = ha->rsp_q_map[0];
2d70c103 4797 unsigned long flags;
1da177e4
LT		 4798
4799 /* If firmware needs to be loaded */
e315cd28
AC		 4800 if (qla2x00_isp_firmware(vha)) {
4801 vha->flags.online = 0;
4802 status = ha->isp_ops->chip_diag(vha);
4803 if (!status)
4804 status = qla2x00_setup_chip(vha);
1da177e4
LT		 4805 }
4806
e315cd28
AC		 4807 if (!status && !(status = qla2x00_init_rings(vha))) {
4808 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
2533cf67 4809 ha->flags.chip_reset_done = 1;
7108b76e 4810
73208dfd
AC		 4811 /* Initialize the queues in use */
4812 qla25xx_init_queues(ha);
4813
e315cd28
AC		 4814 status = qla2x00_fw_ready(vha);
4815 if (!status) {
0107109e 4816 /* Issue a marker after FW becomes ready. */
73208dfd 4817 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
0107109e 4818
e315cd28 4819 vha->flags.online = 1;
2d70c103
NB		 4820
4821 /*
4822 * Process any ATIO queue entries that came in
4823 * while we weren't online.
4824 */
4825 spin_lock_irqsave(&ha->hardware_lock, flags);
4826 if (qla_tgt_mode_enabled(vha))
4827 qlt_24xx_process_atio_queue(vha);
4828 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4829
7108b76e 4830 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4
LT		 4831 }
4832
4833 /* if no cable then assume it's good */
e315cd28 4834 if ((vha->device_flags & DFLG_NO_CABLE))
1da177e4 4835 status = 0;
1da177e4
LT		 4836 }
4837 return (status);
4838}
4839
73208dfd
AC		 4840static int
4841qla25xx_init_queues(struct qla_hw_data *ha)
4842{
4843 struct rsp_que *rsp = NULL;
4844 struct req_que *req = NULL;
4845 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
4846 int ret = -1;
4847 int i;
4848
2afa19a9 4849 for (i = 1; i < ha->max_rsp_queues; i++) {
73208dfd
AC		 4850 rsp = ha->rsp_q_map[i];
4851 if (rsp) {
4852 rsp->options &= ~BIT_0;
618a7523 4853 ret = qla25xx_init_rsp_que(base_vha, rsp);
73208dfd 4854 if (ret != QLA_SUCCESS)
7c3df132
SK		 4855 ql_dbg(ql_dbg_init, base_vha, 0x00ff,
4856 "%s Rsp que: %d init failed.\n",
4857 __func__, rsp->id);
73208dfd 4858 else
7c3df132
SK		 4859 ql_dbg(ql_dbg_init, base_vha, 0x0100,
4860 "%s Rsp que: %d inited.\n",
4861 __func__, rsp->id);
73208dfd 4862 }
2afa19a9
AC		 4863 }
4864 for (i = 1; i < ha->max_req_queues; i++) {
73208dfd
AC		 4865 req = ha->req_q_map[i];
4866 if (req) {
29bdccbe 4867 /* Clear outstanding commands array. */
73208dfd 4868 req->options &= ~BIT_0;
618a7523 4869 ret = qla25xx_init_req_que(base_vha, req);
73208dfd 4870 if (ret != QLA_SUCCESS)
7c3df132
SK		 4871 ql_dbg(ql_dbg_init, base_vha, 0x0101,
4872 "%s Req que: %d init failed.\n",
4873 __func__, req->id);
73208dfd 4874 else
7c3df132
SK		 4875 ql_dbg(ql_dbg_init, base_vha, 0x0102,
4876 "%s Req que: %d inited.\n",
4877 __func__, req->id);
73208dfd
AC		 4878 }
4879 }
4880 return ret;
4881}
4882
1da177e4
LT		 4883/*
4884* qla2x00_reset_adapter
4885* Reset adapter.
4886*
4887* Input:
4888* ha = adapter block pointer.
4889*/
abbd8870 4890void
e315cd28 4891qla2x00_reset_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 4892{
4893 unsigned long flags = 0;
e315cd28 4894 struct qla_hw_data *ha = vha->hw;
3d71644c 4895 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 4896
e315cd28 4897 vha->flags.online = 0;
fd34f556 4898 ha->isp_ops->disable_intrs(ha);
1da177e4 4899
1da177e4
LT		 4900 spin_lock_irqsave(&ha->hardware_lock, flags);
4901 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
4902 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
4903 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
4904 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
4905 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4906}
0107109e
AV		 4907
4908void
e315cd28 4909qla24xx_reset_adapter(scsi_qla_host_t *vha)
0107109e
AV		 4910{
4911 unsigned long flags = 0;
e315cd28 4912 struct qla_hw_data *ha = vha->hw;
0107109e
AV		 4913 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
4914
7ec0effd 4915 if (IS_P3P_TYPE(ha))
a9083016
GM		 4916 return;
4917
e315cd28 4918 vha->flags.online = 0;
fd34f556 4919 ha->isp_ops->disable_intrs(ha);
0107109e
AV		 4920
4921 spin_lock_irqsave(&ha->hardware_lock, flags);
4922 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
4923 RD_REG_DWORD(&reg->hccr);
4924 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
4925 RD_REG_DWORD(&reg->hccr);
4926 spin_unlock_irqrestore(&ha->hardware_lock, flags);
09ff36d3
AV		 4927
4928 if (IS_NOPOLLING_TYPE(ha))
4929 ha->isp_ops->enable_intrs(ha);
0107109e
AV		 4930}
4931
4e08df3f
DM		 4932/* On sparc systems, obtain port and node WWN from firmware
4933 * properties.
4934 */
e315cd28
AC		 4935static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha,
4936 struct nvram_24xx *nv)
4e08df3f
DM		 4937{
4938#ifdef CONFIG_SPARC
e315cd28 4939 struct qla_hw_data *ha = vha->hw;
4e08df3f 4940 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 4941 struct device_node *dp = pci_device_to_OF_node(pdev);
4942 const u8 *val;
4e08df3f
DM		 4943 int len;
4944
4945 val = of_get_property(dp, "port-wwn", &len);
4946 if (val && len >= WWN_SIZE)
4947 memcpy(nv->port_name, val, WWN_SIZE);
4948
4949 val = of_get_property(dp, "node-wwn", &len);
4950 if (val && len >= WWN_SIZE)
4951 memcpy(nv->node_name, val, WWN_SIZE);
4952#endif
4953}
4954
0107109e 4955int
e315cd28 4956qla24xx_nvram_config(scsi_qla_host_t *vha)
0107109e 4957{
4e08df3f 4958 int rval;
0107109e
AV		 4959 struct init_cb_24xx *icb;
4960 struct nvram_24xx *nv;
4961 uint32_t *dptr;
4962 uint8_t *dptr1, *dptr2;
4963 uint32_t chksum;
4964 uint16_t cnt;
e315cd28 4965 struct qla_hw_data *ha = vha->hw;
0107109e 4966
4e08df3f 4967 rval = QLA_SUCCESS;
0107109e 4968 icb = (struct init_cb_24xx *)ha->init_cb;
281afe19 4969 nv = ha->nvram;
0107109e
AV		 4970
4971 /* Determine NVRAM starting address. */
f73cb695 4972 if (ha->port_no == 0) {
e5b68a61
AC		 4973 ha->nvram_base = FA_NVRAM_FUNC0_ADDR;
4974 ha->vpd_base = FA_NVRAM_VPD0_ADDR;
4975 } else {
0107109e 4976 ha->nvram_base = FA_NVRAM_FUNC1_ADDR;
6f641790
AV		 4977 ha->vpd_base = FA_NVRAM_VPD1_ADDR;
4978 }
f73cb695 4979
e5b68a61
AC		 4980 ha->nvram_size = sizeof(struct nvram_24xx);
4981 ha->vpd_size = FA_NVRAM_VPD_SIZE;
0107109e 4982
281afe19
SJ		 4983 /* Get VPD data into cache */
4984 ha->vpd = ha->nvram + VPD_OFFSET;
e315cd28 4985 ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd,
281afe19
SJ		 4986 ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
4987
4988 /* Get NVRAM data into cache and calculate checksum. */
0107109e 4989 dptr = (uint32_t *)nv;
e315cd28 4990 ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base,
0107109e
AV		 4991 ha->nvram_size);
4992 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
4993 chksum += le32_to_cpu(*dptr++);
4994
7c3df132
SK		 4995 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
4996 "Contents of NVRAM\n");
4997 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
4998 (uint8_t *)nv, ha->nvram_size);
0107109e
AV		 4999
5000 /* Bad NVRAM data, set defaults parameters. */
5001 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
5002 || nv->id[3] != ' ' ||
ad950360 5003 nv->nvram_version < cpu_to_le16(ICB_VERSION)) {
0107109e 5004 /* Reset NVRAM data. */
7c3df132 5005 ql_log(ql_log_warn, vha, 0x006b,
9e336520 5006 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132
SK		 5007 "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version);
5008 ql_log(ql_log_warn, vha, 0x006c,
5009 "Falling back to functioning (yet invalid -- WWPN) "
5010 "defaults.\n");
4e08df3f
DM		 5011
5012 /*
5013 * Set default initialization control block.
5014 */
5015 memset(nv, 0, ha->nvram_size);
ad950360
BVA		 5016 nv->nvram_version = cpu_to_le16(ICB_VERSION);
5017 nv->version = cpu_to_le16(ICB_VERSION);
98aee70d 5018 nv->frame_payload_size = 2048;
ad950360
BVA		 5019 nv->execution_throttle = cpu_to_le16(0xFFFF);
5020 nv->exchange_count = cpu_to_le16(0);
5021 nv->hard_address = cpu_to_le16(124);
4e08df3f 5022 nv->port_name[0] = 0x21;
f73cb695 5023 nv->port_name[1] = 0x00 + ha->port_no + 1;
4e08df3f
DM		 5024 nv->port_name[2] = 0x00;
5025 nv->port_name[3] = 0xe0;
5026 nv->port_name[4] = 0x8b;
5027 nv->port_name[5] = 0x1c;
5028 nv->port_name[6] = 0x55;
5029 nv->port_name[7] = 0x86;
5030 nv->node_name[0] = 0x20;
5031 nv->node_name[1] = 0x00;
5032 nv->node_name[2] = 0x00;
5033 nv->node_name[3] = 0xe0;
5034 nv->node_name[4] = 0x8b;
5035 nv->node_name[5] = 0x1c;
5036 nv->node_name[6] = 0x55;
5037 nv->node_name[7] = 0x86;
e315cd28 5038 qla24xx_nvram_wwn_from_ofw(vha, nv);
ad950360
BVA		 5039 nv->login_retry_count = cpu_to_le16(8);
5040 nv->interrupt_delay_timer = cpu_to_le16(0);
5041 nv->login_timeout = cpu_to_le16(0);
4e08df3f 5042 nv->firmware_options_1 =
ad950360
BVA		 5043 cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
5044 nv->firmware_options_2 = cpu_to_le32(2 << 4);
5045 nv->firmware_options_2 |= cpu_to_le32(BIT_12);
5046 nv->firmware_options_3 = cpu_to_le32(2 << 13);
5047 nv->host_p = cpu_to_le32(BIT_11|BIT_10);
5048 nv->efi_parameters = cpu_to_le32(0);
4e08df3f 5049 nv->reset_delay = 5;
ad950360
BVA		 5050 nv->max_luns_per_target = cpu_to_le16(128);
5051 nv->port_down_retry_count = cpu_to_le16(30);
5052 nv->link_down_timeout = cpu_to_le16(30);
4e08df3f
DM		 5053
5054 rval = 1;
0107109e
AV		 5055 }
5056
2d70c103
NB		 5057 if (!qla_ini_mode_enabled(vha)) {
5058 /* Don't enable full login after initial LIP */
ad950360 5059 nv->firmware_options_1 &= cpu_to_le32(~BIT_13);
2d70c103 5060 /* Don't enable LIP full login for initiator */
ad950360 5061 nv->host_p &= cpu_to_le32(~BIT_10);
2d70c103
NB		 5062 }
5063
5064 qlt_24xx_config_nvram_stage1(vha, nv);
5065
0107109e 5066 /* Reset Initialization control block */
e315cd28 5067 memset(icb, 0, ha->init_cb_size);
0107109e
AV		 5068
5069 /* Copy 1st segment. */
5070 dptr1 = (uint8_t *)icb;
5071 dptr2 = (uint8_t *)&nv->version;
5072 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
5073 while (cnt--)
5074 *dptr1++ = *dptr2++;
5075
5076 icb->login_retry_count = nv->login_retry_count;
3ea66e28 5077 icb->link_down_on_nos = nv->link_down_on_nos;
0107109e
AV		 5078
5079 /* Copy 2nd segment. */
5080 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
5081 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
5082 cnt = (uint8_t *)&icb->reserved_3 -
5083 (uint8_t *)&icb->interrupt_delay_timer;
5084 while (cnt--)
5085 *dptr1++ = *dptr2++;
5086
5087 /*
5088 * Setup driver NVRAM options.
5089 */
e315cd28 5090 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
9bb9fcf2 5091 "QLA2462");
0107109e 5092
2d70c103
NB		 5093 qlt_24xx_config_nvram_stage2(vha, icb);
5094
ad950360 5095 if (nv->host_p & cpu_to_le32(BIT_15)) {
2d70c103 5096 /* Use alternate WWN? */
5341e868
AV		 5097 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
5098 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
5099 }
5100
0107109e 5101 /* Prepare nodename */
ad950360 5102 if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) {
0107109e
AV		 5103 /*
5104 * Firmware will apply the following mask if the nodename was
5105 * not provided.
5106 */
5107 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
5108 icb->node_name[0] &= 0xF0;
5109 }
5110
5111 /* Set host adapter parameters. */
5112 ha->flags.disable_risc_code_load = 0;
0c8c39af
AV		 5113 ha->flags.enable_lip_reset = 0;
5114 ha->flags.enable_lip_full_login =
5115 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
5116 ha->flags.enable_target_reset =
5117 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
0107109e 5118 ha->flags.enable_led_scheme = 0;
d4c760c2 5119 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
0107109e 5120
fd0e7e4d
AV		 5121 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
5122 (BIT_6 | BIT_5 | BIT_4)) >> 4;
0107109e
AV		 5123
5124 memcpy(ha->fw_seriallink_options24, nv->seriallink_options,
5125 sizeof(ha->fw_seriallink_options24));
5126
5127 /* save HBA serial number */
5128 ha->serial0 = icb->port_name[5];
5129 ha->serial1 = icb->port_name[6];
5130 ha->serial2 = icb->port_name[7];
e315cd28
AC		 5131 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
5132 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
0107109e 5133
ad950360 5134 icb->execution_throttle = cpu_to_le16(0xFFFF);
bc8fb3cb 5135
0107109e
AV		 5136 ha->retry_count = le16_to_cpu(nv->login_retry_count);
5137
5138 /* Set minimum login_timeout to 4 seconds. */
5139 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
5140 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
5141 if (le16_to_cpu(nv->login_timeout) < 4)
ad950360 5142 nv->login_timeout = cpu_to_le16(4);
0107109e 5143 ha->login_timeout = le16_to_cpu(nv->login_timeout);
c6852c4c 5144 icb->login_timeout = nv->login_timeout;
0107109e 5145
00a537b8
AV		 5146 /* Set minimum RATOV to 100 tenths of a second. */
5147 ha->r_a_tov = 100;
0107109e
AV		 5148
5149 ha->loop_reset_delay = nv->reset_delay;
5150
5151 /* Link Down Timeout = 0:
5152 *
5153 * When Port Down timer expires we will start returning
5154 * I/O's to OS with "DID_NO_CONNECT".
5155 *
5156 * Link Down Timeout != 0:
5157 *
5158 * The driver waits for the link to come up after link down
5159 * before returning I/Os to OS with "DID_NO_CONNECT".
5160 */
5161 if (le16_to_cpu(nv->link_down_timeout) == 0) {
5162 ha->loop_down_abort_time =
5163 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
5164 } else {
5165 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
5166 ha->loop_down_abort_time =
5167 (LOOP_DOWN_TIME - ha->link_down_timeout);
5168 }
5169
5170 /* Need enough time to try and get the port back. */
5171 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
5172 if (qlport_down_retry)
5173 ha->port_down_retry_count = qlport_down_retry;
5174
5175 /* Set login_retry_count */
5176 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
5177 if (ha->port_down_retry_count ==
5178 le16_to_cpu(nv->port_down_retry_count) &&
5179 ha->port_down_retry_count > 3)
5180 ha->login_retry_count = ha->port_down_retry_count;
5181 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
5182 ha->login_retry_count = ha->port_down_retry_count;
5183 if (ql2xloginretrycount)
5184 ha->login_retry_count = ql2xloginretrycount;
5185
4fdfefe5 5186 /* Enable ZIO. */
e315cd28 5187 if (!vha->flags.init_done) {
4fdfefe5
AV		 5188 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
5189 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
5190 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
5191 le16_to_cpu(icb->interrupt_delay_timer): 2;
5192 }
ad950360 5193 icb->firmware_options_2 &= cpu_to_le32(
4fdfefe5 5194 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
e315cd28 5195 vha->flags.process_response_queue = 0;
4fdfefe5 5196 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d
AV		 5197 ha->zio_mode = QLA_ZIO_MODE_6;
5198
7c3df132 5199 ql_log(ql_log_info, vha, 0x006f,
4fdfefe5
AV		 5200 "ZIO mode %d enabled; timer delay (%d us).\n",
5201 ha->zio_mode, ha->zio_timer * 100);
5202
5203 icb->firmware_options_2 |= cpu_to_le32(
5204 (uint32_t)ha->zio_mode);
5205 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
e315cd28 5206 vha->flags.process_response_queue = 1;
4fdfefe5
AV		 5207 }
5208
4e08df3f 5209 if (rval) {
7c3df132
SK		 5210 ql_log(ql_log_warn, vha, 0x0070,
5211 "NVRAM configuration failed.\n");
4e08df3f
DM		 5212 }
5213 return (rval);
0107109e
AV		 5214}
5215
413975a0 5216static int
cbc8eb67
AV		 5217qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
5218 uint32_t faddr)
d1c61909 5219{
73208dfd 5220 int rval = QLA_SUCCESS;
d1c61909 5221 int segments, fragment;
d1c61909
AV		 5222 uint32_t *dcode, dlen;
5223 uint32_t risc_addr;
5224 uint32_t risc_size;
5225 uint32_t i;
e315cd28 5226 struct qla_hw_data *ha = vha->hw;
73208dfd 5227 struct req_que *req = ha->req_q_map[0];
eaac30be 5228
7c3df132 5229 ql_dbg(ql_dbg_init, vha, 0x008b,
cfb0919c 5230 "FW: Loading firmware from flash (%x).\n", faddr);
eaac30be 5231
d1c61909
AV		 5232 rval = QLA_SUCCESS;
5233
5234 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 5235 dcode = (uint32_t *)req->ring;
d1c61909
AV		 5236 *srisc_addr = 0;
5237
5238 /* Validate firmware image by checking version. */
e315cd28 5239 qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
d1c61909
AV		 5240 for (i = 0; i < 4; i++)
5241 dcode[i] = be32_to_cpu(dcode[i]);
5242 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
5243 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
5244 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
5245 dcode[3] == 0)) {
7c3df132
SK		 5246 ql_log(ql_log_fatal, vha, 0x008c,
5247 "Unable to verify the integrity of flash firmware "
5248 "image.\n");
5249 ql_log(ql_log_fatal, vha, 0x008d,
5250 "Firmware data: %08x %08x %08x %08x.\n",
5251 dcode[0], dcode[1], dcode[2], dcode[3]);
d1c61909
AV		 5252
5253 return QLA_FUNCTION_FAILED;
5254 }
5255
5256 while (segments && rval == QLA_SUCCESS) {
5257 /* Read segment's load information. */
e315cd28 5258 qla24xx_read_flash_data(vha, dcode, faddr, 4);
d1c61909
AV		 5259
5260 risc_addr = be32_to_cpu(dcode[2]);
5261 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
5262 risc_size = be32_to_cpu(dcode[3]);
5263
5264 fragment = 0;
5265 while (risc_size > 0 && rval == QLA_SUCCESS) {
5266 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
5267 if (dlen > risc_size)
5268 dlen = risc_size;
5269
7c3df132
SK		 5270 ql_dbg(ql_dbg_init, vha, 0x008e,
5271 "Loading risc segment@ risc addr %x "
5272 "number of dwords 0x%x offset 0x%x.\n",
5273 risc_addr, dlen, faddr);
d1c61909 5274
e315cd28 5275 qla24xx_read_flash_data(vha, dcode, faddr, dlen);
d1c61909
AV		 5276 for (i = 0; i < dlen; i++)
5277 dcode[i] = swab32(dcode[i]);
5278
73208dfd 5279 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
d1c61909
AV		 5280 dlen);
5281 if (rval) {
7c3df132
SK		 5282 ql_log(ql_log_fatal, vha, 0x008f,
5283 "Failed to load segment %d of firmware.\n",
5284 fragment);
f261f7af 5285 return QLA_FUNCTION_FAILED;
d1c61909
AV		 5286 }
5287
5288 faddr += dlen;
5289 risc_addr += dlen;
5290 risc_size -= dlen;
5291 fragment++;
5292 }
5293
5294 /* Next segment. */
5295 segments--;
5296 }
5297
f73cb695
CD		 5298 if (!IS_QLA27XX(ha))
5299 return rval;
5300
5301 if (ha->fw_dump_template)
5302 vfree(ha->fw_dump_template);
5303 ha->fw_dump_template = NULL;
5304 ha->fw_dump_template_len = 0;
5305
5306 ql_dbg(ql_dbg_init, vha, 0x0161,
5307 "Loading fwdump template from %x\n", faddr);
5308 qla24xx_read_flash_data(vha, dcode, faddr, 7);
5309 risc_size = be32_to_cpu(dcode[2]);
5310 ql_dbg(ql_dbg_init, vha, 0x0162,
5311 "-> array size %x dwords\n", risc_size);
5312 if (risc_size == 0 || risc_size == ~0)
5313 goto default_template;
5314
5315 dlen = (risc_size - 8) * sizeof(*dcode);
5316 ql_dbg(ql_dbg_init, vha, 0x0163,
5317 "-> template allocating %x bytes...\n", dlen);
5318 ha->fw_dump_template = vmalloc(dlen);
5319 if (!ha->fw_dump_template) {
5320 ql_log(ql_log_warn, vha, 0x0164,
5321 "Failed fwdump template allocate %x bytes.\n", risc_size);
5322 goto default_template;
5323 }
5324
5325 faddr += 7;
5326 risc_size -= 8;
5327 dcode = ha->fw_dump_template;
5328 qla24xx_read_flash_data(vha, dcode, faddr, risc_size);
5329 for (i = 0; i < risc_size; i++)
5330 dcode[i] = le32_to_cpu(dcode[i]);
5331
5332 if (!qla27xx_fwdt_template_valid(dcode)) {
5333 ql_log(ql_log_warn, vha, 0x0165,
5334 "Failed fwdump template validate\n");
5335 goto default_template;
5336 }
5337
5338 dlen = qla27xx_fwdt_template_size(dcode);
5339 ql_dbg(ql_dbg_init, vha, 0x0166,
5340 "-> template size %x bytes\n", dlen);
5341 if (dlen > risc_size * sizeof(*dcode)) {
5342 ql_log(ql_log_warn, vha, 0x0167,
97ea702b
CD		 5343 "Failed fwdump template exceeds array by %x bytes\n",
5344 (uint32_t)(dlen - risc_size * sizeof(*dcode)));
f73cb695
CD		 5345 goto default_template;
5346 }
5347 ha->fw_dump_template_len = dlen;
5348 return rval;
5349
5350default_template:
5351 ql_log(ql_log_warn, vha, 0x0168, "Using default fwdump template\n");
5352 if (ha->fw_dump_template)
5353 vfree(ha->fw_dump_template);
5354 ha->fw_dump_template = NULL;
5355 ha->fw_dump_template_len = 0;
5356
5357 dlen = qla27xx_fwdt_template_default_size();
5358 ql_dbg(ql_dbg_init, vha, 0x0169,
5359 "-> template allocating %x bytes...\n", dlen);
5360 ha->fw_dump_template = vmalloc(dlen);
5361 if (!ha->fw_dump_template) {
5362 ql_log(ql_log_warn, vha, 0x016a,
5363 "Failed fwdump template allocate %x bytes.\n", risc_size);
5364 goto failed_template;
5365 }
5366
5367 dcode = ha->fw_dump_template;
5368 risc_size = dlen / sizeof(*dcode);
5369 memcpy(dcode, qla27xx_fwdt_template_default(), dlen);
5370 for (i = 0; i < risc_size; i++)
5371 dcode[i] = be32_to_cpu(dcode[i]);
5372
5373 if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) {
5374 ql_log(ql_log_warn, vha, 0x016b,
5375 "Failed fwdump template validate\n");
5376 goto failed_template;
5377 }
5378
5379 dlen = qla27xx_fwdt_template_size(ha->fw_dump_template);
5380 ql_dbg(ql_dbg_init, vha, 0x016c,
5381 "-> template size %x bytes\n", dlen);
5382 ha->fw_dump_template_len = dlen;
5383 return rval;
5384
5385failed_template:
5386 ql_log(ql_log_warn, vha, 0x016d, "Failed default fwdump template\n");
5387 if (ha->fw_dump_template)
5388 vfree(ha->fw_dump_template);
5389 ha->fw_dump_template = NULL;
5390 ha->fw_dump_template_len = 0;
d1c61909
AV		 5391 return rval;
5392}
5393
e9454a88 5394#define QLA_FW_URL "http://ldriver.qlogic.com/firmware/"
d1c61909 5395
0107109e 5396int
e315cd28 5397qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5433383e
AV		 5398{
5399 int rval;
5400 int i, fragment;
5401 uint16_t *wcode, *fwcode;
5402 uint32_t risc_addr, risc_size, fwclen, wlen, *seg;
5403 struct fw_blob *blob;
e315cd28 5404 struct qla_hw_data *ha = vha->hw;
73208dfd 5405 struct req_que *req = ha->req_q_map[0];
5433383e
AV		 5406
5407 /* Load firmware blob. */
e315cd28 5408 blob = qla2x00_request_firmware(vha);
5433383e 5409 if (!blob) {
7c3df132 5410 ql_log(ql_log_info, vha, 0x0083,
94bcf830 5411 "Firmware image unavailable.\n");
7c3df132
SK		 5412 ql_log(ql_log_info, vha, 0x0084,
5413 "Firmware images can be retrieved from: "QLA_FW_URL ".\n");
5433383e
AV		 5414 return QLA_FUNCTION_FAILED;
5415 }
5416
5417 rval = QLA_SUCCESS;
5418
73208dfd 5419 wcode = (uint16_t *)req->ring;
5433383e
AV		 5420 *srisc_addr = 0;
5421 fwcode = (uint16_t *)blob->fw->data;
5422 fwclen = 0;
5423
5424 /* Validate firmware image by checking version. */
5425 if (blob->fw->size < 8 * sizeof(uint16_t)) {
7c3df132
SK		 5426 ql_log(ql_log_fatal, vha, 0x0085,
5427 "Unable to verify integrity of firmware image (%Zd).\n",
5433383e
AV		 5428 blob->fw->size);
5429 goto fail_fw_integrity;
5430 }
5431 for (i = 0; i < 4; i++)
5432 wcode[i] = be16_to_cpu(fwcode[i + 4]);
5433 if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff &&
5434 wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 &&
5435 wcode[2] == 0 && wcode[3] == 0)) {
7c3df132
SK		 5436 ql_log(ql_log_fatal, vha, 0x0086,
5437 "Unable to verify integrity of firmware image.\n");
5438 ql_log(ql_log_fatal, vha, 0x0087,
5439 "Firmware data: %04x %04x %04x %04x.\n",
5440 wcode[0], wcode[1], wcode[2], wcode[3]);
5433383e
AV		 5441 goto fail_fw_integrity;
5442 }
5443
5444 seg = blob->segs;
5445 while (*seg && rval == QLA_SUCCESS) {
5446 risc_addr = *seg;
5447 *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr;
5448 risc_size = be16_to_cpu(fwcode[3]);
5449
5450 /* Validate firmware image size. */
5451 fwclen += risc_size * sizeof(uint16_t);
5452 if (blob->fw->size < fwclen) {
7c3df132 5453 ql_log(ql_log_fatal, vha, 0x0088,
5433383e 5454 "Unable to verify integrity of firmware image "
7c3df132 5455 "(%Zd).\n", blob->fw->size);
5433383e
AV		 5456 goto fail_fw_integrity;
5457 }
5458
5459 fragment = 0;
5460 while (risc_size > 0 && rval == QLA_SUCCESS) {
5461 wlen = (uint16_t)(ha->fw_transfer_size >> 1);
5462 if (wlen > risc_size)
5463 wlen = risc_size;
7c3df132
SK		 5464 ql_dbg(ql_dbg_init, vha, 0x0089,
5465 "Loading risc segment@ risc addr %x number of "
5466 "words 0x%x.\n", risc_addr, wlen);
5433383e
AV		 5467
5468 for (i = 0; i < wlen; i++)
5469 wcode[i] = swab16(fwcode[i]);
5470
73208dfd 5471 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
5433383e
AV		 5472 wlen);
5473 if (rval) {
7c3df132
SK		 5474 ql_log(ql_log_fatal, vha, 0x008a,
5475 "Failed to load segment %d of firmware.\n",
5476 fragment);
5433383e
AV		 5477 break;
5478 }
5479
5480 fwcode += wlen;
5481 risc_addr += wlen;
5482 risc_size -= wlen;
5483 fragment++;
5484 }
5485
5486 /* Next segment. */
5487 seg++;
5488 }
5489 return rval;
5490
5491fail_fw_integrity:
5492 return QLA_FUNCTION_FAILED;
5493}
5494
eaac30be
AV		 5495static int
5496qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
0107109e
AV		 5497{
5498 int rval;
5499 int segments, fragment;
5500 uint32_t *dcode, dlen;
5501 uint32_t risc_addr;
5502 uint32_t risc_size;
5503 uint32_t i;
5433383e 5504 struct fw_blob *blob;
f73cb695
CD		 5505 const uint32_t *fwcode;
5506 uint32_t fwclen;
e315cd28 5507 struct qla_hw_data *ha = vha->hw;
73208dfd 5508 struct req_que *req = ha->req_q_map[0];
0107109e 5509
5433383e 5510 /* Load firmware blob. */
e315cd28 5511 blob = qla2x00_request_firmware(vha);
5433383e 5512 if (!blob) {
7c3df132 5513 ql_log(ql_log_warn, vha, 0x0090,
94bcf830 5514 "Firmware image unavailable.\n");
7c3df132
SK		 5515 ql_log(ql_log_warn, vha, 0x0091,
5516 "Firmware images can be retrieved from: "
5517 QLA_FW_URL ".\n");
d1c61909 5518
eaac30be 5519 return QLA_FUNCTION_FAILED;
0107109e
AV		 5520 }
5521
cfb0919c
CD		 5522 ql_dbg(ql_dbg_init, vha, 0x0092,
5523 "FW: Loading via request-firmware.\n");
eaac30be 5524
0107109e
AV		 5525 rval = QLA_SUCCESS;
5526
5527 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 5528 dcode = (uint32_t *)req->ring;
0107109e 5529 *srisc_addr = 0;
5433383e 5530 fwcode = (uint32_t *)blob->fw->data;
0107109e
AV		 5531 fwclen = 0;
5532
5533 /* Validate firmware image by checking version. */
5433383e 5534 if (blob->fw->size < 8 * sizeof(uint32_t)) {
7c3df132
SK		 5535 ql_log(ql_log_fatal, vha, 0x0093,
5536 "Unable to verify integrity of firmware image (%Zd).\n",
5433383e 5537 blob->fw->size);
f73cb695 5538 return QLA_FUNCTION_FAILED;
0107109e
AV		 5539 }
5540 for (i = 0; i < 4; i++)
5541 dcode[i] = be32_to_cpu(fwcode[i + 4]);
5542 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
5543 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
5544 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
5545 dcode[3] == 0)) {
7c3df132
SK		 5546 ql_log(ql_log_fatal, vha, 0x0094,
5547 "Unable to verify integrity of firmware image (%Zd).\n",
5548 blob->fw->size);
5549 ql_log(ql_log_fatal, vha, 0x0095,
5550 "Firmware data: %08x %08x %08x %08x.\n",
5551 dcode[0], dcode[1], dcode[2], dcode[3]);
f73cb695 5552 return QLA_FUNCTION_FAILED;
0107109e
AV		 5553 }
5554
5555 while (segments && rval == QLA_SUCCESS) {
5556 risc_addr = be32_to_cpu(fwcode[2]);
5557 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
5558 risc_size = be32_to_cpu(fwcode[3]);
5559
5560 /* Validate firmware image size. */
5561 fwclen += risc_size * sizeof(uint32_t);
5433383e 5562 if (blob->fw->size < fwclen) {
7c3df132 5563 ql_log(ql_log_fatal, vha, 0x0096,
5433383e 5564 "Unable to verify integrity of firmware image "
7c3df132 5565 "(%Zd).\n", blob->fw->size);
f73cb695 5566 return QLA_FUNCTION_FAILED;
0107109e
AV		 5567 }
5568
5569 fragment = 0;
5570 while (risc_size > 0 && rval == QLA_SUCCESS) {
5571 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
5572 if (dlen > risc_size)
5573 dlen = risc_size;
5574
7c3df132
SK		 5575 ql_dbg(ql_dbg_init, vha, 0x0097,
5576 "Loading risc segment@ risc addr %x "
5577 "number of dwords 0x%x.\n", risc_addr, dlen);
0107109e
AV		 5578
5579 for (i = 0; i < dlen; i++)
5580 dcode[i] = swab32(fwcode[i]);
5581
73208dfd 5582 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
590f98e5 5583 dlen);
0107109e 5584 if (rval) {
7c3df132
SK		 5585 ql_log(ql_log_fatal, vha, 0x0098,
5586 "Failed to load segment %d of firmware.\n",
5587 fragment);
f261f7af 5588 return QLA_FUNCTION_FAILED;
0107109e
AV		 5589 }
5590
5591 fwcode += dlen;
5592 risc_addr += dlen;
5593 risc_size -= dlen;
5594 fragment++;
5595 }
5596
5597 /* Next segment. */
5598 segments--;
5599 }
f73cb695
CD		 5600
5601 if (!IS_QLA27XX(ha))
5602 return rval;
5603
5604 if (ha->fw_dump_template)
5605 vfree(ha->fw_dump_template);
5606 ha->fw_dump_template = NULL;
5607 ha->fw_dump_template_len = 0;
5608
5609 ql_dbg(ql_dbg_init, vha, 0x171,
97ea702b
CD		 5610 "Loading fwdump template from %x\n",
5611 (uint32_t)((void *)fwcode - (void *)blob->fw->data));
f73cb695
CD		 5612 risc_size = be32_to_cpu(fwcode[2]);
5613 ql_dbg(ql_dbg_init, vha, 0x172,
5614 "-> array size %x dwords\n", risc_size);
5615 if (risc_size == 0 || risc_size == ~0)
5616 goto default_template;
5617
5618 dlen = (risc_size - 8) * sizeof(*fwcode);
5619 ql_dbg(ql_dbg_init, vha, 0x0173,
5620 "-> template allocating %x bytes...\n", dlen);
5621 ha->fw_dump_template = vmalloc(dlen);
5622 if (!ha->fw_dump_template) {
5623 ql_log(ql_log_warn, vha, 0x0174,
5624 "Failed fwdump template allocate %x bytes.\n", risc_size);
5625 goto default_template;
5626 }
5627
5628 fwcode += 7;
5629 risc_size -= 8;
5630 dcode = ha->fw_dump_template;
5631 for (i = 0; i < risc_size; i++)
5632 dcode[i] = le32_to_cpu(fwcode[i]);
5633
5634 if (!qla27xx_fwdt_template_valid(dcode)) {
5635 ql_log(ql_log_warn, vha, 0x0175,
5636 "Failed fwdump template validate\n");
5637 goto default_template;
5638 }
5639
5640 dlen = qla27xx_fwdt_template_size(dcode);
5641 ql_dbg(ql_dbg_init, vha, 0x0176,
5642 "-> template size %x bytes\n", dlen);
5643 if (dlen > risc_size * sizeof(*fwcode)) {
5644 ql_log(ql_log_warn, vha, 0x0177,
97ea702b
CD		 5645 "Failed fwdump template exceeds array by %x bytes\n",
5646 (uint32_t)(dlen - risc_size * sizeof(*fwcode)));
f73cb695
CD		 5647 goto default_template;
5648 }
5649 ha->fw_dump_template_len = dlen;
0107109e
AV		 5650 return rval;
5651
f73cb695
CD		 5652default_template:
5653 ql_log(ql_log_warn, vha, 0x0178, "Using default fwdump template\n");
5654 if (ha->fw_dump_template)
5655 vfree(ha->fw_dump_template);
5656 ha->fw_dump_template = NULL;
5657 ha->fw_dump_template_len = 0;
5658
5659 dlen = qla27xx_fwdt_template_default_size();
5660 ql_dbg(ql_dbg_init, vha, 0x0179,
5661 "-> template allocating %x bytes...\n", dlen);
5662 ha->fw_dump_template = vmalloc(dlen);
5663 if (!ha->fw_dump_template) {
5664 ql_log(ql_log_warn, vha, 0x017a,
5665 "Failed fwdump template allocate %x bytes.\n", risc_size);
5666 goto failed_template;
5667 }
5668
5669 dcode = ha->fw_dump_template;
5670 risc_size = dlen / sizeof(*fwcode);
5671 fwcode = qla27xx_fwdt_template_default();
5672 for (i = 0; i < risc_size; i++)
5673 dcode[i] = be32_to_cpu(fwcode[i]);
5674
5675 if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) {
5676 ql_log(ql_log_warn, vha, 0x017b,
5677 "Failed fwdump template validate\n");
5678 goto failed_template;
5679 }
5680
5681 dlen = qla27xx_fwdt_template_size(ha->fw_dump_template);
5682 ql_dbg(ql_dbg_init, vha, 0x017c,
5683 "-> template size %x bytes\n", dlen);
5684 ha->fw_dump_template_len = dlen;
5685 return rval;
5686
5687failed_template:
5688 ql_log(ql_log_warn, vha, 0x017d, "Failed default fwdump template\n");
5689 if (ha->fw_dump_template)
5690 vfree(ha->fw_dump_template);
5691 ha->fw_dump_template = NULL;
5692 ha->fw_dump_template_len = 0;
5693 return rval;
0107109e 5694}
18c6c127 5695
eaac30be
AV		 5696int
5697qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5698{
5699 int rval;
5700
e337d907
AV		 5701 if (ql2xfwloadbin == 1)
5702 return qla81xx_load_risc(vha, srisc_addr);
5703
eaac30be
AV		 5704 /*
5705 * FW Load priority:
5706 * 1) Firmware via request-firmware interface (.bin file).
5707 * 2) Firmware residing in flash.
5708 */
5709 rval = qla24xx_load_risc_blob(vha, srisc_addr);
5710 if (rval == QLA_SUCCESS)
5711 return rval;
5712
cbc8eb67
AV		 5713 return qla24xx_load_risc_flash(vha, srisc_addr,
5714 vha->hw->flt_region_fw);
eaac30be
AV		 5715}
5716
5717int
5718qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5719{
5720 int rval;
cbc8eb67 5721 struct qla_hw_data *ha = vha->hw;
eaac30be 5722
e337d907 5723 if (ql2xfwloadbin == 2)
cbc8eb67 5724 goto try_blob_fw;
e337d907 5725
eaac30be
AV		 5726 /*
5727 * FW Load priority:
5728 * 1) Firmware residing in flash.
5729 * 2) Firmware via request-firmware interface (.bin file).
cbc8eb67 5730 * 3) Golden-Firmware residing in flash -- limited operation.
eaac30be 5731 */
cbc8eb67 5732 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
eaac30be
AV		 5733 if (rval == QLA_SUCCESS)
5734 return rval;
5735
cbc8eb67
AV		 5736try_blob_fw:
5737 rval = qla24xx_load_risc_blob(vha, srisc_addr);
5738 if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw)
5739 return rval;
5740
7c3df132
SK		 5741 ql_log(ql_log_info, vha, 0x0099,
5742 "Attempting to fallback to golden firmware.\n");
cbc8eb67
AV		 5743 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
5744 if (rval != QLA_SUCCESS)
5745 return rval;
5746
7c3df132 5747 ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n");
cbc8eb67 5748 ha->flags.running_gold_fw = 1;
cbc8eb67 5749 return rval;
eaac30be
AV		 5750}
5751
18c6c127 5752void
e315cd28 5753qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha)
18c6c127
AV		 5754{
5755 int ret, retries;
e315cd28 5756 struct qla_hw_data *ha = vha->hw;
18c6c127 5757
85880801
AV		 5758 if (ha->flags.pci_channel_io_perm_failure)
5759 return;
e428924c 5760 if (!IS_FWI2_CAPABLE(ha))
18c6c127 5761 return;
75edf81d
AV		 5762 if (!ha->fw_major_version)
5763 return;
18c6c127 5764
e315cd28 5765 ret = qla2x00_stop_firmware(vha);
7c7f1f29 5766 for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&
b469a7cb 5767 ret != QLA_INVALID_COMMAND && retries ; retries--) {
e315cd28
AC		 5768 ha->isp_ops->reset_chip(vha);
5769 if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS)
18c6c127 5770 continue;
e315cd28 5771 if (qla2x00_setup_chip(vha) != QLA_SUCCESS)
18c6c127 5772 continue;
7c3df132
SK		 5773 ql_log(ql_log_info, vha, 0x8015,
5774 "Attempting retry of stop-firmware command.\n");
e315cd28 5775 ret = qla2x00_stop_firmware(vha);
18c6c127
AV		 5776 }
5777}
2c3dfe3f
SJ		 5778
5779int
e315cd28 5780qla24xx_configure_vhba(scsi_qla_host_t *vha)
2c3dfe3f
SJ		 5781{
5782 int rval = QLA_SUCCESS;
0b91d116 5783 int rval2;
2c3dfe3f 5784 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28
AC		 5785 struct qla_hw_data *ha = vha->hw;
5786 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
67c2e93a
AC		 5787 struct req_que *req;
5788 struct rsp_que *rsp;
2c3dfe3f 5789
e315cd28 5790 if (!vha->vp_idx)
2c3dfe3f
SJ		 5791 return -EINVAL;
5792
e315cd28 5793 rval = qla2x00_fw_ready(base_vha);
7163ea81 5794 if (ha->flags.cpu_affinity_enabled)
67c2e93a
AC		 5795 req = ha->req_q_map[0];
5796 else
5797 req = vha->req;
5798 rsp = req->rsp;
5799
2c3dfe3f 5800 if (rval == QLA_SUCCESS) {
e315cd28 5801 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
73208dfd 5802 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
2c3dfe3f
SJ		 5803 }
5804
e315cd28 5805 vha->flags.management_server_logged_in = 0;
2c3dfe3f
SJ		 5806
5807 /* Login to SNS first */
0b91d116
CD		 5808 rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb,
5809 BIT_1);
5810 if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
5811 if (rval2 == QLA_MEMORY_ALLOC_FAILED)
5812 ql_dbg(ql_dbg_init, vha, 0x0120,
5813 "Failed SNS login: loop_id=%x, rval2=%d\n",
5814 NPH_SNS, rval2);
5815 else
5816 ql_dbg(ql_dbg_init, vha, 0x0103,
5817 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x "
5818 "mb[2]=%x mb[6]=%x mb[7]=%x.\n",
5819 NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]);
2c3dfe3f
SJ		 5820 return (QLA_FUNCTION_FAILED);
5821 }
5822
e315cd28
AC		 5823 atomic_set(&vha->loop_down_timer, 0);
5824 atomic_set(&vha->loop_state, LOOP_UP);
5825 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5826 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
5827 rval = qla2x00_loop_resync(base_vha);
2c3dfe3f
SJ		 5828
5829 return rval;
5830}
4d4df193
HK		 5831
5832/* 84XX Support **************************************************************/
5833
5834static LIST_HEAD(qla_cs84xx_list);
5835static DEFINE_MUTEX(qla_cs84xx_mutex);
5836
5837static struct qla_chip_state_84xx *
e315cd28 5838qla84xx_get_chip(struct scsi_qla_host *vha)
4d4df193
HK		 5839{
5840 struct qla_chip_state_84xx *cs84xx;
e315cd28 5841 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5842
5843 mutex_lock(&qla_cs84xx_mutex);
5844
5845 /* Find any shared 84xx chip. */
5846 list_for_each_entry(cs84xx, &qla_cs84xx_list, list) {
5847 if (cs84xx->bus == ha->pdev->bus) {
5848 kref_get(&cs84xx->kref);
5849 goto done;
5850 }
5851 }
5852
5853 cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL);
5854 if (!cs84xx)
5855 goto done;
5856
5857 kref_init(&cs84xx->kref);
5858 spin_lock_init(&cs84xx->access_lock);
5859 mutex_init(&cs84xx->fw_update_mutex);
5860 cs84xx->bus = ha->pdev->bus;
5861
5862 list_add_tail(&cs84xx->list, &qla_cs84xx_list);
5863done:
5864 mutex_unlock(&qla_cs84xx_mutex);
5865 return cs84xx;
5866}
5867
5868static void
5869__qla84xx_chip_release(struct kref *kref)
5870{
5871 struct qla_chip_state_84xx *cs84xx =
5872 container_of(kref, struct qla_chip_state_84xx, kref);
5873
5874 mutex_lock(&qla_cs84xx_mutex);
5875 list_del(&cs84xx->list);
5876 mutex_unlock(&qla_cs84xx_mutex);
5877 kfree(cs84xx);
5878}
5879
5880void
e315cd28 5881qla84xx_put_chip(struct scsi_qla_host *vha)
4d4df193 5882{
e315cd28 5883 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5884 if (ha->cs84xx)
5885 kref_put(&ha->cs84xx->kref, __qla84xx_chip_release);
5886}
5887
5888static int
e315cd28 5889qla84xx_init_chip(scsi_qla_host_t *vha)
4d4df193
HK		 5890{
5891 int rval;
5892 uint16_t status[2];
e315cd28 5893 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5894
5895 mutex_lock(&ha->cs84xx->fw_update_mutex);
5896
e315cd28 5897 rval = qla84xx_verify_chip(vha, status);
4d4df193
HK		 5898
5899 mutex_unlock(&ha->cs84xx->fw_update_mutex);
5900
5901 return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED:
5902 QLA_SUCCESS;
5903}
3a03eb79
AV		 5904
5905/* 81XX Support **************************************************************/
5906
5907int
5908qla81xx_nvram_config(scsi_qla_host_t *vha)
5909{
5910 int rval;
5911 struct init_cb_81xx *icb;
5912 struct nvram_81xx *nv;
5913 uint32_t *dptr;
5914 uint8_t *dptr1, *dptr2;
5915 uint32_t chksum;
5916 uint16_t cnt;
5917 struct qla_hw_data *ha = vha->hw;
5918
5919 rval = QLA_SUCCESS;
5920 icb = (struct init_cb_81xx *)ha->init_cb;
5921 nv = ha->nvram;
5922
5923 /* Determine NVRAM starting address. */
5924 ha->nvram_size = sizeof(struct nvram_81xx);
3a03eb79 5925 ha->vpd_size = FA_NVRAM_VPD_SIZE;
7ec0effd
AD		 5926 if (IS_P3P_TYPE(ha) || IS_QLA8031(ha))
5927 ha->vpd_size = FA_VPD_SIZE_82XX;
3a03eb79
AV		 5928
5929 /* Get VPD data into cache */
5930 ha->vpd = ha->nvram + VPD_OFFSET;
3d79038f
AV		 5931 ha->isp_ops->read_optrom(vha, ha->vpd, ha->flt_region_vpd << 2,
5932 ha->vpd_size);
3a03eb79
AV		 5933
5934 /* Get NVRAM data into cache and calculate checksum. */
3d79038f 5935 ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2,
3a03eb79 5936 ha->nvram_size);
3d79038f 5937 dptr = (uint32_t *)nv;
3a03eb79
AV		 5938 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
5939 chksum += le32_to_cpu(*dptr++);
5940
7c3df132
SK		 5941 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
5942 "Contents of NVRAM:\n");
5943 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
5944 (uint8_t *)nv, ha->nvram_size);
3a03eb79
AV		 5945
5946 /* Bad NVRAM data, set defaults parameters. */
5947 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
5948 || nv->id[3] != ' ' ||
ad950360 5949 nv->nvram_version < cpu_to_le16(ICB_VERSION)) {
3a03eb79 5950 /* Reset NVRAM data. */
7c3df132 5951 ql_log(ql_log_info, vha, 0x0073,
9e336520 5952 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132 5953 "version=0x%x.\n", chksum, nv->id[0],
3a03eb79 5954 le16_to_cpu(nv->nvram_version));
7c3df132
SK		 5955 ql_log(ql_log_info, vha, 0x0074,
5956 "Falling back to functioning (yet invalid -- WWPN) "
5957 "defaults.\n");
3a03eb79
AV		 5958
5959 /*
5960 * Set default initialization control block.
5961 */
5962 memset(nv, 0, ha->nvram_size);
ad950360
BVA		 5963 nv->nvram_version = cpu_to_le16(ICB_VERSION);
5964 nv->version = cpu_to_le16(ICB_VERSION);
98aee70d 5965 nv->frame_payload_size = 2048;
ad950360
BVA		 5966 nv->execution_throttle = cpu_to_le16(0xFFFF);
5967 nv->exchange_count = cpu_to_le16(0);
3a03eb79 5968 nv->port_name[0] = 0x21;
f73cb695 5969 nv->port_name[1] = 0x00 + ha->port_no + 1;
3a03eb79
AV		 5970 nv->port_name[2] = 0x00;
5971 nv->port_name[3] = 0xe0;
5972 nv->port_name[4] = 0x8b;
5973 nv->port_name[5] = 0x1c;
5974 nv->port_name[6] = 0x55;
5975 nv->port_name[7] = 0x86;
5976 nv->node_name[0] = 0x20;
5977 nv->node_name[1] = 0x00;
5978 nv->node_name[2] = 0x00;
5979 nv->node_name[3] = 0xe0;
5980 nv->node_name[4] = 0x8b;
5981 nv->node_name[5] = 0x1c;
5982 nv->node_name[6] = 0x55;
5983 nv->node_name[7] = 0x86;
ad950360
BVA		 5984 nv->login_retry_count = cpu_to_le16(8);
5985 nv->interrupt_delay_timer = cpu_to_le16(0);
5986 nv->login_timeout = cpu_to_le16(0);
3a03eb79 5987 nv->firmware_options_1 =
ad950360
BVA		 5988 cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
5989 nv->firmware_options_2 = cpu_to_le32(2 << 4);
5990 nv->firmware_options_2 |= cpu_to_le32(BIT_12);
5991 nv->firmware_options_3 = cpu_to_le32(2 << 13);
5992 nv->host_p = cpu_to_le32(BIT_11|BIT_10);
5993 nv->efi_parameters = cpu_to_le32(0);
3a03eb79 5994 nv->reset_delay = 5;
ad950360
BVA		 5995 nv->max_luns_per_target = cpu_to_le16(128);
5996 nv->port_down_retry_count = cpu_to_le16(30);
5997 nv->link_down_timeout = cpu_to_le16(180);
eeebcc92 5998 nv->enode_mac[0] = 0x00;
6246b8a1
GM		 5999 nv->enode_mac[1] = 0xC0;
6000 nv->enode_mac[2] = 0xDD;
3a03eb79
AV		 6001 nv->enode_mac[3] = 0x04;
6002 nv->enode_mac[4] = 0x05;
f73cb695 6003 nv->enode_mac[5] = 0x06 + ha->port_no + 1;
3a03eb79
AV		 6004
6005 rval = 1;
6006 }
6007
9e522cd8
AE		 6008 if (IS_T10_PI_CAPABLE(ha))
6009 nv->frame_payload_size &= ~7;
6010
aa230bc5
AE		 6011 qlt_81xx_config_nvram_stage1(vha, nv);
6012
3a03eb79 6013 /* Reset Initialization control block */
773120e4 6014 memset(icb, 0, ha->init_cb_size);
3a03eb79
AV		 6015
6016 /* Copy 1st segment. */
6017 dptr1 = (uint8_t *)icb;
6018 dptr2 = (uint8_t *)&nv->version;
6019 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
6020 while (cnt--)
6021 *dptr1++ = *dptr2++;
6022
6023 icb->login_retry_count = nv->login_retry_count;
6024
6025 /* Copy 2nd segment. */
6026 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
6027 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
6028 cnt = (uint8_t *)&icb->reserved_5 -
6029 (uint8_t *)&icb->interrupt_delay_timer;
6030 while (cnt--)
6031 *dptr1++ = *dptr2++;
6032
6033 memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac));
6034 /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */
6035 if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) {
69e5f1ea
AV		 6036 icb->enode_mac[0] = 0x00;
6037 icb->enode_mac[1] = 0xC0;
6038 icb->enode_mac[2] = 0xDD;
3a03eb79
AV		 6039 icb->enode_mac[3] = 0x04;
6040 icb->enode_mac[4] = 0x05;
f73cb695 6041 icb->enode_mac[5] = 0x06 + ha->port_no + 1;
3a03eb79
AV		 6042 }
6043
b64b0e8f
AV		 6044 /* Use extended-initialization control block. */
6045 memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb));
6046
3a03eb79
AV		 6047 /*
6048 * Setup driver NVRAM options.
6049 */
6050 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
a9083016 6051 "QLE8XXX");
3a03eb79 6052
aa230bc5
AE		 6053 qlt_81xx_config_nvram_stage2(vha, icb);
6054
3a03eb79 6055 /* Use alternate WWN? */
ad950360 6056 if (nv->host_p & cpu_to_le32(BIT_15)) {
3a03eb79
AV		 6057 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
6058 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
6059 }
6060
6061 /* Prepare nodename */
ad950360 6062 if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) {
3a03eb79
AV		 6063 /*
6064 * Firmware will apply the following mask if the nodename was
6065 * not provided.
6066 */
6067 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
6068 icb->node_name[0] &= 0xF0;
6069 }
6070
6071 /* Set host adapter parameters. */
6072 ha->flags.disable_risc_code_load = 0;
6073 ha->flags.enable_lip_reset = 0;
6074 ha->flags.enable_lip_full_login =
6075 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
6076 ha->flags.enable_target_reset =
6077 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
6078 ha->flags.enable_led_scheme = 0;
6079 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
6080
6081 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
6082 (BIT_6 | BIT_5 | BIT_4)) >> 4;
6083
6084 /* save HBA serial number */
6085 ha->serial0 = icb->port_name[5];
6086 ha->serial1 = icb->port_name[6];
6087 ha->serial2 = icb->port_name[7];
6088 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
6089 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
6090
ad950360 6091 icb->execution_throttle = cpu_to_le16(0xFFFF);
3a03eb79
AV		 6092
6093 ha->retry_count = le16_to_cpu(nv->login_retry_count);
6094
6095 /* Set minimum login_timeout to 4 seconds. */
6096 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
6097 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
6098 if (le16_to_cpu(nv->login_timeout) < 4)
ad950360 6099 nv->login_timeout = cpu_to_le16(4);
3a03eb79
AV		 6100 ha->login_timeout = le16_to_cpu(nv->login_timeout);
6101 icb->login_timeout = nv->login_timeout;
6102
6103 /* Set minimum RATOV to 100 tenths of a second. */
6104 ha->r_a_tov = 100;
6105
6106 ha->loop_reset_delay = nv->reset_delay;
6107
6108 /* Link Down Timeout = 0:
6109 *
7ec0effd 6110 * When Port Down timer expires we will start returning
3a03eb79
AV		 6111 * I/O's to OS with "DID_NO_CONNECT".
6112 *
6113 * Link Down Timeout != 0:
6114 *
6115 * The driver waits for the link to come up after link down
6116 * before returning I/Os to OS with "DID_NO_CONNECT".
6117 */
6118 if (le16_to_cpu(nv->link_down_timeout) == 0) {
6119 ha->loop_down_abort_time =
6120 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
6121 } else {
6122 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
6123 ha->loop_down_abort_time =
6124 (LOOP_DOWN_TIME - ha->link_down_timeout);
6125 }
6126
6127 /* Need enough time to try and get the port back. */
6128 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
6129 if (qlport_down_retry)
6130 ha->port_down_retry_count = qlport_down_retry;
6131
6132 /* Set login_retry_count */
6133 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
6134 if (ha->port_down_retry_count ==
6135 le16_to_cpu(nv->port_down_retry_count) &&
6136 ha->port_down_retry_count > 3)
6137 ha->login_retry_count = ha->port_down_retry_count;
6138 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
6139 ha->login_retry_count = ha->port_down_retry_count;
6140 if (ql2xloginretrycount)
6141 ha->login_retry_count = ql2xloginretrycount;
6142
6246b8a1 6143 /* if not running MSI-X we need handshaking on interrupts */
f73cb695 6144 if (!vha->hw->flags.msix_enabled && (IS_QLA83XX(ha) || IS_QLA27XX(ha)))
ad950360 6145 icb->firmware_options_2 |= cpu_to_le32(BIT_22);
6246b8a1 6146
3a03eb79
AV		 6147 /* Enable ZIO. */
6148 if (!vha->flags.init_done) {
6149 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
6150 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
6151 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
6152 le16_to_cpu(icb->interrupt_delay_timer): 2;
6153 }
ad950360 6154 icb->firmware_options_2 &= cpu_to_le32(
3a03eb79
AV		 6155 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
6156 vha->flags.process_response_queue = 0;
6157 if (ha->zio_mode != QLA_ZIO_DISABLED) {
6158 ha->zio_mode = QLA_ZIO_MODE_6;
6159
7c3df132 6160 ql_log(ql_log_info, vha, 0x0075,
3a03eb79 6161 "ZIO mode %d enabled; timer delay (%d us).\n",
7c3df132
SK		 6162 ha->zio_mode,
6163 ha->zio_timer * 100);
3a03eb79
AV		 6164
6165 icb->firmware_options_2 |= cpu_to_le32(
6166 (uint32_t)ha->zio_mode);
6167 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
6168 vha->flags.process_response_queue = 1;
6169 }
6170
6171 if (rval) {
7c3df132
SK		 6172 ql_log(ql_log_warn, vha, 0x0076,
6173 "NVRAM configuration failed.\n");
3a03eb79
AV		 6174 }
6175 return (rval);
6176}
6177
a9083016
GM		 6178int
6179qla82xx_restart_isp(scsi_qla_host_t *vha)
6180{
6181 int status, rval;
a9083016
GM		 6182 struct qla_hw_data *ha = vha->hw;
6183 struct req_que *req = ha->req_q_map[0];
6184 struct rsp_que *rsp = ha->rsp_q_map[0];
6185 struct scsi_qla_host *vp;
feafb7b1 6186 unsigned long flags;
a9083016
GM		 6187
6188 status = qla2x00_init_rings(vha);
6189 if (!status) {
6190 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
6191 ha->flags.chip_reset_done = 1;
6192
6193 status = qla2x00_fw_ready(vha);
6194 if (!status) {
a9083016
GM		 6195 /* Issue a marker after FW becomes ready. */
6196 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
a9083016 6197 vha->flags.online = 1;
7108b76e 6198 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
a9083016
GM		 6199 }
6200
6201 /* if no cable then assume it's good */
6202 if ((vha->device_flags & DFLG_NO_CABLE))
6203 status = 0;
a9083016
GM		 6204 }
6205
6206 if (!status) {
6207 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
6208
6209 if (!atomic_read(&vha->loop_down_timer)) {
6210 /*
6211 * Issue marker command only when we are going
6212 * to start the I/O .
6213 */
6214 vha->marker_needed = 1;
6215 }
6216
a9083016
GM		 6217 ha->isp_ops->enable_intrs(ha);
6218
6219 ha->isp_abort_cnt = 0;
6220 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
6221
53296788 6222 /* Update the firmware version */
3173167f 6223 status = qla82xx_check_md_needed(vha);
53296788 6224
a9083016
GM		 6225 if (ha->fce) {
6226 ha->flags.fce_enabled = 1;
6227 memset(ha->fce, 0,
6228 fce_calc_size(ha->fce_bufs));
6229 rval = qla2x00_enable_fce_trace(vha,
6230 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
6231 &ha->fce_bufs);
6232 if (rval) {
cfb0919c 6233 ql_log(ql_log_warn, vha, 0x8001,
7c3df132
SK		 6234 "Unable to reinitialize FCE (%d).\n",
6235 rval);
a9083016
GM		 6236 ha->flags.fce_enabled = 0;
6237 }
6238 }
6239
6240 if (ha->eft) {
6241 memset(ha->eft, 0, EFT_SIZE);
6242 rval = qla2x00_enable_eft_trace(vha,
6243 ha->eft_dma, EFT_NUM_BUFFERS);
6244 if (rval) {
cfb0919c 6245 ql_log(ql_log_warn, vha, 0x8010,
7c3df132
SK		 6246 "Unable to reinitialize EFT (%d).\n",
6247 rval);
a9083016
GM		 6248 }
6249 }
a9083016
GM		 6250 }
6251
6252 if (!status) {
cfb0919c 6253 ql_dbg(ql_dbg_taskm, vha, 0x8011,
7c3df132 6254 "qla82xx_restart_isp succeeded.\n");
feafb7b1
AE		 6255
6256 spin_lock_irqsave(&ha->vport_slock, flags);
6257 list_for_each_entry(vp, &ha->vp_list, list) {
6258 if (vp->vp_idx) {
6259 atomic_inc(&vp->vref_count);
6260 spin_unlock_irqrestore(&ha->vport_slock, flags);
6261
a9083016 6262 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 6263
6264 spin_lock_irqsave(&ha->vport_slock, flags);
6265 atomic_dec(&vp->vref_count);
6266 }
a9083016 6267 }
feafb7b1
AE		 6268 spin_unlock_irqrestore(&ha->vport_slock, flags);
6269
a9083016 6270 } else {
cfb0919c 6271 ql_log(ql_log_warn, vha, 0x8016,
7c3df132 6272 "qla82xx_restart_isp **** FAILED ****.\n");
a9083016
GM		 6273 }
6274
6275 return status;
6276}
6277
3a03eb79 6278void
ae97c91e 6279qla81xx_update_fw_options(scsi_qla_host_t *vha)
3a03eb79 6280{
ae97c91e
AV		 6281 struct qla_hw_data *ha = vha->hw;
6282
6283 if (!ql2xetsenable)
6284 return;
6285
6286 /* Enable ETS Burst. */
6287 memset(ha->fw_options, 0, sizeof(ha->fw_options));
6288 ha->fw_options[2] |= BIT_9;
6289 qla2x00_set_fw_options(vha, ha->fw_options);
3a03eb79 6290}
09ff701a
SR		 6291
6292/*
6293 * qla24xx_get_fcp_prio
6294 * Gets the fcp cmd priority value for the logged in port.
6295 * Looks for a match of the port descriptors within
6296 * each of the fcp prio config entries. If a match is found,
6297 * the tag (priority) value is returned.
6298 *
6299 * Input:
21090cbe 6300 * vha = scsi host structure pointer.
09ff701a
SR		 6301 * fcport = port structure pointer.
6302 *
6303 * Return:
6c452a45 6304 * non-zero (if found)
f28a0a96 6305 * -1 (if not found)
09ff701a
SR		 6306 *
6307 * Context:
6308 * Kernel context
6309 */
f28a0a96 6310static int
09ff701a
SR		 6311qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
6312{
6313 int i, entries;
6314 uint8_t pid_match, wwn_match;
f28a0a96 6315 int priority;
09ff701a
SR		 6316 uint32_t pid1, pid2;
6317 uint64_t wwn1, wwn2;
6318 struct qla_fcp_prio_entry *pri_entry;
6319 struct qla_hw_data *ha = vha->hw;
6320
6321 if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled)
f28a0a96 6322 return -1;
09ff701a 6323
f28a0a96 6324 priority = -1;
09ff701a
SR		 6325 entries = ha->fcp_prio_cfg->num_entries;
6326 pri_entry = &ha->fcp_prio_cfg->entry[0];
6327
6328 for (i = 0; i < entries; i++) {
6329 pid_match = wwn_match = 0;
6330
6331 if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) {
6332 pri_entry++;
6333 continue;
6334 }
6335
6336 /* check source pid for a match */
6337 if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) {
6338 pid1 = pri_entry->src_pid & INVALID_PORT_ID;
6339 pid2 = vha->d_id.b24 & INVALID_PORT_ID;
6340 if (pid1 == INVALID_PORT_ID)
6341 pid_match++;
6342 else if (pid1 == pid2)
6343 pid_match++;
6344 }
6345
6346 /* check destination pid for a match */
6347 if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) {
6348 pid1 = pri_entry->dst_pid & INVALID_PORT_ID;
6349 pid2 = fcport->d_id.b24 & INVALID_PORT_ID;
6350 if (pid1 == INVALID_PORT_ID)
6351 pid_match++;
6352 else if (pid1 == pid2)
6353 pid_match++;
6354 }
6355
6356 /* check source WWN for a match */
6357 if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) {
6358 wwn1 = wwn_to_u64(vha->port_name);
6359 wwn2 = wwn_to_u64(pri_entry->src_wwpn);
6360 if (wwn2 == (uint64_t)-1)
6361 wwn_match++;
6362 else if (wwn1 == wwn2)
6363 wwn_match++;
6364 }
6365
6366 /* check destination WWN for a match */
6367 if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) {
6368 wwn1 = wwn_to_u64(fcport->port_name);
6369 wwn2 = wwn_to_u64(pri_entry->dst_wwpn);
6370 if (wwn2 == (uint64_t)-1)
6371 wwn_match++;
6372 else if (wwn1 == wwn2)
6373 wwn_match++;
6374 }
6375
6376 if (pid_match == 2 || wwn_match == 2) {
6377 /* Found a matching entry */
6378 if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID)
6379 priority = pri_entry->tag;
6380 break;
6381 }
6382
6383 pri_entry++;
6384 }
6385
6386 return priority;
6387}
6388
6389/*
6390 * qla24xx_update_fcport_fcp_prio
6391 * Activates fcp priority for the logged in fc port
6392 *
6393 * Input:
21090cbe 6394 * vha = scsi host structure pointer.
09ff701a
SR		 6395 * fcp = port structure pointer.
6396 *
6397 * Return:
6398 * QLA_SUCCESS or QLA_FUNCTION_FAILED
6399 *
6400 * Context:
6401 * Kernel context.
6402 */
6403int
21090cbe 6404qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
09ff701a
SR		 6405{
6406 int ret;
f28a0a96 6407 int priority;
09ff701a
SR		 6408 uint16_t mb[5];
6409
21090cbe
MI		 6410 if (fcport->port_type != FCT_TARGET ||
6411 fcport->loop_id == FC_NO_LOOP_ID)
09ff701a
SR		 6412 return QLA_FUNCTION_FAILED;
6413
21090cbe 6414 priority = qla24xx_get_fcp_prio(vha, fcport);
f28a0a96
AV		 6415 if (priority < 0)
6416 return QLA_FUNCTION_FAILED;
6417
7ec0effd 6418 if (IS_P3P_TYPE(vha->hw)) {
a00f6296
SK		 6419 fcport->fcp_prio = priority & 0xf;
6420 return QLA_SUCCESS;
6421 }
6422
21090cbe 6423 ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb);
cfb0919c
CD		 6424 if (ret == QLA_SUCCESS) {
6425 if (fcport->fcp_prio != priority)
6426 ql_dbg(ql_dbg_user, vha, 0x709e,
6427 "Updated FCP_CMND priority - value=%d loop_id=%d "
6428 "port_id=%02x%02x%02x.\n", priority,
6429 fcport->loop_id, fcport->d_id.b.domain,
6430 fcport->d_id.b.area, fcport->d_id.b.al_pa);
a00f6296 6431 fcport->fcp_prio = priority & 0xf;
cfb0919c 6432 } else
7c3df132 6433 ql_dbg(ql_dbg_user, vha, 0x704f,
cfb0919c
CD		 6434 "Unable to update FCP_CMND priority - ret=0x%x for "
6435 "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id,
6436 fcport->d_id.b.domain, fcport->d_id.b.area,
6437 fcport->d_id.b.al_pa);
09ff701a
SR		 6438 return ret;
6439}
6440
6441/*
6442 * qla24xx_update_all_fcp_prio
6443 * Activates fcp priority for all the logged in ports
6444 *
6445 * Input:
6446 * ha = adapter block pointer.
6447 *
6448 * Return:
6449 * QLA_SUCCESS or QLA_FUNCTION_FAILED
6450 *
6451 * Context:
6452 * Kernel context.
6453 */
6454int
6455qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha)
6456{
6457 int ret;
6458 fc_port_t *fcport;
6459
6460 ret = QLA_FUNCTION_FAILED;
6461 /* We need to set priority for all logged in ports */
6462 list_for_each_entry(fcport, &vha->vp_fcports, list)
6463 ret = qla24xx_update_fcport_fcp_prio(vha, fcport);
6464
6465 return ret;
6466}
ubuntu-bionic-kernel mirror