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scsi: qla2xxx: Fix slow mem alloc behind lock
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / qla2xxx / qla_init.c
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1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
73208dfd 8#include "qla_gbl.h"
1da177e4
LT		 9
10#include <linux/delay.h>
5a0e3ad6 11#include <linux/slab.h>
0107109e 12#include <linux/vmalloc.h>
1da177e4
LT		 13
14#include "qla_devtbl.h"
15
4e08df3f
DM		 16#ifdef CONFIG_SPARC
17#include <asm/prom.h>
4e08df3f
DM		 18#endif
19
2d70c103
NB		 20#include <target/target_core_base.h>
21#include "qla_target.h"
22
1da177e4
LT		 23/*
24* QLogic ISP2x00 Hardware Support Function Prototypes.
25*/
1da177e4 26static int qla2x00_isp_firmware(scsi_qla_host_t *);
1da177e4 27static int qla2x00_setup_chip(scsi_qla_host_t *);
1da177e4
LT		 28static int qla2x00_fw_ready(scsi_qla_host_t *);
29static int qla2x00_configure_hba(scsi_qla_host_t *);
1da177e4
LT		 30static int qla2x00_configure_loop(scsi_qla_host_t *);
31static int qla2x00_configure_local_loop(scsi_qla_host_t *);
1da177e4 32static int qla2x00_configure_fabric(scsi_qla_host_t *);
726b8548 33static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *);
1da177e4 34static int qla2x00_restart_isp(scsi_qla_host_t *);
1da177e4 35
4d4df193
HK		 36static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *);
37static int qla84xx_init_chip(scsi_qla_host_t *);
73208dfd 38static int qla25xx_init_queues(struct qla_hw_data *);
a5d42f4c 39static int qla24xx_post_prli_work(struct scsi_qla_host*, fc_port_t *);
726b8548
QT		 40static void qla24xx_handle_plogi_done_event(struct scsi_qla_host *,
41 struct event_arg *);
a5d42f4c
DG		 42static void qla24xx_handle_prli_done_event(struct scsi_qla_host *,
43 struct event_arg *);
4d4df193 44
ac280b67
AV		 45/* SRB Extensions ---------------------------------------------------------- */
46
9ba56b95
GM		 47void
48qla2x00_sp_timeout(unsigned long __data)
ac280b67
AV		 49{
50 srb_t *sp = (srb_t *)__data;
4916392b 51 struct srb_iocb *iocb;
25ff6af1 52 scsi_qla_host_t *vha = sp->vha;
ac280b67
AV		 53 struct req_que *req;
54 unsigned long flags;
55
25ff6af1
JC		 56 spin_lock_irqsave(&vha->hw->hardware_lock, flags);
57 req = vha->hw->req_q_map[0];
ac280b67 58 req->outstanding_cmds[sp->handle] = NULL;
9ba56b95 59 iocb = &sp->u.iocb_cmd;
4916392b 60 iocb->timeout(sp);
25ff6af1
JC		 61 sp->free(sp);
62 spin_unlock_irqrestore(&vha->hw->hardware_lock, flags);
ac280b67
AV		 63}
64
9ba56b95 65void
25ff6af1 66qla2x00_sp_free(void *ptr)
ac280b67 67{
25ff6af1 68 srb_t *sp = ptr;
9ba56b95 69 struct srb_iocb *iocb = &sp->u.iocb_cmd;
ac280b67 70
4d97cc53 71 del_timer(&iocb->timer);
25ff6af1 72 qla2x00_rel_sp(sp);
ac280b67
AV		 73}
74
ac280b67
AV		 75/* Asynchronous Login/Logout Routines -------------------------------------- */
76
a9b6f722 77unsigned long
5b91490e
AV		 78qla2x00_get_async_timeout(struct scsi_qla_host *vha)
79{
80 unsigned long tmo;
81 struct qla_hw_data *ha = vha->hw;
82
83 /* Firmware should use switch negotiated r_a_tov for timeout. */
84 tmo = ha->r_a_tov / 10 * 2;
8ae6d9c7
GM		 85 if (IS_QLAFX00(ha)) {
86 tmo = FX00_DEF_RATOV * 2;
87 } else if (!IS_FWI2_CAPABLE(ha)) {
5b91490e
AV		 88 /*
89 * Except for earlier ISPs where the timeout is seeded from the
90 * initialization control block.
91 */
92 tmo = ha->login_timeout;
93 }
94 return tmo;
95}
ac280b67 96
726b8548 97void
9ba56b95 98qla2x00_async_iocb_timeout(void *data)
ac280b67 99{
25ff6af1 100 srb_t *sp = data;
ac280b67 101 fc_port_t *fcport = sp->fcport;
726b8548
QT		 102 struct srb_iocb *lio = &sp->u.iocb_cmd;
103 struct event_arg ea;
ac280b67 104
7c3df132 105 ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
726b8548
QT		 106 "Async-%s timeout - hdl=%x portid=%06x %8phC.\n",
107 sp->name, sp->handle, fcport->d_id.b24, fcport->port_name);
ac280b67 108
5ff1d584 109 fcport->flags &= ~FCF_ASYNC_SENT;
726b8548
QT		 110
111 switch (sp->type) {
112 case SRB_LOGIN_CMD:
6ac52608
AV		 113 /* Retry as needed. */
114 lio->u.logio.data[0] = MBS_COMMAND_ERROR;
115 lio->u.logio.data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
116 QLA_LOGIO_LOGIN_RETRIED : 0;
726b8548
QT		 117 memset(&ea, 0, sizeof(ea));
118 ea.event = FCME_PLOGI_DONE;
119 ea.fcport = sp->fcport;
120 ea.data[0] = lio->u.logio.data[0];
121 ea.data[1] = lio->u.logio.data[1];
122 ea.sp = sp;
123 qla24xx_handle_plogi_done_event(fcport->vha, &ea);
124 break;
125 case SRB_LOGOUT_CMD:
a6ca8878 126 qlt_logo_completion_handler(fcport, QLA_FUNCTION_TIMEOUT);
726b8548
QT		 127 break;
128 case SRB_CT_PTHRU_CMD:
129 case SRB_MB_IOCB:
130 case SRB_NACK_PLOGI:
131 case SRB_NACK_PRLI:
132 case SRB_NACK_LOGO:
25ff6af1 133 sp->done(sp, QLA_FUNCTION_TIMEOUT);
726b8548 134 break;
6ac52608 135 }
ac280b67
AV		 136}
137
99b0bec7 138static void
25ff6af1 139qla2x00_async_login_sp_done(void *ptr, int res)
99b0bec7 140{
25ff6af1
JC		 141 srb_t *sp = ptr;
142 struct scsi_qla_host *vha = sp->vha;
9ba56b95 143 struct srb_iocb *lio = &sp->u.iocb_cmd;
726b8548 144 struct event_arg ea;
9ba56b95 145
83548fe2 146 ql_dbg(ql_dbg_disc, vha, 0x20dd,
25ff6af1 147 "%s %8phC res %d \n", __func__, sp->fcport->port_name, res);
726b8548
QT		 148
149 sp->fcport->flags &= ~FCF_ASYNC_SENT;
150 if (!test_bit(UNLOADING, &vha->dpc_flags)) {
151 memset(&ea, 0, sizeof(ea));
152 ea.event = FCME_PLOGI_DONE;
153 ea.fcport = sp->fcport;
154 ea.data[0] = lio->u.logio.data[0];
155 ea.data[1] = lio->u.logio.data[1];
156 ea.iop[0] = lio->u.logio.iop[0];
157 ea.iop[1] = lio->u.logio.iop[1];
158 ea.sp = sp;
159 qla2x00_fcport_event_handler(vha, &ea);
160 }
9ba56b95 161
25ff6af1 162 sp->free(sp);
99b0bec7
AV		 163}
164
ac280b67
AV		 165int
166qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport,
167 uint16_t *data)
168{
ac280b67 169 srb_t *sp;
4916392b 170 struct srb_iocb *lio;
726b8548
QT		 171 int rval = QLA_FUNCTION_FAILED;
172
173 if (!vha->flags.online)
174 goto done;
175
176 if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) ||
177 (fcport->fw_login_state == DSC_LS_PLOGI_COMP) ||
178 (fcport->fw_login_state == DSC_LS_PRLI_PEND))
179 goto done;
ac280b67 180
9ba56b95 181 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 182 if (!sp)
183 goto done;
184
726b8548
QT		 185 fcport->flags |= FCF_ASYNC_SENT;
186 fcport->logout_completed = 0;
187
9ba56b95
GM		 188 sp->type = SRB_LOGIN_CMD;
189 sp->name = "login";
190 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
191
192 lio = &sp->u.iocb_cmd;
3822263e 193 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 194 sp->done = qla2x00_async_login_sp_done;
4916392b 195 lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI;
a5d42f4c
DG		 196
197 if (fcport->fc4f_nvme)
198 lio->u.logio.flags |= SRB_LOGIN_SKIP_PRLI;
199
ac280b67 200 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 201 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
ac280b67 202 rval = qla2x00_start_sp(sp);
080c9517
CD		 203 if (rval != QLA_SUCCESS) {
204 fcport->flags &= ~FCF_ASYNC_SENT;
205 fcport->flags |= FCF_LOGIN_NEEDED;
206 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
ac280b67 207 goto done_free_sp;
080c9517 208 }
ac280b67 209
7c3df132 210 ql_dbg(ql_dbg_disc, vha, 0x2072,
726b8548
QT		 211 "Async-login - %8phC hdl=%x, loopid=%x portid=%02x%02x%02x "
212 "retries=%d.\n", fcport->port_name, sp->handle, fcport->loop_id,
cfb0919c
CD		 213 fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
214 fcport->login_retry);
ac280b67
AV		 215 return rval;
216
217done_free_sp:
25ff6af1 218 sp->free(sp);
ac280b67 219done:
726b8548 220 fcport->flags &= ~FCF_ASYNC_SENT;
ac280b67
AV		 221 return rval;
222}
223
99b0bec7 224static void
25ff6af1 225qla2x00_async_logout_sp_done(void *ptr, int res)
99b0bec7 226{
25ff6af1 227 srb_t *sp = ptr;
9ba56b95 228 struct srb_iocb *lio = &sp->u.iocb_cmd;
9ba56b95 229
726b8548 230 sp->fcport->flags &= ~FCF_ASYNC_SENT;
25ff6af1
JC		 231 if (!test_bit(UNLOADING, &sp->vha->dpc_flags))
232 qla2x00_post_async_logout_done_work(sp->vha, sp->fcport,
9ba56b95 233 lio->u.logio.data);
25ff6af1 234 sp->free(sp);
99b0bec7
AV		 235}
236
ac280b67
AV		 237int
238qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport)
239{
ac280b67 240 srb_t *sp;
4916392b 241 struct srb_iocb *lio;
ac280b67
AV		 242 int rval;
243
244 rval = QLA_FUNCTION_FAILED;
726b8548 245 fcport->flags |= FCF_ASYNC_SENT;
9ba56b95 246 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 247 if (!sp)
248 goto done;
249
9ba56b95
GM		 250 sp->type = SRB_LOGOUT_CMD;
251 sp->name = "logout";
252 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
253
254 lio = &sp->u.iocb_cmd;
3822263e 255 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 256 sp->done = qla2x00_async_logout_sp_done;
ac280b67
AV		 257 rval = qla2x00_start_sp(sp);
258 if (rval != QLA_SUCCESS)
259 goto done_free_sp;
260
7c3df132 261 ql_dbg(ql_dbg_disc, vha, 0x2070,
726b8548 262 "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x %8phC.\n",
cfb0919c 263 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
726b8548
QT		 264 fcport->d_id.b.area, fcport->d_id.b.al_pa,
265 fcport->port_name);
ac280b67
AV		 266 return rval;
267
268done_free_sp:
25ff6af1 269 sp->free(sp);
ac280b67 270done:
726b8548 271 fcport->flags &= ~FCF_ASYNC_SENT;
ac280b67
AV		 272 return rval;
273}
274
5ff1d584 275static void
25ff6af1 276qla2x00_async_adisc_sp_done(void *ptr, int res)
5ff1d584 277{
25ff6af1
JC		 278 srb_t *sp = ptr;
279 struct scsi_qla_host *vha = sp->vha;
9ba56b95 280 struct srb_iocb *lio = &sp->u.iocb_cmd;
9ba56b95
GM		 281
282 if (!test_bit(UNLOADING, &vha->dpc_flags))
25ff6af1 283 qla2x00_post_async_adisc_done_work(sp->vha, sp->fcport,
9ba56b95 284 lio->u.logio.data);
25ff6af1 285 sp->free(sp);
5ff1d584
AV		 286}
287
288int
289qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport,
290 uint16_t *data)
291{
5ff1d584 292 srb_t *sp;
4916392b 293 struct srb_iocb *lio;
5ff1d584
AV		 294 int rval;
295
296 rval = QLA_FUNCTION_FAILED;
726b8548 297 fcport->flags |= FCF_ASYNC_SENT;
9ba56b95 298 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
5ff1d584
AV		 299 if (!sp)
300 goto done;
301
9ba56b95
GM		 302 sp->type = SRB_ADISC_CMD;
303 sp->name = "adisc";
304 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
305
306 lio = &sp->u.iocb_cmd;
3822263e 307 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 308 sp->done = qla2x00_async_adisc_sp_done;
5ff1d584 309 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 310 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
5ff1d584
AV		 311 rval = qla2x00_start_sp(sp);
312 if (rval != QLA_SUCCESS)
313 goto done_free_sp;
314
7c3df132 315 ql_dbg(ql_dbg_disc, vha, 0x206f,
cfb0919c
CD		 316 "Async-adisc - hdl=%x loopid=%x portid=%02x%02x%02x.\n",
317 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
318 fcport->d_id.b.area, fcport->d_id.b.al_pa);
5ff1d584
AV		 319 return rval;
320
321done_free_sp:
25ff6af1 322 sp->free(sp);
5ff1d584 323done:
726b8548
QT		 324 fcport->flags &= ~FCF_ASYNC_SENT;
325 return rval;
326}
327
328static void qla24xx_handle_gnl_done_event(scsi_qla_host_t *vha,
329 struct event_arg *ea)
330{
331 fc_port_t *fcport, *conflict_fcport;
332 struct get_name_list_extended *e;
333 u16 i, n, found = 0, loop_id;
334 port_id_t id;
335 u64 wwn;
a5d42f4c 336 u8 opt = 0, current_login_state;
726b8548
QT		 337
338 fcport = ea->fcport;
339
340 if (ea->rc) { /* rval */
341 if (fcport->login_retry == 0) {
342 fcport->login_retry = vha->hw->login_retry_count;
83548fe2
QT		 343 ql_dbg(ql_dbg_disc, vha, 0x20de,
344 "GNL failed Port login retry %8phN, retry cnt=%d.\n",
345 fcport->port_name, fcport->login_retry);
726b8548
QT		 346 }
347 return;
348 }
349
350 if (fcport->last_rscn_gen != fcport->rscn_gen) {
83548fe2 351 ql_dbg(ql_dbg_disc, vha, 0x20df,
726b8548
QT		 352 "%s %8phC rscn gen changed rscn %d|%d \n",
353 __func__, fcport->port_name,
354 fcport->last_rscn_gen, fcport->rscn_gen);
355 qla24xx_post_gidpn_work(vha, fcport);
356 return;
357 } else if (fcport->last_login_gen != fcport->login_gen) {
83548fe2
QT		 358 ql_dbg(ql_dbg_disc, vha, 0x20e0,
359 "%s %8phC login gen changed login %d|%d\n",
360 __func__, fcport->port_name,
361 fcport->last_login_gen, fcport->login_gen);
726b8548
QT		 362 return;
363 }
364
365 n = ea->data[0] / sizeof(struct get_name_list_extended);
366
83548fe2 367 ql_dbg(ql_dbg_disc, vha, 0x20e1,
726b8548
QT		 368 "%s %d %8phC n %d %02x%02x%02x lid %d \n",
369 __func__, __LINE__, fcport->port_name, n,
370 fcport->d_id.b.domain, fcport->d_id.b.area,
371 fcport->d_id.b.al_pa, fcport->loop_id);
372
373 for (i = 0; i < n; i++) {
374 e = &vha->gnl.l[i];
375 wwn = wwn_to_u64(e->port_name);
376
377 if (memcmp((u8 *)&wwn, fcport->port_name, WWN_SIZE))
378 continue;
379
380 found = 1;
381 id.b.domain = e->port_id[2];
382 id.b.area = e->port_id[1];
383 id.b.al_pa = e->port_id[0];
384 id.b.rsvd_1 = 0;
385
386 loop_id = le16_to_cpu(e->nport_handle);
387 loop_id = (loop_id & 0x7fff);
388
83548fe2
QT		 389 ql_dbg(ql_dbg_disc, vha, 0x20e2,
390 "%s found %8phC CLS [%d|%d] ID[%02x%02x%02x|%02x%02x%02x] lid[%d|%d]\n",
391 __func__, fcport->port_name,
392 e->current_login_state, fcport->fw_login_state,
393 id.b.domain, id.b.area, id.b.al_pa,
394 fcport->d_id.b.domain, fcport->d_id.b.area,
395 fcport->d_id.b.al_pa, loop_id, fcport->loop_id);
726b8548
QT		 396
397 if ((id.b24 != fcport->d_id.b24) ||
398 ((fcport->loop_id != FC_NO_LOOP_ID) &&
399 (fcport->loop_id != loop_id))) {
83548fe2
QT		 400 ql_dbg(ql_dbg_disc, vha, 0x20e3,
401 "%s %d %8phC post del sess\n",
402 __func__, __LINE__, fcport->port_name);
726b8548
QT		 403 qlt_schedule_sess_for_deletion(fcport, 1);
404 return;
405 }
406
407 fcport->loop_id = loop_id;
408
409 wwn = wwn_to_u64(fcport->port_name);
410 qlt_find_sess_invalidate_other(vha, wwn,
411 id, loop_id, &conflict_fcport);
412
413 if (conflict_fcport) {
414 /*
415 * Another share fcport share the same loop_id &
416 * nport id. Conflict fcport needs to finish
417 * cleanup before this fcport can proceed to login.
418 */
419 conflict_fcport->conflict = fcport;
420 fcport->login_pause = 1;
421 }
422
a5d42f4c
DG		 423 if (fcport->fc4f_nvme)
424 current_login_state = e->current_login_state >> 4;
425 else
426 current_login_state = e->current_login_state & 0xf;
427
428 switch (current_login_state) {
726b8548 429 case DSC_LS_PRLI_COMP:
83548fe2
QT		 430 ql_dbg(ql_dbg_disc, vha, 0x20e4,
431 "%s %d %8phC post gpdb\n",
432 __func__, __LINE__, fcport->port_name);
726b8548
QT		 433 opt = PDO_FORCE_ADISC;
434 qla24xx_post_gpdb_work(vha, fcport, opt);
435 break;
726b8548
QT		 436 case DSC_LS_PORT_UNAVAIL:
437 default:
438 if (fcport->loop_id == FC_NO_LOOP_ID) {
439 qla2x00_find_new_loop_id(vha, fcport);
440 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL;
441 }
83548fe2
QT		 442 ql_dbg(ql_dbg_disc, vha, 0x20e5,
443 "%s %d %8phC\n",
444 __func__, __LINE__, fcport->port_name);
726b8548
QT		 445 qla24xx_fcport_handle_login(vha, fcport);
446 break;
447 }
448 }
449
450 if (!found) {
451 /* fw has no record of this port */
452 if (fcport->loop_id == FC_NO_LOOP_ID) {
453 qla2x00_find_new_loop_id(vha, fcport);
454 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL;
455 } else {
456 for (i = 0; i < n; i++) {
457 e = &vha->gnl.l[i];
458 id.b.domain = e->port_id[0];
459 id.b.area = e->port_id[1];
460 id.b.al_pa = e->port_id[2];
461 id.b.rsvd_1 = 0;
462 loop_id = le16_to_cpu(e->nport_handle);
463
464 if (fcport->d_id.b24 == id.b24) {
465 conflict_fcport =
466 qla2x00_find_fcport_by_wwpn(vha,
467 e->port_name, 0);
468
83548fe2 469 ql_dbg(ql_dbg_disc, vha, 0x20e6,
726b8548
QT		 470 "%s %d %8phC post del sess\n",
471 __func__, __LINE__,
472 conflict_fcport->port_name);
473 qlt_schedule_sess_for_deletion
474 (conflict_fcport, 1);
475 }
476
477 if (fcport->loop_id == loop_id) {
478 /* FW already picked this loop id for another fcport */
479 qla2x00_find_new_loop_id(vha, fcport);
480 }
481 }
482 }
483 qla24xx_fcport_handle_login(vha, fcport);
484 }
485} /* gnl_event */
486
487static void
25ff6af1 488qla24xx_async_gnl_sp_done(void *s, int res)
726b8548 489{
25ff6af1
JC		 490 struct srb *sp = s;
491 struct scsi_qla_host *vha = sp->vha;
726b8548
QT		 492 unsigned long flags;
493 struct fc_port *fcport = NULL, *tf;
494 u16 i, n = 0, loop_id;
495 struct event_arg ea;
496 struct get_name_list_extended *e;
497 u64 wwn;
498 struct list_head h;
499
83548fe2 500 ql_dbg(ql_dbg_disc, vha, 0x20e7,
726b8548
QT		 501 "Async done-%s res %x mb[1]=%x mb[2]=%x \n",
502 sp->name, res, sp->u.iocb_cmd.u.mbx.in_mb[1],
503 sp->u.iocb_cmd.u.mbx.in_mb[2]);
504
505 memset(&ea, 0, sizeof(ea));
506 ea.sp = sp;
507 ea.rc = res;
508 ea.event = FCME_GNL_DONE;
509
510 if (sp->u.iocb_cmd.u.mbx.in_mb[1] >=
511 sizeof(struct get_name_list_extended)) {
512 n = sp->u.iocb_cmd.u.mbx.in_mb[1] /
513 sizeof(struct get_name_list_extended);
514 ea.data[0] = sp->u.iocb_cmd.u.mbx.in_mb[1]; /* amnt xfered */
515 }
516
517 for (i = 0; i < n; i++) {
518 e = &vha->gnl.l[i];
519 loop_id = le16_to_cpu(e->nport_handle);
520 /* mask out reserve bit */
521 loop_id = (loop_id & 0x7fff);
522 set_bit(loop_id, vha->hw->loop_id_map);
523 wwn = wwn_to_u64(e->port_name);
524
83548fe2 525 ql_dbg(ql_dbg_disc + ql_dbg_verbose, vha, 0x20e8,
726b8548
QT		 526 "%s %8phC %02x:%02x:%02x state %d/%d lid %x \n",
527 __func__, (void *)&wwn, e->port_id[2], e->port_id[1],
528 e->port_id[0], e->current_login_state, e->last_login_state,
529 (loop_id & 0x7fff));
530 }
531
532 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
533 vha->gnl.sent = 0;
534
535 INIT_LIST_HEAD(&h);
536 fcport = tf = NULL;
537 if (!list_empty(&vha->gnl.fcports))
538 list_splice_init(&vha->gnl.fcports, &h);
539
540 list_for_each_entry_safe(fcport, tf, &h, gnl_entry) {
541 list_del_init(&fcport->gnl_entry);
542 fcport->flags &= ~FCF_ASYNC_SENT;
543 ea.fcport = fcport;
544
545 qla2x00_fcport_event_handler(vha, &ea);
546 }
547
548 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
549
25ff6af1 550 sp->free(sp);
726b8548
QT		 551}
552
553int qla24xx_async_gnl(struct scsi_qla_host *vha, fc_port_t *fcport)
554{
555 srb_t *sp;
556 struct srb_iocb *mbx;
557 int rval = QLA_FUNCTION_FAILED;
558 unsigned long flags;
559 u16 *mb;
560
561 if (!vha->flags.online)
562 goto done;
563
83548fe2 564 ql_dbg(ql_dbg_disc, vha, 0x20d9,
726b8548
QT		 565 "Async-gnlist WWPN %8phC \n", fcport->port_name);
566
567 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
568 fcport->flags |= FCF_ASYNC_SENT;
569 fcport->disc_state = DSC_GNL;
570 fcport->last_rscn_gen = fcport->rscn_gen;
571 fcport->last_login_gen = fcport->login_gen;
572
573 list_add_tail(&fcport->gnl_entry, &vha->gnl.fcports);
574 if (vha->gnl.sent) {
575 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
576 rval = QLA_SUCCESS;
577 goto done;
578 }
579 vha->gnl.sent = 1;
580 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
581
582 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
583 if (!sp)
584 goto done;
585 sp->type = SRB_MB_IOCB;
586 sp->name = "gnlist";
587 sp->gen1 = fcport->rscn_gen;
588 sp->gen2 = fcport->login_gen;
589
590 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha)+2);
591
592 mb = sp->u.iocb_cmd.u.mbx.out_mb;
593 mb[0] = MBC_PORT_NODE_NAME_LIST;
594 mb[1] = BIT_2 | BIT_3;
595 mb[2] = MSW(vha->gnl.ldma);
596 mb[3] = LSW(vha->gnl.ldma);
597 mb[6] = MSW(MSD(vha->gnl.ldma));
598 mb[7] = LSW(MSD(vha->gnl.ldma));
599 mb[8] = vha->gnl.size;
600 mb[9] = vha->vp_idx;
601
602 mbx = &sp->u.iocb_cmd;
603 mbx->timeout = qla2x00_async_iocb_timeout;
604
605 sp->done = qla24xx_async_gnl_sp_done;
606
607 rval = qla2x00_start_sp(sp);
608 if (rval != QLA_SUCCESS)
609 goto done_free_sp;
610
83548fe2
QT		 611 ql_dbg(ql_dbg_disc, vha, 0x20da,
612 "Async-%s - OUT WWPN %8phC hndl %x\n",
613 sp->name, fcport->port_name, sp->handle);
726b8548
QT		 614
615 return rval;
616
617done_free_sp:
25ff6af1 618 sp->free(sp);
726b8548
QT		 619done:
620 fcport->flags &= ~FCF_ASYNC_SENT;
621 return rval;
622}
623
624int qla24xx_post_gnl_work(struct scsi_qla_host *vha, fc_port_t *fcport)
625{
626 struct qla_work_evt *e;
627
628 e = qla2x00_alloc_work(vha, QLA_EVT_GNL);
629 if (!e)
630 return QLA_FUNCTION_FAILED;
631
632 e->u.fcport.fcport = fcport;
633 return qla2x00_post_work(vha, e);
634}
635
636static
25ff6af1 637void qla24xx_async_gpdb_sp_done(void *s, int res)
726b8548 638{
25ff6af1
JC		 639 struct srb *sp = s;
640 struct scsi_qla_host *vha = sp->vha;
726b8548 641 struct qla_hw_data *ha = vha->hw;
726b8548
QT		 642 struct port_database_24xx *pd;
643 fc_port_t *fcport = sp->fcport;
644 u16 *mb = sp->u.iocb_cmd.u.mbx.in_mb;
645 int rval = QLA_SUCCESS;
646 struct event_arg ea;
647
83548fe2 648 ql_dbg(ql_dbg_disc, vha, 0x20db,
726b8548
QT		 649 "Async done-%s res %x, WWPN %8phC mb[1]=%x mb[2]=%x \n",
650 sp->name, res, fcport->port_name, mb[1], mb[2]);
651
652 fcport->flags &= ~FCF_ASYNC_SENT;
653
654 if (res) {
655 rval = res;
656 goto gpd_error_out;
657 }
658
659 pd = (struct port_database_24xx *)sp->u.iocb_cmd.u.mbx.in;
660
15f30a57 661 rval = __qla24xx_parse_gpdb(vha, fcport, pd);
726b8548
QT		 662
663gpd_error_out:
664 memset(&ea, 0, sizeof(ea));
665 ea.event = FCME_GPDB_DONE;
666 ea.rc = rval;
667 ea.fcport = fcport;
668 ea.sp = sp;
669
670 qla2x00_fcport_event_handler(vha, &ea);
671
672 dma_pool_free(ha->s_dma_pool, sp->u.iocb_cmd.u.mbx.in,
673 sp->u.iocb_cmd.u.mbx.in_dma);
674
25ff6af1 675 sp->free(sp);
726b8548
QT		 676}
677
a5d42f4c
DG		 678static int qla24xx_post_prli_work(struct scsi_qla_host *vha, fc_port_t *fcport)
679{
680 struct qla_work_evt *e;
681
682 e = qla2x00_alloc_work(vha, QLA_EVT_PRLI);
683 if (!e)
684 return QLA_FUNCTION_FAILED;
685
686 e->u.fcport.fcport = fcport;
687
688 return qla2x00_post_work(vha, e);
689}
690
691static void
692qla2x00_async_prli_sp_done(void *ptr, int res)
693{
694 srb_t *sp = ptr;
695 struct scsi_qla_host *vha = sp->vha;
696 struct srb_iocb *lio = &sp->u.iocb_cmd;
697 struct event_arg ea;
698
699 ql_dbg(ql_dbg_disc, vha, 0x2129,
700 "%s %8phC res %d \n", __func__,
701 sp->fcport->port_name, res);
702
703 sp->fcport->flags &= ~FCF_ASYNC_SENT;
704
705 if (!test_bit(UNLOADING, &vha->dpc_flags)) {
706 memset(&ea, 0, sizeof(ea));
707 ea.event = FCME_PRLI_DONE;
708 ea.fcport = sp->fcport;
709 ea.data[0] = lio->u.logio.data[0];
710 ea.data[1] = lio->u.logio.data[1];
711 ea.iop[0] = lio->u.logio.iop[0];
712 ea.iop[1] = lio->u.logio.iop[1];
713 ea.sp = sp;
714
715 qla2x00_fcport_event_handler(vha, &ea);
716 }
717
718 sp->free(sp);
719}
720
721int
722qla24xx_async_prli(struct scsi_qla_host *vha, fc_port_t *fcport)
723{
724 srb_t *sp;
725 struct srb_iocb *lio;
726 int rval = QLA_FUNCTION_FAILED;
727
728 if (!vha->flags.online)
729 return rval;
730
731 if (fcport->fw_login_state == DSC_LS_PLOGI_PEND ||
732 fcport->fw_login_state == DSC_LS_PLOGI_COMP ||
733 fcport->fw_login_state == DSC_LS_PRLI_PEND)
734 return rval;
735
736 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
737 if (!sp)
738 return rval;
739
740 fcport->flags |= FCF_ASYNC_SENT;
741 fcport->logout_completed = 0;
742
743 sp->type = SRB_PRLI_CMD;
744 sp->name = "prli";
745 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
746
747 lio = &sp->u.iocb_cmd;
748 lio->timeout = qla2x00_async_iocb_timeout;
749 sp->done = qla2x00_async_prli_sp_done;
750 lio->u.logio.flags = 0;
751
752 if (fcport->fc4f_nvme)
753 lio->u.logio.flags |= SRB_LOGIN_NVME_PRLI;
754
755 rval = qla2x00_start_sp(sp);
756 if (rval != QLA_SUCCESS) {
757 fcport->flags &= ~FCF_ASYNC_SENT;
758 fcport->flags |= FCF_LOGIN_NEEDED;
759 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
760 goto done_free_sp;
761 }
762
763 ql_dbg(ql_dbg_disc, vha, 0x211b,
764 "Async-prli - %8phC hdl=%x, loopid=%x portid=%06x retries=%d.\n",
765 fcport->port_name, sp->handle, fcport->loop_id,
766 fcport->d_id.b24, fcport->login_retry);
767
768 return rval;
769
770done_free_sp:
771 sp->free(sp);
772 fcport->flags &= ~FCF_ASYNC_SENT;
773 return rval;
774}
775
a07fc0a4 776int qla24xx_post_gpdb_work(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt)
726b8548
QT		 777{
778 struct qla_work_evt *e;
779
780 e = qla2x00_alloc_work(vha, QLA_EVT_GPDB);
781 if (!e)
782 return QLA_FUNCTION_FAILED;
783
784 e->u.fcport.fcport = fcport;
785 e->u.fcport.opt = opt;
786 return qla2x00_post_work(vha, e);
787}
788
789int qla24xx_async_gpdb(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt)
790{
791 srb_t *sp;
792 struct srb_iocb *mbx;
793 int rval = QLA_FUNCTION_FAILED;
794 u16 *mb;
795 dma_addr_t pd_dma;
796 struct port_database_24xx *pd;
797 struct qla_hw_data *ha = vha->hw;
798
799 if (!vha->flags.online)
800 goto done;
801
802 fcport->flags |= FCF_ASYNC_SENT;
803 fcport->disc_state = DSC_GPDB;
804
805 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
806 if (!sp)
807 goto done;
808
e0824e69
JC		 809 sp->type = SRB_MB_IOCB;
810 sp->name = "gpdb";
811 sp->gen1 = fcport->rscn_gen;
812 sp->gen2 = fcport->login_gen;
813 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
814
726b8548
QT		 815 pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
816 if (pd == NULL) {
83548fe2
QT		 817 ql_log(ql_log_warn, vha, 0xd043,
818 "Failed to allocate port database structure.\n");
726b8548
QT		 819 goto done_free_sp;
820 }
821 memset(pd, 0, max(PORT_DATABASE_SIZE, PORT_DATABASE_24XX_SIZE));
822
726b8548
QT		 823 mb = sp->u.iocb_cmd.u.mbx.out_mb;
824 mb[0] = MBC_GET_PORT_DATABASE;
825 mb[1] = fcport->loop_id;
826 mb[2] = MSW(pd_dma);
827 mb[3] = LSW(pd_dma);
828 mb[6] = MSW(MSD(pd_dma));
829 mb[7] = LSW(MSD(pd_dma));
830 mb[9] = vha->vp_idx;
831 mb[10] = opt;
832
833 mbx = &sp->u.iocb_cmd;
834 mbx->timeout = qla2x00_async_iocb_timeout;
835 mbx->u.mbx.in = (void *)pd;
836 mbx->u.mbx.in_dma = pd_dma;
837
838 sp->done = qla24xx_async_gpdb_sp_done;
839
840 rval = qla2x00_start_sp(sp);
841 if (rval != QLA_SUCCESS)
842 goto done_free_sp;
843
83548fe2
QT		 844 ql_dbg(ql_dbg_disc, vha, 0x20dc,
845 "Async-%s %8phC hndl %x opt %x\n",
846 sp->name, fcport->port_name, sp->handle, opt);
726b8548
QT		 847
848 return rval;
849
850done_free_sp:
851 if (pd)
852 dma_pool_free(ha->s_dma_pool, pd, pd_dma);
853
25ff6af1 854 sp->free(sp);
726b8548
QT		 855done:
856 fcport->flags &= ~FCF_ASYNC_SENT;
857 qla24xx_post_gpdb_work(vha, fcport, opt);
5ff1d584
AV		 858 return rval;
859}
860
726b8548
QT		 861static
862void qla24xx_handle_gpdb_event(scsi_qla_host_t *vha, struct event_arg *ea)
863{
864 int rval = ea->rc;
865 fc_port_t *fcport = ea->fcport;
866 unsigned long flags;
867
868 fcport->flags &= ~FCF_ASYNC_SENT;
869
83548fe2 870 ql_dbg(ql_dbg_disc, vha, 0x20d2,
726b8548
QT		 871 "%s %8phC DS %d LS %d rval %d\n", __func__, fcport->port_name,
872 fcport->disc_state, fcport->fw_login_state, rval);
873
874 if (ea->sp->gen2 != fcport->login_gen) {
875 /* target side must have changed it. */
83548fe2 876 ql_dbg(ql_dbg_disc, vha, 0x20d3,
726b8548
QT		 877 "%s %8phC generation changed rscn %d|%d login %d|%d \n",
878 __func__, fcport->port_name, fcport->last_rscn_gen,
879 fcport->rscn_gen, fcport->last_login_gen,
880 fcport->login_gen);
881 return;
882 } else if (ea->sp->gen1 != fcport->rscn_gen) {
83548fe2 883 ql_dbg(ql_dbg_disc, vha, 0x20d4, "%s %d %8phC post gidpn\n",
726b8548
QT		 884 __func__, __LINE__, fcport->port_name);
885 qla24xx_post_gidpn_work(vha, fcport);
886 return;
887 }
888
889 if (rval != QLA_SUCCESS) {
83548fe2 890 ql_dbg(ql_dbg_disc, vha, 0x20d5, "%s %d %8phC post del sess\n",
726b8548
QT		 891 __func__, __LINE__, fcport->port_name);
892 qlt_schedule_sess_for_deletion_lock(fcport);
893 return;
894 }
895
896 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
897 ea->fcport->login_gen++;
898 ea->fcport->deleted = 0;
899 ea->fcport->logout_on_delete = 1;
900
901 if (!ea->fcport->login_succ && !IS_SW_RESV_ADDR(ea->fcport->d_id)) {
902 vha->fcport_count++;
903 ea->fcport->login_succ = 1;
904
905 if (!IS_IIDMA_CAPABLE(vha->hw) ||
906 !vha->hw->flags.gpsc_supported) {
83548fe2 907 ql_dbg(ql_dbg_disc, vha, 0x20d6,
726b8548
QT		 908 "%s %d %8phC post upd_fcport fcp_cnt %d\n",
909 __func__, __LINE__, fcport->port_name,
910 vha->fcport_count);
911
912 qla24xx_post_upd_fcport_work(vha, fcport);
913 } else {
83548fe2 914 ql_dbg(ql_dbg_disc, vha, 0x20d7,
726b8548
QT		 915 "%s %d %8phC post gpsc fcp_cnt %d\n",
916 __func__, __LINE__, fcport->port_name,
917 vha->fcport_count);
918
919 qla24xx_post_gpsc_work(vha, fcport);
920 }
921 }
922 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
923} /* gpdb event */
924
925int qla24xx_fcport_handle_login(struct scsi_qla_host *vha, fc_port_t *fcport)
926{
927 if (fcport->login_retry == 0)
928 return 0;
929
930 if (fcport->scan_state != QLA_FCPORT_FOUND)
931 return 0;
932
83548fe2 933 ql_dbg(ql_dbg_disc, vha, 0x20d8,
726b8548
QT		 934 "%s %8phC DS %d LS %d P %d fl %x confl %p rscn %d|%d login %d|%d retry %d lid %d\n",
935 __func__, fcport->port_name, fcport->disc_state,
936 fcport->fw_login_state, fcport->login_pause, fcport->flags,
937 fcport->conflict, fcport->last_rscn_gen, fcport->rscn_gen,
938 fcport->last_login_gen, fcport->login_gen, fcport->login_retry,
939 fcport->loop_id);
940
941 fcport->login_retry--;
942
943 if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) ||
726b8548
QT		 944 (fcport->fw_login_state == DSC_LS_PRLI_PEND))
945 return 0;
946
5b33469a
QT		 947 if (fcport->fw_login_state == DSC_LS_PLOGI_COMP) {
948 if (time_before_eq(jiffies, fcport->plogi_nack_done_deadline))
949 return 0;
950 }
951
726b8548
QT		 952 /* for pure Target Mode. Login will not be initiated */
953 if (vha->host->active_mode == MODE_TARGET)
954 return 0;
955
956 if (fcport->flags & FCF_ASYNC_SENT) {
957 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
958 return 0;
959 }
960
961 switch (fcport->disc_state) {
962 case DSC_DELETED:
963 if (fcport->loop_id == FC_NO_LOOP_ID) {
83548fe2
QT		 964 ql_dbg(ql_dbg_disc, vha, 0x20bd,
965 "%s %d %8phC post gnl\n",
966 __func__, __LINE__, fcport->port_name);
726b8548
QT		 967 qla24xx_async_gnl(vha, fcport);
968 } else {
83548fe2
QT		 969 ql_dbg(ql_dbg_disc, vha, 0x20bf,
970 "%s %d %8phC post login\n",
971 __func__, __LINE__, fcport->port_name);
726b8548
QT		 972 fcport->disc_state = DSC_LOGIN_PEND;
973 qla2x00_post_async_login_work(vha, fcport, NULL);
974 }
975 break;
976
977 case DSC_GNL:
978 if (fcport->login_pause) {
979 fcport->last_rscn_gen = fcport->rscn_gen;
980 fcport->last_login_gen = fcport->login_gen;
981 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
982 break;
983 }
984
985 if (fcport->flags & FCF_FCP2_DEVICE) {
986 u8 opt = PDO_FORCE_ADISC;
987
83548fe2
QT		 988 ql_dbg(ql_dbg_disc, vha, 0x20c9,
989 "%s %d %8phC post gpdb\n",
990 __func__, __LINE__, fcport->port_name);
726b8548
QT		 991
992 fcport->disc_state = DSC_GPDB;
993 qla24xx_post_gpdb_work(vha, fcport, opt);
994 } else {
83548fe2
QT		 995 ql_dbg(ql_dbg_disc, vha, 0x20cf,
996 "%s %d %8phC post login\n",
997 __func__, __LINE__, fcport->port_name);
726b8548
QT		 998 fcport->disc_state = DSC_LOGIN_PEND;
999 qla2x00_post_async_login_work(vha, fcport, NULL);
1000 }
1001
1002 break;
1003
1004 case DSC_LOGIN_FAILED:
83548fe2
QT		 1005 ql_dbg(ql_dbg_disc, vha, 0x20d0,
1006 "%s %d %8phC post gidpn\n",
1007 __func__, __LINE__, fcport->port_name);
726b8548
QT		 1008
1009 qla24xx_post_gidpn_work(vha, fcport);
1010 break;
1011
1012 case DSC_LOGIN_COMPLETE:
1013 /* recheck login state */
83548fe2
QT		 1014 ql_dbg(ql_dbg_disc, vha, 0x20d1,
1015 "%s %d %8phC post gpdb\n",
1016 __func__, __LINE__, fcport->port_name);
726b8548
QT		 1017
1018 qla24xx_post_gpdb_work(vha, fcport, PDO_FORCE_ADISC);
1019 break;
1020
1021 default:
1022 break;
1023 }
1024
1025 return 0;
1026}
1027
1028static
1029void qla24xx_handle_rscn_event(fc_port_t *fcport, struct event_arg *ea)
1030{
1031 fcport->rscn_gen++;
1032
83548fe2
QT		 1033 ql_dbg(ql_dbg_disc, fcport->vha, 0x210c,
1034 "%s %8phC DS %d LS %d\n",
1035 __func__, fcport->port_name, fcport->disc_state,
1036 fcport->fw_login_state);
726b8548
QT		 1037
1038 if (fcport->flags & FCF_ASYNC_SENT)
1039 return;
1040
1041 switch (fcport->disc_state) {
1042 case DSC_DELETED:
1043 case DSC_LOGIN_COMPLETE:
1044 qla24xx_post_gidpn_work(fcport->vha, fcport);
1045 break;
1046
1047 default:
1048 break;
1049 }
1050}
1051
1052int qla24xx_post_newsess_work(struct scsi_qla_host *vha, port_id_t *id,
1053 u8 *port_name, void *pla)
1054{
1055 struct qla_work_evt *e;
1056 e = qla2x00_alloc_work(vha, QLA_EVT_NEW_SESS);
1057 if (!e)
1058 return QLA_FUNCTION_FAILED;
1059
1060 e->u.new_sess.id = *id;
1061 e->u.new_sess.pla = pla;
1062 memcpy(e->u.new_sess.port_name, port_name, WWN_SIZE);
1063
1064 return qla2x00_post_work(vha, e);
1065}
1066
1067static
1068int qla24xx_handle_delete_done_event(scsi_qla_host_t *vha,
1069 struct event_arg *ea)
1070{
1071 fc_port_t *fcport = ea->fcport;
1072
1073 if (test_bit(UNLOADING, &vha->dpc_flags))
1074 return 0;
1075
1076 switch (vha->host->active_mode) {
1077 case MODE_INITIATOR:
1078 case MODE_DUAL:
1079 if (fcport->scan_state == QLA_FCPORT_FOUND)
1080 qla24xx_fcport_handle_login(vha, fcport);
1081 break;
1082
1083 case MODE_TARGET:
1084 default:
1085 /* no-op */
1086 break;
1087 }
1088
1089 return 0;
1090}
1091
1092static
1093void qla24xx_handle_relogin_event(scsi_qla_host_t *vha,
1094 struct event_arg *ea)
1095{
1096 fc_port_t *fcport = ea->fcport;
1097
1098 if (fcport->scan_state != QLA_FCPORT_FOUND) {
1099 fcport->login_retry++;
1100 return;
1101 }
1102
83548fe2
QT		 1103 ql_dbg(ql_dbg_disc, vha, 0x2102,
1104 "%s %8phC DS %d LS %d P %d del %d cnfl %p rscn %d|%d login %d|%d fl %x\n",
1105 __func__, fcport->port_name, fcport->disc_state,
1106 fcport->fw_login_state, fcport->login_pause,
1107 fcport->deleted, fcport->conflict,
1108 fcport->last_rscn_gen, fcport->rscn_gen,
1109 fcport->last_login_gen, fcport->login_gen,
1110 fcport->flags);
726b8548
QT		 1111
1112 if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) ||
726b8548
QT		 1113 (fcport->fw_login_state == DSC_LS_PRLI_PEND))
1114 return;
1115
5b33469a
QT		 1116 if (fcport->fw_login_state == DSC_LS_PLOGI_COMP) {
1117 if (time_before_eq(jiffies, fcport->plogi_nack_done_deadline))
1118 return;
1119 }
1120
726b8548
QT		 1121 if (fcport->flags & FCF_ASYNC_SENT) {
1122 fcport->login_retry++;
1123 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1124 return;
1125 }
1126
1127 if (fcport->disc_state == DSC_DELETE_PEND) {
1128 fcport->login_retry++;
1129 return;
1130 }
1131
1132 if (fcport->last_rscn_gen != fcport->rscn_gen) {
83548fe2 1133 ql_dbg(ql_dbg_disc, vha, 0x20e9, "%s %d %8phC post gidpn\n",
726b8548
QT		 1134 __func__, __LINE__, fcport->port_name);
1135
1136 qla24xx_async_gidpn(vha, fcport);
1137 return;
1138 }
1139
1140 qla24xx_fcport_handle_login(vha, fcport);
1141}
1142
41dc529a 1143void qla2x00_fcport_event_handler(scsi_qla_host_t *vha, struct event_arg *ea)
726b8548 1144{
41dc529a
QT		 1145 fc_port_t *fcport, *f, *tf;
1146 uint32_t id = 0, mask, rid;
726b8548
QT		 1147 int rc;
1148
b98ae0d7
QT		 1149 switch (ea->event) {
1150 case FCME_RELOGIN:
1151 case FCME_RSCN:
1152 case FCME_GIDPN_DONE:
1153 case FCME_GPSC_DONE:
1154 case FCME_GPNID_DONE:
1155 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
1156 test_bit(LOOP_RESYNC_ACTIVE, &vha->dpc_flags))
1157 return;
1158 break;
1159 default:
1160 break;
1161 }
1162
726b8548
QT		 1163 switch (ea->event) {
1164 case FCME_RELOGIN:
1165 if (test_bit(UNLOADING, &vha->dpc_flags))
1166 return;
5ff1d584 1167
726b8548
QT		 1168 qla24xx_handle_relogin_event(vha, ea);
1169 break;
1170 case FCME_RSCN:
1171 if (test_bit(UNLOADING, &vha->dpc_flags))
1172 return;
41dc529a
QT		 1173 switch (ea->id.b.rsvd_1) {
1174 case RSCN_PORT_ADDR:
1175 fcport = qla2x00_find_fcport_by_nportid(vha, &ea->id, 1);
1176 if (!fcport) {
1177 /* cable moved */
1178 rc = qla24xx_post_gpnid_work(vha, &ea->id);
1179 if (rc) {
83548fe2
QT		 1180 ql_log(ql_log_warn, vha, 0xd044,
1181 "RSCN GPNID work failed %02x%02x%02x\n",
1182 ea->id.b.domain, ea->id.b.area,
1183 ea->id.b.al_pa);
41dc529a
QT		 1184 }
1185 } else {
1186 ea->fcport = fcport;
1187 qla24xx_handle_rscn_event(fcport, ea);
1188 }
1189 break;
1190 case RSCN_AREA_ADDR:
1191 case RSCN_DOM_ADDR:
1192 if (ea->id.b.rsvd_1 == RSCN_AREA_ADDR) {
1193 mask = 0xffff00;
83548fe2
QT		 1194 ql_dbg(ql_dbg_async, vha, 0x5044,
1195 "RSCN: Area 0x%06x was affected\n",
1196 ea->id.b24);
41dc529a
QT		 1197 } else {
1198 mask = 0xff0000;
83548fe2
QT		 1199 ql_dbg(ql_dbg_async, vha, 0x507a,
1200 "RSCN: Domain 0x%06x was affected\n",
1201 ea->id.b24);
41dc529a 1202 }
726b8548 1203
41dc529a
QT		 1204 rid = ea->id.b24 & mask;
1205 list_for_each_entry_safe(f, tf, &vha->vp_fcports,
1206 list) {
1207 id = f->d_id.b24 & mask;
1208 if (rid == id) {
1209 ea->fcport = f;
1210 qla24xx_handle_rscn_event(f, ea);
1211 }
726b8548 1212 }
41dc529a
QT		 1213 break;
1214 case RSCN_FAB_ADDR:
1215 default:
83548fe2
QT		 1216 ql_log(ql_log_warn, vha, 0xd045,
1217 "RSCN: Fabric was affected. Addr format %d\n",
1218 ea->id.b.rsvd_1);
41dc529a
QT		 1219 qla2x00_mark_all_devices_lost(vha, 1);
1220 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1221 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
726b8548
QT		 1222 }
1223 break;
1224 case FCME_GIDPN_DONE:
1225 qla24xx_handle_gidpn_event(vha, ea);
1226 break;
1227 case FCME_GNL_DONE:
1228 qla24xx_handle_gnl_done_event(vha, ea);
1229 break;
1230 case FCME_GPSC_DONE:
1231 qla24xx_post_upd_fcport_work(vha, ea->fcport);
1232 break;
1233 case FCME_PLOGI_DONE: /* Initiator side sent LLIOCB */
1234 qla24xx_handle_plogi_done_event(vha, ea);
1235 break;
a5d42f4c
DG		 1236 case FCME_PRLI_DONE:
1237 qla24xx_handle_prli_done_event(vha, ea);
1238 break;
726b8548
QT		 1239 case FCME_GPDB_DONE:
1240 qla24xx_handle_gpdb_event(vha, ea);
1241 break;
1242 case FCME_GPNID_DONE:
1243 qla24xx_handle_gpnid_event(vha, ea);
1244 break;
d3bae931
DG		 1245 case FCME_GFFID_DONE:
1246 qla24xx_handle_gffid_event(vha, ea);
1247 break;
726b8548
QT		 1248 case FCME_DELETE_DONE:
1249 qla24xx_handle_delete_done_event(vha, ea);
1250 break;
1251 default:
1252 BUG_ON(1);
1253 break;
1254 }
5ff1d584
AV		 1255}
1256
3822263e 1257static void
faef62d1 1258qla2x00_tmf_iocb_timeout(void *data)
3822263e 1259{
25ff6af1 1260 srb_t *sp = data;
faef62d1 1261 struct srb_iocb *tmf = &sp->u.iocb_cmd;
3822263e 1262
faef62d1
AB		 1263 tmf->u.tmf.comp_status = CS_TIMEOUT;
1264 complete(&tmf->u.tmf.comp);
1265}
9ba56b95 1266
faef62d1 1267static void
25ff6af1 1268qla2x00_tmf_sp_done(void *ptr, int res)
faef62d1 1269{
25ff6af1 1270 srb_t *sp = ptr;
faef62d1 1271 struct srb_iocb *tmf = &sp->u.iocb_cmd;
25ff6af1 1272
faef62d1 1273 complete(&tmf->u.tmf.comp);
3822263e
MI		 1274}
1275
1276int
faef62d1 1277qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t flags, uint32_t lun,
3822263e
MI		 1278 uint32_t tag)
1279{
1280 struct scsi_qla_host *vha = fcport->vha;
faef62d1 1281 struct srb_iocb *tm_iocb;
3822263e 1282 srb_t *sp;
faef62d1 1283 int rval = QLA_FUNCTION_FAILED;
3822263e 1284
9ba56b95 1285 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
3822263e
MI		 1286 if (!sp)
1287 goto done;
1288
faef62d1 1289 tm_iocb = &sp->u.iocb_cmd;
9ba56b95
GM		 1290 sp->type = SRB_TM_CMD;
1291 sp->name = "tmf";
faef62d1
AB		 1292 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
1293 tm_iocb->u.tmf.flags = flags;
1294 tm_iocb->u.tmf.lun = lun;
1295 tm_iocb->u.tmf.data = tag;
1296 sp->done = qla2x00_tmf_sp_done;
1297 tm_iocb->timeout = qla2x00_tmf_iocb_timeout;
1298 init_completion(&tm_iocb->u.tmf.comp);
3822263e
MI		 1299
1300 rval = qla2x00_start_sp(sp);
1301 if (rval != QLA_SUCCESS)
1302 goto done_free_sp;
1303
7c3df132 1304 ql_dbg(ql_dbg_taskm, vha, 0x802f,
cfb0919c
CD		 1305 "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
1306 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
1307 fcport->d_id.b.area, fcport->d_id.b.al_pa);
faef62d1
AB		 1308
1309 wait_for_completion(&tm_iocb->u.tmf.comp);
1310
1311 rval = tm_iocb->u.tmf.comp_status == CS_COMPLETE ?
1312 QLA_SUCCESS : QLA_FUNCTION_FAILED;
1313
1314 if ((rval != QLA_SUCCESS) || tm_iocb->u.tmf.data) {
1315 ql_dbg(ql_dbg_taskm, vha, 0x8030,
1316 "TM IOCB failed (%x).\n", rval);
1317 }
1318
1319 if (!test_bit(UNLOADING, &vha->dpc_flags) && !IS_QLAFX00(vha->hw)) {
1320 flags = tm_iocb->u.tmf.flags;
1321 lun = (uint16_t)tm_iocb->u.tmf.lun;
1322
1323 /* Issue Marker IOCB */
1324 qla2x00_marker(vha, vha->hw->req_q_map[0],
1325 vha->hw->rsp_q_map[0], sp->fcport->loop_id, lun,
1326 flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
1327 }
3822263e
MI		 1328
1329done_free_sp:
25ff6af1 1330 sp->free(sp);
3822263e
MI		 1331done:
1332 return rval;
1333}
1334
4440e46d
AB		 1335static void
1336qla24xx_abort_iocb_timeout(void *data)
1337{
25ff6af1 1338 srb_t *sp = data;
4440e46d
AB		 1339 struct srb_iocb *abt = &sp->u.iocb_cmd;
1340
1341 abt->u.abt.comp_status = CS_TIMEOUT;
1342 complete(&abt->u.abt.comp);
1343}
1344
1345static void
25ff6af1 1346qla24xx_abort_sp_done(void *ptr, int res)
4440e46d 1347{
25ff6af1 1348 srb_t *sp = ptr;
4440e46d
AB		 1349 struct srb_iocb *abt = &sp->u.iocb_cmd;
1350
1351 complete(&abt->u.abt.comp);
1352}
1353
15f30a57 1354int
4440e46d
AB		 1355qla24xx_async_abort_cmd(srb_t *cmd_sp)
1356{
25ff6af1 1357 scsi_qla_host_t *vha = cmd_sp->vha;
4440e46d
AB		 1358 fc_port_t *fcport = cmd_sp->fcport;
1359 struct srb_iocb *abt_iocb;
1360 srb_t *sp;
1361 int rval = QLA_FUNCTION_FAILED;
1362
1363 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
1364 if (!sp)
1365 goto done;
1366
1367 abt_iocb = &sp->u.iocb_cmd;
1368 sp->type = SRB_ABT_CMD;
1369 sp->name = "abort";
1370 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
1371 abt_iocb->u.abt.cmd_hndl = cmd_sp->handle;
1372 sp->done = qla24xx_abort_sp_done;
1373 abt_iocb->timeout = qla24xx_abort_iocb_timeout;
1374 init_completion(&abt_iocb->u.abt.comp);
1375
1376 rval = qla2x00_start_sp(sp);
1377 if (rval != QLA_SUCCESS)
1378 goto done_free_sp;
1379
1380 ql_dbg(ql_dbg_async, vha, 0x507c,
1381 "Abort command issued - hdl=%x, target_id=%x\n",
1382 cmd_sp->handle, fcport->tgt_id);
1383
1384 wait_for_completion(&abt_iocb->u.abt.comp);
1385
1386 rval = abt_iocb->u.abt.comp_status == CS_COMPLETE ?
1387 QLA_SUCCESS : QLA_FUNCTION_FAILED;
1388
1389done_free_sp:
25ff6af1 1390 sp->free(sp);
4440e46d
AB		 1391done:
1392 return rval;
1393}
1394
1395int
1396qla24xx_async_abort_command(srb_t *sp)
1397{
1398 unsigned long flags = 0;
1399
1400 uint32_t handle;
1401 fc_port_t *fcport = sp->fcport;
1402 struct scsi_qla_host *vha = fcport->vha;
1403 struct qla_hw_data *ha = vha->hw;
1404 struct req_que *req = vha->req;
1405
1406 spin_lock_irqsave(&ha->hardware_lock, flags);
1407 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
1408 if (req->outstanding_cmds[handle] == sp)
1409 break;
1410 }
1411 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1412 if (handle == req->num_outstanding_cmds) {
1413 /* Command not found. */
1414 return QLA_FUNCTION_FAILED;
1415 }
1416 if (sp->type == SRB_FXIOCB_DCMD)
1417 return qlafx00_fx_disc(vha, &vha->hw->mr.fcport,
1418 FXDISC_ABORT_IOCTL);
1419
1420 return qla24xx_async_abort_cmd(sp);
1421}
1422
a5d42f4c
DG		 1423static void
1424qla24xx_handle_prli_done_event(struct scsi_qla_host *vha, struct event_arg *ea)
1425{
1426 switch (ea->data[0]) {
1427 case MBS_COMMAND_COMPLETE:
1428 ql_dbg(ql_dbg_disc, vha, 0x2118,
1429 "%s %d %8phC post gpdb\n",
1430 __func__, __LINE__, ea->fcport->port_name);
1431
1432 ea->fcport->chip_reset = vha->hw->base_qpair->chip_reset;
1433 ea->fcport->logout_on_delete = 1;
1434 qla24xx_post_gpdb_work(vha, ea->fcport, 0);
1435 break;
1436 default:
1437 ql_dbg(ql_dbg_disc, vha, 0x2119,
1438 "%s %d %8phC unhandle event of %x\n",
1439 __func__, __LINE__, ea->fcport->port_name, ea->data[0]);
1440 break;
1441 }
1442}
1443
726b8548
QT		 1444static void
1445qla24xx_handle_plogi_done_event(struct scsi_qla_host *vha, struct event_arg *ea)
ac280b67 1446{
726b8548 1447 port_id_t cid; /* conflict Nport id */
ac280b67 1448
726b8548 1449 switch (ea->data[0]) {
ac280b67 1450 case MBS_COMMAND_COMPLETE:
a4f92a32
AV		 1451 /*
1452 * Driver must validate login state - If PRLI not complete,
1453 * force a relogin attempt via implicit LOGO, PLOGI, and PRLI
1454 * requests.
1455 */
a5d42f4c
DG		 1456 if (ea->fcport->fc4f_nvme) {
1457 ql_dbg(ql_dbg_disc, vha, 0x2117,
1458 "%s %d %8phC post prli\n",
1459 __func__, __LINE__, ea->fcport->port_name);
1460 qla24xx_post_prli_work(vha, ea->fcport);
1461 } else {
1462 ql_dbg(ql_dbg_disc, vha, 0x20ea,
1463 "%s %d %8phC post gpdb\n",
1464 __func__, __LINE__, ea->fcport->port_name);
1465 ea->fcport->chip_reset = vha->hw->base_qpair->chip_reset;
1466 ea->fcport->logout_on_delete = 1;
1467 qla24xx_post_gpdb_work(vha, ea->fcport, 0);
1468 }
ac280b67
AV		 1469 break;
1470 case MBS_COMMAND_ERROR:
83548fe2 1471 ql_dbg(ql_dbg_disc, vha, 0x20eb, "%s %d %8phC cmd error %x\n",
726b8548
QT		 1472 __func__, __LINE__, ea->fcport->port_name, ea->data[1]);
1473
1474 ea->fcport->flags &= ~FCF_ASYNC_SENT;
1475 ea->fcport->disc_state = DSC_LOGIN_FAILED;
1476 if (ea->data[1] & QLA_LOGIO_LOGIN_RETRIED)
ac280b67
AV		 1477 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1478 else
726b8548 1479 qla2x00_mark_device_lost(vha, ea->fcport, 1, 0);
ac280b67
AV		 1480 break;
1481 case MBS_LOOP_ID_USED:
726b8548
QT		 1482 /* data[1] = IO PARAM 1 = nport ID */
1483 cid.b.domain = (ea->iop[1] >> 16) & 0xff;
1484 cid.b.area = (ea->iop[1] >> 8) & 0xff;
1485 cid.b.al_pa = ea->iop[1] & 0xff;
1486 cid.b.rsvd_1 = 0;
1487
83548fe2
QT		 1488 ql_dbg(ql_dbg_disc, vha, 0x20ec,
1489 "%s %d %8phC LoopID 0x%x in use post gnl\n",
1490 __func__, __LINE__, ea->fcport->port_name,
1491 ea->fcport->loop_id);
726b8548
QT		 1492
1493 if (IS_SW_RESV_ADDR(cid)) {
1494 set_bit(ea->fcport->loop_id, vha->hw->loop_id_map);
1495 ea->fcport->loop_id = FC_NO_LOOP_ID;
1496 } else {
1497 qla2x00_clear_loop_id(ea->fcport);
ac280b67 1498 }
726b8548
QT		 1499 qla24xx_post_gnl_work(vha, ea->fcport);
1500 break;
1501 case MBS_PORT_ID_USED:
83548fe2
QT		 1502 ql_dbg(ql_dbg_disc, vha, 0x20ed,
1503 "%s %d %8phC NPortId %02x%02x%02x inuse post gidpn\n",
1504 __func__, __LINE__, ea->fcport->port_name,
1505 ea->fcport->d_id.b.domain, ea->fcport->d_id.b.area,
1506 ea->fcport->d_id.b.al_pa);
726b8548
QT		 1507
1508 qla2x00_clear_loop_id(ea->fcport);
1509 qla24xx_post_gidpn_work(vha, ea->fcport);
ac280b67
AV		 1510 break;
1511 }
4916392b 1512 return;
ac280b67
AV		 1513}
1514
4916392b 1515void
ac280b67
AV		 1516qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport,
1517 uint16_t *data)
1518{
726b8548 1519 qla2x00_mark_device_lost(vha, fcport, 1, 0);
a6ca8878 1520 qlt_logo_completion_handler(fcport, data[0]);
726b8548 1521 fcport->login_gen++;
4916392b 1522 return;
ac280b67
AV		 1523}
1524
4916392b 1525void
5ff1d584
AV		 1526qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport,
1527 uint16_t *data)
1528{
1529 if (data[0] == MBS_COMMAND_COMPLETE) {
1530 qla2x00_update_fcport(vha, fcport);
1531
4916392b 1532 return;
5ff1d584
AV		 1533 }
1534
1535 /* Retry login. */
1536 fcport->flags &= ~FCF_ASYNC_SENT;
1537 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
1538 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1539 else
80d79440 1540 qla2x00_mark_device_lost(vha, fcport, 1, 0);
5ff1d584 1541
4916392b 1542 return;
5ff1d584
AV		 1543}
1544
1da177e4
LT		 1545/****************************************************************************/
1546/* QLogic ISP2x00 Hardware Support Functions. */
1547/****************************************************************************/
1548
fa492630 1549static int
7d613ac6
SV		 1550qla83xx_nic_core_fw_load(scsi_qla_host_t *vha)
1551{
1552 int rval = QLA_SUCCESS;
1553 struct qla_hw_data *ha = vha->hw;
1554 uint32_t idc_major_ver, idc_minor_ver;
711aa7f7 1555 uint16_t config[4];
7d613ac6
SV		 1556
1557 qla83xx_idc_lock(vha, 0);
1558
1559 /* SV: TODO: Assign initialization timeout from
1560 * flash-info / other param
1561 */
1562 ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT;
1563 ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT;
1564
1565 /* Set our fcoe function presence */
1566 if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) {
1567 ql_dbg(ql_dbg_p3p, vha, 0xb077,
1568 "Error while setting DRV-Presence.\n");
1569 rval = QLA_FUNCTION_FAILED;
1570 goto exit;
1571 }
1572
1573 /* Decide the reset ownership */
1574 qla83xx_reset_ownership(vha);
1575
1576 /*
1577 * On first protocol driver load:
1578 * Init-Owner: Set IDC-Major-Version and Clear IDC-Lock-Recovery
1579 * register.
1580 * Others: Check compatibility with current IDC Major version.
1581 */
1582 qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver);
1583 if (ha->flags.nic_core_reset_owner) {
1584 /* Set IDC Major version */
1585 idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION;
1586 qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver);
1587
1588 /* Clearing IDC-Lock-Recovery register */
1589 qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0);
1590 } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) {
1591 /*
1592 * Clear further IDC participation if we are not compatible with
1593 * the current IDC Major Version.
1594 */
1595 ql_log(ql_log_warn, vha, 0xb07d,
1596 "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n",
1597 idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION);
1598 __qla83xx_clear_drv_presence(vha);
1599 rval = QLA_FUNCTION_FAILED;
1600 goto exit;
1601 }
1602 /* Each function sets its supported Minor version. */
1603 qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver);
1604 idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2));
1605 qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver);
1606
711aa7f7
SK		 1607 if (ha->flags.nic_core_reset_owner) {
1608 memset(config, 0, sizeof(config));
1609 if (!qla81xx_get_port_config(vha, config))
1610 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
1611 QLA8XXX_DEV_READY);
1612 }
1613
7d613ac6
SV		 1614 rval = qla83xx_idc_state_handler(vha);
1615
1616exit:
1617 qla83xx_idc_unlock(vha, 0);
1618
1619 return rval;
1620}
1621
1da177e4
LT		 1622/*
1623* qla2x00_initialize_adapter
1624* Initialize board.
1625*
1626* Input:
1627* ha = adapter block pointer.
1628*
1629* Returns:
1630* 0 = success
1631*/
1632int
e315cd28 1633qla2x00_initialize_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 1634{
1635 int rval;
e315cd28 1636 struct qla_hw_data *ha = vha->hw;
73208dfd 1637 struct req_que *req = ha->req_q_map[0];
2533cf67 1638
fc90adaf
JC		 1639 memset(&vha->qla_stats, 0, sizeof(vha->qla_stats));
1640 memset(&vha->fc_host_stat, 0, sizeof(vha->fc_host_stat));
1641
1da177e4 1642 /* Clear adapter flags. */
e315cd28 1643 vha->flags.online = 0;
2533cf67 1644 ha->flags.chip_reset_done = 0;
e315cd28 1645 vha->flags.reset_active = 0;
85880801
AV		 1646 ha->flags.pci_channel_io_perm_failure = 0;
1647 ha->flags.eeh_busy = 0;
fabbb8df 1648 vha->qla_stats.jiffies_at_last_reset = get_jiffies_64();
e315cd28
AC		 1649 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1650 atomic_set(&vha->loop_state, LOOP_DOWN);
1651 vha->device_flags = DFLG_NO_CABLE;
1652 vha->dpc_flags = 0;
1653 vha->flags.management_server_logged_in = 0;
1654 vha->marker_needed = 0;
1da177e4
LT		 1655 ha->isp_abort_cnt = 0;
1656 ha->beacon_blink_led = 0;
1657
73208dfd
AC		 1658 set_bit(0, ha->req_qid_map);
1659 set_bit(0, ha->rsp_qid_map);
1660
cfb0919c 1661 ql_dbg(ql_dbg_init, vha, 0x0040,
7c3df132 1662 "Configuring PCI space...\n");
e315cd28 1663 rval = ha->isp_ops->pci_config(vha);
1da177e4 1664 if (rval) {
7c3df132
SK		 1665 ql_log(ql_log_warn, vha, 0x0044,
1666 "Unable to configure PCI space.\n");
1da177e4
LT		 1667 return (rval);
1668 }
1669
e315cd28 1670 ha->isp_ops->reset_chip(vha);
1da177e4 1671
e315cd28 1672 rval = qla2xxx_get_flash_info(vha);
c00d8994 1673 if (rval) {
7c3df132
SK		 1674 ql_log(ql_log_fatal, vha, 0x004f,
1675 "Unable to validate FLASH data.\n");
7ec0effd
AD		 1676 return rval;
1677 }
1678
1679 if (IS_QLA8044(ha)) {
1680 qla8044_read_reset_template(vha);
1681
1682 /* NOTE: If ql2xdontresethba==1, set IDC_CTRL DONTRESET_BIT0.
1683 * If DONRESET_BIT0 is set, drivers should not set dev_state
1684 * to NEED_RESET. But if NEED_RESET is set, drivers should
1685 * should honor the reset. */
1686 if (ql2xdontresethba == 1)
1687 qla8044_set_idc_dontreset(vha);
c00d8994
AV		 1688 }
1689
73208dfd 1690 ha->isp_ops->get_flash_version(vha, req->ring);
cfb0919c 1691 ql_dbg(ql_dbg_init, vha, 0x0061,
7c3df132 1692 "Configure NVRAM parameters...\n");
0107109e 1693
e315cd28 1694 ha->isp_ops->nvram_config(vha);
1da177e4 1695
d4c760c2
AV		 1696 if (ha->flags.disable_serdes) {
1697 /* Mask HBA via NVRAM settings? */
7c3df132 1698 ql_log(ql_log_info, vha, 0x0077,
7b833558 1699 "Masking HBA WWPN %8phN (via NVRAM).\n", vha->port_name);
d4c760c2
AV		 1700 return QLA_FUNCTION_FAILED;
1701 }
1702
cfb0919c 1703 ql_dbg(ql_dbg_init, vha, 0x0078,
7c3df132 1704 "Verifying loaded RISC code...\n");
1da177e4 1705
e315cd28
AC		 1706 if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) {
1707 rval = ha->isp_ops->chip_diag(vha);
d19044c3
AV		 1708 if (rval)
1709 return (rval);
e315cd28 1710 rval = qla2x00_setup_chip(vha);
d19044c3
AV		 1711 if (rval)
1712 return (rval);
1da177e4 1713 }
a9083016 1714
4d4df193 1715 if (IS_QLA84XX(ha)) {
e315cd28 1716 ha->cs84xx = qla84xx_get_chip(vha);
4d4df193 1717 if (!ha->cs84xx) {
7c3df132 1718 ql_log(ql_log_warn, vha, 0x00d0,
4d4df193
HK		 1719 "Unable to configure ISP84XX.\n");
1720 return QLA_FUNCTION_FAILED;
1721 }
1722 }
2d70c103 1723
ead03855 1724 if (qla_ini_mode_enabled(vha) || qla_dual_mode_enabled(vha))
2d70c103
NB		 1725 rval = qla2x00_init_rings(vha);
1726
2533cf67 1727 ha->flags.chip_reset_done = 1;
1da177e4 1728
9a069e19 1729 if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) {
6c452a45 1730 /* Issue verify 84xx FW IOCB to complete 84xx initialization */
9a069e19
GM		 1731 rval = qla84xx_init_chip(vha);
1732 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1733 ql_log(ql_log_warn, vha, 0x00d4,
1734 "Unable to initialize ISP84XX.\n");
8d2b21db 1735 qla84xx_put_chip(vha);
9a069e19
GM		 1736 }
1737 }
1738
7d613ac6
SV		 1739 /* Load the NIC Core f/w if we are the first protocol driver. */
1740 if (IS_QLA8031(ha)) {
1741 rval = qla83xx_nic_core_fw_load(vha);
1742 if (rval)
1743 ql_log(ql_log_warn, vha, 0x0124,
1744 "Error in initializing NIC Core f/w.\n");
1745 }
1746
2f0f3f4f
MI		 1747 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
1748 qla24xx_read_fcp_prio_cfg(vha);
09ff701a 1749
c46e65c7
JC		 1750 if (IS_P3P_TYPE(ha))
1751 qla82xx_set_driver_version(vha, QLA2XXX_VERSION);
1752 else
1753 qla25xx_set_driver_version(vha, QLA2XXX_VERSION);
1754
1da177e4
LT		 1755 return (rval);
1756}
1757
1758/**
abbd8870 1759 * qla2100_pci_config() - Setup ISP21xx PCI configuration registers.
1da177e4
LT		 1760 * @ha: HA context
1761 *
1762 * Returns 0 on success.
1763 */
abbd8870 1764int
e315cd28 1765qla2100_pci_config(scsi_qla_host_t *vha)
1da177e4 1766{
a157b101 1767 uint16_t w;
abbd8870 1768 unsigned long flags;
e315cd28 1769 struct qla_hw_data *ha = vha->hw;
3d71644c 1770 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 1771
1da177e4 1772 pci_set_master(ha->pdev);
af6177d8 1773 pci_try_set_mwi(ha->pdev);
1da177e4 1774
1da177e4 1775 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 1776 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
abbd8870
AV		 1777 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1778
737faece 1779 pci_disable_rom(ha->pdev);
1da177e4
LT		 1780
1781 /* Get PCI bus information. */
1782 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 1783 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
1da177e4
LT		 1784 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1785
abbd8870
AV		 1786 return QLA_SUCCESS;
1787}
1da177e4 1788
abbd8870
AV		 1789/**
1790 * qla2300_pci_config() - Setup ISP23xx PCI configuration registers.
1791 * @ha: HA context
1792 *
1793 * Returns 0 on success.
1794 */
1795int
e315cd28 1796qla2300_pci_config(scsi_qla_host_t *vha)
abbd8870 1797{
a157b101 1798 uint16_t w;
abbd8870
AV		 1799 unsigned long flags = 0;
1800 uint32_t cnt;
e315cd28 1801 struct qla_hw_data *ha = vha->hw;
3d71644c 1802 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 1803
abbd8870 1804 pci_set_master(ha->pdev);
af6177d8 1805 pci_try_set_mwi(ha->pdev);
1da177e4 1806
abbd8870 1807 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 1808 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
1da177e4 1809
abbd8870
AV		 1810 if (IS_QLA2322(ha) || IS_QLA6322(ha))
1811 w &= ~PCI_COMMAND_INTX_DISABLE;
a157b101 1812 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1da177e4 1813
abbd8870
AV		 1814 /*
1815 * If this is a 2300 card and not 2312, reset the
1816 * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately,
1817 * the 2310 also reports itself as a 2300 so we need to get the
1818 * fb revision level -- a 6 indicates it really is a 2300 and
1819 * not a 2310.
1820 */
1821 if (IS_QLA2300(ha)) {
1822 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1823
abbd8870 1824 /* Pause RISC. */
3d71644c 1825 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
abbd8870 1826 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 1827 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
abbd8870 1828 break;
1da177e4 1829
abbd8870
AV		 1830 udelay(10);
1831 }
1da177e4 1832
abbd8870 1833 /* Select FPM registers. */
3d71644c
AV		 1834 WRT_REG_WORD(&reg->ctrl_status, 0x20);
1835 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 1836
1837 /* Get the fb rev level */
3d71644c 1838 ha->fb_rev = RD_FB_CMD_REG(ha, reg);
abbd8870
AV		 1839
1840 if (ha->fb_rev == FPM_2300)
a157b101 1841 pci_clear_mwi(ha->pdev);
abbd8870
AV		 1842
1843 /* Deselect FPM registers. */
3d71644c
AV		 1844 WRT_REG_WORD(&reg->ctrl_status, 0x0);
1845 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 1846
1847 /* Release RISC module. */
3d71644c 1848 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
abbd8870 1849 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 1850 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0)
abbd8870
AV		 1851 break;
1852
1853 udelay(10);
1da177e4 1854 }
1da177e4 1855
abbd8870
AV		 1856 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1857 }
1da177e4 1858
abbd8870
AV		 1859 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
1860
737faece 1861 pci_disable_rom(ha->pdev);
1da177e4 1862
abbd8870
AV		 1863 /* Get PCI bus information. */
1864 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 1865 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 1866 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1867
1868 return QLA_SUCCESS;
1da177e4
LT		 1869}
1870
0107109e
AV		 1871/**
1872 * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers.
1873 * @ha: HA context
1874 *
1875 * Returns 0 on success.
1876 */
1877int
e315cd28 1878qla24xx_pci_config(scsi_qla_host_t *vha)
0107109e 1879{
a157b101 1880 uint16_t w;
0107109e 1881 unsigned long flags = 0;
e315cd28 1882 struct qla_hw_data *ha = vha->hw;
0107109e 1883 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
0107109e
AV		 1884
1885 pci_set_master(ha->pdev);
af6177d8 1886 pci_try_set_mwi(ha->pdev);
0107109e
AV		 1887
1888 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 1889 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
0107109e
AV		 1890 w &= ~PCI_COMMAND_INTX_DISABLE;
1891 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1892
1893 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
1894
1895 /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */
f85ec187
AV		 1896 if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
1897 pcix_set_mmrbc(ha->pdev, 2048);
0107109e
AV		 1898
1899 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 1900 if (pci_is_pcie(ha->pdev))
5ffd3a52 1901 pcie_set_readrq(ha->pdev, 4096);
0107109e 1902
737faece 1903 pci_disable_rom(ha->pdev);
0107109e 1904
44c10138 1905 ha->chip_revision = ha->pdev->revision;
a8488abe 1906
0107109e
AV		 1907 /* Get PCI bus information. */
1908 spin_lock_irqsave(&ha->hardware_lock, flags);
1909 ha->pci_attr = RD_REG_DWORD(&reg->ctrl_status);
1910 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1911
1912 return QLA_SUCCESS;
1913}
1914
c3a2f0df
AV		 1915/**
1916 * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers.
1917 * @ha: HA context
1918 *
1919 * Returns 0 on success.
1920 */
1921int
e315cd28 1922qla25xx_pci_config(scsi_qla_host_t *vha)
c3a2f0df
AV		 1923{
1924 uint16_t w;
e315cd28 1925 struct qla_hw_data *ha = vha->hw;
c3a2f0df
AV		 1926
1927 pci_set_master(ha->pdev);
1928 pci_try_set_mwi(ha->pdev);
1929
1930 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
1931 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
1932 w &= ~PCI_COMMAND_INTX_DISABLE;
1933 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1934
1935 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 1936 if (pci_is_pcie(ha->pdev))
5ffd3a52 1937 pcie_set_readrq(ha->pdev, 4096);
c3a2f0df 1938
737faece 1939 pci_disable_rom(ha->pdev);
c3a2f0df
AV		 1940
1941 ha->chip_revision = ha->pdev->revision;
1942
1943 return QLA_SUCCESS;
1944}
1945
1da177e4
LT		 1946/**
1947 * qla2x00_isp_firmware() - Choose firmware image.
1948 * @ha: HA context
1949 *
1950 * Returns 0 on success.
1951 */
1952static int
e315cd28 1953qla2x00_isp_firmware(scsi_qla_host_t *vha)
1da177e4
LT		 1954{
1955 int rval;
42e421b1
AV		 1956 uint16_t loop_id, topo, sw_cap;
1957 uint8_t domain, area, al_pa;
e315cd28 1958 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 1959
1960 /* Assume loading risc code */
fa2a1ce5 1961 rval = QLA_FUNCTION_FAILED;
1da177e4
LT		 1962
1963 if (ha->flags.disable_risc_code_load) {
7c3df132 1964 ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n");
1da177e4
LT		 1965
1966 /* Verify checksum of loaded RISC code. */
e315cd28 1967 rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address);
42e421b1
AV		 1968 if (rval == QLA_SUCCESS) {
1969 /* And, verify we are not in ROM code. */
e315cd28 1970 rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa,
42e421b1
AV		 1971 &area, &domain, &topo, &sw_cap);
1972 }
1da177e4
LT		 1973 }
1974
7c3df132
SK		 1975 if (rval)
1976 ql_dbg(ql_dbg_init, vha, 0x007a,
1977 "**** Load RISC code ****.\n");
1da177e4
LT		 1978
1979 return (rval);
1980}
1981
1982/**
1983 * qla2x00_reset_chip() - Reset ISP chip.
1984 * @ha: HA context
1985 *
1986 * Returns 0 on success.
1987 */
abbd8870 1988void
e315cd28 1989qla2x00_reset_chip(scsi_qla_host_t *vha)
1da177e4
LT		 1990{
1991 unsigned long flags = 0;
e315cd28 1992 struct qla_hw_data *ha = vha->hw;
3d71644c 1993 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 1994 uint32_t cnt;
1da177e4
LT		 1995 uint16_t cmd;
1996
85880801
AV		 1997 if (unlikely(pci_channel_offline(ha->pdev)))
1998 return;
1999
fd34f556 2000 ha->isp_ops->disable_intrs(ha);
1da177e4
LT		 2001
2002 spin_lock_irqsave(&ha->hardware_lock, flags);
2003
2004 /* Turn off master enable */
2005 cmd = 0;
2006 pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd);
2007 cmd &= ~PCI_COMMAND_MASTER;
2008 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
2009
2010 if (!IS_QLA2100(ha)) {
2011 /* Pause RISC. */
2012 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
2013 if (IS_QLA2200(ha) || IS_QLA2300(ha)) {
2014 for (cnt = 0; cnt < 30000; cnt++) {
2015 if ((RD_REG_WORD(&reg->hccr) &
2016 HCCR_RISC_PAUSE) != 0)
2017 break;
2018 udelay(100);
2019 }
2020 } else {
2021 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
2022 udelay(10);
2023 }
2024
2025 /* Select FPM registers. */
2026 WRT_REG_WORD(&reg->ctrl_status, 0x20);
2027 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2028
2029 /* FPM Soft Reset. */
2030 WRT_REG_WORD(&reg->fpm_diag_config, 0x100);
2031 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
2032
2033 /* Toggle Fpm Reset. */
2034 if (!IS_QLA2200(ha)) {
2035 WRT_REG_WORD(&reg->fpm_diag_config, 0x0);
2036 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
2037 }
2038
2039 /* Select frame buffer registers. */
2040 WRT_REG_WORD(&reg->ctrl_status, 0x10);
2041 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2042
2043 /* Reset frame buffer FIFOs. */
2044 if (IS_QLA2200(ha)) {
2045 WRT_FB_CMD_REG(ha, reg, 0xa000);
2046 RD_FB_CMD_REG(ha, reg); /* PCI Posting. */
2047 } else {
2048 WRT_FB_CMD_REG(ha, reg, 0x00fc);
2049
2050 /* Read back fb_cmd until zero or 3 seconds max */
2051 for (cnt = 0; cnt < 3000; cnt++) {
2052 if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0)
2053 break;
2054 udelay(100);
2055 }
2056 }
2057
2058 /* Select RISC module registers. */
2059 WRT_REG_WORD(&reg->ctrl_status, 0);
2060 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2061
2062 /* Reset RISC processor. */
2063 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
2064 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
2065
2066 /* Release RISC processor. */
2067 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
2068 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
2069 }
2070
2071 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
2072 WRT_REG_WORD(&reg->hccr, HCCR_CLR_HOST_INT);
2073
2074 /* Reset ISP chip. */
2075 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
2076
2077 /* Wait for RISC to recover from reset. */
2078 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
2079 /*
2080 * It is necessary to for a delay here since the card doesn't
2081 * respond to PCI reads during a reset. On some architectures
2082 * this will result in an MCA.
2083 */
2084 udelay(20);
2085 for (cnt = 30000; cnt; cnt--) {
2086 if ((RD_REG_WORD(&reg->ctrl_status) &
2087 CSR_ISP_SOFT_RESET) == 0)
2088 break;
2089 udelay(100);
2090 }
2091 } else
2092 udelay(10);
2093
2094 /* Reset RISC processor. */
2095 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
2096
2097 WRT_REG_WORD(&reg->semaphore, 0);
2098
2099 /* Release RISC processor. */
2100 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
2101 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
2102
2103 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
2104 for (cnt = 0; cnt < 30000; cnt++) {
ffb39f03 2105 if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY)
1da177e4 2106 break;
1da177e4
LT		 2107
2108 udelay(100);
2109 }
2110 } else
2111 udelay(100);
2112
2113 /* Turn on master enable */
2114 cmd |= PCI_COMMAND_MASTER;
2115 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
2116
2117 /* Disable RISC pause on FPM parity error. */
2118 if (!IS_QLA2100(ha)) {
2119 WRT_REG_WORD(&reg->hccr, HCCR_DISABLE_PARITY_PAUSE);
2120 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
2121 }
2122
2123 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2124}
2125
b1d46989
MI		 2126/**
2127 * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC.
2128 *
2129 * Returns 0 on success.
2130 */
fa492630 2131static int
b1d46989
MI		 2132qla81xx_reset_mpi(scsi_qla_host_t *vha)
2133{
2134 uint16_t mb[4] = {0x1010, 0, 1, 0};
2135
6246b8a1
GM		 2136 if (!IS_QLA81XX(vha->hw))
2137 return QLA_SUCCESS;
2138
b1d46989
MI		 2139 return qla81xx_write_mpi_register(vha, mb);
2140}
2141
0107109e 2142/**
88c26663 2143 * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC.
0107109e
AV		 2144 * @ha: HA context
2145 *
2146 * Returns 0 on success.
2147 */
d14e72fb 2148static inline int
e315cd28 2149qla24xx_reset_risc(scsi_qla_host_t *vha)
0107109e
AV		 2150{
2151 unsigned long flags = 0;
e315cd28 2152 struct qla_hw_data *ha = vha->hw;
0107109e 2153 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
52c82823 2154 uint32_t cnt;
335a1cc9 2155 uint16_t wd;
b1d46989 2156 static int abts_cnt; /* ISP abort retry counts */
d14e72fb 2157 int rval = QLA_SUCCESS;
0107109e 2158
0107109e
AV		 2159 spin_lock_irqsave(&ha->hardware_lock, flags);
2160
2161 /* Reset RISC. */
2162 WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
2163 for (cnt = 0; cnt < 30000; cnt++) {
2164 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
2165 break;
2166
2167 udelay(10);
2168 }
2169
d14e72fb
HM		 2170 if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE))
2171 set_bit(DMA_SHUTDOWN_CMPL, &ha->fw_dump_cap_flags);
2172
2173 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017e,
2174 "HCCR: 0x%x, Control Status %x, DMA active status:0x%x\n",
2175 RD_REG_DWORD(&reg->hccr),
2176 RD_REG_DWORD(&reg->ctrl_status),
2177 (RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE));
2178
0107109e
AV		 2179 WRT_REG_DWORD(&reg->ctrl_status,
2180 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
335a1cc9 2181 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
88c26663 2182
335a1cc9 2183 udelay(100);
d14e72fb 2184
88c26663 2185 /* Wait for firmware to complete NVRAM accesses. */
52c82823 2186 RD_REG_WORD(&reg->mailbox0);
d14e72fb
HM		 2187 for (cnt = 10000; RD_REG_WORD(&reg->mailbox0) != 0 &&
2188 rval == QLA_SUCCESS; cnt--) {
88c26663 2189 barrier();
d14e72fb
HM		 2190 if (cnt)
2191 udelay(5);
2192 else
2193 rval = QLA_FUNCTION_TIMEOUT;
88c26663
AV		 2194 }
2195
d14e72fb
HM		 2196 if (rval == QLA_SUCCESS)
2197 set_bit(ISP_MBX_RDY, &ha->fw_dump_cap_flags);
2198
2199 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017f,
2200 "HCCR: 0x%x, MailBox0 Status 0x%x\n",
2201 RD_REG_DWORD(&reg->hccr),
2202 RD_REG_DWORD(&reg->mailbox0));
2203
335a1cc9 2204 /* Wait for soft-reset to complete. */
52c82823 2205 RD_REG_DWORD(&reg->ctrl_status);
200ffb15 2206 for (cnt = 0; cnt < 60; cnt++) {
0107109e 2207 barrier();
d14e72fb
HM		 2208 if ((RD_REG_DWORD(&reg->ctrl_status) &
2209 CSRX_ISP_SOFT_RESET) == 0)
2210 break;
2211
2212 udelay(5);
0107109e 2213 }
d14e72fb
HM		 2214 if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_ISP_SOFT_RESET))
2215 set_bit(ISP_SOFT_RESET_CMPL, &ha->fw_dump_cap_flags);
2216
2217 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015d,
2218 "HCCR: 0x%x, Soft Reset status: 0x%x\n",
2219 RD_REG_DWORD(&reg->hccr),
2220 RD_REG_DWORD(&reg->ctrl_status));
0107109e 2221
b1d46989
MI		 2222 /* If required, do an MPI FW reset now */
2223 if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
2224 if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
2225 if (++abts_cnt < 5) {
2226 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2227 set_bit(MPI_RESET_NEEDED, &vha->dpc_flags);
2228 } else {
2229 /*
2230 * We exhausted the ISP abort retries. We have to
2231 * set the board offline.
2232 */
2233 abts_cnt = 0;
2234 vha->flags.online = 0;
2235 }
2236 }
2237 }
2238
0107109e
AV		 2239 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
2240 RD_REG_DWORD(&reg->hccr);
2241
2242 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
2243 RD_REG_DWORD(&reg->hccr);
2244
2245 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
2246 RD_REG_DWORD(&reg->hccr);
2247
52c82823 2248 RD_REG_WORD(&reg->mailbox0);
200ffb15 2249 for (cnt = 60; RD_REG_WORD(&reg->mailbox0) != 0 &&
d14e72fb 2250 rval == QLA_SUCCESS; cnt--) {
0107109e 2251 barrier();
d14e72fb
HM		 2252 if (cnt)
2253 udelay(5);
2254 else
2255 rval = QLA_FUNCTION_TIMEOUT;
0107109e 2256 }
d14e72fb
HM		 2257 if (rval == QLA_SUCCESS)
2258 set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags);
2259
2260 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015e,
2261 "Host Risc 0x%x, mailbox0 0x%x\n",
2262 RD_REG_DWORD(&reg->hccr),
2263 RD_REG_WORD(&reg->mailbox0));
0107109e
AV		 2264
2265 spin_unlock_irqrestore(&ha->hardware_lock, flags);
124f85e6 2266
d14e72fb
HM		 2267 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015f,
2268 "Driver in %s mode\n",
2269 IS_NOPOLLING_TYPE(ha) ? "Interrupt" : "Polling");
2270
124f85e6
AV		 2271 if (IS_NOPOLLING_TYPE(ha))
2272 ha->isp_ops->enable_intrs(ha);
d14e72fb
HM		 2273
2274 return rval;
0107109e
AV		 2275}
2276
4ea2c9c7
JC		 2277static void
2278qla25xx_read_risc_sema_reg(scsi_qla_host_t *vha, uint32_t *data)
2279{
2280 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
2281
2282 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
2283 *data = RD_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET);
2284
2285}
2286
2287static void
2288qla25xx_write_risc_sema_reg(scsi_qla_host_t *vha, uint32_t data)
2289{
2290 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
2291
2292 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
2293 WRT_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET, data);
2294}
2295
2296static void
2297qla25xx_manipulate_risc_semaphore(scsi_qla_host_t *vha)
2298{
4ea2c9c7
JC		 2299 uint32_t wd32 = 0;
2300 uint delta_msec = 100;
2301 uint elapsed_msec = 0;
2302 uint timeout_msec;
2303 ulong n;
2304
cc790764
JC		 2305 if (vha->hw->pdev->subsystem_device != 0x0175 &&
2306 vha->hw->pdev->subsystem_device != 0x0240)
4ea2c9c7
JC		 2307 return;
2308
8dd7e3a5
JC		 2309 WRT_REG_DWORD(&vha->hw->iobase->isp24.hccr, HCCRX_SET_RISC_PAUSE);
2310 udelay(100);
2311
4ea2c9c7
JC		 2312attempt:
2313 timeout_msec = TIMEOUT_SEMAPHORE;
2314 n = timeout_msec / delta_msec;
2315 while (n--) {
2316 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_SET);
2317 qla25xx_read_risc_sema_reg(vha, &wd32);
2318 if (wd32 & RISC_SEMAPHORE)
2319 break;
2320 msleep(delta_msec);
2321 elapsed_msec += delta_msec;
2322 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
2323 goto force;
2324 }
2325
2326 if (!(wd32 & RISC_SEMAPHORE))
2327 goto force;
2328
2329 if (!(wd32 & RISC_SEMAPHORE_FORCE))
2330 goto acquired;
2331
2332 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_CLR);
2333 timeout_msec = TIMEOUT_SEMAPHORE_FORCE;
2334 n = timeout_msec / delta_msec;
2335 while (n--) {
2336 qla25xx_read_risc_sema_reg(vha, &wd32);
2337 if (!(wd32 & RISC_SEMAPHORE_FORCE))
2338 break;
2339 msleep(delta_msec);
2340 elapsed_msec += delta_msec;
2341 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
2342 goto force;
2343 }
2344
2345 if (wd32 & RISC_SEMAPHORE_FORCE)
2346 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_CLR);
2347
2348 goto attempt;
2349
2350force:
2351 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_SET);
2352
2353acquired:
2354 return;
2355}
2356
88c26663
AV		 2357/**
2358 * qla24xx_reset_chip() - Reset ISP24xx chip.
2359 * @ha: HA context
2360 *
2361 * Returns 0 on success.
2362 */
2363void
e315cd28 2364qla24xx_reset_chip(scsi_qla_host_t *vha)
88c26663 2365{
e315cd28 2366 struct qla_hw_data *ha = vha->hw;
85880801
AV		 2367
2368 if (pci_channel_offline(ha->pdev) &&
2369 ha->flags.pci_channel_io_perm_failure) {
2370 return;
2371 }
2372
fd34f556 2373 ha->isp_ops->disable_intrs(ha);
88c26663 2374
4ea2c9c7
JC		 2375 qla25xx_manipulate_risc_semaphore(vha);
2376
88c26663 2377 /* Perform RISC reset. */
e315cd28 2378 qla24xx_reset_risc(vha);
88c26663
AV		 2379}
2380
1da177e4
LT		 2381/**
2382 * qla2x00_chip_diag() - Test chip for proper operation.
2383 * @ha: HA context
2384 *
2385 * Returns 0 on success.
2386 */
abbd8870 2387int
e315cd28 2388qla2x00_chip_diag(scsi_qla_host_t *vha)
1da177e4
LT		 2389{
2390 int rval;
e315cd28 2391 struct qla_hw_data *ha = vha->hw;
3d71644c 2392 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 2393 unsigned long flags = 0;
2394 uint16_t data;
2395 uint32_t cnt;
2396 uint16_t mb[5];
73208dfd 2397 struct req_que *req = ha->req_q_map[0];
1da177e4
LT		 2398
2399 /* Assume a failed state */
2400 rval = QLA_FUNCTION_FAILED;
2401
7c3df132
SK		 2402 ql_dbg(ql_dbg_init, vha, 0x007b,
2403 "Testing device at %lx.\n", (u_long)&reg->flash_address);
1da177e4
LT		 2404
2405 spin_lock_irqsave(&ha->hardware_lock, flags);
2406
2407 /* Reset ISP chip. */
2408 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
2409
2410 /*
2411 * We need to have a delay here since the card will not respond while
2412 * in reset causing an MCA on some architectures.
2413 */
2414 udelay(20);
2415 data = qla2x00_debounce_register(&reg->ctrl_status);
2416 for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {
2417 udelay(5);
2418 data = RD_REG_WORD(&reg->ctrl_status);
2419 barrier();
2420 }
2421
2422 if (!cnt)
2423 goto chip_diag_failed;
2424
7c3df132
SK		 2425 ql_dbg(ql_dbg_init, vha, 0x007c,
2426 "Reset register cleared by chip reset.\n");
1da177e4
LT		 2427
2428 /* Reset RISC processor. */
2429 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
2430 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
2431
2432 /* Workaround for QLA2312 PCI parity error */
2433 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
2434 data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0));
2435 for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) {
2436 udelay(5);
2437 data = RD_MAILBOX_REG(ha, reg, 0);
fa2a1ce5 2438 barrier();
1da177e4
LT		 2439 }
2440 } else
2441 udelay(10);
2442
2443 if (!cnt)
2444 goto chip_diag_failed;
2445
2446 /* Check product ID of chip */
5a68a1c2 2447 ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product ID of chip.\n");
1da177e4
LT		 2448
2449 mb[1] = RD_MAILBOX_REG(ha, reg, 1);
2450 mb[2] = RD_MAILBOX_REG(ha, reg, 2);
2451 mb[3] = RD_MAILBOX_REG(ha, reg, 3);
2452 mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4));
2453 if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) ||
2454 mb[3] != PROD_ID_3) {
7c3df132
SK		 2455 ql_log(ql_log_warn, vha, 0x0062,
2456 "Wrong product ID = 0x%x,0x%x,0x%x.\n",
2457 mb[1], mb[2], mb[3]);
1da177e4
LT		 2458
2459 goto chip_diag_failed;
2460 }
2461 ha->product_id[0] = mb[1];
2462 ha->product_id[1] = mb[2];
2463 ha->product_id[2] = mb[3];
2464 ha->product_id[3] = mb[4];
2465
2466 /* Adjust fw RISC transfer size */
73208dfd 2467 if (req->length > 1024)
1da177e4
LT		 2468 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024;
2469 else
2470 ha->fw_transfer_size = REQUEST_ENTRY_SIZE *
73208dfd 2471 req->length;
1da177e4
LT		 2472
2473 if (IS_QLA2200(ha) &&
2474 RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) {
2475 /* Limit firmware transfer size with a 2200A */
7c3df132 2476 ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n");
1da177e4 2477
ea5b6382 2478 ha->device_type |= DT_ISP2200A;
1da177e4
LT		 2479 ha->fw_transfer_size = 128;
2480 }
2481
2482 /* Wrap Incoming Mailboxes Test. */
2483 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2484
7c3df132 2485 ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n");
e315cd28 2486 rval = qla2x00_mbx_reg_test(vha);
7c3df132
SK		 2487 if (rval)
2488 ql_log(ql_log_warn, vha, 0x0080,
2489 "Failed mailbox send register test.\n");
2490 else
1da177e4
LT		 2491 /* Flag a successful rval */
2492 rval = QLA_SUCCESS;
1da177e4
LT		 2493 spin_lock_irqsave(&ha->hardware_lock, flags);
2494
2495chip_diag_failed:
2496 if (rval)
7c3df132
SK		 2497 ql_log(ql_log_info, vha, 0x0081,
2498 "Chip diagnostics **** FAILED ****.\n");
1da177e4
LT		 2499
2500 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2501
2502 return (rval);
2503}
2504
0107109e
AV		 2505/**
2506 * qla24xx_chip_diag() - Test ISP24xx for proper operation.
2507 * @ha: HA context
2508 *
2509 * Returns 0 on success.
2510 */
2511int
e315cd28 2512qla24xx_chip_diag(scsi_qla_host_t *vha)
0107109e
AV		 2513{
2514 int rval;
e315cd28 2515 struct qla_hw_data *ha = vha->hw;
73208dfd 2516 struct req_que *req = ha->req_q_map[0];
0107109e 2517
7ec0effd 2518 if (IS_P3P_TYPE(ha))
a9083016
GM		 2519 return QLA_SUCCESS;
2520
73208dfd 2521 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
0107109e 2522
e315cd28 2523 rval = qla2x00_mbx_reg_test(vha);
0107109e 2524 if (rval) {
7c3df132
SK		 2525 ql_log(ql_log_warn, vha, 0x0082,
2526 "Failed mailbox send register test.\n");
0107109e
AV		 2527 } else {
2528 /* Flag a successful rval */
2529 rval = QLA_SUCCESS;
2530 }
2531
2532 return rval;
2533}
2534
a7a167bf 2535void
e315cd28 2536qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
0107109e 2537{
a7a167bf
AV		 2538 int rval;
2539 uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
73208dfd 2540 eft_size, fce_size, mq_size;
df613b96
AV		 2541 dma_addr_t tc_dma;
2542 void *tc;
e315cd28 2543 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 2544 struct req_que *req = ha->req_q_map[0];
2545 struct rsp_que *rsp = ha->rsp_q_map[0];
a7a167bf
AV		 2546
2547 if (ha->fw_dump) {
7c3df132
SK		 2548 ql_dbg(ql_dbg_init, vha, 0x00bd,
2549 "Firmware dump already allocated.\n");
a7a167bf
AV		 2550 return;
2551 }
d4e3e04d 2552
0107109e 2553 ha->fw_dumped = 0;
61f098dd 2554 ha->fw_dump_cap_flags = 0;
f73cb695
CD		 2555 dump_size = fixed_size = mem_size = eft_size = fce_size = mq_size = 0;
2556 req_q_size = rsp_q_size = 0;
2557
2558 if (IS_QLA27XX(ha))
2559 goto try_fce;
2560
d4e3e04d 2561 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
a7a167bf 2562 fixed_size = sizeof(struct qla2100_fw_dump);
d4e3e04d 2563 } else if (IS_QLA23XX(ha)) {
a7a167bf
AV		 2564 fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
2565 mem_size = (ha->fw_memory_size - 0x11000 + 1) *
2566 sizeof(uint16_t);
e428924c 2567 } else if (IS_FWI2_CAPABLE(ha)) {
b20f02e1 2568 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
6246b8a1
GM		 2569 fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem);
2570 else if (IS_QLA81XX(ha))
3a03eb79
AV		 2571 fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
2572 else if (IS_QLA25XX(ha))
2573 fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
2574 else
2575 fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
f73cb695 2576
a7a167bf
AV		 2577 mem_size = (ha->fw_memory_size - 0x100000 + 1) *
2578 sizeof(uint32_t);
050c9bb1 2579 if (ha->mqenable) {
b20f02e1 2580 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
6246b8a1 2581 mq_size = sizeof(struct qla2xxx_mq_chain);
050c9bb1
GM		 2582 /*
2583 * Allocate maximum buffer size for all queues.
2584 * Resizing must be done at end-of-dump processing.
2585 */
2586 mq_size += ha->max_req_queues *
2587 (req->length * sizeof(request_t));
2588 mq_size += ha->max_rsp_queues *
2589 (rsp->length * sizeof(response_t));
2590 }
00876ae8 2591 if (ha->tgt.atio_ring)
2d70c103 2592 mq_size += ha->tgt.atio_q_length * sizeof(request_t);
df613b96 2593 /* Allocate memory for Fibre Channel Event Buffer. */
f73cb695
CD		 2594 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
2595 !IS_QLA27XX(ha))
436a7b11 2596 goto try_eft;
df613b96 2597
f73cb695
CD		 2598try_fce:
2599 if (ha->fce)
2600 dma_free_coherent(&ha->pdev->dev,
2601 FCE_SIZE, ha->fce, ha->fce_dma);
2602
2603 /* Allocate memory for Fibre Channel Event Buffer. */
0ea85b50
JP		 2604 tc = dma_zalloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
2605 GFP_KERNEL);
df613b96 2606 if (!tc) {
7c3df132
SK		 2607 ql_log(ql_log_warn, vha, 0x00be,
2608 "Unable to allocate (%d KB) for FCE.\n",
2609 FCE_SIZE / 1024);
17d98630 2610 goto try_eft;
df613b96
AV		 2611 }
2612
e315cd28 2613 rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS,
df613b96
AV		 2614 ha->fce_mb, &ha->fce_bufs);
2615 if (rval) {
7c3df132
SK		 2616 ql_log(ql_log_warn, vha, 0x00bf,
2617 "Unable to initialize FCE (%d).\n", rval);
df613b96
AV		 2618 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc,
2619 tc_dma);
2620 ha->flags.fce_enabled = 0;
17d98630 2621 goto try_eft;
df613b96 2622 }
cfb0919c 2623 ql_dbg(ql_dbg_init, vha, 0x00c0,
7c3df132 2624 "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024);
df613b96 2625
7d9dade3 2626 fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE;
df613b96
AV		 2627 ha->flags.fce_enabled = 1;
2628 ha->fce_dma = tc_dma;
2629 ha->fce = tc;
f73cb695 2630
436a7b11 2631try_eft:
f73cb695
CD		 2632 if (ha->eft)
2633 dma_free_coherent(&ha->pdev->dev,
2634 EFT_SIZE, ha->eft, ha->eft_dma);
2635
436a7b11 2636 /* Allocate memory for Extended Trace Buffer. */
0ea85b50
JP		 2637 tc = dma_zalloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
2638 GFP_KERNEL);
436a7b11 2639 if (!tc) {
7c3df132
SK		 2640 ql_log(ql_log_warn, vha, 0x00c1,
2641 "Unable to allocate (%d KB) for EFT.\n",
2642 EFT_SIZE / 1024);
436a7b11
AV		 2643 goto cont_alloc;
2644 }
2645
e315cd28 2646 rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
436a7b11 2647 if (rval) {
7c3df132
SK		 2648 ql_log(ql_log_warn, vha, 0x00c2,
2649 "Unable to initialize EFT (%d).\n", rval);
436a7b11
AV		 2650 dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc,
2651 tc_dma);
2652 goto cont_alloc;
2653 }
cfb0919c 2654 ql_dbg(ql_dbg_init, vha, 0x00c3,
7c3df132 2655 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
436a7b11
AV		 2656
2657 eft_size = EFT_SIZE;
2658 ha->eft_dma = tc_dma;
2659 ha->eft = tc;
d4e3e04d 2660 }
f73cb695 2661
a7a167bf 2662cont_alloc:
f73cb695
CD		 2663 if (IS_QLA27XX(ha)) {
2664 if (!ha->fw_dump_template) {
2665 ql_log(ql_log_warn, vha, 0x00ba,
2666 "Failed missing fwdump template\n");
2667 return;
2668 }
2669 dump_size = qla27xx_fwdt_calculate_dump_size(vha);
2670 ql_dbg(ql_dbg_init, vha, 0x00fa,
2671 "-> allocating fwdump (%x bytes)...\n", dump_size);
2672 goto allocate;
2673 }
2674
73208dfd
AC		 2675 req_q_size = req->length * sizeof(request_t);
2676 rsp_q_size = rsp->length * sizeof(response_t);
a7a167bf 2677 dump_size = offsetof(struct qla2xxx_fw_dump, isp);
2afa19a9 2678 dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size;
bb99de67
AV		 2679 ha->chain_offset = dump_size;
2680 dump_size += mq_size + fce_size;
d4e3e04d 2681
b945e777
QT		 2682 if (ha->exchoffld_buf)
2683 dump_size += sizeof(struct qla2xxx_offld_chain) +
2684 ha->exchoffld_size;
2685 if (ha->exlogin_buf)
2686 dump_size += sizeof(struct qla2xxx_offld_chain) +
2687 ha->exlogin_size;
2688
f73cb695 2689allocate:
d4e3e04d 2690 ha->fw_dump = vmalloc(dump_size);
a7a167bf 2691 if (!ha->fw_dump) {
7c3df132
SK		 2692 ql_log(ql_log_warn, vha, 0x00c4,
2693 "Unable to allocate (%d KB) for firmware dump.\n",
2694 dump_size / 1024);
a7a167bf 2695
e30d1756
MI		 2696 if (ha->fce) {
2697 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
2698 ha->fce_dma);
2699 ha->fce = NULL;
2700 ha->fce_dma = 0;
2701 }
2702
a7a167bf
AV		 2703 if (ha->eft) {
2704 dma_free_coherent(&ha->pdev->dev, eft_size, ha->eft,
2705 ha->eft_dma);
2706 ha->eft = NULL;
2707 ha->eft_dma = 0;
2708 }
2709 return;
2710 }
f73cb695 2711 ha->fw_dump_len = dump_size;
cfb0919c 2712 ql_dbg(ql_dbg_init, vha, 0x00c5,
7c3df132 2713 "Allocated (%d KB) for firmware dump.\n", dump_size / 1024);
a7a167bf 2714
f73cb695
CD		 2715 if (IS_QLA27XX(ha))
2716 return;
2717
a7a167bf
AV		 2718 ha->fw_dump->signature[0] = 'Q';
2719 ha->fw_dump->signature[1] = 'L';
2720 ha->fw_dump->signature[2] = 'G';
2721 ha->fw_dump->signature[3] = 'C';
ad950360 2722 ha->fw_dump->version = htonl(1);
a7a167bf
AV		 2723
2724 ha->fw_dump->fixed_size = htonl(fixed_size);
2725 ha->fw_dump->mem_size = htonl(mem_size);
2726 ha->fw_dump->req_q_size = htonl(req_q_size);
2727 ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
2728
2729 ha->fw_dump->eft_size = htonl(eft_size);
2730 ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma));
2731 ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma));
2732
2733 ha->fw_dump->header_size =
2734 htonl(offsetof(struct qla2xxx_fw_dump, isp));
0107109e
AV		 2735}
2736
18e7555a
AV		 2737static int
2738qla81xx_mpi_sync(scsi_qla_host_t *vha)
2739{
2740#define MPS_MASK 0xe0
2741 int rval;
2742 uint16_t dc;
2743 uint32_t dw;
18e7555a
AV		 2744
2745 if (!IS_QLA81XX(vha->hw))
2746 return QLA_SUCCESS;
2747
2748 rval = qla2x00_write_ram_word(vha, 0x7c00, 1);
2749 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2750 ql_log(ql_log_warn, vha, 0x0105,
2751 "Unable to acquire semaphore.\n");
18e7555a
AV		 2752 goto done;
2753 }
2754
2755 pci_read_config_word(vha->hw->pdev, 0x54, &dc);
2756 rval = qla2x00_read_ram_word(vha, 0x7a15, &dw);
2757 if (rval != QLA_SUCCESS) {
7c3df132 2758 ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n");
18e7555a
AV		 2759 goto done_release;
2760 }
2761
2762 dc &= MPS_MASK;
2763 if (dc == (dw & MPS_MASK))
2764 goto done_release;
2765
2766 dw &= ~MPS_MASK;
2767 dw |= dc;
2768 rval = qla2x00_write_ram_word(vha, 0x7a15, dw);
2769 if (rval != QLA_SUCCESS) {
7c3df132 2770 ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n");
18e7555a
AV		 2771 }
2772
2773done_release:
2774 rval = qla2x00_write_ram_word(vha, 0x7c00, 0);
2775 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2776 ql_log(ql_log_warn, vha, 0x006d,
2777 "Unable to release semaphore.\n");
18e7555a
AV		 2778 }
2779
2780done:
2781 return rval;
2782}
2783
8d93f550
CD		 2784int
2785qla2x00_alloc_outstanding_cmds(struct qla_hw_data *ha, struct req_que *req)
2786{
2787 /* Don't try to reallocate the array */
2788 if (req->outstanding_cmds)
2789 return QLA_SUCCESS;
2790
d7459527 2791 if (!IS_FWI2_CAPABLE(ha))
8d93f550
CD		 2792 req->num_outstanding_cmds = DEFAULT_OUTSTANDING_COMMANDS;
2793 else {
03e8c680
QT		 2794 if (ha->cur_fw_xcb_count <= ha->cur_fw_iocb_count)
2795 req->num_outstanding_cmds = ha->cur_fw_xcb_count;
8d93f550 2796 else
03e8c680 2797 req->num_outstanding_cmds = ha->cur_fw_iocb_count;
8d93f550
CD		 2798 }
2799
2800 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
2801 req->num_outstanding_cmds, GFP_KERNEL);
2802
2803 if (!req->outstanding_cmds) {
2804 /*
2805 * Try to allocate a minimal size just so we can get through
2806 * initialization.
2807 */
2808 req->num_outstanding_cmds = MIN_OUTSTANDING_COMMANDS;
2809 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
2810 req->num_outstanding_cmds, GFP_KERNEL);
2811
2812 if (!req->outstanding_cmds) {
2813 ql_log(ql_log_fatal, NULL, 0x0126,
2814 "Failed to allocate memory for "
2815 "outstanding_cmds for req_que %p.\n", req);
2816 req->num_outstanding_cmds = 0;
2817 return QLA_FUNCTION_FAILED;
2818 }
2819 }
2820
2821 return QLA_SUCCESS;
2822}
2823
e4e3a2ce
QT		 2824#define PRINT_FIELD(_field, _flag, _str) { \
2825 if (a0->_field & _flag) {\
2826 if (p) {\
2827 strcat(ptr, "|");\
2828 ptr++;\
2829 leftover--;\
2830 } \
2831 len = snprintf(ptr, leftover, "%s", _str); \
2832 p = 1;\
2833 leftover -= len;\
2834 ptr += len; \
2835 } \
2836}
2837
2838static void qla2xxx_print_sfp_info(struct scsi_qla_host *vha)
2839{
2840#define STR_LEN 64
2841 struct sff_8247_a0 *a0 = (struct sff_8247_a0 *)vha->hw->sfp_data;
2842 u8 str[STR_LEN], *ptr, p;
2843 int leftover, len;
2844
2845 memset(str, 0, STR_LEN);
2846 snprintf(str, SFF_VEN_NAME_LEN+1, a0->vendor_name);
2847 ql_dbg(ql_dbg_init, vha, 0x015a,
2848 "SFP MFG Name: %s\n", str);
2849
2850 memset(str, 0, STR_LEN);
2851 snprintf(str, SFF_PART_NAME_LEN+1, a0->vendor_pn);
2852 ql_dbg(ql_dbg_init, vha, 0x015c,
2853 "SFP Part Name: %s\n", str);
2854
2855 /* media */
2856 memset(str, 0, STR_LEN);
2857 ptr = str;
2858 leftover = STR_LEN;
2859 p = len = 0;
2860 PRINT_FIELD(fc_med_cc9, FC_MED_TW, "Twin AX");
2861 PRINT_FIELD(fc_med_cc9, FC_MED_TP, "Twisted Pair");
2862 PRINT_FIELD(fc_med_cc9, FC_MED_MI, "Min Coax");
2863 PRINT_FIELD(fc_med_cc9, FC_MED_TV, "Video Coax");
2864 PRINT_FIELD(fc_med_cc9, FC_MED_M6, "MultiMode 62.5um");
2865 PRINT_FIELD(fc_med_cc9, FC_MED_M5, "MultiMode 50um");
2866 PRINT_FIELD(fc_med_cc9, FC_MED_SM, "SingleMode");
2867 ql_dbg(ql_dbg_init, vha, 0x0160,
2868 "SFP Media: %s\n", str);
2869
2870 /* link length */
2871 memset(str, 0, STR_LEN);
2872 ptr = str;
2873 leftover = STR_LEN;
2874 p = len = 0;
2875 PRINT_FIELD(fc_ll_cc7, FC_LL_VL, "Very Long");
2876 PRINT_FIELD(fc_ll_cc7, FC_LL_S, "Short");
2877 PRINT_FIELD(fc_ll_cc7, FC_LL_I, "Intermediate");
2878 PRINT_FIELD(fc_ll_cc7, FC_LL_L, "Long");
2879 PRINT_FIELD(fc_ll_cc7, FC_LL_M, "Medium");
2880 ql_dbg(ql_dbg_init, vha, 0x0196,
2881 "SFP Link Length: %s\n", str);
2882
2883 memset(str, 0, STR_LEN);
2884 ptr = str;
2885 leftover = STR_LEN;
2886 p = len = 0;
2887 PRINT_FIELD(fc_ll_cc7, FC_LL_SA, "Short Wave (SA)");
2888 PRINT_FIELD(fc_ll_cc7, FC_LL_LC, "Long Wave(LC)");
2889 PRINT_FIELD(fc_tec_cc8, FC_TEC_SN, "Short Wave (SN)");
2890 PRINT_FIELD(fc_tec_cc8, FC_TEC_SL, "Short Wave (SL)");
2891 PRINT_FIELD(fc_tec_cc8, FC_TEC_LL, "Long Wave (LL)");
2892 ql_dbg(ql_dbg_init, vha, 0x016e,
2893 "SFP FC Link Tech: %s\n", str);
2894
2895 if (a0->length_km)
2896 ql_dbg(ql_dbg_init, vha, 0x016f,
2897 "SFP Distant: %d km\n", a0->length_km);
2898 if (a0->length_100m)
2899 ql_dbg(ql_dbg_init, vha, 0x0170,
2900 "SFP Distant: %d m\n", a0->length_100m*100);
2901 if (a0->length_50um_10m)
2902 ql_dbg(ql_dbg_init, vha, 0x0189,
2903 "SFP Distant (WL=50um): %d m\n", a0->length_50um_10m * 10);
2904 if (a0->length_62um_10m)
2905 ql_dbg(ql_dbg_init, vha, 0x018a,
2906 "SFP Distant (WL=62.5um): %d m\n", a0->length_62um_10m * 10);
2907 if (a0->length_om4_10m)
2908 ql_dbg(ql_dbg_init, vha, 0x0194,
2909 "SFP Distant (OM4): %d m\n", a0->length_om4_10m * 10);
2910 if (a0->length_om3_10m)
2911 ql_dbg(ql_dbg_init, vha, 0x0195,
2912 "SFP Distant (OM3): %d m\n", a0->length_om3_10m * 10);
2913}
2914
2915
2916/*
2917 * Return Code:
2918 * QLA_SUCCESS: no action
2919 * QLA_INTERFACE_ERROR: SFP is not there.
2920 * QLA_FUNCTION_FAILED: detected New SFP
2921 */
2922int
2923qla24xx_detect_sfp(scsi_qla_host_t *vha)
2924{
2925 int rc = QLA_SUCCESS;
2926 struct sff_8247_a0 *a;
2927 struct qla_hw_data *ha = vha->hw;
2928
2929 if (!AUTO_DETECT_SFP_SUPPORT(vha))
2930 goto out;
2931
2932 rc = qla2x00_read_sfp_dev(vha, NULL, 0);
2933 if (rc)
2934 goto out;
2935
2936 a = (struct sff_8247_a0 *)vha->hw->sfp_data;
2937 qla2xxx_print_sfp_info(vha);
2938
2939 if (a->fc_ll_cc7 & FC_LL_VL || a->fc_ll_cc7 & FC_LL_L) {
2940 /* long range */
2941 ha->flags.detected_lr_sfp = 1;
2942
2943 if (a->length_km > 5 || a->length_100m > 50)
2944 ha->long_range_distance = LR_DISTANCE_10K;
2945 else
2946 ha->long_range_distance = LR_DISTANCE_5K;
2947
2948 if (ha->flags.detected_lr_sfp != ha->flags.using_lr_setting)
2949 ql_dbg(ql_dbg_async, vha, 0x507b,
2950 "Detected Long Range SFP.\n");
2951 } else {
2952 /* short range */
2953 ha->flags.detected_lr_sfp = 0;
2954 if (ha->flags.using_lr_setting)
2955 ql_dbg(ql_dbg_async, vha, 0x5084,
2956 "Detected Short Range SFP.\n");
2957 }
2958
2959 if (!vha->flags.init_done)
2960 rc = QLA_SUCCESS;
2961out:
2962 return rc;
2963}
2964
1da177e4
LT		 2965/**
2966 * qla2x00_setup_chip() - Load and start RISC firmware.
2967 * @ha: HA context
2968 *
2969 * Returns 0 on success.
2970 */
2971static int
e315cd28 2972qla2x00_setup_chip(scsi_qla_host_t *vha)
1da177e4 2973{
0107109e
AV		 2974 int rval;
2975 uint32_t srisc_address = 0;
e315cd28 2976 struct qla_hw_data *ha = vha->hw;
3db0652e
AV		 2977 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2978 unsigned long flags;
dda772e8 2979 uint16_t fw_major_version;
3db0652e 2980
7ec0effd 2981 if (IS_P3P_TYPE(ha)) {
a9083016 2982 rval = ha->isp_ops->load_risc(vha, &srisc_address);
14e303d9
AV		 2983 if (rval == QLA_SUCCESS) {
2984 qla2x00_stop_firmware(vha);
a9083016 2985 goto enable_82xx_npiv;
14e303d9 2986 } else
b963752f 2987 goto failed;
a9083016
GM		 2988 }
2989
3db0652e
AV		 2990 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
2991 /* Disable SRAM, Instruction RAM and GP RAM parity. */
2992 spin_lock_irqsave(&ha->hardware_lock, flags);
2993 WRT_REG_WORD(&reg->hccr, (HCCR_ENABLE_PARITY + 0x0));
2994 RD_REG_WORD(&reg->hccr);
2995 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2996 }
1da177e4 2997
18e7555a
AV		 2998 qla81xx_mpi_sync(vha);
2999
1da177e4 3000 /* Load firmware sequences */
e315cd28 3001 rval = ha->isp_ops->load_risc(vha, &srisc_address);
0107109e 3002 if (rval == QLA_SUCCESS) {
7c3df132
SK		 3003 ql_dbg(ql_dbg_init, vha, 0x00c9,
3004 "Verifying Checksum of loaded RISC code.\n");
1da177e4 3005
e315cd28 3006 rval = qla2x00_verify_checksum(vha, srisc_address);
1da177e4
LT		 3007 if (rval == QLA_SUCCESS) {
3008 /* Start firmware execution. */
7c3df132
SK		 3009 ql_dbg(ql_dbg_init, vha, 0x00ca,
3010 "Starting firmware.\n");
1da177e4 3011
b0d6cabd
HM		 3012 if (ql2xexlogins)
3013 ha->flags.exlogins_enabled = 1;
3014
99e1b683 3015 if (qla_is_exch_offld_enabled(vha))
2f56a7f1
HM		 3016 ha->flags.exchoffld_enabled = 1;
3017
e315cd28 3018 rval = qla2x00_execute_fw(vha, srisc_address);
1da177e4 3019 /* Retrieve firmware information. */
dda772e8 3020 if (rval == QLA_SUCCESS) {
e4e3a2ce
QT		 3021 qla24xx_detect_sfp(vha);
3022
b0d6cabd
HM		 3023 rval = qla2x00_set_exlogins_buffer(vha);
3024 if (rval != QLA_SUCCESS)
3025 goto failed;
3026
2f56a7f1
HM		 3027 rval = qla2x00_set_exchoffld_buffer(vha);
3028 if (rval != QLA_SUCCESS)
3029 goto failed;
3030
a9083016 3031enable_82xx_npiv:
dda772e8 3032 fw_major_version = ha->fw_major_version;
7ec0effd 3033 if (IS_P3P_TYPE(ha))
3173167f 3034 qla82xx_check_md_needed(vha);
6246b8a1
GM		 3035 else
3036 rval = qla2x00_get_fw_version(vha);
ca9e9c3e
AV		 3037 if (rval != QLA_SUCCESS)
3038 goto failed;
2c3dfe3f 3039 ha->flags.npiv_supported = 0;
e315cd28 3040 if (IS_QLA2XXX_MIDTYPE(ha) &&
946fb891 3041 (ha->fw_attributes & BIT_2)) {
2c3dfe3f 3042 ha->flags.npiv_supported = 1;
4d0ea247
SJ		 3043 if ((!ha->max_npiv_vports) ||
3044 ((ha->max_npiv_vports + 1) %
eb66dc60 3045 MIN_MULTI_ID_FABRIC))
4d0ea247 3046 ha->max_npiv_vports =
eb66dc60 3047 MIN_MULTI_ID_FABRIC - 1;
4d0ea247 3048 }
03e8c680 3049 qla2x00_get_resource_cnts(vha);
d743de66 3050
8d93f550
CD		 3051 /*
3052 * Allocate the array of outstanding commands
3053 * now that we know the firmware resources.
3054 */
3055 rval = qla2x00_alloc_outstanding_cmds(ha,
3056 vha->req);
3057 if (rval != QLA_SUCCESS)
3058 goto failed;
3059
be5ea3cf 3060 if (!fw_major_version && ql2xallocfwdump
7ec0effd 3061 && !(IS_P3P_TYPE(ha)))
08de2844 3062 qla2x00_alloc_fw_dump(vha);
3b6e5b9d
CD		 3063 } else {
3064 goto failed;
1da177e4
LT		 3065 }
3066 } else {
7c3df132
SK		 3067 ql_log(ql_log_fatal, vha, 0x00cd,
3068 "ISP Firmware failed checksum.\n");
3069 goto failed;
1da177e4 3070 }
c74d88a4
AV		 3071 } else
3072 goto failed;
1da177e4 3073
3db0652e
AV		 3074 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
3075 /* Enable proper parity. */
3076 spin_lock_irqsave(&ha->hardware_lock, flags);
3077 if (IS_QLA2300(ha))
3078 /* SRAM parity */
3079 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x1);
3080 else
3081 /* SRAM, Instruction RAM and GP RAM parity */
3082 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x7);
3083 RD_REG_WORD(&reg->hccr);
3084 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3085 }
3086
f3982d89
CD		 3087 if (IS_QLA27XX(ha))
3088 ha->flags.fac_supported = 1;
3089 else if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
1d2874de
JC		 3090 uint32_t size;
3091
3092 rval = qla81xx_fac_get_sector_size(vha, &size);
3093 if (rval == QLA_SUCCESS) {
3094 ha->flags.fac_supported = 1;
3095 ha->fdt_block_size = size << 2;
3096 } else {
7c3df132 3097 ql_log(ql_log_warn, vha, 0x00ce,
1d2874de
JC		 3098 "Unsupported FAC firmware (%d.%02d.%02d).\n",
3099 ha->fw_major_version, ha->fw_minor_version,
3100 ha->fw_subminor_version);
1ca60e3b 3101
f73cb695 3102 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
6246b8a1
GM		 3103 ha->flags.fac_supported = 0;
3104 rval = QLA_SUCCESS;
3105 }
1d2874de
JC		 3106 }
3107 }
ca9e9c3e 3108failed:
1da177e4 3109 if (rval) {
7c3df132
SK		 3110 ql_log(ql_log_fatal, vha, 0x00cf,
3111 "Setup chip ****FAILED****.\n");
1da177e4
LT		 3112 }
3113
3114 return (rval);
3115}
3116
3117/**
3118 * qla2x00_init_response_q_entries() - Initializes response queue entries.
3119 * @ha: HA context
3120 *
3121 * Beginning of request ring has initialization control block already built
3122 * by nvram config routine.
3123 *
3124 * Returns 0 on success.
3125 */
73208dfd
AC		 3126void
3127qla2x00_init_response_q_entries(struct rsp_que *rsp)
1da177e4
LT		 3128{
3129 uint16_t cnt;
3130 response_t *pkt;
3131
2afa19a9
AC		 3132 rsp->ring_ptr = rsp->ring;
3133 rsp->ring_index = 0;
3134 rsp->status_srb = NULL;
e315cd28
AC		 3135 pkt = rsp->ring_ptr;
3136 for (cnt = 0; cnt < rsp->length; cnt++) {
1da177e4
LT		 3137 pkt->signature = RESPONSE_PROCESSED;
3138 pkt++;
3139 }
1da177e4
LT		 3140}
3141
3142/**
3143 * qla2x00_update_fw_options() - Read and process firmware options.
3144 * @ha: HA context
3145 *
3146 * Returns 0 on success.
3147 */
abbd8870 3148void
e315cd28 3149qla2x00_update_fw_options(scsi_qla_host_t *vha)
1da177e4
LT		 3150{
3151 uint16_t swing, emphasis, tx_sens, rx_sens;
e315cd28 3152 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3153
3154 memset(ha->fw_options, 0, sizeof(ha->fw_options));
e315cd28 3155 qla2x00_get_fw_options(vha, ha->fw_options);
1da177e4
LT		 3156
3157 if (IS_QLA2100(ha) || IS_QLA2200(ha))
3158 return;
3159
3160 /* Serial Link options. */
7c3df132
SK		 3161 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
3162 "Serial link options.\n");
3163 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
3164 (uint8_t *)&ha->fw_seriallink_options,
3165 sizeof(ha->fw_seriallink_options));
1da177e4
LT		 3166
3167 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
3168 if (ha->fw_seriallink_options[3] & BIT_2) {
3169 ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING;
3170
3171 /* 1G settings */
3172 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
3173 emphasis = (ha->fw_seriallink_options[2] &
3174 (BIT_4 | BIT_3)) >> 3;
3175 tx_sens = ha->fw_seriallink_options[0] &
fa2a1ce5 3176 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 3177 rx_sens = (ha->fw_seriallink_options[0] &
3178 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
3179 ha->fw_options[10] = (emphasis << 14) | (swing << 8);
3180 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
3181 if (rx_sens == 0x0)
3182 rx_sens = 0x3;
3183 ha->fw_options[10] |= (tx_sens << 4) | rx_sens;
3184 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
3185 ha->fw_options[10] |= BIT_5 |
3186 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
3187 (tx_sens & (BIT_1 | BIT_0));
3188
3189 /* 2G settings */
3190 swing = (ha->fw_seriallink_options[2] &
3191 (BIT_7 | BIT_6 | BIT_5)) >> 5;
3192 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
3193 tx_sens = ha->fw_seriallink_options[1] &
fa2a1ce5 3194 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 3195 rx_sens = (ha->fw_seriallink_options[1] &
3196 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
3197 ha->fw_options[11] = (emphasis << 14) | (swing << 8);
3198 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
3199 if (rx_sens == 0x0)
3200 rx_sens = 0x3;
3201 ha->fw_options[11] |= (tx_sens << 4) | rx_sens;
3202 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
3203 ha->fw_options[11] |= BIT_5 |
3204 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
3205 (tx_sens & (BIT_1 | BIT_0));
3206 }
3207
3208 /* FCP2 options. */
3209 /* Return command IOCBs without waiting for an ABTS to complete. */
3210 ha->fw_options[3] |= BIT_13;
3211
3212 /* LED scheme. */
3213 if (ha->flags.enable_led_scheme)
3214 ha->fw_options[2] |= BIT_12;
3215
48c02fde
AV		 3216 /* Detect ISP6312. */
3217 if (IS_QLA6312(ha))
3218 ha->fw_options[2] |= BIT_13;
3219
088d09d4
GM		 3220 /* Set Retry FLOGI in case of P2P connection */
3221 if (ha->operating_mode == P2P) {
3222 ha->fw_options[2] |= BIT_3;
3223 ql_dbg(ql_dbg_disc, vha, 0x2100,
3224 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
3225 __func__, ha->fw_options[2]);
3226 }
3227
1da177e4 3228 /* Update firmware options. */
e315cd28 3229 qla2x00_set_fw_options(vha, ha->fw_options);
1da177e4
LT		 3230}
3231
0107109e 3232void
e315cd28 3233qla24xx_update_fw_options(scsi_qla_host_t *vha)
0107109e
AV		 3234{
3235 int rval;
e315cd28 3236 struct qla_hw_data *ha = vha->hw;
0107109e 3237
7ec0effd 3238 if (IS_P3P_TYPE(ha))
a9083016
GM		 3239 return;
3240
f198cafa
HM		 3241 /* Hold status IOCBs until ABTS response received. */
3242 if (ql2xfwholdabts)
3243 ha->fw_options[3] |= BIT_12;
3244
088d09d4
GM		 3245 /* Set Retry FLOGI in case of P2P connection */
3246 if (ha->operating_mode == P2P) {
3247 ha->fw_options[2] |= BIT_3;
3248 ql_dbg(ql_dbg_disc, vha, 0x2101,
3249 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
3250 __func__, ha->fw_options[2]);
3251 }
3252
41dc529a 3253 /* Move PUREX, ABTS RX & RIDA to ATIOQ */
3c4810ff
QT		 3254 if (ql2xmvasynctoatio &&
3255 (IS_QLA83XX(ha) || IS_QLA27XX(ha))) {
41dc529a
QT		 3256 if (qla_tgt_mode_enabled(vha) ||
3257 qla_dual_mode_enabled(vha))
3258 ha->fw_options[2] |= BIT_11;
3259 else
3260 ha->fw_options[2] &= ~BIT_11;
3261 }
3262
f7e761f5
QT		 3263 if (IS_QLA25XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
3264 /*
3265 * Tell FW to track each exchange to prevent
3266 * driver from using stale exchange.
3267 */
3268 if (qla_tgt_mode_enabled(vha) ||
3269 qla_dual_mode_enabled(vha))
3270 ha->fw_options[2] |= BIT_4;
3271 else
3272 ha->fw_options[2] &= ~BIT_4;
3273 }
3274
83548fe2
QT		 3275 ql_dbg(ql_dbg_init, vha, 0x00e8,
3276 "%s, add FW options 1-3 = 0x%04x 0x%04x 0x%04x mode %x\n",
3277 __func__, ha->fw_options[1], ha->fw_options[2],
3278 ha->fw_options[3], vha->host->active_mode);
3c4810ff
QT		 3279
3280 if (ha->fw_options[1] || ha->fw_options[2] || ha->fw_options[3])
3281 qla2x00_set_fw_options(vha, ha->fw_options);
41dc529a 3282
0107109e 3283 /* Update Serial Link options. */
f94097ed 3284 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0)
0107109e
AV		 3285 return;
3286
e315cd28 3287 rval = qla2x00_set_serdes_params(vha,
f94097ed
AV		 3288 le16_to_cpu(ha->fw_seriallink_options24[1]),
3289 le16_to_cpu(ha->fw_seriallink_options24[2]),
3290 le16_to_cpu(ha->fw_seriallink_options24[3]));
0107109e 3291 if (rval != QLA_SUCCESS) {
7c3df132 3292 ql_log(ql_log_warn, vha, 0x0104,
0107109e
AV		 3293 "Unable to update Serial Link options (%x).\n", rval);
3294 }
3295}
3296
abbd8870 3297void
e315cd28 3298qla2x00_config_rings(struct scsi_qla_host *vha)
abbd8870 3299{
e315cd28 3300 struct qla_hw_data *ha = vha->hw;
3d71644c 3301 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
73208dfd
AC		 3302 struct req_que *req = ha->req_q_map[0];
3303 struct rsp_que *rsp = ha->rsp_q_map[0];
abbd8870
AV		 3304
3305 /* Setup ring parameters in initialization control block. */
ad950360
BVA		 3306 ha->init_cb->request_q_outpointer = cpu_to_le16(0);
3307 ha->init_cb->response_q_inpointer = cpu_to_le16(0);
e315cd28
AC		 3308 ha->init_cb->request_q_length = cpu_to_le16(req->length);
3309 ha->init_cb->response_q_length = cpu_to_le16(rsp->length);
3310 ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
3311 ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
3312 ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
3313 ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
abbd8870
AV		 3314
3315 WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0);
3316 WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0);
3317 WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0);
3318 WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0);
3319 RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */
3320}
3321
0107109e 3322void
e315cd28 3323qla24xx_config_rings(struct scsi_qla_host *vha)
0107109e 3324{
e315cd28 3325 struct qla_hw_data *ha = vha->hw;
118e2ef9 3326 device_reg_t *reg = ISP_QUE_REG(ha, 0);
73208dfd
AC		 3327 struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
3328 struct qla_msix_entry *msix;
0107109e 3329 struct init_cb_24xx *icb;
73208dfd
AC		 3330 uint16_t rid = 0;
3331 struct req_que *req = ha->req_q_map[0];
3332 struct rsp_que *rsp = ha->rsp_q_map[0];
0107109e 3333
6246b8a1 3334 /* Setup ring parameters in initialization control block. */
0107109e 3335 icb = (struct init_cb_24xx *)ha->init_cb;
ad950360
BVA		 3336 icb->request_q_outpointer = cpu_to_le16(0);
3337 icb->response_q_inpointer = cpu_to_le16(0);
e315cd28
AC		 3338 icb->request_q_length = cpu_to_le16(req->length);
3339 icb->response_q_length = cpu_to_le16(rsp->length);
3340 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
3341 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
3342 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
3343 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
0107109e 3344
2d70c103 3345 /* Setup ATIO queue dma pointers for target mode */
ad950360 3346 icb->atio_q_inpointer = cpu_to_le16(0);
2d70c103
NB		 3347 icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length);
3348 icb->atio_q_address[0] = cpu_to_le32(LSD(ha->tgt.atio_dma));
3349 icb->atio_q_address[1] = cpu_to_le32(MSD(ha->tgt.atio_dma));
3350
7c6300e3 3351 if (IS_SHADOW_REG_CAPABLE(ha))
ad950360 3352 icb->firmware_options_2 |= cpu_to_le32(BIT_30|BIT_29);
7c6300e3 3353
f73cb695 3354 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
ad950360
BVA		 3355 icb->qos = cpu_to_le16(QLA_DEFAULT_QUE_QOS);
3356 icb->rid = cpu_to_le16(rid);
73208dfd
AC		 3357 if (ha->flags.msix_enabled) {
3358 msix = &ha->msix_entries[1];
83548fe2 3359 ql_dbg(ql_dbg_init, vha, 0x0019,
7c3df132
SK		 3360 "Registering vector 0x%x for base que.\n",
3361 msix->entry);
73208dfd
AC		 3362 icb->msix = cpu_to_le16(msix->entry);
3363 }
3364 /* Use alternate PCI bus number */
3365 if (MSB(rid))
ad950360 3366 icb->firmware_options_2 |= cpu_to_le32(BIT_19);
73208dfd
AC		 3367 /* Use alternate PCI devfn */
3368 if (LSB(rid))
ad950360 3369 icb->firmware_options_2 |= cpu_to_le32(BIT_18);
73208dfd 3370
3155754a 3371 /* Use Disable MSIX Handshake mode for capable adapters */
6246b8a1
GM		 3372 if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) &&
3373 (ha->flags.msix_enabled)) {
ad950360 3374 icb->firmware_options_2 &= cpu_to_le32(~BIT_22);
3155754a 3375 ha->flags.disable_msix_handshake = 1;
7c3df132
SK		 3376 ql_dbg(ql_dbg_init, vha, 0x00fe,
3377 "MSIX Handshake Disable Mode turned on.\n");
3155754a 3378 } else {
ad950360 3379 icb->firmware_options_2 |= cpu_to_le32(BIT_22);
3155754a 3380 }
ad950360 3381 icb->firmware_options_2 |= cpu_to_le32(BIT_23);
73208dfd
AC		 3382
3383 WRT_REG_DWORD(&reg->isp25mq.req_q_in, 0);
3384 WRT_REG_DWORD(&reg->isp25mq.req_q_out, 0);
3385 WRT_REG_DWORD(&reg->isp25mq.rsp_q_in, 0);
3386 WRT_REG_DWORD(&reg->isp25mq.rsp_q_out, 0);
3387 } else {
3388 WRT_REG_DWORD(&reg->isp24.req_q_in, 0);
3389 WRT_REG_DWORD(&reg->isp24.req_q_out, 0);
3390 WRT_REG_DWORD(&reg->isp24.rsp_q_in, 0);
3391 WRT_REG_DWORD(&reg->isp24.rsp_q_out, 0);
3392 }
aa230bc5 3393 qlt_24xx_config_rings(vha);
2d70c103 3394
73208dfd
AC		 3395 /* PCI posting */
3396 RD_REG_DWORD(&ioreg->hccr);
0107109e
AV		 3397}
3398
1da177e4
LT		 3399/**
3400 * qla2x00_init_rings() - Initializes firmware.
3401 * @ha: HA context
3402 *
3403 * Beginning of request ring has initialization control block already built
3404 * by nvram config routine.
3405 *
3406 * Returns 0 on success.
3407 */
8ae6d9c7 3408int
e315cd28 3409qla2x00_init_rings(scsi_qla_host_t *vha)
1da177e4
LT		 3410{
3411 int rval;
3412 unsigned long flags = 0;
29bdccbe 3413 int cnt, que;
e315cd28 3414 struct qla_hw_data *ha = vha->hw;
29bdccbe
AC		 3415 struct req_que *req;
3416 struct rsp_que *rsp;
2c3dfe3f
SJ		 3417 struct mid_init_cb_24xx *mid_init_cb =
3418 (struct mid_init_cb_24xx *) ha->init_cb;
1da177e4
LT		 3419
3420 spin_lock_irqsave(&ha->hardware_lock, flags);
3421
3422 /* Clear outstanding commands array. */
2afa19a9 3423 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 3424 req = ha->req_q_map[que];
cb43285f 3425 if (!req || !test_bit(que, ha->req_qid_map))
29bdccbe 3426 continue;
7c6300e3
JC		 3427 req->out_ptr = (void *)(req->ring + req->length);
3428 *req->out_ptr = 0;
8d93f550 3429 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++)
29bdccbe 3430 req->outstanding_cmds[cnt] = NULL;
1da177e4 3431
2afa19a9 3432 req->current_outstanding_cmd = 1;
1da177e4 3433
29bdccbe
AC		 3434 /* Initialize firmware. */
3435 req->ring_ptr = req->ring;
3436 req->ring_index = 0;
3437 req->cnt = req->length;
3438 }
1da177e4 3439
2afa19a9 3440 for (que = 0; que < ha->max_rsp_queues; que++) {
29bdccbe 3441 rsp = ha->rsp_q_map[que];
cb43285f 3442 if (!rsp || !test_bit(que, ha->rsp_qid_map))
29bdccbe 3443 continue;
7c6300e3
JC		 3444 rsp->in_ptr = (void *)(rsp->ring + rsp->length);
3445 *rsp->in_ptr = 0;
29bdccbe 3446 /* Initialize response queue entries */
8ae6d9c7
GM		 3447 if (IS_QLAFX00(ha))
3448 qlafx00_init_response_q_entries(rsp);
3449 else
3450 qla2x00_init_response_q_entries(rsp);
29bdccbe 3451 }
1da177e4 3452
2d70c103
NB		 3453 ha->tgt.atio_ring_ptr = ha->tgt.atio_ring;
3454 ha->tgt.atio_ring_index = 0;
3455 /* Initialize ATIO queue entries */
3456 qlt_init_atio_q_entries(vha);
3457
e315cd28 3458 ha->isp_ops->config_rings(vha);
1da177e4
LT		 3459
3460 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3461
8ae6d9c7
GM		 3462 ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n");
3463
3464 if (IS_QLAFX00(ha)) {
3465 rval = qlafx00_init_firmware(vha, ha->init_cb_size);
3466 goto next_check;
3467 }
3468
1da177e4 3469 /* Update any ISP specific firmware options before initialization. */
e315cd28 3470 ha->isp_ops->update_fw_options(vha);
1da177e4 3471
605aa2bc 3472 if (ha->flags.npiv_supported) {
45980cc2 3473 if (ha->operating_mode == LOOP && !IS_CNA_CAPABLE(ha))
605aa2bc 3474 ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
c48339de 3475 mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
605aa2bc
LC		 3476 }
3477
24a08138 3478 if (IS_FWI2_CAPABLE(ha)) {
ad950360 3479 mid_init_cb->options = cpu_to_le16(BIT_1);
24a08138 3480 mid_init_cb->init_cb.execution_throttle =
03e8c680 3481 cpu_to_le16(ha->cur_fw_xcb_count);
40f3862b
JC		 3482 ha->flags.dport_enabled =
3483 (mid_init_cb->init_cb.firmware_options_1 & BIT_7) != 0;
3484 ql_dbg(ql_dbg_init, vha, 0x0191, "DPORT Support: %s.\n",
3485 (ha->flags.dport_enabled) ? "enabled" : "disabled");
3486 /* FA-WWPN Status */
2486c627 3487 ha->flags.fawwpn_enabled =
40f3862b 3488 (mid_init_cb->init_cb.firmware_options_1 & BIT_6) != 0;
83548fe2 3489 ql_dbg(ql_dbg_init, vha, 0x00bc, "FA-WWPN Support: %s.\n",
2486c627 3490 (ha->flags.fawwpn_enabled) ? "enabled" : "disabled");
24a08138 3491 }
2c3dfe3f 3492
e315cd28 3493 rval = qla2x00_init_firmware(vha, ha->init_cb_size);
8ae6d9c7 3494next_check:
1da177e4 3495 if (rval) {
7c3df132
SK		 3496 ql_log(ql_log_fatal, vha, 0x00d2,
3497 "Init Firmware **** FAILED ****.\n");
1da177e4 3498 } else {
7c3df132
SK		 3499 ql_dbg(ql_dbg_init, vha, 0x00d3,
3500 "Init Firmware -- success.\n");
4b60c827 3501 QLA_FW_STARTED(ha);
1da177e4
LT		 3502 }
3503
3504 return (rval);
3505}
3506
3507/**
3508 * qla2x00_fw_ready() - Waits for firmware ready.
3509 * @ha: HA context
3510 *
3511 * Returns 0 on success.
3512 */
3513static int
e315cd28 3514qla2x00_fw_ready(scsi_qla_host_t *vha)
1da177e4
LT		 3515{
3516 int rval;
4d4df193 3517 unsigned long wtime, mtime, cs84xx_time;
1da177e4
LT		 3518 uint16_t min_wait; /* Minimum wait time if loop is down */
3519 uint16_t wait_time; /* Wait time if loop is coming ready */
b5a340dd 3520 uint16_t state[6];
e315cd28 3521 struct qla_hw_data *ha = vha->hw;
1da177e4 3522
8ae6d9c7
GM		 3523 if (IS_QLAFX00(vha->hw))
3524 return qlafx00_fw_ready(vha);
3525
1da177e4
LT		 3526 rval = QLA_SUCCESS;
3527
33461491
CD		 3528 /* Time to wait for loop down */
3529 if (IS_P3P_TYPE(ha))
3530 min_wait = 30;
3531 else
3532 min_wait = 20;
1da177e4
LT		 3533
3534 /*
3535 * Firmware should take at most one RATOV to login, plus 5 seconds for
3536 * our own processing.
3537 */
3538 if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) {
3539 wait_time = min_wait;
3540 }
3541
3542 /* Min wait time if loop down */
3543 mtime = jiffies + (min_wait * HZ);
3544
3545 /* wait time before firmware ready */
3546 wtime = jiffies + (wait_time * HZ);
3547
3548 /* Wait for ISP to finish LIP */
e315cd28 3549 if (!vha->flags.init_done)
7c3df132
SK		 3550 ql_log(ql_log_info, vha, 0x801e,
3551 "Waiting for LIP to complete.\n");
1da177e4
LT		 3552
3553 do {
5b939038 3554 memset(state, -1, sizeof(state));
e315cd28 3555 rval = qla2x00_get_firmware_state(vha, state);
1da177e4 3556 if (rval == QLA_SUCCESS) {
4d4df193 3557 if (state[0] < FSTATE_LOSS_OF_SYNC) {
e315cd28 3558 vha->device_flags &= ~DFLG_NO_CABLE;
1da177e4 3559 }
4d4df193 3560 if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) {
7c3df132
SK		 3561 ql_dbg(ql_dbg_taskm, vha, 0x801f,
3562 "fw_state=%x 84xx=%x.\n", state[0],
3563 state[2]);
4d4df193
HK		 3564 if ((state[2] & FSTATE_LOGGED_IN) &&
3565 (state[2] & FSTATE_WAITING_FOR_VERIFY)) {
7c3df132
SK		 3566 ql_dbg(ql_dbg_taskm, vha, 0x8028,
3567 "Sending verify iocb.\n");
4d4df193
HK		 3568
3569 cs84xx_time = jiffies;
e315cd28 3570 rval = qla84xx_init_chip(vha);
7c3df132
SK		 3571 if (rval != QLA_SUCCESS) {
3572 ql_log(ql_log_warn,
cfb0919c 3573 vha, 0x8007,
7c3df132 3574 "Init chip failed.\n");
4d4df193 3575 break;
7c3df132 3576 }
4d4df193
HK		 3577
3578 /* Add time taken to initialize. */
3579 cs84xx_time = jiffies - cs84xx_time;
3580 wtime += cs84xx_time;
3581 mtime += cs84xx_time;
cfb0919c 3582 ql_dbg(ql_dbg_taskm, vha, 0x8008,
7c3df132
SK		 3583 "Increasing wait time by %ld. "
3584 "New time %ld.\n", cs84xx_time,
3585 wtime);
4d4df193
HK		 3586 }
3587 } else if (state[0] == FSTATE_READY) {
7c3df132
SK		 3588 ql_dbg(ql_dbg_taskm, vha, 0x8037,
3589 "F/W Ready - OK.\n");
1da177e4 3590
e315cd28 3591 qla2x00_get_retry_cnt(vha, &ha->retry_count,
1da177e4
LT		 3592 &ha->login_timeout, &ha->r_a_tov);
3593
3594 rval = QLA_SUCCESS;
3595 break;
3596 }
3597
3598 rval = QLA_FUNCTION_FAILED;
3599
e315cd28 3600 if (atomic_read(&vha->loop_down_timer) &&
4d4df193 3601 state[0] != FSTATE_READY) {
1da177e4 3602 /* Loop down. Timeout on min_wait for states
fa2a1ce5
AV		 3603 * other than Wait for Login.
3604 */
1da177e4 3605 if (time_after_eq(jiffies, mtime)) {
7c3df132 3606 ql_log(ql_log_info, vha, 0x8038,
1da177e4
LT		 3607 "Cable is unplugged...\n");
3608
e315cd28 3609 vha->device_flags |= DFLG_NO_CABLE;
1da177e4
LT		 3610 break;
3611 }
3612 }
3613 } else {
3614 /* Mailbox cmd failed. Timeout on min_wait. */
cdbb0a4f 3615 if (time_after_eq(jiffies, mtime) ||
7190575f 3616 ha->flags.isp82xx_fw_hung)
1da177e4
LT		 3617 break;
3618 }
3619
3620 if (time_after_eq(jiffies, wtime))
3621 break;
3622
3623 /* Delay for a while */
3624 msleep(500);
1da177e4
LT		 3625 } while (1);
3626
7c3df132 3627 ql_dbg(ql_dbg_taskm, vha, 0x803a,
b5a340dd
JC		 3628 "fw_state=%x (%x, %x, %x, %x %x) curr time=%lx.\n", state[0],
3629 state[1], state[2], state[3], state[4], state[5], jiffies);
1da177e4 3630
cfb0919c 3631 if (rval && !(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132
SK		 3632 ql_log(ql_log_warn, vha, 0x803b,
3633 "Firmware ready **** FAILED ****.\n");
1da177e4
LT		 3634 }
3635
3636 return (rval);
3637}
3638
3639/*
3640* qla2x00_configure_hba
3641* Setup adapter context.
3642*
3643* Input:
3644* ha = adapter state pointer.
3645*
3646* Returns:
3647* 0 = success
3648*
3649* Context:
3650* Kernel context.
3651*/
3652static int
e315cd28 3653qla2x00_configure_hba(scsi_qla_host_t *vha)
1da177e4
LT		 3654{
3655 int rval;
3656 uint16_t loop_id;
3657 uint16_t topo;
2c3dfe3f 3658 uint16_t sw_cap;
1da177e4
LT		 3659 uint8_t al_pa;
3660 uint8_t area;
3661 uint8_t domain;
3662 char connect_type[22];
e315cd28 3663 struct qla_hw_data *ha = vha->hw;
61e1b269 3664 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
482c9dc7 3665 port_id_t id;
1da177e4
LT		 3666
3667 /* Get host addresses. */
e315cd28 3668 rval = qla2x00_get_adapter_id(vha,
2c3dfe3f 3669 &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
1da177e4 3670 if (rval != QLA_SUCCESS) {
e315cd28 3671 if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
6246b8a1 3672 IS_CNA_CAPABLE(ha) ||
33135aa2 3673 (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
7c3df132
SK		 3674 ql_dbg(ql_dbg_disc, vha, 0x2008,
3675 "Loop is in a transition state.\n");
33135aa2 3676 } else {
7c3df132
SK		 3677 ql_log(ql_log_warn, vha, 0x2009,
3678 "Unable to get host loop ID.\n");
61e1b269
JC		 3679 if (IS_FWI2_CAPABLE(ha) && (vha == base_vha) &&
3680 (rval == QLA_COMMAND_ERROR && loop_id == 0x1b)) {
3681 ql_log(ql_log_warn, vha, 0x1151,
3682 "Doing link init.\n");
3683 if (qla24xx_link_initialize(vha) == QLA_SUCCESS)
3684 return rval;
3685 }
e315cd28 3686 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
33135aa2 3687 }
1da177e4
LT		 3688 return (rval);
3689 }
3690
3691 if (topo == 4) {
7c3df132
SK		 3692 ql_log(ql_log_info, vha, 0x200a,
3693 "Cannot get topology - retrying.\n");
1da177e4
LT		 3694 return (QLA_FUNCTION_FAILED);
3695 }
3696
e315cd28 3697 vha->loop_id = loop_id;
1da177e4
LT		 3698
3699 /* initialize */
3700 ha->min_external_loopid = SNS_FIRST_LOOP_ID;
3701 ha->operating_mode = LOOP;
2c3dfe3f 3702 ha->switch_cap = 0;
1da177e4
LT		 3703
3704 switch (topo) {
3705 case 0:
7c3df132 3706 ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n");
1da177e4
LT		 3707 ha->current_topology = ISP_CFG_NL;
3708 strcpy(connect_type, "(Loop)");
3709 break;
3710
3711 case 1:
7c3df132 3712 ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n");
2c3dfe3f 3713 ha->switch_cap = sw_cap;
1da177e4
LT		 3714 ha->current_topology = ISP_CFG_FL;
3715 strcpy(connect_type, "(FL_Port)");
3716 break;
3717
3718 case 2:
7c3df132 3719 ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n");
1da177e4
LT		 3720 ha->operating_mode = P2P;
3721 ha->current_topology = ISP_CFG_N;
3722 strcpy(connect_type, "(N_Port-to-N_Port)");
3723 break;
3724
3725 case 3:
7c3df132 3726 ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n");
2c3dfe3f 3727 ha->switch_cap = sw_cap;
1da177e4
LT		 3728 ha->operating_mode = P2P;
3729 ha->current_topology = ISP_CFG_F;
3730 strcpy(connect_type, "(F_Port)");
3731 break;
3732
3733 default:
7c3df132
SK		 3734 ql_dbg(ql_dbg_disc, vha, 0x200f,
3735 "HBA in unknown topology %x, using NL.\n", topo);
1da177e4
LT		 3736 ha->current_topology = ISP_CFG_NL;
3737 strcpy(connect_type, "(Loop)");
3738 break;
3739 }
3740
3741 /* Save Host port and loop ID. */
3742 /* byte order - Big Endian */
482c9dc7
QT		 3743 id.b.domain = domain;
3744 id.b.area = area;
3745 id.b.al_pa = al_pa;
3746 id.b.rsvd_1 = 0;
3747 qlt_update_host_map(vha, id);
2d70c103 3748
e315cd28 3749 if (!vha->flags.init_done)
7c3df132
SK		 3750 ql_log(ql_log_info, vha, 0x2010,
3751 "Topology - %s, Host Loop address 0x%x.\n",
e315cd28 3752 connect_type, vha->loop_id);
1da177e4 3753
1da177e4
LT		 3754 return(rval);
3755}
3756
a9083016 3757inline void
e315cd28
AC		 3758qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
3759 char *def)
9bb9fcf2
AV		 3760{
3761 char *st, *en;
3762 uint16_t index;
e315cd28 3763 struct qla_hw_data *ha = vha->hw;
ab671149 3764 int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
6246b8a1 3765 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha);
9bb9fcf2
AV		 3766
3767 if (memcmp(model, BINZERO, len) != 0) {
3768 strncpy(ha->model_number, model, len);
3769 st = en = ha->model_number;
3770 en += len - 1;
3771 while (en > st) {
3772 if (*en != 0x20 && *en != 0x00)
3773 break;
3774 *en-- = '\0';
3775 }
3776
3777 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 3778 if (use_tbl &&
3779 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2 3780 index < QLA_MODEL_NAMES)
1ee27146
JC		 3781 strncpy(ha->model_desc,
3782 qla2x00_model_name[index * 2 + 1],
3783 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 3784 } else {
3785 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 3786 if (use_tbl &&
3787 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2
AV		 3788 index < QLA_MODEL_NAMES) {
3789 strcpy(ha->model_number,
3790 qla2x00_model_name[index * 2]);
1ee27146
JC		 3791 strncpy(ha->model_desc,
3792 qla2x00_model_name[index * 2 + 1],
3793 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 3794 } else {
3795 strcpy(ha->model_number, def);
3796 }
3797 }
1ee27146 3798 if (IS_FWI2_CAPABLE(ha))
e315cd28 3799 qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc,
1ee27146 3800 sizeof(ha->model_desc));
9bb9fcf2
AV		 3801}
3802
4e08df3f
DM		 3803/* On sparc systems, obtain port and node WWN from firmware
3804 * properties.
3805 */
e315cd28 3806static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv)
4e08df3f
DM		 3807{
3808#ifdef CONFIG_SPARC
e315cd28 3809 struct qla_hw_data *ha = vha->hw;
4e08df3f 3810 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 3811 struct device_node *dp = pci_device_to_OF_node(pdev);
3812 const u8 *val;
4e08df3f
DM		 3813 int len;
3814
3815 val = of_get_property(dp, "port-wwn", &len);
3816 if (val && len >= WWN_SIZE)
3817 memcpy(nv->port_name, val, WWN_SIZE);
3818
3819 val = of_get_property(dp, "node-wwn", &len);
3820 if (val && len >= WWN_SIZE)
3821 memcpy(nv->node_name, val, WWN_SIZE);
3822#endif
3823}
3824
1da177e4
LT		 3825/*
3826* NVRAM configuration for ISP 2xxx
3827*
3828* Input:
3829* ha = adapter block pointer.
3830*
3831* Output:
3832* initialization control block in response_ring
3833* host adapters parameters in host adapter block
3834*
3835* Returns:
3836* 0 = success.
3837*/
abbd8870 3838int
e315cd28 3839qla2x00_nvram_config(scsi_qla_host_t *vha)
1da177e4 3840{
4e08df3f 3841 int rval;
0107109e
AV		 3842 uint8_t chksum = 0;
3843 uint16_t cnt;
3844 uint8_t *dptr1, *dptr2;
e315cd28 3845 struct qla_hw_data *ha = vha->hw;
0107109e 3846 init_cb_t *icb = ha->init_cb;
281afe19
SJ		 3847 nvram_t *nv = ha->nvram;
3848 uint8_t *ptr = ha->nvram;
3d71644c 3849 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 3850
4e08df3f
DM		 3851 rval = QLA_SUCCESS;
3852
1da177e4 3853 /* Determine NVRAM starting address. */
0107109e 3854 ha->nvram_size = sizeof(nvram_t);
1da177e4
LT		 3855 ha->nvram_base = 0;
3856 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
3857 if ((RD_REG_WORD(&reg->ctrl_status) >> 14) == 1)
3858 ha->nvram_base = 0x80;
3859
3860 /* Get NVRAM data and calculate checksum. */
e315cd28 3861 ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size);
0107109e
AV		 3862 for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++)
3863 chksum += *ptr++;
1da177e4 3864
7c3df132
SK		 3865 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
3866 "Contents of NVRAM.\n");
3867 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
3868 (uint8_t *)nv, ha->nvram_size);
1da177e4
LT		 3869
3870 /* Bad NVRAM data, set defaults parameters. */
3871 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' ||
3872 nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) {
3873 /* Reset NVRAM data. */
7c3df132 3874 ql_log(ql_log_warn, vha, 0x0064,
9e336520 3875 "Inconsistent NVRAM "
7c3df132
SK		 3876 "detected: checksum=0x%x id=%c version=0x%x.\n",
3877 chksum, nv->id[0], nv->nvram_version);
3878 ql_log(ql_log_warn, vha, 0x0065,
3879 "Falling back to "
3880 "functioning (yet invalid -- WWPN) defaults.\n");
4e08df3f
DM		 3881
3882 /*
3883 * Set default initialization control block.
3884 */
3885 memset(nv, 0, ha->nvram_size);
3886 nv->parameter_block_version = ICB_VERSION;
3887
3888 if (IS_QLA23XX(ha)) {
3889 nv->firmware_options[0] = BIT_2 | BIT_1;
3890 nv->firmware_options[1] = BIT_7 | BIT_5;
3891 nv->add_firmware_options[0] = BIT_5;
3892 nv->add_firmware_options[1] = BIT_5 | BIT_4;
98aee70d 3893 nv->frame_payload_size = 2048;
4e08df3f
DM		 3894 nv->special_options[1] = BIT_7;
3895 } else if (IS_QLA2200(ha)) {
3896 nv->firmware_options[0] = BIT_2 | BIT_1;
3897 nv->firmware_options[1] = BIT_7 | BIT_5;
3898 nv->add_firmware_options[0] = BIT_5;
3899 nv->add_firmware_options[1] = BIT_5 | BIT_4;
98aee70d 3900 nv->frame_payload_size = 1024;
4e08df3f
DM		 3901 } else if (IS_QLA2100(ha)) {
3902 nv->firmware_options[0] = BIT_3 | BIT_1;
3903 nv->firmware_options[1] = BIT_5;
98aee70d 3904 nv->frame_payload_size = 1024;
4e08df3f
DM		 3905 }
3906
ad950360
BVA		 3907 nv->max_iocb_allocation = cpu_to_le16(256);
3908 nv->execution_throttle = cpu_to_le16(16);
4e08df3f
DM		 3909 nv->retry_count = 8;
3910 nv->retry_delay = 1;
3911
3912 nv->port_name[0] = 33;
3913 nv->port_name[3] = 224;
3914 nv->port_name[4] = 139;
3915
e315cd28 3916 qla2xxx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 3917
3918 nv->login_timeout = 4;
3919
3920 /*
3921 * Set default host adapter parameters
3922 */
3923 nv->host_p[1] = BIT_2;
3924 nv->reset_delay = 5;
3925 nv->port_down_retry_count = 8;
ad950360 3926 nv->max_luns_per_target = cpu_to_le16(8);
4e08df3f
DM		 3927 nv->link_down_timeout = 60;
3928
3929 rval = 1;
1da177e4
LT		 3930 }
3931
3932#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
3933 /*
3934 * The SN2 does not provide BIOS emulation which means you can't change
3935 * potentially bogus BIOS settings. Force the use of default settings
3936 * for link rate and frame size. Hope that the rest of the settings
3937 * are valid.
3938 */
3939 if (ia64_platform_is("sn2")) {
98aee70d 3940 nv->frame_payload_size = 2048;
1da177e4
LT		 3941 if (IS_QLA23XX(ha))
3942 nv->special_options[1] = BIT_7;
3943 }
3944#endif
3945
3946 /* Reset Initialization control block */
0107109e 3947 memset(icb, 0, ha->init_cb_size);
1da177e4
LT		 3948
3949 /*
3950 * Setup driver NVRAM options.
3951 */
3952 nv->firmware_options[0] |= (BIT_6 | BIT_1);
3953 nv->firmware_options[0] &= ~(BIT_5 | BIT_4);
3954 nv->firmware_options[1] |= (BIT_5 | BIT_0);
3955 nv->firmware_options[1] &= ~BIT_4;
3956
3957 if (IS_QLA23XX(ha)) {
3958 nv->firmware_options[0] |= BIT_2;
3959 nv->firmware_options[0] &= ~BIT_3;
2d70c103 3960 nv->special_options[0] &= ~BIT_6;
0107109e 3961 nv->add_firmware_options[1] |= BIT_5 | BIT_4;
1da177e4
LT		 3962
3963 if (IS_QLA2300(ha)) {
3964 if (ha->fb_rev == FPM_2310) {
3965 strcpy(ha->model_number, "QLA2310");
3966 } else {
3967 strcpy(ha->model_number, "QLA2300");
3968 }
3969 } else {
e315cd28 3970 qla2x00_set_model_info(vha, nv->model_number,
9bb9fcf2 3971 sizeof(nv->model_number), "QLA23xx");
1da177e4
LT		 3972 }
3973 } else if (IS_QLA2200(ha)) {
3974 nv->firmware_options[0] |= BIT_2;
3975 /*
3976 * 'Point-to-point preferred, else loop' is not a safe
3977 * connection mode setting.
3978 */
3979 if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
3980 (BIT_5 | BIT_4)) {
3981 /* Force 'loop preferred, else point-to-point'. */
3982 nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
3983 nv->add_firmware_options[0] |= BIT_5;
3984 }
3985 strcpy(ha->model_number, "QLA22xx");
3986 } else /*if (IS_QLA2100(ha))*/ {
3987 strcpy(ha->model_number, "QLA2100");
3988 }
3989
3990 /*
3991 * Copy over NVRAM RISC parameter block to initialization control block.
3992 */
3993 dptr1 = (uint8_t *)icb;
3994 dptr2 = (uint8_t *)&nv->parameter_block_version;
3995 cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;
3996 while (cnt--)
3997 *dptr1++ = *dptr2++;
3998
3999 /* Copy 2nd half. */
4000 dptr1 = (uint8_t *)icb->add_firmware_options;
4001 cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;
4002 while (cnt--)
4003 *dptr1++ = *dptr2++;
4004
5341e868
AV		 4005 /* Use alternate WWN? */
4006 if (nv->host_p[1] & BIT_7) {
4007 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
4008 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
4009 }
4010
1da177e4
LT		 4011 /* Prepare nodename */
4012 if ((icb->firmware_options[1] & BIT_6) == 0) {
4013 /*
4014 * Firmware will apply the following mask if the nodename was
4015 * not provided.
4016 */
4017 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
4018 icb->node_name[0] &= 0xF0;
4019 }
4020
4021 /*
4022 * Set host adapter parameters.
4023 */
3ce8866c
SK		 4024
4025 /*
4026 * BIT_7 in the host-parameters section allows for modification to
4027 * internal driver logging.
4028 */
0181944f 4029 if (nv->host_p[0] & BIT_7)
cfb0919c 4030 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
1da177e4
LT		 4031 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
4032 /* Always load RISC code on non ISP2[12]00 chips. */
4033 if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
4034 ha->flags.disable_risc_code_load = 0;
4035 ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0);
4036 ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
4037 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
06c22bd1 4038 ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
d4c760c2 4039 ha->flags.disable_serdes = 0;
1da177e4
LT		 4040
4041 ha->operating_mode =
4042 (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
4043
4044 memcpy(ha->fw_seriallink_options, nv->seriallink_options,
4045 sizeof(ha->fw_seriallink_options));
4046
4047 /* save HBA serial number */
4048 ha->serial0 = icb->port_name[5];
4049 ha->serial1 = icb->port_name[6];
4050 ha->serial2 = icb->port_name[7];
e315cd28
AC		 4051 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
4052 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
1da177e4 4053
ad950360 4054 icb->execution_throttle = cpu_to_le16(0xFFFF);
1da177e4
LT		 4055
4056 ha->retry_count = nv->retry_count;
4057
4058 /* Set minimum login_timeout to 4 seconds. */
5b91490e 4059 if (nv->login_timeout != ql2xlogintimeout)
1da177e4
LT		 4060 nv->login_timeout = ql2xlogintimeout;
4061 if (nv->login_timeout < 4)
4062 nv->login_timeout = 4;
4063 ha->login_timeout = nv->login_timeout;
1da177e4 4064
00a537b8
AV		 4065 /* Set minimum RATOV to 100 tenths of a second. */
4066 ha->r_a_tov = 100;
1da177e4 4067
1da177e4
LT		 4068 ha->loop_reset_delay = nv->reset_delay;
4069
1da177e4
LT		 4070 /* Link Down Timeout = 0:
4071 *
4072 * When Port Down timer expires we will start returning
4073 * I/O's to OS with "DID_NO_CONNECT".
4074 *
4075 * Link Down Timeout != 0:
4076 *
4077 * The driver waits for the link to come up after link down
4078 * before returning I/Os to OS with "DID_NO_CONNECT".
fa2a1ce5 4079 */
1da177e4
LT		 4080 if (nv->link_down_timeout == 0) {
4081 ha->loop_down_abort_time =
354d6b21 4082 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
1da177e4
LT		 4083 } else {
4084 ha->link_down_timeout = nv->link_down_timeout;
4085 ha->loop_down_abort_time =
4086 (LOOP_DOWN_TIME - ha->link_down_timeout);
fa2a1ce5 4087 }
1da177e4 4088
1da177e4
LT		 4089 /*
4090 * Need enough time to try and get the port back.
4091 */
4092 ha->port_down_retry_count = nv->port_down_retry_count;
4093 if (qlport_down_retry)
4094 ha->port_down_retry_count = qlport_down_retry;
4095 /* Set login_retry_count */
4096 ha->login_retry_count = nv->retry_count;
4097 if (ha->port_down_retry_count == nv->port_down_retry_count &&
4098 ha->port_down_retry_count > 3)
4099 ha->login_retry_count = ha->port_down_retry_count;
4100 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
4101 ha->login_retry_count = ha->port_down_retry_count;
4102 if (ql2xloginretrycount)
4103 ha->login_retry_count = ql2xloginretrycount;
4104
ad950360 4105 icb->lun_enables = cpu_to_le16(0);
1da177e4
LT		 4106 icb->command_resource_count = 0;
4107 icb->immediate_notify_resource_count = 0;
ad950360 4108 icb->timeout = cpu_to_le16(0);
1da177e4
LT		 4109
4110 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
4111 /* Enable RIO */
4112 icb->firmware_options[0] &= ~BIT_3;
4113 icb->add_firmware_options[0] &=
4114 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
4115 icb->add_firmware_options[0] |= BIT_2;
4116 icb->response_accumulation_timer = 3;
4117 icb->interrupt_delay_timer = 5;
4118
e315cd28 4119 vha->flags.process_response_queue = 1;
1da177e4 4120 } else {
4fdfefe5 4121 /* Enable ZIO. */
e315cd28 4122 if (!vha->flags.init_done) {
4fdfefe5
AV		 4123 ha->zio_mode = icb->add_firmware_options[0] &
4124 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
4125 ha->zio_timer = icb->interrupt_delay_timer ?
4126 icb->interrupt_delay_timer: 2;
4127 }
1da177e4
LT		 4128 icb->add_firmware_options[0] &=
4129 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
e315cd28 4130 vha->flags.process_response_queue = 0;
4fdfefe5 4131 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d
AV		 4132 ha->zio_mode = QLA_ZIO_MODE_6;
4133
7c3df132 4134 ql_log(ql_log_info, vha, 0x0068,
4fdfefe5
AV		 4135 "ZIO mode %d enabled; timer delay (%d us).\n",
4136 ha->zio_mode, ha->zio_timer * 100);
1da177e4 4137
4fdfefe5
AV		 4138 icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;
4139 icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;
e315cd28 4140 vha->flags.process_response_queue = 1;
1da177e4
LT		 4141 }
4142 }
4143
4e08df3f 4144 if (rval) {
7c3df132
SK		 4145 ql_log(ql_log_warn, vha, 0x0069,
4146 "NVRAM configuration failed.\n");
4e08df3f
DM		 4147 }
4148 return (rval);
1da177e4
LT		 4149}
4150
19a7b4ae
JSEC		 4151static void
4152qla2x00_rport_del(void *data)
4153{
4154 fc_port_t *fcport = data;
d97994dc 4155 struct fc_rport *rport;
044d78e1 4156 unsigned long flags;
d97994dc 4157
044d78e1 4158 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
ac280b67 4159 rport = fcport->drport ? fcport->drport: fcport->rport;
d97994dc 4160 fcport->drport = NULL;
044d78e1 4161 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
726b8548 4162 if (rport) {
83548fe2
QT		 4163 ql_dbg(ql_dbg_disc, fcport->vha, 0x210b,
4164 "%s %8phN. rport %p roles %x\n",
4165 __func__, fcport->port_name, rport,
4166 rport->roles);
726b8548 4167
d97994dc 4168 fc_remote_port_delete(rport);
726b8548 4169 }
19a7b4ae
JSEC		 4170}
4171
1da177e4
LT		 4172/**
4173 * qla2x00_alloc_fcport() - Allocate a generic fcport.
4174 * @ha: HA context
4175 * @flags: allocation flags
4176 *
4177 * Returns a pointer to the allocated fcport, or NULL, if none available.
4178 */
9a069e19 4179fc_port_t *
e315cd28 4180qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags)
1da177e4
LT		 4181{
4182 fc_port_t *fcport;
4183
bbfbbbc1
MK		 4184 fcport = kzalloc(sizeof(fc_port_t), flags);
4185 if (!fcport)
4186 return NULL;
1da177e4
LT		 4187
4188 /* Setup fcport template structure. */
e315cd28 4189 fcport->vha = vha;
1da177e4
LT		 4190 fcport->port_type = FCT_UNKNOWN;
4191 fcport->loop_id = FC_NO_LOOP_ID;
ec426e10 4192 qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
ad3e0eda 4193 fcport->supported_classes = FC_COS_UNSPECIFIED;
1da177e4 4194
726b8548
QT		 4195 fcport->ct_desc.ct_sns = dma_alloc_coherent(&vha->hw->pdev->dev,
4196 sizeof(struct ct_sns_pkt), &fcport->ct_desc.ct_sns_dma,
6cb3216a 4197 flags);
726b8548
QT		 4198 fcport->disc_state = DSC_DELETED;
4199 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL;
4200 fcport->deleted = QLA_SESS_DELETED;
4201 fcport->login_retry = vha->hw->login_retry_count;
4202 fcport->login_retry = 5;
4203 fcport->logout_on_delete = 1;
4204
4205 if (!fcport->ct_desc.ct_sns) {
83548fe2 4206 ql_log(ql_log_warn, vha, 0xd049,
726b8548
QT		 4207 "Failed to allocate ct_sns request.\n");
4208 kfree(fcport);
4209 fcport = NULL;
4210 }
4211 INIT_WORK(&fcport->del_work, qla24xx_delete_sess_fn);
4212 INIT_LIST_HEAD(&fcport->gnl_entry);
4213 INIT_LIST_HEAD(&fcport->list);
4214
bbfbbbc1 4215 return fcport;
1da177e4
LT		 4216}
4217
726b8548
QT		 4218void
4219qla2x00_free_fcport(fc_port_t *fcport)
4220{
4221 if (fcport->ct_desc.ct_sns) {
4222 dma_free_coherent(&fcport->vha->hw->pdev->dev,
4223 sizeof(struct ct_sns_pkt), fcport->ct_desc.ct_sns,
4224 fcport->ct_desc.ct_sns_dma);
4225
4226 fcport->ct_desc.ct_sns = NULL;
4227 }
4228 kfree(fcport);
4229}
4230
1da177e4
LT		 4231/*
4232 * qla2x00_configure_loop
4233 * Updates Fibre Channel Device Database with what is actually on loop.
4234 *
4235 * Input:
4236 * ha = adapter block pointer.
4237 *
4238 * Returns:
4239 * 0 = success.
4240 * 1 = error.
4241 * 2 = database was full and device was not configured.
4242 */
4243static int
e315cd28 4244qla2x00_configure_loop(scsi_qla_host_t *vha)
1da177e4
LT		 4245{
4246 int rval;
4247 unsigned long flags, save_flags;
e315cd28 4248 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 4249 rval = QLA_SUCCESS;
4250
4251 /* Get Initiator ID */
e315cd28
AC		 4252 if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) {
4253 rval = qla2x00_configure_hba(vha);
1da177e4 4254 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4255 ql_dbg(ql_dbg_disc, vha, 0x2013,
4256 "Unable to configure HBA.\n");
1da177e4
LT		 4257 return (rval);
4258 }
4259 }
4260
e315cd28 4261 save_flags = flags = vha->dpc_flags;
7c3df132
SK		 4262 ql_dbg(ql_dbg_disc, vha, 0x2014,
4263 "Configure loop -- dpc flags = 0x%lx.\n", flags);
1da177e4
LT		 4264
4265 /*
4266 * If we have both an RSCN and PORT UPDATE pending then handle them
4267 * both at the same time.
4268 */
e315cd28
AC		 4269 clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
4270 clear_bit(RSCN_UPDATE, &vha->dpc_flags);
1da177e4 4271
3064ff39
MH		 4272 qla2x00_get_data_rate(vha);
4273
1da177e4
LT		 4274 /* Determine what we need to do */
4275 if (ha->current_topology == ISP_CFG_FL &&
4276 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
4277
1da177e4
LT		 4278 set_bit(RSCN_UPDATE, &flags);
4279
4280 } else if (ha->current_topology == ISP_CFG_F &&
4281 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
4282
1da177e4
LT		 4283 set_bit(RSCN_UPDATE, &flags);
4284 clear_bit(LOCAL_LOOP_UPDATE, &flags);
21333b48
AV		 4285
4286 } else if (ha->current_topology == ISP_CFG_N) {
4287 clear_bit(RSCN_UPDATE, &flags);
41dc529a
QT		 4288 } else if (ha->current_topology == ISP_CFG_NL) {
4289 clear_bit(RSCN_UPDATE, &flags);
4290 set_bit(LOCAL_LOOP_UPDATE, &flags);
e315cd28 4291 } else if (!vha->flags.online ||
1da177e4 4292 (test_bit(ABORT_ISP_ACTIVE, &flags))) {
1da177e4
LT		 4293 set_bit(RSCN_UPDATE, &flags);
4294 set_bit(LOCAL_LOOP_UPDATE, &flags);
4295 }
4296
4297 if (test_bit(LOCAL_LOOP_UPDATE, &flags)) {
7c3df132
SK		 4298 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
4299 ql_dbg(ql_dbg_disc, vha, 0x2015,
4300 "Loop resync needed, failing.\n");
1da177e4 4301 rval = QLA_FUNCTION_FAILED;
642ef983 4302 } else
e315cd28 4303 rval = qla2x00_configure_local_loop(vha);
1da177e4
LT		 4304 }
4305
4306 if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
7c3df132 4307 if (LOOP_TRANSITION(vha)) {
83548fe2 4308 ql_dbg(ql_dbg_disc, vha, 0x2099,
7c3df132 4309 "Needs RSCN update and loop transition.\n");
1da177e4 4310 rval = QLA_FUNCTION_FAILED;
7c3df132 4311 }
e315cd28
AC		 4312 else
4313 rval = qla2x00_configure_fabric(vha);
1da177e4
LT		 4314 }
4315
4316 if (rval == QLA_SUCCESS) {
e315cd28
AC		 4317 if (atomic_read(&vha->loop_down_timer) ||
4318 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4
LT		 4319 rval = QLA_FUNCTION_FAILED;
4320 } else {
e315cd28 4321 atomic_set(&vha->loop_state, LOOP_READY);
7c3df132
SK		 4322 ql_dbg(ql_dbg_disc, vha, 0x2069,
4323 "LOOP READY.\n");
ec7193e2 4324 ha->flags.fw_init_done = 1;
3bb67df5
DKU		 4325
4326 /*
4327 * Process any ATIO queue entries that came in
4328 * while we weren't online.
4329 */
ead03855
QT		 4330 if (qla_tgt_mode_enabled(vha) ||
4331 qla_dual_mode_enabled(vha)) {
3bb67df5
DKU		 4332 if (IS_QLA27XX(ha) || IS_QLA83XX(ha)) {
4333 spin_lock_irqsave(&ha->tgt.atio_lock,
4334 flags);
4335 qlt_24xx_process_atio_queue(vha, 0);
4336 spin_unlock_irqrestore(
4337 &ha->tgt.atio_lock, flags);
4338 } else {
4339 spin_lock_irqsave(&ha->hardware_lock,
4340 flags);
4341 qlt_24xx_process_atio_queue(vha, 1);
4342 spin_unlock_irqrestore(
4343 &ha->hardware_lock, flags);
4344 }
4345 }
1da177e4
LT		 4346 }
4347 }
4348
4349 if (rval) {
7c3df132
SK		 4350 ql_dbg(ql_dbg_disc, vha, 0x206a,
4351 "%s *** FAILED ***.\n", __func__);
1da177e4 4352 } else {
7c3df132
SK		 4353 ql_dbg(ql_dbg_disc, vha, 0x206b,
4354 "%s: exiting normally.\n", __func__);
1da177e4
LT		 4355 }
4356
cc3ef7bc 4357 /* Restore state if a resync event occurred during processing */
e315cd28 4358 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4 4359 if (test_bit(LOCAL_LOOP_UPDATE, &save_flags))
e315cd28 4360 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
f4658b6c 4361 if (test_bit(RSCN_UPDATE, &save_flags)) {
e315cd28 4362 set_bit(RSCN_UPDATE, &vha->dpc_flags);
f4658b6c 4363 }
1da177e4
LT		 4364 }
4365
4366 return (rval);
4367}
4368
4369
4370
4371/*
4372 * qla2x00_configure_local_loop
4373 * Updates Fibre Channel Device Database with local loop devices.
4374 *
4375 * Input:
4376 * ha = adapter block pointer.
4377 *
4378 * Returns:
4379 * 0 = success.
4380 */
4381static int
e315cd28 4382qla2x00_configure_local_loop(scsi_qla_host_t *vha)
1da177e4
LT		 4383{
4384 int rval, rval2;
4385 int found_devs;
4386 int found;
4387 fc_port_t *fcport, *new_fcport;
4388
4389 uint16_t index;
4390 uint16_t entries;
4391 char *id_iter;
4392 uint16_t loop_id;
4393 uint8_t domain, area, al_pa;
e315cd28 4394 struct qla_hw_data *ha = vha->hw;
41dc529a 4395 unsigned long flags;
1da177e4
LT		 4396
4397 found_devs = 0;
4398 new_fcport = NULL;
642ef983 4399 entries = MAX_FIBRE_DEVICES_LOOP;
1da177e4 4400
1da177e4 4401 /* Get list of logged in devices. */
642ef983 4402 memset(ha->gid_list, 0, qla2x00_gid_list_size(ha));
e315cd28 4403 rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma,
1da177e4
LT		 4404 &entries);
4405 if (rval != QLA_SUCCESS)
4406 goto cleanup_allocation;
4407
83548fe2 4408 ql_dbg(ql_dbg_disc, vha, 0x2011,
7c3df132
SK		 4409 "Entries in ID list (%d).\n", entries);
4410 ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
4411 (uint8_t *)ha->gid_list,
4412 entries * sizeof(struct gid_list_info));
1da177e4
LT		 4413
4414 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 4415 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 4416 if (new_fcport == NULL) {
83548fe2 4417 ql_log(ql_log_warn, vha, 0x2012,
7c3df132 4418 "Memory allocation failed for fcport.\n");
1da177e4
LT		 4419 rval = QLA_MEMORY_ALLOC_FAILED;
4420 goto cleanup_allocation;
4421 }
4422 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
4423
4424 /*
4425 * Mark local devices that were present with FCF_DEVICE_LOST for now.
4426 */
e315cd28 4427 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 4428 if (atomic_read(&fcport->state) == FCS_ONLINE &&
4429 fcport->port_type != FCT_BROADCAST &&
4430 (fcport->flags & FCF_FABRIC_DEVICE) == 0) {
4431
83548fe2 4432 ql_dbg(ql_dbg_disc, vha, 0x2096,
7c3df132
SK		 4433 "Marking port lost loop_id=0x%04x.\n",
4434 fcport->loop_id);
1da177e4 4435
41dc529a 4436 qla2x00_mark_device_lost(vha, fcport, 0, 0);
1da177e4
LT		 4437 }
4438 }
4439
4440 /* Add devices to port list. */
4441 id_iter = (char *)ha->gid_list;
4442 for (index = 0; index < entries; index++) {
4443 domain = ((struct gid_list_info *)id_iter)->domain;
4444 area = ((struct gid_list_info *)id_iter)->area;
4445 al_pa = ((struct gid_list_info *)id_iter)->al_pa;
abbd8870 4446 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1da177e4
LT		 4447 loop_id = (uint16_t)
4448 ((struct gid_list_info *)id_iter)->loop_id_2100;
abbd8870 4449 else
1da177e4
LT		 4450 loop_id = le16_to_cpu(
4451 ((struct gid_list_info *)id_iter)->loop_id);
abbd8870 4452 id_iter += ha->gid_list_info_size;
1da177e4
LT		 4453
4454 /* Bypass reserved domain fields. */
4455 if ((domain & 0xf0) == 0xf0)
4456 continue;
4457
4458 /* Bypass if not same domain and area of adapter. */
f7d289f6 4459 if (area && domain &&
e315cd28 4460 (area != vha->d_id.b.area || domain != vha->d_id.b.domain))
1da177e4
LT		 4461 continue;
4462
4463 /* Bypass invalid local loop ID. */
4464 if (loop_id > LAST_LOCAL_LOOP_ID)
4465 continue;
4466
41dc529a 4467 memset(new_fcport->port_name, 0, WWN_SIZE);
370d550e 4468
1da177e4
LT		 4469 /* Fill in member data. */
4470 new_fcport->d_id.b.domain = domain;
4471 new_fcport->d_id.b.area = area;
4472 new_fcport->d_id.b.al_pa = al_pa;
4473 new_fcport->loop_id = loop_id;
41dc529a 4474
e315cd28 4475 rval2 = qla2x00_get_port_database(vha, new_fcport, 0);
1da177e4 4476 if (rval2 != QLA_SUCCESS) {
83548fe2 4477 ql_dbg(ql_dbg_disc, vha, 0x2097,
7c3df132
SK		 4478 "Failed to retrieve fcport information "
4479 "-- get_port_database=%x, loop_id=0x%04x.\n",
4480 rval2, new_fcport->loop_id);
83548fe2 4481 ql_dbg(ql_dbg_disc, vha, 0x2105,
7c3df132 4482 "Scheduling resync.\n");
e315cd28 4483 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4
LT		 4484 continue;
4485 }
4486
41dc529a 4487 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
1da177e4
LT		 4488 /* Check for matching device in port list. */
4489 found = 0;
4490 fcport = NULL;
e315cd28 4491 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 4492 if (memcmp(new_fcport->port_name, fcport->port_name,
4493 WWN_SIZE))
4494 continue;
4495
ddb9b126 4496 fcport->flags &= ~FCF_FABRIC_DEVICE;
1da177e4
LT		 4497 fcport->loop_id = new_fcport->loop_id;
4498 fcport->port_type = new_fcport->port_type;
4499 fcport->d_id.b24 = new_fcport->d_id.b24;
4500 memcpy(fcport->node_name, new_fcport->node_name,
4501 WWN_SIZE);
4502
41dc529a
QT		 4503 if (!fcport->login_succ) {
4504 vha->fcport_count++;
4505 fcport->login_succ = 1;
4506 fcport->disc_state = DSC_LOGIN_COMPLETE;
4507 }
4508
1da177e4
LT		 4509 found++;
4510 break;
4511 }
4512
4513 if (!found) {
4514 /* New device, add to fcports list. */
e315cd28 4515 list_add_tail(&new_fcport->list, &vha->vp_fcports);
1da177e4
LT		 4516
4517 /* Allocate a new replacement fcport. */
4518 fcport = new_fcport;
41dc529a
QT		 4519 if (!fcport->login_succ) {
4520 vha->fcport_count++;
4521 fcport->login_succ = 1;
4522 fcport->disc_state = DSC_LOGIN_COMPLETE;
4523 }
4524
4525 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
4526
e315cd28 4527 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
41dc529a 4528
1da177e4 4529 if (new_fcport == NULL) {
83548fe2 4530 ql_log(ql_log_warn, vha, 0xd031,
7c3df132 4531 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 4532 rval = QLA_MEMORY_ALLOC_FAILED;
4533 goto cleanup_allocation;
4534 }
41dc529a 4535 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
1da177e4
LT		 4536 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
4537 }
4538
41dc529a
QT		 4539 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
4540
d8b45213 4541 /* Base iIDMA settings on HBA port speed. */
a3cbdfad 4542 fcport->fp_speed = ha->link_data_rate;
d8b45213 4543
e315cd28 4544 qla2x00_update_fcport(vha, fcport);
1da177e4
LT		 4545
4546 found_devs++;
4547 }
4548
4549cleanup_allocation:
c9475cb0 4550 kfree(new_fcport);
1da177e4
LT		 4551
4552 if (rval != QLA_SUCCESS) {
83548fe2 4553 ql_dbg(ql_dbg_disc, vha, 0x2098,
7c3df132 4554 "Configure local loop error exit: rval=%x.\n", rval);
1da177e4
LT		 4555 }
4556
1da177e4
LT		 4557 return (rval);
4558}
4559
d8b45213 4560static void
e315cd28 4561qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
d8b45213 4562{
d8b45213 4563 int rval;
93f2bd67 4564 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 4565 struct qla_hw_data *ha = vha->hw;
d8b45213 4566
c76f2c01 4567 if (!IS_IIDMA_CAPABLE(ha))
d8b45213
AV		 4568 return;
4569
c9afb9a2
GM		 4570 if (atomic_read(&fcport->state) != FCS_ONLINE)
4571 return;
4572
39bd9622
AV		 4573 if (fcport->fp_speed == PORT_SPEED_UNKNOWN ||
4574 fcport->fp_speed > ha->link_data_rate)
d8b45213
AV		 4575 return;
4576
e315cd28 4577 rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed,
a3cbdfad 4578 mb);
d8b45213 4579 if (rval != QLA_SUCCESS) {
7c3df132 4580 ql_dbg(ql_dbg_disc, vha, 0x2004,
7b833558
OK		 4581 "Unable to adjust iIDMA %8phN -- %04x %x %04x %04x.\n",
4582 fcport->port_name, rval, fcport->fp_speed, mb[0], mb[1]);
d8b45213 4583 } else {
7c3df132 4584 ql_dbg(ql_dbg_disc, vha, 0x2005,
7b833558 4585 "iIDMA adjusted to %s GB/s on %8phN.\n",
d0297c9a 4586 qla2x00_get_link_speed_str(ha, fcport->fp_speed),
7b833558 4587 fcport->port_name);
d8b45213
AV		 4588 }
4589}
4590
726b8548 4591/* qla2x00_reg_remote_port is reserved for Initiator Mode only.*/
23be331d 4592static void
e315cd28 4593qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport)
8482e118
AV		 4594{
4595 struct fc_rport_identifiers rport_ids;
bdf79621 4596 struct fc_rport *rport;
044d78e1 4597 unsigned long flags;
8482e118 4598
f8b02a85
AV		 4599 rport_ids.node_name = wwn_to_u64(fcport->node_name);
4600 rport_ids.port_name = wwn_to_u64(fcport->port_name);
8482e118
AV		 4601 rport_ids.port_id = fcport->d_id.b.domain << 16 |
4602 fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa;
77d74143 4603 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
e315cd28 4604 fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids);
77d74143 4605 if (!rport) {
7c3df132
SK		 4606 ql_log(ql_log_warn, vha, 0x2006,
4607 "Unable to allocate fc remote port.\n");
77d74143
AV		 4608 return;
4609 }
2d70c103 4610
044d78e1 4611 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
19a7b4ae 4612 *((fc_port_t **)rport->dd_data) = fcport;
044d78e1 4613 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
d97994dc 4614
ad3e0eda 4615 rport->supported_classes = fcport->supported_classes;
77d74143 4616
8482e118
AV		 4617 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
4618 if (fcport->port_type == FCT_INITIATOR)
4619 rport_ids.roles |= FC_RPORT_ROLE_FCP_INITIATOR;
4620 if (fcport->port_type == FCT_TARGET)
4621 rport_ids.roles |= FC_RPORT_ROLE_FCP_TARGET;
726b8548 4622
83548fe2
QT		 4623 ql_dbg(ql_dbg_disc, vha, 0x20ee,
4624 "%s %8phN. rport %p is %s mode\n",
4625 __func__, fcport->port_name, rport,
4626 (fcport->port_type == FCT_TARGET) ? "tgt" : "ini");
726b8548 4627
77d74143 4628 fc_remote_port_rolechg(rport, rport_ids.roles);
1da177e4
LT		 4629}
4630
23be331d
AB		 4631/*
4632 * qla2x00_update_fcport
4633 * Updates device on list.
4634 *
4635 * Input:
4636 * ha = adapter block pointer.
4637 * fcport = port structure pointer.
4638 *
4639 * Return:
4640 * 0 - Success
4641 * BIT_0 - error
4642 *
4643 * Context:
4644 * Kernel context.
4645 */
4646void
e315cd28 4647qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
23be331d 4648{
e315cd28 4649 fcport->vha = vha;
8ae6d9c7 4650
726b8548
QT		 4651 if (IS_SW_RESV_ADDR(fcport->d_id))
4652 return;
4653
83548fe2 4654 ql_dbg(ql_dbg_disc, vha, 0x20ef, "%s %8phC\n",
726b8548
QT		 4655 __func__, fcport->port_name);
4656
8ae6d9c7
GM		 4657 if (IS_QLAFX00(vha->hw)) {
4658 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
d20ed91b 4659 goto reg_port;
8ae6d9c7 4660 }
23be331d 4661 fcport->login_retry = 0;
5ff1d584 4662 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
726b8548
QT		 4663 fcport->disc_state = DSC_LOGIN_COMPLETE;
4664 fcport->deleted = 0;
4665 fcport->logout_on_delete = 1;
23be331d 4666
e84067d7
DG		 4667 if (fcport->fc4f_nvme) {
4668 qla_nvme_register_remote(vha, fcport);
4669 return;
4670 }
4671
1f93da52 4672 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
e315cd28 4673 qla2x00_iidma_fcport(vha, fcport);
21090cbe 4674 qla24xx_update_fcport_fcp_prio(vha, fcport);
d20ed91b
AP		 4675
4676reg_port:
726b8548
QT		 4677 switch (vha->host->active_mode) {
4678 case MODE_INITIATOR:
d20ed91b 4679 qla2x00_reg_remote_port(vha, fcport);
726b8548
QT		 4680 break;
4681 case MODE_TARGET:
4682 if (!vha->vha_tgt.qla_tgt->tgt_stop &&
4683 !vha->vha_tgt.qla_tgt->tgt_stopped)
4684 qlt_fc_port_added(vha, fcport);
4685 break;
4686 case MODE_DUAL:
d20ed91b 4687 qla2x00_reg_remote_port(vha, fcport);
726b8548
QT		 4688 if (!vha->vha_tgt.qla_tgt->tgt_stop &&
4689 !vha->vha_tgt.qla_tgt->tgt_stopped)
4690 qlt_fc_port_added(vha, fcport);
4691 break;
4692 default:
4693 break;
d20ed91b 4694 }
23be331d
AB		 4695}
4696
1da177e4
LT		 4697/*
4698 * qla2x00_configure_fabric
4699 * Setup SNS devices with loop ID's.
4700 *
4701 * Input:
4702 * ha = adapter block pointer.
4703 *
4704 * Returns:
4705 * 0 = success.
4706 * BIT_0 = error
4707 */
4708static int
e315cd28 4709qla2x00_configure_fabric(scsi_qla_host_t *vha)
1da177e4 4710{
b3b02e6e 4711 int rval;
726b8548 4712 fc_port_t *fcport;
1da177e4 4713 uint16_t mb[MAILBOX_REGISTER_COUNT];
0107109e 4714 uint16_t loop_id;
1da177e4 4715 LIST_HEAD(new_fcports);
e315cd28 4716 struct qla_hw_data *ha = vha->hw;
df673274 4717 int discovery_gen;
1da177e4
LT		 4718
4719 /* If FL port exists, then SNS is present */
e428924c 4720 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 4721 loop_id = NPH_F_PORT;
4722 else
4723 loop_id = SNS_FL_PORT;
e315cd28 4724 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1);
1da177e4 4725 if (rval != QLA_SUCCESS) {
83548fe2 4726 ql_dbg(ql_dbg_disc, vha, 0x20a0,
7c3df132 4727 "MBX_GET_PORT_NAME failed, No FL Port.\n");
1da177e4 4728
e315cd28 4729 vha->device_flags &= ~SWITCH_FOUND;
1da177e4
LT		 4730 return (QLA_SUCCESS);
4731 }
e315cd28 4732 vha->device_flags |= SWITCH_FOUND;
1da177e4 4733
41dc529a
QT		 4734
4735 if (qla_tgt_mode_enabled(vha) || qla_dual_mode_enabled(vha)) {
4736 rval = qla2x00_send_change_request(vha, 0x3, 0);
4737 if (rval != QLA_SUCCESS)
4738 ql_log(ql_log_warn, vha, 0x121,
4739 "Failed to enable receiving of RSCN requests: 0x%x.\n",
4740 rval);
4741 }
4742
4743
1da177e4 4744 do {
726b8548
QT		 4745 qla2x00_mgmt_svr_login(vha);
4746
cca5335c
AV		 4747 /* FDMI support. */
4748 if (ql2xfdmienable &&
e315cd28
AC		 4749 test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags))
4750 qla2x00_fdmi_register(vha);
cca5335c 4751
1da177e4 4752 /* Ensure we are logged into the SNS. */
a14c7711 4753 loop_id = NPH_SNS_LID(ha);
0b91d116
CD		 4754 rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff,
4755 0xfc, mb, BIT_1|BIT_0);
a14c7711
JC		 4756 if (rval != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
4757 ql_dbg(ql_dbg_disc, vha, 0x20a1,
4758 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[6]=%x mb[7]=%x (%x).\n",
4759 loop_id, mb[0], mb[1], mb[2], mb[6], mb[7], rval);
0b91d116 4760 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
e452ceb6 4761 return rval;
0b91d116 4762 }
e315cd28
AC		 4763 if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) {
4764 if (qla2x00_rft_id(vha)) {
1da177e4 4765 /* EMPTY */
83548fe2 4766 ql_dbg(ql_dbg_disc, vha, 0x20a2,
7c3df132 4767 "Register FC-4 TYPE failed.\n");
b98ae0d7
QT		 4768 if (test_bit(LOOP_RESYNC_NEEDED,
4769 &vha->dpc_flags))
4770 break;
1da177e4 4771 }
d3bae931 4772 if (qla2x00_rff_id(vha, FC4_TYPE_FCP_SCSI)) {
1da177e4 4773 /* EMPTY */
83548fe2 4774 ql_dbg(ql_dbg_disc, vha, 0x209a,
7c3df132 4775 "Register FC-4 Features failed.\n");
b98ae0d7
QT		 4776 if (test_bit(LOOP_RESYNC_NEEDED,
4777 &vha->dpc_flags))
4778 break;
1da177e4 4779 }
d3bae931
DG		 4780 if (vha->flags.nvme_enabled) {
4781 if (qla2x00_rff_id(vha, FC_TYPE_NVME)) {
4782 ql_dbg(ql_dbg_disc, vha, 0x2049,
4783 "Register NVME FC Type Features failed.\n");
4784 }
4785 }
e315cd28 4786 if (qla2x00_rnn_id(vha)) {
1da177e4 4787 /* EMPTY */
83548fe2 4788 ql_dbg(ql_dbg_disc, vha, 0x2104,
7c3df132 4789 "Register Node Name failed.\n");
b98ae0d7
QT		 4790 if (test_bit(LOOP_RESYNC_NEEDED,
4791 &vha->dpc_flags))
4792 break;
e315cd28 4793 } else if (qla2x00_rsnn_nn(vha)) {
1da177e4 4794 /* EMPTY */
83548fe2 4795 ql_dbg(ql_dbg_disc, vha, 0x209b,
0bf0efa1 4796 "Register Symbolic Node Name failed.\n");
b98ae0d7
QT		 4797 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4798 break;
1da177e4
LT		 4799 }
4800 }
4801
827210ba
JC		 4802 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4803 fcport->scan_state = QLA_FCPORT_SCAN;
4804 }
4805
df673274
AP		 4806 /* Mark the time right before querying FW for connected ports.
4807 * This process is long, asynchronous and by the time it's done,
4808 * collected information might not be accurate anymore. E.g.
4809 * disconnected port might have re-connected and a brand new
4810 * session has been created. In this case session's generation
4811 * will be newer than discovery_gen. */
4812 qlt_do_generation_tick(vha, &discovery_gen);
4813
726b8548 4814 rval = qla2x00_find_all_fabric_devs(vha);
1da177e4
LT		 4815 if (rval != QLA_SUCCESS)
4816 break;
1da177e4
LT		 4817 } while (0);
4818
e84067d7
DG		 4819 if (!vha->nvme_local_port && vha->flags.nvme_enabled)
4820 qla_nvme_register_hba(vha);
4821
726b8548 4822 if (rval)
7c3df132
SK		 4823 ql_dbg(ql_dbg_disc, vha, 0x2068,
4824 "Configure fabric error exit rval=%d.\n", rval);
1da177e4
LT		 4825
4826 return (rval);
4827}
4828
1da177e4
LT		 4829/*
4830 * qla2x00_find_all_fabric_devs
4831 *
4832 * Input:
4833 * ha = adapter block pointer.
4834 * dev = database device entry pointer.
4835 *
4836 * Returns:
4837 * 0 = success.
4838 *
4839 * Context:
4840 * Kernel context.
4841 */
4842static int
726b8548 4843qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha)
1da177e4
LT		 4844{
4845 int rval;
4846 uint16_t loop_id;
726b8548 4847 fc_port_t *fcport, *new_fcport;
1da177e4
LT		 4848 int found;
4849
4850 sw_info_t *swl;
4851 int swl_idx;
4852 int first_dev, last_dev;
1516ef44 4853 port_id_t wrap = {}, nxt_d_id;
e315cd28 4854 struct qla_hw_data *ha = vha->hw;
bb4cf5b7 4855 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
726b8548 4856 unsigned long flags;
1da177e4
LT		 4857
4858 rval = QLA_SUCCESS;
4859
4860 /* Try GID_PT to get device list, else GAN. */
7a67735b 4861 if (!ha->swl)
642ef983 4862 ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t),
7a67735b
AV		 4863 GFP_KERNEL);
4864 swl = ha->swl;
bbfbbbc1 4865 if (!swl) {
1da177e4 4866 /*EMPTY*/
83548fe2 4867 ql_dbg(ql_dbg_disc, vha, 0x209c,
7c3df132 4868 "GID_PT allocations failed, fallback on GA_NXT.\n");
1da177e4 4869 } else {
642ef983 4870 memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t));
e315cd28 4871 if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) {
1da177e4 4872 swl = NULL;
b98ae0d7
QT		 4873 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4874 return rval;
e315cd28 4875 } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 4876 swl = NULL;
b98ae0d7
QT		 4877 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4878 return rval;
e315cd28 4879 } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 4880 swl = NULL;
b98ae0d7
QT		 4881 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4882 return rval;
726b8548
QT		 4883 } else if (qla2x00_gfpn_id(vha, swl) != QLA_SUCCESS) {
4884 swl = NULL;
b98ae0d7
QT		 4885 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4886 return rval;
1da177e4 4887 }
e8c72ba5
CD		 4888
4889 /* If other queries succeeded probe for FC-4 type */
b98ae0d7 4890 if (swl) {
e8c72ba5 4891 qla2x00_gff_id(vha, swl);
b98ae0d7
QT		 4892 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4893 return rval;
4894 }
1da177e4
LT		 4895 }
4896 swl_idx = 0;
4897
4898 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 4899 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 4900 if (new_fcport == NULL) {
83548fe2 4901 ql_log(ql_log_warn, vha, 0x209d,
7c3df132 4902 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 4903 return (QLA_MEMORY_ALLOC_FAILED);
4904 }
4905 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
1da177e4
LT		 4906 /* Set start port ID scan at adapter ID. */
4907 first_dev = 1;
4908 last_dev = 0;
4909
4910 /* Starting free loop ID. */
e315cd28
AC		 4911 loop_id = ha->min_external_loopid;
4912 for (; loop_id <= ha->max_loop_id; loop_id++) {
4913 if (qla2x00_is_reserved_id(vha, loop_id))
1da177e4
LT		 4914 continue;
4915
3a6478df
GM		 4916 if (ha->current_topology == ISP_CFG_FL &&
4917 (atomic_read(&vha->loop_down_timer) ||
4918 LOOP_TRANSITION(vha))) {
bb2d52b2
AV		 4919 atomic_set(&vha->loop_down_timer, 0);
4920 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
4921 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
1da177e4 4922 break;
bb2d52b2 4923 }
1da177e4
LT		 4924
4925 if (swl != NULL) {
4926 if (last_dev) {
4927 wrap.b24 = new_fcport->d_id.b24;
4928 } else {
4929 new_fcport->d_id.b24 = swl[swl_idx].d_id.b24;
4930 memcpy(new_fcport->node_name,
4931 swl[swl_idx].node_name, WWN_SIZE);
4932 memcpy(new_fcport->port_name,
4933 swl[swl_idx].port_name, WWN_SIZE);
d8b45213
AV		 4934 memcpy(new_fcport->fabric_port_name,
4935 swl[swl_idx].fabric_port_name, WWN_SIZE);
4936 new_fcport->fp_speed = swl[swl_idx].fp_speed;
e8c72ba5 4937 new_fcport->fc4_type = swl[swl_idx].fc4_type;
1da177e4 4938
a5d42f4c 4939 new_fcport->nvme_flag = 0;
1a28faa0 4940 new_fcport->fc4f_nvme = 0;
a5d42f4c
DG		 4941 if (vha->flags.nvme_enabled &&
4942 swl[swl_idx].fc4f_nvme) {
4943 new_fcport->fc4f_nvme =
4944 swl[swl_idx].fc4f_nvme;
4945 ql_log(ql_log_info, vha, 0x2131,
4946 "FOUND: NVME port %8phC as FC Type 28h\n",
4947 new_fcport->port_name);
4948 }
4949
1da177e4
LT		 4950 if (swl[swl_idx].d_id.b.rsvd_1 != 0) {
4951 last_dev = 1;
4952 }
4953 swl_idx++;
4954 }
4955 } else {
4956 /* Send GA_NXT to the switch */
e315cd28 4957 rval = qla2x00_ga_nxt(vha, new_fcport);
1da177e4 4958 if (rval != QLA_SUCCESS) {
83548fe2 4959 ql_log(ql_log_warn, vha, 0x209e,
7c3df132
SK		 4960 "SNS scan failed -- assuming "
4961 "zero-entry result.\n");
1da177e4
LT		 4962 rval = QLA_SUCCESS;
4963 break;
4964 }
4965 }
4966
4967 /* If wrap on switch device list, exit. */
4968 if (first_dev) {
4969 wrap.b24 = new_fcport->d_id.b24;
4970 first_dev = 0;
4971 } else if (new_fcport->d_id.b24 == wrap.b24) {
83548fe2 4972 ql_dbg(ql_dbg_disc, vha, 0x209f,
7c3df132
SK		 4973 "Device wrap (%02x%02x%02x).\n",
4974 new_fcport->d_id.b.domain,
4975 new_fcport->d_id.b.area,
4976 new_fcport->d_id.b.al_pa);
1da177e4
LT		 4977 break;
4978 }
4979
2c3dfe3f 4980 /* Bypass if same physical adapter. */
e315cd28 4981 if (new_fcport->d_id.b24 == base_vha->d_id.b24)
1da177e4
LT		 4982 continue;
4983
2c3dfe3f 4984 /* Bypass virtual ports of the same host. */
bb4cf5b7
CD		 4985 if (qla2x00_is_a_vp_did(vha, new_fcport->d_id.b24))
4986 continue;
2c3dfe3f 4987
f7d289f6
AV		 4988 /* Bypass if same domain and area of adapter. */
4989 if (((new_fcport->d_id.b24 & 0xffff00) ==
e315cd28 4990 (vha->d_id.b24 & 0xffff00)) && ha->current_topology ==
f7d289f6
AV		 4991 ISP_CFG_FL)
4992 continue;
4993
1da177e4
LT		 4994 /* Bypass reserved domain fields. */
4995 if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0)
4996 continue;
4997
e8c72ba5 4998 /* Bypass ports whose FCP-4 type is not FCP_SCSI */
4da26e16
CD		 4999 if (ql2xgffidenable &&
5000 (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI &&
5001 new_fcport->fc4_type != FC4_TYPE_UNKNOWN))
e8c72ba5
CD		 5002 continue;
5003
726b8548
QT		 5004 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5005
1da177e4
LT		 5006 /* Locate matching device in database. */
5007 found = 0;
e315cd28 5008 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 5009 if (memcmp(new_fcport->port_name, fcport->port_name,
5010 WWN_SIZE))
5011 continue;
5012
827210ba 5013 fcport->scan_state = QLA_FCPORT_FOUND;
b3b02e6e 5014
1da177e4
LT		 5015 found++;
5016
d8b45213
AV		 5017 /* Update port state. */
5018 memcpy(fcport->fabric_port_name,
5019 new_fcport->fabric_port_name, WWN_SIZE);
5020 fcport->fp_speed = new_fcport->fp_speed;
5021
1da177e4 5022 /*
b2032fd5
RD		 5023 * If address the same and state FCS_ONLINE
5024 * (or in target mode), nothing changed.
1da177e4
LT		 5025 */
5026 if (fcport->d_id.b24 == new_fcport->d_id.b24 &&
b2032fd5 5027 (atomic_read(&fcport->state) == FCS_ONLINE ||
726b8548 5028 (vha->host->active_mode == MODE_TARGET))) {
1da177e4
LT		 5029 break;
5030 }
5031
5032 /*
5033 * If device was not a fabric device before.
5034 */
5035 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) {
5036 fcport->d_id.b24 = new_fcport->d_id.b24;
5f16b331 5037 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 5038 fcport->flags |= (FCF_FABRIC_DEVICE |
5039 FCF_LOGIN_NEEDED);
1da177e4
LT		 5040 break;
5041 }
5042
5043 /*
5044 * Port ID changed or device was marked to be updated;
5045 * Log it out if still logged in and mark it for
5046 * relogin later.
5047 */
726b8548 5048 if (qla_tgt_mode_enabled(base_vha)) {
b2032fd5
RD		 5049 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf080,
5050 "port changed FC ID, %8phC"
5051 " old %x:%x:%x (loop_id 0x%04x)-> new %x:%x:%x\n",
5052 fcport->port_name,
5053 fcport->d_id.b.domain,
5054 fcport->d_id.b.area,
5055 fcport->d_id.b.al_pa,
5056 fcport->loop_id,
5057 new_fcport->d_id.b.domain,
5058 new_fcport->d_id.b.area,
5059 new_fcport->d_id.b.al_pa);
5060 fcport->d_id.b24 = new_fcport->d_id.b24;
5061 break;
5062 }
5063
1da177e4
LT		 5064 fcport->d_id.b24 = new_fcport->d_id.b24;
5065 fcport->flags |= FCF_LOGIN_NEEDED;
1da177e4
LT		 5066 break;
5067 }
5068
726b8548
QT		 5069 if (found) {
5070 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1da177e4 5071 continue;
726b8548 5072 }
1da177e4 5073 /* If device was not in our fcports list, then add it. */
b2032fd5 5074 new_fcport->scan_state = QLA_FCPORT_FOUND;
726b8548
QT		 5075 list_add_tail(&new_fcport->list, &vha->vp_fcports);
5076
5077 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5078
1da177e4
LT		 5079
5080 /* Allocate a new replacement fcport. */
5081 nxt_d_id.b24 = new_fcport->d_id.b24;
e315cd28 5082 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 5083 if (new_fcport == NULL) {
83548fe2 5084 ql_log(ql_log_warn, vha, 0xd032,
7c3df132 5085 "Memory allocation failed for fcport.\n");
1da177e4
LT		 5086 return (QLA_MEMORY_ALLOC_FAILED);
5087 }
5088 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
5089 new_fcport->d_id.b24 = nxt_d_id.b24;
5090 }
5091
726b8548
QT		 5092 qla2x00_free_fcport(new_fcport);
5093
5094 /*
5095 * Logout all previous fabric dev marked lost, except FCP2 devices.
5096 */
5097 list_for_each_entry(fcport, &vha->vp_fcports, list) {
5098 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5099 break;
5100
5101 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0 ||
5102 (fcport->flags & FCF_LOGIN_NEEDED) == 0)
5103 continue;
5104
5105 if (fcport->scan_state == QLA_FCPORT_SCAN) {
5106 if ((qla_dual_mode_enabled(vha) ||
5107 qla_ini_mode_enabled(vha)) &&
5108 atomic_read(&fcport->state) == FCS_ONLINE) {
5109 qla2x00_mark_device_lost(vha, fcport,
5110 ql2xplogiabsentdevice, 0);
5111 if (fcport->loop_id != FC_NO_LOOP_ID &&
5112 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
5113 fcport->port_type != FCT_INITIATOR &&
5114 fcport->port_type != FCT_BROADCAST) {
83548fe2 5115 ql_dbg(ql_dbg_disc, vha, 0x20f0,
726b8548
QT		 5116 "%s %d %8phC post del sess\n",
5117 __func__, __LINE__,
5118 fcport->port_name);
5119
5120 qlt_schedule_sess_for_deletion_lock
5121 (fcport);
5122 continue;
5123 }
5124 }
5125 }
1da177e4 5126
726b8548
QT		 5127 if (fcport->scan_state == QLA_FCPORT_FOUND)
5128 qla24xx_fcport_handle_login(vha, fcport);
5129 }
1da177e4
LT		 5130 return (rval);
5131}
5132
5133/*
5134 * qla2x00_find_new_loop_id
5135 * Scan through our port list and find a new usable loop ID.
5136 *
5137 * Input:
5138 * ha: adapter state pointer.
5139 * dev: port structure pointer.
5140 *
5141 * Returns:
5142 * qla2x00 local function return status code.
5143 *
5144 * Context:
5145 * Kernel context.
5146 */
03bcfb57 5147int
e315cd28 5148qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
1da177e4
LT		 5149{
5150 int rval;
e315cd28 5151 struct qla_hw_data *ha = vha->hw;
feafb7b1 5152 unsigned long flags = 0;
1da177e4
LT		 5153
5154 rval = QLA_SUCCESS;
5155
5f16b331 5156 spin_lock_irqsave(&ha->vport_slock, flags);
1da177e4 5157
5f16b331
CD		 5158 dev->loop_id = find_first_zero_bit(ha->loop_id_map,
5159 LOOPID_MAP_SIZE);
5160 if (dev->loop_id >= LOOPID_MAP_SIZE ||
5161 qla2x00_is_reserved_id(vha, dev->loop_id)) {
5162 dev->loop_id = FC_NO_LOOP_ID;
5163 rval = QLA_FUNCTION_FAILED;
5164 } else
5165 set_bit(dev->loop_id, ha->loop_id_map);
1da177e4 5166
5f16b331 5167 spin_unlock_irqrestore(&ha->vport_slock, flags);
1da177e4 5168
5f16b331
CD		 5169 if (rval == QLA_SUCCESS)
5170 ql_dbg(ql_dbg_disc, dev->vha, 0x2086,
5171 "Assigning new loopid=%x, portid=%x.\n",
5172 dev->loop_id, dev->d_id.b24);
5173 else
5174 ql_log(ql_log_warn, dev->vha, 0x2087,
5175 "No loop_id's available, portid=%x.\n",
5176 dev->d_id.b24);
1da177e4
LT		 5177
5178 return (rval);
5179}
5180
1da177e4
LT		 5181
5182/*
5183 * qla2x00_fabric_login
5184 * Issue fabric login command.
5185 *
5186 * Input:
5187 * ha = adapter block pointer.
5188 * device = pointer to FC device type structure.
5189 *
5190 * Returns:
5191 * 0 - Login successfully
5192 * 1 - Login failed
5193 * 2 - Initiator device
5194 * 3 - Fatal error
5195 */
5196int
e315cd28 5197qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 5198 uint16_t *next_loopid)
5199{
5200 int rval;
5201 int retry;
5202 uint16_t tmp_loopid;
5203 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 5204 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 5205
5206 retry = 0;
5207 tmp_loopid = 0;
5208
5209 for (;;) {
7c3df132
SK		 5210 ql_dbg(ql_dbg_disc, vha, 0x2000,
5211 "Trying Fabric Login w/loop id 0x%04x for port "
5212 "%02x%02x%02x.\n",
5213 fcport->loop_id, fcport->d_id.b.domain,
5214 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 5215
5216 /* Login fcport on switch. */
0b91d116 5217 rval = ha->isp_ops->fabric_login(vha, fcport->loop_id,
1da177e4
LT		 5218 fcport->d_id.b.domain, fcport->d_id.b.area,
5219 fcport->d_id.b.al_pa, mb, BIT_0);
0b91d116
CD		 5220 if (rval != QLA_SUCCESS) {
5221 return rval;
5222 }
1da177e4
LT		 5223 if (mb[0] == MBS_PORT_ID_USED) {
5224 /*
5225 * Device has another loop ID. The firmware team
0107109e
AV		 5226 * recommends the driver perform an implicit login with
5227 * the specified ID again. The ID we just used is save
5228 * here so we return with an ID that can be tried by
5229 * the next login.
1da177e4
LT		 5230 */
5231 retry++;
5232 tmp_loopid = fcport->loop_id;
5233 fcport->loop_id = mb[1];
5234
7c3df132
SK		 5235 ql_dbg(ql_dbg_disc, vha, 0x2001,
5236 "Fabric Login: port in use - next loop "
5237 "id=0x%04x, port id= %02x%02x%02x.\n",
1da177e4 5238 fcport->loop_id, fcport->d_id.b.domain,
7c3df132 5239 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 5240
5241 } else if (mb[0] == MBS_COMMAND_COMPLETE) {
5242 /*
5243 * Login succeeded.
5244 */
5245 if (retry) {
5246 /* A retry occurred before. */
5247 *next_loopid = tmp_loopid;
5248 } else {
5249 /*
5250 * No retry occurred before. Just increment the
5251 * ID value for next login.
5252 */
5253 *next_loopid = (fcport->loop_id + 1);
5254 }
5255
5256 if (mb[1] & BIT_0) {
5257 fcport->port_type = FCT_INITIATOR;
5258 } else {
5259 fcport->port_type = FCT_TARGET;
5260 if (mb[1] & BIT_1) {
8474f3a0 5261 fcport->flags |= FCF_FCP2_DEVICE;
1da177e4
LT		 5262 }
5263 }
5264
ad3e0eda
AV		 5265 if (mb[10] & BIT_0)
5266 fcport->supported_classes |= FC_COS_CLASS2;
5267 if (mb[10] & BIT_1)
5268 fcport->supported_classes |= FC_COS_CLASS3;
5269
2d70c103
NB		 5270 if (IS_FWI2_CAPABLE(ha)) {
5271 if (mb[10] & BIT_7)
5272 fcport->flags |=
5273 FCF_CONF_COMP_SUPPORTED;
5274 }
5275
1da177e4
LT		 5276 rval = QLA_SUCCESS;
5277 break;
5278 } else if (mb[0] == MBS_LOOP_ID_USED) {
5279 /*
5280 * Loop ID already used, try next loop ID.
5281 */
5282 fcport->loop_id++;
e315cd28 5283 rval = qla2x00_find_new_loop_id(vha, fcport);
1da177e4
LT		 5284 if (rval != QLA_SUCCESS) {
5285 /* Ran out of loop IDs to use */
5286 break;
5287 }
5288 } else if (mb[0] == MBS_COMMAND_ERROR) {
5289 /*
5290 * Firmware possibly timed out during login. If NO
5291 * retries are left to do then the device is declared
5292 * dead.
5293 */
5294 *next_loopid = fcport->loop_id;
e315cd28 5295 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 5296 fcport->d_id.b.domain, fcport->d_id.b.area,
5297 fcport->d_id.b.al_pa);
e315cd28 5298 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 5299
5300 rval = 1;
5301 break;
5302 } else {
5303 /*
5304 * unrecoverable / not handled error
5305 */
7c3df132
SK		 5306 ql_dbg(ql_dbg_disc, vha, 0x2002,
5307 "Failed=%x port_id=%02x%02x%02x loop_id=%x "
5308 "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain,
5309 fcport->d_id.b.area, fcport->d_id.b.al_pa,
5310 fcport->loop_id, jiffies);
1da177e4
LT		 5311
5312 *next_loopid = fcport->loop_id;
e315cd28 5313 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 5314 fcport->d_id.b.domain, fcport->d_id.b.area,
5315 fcport->d_id.b.al_pa);
5f16b331 5316 qla2x00_clear_loop_id(fcport);
0eedfcf0 5317 fcport->login_retry = 0;
1da177e4
LT		 5318
5319 rval = 3;
5320 break;
5321 }
5322 }
5323
5324 return (rval);
5325}
5326
5327/*
5328 * qla2x00_local_device_login
5329 * Issue local device login command.
5330 *
5331 * Input:
5332 * ha = adapter block pointer.
5333 * loop_id = loop id of device to login to.
5334 *
5335 * Returns (Where's the #define!!!!):
5336 * 0 - Login successfully
5337 * 1 - Login failed
5338 * 3 - Fatal error
5339 */
5340int
e315cd28 5341qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport)
1da177e4
LT		 5342{
5343 int rval;
5344 uint16_t mb[MAILBOX_REGISTER_COUNT];
5345
5346 memset(mb, 0, sizeof(mb));
e315cd28 5347 rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0);
1da177e4
LT		 5348 if (rval == QLA_SUCCESS) {
5349 /* Interrogate mailbox registers for any errors */
5350 if (mb[0] == MBS_COMMAND_ERROR)
5351 rval = 1;
5352 else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR)
5353 /* device not in PCB table */
5354 rval = 3;
5355 }
5356
5357 return (rval);
5358}
5359
5360/*
5361 * qla2x00_loop_resync
5362 * Resync with fibre channel devices.
5363 *
5364 * Input:
5365 * ha = adapter block pointer.
5366 *
5367 * Returns:
5368 * 0 = success
5369 */
5370int
e315cd28 5371qla2x00_loop_resync(scsi_qla_host_t *vha)
1da177e4 5372{
73208dfd 5373 int rval = QLA_SUCCESS;
1da177e4 5374 uint32_t wait_time;
67c2e93a
AC		 5375 struct req_que *req;
5376 struct rsp_que *rsp;
5377
d7459527 5378 req = vha->req;
67c2e93a 5379 rsp = req->rsp;
1da177e4 5380
e315cd28
AC		 5381 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
5382 if (vha->flags.online) {
5383 if (!(rval = qla2x00_fw_ready(vha))) {
1da177e4
LT		 5384 /* Wait at most MAX_TARGET RSCNs for a stable link. */
5385 wait_time = 256;
5386 do {
8ae6d9c7
GM		 5387 if (!IS_QLAFX00(vha->hw)) {
5388 /*
5389 * Issue a marker after FW becomes
5390 * ready.
5391 */
5392 qla2x00_marker(vha, req, rsp, 0, 0,
5393 MK_SYNC_ALL);
5394 vha->marker_needed = 0;
5395 }
1da177e4
LT		 5396
5397 /* Remap devices on Loop. */
e315cd28 5398 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4 5399
8ae6d9c7
GM		 5400 if (IS_QLAFX00(vha->hw))
5401 qlafx00_configure_devices(vha);
5402 else
5403 qla2x00_configure_loop(vha);
5404
1da177e4 5405 wait_time--;
e315cd28
AC		 5406 } while (!atomic_read(&vha->loop_down_timer) &&
5407 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
5408 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
5409 &vha->dpc_flags)));
1da177e4 5410 }
1da177e4
LT		 5411 }
5412
e315cd28 5413 if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
1da177e4 5414 return (QLA_FUNCTION_FAILED);
1da177e4 5415
e315cd28 5416 if (rval)
7c3df132
SK		 5417 ql_dbg(ql_dbg_disc, vha, 0x206c,
5418 "%s *** FAILED ***.\n", __func__);
1da177e4
LT		 5419
5420 return (rval);
5421}
5422
579d12b5
SK		 5423/*
5424* qla2x00_perform_loop_resync
5425* Description: This function will set the appropriate flags and call
5426* qla2x00_loop_resync. If successful loop will be resynced
5427* Arguments : scsi_qla_host_t pointer
5428* returm : Success or Failure
5429*/
5430
5431int qla2x00_perform_loop_resync(scsi_qla_host_t *ha)
5432{
5433 int32_t rval = 0;
5434
5435 if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) {
5436 /*Configure the flags so that resync happens properly*/
5437 atomic_set(&ha->loop_down_timer, 0);
5438 if (!(ha->device_flags & DFLG_NO_CABLE)) {
5439 atomic_set(&ha->loop_state, LOOP_UP);
5440 set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags);
5441 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
5442 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
5443
5444 rval = qla2x00_loop_resync(ha);
5445 } else
5446 atomic_set(&ha->loop_state, LOOP_DEAD);
5447
5448 clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags);
5449 }
5450
5451 return rval;
5452}
5453
d97994dc 5454void
67becc00 5455qla2x00_update_fcports(scsi_qla_host_t *base_vha)
d97994dc
AV		 5456{
5457 fc_port_t *fcport;
feafb7b1
AE		 5458 struct scsi_qla_host *vha;
5459 struct qla_hw_data *ha = base_vha->hw;
5460 unsigned long flags;
d97994dc 5461
feafb7b1 5462 spin_lock_irqsave(&ha->vport_slock, flags);
d97994dc 5463 /* Go with deferred removal of rport references. */
feafb7b1
AE		 5464 list_for_each_entry(vha, &base_vha->hw->vp_list, list) {
5465 atomic_inc(&vha->vref_count);
5466 list_for_each_entry(fcport, &vha->vp_fcports, list) {
8ae598d0 5467 if (fcport->drport &&
feafb7b1
AE		 5468 atomic_read(&fcport->state) != FCS_UNCONFIGURED) {
5469 spin_unlock_irqrestore(&ha->vport_slock, flags);
67becc00 5470 qla2x00_rport_del(fcport);
df673274 5471
feafb7b1
AE		 5472 spin_lock_irqsave(&ha->vport_slock, flags);
5473 }
5474 }
5475 atomic_dec(&vha->vref_count);
c4a9b538 5476 wake_up(&vha->vref_waitq);
feafb7b1
AE		 5477 }
5478 spin_unlock_irqrestore(&ha->vport_slock, flags);
d97994dc
AV		 5479}
5480
7d613ac6
SV		 5481/* Assumes idc_lock always held on entry */
5482void
5483qla83xx_reset_ownership(scsi_qla_host_t *vha)
5484{
5485 struct qla_hw_data *ha = vha->hw;
5486 uint32_t drv_presence, drv_presence_mask;
5487 uint32_t dev_part_info1, dev_part_info2, class_type;
5488 uint32_t class_type_mask = 0x3;
5489 uint16_t fcoe_other_function = 0xffff, i;
5490
7ec0effd
AD		 5491 if (IS_QLA8044(ha)) {
5492 drv_presence = qla8044_rd_direct(vha,
5493 QLA8044_CRB_DRV_ACTIVE_INDEX);
5494 dev_part_info1 = qla8044_rd_direct(vha,
5495 QLA8044_CRB_DEV_PART_INFO_INDEX);
5496 dev_part_info2 = qla8044_rd_direct(vha,
5497 QLA8044_CRB_DEV_PART_INFO2);
5498 } else {
5499 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5500 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1);
5501 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2);
5502 }
7d613ac6
SV		 5503 for (i = 0; i < 8; i++) {
5504 class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask);
5505 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
5506 (i != ha->portnum)) {
5507 fcoe_other_function = i;
5508 break;
5509 }
5510 }
5511 if (fcoe_other_function == 0xffff) {
5512 for (i = 0; i < 8; i++) {
5513 class_type = ((dev_part_info2 >> (i * 4)) &
5514 class_type_mask);
5515 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
5516 ((i + 8) != ha->portnum)) {
5517 fcoe_other_function = i + 8;
5518 break;
5519 }
5520 }
5521 }
5522 /*
5523 * Prepare drv-presence mask based on fcoe functions present.
5524 * However consider only valid physical fcoe function numbers (0-15).
5525 */
5526 drv_presence_mask = ~((1 << (ha->portnum)) |
5527 ((fcoe_other_function == 0xffff) ?
5528 0 : (1 << (fcoe_other_function))));
5529
5530 /* We are the reset owner iff:
5531 * - No other protocol drivers present.
5532 * - This is the lowest among fcoe functions. */
5533 if (!(drv_presence & drv_presence_mask) &&
5534 (ha->portnum < fcoe_other_function)) {
5535 ql_dbg(ql_dbg_p3p, vha, 0xb07f,
5536 "This host is Reset owner.\n");
5537 ha->flags.nic_core_reset_owner = 1;
5538 }
5539}
5540
fa492630 5541static int
7d613ac6
SV		 5542__qla83xx_set_drv_ack(scsi_qla_host_t *vha)
5543{
5544 int rval = QLA_SUCCESS;
5545 struct qla_hw_data *ha = vha->hw;
5546 uint32_t drv_ack;
5547
5548 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
5549 if (rval == QLA_SUCCESS) {
5550 drv_ack |= (1 << ha->portnum);
5551 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
5552 }
5553
5554 return rval;
5555}
5556
fa492630 5557static int
7d613ac6
SV		 5558__qla83xx_clear_drv_ack(scsi_qla_host_t *vha)
5559{
5560 int rval = QLA_SUCCESS;
5561 struct qla_hw_data *ha = vha->hw;
5562 uint32_t drv_ack;
5563
5564 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
5565 if (rval == QLA_SUCCESS) {
5566 drv_ack &= ~(1 << ha->portnum);
5567 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
5568 }
5569
5570 return rval;
5571}
5572
fa492630 5573static const char *
7d613ac6
SV		 5574qla83xx_dev_state_to_string(uint32_t dev_state)
5575{
5576 switch (dev_state) {
5577 case QLA8XXX_DEV_COLD:
5578 return "COLD/RE-INIT";
5579 case QLA8XXX_DEV_INITIALIZING:
5580 return "INITIALIZING";
5581 case QLA8XXX_DEV_READY:
5582 return "READY";
5583 case QLA8XXX_DEV_NEED_RESET:
5584 return "NEED RESET";
5585 case QLA8XXX_DEV_NEED_QUIESCENT:
5586 return "NEED QUIESCENT";
5587 case QLA8XXX_DEV_FAILED:
5588 return "FAILED";
5589 case QLA8XXX_DEV_QUIESCENT:
5590 return "QUIESCENT";
5591 default:
5592 return "Unknown";
5593 }
5594}
5595
5596/* Assumes idc-lock always held on entry */
5597void
5598qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type)
5599{
5600 struct qla_hw_data *ha = vha->hw;
5601 uint32_t idc_audit_reg = 0, duration_secs = 0;
5602
5603 switch (audit_type) {
5604 case IDC_AUDIT_TIMESTAMP:
5605 ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000);
5606 idc_audit_reg = (ha->portnum) |
5607 (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8);
5608 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
5609 break;
5610
5611 case IDC_AUDIT_COMPLETION:
5612 duration_secs = ((jiffies_to_msecs(jiffies) -
5613 jiffies_to_msecs(ha->idc_audit_ts)) / 1000);
5614 idc_audit_reg = (ha->portnum) |
5615 (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8);
5616 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
5617 break;
5618
5619 default:
5620 ql_log(ql_log_warn, vha, 0xb078,
5621 "Invalid audit type specified.\n");
5622 break;
5623 }
5624}
5625
5626/* Assumes idc_lock always held on entry */
fa492630 5627static int
7d613ac6
SV		 5628qla83xx_initiating_reset(scsi_qla_host_t *vha)
5629{
5630 struct qla_hw_data *ha = vha->hw;
5631 uint32_t idc_control, dev_state;
5632
5633 __qla83xx_get_idc_control(vha, &idc_control);
5634 if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) {
5635 ql_log(ql_log_info, vha, 0xb080,
5636 "NIC Core reset has been disabled. idc-control=0x%x\n",
5637 idc_control);
5638 return QLA_FUNCTION_FAILED;
5639 }
5640
5641 /* Set NEED-RESET iff in READY state and we are the reset-owner */
5642 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5643 if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) {
5644 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
5645 QLA8XXX_DEV_NEED_RESET);
5646 ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n");
5647 qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP);
5648 } else {
5649 const char *state = qla83xx_dev_state_to_string(dev_state);
5650 ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n", state);
5651
5652 /* SV: XXX: Is timeout required here? */
5653 /* Wait for IDC state change READY -> NEED_RESET */
5654 while (dev_state == QLA8XXX_DEV_READY) {
5655 qla83xx_idc_unlock(vha, 0);
5656 msleep(200);
5657 qla83xx_idc_lock(vha, 0);
5658 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5659 }
5660 }
5661
5662 /* Send IDC ack by writing to drv-ack register */
5663 __qla83xx_set_drv_ack(vha);
5664
5665 return QLA_SUCCESS;
5666}
5667
5668int
5669__qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control)
5670{
5671 return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
5672}
5673
7d613ac6
SV		 5674int
5675__qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control)
5676{
5677 return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
5678}
5679
fa492630 5680static int
7d613ac6
SV		 5681qla83xx_check_driver_presence(scsi_qla_host_t *vha)
5682{
5683 uint32_t drv_presence = 0;
5684 struct qla_hw_data *ha = vha->hw;
5685
5686 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5687 if (drv_presence & (1 << ha->portnum))
5688 return QLA_SUCCESS;
5689 else
5690 return QLA_TEST_FAILED;
5691}
5692
5693int
5694qla83xx_nic_core_reset(scsi_qla_host_t *vha)
5695{
5696 int rval = QLA_SUCCESS;
5697 struct qla_hw_data *ha = vha->hw;
5698
5699 ql_dbg(ql_dbg_p3p, vha, 0xb058,
5700 "Entered %s().\n", __func__);
5701
5702 if (vha->device_flags & DFLG_DEV_FAILED) {
5703 ql_log(ql_log_warn, vha, 0xb059,
5704 "Device in unrecoverable FAILED state.\n");
5705 return QLA_FUNCTION_FAILED;
5706 }
5707
5708 qla83xx_idc_lock(vha, 0);
5709
5710 if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) {
5711 ql_log(ql_log_warn, vha, 0xb05a,
5712 "Function=0x%x has been removed from IDC participation.\n",
5713 ha->portnum);
5714 rval = QLA_FUNCTION_FAILED;
5715 goto exit;
5716 }
5717
5718 qla83xx_reset_ownership(vha);
5719
5720 rval = qla83xx_initiating_reset(vha);
5721
5722 /*
5723 * Perform reset if we are the reset-owner,
5724 * else wait till IDC state changes to READY/FAILED.
5725 */
5726 if (rval == QLA_SUCCESS) {
5727 rval = qla83xx_idc_state_handler(vha);
5728
5729 if (rval == QLA_SUCCESS)
5730 ha->flags.nic_core_hung = 0;
5731 __qla83xx_clear_drv_ack(vha);
5732 }
5733
5734exit:
5735 qla83xx_idc_unlock(vha, 0);
5736
5737 ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__);
5738
5739 return rval;
5740}
5741
81178772
SK		 5742int
5743qla2xxx_mctp_dump(scsi_qla_host_t *vha)
5744{
5745 struct qla_hw_data *ha = vha->hw;
5746 int rval = QLA_FUNCTION_FAILED;
5747
5748 if (!IS_MCTP_CAPABLE(ha)) {
5749 /* This message can be removed from the final version */
5750 ql_log(ql_log_info, vha, 0x506d,
5751 "This board is not MCTP capable\n");
5752 return rval;
5753 }
5754
5755 if (!ha->mctp_dump) {
5756 ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev,
5757 MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL);
5758
5759 if (!ha->mctp_dump) {
5760 ql_log(ql_log_warn, vha, 0x506e,
5761 "Failed to allocate memory for mctp dump\n");
5762 return rval;
5763 }
5764 }
5765
5766#define MCTP_DUMP_STR_ADDR 0x00000000
5767 rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma,
5768 MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4);
5769 if (rval != QLA_SUCCESS) {
5770 ql_log(ql_log_warn, vha, 0x506f,
5771 "Failed to capture mctp dump\n");
5772 } else {
5773 ql_log(ql_log_info, vha, 0x5070,
5774 "Mctp dump capture for host (%ld/%p).\n",
5775 vha->host_no, ha->mctp_dump);
5776 ha->mctp_dumped = 1;
5777 }
5778
409ee0fe 5779 if (!ha->flags.nic_core_reset_hdlr_active && !ha->portnum) {
81178772
SK		 5780 ha->flags.nic_core_reset_hdlr_active = 1;
5781 rval = qla83xx_restart_nic_firmware(vha);
5782 if (rval)
5783 /* NIC Core reset failed. */
5784 ql_log(ql_log_warn, vha, 0x5071,
5785 "Failed to restart nic firmware\n");
5786 else
5787 ql_dbg(ql_dbg_p3p, vha, 0xb084,
5788 "Restarted NIC firmware successfully.\n");
5789 ha->flags.nic_core_reset_hdlr_active = 0;
5790 }
5791
5792 return rval;
5793
5794}
5795
579d12b5 5796/*
8fcd6b8b 5797* qla2x00_quiesce_io
579d12b5
SK		 5798* Description: This function will block the new I/Os
5799* Its not aborting any I/Os as context
5800* is not destroyed during quiescence
5801* Arguments: scsi_qla_host_t
5802* return : void
5803*/
5804void
8fcd6b8b 5805qla2x00_quiesce_io(scsi_qla_host_t *vha)
579d12b5
SK		 5806{
5807 struct qla_hw_data *ha = vha->hw;
5808 struct scsi_qla_host *vp;
5809
8fcd6b8b
CD		 5810 ql_dbg(ql_dbg_dpc, vha, 0x401d,
5811 "Quiescing I/O - ha=%p.\n", ha);
579d12b5
SK		 5812
5813 atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME);
5814 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
5815 atomic_set(&vha->loop_state, LOOP_DOWN);
5816 qla2x00_mark_all_devices_lost(vha, 0);
5817 list_for_each_entry(vp, &ha->vp_list, list)
8fcd6b8b 5818 qla2x00_mark_all_devices_lost(vp, 0);
579d12b5
SK		 5819 } else {
5820 if (!atomic_read(&vha->loop_down_timer))
5821 atomic_set(&vha->loop_down_timer,
5822 LOOP_DOWN_TIME);
5823 }
5824 /* Wait for pending cmds to complete */
5825 qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST);
5826}
5827
a9083016
GM		 5828void
5829qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
5830{
5831 struct qla_hw_data *ha = vha->hw;
579d12b5 5832 struct scsi_qla_host *vp;
feafb7b1 5833 unsigned long flags;
6aef87be 5834 fc_port_t *fcport;
7c3f8fd1 5835 u16 i;
a9083016 5836
e46ef004
SK		 5837 /* For ISP82XX, driver waits for completion of the commands.
5838 * online flag should be set.
5839 */
7ec0effd 5840 if (!(IS_P3P_TYPE(ha)))
e46ef004 5841 vha->flags.online = 0;
a9083016
GM		 5842 ha->flags.chip_reset_done = 0;
5843 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2be21fa2 5844 vha->qla_stats.total_isp_aborts++;
a9083016 5845
7c3df132
SK		 5846 ql_log(ql_log_info, vha, 0x00af,
5847 "Performing ISP error recovery - ha=%p.\n", ha);
a9083016 5848
e46ef004
SK		 5849 /* For ISP82XX, reset_chip is just disabling interrupts.
5850 * Driver waits for the completion of the commands.
5851 * the interrupts need to be enabled.
5852 */
7ec0effd 5853 if (!(IS_P3P_TYPE(ha)))
a9083016
GM		 5854 ha->isp_ops->reset_chip(vha);
5855
ec7193e2
QT		 5856 ha->flags.n2n_ae = 0;
5857 ha->flags.lip_ae = 0;
5858 ha->current_topology = 0;
5859 ha->flags.fw_started = 0;
5860 ha->flags.fw_init_done = 0;
7c3f8fd1
QT		 5861 ha->base_qpair->chip_reset++;
5862 for (i = 0; i < ha->max_qpairs; i++) {
5863 if (ha->queue_pair_map[i])
5864 ha->queue_pair_map[i]->chip_reset =
5865 ha->base_qpair->chip_reset;
5866 }
726b8548 5867
a9083016
GM		 5868 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
5869 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
5870 atomic_set(&vha->loop_state, LOOP_DOWN);
5871 qla2x00_mark_all_devices_lost(vha, 0);
feafb7b1
AE		 5872
5873 spin_lock_irqsave(&ha->vport_slock, flags);
579d12b5 5874 list_for_each_entry(vp, &ha->vp_list, list) {
feafb7b1
AE		 5875 atomic_inc(&vp->vref_count);
5876 spin_unlock_irqrestore(&ha->vport_slock, flags);
5877
a9083016 5878 qla2x00_mark_all_devices_lost(vp, 0);
feafb7b1
AE		 5879
5880 spin_lock_irqsave(&ha->vport_slock, flags);
5881 atomic_dec(&vp->vref_count);
5882 }
5883 spin_unlock_irqrestore(&ha->vport_slock, flags);
a9083016
GM		 5884 } else {
5885 if (!atomic_read(&vha->loop_down_timer))
5886 atomic_set(&vha->loop_down_timer,
5887 LOOP_DOWN_TIME);
5888 }
5889
6aef87be
AV		 5890 /* Clear all async request states across all VPs. */
5891 list_for_each_entry(fcport, &vha->vp_fcports, list)
5892 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
5893 spin_lock_irqsave(&ha->vport_slock, flags);
5894 list_for_each_entry(vp, &ha->vp_list, list) {
5895 atomic_inc(&vp->vref_count);
5896 spin_unlock_irqrestore(&ha->vport_slock, flags);
5897
5898 list_for_each_entry(fcport, &vp->vp_fcports, list)
5899 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
5900
5901 spin_lock_irqsave(&ha->vport_slock, flags);
5902 atomic_dec(&vp->vref_count);
5903 }
5904 spin_unlock_irqrestore(&ha->vport_slock, flags);
5905
bddd2d65
LC		 5906 if (!ha->flags.eeh_busy) {
5907 /* Make sure for ISP 82XX IO DMA is complete */
7ec0effd 5908 if (IS_P3P_TYPE(ha)) {
7190575f 5909 qla82xx_chip_reset_cleanup(vha);
7c3df132
SK		 5910 ql_log(ql_log_info, vha, 0x00b4,
5911 "Done chip reset cleanup.\n");
a9083016 5912
e46ef004
SK		 5913 /* Done waiting for pending commands.
5914 * Reset the online flag.
5915 */
5916 vha->flags.online = 0;
4d78c973 5917 }
a9083016 5918
bddd2d65
LC		 5919 /* Requeue all commands in outstanding command list. */
5920 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
5921 }
b6a029e1
AE		 5922 /* memory barrier */
5923 wmb();
a9083016
GM		 5924}
5925
1da177e4
LT		 5926/*
5927* qla2x00_abort_isp
5928* Resets ISP and aborts all outstanding commands.
5929*
5930* Input:
5931* ha = adapter block pointer.
5932*
5933* Returns:
5934* 0 = success
5935*/
5936int
e315cd28 5937qla2x00_abort_isp(scsi_qla_host_t *vha)
1da177e4 5938{
476e8978 5939 int rval;
1da177e4 5940 uint8_t status = 0;
e315cd28
AC		 5941 struct qla_hw_data *ha = vha->hw;
5942 struct scsi_qla_host *vp;
73208dfd 5943 struct req_que *req = ha->req_q_map[0];
feafb7b1 5944 unsigned long flags;
1da177e4 5945
e315cd28 5946 if (vha->flags.online) {
a9083016 5947 qla2x00_abort_isp_cleanup(vha);
1da177e4 5948
a6171297
SV		 5949 if (IS_QLA8031(ha)) {
5950 ql_dbg(ql_dbg_p3p, vha, 0xb05c,
5951 "Clearing fcoe driver presence.\n");
5952 if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS)
5953 ql_dbg(ql_dbg_p3p, vha, 0xb073,
5954 "Error while clearing DRV-Presence.\n");
5955 }
5956
85880801
AV		 5957 if (unlikely(pci_channel_offline(ha->pdev) &&
5958 ha->flags.pci_channel_io_perm_failure)) {
5959 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
5960 status = 0;
5961 return status;
5962 }
5963
73208dfd 5964 ha->isp_ops->get_flash_version(vha, req->ring);
30c47662 5965
e315cd28 5966 ha->isp_ops->nvram_config(vha);
1da177e4 5967
e315cd28
AC		 5968 if (!qla2x00_restart_isp(vha)) {
5969 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4 5970
e315cd28 5971 if (!atomic_read(&vha->loop_down_timer)) {
1da177e4
LT		 5972 /*
5973 * Issue marker command only when we are going
5974 * to start the I/O .
5975 */
e315cd28 5976 vha->marker_needed = 1;
1da177e4
LT		 5977 }
5978
e315cd28 5979 vha->flags.online = 1;
1da177e4 5980
fd34f556 5981 ha->isp_ops->enable_intrs(ha);
1da177e4 5982
fa2a1ce5 5983 ha->isp_abort_cnt = 0;
e315cd28 5984 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
476e8978 5985
6246b8a1
GM		 5986 if (IS_QLA81XX(ha) || IS_QLA8031(ha))
5987 qla2x00_get_fw_version(vha);
df613b96
AV		 5988 if (ha->fce) {
5989 ha->flags.fce_enabled = 1;
5990 memset(ha->fce, 0,
5991 fce_calc_size(ha->fce_bufs));
e315cd28 5992 rval = qla2x00_enable_fce_trace(vha,
df613b96
AV		 5993 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
5994 &ha->fce_bufs);
5995 if (rval) {
7c3df132 5996 ql_log(ql_log_warn, vha, 0x8033,
df613b96
AV		 5997 "Unable to reinitialize FCE "
5998 "(%d).\n", rval);
5999 ha->flags.fce_enabled = 0;
6000 }
6001 }
436a7b11
AV		 6002
6003 if (ha->eft) {
6004 memset(ha->eft, 0, EFT_SIZE);
e315cd28 6005 rval = qla2x00_enable_eft_trace(vha,
436a7b11
AV		 6006 ha->eft_dma, EFT_NUM_BUFFERS);
6007 if (rval) {
7c3df132 6008 ql_log(ql_log_warn, vha, 0x8034,
436a7b11
AV		 6009 "Unable to reinitialize EFT "
6010 "(%d).\n", rval);
6011 }
6012 }
1da177e4 6013 } else { /* failed the ISP abort */
e315cd28
AC		 6014 vha->flags.online = 1;
6015 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
1da177e4 6016 if (ha->isp_abort_cnt == 0) {
7c3df132
SK		 6017 ql_log(ql_log_fatal, vha, 0x8035,
6018 "ISP error recover failed - "
6019 "board disabled.\n");
fa2a1ce5 6020 /*
1da177e4
LT		 6021 * The next call disables the board
6022 * completely.
6023 */
e315cd28
AC		 6024 ha->isp_ops->reset_adapter(vha);
6025 vha->flags.online = 0;
1da177e4 6026 clear_bit(ISP_ABORT_RETRY,
e315cd28 6027 &vha->dpc_flags);
1da177e4
LT		 6028 status = 0;
6029 } else { /* schedule another ISP abort */
6030 ha->isp_abort_cnt--;
7c3df132
SK		 6031 ql_dbg(ql_dbg_taskm, vha, 0x8020,
6032 "ISP abort - retry remaining %d.\n",
6033 ha->isp_abort_cnt);
1da177e4
LT		 6034 status = 1;
6035 }
6036 } else {
6037 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
7c3df132
SK		 6038 ql_dbg(ql_dbg_taskm, vha, 0x8021,
6039 "ISP error recovery - retrying (%d) "
6040 "more times.\n", ha->isp_abort_cnt);
e315cd28 6041 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
1da177e4
LT		 6042 status = 1;
6043 }
6044 }
fa2a1ce5 6045
1da177e4
LT		 6046 }
6047
e315cd28 6048 if (!status) {
7c3df132 6049 ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__);
1608cc4a 6050 qla2x00_configure_hba(vha);
feafb7b1
AE		 6051 spin_lock_irqsave(&ha->vport_slock, flags);
6052 list_for_each_entry(vp, &ha->vp_list, list) {
6053 if (vp->vp_idx) {
6054 atomic_inc(&vp->vref_count);
6055 spin_unlock_irqrestore(&ha->vport_slock, flags);
6056
e315cd28 6057 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 6058
6059 spin_lock_irqsave(&ha->vport_slock, flags);
6060 atomic_dec(&vp->vref_count);
6061 }
e315cd28 6062 }
feafb7b1
AE		 6063 spin_unlock_irqrestore(&ha->vport_slock, flags);
6064
7d613ac6
SV		 6065 if (IS_QLA8031(ha)) {
6066 ql_dbg(ql_dbg_p3p, vha, 0xb05d,
6067 "Setting back fcoe driver presence.\n");
6068 if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS)
6069 ql_dbg(ql_dbg_p3p, vha, 0xb074,
6070 "Error while setting DRV-Presence.\n");
6071 }
e315cd28 6072 } else {
d8424f68
JP		 6073 ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n",
6074 __func__);
1da177e4
LT		 6075 }
6076
6077 return(status);
6078}
6079
6080/*
6081* qla2x00_restart_isp
6082* restarts the ISP after a reset
6083*
6084* Input:
6085* ha = adapter block pointer.
6086*
6087* Returns:
6088* 0 = success
6089*/
6090static int
e315cd28 6091qla2x00_restart_isp(scsi_qla_host_t *vha)
1da177e4 6092{
c6b2fca8 6093 int status = 0;
e315cd28 6094 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 6095 struct req_que *req = ha->req_q_map[0];
6096 struct rsp_que *rsp = ha->rsp_q_map[0];
1da177e4
LT		 6097
6098 /* If firmware needs to be loaded */
e315cd28
AC		 6099 if (qla2x00_isp_firmware(vha)) {
6100 vha->flags.online = 0;
6101 status = ha->isp_ops->chip_diag(vha);
6102 if (!status)
6103 status = qla2x00_setup_chip(vha);
1da177e4
LT		 6104 }
6105
e315cd28
AC		 6106 if (!status && !(status = qla2x00_init_rings(vha))) {
6107 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
2533cf67 6108 ha->flags.chip_reset_done = 1;
7108b76e 6109
73208dfd
AC		 6110 /* Initialize the queues in use */
6111 qla25xx_init_queues(ha);
6112
e315cd28
AC		 6113 status = qla2x00_fw_ready(vha);
6114 if (!status) {
0107109e 6115 /* Issue a marker after FW becomes ready. */
73208dfd 6116 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
7108b76e 6117 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4
LT		 6118 }
6119
6120 /* if no cable then assume it's good */
e315cd28 6121 if ((vha->device_flags & DFLG_NO_CABLE))
1da177e4 6122 status = 0;
1da177e4
LT		 6123 }
6124 return (status);
6125}
6126
73208dfd
AC		 6127static int
6128qla25xx_init_queues(struct qla_hw_data *ha)
6129{
6130 struct rsp_que *rsp = NULL;
6131 struct req_que *req = NULL;
6132 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
6133 int ret = -1;
6134 int i;
6135
2afa19a9 6136 for (i = 1; i < ha->max_rsp_queues; i++) {
73208dfd 6137 rsp = ha->rsp_q_map[i];
cb43285f 6138 if (rsp && test_bit(i, ha->rsp_qid_map)) {
73208dfd 6139 rsp->options &= ~BIT_0;
618a7523 6140 ret = qla25xx_init_rsp_que(base_vha, rsp);
73208dfd 6141 if (ret != QLA_SUCCESS)
7c3df132
SK		 6142 ql_dbg(ql_dbg_init, base_vha, 0x00ff,
6143 "%s Rsp que: %d init failed.\n",
6144 __func__, rsp->id);
73208dfd 6145 else
7c3df132
SK		 6146 ql_dbg(ql_dbg_init, base_vha, 0x0100,
6147 "%s Rsp que: %d inited.\n",
6148 __func__, rsp->id);
73208dfd 6149 }
2afa19a9
AC		 6150 }
6151 for (i = 1; i < ha->max_req_queues; i++) {
73208dfd 6152 req = ha->req_q_map[i];
cb43285f
QT		 6153 if (req && test_bit(i, ha->req_qid_map)) {
6154 /* Clear outstanding commands array. */
73208dfd 6155 req->options &= ~BIT_0;
618a7523 6156 ret = qla25xx_init_req_que(base_vha, req);
73208dfd 6157 if (ret != QLA_SUCCESS)
7c3df132
SK		 6158 ql_dbg(ql_dbg_init, base_vha, 0x0101,
6159 "%s Req que: %d init failed.\n",
6160 __func__, req->id);
73208dfd 6161 else
7c3df132
SK		 6162 ql_dbg(ql_dbg_init, base_vha, 0x0102,
6163 "%s Req que: %d inited.\n",
6164 __func__, req->id);
73208dfd
AC		 6165 }
6166 }
6167 return ret;
6168}
6169
1da177e4
LT		 6170/*
6171* qla2x00_reset_adapter
6172* Reset adapter.
6173*
6174* Input:
6175* ha = adapter block pointer.
6176*/
abbd8870 6177void
e315cd28 6178qla2x00_reset_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 6179{
6180 unsigned long flags = 0;
e315cd28 6181 struct qla_hw_data *ha = vha->hw;
3d71644c 6182 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 6183
e315cd28 6184 vha->flags.online = 0;
fd34f556 6185 ha->isp_ops->disable_intrs(ha);
1da177e4 6186
1da177e4
LT		 6187 spin_lock_irqsave(&ha->hardware_lock, flags);
6188 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
6189 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
6190 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
6191 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
6192 spin_unlock_irqrestore(&ha->hardware_lock, flags);
6193}
0107109e
AV		 6194
6195void
e315cd28 6196qla24xx_reset_adapter(scsi_qla_host_t *vha)
0107109e
AV		 6197{
6198 unsigned long flags = 0;
e315cd28 6199 struct qla_hw_data *ha = vha->hw;
0107109e
AV		 6200 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
6201
7ec0effd 6202 if (IS_P3P_TYPE(ha))
a9083016
GM		 6203 return;
6204
e315cd28 6205 vha->flags.online = 0;
fd34f556 6206 ha->isp_ops->disable_intrs(ha);
0107109e
AV		 6207
6208 spin_lock_irqsave(&ha->hardware_lock, flags);
6209 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
6210 RD_REG_DWORD(&reg->hccr);
6211 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
6212 RD_REG_DWORD(&reg->hccr);
6213 spin_unlock_irqrestore(&ha->hardware_lock, flags);
09ff36d3
AV		 6214
6215 if (IS_NOPOLLING_TYPE(ha))
6216 ha->isp_ops->enable_intrs(ha);
0107109e
AV		 6217}
6218
4e08df3f
DM		 6219/* On sparc systems, obtain port and node WWN from firmware
6220 * properties.
6221 */
e315cd28
AC		 6222static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha,
6223 struct nvram_24xx *nv)
4e08df3f
DM		 6224{
6225#ifdef CONFIG_SPARC
e315cd28 6226 struct qla_hw_data *ha = vha->hw;
4e08df3f 6227 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 6228 struct device_node *dp = pci_device_to_OF_node(pdev);
6229 const u8 *val;
4e08df3f
DM		 6230 int len;
6231
6232 val = of_get_property(dp, "port-wwn", &len);
6233 if (val && len >= WWN_SIZE)
6234 memcpy(nv->port_name, val, WWN_SIZE);
6235
6236 val = of_get_property(dp, "node-wwn", &len);
6237 if (val && len >= WWN_SIZE)
6238 memcpy(nv->node_name, val, WWN_SIZE);
6239#endif
6240}
6241
0107109e 6242int
e315cd28 6243qla24xx_nvram_config(scsi_qla_host_t *vha)
0107109e 6244{
4e08df3f 6245 int rval;
0107109e
AV		 6246 struct init_cb_24xx *icb;
6247 struct nvram_24xx *nv;
6248 uint32_t *dptr;
6249 uint8_t *dptr1, *dptr2;
6250 uint32_t chksum;
6251 uint16_t cnt;
e315cd28 6252 struct qla_hw_data *ha = vha->hw;
0107109e 6253
4e08df3f 6254 rval = QLA_SUCCESS;
0107109e 6255 icb = (struct init_cb_24xx *)ha->init_cb;
281afe19 6256 nv = ha->nvram;
0107109e
AV		 6257
6258 /* Determine NVRAM starting address. */
f73cb695 6259 if (ha->port_no == 0) {
e5b68a61
AC		 6260 ha->nvram_base = FA_NVRAM_FUNC0_ADDR;
6261 ha->vpd_base = FA_NVRAM_VPD0_ADDR;
6262 } else {
0107109e 6263 ha->nvram_base = FA_NVRAM_FUNC1_ADDR;
6f641790
AV		 6264 ha->vpd_base = FA_NVRAM_VPD1_ADDR;
6265 }
f73cb695 6266
e5b68a61
AC		 6267 ha->nvram_size = sizeof(struct nvram_24xx);
6268 ha->vpd_size = FA_NVRAM_VPD_SIZE;
0107109e 6269
281afe19
SJ		 6270 /* Get VPD data into cache */
6271 ha->vpd = ha->nvram + VPD_OFFSET;
e315cd28 6272 ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd,
281afe19
SJ		 6273 ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
6274
6275 /* Get NVRAM data into cache and calculate checksum. */
0107109e 6276 dptr = (uint32_t *)nv;
e315cd28 6277 ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base,
0107109e 6278 ha->nvram_size);
da08ef5c
JC		 6279 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++)
6280 chksum += le32_to_cpu(*dptr);
0107109e 6281
7c3df132
SK		 6282 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
6283 "Contents of NVRAM\n");
6284 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
6285 (uint8_t *)nv, ha->nvram_size);
0107109e
AV		 6286
6287 /* Bad NVRAM data, set defaults parameters. */
6288 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
6289 || nv->id[3] != ' ' ||
ad950360 6290 nv->nvram_version < cpu_to_le16(ICB_VERSION)) {
0107109e 6291 /* Reset NVRAM data. */
7c3df132 6292 ql_log(ql_log_warn, vha, 0x006b,
9e336520 6293 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132
SK		 6294 "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version);
6295 ql_log(ql_log_warn, vha, 0x006c,
6296 "Falling back to functioning (yet invalid -- WWPN) "
6297 "defaults.\n");
4e08df3f
DM		 6298
6299 /*
6300 * Set default initialization control block.
6301 */
6302 memset(nv, 0, ha->nvram_size);
ad950360
BVA		 6303 nv->nvram_version = cpu_to_le16(ICB_VERSION);
6304 nv->version = cpu_to_le16(ICB_VERSION);
98aee70d 6305 nv->frame_payload_size = 2048;
ad950360
BVA		 6306 nv->execution_throttle = cpu_to_le16(0xFFFF);
6307 nv->exchange_count = cpu_to_le16(0);
6308 nv->hard_address = cpu_to_le16(124);
4e08df3f 6309 nv->port_name[0] = 0x21;
f73cb695 6310 nv->port_name[1] = 0x00 + ha->port_no + 1;
4e08df3f
DM		 6311 nv->port_name[2] = 0x00;
6312 nv->port_name[3] = 0xe0;
6313 nv->port_name[4] = 0x8b;
6314 nv->port_name[5] = 0x1c;
6315 nv->port_name[6] = 0x55;
6316 nv->port_name[7] = 0x86;
6317 nv->node_name[0] = 0x20;
6318 nv->node_name[1] = 0x00;
6319 nv->node_name[2] = 0x00;
6320 nv->node_name[3] = 0xe0;
6321 nv->node_name[4] = 0x8b;
6322 nv->node_name[5] = 0x1c;
6323 nv->node_name[6] = 0x55;
6324 nv->node_name[7] = 0x86;
e315cd28 6325 qla24xx_nvram_wwn_from_ofw(vha, nv);
ad950360
BVA		 6326 nv->login_retry_count = cpu_to_le16(8);
6327 nv->interrupt_delay_timer = cpu_to_le16(0);
6328 nv->login_timeout = cpu_to_le16(0);
4e08df3f 6329 nv->firmware_options_1 =
ad950360
BVA		 6330 cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
6331 nv->firmware_options_2 = cpu_to_le32(2 << 4);
6332 nv->firmware_options_2 |= cpu_to_le32(BIT_12);
6333 nv->firmware_options_3 = cpu_to_le32(2 << 13);
6334 nv->host_p = cpu_to_le32(BIT_11|BIT_10);
6335 nv->efi_parameters = cpu_to_le32(0);
4e08df3f 6336 nv->reset_delay = 5;
ad950360
BVA		 6337 nv->max_luns_per_target = cpu_to_le16(128);
6338 nv->port_down_retry_count = cpu_to_le16(30);
6339 nv->link_down_timeout = cpu_to_le16(30);
4e08df3f
DM		 6340
6341 rval = 1;
0107109e
AV		 6342 }
6343
726b8548 6344 if (qla_tgt_mode_enabled(vha)) {
2d70c103 6345 /* Don't enable full login after initial LIP */
ad950360 6346 nv->firmware_options_1 &= cpu_to_le32(~BIT_13);
2d70c103 6347 /* Don't enable LIP full login for initiator */
ad950360 6348 nv->host_p &= cpu_to_le32(~BIT_10);
2d70c103
NB		 6349 }
6350
6351 qlt_24xx_config_nvram_stage1(vha, nv);
6352
0107109e 6353 /* Reset Initialization control block */
e315cd28 6354 memset(icb, 0, ha->init_cb_size);
0107109e
AV		 6355
6356 /* Copy 1st segment. */
6357 dptr1 = (uint8_t *)icb;
6358 dptr2 = (uint8_t *)&nv->version;
6359 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
6360 while (cnt--)
6361 *dptr1++ = *dptr2++;
6362
6363 icb->login_retry_count = nv->login_retry_count;
3ea66e28 6364 icb->link_down_on_nos = nv->link_down_on_nos;
0107109e
AV		 6365
6366 /* Copy 2nd segment. */
6367 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
6368 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
6369 cnt = (uint8_t *)&icb->reserved_3 -
6370 (uint8_t *)&icb->interrupt_delay_timer;
6371 while (cnt--)
6372 *dptr1++ = *dptr2++;
6373
6374 /*
6375 * Setup driver NVRAM options.
6376 */
e315cd28 6377 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
9bb9fcf2 6378 "QLA2462");
0107109e 6379
2d70c103
NB		 6380 qlt_24xx_config_nvram_stage2(vha, icb);
6381
ad950360 6382 if (nv->host_p & cpu_to_le32(BIT_15)) {
2d70c103 6383 /* Use alternate WWN? */
5341e868
AV		 6384 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
6385 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
6386 }
6387
0107109e 6388 /* Prepare nodename */
ad950360 6389 if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) {
0107109e
AV		 6390 /*
6391 * Firmware will apply the following mask if the nodename was
6392 * not provided.
6393 */
6394 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
6395 icb->node_name[0] &= 0xF0;
6396 }
6397
6398 /* Set host adapter parameters. */
6399 ha->flags.disable_risc_code_load = 0;
0c8c39af
AV		 6400 ha->flags.enable_lip_reset = 0;
6401 ha->flags.enable_lip_full_login =
6402 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
6403 ha->flags.enable_target_reset =
6404 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
0107109e 6405 ha->flags.enable_led_scheme = 0;
d4c760c2 6406 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
0107109e 6407
fd0e7e4d
AV		 6408 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
6409 (BIT_6 | BIT_5 | BIT_4)) >> 4;
0107109e
AV		 6410
6411 memcpy(ha->fw_seriallink_options24, nv->seriallink_options,
6412 sizeof(ha->fw_seriallink_options24));
6413
6414 /* save HBA serial number */
6415 ha->serial0 = icb->port_name[5];
6416 ha->serial1 = icb->port_name[6];
6417 ha->serial2 = icb->port_name[7];
e315cd28
AC		 6418 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
6419 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
0107109e 6420
ad950360 6421 icb->execution_throttle = cpu_to_le16(0xFFFF);
bc8fb3cb 6422
0107109e
AV		 6423 ha->retry_count = le16_to_cpu(nv->login_retry_count);
6424
6425 /* Set minimum login_timeout to 4 seconds. */
6426 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
6427 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
6428 if (le16_to_cpu(nv->login_timeout) < 4)
ad950360 6429 nv->login_timeout = cpu_to_le16(4);
0107109e 6430 ha->login_timeout = le16_to_cpu(nv->login_timeout);
0107109e 6431
00a537b8
AV		 6432 /* Set minimum RATOV to 100 tenths of a second. */
6433 ha->r_a_tov = 100;
0107109e
AV		 6434
6435 ha->loop_reset_delay = nv->reset_delay;
6436
6437 /* Link Down Timeout = 0:
6438 *
6439 * When Port Down timer expires we will start returning
6440 * I/O's to OS with "DID_NO_CONNECT".
6441 *
6442 * Link Down Timeout != 0:
6443 *
6444 * The driver waits for the link to come up after link down
6445 * before returning I/Os to OS with "DID_NO_CONNECT".
6446 */
6447 if (le16_to_cpu(nv->link_down_timeout) == 0) {
6448 ha->loop_down_abort_time =
6449 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
6450 } else {
6451 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
6452 ha->loop_down_abort_time =
6453 (LOOP_DOWN_TIME - ha->link_down_timeout);
6454 }
6455
6456 /* Need enough time to try and get the port back. */
6457 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
6458 if (qlport_down_retry)
6459 ha->port_down_retry_count = qlport_down_retry;
6460
6461 /* Set login_retry_count */
6462 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
6463 if (ha->port_down_retry_count ==
6464 le16_to_cpu(nv->port_down_retry_count) &&
6465 ha->port_down_retry_count > 3)
6466 ha->login_retry_count = ha->port_down_retry_count;
6467 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
6468 ha->login_retry_count = ha->port_down_retry_count;
6469 if (ql2xloginretrycount)
6470 ha->login_retry_count = ql2xloginretrycount;
6471
4fdfefe5 6472 /* Enable ZIO. */
e315cd28 6473 if (!vha->flags.init_done) {
4fdfefe5
AV		 6474 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
6475 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
6476 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
6477 le16_to_cpu(icb->interrupt_delay_timer): 2;
6478 }
ad950360 6479 icb->firmware_options_2 &= cpu_to_le32(
4fdfefe5 6480 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
e315cd28 6481 vha->flags.process_response_queue = 0;
4fdfefe5 6482 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d
AV		 6483 ha->zio_mode = QLA_ZIO_MODE_6;
6484
7c3df132 6485 ql_log(ql_log_info, vha, 0x006f,
4fdfefe5
AV		 6486 "ZIO mode %d enabled; timer delay (%d us).\n",
6487 ha->zio_mode, ha->zio_timer * 100);
6488
6489 icb->firmware_options_2 |= cpu_to_le32(
6490 (uint32_t)ha->zio_mode);
6491 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
e315cd28 6492 vha->flags.process_response_queue = 1;
4fdfefe5
AV		 6493 }
6494
4e08df3f 6495 if (rval) {
7c3df132
SK		 6496 ql_log(ql_log_warn, vha, 0x0070,
6497 "NVRAM configuration failed.\n");
4e08df3f
DM		 6498 }
6499 return (rval);
0107109e
AV		 6500}
6501
4243c115
SC		 6502uint8_t qla27xx_find_valid_image(struct scsi_qla_host *vha)
6503{
6504 struct qla27xx_image_status pri_image_status, sec_image_status;
6505 uint8_t valid_pri_image, valid_sec_image;
6506 uint32_t *wptr;
6507 uint32_t cnt, chksum, size;
6508 struct qla_hw_data *ha = vha->hw;
6509
6510 valid_pri_image = valid_sec_image = 1;
6511 ha->active_image = 0;
6512 size = sizeof(struct qla27xx_image_status) / sizeof(uint32_t);
6513
6514 if (!ha->flt_region_img_status_pri) {
6515 valid_pri_image = 0;
6516 goto check_sec_image;
6517 }
6518
6519 qla24xx_read_flash_data(vha, (uint32_t *)(&pri_image_status),
6520 ha->flt_region_img_status_pri, size);
6521
6522 if (pri_image_status.signature != QLA27XX_IMG_STATUS_SIGN) {
6523 ql_dbg(ql_dbg_init, vha, 0x018b,
6524 "Primary image signature (0x%x) not valid\n",
6525 pri_image_status.signature);
6526 valid_pri_image = 0;
6527 goto check_sec_image;
6528 }
6529
6530 wptr = (uint32_t *)(&pri_image_status);
6531 cnt = size;
6532
da08ef5c
JC		 6533 for (chksum = 0; cnt--; wptr++)
6534 chksum += le32_to_cpu(*wptr);
41dc529a 6535
4243c115
SC		 6536 if (chksum) {
6537 ql_dbg(ql_dbg_init, vha, 0x018c,
6538 "Checksum validation failed for primary image (0x%x)\n",
6539 chksum);
6540 valid_pri_image = 0;
6541 }
6542
6543check_sec_image:
6544 if (!ha->flt_region_img_status_sec) {
6545 valid_sec_image = 0;
6546 goto check_valid_image;
6547 }
6548
6549 qla24xx_read_flash_data(vha, (uint32_t *)(&sec_image_status),
6550 ha->flt_region_img_status_sec, size);
6551
6552 if (sec_image_status.signature != QLA27XX_IMG_STATUS_SIGN) {
6553 ql_dbg(ql_dbg_init, vha, 0x018d,
6554 "Secondary image signature(0x%x) not valid\n",
6555 sec_image_status.signature);
6556 valid_sec_image = 0;
6557 goto check_valid_image;
6558 }
6559
6560 wptr = (uint32_t *)(&sec_image_status);
6561 cnt = size;
da08ef5c
JC		 6562 for (chksum = 0; cnt--; wptr++)
6563 chksum += le32_to_cpu(*wptr);
4243c115
SC		 6564 if (chksum) {
6565 ql_dbg(ql_dbg_init, vha, 0x018e,
6566 "Checksum validation failed for secondary image (0x%x)\n",
6567 chksum);
6568 valid_sec_image = 0;
6569 }
6570
6571check_valid_image:
6572 if (valid_pri_image && (pri_image_status.image_status_mask & 0x1))
6573 ha->active_image = QLA27XX_PRIMARY_IMAGE;
6574 if (valid_sec_image && (sec_image_status.image_status_mask & 0x1)) {
6575 if (!ha->active_image ||
6576 pri_image_status.generation_number <
6577 sec_image_status.generation_number)
6578 ha->active_image = QLA27XX_SECONDARY_IMAGE;
6579 }
6580
6581 ql_dbg(ql_dbg_init, vha, 0x018f, "%s image\n",
6582 ha->active_image == 0 ? "default bootld and fw" :
6583 ha->active_image == 1 ? "primary" :
6584 ha->active_image == 2 ? "secondary" :
6585 "Invalid");
6586
6587 return ha->active_image;
6588}
6589
413975a0 6590static int
cbc8eb67
AV		 6591qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
6592 uint32_t faddr)
d1c61909 6593{
73208dfd 6594 int rval = QLA_SUCCESS;
d1c61909 6595 int segments, fragment;
d1c61909
AV		 6596 uint32_t *dcode, dlen;
6597 uint32_t risc_addr;
6598 uint32_t risc_size;
6599 uint32_t i;
e315cd28 6600 struct qla_hw_data *ha = vha->hw;
73208dfd 6601 struct req_que *req = ha->req_q_map[0];
eaac30be 6602
7c3df132 6603 ql_dbg(ql_dbg_init, vha, 0x008b,
cfb0919c 6604 "FW: Loading firmware from flash (%x).\n", faddr);
eaac30be 6605
d1c61909
AV		 6606 rval = QLA_SUCCESS;
6607
6608 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 6609 dcode = (uint32_t *)req->ring;
d1c61909
AV		 6610 *srisc_addr = 0;
6611
4243c115
SC		 6612 if (IS_QLA27XX(ha) &&
6613 qla27xx_find_valid_image(vha) == QLA27XX_SECONDARY_IMAGE)
6614 faddr = ha->flt_region_fw_sec;
6615
d1c61909 6616 /* Validate firmware image by checking version. */
e315cd28 6617 qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
d1c61909
AV		 6618 for (i = 0; i < 4; i++)
6619 dcode[i] = be32_to_cpu(dcode[i]);
6620 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
6621 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
6622 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
6623 dcode[3] == 0)) {
7c3df132
SK		 6624 ql_log(ql_log_fatal, vha, 0x008c,
6625 "Unable to verify the integrity of flash firmware "
6626 "image.\n");
6627 ql_log(ql_log_fatal, vha, 0x008d,
6628 "Firmware data: %08x %08x %08x %08x.\n",
6629 dcode[0], dcode[1], dcode[2], dcode[3]);
d1c61909
AV		 6630
6631 return QLA_FUNCTION_FAILED;
6632 }
6633
6634 while (segments && rval == QLA_SUCCESS) {
6635 /* Read segment's load information. */
e315cd28 6636 qla24xx_read_flash_data(vha, dcode, faddr, 4);
d1c61909
AV		 6637
6638 risc_addr = be32_to_cpu(dcode[2]);
6639 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
6640 risc_size = be32_to_cpu(dcode[3]);
6641
6642 fragment = 0;
6643 while (risc_size > 0 && rval == QLA_SUCCESS) {
6644 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
6645 if (dlen > risc_size)
6646 dlen = risc_size;
6647
7c3df132
SK		 6648 ql_dbg(ql_dbg_init, vha, 0x008e,
6649 "Loading risc segment@ risc addr %x "
6650 "number of dwords 0x%x offset 0x%x.\n",
6651 risc_addr, dlen, faddr);
d1c61909 6652
e315cd28 6653 qla24xx_read_flash_data(vha, dcode, faddr, dlen);
d1c61909
AV		 6654 for (i = 0; i < dlen; i++)
6655 dcode[i] = swab32(dcode[i]);
6656
73208dfd 6657 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
d1c61909
AV		 6658 dlen);
6659 if (rval) {
7c3df132
SK		 6660 ql_log(ql_log_fatal, vha, 0x008f,
6661 "Failed to load segment %d of firmware.\n",
6662 fragment);
f261f7af 6663 return QLA_FUNCTION_FAILED;
d1c61909
AV		 6664 }
6665
6666 faddr += dlen;
6667 risc_addr += dlen;
6668 risc_size -= dlen;
6669 fragment++;
6670 }
6671
6672 /* Next segment. */
6673 segments--;
6674 }
6675
f73cb695
CD		 6676 if (!IS_QLA27XX(ha))
6677 return rval;
6678
6679 if (ha->fw_dump_template)
6680 vfree(ha->fw_dump_template);
6681 ha->fw_dump_template = NULL;
6682 ha->fw_dump_template_len = 0;
6683
6684 ql_dbg(ql_dbg_init, vha, 0x0161,
6685 "Loading fwdump template from %x\n", faddr);
6686 qla24xx_read_flash_data(vha, dcode, faddr, 7);
6687 risc_size = be32_to_cpu(dcode[2]);
6688 ql_dbg(ql_dbg_init, vha, 0x0162,
6689 "-> array size %x dwords\n", risc_size);
6690 if (risc_size == 0 || risc_size == ~0)
6691 goto default_template;
6692
6693 dlen = (risc_size - 8) * sizeof(*dcode);
6694 ql_dbg(ql_dbg_init, vha, 0x0163,
6695 "-> template allocating %x bytes...\n", dlen);
6696 ha->fw_dump_template = vmalloc(dlen);
6697 if (!ha->fw_dump_template) {
6698 ql_log(ql_log_warn, vha, 0x0164,
6699 "Failed fwdump template allocate %x bytes.\n", risc_size);
6700 goto default_template;
6701 }
6702
6703 faddr += 7;
6704 risc_size -= 8;
6705 dcode = ha->fw_dump_template;
6706 qla24xx_read_flash_data(vha, dcode, faddr, risc_size);
6707 for (i = 0; i < risc_size; i++)
6708 dcode[i] = le32_to_cpu(dcode[i]);
6709
6710 if (!qla27xx_fwdt_template_valid(dcode)) {
6711 ql_log(ql_log_warn, vha, 0x0165,
6712 "Failed fwdump template validate\n");
6713 goto default_template;
6714 }
6715
6716 dlen = qla27xx_fwdt_template_size(dcode);
6717 ql_dbg(ql_dbg_init, vha, 0x0166,
6718 "-> template size %x bytes\n", dlen);
6719 if (dlen > risc_size * sizeof(*dcode)) {
6720 ql_log(ql_log_warn, vha, 0x0167,
4fae52b5 6721 "Failed fwdump template exceeds array by %zx bytes\n",
383a298b 6722 (size_t)(dlen - risc_size * sizeof(*dcode)));
f73cb695
CD		 6723 goto default_template;
6724 }
6725 ha->fw_dump_template_len = dlen;
6726 return rval;
6727
6728default_template:
6729 ql_log(ql_log_warn, vha, 0x0168, "Using default fwdump template\n");
6730 if (ha->fw_dump_template)
6731 vfree(ha->fw_dump_template);
6732 ha->fw_dump_template = NULL;
6733 ha->fw_dump_template_len = 0;
6734
6735 dlen = qla27xx_fwdt_template_default_size();
6736 ql_dbg(ql_dbg_init, vha, 0x0169,
6737 "-> template allocating %x bytes...\n", dlen);
6738 ha->fw_dump_template = vmalloc(dlen);
6739 if (!ha->fw_dump_template) {
6740 ql_log(ql_log_warn, vha, 0x016a,
6741 "Failed fwdump template allocate %x bytes.\n", risc_size);
6742 goto failed_template;
6743 }
6744
6745 dcode = ha->fw_dump_template;
6746 risc_size = dlen / sizeof(*dcode);
6747 memcpy(dcode, qla27xx_fwdt_template_default(), dlen);
6748 for (i = 0; i < risc_size; i++)
6749 dcode[i] = be32_to_cpu(dcode[i]);
6750
6751 if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) {
6752 ql_log(ql_log_warn, vha, 0x016b,
6753 "Failed fwdump template validate\n");
6754 goto failed_template;
6755 }
6756
6757 dlen = qla27xx_fwdt_template_size(ha->fw_dump_template);
6758 ql_dbg(ql_dbg_init, vha, 0x016c,
6759 "-> template size %x bytes\n", dlen);
6760 ha->fw_dump_template_len = dlen;
6761 return rval;
6762
6763failed_template:
6764 ql_log(ql_log_warn, vha, 0x016d, "Failed default fwdump template\n");
6765 if (ha->fw_dump_template)
6766 vfree(ha->fw_dump_template);
6767 ha->fw_dump_template = NULL;
6768 ha->fw_dump_template_len = 0;
d1c61909
AV		 6769 return rval;
6770}
6771
e9454a88 6772#define QLA_FW_URL "http://ldriver.qlogic.com/firmware/"
d1c61909 6773
0107109e 6774int
e315cd28 6775qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5433383e
AV		 6776{
6777 int rval;
6778 int i, fragment;
6779 uint16_t *wcode, *fwcode;
6780 uint32_t risc_addr, risc_size, fwclen, wlen, *seg;
6781 struct fw_blob *blob;
e315cd28 6782 struct qla_hw_data *ha = vha->hw;
73208dfd 6783 struct req_que *req = ha->req_q_map[0];
5433383e
AV		 6784
6785 /* Load firmware blob. */
e315cd28 6786 blob = qla2x00_request_firmware(vha);
5433383e 6787 if (!blob) {
7c3df132 6788 ql_log(ql_log_info, vha, 0x0083,
94bcf830 6789 "Firmware image unavailable.\n");
7c3df132
SK		 6790 ql_log(ql_log_info, vha, 0x0084,
6791 "Firmware images can be retrieved from: "QLA_FW_URL ".\n");
5433383e
AV		 6792 return QLA_FUNCTION_FAILED;
6793 }
6794
6795 rval = QLA_SUCCESS;
6796
73208dfd 6797 wcode = (uint16_t *)req->ring;
5433383e
AV		 6798 *srisc_addr = 0;
6799 fwcode = (uint16_t *)blob->fw->data;
6800 fwclen = 0;
6801
6802 /* Validate firmware image by checking version. */
6803 if (blob->fw->size < 8 * sizeof(uint16_t)) {
7c3df132 6804 ql_log(ql_log_fatal, vha, 0x0085,
5b5e0928 6805 "Unable to verify integrity of firmware image (%zd).\n",
5433383e
AV		 6806 blob->fw->size);
6807 goto fail_fw_integrity;
6808 }
6809 for (i = 0; i < 4; i++)
6810 wcode[i] = be16_to_cpu(fwcode[i + 4]);
6811 if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff &&
6812 wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 &&
6813 wcode[2] == 0 && wcode[3] == 0)) {
7c3df132
SK		 6814 ql_log(ql_log_fatal, vha, 0x0086,
6815 "Unable to verify integrity of firmware image.\n");
6816 ql_log(ql_log_fatal, vha, 0x0087,
6817 "Firmware data: %04x %04x %04x %04x.\n",
6818 wcode[0], wcode[1], wcode[2], wcode[3]);
5433383e
AV		 6819 goto fail_fw_integrity;
6820 }
6821
6822 seg = blob->segs;
6823 while (*seg && rval == QLA_SUCCESS) {
6824 risc_addr = *seg;
6825 *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr;
6826 risc_size = be16_to_cpu(fwcode[3]);
6827
6828 /* Validate firmware image size. */
6829 fwclen += risc_size * sizeof(uint16_t);
6830 if (blob->fw->size < fwclen) {
7c3df132 6831 ql_log(ql_log_fatal, vha, 0x0088,
5433383e 6832 "Unable to verify integrity of firmware image "
5b5e0928 6833 "(%zd).\n", blob->fw->size);
5433383e
AV		 6834 goto fail_fw_integrity;
6835 }
6836
6837 fragment = 0;
6838 while (risc_size > 0 && rval == QLA_SUCCESS) {
6839 wlen = (uint16_t)(ha->fw_transfer_size >> 1);
6840 if (wlen > risc_size)
6841 wlen = risc_size;
7c3df132
SK		 6842 ql_dbg(ql_dbg_init, vha, 0x0089,
6843 "Loading risc segment@ risc addr %x number of "
6844 "words 0x%x.\n", risc_addr, wlen);
5433383e
AV		 6845
6846 for (i = 0; i < wlen; i++)
6847 wcode[i] = swab16(fwcode[i]);
6848
73208dfd 6849 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
5433383e
AV		 6850 wlen);
6851 if (rval) {
7c3df132
SK		 6852 ql_log(ql_log_fatal, vha, 0x008a,
6853 "Failed to load segment %d of firmware.\n",
6854 fragment);
5433383e
AV		 6855 break;
6856 }
6857
6858 fwcode += wlen;
6859 risc_addr += wlen;
6860 risc_size -= wlen;
6861 fragment++;
6862 }
6863
6864 /* Next segment. */
6865 seg++;
6866 }
6867 return rval;
6868
6869fail_fw_integrity:
6870 return QLA_FUNCTION_FAILED;
6871}
6872
eaac30be
AV		 6873static int
6874qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
0107109e
AV		 6875{
6876 int rval;
6877 int segments, fragment;
6878 uint32_t *dcode, dlen;
6879 uint32_t risc_addr;
6880 uint32_t risc_size;
6881 uint32_t i;
5433383e 6882 struct fw_blob *blob;
f73cb695
CD		 6883 const uint32_t *fwcode;
6884 uint32_t fwclen;
e315cd28 6885 struct qla_hw_data *ha = vha->hw;
73208dfd 6886 struct req_que *req = ha->req_q_map[0];
0107109e 6887
5433383e 6888 /* Load firmware blob. */
e315cd28 6889 blob = qla2x00_request_firmware(vha);
5433383e 6890 if (!blob) {
7c3df132 6891 ql_log(ql_log_warn, vha, 0x0090,
94bcf830 6892 "Firmware image unavailable.\n");
7c3df132
SK		 6893 ql_log(ql_log_warn, vha, 0x0091,
6894 "Firmware images can be retrieved from: "
6895 QLA_FW_URL ".\n");
d1c61909 6896
eaac30be 6897 return QLA_FUNCTION_FAILED;
0107109e
AV		 6898 }
6899
cfb0919c
CD		 6900 ql_dbg(ql_dbg_init, vha, 0x0092,
6901 "FW: Loading via request-firmware.\n");
eaac30be 6902
0107109e
AV		 6903 rval = QLA_SUCCESS;
6904
6905 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 6906 dcode = (uint32_t *)req->ring;
0107109e 6907 *srisc_addr = 0;
5433383e 6908 fwcode = (uint32_t *)blob->fw->data;
0107109e
AV		 6909 fwclen = 0;
6910
6911 /* Validate firmware image by checking version. */
5433383e 6912 if (blob->fw->size < 8 * sizeof(uint32_t)) {
7c3df132 6913 ql_log(ql_log_fatal, vha, 0x0093,
5b5e0928 6914 "Unable to verify integrity of firmware image (%zd).\n",
5433383e 6915 blob->fw->size);
f73cb695 6916 return QLA_FUNCTION_FAILED;
0107109e
AV		 6917 }
6918 for (i = 0; i < 4; i++)
6919 dcode[i] = be32_to_cpu(fwcode[i + 4]);
6920 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
6921 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
6922 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
6923 dcode[3] == 0)) {
7c3df132 6924 ql_log(ql_log_fatal, vha, 0x0094,
5b5e0928 6925 "Unable to verify integrity of firmware image (%zd).\n",
7c3df132
SK		 6926 blob->fw->size);
6927 ql_log(ql_log_fatal, vha, 0x0095,
6928 "Firmware data: %08x %08x %08x %08x.\n",
6929 dcode[0], dcode[1], dcode[2], dcode[3]);
f73cb695 6930 return QLA_FUNCTION_FAILED;
0107109e
AV		 6931 }
6932
6933 while (segments && rval == QLA_SUCCESS) {
6934 risc_addr = be32_to_cpu(fwcode[2]);
6935 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
6936 risc_size = be32_to_cpu(fwcode[3]);
6937
6938 /* Validate firmware image size. */
6939 fwclen += risc_size * sizeof(uint32_t);
5433383e 6940 if (blob->fw->size < fwclen) {
7c3df132 6941 ql_log(ql_log_fatal, vha, 0x0096,
5433383e 6942 "Unable to verify integrity of firmware image "
5b5e0928 6943 "(%zd).\n", blob->fw->size);
f73cb695 6944 return QLA_FUNCTION_FAILED;
0107109e
AV		 6945 }
6946
6947 fragment = 0;
6948 while (risc_size > 0 && rval == QLA_SUCCESS) {
6949 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
6950 if (dlen > risc_size)
6951 dlen = risc_size;
6952
7c3df132
SK		 6953 ql_dbg(ql_dbg_init, vha, 0x0097,
6954 "Loading risc segment@ risc addr %x "
6955 "number of dwords 0x%x.\n", risc_addr, dlen);
0107109e
AV		 6956
6957 for (i = 0; i < dlen; i++)
6958 dcode[i] = swab32(fwcode[i]);
6959
73208dfd 6960 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
590f98e5 6961 dlen);
0107109e 6962 if (rval) {
7c3df132
SK		 6963 ql_log(ql_log_fatal, vha, 0x0098,
6964 "Failed to load segment %d of firmware.\n",
6965 fragment);
f261f7af 6966 return QLA_FUNCTION_FAILED;
0107109e
AV		 6967 }
6968
6969 fwcode += dlen;
6970 risc_addr += dlen;
6971 risc_size -= dlen;
6972 fragment++;
6973 }
6974
6975 /* Next segment. */
6976 segments--;
6977 }
f73cb695
CD		 6978
6979 if (!IS_QLA27XX(ha))
6980 return rval;
6981
6982 if (ha->fw_dump_template)
6983 vfree(ha->fw_dump_template);
6984 ha->fw_dump_template = NULL;
6985 ha->fw_dump_template_len = 0;
6986
6987 ql_dbg(ql_dbg_init, vha, 0x171,
97ea702b
CD		 6988 "Loading fwdump template from %x\n",
6989 (uint32_t)((void *)fwcode - (void *)blob->fw->data));
f73cb695
CD		 6990 risc_size = be32_to_cpu(fwcode[2]);
6991 ql_dbg(ql_dbg_init, vha, 0x172,
6992 "-> array size %x dwords\n", risc_size);
6993 if (risc_size == 0 || risc_size == ~0)
6994 goto default_template;
6995
6996 dlen = (risc_size - 8) * sizeof(*fwcode);
6997 ql_dbg(ql_dbg_init, vha, 0x0173,
6998 "-> template allocating %x bytes...\n", dlen);
6999 ha->fw_dump_template = vmalloc(dlen);
7000 if (!ha->fw_dump_template) {
7001 ql_log(ql_log_warn, vha, 0x0174,
7002 "Failed fwdump template allocate %x bytes.\n", risc_size);
7003 goto default_template;
7004 }
7005
7006 fwcode += 7;
7007 risc_size -= 8;
7008 dcode = ha->fw_dump_template;
7009 for (i = 0; i < risc_size; i++)
7010 dcode[i] = le32_to_cpu(fwcode[i]);
7011
7012 if (!qla27xx_fwdt_template_valid(dcode)) {
7013 ql_log(ql_log_warn, vha, 0x0175,
7014 "Failed fwdump template validate\n");
7015 goto default_template;
7016 }
7017
7018 dlen = qla27xx_fwdt_template_size(dcode);
7019 ql_dbg(ql_dbg_init, vha, 0x0176,
7020 "-> template size %x bytes\n", dlen);
7021 if (dlen > risc_size * sizeof(*fwcode)) {
7022 ql_log(ql_log_warn, vha, 0x0177,
4fae52b5 7023 "Failed fwdump template exceeds array by %zx bytes\n",
383a298b 7024 (size_t)(dlen - risc_size * sizeof(*fwcode)));
f73cb695
CD		 7025 goto default_template;
7026 }
7027 ha->fw_dump_template_len = dlen;
0107109e
AV		 7028 return rval;
7029
f73cb695
CD		 7030default_template:
7031 ql_log(ql_log_warn, vha, 0x0178, "Using default fwdump template\n");
7032 if (ha->fw_dump_template)
7033 vfree(ha->fw_dump_template);
7034 ha->fw_dump_template = NULL;
7035 ha->fw_dump_template_len = 0;
7036
7037 dlen = qla27xx_fwdt_template_default_size();
7038 ql_dbg(ql_dbg_init, vha, 0x0179,
7039 "-> template allocating %x bytes...\n", dlen);
7040 ha->fw_dump_template = vmalloc(dlen);
7041 if (!ha->fw_dump_template) {
7042 ql_log(ql_log_warn, vha, 0x017a,
7043 "Failed fwdump template allocate %x bytes.\n", risc_size);
7044 goto failed_template;
7045 }
7046
7047 dcode = ha->fw_dump_template;
7048 risc_size = dlen / sizeof(*fwcode);
7049 fwcode = qla27xx_fwdt_template_default();
7050 for (i = 0; i < risc_size; i++)
7051 dcode[i] = be32_to_cpu(fwcode[i]);
7052
7053 if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) {
7054 ql_log(ql_log_warn, vha, 0x017b,
7055 "Failed fwdump template validate\n");
7056 goto failed_template;
7057 }
7058
7059 dlen = qla27xx_fwdt_template_size(ha->fw_dump_template);
7060 ql_dbg(ql_dbg_init, vha, 0x017c,
7061 "-> template size %x bytes\n", dlen);
7062 ha->fw_dump_template_len = dlen;
7063 return rval;
7064
7065failed_template:
7066 ql_log(ql_log_warn, vha, 0x017d, "Failed default fwdump template\n");
7067 if (ha->fw_dump_template)
7068 vfree(ha->fw_dump_template);
7069 ha->fw_dump_template = NULL;
7070 ha->fw_dump_template_len = 0;
7071 return rval;
0107109e 7072}
18c6c127 7073
eaac30be
AV		 7074int
7075qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
7076{
7077 int rval;
7078
e337d907
AV		 7079 if (ql2xfwloadbin == 1)
7080 return qla81xx_load_risc(vha, srisc_addr);
7081
eaac30be
AV		 7082 /*
7083 * FW Load priority:
7084 * 1) Firmware via request-firmware interface (.bin file).
7085 * 2) Firmware residing in flash.
7086 */
7087 rval = qla24xx_load_risc_blob(vha, srisc_addr);
7088 if (rval == QLA_SUCCESS)
7089 return rval;
7090
cbc8eb67
AV		 7091 return qla24xx_load_risc_flash(vha, srisc_addr,
7092 vha->hw->flt_region_fw);
eaac30be
AV		 7093}
7094
7095int
7096qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
7097{
7098 int rval;
cbc8eb67 7099 struct qla_hw_data *ha = vha->hw;
eaac30be 7100
e337d907 7101 if (ql2xfwloadbin == 2)
cbc8eb67 7102 goto try_blob_fw;
e337d907 7103
eaac30be
AV		 7104 /*
7105 * FW Load priority:
7106 * 1) Firmware residing in flash.
7107 * 2) Firmware via request-firmware interface (.bin file).
cbc8eb67 7108 * 3) Golden-Firmware residing in flash -- limited operation.
eaac30be 7109 */
cbc8eb67 7110 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
eaac30be
AV		 7111 if (rval == QLA_SUCCESS)
7112 return rval;
7113
cbc8eb67
AV		 7114try_blob_fw:
7115 rval = qla24xx_load_risc_blob(vha, srisc_addr);
7116 if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw)
7117 return rval;
7118
7c3df132
SK		 7119 ql_log(ql_log_info, vha, 0x0099,
7120 "Attempting to fallback to golden firmware.\n");
cbc8eb67
AV		 7121 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
7122 if (rval != QLA_SUCCESS)
7123 return rval;
7124
7c3df132 7125 ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n");
cbc8eb67 7126 ha->flags.running_gold_fw = 1;
cbc8eb67 7127 return rval;
eaac30be
AV		 7128}
7129
18c6c127 7130void
e315cd28 7131qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha)
18c6c127
AV		 7132{
7133 int ret, retries;
e315cd28 7134 struct qla_hw_data *ha = vha->hw;
18c6c127 7135
85880801
AV		 7136 if (ha->flags.pci_channel_io_perm_failure)
7137 return;
e428924c 7138 if (!IS_FWI2_CAPABLE(ha))
18c6c127 7139 return;
75edf81d
AV		 7140 if (!ha->fw_major_version)
7141 return;
ec7193e2
QT		 7142 if (!ha->flags.fw_started)
7143 return;
18c6c127 7144
e315cd28 7145 ret = qla2x00_stop_firmware(vha);
7c7f1f29 7146 for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&
b469a7cb 7147 ret != QLA_INVALID_COMMAND && retries ; retries--) {
e315cd28
AC		 7148 ha->isp_ops->reset_chip(vha);
7149 if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS)
18c6c127 7150 continue;
e315cd28 7151 if (qla2x00_setup_chip(vha) != QLA_SUCCESS)
18c6c127 7152 continue;
7c3df132
SK		 7153 ql_log(ql_log_info, vha, 0x8015,
7154 "Attempting retry of stop-firmware command.\n");
e315cd28 7155 ret = qla2x00_stop_firmware(vha);
18c6c127 7156 }
ec7193e2 7157
4b60c827 7158 QLA_FW_STOPPED(ha);
ec7193e2 7159 ha->flags.fw_init_done = 0;
18c6c127 7160}
2c3dfe3f
SJ		 7161
7162int
e315cd28 7163qla24xx_configure_vhba(scsi_qla_host_t *vha)
2c3dfe3f
SJ		 7164{
7165 int rval = QLA_SUCCESS;
0b91d116 7166 int rval2;
2c3dfe3f 7167 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28
AC		 7168 struct qla_hw_data *ha = vha->hw;
7169 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
67c2e93a
AC		 7170 struct req_que *req;
7171 struct rsp_que *rsp;
2c3dfe3f 7172
e315cd28 7173 if (!vha->vp_idx)
2c3dfe3f
SJ		 7174 return -EINVAL;
7175
e315cd28 7176 rval = qla2x00_fw_ready(base_vha);
d7459527
MH		 7177 if (vha->qpair)
7178 req = vha->qpair->req;
67c2e93a 7179 else
d7459527 7180 req = ha->req_q_map[0];
67c2e93a
AC		 7181 rsp = req->rsp;
7182
2c3dfe3f 7183 if (rval == QLA_SUCCESS) {
e315cd28 7184 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
73208dfd 7185 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
2c3dfe3f
SJ		 7186 }
7187
e315cd28 7188 vha->flags.management_server_logged_in = 0;
2c3dfe3f
SJ		 7189
7190 /* Login to SNS first */
0b91d116
CD		 7191 rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb,
7192 BIT_1);
7193 if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
7194 if (rval2 == QLA_MEMORY_ALLOC_FAILED)
7195 ql_dbg(ql_dbg_init, vha, 0x0120,
7196 "Failed SNS login: loop_id=%x, rval2=%d\n",
7197 NPH_SNS, rval2);
7198 else
7199 ql_dbg(ql_dbg_init, vha, 0x0103,
7200 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x "
7201 "mb[2]=%x mb[6]=%x mb[7]=%x.\n",
7202 NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]);
2c3dfe3f
SJ		 7203 return (QLA_FUNCTION_FAILED);
7204 }
7205
e315cd28
AC		 7206 atomic_set(&vha->loop_down_timer, 0);
7207 atomic_set(&vha->loop_state, LOOP_UP);
7208 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
7209 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
7210 rval = qla2x00_loop_resync(base_vha);
2c3dfe3f
SJ		 7211
7212 return rval;
7213}
4d4df193
HK		 7214
7215/* 84XX Support **************************************************************/
7216
7217static LIST_HEAD(qla_cs84xx_list);
7218static DEFINE_MUTEX(qla_cs84xx_mutex);
7219
7220static struct qla_chip_state_84xx *
e315cd28 7221qla84xx_get_chip(struct scsi_qla_host *vha)
4d4df193
HK		 7222{
7223 struct qla_chip_state_84xx *cs84xx;
e315cd28 7224 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 7225
7226 mutex_lock(&qla_cs84xx_mutex);
7227
7228 /* Find any shared 84xx chip. */
7229 list_for_each_entry(cs84xx, &qla_cs84xx_list, list) {
7230 if (cs84xx->bus == ha->pdev->bus) {
7231 kref_get(&cs84xx->kref);
7232 goto done;
7233 }
7234 }
7235
7236 cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL);
7237 if (!cs84xx)
7238 goto done;
7239
7240 kref_init(&cs84xx->kref);
7241 spin_lock_init(&cs84xx->access_lock);
7242 mutex_init(&cs84xx->fw_update_mutex);
7243 cs84xx->bus = ha->pdev->bus;
7244
7245 list_add_tail(&cs84xx->list, &qla_cs84xx_list);
7246done:
7247 mutex_unlock(&qla_cs84xx_mutex);
7248 return cs84xx;
7249}
7250
7251static void
7252__qla84xx_chip_release(struct kref *kref)
7253{
7254 struct qla_chip_state_84xx *cs84xx =
7255 container_of(kref, struct qla_chip_state_84xx, kref);
7256
7257 mutex_lock(&qla_cs84xx_mutex);
7258 list_del(&cs84xx->list);
7259 mutex_unlock(&qla_cs84xx_mutex);
7260 kfree(cs84xx);
7261}
7262
7263void
e315cd28 7264qla84xx_put_chip(struct scsi_qla_host *vha)
4d4df193 7265{
e315cd28 7266 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 7267 if (ha->cs84xx)
7268 kref_put(&ha->cs84xx->kref, __qla84xx_chip_release);
7269}
7270
7271static int
e315cd28 7272qla84xx_init_chip(scsi_qla_host_t *vha)
4d4df193
HK		 7273{
7274 int rval;
7275 uint16_t status[2];
e315cd28 7276 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 7277
7278 mutex_lock(&ha->cs84xx->fw_update_mutex);
7279
e315cd28 7280 rval = qla84xx_verify_chip(vha, status);
4d4df193
HK		 7281
7282 mutex_unlock(&ha->cs84xx->fw_update_mutex);
7283
7284 return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED:
7285 QLA_SUCCESS;
7286}
3a03eb79
AV		 7287
7288/* 81XX Support **************************************************************/
7289
7290int
7291qla81xx_nvram_config(scsi_qla_host_t *vha)
7292{
7293 int rval;
7294 struct init_cb_81xx *icb;
7295 struct nvram_81xx *nv;
7296 uint32_t *dptr;
7297 uint8_t *dptr1, *dptr2;
7298 uint32_t chksum;
7299 uint16_t cnt;
7300 struct qla_hw_data *ha = vha->hw;
7301
7302 rval = QLA_SUCCESS;
7303 icb = (struct init_cb_81xx *)ha->init_cb;
7304 nv = ha->nvram;
7305
7306 /* Determine NVRAM starting address. */
7307 ha->nvram_size = sizeof(struct nvram_81xx);
3a03eb79 7308 ha->vpd_size = FA_NVRAM_VPD_SIZE;
7ec0effd
AD		 7309 if (IS_P3P_TYPE(ha) || IS_QLA8031(ha))
7310 ha->vpd_size = FA_VPD_SIZE_82XX;
3a03eb79
AV		 7311
7312 /* Get VPD data into cache */
7313 ha->vpd = ha->nvram + VPD_OFFSET;
3d79038f
AV		 7314 ha->isp_ops->read_optrom(vha, ha->vpd, ha->flt_region_vpd << 2,
7315 ha->vpd_size);
3a03eb79
AV		 7316
7317 /* Get NVRAM data into cache and calculate checksum. */
3d79038f 7318 ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2,
3a03eb79 7319 ha->nvram_size);
3d79038f 7320 dptr = (uint32_t *)nv;
da08ef5c
JC		 7321 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++)
7322 chksum += le32_to_cpu(*dptr);
3a03eb79 7323
7c3df132
SK		 7324 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
7325 "Contents of NVRAM:\n");
7326 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
7327 (uint8_t *)nv, ha->nvram_size);
3a03eb79
AV		 7328
7329 /* Bad NVRAM data, set defaults parameters. */
7330 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
7331 || nv->id[3] != ' ' ||
ad950360 7332 nv->nvram_version < cpu_to_le16(ICB_VERSION)) {
3a03eb79 7333 /* Reset NVRAM data. */
7c3df132 7334 ql_log(ql_log_info, vha, 0x0073,
9e336520 7335 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132 7336 "version=0x%x.\n", chksum, nv->id[0],
3a03eb79 7337 le16_to_cpu(nv->nvram_version));
7c3df132
SK		 7338 ql_log(ql_log_info, vha, 0x0074,
7339 "Falling back to functioning (yet invalid -- WWPN) "
7340 "defaults.\n");
3a03eb79
AV		 7341
7342 /*
7343 * Set default initialization control block.
7344 */
7345 memset(nv, 0, ha->nvram_size);
ad950360
BVA		 7346 nv->nvram_version = cpu_to_le16(ICB_VERSION);
7347 nv->version = cpu_to_le16(ICB_VERSION);
98aee70d 7348 nv->frame_payload_size = 2048;
ad950360
BVA		 7349 nv->execution_throttle = cpu_to_le16(0xFFFF);
7350 nv->exchange_count = cpu_to_le16(0);
3a03eb79 7351 nv->port_name[0] = 0x21;
f73cb695 7352 nv->port_name[1] = 0x00 + ha->port_no + 1;
3a03eb79
AV		 7353 nv->port_name[2] = 0x00;
7354 nv->port_name[3] = 0xe0;
7355 nv->port_name[4] = 0x8b;
7356 nv->port_name[5] = 0x1c;
7357 nv->port_name[6] = 0x55;
7358 nv->port_name[7] = 0x86;
7359 nv->node_name[0] = 0x20;
7360 nv->node_name[1] = 0x00;
7361 nv->node_name[2] = 0x00;
7362 nv->node_name[3] = 0xe0;
7363 nv->node_name[4] = 0x8b;
7364 nv->node_name[5] = 0x1c;
7365 nv->node_name[6] = 0x55;
7366 nv->node_name[7] = 0x86;
ad950360
BVA		 7367 nv->login_retry_count = cpu_to_le16(8);
7368 nv->interrupt_delay_timer = cpu_to_le16(0);
7369 nv->login_timeout = cpu_to_le16(0);
3a03eb79 7370 nv->firmware_options_1 =
ad950360
BVA		 7371 cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
7372 nv->firmware_options_2 = cpu_to_le32(2 << 4);
7373 nv->firmware_options_2 |= cpu_to_le32(BIT_12);
7374 nv->firmware_options_3 = cpu_to_le32(2 << 13);
7375 nv->host_p = cpu_to_le32(BIT_11|BIT_10);
7376 nv->efi_parameters = cpu_to_le32(0);
3a03eb79 7377 nv->reset_delay = 5;
ad950360
BVA		 7378 nv->max_luns_per_target = cpu_to_le16(128);
7379 nv->port_down_retry_count = cpu_to_le16(30);
7380 nv->link_down_timeout = cpu_to_le16(180);
eeebcc92 7381 nv->enode_mac[0] = 0x00;
6246b8a1
GM		 7382 nv->enode_mac[1] = 0xC0;
7383 nv->enode_mac[2] = 0xDD;
3a03eb79
AV		 7384 nv->enode_mac[3] = 0x04;
7385 nv->enode_mac[4] = 0x05;
f73cb695 7386 nv->enode_mac[5] = 0x06 + ha->port_no + 1;
3a03eb79
AV		 7387
7388 rval = 1;
7389 }
7390
9e522cd8
AE		 7391 if (IS_T10_PI_CAPABLE(ha))
7392 nv->frame_payload_size &= ~7;
7393
aa230bc5
AE		 7394 qlt_81xx_config_nvram_stage1(vha, nv);
7395
3a03eb79 7396 /* Reset Initialization control block */
773120e4 7397 memset(icb, 0, ha->init_cb_size);
3a03eb79
AV		 7398
7399 /* Copy 1st segment. */
7400 dptr1 = (uint8_t *)icb;
7401 dptr2 = (uint8_t *)&nv->version;
7402 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
7403 while (cnt--)
7404 *dptr1++ = *dptr2++;
7405
7406 icb->login_retry_count = nv->login_retry_count;
7407
7408 /* Copy 2nd segment. */
7409 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
7410 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
7411 cnt = (uint8_t *)&icb->reserved_5 -
7412 (uint8_t *)&icb->interrupt_delay_timer;
7413 while (cnt--)
7414 *dptr1++ = *dptr2++;
7415
7416 memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac));
7417 /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */
7418 if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) {
69e5f1ea
AV		 7419 icb->enode_mac[0] = 0x00;
7420 icb->enode_mac[1] = 0xC0;
7421 icb->enode_mac[2] = 0xDD;
3a03eb79
AV		 7422 icb->enode_mac[3] = 0x04;
7423 icb->enode_mac[4] = 0x05;
f73cb695 7424 icb->enode_mac[5] = 0x06 + ha->port_no + 1;
3a03eb79
AV		 7425 }
7426
b64b0e8f
AV		 7427 /* Use extended-initialization control block. */
7428 memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb));
7429
3a03eb79
AV		 7430 /*
7431 * Setup driver NVRAM options.
7432 */
7433 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
a9083016 7434 "QLE8XXX");
3a03eb79 7435
aa230bc5
AE		 7436 qlt_81xx_config_nvram_stage2(vha, icb);
7437
3a03eb79 7438 /* Use alternate WWN? */
ad950360 7439 if (nv->host_p & cpu_to_le32(BIT_15)) {
3a03eb79
AV		 7440 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
7441 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
7442 }
7443
7444 /* Prepare nodename */
ad950360 7445 if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) {
3a03eb79
AV		 7446 /*
7447 * Firmware will apply the following mask if the nodename was
7448 * not provided.
7449 */
7450 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
7451 icb->node_name[0] &= 0xF0;
7452 }
7453
7454 /* Set host adapter parameters. */
7455 ha->flags.disable_risc_code_load = 0;
7456 ha->flags.enable_lip_reset = 0;
7457 ha->flags.enable_lip_full_login =
7458 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
7459 ha->flags.enable_target_reset =
7460 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
7461 ha->flags.enable_led_scheme = 0;
7462 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
7463
7464 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
7465 (BIT_6 | BIT_5 | BIT_4)) >> 4;
7466
7467 /* save HBA serial number */
7468 ha->serial0 = icb->port_name[5];
7469 ha->serial1 = icb->port_name[6];
7470 ha->serial2 = icb->port_name[7];
7471 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
7472 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
7473
ad950360 7474 icb->execution_throttle = cpu_to_le16(0xFFFF);
3a03eb79
AV		 7475
7476 ha->retry_count = le16_to_cpu(nv->login_retry_count);
7477
7478 /* Set minimum login_timeout to 4 seconds. */
7479 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
7480 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
7481 if (le16_to_cpu(nv->login_timeout) < 4)
ad950360 7482 nv->login_timeout = cpu_to_le16(4);
3a03eb79 7483 ha->login_timeout = le16_to_cpu(nv->login_timeout);
3a03eb79
AV		 7484
7485 /* Set minimum RATOV to 100 tenths of a second. */
7486 ha->r_a_tov = 100;
7487
7488 ha->loop_reset_delay = nv->reset_delay;
7489
7490 /* Link Down Timeout = 0:
7491 *
7ec0effd 7492 * When Port Down timer expires we will start returning
3a03eb79
AV		 7493 * I/O's to OS with "DID_NO_CONNECT".
7494 *
7495 * Link Down Timeout != 0:
7496 *
7497 * The driver waits for the link to come up after link down
7498 * before returning I/Os to OS with "DID_NO_CONNECT".
7499 */
7500 if (le16_to_cpu(nv->link_down_timeout) == 0) {
7501 ha->loop_down_abort_time =
7502 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
7503 } else {
7504 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
7505 ha->loop_down_abort_time =
7506 (LOOP_DOWN_TIME - ha->link_down_timeout);
7507 }
7508
7509 /* Need enough time to try and get the port back. */
7510 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
7511 if (qlport_down_retry)
7512 ha->port_down_retry_count = qlport_down_retry;
7513
7514 /* Set login_retry_count */
7515 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
7516 if (ha->port_down_retry_count ==
7517 le16_to_cpu(nv->port_down_retry_count) &&
7518 ha->port_down_retry_count > 3)
7519 ha->login_retry_count = ha->port_down_retry_count;
7520 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
7521 ha->login_retry_count = ha->port_down_retry_count;
7522 if (ql2xloginretrycount)
7523 ha->login_retry_count = ql2xloginretrycount;
7524
6246b8a1 7525 /* if not running MSI-X we need handshaking on interrupts */
f73cb695 7526 if (!vha->hw->flags.msix_enabled && (IS_QLA83XX(ha) || IS_QLA27XX(ha)))
ad950360 7527 icb->firmware_options_2 |= cpu_to_le32(BIT_22);
6246b8a1 7528
3a03eb79
AV		 7529 /* Enable ZIO. */
7530 if (!vha->flags.init_done) {
7531 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
7532 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
7533 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
7534 le16_to_cpu(icb->interrupt_delay_timer): 2;
7535 }
ad950360 7536 icb->firmware_options_2 &= cpu_to_le32(
3a03eb79
AV		 7537 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
7538 vha->flags.process_response_queue = 0;
7539 if (ha->zio_mode != QLA_ZIO_DISABLED) {
7540 ha->zio_mode = QLA_ZIO_MODE_6;
7541
7c3df132 7542 ql_log(ql_log_info, vha, 0x0075,
3a03eb79 7543 "ZIO mode %d enabled; timer delay (%d us).\n",
7c3df132
SK		 7544 ha->zio_mode,
7545 ha->zio_timer * 100);
3a03eb79
AV		 7546
7547 icb->firmware_options_2 |= cpu_to_le32(
7548 (uint32_t)ha->zio_mode);
7549 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
7550 vha->flags.process_response_queue = 1;
7551 }
7552
41dc529a
QT		 7553 /* enable RIDA Format2 */
7554 if (qla_tgt_mode_enabled(vha) || qla_dual_mode_enabled(vha))
7555 icb->firmware_options_3 |= BIT_0;
7556
3a03eb79 7557 if (rval) {
7c3df132
SK		 7558 ql_log(ql_log_warn, vha, 0x0076,
7559 "NVRAM configuration failed.\n");
3a03eb79
AV		 7560 }
7561 return (rval);
7562}
7563
a9083016
GM		 7564int
7565qla82xx_restart_isp(scsi_qla_host_t *vha)
7566{
7567 int status, rval;
a9083016
GM		 7568 struct qla_hw_data *ha = vha->hw;
7569 struct req_que *req = ha->req_q_map[0];
7570 struct rsp_que *rsp = ha->rsp_q_map[0];
7571 struct scsi_qla_host *vp;
feafb7b1 7572 unsigned long flags;
a9083016
GM		 7573
7574 status = qla2x00_init_rings(vha);
7575 if (!status) {
7576 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
7577 ha->flags.chip_reset_done = 1;
7578
7579 status = qla2x00_fw_ready(vha);
7580 if (!status) {
a9083016
GM		 7581 /* Issue a marker after FW becomes ready. */
7582 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
a9083016 7583 vha->flags.online = 1;
7108b76e 7584 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
a9083016
GM		 7585 }
7586
7587 /* if no cable then assume it's good */
7588 if ((vha->device_flags & DFLG_NO_CABLE))
7589 status = 0;
a9083016
GM		 7590 }
7591
7592 if (!status) {
7593 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
7594
7595 if (!atomic_read(&vha->loop_down_timer)) {
7596 /*
7597 * Issue marker command only when we are going
7598 * to start the I/O .
7599 */
7600 vha->marker_needed = 1;
7601 }
7602
a9083016
GM		 7603 ha->isp_ops->enable_intrs(ha);
7604
7605 ha->isp_abort_cnt = 0;
7606 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
7607
53296788 7608 /* Update the firmware version */
3173167f 7609 status = qla82xx_check_md_needed(vha);
53296788 7610
a9083016
GM		 7611 if (ha->fce) {
7612 ha->flags.fce_enabled = 1;
7613 memset(ha->fce, 0,
7614 fce_calc_size(ha->fce_bufs));
7615 rval = qla2x00_enable_fce_trace(vha,
7616 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
7617 &ha->fce_bufs);
7618 if (rval) {
cfb0919c 7619 ql_log(ql_log_warn, vha, 0x8001,
7c3df132
SK		 7620 "Unable to reinitialize FCE (%d).\n",
7621 rval);
a9083016
GM		 7622 ha->flags.fce_enabled = 0;
7623 }
7624 }
7625
7626 if (ha->eft) {
7627 memset(ha->eft, 0, EFT_SIZE);
7628 rval = qla2x00_enable_eft_trace(vha,
7629 ha->eft_dma, EFT_NUM_BUFFERS);
7630 if (rval) {
cfb0919c 7631 ql_log(ql_log_warn, vha, 0x8010,
7c3df132
SK		 7632 "Unable to reinitialize EFT (%d).\n",
7633 rval);
a9083016
GM		 7634 }
7635 }
a9083016
GM		 7636 }
7637
7638 if (!status) {
cfb0919c 7639 ql_dbg(ql_dbg_taskm, vha, 0x8011,
7c3df132 7640 "qla82xx_restart_isp succeeded.\n");
feafb7b1
AE		 7641
7642 spin_lock_irqsave(&ha->vport_slock, flags);
7643 list_for_each_entry(vp, &ha->vp_list, list) {
7644 if (vp->vp_idx) {
7645 atomic_inc(&vp->vref_count);
7646 spin_unlock_irqrestore(&ha->vport_slock, flags);
7647
a9083016 7648 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 7649
7650 spin_lock_irqsave(&ha->vport_slock, flags);
7651 atomic_dec(&vp->vref_count);
7652 }
a9083016 7653 }
feafb7b1
AE		 7654 spin_unlock_irqrestore(&ha->vport_slock, flags);
7655
a9083016 7656 } else {
cfb0919c 7657 ql_log(ql_log_warn, vha, 0x8016,
7c3df132 7658 "qla82xx_restart_isp **** FAILED ****.\n");
a9083016
GM		 7659 }
7660
7661 return status;
7662}
7663
3a03eb79 7664void
ae97c91e 7665qla81xx_update_fw_options(scsi_qla_host_t *vha)
3a03eb79 7666{
ae97c91e
AV		 7667 struct qla_hw_data *ha = vha->hw;
7668
f198cafa
HM		 7669 /* Hold status IOCBs until ABTS response received. */
7670 if (ql2xfwholdabts)
7671 ha->fw_options[3] |= BIT_12;
7672
088d09d4
GM		 7673 /* Set Retry FLOGI in case of P2P connection */
7674 if (ha->operating_mode == P2P) {
7675 ha->fw_options[2] |= BIT_3;
7676 ql_dbg(ql_dbg_disc, vha, 0x2103,
7677 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
7678 __func__, ha->fw_options[2]);
7679 }
7680
41dc529a
QT		 7681 /* Move PUREX, ABTS RX & RIDA to ATIOQ */
7682 if (ql2xmvasynctoatio) {
7683 if (qla_tgt_mode_enabled(vha) ||
7684 qla_dual_mode_enabled(vha))
7685 ha->fw_options[2] |= BIT_11;
7686 else
7687 ha->fw_options[2] &= ~BIT_11;
7688 }
7689
f7e761f5 7690 if (qla_tgt_mode_enabled(vha) ||
2da52737
QT		 7691 qla_dual_mode_enabled(vha)) {
7692 /* FW auto send SCSI status during */
7693 ha->fw_options[1] |= BIT_8;
7694 ha->fw_options[10] |= (u16)SAM_STAT_BUSY << 8;
7695
7696 /* FW perform Exchange validation */
f7e761f5 7697 ha->fw_options[2] |= BIT_4;
2da52737
QT		 7698 } else {
7699 ha->fw_options[1] &= ~BIT_8;
7700 ha->fw_options[10] &= 0x00ff;
7701
f7e761f5 7702 ha->fw_options[2] &= ~BIT_4;
2da52737 7703 }
f7e761f5 7704
41dc529a
QT		 7705 if (ql2xetsenable) {
7706 /* Enable ETS Burst. */
7707 memset(ha->fw_options, 0, sizeof(ha->fw_options));
7708 ha->fw_options[2] |= BIT_9;
7709 }
7710
83548fe2
QT		 7711 ql_dbg(ql_dbg_init, vha, 0x00e9,
7712 "%s, add FW options 1-3 = 0x%04x 0x%04x 0x%04x mode %x\n",
7713 __func__, ha->fw_options[1], ha->fw_options[2],
7714 ha->fw_options[3], vha->host->active_mode);
ae97c91e 7715
ae97c91e 7716 qla2x00_set_fw_options(vha, ha->fw_options);
3a03eb79 7717}
09ff701a
SR		 7718
7719/*
7720 * qla24xx_get_fcp_prio
7721 * Gets the fcp cmd priority value for the logged in port.
7722 * Looks for a match of the port descriptors within
7723 * each of the fcp prio config entries. If a match is found,
7724 * the tag (priority) value is returned.
7725 *
7726 * Input:
21090cbe 7727 * vha = scsi host structure pointer.
09ff701a
SR		 7728 * fcport = port structure pointer.
7729 *
7730 * Return:
6c452a45 7731 * non-zero (if found)
f28a0a96 7732 * -1 (if not found)
09ff701a
SR		 7733 *
7734 * Context:
7735 * Kernel context
7736 */
f28a0a96 7737static int
09ff701a
SR		 7738qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
7739{
7740 int i, entries;
7741 uint8_t pid_match, wwn_match;
f28a0a96 7742 int priority;
09ff701a
SR		 7743 uint32_t pid1, pid2;
7744 uint64_t wwn1, wwn2;
7745 struct qla_fcp_prio_entry *pri_entry;
7746 struct qla_hw_data *ha = vha->hw;
7747
7748 if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled)
f28a0a96 7749 return -1;
09ff701a 7750
f28a0a96 7751 priority = -1;
09ff701a
SR		 7752 entries = ha->fcp_prio_cfg->num_entries;
7753 pri_entry = &ha->fcp_prio_cfg->entry[0];
7754
7755 for (i = 0; i < entries; i++) {
7756 pid_match = wwn_match = 0;
7757
7758 if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) {
7759 pri_entry++;
7760 continue;
7761 }
7762
7763 /* check source pid for a match */
7764 if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) {
7765 pid1 = pri_entry->src_pid & INVALID_PORT_ID;
7766 pid2 = vha->d_id.b24 & INVALID_PORT_ID;
7767 if (pid1 == INVALID_PORT_ID)
7768 pid_match++;
7769 else if (pid1 == pid2)
7770 pid_match++;
7771 }
7772
7773 /* check destination pid for a match */
7774 if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) {
7775 pid1 = pri_entry->dst_pid & INVALID_PORT_ID;
7776 pid2 = fcport->d_id.b24 & INVALID_PORT_ID;
7777 if (pid1 == INVALID_PORT_ID)
7778 pid_match++;
7779 else if (pid1 == pid2)
7780 pid_match++;
7781 }
7782
7783 /* check source WWN for a match */
7784 if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) {
7785 wwn1 = wwn_to_u64(vha->port_name);
7786 wwn2 = wwn_to_u64(pri_entry->src_wwpn);
7787 if (wwn2 == (uint64_t)-1)
7788 wwn_match++;
7789 else if (wwn1 == wwn2)
7790 wwn_match++;
7791 }
7792
7793 /* check destination WWN for a match */
7794 if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) {
7795 wwn1 = wwn_to_u64(fcport->port_name);
7796 wwn2 = wwn_to_u64(pri_entry->dst_wwpn);
7797 if (wwn2 == (uint64_t)-1)
7798 wwn_match++;
7799 else if (wwn1 == wwn2)
7800 wwn_match++;
7801 }
7802
7803 if (pid_match == 2 || wwn_match == 2) {
7804 /* Found a matching entry */
7805 if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID)
7806 priority = pri_entry->tag;
7807 break;
7808 }
7809
7810 pri_entry++;
7811 }
7812
7813 return priority;
7814}
7815
7816/*
7817 * qla24xx_update_fcport_fcp_prio
7818 * Activates fcp priority for the logged in fc port
7819 *
7820 * Input:
21090cbe 7821 * vha = scsi host structure pointer.
09ff701a
SR		 7822 * fcp = port structure pointer.
7823 *
7824 * Return:
7825 * QLA_SUCCESS or QLA_FUNCTION_FAILED
7826 *
7827 * Context:
7828 * Kernel context.
7829 */
7830int
21090cbe 7831qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
09ff701a
SR		 7832{
7833 int ret;
f28a0a96 7834 int priority;
09ff701a
SR		 7835 uint16_t mb[5];
7836
21090cbe
MI		 7837 if (fcport->port_type != FCT_TARGET ||
7838 fcport->loop_id == FC_NO_LOOP_ID)
09ff701a
SR		 7839 return QLA_FUNCTION_FAILED;
7840
21090cbe 7841 priority = qla24xx_get_fcp_prio(vha, fcport);
f28a0a96
AV		 7842 if (priority < 0)
7843 return QLA_FUNCTION_FAILED;
7844
7ec0effd 7845 if (IS_P3P_TYPE(vha->hw)) {
a00f6296
SK		 7846 fcport->fcp_prio = priority & 0xf;
7847 return QLA_SUCCESS;
7848 }
7849
21090cbe 7850 ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb);
cfb0919c
CD		 7851 if (ret == QLA_SUCCESS) {
7852 if (fcport->fcp_prio != priority)
7853 ql_dbg(ql_dbg_user, vha, 0x709e,
7854 "Updated FCP_CMND priority - value=%d loop_id=%d "
7855 "port_id=%02x%02x%02x.\n", priority,
7856 fcport->loop_id, fcport->d_id.b.domain,
7857 fcport->d_id.b.area, fcport->d_id.b.al_pa);
a00f6296 7858 fcport->fcp_prio = priority & 0xf;
cfb0919c 7859 } else
7c3df132 7860 ql_dbg(ql_dbg_user, vha, 0x704f,
cfb0919c
CD		 7861 "Unable to update FCP_CMND priority - ret=0x%x for "
7862 "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id,
7863 fcport->d_id.b.domain, fcport->d_id.b.area,
7864 fcport->d_id.b.al_pa);
09ff701a
SR		 7865 return ret;
7866}
7867
7868/*
7869 * qla24xx_update_all_fcp_prio
7870 * Activates fcp priority for all the logged in ports
7871 *
7872 * Input:
7873 * ha = adapter block pointer.
7874 *
7875 * Return:
7876 * QLA_SUCCESS or QLA_FUNCTION_FAILED
7877 *
7878 * Context:
7879 * Kernel context.
7880 */
7881int
7882qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha)
7883{
7884 int ret;
7885 fc_port_t *fcport;
7886
7887 ret = QLA_FUNCTION_FAILED;
7888 /* We need to set priority for all logged in ports */
7889 list_for_each_entry(fcport, &vha->vp_fcports, list)
7890 ret = qla24xx_update_fcport_fcp_prio(vha, fcport);
7891
7892 return ret;
7893}
d7459527 7894
82de802a
QT		 7895struct qla_qpair *qla2xxx_create_qpair(struct scsi_qla_host *vha, int qos,
7896 int vp_idx, bool startqp)
d7459527
MH		 7897{
7898 int rsp_id = 0;
7899 int req_id = 0;
7900 int i;
7901 struct qla_hw_data *ha = vha->hw;
7902 uint16_t qpair_id = 0;
7903 struct qla_qpair *qpair = NULL;
7904 struct qla_msix_entry *msix;
7905
7906 if (!(ha->fw_attributes & BIT_6) || !ha->flags.msix_enabled) {
7907 ql_log(ql_log_warn, vha, 0x00181,
7908 "FW/Driver is not multi-queue capable.\n");
7909 return NULL;
7910 }
7911
7912 if (ql2xmqsupport) {
7913 qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
7914 if (qpair == NULL) {
7915 ql_log(ql_log_warn, vha, 0x0182,
7916 "Failed to allocate memory for queue pair.\n");
7917 return NULL;
7918 }
7919 memset(qpair, 0, sizeof(struct qla_qpair));
7920
7921 qpair->hw = vha->hw;
25ff6af1 7922 qpair->vha = vha;
82de802a
QT		 7923 qpair->qp_lock_ptr = &qpair->qp_lock;
7924 spin_lock_init(&qpair->qp_lock);
af7bb382 7925 qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
d7459527
MH		 7926
7927 /* Assign available que pair id */
7928 mutex_lock(&ha->mq_lock);
7929 qpair_id = find_first_zero_bit(ha->qpair_qid_map, ha->max_qpairs);
b95b9452 7930 if (ha->num_qpairs >= ha->max_qpairs) {
d7459527
MH		 7931 mutex_unlock(&ha->mq_lock);
7932 ql_log(ql_log_warn, vha, 0x0183,
7933 "No resources to create additional q pair.\n");
7934 goto fail_qid_map;
7935 }
b95b9452 7936 ha->num_qpairs++;
d7459527
MH		 7937 set_bit(qpair_id, ha->qpair_qid_map);
7938 ha->queue_pair_map[qpair_id] = qpair;
7939 qpair->id = qpair_id;
7940 qpair->vp_idx = vp_idx;
e6373f33 7941 qpair->fw_started = ha->flags.fw_started;
e326d22a 7942 INIT_LIST_HEAD(&qpair->hints_list);
cf19c45d 7943 INIT_LIST_HEAD(&qpair->nvme_done_list);
7c3f8fd1
QT		 7944 qpair->chip_reset = ha->base_qpair->chip_reset;
7945 qpair->enable_class_2 = ha->base_qpair->enable_class_2;
7946 qpair->enable_explicit_conf =
7947 ha->base_qpair->enable_explicit_conf;
d7459527
MH		 7948
7949 for (i = 0; i < ha->msix_count; i++) {
093df737 7950 msix = &ha->msix_entries[i];
d7459527
MH		 7951 if (msix->in_use)
7952 continue;
7953 qpair->msix = msix;
83548fe2 7954 ql_dbg(ql_dbg_multiq, vha, 0xc00f,
d7459527
MH		 7955 "Vector %x selected for qpair\n", msix->vector);
7956 break;
7957 }
7958 if (!qpair->msix) {
7959 ql_log(ql_log_warn, vha, 0x0184,
7960 "Out of MSI-X vectors!.\n");
7961 goto fail_msix;
7962 }
7963
7964 qpair->msix->in_use = 1;
7965 list_add_tail(&qpair->qp_list_elem, &vha->qp_list);
8abfa9e2
QT		 7966 qpair->pdev = ha->pdev;
7967 if (IS_QLA27XX(ha) || IS_QLA83XX(ha))
7968 qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
d7459527
MH		 7969
7970 mutex_unlock(&ha->mq_lock);
7971
7972 /* Create response queue first */
82de802a 7973 rsp_id = qla25xx_create_rsp_que(ha, 0, 0, 0, qpair, startqp);
d7459527
MH		 7974 if (!rsp_id) {
7975 ql_log(ql_log_warn, vha, 0x0185,
7976 "Failed to create response queue.\n");
7977 goto fail_rsp;
7978 }
7979
7980 qpair->rsp = ha->rsp_q_map[rsp_id];
7981
7982 /* Create request queue */
82de802a
QT		 7983 req_id = qla25xx_create_req_que(ha, 0, vp_idx, 0, rsp_id, qos,
7984 startqp);
d7459527
MH		 7985 if (!req_id) {
7986 ql_log(ql_log_warn, vha, 0x0186,
7987 "Failed to create request queue.\n");
7988 goto fail_req;
7989 }
7990
7991 qpair->req = ha->req_q_map[req_id];
7992 qpair->rsp->req = qpair->req;
82de802a 7993 qpair->rsp->qpair = qpair;
e326d22a
QT		 7994 /* init qpair to this cpu. Will adjust at run time. */
7995 qla_cpu_update(qpair, smp_processor_id());
d7459527
MH		 7996
7997 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
7998 if (ha->fw_attributes & BIT_4)
7999 qpair->difdix_supported = 1;
8000 }
8001
8002 qpair->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
8003 if (!qpair->srb_mempool) {
83548fe2 8004 ql_log(ql_log_warn, vha, 0xd036,
d7459527
MH		 8005 "Failed to create srb mempool for qpair %d\n",
8006 qpair->id);
8007 goto fail_mempool;
8008 }
8009
8010 /* Mark as online */
8011 qpair->online = 1;
8012
8013 if (!vha->flags.qpairs_available)
8014 vha->flags.qpairs_available = 1;
8015
8016 ql_dbg(ql_dbg_multiq, vha, 0xc00d,
8017 "Request/Response queue pair created, id %d\n",
8018 qpair->id);
8019 ql_dbg(ql_dbg_init, vha, 0x0187,
8020 "Request/Response queue pair created, id %d\n",
8021 qpair->id);
8022 }
8023 return qpair;
8024
8025fail_mempool:
8026fail_req:
8027 qla25xx_delete_rsp_que(vha, qpair->rsp);
8028fail_rsp:
8029 mutex_lock(&ha->mq_lock);
8030 qpair->msix->in_use = 0;
8031 list_del(&qpair->qp_list_elem);
8032 if (list_empty(&vha->qp_list))
8033 vha->flags.qpairs_available = 0;
8034fail_msix:
8035 ha->queue_pair_map[qpair_id] = NULL;
8036 clear_bit(qpair_id, ha->qpair_qid_map);
b95b9452 8037 ha->num_qpairs--;
d7459527
MH		 8038 mutex_unlock(&ha->mq_lock);
8039fail_qid_map:
8040 kfree(qpair);
8041 return NULL;
8042}
8043
8044int qla2xxx_delete_qpair(struct scsi_qla_host *vha, struct qla_qpair *qpair)
8045{
d65237c7 8046 int ret = QLA_FUNCTION_FAILED;
d7459527
MH		 8047 struct qla_hw_data *ha = qpair->hw;
8048
d65237c7
SC		 8049 if (!vha->flags.qpairs_req_created && !vha->flags.qpairs_rsp_created)
8050 goto fail;
8051
d7459527
MH		 8052 qpair->delete_in_progress = 1;
8053 while (atomic_read(&qpair->ref_count))
8054 msleep(500);
8055
8056 ret = qla25xx_delete_req_que(vha, qpair->req);
8057 if (ret != QLA_SUCCESS)
8058 goto fail;
8059 ret = qla25xx_delete_rsp_que(vha, qpair->rsp);
8060 if (ret != QLA_SUCCESS)
8061 goto fail;
8062
8063 mutex_lock(&ha->mq_lock);
8064 ha->queue_pair_map[qpair->id] = NULL;
8065 clear_bit(qpair->id, ha->qpair_qid_map);
b95b9452 8066 ha->num_qpairs--;
d7459527 8067 list_del(&qpair->qp_list_elem);
d65237c7 8068 if (list_empty(&vha->qp_list)) {
d7459527 8069 vha->flags.qpairs_available = 0;
d65237c7
SC		 8070 vha->flags.qpairs_req_created = 0;
8071 vha->flags.qpairs_rsp_created = 0;
8072 }
d7459527
MH		 8073 mempool_destroy(qpair->srb_mempool);
8074 kfree(qpair);
8075 mutex_unlock(&ha->mq_lock);
8076
8077 return QLA_SUCCESS;
8078fail:
8079 return ret;
8080}
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