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qla2xxx: ISP27xx firmware dump template spec updates (including T274).
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / qla2xxx / qla_init.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
73208dfd 8#include "qla_gbl.h"
1da177e4
LT		 9
10#include <linux/delay.h>
5a0e3ad6 11#include <linux/slab.h>
0107109e 12#include <linux/vmalloc.h>
1da177e4
LT		 13
14#include "qla_devtbl.h"
15
4e08df3f
DM		 16#ifdef CONFIG_SPARC
17#include <asm/prom.h>
4e08df3f
DM		 18#endif
19
2d70c103
NB		 20#include <target/target_core_base.h>
21#include "qla_target.h"
22
1da177e4
LT		 23/*
24* QLogic ISP2x00 Hardware Support Function Prototypes.
25*/
1da177e4 26static int qla2x00_isp_firmware(scsi_qla_host_t *);
1da177e4 27static int qla2x00_setup_chip(scsi_qla_host_t *);
1da177e4
LT		 28static int qla2x00_fw_ready(scsi_qla_host_t *);
29static int qla2x00_configure_hba(scsi_qla_host_t *);
1da177e4
LT		 30static int qla2x00_configure_loop(scsi_qla_host_t *);
31static int qla2x00_configure_local_loop(scsi_qla_host_t *);
1da177e4
LT		 32static int qla2x00_configure_fabric(scsi_qla_host_t *);
33static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *, struct list_head *);
1da177e4
LT		 34static int qla2x00_fabric_dev_login(scsi_qla_host_t *, fc_port_t *,
35 uint16_t *);
1da177e4
LT		 36
37static int qla2x00_restart_isp(scsi_qla_host_t *);
1da177e4 38
4d4df193
HK		 39static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *);
40static int qla84xx_init_chip(scsi_qla_host_t *);
73208dfd 41static int qla25xx_init_queues(struct qla_hw_data *);
4d4df193 42
ac280b67
AV		 43/* SRB Extensions ---------------------------------------------------------- */
44
9ba56b95
GM		 45void
46qla2x00_sp_timeout(unsigned long __data)
ac280b67
AV		 47{
48 srb_t *sp = (srb_t *)__data;
4916392b 49 struct srb_iocb *iocb;
ac280b67
AV		 50 fc_port_t *fcport = sp->fcport;
51 struct qla_hw_data *ha = fcport->vha->hw;
52 struct req_que *req;
53 unsigned long flags;
54
55 spin_lock_irqsave(&ha->hardware_lock, flags);
56 req = ha->req_q_map[0];
57 req->outstanding_cmds[sp->handle] = NULL;
9ba56b95 58 iocb = &sp->u.iocb_cmd;
4916392b 59 iocb->timeout(sp);
9ba56b95 60 sp->free(fcport->vha, sp);
6ac52608 61 spin_unlock_irqrestore(&ha->hardware_lock, flags);
ac280b67
AV		 62}
63
9ba56b95
GM		 64void
65qla2x00_sp_free(void *data, void *ptr)
ac280b67 66{
9ba56b95
GM		 67 srb_t *sp = (srb_t *)ptr;
68 struct srb_iocb *iocb = &sp->u.iocb_cmd;
69 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
ac280b67 70
4d97cc53 71 del_timer(&iocb->timer);
b00ee7d7 72 qla2x00_rel_sp(vha, sp);
ac280b67
AV		 73}
74
ac280b67
AV		 75/* Asynchronous Login/Logout Routines -------------------------------------- */
76
a9b6f722 77unsigned long
5b91490e
AV		 78qla2x00_get_async_timeout(struct scsi_qla_host *vha)
79{
80 unsigned long tmo;
81 struct qla_hw_data *ha = vha->hw;
82
83 /* Firmware should use switch negotiated r_a_tov for timeout. */
84 tmo = ha->r_a_tov / 10 * 2;
8ae6d9c7
GM		 85 if (IS_QLAFX00(ha)) {
86 tmo = FX00_DEF_RATOV * 2;
87 } else if (!IS_FWI2_CAPABLE(ha)) {
5b91490e
AV		 88 /*
89 * Except for earlier ISPs where the timeout is seeded from the
90 * initialization control block.
91 */
92 tmo = ha->login_timeout;
93 }
94 return tmo;
95}
ac280b67
AV		 96
97static void
9ba56b95 98qla2x00_async_iocb_timeout(void *data)
ac280b67 99{
9ba56b95 100 srb_t *sp = (srb_t *)data;
ac280b67 101 fc_port_t *fcport = sp->fcport;
ac280b67 102
7c3df132 103 ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
cfb0919c 104 "Async-%s timeout - hdl=%x portid=%02x%02x%02x.\n",
9ba56b95 105 sp->name, sp->handle, fcport->d_id.b.domain, fcport->d_id.b.area,
7c3df132 106 fcport->d_id.b.al_pa);
ac280b67 107
5ff1d584 108 fcport->flags &= ~FCF_ASYNC_SENT;
9ba56b95
GM		 109 if (sp->type == SRB_LOGIN_CMD) {
110 struct srb_iocb *lio = &sp->u.iocb_cmd;
ac280b67 111 qla2x00_post_async_logout_work(fcport->vha, fcport, NULL);
6ac52608
AV		 112 /* Retry as needed. */
113 lio->u.logio.data[0] = MBS_COMMAND_ERROR;
114 lio->u.logio.data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
115 QLA_LOGIO_LOGIN_RETRIED : 0;
116 qla2x00_post_async_login_done_work(fcport->vha, fcport,
117 lio->u.logio.data);
118 }
ac280b67
AV		 119}
120
99b0bec7 121static void
9ba56b95 122qla2x00_async_login_sp_done(void *data, void *ptr, int res)
99b0bec7 123{
9ba56b95
GM		 124 srb_t *sp = (srb_t *)ptr;
125 struct srb_iocb *lio = &sp->u.iocb_cmd;
126 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
127
128 if (!test_bit(UNLOADING, &vha->dpc_flags))
129 qla2x00_post_async_login_done_work(sp->fcport->vha, sp->fcport,
130 lio->u.logio.data);
131 sp->free(sp->fcport->vha, sp);
99b0bec7
AV		 132}
133
ac280b67
AV		 134int
135qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport,
136 uint16_t *data)
137{
ac280b67 138 srb_t *sp;
4916392b 139 struct srb_iocb *lio;
ac280b67
AV		 140 int rval;
141
142 rval = QLA_FUNCTION_FAILED;
9ba56b95 143 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 144 if (!sp)
145 goto done;
146
9ba56b95
GM		 147 sp->type = SRB_LOGIN_CMD;
148 sp->name = "login";
149 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
150
151 lio = &sp->u.iocb_cmd;
3822263e 152 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 153 sp->done = qla2x00_async_login_sp_done;
4916392b 154 lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI;
ac280b67 155 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 156 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
ac280b67
AV		 157 rval = qla2x00_start_sp(sp);
158 if (rval != QLA_SUCCESS)
159 goto done_free_sp;
160
7c3df132 161 ql_dbg(ql_dbg_disc, vha, 0x2072,
cfb0919c
CD		 162 "Async-login - hdl=%x, loopid=%x portid=%02x%02x%02x "
163 "retries=%d.\n", sp->handle, fcport->loop_id,
164 fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
165 fcport->login_retry);
ac280b67
AV		 166 return rval;
167
168done_free_sp:
9ba56b95 169 sp->free(fcport->vha, sp);
ac280b67
AV		 170done:
171 return rval;
172}
173
99b0bec7 174static void
9ba56b95 175qla2x00_async_logout_sp_done(void *data, void *ptr, int res)
99b0bec7 176{
9ba56b95
GM		 177 srb_t *sp = (srb_t *)ptr;
178 struct srb_iocb *lio = &sp->u.iocb_cmd;
179 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
180
181 if (!test_bit(UNLOADING, &vha->dpc_flags))
182 qla2x00_post_async_logout_done_work(sp->fcport->vha, sp->fcport,
183 lio->u.logio.data);
184 sp->free(sp->fcport->vha, sp);
99b0bec7
AV		 185}
186
ac280b67
AV		 187int
188qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport)
189{
ac280b67 190 srb_t *sp;
4916392b 191 struct srb_iocb *lio;
ac280b67
AV		 192 int rval;
193
194 rval = QLA_FUNCTION_FAILED;
9ba56b95 195 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 196 if (!sp)
197 goto done;
198
9ba56b95
GM		 199 sp->type = SRB_LOGOUT_CMD;
200 sp->name = "logout";
201 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
202
203 lio = &sp->u.iocb_cmd;
3822263e 204 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 205 sp->done = qla2x00_async_logout_sp_done;
ac280b67
AV		 206 rval = qla2x00_start_sp(sp);
207 if (rval != QLA_SUCCESS)
208 goto done_free_sp;
209
7c3df132 210 ql_dbg(ql_dbg_disc, vha, 0x2070,
cfb0919c
CD		 211 "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
212 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
213 fcport->d_id.b.area, fcport->d_id.b.al_pa);
ac280b67
AV		 214 return rval;
215
216done_free_sp:
9ba56b95 217 sp->free(fcport->vha, sp);
ac280b67
AV		 218done:
219 return rval;
220}
221
5ff1d584 222static void
9ba56b95 223qla2x00_async_adisc_sp_done(void *data, void *ptr, int res)
5ff1d584 224{
9ba56b95
GM		 225 srb_t *sp = (srb_t *)ptr;
226 struct srb_iocb *lio = &sp->u.iocb_cmd;
227 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
228
229 if (!test_bit(UNLOADING, &vha->dpc_flags))
230 qla2x00_post_async_adisc_done_work(sp->fcport->vha, sp->fcport,
231 lio->u.logio.data);
232 sp->free(sp->fcport->vha, sp);
5ff1d584
AV		 233}
234
235int
236qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport,
237 uint16_t *data)
238{
5ff1d584 239 srb_t *sp;
4916392b 240 struct srb_iocb *lio;
5ff1d584
AV		 241 int rval;
242
243 rval = QLA_FUNCTION_FAILED;
9ba56b95 244 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
5ff1d584
AV		 245 if (!sp)
246 goto done;
247
9ba56b95
GM		 248 sp->type = SRB_ADISC_CMD;
249 sp->name = "adisc";
250 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
251
252 lio = &sp->u.iocb_cmd;
3822263e 253 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 254 sp->done = qla2x00_async_adisc_sp_done;
5ff1d584 255 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 256 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
5ff1d584
AV		 257 rval = qla2x00_start_sp(sp);
258 if (rval != QLA_SUCCESS)
259 goto done_free_sp;
260
7c3df132 261 ql_dbg(ql_dbg_disc, vha, 0x206f,
cfb0919c
CD		 262 "Async-adisc - hdl=%x loopid=%x portid=%02x%02x%02x.\n",
263 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
264 fcport->d_id.b.area, fcport->d_id.b.al_pa);
5ff1d584
AV		 265 return rval;
266
267done_free_sp:
9ba56b95 268 sp->free(fcport->vha, sp);
5ff1d584
AV		 269done:
270 return rval;
271}
272
3822263e 273static void
faef62d1 274qla2x00_tmf_iocb_timeout(void *data)
3822263e 275{
faef62d1
AB		 276 srb_t *sp = (srb_t *)data;
277 struct srb_iocb *tmf = &sp->u.iocb_cmd;
3822263e 278
faef62d1
AB		 279 tmf->u.tmf.comp_status = CS_TIMEOUT;
280 complete(&tmf->u.tmf.comp);
281}
9ba56b95 282
faef62d1
AB		 283static void
284qla2x00_tmf_sp_done(void *data, void *ptr, int res)
285{
286 srb_t *sp = (srb_t *)ptr;
287 struct srb_iocb *tmf = &sp->u.iocb_cmd;
288 complete(&tmf->u.tmf.comp);
3822263e
MI		 289}
290
291int
faef62d1 292qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t flags, uint32_t lun,
3822263e
MI		 293 uint32_t tag)
294{
295 struct scsi_qla_host *vha = fcport->vha;
faef62d1 296 struct srb_iocb *tm_iocb;
3822263e 297 srb_t *sp;
faef62d1 298 int rval = QLA_FUNCTION_FAILED;
3822263e 299
9ba56b95 300 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
3822263e
MI		 301 if (!sp)
302 goto done;
303
faef62d1 304 tm_iocb = &sp->u.iocb_cmd;
9ba56b95
GM		 305 sp->type = SRB_TM_CMD;
306 sp->name = "tmf";
faef62d1
AB		 307 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
308 tm_iocb->u.tmf.flags = flags;
309 tm_iocb->u.tmf.lun = lun;
310 tm_iocb->u.tmf.data = tag;
311 sp->done = qla2x00_tmf_sp_done;
312 tm_iocb->timeout = qla2x00_tmf_iocb_timeout;
313 init_completion(&tm_iocb->u.tmf.comp);
3822263e
MI		 314
315 rval = qla2x00_start_sp(sp);
316 if (rval != QLA_SUCCESS)
317 goto done_free_sp;
318
7c3df132 319 ql_dbg(ql_dbg_taskm, vha, 0x802f,
cfb0919c
CD		 320 "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
321 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
322 fcport->d_id.b.area, fcport->d_id.b.al_pa);
faef62d1
AB		 323
324 wait_for_completion(&tm_iocb->u.tmf.comp);
325
326 rval = tm_iocb->u.tmf.comp_status == CS_COMPLETE ?
327 QLA_SUCCESS : QLA_FUNCTION_FAILED;
328
329 if ((rval != QLA_SUCCESS) || tm_iocb->u.tmf.data) {
330 ql_dbg(ql_dbg_taskm, vha, 0x8030,
331 "TM IOCB failed (%x).\n", rval);
332 }
333
334 if (!test_bit(UNLOADING, &vha->dpc_flags) && !IS_QLAFX00(vha->hw)) {
335 flags = tm_iocb->u.tmf.flags;
336 lun = (uint16_t)tm_iocb->u.tmf.lun;
337
338 /* Issue Marker IOCB */
339 qla2x00_marker(vha, vha->hw->req_q_map[0],
340 vha->hw->rsp_q_map[0], sp->fcport->loop_id, lun,
341 flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
342 }
3822263e
MI		 343
344done_free_sp:
faef62d1 345 sp->free(vha, sp);
3822263e
MI		 346done:
347 return rval;
348}
349
4440e46d
AB		 350static void
351qla24xx_abort_iocb_timeout(void *data)
352{
353 srb_t *sp = (srb_t *)data;
354 struct srb_iocb *abt = &sp->u.iocb_cmd;
355
356 abt->u.abt.comp_status = CS_TIMEOUT;
357 complete(&abt->u.abt.comp);
358}
359
360static void
361qla24xx_abort_sp_done(void *data, void *ptr, int res)
362{
363 srb_t *sp = (srb_t *)ptr;
364 struct srb_iocb *abt = &sp->u.iocb_cmd;
365
366 complete(&abt->u.abt.comp);
367}
368
369static int
370qla24xx_async_abort_cmd(srb_t *cmd_sp)
371{
372 scsi_qla_host_t *vha = cmd_sp->fcport->vha;
373 fc_port_t *fcport = cmd_sp->fcport;
374 struct srb_iocb *abt_iocb;
375 srb_t *sp;
376 int rval = QLA_FUNCTION_FAILED;
377
378 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
379 if (!sp)
380 goto done;
381
382 abt_iocb = &sp->u.iocb_cmd;
383 sp->type = SRB_ABT_CMD;
384 sp->name = "abort";
385 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
386 abt_iocb->u.abt.cmd_hndl = cmd_sp->handle;
387 sp->done = qla24xx_abort_sp_done;
388 abt_iocb->timeout = qla24xx_abort_iocb_timeout;
389 init_completion(&abt_iocb->u.abt.comp);
390
391 rval = qla2x00_start_sp(sp);
392 if (rval != QLA_SUCCESS)
393 goto done_free_sp;
394
395 ql_dbg(ql_dbg_async, vha, 0x507c,
396 "Abort command issued - hdl=%x, target_id=%x\n",
397 cmd_sp->handle, fcport->tgt_id);
398
399 wait_for_completion(&abt_iocb->u.abt.comp);
400
401 rval = abt_iocb->u.abt.comp_status == CS_COMPLETE ?
402 QLA_SUCCESS : QLA_FUNCTION_FAILED;
403
404done_free_sp:
405 sp->free(vha, sp);
406done:
407 return rval;
408}
409
410int
411qla24xx_async_abort_command(srb_t *sp)
412{
413 unsigned long flags = 0;
414
415 uint32_t handle;
416 fc_port_t *fcport = sp->fcport;
417 struct scsi_qla_host *vha = fcport->vha;
418 struct qla_hw_data *ha = vha->hw;
419 struct req_que *req = vha->req;
420
421 spin_lock_irqsave(&ha->hardware_lock, flags);
422 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
423 if (req->outstanding_cmds[handle] == sp)
424 break;
425 }
426 spin_unlock_irqrestore(&ha->hardware_lock, flags);
427 if (handle == req->num_outstanding_cmds) {
428 /* Command not found. */
429 return QLA_FUNCTION_FAILED;
430 }
431 if (sp->type == SRB_FXIOCB_DCMD)
432 return qlafx00_fx_disc(vha, &vha->hw->mr.fcport,
433 FXDISC_ABORT_IOCTL);
434
435 return qla24xx_async_abort_cmd(sp);
436}
437
4916392b 438void
ac280b67
AV		 439qla2x00_async_login_done(struct scsi_qla_host *vha, fc_port_t *fcport,
440 uint16_t *data)
441{
442 int rval;
ac280b67
AV		 443
444 switch (data[0]) {
445 case MBS_COMMAND_COMPLETE:
a4f92a32
AV		 446 /*
447 * Driver must validate login state - If PRLI not complete,
448 * force a relogin attempt via implicit LOGO, PLOGI, and PRLI
449 * requests.
450 */
451 rval = qla2x00_get_port_database(vha, fcport, 0);
0eba25df
AE		 452 if (rval == QLA_NOT_LOGGED_IN) {
453 fcport->flags &= ~FCF_ASYNC_SENT;
454 fcport->flags |= FCF_LOGIN_NEEDED;
455 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
456 break;
457 }
458
a4f92a32
AV		 459 if (rval != QLA_SUCCESS) {
460 qla2x00_post_async_logout_work(vha, fcport, NULL);
461 qla2x00_post_async_login_work(vha, fcport, NULL);
462 break;
463 }
99b0bec7 464 if (fcport->flags & FCF_FCP2_DEVICE) {
5ff1d584
AV		 465 qla2x00_post_async_adisc_work(vha, fcport, data);
466 break;
99b0bec7
AV		 467 }
468 qla2x00_update_fcport(vha, fcport);
ac280b67
AV		 469 break;
470 case MBS_COMMAND_ERROR:
5ff1d584 471 fcport->flags &= ~FCF_ASYNC_SENT;
ac280b67
AV		 472 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
473 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
474 else
80d79440 475 qla2x00_mark_device_lost(vha, fcport, 1, 0);
ac280b67
AV		 476 break;
477 case MBS_PORT_ID_USED:
478 fcport->loop_id = data[1];
6ac52608 479 qla2x00_post_async_logout_work(vha, fcport, NULL);
ac280b67
AV		 480 qla2x00_post_async_login_work(vha, fcport, NULL);
481 break;
482 case MBS_LOOP_ID_USED:
483 fcport->loop_id++;
484 rval = qla2x00_find_new_loop_id(vha, fcport);
485 if (rval != QLA_SUCCESS) {
5ff1d584 486 fcport->flags &= ~FCF_ASYNC_SENT;
80d79440 487 qla2x00_mark_device_lost(vha, fcport, 1, 0);
ac280b67
AV		 488 break;
489 }
490 qla2x00_post_async_login_work(vha, fcport, NULL);
491 break;
492 }
4916392b 493 return;
ac280b67
AV		 494}
495
4916392b 496void
ac280b67
AV		 497qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport,
498 uint16_t *data)
499{
500 qla2x00_mark_device_lost(vha, fcport, 1, 0);
4916392b 501 return;
ac280b67
AV		 502}
503
4916392b 504void
5ff1d584
AV		 505qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport,
506 uint16_t *data)
507{
508 if (data[0] == MBS_COMMAND_COMPLETE) {
509 qla2x00_update_fcport(vha, fcport);
510
4916392b 511 return;
5ff1d584
AV		 512 }
513
514 /* Retry login. */
515 fcport->flags &= ~FCF_ASYNC_SENT;
516 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
517 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
518 else
80d79440 519 qla2x00_mark_device_lost(vha, fcport, 1, 0);
5ff1d584 520
4916392b 521 return;
5ff1d584
AV		 522}
523
1da177e4
LT		 524/****************************************************************************/
525/* QLogic ISP2x00 Hardware Support Functions. */
526/****************************************************************************/
527
fa492630 528static int
7d613ac6
SV		 529qla83xx_nic_core_fw_load(scsi_qla_host_t *vha)
530{
531 int rval = QLA_SUCCESS;
532 struct qla_hw_data *ha = vha->hw;
533 uint32_t idc_major_ver, idc_minor_ver;
711aa7f7 534 uint16_t config[4];
7d613ac6
SV		 535
536 qla83xx_idc_lock(vha, 0);
537
538 /* SV: TODO: Assign initialization timeout from
539 * flash-info / other param
540 */
541 ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT;
542 ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT;
543
544 /* Set our fcoe function presence */
545 if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) {
546 ql_dbg(ql_dbg_p3p, vha, 0xb077,
547 "Error while setting DRV-Presence.\n");
548 rval = QLA_FUNCTION_FAILED;
549 goto exit;
550 }
551
552 /* Decide the reset ownership */
553 qla83xx_reset_ownership(vha);
554
555 /*
556 * On first protocol driver load:
557 * Init-Owner: Set IDC-Major-Version and Clear IDC-Lock-Recovery
558 * register.
559 * Others: Check compatibility with current IDC Major version.
560 */
561 qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver);
562 if (ha->flags.nic_core_reset_owner) {
563 /* Set IDC Major version */
564 idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION;
565 qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver);
566
567 /* Clearing IDC-Lock-Recovery register */
568 qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0);
569 } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) {
570 /*
571 * Clear further IDC participation if we are not compatible with
572 * the current IDC Major Version.
573 */
574 ql_log(ql_log_warn, vha, 0xb07d,
575 "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n",
576 idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION);
577 __qla83xx_clear_drv_presence(vha);
578 rval = QLA_FUNCTION_FAILED;
579 goto exit;
580 }
581 /* Each function sets its supported Minor version. */
582 qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver);
583 idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2));
584 qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver);
585
711aa7f7
SK		 586 if (ha->flags.nic_core_reset_owner) {
587 memset(config, 0, sizeof(config));
588 if (!qla81xx_get_port_config(vha, config))
589 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
590 QLA8XXX_DEV_READY);
591 }
592
7d613ac6
SV		 593 rval = qla83xx_idc_state_handler(vha);
594
595exit:
596 qla83xx_idc_unlock(vha, 0);
597
598 return rval;
599}
600
1da177e4
LT		 601/*
602* qla2x00_initialize_adapter
603* Initialize board.
604*
605* Input:
606* ha = adapter block pointer.
607*
608* Returns:
609* 0 = success
610*/
611int
e315cd28 612qla2x00_initialize_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 613{
614 int rval;
e315cd28 615 struct qla_hw_data *ha = vha->hw;
73208dfd 616 struct req_que *req = ha->req_q_map[0];
2533cf67 617
1da177e4 618 /* Clear adapter flags. */
e315cd28 619 vha->flags.online = 0;
2533cf67 620 ha->flags.chip_reset_done = 0;
e315cd28 621 vha->flags.reset_active = 0;
85880801
AV		 622 ha->flags.pci_channel_io_perm_failure = 0;
623 ha->flags.eeh_busy = 0;
fabbb8df 624 vha->qla_stats.jiffies_at_last_reset = get_jiffies_64();
e315cd28
AC		 625 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
626 atomic_set(&vha->loop_state, LOOP_DOWN);
627 vha->device_flags = DFLG_NO_CABLE;
628 vha->dpc_flags = 0;
629 vha->flags.management_server_logged_in = 0;
630 vha->marker_needed = 0;
1da177e4
LT		 631 ha->isp_abort_cnt = 0;
632 ha->beacon_blink_led = 0;
633
73208dfd
AC		 634 set_bit(0, ha->req_qid_map);
635 set_bit(0, ha->rsp_qid_map);
636
cfb0919c 637 ql_dbg(ql_dbg_init, vha, 0x0040,
7c3df132 638 "Configuring PCI space...\n");
e315cd28 639 rval = ha->isp_ops->pci_config(vha);
1da177e4 640 if (rval) {
7c3df132
SK		 641 ql_log(ql_log_warn, vha, 0x0044,
642 "Unable to configure PCI space.\n");
1da177e4
LT		 643 return (rval);
644 }
645
e315cd28 646 ha->isp_ops->reset_chip(vha);
1da177e4 647
e315cd28 648 rval = qla2xxx_get_flash_info(vha);
c00d8994 649 if (rval) {
7c3df132
SK		 650 ql_log(ql_log_fatal, vha, 0x004f,
651 "Unable to validate FLASH data.\n");
7ec0effd
AD		 652 return rval;
653 }
654
655 if (IS_QLA8044(ha)) {
656 qla8044_read_reset_template(vha);
657
658 /* NOTE: If ql2xdontresethba==1, set IDC_CTRL DONTRESET_BIT0.
659 * If DONRESET_BIT0 is set, drivers should not set dev_state
660 * to NEED_RESET. But if NEED_RESET is set, drivers should
661 * should honor the reset. */
662 if (ql2xdontresethba == 1)
663 qla8044_set_idc_dontreset(vha);
c00d8994
AV		 664 }
665
73208dfd 666 ha->isp_ops->get_flash_version(vha, req->ring);
cfb0919c 667 ql_dbg(ql_dbg_init, vha, 0x0061,
7c3df132 668 "Configure NVRAM parameters...\n");
0107109e 669
e315cd28 670 ha->isp_ops->nvram_config(vha);
1da177e4 671
d4c760c2
AV		 672 if (ha->flags.disable_serdes) {
673 /* Mask HBA via NVRAM settings? */
7c3df132 674 ql_log(ql_log_info, vha, 0x0077,
7b833558 675 "Masking HBA WWPN %8phN (via NVRAM).\n", vha->port_name);
d4c760c2
AV		 676 return QLA_FUNCTION_FAILED;
677 }
678
cfb0919c 679 ql_dbg(ql_dbg_init, vha, 0x0078,
7c3df132 680 "Verifying loaded RISC code...\n");
1da177e4 681
e315cd28
AC		 682 if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) {
683 rval = ha->isp_ops->chip_diag(vha);
d19044c3
AV		 684 if (rval)
685 return (rval);
e315cd28 686 rval = qla2x00_setup_chip(vha);
d19044c3
AV		 687 if (rval)
688 return (rval);
1da177e4 689 }
a9083016 690
4d4df193 691 if (IS_QLA84XX(ha)) {
e315cd28 692 ha->cs84xx = qla84xx_get_chip(vha);
4d4df193 693 if (!ha->cs84xx) {
7c3df132 694 ql_log(ql_log_warn, vha, 0x00d0,
4d4df193
HK		 695 "Unable to configure ISP84XX.\n");
696 return QLA_FUNCTION_FAILED;
697 }
698 }
2d70c103
NB		 699
700 if (qla_ini_mode_enabled(vha))
701 rval = qla2x00_init_rings(vha);
702
2533cf67 703 ha->flags.chip_reset_done = 1;
1da177e4 704
9a069e19 705 if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) {
6c452a45 706 /* Issue verify 84xx FW IOCB to complete 84xx initialization */
9a069e19
GM		 707 rval = qla84xx_init_chip(vha);
708 if (rval != QLA_SUCCESS) {
7c3df132
SK		 709 ql_log(ql_log_warn, vha, 0x00d4,
710 "Unable to initialize ISP84XX.\n");
9a069e19
GM		 711 qla84xx_put_chip(vha);
712 }
713 }
714
7d613ac6
SV		 715 /* Load the NIC Core f/w if we are the first protocol driver. */
716 if (IS_QLA8031(ha)) {
717 rval = qla83xx_nic_core_fw_load(vha);
718 if (rval)
719 ql_log(ql_log_warn, vha, 0x0124,
720 "Error in initializing NIC Core f/w.\n");
721 }
722
2f0f3f4f
MI		 723 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
724 qla24xx_read_fcp_prio_cfg(vha);
09ff701a 725
c46e65c7
JC		 726 if (IS_P3P_TYPE(ha))
727 qla82xx_set_driver_version(vha, QLA2XXX_VERSION);
728 else
729 qla25xx_set_driver_version(vha, QLA2XXX_VERSION);
730
1da177e4
LT		 731 return (rval);
732}
733
734/**
abbd8870 735 * qla2100_pci_config() - Setup ISP21xx PCI configuration registers.
1da177e4
LT		 736 * @ha: HA context
737 *
738 * Returns 0 on success.
739 */
abbd8870 740int
e315cd28 741qla2100_pci_config(scsi_qla_host_t *vha)
1da177e4 742{
a157b101 743 uint16_t w;
abbd8870 744 unsigned long flags;
e315cd28 745 struct qla_hw_data *ha = vha->hw;
3d71644c 746 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 747
1da177e4 748 pci_set_master(ha->pdev);
af6177d8 749 pci_try_set_mwi(ha->pdev);
1da177e4 750
1da177e4 751 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 752 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
abbd8870
AV		 753 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
754
737faece 755 pci_disable_rom(ha->pdev);
1da177e4
LT		 756
757 /* Get PCI bus information. */
758 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 759 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
1da177e4
LT		 760 spin_unlock_irqrestore(&ha->hardware_lock, flags);
761
abbd8870
AV		 762 return QLA_SUCCESS;
763}
1da177e4 764
abbd8870
AV		 765/**
766 * qla2300_pci_config() - Setup ISP23xx PCI configuration registers.
767 * @ha: HA context
768 *
769 * Returns 0 on success.
770 */
771int
e315cd28 772qla2300_pci_config(scsi_qla_host_t *vha)
abbd8870 773{
a157b101 774 uint16_t w;
abbd8870
AV		 775 unsigned long flags = 0;
776 uint32_t cnt;
e315cd28 777 struct qla_hw_data *ha = vha->hw;
3d71644c 778 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 779
abbd8870 780 pci_set_master(ha->pdev);
af6177d8 781 pci_try_set_mwi(ha->pdev);
1da177e4 782
abbd8870 783 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 784 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
1da177e4 785
abbd8870
AV		 786 if (IS_QLA2322(ha) || IS_QLA6322(ha))
787 w &= ~PCI_COMMAND_INTX_DISABLE;
a157b101 788 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1da177e4 789
abbd8870
AV		 790 /*
791 * If this is a 2300 card and not 2312, reset the
792 * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately,
793 * the 2310 also reports itself as a 2300 so we need to get the
794 * fb revision level -- a 6 indicates it really is a 2300 and
795 * not a 2310.
796 */
797 if (IS_QLA2300(ha)) {
798 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 799
abbd8870 800 /* Pause RISC. */
3d71644c 801 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
abbd8870 802 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 803 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
abbd8870 804 break;
1da177e4 805
abbd8870
AV		 806 udelay(10);
807 }
1da177e4 808
abbd8870 809 /* Select FPM registers. */
3d71644c
AV		 810 WRT_REG_WORD(&reg->ctrl_status, 0x20);
811 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 812
813 /* Get the fb rev level */
3d71644c 814 ha->fb_rev = RD_FB_CMD_REG(ha, reg);
abbd8870
AV		 815
816 if (ha->fb_rev == FPM_2300)
a157b101 817 pci_clear_mwi(ha->pdev);
abbd8870
AV		 818
819 /* Deselect FPM registers. */
3d71644c
AV		 820 WRT_REG_WORD(&reg->ctrl_status, 0x0);
821 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 822
823 /* Release RISC module. */
3d71644c 824 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
abbd8870 825 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 826 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0)
abbd8870
AV		 827 break;
828
829 udelay(10);
1da177e4 830 }
1da177e4 831
abbd8870
AV		 832 spin_unlock_irqrestore(&ha->hardware_lock, flags);
833 }
1da177e4 834
abbd8870
AV		 835 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
836
737faece 837 pci_disable_rom(ha->pdev);
1da177e4 838
abbd8870
AV		 839 /* Get PCI bus information. */
840 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 841 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 842 spin_unlock_irqrestore(&ha->hardware_lock, flags);
843
844 return QLA_SUCCESS;
1da177e4
LT		 845}
846
0107109e
AV		 847/**
848 * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers.
849 * @ha: HA context
850 *
851 * Returns 0 on success.
852 */
853int
e315cd28 854qla24xx_pci_config(scsi_qla_host_t *vha)
0107109e 855{
a157b101 856 uint16_t w;
0107109e 857 unsigned long flags = 0;
e315cd28 858 struct qla_hw_data *ha = vha->hw;
0107109e 859 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
0107109e
AV		 860
861 pci_set_master(ha->pdev);
af6177d8 862 pci_try_set_mwi(ha->pdev);
0107109e
AV		 863
864 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 865 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
0107109e
AV		 866 w &= ~PCI_COMMAND_INTX_DISABLE;
867 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
868
869 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
870
871 /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */
f85ec187
AV		 872 if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
873 pcix_set_mmrbc(ha->pdev, 2048);
0107109e
AV		 874
875 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 876 if (pci_is_pcie(ha->pdev))
5ffd3a52 877 pcie_set_readrq(ha->pdev, 4096);
0107109e 878
737faece 879 pci_disable_rom(ha->pdev);
0107109e 880
44c10138 881 ha->chip_revision = ha->pdev->revision;
a8488abe 882
0107109e
AV		 883 /* Get PCI bus information. */
884 spin_lock_irqsave(&ha->hardware_lock, flags);
885 ha->pci_attr = RD_REG_DWORD(&reg->ctrl_status);
886 spin_unlock_irqrestore(&ha->hardware_lock, flags);
887
888 return QLA_SUCCESS;
889}
890
c3a2f0df
AV		 891/**
892 * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers.
893 * @ha: HA context
894 *
895 * Returns 0 on success.
896 */
897int
e315cd28 898qla25xx_pci_config(scsi_qla_host_t *vha)
c3a2f0df
AV		 899{
900 uint16_t w;
e315cd28 901 struct qla_hw_data *ha = vha->hw;
c3a2f0df
AV		 902
903 pci_set_master(ha->pdev);
904 pci_try_set_mwi(ha->pdev);
905
906 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
907 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
908 w &= ~PCI_COMMAND_INTX_DISABLE;
909 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
910
911 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 912 if (pci_is_pcie(ha->pdev))
5ffd3a52 913 pcie_set_readrq(ha->pdev, 4096);
c3a2f0df 914
737faece 915 pci_disable_rom(ha->pdev);
c3a2f0df
AV		 916
917 ha->chip_revision = ha->pdev->revision;
918
919 return QLA_SUCCESS;
920}
921
1da177e4
LT		 922/**
923 * qla2x00_isp_firmware() - Choose firmware image.
924 * @ha: HA context
925 *
926 * Returns 0 on success.
927 */
928static int
e315cd28 929qla2x00_isp_firmware(scsi_qla_host_t *vha)
1da177e4
LT		 930{
931 int rval;
42e421b1
AV		 932 uint16_t loop_id, topo, sw_cap;
933 uint8_t domain, area, al_pa;
e315cd28 934 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 935
936 /* Assume loading risc code */
fa2a1ce5 937 rval = QLA_FUNCTION_FAILED;
1da177e4
LT		 938
939 if (ha->flags.disable_risc_code_load) {
7c3df132 940 ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n");
1da177e4
LT		 941
942 /* Verify checksum of loaded RISC code. */
e315cd28 943 rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address);
42e421b1
AV		 944 if (rval == QLA_SUCCESS) {
945 /* And, verify we are not in ROM code. */
e315cd28 946 rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa,
42e421b1
AV		 947 &area, &domain, &topo, &sw_cap);
948 }
1da177e4
LT		 949 }
950
7c3df132
SK		 951 if (rval)
952 ql_dbg(ql_dbg_init, vha, 0x007a,
953 "**** Load RISC code ****.\n");
1da177e4
LT		 954
955 return (rval);
956}
957
958/**
959 * qla2x00_reset_chip() - Reset ISP chip.
960 * @ha: HA context
961 *
962 * Returns 0 on success.
963 */
abbd8870 964void
e315cd28 965qla2x00_reset_chip(scsi_qla_host_t *vha)
1da177e4
LT		 966{
967 unsigned long flags = 0;
e315cd28 968 struct qla_hw_data *ha = vha->hw;
3d71644c 969 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 970 uint32_t cnt;
1da177e4
LT		 971 uint16_t cmd;
972
85880801
AV		 973 if (unlikely(pci_channel_offline(ha->pdev)))
974 return;
975
fd34f556 976 ha->isp_ops->disable_intrs(ha);
1da177e4
LT		 977
978 spin_lock_irqsave(&ha->hardware_lock, flags);
979
980 /* Turn off master enable */
981 cmd = 0;
982 pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd);
983 cmd &= ~PCI_COMMAND_MASTER;
984 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
985
986 if (!IS_QLA2100(ha)) {
987 /* Pause RISC. */
988 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
989 if (IS_QLA2200(ha) || IS_QLA2300(ha)) {
990 for (cnt = 0; cnt < 30000; cnt++) {
991 if ((RD_REG_WORD(&reg->hccr) &
992 HCCR_RISC_PAUSE) != 0)
993 break;
994 udelay(100);
995 }
996 } else {
997 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
998 udelay(10);
999 }
1000
1001 /* Select FPM registers. */
1002 WRT_REG_WORD(&reg->ctrl_status, 0x20);
1003 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1004
1005 /* FPM Soft Reset. */
1006 WRT_REG_WORD(&reg->fpm_diag_config, 0x100);
1007 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
1008
1009 /* Toggle Fpm Reset. */
1010 if (!IS_QLA2200(ha)) {
1011 WRT_REG_WORD(&reg->fpm_diag_config, 0x0);
1012 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
1013 }
1014
1015 /* Select frame buffer registers. */
1016 WRT_REG_WORD(&reg->ctrl_status, 0x10);
1017 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1018
1019 /* Reset frame buffer FIFOs. */
1020 if (IS_QLA2200(ha)) {
1021 WRT_FB_CMD_REG(ha, reg, 0xa000);
1022 RD_FB_CMD_REG(ha, reg); /* PCI Posting. */
1023 } else {
1024 WRT_FB_CMD_REG(ha, reg, 0x00fc);
1025
1026 /* Read back fb_cmd until zero or 3 seconds max */
1027 for (cnt = 0; cnt < 3000; cnt++) {
1028 if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0)
1029 break;
1030 udelay(100);
1031 }
1032 }
1033
1034 /* Select RISC module registers. */
1035 WRT_REG_WORD(&reg->ctrl_status, 0);
1036 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1037
1038 /* Reset RISC processor. */
1039 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
1040 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1041
1042 /* Release RISC processor. */
1043 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
1044 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1045 }
1046
1047 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
1048 WRT_REG_WORD(&reg->hccr, HCCR_CLR_HOST_INT);
1049
1050 /* Reset ISP chip. */
1051 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1052
1053 /* Wait for RISC to recover from reset. */
1054 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1055 /*
1056 * It is necessary to for a delay here since the card doesn't
1057 * respond to PCI reads during a reset. On some architectures
1058 * this will result in an MCA.
1059 */
1060 udelay(20);
1061 for (cnt = 30000; cnt; cnt--) {
1062 if ((RD_REG_WORD(&reg->ctrl_status) &
1063 CSR_ISP_SOFT_RESET) == 0)
1064 break;
1065 udelay(100);
1066 }
1067 } else
1068 udelay(10);
1069
1070 /* Reset RISC processor. */
1071 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
1072
1073 WRT_REG_WORD(&reg->semaphore, 0);
1074
1075 /* Release RISC processor. */
1076 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
1077 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1078
1079 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1080 for (cnt = 0; cnt < 30000; cnt++) {
ffb39f03 1081 if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY)
1da177e4 1082 break;
1da177e4
LT		 1083
1084 udelay(100);
1085 }
1086 } else
1087 udelay(100);
1088
1089 /* Turn on master enable */
1090 cmd |= PCI_COMMAND_MASTER;
1091 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
1092
1093 /* Disable RISC pause on FPM parity error. */
1094 if (!IS_QLA2100(ha)) {
1095 WRT_REG_WORD(&reg->hccr, HCCR_DISABLE_PARITY_PAUSE);
1096 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1097 }
1098
1099 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1100}
1101
b1d46989
MI		 1102/**
1103 * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC.
1104 *
1105 * Returns 0 on success.
1106 */
fa492630 1107static int
b1d46989
MI		 1108qla81xx_reset_mpi(scsi_qla_host_t *vha)
1109{
1110 uint16_t mb[4] = {0x1010, 0, 1, 0};
1111
6246b8a1
GM		 1112 if (!IS_QLA81XX(vha->hw))
1113 return QLA_SUCCESS;
1114
b1d46989
MI		 1115 return qla81xx_write_mpi_register(vha, mb);
1116}
1117
0107109e 1118/**
88c26663 1119 * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC.
0107109e
AV		 1120 * @ha: HA context
1121 *
1122 * Returns 0 on success.
1123 */
88c26663 1124static inline void
e315cd28 1125qla24xx_reset_risc(scsi_qla_host_t *vha)
0107109e
AV		 1126{
1127 unsigned long flags = 0;
e315cd28 1128 struct qla_hw_data *ha = vha->hw;
0107109e
AV		 1129 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1130 uint32_t cnt, d2;
335a1cc9 1131 uint16_t wd;
b1d46989 1132 static int abts_cnt; /* ISP abort retry counts */
0107109e 1133
0107109e
AV		 1134 spin_lock_irqsave(&ha->hardware_lock, flags);
1135
1136 /* Reset RISC. */
1137 WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
1138 for (cnt = 0; cnt < 30000; cnt++) {
1139 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
1140 break;
1141
1142 udelay(10);
1143 }
1144
1145 WRT_REG_DWORD(&reg->ctrl_status,
1146 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
335a1cc9 1147 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
88c26663 1148
335a1cc9 1149 udelay(100);
88c26663 1150 /* Wait for firmware to complete NVRAM accesses. */
88c26663
AV		 1151 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1152 for (cnt = 10000 ; cnt && d2; cnt--) {
1153 udelay(5);
1154 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1155 barrier();
1156 }
1157
335a1cc9 1158 /* Wait for soft-reset to complete. */
0107109e
AV		 1159 d2 = RD_REG_DWORD(&reg->ctrl_status);
1160 for (cnt = 6000000 ; cnt && (d2 & CSRX_ISP_SOFT_RESET); cnt--) {
1161 udelay(5);
1162 d2 = RD_REG_DWORD(&reg->ctrl_status);
1163 barrier();
1164 }
1165
b1d46989
MI		 1166 /* If required, do an MPI FW reset now */
1167 if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
1168 if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
1169 if (++abts_cnt < 5) {
1170 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1171 set_bit(MPI_RESET_NEEDED, &vha->dpc_flags);
1172 } else {
1173 /*
1174 * We exhausted the ISP abort retries. We have to
1175 * set the board offline.
1176 */
1177 abts_cnt = 0;
1178 vha->flags.online = 0;
1179 }
1180 }
1181 }
1182
0107109e
AV		 1183 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
1184 RD_REG_DWORD(&reg->hccr);
1185
1186 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
1187 RD_REG_DWORD(&reg->hccr);
1188
1189 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
1190 RD_REG_DWORD(&reg->hccr);
1191
1192 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1193 for (cnt = 6000000 ; cnt && d2; cnt--) {
1194 udelay(5);
1195 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1196 barrier();
1197 }
1198
1199 spin_unlock_irqrestore(&ha->hardware_lock, flags);
124f85e6
AV		 1200
1201 if (IS_NOPOLLING_TYPE(ha))
1202 ha->isp_ops->enable_intrs(ha);
0107109e
AV		 1203}
1204
4ea2c9c7
JC		 1205static void
1206qla25xx_read_risc_sema_reg(scsi_qla_host_t *vha, uint32_t *data)
1207{
1208 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
1209
1210 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
1211 *data = RD_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET);
1212
1213}
1214
1215static void
1216qla25xx_write_risc_sema_reg(scsi_qla_host_t *vha, uint32_t data)
1217{
1218 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
1219
1220 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
1221 WRT_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET, data);
1222}
1223
1224static void
1225qla25xx_manipulate_risc_semaphore(scsi_qla_host_t *vha)
1226{
1227 struct qla_hw_data *ha = vha->hw;
1228 uint32_t wd32 = 0;
1229 uint delta_msec = 100;
1230 uint elapsed_msec = 0;
1231 uint timeout_msec;
1232 ulong n;
1233
1234 if (!IS_QLA25XX(ha) && !IS_QLA2031(ha))
1235 return;
1236
1237attempt:
1238 timeout_msec = TIMEOUT_SEMAPHORE;
1239 n = timeout_msec / delta_msec;
1240 while (n--) {
1241 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_SET);
1242 qla25xx_read_risc_sema_reg(vha, &wd32);
1243 if (wd32 & RISC_SEMAPHORE)
1244 break;
1245 msleep(delta_msec);
1246 elapsed_msec += delta_msec;
1247 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
1248 goto force;
1249 }
1250
1251 if (!(wd32 & RISC_SEMAPHORE))
1252 goto force;
1253
1254 if (!(wd32 & RISC_SEMAPHORE_FORCE))
1255 goto acquired;
1256
1257 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_CLR);
1258 timeout_msec = TIMEOUT_SEMAPHORE_FORCE;
1259 n = timeout_msec / delta_msec;
1260 while (n--) {
1261 qla25xx_read_risc_sema_reg(vha, &wd32);
1262 if (!(wd32 & RISC_SEMAPHORE_FORCE))
1263 break;
1264 msleep(delta_msec);
1265 elapsed_msec += delta_msec;
1266 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
1267 goto force;
1268 }
1269
1270 if (wd32 & RISC_SEMAPHORE_FORCE)
1271 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_CLR);
1272
1273 goto attempt;
1274
1275force:
1276 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_SET);
1277
1278acquired:
1279 return;
1280}
1281
88c26663
AV		 1282/**
1283 * qla24xx_reset_chip() - Reset ISP24xx chip.
1284 * @ha: HA context
1285 *
1286 * Returns 0 on success.
1287 */
1288void
e315cd28 1289qla24xx_reset_chip(scsi_qla_host_t *vha)
88c26663 1290{
e315cd28 1291 struct qla_hw_data *ha = vha->hw;
85880801
AV		 1292
1293 if (pci_channel_offline(ha->pdev) &&
1294 ha->flags.pci_channel_io_perm_failure) {
1295 return;
1296 }
1297
fd34f556 1298 ha->isp_ops->disable_intrs(ha);
88c26663 1299
4ea2c9c7
JC		 1300 qla25xx_manipulate_risc_semaphore(vha);
1301
88c26663 1302 /* Perform RISC reset. */
e315cd28 1303 qla24xx_reset_risc(vha);
88c26663
AV		 1304}
1305
1da177e4
LT		 1306/**
1307 * qla2x00_chip_diag() - Test chip for proper operation.
1308 * @ha: HA context
1309 *
1310 * Returns 0 on success.
1311 */
abbd8870 1312int
e315cd28 1313qla2x00_chip_diag(scsi_qla_host_t *vha)
1da177e4
LT		 1314{
1315 int rval;
e315cd28 1316 struct qla_hw_data *ha = vha->hw;
3d71644c 1317 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 1318 unsigned long flags = 0;
1319 uint16_t data;
1320 uint32_t cnt;
1321 uint16_t mb[5];
73208dfd 1322 struct req_que *req = ha->req_q_map[0];
1da177e4
LT		 1323
1324 /* Assume a failed state */
1325 rval = QLA_FUNCTION_FAILED;
1326
7c3df132
SK		 1327 ql_dbg(ql_dbg_init, vha, 0x007b,
1328 "Testing device at %lx.\n", (u_long)&reg->flash_address);
1da177e4
LT		 1329
1330 spin_lock_irqsave(&ha->hardware_lock, flags);
1331
1332 /* Reset ISP chip. */
1333 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1334
1335 /*
1336 * We need to have a delay here since the card will not respond while
1337 * in reset causing an MCA on some architectures.
1338 */
1339 udelay(20);
1340 data = qla2x00_debounce_register(&reg->ctrl_status);
1341 for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {
1342 udelay(5);
1343 data = RD_REG_WORD(&reg->ctrl_status);
1344 barrier();
1345 }
1346
1347 if (!cnt)
1348 goto chip_diag_failed;
1349
7c3df132
SK		 1350 ql_dbg(ql_dbg_init, vha, 0x007c,
1351 "Reset register cleared by chip reset.\n");
1da177e4
LT		 1352
1353 /* Reset RISC processor. */
1354 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
1355 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
1356
1357 /* Workaround for QLA2312 PCI parity error */
1358 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1359 data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0));
1360 for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) {
1361 udelay(5);
1362 data = RD_MAILBOX_REG(ha, reg, 0);
fa2a1ce5 1363 barrier();
1da177e4
LT		 1364 }
1365 } else
1366 udelay(10);
1367
1368 if (!cnt)
1369 goto chip_diag_failed;
1370
1371 /* Check product ID of chip */
7c3df132 1372 ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product Id of chip.\n");
1da177e4
LT		 1373
1374 mb[1] = RD_MAILBOX_REG(ha, reg, 1);
1375 mb[2] = RD_MAILBOX_REG(ha, reg, 2);
1376 mb[3] = RD_MAILBOX_REG(ha, reg, 3);
1377 mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4));
1378 if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) ||
1379 mb[3] != PROD_ID_3) {
7c3df132
SK		 1380 ql_log(ql_log_warn, vha, 0x0062,
1381 "Wrong product ID = 0x%x,0x%x,0x%x.\n",
1382 mb[1], mb[2], mb[3]);
1da177e4
LT		 1383
1384 goto chip_diag_failed;
1385 }
1386 ha->product_id[0] = mb[1];
1387 ha->product_id[1] = mb[2];
1388 ha->product_id[2] = mb[3];
1389 ha->product_id[3] = mb[4];
1390
1391 /* Adjust fw RISC transfer size */
73208dfd 1392 if (req->length > 1024)
1da177e4
LT		 1393 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024;
1394 else
1395 ha->fw_transfer_size = REQUEST_ENTRY_SIZE *
73208dfd 1396 req->length;
1da177e4
LT		 1397
1398 if (IS_QLA2200(ha) &&
1399 RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) {
1400 /* Limit firmware transfer size with a 2200A */
7c3df132 1401 ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n");
1da177e4 1402
ea5b6382 1403 ha->device_type |= DT_ISP2200A;
1da177e4
LT		 1404 ha->fw_transfer_size = 128;
1405 }
1406
1407 /* Wrap Incoming Mailboxes Test. */
1408 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1409
7c3df132 1410 ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n");
e315cd28 1411 rval = qla2x00_mbx_reg_test(vha);
7c3df132
SK		 1412 if (rval)
1413 ql_log(ql_log_warn, vha, 0x0080,
1414 "Failed mailbox send register test.\n");
1415 else
1da177e4
LT		 1416 /* Flag a successful rval */
1417 rval = QLA_SUCCESS;
1da177e4
LT		 1418 spin_lock_irqsave(&ha->hardware_lock, flags);
1419
1420chip_diag_failed:
1421 if (rval)
7c3df132
SK		 1422 ql_log(ql_log_info, vha, 0x0081,
1423 "Chip diagnostics **** FAILED ****.\n");
1da177e4
LT		 1424
1425 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1426
1427 return (rval);
1428}
1429
0107109e
AV		 1430/**
1431 * qla24xx_chip_diag() - Test ISP24xx for proper operation.
1432 * @ha: HA context
1433 *
1434 * Returns 0 on success.
1435 */
1436int
e315cd28 1437qla24xx_chip_diag(scsi_qla_host_t *vha)
0107109e
AV		 1438{
1439 int rval;
e315cd28 1440 struct qla_hw_data *ha = vha->hw;
73208dfd 1441 struct req_que *req = ha->req_q_map[0];
0107109e 1442
7ec0effd 1443 if (IS_P3P_TYPE(ha))
a9083016
GM		 1444 return QLA_SUCCESS;
1445
73208dfd 1446 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
0107109e 1447
e315cd28 1448 rval = qla2x00_mbx_reg_test(vha);
0107109e 1449 if (rval) {
7c3df132
SK		 1450 ql_log(ql_log_warn, vha, 0x0082,
1451 "Failed mailbox send register test.\n");
0107109e
AV		 1452 } else {
1453 /* Flag a successful rval */
1454 rval = QLA_SUCCESS;
1455 }
1456
1457 return rval;
1458}
1459
a7a167bf 1460void
e315cd28 1461qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
0107109e 1462{
a7a167bf
AV		 1463 int rval;
1464 uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
73208dfd 1465 eft_size, fce_size, mq_size;
df613b96
AV		 1466 dma_addr_t tc_dma;
1467 void *tc;
e315cd28 1468 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 1469 struct req_que *req = ha->req_q_map[0];
1470 struct rsp_que *rsp = ha->rsp_q_map[0];
a7a167bf
AV		 1471
1472 if (ha->fw_dump) {
7c3df132
SK		 1473 ql_dbg(ql_dbg_init, vha, 0x00bd,
1474 "Firmware dump already allocated.\n");
a7a167bf
AV		 1475 return;
1476 }
d4e3e04d 1477
0107109e 1478 ha->fw_dumped = 0;
61f098dd 1479 ha->fw_dump_cap_flags = 0;
f73cb695
CD		 1480 dump_size = fixed_size = mem_size = eft_size = fce_size = mq_size = 0;
1481 req_q_size = rsp_q_size = 0;
1482
1483 if (IS_QLA27XX(ha))
1484 goto try_fce;
1485
d4e3e04d 1486 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
a7a167bf 1487 fixed_size = sizeof(struct qla2100_fw_dump);
d4e3e04d 1488 } else if (IS_QLA23XX(ha)) {
a7a167bf
AV		 1489 fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
1490 mem_size = (ha->fw_memory_size - 0x11000 + 1) *
1491 sizeof(uint16_t);
e428924c 1492 } else if (IS_FWI2_CAPABLE(ha)) {
6246b8a1
GM		 1493 if (IS_QLA83XX(ha))
1494 fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem);
1495 else if (IS_QLA81XX(ha))
3a03eb79
AV		 1496 fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
1497 else if (IS_QLA25XX(ha))
1498 fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
1499 else
1500 fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
f73cb695 1501
a7a167bf
AV		 1502 mem_size = (ha->fw_memory_size - 0x100000 + 1) *
1503 sizeof(uint32_t);
050c9bb1 1504 if (ha->mqenable) {
6246b8a1
GM		 1505 if (!IS_QLA83XX(ha))
1506 mq_size = sizeof(struct qla2xxx_mq_chain);
050c9bb1
GM		 1507 /*
1508 * Allocate maximum buffer size for all queues.
1509 * Resizing must be done at end-of-dump processing.
1510 */
1511 mq_size += ha->max_req_queues *
1512 (req->length * sizeof(request_t));
1513 mq_size += ha->max_rsp_queues *
1514 (rsp->length * sizeof(response_t));
1515 }
00876ae8 1516 if (ha->tgt.atio_ring)
2d70c103 1517 mq_size += ha->tgt.atio_q_length * sizeof(request_t);
df613b96 1518 /* Allocate memory for Fibre Channel Event Buffer. */
f73cb695
CD		 1519 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
1520 !IS_QLA27XX(ha))
436a7b11 1521 goto try_eft;
df613b96 1522
f73cb695
CD		 1523try_fce:
1524 if (ha->fce)
1525 dma_free_coherent(&ha->pdev->dev,
1526 FCE_SIZE, ha->fce, ha->fce_dma);
1527
1528 /* Allocate memory for Fibre Channel Event Buffer. */
df613b96
AV		 1529 tc = dma_alloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
1530 GFP_KERNEL);
1531 if (!tc) {
7c3df132
SK		 1532 ql_log(ql_log_warn, vha, 0x00be,
1533 "Unable to allocate (%d KB) for FCE.\n",
1534 FCE_SIZE / 1024);
17d98630 1535 goto try_eft;
df613b96
AV		 1536 }
1537
1538 memset(tc, 0, FCE_SIZE);
e315cd28 1539 rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS,
df613b96
AV		 1540 ha->fce_mb, &ha->fce_bufs);
1541 if (rval) {
7c3df132
SK		 1542 ql_log(ql_log_warn, vha, 0x00bf,
1543 "Unable to initialize FCE (%d).\n", rval);
df613b96
AV		 1544 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc,
1545 tc_dma);
1546 ha->flags.fce_enabled = 0;
17d98630 1547 goto try_eft;
df613b96 1548 }
cfb0919c 1549 ql_dbg(ql_dbg_init, vha, 0x00c0,
7c3df132 1550 "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024);
df613b96 1551
7d9dade3 1552 fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE;
df613b96
AV		 1553 ha->flags.fce_enabled = 1;
1554 ha->fce_dma = tc_dma;
1555 ha->fce = tc;
f73cb695 1556
436a7b11 1557try_eft:
f73cb695
CD		 1558 if (ha->eft)
1559 dma_free_coherent(&ha->pdev->dev,
1560 EFT_SIZE, ha->eft, ha->eft_dma);
1561
436a7b11
AV		 1562 /* Allocate memory for Extended Trace Buffer. */
1563 tc = dma_alloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
1564 GFP_KERNEL);
1565 if (!tc) {
7c3df132
SK		 1566 ql_log(ql_log_warn, vha, 0x00c1,
1567 "Unable to allocate (%d KB) for EFT.\n",
1568 EFT_SIZE / 1024);
436a7b11
AV		 1569 goto cont_alloc;
1570 }
1571
1572 memset(tc, 0, EFT_SIZE);
e315cd28 1573 rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
436a7b11 1574 if (rval) {
7c3df132
SK		 1575 ql_log(ql_log_warn, vha, 0x00c2,
1576 "Unable to initialize EFT (%d).\n", rval);
436a7b11
AV		 1577 dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc,
1578 tc_dma);
1579 goto cont_alloc;
1580 }
cfb0919c 1581 ql_dbg(ql_dbg_init, vha, 0x00c3,
7c3df132 1582 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
436a7b11
AV		 1583
1584 eft_size = EFT_SIZE;
1585 ha->eft_dma = tc_dma;
1586 ha->eft = tc;
d4e3e04d 1587 }
f73cb695 1588
a7a167bf 1589cont_alloc:
f73cb695
CD		 1590 if (IS_QLA27XX(ha)) {
1591 if (!ha->fw_dump_template) {
1592 ql_log(ql_log_warn, vha, 0x00ba,
1593 "Failed missing fwdump template\n");
1594 return;
1595 }
1596 dump_size = qla27xx_fwdt_calculate_dump_size(vha);
1597 ql_dbg(ql_dbg_init, vha, 0x00fa,
1598 "-> allocating fwdump (%x bytes)...\n", dump_size);
1599 goto allocate;
1600 }
1601
73208dfd
AC		 1602 req_q_size = req->length * sizeof(request_t);
1603 rsp_q_size = rsp->length * sizeof(response_t);
a7a167bf 1604 dump_size = offsetof(struct qla2xxx_fw_dump, isp);
2afa19a9 1605 dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size;
bb99de67
AV		 1606 ha->chain_offset = dump_size;
1607 dump_size += mq_size + fce_size;
d4e3e04d 1608
f73cb695 1609allocate:
d4e3e04d 1610 ha->fw_dump = vmalloc(dump_size);
a7a167bf 1611 if (!ha->fw_dump) {
7c3df132
SK		 1612 ql_log(ql_log_warn, vha, 0x00c4,
1613 "Unable to allocate (%d KB) for firmware dump.\n",
1614 dump_size / 1024);
a7a167bf 1615
e30d1756
MI		 1616 if (ha->fce) {
1617 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
1618 ha->fce_dma);
1619 ha->fce = NULL;
1620 ha->fce_dma = 0;
1621 }
1622
a7a167bf
AV		 1623 if (ha->eft) {
1624 dma_free_coherent(&ha->pdev->dev, eft_size, ha->eft,
1625 ha->eft_dma);
1626 ha->eft = NULL;
1627 ha->eft_dma = 0;
1628 }
1629 return;
1630 }
f73cb695 1631 ha->fw_dump_len = dump_size;
cfb0919c 1632 ql_dbg(ql_dbg_init, vha, 0x00c5,
7c3df132 1633 "Allocated (%d KB) for firmware dump.\n", dump_size / 1024);
a7a167bf 1634
f73cb695
CD		 1635 if (IS_QLA27XX(ha))
1636 return;
1637
a7a167bf
AV		 1638 ha->fw_dump->signature[0] = 'Q';
1639 ha->fw_dump->signature[1] = 'L';
1640 ha->fw_dump->signature[2] = 'G';
1641 ha->fw_dump->signature[3] = 'C';
1642 ha->fw_dump->version = __constant_htonl(1);
1643
1644 ha->fw_dump->fixed_size = htonl(fixed_size);
1645 ha->fw_dump->mem_size = htonl(mem_size);
1646 ha->fw_dump->req_q_size = htonl(req_q_size);
1647 ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
1648
1649 ha->fw_dump->eft_size = htonl(eft_size);
1650 ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma));
1651 ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma));
1652
1653 ha->fw_dump->header_size =
1654 htonl(offsetof(struct qla2xxx_fw_dump, isp));
0107109e
AV		 1655}
1656
18e7555a
AV		 1657static int
1658qla81xx_mpi_sync(scsi_qla_host_t *vha)
1659{
1660#define MPS_MASK 0xe0
1661 int rval;
1662 uint16_t dc;
1663 uint32_t dw;
18e7555a
AV		 1664
1665 if (!IS_QLA81XX(vha->hw))
1666 return QLA_SUCCESS;
1667
1668 rval = qla2x00_write_ram_word(vha, 0x7c00, 1);
1669 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1670 ql_log(ql_log_warn, vha, 0x0105,
1671 "Unable to acquire semaphore.\n");
18e7555a
AV		 1672 goto done;
1673 }
1674
1675 pci_read_config_word(vha->hw->pdev, 0x54, &dc);
1676 rval = qla2x00_read_ram_word(vha, 0x7a15, &dw);
1677 if (rval != QLA_SUCCESS) {
7c3df132 1678 ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n");
18e7555a
AV		 1679 goto done_release;
1680 }
1681
1682 dc &= MPS_MASK;
1683 if (dc == (dw & MPS_MASK))
1684 goto done_release;
1685
1686 dw &= ~MPS_MASK;
1687 dw |= dc;
1688 rval = qla2x00_write_ram_word(vha, 0x7a15, dw);
1689 if (rval != QLA_SUCCESS) {
7c3df132 1690 ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n");
18e7555a
AV		 1691 }
1692
1693done_release:
1694 rval = qla2x00_write_ram_word(vha, 0x7c00, 0);
1695 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1696 ql_log(ql_log_warn, vha, 0x006d,
1697 "Unable to release semaphore.\n");
18e7555a
AV		 1698 }
1699
1700done:
1701 return rval;
1702}
1703
8d93f550
CD		 1704int
1705qla2x00_alloc_outstanding_cmds(struct qla_hw_data *ha, struct req_que *req)
1706{
1707 /* Don't try to reallocate the array */
1708 if (req->outstanding_cmds)
1709 return QLA_SUCCESS;
1710
1711 if (!IS_FWI2_CAPABLE(ha) || (ha->mqiobase &&
1712 (ql2xmultique_tag || ql2xmaxqueues > 1)))
1713 req->num_outstanding_cmds = DEFAULT_OUTSTANDING_COMMANDS;
1714 else {
1715 if (ha->fw_xcb_count <= ha->fw_iocb_count)
1716 req->num_outstanding_cmds = ha->fw_xcb_count;
1717 else
1718 req->num_outstanding_cmds = ha->fw_iocb_count;
1719 }
1720
1721 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
1722 req->num_outstanding_cmds, GFP_KERNEL);
1723
1724 if (!req->outstanding_cmds) {
1725 /*
1726 * Try to allocate a minimal size just so we can get through
1727 * initialization.
1728 */
1729 req->num_outstanding_cmds = MIN_OUTSTANDING_COMMANDS;
1730 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
1731 req->num_outstanding_cmds, GFP_KERNEL);
1732
1733 if (!req->outstanding_cmds) {
1734 ql_log(ql_log_fatal, NULL, 0x0126,
1735 "Failed to allocate memory for "
1736 "outstanding_cmds for req_que %p.\n", req);
1737 req->num_outstanding_cmds = 0;
1738 return QLA_FUNCTION_FAILED;
1739 }
1740 }
1741
1742 return QLA_SUCCESS;
1743}
1744
1da177e4
LT		 1745/**
1746 * qla2x00_setup_chip() - Load and start RISC firmware.
1747 * @ha: HA context
1748 *
1749 * Returns 0 on success.
1750 */
1751static int
e315cd28 1752qla2x00_setup_chip(scsi_qla_host_t *vha)
1da177e4 1753{
0107109e
AV		 1754 int rval;
1755 uint32_t srisc_address = 0;
e315cd28 1756 struct qla_hw_data *ha = vha->hw;
3db0652e
AV		 1757 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1758 unsigned long flags;
dda772e8 1759 uint16_t fw_major_version;
3db0652e 1760
7ec0effd 1761 if (IS_P3P_TYPE(ha)) {
a9083016 1762 rval = ha->isp_ops->load_risc(vha, &srisc_address);
14e303d9
AV		 1763 if (rval == QLA_SUCCESS) {
1764 qla2x00_stop_firmware(vha);
a9083016 1765 goto enable_82xx_npiv;
14e303d9 1766 } else
b963752f 1767 goto failed;
a9083016
GM		 1768 }
1769
3db0652e
AV		 1770 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1771 /* Disable SRAM, Instruction RAM and GP RAM parity. */
1772 spin_lock_irqsave(&ha->hardware_lock, flags);
1773 WRT_REG_WORD(&reg->hccr, (HCCR_ENABLE_PARITY + 0x0));
1774 RD_REG_WORD(&reg->hccr);
1775 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1776 }
1da177e4 1777
18e7555a
AV		 1778 qla81xx_mpi_sync(vha);
1779
1da177e4 1780 /* Load firmware sequences */
e315cd28 1781 rval = ha->isp_ops->load_risc(vha, &srisc_address);
0107109e 1782 if (rval == QLA_SUCCESS) {
7c3df132
SK		 1783 ql_dbg(ql_dbg_init, vha, 0x00c9,
1784 "Verifying Checksum of loaded RISC code.\n");
1da177e4 1785
e315cd28 1786 rval = qla2x00_verify_checksum(vha, srisc_address);
1da177e4
LT		 1787 if (rval == QLA_SUCCESS) {
1788 /* Start firmware execution. */
7c3df132
SK		 1789 ql_dbg(ql_dbg_init, vha, 0x00ca,
1790 "Starting firmware.\n");
1da177e4 1791
e315cd28 1792 rval = qla2x00_execute_fw(vha, srisc_address);
1da177e4 1793 /* Retrieve firmware information. */
dda772e8 1794 if (rval == QLA_SUCCESS) {
a9083016 1795enable_82xx_npiv:
dda772e8 1796 fw_major_version = ha->fw_major_version;
7ec0effd 1797 if (IS_P3P_TYPE(ha))
3173167f 1798 qla82xx_check_md_needed(vha);
6246b8a1
GM		 1799 else
1800 rval = qla2x00_get_fw_version(vha);
ca9e9c3e
AV		 1801 if (rval != QLA_SUCCESS)
1802 goto failed;
2c3dfe3f 1803 ha->flags.npiv_supported = 0;
e315cd28 1804 if (IS_QLA2XXX_MIDTYPE(ha) &&
946fb891 1805 (ha->fw_attributes & BIT_2)) {
2c3dfe3f 1806 ha->flags.npiv_supported = 1;
4d0ea247
SJ		 1807 if ((!ha->max_npiv_vports) ||
1808 ((ha->max_npiv_vports + 1) %
eb66dc60 1809 MIN_MULTI_ID_FABRIC))
4d0ea247 1810 ha->max_npiv_vports =
eb66dc60 1811 MIN_MULTI_ID_FABRIC - 1;
4d0ea247 1812 }
24a08138 1813 qla2x00_get_resource_cnts(vha, NULL,
8d93f550 1814 &ha->fw_xcb_count, NULL, &ha->fw_iocb_count,
f3a0a77e 1815 &ha->max_npiv_vports, NULL);
d743de66 1816
8d93f550
CD		 1817 /*
1818 * Allocate the array of outstanding commands
1819 * now that we know the firmware resources.
1820 */
1821 rval = qla2x00_alloc_outstanding_cmds(ha,
1822 vha->req);
1823 if (rval != QLA_SUCCESS)
1824 goto failed;
1825
be5ea3cf 1826 if (!fw_major_version && ql2xallocfwdump
7ec0effd 1827 && !(IS_P3P_TYPE(ha)))
08de2844 1828 qla2x00_alloc_fw_dump(vha);
3b6e5b9d
CD		 1829 } else {
1830 goto failed;
1da177e4
LT		 1831 }
1832 } else {
7c3df132
SK		 1833 ql_log(ql_log_fatal, vha, 0x00cd,
1834 "ISP Firmware failed checksum.\n");
1835 goto failed;
1da177e4 1836 }
c74d88a4
AV		 1837 } else
1838 goto failed;
1da177e4 1839
3db0652e
AV		 1840 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1841 /* Enable proper parity. */
1842 spin_lock_irqsave(&ha->hardware_lock, flags);
1843 if (IS_QLA2300(ha))
1844 /* SRAM parity */
1845 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x1);
1846 else
1847 /* SRAM, Instruction RAM and GP RAM parity */
1848 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x7);
1849 RD_REG_WORD(&reg->hccr);
1850 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1851 }
1852
1d2874de
JC		 1853 if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
1854 uint32_t size;
1855
1856 rval = qla81xx_fac_get_sector_size(vha, &size);
1857 if (rval == QLA_SUCCESS) {
1858 ha->flags.fac_supported = 1;
1859 ha->fdt_block_size = size << 2;
1860 } else {
7c3df132 1861 ql_log(ql_log_warn, vha, 0x00ce,
1d2874de
JC		 1862 "Unsupported FAC firmware (%d.%02d.%02d).\n",
1863 ha->fw_major_version, ha->fw_minor_version,
1864 ha->fw_subminor_version);
1ca60e3b 1865
f73cb695 1866 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
6246b8a1
GM		 1867 ha->flags.fac_supported = 0;
1868 rval = QLA_SUCCESS;
1869 }
1d2874de
JC		 1870 }
1871 }
ca9e9c3e 1872failed:
1da177e4 1873 if (rval) {
7c3df132
SK		 1874 ql_log(ql_log_fatal, vha, 0x00cf,
1875 "Setup chip ****FAILED****.\n");
1da177e4
LT		 1876 }
1877
1878 return (rval);
1879}
1880
1881/**
1882 * qla2x00_init_response_q_entries() - Initializes response queue entries.
1883 * @ha: HA context
1884 *
1885 * Beginning of request ring has initialization control block already built
1886 * by nvram config routine.
1887 *
1888 * Returns 0 on success.
1889 */
73208dfd
AC		 1890void
1891qla2x00_init_response_q_entries(struct rsp_que *rsp)
1da177e4
LT		 1892{
1893 uint16_t cnt;
1894 response_t *pkt;
1895
2afa19a9
AC		 1896 rsp->ring_ptr = rsp->ring;
1897 rsp->ring_index = 0;
1898 rsp->status_srb = NULL;
e315cd28
AC		 1899 pkt = rsp->ring_ptr;
1900 for (cnt = 0; cnt < rsp->length; cnt++) {
1da177e4
LT		 1901 pkt->signature = RESPONSE_PROCESSED;
1902 pkt++;
1903 }
1da177e4
LT		 1904}
1905
1906/**
1907 * qla2x00_update_fw_options() - Read and process firmware options.
1908 * @ha: HA context
1909 *
1910 * Returns 0 on success.
1911 */
abbd8870 1912void
e315cd28 1913qla2x00_update_fw_options(scsi_qla_host_t *vha)
1da177e4
LT		 1914{
1915 uint16_t swing, emphasis, tx_sens, rx_sens;
e315cd28 1916 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 1917
1918 memset(ha->fw_options, 0, sizeof(ha->fw_options));
e315cd28 1919 qla2x00_get_fw_options(vha, ha->fw_options);
1da177e4
LT		 1920
1921 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1922 return;
1923
1924 /* Serial Link options. */
7c3df132
SK		 1925 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
1926 "Serial link options.\n");
1927 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
1928 (uint8_t *)&ha->fw_seriallink_options,
1929 sizeof(ha->fw_seriallink_options));
1da177e4
LT		 1930
1931 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1932 if (ha->fw_seriallink_options[3] & BIT_2) {
1933 ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING;
1934
1935 /* 1G settings */
1936 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
1937 emphasis = (ha->fw_seriallink_options[2] &
1938 (BIT_4 | BIT_3)) >> 3;
1939 tx_sens = ha->fw_seriallink_options[0] &
fa2a1ce5 1940 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 1941 rx_sens = (ha->fw_seriallink_options[0] &
1942 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
1943 ha->fw_options[10] = (emphasis << 14) | (swing << 8);
1944 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
1945 if (rx_sens == 0x0)
1946 rx_sens = 0x3;
1947 ha->fw_options[10] |= (tx_sens << 4) | rx_sens;
1948 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
1949 ha->fw_options[10] |= BIT_5 |
1950 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
1951 (tx_sens & (BIT_1 | BIT_0));
1952
1953 /* 2G settings */
1954 swing = (ha->fw_seriallink_options[2] &
1955 (BIT_7 | BIT_6 | BIT_5)) >> 5;
1956 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
1957 tx_sens = ha->fw_seriallink_options[1] &
fa2a1ce5 1958 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 1959 rx_sens = (ha->fw_seriallink_options[1] &
1960 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
1961 ha->fw_options[11] = (emphasis << 14) | (swing << 8);
1962 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
1963 if (rx_sens == 0x0)
1964 rx_sens = 0x3;
1965 ha->fw_options[11] |= (tx_sens << 4) | rx_sens;
1966 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
1967 ha->fw_options[11] |= BIT_5 |
1968 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
1969 (tx_sens & (BIT_1 | BIT_0));
1970 }
1971
1972 /* FCP2 options. */
1973 /* Return command IOCBs without waiting for an ABTS to complete. */
1974 ha->fw_options[3] |= BIT_13;
1975
1976 /* LED scheme. */
1977 if (ha->flags.enable_led_scheme)
1978 ha->fw_options[2] |= BIT_12;
1979
48c02fde
AV		 1980 /* Detect ISP6312. */
1981 if (IS_QLA6312(ha))
1982 ha->fw_options[2] |= BIT_13;
1983
1da177e4 1984 /* Update firmware options. */
e315cd28 1985 qla2x00_set_fw_options(vha, ha->fw_options);
1da177e4
LT		 1986}
1987
0107109e 1988void
e315cd28 1989qla24xx_update_fw_options(scsi_qla_host_t *vha)
0107109e
AV		 1990{
1991 int rval;
e315cd28 1992 struct qla_hw_data *ha = vha->hw;
0107109e 1993
7ec0effd 1994 if (IS_P3P_TYPE(ha))
a9083016
GM		 1995 return;
1996
0107109e 1997 /* Update Serial Link options. */
f94097ed 1998 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0)
0107109e
AV		 1999 return;
2000
e315cd28 2001 rval = qla2x00_set_serdes_params(vha,
f94097ed
AV		 2002 le16_to_cpu(ha->fw_seriallink_options24[1]),
2003 le16_to_cpu(ha->fw_seriallink_options24[2]),
2004 le16_to_cpu(ha->fw_seriallink_options24[3]));
0107109e 2005 if (rval != QLA_SUCCESS) {
7c3df132 2006 ql_log(ql_log_warn, vha, 0x0104,
0107109e
AV		 2007 "Unable to update Serial Link options (%x).\n", rval);
2008 }
2009}
2010
abbd8870 2011void
e315cd28 2012qla2x00_config_rings(struct scsi_qla_host *vha)
abbd8870 2013{
e315cd28 2014 struct qla_hw_data *ha = vha->hw;
3d71644c 2015 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
73208dfd
AC		 2016 struct req_que *req = ha->req_q_map[0];
2017 struct rsp_que *rsp = ha->rsp_q_map[0];
abbd8870
AV		 2018
2019 /* Setup ring parameters in initialization control block. */
2020 ha->init_cb->request_q_outpointer = __constant_cpu_to_le16(0);
2021 ha->init_cb->response_q_inpointer = __constant_cpu_to_le16(0);
e315cd28
AC		 2022 ha->init_cb->request_q_length = cpu_to_le16(req->length);
2023 ha->init_cb->response_q_length = cpu_to_le16(rsp->length);
2024 ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
2025 ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
2026 ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
2027 ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
abbd8870
AV		 2028
2029 WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0);
2030 WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0);
2031 WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0);
2032 WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0);
2033 RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */
2034}
2035
0107109e 2036void
e315cd28 2037qla24xx_config_rings(struct scsi_qla_host *vha)
0107109e 2038{
e315cd28 2039 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 2040 device_reg_t __iomem *reg = ISP_QUE_REG(ha, 0);
2041 struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
2042 struct qla_msix_entry *msix;
0107109e 2043 struct init_cb_24xx *icb;
73208dfd
AC		 2044 uint16_t rid = 0;
2045 struct req_que *req = ha->req_q_map[0];
2046 struct rsp_que *rsp = ha->rsp_q_map[0];
0107109e 2047
6246b8a1 2048 /* Setup ring parameters in initialization control block. */
0107109e
AV		 2049 icb = (struct init_cb_24xx *)ha->init_cb;
2050 icb->request_q_outpointer = __constant_cpu_to_le16(0);
2051 icb->response_q_inpointer = __constant_cpu_to_le16(0);
e315cd28
AC		 2052 icb->request_q_length = cpu_to_le16(req->length);
2053 icb->response_q_length = cpu_to_le16(rsp->length);
2054 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
2055 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
2056 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
2057 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
0107109e 2058
2d70c103
NB		 2059 /* Setup ATIO queue dma pointers for target mode */
2060 icb->atio_q_inpointer = __constant_cpu_to_le16(0);
2061 icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length);
2062 icb->atio_q_address[0] = cpu_to_le32(LSD(ha->tgt.atio_dma));
2063 icb->atio_q_address[1] = cpu_to_le32(MSD(ha->tgt.atio_dma));
2064
f73cb695 2065 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
73208dfd
AC		 2066 icb->qos = __constant_cpu_to_le16(QLA_DEFAULT_QUE_QOS);
2067 icb->rid = __constant_cpu_to_le16(rid);
2068 if (ha->flags.msix_enabled) {
2069 msix = &ha->msix_entries[1];
7c3df132
SK		 2070 ql_dbg(ql_dbg_init, vha, 0x00fd,
2071 "Registering vector 0x%x for base que.\n",
2072 msix->entry);
73208dfd
AC		 2073 icb->msix = cpu_to_le16(msix->entry);
2074 }
2075 /* Use alternate PCI bus number */
2076 if (MSB(rid))
2077 icb->firmware_options_2 |=
2078 __constant_cpu_to_le32(BIT_19);
2079 /* Use alternate PCI devfn */
2080 if (LSB(rid))
2081 icb->firmware_options_2 |=
2082 __constant_cpu_to_le32(BIT_18);
2083
3155754a 2084 /* Use Disable MSIX Handshake mode for capable adapters */
6246b8a1
GM		 2085 if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) &&
2086 (ha->flags.msix_enabled)) {
3155754a
AC		 2087 icb->firmware_options_2 &=
2088 __constant_cpu_to_le32(~BIT_22);
2089 ha->flags.disable_msix_handshake = 1;
7c3df132
SK		 2090 ql_dbg(ql_dbg_init, vha, 0x00fe,
2091 "MSIX Handshake Disable Mode turned on.\n");
3155754a
AC		 2092 } else {
2093 icb->firmware_options_2 |=
2094 __constant_cpu_to_le32(BIT_22);
2095 }
73208dfd 2096 icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_23);
73208dfd
AC		 2097
2098 WRT_REG_DWORD(&reg->isp25mq.req_q_in, 0);
2099 WRT_REG_DWORD(&reg->isp25mq.req_q_out, 0);
2100 WRT_REG_DWORD(&reg->isp25mq.rsp_q_in, 0);
2101 WRT_REG_DWORD(&reg->isp25mq.rsp_q_out, 0);
2102 } else {
2103 WRT_REG_DWORD(&reg->isp24.req_q_in, 0);
2104 WRT_REG_DWORD(&reg->isp24.req_q_out, 0);
2105 WRT_REG_DWORD(&reg->isp24.rsp_q_in, 0);
2106 WRT_REG_DWORD(&reg->isp24.rsp_q_out, 0);
2107 }
aa230bc5 2108 qlt_24xx_config_rings(vha);
2d70c103 2109
73208dfd
AC		 2110 /* PCI posting */
2111 RD_REG_DWORD(&ioreg->hccr);
0107109e
AV		 2112}
2113
1da177e4
LT		 2114/**
2115 * qla2x00_init_rings() - Initializes firmware.
2116 * @ha: HA context
2117 *
2118 * Beginning of request ring has initialization control block already built
2119 * by nvram config routine.
2120 *
2121 * Returns 0 on success.
2122 */
8ae6d9c7 2123int
e315cd28 2124qla2x00_init_rings(scsi_qla_host_t *vha)
1da177e4
LT		 2125{
2126 int rval;
2127 unsigned long flags = 0;
29bdccbe 2128 int cnt, que;
e315cd28 2129 struct qla_hw_data *ha = vha->hw;
29bdccbe
AC		 2130 struct req_que *req;
2131 struct rsp_que *rsp;
2c3dfe3f
SJ		 2132 struct mid_init_cb_24xx *mid_init_cb =
2133 (struct mid_init_cb_24xx *) ha->init_cb;
1da177e4
LT		 2134
2135 spin_lock_irqsave(&ha->hardware_lock, flags);
2136
2137 /* Clear outstanding commands array. */
2afa19a9 2138 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe
AC		 2139 req = ha->req_q_map[que];
2140 if (!req)
2141 continue;
8d93f550 2142 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++)
29bdccbe 2143 req->outstanding_cmds[cnt] = NULL;
1da177e4 2144
2afa19a9 2145 req->current_outstanding_cmd = 1;
1da177e4 2146
29bdccbe
AC		 2147 /* Initialize firmware. */
2148 req->ring_ptr = req->ring;
2149 req->ring_index = 0;
2150 req->cnt = req->length;
2151 }
1da177e4 2152
2afa19a9 2153 for (que = 0; que < ha->max_rsp_queues; que++) {
29bdccbe
AC		 2154 rsp = ha->rsp_q_map[que];
2155 if (!rsp)
2156 continue;
29bdccbe 2157 /* Initialize response queue entries */
8ae6d9c7
GM		 2158 if (IS_QLAFX00(ha))
2159 qlafx00_init_response_q_entries(rsp);
2160 else
2161 qla2x00_init_response_q_entries(rsp);
29bdccbe 2162 }
1da177e4 2163
2d70c103
NB		 2164 ha->tgt.atio_ring_ptr = ha->tgt.atio_ring;
2165 ha->tgt.atio_ring_index = 0;
2166 /* Initialize ATIO queue entries */
2167 qlt_init_atio_q_entries(vha);
2168
e315cd28 2169 ha->isp_ops->config_rings(vha);
1da177e4
LT		 2170
2171 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2172
8ae6d9c7
GM		 2173 ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n");
2174
2175 if (IS_QLAFX00(ha)) {
2176 rval = qlafx00_init_firmware(vha, ha->init_cb_size);
2177 goto next_check;
2178 }
2179
1da177e4 2180 /* Update any ISP specific firmware options before initialization. */
e315cd28 2181 ha->isp_ops->update_fw_options(vha);
1da177e4 2182
605aa2bc 2183 if (ha->flags.npiv_supported) {
45980cc2 2184 if (ha->operating_mode == LOOP && !IS_CNA_CAPABLE(ha))
605aa2bc 2185 ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
c48339de 2186 mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
605aa2bc
LC		 2187 }
2188
24a08138
AV		 2189 if (IS_FWI2_CAPABLE(ha)) {
2190 mid_init_cb->options = __constant_cpu_to_le16(BIT_1);
2191 mid_init_cb->init_cb.execution_throttle =
2192 cpu_to_le16(ha->fw_xcb_count);
2193 }
2c3dfe3f 2194
e315cd28 2195 rval = qla2x00_init_firmware(vha, ha->init_cb_size);
8ae6d9c7 2196next_check:
1da177e4 2197 if (rval) {
7c3df132
SK		 2198 ql_log(ql_log_fatal, vha, 0x00d2,
2199 "Init Firmware **** FAILED ****.\n");
1da177e4 2200 } else {
7c3df132
SK		 2201 ql_dbg(ql_dbg_init, vha, 0x00d3,
2202 "Init Firmware -- success.\n");
1da177e4
LT		 2203 }
2204
2205 return (rval);
2206}
2207
2208/**
2209 * qla2x00_fw_ready() - Waits for firmware ready.
2210 * @ha: HA context
2211 *
2212 * Returns 0 on success.
2213 */
2214static int
e315cd28 2215qla2x00_fw_ready(scsi_qla_host_t *vha)
1da177e4
LT		 2216{
2217 int rval;
4d4df193 2218 unsigned long wtime, mtime, cs84xx_time;
1da177e4
LT		 2219 uint16_t min_wait; /* Minimum wait time if loop is down */
2220 uint16_t wait_time; /* Wait time if loop is coming ready */
656e8912 2221 uint16_t state[5];
e315cd28 2222 struct qla_hw_data *ha = vha->hw;
1da177e4 2223
8ae6d9c7
GM		 2224 if (IS_QLAFX00(vha->hw))
2225 return qlafx00_fw_ready(vha);
2226
1da177e4
LT		 2227 rval = QLA_SUCCESS;
2228
2229 /* 20 seconds for loop down. */
fa2a1ce5 2230 min_wait = 20;
1da177e4
LT		 2231
2232 /*
2233 * Firmware should take at most one RATOV to login, plus 5 seconds for
2234 * our own processing.
2235 */
2236 if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) {
2237 wait_time = min_wait;
2238 }
2239
2240 /* Min wait time if loop down */
2241 mtime = jiffies + (min_wait * HZ);
2242
2243 /* wait time before firmware ready */
2244 wtime = jiffies + (wait_time * HZ);
2245
2246 /* Wait for ISP to finish LIP */
e315cd28 2247 if (!vha->flags.init_done)
7c3df132
SK		 2248 ql_log(ql_log_info, vha, 0x801e,
2249 "Waiting for LIP to complete.\n");
1da177e4
LT		 2250
2251 do {
5b939038 2252 memset(state, -1, sizeof(state));
e315cd28 2253 rval = qla2x00_get_firmware_state(vha, state);
1da177e4 2254 if (rval == QLA_SUCCESS) {
4d4df193 2255 if (state[0] < FSTATE_LOSS_OF_SYNC) {
e315cd28 2256 vha->device_flags &= ~DFLG_NO_CABLE;
1da177e4 2257 }
4d4df193 2258 if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) {
7c3df132
SK		 2259 ql_dbg(ql_dbg_taskm, vha, 0x801f,
2260 "fw_state=%x 84xx=%x.\n", state[0],
2261 state[2]);
4d4df193
HK		 2262 if ((state[2] & FSTATE_LOGGED_IN) &&
2263 (state[2] & FSTATE_WAITING_FOR_VERIFY)) {
7c3df132
SK		 2264 ql_dbg(ql_dbg_taskm, vha, 0x8028,
2265 "Sending verify iocb.\n");
4d4df193
HK		 2266
2267 cs84xx_time = jiffies;
e315cd28 2268 rval = qla84xx_init_chip(vha);
7c3df132
SK		 2269 if (rval != QLA_SUCCESS) {
2270 ql_log(ql_log_warn,
cfb0919c 2271 vha, 0x8007,
7c3df132 2272 "Init chip failed.\n");
4d4df193 2273 break;
7c3df132 2274 }
4d4df193
HK		 2275
2276 /* Add time taken to initialize. */
2277 cs84xx_time = jiffies - cs84xx_time;
2278 wtime += cs84xx_time;
2279 mtime += cs84xx_time;
cfb0919c 2280 ql_dbg(ql_dbg_taskm, vha, 0x8008,
7c3df132
SK		 2281 "Increasing wait time by %ld. "
2282 "New time %ld.\n", cs84xx_time,
2283 wtime);
4d4df193
HK		 2284 }
2285 } else if (state[0] == FSTATE_READY) {
7c3df132
SK		 2286 ql_dbg(ql_dbg_taskm, vha, 0x8037,
2287 "F/W Ready - OK.\n");
1da177e4 2288
e315cd28 2289 qla2x00_get_retry_cnt(vha, &ha->retry_count,
1da177e4
LT		 2290 &ha->login_timeout, &ha->r_a_tov);
2291
2292 rval = QLA_SUCCESS;
2293 break;
2294 }
2295
2296 rval = QLA_FUNCTION_FAILED;
2297
e315cd28 2298 if (atomic_read(&vha->loop_down_timer) &&
4d4df193 2299 state[0] != FSTATE_READY) {
1da177e4 2300 /* Loop down. Timeout on min_wait for states
fa2a1ce5
AV		 2301 * other than Wait for Login.
2302 */
1da177e4 2303 if (time_after_eq(jiffies, mtime)) {
7c3df132 2304 ql_log(ql_log_info, vha, 0x8038,
1da177e4
LT		 2305 "Cable is unplugged...\n");
2306
e315cd28 2307 vha->device_flags |= DFLG_NO_CABLE;
1da177e4
LT		 2308 break;
2309 }
2310 }
2311 } else {
2312 /* Mailbox cmd failed. Timeout on min_wait. */
cdbb0a4f 2313 if (time_after_eq(jiffies, mtime) ||
7190575f 2314 ha->flags.isp82xx_fw_hung)
1da177e4
LT		 2315 break;
2316 }
2317
2318 if (time_after_eq(jiffies, wtime))
2319 break;
2320
2321 /* Delay for a while */
2322 msleep(500);
1da177e4
LT		 2323 } while (1);
2324
7c3df132
SK		 2325 ql_dbg(ql_dbg_taskm, vha, 0x803a,
2326 "fw_state=%x (%x, %x, %x, %x) " "curr time=%lx.\n", state[0],
2327 state[1], state[2], state[3], state[4], jiffies);
1da177e4 2328
cfb0919c 2329 if (rval && !(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132
SK		 2330 ql_log(ql_log_warn, vha, 0x803b,
2331 "Firmware ready **** FAILED ****.\n");
1da177e4
LT		 2332 }
2333
2334 return (rval);
2335}
2336
2337/*
2338* qla2x00_configure_hba
2339* Setup adapter context.
2340*
2341* Input:
2342* ha = adapter state pointer.
2343*
2344* Returns:
2345* 0 = success
2346*
2347* Context:
2348* Kernel context.
2349*/
2350static int
e315cd28 2351qla2x00_configure_hba(scsi_qla_host_t *vha)
1da177e4
LT		 2352{
2353 int rval;
2354 uint16_t loop_id;
2355 uint16_t topo;
2c3dfe3f 2356 uint16_t sw_cap;
1da177e4
LT		 2357 uint8_t al_pa;
2358 uint8_t area;
2359 uint8_t domain;
2360 char connect_type[22];
e315cd28 2361 struct qla_hw_data *ha = vha->hw;
f24b5cb8 2362 unsigned long flags;
61e1b269 2363 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 2364
2365 /* Get host addresses. */
e315cd28 2366 rval = qla2x00_get_adapter_id(vha,
2c3dfe3f 2367 &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
1da177e4 2368 if (rval != QLA_SUCCESS) {
e315cd28 2369 if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
6246b8a1 2370 IS_CNA_CAPABLE(ha) ||
33135aa2 2371 (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
7c3df132
SK		 2372 ql_dbg(ql_dbg_disc, vha, 0x2008,
2373 "Loop is in a transition state.\n");
33135aa2 2374 } else {
7c3df132
SK		 2375 ql_log(ql_log_warn, vha, 0x2009,
2376 "Unable to get host loop ID.\n");
61e1b269
JC		 2377 if (IS_FWI2_CAPABLE(ha) && (vha == base_vha) &&
2378 (rval == QLA_COMMAND_ERROR && loop_id == 0x1b)) {
2379 ql_log(ql_log_warn, vha, 0x1151,
2380 "Doing link init.\n");
2381 if (qla24xx_link_initialize(vha) == QLA_SUCCESS)
2382 return rval;
2383 }
e315cd28 2384 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
33135aa2 2385 }
1da177e4
LT		 2386 return (rval);
2387 }
2388
2389 if (topo == 4) {
7c3df132
SK		 2390 ql_log(ql_log_info, vha, 0x200a,
2391 "Cannot get topology - retrying.\n");
1da177e4
LT		 2392 return (QLA_FUNCTION_FAILED);
2393 }
2394
e315cd28 2395 vha->loop_id = loop_id;
1da177e4
LT		 2396
2397 /* initialize */
2398 ha->min_external_loopid = SNS_FIRST_LOOP_ID;
2399 ha->operating_mode = LOOP;
2c3dfe3f 2400 ha->switch_cap = 0;
1da177e4
LT		 2401
2402 switch (topo) {
2403 case 0:
7c3df132 2404 ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n");
1da177e4
LT		 2405 ha->current_topology = ISP_CFG_NL;
2406 strcpy(connect_type, "(Loop)");
2407 break;
2408
2409 case 1:
7c3df132 2410 ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n");
2c3dfe3f 2411 ha->switch_cap = sw_cap;
1da177e4
LT		 2412 ha->current_topology = ISP_CFG_FL;
2413 strcpy(connect_type, "(FL_Port)");
2414 break;
2415
2416 case 2:
7c3df132 2417 ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n");
1da177e4
LT		 2418 ha->operating_mode = P2P;
2419 ha->current_topology = ISP_CFG_N;
2420 strcpy(connect_type, "(N_Port-to-N_Port)");
2421 break;
2422
2423 case 3:
7c3df132 2424 ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n");
2c3dfe3f 2425 ha->switch_cap = sw_cap;
1da177e4
LT		 2426 ha->operating_mode = P2P;
2427 ha->current_topology = ISP_CFG_F;
2428 strcpy(connect_type, "(F_Port)");
2429 break;
2430
2431 default:
7c3df132
SK		 2432 ql_dbg(ql_dbg_disc, vha, 0x200f,
2433 "HBA in unknown topology %x, using NL.\n", topo);
1da177e4
LT		 2434 ha->current_topology = ISP_CFG_NL;
2435 strcpy(connect_type, "(Loop)");
2436 break;
2437 }
2438
2439 /* Save Host port and loop ID. */
2440 /* byte order - Big Endian */
e315cd28
AC		 2441 vha->d_id.b.domain = domain;
2442 vha->d_id.b.area = area;
2443 vha->d_id.b.al_pa = al_pa;
1da177e4 2444
f24b5cb8 2445 spin_lock_irqsave(&ha->vport_slock, flags);
2d70c103 2446 qlt_update_vp_map(vha, SET_AL_PA);
f24b5cb8 2447 spin_unlock_irqrestore(&ha->vport_slock, flags);
2d70c103 2448
e315cd28 2449 if (!vha->flags.init_done)
7c3df132
SK		 2450 ql_log(ql_log_info, vha, 0x2010,
2451 "Topology - %s, Host Loop address 0x%x.\n",
e315cd28 2452 connect_type, vha->loop_id);
1da177e4 2453
1da177e4
LT		 2454 return(rval);
2455}
2456
a9083016 2457inline void
e315cd28
AC		 2458qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
2459 char *def)
9bb9fcf2
AV		 2460{
2461 char *st, *en;
2462 uint16_t index;
e315cd28 2463 struct qla_hw_data *ha = vha->hw;
ab671149 2464 int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
6246b8a1 2465 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha);
9bb9fcf2
AV		 2466
2467 if (memcmp(model, BINZERO, len) != 0) {
2468 strncpy(ha->model_number, model, len);
2469 st = en = ha->model_number;
2470 en += len - 1;
2471 while (en > st) {
2472 if (*en != 0x20 && *en != 0x00)
2473 break;
2474 *en-- = '\0';
2475 }
2476
2477 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 2478 if (use_tbl &&
2479 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2 2480 index < QLA_MODEL_NAMES)
1ee27146
JC		 2481 strncpy(ha->model_desc,
2482 qla2x00_model_name[index * 2 + 1],
2483 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 2484 } else {
2485 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 2486 if (use_tbl &&
2487 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2
AV		 2488 index < QLA_MODEL_NAMES) {
2489 strcpy(ha->model_number,
2490 qla2x00_model_name[index * 2]);
1ee27146
JC		 2491 strncpy(ha->model_desc,
2492 qla2x00_model_name[index * 2 + 1],
2493 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 2494 } else {
2495 strcpy(ha->model_number, def);
2496 }
2497 }
1ee27146 2498 if (IS_FWI2_CAPABLE(ha))
e315cd28 2499 qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc,
1ee27146 2500 sizeof(ha->model_desc));
9bb9fcf2
AV		 2501}
2502
4e08df3f
DM		 2503/* On sparc systems, obtain port and node WWN from firmware
2504 * properties.
2505 */
e315cd28 2506static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv)
4e08df3f
DM		 2507{
2508#ifdef CONFIG_SPARC
e315cd28 2509 struct qla_hw_data *ha = vha->hw;
4e08df3f 2510 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 2511 struct device_node *dp = pci_device_to_OF_node(pdev);
2512 const u8 *val;
4e08df3f
DM		 2513 int len;
2514
2515 val = of_get_property(dp, "port-wwn", &len);
2516 if (val && len >= WWN_SIZE)
2517 memcpy(nv->port_name, val, WWN_SIZE);
2518
2519 val = of_get_property(dp, "node-wwn", &len);
2520 if (val && len >= WWN_SIZE)
2521 memcpy(nv->node_name, val, WWN_SIZE);
2522#endif
2523}
2524
1da177e4
LT		 2525/*
2526* NVRAM configuration for ISP 2xxx
2527*
2528* Input:
2529* ha = adapter block pointer.
2530*
2531* Output:
2532* initialization control block in response_ring
2533* host adapters parameters in host adapter block
2534*
2535* Returns:
2536* 0 = success.
2537*/
abbd8870 2538int
e315cd28 2539qla2x00_nvram_config(scsi_qla_host_t *vha)
1da177e4 2540{
4e08df3f 2541 int rval;
0107109e
AV		 2542 uint8_t chksum = 0;
2543 uint16_t cnt;
2544 uint8_t *dptr1, *dptr2;
e315cd28 2545 struct qla_hw_data *ha = vha->hw;
0107109e 2546 init_cb_t *icb = ha->init_cb;
281afe19
SJ		 2547 nvram_t *nv = ha->nvram;
2548 uint8_t *ptr = ha->nvram;
3d71644c 2549 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 2550
4e08df3f
DM		 2551 rval = QLA_SUCCESS;
2552
1da177e4 2553 /* Determine NVRAM starting address. */
0107109e 2554 ha->nvram_size = sizeof(nvram_t);
1da177e4
LT		 2555 ha->nvram_base = 0;
2556 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
2557 if ((RD_REG_WORD(&reg->ctrl_status) >> 14) == 1)
2558 ha->nvram_base = 0x80;
2559
2560 /* Get NVRAM data and calculate checksum. */
e315cd28 2561 ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size);
0107109e
AV		 2562 for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++)
2563 chksum += *ptr++;
1da177e4 2564
7c3df132
SK		 2565 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
2566 "Contents of NVRAM.\n");
2567 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
2568 (uint8_t *)nv, ha->nvram_size);
1da177e4
LT		 2569
2570 /* Bad NVRAM data, set defaults parameters. */
2571 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' ||
2572 nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) {
2573 /* Reset NVRAM data. */
7c3df132 2574 ql_log(ql_log_warn, vha, 0x0064,
9e336520 2575 "Inconsistent NVRAM "
7c3df132
SK		 2576 "detected: checksum=0x%x id=%c version=0x%x.\n",
2577 chksum, nv->id[0], nv->nvram_version);
2578 ql_log(ql_log_warn, vha, 0x0065,
2579 "Falling back to "
2580 "functioning (yet invalid -- WWPN) defaults.\n");
4e08df3f
DM		 2581
2582 /*
2583 * Set default initialization control block.
2584 */
2585 memset(nv, 0, ha->nvram_size);
2586 nv->parameter_block_version = ICB_VERSION;
2587
2588 if (IS_QLA23XX(ha)) {
2589 nv->firmware_options[0] = BIT_2 | BIT_1;
2590 nv->firmware_options[1] = BIT_7 | BIT_5;
2591 nv->add_firmware_options[0] = BIT_5;
2592 nv->add_firmware_options[1] = BIT_5 | BIT_4;
2593 nv->frame_payload_size = __constant_cpu_to_le16(2048);
2594 nv->special_options[1] = BIT_7;
2595 } else if (IS_QLA2200(ha)) {
2596 nv->firmware_options[0] = BIT_2 | BIT_1;
2597 nv->firmware_options[1] = BIT_7 | BIT_5;
2598 nv->add_firmware_options[0] = BIT_5;
2599 nv->add_firmware_options[1] = BIT_5 | BIT_4;
2600 nv->frame_payload_size = __constant_cpu_to_le16(1024);
2601 } else if (IS_QLA2100(ha)) {
2602 nv->firmware_options[0] = BIT_3 | BIT_1;
2603 nv->firmware_options[1] = BIT_5;
2604 nv->frame_payload_size = __constant_cpu_to_le16(1024);
2605 }
2606
2607 nv->max_iocb_allocation = __constant_cpu_to_le16(256);
2608 nv->execution_throttle = __constant_cpu_to_le16(16);
2609 nv->retry_count = 8;
2610 nv->retry_delay = 1;
2611
2612 nv->port_name[0] = 33;
2613 nv->port_name[3] = 224;
2614 nv->port_name[4] = 139;
2615
e315cd28 2616 qla2xxx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 2617
2618 nv->login_timeout = 4;
2619
2620 /*
2621 * Set default host adapter parameters
2622 */
2623 nv->host_p[1] = BIT_2;
2624 nv->reset_delay = 5;
2625 nv->port_down_retry_count = 8;
2626 nv->max_luns_per_target = __constant_cpu_to_le16(8);
2627 nv->link_down_timeout = 60;
2628
2629 rval = 1;
1da177e4
LT		 2630 }
2631
2632#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
2633 /*
2634 * The SN2 does not provide BIOS emulation which means you can't change
2635 * potentially bogus BIOS settings. Force the use of default settings
2636 * for link rate and frame size. Hope that the rest of the settings
2637 * are valid.
2638 */
2639 if (ia64_platform_is("sn2")) {
2640 nv->frame_payload_size = __constant_cpu_to_le16(2048);
2641 if (IS_QLA23XX(ha))
2642 nv->special_options[1] = BIT_7;
2643 }
2644#endif
2645
2646 /* Reset Initialization control block */
0107109e 2647 memset(icb, 0, ha->init_cb_size);
1da177e4
LT		 2648
2649 /*
2650 * Setup driver NVRAM options.
2651 */
2652 nv->firmware_options[0] |= (BIT_6 | BIT_1);
2653 nv->firmware_options[0] &= ~(BIT_5 | BIT_4);
2654 nv->firmware_options[1] |= (BIT_5 | BIT_0);
2655 nv->firmware_options[1] &= ~BIT_4;
2656
2657 if (IS_QLA23XX(ha)) {
2658 nv->firmware_options[0] |= BIT_2;
2659 nv->firmware_options[0] &= ~BIT_3;
2d70c103 2660 nv->special_options[0] &= ~BIT_6;
0107109e 2661 nv->add_firmware_options[1] |= BIT_5 | BIT_4;
1da177e4
LT		 2662
2663 if (IS_QLA2300(ha)) {
2664 if (ha->fb_rev == FPM_2310) {
2665 strcpy(ha->model_number, "QLA2310");
2666 } else {
2667 strcpy(ha->model_number, "QLA2300");
2668 }
2669 } else {
e315cd28 2670 qla2x00_set_model_info(vha, nv->model_number,
9bb9fcf2 2671 sizeof(nv->model_number), "QLA23xx");
1da177e4
LT		 2672 }
2673 } else if (IS_QLA2200(ha)) {
2674 nv->firmware_options[0] |= BIT_2;
2675 /*
2676 * 'Point-to-point preferred, else loop' is not a safe
2677 * connection mode setting.
2678 */
2679 if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
2680 (BIT_5 | BIT_4)) {
2681 /* Force 'loop preferred, else point-to-point'. */
2682 nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
2683 nv->add_firmware_options[0] |= BIT_5;
2684 }
2685 strcpy(ha->model_number, "QLA22xx");
2686 } else /*if (IS_QLA2100(ha))*/ {
2687 strcpy(ha->model_number, "QLA2100");
2688 }
2689
2690 /*
2691 * Copy over NVRAM RISC parameter block to initialization control block.
2692 */
2693 dptr1 = (uint8_t *)icb;
2694 dptr2 = (uint8_t *)&nv->parameter_block_version;
2695 cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;
2696 while (cnt--)
2697 *dptr1++ = *dptr2++;
2698
2699 /* Copy 2nd half. */
2700 dptr1 = (uint8_t *)icb->add_firmware_options;
2701 cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;
2702 while (cnt--)
2703 *dptr1++ = *dptr2++;
2704
5341e868
AV		 2705 /* Use alternate WWN? */
2706 if (nv->host_p[1] & BIT_7) {
2707 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
2708 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
2709 }
2710
1da177e4
LT		 2711 /* Prepare nodename */
2712 if ((icb->firmware_options[1] & BIT_6) == 0) {
2713 /*
2714 * Firmware will apply the following mask if the nodename was
2715 * not provided.
2716 */
2717 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
2718 icb->node_name[0] &= 0xF0;
2719 }
2720
2721 /*
2722 * Set host adapter parameters.
2723 */
3ce8866c
SK		 2724
2725 /*
2726 * BIT_7 in the host-parameters section allows for modification to
2727 * internal driver logging.
2728 */
0181944f 2729 if (nv->host_p[0] & BIT_7)
cfb0919c 2730 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
1da177e4
LT		 2731 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
2732 /* Always load RISC code on non ISP2[12]00 chips. */
2733 if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
2734 ha->flags.disable_risc_code_load = 0;
2735 ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0);
2736 ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
2737 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
06c22bd1 2738 ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
d4c760c2 2739 ha->flags.disable_serdes = 0;
1da177e4
LT		 2740
2741 ha->operating_mode =
2742 (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
2743
2744 memcpy(ha->fw_seriallink_options, nv->seriallink_options,
2745 sizeof(ha->fw_seriallink_options));
2746
2747 /* save HBA serial number */
2748 ha->serial0 = icb->port_name[5];
2749 ha->serial1 = icb->port_name[6];
2750 ha->serial2 = icb->port_name[7];
e315cd28
AC		 2751 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
2752 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
1da177e4
LT		 2753
2754 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
2755
2756 ha->retry_count = nv->retry_count;
2757
2758 /* Set minimum login_timeout to 4 seconds. */
5b91490e 2759 if (nv->login_timeout != ql2xlogintimeout)
1da177e4
LT		 2760 nv->login_timeout = ql2xlogintimeout;
2761 if (nv->login_timeout < 4)
2762 nv->login_timeout = 4;
2763 ha->login_timeout = nv->login_timeout;
2764 icb->login_timeout = nv->login_timeout;
2765
00a537b8
AV		 2766 /* Set minimum RATOV to 100 tenths of a second. */
2767 ha->r_a_tov = 100;
1da177e4 2768
1da177e4
LT		 2769 ha->loop_reset_delay = nv->reset_delay;
2770
1da177e4
LT		 2771 /* Link Down Timeout = 0:
2772 *
2773 * When Port Down timer expires we will start returning
2774 * I/O's to OS with "DID_NO_CONNECT".
2775 *
2776 * Link Down Timeout != 0:
2777 *
2778 * The driver waits for the link to come up after link down
2779 * before returning I/Os to OS with "DID_NO_CONNECT".
fa2a1ce5 2780 */
1da177e4
LT		 2781 if (nv->link_down_timeout == 0) {
2782 ha->loop_down_abort_time =
354d6b21 2783 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
1da177e4
LT		 2784 } else {
2785 ha->link_down_timeout = nv->link_down_timeout;
2786 ha->loop_down_abort_time =
2787 (LOOP_DOWN_TIME - ha->link_down_timeout);
fa2a1ce5 2788 }
1da177e4 2789
1da177e4
LT		 2790 /*
2791 * Need enough time to try and get the port back.
2792 */
2793 ha->port_down_retry_count = nv->port_down_retry_count;
2794 if (qlport_down_retry)
2795 ha->port_down_retry_count = qlport_down_retry;
2796 /* Set login_retry_count */
2797 ha->login_retry_count = nv->retry_count;
2798 if (ha->port_down_retry_count == nv->port_down_retry_count &&
2799 ha->port_down_retry_count > 3)
2800 ha->login_retry_count = ha->port_down_retry_count;
2801 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
2802 ha->login_retry_count = ha->port_down_retry_count;
2803 if (ql2xloginretrycount)
2804 ha->login_retry_count = ql2xloginretrycount;
2805
1da177e4
LT		 2806 icb->lun_enables = __constant_cpu_to_le16(0);
2807 icb->command_resource_count = 0;
2808 icb->immediate_notify_resource_count = 0;
2809 icb->timeout = __constant_cpu_to_le16(0);
2810
2811 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
2812 /* Enable RIO */
2813 icb->firmware_options[0] &= ~BIT_3;
2814 icb->add_firmware_options[0] &=
2815 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
2816 icb->add_firmware_options[0] |= BIT_2;
2817 icb->response_accumulation_timer = 3;
2818 icb->interrupt_delay_timer = 5;
2819
e315cd28 2820 vha->flags.process_response_queue = 1;
1da177e4 2821 } else {
4fdfefe5 2822 /* Enable ZIO. */
e315cd28 2823 if (!vha->flags.init_done) {
4fdfefe5
AV		 2824 ha->zio_mode = icb->add_firmware_options[0] &
2825 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
2826 ha->zio_timer = icb->interrupt_delay_timer ?
2827 icb->interrupt_delay_timer: 2;
2828 }
1da177e4
LT		 2829 icb->add_firmware_options[0] &=
2830 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
e315cd28 2831 vha->flags.process_response_queue = 0;
4fdfefe5 2832 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d
AV		 2833 ha->zio_mode = QLA_ZIO_MODE_6;
2834
7c3df132 2835 ql_log(ql_log_info, vha, 0x0068,
4fdfefe5
AV		 2836 "ZIO mode %d enabled; timer delay (%d us).\n",
2837 ha->zio_mode, ha->zio_timer * 100);
1da177e4 2838
4fdfefe5
AV		 2839 icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;
2840 icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;
e315cd28 2841 vha->flags.process_response_queue = 1;
1da177e4
LT		 2842 }
2843 }
2844
4e08df3f 2845 if (rval) {
7c3df132
SK		 2846 ql_log(ql_log_warn, vha, 0x0069,
2847 "NVRAM configuration failed.\n");
4e08df3f
DM		 2848 }
2849 return (rval);
1da177e4
LT		 2850}
2851
19a7b4ae
JSEC		 2852static void
2853qla2x00_rport_del(void *data)
2854{
2855 fc_port_t *fcport = data;
d97994dc 2856 struct fc_rport *rport;
2d70c103 2857 scsi_qla_host_t *vha = fcport->vha;
044d78e1 2858 unsigned long flags;
d97994dc 2859
044d78e1 2860 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
ac280b67 2861 rport = fcport->drport ? fcport->drport: fcport->rport;
d97994dc 2862 fcport->drport = NULL;
044d78e1 2863 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
2d70c103 2864 if (rport) {
d97994dc 2865 fc_remote_port_delete(rport);
2d70c103
NB		 2866 /*
2867 * Release the target mode FC NEXUS in qla_target.c code
2868 * if target mod is enabled.
2869 */
2870 qlt_fc_port_deleted(vha, fcport);
2871 }
19a7b4ae
JSEC		 2872}
2873
1da177e4
LT		 2874/**
2875 * qla2x00_alloc_fcport() - Allocate a generic fcport.
2876 * @ha: HA context
2877 * @flags: allocation flags
2878 *
2879 * Returns a pointer to the allocated fcport, or NULL, if none available.
2880 */
9a069e19 2881fc_port_t *
e315cd28 2882qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags)
1da177e4
LT		 2883{
2884 fc_port_t *fcport;
2885
bbfbbbc1
MK		 2886 fcport = kzalloc(sizeof(fc_port_t), flags);
2887 if (!fcport)
2888 return NULL;
1da177e4
LT		 2889
2890 /* Setup fcport template structure. */
e315cd28 2891 fcport->vha = vha;
1da177e4
LT		 2892 fcport->port_type = FCT_UNKNOWN;
2893 fcport->loop_id = FC_NO_LOOP_ID;
ec426e10 2894 qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
ad3e0eda 2895 fcport->supported_classes = FC_COS_UNSPECIFIED;
1da177e4 2896
bbfbbbc1 2897 return fcport;
1da177e4
LT		 2898}
2899
2900/*
2901 * qla2x00_configure_loop
2902 * Updates Fibre Channel Device Database with what is actually on loop.
2903 *
2904 * Input:
2905 * ha = adapter block pointer.
2906 *
2907 * Returns:
2908 * 0 = success.
2909 * 1 = error.
2910 * 2 = database was full and device was not configured.
2911 */
2912static int
e315cd28 2913qla2x00_configure_loop(scsi_qla_host_t *vha)
1da177e4
LT		 2914{
2915 int rval;
2916 unsigned long flags, save_flags;
e315cd28 2917 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2918 rval = QLA_SUCCESS;
2919
2920 /* Get Initiator ID */
e315cd28
AC		 2921 if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) {
2922 rval = qla2x00_configure_hba(vha);
1da177e4 2923 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2924 ql_dbg(ql_dbg_disc, vha, 0x2013,
2925 "Unable to configure HBA.\n");
1da177e4
LT		 2926 return (rval);
2927 }
2928 }
2929
e315cd28 2930 save_flags = flags = vha->dpc_flags;
7c3df132
SK		 2931 ql_dbg(ql_dbg_disc, vha, 0x2014,
2932 "Configure loop -- dpc flags = 0x%lx.\n", flags);
1da177e4
LT		 2933
2934 /*
2935 * If we have both an RSCN and PORT UPDATE pending then handle them
2936 * both at the same time.
2937 */
e315cd28
AC		 2938 clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2939 clear_bit(RSCN_UPDATE, &vha->dpc_flags);
1da177e4 2940
3064ff39
MH		 2941 qla2x00_get_data_rate(vha);
2942
1da177e4
LT		 2943 /* Determine what we need to do */
2944 if (ha->current_topology == ISP_CFG_FL &&
2945 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
2946
1da177e4
LT		 2947 set_bit(RSCN_UPDATE, &flags);
2948
2949 } else if (ha->current_topology == ISP_CFG_F &&
2950 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
2951
1da177e4
LT		 2952 set_bit(RSCN_UPDATE, &flags);
2953 clear_bit(LOCAL_LOOP_UPDATE, &flags);
21333b48
AV		 2954
2955 } else if (ha->current_topology == ISP_CFG_N) {
2956 clear_bit(RSCN_UPDATE, &flags);
1da177e4 2957
e315cd28 2958 } else if (!vha->flags.online ||
1da177e4
LT		 2959 (test_bit(ABORT_ISP_ACTIVE, &flags))) {
2960
1da177e4
LT		 2961 set_bit(RSCN_UPDATE, &flags);
2962 set_bit(LOCAL_LOOP_UPDATE, &flags);
2963 }
2964
2965 if (test_bit(LOCAL_LOOP_UPDATE, &flags)) {
7c3df132
SK		 2966 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
2967 ql_dbg(ql_dbg_disc, vha, 0x2015,
2968 "Loop resync needed, failing.\n");
1da177e4 2969 rval = QLA_FUNCTION_FAILED;
642ef983 2970 } else
e315cd28 2971 rval = qla2x00_configure_local_loop(vha);
1da177e4
LT		 2972 }
2973
2974 if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
7c3df132
SK		 2975 if (LOOP_TRANSITION(vha)) {
2976 ql_dbg(ql_dbg_disc, vha, 0x201e,
2977 "Needs RSCN update and loop transition.\n");
1da177e4 2978 rval = QLA_FUNCTION_FAILED;
7c3df132 2979 }
e315cd28
AC		 2980 else
2981 rval = qla2x00_configure_fabric(vha);
1da177e4
LT		 2982 }
2983
2984 if (rval == QLA_SUCCESS) {
e315cd28
AC		 2985 if (atomic_read(&vha->loop_down_timer) ||
2986 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4
LT		 2987 rval = QLA_FUNCTION_FAILED;
2988 } else {
e315cd28 2989 atomic_set(&vha->loop_state, LOOP_READY);
7c3df132
SK		 2990 ql_dbg(ql_dbg_disc, vha, 0x2069,
2991 "LOOP READY.\n");
1da177e4
LT		 2992 }
2993 }
2994
2995 if (rval) {
7c3df132
SK		 2996 ql_dbg(ql_dbg_disc, vha, 0x206a,
2997 "%s *** FAILED ***.\n", __func__);
1da177e4 2998 } else {
7c3df132
SK		 2999 ql_dbg(ql_dbg_disc, vha, 0x206b,
3000 "%s: exiting normally.\n", __func__);
1da177e4
LT		 3001 }
3002
cc3ef7bc 3003 /* Restore state if a resync event occurred during processing */
e315cd28 3004 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4 3005 if (test_bit(LOCAL_LOOP_UPDATE, &save_flags))
e315cd28 3006 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
f4658b6c 3007 if (test_bit(RSCN_UPDATE, &save_flags)) {
e315cd28 3008 set_bit(RSCN_UPDATE, &vha->dpc_flags);
f4658b6c 3009 }
1da177e4
LT		 3010 }
3011
3012 return (rval);
3013}
3014
3015
3016
3017/*
3018 * qla2x00_configure_local_loop
3019 * Updates Fibre Channel Device Database with local loop devices.
3020 *
3021 * Input:
3022 * ha = adapter block pointer.
3023 *
3024 * Returns:
3025 * 0 = success.
3026 */
3027static int
e315cd28 3028qla2x00_configure_local_loop(scsi_qla_host_t *vha)
1da177e4
LT		 3029{
3030 int rval, rval2;
3031 int found_devs;
3032 int found;
3033 fc_port_t *fcport, *new_fcport;
3034
3035 uint16_t index;
3036 uint16_t entries;
3037 char *id_iter;
3038 uint16_t loop_id;
3039 uint8_t domain, area, al_pa;
e315cd28 3040 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3041
3042 found_devs = 0;
3043 new_fcport = NULL;
642ef983 3044 entries = MAX_FIBRE_DEVICES_LOOP;
1da177e4 3045
1da177e4 3046 /* Get list of logged in devices. */
642ef983 3047 memset(ha->gid_list, 0, qla2x00_gid_list_size(ha));
e315cd28 3048 rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma,
1da177e4
LT		 3049 &entries);
3050 if (rval != QLA_SUCCESS)
3051 goto cleanup_allocation;
3052
7c3df132
SK		 3053 ql_dbg(ql_dbg_disc, vha, 0x2017,
3054 "Entries in ID list (%d).\n", entries);
3055 ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
3056 (uint8_t *)ha->gid_list,
3057 entries * sizeof(struct gid_list_info));
1da177e4
LT		 3058
3059 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 3060 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3061 if (new_fcport == NULL) {
7c3df132
SK		 3062 ql_log(ql_log_warn, vha, 0x2018,
3063 "Memory allocation failed for fcport.\n");
1da177e4
LT		 3064 rval = QLA_MEMORY_ALLOC_FAILED;
3065 goto cleanup_allocation;
3066 }
3067 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
3068
3069 /*
3070 * Mark local devices that were present with FCF_DEVICE_LOST for now.
3071 */
e315cd28 3072 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 3073 if (atomic_read(&fcport->state) == FCS_ONLINE &&
3074 fcport->port_type != FCT_BROADCAST &&
3075 (fcport->flags & FCF_FABRIC_DEVICE) == 0) {
3076
7c3df132
SK		 3077 ql_dbg(ql_dbg_disc, vha, 0x2019,
3078 "Marking port lost loop_id=0x%04x.\n",
3079 fcport->loop_id);
1da177e4 3080
ec426e10 3081 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3082 }
3083 }
3084
3085 /* Add devices to port list. */
3086 id_iter = (char *)ha->gid_list;
3087 for (index = 0; index < entries; index++) {
3088 domain = ((struct gid_list_info *)id_iter)->domain;
3089 area = ((struct gid_list_info *)id_iter)->area;
3090 al_pa = ((struct gid_list_info *)id_iter)->al_pa;
abbd8870 3091 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1da177e4
LT		 3092 loop_id = (uint16_t)
3093 ((struct gid_list_info *)id_iter)->loop_id_2100;
abbd8870 3094 else
1da177e4
LT		 3095 loop_id = le16_to_cpu(
3096 ((struct gid_list_info *)id_iter)->loop_id);
abbd8870 3097 id_iter += ha->gid_list_info_size;
1da177e4
LT		 3098
3099 /* Bypass reserved domain fields. */
3100 if ((domain & 0xf0) == 0xf0)
3101 continue;
3102
3103 /* Bypass if not same domain and area of adapter. */
f7d289f6 3104 if (area && domain &&
e315cd28 3105 (area != vha->d_id.b.area || domain != vha->d_id.b.domain))
1da177e4
LT		 3106 continue;
3107
3108 /* Bypass invalid local loop ID. */
3109 if (loop_id > LAST_LOCAL_LOOP_ID)
3110 continue;
3111
370d550e
AE		 3112 memset(new_fcport, 0, sizeof(fc_port_t));
3113
1da177e4
LT		 3114 /* Fill in member data. */
3115 new_fcport->d_id.b.domain = domain;
3116 new_fcport->d_id.b.area = area;
3117 new_fcport->d_id.b.al_pa = al_pa;
3118 new_fcport->loop_id = loop_id;
e315cd28 3119 rval2 = qla2x00_get_port_database(vha, new_fcport, 0);
1da177e4 3120 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 3121 ql_dbg(ql_dbg_disc, vha, 0x201a,
3122 "Failed to retrieve fcport information "
3123 "-- get_port_database=%x, loop_id=0x%04x.\n",
3124 rval2, new_fcport->loop_id);
3125 ql_dbg(ql_dbg_disc, vha, 0x201b,
3126 "Scheduling resync.\n");
e315cd28 3127 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4
LT		 3128 continue;
3129 }
3130
3131 /* Check for matching device in port list. */
3132 found = 0;
3133 fcport = NULL;
e315cd28 3134 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 3135 if (memcmp(new_fcport->port_name, fcport->port_name,
3136 WWN_SIZE))
3137 continue;
3138
ddb9b126 3139 fcport->flags &= ~FCF_FABRIC_DEVICE;
1da177e4
LT		 3140 fcport->loop_id = new_fcport->loop_id;
3141 fcport->port_type = new_fcport->port_type;
3142 fcport->d_id.b24 = new_fcport->d_id.b24;
3143 memcpy(fcport->node_name, new_fcport->node_name,
3144 WWN_SIZE);
3145
3146 found++;
3147 break;
3148 }
3149
3150 if (!found) {
3151 /* New device, add to fcports list. */
e315cd28 3152 list_add_tail(&new_fcport->list, &vha->vp_fcports);
1da177e4
LT		 3153
3154 /* Allocate a new replacement fcport. */
3155 fcport = new_fcport;
e315cd28 3156 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3157 if (new_fcport == NULL) {
7c3df132
SK		 3158 ql_log(ql_log_warn, vha, 0x201c,
3159 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 3160 rval = QLA_MEMORY_ALLOC_FAILED;
3161 goto cleanup_allocation;
3162 }
3163 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
3164 }
3165
d8b45213 3166 /* Base iIDMA settings on HBA port speed. */
a3cbdfad 3167 fcport->fp_speed = ha->link_data_rate;
d8b45213 3168
e315cd28 3169 qla2x00_update_fcport(vha, fcport);
1da177e4
LT		 3170
3171 found_devs++;
3172 }
3173
3174cleanup_allocation:
c9475cb0 3175 kfree(new_fcport);
1da177e4
LT		 3176
3177 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3178 ql_dbg(ql_dbg_disc, vha, 0x201d,
3179 "Configure local loop error exit: rval=%x.\n", rval);
1da177e4
LT		 3180 }
3181
1da177e4
LT		 3182 return (rval);
3183}
3184
d8b45213 3185static void
e315cd28 3186qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
d8b45213 3187{
d8b45213 3188 int rval;
1bb39548 3189 uint16_t mb[4];
e315cd28 3190 struct qla_hw_data *ha = vha->hw;
d8b45213 3191
c76f2c01 3192 if (!IS_IIDMA_CAPABLE(ha))
d8b45213
AV		 3193 return;
3194
c9afb9a2
GM		 3195 if (atomic_read(&fcport->state) != FCS_ONLINE)
3196 return;
3197
39bd9622
AV		 3198 if (fcport->fp_speed == PORT_SPEED_UNKNOWN ||
3199 fcport->fp_speed > ha->link_data_rate)
d8b45213
AV		 3200 return;
3201
e315cd28 3202 rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed,
a3cbdfad 3203 mb);
d8b45213 3204 if (rval != QLA_SUCCESS) {
7c3df132 3205 ql_dbg(ql_dbg_disc, vha, 0x2004,
7b833558
OK		 3206 "Unable to adjust iIDMA %8phN -- %04x %x %04x %04x.\n",
3207 fcport->port_name, rval, fcport->fp_speed, mb[0], mb[1]);
d8b45213 3208 } else {
7c3df132 3209 ql_dbg(ql_dbg_disc, vha, 0x2005,
7b833558 3210 "iIDMA adjusted to %s GB/s on %8phN.\n",
d0297c9a 3211 qla2x00_get_link_speed_str(ha, fcport->fp_speed),
7b833558 3212 fcport->port_name);
d8b45213
AV		 3213 }
3214}
3215
23be331d 3216static void
e315cd28 3217qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport)
8482e118
AV		 3218{
3219 struct fc_rport_identifiers rport_ids;
bdf79621 3220 struct fc_rport *rport;
044d78e1 3221 unsigned long flags;
8482e118 3222
ac280b67 3223 qla2x00_rport_del(fcport);
8482e118 3224
f8b02a85
AV		 3225 rport_ids.node_name = wwn_to_u64(fcport->node_name);
3226 rport_ids.port_name = wwn_to_u64(fcport->port_name);
8482e118
AV		 3227 rport_ids.port_id = fcport->d_id.b.domain << 16 |
3228 fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa;
77d74143 3229 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
e315cd28 3230 fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids);
77d74143 3231 if (!rport) {
7c3df132
SK		 3232 ql_log(ql_log_warn, vha, 0x2006,
3233 "Unable to allocate fc remote port.\n");
77d74143
AV		 3234 return;
3235 }
2d70c103
NB		 3236 /*
3237 * Create target mode FC NEXUS in qla_target.c if target mode is
3238 * enabled..
3239 */
3240 qlt_fc_port_added(vha, fcport);
3241
044d78e1 3242 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
19a7b4ae 3243 *((fc_port_t **)rport->dd_data) = fcport;
044d78e1 3244 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
d97994dc 3245
ad3e0eda 3246 rport->supported_classes = fcport->supported_classes;
77d74143 3247
8482e118
AV		 3248 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
3249 if (fcport->port_type == FCT_INITIATOR)
3250 rport_ids.roles |= FC_RPORT_ROLE_FCP_INITIATOR;
3251 if (fcport->port_type == FCT_TARGET)
3252 rport_ids.roles |= FC_RPORT_ROLE_FCP_TARGET;
77d74143 3253 fc_remote_port_rolechg(rport, rport_ids.roles);
1da177e4
LT		 3254}
3255
23be331d
AB		 3256/*
3257 * qla2x00_update_fcport
3258 * Updates device on list.
3259 *
3260 * Input:
3261 * ha = adapter block pointer.
3262 * fcport = port structure pointer.
3263 *
3264 * Return:
3265 * 0 - Success
3266 * BIT_0 - error
3267 *
3268 * Context:
3269 * Kernel context.
3270 */
3271void
e315cd28 3272qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
23be331d 3273{
e315cd28 3274 fcport->vha = vha;
8ae6d9c7
GM		 3275
3276 if (IS_QLAFX00(vha->hw)) {
3277 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
3278 qla2x00_reg_remote_port(vha, fcport);
3279 return;
3280 }
23be331d 3281 fcport->login_retry = 0;
5ff1d584 3282 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
23be331d 3283
1f93da52 3284 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
e315cd28 3285 qla2x00_iidma_fcport(vha, fcport);
21090cbe 3286 qla24xx_update_fcport_fcp_prio(vha, fcport);
e315cd28 3287 qla2x00_reg_remote_port(vha, fcport);
23be331d
AB		 3288}
3289
1da177e4
LT		 3290/*
3291 * qla2x00_configure_fabric
3292 * Setup SNS devices with loop ID's.
3293 *
3294 * Input:
3295 * ha = adapter block pointer.
3296 *
3297 * Returns:
3298 * 0 = success.
3299 * BIT_0 = error
3300 */
3301static int
e315cd28 3302qla2x00_configure_fabric(scsi_qla_host_t *vha)
1da177e4 3303{
b3b02e6e 3304 int rval;
e452ceb6 3305 fc_port_t *fcport, *fcptemp;
1da177e4
LT		 3306 uint16_t next_loopid;
3307 uint16_t mb[MAILBOX_REGISTER_COUNT];
0107109e 3308 uint16_t loop_id;
1da177e4 3309 LIST_HEAD(new_fcports);
e315cd28
AC		 3310 struct qla_hw_data *ha = vha->hw;
3311 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 3312
3313 /* If FL port exists, then SNS is present */
e428924c 3314 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 3315 loop_id = NPH_F_PORT;
3316 else
3317 loop_id = SNS_FL_PORT;
e315cd28 3318 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1);
1da177e4 3319 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3320 ql_dbg(ql_dbg_disc, vha, 0x201f,
3321 "MBX_GET_PORT_NAME failed, No FL Port.\n");
1da177e4 3322
e315cd28 3323 vha->device_flags &= ~SWITCH_FOUND;
1da177e4
LT		 3324 return (QLA_SUCCESS);
3325 }
e315cd28 3326 vha->device_flags |= SWITCH_FOUND;
1da177e4 3327
1da177e4 3328 do {
cca5335c
AV		 3329 /* FDMI support. */
3330 if (ql2xfdmienable &&
e315cd28
AC		 3331 test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags))
3332 qla2x00_fdmi_register(vha);
cca5335c 3333
1da177e4 3334 /* Ensure we are logged into the SNS. */
e428924c 3335 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 3336 loop_id = NPH_SNS;
3337 else
3338 loop_id = SIMPLE_NAME_SERVER;
0b91d116
CD		 3339 rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff,
3340 0xfc, mb, BIT_1|BIT_0);
3341 if (rval != QLA_SUCCESS) {
3342 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
e452ceb6 3343 return rval;
0b91d116 3344 }
1da177e4 3345 if (mb[0] != MBS_COMMAND_COMPLETE) {
7c3df132
SK		 3346 ql_dbg(ql_dbg_disc, vha, 0x2042,
3347 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x "
3348 "mb[6]=%x mb[7]=%x.\n", loop_id, mb[0], mb[1],
3349 mb[2], mb[6], mb[7]);
1da177e4
LT		 3350 return (QLA_SUCCESS);
3351 }
3352
e315cd28
AC		 3353 if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) {
3354 if (qla2x00_rft_id(vha)) {
1da177e4 3355 /* EMPTY */
7c3df132
SK		 3356 ql_dbg(ql_dbg_disc, vha, 0x2045,
3357 "Register FC-4 TYPE failed.\n");
1da177e4 3358 }
e315cd28 3359 if (qla2x00_rff_id(vha)) {
1da177e4 3360 /* EMPTY */
7c3df132
SK		 3361 ql_dbg(ql_dbg_disc, vha, 0x2049,
3362 "Register FC-4 Features failed.\n");
1da177e4 3363 }
e315cd28 3364 if (qla2x00_rnn_id(vha)) {
1da177e4 3365 /* EMPTY */
7c3df132
SK		 3366 ql_dbg(ql_dbg_disc, vha, 0x204f,
3367 "Register Node Name failed.\n");
e315cd28 3368 } else if (qla2x00_rsnn_nn(vha)) {
1da177e4 3369 /* EMPTY */
7c3df132
SK		 3370 ql_dbg(ql_dbg_disc, vha, 0x2053,
3371 "Register Symobilic Node Name failed.\n");
1da177e4
LT		 3372 }
3373 }
3374
827210ba
JC		 3375#define QLA_FCPORT_SCAN 1
3376#define QLA_FCPORT_FOUND 2
3377
3378 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3379 fcport->scan_state = QLA_FCPORT_SCAN;
3380 }
3381
e315cd28 3382 rval = qla2x00_find_all_fabric_devs(vha, &new_fcports);
1da177e4
LT		 3383 if (rval != QLA_SUCCESS)
3384 break;
3385
e452ceb6
JC		 3386 /*
3387 * Logout all previous fabric devices marked lost, except
3388 * FCP2 devices.
3389 */
e315cd28
AC		 3390 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3391 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
1da177e4
LT		 3392 break;
3393
3394 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0)
3395 continue;
3396
827210ba 3397 if (fcport->scan_state == QLA_FCPORT_SCAN &&
b3b02e6e 3398 atomic_read(&fcport->state) == FCS_ONLINE) {
e315cd28 3399 qla2x00_mark_device_lost(vha, fcport,
d97994dc 3400 ql2xplogiabsentdevice, 0);
1da177e4 3401 if (fcport->loop_id != FC_NO_LOOP_ID &&
f08b7251 3402 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
1da177e4
LT		 3403 fcport->port_type != FCT_INITIATOR &&
3404 fcport->port_type != FCT_BROADCAST) {
e315cd28 3405 ha->isp_ops->fabric_logout(vha,
1c7c6357
AV		 3406 fcport->loop_id,
3407 fcport->d_id.b.domain,
3408 fcport->d_id.b.area,
3409 fcport->d_id.b.al_pa);
1a5c69bf 3410 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 3411 }
3412 }
e452ceb6 3413 }
1da177e4 3414
e452ceb6
JC		 3415 /* Starting free loop ID. */
3416 next_loopid = ha->min_external_loopid;
3417
3418 /*
3419 * Scan through our port list and login entries that need to be
3420 * logged in.
3421 */
3422 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3423 if (atomic_read(&vha->loop_down_timer) ||
3424 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3425 break;
3426
3427 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0 ||
3428 (fcport->flags & FCF_LOGIN_NEEDED) == 0)
3429 continue;
3430
3431 if (fcport->loop_id == FC_NO_LOOP_ID) {
3432 fcport->loop_id = next_loopid;
3433 rval = qla2x00_find_new_loop_id(
3434 base_vha, fcport);
3435 if (rval != QLA_SUCCESS) {
3436 /* Ran out of IDs to use */
3437 break;
1da177e4
LT		 3438 }
3439 }
e452ceb6
JC		 3440 /* Login and update database */
3441 qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
3442 }
3443
3444 /* Exit if out of loop IDs. */
3445 if (rval != QLA_SUCCESS) {
3446 break;
3447 }
3448
3449 /*
3450 * Login and add the new devices to our port list.
3451 */
3452 list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) {
3453 if (atomic_read(&vha->loop_down_timer) ||
3454 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3455 break;
3456
3457 /* Find a new loop ID to use. */
3458 fcport->loop_id = next_loopid;
3459 rval = qla2x00_find_new_loop_id(base_vha, fcport);
3460 if (rval != QLA_SUCCESS) {
3461 /* Ran out of IDs to use */
3462 break;
3463 }
1da177e4 3464
bdf79621 3465 /* Login and update database */
e315cd28 3466 qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
e452ceb6
JC		 3467
3468 list_move_tail(&fcport->list, &vha->vp_fcports);
1da177e4
LT		 3469 }
3470 } while (0);
3471
e452ceb6
JC		 3472 /* Free all new device structures not processed. */
3473 list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) {
3474 list_del(&fcport->list);
3475 kfree(fcport);
3476 }
3477
1da177e4 3478 if (rval) {
7c3df132
SK		 3479 ql_dbg(ql_dbg_disc, vha, 0x2068,
3480 "Configure fabric error exit rval=%d.\n", rval);
1da177e4
LT		 3481 }
3482
3483 return (rval);
3484}
3485
1da177e4
LT		 3486/*
3487 * qla2x00_find_all_fabric_devs
3488 *
3489 * Input:
3490 * ha = adapter block pointer.
3491 * dev = database device entry pointer.
3492 *
3493 * Returns:
3494 * 0 = success.
3495 *
3496 * Context:
3497 * Kernel context.
3498 */
3499static int
e315cd28
AC		 3500qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha,
3501 struct list_head *new_fcports)
1da177e4
LT		 3502{
3503 int rval;
3504 uint16_t loop_id;
3505 fc_port_t *fcport, *new_fcport, *fcptemp;
3506 int found;
3507
3508 sw_info_t *swl;
3509 int swl_idx;
3510 int first_dev, last_dev;
1516ef44 3511 port_id_t wrap = {}, nxt_d_id;
e315cd28 3512 struct qla_hw_data *ha = vha->hw;
bb4cf5b7 3513 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 3514
3515 rval = QLA_SUCCESS;
3516
3517 /* Try GID_PT to get device list, else GAN. */
7a67735b 3518 if (!ha->swl)
642ef983 3519 ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t),
7a67735b
AV		 3520 GFP_KERNEL);
3521 swl = ha->swl;
bbfbbbc1 3522 if (!swl) {
1da177e4 3523 /*EMPTY*/
7c3df132
SK		 3524 ql_dbg(ql_dbg_disc, vha, 0x2054,
3525 "GID_PT allocations failed, fallback on GA_NXT.\n");
1da177e4 3526 } else {
642ef983 3527 memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t));
e315cd28 3528 if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) {
1da177e4 3529 swl = NULL;
e315cd28 3530 } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 3531 swl = NULL;
e315cd28 3532 } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 3533 swl = NULL;
e5896bd5 3534 } else if (ql2xiidmaenable &&
e315cd28
AC		 3535 qla2x00_gfpn_id(vha, swl) == QLA_SUCCESS) {
3536 qla2x00_gpsc(vha, swl);
1da177e4 3537 }
e8c72ba5
CD		 3538
3539 /* If other queries succeeded probe for FC-4 type */
3540 if (swl)
3541 qla2x00_gff_id(vha, swl);
1da177e4
LT		 3542 }
3543 swl_idx = 0;
3544
3545 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 3546 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3547 if (new_fcport == NULL) {
7c3df132
SK		 3548 ql_log(ql_log_warn, vha, 0x205e,
3549 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 3550 return (QLA_MEMORY_ALLOC_FAILED);
3551 }
3552 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
1da177e4
LT		 3553 /* Set start port ID scan at adapter ID. */
3554 first_dev = 1;
3555 last_dev = 0;
3556
3557 /* Starting free loop ID. */
e315cd28
AC		 3558 loop_id = ha->min_external_loopid;
3559 for (; loop_id <= ha->max_loop_id; loop_id++) {
3560 if (qla2x00_is_reserved_id(vha, loop_id))
1da177e4
LT		 3561 continue;
3562
3a6478df
GM		 3563 if (ha->current_topology == ISP_CFG_FL &&
3564 (atomic_read(&vha->loop_down_timer) ||
3565 LOOP_TRANSITION(vha))) {
bb2d52b2
AV		 3566 atomic_set(&vha->loop_down_timer, 0);
3567 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
3568 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
1da177e4 3569 break;
bb2d52b2 3570 }
1da177e4
LT		 3571
3572 if (swl != NULL) {
3573 if (last_dev) {
3574 wrap.b24 = new_fcport->d_id.b24;
3575 } else {
3576 new_fcport->d_id.b24 = swl[swl_idx].d_id.b24;
3577 memcpy(new_fcport->node_name,
3578 swl[swl_idx].node_name, WWN_SIZE);
3579 memcpy(new_fcport->port_name,
3580 swl[swl_idx].port_name, WWN_SIZE);
d8b45213
AV		 3581 memcpy(new_fcport->fabric_port_name,
3582 swl[swl_idx].fabric_port_name, WWN_SIZE);
3583 new_fcport->fp_speed = swl[swl_idx].fp_speed;
e8c72ba5 3584 new_fcport->fc4_type = swl[swl_idx].fc4_type;
1da177e4
LT		 3585
3586 if (swl[swl_idx].d_id.b.rsvd_1 != 0) {
3587 last_dev = 1;
3588 }
3589 swl_idx++;
3590 }
3591 } else {
3592 /* Send GA_NXT to the switch */
e315cd28 3593 rval = qla2x00_ga_nxt(vha, new_fcport);
1da177e4 3594 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3595 ql_log(ql_log_warn, vha, 0x2064,
3596 "SNS scan failed -- assuming "
3597 "zero-entry result.\n");
1da177e4
LT		 3598 list_for_each_entry_safe(fcport, fcptemp,
3599 new_fcports, list) {
3600 list_del(&fcport->list);
3601 kfree(fcport);
3602 }
3603 rval = QLA_SUCCESS;
3604 break;
3605 }
3606 }
3607
3608 /* If wrap on switch device list, exit. */
3609 if (first_dev) {
3610 wrap.b24 = new_fcport->d_id.b24;
3611 first_dev = 0;
3612 } else if (new_fcport->d_id.b24 == wrap.b24) {
7c3df132
SK		 3613 ql_dbg(ql_dbg_disc, vha, 0x2065,
3614 "Device wrap (%02x%02x%02x).\n",
3615 new_fcport->d_id.b.domain,
3616 new_fcport->d_id.b.area,
3617 new_fcport->d_id.b.al_pa);
1da177e4
LT		 3618 break;
3619 }
3620
2c3dfe3f 3621 /* Bypass if same physical adapter. */
e315cd28 3622 if (new_fcport->d_id.b24 == base_vha->d_id.b24)
1da177e4
LT		 3623 continue;
3624
2c3dfe3f 3625 /* Bypass virtual ports of the same host. */
bb4cf5b7
CD		 3626 if (qla2x00_is_a_vp_did(vha, new_fcport->d_id.b24))
3627 continue;
2c3dfe3f 3628
f7d289f6
AV		 3629 /* Bypass if same domain and area of adapter. */
3630 if (((new_fcport->d_id.b24 & 0xffff00) ==
e315cd28 3631 (vha->d_id.b24 & 0xffff00)) && ha->current_topology ==
f7d289f6
AV		 3632 ISP_CFG_FL)
3633 continue;
3634
1da177e4
LT		 3635 /* Bypass reserved domain fields. */
3636 if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0)
3637 continue;
3638
e8c72ba5 3639 /* Bypass ports whose FCP-4 type is not FCP_SCSI */
4da26e16
CD		 3640 if (ql2xgffidenable &&
3641 (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI &&
3642 new_fcport->fc4_type != FC4_TYPE_UNKNOWN))
e8c72ba5
CD		 3643 continue;
3644
1da177e4
LT		 3645 /* Locate matching device in database. */
3646 found = 0;
e315cd28 3647 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 3648 if (memcmp(new_fcport->port_name, fcport->port_name,
3649 WWN_SIZE))
3650 continue;
3651
827210ba 3652 fcport->scan_state = QLA_FCPORT_FOUND;
b3b02e6e 3653
1da177e4
LT		 3654 found++;
3655
d8b45213
AV		 3656 /* Update port state. */
3657 memcpy(fcport->fabric_port_name,
3658 new_fcport->fabric_port_name, WWN_SIZE);
3659 fcport->fp_speed = new_fcport->fp_speed;
3660
1da177e4
LT		 3661 /*
3662 * If address the same and state FCS_ONLINE, nothing
3663 * changed.
3664 */
3665 if (fcport->d_id.b24 == new_fcport->d_id.b24 &&
3666 atomic_read(&fcport->state) == FCS_ONLINE) {
3667 break;
3668 }
3669
3670 /*
3671 * If device was not a fabric device before.
3672 */
3673 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) {
3674 fcport->d_id.b24 = new_fcport->d_id.b24;
5f16b331 3675 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 3676 fcport->flags |= (FCF_FABRIC_DEVICE |
3677 FCF_LOGIN_NEEDED);
1da177e4
LT		 3678 break;
3679 }
3680
3681 /*
3682 * Port ID changed or device was marked to be updated;
3683 * Log it out if still logged in and mark it for
3684 * relogin later.
3685 */
3686 fcport->d_id.b24 = new_fcport->d_id.b24;
3687 fcport->flags |= FCF_LOGIN_NEEDED;
3688 if (fcport->loop_id != FC_NO_LOOP_ID &&
f08b7251 3689 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
0eba25df 3690 (fcport->flags & FCF_ASYNC_SENT) == 0 &&
1da177e4
LT		 3691 fcport->port_type != FCT_INITIATOR &&
3692 fcport->port_type != FCT_BROADCAST) {
e315cd28 3693 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3694 fcport->d_id.b.domain, fcport->d_id.b.area,
3695 fcport->d_id.b.al_pa);
5f16b331 3696 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 3697 }
3698
3699 break;
3700 }
3701
3702 if (found)
3703 continue;
1da177e4
LT		 3704 /* If device was not in our fcports list, then add it. */
3705 list_add_tail(&new_fcport->list, new_fcports);
3706
3707 /* Allocate a new replacement fcport. */
3708 nxt_d_id.b24 = new_fcport->d_id.b24;
e315cd28 3709 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3710 if (new_fcport == NULL) {
7c3df132
SK		 3711 ql_log(ql_log_warn, vha, 0x2066,
3712 "Memory allocation failed for fcport.\n");
1da177e4
LT		 3713 return (QLA_MEMORY_ALLOC_FAILED);
3714 }
3715 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
3716 new_fcport->d_id.b24 = nxt_d_id.b24;
3717 }
3718
c9475cb0 3719 kfree(new_fcport);
1da177e4 3720
1da177e4
LT		 3721 return (rval);
3722}
3723
3724/*
3725 * qla2x00_find_new_loop_id
3726 * Scan through our port list and find a new usable loop ID.
3727 *
3728 * Input:
3729 * ha: adapter state pointer.
3730 * dev: port structure pointer.
3731 *
3732 * Returns:
3733 * qla2x00 local function return status code.
3734 *
3735 * Context:
3736 * Kernel context.
3737 */
03bcfb57 3738int
e315cd28 3739qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
1da177e4
LT		 3740{
3741 int rval;
e315cd28 3742 struct qla_hw_data *ha = vha->hw;
feafb7b1 3743 unsigned long flags = 0;
1da177e4
LT		 3744
3745 rval = QLA_SUCCESS;
3746
5f16b331 3747 spin_lock_irqsave(&ha->vport_slock, flags);
1da177e4 3748
5f16b331
CD		 3749 dev->loop_id = find_first_zero_bit(ha->loop_id_map,
3750 LOOPID_MAP_SIZE);
3751 if (dev->loop_id >= LOOPID_MAP_SIZE ||
3752 qla2x00_is_reserved_id(vha, dev->loop_id)) {
3753 dev->loop_id = FC_NO_LOOP_ID;
3754 rval = QLA_FUNCTION_FAILED;
3755 } else
3756 set_bit(dev->loop_id, ha->loop_id_map);
1da177e4 3757
5f16b331 3758 spin_unlock_irqrestore(&ha->vport_slock, flags);
1da177e4 3759
5f16b331
CD		 3760 if (rval == QLA_SUCCESS)
3761 ql_dbg(ql_dbg_disc, dev->vha, 0x2086,
3762 "Assigning new loopid=%x, portid=%x.\n",
3763 dev->loop_id, dev->d_id.b24);
3764 else
3765 ql_log(ql_log_warn, dev->vha, 0x2087,
3766 "No loop_id's available, portid=%x.\n",
3767 dev->d_id.b24);
1da177e4
LT		 3768
3769 return (rval);
3770}
3771
1da177e4
LT		 3772/*
3773 * qla2x00_fabric_dev_login
3774 * Login fabric target device and update FC port database.
3775 *
3776 * Input:
3777 * ha: adapter state pointer.
3778 * fcport: port structure list pointer.
3779 * next_loopid: contains value of a new loop ID that can be used
3780 * by the next login attempt.
3781 *
3782 * Returns:
3783 * qla2x00 local function return status code.
3784 *
3785 * Context:
3786 * Kernel context.
3787 */
3788static int
e315cd28 3789qla2x00_fabric_dev_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 3790 uint16_t *next_loopid)
3791{
3792 int rval;
3793 int retry;
0107109e 3794 uint8_t opts;
e315cd28 3795 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3796
3797 rval = QLA_SUCCESS;
3798 retry = 0;
3799
ac280b67 3800 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584
AV		 3801 if (fcport->flags & FCF_ASYNC_SENT)
3802 return rval;
3803 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 3804 rval = qla2x00_post_async_login_work(vha, fcport, NULL);
3805 if (!rval)
3806 return rval;
3807 }
3808
5ff1d584 3809 fcport->flags &= ~FCF_ASYNC_SENT;
e315cd28 3810 rval = qla2x00_fabric_login(vha, fcport, next_loopid);
1da177e4 3811 if (rval == QLA_SUCCESS) {
f08b7251 3812 /* Send an ADISC to FCP2 devices.*/
0107109e 3813 opts = 0;
f08b7251 3814 if (fcport->flags & FCF_FCP2_DEVICE)
0107109e 3815 opts |= BIT_1;
e315cd28 3816 rval = qla2x00_get_port_database(vha, fcport, opts);
1da177e4 3817 if (rval != QLA_SUCCESS) {
e315cd28 3818 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3819 fcport->d_id.b.domain, fcport->d_id.b.area,
3820 fcport->d_id.b.al_pa);
e315cd28 3821 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4 3822 } else {
e315cd28 3823 qla2x00_update_fcport(vha, fcport);
1da177e4 3824 }
0b91d116
CD		 3825 } else {
3826 /* Retry Login. */
3827 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 3828 }
3829
3830 return (rval);
3831}
3832
3833/*
3834 * qla2x00_fabric_login
3835 * Issue fabric login command.
3836 *
3837 * Input:
3838 * ha = adapter block pointer.
3839 * device = pointer to FC device type structure.
3840 *
3841 * Returns:
3842 * 0 - Login successfully
3843 * 1 - Login failed
3844 * 2 - Initiator device
3845 * 3 - Fatal error
3846 */
3847int
e315cd28 3848qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 3849 uint16_t *next_loopid)
3850{
3851 int rval;
3852 int retry;
3853 uint16_t tmp_loopid;
3854 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 3855 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3856
3857 retry = 0;
3858 tmp_loopid = 0;
3859
3860 for (;;) {
7c3df132
SK		 3861 ql_dbg(ql_dbg_disc, vha, 0x2000,
3862 "Trying Fabric Login w/loop id 0x%04x for port "
3863 "%02x%02x%02x.\n",
3864 fcport->loop_id, fcport->d_id.b.domain,
3865 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 3866
3867 /* Login fcport on switch. */
0b91d116 3868 rval = ha->isp_ops->fabric_login(vha, fcport->loop_id,
1da177e4
LT		 3869 fcport->d_id.b.domain, fcport->d_id.b.area,
3870 fcport->d_id.b.al_pa, mb, BIT_0);
0b91d116
CD		 3871 if (rval != QLA_SUCCESS) {
3872 return rval;
3873 }
1da177e4
LT		 3874 if (mb[0] == MBS_PORT_ID_USED) {
3875 /*
3876 * Device has another loop ID. The firmware team
0107109e
AV		 3877 * recommends the driver perform an implicit login with
3878 * the specified ID again. The ID we just used is save
3879 * here so we return with an ID that can be tried by
3880 * the next login.
1da177e4
LT		 3881 */
3882 retry++;
3883 tmp_loopid = fcport->loop_id;
3884 fcport->loop_id = mb[1];
3885
7c3df132
SK		 3886 ql_dbg(ql_dbg_disc, vha, 0x2001,
3887 "Fabric Login: port in use - next loop "
3888 "id=0x%04x, port id= %02x%02x%02x.\n",
1da177e4 3889 fcport->loop_id, fcport->d_id.b.domain,
7c3df132 3890 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 3891
3892 } else if (mb[0] == MBS_COMMAND_COMPLETE) {
3893 /*
3894 * Login succeeded.
3895 */
3896 if (retry) {
3897 /* A retry occurred before. */
3898 *next_loopid = tmp_loopid;
3899 } else {
3900 /*
3901 * No retry occurred before. Just increment the
3902 * ID value for next login.
3903 */
3904 *next_loopid = (fcport->loop_id + 1);
3905 }
3906
3907 if (mb[1] & BIT_0) {
3908 fcport->port_type = FCT_INITIATOR;
3909 } else {
3910 fcport->port_type = FCT_TARGET;
3911 if (mb[1] & BIT_1) {
8474f3a0 3912 fcport->flags |= FCF_FCP2_DEVICE;
1da177e4
LT		 3913 }
3914 }
3915
ad3e0eda
AV		 3916 if (mb[10] & BIT_0)
3917 fcport->supported_classes |= FC_COS_CLASS2;
3918 if (mb[10] & BIT_1)
3919 fcport->supported_classes |= FC_COS_CLASS3;
3920
2d70c103
NB		 3921 if (IS_FWI2_CAPABLE(ha)) {
3922 if (mb[10] & BIT_7)
3923 fcport->flags |=
3924 FCF_CONF_COMP_SUPPORTED;
3925 }
3926
1da177e4
LT		 3927 rval = QLA_SUCCESS;
3928 break;
3929 } else if (mb[0] == MBS_LOOP_ID_USED) {
3930 /*
3931 * Loop ID already used, try next loop ID.
3932 */
3933 fcport->loop_id++;
e315cd28 3934 rval = qla2x00_find_new_loop_id(vha, fcport);
1da177e4
LT		 3935 if (rval != QLA_SUCCESS) {
3936 /* Ran out of loop IDs to use */
3937 break;
3938 }
3939 } else if (mb[0] == MBS_COMMAND_ERROR) {
3940 /*
3941 * Firmware possibly timed out during login. If NO
3942 * retries are left to do then the device is declared
3943 * dead.
3944 */
3945 *next_loopid = fcport->loop_id;
e315cd28 3946 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3947 fcport->d_id.b.domain, fcport->d_id.b.area,
3948 fcport->d_id.b.al_pa);
e315cd28 3949 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 3950
3951 rval = 1;
3952 break;
3953 } else {
3954 /*
3955 * unrecoverable / not handled error
3956 */
7c3df132
SK		 3957 ql_dbg(ql_dbg_disc, vha, 0x2002,
3958 "Failed=%x port_id=%02x%02x%02x loop_id=%x "
3959 "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain,
3960 fcport->d_id.b.area, fcport->d_id.b.al_pa,
3961 fcport->loop_id, jiffies);
1da177e4
LT		 3962
3963 *next_loopid = fcport->loop_id;
e315cd28 3964 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3965 fcport->d_id.b.domain, fcport->d_id.b.area,
3966 fcport->d_id.b.al_pa);
5f16b331 3967 qla2x00_clear_loop_id(fcport);
0eedfcf0 3968 fcport->login_retry = 0;
1da177e4
LT		 3969
3970 rval = 3;
3971 break;
3972 }
3973 }
3974
3975 return (rval);
3976}
3977
3978/*
3979 * qla2x00_local_device_login
3980 * Issue local device login command.
3981 *
3982 * Input:
3983 * ha = adapter block pointer.
3984 * loop_id = loop id of device to login to.
3985 *
3986 * Returns (Where's the #define!!!!):
3987 * 0 - Login successfully
3988 * 1 - Login failed
3989 * 3 - Fatal error
3990 */
3991int
e315cd28 3992qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport)
1da177e4
LT		 3993{
3994 int rval;
3995 uint16_t mb[MAILBOX_REGISTER_COUNT];
3996
3997 memset(mb, 0, sizeof(mb));
e315cd28 3998 rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0);
1da177e4
LT		 3999 if (rval == QLA_SUCCESS) {
4000 /* Interrogate mailbox registers for any errors */
4001 if (mb[0] == MBS_COMMAND_ERROR)
4002 rval = 1;
4003 else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR)
4004 /* device not in PCB table */
4005 rval = 3;
4006 }
4007
4008 return (rval);
4009}
4010
4011/*
4012 * qla2x00_loop_resync
4013 * Resync with fibre channel devices.
4014 *
4015 * Input:
4016 * ha = adapter block pointer.
4017 *
4018 * Returns:
4019 * 0 = success
4020 */
4021int
e315cd28 4022qla2x00_loop_resync(scsi_qla_host_t *vha)
1da177e4 4023{
73208dfd 4024 int rval = QLA_SUCCESS;
1da177e4 4025 uint32_t wait_time;
67c2e93a
AC		 4026 struct req_que *req;
4027 struct rsp_que *rsp;
4028
7163ea81 4029 if (vha->hw->flags.cpu_affinity_enabled)
67c2e93a
AC		 4030 req = vha->hw->req_q_map[0];
4031 else
4032 req = vha->req;
4033 rsp = req->rsp;
1da177e4 4034
e315cd28
AC		 4035 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
4036 if (vha->flags.online) {
4037 if (!(rval = qla2x00_fw_ready(vha))) {
1da177e4
LT		 4038 /* Wait at most MAX_TARGET RSCNs for a stable link. */
4039 wait_time = 256;
4040 do {
8ae6d9c7
GM		 4041 if (!IS_QLAFX00(vha->hw)) {
4042 /*
4043 * Issue a marker after FW becomes
4044 * ready.
4045 */
4046 qla2x00_marker(vha, req, rsp, 0, 0,
4047 MK_SYNC_ALL);
4048 vha->marker_needed = 0;
4049 }
1da177e4
LT		 4050
4051 /* Remap devices on Loop. */
e315cd28 4052 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4 4053
8ae6d9c7
GM		 4054 if (IS_QLAFX00(vha->hw))
4055 qlafx00_configure_devices(vha);
4056 else
4057 qla2x00_configure_loop(vha);
4058
1da177e4 4059 wait_time--;
e315cd28
AC		 4060 } while (!atomic_read(&vha->loop_down_timer) &&
4061 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
4062 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
4063 &vha->dpc_flags)));
1da177e4 4064 }
1da177e4
LT		 4065 }
4066
e315cd28 4067 if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
1da177e4 4068 return (QLA_FUNCTION_FAILED);
1da177e4 4069
e315cd28 4070 if (rval)
7c3df132
SK		 4071 ql_dbg(ql_dbg_disc, vha, 0x206c,
4072 "%s *** FAILED ***.\n", __func__);
1da177e4
LT		 4073
4074 return (rval);
4075}
4076
579d12b5
SK		 4077/*
4078* qla2x00_perform_loop_resync
4079* Description: This function will set the appropriate flags and call
4080* qla2x00_loop_resync. If successful loop will be resynced
4081* Arguments : scsi_qla_host_t pointer
4082* returm : Success or Failure
4083*/
4084
4085int qla2x00_perform_loop_resync(scsi_qla_host_t *ha)
4086{
4087 int32_t rval = 0;
4088
4089 if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) {
4090 /*Configure the flags so that resync happens properly*/
4091 atomic_set(&ha->loop_down_timer, 0);
4092 if (!(ha->device_flags & DFLG_NO_CABLE)) {
4093 atomic_set(&ha->loop_state, LOOP_UP);
4094 set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags);
4095 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
4096 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
4097
4098 rval = qla2x00_loop_resync(ha);
4099 } else
4100 atomic_set(&ha->loop_state, LOOP_DEAD);
4101
4102 clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags);
4103 }
4104
4105 return rval;
4106}
4107
d97994dc 4108void
67becc00 4109qla2x00_update_fcports(scsi_qla_host_t *base_vha)
d97994dc
AV		 4110{
4111 fc_port_t *fcport;
feafb7b1
AE		 4112 struct scsi_qla_host *vha;
4113 struct qla_hw_data *ha = base_vha->hw;
4114 unsigned long flags;
d97994dc 4115
feafb7b1 4116 spin_lock_irqsave(&ha->vport_slock, flags);
d97994dc 4117 /* Go with deferred removal of rport references. */
feafb7b1
AE		 4118 list_for_each_entry(vha, &base_vha->hw->vp_list, list) {
4119 atomic_inc(&vha->vref_count);
4120 list_for_each_entry(fcport, &vha->vp_fcports, list) {
8ae598d0 4121 if (fcport->drport &&
feafb7b1
AE		 4122 atomic_read(&fcport->state) != FCS_UNCONFIGURED) {
4123 spin_unlock_irqrestore(&ha->vport_slock, flags);
67becc00 4124 qla2x00_rport_del(fcport);
feafb7b1
AE		 4125 spin_lock_irqsave(&ha->vport_slock, flags);
4126 }
4127 }
4128 atomic_dec(&vha->vref_count);
4129 }
4130 spin_unlock_irqrestore(&ha->vport_slock, flags);
d97994dc
AV		 4131}
4132
7d613ac6
SV		 4133/* Assumes idc_lock always held on entry */
4134void
4135qla83xx_reset_ownership(scsi_qla_host_t *vha)
4136{
4137 struct qla_hw_data *ha = vha->hw;
4138 uint32_t drv_presence, drv_presence_mask;
4139 uint32_t dev_part_info1, dev_part_info2, class_type;
4140 uint32_t class_type_mask = 0x3;
4141 uint16_t fcoe_other_function = 0xffff, i;
4142
7ec0effd
AD		 4143 if (IS_QLA8044(ha)) {
4144 drv_presence = qla8044_rd_direct(vha,
4145 QLA8044_CRB_DRV_ACTIVE_INDEX);
4146 dev_part_info1 = qla8044_rd_direct(vha,
4147 QLA8044_CRB_DEV_PART_INFO_INDEX);
4148 dev_part_info2 = qla8044_rd_direct(vha,
4149 QLA8044_CRB_DEV_PART_INFO2);
4150 } else {
4151 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4152 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1);
4153 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2);
4154 }
7d613ac6
SV		 4155 for (i = 0; i < 8; i++) {
4156 class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask);
4157 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
4158 (i != ha->portnum)) {
4159 fcoe_other_function = i;
4160 break;
4161 }
4162 }
4163 if (fcoe_other_function == 0xffff) {
4164 for (i = 0; i < 8; i++) {
4165 class_type = ((dev_part_info2 >> (i * 4)) &
4166 class_type_mask);
4167 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
4168 ((i + 8) != ha->portnum)) {
4169 fcoe_other_function = i + 8;
4170 break;
4171 }
4172 }
4173 }
4174 /*
4175 * Prepare drv-presence mask based on fcoe functions present.
4176 * However consider only valid physical fcoe function numbers (0-15).
4177 */
4178 drv_presence_mask = ~((1 << (ha->portnum)) |
4179 ((fcoe_other_function == 0xffff) ?
4180 0 : (1 << (fcoe_other_function))));
4181
4182 /* We are the reset owner iff:
4183 * - No other protocol drivers present.
4184 * - This is the lowest among fcoe functions. */
4185 if (!(drv_presence & drv_presence_mask) &&
4186 (ha->portnum < fcoe_other_function)) {
4187 ql_dbg(ql_dbg_p3p, vha, 0xb07f,
4188 "This host is Reset owner.\n");
4189 ha->flags.nic_core_reset_owner = 1;
4190 }
4191}
4192
fa492630 4193static int
7d613ac6
SV		 4194__qla83xx_set_drv_ack(scsi_qla_host_t *vha)
4195{
4196 int rval = QLA_SUCCESS;
4197 struct qla_hw_data *ha = vha->hw;
4198 uint32_t drv_ack;
4199
4200 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4201 if (rval == QLA_SUCCESS) {
4202 drv_ack |= (1 << ha->portnum);
4203 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
4204 }
4205
4206 return rval;
4207}
4208
fa492630 4209static int
7d613ac6
SV		 4210__qla83xx_clear_drv_ack(scsi_qla_host_t *vha)
4211{
4212 int rval = QLA_SUCCESS;
4213 struct qla_hw_data *ha = vha->hw;
4214 uint32_t drv_ack;
4215
4216 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4217 if (rval == QLA_SUCCESS) {
4218 drv_ack &= ~(1 << ha->portnum);
4219 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
4220 }
4221
4222 return rval;
4223}
4224
fa492630 4225static const char *
7d613ac6
SV		 4226qla83xx_dev_state_to_string(uint32_t dev_state)
4227{
4228 switch (dev_state) {
4229 case QLA8XXX_DEV_COLD:
4230 return "COLD/RE-INIT";
4231 case QLA8XXX_DEV_INITIALIZING:
4232 return "INITIALIZING";
4233 case QLA8XXX_DEV_READY:
4234 return "READY";
4235 case QLA8XXX_DEV_NEED_RESET:
4236 return "NEED RESET";
4237 case QLA8XXX_DEV_NEED_QUIESCENT:
4238 return "NEED QUIESCENT";
4239 case QLA8XXX_DEV_FAILED:
4240 return "FAILED";
4241 case QLA8XXX_DEV_QUIESCENT:
4242 return "QUIESCENT";
4243 default:
4244 return "Unknown";
4245 }
4246}
4247
4248/* Assumes idc-lock always held on entry */
4249void
4250qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type)
4251{
4252 struct qla_hw_data *ha = vha->hw;
4253 uint32_t idc_audit_reg = 0, duration_secs = 0;
4254
4255 switch (audit_type) {
4256 case IDC_AUDIT_TIMESTAMP:
4257 ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000);
4258 idc_audit_reg = (ha->portnum) |
4259 (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8);
4260 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
4261 break;
4262
4263 case IDC_AUDIT_COMPLETION:
4264 duration_secs = ((jiffies_to_msecs(jiffies) -
4265 jiffies_to_msecs(ha->idc_audit_ts)) / 1000);
4266 idc_audit_reg = (ha->portnum) |
4267 (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8);
4268 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
4269 break;
4270
4271 default:
4272 ql_log(ql_log_warn, vha, 0xb078,
4273 "Invalid audit type specified.\n");
4274 break;
4275 }
4276}
4277
4278/* Assumes idc_lock always held on entry */
fa492630 4279static int
7d613ac6
SV		 4280qla83xx_initiating_reset(scsi_qla_host_t *vha)
4281{
4282 struct qla_hw_data *ha = vha->hw;
4283 uint32_t idc_control, dev_state;
4284
4285 __qla83xx_get_idc_control(vha, &idc_control);
4286 if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) {
4287 ql_log(ql_log_info, vha, 0xb080,
4288 "NIC Core reset has been disabled. idc-control=0x%x\n",
4289 idc_control);
4290 return QLA_FUNCTION_FAILED;
4291 }
4292
4293 /* Set NEED-RESET iff in READY state and we are the reset-owner */
4294 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4295 if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) {
4296 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
4297 QLA8XXX_DEV_NEED_RESET);
4298 ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n");
4299 qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP);
4300 } else {
4301 const char *state = qla83xx_dev_state_to_string(dev_state);
4302 ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n", state);
4303
4304 /* SV: XXX: Is timeout required here? */
4305 /* Wait for IDC state change READY -> NEED_RESET */
4306 while (dev_state == QLA8XXX_DEV_READY) {
4307 qla83xx_idc_unlock(vha, 0);
4308 msleep(200);
4309 qla83xx_idc_lock(vha, 0);
4310 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4311 }
4312 }
4313
4314 /* Send IDC ack by writing to drv-ack register */
4315 __qla83xx_set_drv_ack(vha);
4316
4317 return QLA_SUCCESS;
4318}
4319
4320int
4321__qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control)
4322{
4323 return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
4324}
4325
7d613ac6
SV		 4326int
4327__qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control)
4328{
4329 return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
4330}
4331
fa492630 4332static int
7d613ac6
SV		 4333qla83xx_check_driver_presence(scsi_qla_host_t *vha)
4334{
4335 uint32_t drv_presence = 0;
4336 struct qla_hw_data *ha = vha->hw;
4337
4338 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4339 if (drv_presence & (1 << ha->portnum))
4340 return QLA_SUCCESS;
4341 else
4342 return QLA_TEST_FAILED;
4343}
4344
4345int
4346qla83xx_nic_core_reset(scsi_qla_host_t *vha)
4347{
4348 int rval = QLA_SUCCESS;
4349 struct qla_hw_data *ha = vha->hw;
4350
4351 ql_dbg(ql_dbg_p3p, vha, 0xb058,
4352 "Entered %s().\n", __func__);
4353
4354 if (vha->device_flags & DFLG_DEV_FAILED) {
4355 ql_log(ql_log_warn, vha, 0xb059,
4356 "Device in unrecoverable FAILED state.\n");
4357 return QLA_FUNCTION_FAILED;
4358 }
4359
4360 qla83xx_idc_lock(vha, 0);
4361
4362 if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) {
4363 ql_log(ql_log_warn, vha, 0xb05a,
4364 "Function=0x%x has been removed from IDC participation.\n",
4365 ha->portnum);
4366 rval = QLA_FUNCTION_FAILED;
4367 goto exit;
4368 }
4369
4370 qla83xx_reset_ownership(vha);
4371
4372 rval = qla83xx_initiating_reset(vha);
4373
4374 /*
4375 * Perform reset if we are the reset-owner,
4376 * else wait till IDC state changes to READY/FAILED.
4377 */
4378 if (rval == QLA_SUCCESS) {
4379 rval = qla83xx_idc_state_handler(vha);
4380
4381 if (rval == QLA_SUCCESS)
4382 ha->flags.nic_core_hung = 0;
4383 __qla83xx_clear_drv_ack(vha);
4384 }
4385
4386exit:
4387 qla83xx_idc_unlock(vha, 0);
4388
4389 ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__);
4390
4391 return rval;
4392}
4393
81178772
SK		 4394int
4395qla2xxx_mctp_dump(scsi_qla_host_t *vha)
4396{
4397 struct qla_hw_data *ha = vha->hw;
4398 int rval = QLA_FUNCTION_FAILED;
4399
4400 if (!IS_MCTP_CAPABLE(ha)) {
4401 /* This message can be removed from the final version */
4402 ql_log(ql_log_info, vha, 0x506d,
4403 "This board is not MCTP capable\n");
4404 return rval;
4405 }
4406
4407 if (!ha->mctp_dump) {
4408 ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev,
4409 MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL);
4410
4411 if (!ha->mctp_dump) {
4412 ql_log(ql_log_warn, vha, 0x506e,
4413 "Failed to allocate memory for mctp dump\n");
4414 return rval;
4415 }
4416 }
4417
4418#define MCTP_DUMP_STR_ADDR 0x00000000
4419 rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma,
4420 MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4);
4421 if (rval != QLA_SUCCESS) {
4422 ql_log(ql_log_warn, vha, 0x506f,
4423 "Failed to capture mctp dump\n");
4424 } else {
4425 ql_log(ql_log_info, vha, 0x5070,
4426 "Mctp dump capture for host (%ld/%p).\n",
4427 vha->host_no, ha->mctp_dump);
4428 ha->mctp_dumped = 1;
4429 }
4430
409ee0fe 4431 if (!ha->flags.nic_core_reset_hdlr_active && !ha->portnum) {
81178772
SK		 4432 ha->flags.nic_core_reset_hdlr_active = 1;
4433 rval = qla83xx_restart_nic_firmware(vha);
4434 if (rval)
4435 /* NIC Core reset failed. */
4436 ql_log(ql_log_warn, vha, 0x5071,
4437 "Failed to restart nic firmware\n");
4438 else
4439 ql_dbg(ql_dbg_p3p, vha, 0xb084,
4440 "Restarted NIC firmware successfully.\n");
4441 ha->flags.nic_core_reset_hdlr_active = 0;
4442 }
4443
4444 return rval;
4445
4446}
4447
579d12b5 4448/*
8fcd6b8b 4449* qla2x00_quiesce_io
579d12b5
SK		 4450* Description: This function will block the new I/Os
4451* Its not aborting any I/Os as context
4452* is not destroyed during quiescence
4453* Arguments: scsi_qla_host_t
4454* return : void
4455*/
4456void
8fcd6b8b 4457qla2x00_quiesce_io(scsi_qla_host_t *vha)
579d12b5
SK		 4458{
4459 struct qla_hw_data *ha = vha->hw;
4460 struct scsi_qla_host *vp;
4461
8fcd6b8b
CD		 4462 ql_dbg(ql_dbg_dpc, vha, 0x401d,
4463 "Quiescing I/O - ha=%p.\n", ha);
579d12b5
SK		 4464
4465 atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME);
4466 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
4467 atomic_set(&vha->loop_state, LOOP_DOWN);
4468 qla2x00_mark_all_devices_lost(vha, 0);
4469 list_for_each_entry(vp, &ha->vp_list, list)
8fcd6b8b 4470 qla2x00_mark_all_devices_lost(vp, 0);
579d12b5
SK		 4471 } else {
4472 if (!atomic_read(&vha->loop_down_timer))
4473 atomic_set(&vha->loop_down_timer,
4474 LOOP_DOWN_TIME);
4475 }
4476 /* Wait for pending cmds to complete */
4477 qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST);
4478}
4479
a9083016
GM		 4480void
4481qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
4482{
4483 struct qla_hw_data *ha = vha->hw;
579d12b5 4484 struct scsi_qla_host *vp;
feafb7b1 4485 unsigned long flags;
6aef87be 4486 fc_port_t *fcport;
a9083016 4487
e46ef004
SK		 4488 /* For ISP82XX, driver waits for completion of the commands.
4489 * online flag should be set.
4490 */
7ec0effd 4491 if (!(IS_P3P_TYPE(ha)))
e46ef004 4492 vha->flags.online = 0;
a9083016
GM		 4493 ha->flags.chip_reset_done = 0;
4494 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2be21fa2 4495 vha->qla_stats.total_isp_aborts++;
a9083016 4496
7c3df132
SK		 4497 ql_log(ql_log_info, vha, 0x00af,
4498 "Performing ISP error recovery - ha=%p.\n", ha);
a9083016 4499
e46ef004
SK		 4500 /* For ISP82XX, reset_chip is just disabling interrupts.
4501 * Driver waits for the completion of the commands.
4502 * the interrupts need to be enabled.
4503 */
7ec0effd 4504 if (!(IS_P3P_TYPE(ha)))
a9083016
GM		 4505 ha->isp_ops->reset_chip(vha);
4506
4507 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
4508 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
4509 atomic_set(&vha->loop_state, LOOP_DOWN);
4510 qla2x00_mark_all_devices_lost(vha, 0);
feafb7b1
AE		 4511
4512 spin_lock_irqsave(&ha->vport_slock, flags);
579d12b5 4513 list_for_each_entry(vp, &ha->vp_list, list) {
feafb7b1
AE		 4514 atomic_inc(&vp->vref_count);
4515 spin_unlock_irqrestore(&ha->vport_slock, flags);
4516
a9083016 4517 qla2x00_mark_all_devices_lost(vp, 0);
feafb7b1
AE		 4518
4519 spin_lock_irqsave(&ha->vport_slock, flags);
4520 atomic_dec(&vp->vref_count);
4521 }
4522 spin_unlock_irqrestore(&ha->vport_slock, flags);
a9083016
GM		 4523 } else {
4524 if (!atomic_read(&vha->loop_down_timer))
4525 atomic_set(&vha->loop_down_timer,
4526 LOOP_DOWN_TIME);
4527 }
4528
6aef87be
AV		 4529 /* Clear all async request states across all VPs. */
4530 list_for_each_entry(fcport, &vha->vp_fcports, list)
4531 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
4532 spin_lock_irqsave(&ha->vport_slock, flags);
4533 list_for_each_entry(vp, &ha->vp_list, list) {
4534 atomic_inc(&vp->vref_count);
4535 spin_unlock_irqrestore(&ha->vport_slock, flags);
4536
4537 list_for_each_entry(fcport, &vp->vp_fcports, list)
4538 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
4539
4540 spin_lock_irqsave(&ha->vport_slock, flags);
4541 atomic_dec(&vp->vref_count);
4542 }
4543 spin_unlock_irqrestore(&ha->vport_slock, flags);
4544
bddd2d65
LC		 4545 if (!ha->flags.eeh_busy) {
4546 /* Make sure for ISP 82XX IO DMA is complete */
7ec0effd 4547 if (IS_P3P_TYPE(ha)) {
7190575f 4548 qla82xx_chip_reset_cleanup(vha);
7c3df132
SK		 4549 ql_log(ql_log_info, vha, 0x00b4,
4550 "Done chip reset cleanup.\n");
a9083016 4551
e46ef004
SK		 4552 /* Done waiting for pending commands.
4553 * Reset the online flag.
4554 */
4555 vha->flags.online = 0;
4d78c973 4556 }
a9083016 4557
bddd2d65
LC		 4558 /* Requeue all commands in outstanding command list. */
4559 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
4560 }
a9083016
GM		 4561}
4562
1da177e4
LT		 4563/*
4564* qla2x00_abort_isp
4565* Resets ISP and aborts all outstanding commands.
4566*
4567* Input:
4568* ha = adapter block pointer.
4569*
4570* Returns:
4571* 0 = success
4572*/
4573int
e315cd28 4574qla2x00_abort_isp(scsi_qla_host_t *vha)
1da177e4 4575{
476e8978 4576 int rval;
1da177e4 4577 uint8_t status = 0;
e315cd28
AC		 4578 struct qla_hw_data *ha = vha->hw;
4579 struct scsi_qla_host *vp;
73208dfd 4580 struct req_que *req = ha->req_q_map[0];
feafb7b1 4581 unsigned long flags;
1da177e4 4582
e315cd28 4583 if (vha->flags.online) {
a9083016 4584 qla2x00_abort_isp_cleanup(vha);
1da177e4 4585
a6171297
SV		 4586 if (IS_QLA8031(ha)) {
4587 ql_dbg(ql_dbg_p3p, vha, 0xb05c,
4588 "Clearing fcoe driver presence.\n");
4589 if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS)
4590 ql_dbg(ql_dbg_p3p, vha, 0xb073,
4591 "Error while clearing DRV-Presence.\n");
4592 }
4593
85880801
AV		 4594 if (unlikely(pci_channel_offline(ha->pdev) &&
4595 ha->flags.pci_channel_io_perm_failure)) {
4596 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
4597 status = 0;
4598 return status;
4599 }
4600
73208dfd 4601 ha->isp_ops->get_flash_version(vha, req->ring);
30c47662 4602
e315cd28 4603 ha->isp_ops->nvram_config(vha);
1da177e4 4604
e315cd28
AC		 4605 if (!qla2x00_restart_isp(vha)) {
4606 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4 4607
e315cd28 4608 if (!atomic_read(&vha->loop_down_timer)) {
1da177e4
LT		 4609 /*
4610 * Issue marker command only when we are going
4611 * to start the I/O .
4612 */
e315cd28 4613 vha->marker_needed = 1;
1da177e4
LT		 4614 }
4615
e315cd28 4616 vha->flags.online = 1;
1da177e4 4617
fd34f556 4618 ha->isp_ops->enable_intrs(ha);
1da177e4 4619
fa2a1ce5 4620 ha->isp_abort_cnt = 0;
e315cd28 4621 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
476e8978 4622
6246b8a1
GM		 4623 if (IS_QLA81XX(ha) || IS_QLA8031(ha))
4624 qla2x00_get_fw_version(vha);
df613b96
AV		 4625 if (ha->fce) {
4626 ha->flags.fce_enabled = 1;
4627 memset(ha->fce, 0,
4628 fce_calc_size(ha->fce_bufs));
e315cd28 4629 rval = qla2x00_enable_fce_trace(vha,
df613b96
AV		 4630 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
4631 &ha->fce_bufs);
4632 if (rval) {
7c3df132 4633 ql_log(ql_log_warn, vha, 0x8033,
df613b96
AV		 4634 "Unable to reinitialize FCE "
4635 "(%d).\n", rval);
4636 ha->flags.fce_enabled = 0;
4637 }
4638 }
436a7b11
AV		 4639
4640 if (ha->eft) {
4641 memset(ha->eft, 0, EFT_SIZE);
e315cd28 4642 rval = qla2x00_enable_eft_trace(vha,
436a7b11
AV		 4643 ha->eft_dma, EFT_NUM_BUFFERS);
4644 if (rval) {
7c3df132 4645 ql_log(ql_log_warn, vha, 0x8034,
436a7b11
AV		 4646 "Unable to reinitialize EFT "
4647 "(%d).\n", rval);
4648 }
4649 }
1da177e4 4650 } else { /* failed the ISP abort */
e315cd28
AC		 4651 vha->flags.online = 1;
4652 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
1da177e4 4653 if (ha->isp_abort_cnt == 0) {
7c3df132
SK		 4654 ql_log(ql_log_fatal, vha, 0x8035,
4655 "ISP error recover failed - "
4656 "board disabled.\n");
fa2a1ce5 4657 /*
1da177e4
LT		 4658 * The next call disables the board
4659 * completely.
4660 */
e315cd28
AC		 4661 ha->isp_ops->reset_adapter(vha);
4662 vha->flags.online = 0;
1da177e4 4663 clear_bit(ISP_ABORT_RETRY,
e315cd28 4664 &vha->dpc_flags);
1da177e4
LT		 4665 status = 0;
4666 } else { /* schedule another ISP abort */
4667 ha->isp_abort_cnt--;
7c3df132
SK		 4668 ql_dbg(ql_dbg_taskm, vha, 0x8020,
4669 "ISP abort - retry remaining %d.\n",
4670 ha->isp_abort_cnt);
1da177e4
LT		 4671 status = 1;
4672 }
4673 } else {
4674 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
7c3df132
SK		 4675 ql_dbg(ql_dbg_taskm, vha, 0x8021,
4676 "ISP error recovery - retrying (%d) "
4677 "more times.\n", ha->isp_abort_cnt);
e315cd28 4678 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
1da177e4
LT		 4679 status = 1;
4680 }
4681 }
fa2a1ce5 4682
1da177e4
LT		 4683 }
4684
e315cd28 4685 if (!status) {
7c3df132 4686 ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__);
feafb7b1
AE		 4687
4688 spin_lock_irqsave(&ha->vport_slock, flags);
4689 list_for_each_entry(vp, &ha->vp_list, list) {
4690 if (vp->vp_idx) {
4691 atomic_inc(&vp->vref_count);
4692 spin_unlock_irqrestore(&ha->vport_slock, flags);
4693
e315cd28 4694 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 4695
4696 spin_lock_irqsave(&ha->vport_slock, flags);
4697 atomic_dec(&vp->vref_count);
4698 }
e315cd28 4699 }
feafb7b1
AE		 4700 spin_unlock_irqrestore(&ha->vport_slock, flags);
4701
7d613ac6
SV		 4702 if (IS_QLA8031(ha)) {
4703 ql_dbg(ql_dbg_p3p, vha, 0xb05d,
4704 "Setting back fcoe driver presence.\n");
4705 if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS)
4706 ql_dbg(ql_dbg_p3p, vha, 0xb074,
4707 "Error while setting DRV-Presence.\n");
4708 }
e315cd28 4709 } else {
d8424f68
JP		 4710 ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n",
4711 __func__);
1da177e4
LT		 4712 }
4713
4714 return(status);
4715}
4716
4717/*
4718* qla2x00_restart_isp
4719* restarts the ISP after a reset
4720*
4721* Input:
4722* ha = adapter block pointer.
4723*
4724* Returns:
4725* 0 = success
4726*/
4727static int
e315cd28 4728qla2x00_restart_isp(scsi_qla_host_t *vha)
1da177e4 4729{
c6b2fca8 4730 int status = 0;
1da177e4 4731 uint32_t wait_time;
e315cd28 4732 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 4733 struct req_que *req = ha->req_q_map[0];
4734 struct rsp_que *rsp = ha->rsp_q_map[0];
2d70c103 4735 unsigned long flags;
1da177e4
LT		 4736
4737 /* If firmware needs to be loaded */
e315cd28
AC		 4738 if (qla2x00_isp_firmware(vha)) {
4739 vha->flags.online = 0;
4740 status = ha->isp_ops->chip_diag(vha);
4741 if (!status)
4742 status = qla2x00_setup_chip(vha);
1da177e4
LT		 4743 }
4744
e315cd28
AC		 4745 if (!status && !(status = qla2x00_init_rings(vha))) {
4746 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
2533cf67 4747 ha->flags.chip_reset_done = 1;
73208dfd
AC		 4748 /* Initialize the queues in use */
4749 qla25xx_init_queues(ha);
4750
e315cd28
AC		 4751 status = qla2x00_fw_ready(vha);
4752 if (!status) {
7c3df132
SK		 4753 ql_dbg(ql_dbg_taskm, vha, 0x8031,
4754 "Start configure loop status = %d.\n", status);
0107109e
AV		 4755
4756 /* Issue a marker after FW becomes ready. */
73208dfd 4757 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
0107109e 4758
e315cd28 4759 vha->flags.online = 1;
2d70c103
NB		 4760
4761 /*
4762 * Process any ATIO queue entries that came in
4763 * while we weren't online.
4764 */
4765 spin_lock_irqsave(&ha->hardware_lock, flags);
4766 if (qla_tgt_mode_enabled(vha))
4767 qlt_24xx_process_atio_queue(vha);
4768 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4769
1da177e4
LT		 4770 /* Wait at most MAX_TARGET RSCNs for a stable link. */
4771 wait_time = 256;
4772 do {
e315cd28
AC		 4773 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
4774 qla2x00_configure_loop(vha);
1da177e4 4775 wait_time--;
e315cd28
AC		 4776 } while (!atomic_read(&vha->loop_down_timer) &&
4777 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
4778 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
4779 &vha->dpc_flags)));
1da177e4
LT		 4780 }
4781
4782 /* if no cable then assume it's good */
e315cd28 4783 if ((vha->device_flags & DFLG_NO_CABLE))
1da177e4
LT		 4784 status = 0;
4785
7c3df132
SK		 4786 ql_dbg(ql_dbg_taskm, vha, 0x8032,
4787 "Configure loop done, status = 0x%x.\n", status);
1da177e4
LT		 4788 }
4789 return (status);
4790}
4791
73208dfd
AC		 4792static int
4793qla25xx_init_queues(struct qla_hw_data *ha)
4794{
4795 struct rsp_que *rsp = NULL;
4796 struct req_que *req = NULL;
4797 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
4798 int ret = -1;
4799 int i;
4800
2afa19a9 4801 for (i = 1; i < ha->max_rsp_queues; i++) {
73208dfd
AC		 4802 rsp = ha->rsp_q_map[i];
4803 if (rsp) {
4804 rsp->options &= ~BIT_0;
618a7523 4805 ret = qla25xx_init_rsp_que(base_vha, rsp);
73208dfd 4806 if (ret != QLA_SUCCESS)
7c3df132
SK		 4807 ql_dbg(ql_dbg_init, base_vha, 0x00ff,
4808 "%s Rsp que: %d init failed.\n",
4809 __func__, rsp->id);
73208dfd 4810 else
7c3df132
SK		 4811 ql_dbg(ql_dbg_init, base_vha, 0x0100,
4812 "%s Rsp que: %d inited.\n",
4813 __func__, rsp->id);
73208dfd 4814 }
2afa19a9
AC		 4815 }
4816 for (i = 1; i < ha->max_req_queues; i++) {
73208dfd
AC		 4817 req = ha->req_q_map[i];
4818 if (req) {
29bdccbe 4819 /* Clear outstanding commands array. */
73208dfd 4820 req->options &= ~BIT_0;
618a7523 4821 ret = qla25xx_init_req_que(base_vha, req);
73208dfd 4822 if (ret != QLA_SUCCESS)
7c3df132
SK		 4823 ql_dbg(ql_dbg_init, base_vha, 0x0101,
4824 "%s Req que: %d init failed.\n",
4825 __func__, req->id);
73208dfd 4826 else
7c3df132
SK		 4827 ql_dbg(ql_dbg_init, base_vha, 0x0102,
4828 "%s Req que: %d inited.\n",
4829 __func__, req->id);
73208dfd
AC		 4830 }
4831 }
4832 return ret;
4833}
4834
1da177e4
LT		 4835/*
4836* qla2x00_reset_adapter
4837* Reset adapter.
4838*
4839* Input:
4840* ha = adapter block pointer.
4841*/
abbd8870 4842void
e315cd28 4843qla2x00_reset_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 4844{
4845 unsigned long flags = 0;
e315cd28 4846 struct qla_hw_data *ha = vha->hw;
3d71644c 4847 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 4848
e315cd28 4849 vha->flags.online = 0;
fd34f556 4850 ha->isp_ops->disable_intrs(ha);
1da177e4 4851
1da177e4
LT		 4852 spin_lock_irqsave(&ha->hardware_lock, flags);
4853 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
4854 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
4855 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
4856 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
4857 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4858}
0107109e
AV		 4859
4860void
e315cd28 4861qla24xx_reset_adapter(scsi_qla_host_t *vha)
0107109e
AV		 4862{
4863 unsigned long flags = 0;
e315cd28 4864 struct qla_hw_data *ha = vha->hw;
0107109e
AV		 4865 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
4866
7ec0effd 4867 if (IS_P3P_TYPE(ha))
a9083016
GM		 4868 return;
4869
e315cd28 4870 vha->flags.online = 0;
fd34f556 4871 ha->isp_ops->disable_intrs(ha);
0107109e
AV		 4872
4873 spin_lock_irqsave(&ha->hardware_lock, flags);
4874 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
4875 RD_REG_DWORD(&reg->hccr);
4876 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
4877 RD_REG_DWORD(&reg->hccr);
4878 spin_unlock_irqrestore(&ha->hardware_lock, flags);
09ff36d3
AV		 4879
4880 if (IS_NOPOLLING_TYPE(ha))
4881 ha->isp_ops->enable_intrs(ha);
0107109e
AV		 4882}
4883
4e08df3f
DM		 4884/* On sparc systems, obtain port and node WWN from firmware
4885 * properties.
4886 */
e315cd28
AC		 4887static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha,
4888 struct nvram_24xx *nv)
4e08df3f
DM		 4889{
4890#ifdef CONFIG_SPARC
e315cd28 4891 struct qla_hw_data *ha = vha->hw;
4e08df3f 4892 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 4893 struct device_node *dp = pci_device_to_OF_node(pdev);
4894 const u8 *val;
4e08df3f
DM		 4895 int len;
4896
4897 val = of_get_property(dp, "port-wwn", &len);
4898 if (val && len >= WWN_SIZE)
4899 memcpy(nv->port_name, val, WWN_SIZE);
4900
4901 val = of_get_property(dp, "node-wwn", &len);
4902 if (val && len >= WWN_SIZE)
4903 memcpy(nv->node_name, val, WWN_SIZE);
4904#endif
4905}
4906
0107109e 4907int
e315cd28 4908qla24xx_nvram_config(scsi_qla_host_t *vha)
0107109e 4909{
4e08df3f 4910 int rval;
0107109e
AV		 4911 struct init_cb_24xx *icb;
4912 struct nvram_24xx *nv;
4913 uint32_t *dptr;
4914 uint8_t *dptr1, *dptr2;
4915 uint32_t chksum;
4916 uint16_t cnt;
e315cd28 4917 struct qla_hw_data *ha = vha->hw;
0107109e 4918
4e08df3f 4919 rval = QLA_SUCCESS;
0107109e 4920 icb = (struct init_cb_24xx *)ha->init_cb;
281afe19 4921 nv = ha->nvram;
0107109e
AV		 4922
4923 /* Determine NVRAM starting address. */
f73cb695 4924 if (ha->port_no == 0) {
e5b68a61
AC		 4925 ha->nvram_base = FA_NVRAM_FUNC0_ADDR;
4926 ha->vpd_base = FA_NVRAM_VPD0_ADDR;
4927 } else {
0107109e 4928 ha->nvram_base = FA_NVRAM_FUNC1_ADDR;
6f641790
AV		 4929 ha->vpd_base = FA_NVRAM_VPD1_ADDR;
4930 }
f73cb695 4931
e5b68a61
AC		 4932 ha->nvram_size = sizeof(struct nvram_24xx);
4933 ha->vpd_size = FA_NVRAM_VPD_SIZE;
0107109e 4934
281afe19
SJ		 4935 /* Get VPD data into cache */
4936 ha->vpd = ha->nvram + VPD_OFFSET;
e315cd28 4937 ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd,
281afe19
SJ		 4938 ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
4939
4940 /* Get NVRAM data into cache and calculate checksum. */
0107109e 4941 dptr = (uint32_t *)nv;
e315cd28 4942 ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base,
0107109e
AV		 4943 ha->nvram_size);
4944 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
4945 chksum += le32_to_cpu(*dptr++);
4946
7c3df132
SK		 4947 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
4948 "Contents of NVRAM\n");
4949 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
4950 (uint8_t *)nv, ha->nvram_size);
0107109e
AV		 4951
4952 /* Bad NVRAM data, set defaults parameters. */
4953 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
4954 || nv->id[3] != ' ' ||
4955 nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
4956 /* Reset NVRAM data. */
7c3df132 4957 ql_log(ql_log_warn, vha, 0x006b,
9e336520 4958 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132
SK		 4959 "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version);
4960 ql_log(ql_log_warn, vha, 0x006c,
4961 "Falling back to functioning (yet invalid -- WWPN) "
4962 "defaults.\n");
4e08df3f
DM		 4963
4964 /*
4965 * Set default initialization control block.
4966 */
4967 memset(nv, 0, ha->nvram_size);
4968 nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
4969 nv->version = __constant_cpu_to_le16(ICB_VERSION);
4970 nv->frame_payload_size = __constant_cpu_to_le16(2048);
4971 nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
4972 nv->exchange_count = __constant_cpu_to_le16(0);
4973 nv->hard_address = __constant_cpu_to_le16(124);
4974 nv->port_name[0] = 0x21;
f73cb695 4975 nv->port_name[1] = 0x00 + ha->port_no + 1;
4e08df3f
DM		 4976 nv->port_name[2] = 0x00;
4977 nv->port_name[3] = 0xe0;
4978 nv->port_name[4] = 0x8b;
4979 nv->port_name[5] = 0x1c;
4980 nv->port_name[6] = 0x55;
4981 nv->port_name[7] = 0x86;
4982 nv->node_name[0] = 0x20;
4983 nv->node_name[1] = 0x00;
4984 nv->node_name[2] = 0x00;
4985 nv->node_name[3] = 0xe0;
4986 nv->node_name[4] = 0x8b;
4987 nv->node_name[5] = 0x1c;
4988 nv->node_name[6] = 0x55;
4989 nv->node_name[7] = 0x86;
e315cd28 4990 qla24xx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 4991 nv->login_retry_count = __constant_cpu_to_le16(8);
4992 nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
4993 nv->login_timeout = __constant_cpu_to_le16(0);
4994 nv->firmware_options_1 =
4995 __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
4996 nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
4997 nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
4998 nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
4999 nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
5000 nv->efi_parameters = __constant_cpu_to_le32(0);
5001 nv->reset_delay = 5;
5002 nv->max_luns_per_target = __constant_cpu_to_le16(128);
5003 nv->port_down_retry_count = __constant_cpu_to_le16(30);
5004 nv->link_down_timeout = __constant_cpu_to_le16(30);
5005
5006 rval = 1;
0107109e
AV		 5007 }
5008
2d70c103
NB		 5009 if (!qla_ini_mode_enabled(vha)) {
5010 /* Don't enable full login after initial LIP */
5011 nv->firmware_options_1 &= __constant_cpu_to_le32(~BIT_13);
5012 /* Don't enable LIP full login for initiator */
5013 nv->host_p &= __constant_cpu_to_le32(~BIT_10);
5014 }
5015
5016 qlt_24xx_config_nvram_stage1(vha, nv);
5017
0107109e 5018 /* Reset Initialization control block */
e315cd28 5019 memset(icb, 0, ha->init_cb_size);
0107109e
AV		 5020
5021 /* Copy 1st segment. */
5022 dptr1 = (uint8_t *)icb;
5023 dptr2 = (uint8_t *)&nv->version;
5024 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
5025 while (cnt--)
5026 *dptr1++ = *dptr2++;
5027
5028 icb->login_retry_count = nv->login_retry_count;
3ea66e28 5029 icb->link_down_on_nos = nv->link_down_on_nos;
0107109e
AV		 5030
5031 /* Copy 2nd segment. */
5032 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
5033 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
5034 cnt = (uint8_t *)&icb->reserved_3 -
5035 (uint8_t *)&icb->interrupt_delay_timer;
5036 while (cnt--)
5037 *dptr1++ = *dptr2++;
5038
5039 /*
5040 * Setup driver NVRAM options.
5041 */
e315cd28 5042 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
9bb9fcf2 5043 "QLA2462");
0107109e 5044
2d70c103
NB		 5045 qlt_24xx_config_nvram_stage2(vha, icb);
5046
5341e868 5047 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
2d70c103 5048 /* Use alternate WWN? */
5341e868
AV		 5049 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
5050 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
5051 }
5052
0107109e 5053 /* Prepare nodename */
fd0e7e4d 5054 if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
0107109e
AV		 5055 /*
5056 * Firmware will apply the following mask if the nodename was
5057 * not provided.
5058 */
5059 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
5060 icb->node_name[0] &= 0xF0;
5061 }
5062
5063 /* Set host adapter parameters. */
5064 ha->flags.disable_risc_code_load = 0;
0c8c39af
AV		 5065 ha->flags.enable_lip_reset = 0;
5066 ha->flags.enable_lip_full_login =
5067 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
5068 ha->flags.enable_target_reset =
5069 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
0107109e 5070 ha->flags.enable_led_scheme = 0;
d4c760c2 5071 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
0107109e 5072
fd0e7e4d
AV		 5073 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
5074 (BIT_6 | BIT_5 | BIT_4)) >> 4;
0107109e
AV		 5075
5076 memcpy(ha->fw_seriallink_options24, nv->seriallink_options,
5077 sizeof(ha->fw_seriallink_options24));
5078
5079 /* save HBA serial number */
5080 ha->serial0 = icb->port_name[5];
5081 ha->serial1 = icb->port_name[6];
5082 ha->serial2 = icb->port_name[7];
e315cd28
AC		 5083 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
5084 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
0107109e 5085
bc8fb3cb
AV		 5086 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
5087
0107109e
AV		 5088 ha->retry_count = le16_to_cpu(nv->login_retry_count);
5089
5090 /* Set minimum login_timeout to 4 seconds. */
5091 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
5092 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
5093 if (le16_to_cpu(nv->login_timeout) < 4)
5094 nv->login_timeout = __constant_cpu_to_le16(4);
5095 ha->login_timeout = le16_to_cpu(nv->login_timeout);
c6852c4c 5096 icb->login_timeout = nv->login_timeout;
0107109e 5097
00a537b8
AV		 5098 /* Set minimum RATOV to 100 tenths of a second. */
5099 ha->r_a_tov = 100;
0107109e
AV		 5100
5101 ha->loop_reset_delay = nv->reset_delay;
5102
5103 /* Link Down Timeout = 0:
5104 *
5105 * When Port Down timer expires we will start returning
5106 * I/O's to OS with "DID_NO_CONNECT".
5107 *
5108 * Link Down Timeout != 0:
5109 *
5110 * The driver waits for the link to come up after link down
5111 * before returning I/Os to OS with "DID_NO_CONNECT".
5112 */
5113 if (le16_to_cpu(nv->link_down_timeout) == 0) {
5114 ha->loop_down_abort_time =
5115 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
5116 } else {
5117 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
5118 ha->loop_down_abort_time =
5119 (LOOP_DOWN_TIME - ha->link_down_timeout);
5120 }
5121
5122 /* Need enough time to try and get the port back. */
5123 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
5124 if (qlport_down_retry)
5125 ha->port_down_retry_count = qlport_down_retry;
5126
5127 /* Set login_retry_count */
5128 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
5129 if (ha->port_down_retry_count ==
5130 le16_to_cpu(nv->port_down_retry_count) &&
5131 ha->port_down_retry_count > 3)
5132 ha->login_retry_count = ha->port_down_retry_count;
5133 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
5134 ha->login_retry_count = ha->port_down_retry_count;
5135 if (ql2xloginretrycount)
5136 ha->login_retry_count = ql2xloginretrycount;
5137
4fdfefe5 5138 /* Enable ZIO. */
e315cd28 5139 if (!vha->flags.init_done) {
4fdfefe5
AV		 5140 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
5141 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
5142 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
5143 le16_to_cpu(icb->interrupt_delay_timer): 2;
5144 }
5145 icb->firmware_options_2 &= __constant_cpu_to_le32(
5146 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
e315cd28 5147 vha->flags.process_response_queue = 0;
4fdfefe5 5148 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d
AV		 5149 ha->zio_mode = QLA_ZIO_MODE_6;
5150
7c3df132 5151 ql_log(ql_log_info, vha, 0x006f,
4fdfefe5
AV		 5152 "ZIO mode %d enabled; timer delay (%d us).\n",
5153 ha->zio_mode, ha->zio_timer * 100);
5154
5155 icb->firmware_options_2 |= cpu_to_le32(
5156 (uint32_t)ha->zio_mode);
5157 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
e315cd28 5158 vha->flags.process_response_queue = 1;
4fdfefe5
AV		 5159 }
5160
4e08df3f 5161 if (rval) {
7c3df132
SK		 5162 ql_log(ql_log_warn, vha, 0x0070,
5163 "NVRAM configuration failed.\n");
4e08df3f
DM		 5164 }
5165 return (rval);
0107109e
AV		 5166}
5167
413975a0 5168static int
cbc8eb67
AV		 5169qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
5170 uint32_t faddr)
d1c61909 5171{
73208dfd 5172 int rval = QLA_SUCCESS;
d1c61909 5173 int segments, fragment;
d1c61909
AV		 5174 uint32_t *dcode, dlen;
5175 uint32_t risc_addr;
5176 uint32_t risc_size;
5177 uint32_t i;
e315cd28 5178 struct qla_hw_data *ha = vha->hw;
73208dfd 5179 struct req_que *req = ha->req_q_map[0];
eaac30be 5180
7c3df132 5181 ql_dbg(ql_dbg_init, vha, 0x008b,
cfb0919c 5182 "FW: Loading firmware from flash (%x).\n", faddr);
eaac30be 5183
d1c61909
AV		 5184 rval = QLA_SUCCESS;
5185
5186 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 5187 dcode = (uint32_t *)req->ring;
d1c61909
AV		 5188 *srisc_addr = 0;
5189
5190 /* Validate firmware image by checking version. */
e315cd28 5191 qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
d1c61909
AV		 5192 for (i = 0; i < 4; i++)
5193 dcode[i] = be32_to_cpu(dcode[i]);
5194 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
5195 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
5196 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
5197 dcode[3] == 0)) {
7c3df132
SK		 5198 ql_log(ql_log_fatal, vha, 0x008c,
5199 "Unable to verify the integrity of flash firmware "
5200 "image.\n");
5201 ql_log(ql_log_fatal, vha, 0x008d,
5202 "Firmware data: %08x %08x %08x %08x.\n",
5203 dcode[0], dcode[1], dcode[2], dcode[3]);
d1c61909
AV		 5204
5205 return QLA_FUNCTION_FAILED;
5206 }
5207
5208 while (segments && rval == QLA_SUCCESS) {
5209 /* Read segment's load information. */
e315cd28 5210 qla24xx_read_flash_data(vha, dcode, faddr, 4);
d1c61909
AV		 5211
5212 risc_addr = be32_to_cpu(dcode[2]);
5213 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
5214 risc_size = be32_to_cpu(dcode[3]);
5215
5216 fragment = 0;
5217 while (risc_size > 0 && rval == QLA_SUCCESS) {
5218 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
5219 if (dlen > risc_size)
5220 dlen = risc_size;
5221
7c3df132
SK		 5222 ql_dbg(ql_dbg_init, vha, 0x008e,
5223 "Loading risc segment@ risc addr %x "
5224 "number of dwords 0x%x offset 0x%x.\n",
5225 risc_addr, dlen, faddr);
d1c61909 5226
e315cd28 5227 qla24xx_read_flash_data(vha, dcode, faddr, dlen);
d1c61909
AV		 5228 for (i = 0; i < dlen; i++)
5229 dcode[i] = swab32(dcode[i]);
5230
73208dfd 5231 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
d1c61909
AV		 5232 dlen);
5233 if (rval) {
7c3df132
SK		 5234 ql_log(ql_log_fatal, vha, 0x008f,
5235 "Failed to load segment %d of firmware.\n",
5236 fragment);
d1c61909
AV		 5237 break;
5238 }
5239
5240 faddr += dlen;
5241 risc_addr += dlen;
5242 risc_size -= dlen;
5243 fragment++;
5244 }
5245
5246 /* Next segment. */
5247 segments--;
5248 }
5249
f73cb695
CD		 5250 if (!IS_QLA27XX(ha))
5251 return rval;
5252
5253 if (ha->fw_dump_template)
5254 vfree(ha->fw_dump_template);
5255 ha->fw_dump_template = NULL;
5256 ha->fw_dump_template_len = 0;
5257
5258 ql_dbg(ql_dbg_init, vha, 0x0161,
5259 "Loading fwdump template from %x\n", faddr);
5260 qla24xx_read_flash_data(vha, dcode, faddr, 7);
5261 risc_size = be32_to_cpu(dcode[2]);
5262 ql_dbg(ql_dbg_init, vha, 0x0162,
5263 "-> array size %x dwords\n", risc_size);
5264 if (risc_size == 0 || risc_size == ~0)
5265 goto default_template;
5266
5267 dlen = (risc_size - 8) * sizeof(*dcode);
5268 ql_dbg(ql_dbg_init, vha, 0x0163,
5269 "-> template allocating %x bytes...\n", dlen);
5270 ha->fw_dump_template = vmalloc(dlen);
5271 if (!ha->fw_dump_template) {
5272 ql_log(ql_log_warn, vha, 0x0164,
5273 "Failed fwdump template allocate %x bytes.\n", risc_size);
5274 goto default_template;
5275 }
5276
5277 faddr += 7;
5278 risc_size -= 8;
5279 dcode = ha->fw_dump_template;
5280 qla24xx_read_flash_data(vha, dcode, faddr, risc_size);
5281 for (i = 0; i < risc_size; i++)
5282 dcode[i] = le32_to_cpu(dcode[i]);
5283
5284 if (!qla27xx_fwdt_template_valid(dcode)) {
5285 ql_log(ql_log_warn, vha, 0x0165,
5286 "Failed fwdump template validate\n");
5287 goto default_template;
5288 }
5289
5290 dlen = qla27xx_fwdt_template_size(dcode);
5291 ql_dbg(ql_dbg_init, vha, 0x0166,
5292 "-> template size %x bytes\n", dlen);
5293 if (dlen > risc_size * sizeof(*dcode)) {
5294 ql_log(ql_log_warn, vha, 0x0167,
97ea702b
CD		 5295 "Failed fwdump template exceeds array by %x bytes\n",
5296 (uint32_t)(dlen - risc_size * sizeof(*dcode)));
f73cb695
CD		 5297 goto default_template;
5298 }
5299 ha->fw_dump_template_len = dlen;
5300 return rval;
5301
5302default_template:
5303 ql_log(ql_log_warn, vha, 0x0168, "Using default fwdump template\n");
5304 if (ha->fw_dump_template)
5305 vfree(ha->fw_dump_template);
5306 ha->fw_dump_template = NULL;
5307 ha->fw_dump_template_len = 0;
5308
5309 dlen = qla27xx_fwdt_template_default_size();
5310 ql_dbg(ql_dbg_init, vha, 0x0169,
5311 "-> template allocating %x bytes...\n", dlen);
5312 ha->fw_dump_template = vmalloc(dlen);
5313 if (!ha->fw_dump_template) {
5314 ql_log(ql_log_warn, vha, 0x016a,
5315 "Failed fwdump template allocate %x bytes.\n", risc_size);
5316 goto failed_template;
5317 }
5318
5319 dcode = ha->fw_dump_template;
5320 risc_size = dlen / sizeof(*dcode);
5321 memcpy(dcode, qla27xx_fwdt_template_default(), dlen);
5322 for (i = 0; i < risc_size; i++)
5323 dcode[i] = be32_to_cpu(dcode[i]);
5324
5325 if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) {
5326 ql_log(ql_log_warn, vha, 0x016b,
5327 "Failed fwdump template validate\n");
5328 goto failed_template;
5329 }
5330
5331 dlen = qla27xx_fwdt_template_size(ha->fw_dump_template);
5332 ql_dbg(ql_dbg_init, vha, 0x016c,
5333 "-> template size %x bytes\n", dlen);
5334 ha->fw_dump_template_len = dlen;
5335 return rval;
5336
5337failed_template:
5338 ql_log(ql_log_warn, vha, 0x016d, "Failed default fwdump template\n");
5339 if (ha->fw_dump_template)
5340 vfree(ha->fw_dump_template);
5341 ha->fw_dump_template = NULL;
5342 ha->fw_dump_template_len = 0;
d1c61909
AV		 5343 return rval;
5344}
5345
e9454a88 5346#define QLA_FW_URL "http://ldriver.qlogic.com/firmware/"
d1c61909 5347
0107109e 5348int
e315cd28 5349qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5433383e
AV		 5350{
5351 int rval;
5352 int i, fragment;
5353 uint16_t *wcode, *fwcode;
5354 uint32_t risc_addr, risc_size, fwclen, wlen, *seg;
5355 struct fw_blob *blob;
e315cd28 5356 struct qla_hw_data *ha = vha->hw;
73208dfd 5357 struct req_que *req = ha->req_q_map[0];
5433383e
AV		 5358
5359 /* Load firmware blob. */
e315cd28 5360 blob = qla2x00_request_firmware(vha);
5433383e 5361 if (!blob) {
7c3df132
SK		 5362 ql_log(ql_log_info, vha, 0x0083,
5363 "Fimware image unavailable.\n");
5364 ql_log(ql_log_info, vha, 0x0084,
5365 "Firmware images can be retrieved from: "QLA_FW_URL ".\n");
5433383e
AV		 5366 return QLA_FUNCTION_FAILED;
5367 }
5368
5369 rval = QLA_SUCCESS;
5370
73208dfd 5371 wcode = (uint16_t *)req->ring;
5433383e
AV		 5372 *srisc_addr = 0;
5373 fwcode = (uint16_t *)blob->fw->data;
5374 fwclen = 0;
5375
5376 /* Validate firmware image by checking version. */
5377 if (blob->fw->size < 8 * sizeof(uint16_t)) {
7c3df132
SK		 5378 ql_log(ql_log_fatal, vha, 0x0085,
5379 "Unable to verify integrity of firmware image (%Zd).\n",
5433383e
AV		 5380 blob->fw->size);
5381 goto fail_fw_integrity;
5382 }
5383 for (i = 0; i < 4; i++)
5384 wcode[i] = be16_to_cpu(fwcode[i + 4]);
5385 if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff &&
5386 wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 &&
5387 wcode[2] == 0 && wcode[3] == 0)) {
7c3df132
SK		 5388 ql_log(ql_log_fatal, vha, 0x0086,
5389 "Unable to verify integrity of firmware image.\n");
5390 ql_log(ql_log_fatal, vha, 0x0087,
5391 "Firmware data: %04x %04x %04x %04x.\n",
5392 wcode[0], wcode[1], wcode[2], wcode[3]);
5433383e
AV		 5393 goto fail_fw_integrity;
5394 }
5395
5396 seg = blob->segs;
5397 while (*seg && rval == QLA_SUCCESS) {
5398 risc_addr = *seg;
5399 *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr;
5400 risc_size = be16_to_cpu(fwcode[3]);
5401
5402 /* Validate firmware image size. */
5403 fwclen += risc_size * sizeof(uint16_t);
5404 if (blob->fw->size < fwclen) {
7c3df132 5405 ql_log(ql_log_fatal, vha, 0x0088,
5433383e 5406 "Unable to verify integrity of firmware image "
7c3df132 5407 "(%Zd).\n", blob->fw->size);
5433383e
AV		 5408 goto fail_fw_integrity;
5409 }
5410
5411 fragment = 0;
5412 while (risc_size > 0 && rval == QLA_SUCCESS) {
5413 wlen = (uint16_t)(ha->fw_transfer_size >> 1);
5414 if (wlen > risc_size)
5415 wlen = risc_size;
7c3df132
SK		 5416 ql_dbg(ql_dbg_init, vha, 0x0089,
5417 "Loading risc segment@ risc addr %x number of "
5418 "words 0x%x.\n", risc_addr, wlen);
5433383e
AV		 5419
5420 for (i = 0; i < wlen; i++)
5421 wcode[i] = swab16(fwcode[i]);
5422
73208dfd 5423 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
5433383e
AV		 5424 wlen);
5425 if (rval) {
7c3df132
SK		 5426 ql_log(ql_log_fatal, vha, 0x008a,
5427 "Failed to load segment %d of firmware.\n",
5428 fragment);
5433383e
AV		 5429 break;
5430 }
5431
5432 fwcode += wlen;
5433 risc_addr += wlen;
5434 risc_size -= wlen;
5435 fragment++;
5436 }
5437
5438 /* Next segment. */
5439 seg++;
5440 }
5441 return rval;
5442
5443fail_fw_integrity:
5444 return QLA_FUNCTION_FAILED;
5445}
5446
eaac30be
AV		 5447static int
5448qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
0107109e
AV		 5449{
5450 int rval;
5451 int segments, fragment;
5452 uint32_t *dcode, dlen;
5453 uint32_t risc_addr;
5454 uint32_t risc_size;
5455 uint32_t i;
5433383e 5456 struct fw_blob *blob;
f73cb695
CD		 5457 const uint32_t *fwcode;
5458 uint32_t fwclen;
e315cd28 5459 struct qla_hw_data *ha = vha->hw;
73208dfd 5460 struct req_que *req = ha->req_q_map[0];
0107109e 5461
5433383e 5462 /* Load firmware blob. */
e315cd28 5463 blob = qla2x00_request_firmware(vha);
5433383e 5464 if (!blob) {
7c3df132
SK		 5465 ql_log(ql_log_warn, vha, 0x0090,
5466 "Fimware image unavailable.\n");
5467 ql_log(ql_log_warn, vha, 0x0091,
5468 "Firmware images can be retrieved from: "
5469 QLA_FW_URL ".\n");
d1c61909 5470
eaac30be 5471 return QLA_FUNCTION_FAILED;
0107109e
AV		 5472 }
5473
cfb0919c
CD		 5474 ql_dbg(ql_dbg_init, vha, 0x0092,
5475 "FW: Loading via request-firmware.\n");
eaac30be 5476
0107109e
AV		 5477 rval = QLA_SUCCESS;
5478
5479 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 5480 dcode = (uint32_t *)req->ring;
0107109e 5481 *srisc_addr = 0;
5433383e 5482 fwcode = (uint32_t *)blob->fw->data;
0107109e
AV		 5483 fwclen = 0;
5484
5485 /* Validate firmware image by checking version. */
5433383e 5486 if (blob->fw->size < 8 * sizeof(uint32_t)) {
7c3df132
SK		 5487 ql_log(ql_log_fatal, vha, 0x0093,
5488 "Unable to verify integrity of firmware image (%Zd).\n",
5433383e 5489 blob->fw->size);
f73cb695 5490 return QLA_FUNCTION_FAILED;
0107109e
AV		 5491 }
5492 for (i = 0; i < 4; i++)
5493 dcode[i] = be32_to_cpu(fwcode[i + 4]);
5494 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
5495 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
5496 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
5497 dcode[3] == 0)) {
7c3df132
SK		 5498 ql_log(ql_log_fatal, vha, 0x0094,
5499 "Unable to verify integrity of firmware image (%Zd).\n",
5500 blob->fw->size);
5501 ql_log(ql_log_fatal, vha, 0x0095,
5502 "Firmware data: %08x %08x %08x %08x.\n",
5503 dcode[0], dcode[1], dcode[2], dcode[3]);
f73cb695 5504 return QLA_FUNCTION_FAILED;
0107109e
AV		 5505 }
5506
5507 while (segments && rval == QLA_SUCCESS) {
5508 risc_addr = be32_to_cpu(fwcode[2]);
5509 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
5510 risc_size = be32_to_cpu(fwcode[3]);
5511
5512 /* Validate firmware image size. */
5513 fwclen += risc_size * sizeof(uint32_t);
5433383e 5514 if (blob->fw->size < fwclen) {
7c3df132 5515 ql_log(ql_log_fatal, vha, 0x0096,
5433383e 5516 "Unable to verify integrity of firmware image "
7c3df132 5517 "(%Zd).\n", blob->fw->size);
f73cb695 5518 return QLA_FUNCTION_FAILED;
0107109e
AV		 5519 }
5520
5521 fragment = 0;
5522 while (risc_size > 0 && rval == QLA_SUCCESS) {
5523 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
5524 if (dlen > risc_size)
5525 dlen = risc_size;
5526
7c3df132
SK		 5527 ql_dbg(ql_dbg_init, vha, 0x0097,
5528 "Loading risc segment@ risc addr %x "
5529 "number of dwords 0x%x.\n", risc_addr, dlen);
0107109e
AV		 5530
5531 for (i = 0; i < dlen; i++)
5532 dcode[i] = swab32(fwcode[i]);
5533
73208dfd 5534 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
590f98e5 5535 dlen);
0107109e 5536 if (rval) {
7c3df132
SK		 5537 ql_log(ql_log_fatal, vha, 0x0098,
5538 "Failed to load segment %d of firmware.\n",
5539 fragment);
0107109e
AV		 5540 break;
5541 }
5542
5543 fwcode += dlen;
5544 risc_addr += dlen;
5545 risc_size -= dlen;
5546 fragment++;
5547 }
5548
5549 /* Next segment. */
5550 segments--;
5551 }
f73cb695
CD		 5552
5553 if (!IS_QLA27XX(ha))
5554 return rval;
5555
5556 if (ha->fw_dump_template)
5557 vfree(ha->fw_dump_template);
5558 ha->fw_dump_template = NULL;
5559 ha->fw_dump_template_len = 0;
5560
5561 ql_dbg(ql_dbg_init, vha, 0x171,
97ea702b
CD		 5562 "Loading fwdump template from %x\n",
5563 (uint32_t)((void *)fwcode - (void *)blob->fw->data));
f73cb695
CD		 5564 risc_size = be32_to_cpu(fwcode[2]);
5565 ql_dbg(ql_dbg_init, vha, 0x172,
5566 "-> array size %x dwords\n", risc_size);
5567 if (risc_size == 0 || risc_size == ~0)
5568 goto default_template;
5569
5570 dlen = (risc_size - 8) * sizeof(*fwcode);
5571 ql_dbg(ql_dbg_init, vha, 0x0173,
5572 "-> template allocating %x bytes...\n", dlen);
5573 ha->fw_dump_template = vmalloc(dlen);
5574 if (!ha->fw_dump_template) {
5575 ql_log(ql_log_warn, vha, 0x0174,
5576 "Failed fwdump template allocate %x bytes.\n", risc_size);
5577 goto default_template;
5578 }
5579
5580 fwcode += 7;
5581 risc_size -= 8;
5582 dcode = ha->fw_dump_template;
5583 for (i = 0; i < risc_size; i++)
5584 dcode[i] = le32_to_cpu(fwcode[i]);
5585
5586 if (!qla27xx_fwdt_template_valid(dcode)) {
5587 ql_log(ql_log_warn, vha, 0x0175,
5588 "Failed fwdump template validate\n");
5589 goto default_template;
5590 }
5591
5592 dlen = qla27xx_fwdt_template_size(dcode);
5593 ql_dbg(ql_dbg_init, vha, 0x0176,
5594 "-> template size %x bytes\n", dlen);
5595 if (dlen > risc_size * sizeof(*fwcode)) {
5596 ql_log(ql_log_warn, vha, 0x0177,
97ea702b
CD		 5597 "Failed fwdump template exceeds array by %x bytes\n",
5598 (uint32_t)(dlen - risc_size * sizeof(*fwcode)));
f73cb695
CD		 5599 goto default_template;
5600 }
5601 ha->fw_dump_template_len = dlen;
0107109e
AV		 5602 return rval;
5603
f73cb695
CD		 5604default_template:
5605 ql_log(ql_log_warn, vha, 0x0178, "Using default fwdump template\n");
5606 if (ha->fw_dump_template)
5607 vfree(ha->fw_dump_template);
5608 ha->fw_dump_template = NULL;
5609 ha->fw_dump_template_len = 0;
5610
5611 dlen = qla27xx_fwdt_template_default_size();
5612 ql_dbg(ql_dbg_init, vha, 0x0179,
5613 "-> template allocating %x bytes...\n", dlen);
5614 ha->fw_dump_template = vmalloc(dlen);
5615 if (!ha->fw_dump_template) {
5616 ql_log(ql_log_warn, vha, 0x017a,
5617 "Failed fwdump template allocate %x bytes.\n", risc_size);
5618 goto failed_template;
5619 }
5620
5621 dcode = ha->fw_dump_template;
5622 risc_size = dlen / sizeof(*fwcode);
5623 fwcode = qla27xx_fwdt_template_default();
5624 for (i = 0; i < risc_size; i++)
5625 dcode[i] = be32_to_cpu(fwcode[i]);
5626
5627 if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) {
5628 ql_log(ql_log_warn, vha, 0x017b,
5629 "Failed fwdump template validate\n");
5630 goto failed_template;
5631 }
5632
5633 dlen = qla27xx_fwdt_template_size(ha->fw_dump_template);
5634 ql_dbg(ql_dbg_init, vha, 0x017c,
5635 "-> template size %x bytes\n", dlen);
5636 ha->fw_dump_template_len = dlen;
5637 return rval;
5638
5639failed_template:
5640 ql_log(ql_log_warn, vha, 0x017d, "Failed default fwdump template\n");
5641 if (ha->fw_dump_template)
5642 vfree(ha->fw_dump_template);
5643 ha->fw_dump_template = NULL;
5644 ha->fw_dump_template_len = 0;
5645 return rval;
0107109e 5646}
18c6c127 5647
eaac30be
AV		 5648int
5649qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5650{
5651 int rval;
5652
e337d907
AV		 5653 if (ql2xfwloadbin == 1)
5654 return qla81xx_load_risc(vha, srisc_addr);
5655
eaac30be
AV		 5656 /*
5657 * FW Load priority:
5658 * 1) Firmware via request-firmware interface (.bin file).
5659 * 2) Firmware residing in flash.
5660 */
5661 rval = qla24xx_load_risc_blob(vha, srisc_addr);
5662 if (rval == QLA_SUCCESS)
5663 return rval;
5664
cbc8eb67
AV		 5665 return qla24xx_load_risc_flash(vha, srisc_addr,
5666 vha->hw->flt_region_fw);
eaac30be
AV		 5667}
5668
5669int
5670qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5671{
5672 int rval;
cbc8eb67 5673 struct qla_hw_data *ha = vha->hw;
eaac30be 5674
e337d907 5675 if (ql2xfwloadbin == 2)
cbc8eb67 5676 goto try_blob_fw;
e337d907 5677
eaac30be
AV		 5678 /*
5679 * FW Load priority:
5680 * 1) Firmware residing in flash.
5681 * 2) Firmware via request-firmware interface (.bin file).
cbc8eb67 5682 * 3) Golden-Firmware residing in flash -- limited operation.
eaac30be 5683 */
cbc8eb67 5684 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
eaac30be
AV		 5685 if (rval == QLA_SUCCESS)
5686 return rval;
5687
cbc8eb67
AV		 5688try_blob_fw:
5689 rval = qla24xx_load_risc_blob(vha, srisc_addr);
5690 if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw)
5691 return rval;
5692
7c3df132
SK		 5693 ql_log(ql_log_info, vha, 0x0099,
5694 "Attempting to fallback to golden firmware.\n");
cbc8eb67
AV		 5695 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
5696 if (rval != QLA_SUCCESS)
5697 return rval;
5698
7c3df132 5699 ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n");
cbc8eb67 5700 ha->flags.running_gold_fw = 1;
cbc8eb67 5701 return rval;
eaac30be
AV		 5702}
5703
18c6c127 5704void
e315cd28 5705qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha)
18c6c127
AV		 5706{
5707 int ret, retries;
e315cd28 5708 struct qla_hw_data *ha = vha->hw;
18c6c127 5709
85880801
AV		 5710 if (ha->flags.pci_channel_io_perm_failure)
5711 return;
e428924c 5712 if (!IS_FWI2_CAPABLE(ha))
18c6c127 5713 return;
75edf81d
AV		 5714 if (!ha->fw_major_version)
5715 return;
18c6c127 5716
e315cd28 5717 ret = qla2x00_stop_firmware(vha);
7c7f1f29 5718 for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&
b469a7cb 5719 ret != QLA_INVALID_COMMAND && retries ; retries--) {
e315cd28
AC		 5720 ha->isp_ops->reset_chip(vha);
5721 if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS)
18c6c127 5722 continue;
e315cd28 5723 if (qla2x00_setup_chip(vha) != QLA_SUCCESS)
18c6c127 5724 continue;
7c3df132
SK		 5725 ql_log(ql_log_info, vha, 0x8015,
5726 "Attempting retry of stop-firmware command.\n");
e315cd28 5727 ret = qla2x00_stop_firmware(vha);
18c6c127
AV		 5728 }
5729}
2c3dfe3f
SJ		 5730
5731int
e315cd28 5732qla24xx_configure_vhba(scsi_qla_host_t *vha)
2c3dfe3f
SJ		 5733{
5734 int rval = QLA_SUCCESS;
0b91d116 5735 int rval2;
2c3dfe3f 5736 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28
AC		 5737 struct qla_hw_data *ha = vha->hw;
5738 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
67c2e93a
AC		 5739 struct req_que *req;
5740 struct rsp_que *rsp;
2c3dfe3f 5741
e315cd28 5742 if (!vha->vp_idx)
2c3dfe3f
SJ		 5743 return -EINVAL;
5744
e315cd28 5745 rval = qla2x00_fw_ready(base_vha);
7163ea81 5746 if (ha->flags.cpu_affinity_enabled)
67c2e93a
AC		 5747 req = ha->req_q_map[0];
5748 else
5749 req = vha->req;
5750 rsp = req->rsp;
5751
2c3dfe3f 5752 if (rval == QLA_SUCCESS) {
e315cd28 5753 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
73208dfd 5754 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
2c3dfe3f
SJ		 5755 }
5756
e315cd28 5757 vha->flags.management_server_logged_in = 0;
2c3dfe3f
SJ		 5758
5759 /* Login to SNS first */
0b91d116
CD		 5760 rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb,
5761 BIT_1);
5762 if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
5763 if (rval2 == QLA_MEMORY_ALLOC_FAILED)
5764 ql_dbg(ql_dbg_init, vha, 0x0120,
5765 "Failed SNS login: loop_id=%x, rval2=%d\n",
5766 NPH_SNS, rval2);
5767 else
5768 ql_dbg(ql_dbg_init, vha, 0x0103,
5769 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x "
5770 "mb[2]=%x mb[6]=%x mb[7]=%x.\n",
5771 NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]);
2c3dfe3f
SJ		 5772 return (QLA_FUNCTION_FAILED);
5773 }
5774
e315cd28
AC		 5775 atomic_set(&vha->loop_down_timer, 0);
5776 atomic_set(&vha->loop_state, LOOP_UP);
5777 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5778 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
5779 rval = qla2x00_loop_resync(base_vha);
2c3dfe3f
SJ		 5780
5781 return rval;
5782}
4d4df193
HK		 5783
5784/* 84XX Support **************************************************************/
5785
5786static LIST_HEAD(qla_cs84xx_list);
5787static DEFINE_MUTEX(qla_cs84xx_mutex);
5788
5789static struct qla_chip_state_84xx *
e315cd28 5790qla84xx_get_chip(struct scsi_qla_host *vha)
4d4df193
HK		 5791{
5792 struct qla_chip_state_84xx *cs84xx;
e315cd28 5793 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5794
5795 mutex_lock(&qla_cs84xx_mutex);
5796
5797 /* Find any shared 84xx chip. */
5798 list_for_each_entry(cs84xx, &qla_cs84xx_list, list) {
5799 if (cs84xx->bus == ha->pdev->bus) {
5800 kref_get(&cs84xx->kref);
5801 goto done;
5802 }
5803 }
5804
5805 cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL);
5806 if (!cs84xx)
5807 goto done;
5808
5809 kref_init(&cs84xx->kref);
5810 spin_lock_init(&cs84xx->access_lock);
5811 mutex_init(&cs84xx->fw_update_mutex);
5812 cs84xx->bus = ha->pdev->bus;
5813
5814 list_add_tail(&cs84xx->list, &qla_cs84xx_list);
5815done:
5816 mutex_unlock(&qla_cs84xx_mutex);
5817 return cs84xx;
5818}
5819
5820static void
5821__qla84xx_chip_release(struct kref *kref)
5822{
5823 struct qla_chip_state_84xx *cs84xx =
5824 container_of(kref, struct qla_chip_state_84xx, kref);
5825
5826 mutex_lock(&qla_cs84xx_mutex);
5827 list_del(&cs84xx->list);
5828 mutex_unlock(&qla_cs84xx_mutex);
5829 kfree(cs84xx);
5830}
5831
5832void
e315cd28 5833qla84xx_put_chip(struct scsi_qla_host *vha)
4d4df193 5834{
e315cd28 5835 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5836 if (ha->cs84xx)
5837 kref_put(&ha->cs84xx->kref, __qla84xx_chip_release);
5838}
5839
5840static int
e315cd28 5841qla84xx_init_chip(scsi_qla_host_t *vha)
4d4df193
HK		 5842{
5843 int rval;
5844 uint16_t status[2];
e315cd28 5845 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5846
5847 mutex_lock(&ha->cs84xx->fw_update_mutex);
5848
e315cd28 5849 rval = qla84xx_verify_chip(vha, status);
4d4df193
HK		 5850
5851 mutex_unlock(&ha->cs84xx->fw_update_mutex);
5852
5853 return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED:
5854 QLA_SUCCESS;
5855}
3a03eb79
AV		 5856
5857/* 81XX Support **************************************************************/
5858
5859int
5860qla81xx_nvram_config(scsi_qla_host_t *vha)
5861{
5862 int rval;
5863 struct init_cb_81xx *icb;
5864 struct nvram_81xx *nv;
5865 uint32_t *dptr;
5866 uint8_t *dptr1, *dptr2;
5867 uint32_t chksum;
5868 uint16_t cnt;
5869 struct qla_hw_data *ha = vha->hw;
5870
5871 rval = QLA_SUCCESS;
5872 icb = (struct init_cb_81xx *)ha->init_cb;
5873 nv = ha->nvram;
5874
5875 /* Determine NVRAM starting address. */
5876 ha->nvram_size = sizeof(struct nvram_81xx);
3a03eb79 5877 ha->vpd_size = FA_NVRAM_VPD_SIZE;
7ec0effd
AD		 5878 if (IS_P3P_TYPE(ha) || IS_QLA8031(ha))
5879 ha->vpd_size = FA_VPD_SIZE_82XX;
3a03eb79
AV		 5880
5881 /* Get VPD data into cache */
5882 ha->vpd = ha->nvram + VPD_OFFSET;
3d79038f
AV		 5883 ha->isp_ops->read_optrom(vha, ha->vpd, ha->flt_region_vpd << 2,
5884 ha->vpd_size);
3a03eb79
AV		 5885
5886 /* Get NVRAM data into cache and calculate checksum. */
3d79038f 5887 ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2,
3a03eb79 5888 ha->nvram_size);
3d79038f 5889 dptr = (uint32_t *)nv;
3a03eb79
AV		 5890 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
5891 chksum += le32_to_cpu(*dptr++);
5892
7c3df132
SK		 5893 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
5894 "Contents of NVRAM:\n");
5895 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
5896 (uint8_t *)nv, ha->nvram_size);
3a03eb79
AV		 5897
5898 /* Bad NVRAM data, set defaults parameters. */
5899 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
5900 || nv->id[3] != ' ' ||
5901 nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
5902 /* Reset NVRAM data. */
7c3df132 5903 ql_log(ql_log_info, vha, 0x0073,
9e336520 5904 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132 5905 "version=0x%x.\n", chksum, nv->id[0],
3a03eb79 5906 le16_to_cpu(nv->nvram_version));
7c3df132
SK		 5907 ql_log(ql_log_info, vha, 0x0074,
5908 "Falling back to functioning (yet invalid -- WWPN) "
5909 "defaults.\n");
3a03eb79
AV		 5910
5911 /*
5912 * Set default initialization control block.
5913 */
5914 memset(nv, 0, ha->nvram_size);
5915 nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
5916 nv->version = __constant_cpu_to_le16(ICB_VERSION);
5917 nv->frame_payload_size = __constant_cpu_to_le16(2048);
5918 nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
5919 nv->exchange_count = __constant_cpu_to_le16(0);
5920 nv->port_name[0] = 0x21;
f73cb695 5921 nv->port_name[1] = 0x00 + ha->port_no + 1;
3a03eb79
AV		 5922 nv->port_name[2] = 0x00;
5923 nv->port_name[3] = 0xe0;
5924 nv->port_name[4] = 0x8b;
5925 nv->port_name[5] = 0x1c;
5926 nv->port_name[6] = 0x55;
5927 nv->port_name[7] = 0x86;
5928 nv->node_name[0] = 0x20;
5929 nv->node_name[1] = 0x00;
5930 nv->node_name[2] = 0x00;
5931 nv->node_name[3] = 0xe0;
5932 nv->node_name[4] = 0x8b;
5933 nv->node_name[5] = 0x1c;
5934 nv->node_name[6] = 0x55;
5935 nv->node_name[7] = 0x86;
5936 nv->login_retry_count = __constant_cpu_to_le16(8);
5937 nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
5938 nv->login_timeout = __constant_cpu_to_le16(0);
5939 nv->firmware_options_1 =
5940 __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
5941 nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
5942 nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
5943 nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
5944 nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
5945 nv->efi_parameters = __constant_cpu_to_le32(0);
5946 nv->reset_delay = 5;
5947 nv->max_luns_per_target = __constant_cpu_to_le16(128);
5948 nv->port_down_retry_count = __constant_cpu_to_le16(30);
6246b8a1 5949 nv->link_down_timeout = __constant_cpu_to_le16(180);
eeebcc92 5950 nv->enode_mac[0] = 0x00;
6246b8a1
GM		 5951 nv->enode_mac[1] = 0xC0;
5952 nv->enode_mac[2] = 0xDD;
3a03eb79
AV		 5953 nv->enode_mac[3] = 0x04;
5954 nv->enode_mac[4] = 0x05;
f73cb695 5955 nv->enode_mac[5] = 0x06 + ha->port_no + 1;
3a03eb79
AV		 5956
5957 rval = 1;
5958 }
5959
9e522cd8
AE		 5960 if (IS_T10_PI_CAPABLE(ha))
5961 nv->frame_payload_size &= ~7;
5962
aa230bc5
AE		 5963 qlt_81xx_config_nvram_stage1(vha, nv);
5964
3a03eb79 5965 /* Reset Initialization control block */
773120e4 5966 memset(icb, 0, ha->init_cb_size);
3a03eb79
AV		 5967
5968 /* Copy 1st segment. */
5969 dptr1 = (uint8_t *)icb;
5970 dptr2 = (uint8_t *)&nv->version;
5971 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
5972 while (cnt--)
5973 *dptr1++ = *dptr2++;
5974
5975 icb->login_retry_count = nv->login_retry_count;
5976
5977 /* Copy 2nd segment. */
5978 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
5979 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
5980 cnt = (uint8_t *)&icb->reserved_5 -
5981 (uint8_t *)&icb->interrupt_delay_timer;
5982 while (cnt--)
5983 *dptr1++ = *dptr2++;
5984
5985 memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac));
5986 /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */
5987 if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) {
69e5f1ea
AV		 5988 icb->enode_mac[0] = 0x00;
5989 icb->enode_mac[1] = 0xC0;
5990 icb->enode_mac[2] = 0xDD;
3a03eb79
AV		 5991 icb->enode_mac[3] = 0x04;
5992 icb->enode_mac[4] = 0x05;
f73cb695 5993 icb->enode_mac[5] = 0x06 + ha->port_no + 1;
3a03eb79
AV		 5994 }
5995
b64b0e8f
AV		 5996 /* Use extended-initialization control block. */
5997 memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb));
5998
3a03eb79
AV		 5999 /*
6000 * Setup driver NVRAM options.
6001 */
6002 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
a9083016 6003 "QLE8XXX");
3a03eb79 6004
aa230bc5
AE		 6005 qlt_81xx_config_nvram_stage2(vha, icb);
6006
3a03eb79
AV		 6007 /* Use alternate WWN? */
6008 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
6009 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
6010 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
6011 }
6012
6013 /* Prepare nodename */
6014 if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
6015 /*
6016 * Firmware will apply the following mask if the nodename was
6017 * not provided.
6018 */
6019 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
6020 icb->node_name[0] &= 0xF0;
6021 }
6022
6023 /* Set host adapter parameters. */
6024 ha->flags.disable_risc_code_load = 0;
6025 ha->flags.enable_lip_reset = 0;
6026 ha->flags.enable_lip_full_login =
6027 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
6028 ha->flags.enable_target_reset =
6029 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
6030 ha->flags.enable_led_scheme = 0;
6031 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
6032
6033 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
6034 (BIT_6 | BIT_5 | BIT_4)) >> 4;
6035
6036 /* save HBA serial number */
6037 ha->serial0 = icb->port_name[5];
6038 ha->serial1 = icb->port_name[6];
6039 ha->serial2 = icb->port_name[7];
6040 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
6041 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
6042
6043 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
6044
6045 ha->retry_count = le16_to_cpu(nv->login_retry_count);
6046
6047 /* Set minimum login_timeout to 4 seconds. */
6048 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
6049 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
6050 if (le16_to_cpu(nv->login_timeout) < 4)
6051 nv->login_timeout = __constant_cpu_to_le16(4);
6052 ha->login_timeout = le16_to_cpu(nv->login_timeout);
6053 icb->login_timeout = nv->login_timeout;
6054
6055 /* Set minimum RATOV to 100 tenths of a second. */
6056 ha->r_a_tov = 100;
6057
6058 ha->loop_reset_delay = nv->reset_delay;
6059
6060 /* Link Down Timeout = 0:
6061 *
7ec0effd 6062 * When Port Down timer expires we will start returning
3a03eb79
AV		 6063 * I/O's to OS with "DID_NO_CONNECT".
6064 *
6065 * Link Down Timeout != 0:
6066 *
6067 * The driver waits for the link to come up after link down
6068 * before returning I/Os to OS with "DID_NO_CONNECT".
6069 */
6070 if (le16_to_cpu(nv->link_down_timeout) == 0) {
6071 ha->loop_down_abort_time =
6072 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
6073 } else {
6074 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
6075 ha->loop_down_abort_time =
6076 (LOOP_DOWN_TIME - ha->link_down_timeout);
6077 }
6078
6079 /* Need enough time to try and get the port back. */
6080 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
6081 if (qlport_down_retry)
6082 ha->port_down_retry_count = qlport_down_retry;
6083
6084 /* Set login_retry_count */
6085 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
6086 if (ha->port_down_retry_count ==
6087 le16_to_cpu(nv->port_down_retry_count) &&
6088 ha->port_down_retry_count > 3)
6089 ha->login_retry_count = ha->port_down_retry_count;
6090 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
6091 ha->login_retry_count = ha->port_down_retry_count;
6092 if (ql2xloginretrycount)
6093 ha->login_retry_count = ql2xloginretrycount;
6094
6246b8a1 6095 /* if not running MSI-X we need handshaking on interrupts */
f73cb695 6096 if (!vha->hw->flags.msix_enabled && (IS_QLA83XX(ha) || IS_QLA27XX(ha)))
6246b8a1
GM		 6097 icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_22);
6098
3a03eb79
AV		 6099 /* Enable ZIO. */
6100 if (!vha->flags.init_done) {
6101 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
6102 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
6103 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
6104 le16_to_cpu(icb->interrupt_delay_timer): 2;
6105 }
6106 icb->firmware_options_2 &= __constant_cpu_to_le32(
6107 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
6108 vha->flags.process_response_queue = 0;
6109 if (ha->zio_mode != QLA_ZIO_DISABLED) {
6110 ha->zio_mode = QLA_ZIO_MODE_6;
6111
7c3df132 6112 ql_log(ql_log_info, vha, 0x0075,
3a03eb79 6113 "ZIO mode %d enabled; timer delay (%d us).\n",
7c3df132
SK		 6114 ha->zio_mode,
6115 ha->zio_timer * 100);
3a03eb79
AV		 6116
6117 icb->firmware_options_2 |= cpu_to_le32(
6118 (uint32_t)ha->zio_mode);
6119 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
6120 vha->flags.process_response_queue = 1;
6121 }
6122
6123 if (rval) {
7c3df132
SK		 6124 ql_log(ql_log_warn, vha, 0x0076,
6125 "NVRAM configuration failed.\n");
3a03eb79
AV		 6126 }
6127 return (rval);
6128}
6129
a9083016
GM		 6130int
6131qla82xx_restart_isp(scsi_qla_host_t *vha)
6132{
6133 int status, rval;
6134 uint32_t wait_time;
6135 struct qla_hw_data *ha = vha->hw;
6136 struct req_que *req = ha->req_q_map[0];
6137 struct rsp_que *rsp = ha->rsp_q_map[0];
6138 struct scsi_qla_host *vp;
feafb7b1 6139 unsigned long flags;
a9083016
GM		 6140
6141 status = qla2x00_init_rings(vha);
6142 if (!status) {
6143 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
6144 ha->flags.chip_reset_done = 1;
6145
6146 status = qla2x00_fw_ready(vha);
6147 if (!status) {
7c3df132
SK		 6148 ql_log(ql_log_info, vha, 0x803c,
6149 "Start configure loop, status =%d.\n", status);
a9083016
GM		 6150
6151 /* Issue a marker after FW becomes ready. */
6152 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
6153
6154 vha->flags.online = 1;
6155 /* Wait at most MAX_TARGET RSCNs for a stable link. */
6156 wait_time = 256;
6157 do {
6158 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
6159 qla2x00_configure_loop(vha);
6160 wait_time--;
6161 } while (!atomic_read(&vha->loop_down_timer) &&
6162 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) &&
6163 wait_time &&
6164 (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)));
6165 }
6166
6167 /* if no cable then assume it's good */
6168 if ((vha->device_flags & DFLG_NO_CABLE))
6169 status = 0;
6170
cfb0919c 6171 ql_log(ql_log_info, vha, 0x8000,
7c3df132 6172 "Configure loop done, status = 0x%x.\n", status);
a9083016
GM		 6173 }
6174
6175 if (!status) {
6176 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
6177
6178 if (!atomic_read(&vha->loop_down_timer)) {
6179 /*
6180 * Issue marker command only when we are going
6181 * to start the I/O .
6182 */
6183 vha->marker_needed = 1;
6184 }
6185
6186 vha->flags.online = 1;
6187
6188 ha->isp_ops->enable_intrs(ha);
6189
6190 ha->isp_abort_cnt = 0;
6191 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
6192
53296788 6193 /* Update the firmware version */
3173167f 6194 status = qla82xx_check_md_needed(vha);
53296788 6195
a9083016
GM		 6196 if (ha->fce) {
6197 ha->flags.fce_enabled = 1;
6198 memset(ha->fce, 0,
6199 fce_calc_size(ha->fce_bufs));
6200 rval = qla2x00_enable_fce_trace(vha,
6201 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
6202 &ha->fce_bufs);
6203 if (rval) {
cfb0919c 6204 ql_log(ql_log_warn, vha, 0x8001,
7c3df132
SK		 6205 "Unable to reinitialize FCE (%d).\n",
6206 rval);
a9083016
GM		 6207 ha->flags.fce_enabled = 0;
6208 }
6209 }
6210
6211 if (ha->eft) {
6212 memset(ha->eft, 0, EFT_SIZE);
6213 rval = qla2x00_enable_eft_trace(vha,
6214 ha->eft_dma, EFT_NUM_BUFFERS);
6215 if (rval) {
cfb0919c 6216 ql_log(ql_log_warn, vha, 0x8010,
7c3df132
SK		 6217 "Unable to reinitialize EFT (%d).\n",
6218 rval);
a9083016
GM		 6219 }
6220 }
a9083016
GM		 6221 }
6222
6223 if (!status) {
cfb0919c 6224 ql_dbg(ql_dbg_taskm, vha, 0x8011,
7c3df132 6225 "qla82xx_restart_isp succeeded.\n");
feafb7b1
AE		 6226
6227 spin_lock_irqsave(&ha->vport_slock, flags);
6228 list_for_each_entry(vp, &ha->vp_list, list) {
6229 if (vp->vp_idx) {
6230 atomic_inc(&vp->vref_count);
6231 spin_unlock_irqrestore(&ha->vport_slock, flags);
6232
a9083016 6233 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 6234
6235 spin_lock_irqsave(&ha->vport_slock, flags);
6236 atomic_dec(&vp->vref_count);
6237 }
a9083016 6238 }
feafb7b1
AE		 6239 spin_unlock_irqrestore(&ha->vport_slock, flags);
6240
a9083016 6241 } else {
cfb0919c 6242 ql_log(ql_log_warn, vha, 0x8016,
7c3df132 6243 "qla82xx_restart_isp **** FAILED ****.\n");
a9083016
GM		 6244 }
6245
6246 return status;
6247}
6248
3a03eb79 6249void
ae97c91e 6250qla81xx_update_fw_options(scsi_qla_host_t *vha)
3a03eb79 6251{
ae97c91e
AV		 6252 struct qla_hw_data *ha = vha->hw;
6253
6254 if (!ql2xetsenable)
6255 return;
6256
6257 /* Enable ETS Burst. */
6258 memset(ha->fw_options, 0, sizeof(ha->fw_options));
6259 ha->fw_options[2] |= BIT_9;
6260 qla2x00_set_fw_options(vha, ha->fw_options);
3a03eb79 6261}
09ff701a
SR		 6262
6263/*
6264 * qla24xx_get_fcp_prio
6265 * Gets the fcp cmd priority value for the logged in port.
6266 * Looks for a match of the port descriptors within
6267 * each of the fcp prio config entries. If a match is found,
6268 * the tag (priority) value is returned.
6269 *
6270 * Input:
21090cbe 6271 * vha = scsi host structure pointer.
09ff701a
SR		 6272 * fcport = port structure pointer.
6273 *
6274 * Return:
6c452a45 6275 * non-zero (if found)
f28a0a96 6276 * -1 (if not found)
09ff701a
SR		 6277 *
6278 * Context:
6279 * Kernel context
6280 */
f28a0a96 6281static int
09ff701a
SR		 6282qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
6283{
6284 int i, entries;
6285 uint8_t pid_match, wwn_match;
f28a0a96 6286 int priority;
09ff701a
SR		 6287 uint32_t pid1, pid2;
6288 uint64_t wwn1, wwn2;
6289 struct qla_fcp_prio_entry *pri_entry;
6290 struct qla_hw_data *ha = vha->hw;
6291
6292 if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled)
f28a0a96 6293 return -1;
09ff701a 6294
f28a0a96 6295 priority = -1;
09ff701a
SR		 6296 entries = ha->fcp_prio_cfg->num_entries;
6297 pri_entry = &ha->fcp_prio_cfg->entry[0];
6298
6299 for (i = 0; i < entries; i++) {
6300 pid_match = wwn_match = 0;
6301
6302 if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) {
6303 pri_entry++;
6304 continue;
6305 }
6306
6307 /* check source pid for a match */
6308 if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) {
6309 pid1 = pri_entry->src_pid & INVALID_PORT_ID;
6310 pid2 = vha->d_id.b24 & INVALID_PORT_ID;
6311 if (pid1 == INVALID_PORT_ID)
6312 pid_match++;
6313 else if (pid1 == pid2)
6314 pid_match++;
6315 }
6316
6317 /* check destination pid for a match */
6318 if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) {
6319 pid1 = pri_entry->dst_pid & INVALID_PORT_ID;
6320 pid2 = fcport->d_id.b24 & INVALID_PORT_ID;
6321 if (pid1 == INVALID_PORT_ID)
6322 pid_match++;
6323 else if (pid1 == pid2)
6324 pid_match++;
6325 }
6326
6327 /* check source WWN for a match */
6328 if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) {
6329 wwn1 = wwn_to_u64(vha->port_name);
6330 wwn2 = wwn_to_u64(pri_entry->src_wwpn);
6331 if (wwn2 == (uint64_t)-1)
6332 wwn_match++;
6333 else if (wwn1 == wwn2)
6334 wwn_match++;
6335 }
6336
6337 /* check destination WWN for a match */
6338 if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) {
6339 wwn1 = wwn_to_u64(fcport->port_name);
6340 wwn2 = wwn_to_u64(pri_entry->dst_wwpn);
6341 if (wwn2 == (uint64_t)-1)
6342 wwn_match++;
6343 else if (wwn1 == wwn2)
6344 wwn_match++;
6345 }
6346
6347 if (pid_match == 2 || wwn_match == 2) {
6348 /* Found a matching entry */
6349 if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID)
6350 priority = pri_entry->tag;
6351 break;
6352 }
6353
6354 pri_entry++;
6355 }
6356
6357 return priority;
6358}
6359
6360/*
6361 * qla24xx_update_fcport_fcp_prio
6362 * Activates fcp priority for the logged in fc port
6363 *
6364 * Input:
21090cbe 6365 * vha = scsi host structure pointer.
09ff701a
SR		 6366 * fcp = port structure pointer.
6367 *
6368 * Return:
6369 * QLA_SUCCESS or QLA_FUNCTION_FAILED
6370 *
6371 * Context:
6372 * Kernel context.
6373 */
6374int
21090cbe 6375qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
09ff701a
SR		 6376{
6377 int ret;
f28a0a96 6378 int priority;
09ff701a
SR		 6379 uint16_t mb[5];
6380
21090cbe
MI		 6381 if (fcport->port_type != FCT_TARGET ||
6382 fcport->loop_id == FC_NO_LOOP_ID)
09ff701a
SR		 6383 return QLA_FUNCTION_FAILED;
6384
21090cbe 6385 priority = qla24xx_get_fcp_prio(vha, fcport);
f28a0a96
AV		 6386 if (priority < 0)
6387 return QLA_FUNCTION_FAILED;
6388
7ec0effd 6389 if (IS_P3P_TYPE(vha->hw)) {
a00f6296
SK		 6390 fcport->fcp_prio = priority & 0xf;
6391 return QLA_SUCCESS;
6392 }
6393
21090cbe 6394 ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb);
cfb0919c
CD		 6395 if (ret == QLA_SUCCESS) {
6396 if (fcport->fcp_prio != priority)
6397 ql_dbg(ql_dbg_user, vha, 0x709e,
6398 "Updated FCP_CMND priority - value=%d loop_id=%d "
6399 "port_id=%02x%02x%02x.\n", priority,
6400 fcport->loop_id, fcport->d_id.b.domain,
6401 fcport->d_id.b.area, fcport->d_id.b.al_pa);
a00f6296 6402 fcport->fcp_prio = priority & 0xf;
cfb0919c 6403 } else
7c3df132 6404 ql_dbg(ql_dbg_user, vha, 0x704f,
cfb0919c
CD		 6405 "Unable to update FCP_CMND priority - ret=0x%x for "
6406 "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id,
6407 fcport->d_id.b.domain, fcport->d_id.b.area,
6408 fcport->d_id.b.al_pa);
09ff701a
SR		 6409 return ret;
6410}
6411
6412/*
6413 * qla24xx_update_all_fcp_prio
6414 * Activates fcp priority for all the logged in ports
6415 *
6416 * Input:
6417 * ha = adapter block pointer.
6418 *
6419 * Return:
6420 * QLA_SUCCESS or QLA_FUNCTION_FAILED
6421 *
6422 * Context:
6423 * Kernel context.
6424 */
6425int
6426qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha)
6427{
6428 int ret;
6429 fc_port_t *fcport;
6430
6431 ret = QLA_FUNCTION_FAILED;
6432 /* We need to set priority for all logged in ports */
6433 list_for_each_entry(fcport, &vha->vp_fcports, list)
6434 ret = qla24xx_update_fcport_fcp_prio(vha, fcport);
6435
6436 return ret;
6437}
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