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qla2xxx: Add DebugFS node to display Port Database
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / qla2xxx / qla_init.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
73208dfd 8#include "qla_gbl.h"
1da177e4
LT		 9
10#include <linux/delay.h>
5a0e3ad6 11#include <linux/slab.h>
0107109e 12#include <linux/vmalloc.h>
1da177e4
LT		 13
14#include "qla_devtbl.h"
15
4e08df3f
DM		 16#ifdef CONFIG_SPARC
17#include <asm/prom.h>
4e08df3f
DM		 18#endif
19
2d70c103
NB		 20#include <target/target_core_base.h>
21#include "qla_target.h"
22
1da177e4
LT		 23/*
24* QLogic ISP2x00 Hardware Support Function Prototypes.
25*/
1da177e4 26static int qla2x00_isp_firmware(scsi_qla_host_t *);
1da177e4 27static int qla2x00_setup_chip(scsi_qla_host_t *);
1da177e4
LT		 28static int qla2x00_fw_ready(scsi_qla_host_t *);
29static int qla2x00_configure_hba(scsi_qla_host_t *);
1da177e4
LT		 30static int qla2x00_configure_loop(scsi_qla_host_t *);
31static int qla2x00_configure_local_loop(scsi_qla_host_t *);
1da177e4 32static int qla2x00_configure_fabric(scsi_qla_host_t *);
726b8548 33static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *);
1da177e4 34static int qla2x00_restart_isp(scsi_qla_host_t *);
1da177e4 35
4d4df193
HK		 36static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *);
37static int qla84xx_init_chip(scsi_qla_host_t *);
73208dfd 38static int qla25xx_init_queues(struct qla_hw_data *);
726b8548
QT		 39static int qla24xx_post_gpdb_work(struct scsi_qla_host *, fc_port_t *, u8);
40static void qla24xx_handle_plogi_done_event(struct scsi_qla_host *,
41 struct event_arg *);
4d4df193 42
ac280b67
AV		 43/* SRB Extensions ---------------------------------------------------------- */
44
9ba56b95
GM		 45void
46qla2x00_sp_timeout(unsigned long __data)
ac280b67
AV		 47{
48 srb_t *sp = (srb_t *)__data;
4916392b 49 struct srb_iocb *iocb;
25ff6af1 50 scsi_qla_host_t *vha = sp->vha;
ac280b67
AV		 51 struct req_que *req;
52 unsigned long flags;
53
25ff6af1
JC		 54 spin_lock_irqsave(&vha->hw->hardware_lock, flags);
55 req = vha->hw->req_q_map[0];
ac280b67 56 req->outstanding_cmds[sp->handle] = NULL;
9ba56b95 57 iocb = &sp->u.iocb_cmd;
4916392b 58 iocb->timeout(sp);
25ff6af1
JC		 59 sp->free(sp);
60 spin_unlock_irqrestore(&vha->hw->hardware_lock, flags);
ac280b67
AV		 61}
62
9ba56b95 63void
25ff6af1 64qla2x00_sp_free(void *ptr)
ac280b67 65{
25ff6af1 66 srb_t *sp = ptr;
9ba56b95 67 struct srb_iocb *iocb = &sp->u.iocb_cmd;
ac280b67 68
4d97cc53 69 del_timer(&iocb->timer);
25ff6af1 70 qla2x00_rel_sp(sp);
ac280b67
AV		 71}
72
ac280b67
AV		 73/* Asynchronous Login/Logout Routines -------------------------------------- */
74
a9b6f722 75unsigned long
5b91490e
AV		 76qla2x00_get_async_timeout(struct scsi_qla_host *vha)
77{
78 unsigned long tmo;
79 struct qla_hw_data *ha = vha->hw;
80
81 /* Firmware should use switch negotiated r_a_tov for timeout. */
82 tmo = ha->r_a_tov / 10 * 2;
8ae6d9c7
GM		 83 if (IS_QLAFX00(ha)) {
84 tmo = FX00_DEF_RATOV * 2;
85 } else if (!IS_FWI2_CAPABLE(ha)) {
5b91490e
AV		 86 /*
87 * Except for earlier ISPs where the timeout is seeded from the
88 * initialization control block.
89 */
90 tmo = ha->login_timeout;
91 }
92 return tmo;
93}
ac280b67 94
726b8548 95void
9ba56b95 96qla2x00_async_iocb_timeout(void *data)
ac280b67 97{
25ff6af1 98 srb_t *sp = data;
ac280b67 99 fc_port_t *fcport = sp->fcport;
726b8548
QT		 100 struct srb_iocb *lio = &sp->u.iocb_cmd;
101 struct event_arg ea;
ac280b67 102
7c3df132 103 ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
726b8548
QT		 104 "Async-%s timeout - hdl=%x portid=%06x %8phC.\n",
105 sp->name, sp->handle, fcport->d_id.b24, fcport->port_name);
ac280b67 106
5ff1d584 107 fcport->flags &= ~FCF_ASYNC_SENT;
726b8548
QT		 108
109 switch (sp->type) {
110 case SRB_LOGIN_CMD:
6ac52608
AV		 111 /* Retry as needed. */
112 lio->u.logio.data[0] = MBS_COMMAND_ERROR;
113 lio->u.logio.data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
114 QLA_LOGIO_LOGIN_RETRIED : 0;
726b8548
QT		 115 memset(&ea, 0, sizeof(ea));
116 ea.event = FCME_PLOGI_DONE;
117 ea.fcport = sp->fcport;
118 ea.data[0] = lio->u.logio.data[0];
119 ea.data[1] = lio->u.logio.data[1];
120 ea.sp = sp;
121 qla24xx_handle_plogi_done_event(fcport->vha, &ea);
122 break;
123 case SRB_LOGOUT_CMD:
a6ca8878 124 qlt_logo_completion_handler(fcport, QLA_FUNCTION_TIMEOUT);
726b8548
QT		 125 break;
126 case SRB_CT_PTHRU_CMD:
127 case SRB_MB_IOCB:
128 case SRB_NACK_PLOGI:
129 case SRB_NACK_PRLI:
130 case SRB_NACK_LOGO:
25ff6af1 131 sp->done(sp, QLA_FUNCTION_TIMEOUT);
726b8548 132 break;
6ac52608 133 }
ac280b67
AV		 134}
135
99b0bec7 136static void
25ff6af1 137qla2x00_async_login_sp_done(void *ptr, int res)
99b0bec7 138{
25ff6af1
JC		 139 srb_t *sp = ptr;
140 struct scsi_qla_host *vha = sp->vha;
9ba56b95 141 struct srb_iocb *lio = &sp->u.iocb_cmd;
726b8548 142 struct event_arg ea;
9ba56b95 143
726b8548 144 ql_dbg(ql_dbg_disc, vha, 0xffff,
25ff6af1 145 "%s %8phC res %d \n", __func__, sp->fcport->port_name, res);
726b8548
QT		 146
147 sp->fcport->flags &= ~FCF_ASYNC_SENT;
148 if (!test_bit(UNLOADING, &vha->dpc_flags)) {
149 memset(&ea, 0, sizeof(ea));
150 ea.event = FCME_PLOGI_DONE;
151 ea.fcport = sp->fcport;
152 ea.data[0] = lio->u.logio.data[0];
153 ea.data[1] = lio->u.logio.data[1];
154 ea.iop[0] = lio->u.logio.iop[0];
155 ea.iop[1] = lio->u.logio.iop[1];
156 ea.sp = sp;
157 qla2x00_fcport_event_handler(vha, &ea);
158 }
9ba56b95 159
25ff6af1 160 sp->free(sp);
99b0bec7
AV		 161}
162
ac280b67
AV		 163int
164qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport,
165 uint16_t *data)
166{
ac280b67 167 srb_t *sp;
4916392b 168 struct srb_iocb *lio;
726b8548
QT		 169 int rval = QLA_FUNCTION_FAILED;
170
171 if (!vha->flags.online)
172 goto done;
173
174 if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) ||
175 (fcport->fw_login_state == DSC_LS_PLOGI_COMP) ||
176 (fcport->fw_login_state == DSC_LS_PRLI_PEND))
177 goto done;
ac280b67 178
9ba56b95 179 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 180 if (!sp)
181 goto done;
182
726b8548
QT		 183 fcport->flags |= FCF_ASYNC_SENT;
184 fcport->logout_completed = 0;
185
9ba56b95
GM		 186 sp->type = SRB_LOGIN_CMD;
187 sp->name = "login";
188 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
189
190 lio = &sp->u.iocb_cmd;
3822263e 191 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 192 sp->done = qla2x00_async_login_sp_done;
4916392b 193 lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI;
ac280b67 194 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 195 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
ac280b67 196 rval = qla2x00_start_sp(sp);
080c9517
CD		 197 if (rval != QLA_SUCCESS) {
198 fcport->flags &= ~FCF_ASYNC_SENT;
199 fcport->flags |= FCF_LOGIN_NEEDED;
200 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
ac280b67 201 goto done_free_sp;
080c9517 202 }
ac280b67 203
7c3df132 204 ql_dbg(ql_dbg_disc, vha, 0x2072,
726b8548
QT		 205 "Async-login - %8phC hdl=%x, loopid=%x portid=%02x%02x%02x "
206 "retries=%d.\n", fcport->port_name, sp->handle, fcport->loop_id,
cfb0919c
CD		 207 fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
208 fcport->login_retry);
ac280b67
AV		 209 return rval;
210
211done_free_sp:
25ff6af1 212 sp->free(sp);
ac280b67 213done:
726b8548 214 fcport->flags &= ~FCF_ASYNC_SENT;
ac280b67
AV		 215 return rval;
216}
217
99b0bec7 218static void
25ff6af1 219qla2x00_async_logout_sp_done(void *ptr, int res)
99b0bec7 220{
25ff6af1 221 srb_t *sp = ptr;
9ba56b95 222 struct srb_iocb *lio = &sp->u.iocb_cmd;
9ba56b95 223
726b8548 224 sp->fcport->flags &= ~FCF_ASYNC_SENT;
25ff6af1
JC		 225 if (!test_bit(UNLOADING, &sp->vha->dpc_flags))
226 qla2x00_post_async_logout_done_work(sp->vha, sp->fcport,
9ba56b95 227 lio->u.logio.data);
25ff6af1 228 sp->free(sp);
99b0bec7
AV		 229}
230
ac280b67
AV		 231int
232qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport)
233{
ac280b67 234 srb_t *sp;
4916392b 235 struct srb_iocb *lio;
ac280b67
AV		 236 int rval;
237
238 rval = QLA_FUNCTION_FAILED;
726b8548 239 fcport->flags |= FCF_ASYNC_SENT;
9ba56b95 240 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 241 if (!sp)
242 goto done;
243
9ba56b95
GM		 244 sp->type = SRB_LOGOUT_CMD;
245 sp->name = "logout";
246 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
247
248 lio = &sp->u.iocb_cmd;
3822263e 249 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 250 sp->done = qla2x00_async_logout_sp_done;
ac280b67
AV		 251 rval = qla2x00_start_sp(sp);
252 if (rval != QLA_SUCCESS)
253 goto done_free_sp;
254
7c3df132 255 ql_dbg(ql_dbg_disc, vha, 0x2070,
726b8548 256 "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x %8phC.\n",
cfb0919c 257 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
726b8548
QT		 258 fcport->d_id.b.area, fcport->d_id.b.al_pa,
259 fcport->port_name);
ac280b67
AV		 260 return rval;
261
262done_free_sp:
25ff6af1 263 sp->free(sp);
ac280b67 264done:
726b8548 265 fcport->flags &= ~FCF_ASYNC_SENT;
ac280b67
AV		 266 return rval;
267}
268
5ff1d584 269static void
25ff6af1 270qla2x00_async_adisc_sp_done(void *ptr, int res)
5ff1d584 271{
25ff6af1
JC		 272 srb_t *sp = ptr;
273 struct scsi_qla_host *vha = sp->vha;
9ba56b95 274 struct srb_iocb *lio = &sp->u.iocb_cmd;
9ba56b95
GM		 275
276 if (!test_bit(UNLOADING, &vha->dpc_flags))
25ff6af1 277 qla2x00_post_async_adisc_done_work(sp->vha, sp->fcport,
9ba56b95 278 lio->u.logio.data);
25ff6af1 279 sp->free(sp);
5ff1d584
AV		 280}
281
282int
283qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport,
284 uint16_t *data)
285{
5ff1d584 286 srb_t *sp;
4916392b 287 struct srb_iocb *lio;
5ff1d584
AV		 288 int rval;
289
290 rval = QLA_FUNCTION_FAILED;
726b8548 291 fcport->flags |= FCF_ASYNC_SENT;
9ba56b95 292 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
5ff1d584
AV		 293 if (!sp)
294 goto done;
295
9ba56b95
GM		 296 sp->type = SRB_ADISC_CMD;
297 sp->name = "adisc";
298 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
299
300 lio = &sp->u.iocb_cmd;
3822263e 301 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 302 sp->done = qla2x00_async_adisc_sp_done;
5ff1d584 303 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 304 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
5ff1d584
AV		 305 rval = qla2x00_start_sp(sp);
306 if (rval != QLA_SUCCESS)
307 goto done_free_sp;
308
7c3df132 309 ql_dbg(ql_dbg_disc, vha, 0x206f,
cfb0919c
CD		 310 "Async-adisc - hdl=%x loopid=%x portid=%02x%02x%02x.\n",
311 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
312 fcport->d_id.b.area, fcport->d_id.b.al_pa);
5ff1d584
AV		 313 return rval;
314
315done_free_sp:
25ff6af1 316 sp->free(sp);
5ff1d584 317done:
726b8548
QT		 318 fcport->flags &= ~FCF_ASYNC_SENT;
319 return rval;
320}
321
322static void qla24xx_handle_gnl_done_event(scsi_qla_host_t *vha,
323 struct event_arg *ea)
324{
325 fc_port_t *fcport, *conflict_fcport;
326 struct get_name_list_extended *e;
327 u16 i, n, found = 0, loop_id;
328 port_id_t id;
329 u64 wwn;
330 u8 opt = 0;
331
332 fcport = ea->fcport;
333
334 if (ea->rc) { /* rval */
335 if (fcport->login_retry == 0) {
336 fcport->login_retry = vha->hw->login_retry_count;
337 ql_dbg(ql_dbg_disc, vha, 0xffff,
338 "GNL failed Port login retry %8phN, retry cnt=%d.\n",
339 fcport->port_name, fcport->login_retry);
340 }
341 return;
342 }
343
344 if (fcport->last_rscn_gen != fcport->rscn_gen) {
345 ql_dbg(ql_dbg_disc, vha, 0xffff,
346 "%s %8phC rscn gen changed rscn %d|%d \n",
347 __func__, fcport->port_name,
348 fcport->last_rscn_gen, fcport->rscn_gen);
349 qla24xx_post_gidpn_work(vha, fcport);
350 return;
351 } else if (fcport->last_login_gen != fcport->login_gen) {
352 ql_dbg(ql_dbg_disc, vha, 0xffff,
353 "%s %8phC login gen changed login %d|%d \n",
354 __func__, fcport->port_name,
355 fcport->last_login_gen, fcport->login_gen);
356 return;
357 }
358
359 n = ea->data[0] / sizeof(struct get_name_list_extended);
360
361 ql_dbg(ql_dbg_disc, vha, 0xffff,
362 "%s %d %8phC n %d %02x%02x%02x lid %d \n",
363 __func__, __LINE__, fcport->port_name, n,
364 fcport->d_id.b.domain, fcport->d_id.b.area,
365 fcport->d_id.b.al_pa, fcport->loop_id);
366
367 for (i = 0; i < n; i++) {
368 e = &vha->gnl.l[i];
369 wwn = wwn_to_u64(e->port_name);
370
371 if (memcmp((u8 *)&wwn, fcport->port_name, WWN_SIZE))
372 continue;
373
374 found = 1;
375 id.b.domain = e->port_id[2];
376 id.b.area = e->port_id[1];
377 id.b.al_pa = e->port_id[0];
378 id.b.rsvd_1 = 0;
379
380 loop_id = le16_to_cpu(e->nport_handle);
381 loop_id = (loop_id & 0x7fff);
382
383 ql_dbg(ql_dbg_disc, vha, 0xffff,
384 "%s found %8phC CLS [%d|%d] ID[%02x%02x%02x|%02x%02x%02x] lid[%d|%d]\n",
385 __func__, fcport->port_name,
386 e->current_login_state, fcport->fw_login_state,
387 id.b.domain, id.b.area, id.b.al_pa,
388 fcport->d_id.b.domain, fcport->d_id.b.area,
389 fcport->d_id.b.al_pa, loop_id, fcport->loop_id);
390
391 if ((id.b24 != fcport->d_id.b24) ||
392 ((fcport->loop_id != FC_NO_LOOP_ID) &&
393 (fcport->loop_id != loop_id))) {
394 ql_dbg(ql_dbg_disc, vha, 0xffff,
395 "%s %d %8phC post del sess\n",
396 __func__, __LINE__, fcport->port_name);
397 qlt_schedule_sess_for_deletion(fcport, 1);
398 return;
399 }
400
401 fcport->loop_id = loop_id;
402
403 wwn = wwn_to_u64(fcport->port_name);
404 qlt_find_sess_invalidate_other(vha, wwn,
405 id, loop_id, &conflict_fcport);
406
407 if (conflict_fcport) {
408 /*
409 * Another share fcport share the same loop_id &
410 * nport id. Conflict fcport needs to finish
411 * cleanup before this fcport can proceed to login.
412 */
413 conflict_fcport->conflict = fcport;
414 fcport->login_pause = 1;
415 }
416
417 switch (e->current_login_state) {
418 case DSC_LS_PRLI_COMP:
419 ql_dbg(ql_dbg_disc, vha, 0xffff,
420 "%s %d %8phC post gpdb\n",
421 __func__, __LINE__, fcport->port_name);
422 opt = PDO_FORCE_ADISC;
423 qla24xx_post_gpdb_work(vha, fcport, opt);
424 break;
425
426 case DSC_LS_PORT_UNAVAIL:
427 default:
428 if (fcport->loop_id == FC_NO_LOOP_ID) {
429 qla2x00_find_new_loop_id(vha, fcport);
430 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL;
431 }
432 ql_dbg(ql_dbg_disc, vha, 0xffff,
433 "%s %d %8phC \n",
434 __func__, __LINE__, fcport->port_name);
435 qla24xx_fcport_handle_login(vha, fcport);
436 break;
437 }
438 }
439
440 if (!found) {
441 /* fw has no record of this port */
442 if (fcport->loop_id == FC_NO_LOOP_ID) {
443 qla2x00_find_new_loop_id(vha, fcport);
444 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL;
445 } else {
446 for (i = 0; i < n; i++) {
447 e = &vha->gnl.l[i];
448 id.b.domain = e->port_id[0];
449 id.b.area = e->port_id[1];
450 id.b.al_pa = e->port_id[2];
451 id.b.rsvd_1 = 0;
452 loop_id = le16_to_cpu(e->nport_handle);
453
454 if (fcport->d_id.b24 == id.b24) {
455 conflict_fcport =
456 qla2x00_find_fcport_by_wwpn(vha,
457 e->port_name, 0);
458
459 ql_dbg(ql_dbg_disc, vha, 0xffff,
460 "%s %d %8phC post del sess\n",
461 __func__, __LINE__,
462 conflict_fcport->port_name);
463 qlt_schedule_sess_for_deletion
464 (conflict_fcport, 1);
465 }
466
467 if (fcport->loop_id == loop_id) {
468 /* FW already picked this loop id for another fcport */
469 qla2x00_find_new_loop_id(vha, fcport);
470 }
471 }
472 }
473 qla24xx_fcport_handle_login(vha, fcport);
474 }
475} /* gnl_event */
476
477static void
25ff6af1 478qla24xx_async_gnl_sp_done(void *s, int res)
726b8548 479{
25ff6af1
JC		 480 struct srb *sp = s;
481 struct scsi_qla_host *vha = sp->vha;
726b8548
QT		 482 unsigned long flags;
483 struct fc_port *fcport = NULL, *tf;
484 u16 i, n = 0, loop_id;
485 struct event_arg ea;
486 struct get_name_list_extended *e;
487 u64 wwn;
488 struct list_head h;
489
490 ql_dbg(ql_dbg_disc, vha, 0xffff,
491 "Async done-%s res %x mb[1]=%x mb[2]=%x \n",
492 sp->name, res, sp->u.iocb_cmd.u.mbx.in_mb[1],
493 sp->u.iocb_cmd.u.mbx.in_mb[2]);
494
495 memset(&ea, 0, sizeof(ea));
496 ea.sp = sp;
497 ea.rc = res;
498 ea.event = FCME_GNL_DONE;
499
500 if (sp->u.iocb_cmd.u.mbx.in_mb[1] >=
501 sizeof(struct get_name_list_extended)) {
502 n = sp->u.iocb_cmd.u.mbx.in_mb[1] /
503 sizeof(struct get_name_list_extended);
504 ea.data[0] = sp->u.iocb_cmd.u.mbx.in_mb[1]; /* amnt xfered */
505 }
506
507 for (i = 0; i < n; i++) {
508 e = &vha->gnl.l[i];
509 loop_id = le16_to_cpu(e->nport_handle);
510 /* mask out reserve bit */
511 loop_id = (loop_id & 0x7fff);
512 set_bit(loop_id, vha->hw->loop_id_map);
513 wwn = wwn_to_u64(e->port_name);
514
515 ql_dbg(ql_dbg_disc + ql_dbg_verbose, vha, 0xffff,
516 "%s %8phC %02x:%02x:%02x state %d/%d lid %x \n",
517 __func__, (void *)&wwn, e->port_id[2], e->port_id[1],
518 e->port_id[0], e->current_login_state, e->last_login_state,
519 (loop_id & 0x7fff));
520 }
521
522 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
523 vha->gnl.sent = 0;
524
525 INIT_LIST_HEAD(&h);
526 fcport = tf = NULL;
527 if (!list_empty(&vha->gnl.fcports))
528 list_splice_init(&vha->gnl.fcports, &h);
529
530 list_for_each_entry_safe(fcport, tf, &h, gnl_entry) {
531 list_del_init(&fcport->gnl_entry);
532 fcport->flags &= ~FCF_ASYNC_SENT;
533 ea.fcport = fcport;
534
535 qla2x00_fcport_event_handler(vha, &ea);
536 }
537
538 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
539
25ff6af1 540 sp->free(sp);
726b8548
QT		 541}
542
543int qla24xx_async_gnl(struct scsi_qla_host *vha, fc_port_t *fcport)
544{
545 srb_t *sp;
546 struct srb_iocb *mbx;
547 int rval = QLA_FUNCTION_FAILED;
548 unsigned long flags;
549 u16 *mb;
550
551 if (!vha->flags.online)
552 goto done;
553
554 ql_dbg(ql_dbg_disc, vha, 0xffff,
555 "Async-gnlist WWPN %8phC \n", fcport->port_name);
556
557 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
558 fcport->flags |= FCF_ASYNC_SENT;
559 fcport->disc_state = DSC_GNL;
560 fcport->last_rscn_gen = fcport->rscn_gen;
561 fcport->last_login_gen = fcport->login_gen;
562
563 list_add_tail(&fcport->gnl_entry, &vha->gnl.fcports);
564 if (vha->gnl.sent) {
565 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
566 rval = QLA_SUCCESS;
567 goto done;
568 }
569 vha->gnl.sent = 1;
570 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
571
572 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
573 if (!sp)
574 goto done;
575 sp->type = SRB_MB_IOCB;
576 sp->name = "gnlist";
577 sp->gen1 = fcport->rscn_gen;
578 sp->gen2 = fcport->login_gen;
579
580 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha)+2);
581
582 mb = sp->u.iocb_cmd.u.mbx.out_mb;
583 mb[0] = MBC_PORT_NODE_NAME_LIST;
584 mb[1] = BIT_2 | BIT_3;
585 mb[2] = MSW(vha->gnl.ldma);
586 mb[3] = LSW(vha->gnl.ldma);
587 mb[6] = MSW(MSD(vha->gnl.ldma));
588 mb[7] = LSW(MSD(vha->gnl.ldma));
589 mb[8] = vha->gnl.size;
590 mb[9] = vha->vp_idx;
591
592 mbx = &sp->u.iocb_cmd;
593 mbx->timeout = qla2x00_async_iocb_timeout;
594
595 sp->done = qla24xx_async_gnl_sp_done;
596
597 rval = qla2x00_start_sp(sp);
598 if (rval != QLA_SUCCESS)
599 goto done_free_sp;
600
601 ql_dbg(ql_dbg_disc, vha, 0xffff,
602 "Async-%s - OUT WWPN %8phC hndl %x\n",
603 sp->name, fcport->port_name, sp->handle);
604
605 return rval;
606
607done_free_sp:
25ff6af1 608 sp->free(sp);
726b8548
QT		 609done:
610 fcport->flags &= ~FCF_ASYNC_SENT;
611 return rval;
612}
613
614int qla24xx_post_gnl_work(struct scsi_qla_host *vha, fc_port_t *fcport)
615{
616 struct qla_work_evt *e;
617
618 e = qla2x00_alloc_work(vha, QLA_EVT_GNL);
619 if (!e)
620 return QLA_FUNCTION_FAILED;
621
622 e->u.fcport.fcport = fcport;
623 return qla2x00_post_work(vha, e);
624}
625
626static
25ff6af1 627void qla24xx_async_gpdb_sp_done(void *s, int res)
726b8548 628{
25ff6af1
JC		 629 struct srb *sp = s;
630 struct scsi_qla_host *vha = sp->vha;
726b8548 631 struct qla_hw_data *ha = vha->hw;
726b8548
QT		 632 struct port_database_24xx *pd;
633 fc_port_t *fcport = sp->fcport;
634 u16 *mb = sp->u.iocb_cmd.u.mbx.in_mb;
635 int rval = QLA_SUCCESS;
636 struct event_arg ea;
637
638 ql_dbg(ql_dbg_disc, vha, 0xffff,
639 "Async done-%s res %x, WWPN %8phC mb[1]=%x mb[2]=%x \n",
640 sp->name, res, fcport->port_name, mb[1], mb[2]);
641
642 fcport->flags &= ~FCF_ASYNC_SENT;
643
644 if (res) {
645 rval = res;
646 goto gpd_error_out;
647 }
648
649 pd = (struct port_database_24xx *)sp->u.iocb_cmd.u.mbx.in;
650
15f30a57 651 rval = __qla24xx_parse_gpdb(vha, fcport, pd);
726b8548
QT		 652
653gpd_error_out:
654 memset(&ea, 0, sizeof(ea));
655 ea.event = FCME_GPDB_DONE;
656 ea.rc = rval;
657 ea.fcport = fcport;
658 ea.sp = sp;
659
660 qla2x00_fcport_event_handler(vha, &ea);
661
662 dma_pool_free(ha->s_dma_pool, sp->u.iocb_cmd.u.mbx.in,
663 sp->u.iocb_cmd.u.mbx.in_dma);
664
25ff6af1 665 sp->free(sp);
726b8548
QT		 666}
667
668static int qla24xx_post_gpdb_work(struct scsi_qla_host *vha, fc_port_t *fcport,
669 u8 opt)
670{
671 struct qla_work_evt *e;
672
673 e = qla2x00_alloc_work(vha, QLA_EVT_GPDB);
674 if (!e)
675 return QLA_FUNCTION_FAILED;
676
677 e->u.fcport.fcport = fcport;
678 e->u.fcport.opt = opt;
679 return qla2x00_post_work(vha, e);
680}
681
682int qla24xx_async_gpdb(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt)
683{
684 srb_t *sp;
685 struct srb_iocb *mbx;
686 int rval = QLA_FUNCTION_FAILED;
687 u16 *mb;
688 dma_addr_t pd_dma;
689 struct port_database_24xx *pd;
690 struct qla_hw_data *ha = vha->hw;
691
692 if (!vha->flags.online)
693 goto done;
694
695 fcport->flags |= FCF_ASYNC_SENT;
696 fcport->disc_state = DSC_GPDB;
697
698 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
699 if (!sp)
700 goto done;
701
702 pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
703 if (pd == NULL) {
704 ql_log(ql_log_warn, vha, 0xffff,
705 "Failed to allocate port database structure.\n");
706 goto done_free_sp;
707 }
708 memset(pd, 0, max(PORT_DATABASE_SIZE, PORT_DATABASE_24XX_SIZE));
709
710 sp->type = SRB_MB_IOCB;
711 sp->name = "gpdb";
712 sp->gen1 = fcport->rscn_gen;
713 sp->gen2 = fcport->login_gen;
714 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
715
716 mb = sp->u.iocb_cmd.u.mbx.out_mb;
717 mb[0] = MBC_GET_PORT_DATABASE;
718 mb[1] = fcport->loop_id;
719 mb[2] = MSW(pd_dma);
720 mb[3] = LSW(pd_dma);
721 mb[6] = MSW(MSD(pd_dma));
722 mb[7] = LSW(MSD(pd_dma));
723 mb[9] = vha->vp_idx;
724 mb[10] = opt;
725
726 mbx = &sp->u.iocb_cmd;
727 mbx->timeout = qla2x00_async_iocb_timeout;
728 mbx->u.mbx.in = (void *)pd;
729 mbx->u.mbx.in_dma = pd_dma;
730
731 sp->done = qla24xx_async_gpdb_sp_done;
732
733 rval = qla2x00_start_sp(sp);
734 if (rval != QLA_SUCCESS)
735 goto done_free_sp;
736
737 ql_dbg(ql_dbg_disc, vha, 0xffff,
738 "Async-%s %8phC hndl %x opt %x\n",
739 sp->name, fcport->port_name, sp->handle, opt);
740
741 return rval;
742
743done_free_sp:
744 if (pd)
745 dma_pool_free(ha->s_dma_pool, pd, pd_dma);
746
25ff6af1 747 sp->free(sp);
726b8548
QT		 748done:
749 fcport->flags &= ~FCF_ASYNC_SENT;
750 qla24xx_post_gpdb_work(vha, fcport, opt);
5ff1d584
AV		 751 return rval;
752}
753
726b8548
QT		 754static
755void qla24xx_handle_gpdb_event(scsi_qla_host_t *vha, struct event_arg *ea)
756{
757 int rval = ea->rc;
758 fc_port_t *fcport = ea->fcport;
759 unsigned long flags;
760
761 fcport->flags &= ~FCF_ASYNC_SENT;
762
763 ql_dbg(ql_dbg_disc, vha, 0xffff,
764 "%s %8phC DS %d LS %d rval %d\n", __func__, fcport->port_name,
765 fcport->disc_state, fcport->fw_login_state, rval);
766
767 if (ea->sp->gen2 != fcport->login_gen) {
768 /* target side must have changed it. */
769 ql_dbg(ql_dbg_disc, vha, 0xffff,
770 "%s %8phC generation changed rscn %d|%d login %d|%d \n",
771 __func__, fcport->port_name, fcport->last_rscn_gen,
772 fcport->rscn_gen, fcport->last_login_gen,
773 fcport->login_gen);
774 return;
775 } else if (ea->sp->gen1 != fcport->rscn_gen) {
776 ql_dbg(ql_dbg_disc, vha, 0xffff, "%s %d %8phC post gidpn\n",
777 __func__, __LINE__, fcport->port_name);
778 qla24xx_post_gidpn_work(vha, fcport);
779 return;
780 }
781
782 if (rval != QLA_SUCCESS) {
783 ql_dbg(ql_dbg_disc, vha, 0xffff, "%s %d %8phC post del sess\n",
784 __func__, __LINE__, fcport->port_name);
785 qlt_schedule_sess_for_deletion_lock(fcport);
786 return;
787 }
788
789 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
790 ea->fcport->login_gen++;
791 ea->fcport->deleted = 0;
792 ea->fcport->logout_on_delete = 1;
793
794 if (!ea->fcport->login_succ && !IS_SW_RESV_ADDR(ea->fcport->d_id)) {
795 vha->fcport_count++;
796 ea->fcport->login_succ = 1;
797
798 if (!IS_IIDMA_CAPABLE(vha->hw) ||
799 !vha->hw->flags.gpsc_supported) {
800 ql_dbg(ql_dbg_disc, vha, 0xffff,
801 "%s %d %8phC post upd_fcport fcp_cnt %d\n",
802 __func__, __LINE__, fcport->port_name,
803 vha->fcport_count);
804
805 qla24xx_post_upd_fcport_work(vha, fcport);
806 } else {
807 ql_dbg(ql_dbg_disc, vha, 0xffff,
808 "%s %d %8phC post gpsc fcp_cnt %d\n",
809 __func__, __LINE__, fcport->port_name,
810 vha->fcport_count);
811
812 qla24xx_post_gpsc_work(vha, fcport);
813 }
814 }
815 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
816} /* gpdb event */
817
818int qla24xx_fcport_handle_login(struct scsi_qla_host *vha, fc_port_t *fcport)
819{
820 if (fcport->login_retry == 0)
821 return 0;
822
823 if (fcport->scan_state != QLA_FCPORT_FOUND)
824 return 0;
825
826 ql_dbg(ql_dbg_disc, vha, 0xffff,
827 "%s %8phC DS %d LS %d P %d fl %x confl %p rscn %d|%d login %d|%d retry %d lid %d\n",
828 __func__, fcport->port_name, fcport->disc_state,
829 fcport->fw_login_state, fcport->login_pause, fcport->flags,
830 fcport->conflict, fcport->last_rscn_gen, fcport->rscn_gen,
831 fcport->last_login_gen, fcport->login_gen, fcport->login_retry,
832 fcport->loop_id);
833
834 fcport->login_retry--;
835
836 if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) ||
726b8548
QT		 837 (fcport->fw_login_state == DSC_LS_PRLI_PEND))
838 return 0;
839
5b33469a
QT		 840 if (fcport->fw_login_state == DSC_LS_PLOGI_COMP) {
841 if (time_before_eq(jiffies, fcport->plogi_nack_done_deadline))
842 return 0;
843 }
844
726b8548
QT		 845 /* for pure Target Mode. Login will not be initiated */
846 if (vha->host->active_mode == MODE_TARGET)
847 return 0;
848
849 if (fcport->flags & FCF_ASYNC_SENT) {
850 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
851 return 0;
852 }
853
854 switch (fcport->disc_state) {
855 case DSC_DELETED:
856 if (fcport->loop_id == FC_NO_LOOP_ID) {
857 ql_dbg(ql_dbg_disc, vha, 0xffff,
858 "%s %d %8phC post gnl\n",
859 __func__, __LINE__, fcport->port_name);
860 qla24xx_async_gnl(vha, fcport);
861 } else {
862 ql_dbg(ql_dbg_disc, vha, 0xffff,
863 "%s %d %8phC post login\n",
864 __func__, __LINE__, fcport->port_name);
865 fcport->disc_state = DSC_LOGIN_PEND;
866 qla2x00_post_async_login_work(vha, fcport, NULL);
867 }
868 break;
869
870 case DSC_GNL:
871 if (fcport->login_pause) {
872 fcport->last_rscn_gen = fcport->rscn_gen;
873 fcport->last_login_gen = fcport->login_gen;
874 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
875 break;
876 }
877
878 if (fcport->flags & FCF_FCP2_DEVICE) {
879 u8 opt = PDO_FORCE_ADISC;
880
881 ql_dbg(ql_dbg_disc, vha, 0xffff,
882 "%s %d %8phC post gpdb\n",
883 __func__, __LINE__, fcport->port_name);
884
885 fcport->disc_state = DSC_GPDB;
886 qla24xx_post_gpdb_work(vha, fcport, opt);
887 } else {
888 ql_dbg(ql_dbg_disc, vha, 0xffff,
889 "%s %d %8phC post login \n",
890 __func__, __LINE__, fcport->port_name);
891 fcport->disc_state = DSC_LOGIN_PEND;
892 qla2x00_post_async_login_work(vha, fcport, NULL);
893 }
894
895 break;
896
897 case DSC_LOGIN_FAILED:
898 ql_dbg(ql_dbg_disc, vha, 0xffff,
899 "%s %d %8phC post gidpn \n",
900 __func__, __LINE__, fcport->port_name);
901
902 qla24xx_post_gidpn_work(vha, fcport);
903 break;
904
905 case DSC_LOGIN_COMPLETE:
906 /* recheck login state */
907 ql_dbg(ql_dbg_disc, vha, 0xffff,
908 "%s %d %8phC post gpdb \n",
909 __func__, __LINE__, fcport->port_name);
910
911 qla24xx_post_gpdb_work(vha, fcport, PDO_FORCE_ADISC);
912 break;
913
914 default:
915 break;
916 }
917
918 return 0;
919}
920
921static
922void qla24xx_handle_rscn_event(fc_port_t *fcport, struct event_arg *ea)
923{
924 fcport->rscn_gen++;
925
926 ql_dbg(ql_dbg_disc, fcport->vha, 0xffff,
927 "%s %8phC DS %d LS %d\n",
928 __func__, fcport->port_name, fcport->disc_state,
929 fcport->fw_login_state);
930
931 if (fcport->flags & FCF_ASYNC_SENT)
932 return;
933
934 switch (fcport->disc_state) {
935 case DSC_DELETED:
936 case DSC_LOGIN_COMPLETE:
937 qla24xx_post_gidpn_work(fcport->vha, fcport);
938 break;
939
940 default:
941 break;
942 }
943}
944
945int qla24xx_post_newsess_work(struct scsi_qla_host *vha, port_id_t *id,
946 u8 *port_name, void *pla)
947{
948 struct qla_work_evt *e;
949 e = qla2x00_alloc_work(vha, QLA_EVT_NEW_SESS);
950 if (!e)
951 return QLA_FUNCTION_FAILED;
952
953 e->u.new_sess.id = *id;
954 e->u.new_sess.pla = pla;
955 memcpy(e->u.new_sess.port_name, port_name, WWN_SIZE);
956
957 return qla2x00_post_work(vha, e);
958}
959
960static
961int qla24xx_handle_delete_done_event(scsi_qla_host_t *vha,
962 struct event_arg *ea)
963{
964 fc_port_t *fcport = ea->fcport;
965
966 if (test_bit(UNLOADING, &vha->dpc_flags))
967 return 0;
968
969 switch (vha->host->active_mode) {
970 case MODE_INITIATOR:
971 case MODE_DUAL:
972 if (fcport->scan_state == QLA_FCPORT_FOUND)
973 qla24xx_fcport_handle_login(vha, fcport);
974 break;
975
976 case MODE_TARGET:
977 default:
978 /* no-op */
979 break;
980 }
981
982 return 0;
983}
984
985static
986void qla24xx_handle_relogin_event(scsi_qla_host_t *vha,
987 struct event_arg *ea)
988{
989 fc_port_t *fcport = ea->fcport;
990
991 if (fcport->scan_state != QLA_FCPORT_FOUND) {
992 fcport->login_retry++;
993 return;
994 }
995
996 ql_dbg(ql_dbg_disc, vha, 0xffff,
997 "%s %8phC DS %d LS %d P %d del %d cnfl %p rscn %d|%d login %d|%d fl %x\n",
998 __func__, fcport->port_name, fcport->disc_state,
999 fcport->fw_login_state, fcport->login_pause,
1000 fcport->deleted, fcport->conflict,
1001 fcport->last_rscn_gen, fcport->rscn_gen,
1002 fcport->last_login_gen, fcport->login_gen,
1003 fcport->flags);
1004
1005 if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) ||
726b8548
QT		 1006 (fcport->fw_login_state == DSC_LS_PRLI_PEND))
1007 return;
1008
5b33469a
QT		 1009 if (fcport->fw_login_state == DSC_LS_PLOGI_COMP) {
1010 if (time_before_eq(jiffies, fcport->plogi_nack_done_deadline))
1011 return;
1012 }
1013
726b8548
QT		 1014 if (fcport->flags & FCF_ASYNC_SENT) {
1015 fcport->login_retry++;
1016 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1017 return;
1018 }
1019
1020 if (fcport->disc_state == DSC_DELETE_PEND) {
1021 fcport->login_retry++;
1022 return;
1023 }
1024
1025 if (fcport->last_rscn_gen != fcport->rscn_gen) {
1026 ql_dbg(ql_dbg_disc, vha, 0xffff, "%s %d %8phC post gidpn\n",
1027 __func__, __LINE__, fcport->port_name);
1028
1029 qla24xx_async_gidpn(vha, fcport);
1030 return;
1031 }
1032
1033 qla24xx_fcport_handle_login(vha, fcport);
1034}
1035
41dc529a 1036void qla2x00_fcport_event_handler(scsi_qla_host_t *vha, struct event_arg *ea)
726b8548 1037{
41dc529a
QT		 1038 fc_port_t *fcport, *f, *tf;
1039 uint32_t id = 0, mask, rid;
726b8548
QT		 1040 int rc;
1041
1042 switch (ea->event) {
1043 case FCME_RELOGIN:
1044 if (test_bit(UNLOADING, &vha->dpc_flags))
1045 return;
5ff1d584 1046
726b8548
QT		 1047 qla24xx_handle_relogin_event(vha, ea);
1048 break;
1049 case FCME_RSCN:
1050 if (test_bit(UNLOADING, &vha->dpc_flags))
1051 return;
41dc529a
QT		 1052 switch (ea->id.b.rsvd_1) {
1053 case RSCN_PORT_ADDR:
1054 fcport = qla2x00_find_fcport_by_nportid(vha, &ea->id, 1);
1055 if (!fcport) {
1056 /* cable moved */
1057 rc = qla24xx_post_gpnid_work(vha, &ea->id);
1058 if (rc) {
1059 ql_log(ql_log_warn, vha, 0xffff,
1060 "RSCN GPNID work failed %02x%02x%02x\n",
1061 ea->id.b.domain, ea->id.b.area,
1062 ea->id.b.al_pa);
1063 }
1064 } else {
1065 ea->fcport = fcport;
1066 qla24xx_handle_rscn_event(fcport, ea);
1067 }
1068 break;
1069 case RSCN_AREA_ADDR:
1070 case RSCN_DOM_ADDR:
1071 if (ea->id.b.rsvd_1 == RSCN_AREA_ADDR) {
1072 mask = 0xffff00;
1073 ql_log(ql_dbg_async, vha, 0xffff,
1074 "RSCN: Area 0x%06x was affected\n",
1075 ea->id.b24);
1076 } else {
1077 mask = 0xff0000;
1078 ql_log(ql_dbg_async, vha, 0xffff,
1079 "RSCN: Domain 0x%06x was affected\n",
1080 ea->id.b24);
1081 }
726b8548 1082
41dc529a
QT		 1083 rid = ea->id.b24 & mask;
1084 list_for_each_entry_safe(f, tf, &vha->vp_fcports,
1085 list) {
1086 id = f->d_id.b24 & mask;
1087 if (rid == id) {
1088 ea->fcport = f;
1089 qla24xx_handle_rscn_event(f, ea);
1090 }
726b8548 1091 }
41dc529a
QT		 1092 break;
1093 case RSCN_FAB_ADDR:
1094 default:
1095 ql_log(ql_log_warn, vha, 0xffff,
1096 "RSCN: Fabric was affected. Addr format %d\n",
1097 ea->id.b.rsvd_1);
1098 qla2x00_mark_all_devices_lost(vha, 1);
1099 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1100 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
726b8548
QT		 1101 }
1102 break;
1103 case FCME_GIDPN_DONE:
1104 qla24xx_handle_gidpn_event(vha, ea);
1105 break;
1106 case FCME_GNL_DONE:
1107 qla24xx_handle_gnl_done_event(vha, ea);
1108 break;
1109 case FCME_GPSC_DONE:
1110 qla24xx_post_upd_fcport_work(vha, ea->fcport);
1111 break;
1112 case FCME_PLOGI_DONE: /* Initiator side sent LLIOCB */
1113 qla24xx_handle_plogi_done_event(vha, ea);
1114 break;
1115 case FCME_GPDB_DONE:
1116 qla24xx_handle_gpdb_event(vha, ea);
1117 break;
1118 case FCME_GPNID_DONE:
1119 qla24xx_handle_gpnid_event(vha, ea);
1120 break;
1121 case FCME_DELETE_DONE:
1122 qla24xx_handle_delete_done_event(vha, ea);
1123 break;
1124 default:
1125 BUG_ON(1);
1126 break;
1127 }
5ff1d584
AV		 1128}
1129
3822263e 1130static void
faef62d1 1131qla2x00_tmf_iocb_timeout(void *data)
3822263e 1132{
25ff6af1 1133 srb_t *sp = data;
faef62d1 1134 struct srb_iocb *tmf = &sp->u.iocb_cmd;
3822263e 1135
faef62d1
AB		 1136 tmf->u.tmf.comp_status = CS_TIMEOUT;
1137 complete(&tmf->u.tmf.comp);
1138}
9ba56b95 1139
faef62d1 1140static void
25ff6af1 1141qla2x00_tmf_sp_done(void *ptr, int res)
faef62d1 1142{
25ff6af1 1143 srb_t *sp = ptr;
faef62d1 1144 struct srb_iocb *tmf = &sp->u.iocb_cmd;
25ff6af1 1145
faef62d1 1146 complete(&tmf->u.tmf.comp);
3822263e
MI		 1147}
1148
1149int
faef62d1 1150qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t flags, uint32_t lun,
3822263e
MI		 1151 uint32_t tag)
1152{
1153 struct scsi_qla_host *vha = fcport->vha;
faef62d1 1154 struct srb_iocb *tm_iocb;
3822263e 1155 srb_t *sp;
faef62d1 1156 int rval = QLA_FUNCTION_FAILED;
3822263e 1157
9ba56b95 1158 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
3822263e
MI		 1159 if (!sp)
1160 goto done;
1161
faef62d1 1162 tm_iocb = &sp->u.iocb_cmd;
9ba56b95
GM		 1163 sp->type = SRB_TM_CMD;
1164 sp->name = "tmf";
faef62d1
AB		 1165 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
1166 tm_iocb->u.tmf.flags = flags;
1167 tm_iocb->u.tmf.lun = lun;
1168 tm_iocb->u.tmf.data = tag;
1169 sp->done = qla2x00_tmf_sp_done;
1170 tm_iocb->timeout = qla2x00_tmf_iocb_timeout;
1171 init_completion(&tm_iocb->u.tmf.comp);
3822263e
MI		 1172
1173 rval = qla2x00_start_sp(sp);
1174 if (rval != QLA_SUCCESS)
1175 goto done_free_sp;
1176
7c3df132 1177 ql_dbg(ql_dbg_taskm, vha, 0x802f,
cfb0919c
CD		 1178 "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
1179 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
1180 fcport->d_id.b.area, fcport->d_id.b.al_pa);
faef62d1
AB		 1181
1182 wait_for_completion(&tm_iocb->u.tmf.comp);
1183
1184 rval = tm_iocb->u.tmf.comp_status == CS_COMPLETE ?
1185 QLA_SUCCESS : QLA_FUNCTION_FAILED;
1186
1187 if ((rval != QLA_SUCCESS) || tm_iocb->u.tmf.data) {
1188 ql_dbg(ql_dbg_taskm, vha, 0x8030,
1189 "TM IOCB failed (%x).\n", rval);
1190 }
1191
1192 if (!test_bit(UNLOADING, &vha->dpc_flags) && !IS_QLAFX00(vha->hw)) {
1193 flags = tm_iocb->u.tmf.flags;
1194 lun = (uint16_t)tm_iocb->u.tmf.lun;
1195
1196 /* Issue Marker IOCB */
1197 qla2x00_marker(vha, vha->hw->req_q_map[0],
1198 vha->hw->rsp_q_map[0], sp->fcport->loop_id, lun,
1199 flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
1200 }
3822263e
MI		 1201
1202done_free_sp:
25ff6af1 1203 sp->free(sp);
3822263e
MI		 1204done:
1205 return rval;
1206}
1207
4440e46d
AB		 1208static void
1209qla24xx_abort_iocb_timeout(void *data)
1210{
25ff6af1 1211 srb_t *sp = data;
4440e46d
AB		 1212 struct srb_iocb *abt = &sp->u.iocb_cmd;
1213
1214 abt->u.abt.comp_status = CS_TIMEOUT;
1215 complete(&abt->u.abt.comp);
1216}
1217
1218static void
25ff6af1 1219qla24xx_abort_sp_done(void *ptr, int res)
4440e46d 1220{
25ff6af1 1221 srb_t *sp = ptr;
4440e46d
AB		 1222 struct srb_iocb *abt = &sp->u.iocb_cmd;
1223
1224 complete(&abt->u.abt.comp);
1225}
1226
15f30a57 1227int
4440e46d
AB		 1228qla24xx_async_abort_cmd(srb_t *cmd_sp)
1229{
25ff6af1 1230 scsi_qla_host_t *vha = cmd_sp->vha;
4440e46d
AB		 1231 fc_port_t *fcport = cmd_sp->fcport;
1232 struct srb_iocb *abt_iocb;
1233 srb_t *sp;
1234 int rval = QLA_FUNCTION_FAILED;
1235
1236 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
1237 if (!sp)
1238 goto done;
1239
1240 abt_iocb = &sp->u.iocb_cmd;
1241 sp->type = SRB_ABT_CMD;
1242 sp->name = "abort";
1243 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
1244 abt_iocb->u.abt.cmd_hndl = cmd_sp->handle;
1245 sp->done = qla24xx_abort_sp_done;
1246 abt_iocb->timeout = qla24xx_abort_iocb_timeout;
1247 init_completion(&abt_iocb->u.abt.comp);
1248
1249 rval = qla2x00_start_sp(sp);
1250 if (rval != QLA_SUCCESS)
1251 goto done_free_sp;
1252
1253 ql_dbg(ql_dbg_async, vha, 0x507c,
1254 "Abort command issued - hdl=%x, target_id=%x\n",
1255 cmd_sp->handle, fcport->tgt_id);
1256
1257 wait_for_completion(&abt_iocb->u.abt.comp);
1258
1259 rval = abt_iocb->u.abt.comp_status == CS_COMPLETE ?
1260 QLA_SUCCESS : QLA_FUNCTION_FAILED;
1261
1262done_free_sp:
25ff6af1 1263 sp->free(sp);
4440e46d
AB		 1264done:
1265 return rval;
1266}
1267
1268int
1269qla24xx_async_abort_command(srb_t *sp)
1270{
1271 unsigned long flags = 0;
1272
1273 uint32_t handle;
1274 fc_port_t *fcport = sp->fcport;
1275 struct scsi_qla_host *vha = fcport->vha;
1276 struct qla_hw_data *ha = vha->hw;
1277 struct req_que *req = vha->req;
1278
1279 spin_lock_irqsave(&ha->hardware_lock, flags);
1280 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
1281 if (req->outstanding_cmds[handle] == sp)
1282 break;
1283 }
1284 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1285 if (handle == req->num_outstanding_cmds) {
1286 /* Command not found. */
1287 return QLA_FUNCTION_FAILED;
1288 }
1289 if (sp->type == SRB_FXIOCB_DCMD)
1290 return qlafx00_fx_disc(vha, &vha->hw->mr.fcport,
1291 FXDISC_ABORT_IOCTL);
1292
1293 return qla24xx_async_abort_cmd(sp);
1294}
1295
726b8548
QT		 1296static void
1297qla24xx_handle_plogi_done_event(struct scsi_qla_host *vha, struct event_arg *ea)
ac280b67 1298{
726b8548 1299 port_id_t cid; /* conflict Nport id */
ac280b67 1300
726b8548 1301 switch (ea->data[0]) {
ac280b67 1302 case MBS_COMMAND_COMPLETE:
a4f92a32
AV		 1303 /*
1304 * Driver must validate login state - If PRLI not complete,
1305 * force a relogin attempt via implicit LOGO, PLOGI, and PRLI
1306 * requests.
1307 */
726b8548
QT		 1308 ql_dbg(ql_dbg_disc, vha, 0xffff,
1309 "%s %d %8phC post gpdb\n",
1310 __func__, __LINE__, ea->fcport->port_name);
1311 ea->fcport->chip_reset = vha->hw->chip_reset;
1312 ea->fcport->logout_on_delete = 1;
1313 qla24xx_post_gpdb_work(vha, ea->fcport, 0);
ac280b67
AV		 1314 break;
1315 case MBS_COMMAND_ERROR:
726b8548
QT		 1316 ql_dbg(ql_dbg_disc, vha, 0xffff, "%s %d %8phC cmd error %x\n",
1317 __func__, __LINE__, ea->fcport->port_name, ea->data[1]);
1318
1319 ea->fcport->flags &= ~FCF_ASYNC_SENT;
1320 ea->fcport->disc_state = DSC_LOGIN_FAILED;
1321 if (ea->data[1] & QLA_LOGIO_LOGIN_RETRIED)
ac280b67
AV		 1322 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1323 else
726b8548 1324 qla2x00_mark_device_lost(vha, ea->fcport, 1, 0);
ac280b67
AV		 1325 break;
1326 case MBS_LOOP_ID_USED:
726b8548
QT		 1327 /* data[1] = IO PARAM 1 = nport ID */
1328 cid.b.domain = (ea->iop[1] >> 16) & 0xff;
1329 cid.b.area = (ea->iop[1] >> 8) & 0xff;
1330 cid.b.al_pa = ea->iop[1] & 0xff;
1331 cid.b.rsvd_1 = 0;
1332
1333 ql_dbg(ql_dbg_disc, vha, 0xffff,
1334 "%s %d %8phC LoopID 0x%x in use post gnl\n",
1335 __func__, __LINE__, ea->fcport->port_name,
1336 ea->fcport->loop_id);
1337
1338 if (IS_SW_RESV_ADDR(cid)) {
1339 set_bit(ea->fcport->loop_id, vha->hw->loop_id_map);
1340 ea->fcport->loop_id = FC_NO_LOOP_ID;
1341 } else {
1342 qla2x00_clear_loop_id(ea->fcport);
ac280b67 1343 }
726b8548
QT		 1344 qla24xx_post_gnl_work(vha, ea->fcport);
1345 break;
1346 case MBS_PORT_ID_USED:
1347 ql_dbg(ql_dbg_disc, vha, 0xffff,
1348 "%s %d %8phC NPortId %02x%02x%02x inuse post gidpn\n",
1349 __func__, __LINE__, ea->fcport->port_name,
1350 ea->fcport->d_id.b.domain, ea->fcport->d_id.b.area,
1351 ea->fcport->d_id.b.al_pa);
1352
1353 qla2x00_clear_loop_id(ea->fcport);
1354 qla24xx_post_gidpn_work(vha, ea->fcport);
ac280b67
AV		 1355 break;
1356 }
4916392b 1357 return;
ac280b67
AV		 1358}
1359
4916392b 1360void
ac280b67
AV		 1361qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport,
1362 uint16_t *data)
1363{
726b8548 1364 qla2x00_mark_device_lost(vha, fcport, 1, 0);
a6ca8878 1365 qlt_logo_completion_handler(fcport, data[0]);
726b8548 1366 fcport->login_gen++;
4916392b 1367 return;
ac280b67
AV		 1368}
1369
4916392b 1370void
5ff1d584
AV		 1371qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport,
1372 uint16_t *data)
1373{
1374 if (data[0] == MBS_COMMAND_COMPLETE) {
1375 qla2x00_update_fcport(vha, fcport);
1376
4916392b 1377 return;
5ff1d584
AV		 1378 }
1379
1380 /* Retry login. */
1381 fcport->flags &= ~FCF_ASYNC_SENT;
1382 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
1383 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1384 else
80d79440 1385 qla2x00_mark_device_lost(vha, fcport, 1, 0);
5ff1d584 1386
4916392b 1387 return;
5ff1d584
AV		 1388}
1389
1da177e4
LT		 1390/****************************************************************************/
1391/* QLogic ISP2x00 Hardware Support Functions. */
1392/****************************************************************************/
1393
fa492630 1394static int
7d613ac6
SV		 1395qla83xx_nic_core_fw_load(scsi_qla_host_t *vha)
1396{
1397 int rval = QLA_SUCCESS;
1398 struct qla_hw_data *ha = vha->hw;
1399 uint32_t idc_major_ver, idc_minor_ver;
711aa7f7 1400 uint16_t config[4];
7d613ac6
SV		 1401
1402 qla83xx_idc_lock(vha, 0);
1403
1404 /* SV: TODO: Assign initialization timeout from
1405 * flash-info / other param
1406 */
1407 ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT;
1408 ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT;
1409
1410 /* Set our fcoe function presence */
1411 if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) {
1412 ql_dbg(ql_dbg_p3p, vha, 0xb077,
1413 "Error while setting DRV-Presence.\n");
1414 rval = QLA_FUNCTION_FAILED;
1415 goto exit;
1416 }
1417
1418 /* Decide the reset ownership */
1419 qla83xx_reset_ownership(vha);
1420
1421 /*
1422 * On first protocol driver load:
1423 * Init-Owner: Set IDC-Major-Version and Clear IDC-Lock-Recovery
1424 * register.
1425 * Others: Check compatibility with current IDC Major version.
1426 */
1427 qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver);
1428 if (ha->flags.nic_core_reset_owner) {
1429 /* Set IDC Major version */
1430 idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION;
1431 qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver);
1432
1433 /* Clearing IDC-Lock-Recovery register */
1434 qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0);
1435 } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) {
1436 /*
1437 * Clear further IDC participation if we are not compatible with
1438 * the current IDC Major Version.
1439 */
1440 ql_log(ql_log_warn, vha, 0xb07d,
1441 "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n",
1442 idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION);
1443 __qla83xx_clear_drv_presence(vha);
1444 rval = QLA_FUNCTION_FAILED;
1445 goto exit;
1446 }
1447 /* Each function sets its supported Minor version. */
1448 qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver);
1449 idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2));
1450 qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver);
1451
711aa7f7
SK		 1452 if (ha->flags.nic_core_reset_owner) {
1453 memset(config, 0, sizeof(config));
1454 if (!qla81xx_get_port_config(vha, config))
1455 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
1456 QLA8XXX_DEV_READY);
1457 }
1458
7d613ac6
SV		 1459 rval = qla83xx_idc_state_handler(vha);
1460
1461exit:
1462 qla83xx_idc_unlock(vha, 0);
1463
1464 return rval;
1465}
1466
1da177e4
LT		 1467/*
1468* qla2x00_initialize_adapter
1469* Initialize board.
1470*
1471* Input:
1472* ha = adapter block pointer.
1473*
1474* Returns:
1475* 0 = success
1476*/
1477int
e315cd28 1478qla2x00_initialize_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 1479{
1480 int rval;
e315cd28 1481 struct qla_hw_data *ha = vha->hw;
73208dfd 1482 struct req_que *req = ha->req_q_map[0];
2533cf67 1483
fc90adaf
JC		 1484 memset(&vha->qla_stats, 0, sizeof(vha->qla_stats));
1485 memset(&vha->fc_host_stat, 0, sizeof(vha->fc_host_stat));
1486
1da177e4 1487 /* Clear adapter flags. */
e315cd28 1488 vha->flags.online = 0;
2533cf67 1489 ha->flags.chip_reset_done = 0;
e315cd28 1490 vha->flags.reset_active = 0;
85880801
AV		 1491 ha->flags.pci_channel_io_perm_failure = 0;
1492 ha->flags.eeh_busy = 0;
fabbb8df 1493 vha->qla_stats.jiffies_at_last_reset = get_jiffies_64();
e315cd28
AC		 1494 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1495 atomic_set(&vha->loop_state, LOOP_DOWN);
1496 vha->device_flags = DFLG_NO_CABLE;
1497 vha->dpc_flags = 0;
1498 vha->flags.management_server_logged_in = 0;
1499 vha->marker_needed = 0;
1da177e4
LT		 1500 ha->isp_abort_cnt = 0;
1501 ha->beacon_blink_led = 0;
1502
73208dfd
AC		 1503 set_bit(0, ha->req_qid_map);
1504 set_bit(0, ha->rsp_qid_map);
1505
cfb0919c 1506 ql_dbg(ql_dbg_init, vha, 0x0040,
7c3df132 1507 "Configuring PCI space...\n");
e315cd28 1508 rval = ha->isp_ops->pci_config(vha);
1da177e4 1509 if (rval) {
7c3df132
SK		 1510 ql_log(ql_log_warn, vha, 0x0044,
1511 "Unable to configure PCI space.\n");
1da177e4
LT		 1512 return (rval);
1513 }
1514
e315cd28 1515 ha->isp_ops->reset_chip(vha);
1da177e4 1516
e315cd28 1517 rval = qla2xxx_get_flash_info(vha);
c00d8994 1518 if (rval) {
7c3df132
SK		 1519 ql_log(ql_log_fatal, vha, 0x004f,
1520 "Unable to validate FLASH data.\n");
7ec0effd
AD		 1521 return rval;
1522 }
1523
1524 if (IS_QLA8044(ha)) {
1525 qla8044_read_reset_template(vha);
1526
1527 /* NOTE: If ql2xdontresethba==1, set IDC_CTRL DONTRESET_BIT0.
1528 * If DONRESET_BIT0 is set, drivers should not set dev_state
1529 * to NEED_RESET. But if NEED_RESET is set, drivers should
1530 * should honor the reset. */
1531 if (ql2xdontresethba == 1)
1532 qla8044_set_idc_dontreset(vha);
c00d8994
AV		 1533 }
1534
73208dfd 1535 ha->isp_ops->get_flash_version(vha, req->ring);
cfb0919c 1536 ql_dbg(ql_dbg_init, vha, 0x0061,
7c3df132 1537 "Configure NVRAM parameters...\n");
0107109e 1538
e315cd28 1539 ha->isp_ops->nvram_config(vha);
1da177e4 1540
d4c760c2
AV		 1541 if (ha->flags.disable_serdes) {
1542 /* Mask HBA via NVRAM settings? */
7c3df132 1543 ql_log(ql_log_info, vha, 0x0077,
7b833558 1544 "Masking HBA WWPN %8phN (via NVRAM).\n", vha->port_name);
d4c760c2
AV		 1545 return QLA_FUNCTION_FAILED;
1546 }
1547
cfb0919c 1548 ql_dbg(ql_dbg_init, vha, 0x0078,
7c3df132 1549 "Verifying loaded RISC code...\n");
1da177e4 1550
e315cd28
AC		 1551 if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) {
1552 rval = ha->isp_ops->chip_diag(vha);
d19044c3
AV		 1553 if (rval)
1554 return (rval);
e315cd28 1555 rval = qla2x00_setup_chip(vha);
d19044c3
AV		 1556 if (rval)
1557 return (rval);
1da177e4 1558 }
a9083016 1559
4d4df193 1560 if (IS_QLA84XX(ha)) {
e315cd28 1561 ha->cs84xx = qla84xx_get_chip(vha);
4d4df193 1562 if (!ha->cs84xx) {
7c3df132 1563 ql_log(ql_log_warn, vha, 0x00d0,
4d4df193
HK		 1564 "Unable to configure ISP84XX.\n");
1565 return QLA_FUNCTION_FAILED;
1566 }
1567 }
2d70c103 1568
ead03855 1569 if (qla_ini_mode_enabled(vha) || qla_dual_mode_enabled(vha))
2d70c103
NB		 1570 rval = qla2x00_init_rings(vha);
1571
2533cf67 1572 ha->flags.chip_reset_done = 1;
1da177e4 1573
9a069e19 1574 if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) {
6c452a45 1575 /* Issue verify 84xx FW IOCB to complete 84xx initialization */
9a069e19
GM		 1576 rval = qla84xx_init_chip(vha);
1577 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1578 ql_log(ql_log_warn, vha, 0x00d4,
1579 "Unable to initialize ISP84XX.\n");
8d2b21db 1580 qla84xx_put_chip(vha);
9a069e19
GM		 1581 }
1582 }
1583
7d613ac6
SV		 1584 /* Load the NIC Core f/w if we are the first protocol driver. */
1585 if (IS_QLA8031(ha)) {
1586 rval = qla83xx_nic_core_fw_load(vha);
1587 if (rval)
1588 ql_log(ql_log_warn, vha, 0x0124,
1589 "Error in initializing NIC Core f/w.\n");
1590 }
1591
2f0f3f4f
MI		 1592 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
1593 qla24xx_read_fcp_prio_cfg(vha);
09ff701a 1594
c46e65c7
JC		 1595 if (IS_P3P_TYPE(ha))
1596 qla82xx_set_driver_version(vha, QLA2XXX_VERSION);
1597 else
1598 qla25xx_set_driver_version(vha, QLA2XXX_VERSION);
1599
1da177e4
LT		 1600 return (rval);
1601}
1602
1603/**
abbd8870 1604 * qla2100_pci_config() - Setup ISP21xx PCI configuration registers.
1da177e4
LT		 1605 * @ha: HA context
1606 *
1607 * Returns 0 on success.
1608 */
abbd8870 1609int
e315cd28 1610qla2100_pci_config(scsi_qla_host_t *vha)
1da177e4 1611{
a157b101 1612 uint16_t w;
abbd8870 1613 unsigned long flags;
e315cd28 1614 struct qla_hw_data *ha = vha->hw;
3d71644c 1615 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 1616
1da177e4 1617 pci_set_master(ha->pdev);
af6177d8 1618 pci_try_set_mwi(ha->pdev);
1da177e4 1619
1da177e4 1620 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 1621 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
abbd8870
AV		 1622 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1623
737faece 1624 pci_disable_rom(ha->pdev);
1da177e4
LT		 1625
1626 /* Get PCI bus information. */
1627 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 1628 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
1da177e4
LT		 1629 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1630
abbd8870
AV		 1631 return QLA_SUCCESS;
1632}
1da177e4 1633
abbd8870
AV		 1634/**
1635 * qla2300_pci_config() - Setup ISP23xx PCI configuration registers.
1636 * @ha: HA context
1637 *
1638 * Returns 0 on success.
1639 */
1640int
e315cd28 1641qla2300_pci_config(scsi_qla_host_t *vha)
abbd8870 1642{
a157b101 1643 uint16_t w;
abbd8870
AV		 1644 unsigned long flags = 0;
1645 uint32_t cnt;
e315cd28 1646 struct qla_hw_data *ha = vha->hw;
3d71644c 1647 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 1648
abbd8870 1649 pci_set_master(ha->pdev);
af6177d8 1650 pci_try_set_mwi(ha->pdev);
1da177e4 1651
abbd8870 1652 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 1653 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
1da177e4 1654
abbd8870
AV		 1655 if (IS_QLA2322(ha) || IS_QLA6322(ha))
1656 w &= ~PCI_COMMAND_INTX_DISABLE;
a157b101 1657 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1da177e4 1658
abbd8870
AV		 1659 /*
1660 * If this is a 2300 card and not 2312, reset the
1661 * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately,
1662 * the 2310 also reports itself as a 2300 so we need to get the
1663 * fb revision level -- a 6 indicates it really is a 2300 and
1664 * not a 2310.
1665 */
1666 if (IS_QLA2300(ha)) {
1667 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1668
abbd8870 1669 /* Pause RISC. */
3d71644c 1670 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
abbd8870 1671 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 1672 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
abbd8870 1673 break;
1da177e4 1674
abbd8870
AV		 1675 udelay(10);
1676 }
1da177e4 1677
abbd8870 1678 /* Select FPM registers. */
3d71644c
AV		 1679 WRT_REG_WORD(&reg->ctrl_status, 0x20);
1680 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 1681
1682 /* Get the fb rev level */
3d71644c 1683 ha->fb_rev = RD_FB_CMD_REG(ha, reg);
abbd8870
AV		 1684
1685 if (ha->fb_rev == FPM_2300)
a157b101 1686 pci_clear_mwi(ha->pdev);
abbd8870
AV		 1687
1688 /* Deselect FPM registers. */
3d71644c
AV		 1689 WRT_REG_WORD(&reg->ctrl_status, 0x0);
1690 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 1691
1692 /* Release RISC module. */
3d71644c 1693 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
abbd8870 1694 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 1695 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0)
abbd8870
AV		 1696 break;
1697
1698 udelay(10);
1da177e4 1699 }
1da177e4 1700
abbd8870
AV		 1701 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1702 }
1da177e4 1703
abbd8870
AV		 1704 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
1705
737faece 1706 pci_disable_rom(ha->pdev);
1da177e4 1707
abbd8870
AV		 1708 /* Get PCI bus information. */
1709 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 1710 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 1711 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1712
1713 return QLA_SUCCESS;
1da177e4
LT		 1714}
1715
0107109e
AV		 1716/**
1717 * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers.
1718 * @ha: HA context
1719 *
1720 * Returns 0 on success.
1721 */
1722int
e315cd28 1723qla24xx_pci_config(scsi_qla_host_t *vha)
0107109e 1724{
a157b101 1725 uint16_t w;
0107109e 1726 unsigned long flags = 0;
e315cd28 1727 struct qla_hw_data *ha = vha->hw;
0107109e 1728 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
0107109e
AV		 1729
1730 pci_set_master(ha->pdev);
af6177d8 1731 pci_try_set_mwi(ha->pdev);
0107109e
AV		 1732
1733 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 1734 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
0107109e
AV		 1735 w &= ~PCI_COMMAND_INTX_DISABLE;
1736 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1737
1738 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
1739
1740 /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */
f85ec187
AV		 1741 if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
1742 pcix_set_mmrbc(ha->pdev, 2048);
0107109e
AV		 1743
1744 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 1745 if (pci_is_pcie(ha->pdev))
5ffd3a52 1746 pcie_set_readrq(ha->pdev, 4096);
0107109e 1747
737faece 1748 pci_disable_rom(ha->pdev);
0107109e 1749
44c10138 1750 ha->chip_revision = ha->pdev->revision;
a8488abe 1751
0107109e
AV		 1752 /* Get PCI bus information. */
1753 spin_lock_irqsave(&ha->hardware_lock, flags);
1754 ha->pci_attr = RD_REG_DWORD(&reg->ctrl_status);
1755 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1756
1757 return QLA_SUCCESS;
1758}
1759
c3a2f0df
AV		 1760/**
1761 * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers.
1762 * @ha: HA context
1763 *
1764 * Returns 0 on success.
1765 */
1766int
e315cd28 1767qla25xx_pci_config(scsi_qla_host_t *vha)
c3a2f0df
AV		 1768{
1769 uint16_t w;
e315cd28 1770 struct qla_hw_data *ha = vha->hw;
c3a2f0df
AV		 1771
1772 pci_set_master(ha->pdev);
1773 pci_try_set_mwi(ha->pdev);
1774
1775 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
1776 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
1777 w &= ~PCI_COMMAND_INTX_DISABLE;
1778 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1779
1780 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 1781 if (pci_is_pcie(ha->pdev))
5ffd3a52 1782 pcie_set_readrq(ha->pdev, 4096);
c3a2f0df 1783
737faece 1784 pci_disable_rom(ha->pdev);
c3a2f0df
AV		 1785
1786 ha->chip_revision = ha->pdev->revision;
1787
1788 return QLA_SUCCESS;
1789}
1790
1da177e4
LT		 1791/**
1792 * qla2x00_isp_firmware() - Choose firmware image.
1793 * @ha: HA context
1794 *
1795 * Returns 0 on success.
1796 */
1797static int
e315cd28 1798qla2x00_isp_firmware(scsi_qla_host_t *vha)
1da177e4
LT		 1799{
1800 int rval;
42e421b1
AV		 1801 uint16_t loop_id, topo, sw_cap;
1802 uint8_t domain, area, al_pa;
e315cd28 1803 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 1804
1805 /* Assume loading risc code */
fa2a1ce5 1806 rval = QLA_FUNCTION_FAILED;
1da177e4
LT		 1807
1808 if (ha->flags.disable_risc_code_load) {
7c3df132 1809 ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n");
1da177e4
LT		 1810
1811 /* Verify checksum of loaded RISC code. */
e315cd28 1812 rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address);
42e421b1
AV		 1813 if (rval == QLA_SUCCESS) {
1814 /* And, verify we are not in ROM code. */
e315cd28 1815 rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa,
42e421b1
AV		 1816 &area, &domain, &topo, &sw_cap);
1817 }
1da177e4
LT		 1818 }
1819
7c3df132
SK		 1820 if (rval)
1821 ql_dbg(ql_dbg_init, vha, 0x007a,
1822 "**** Load RISC code ****.\n");
1da177e4
LT		 1823
1824 return (rval);
1825}
1826
1827/**
1828 * qla2x00_reset_chip() - Reset ISP chip.
1829 * @ha: HA context
1830 *
1831 * Returns 0 on success.
1832 */
abbd8870 1833void
e315cd28 1834qla2x00_reset_chip(scsi_qla_host_t *vha)
1da177e4
LT		 1835{
1836 unsigned long flags = 0;
e315cd28 1837 struct qla_hw_data *ha = vha->hw;
3d71644c 1838 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 1839 uint32_t cnt;
1da177e4
LT		 1840 uint16_t cmd;
1841
85880801
AV		 1842 if (unlikely(pci_channel_offline(ha->pdev)))
1843 return;
1844
fd34f556 1845 ha->isp_ops->disable_intrs(ha);
1da177e4
LT		 1846
1847 spin_lock_irqsave(&ha->hardware_lock, flags);
1848
1849 /* Turn off master enable */
1850 cmd = 0;
1851 pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd);
1852 cmd &= ~PCI_COMMAND_MASTER;
1853 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
1854
1855 if (!IS_QLA2100(ha)) {
1856 /* Pause RISC. */
1857 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1858 if (IS_QLA2200(ha) || IS_QLA2300(ha)) {
1859 for (cnt = 0; cnt < 30000; cnt++) {
1860 if ((RD_REG_WORD(&reg->hccr) &
1861 HCCR_RISC_PAUSE) != 0)
1862 break;
1863 udelay(100);
1864 }
1865 } else {
1866 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1867 udelay(10);
1868 }
1869
1870 /* Select FPM registers. */
1871 WRT_REG_WORD(&reg->ctrl_status, 0x20);
1872 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1873
1874 /* FPM Soft Reset. */
1875 WRT_REG_WORD(&reg->fpm_diag_config, 0x100);
1876 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
1877
1878 /* Toggle Fpm Reset. */
1879 if (!IS_QLA2200(ha)) {
1880 WRT_REG_WORD(&reg->fpm_diag_config, 0x0);
1881 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
1882 }
1883
1884 /* Select frame buffer registers. */
1885 WRT_REG_WORD(&reg->ctrl_status, 0x10);
1886 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1887
1888 /* Reset frame buffer FIFOs. */
1889 if (IS_QLA2200(ha)) {
1890 WRT_FB_CMD_REG(ha, reg, 0xa000);
1891 RD_FB_CMD_REG(ha, reg); /* PCI Posting. */
1892 } else {
1893 WRT_FB_CMD_REG(ha, reg, 0x00fc);
1894
1895 /* Read back fb_cmd until zero or 3 seconds max */
1896 for (cnt = 0; cnt < 3000; cnt++) {
1897 if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0)
1898 break;
1899 udelay(100);
1900 }
1901 }
1902
1903 /* Select RISC module registers. */
1904 WRT_REG_WORD(&reg->ctrl_status, 0);
1905 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1906
1907 /* Reset RISC processor. */
1908 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
1909 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1910
1911 /* Release RISC processor. */
1912 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
1913 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1914 }
1915
1916 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
1917 WRT_REG_WORD(&reg->hccr, HCCR_CLR_HOST_INT);
1918
1919 /* Reset ISP chip. */
1920 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1921
1922 /* Wait for RISC to recover from reset. */
1923 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1924 /*
1925 * It is necessary to for a delay here since the card doesn't
1926 * respond to PCI reads during a reset. On some architectures
1927 * this will result in an MCA.
1928 */
1929 udelay(20);
1930 for (cnt = 30000; cnt; cnt--) {
1931 if ((RD_REG_WORD(&reg->ctrl_status) &
1932 CSR_ISP_SOFT_RESET) == 0)
1933 break;
1934 udelay(100);
1935 }
1936 } else
1937 udelay(10);
1938
1939 /* Reset RISC processor. */
1940 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
1941
1942 WRT_REG_WORD(&reg->semaphore, 0);
1943
1944 /* Release RISC processor. */
1945 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
1946 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1947
1948 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1949 for (cnt = 0; cnt < 30000; cnt++) {
ffb39f03 1950 if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY)
1da177e4 1951 break;
1da177e4
LT		 1952
1953 udelay(100);
1954 }
1955 } else
1956 udelay(100);
1957
1958 /* Turn on master enable */
1959 cmd |= PCI_COMMAND_MASTER;
1960 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
1961
1962 /* Disable RISC pause on FPM parity error. */
1963 if (!IS_QLA2100(ha)) {
1964 WRT_REG_WORD(&reg->hccr, HCCR_DISABLE_PARITY_PAUSE);
1965 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1966 }
1967
1968 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1969}
1970
b1d46989
MI		 1971/**
1972 * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC.
1973 *
1974 * Returns 0 on success.
1975 */
fa492630 1976static int
b1d46989
MI		 1977qla81xx_reset_mpi(scsi_qla_host_t *vha)
1978{
1979 uint16_t mb[4] = {0x1010, 0, 1, 0};
1980
6246b8a1
GM		 1981 if (!IS_QLA81XX(vha->hw))
1982 return QLA_SUCCESS;
1983
b1d46989
MI		 1984 return qla81xx_write_mpi_register(vha, mb);
1985}
1986
0107109e 1987/**
88c26663 1988 * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC.
0107109e
AV		 1989 * @ha: HA context
1990 *
1991 * Returns 0 on success.
1992 */
d14e72fb 1993static inline int
e315cd28 1994qla24xx_reset_risc(scsi_qla_host_t *vha)
0107109e
AV		 1995{
1996 unsigned long flags = 0;
e315cd28 1997 struct qla_hw_data *ha = vha->hw;
0107109e 1998 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
52c82823 1999 uint32_t cnt;
335a1cc9 2000 uint16_t wd;
b1d46989 2001 static int abts_cnt; /* ISP abort retry counts */
d14e72fb 2002 int rval = QLA_SUCCESS;
0107109e 2003
0107109e
AV		 2004 spin_lock_irqsave(&ha->hardware_lock, flags);
2005
2006 /* Reset RISC. */
2007 WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
2008 for (cnt = 0; cnt < 30000; cnt++) {
2009 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
2010 break;
2011
2012 udelay(10);
2013 }
2014
d14e72fb
HM		 2015 if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE))
2016 set_bit(DMA_SHUTDOWN_CMPL, &ha->fw_dump_cap_flags);
2017
2018 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017e,
2019 "HCCR: 0x%x, Control Status %x, DMA active status:0x%x\n",
2020 RD_REG_DWORD(&reg->hccr),
2021 RD_REG_DWORD(&reg->ctrl_status),
2022 (RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE));
2023
0107109e
AV		 2024 WRT_REG_DWORD(&reg->ctrl_status,
2025 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
335a1cc9 2026 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
88c26663 2027
335a1cc9 2028 udelay(100);
d14e72fb 2029
88c26663 2030 /* Wait for firmware to complete NVRAM accesses. */
52c82823 2031 RD_REG_WORD(&reg->mailbox0);
d14e72fb
HM		 2032 for (cnt = 10000; RD_REG_WORD(&reg->mailbox0) != 0 &&
2033 rval == QLA_SUCCESS; cnt--) {
88c26663 2034 barrier();
d14e72fb
HM		 2035 if (cnt)
2036 udelay(5);
2037 else
2038 rval = QLA_FUNCTION_TIMEOUT;
88c26663
AV		 2039 }
2040
d14e72fb
HM		 2041 if (rval == QLA_SUCCESS)
2042 set_bit(ISP_MBX_RDY, &ha->fw_dump_cap_flags);
2043
2044 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017f,
2045 "HCCR: 0x%x, MailBox0 Status 0x%x\n",
2046 RD_REG_DWORD(&reg->hccr),
2047 RD_REG_DWORD(&reg->mailbox0));
2048
335a1cc9 2049 /* Wait for soft-reset to complete. */
52c82823 2050 RD_REG_DWORD(&reg->ctrl_status);
200ffb15 2051 for (cnt = 0; cnt < 60; cnt++) {
0107109e 2052 barrier();
d14e72fb
HM		 2053 if ((RD_REG_DWORD(&reg->ctrl_status) &
2054 CSRX_ISP_SOFT_RESET) == 0)
2055 break;
2056
2057 udelay(5);
0107109e 2058 }
d14e72fb
HM		 2059 if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_ISP_SOFT_RESET))
2060 set_bit(ISP_SOFT_RESET_CMPL, &ha->fw_dump_cap_flags);
2061
2062 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015d,
2063 "HCCR: 0x%x, Soft Reset status: 0x%x\n",
2064 RD_REG_DWORD(&reg->hccr),
2065 RD_REG_DWORD(&reg->ctrl_status));
0107109e 2066
b1d46989
MI		 2067 /* If required, do an MPI FW reset now */
2068 if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
2069 if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
2070 if (++abts_cnt < 5) {
2071 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2072 set_bit(MPI_RESET_NEEDED, &vha->dpc_flags);
2073 } else {
2074 /*
2075 * We exhausted the ISP abort retries. We have to
2076 * set the board offline.
2077 */
2078 abts_cnt = 0;
2079 vha->flags.online = 0;
2080 }
2081 }
2082 }
2083
0107109e
AV		 2084 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
2085 RD_REG_DWORD(&reg->hccr);
2086
2087 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
2088 RD_REG_DWORD(&reg->hccr);
2089
2090 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
2091 RD_REG_DWORD(&reg->hccr);
2092
52c82823 2093 RD_REG_WORD(&reg->mailbox0);
200ffb15 2094 for (cnt = 60; RD_REG_WORD(&reg->mailbox0) != 0 &&
d14e72fb 2095 rval == QLA_SUCCESS; cnt--) {
0107109e 2096 barrier();
d14e72fb
HM		 2097 if (cnt)
2098 udelay(5);
2099 else
2100 rval = QLA_FUNCTION_TIMEOUT;
0107109e 2101 }
d14e72fb
HM		 2102 if (rval == QLA_SUCCESS)
2103 set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags);
2104
2105 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015e,
2106 "Host Risc 0x%x, mailbox0 0x%x\n",
2107 RD_REG_DWORD(&reg->hccr),
2108 RD_REG_WORD(&reg->mailbox0));
0107109e
AV		 2109
2110 spin_unlock_irqrestore(&ha->hardware_lock, flags);
124f85e6 2111
d14e72fb
HM		 2112 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015f,
2113 "Driver in %s mode\n",
2114 IS_NOPOLLING_TYPE(ha) ? "Interrupt" : "Polling");
2115
124f85e6
AV		 2116 if (IS_NOPOLLING_TYPE(ha))
2117 ha->isp_ops->enable_intrs(ha);
d14e72fb
HM		 2118
2119 return rval;
0107109e
AV		 2120}
2121
4ea2c9c7
JC		 2122static void
2123qla25xx_read_risc_sema_reg(scsi_qla_host_t *vha, uint32_t *data)
2124{
2125 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
2126
2127 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
2128 *data = RD_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET);
2129
2130}
2131
2132static void
2133qla25xx_write_risc_sema_reg(scsi_qla_host_t *vha, uint32_t data)
2134{
2135 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
2136
2137 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
2138 WRT_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET, data);
2139}
2140
2141static void
2142qla25xx_manipulate_risc_semaphore(scsi_qla_host_t *vha)
2143{
4ea2c9c7
JC		 2144 uint32_t wd32 = 0;
2145 uint delta_msec = 100;
2146 uint elapsed_msec = 0;
2147 uint timeout_msec;
2148 ulong n;
2149
cc790764
JC		 2150 if (vha->hw->pdev->subsystem_device != 0x0175 &&
2151 vha->hw->pdev->subsystem_device != 0x0240)
4ea2c9c7
JC		 2152 return;
2153
8dd7e3a5
JC		 2154 WRT_REG_DWORD(&vha->hw->iobase->isp24.hccr, HCCRX_SET_RISC_PAUSE);
2155 udelay(100);
2156
4ea2c9c7
JC		 2157attempt:
2158 timeout_msec = TIMEOUT_SEMAPHORE;
2159 n = timeout_msec / delta_msec;
2160 while (n--) {
2161 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_SET);
2162 qla25xx_read_risc_sema_reg(vha, &wd32);
2163 if (wd32 & RISC_SEMAPHORE)
2164 break;
2165 msleep(delta_msec);
2166 elapsed_msec += delta_msec;
2167 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
2168 goto force;
2169 }
2170
2171 if (!(wd32 & RISC_SEMAPHORE))
2172 goto force;
2173
2174 if (!(wd32 & RISC_SEMAPHORE_FORCE))
2175 goto acquired;
2176
2177 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_CLR);
2178 timeout_msec = TIMEOUT_SEMAPHORE_FORCE;
2179 n = timeout_msec / delta_msec;
2180 while (n--) {
2181 qla25xx_read_risc_sema_reg(vha, &wd32);
2182 if (!(wd32 & RISC_SEMAPHORE_FORCE))
2183 break;
2184 msleep(delta_msec);
2185 elapsed_msec += delta_msec;
2186 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
2187 goto force;
2188 }
2189
2190 if (wd32 & RISC_SEMAPHORE_FORCE)
2191 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_CLR);
2192
2193 goto attempt;
2194
2195force:
2196 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_SET);
2197
2198acquired:
2199 return;
2200}
2201
88c26663
AV		 2202/**
2203 * qla24xx_reset_chip() - Reset ISP24xx chip.
2204 * @ha: HA context
2205 *
2206 * Returns 0 on success.
2207 */
2208void
e315cd28 2209qla24xx_reset_chip(scsi_qla_host_t *vha)
88c26663 2210{
e315cd28 2211 struct qla_hw_data *ha = vha->hw;
85880801
AV		 2212
2213 if (pci_channel_offline(ha->pdev) &&
2214 ha->flags.pci_channel_io_perm_failure) {
2215 return;
2216 }
2217
fd34f556 2218 ha->isp_ops->disable_intrs(ha);
88c26663 2219
4ea2c9c7
JC		 2220 qla25xx_manipulate_risc_semaphore(vha);
2221
88c26663 2222 /* Perform RISC reset. */
e315cd28 2223 qla24xx_reset_risc(vha);
88c26663
AV		 2224}
2225
1da177e4
LT		 2226/**
2227 * qla2x00_chip_diag() - Test chip for proper operation.
2228 * @ha: HA context
2229 *
2230 * Returns 0 on success.
2231 */
abbd8870 2232int
e315cd28 2233qla2x00_chip_diag(scsi_qla_host_t *vha)
1da177e4
LT		 2234{
2235 int rval;
e315cd28 2236 struct qla_hw_data *ha = vha->hw;
3d71644c 2237 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 2238 unsigned long flags = 0;
2239 uint16_t data;
2240 uint32_t cnt;
2241 uint16_t mb[5];
73208dfd 2242 struct req_que *req = ha->req_q_map[0];
1da177e4
LT		 2243
2244 /* Assume a failed state */
2245 rval = QLA_FUNCTION_FAILED;
2246
7c3df132
SK		 2247 ql_dbg(ql_dbg_init, vha, 0x007b,
2248 "Testing device at %lx.\n", (u_long)&reg->flash_address);
1da177e4
LT		 2249
2250 spin_lock_irqsave(&ha->hardware_lock, flags);
2251
2252 /* Reset ISP chip. */
2253 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
2254
2255 /*
2256 * We need to have a delay here since the card will not respond while
2257 * in reset causing an MCA on some architectures.
2258 */
2259 udelay(20);
2260 data = qla2x00_debounce_register(&reg->ctrl_status);
2261 for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {
2262 udelay(5);
2263 data = RD_REG_WORD(&reg->ctrl_status);
2264 barrier();
2265 }
2266
2267 if (!cnt)
2268 goto chip_diag_failed;
2269
7c3df132
SK		 2270 ql_dbg(ql_dbg_init, vha, 0x007c,
2271 "Reset register cleared by chip reset.\n");
1da177e4
LT		 2272
2273 /* Reset RISC processor. */
2274 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
2275 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
2276
2277 /* Workaround for QLA2312 PCI parity error */
2278 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
2279 data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0));
2280 for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) {
2281 udelay(5);
2282 data = RD_MAILBOX_REG(ha, reg, 0);
fa2a1ce5 2283 barrier();
1da177e4
LT		 2284 }
2285 } else
2286 udelay(10);
2287
2288 if (!cnt)
2289 goto chip_diag_failed;
2290
2291 /* Check product ID of chip */
7c3df132 2292 ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product Id of chip.\n");
1da177e4
LT		 2293
2294 mb[1] = RD_MAILBOX_REG(ha, reg, 1);
2295 mb[2] = RD_MAILBOX_REG(ha, reg, 2);
2296 mb[3] = RD_MAILBOX_REG(ha, reg, 3);
2297 mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4));
2298 if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) ||
2299 mb[3] != PROD_ID_3) {
7c3df132
SK		 2300 ql_log(ql_log_warn, vha, 0x0062,
2301 "Wrong product ID = 0x%x,0x%x,0x%x.\n",
2302 mb[1], mb[2], mb[3]);
1da177e4
LT		 2303
2304 goto chip_diag_failed;
2305 }
2306 ha->product_id[0] = mb[1];
2307 ha->product_id[1] = mb[2];
2308 ha->product_id[2] = mb[3];
2309 ha->product_id[3] = mb[4];
2310
2311 /* Adjust fw RISC transfer size */
73208dfd 2312 if (req->length > 1024)
1da177e4
LT		 2313 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024;
2314 else
2315 ha->fw_transfer_size = REQUEST_ENTRY_SIZE *
73208dfd 2316 req->length;
1da177e4
LT		 2317
2318 if (IS_QLA2200(ha) &&
2319 RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) {
2320 /* Limit firmware transfer size with a 2200A */
7c3df132 2321 ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n");
1da177e4 2322
ea5b6382 2323 ha->device_type |= DT_ISP2200A;
1da177e4
LT		 2324 ha->fw_transfer_size = 128;
2325 }
2326
2327 /* Wrap Incoming Mailboxes Test. */
2328 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2329
7c3df132 2330 ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n");
e315cd28 2331 rval = qla2x00_mbx_reg_test(vha);
7c3df132
SK		 2332 if (rval)
2333 ql_log(ql_log_warn, vha, 0x0080,
2334 "Failed mailbox send register test.\n");
2335 else
1da177e4
LT		 2336 /* Flag a successful rval */
2337 rval = QLA_SUCCESS;
1da177e4
LT		 2338 spin_lock_irqsave(&ha->hardware_lock, flags);
2339
2340chip_diag_failed:
2341 if (rval)
7c3df132
SK		 2342 ql_log(ql_log_info, vha, 0x0081,
2343 "Chip diagnostics **** FAILED ****.\n");
1da177e4
LT		 2344
2345 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2346
2347 return (rval);
2348}
2349
0107109e
AV		 2350/**
2351 * qla24xx_chip_diag() - Test ISP24xx for proper operation.
2352 * @ha: HA context
2353 *
2354 * Returns 0 on success.
2355 */
2356int
e315cd28 2357qla24xx_chip_diag(scsi_qla_host_t *vha)
0107109e
AV		 2358{
2359 int rval;
e315cd28 2360 struct qla_hw_data *ha = vha->hw;
73208dfd 2361 struct req_que *req = ha->req_q_map[0];
0107109e 2362
7ec0effd 2363 if (IS_P3P_TYPE(ha))
a9083016
GM		 2364 return QLA_SUCCESS;
2365
73208dfd 2366 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
0107109e 2367
e315cd28 2368 rval = qla2x00_mbx_reg_test(vha);
0107109e 2369 if (rval) {
7c3df132
SK		 2370 ql_log(ql_log_warn, vha, 0x0082,
2371 "Failed mailbox send register test.\n");
0107109e
AV		 2372 } else {
2373 /* Flag a successful rval */
2374 rval = QLA_SUCCESS;
2375 }
2376
2377 return rval;
2378}
2379
a7a167bf 2380void
e315cd28 2381qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
0107109e 2382{
a7a167bf
AV		 2383 int rval;
2384 uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
73208dfd 2385 eft_size, fce_size, mq_size;
df613b96
AV		 2386 dma_addr_t tc_dma;
2387 void *tc;
e315cd28 2388 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 2389 struct req_que *req = ha->req_q_map[0];
2390 struct rsp_que *rsp = ha->rsp_q_map[0];
a7a167bf
AV		 2391
2392 if (ha->fw_dump) {
7c3df132
SK		 2393 ql_dbg(ql_dbg_init, vha, 0x00bd,
2394 "Firmware dump already allocated.\n");
a7a167bf
AV		 2395 return;
2396 }
d4e3e04d 2397
0107109e 2398 ha->fw_dumped = 0;
61f098dd 2399 ha->fw_dump_cap_flags = 0;
f73cb695
CD		 2400 dump_size = fixed_size = mem_size = eft_size = fce_size = mq_size = 0;
2401 req_q_size = rsp_q_size = 0;
2402
2403 if (IS_QLA27XX(ha))
2404 goto try_fce;
2405
d4e3e04d 2406 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
a7a167bf 2407 fixed_size = sizeof(struct qla2100_fw_dump);
d4e3e04d 2408 } else if (IS_QLA23XX(ha)) {
a7a167bf
AV		 2409 fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
2410 mem_size = (ha->fw_memory_size - 0x11000 + 1) *
2411 sizeof(uint16_t);
e428924c 2412 } else if (IS_FWI2_CAPABLE(ha)) {
b20f02e1 2413 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
6246b8a1
GM		 2414 fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem);
2415 else if (IS_QLA81XX(ha))
3a03eb79
AV		 2416 fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
2417 else if (IS_QLA25XX(ha))
2418 fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
2419 else
2420 fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
f73cb695 2421
a7a167bf
AV		 2422 mem_size = (ha->fw_memory_size - 0x100000 + 1) *
2423 sizeof(uint32_t);
050c9bb1 2424 if (ha->mqenable) {
b20f02e1 2425 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
6246b8a1 2426 mq_size = sizeof(struct qla2xxx_mq_chain);
050c9bb1
GM		 2427 /*
2428 * Allocate maximum buffer size for all queues.
2429 * Resizing must be done at end-of-dump processing.
2430 */
2431 mq_size += ha->max_req_queues *
2432 (req->length * sizeof(request_t));
2433 mq_size += ha->max_rsp_queues *
2434 (rsp->length * sizeof(response_t));
2435 }
00876ae8 2436 if (ha->tgt.atio_ring)
2d70c103 2437 mq_size += ha->tgt.atio_q_length * sizeof(request_t);
df613b96 2438 /* Allocate memory for Fibre Channel Event Buffer. */
f73cb695
CD		 2439 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
2440 !IS_QLA27XX(ha))
436a7b11 2441 goto try_eft;
df613b96 2442
f73cb695
CD		 2443try_fce:
2444 if (ha->fce)
2445 dma_free_coherent(&ha->pdev->dev,
2446 FCE_SIZE, ha->fce, ha->fce_dma);
2447
2448 /* Allocate memory for Fibre Channel Event Buffer. */
0ea85b50
JP		 2449 tc = dma_zalloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
2450 GFP_KERNEL);
df613b96 2451 if (!tc) {
7c3df132
SK		 2452 ql_log(ql_log_warn, vha, 0x00be,
2453 "Unable to allocate (%d KB) for FCE.\n",
2454 FCE_SIZE / 1024);
17d98630 2455 goto try_eft;
df613b96
AV		 2456 }
2457
e315cd28 2458 rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS,
df613b96
AV		 2459 ha->fce_mb, &ha->fce_bufs);
2460 if (rval) {
7c3df132
SK		 2461 ql_log(ql_log_warn, vha, 0x00bf,
2462 "Unable to initialize FCE (%d).\n", rval);
df613b96
AV		 2463 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc,
2464 tc_dma);
2465 ha->flags.fce_enabled = 0;
17d98630 2466 goto try_eft;
df613b96 2467 }
cfb0919c 2468 ql_dbg(ql_dbg_init, vha, 0x00c0,
7c3df132 2469 "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024);
df613b96 2470
7d9dade3 2471 fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE;
df613b96
AV		 2472 ha->flags.fce_enabled = 1;
2473 ha->fce_dma = tc_dma;
2474 ha->fce = tc;
f73cb695 2475
436a7b11 2476try_eft:
f73cb695
CD		 2477 if (ha->eft)
2478 dma_free_coherent(&ha->pdev->dev,
2479 EFT_SIZE, ha->eft, ha->eft_dma);
2480
436a7b11 2481 /* Allocate memory for Extended Trace Buffer. */
0ea85b50
JP		 2482 tc = dma_zalloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
2483 GFP_KERNEL);
436a7b11 2484 if (!tc) {
7c3df132
SK		 2485 ql_log(ql_log_warn, vha, 0x00c1,
2486 "Unable to allocate (%d KB) for EFT.\n",
2487 EFT_SIZE / 1024);
436a7b11
AV		 2488 goto cont_alloc;
2489 }
2490
e315cd28 2491 rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
436a7b11 2492 if (rval) {
7c3df132
SK		 2493 ql_log(ql_log_warn, vha, 0x00c2,
2494 "Unable to initialize EFT (%d).\n", rval);
436a7b11
AV		 2495 dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc,
2496 tc_dma);
2497 goto cont_alloc;
2498 }
cfb0919c 2499 ql_dbg(ql_dbg_init, vha, 0x00c3,
7c3df132 2500 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
436a7b11
AV		 2501
2502 eft_size = EFT_SIZE;
2503 ha->eft_dma = tc_dma;
2504 ha->eft = tc;
d4e3e04d 2505 }
f73cb695 2506
a7a167bf 2507cont_alloc:
f73cb695
CD		 2508 if (IS_QLA27XX(ha)) {
2509 if (!ha->fw_dump_template) {
2510 ql_log(ql_log_warn, vha, 0x00ba,
2511 "Failed missing fwdump template\n");
2512 return;
2513 }
2514 dump_size = qla27xx_fwdt_calculate_dump_size(vha);
2515 ql_dbg(ql_dbg_init, vha, 0x00fa,
2516 "-> allocating fwdump (%x bytes)...\n", dump_size);
2517 goto allocate;
2518 }
2519
73208dfd
AC		 2520 req_q_size = req->length * sizeof(request_t);
2521 rsp_q_size = rsp->length * sizeof(response_t);
a7a167bf 2522 dump_size = offsetof(struct qla2xxx_fw_dump, isp);
2afa19a9 2523 dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size;
bb99de67
AV		 2524 ha->chain_offset = dump_size;
2525 dump_size += mq_size + fce_size;
d4e3e04d 2526
f73cb695 2527allocate:
d4e3e04d 2528 ha->fw_dump = vmalloc(dump_size);
a7a167bf 2529 if (!ha->fw_dump) {
7c3df132
SK		 2530 ql_log(ql_log_warn, vha, 0x00c4,
2531 "Unable to allocate (%d KB) for firmware dump.\n",
2532 dump_size / 1024);
a7a167bf 2533
e30d1756
MI		 2534 if (ha->fce) {
2535 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
2536 ha->fce_dma);
2537 ha->fce = NULL;
2538 ha->fce_dma = 0;
2539 }
2540
a7a167bf
AV		 2541 if (ha->eft) {
2542 dma_free_coherent(&ha->pdev->dev, eft_size, ha->eft,
2543 ha->eft_dma);
2544 ha->eft = NULL;
2545 ha->eft_dma = 0;
2546 }
2547 return;
2548 }
f73cb695 2549 ha->fw_dump_len = dump_size;
cfb0919c 2550 ql_dbg(ql_dbg_init, vha, 0x00c5,
7c3df132 2551 "Allocated (%d KB) for firmware dump.\n", dump_size / 1024);
a7a167bf 2552
f73cb695
CD		 2553 if (IS_QLA27XX(ha))
2554 return;
2555
a7a167bf
AV		 2556 ha->fw_dump->signature[0] = 'Q';
2557 ha->fw_dump->signature[1] = 'L';
2558 ha->fw_dump->signature[2] = 'G';
2559 ha->fw_dump->signature[3] = 'C';
ad950360 2560 ha->fw_dump->version = htonl(1);
a7a167bf
AV		 2561
2562 ha->fw_dump->fixed_size = htonl(fixed_size);
2563 ha->fw_dump->mem_size = htonl(mem_size);
2564 ha->fw_dump->req_q_size = htonl(req_q_size);
2565 ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
2566
2567 ha->fw_dump->eft_size = htonl(eft_size);
2568 ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma));
2569 ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma));
2570
2571 ha->fw_dump->header_size =
2572 htonl(offsetof(struct qla2xxx_fw_dump, isp));
0107109e
AV		 2573}
2574
18e7555a
AV		 2575static int
2576qla81xx_mpi_sync(scsi_qla_host_t *vha)
2577{
2578#define MPS_MASK 0xe0
2579 int rval;
2580 uint16_t dc;
2581 uint32_t dw;
18e7555a
AV		 2582
2583 if (!IS_QLA81XX(vha->hw))
2584 return QLA_SUCCESS;
2585
2586 rval = qla2x00_write_ram_word(vha, 0x7c00, 1);
2587 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2588 ql_log(ql_log_warn, vha, 0x0105,
2589 "Unable to acquire semaphore.\n");
18e7555a
AV		 2590 goto done;
2591 }
2592
2593 pci_read_config_word(vha->hw->pdev, 0x54, &dc);
2594 rval = qla2x00_read_ram_word(vha, 0x7a15, &dw);
2595 if (rval != QLA_SUCCESS) {
7c3df132 2596 ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n");
18e7555a
AV		 2597 goto done_release;
2598 }
2599
2600 dc &= MPS_MASK;
2601 if (dc == (dw & MPS_MASK))
2602 goto done_release;
2603
2604 dw &= ~MPS_MASK;
2605 dw |= dc;
2606 rval = qla2x00_write_ram_word(vha, 0x7a15, dw);
2607 if (rval != QLA_SUCCESS) {
7c3df132 2608 ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n");
18e7555a
AV		 2609 }
2610
2611done_release:
2612 rval = qla2x00_write_ram_word(vha, 0x7c00, 0);
2613 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2614 ql_log(ql_log_warn, vha, 0x006d,
2615 "Unable to release semaphore.\n");
18e7555a
AV		 2616 }
2617
2618done:
2619 return rval;
2620}
2621
8d93f550
CD		 2622int
2623qla2x00_alloc_outstanding_cmds(struct qla_hw_data *ha, struct req_que *req)
2624{
2625 /* Don't try to reallocate the array */
2626 if (req->outstanding_cmds)
2627 return QLA_SUCCESS;
2628
d7459527 2629 if (!IS_FWI2_CAPABLE(ha))
8d93f550
CD		 2630 req->num_outstanding_cmds = DEFAULT_OUTSTANDING_COMMANDS;
2631 else {
03e8c680
QT		 2632 if (ha->cur_fw_xcb_count <= ha->cur_fw_iocb_count)
2633 req->num_outstanding_cmds = ha->cur_fw_xcb_count;
8d93f550 2634 else
03e8c680 2635 req->num_outstanding_cmds = ha->cur_fw_iocb_count;
8d93f550
CD		 2636 }
2637
2638 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
2639 req->num_outstanding_cmds, GFP_KERNEL);
2640
2641 if (!req->outstanding_cmds) {
2642 /*
2643 * Try to allocate a minimal size just so we can get through
2644 * initialization.
2645 */
2646 req->num_outstanding_cmds = MIN_OUTSTANDING_COMMANDS;
2647 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
2648 req->num_outstanding_cmds, GFP_KERNEL);
2649
2650 if (!req->outstanding_cmds) {
2651 ql_log(ql_log_fatal, NULL, 0x0126,
2652 "Failed to allocate memory for "
2653 "outstanding_cmds for req_que %p.\n", req);
2654 req->num_outstanding_cmds = 0;
2655 return QLA_FUNCTION_FAILED;
2656 }
2657 }
2658
2659 return QLA_SUCCESS;
2660}
2661
1da177e4
LT		 2662/**
2663 * qla2x00_setup_chip() - Load and start RISC firmware.
2664 * @ha: HA context
2665 *
2666 * Returns 0 on success.
2667 */
2668static int
e315cd28 2669qla2x00_setup_chip(scsi_qla_host_t *vha)
1da177e4 2670{
0107109e
AV		 2671 int rval;
2672 uint32_t srisc_address = 0;
e315cd28 2673 struct qla_hw_data *ha = vha->hw;
3db0652e
AV		 2674 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2675 unsigned long flags;
dda772e8 2676 uint16_t fw_major_version;
3db0652e 2677
7ec0effd 2678 if (IS_P3P_TYPE(ha)) {
a9083016 2679 rval = ha->isp_ops->load_risc(vha, &srisc_address);
14e303d9
AV		 2680 if (rval == QLA_SUCCESS) {
2681 qla2x00_stop_firmware(vha);
a9083016 2682 goto enable_82xx_npiv;
14e303d9 2683 } else
b963752f 2684 goto failed;
a9083016
GM		 2685 }
2686
3db0652e
AV		 2687 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
2688 /* Disable SRAM, Instruction RAM and GP RAM parity. */
2689 spin_lock_irqsave(&ha->hardware_lock, flags);
2690 WRT_REG_WORD(&reg->hccr, (HCCR_ENABLE_PARITY + 0x0));
2691 RD_REG_WORD(&reg->hccr);
2692 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2693 }
1da177e4 2694
18e7555a
AV		 2695 qla81xx_mpi_sync(vha);
2696
1da177e4 2697 /* Load firmware sequences */
e315cd28 2698 rval = ha->isp_ops->load_risc(vha, &srisc_address);
0107109e 2699 if (rval == QLA_SUCCESS) {
7c3df132
SK		 2700 ql_dbg(ql_dbg_init, vha, 0x00c9,
2701 "Verifying Checksum of loaded RISC code.\n");
1da177e4 2702
e315cd28 2703 rval = qla2x00_verify_checksum(vha, srisc_address);
1da177e4
LT		 2704 if (rval == QLA_SUCCESS) {
2705 /* Start firmware execution. */
7c3df132
SK		 2706 ql_dbg(ql_dbg_init, vha, 0x00ca,
2707 "Starting firmware.\n");
1da177e4 2708
b0d6cabd
HM		 2709 if (ql2xexlogins)
2710 ha->flags.exlogins_enabled = 1;
2711
2f56a7f1
HM		 2712 if (ql2xexchoffld)
2713 ha->flags.exchoffld_enabled = 1;
2714
e315cd28 2715 rval = qla2x00_execute_fw(vha, srisc_address);
1da177e4 2716 /* Retrieve firmware information. */
dda772e8 2717 if (rval == QLA_SUCCESS) {
b0d6cabd
HM		 2718 rval = qla2x00_set_exlogins_buffer(vha);
2719 if (rval != QLA_SUCCESS)
2720 goto failed;
2721
2f56a7f1
HM		 2722 rval = qla2x00_set_exchoffld_buffer(vha);
2723 if (rval != QLA_SUCCESS)
2724 goto failed;
2725
a9083016 2726enable_82xx_npiv:
dda772e8 2727 fw_major_version = ha->fw_major_version;
7ec0effd 2728 if (IS_P3P_TYPE(ha))
3173167f 2729 qla82xx_check_md_needed(vha);
6246b8a1
GM		 2730 else
2731 rval = qla2x00_get_fw_version(vha);
ca9e9c3e
AV		 2732 if (rval != QLA_SUCCESS)
2733 goto failed;
2c3dfe3f 2734 ha->flags.npiv_supported = 0;
e315cd28 2735 if (IS_QLA2XXX_MIDTYPE(ha) &&
946fb891 2736 (ha->fw_attributes & BIT_2)) {
2c3dfe3f 2737 ha->flags.npiv_supported = 1;
4d0ea247
SJ		 2738 if ((!ha->max_npiv_vports) ||
2739 ((ha->max_npiv_vports + 1) %
eb66dc60 2740 MIN_MULTI_ID_FABRIC))
4d0ea247 2741 ha->max_npiv_vports =
eb66dc60 2742 MIN_MULTI_ID_FABRIC - 1;
4d0ea247 2743 }
03e8c680 2744 qla2x00_get_resource_cnts(vha);
d743de66 2745
8d93f550
CD		 2746 /*
2747 * Allocate the array of outstanding commands
2748 * now that we know the firmware resources.
2749 */
2750 rval = qla2x00_alloc_outstanding_cmds(ha,
2751 vha->req);
2752 if (rval != QLA_SUCCESS)
2753 goto failed;
2754
be5ea3cf 2755 if (!fw_major_version && ql2xallocfwdump
7ec0effd 2756 && !(IS_P3P_TYPE(ha)))
08de2844 2757 qla2x00_alloc_fw_dump(vha);
3b6e5b9d
CD		 2758 } else {
2759 goto failed;
1da177e4
LT		 2760 }
2761 } else {
7c3df132
SK		 2762 ql_log(ql_log_fatal, vha, 0x00cd,
2763 "ISP Firmware failed checksum.\n");
2764 goto failed;
1da177e4 2765 }
c74d88a4
AV		 2766 } else
2767 goto failed;
1da177e4 2768
3db0652e
AV		 2769 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
2770 /* Enable proper parity. */
2771 spin_lock_irqsave(&ha->hardware_lock, flags);
2772 if (IS_QLA2300(ha))
2773 /* SRAM parity */
2774 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x1);
2775 else
2776 /* SRAM, Instruction RAM and GP RAM parity */
2777 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x7);
2778 RD_REG_WORD(&reg->hccr);
2779 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2780 }
2781
f3982d89
CD		 2782 if (IS_QLA27XX(ha))
2783 ha->flags.fac_supported = 1;
2784 else if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
1d2874de
JC		 2785 uint32_t size;
2786
2787 rval = qla81xx_fac_get_sector_size(vha, &size);
2788 if (rval == QLA_SUCCESS) {
2789 ha->flags.fac_supported = 1;
2790 ha->fdt_block_size = size << 2;
2791 } else {
7c3df132 2792 ql_log(ql_log_warn, vha, 0x00ce,
1d2874de
JC		 2793 "Unsupported FAC firmware (%d.%02d.%02d).\n",
2794 ha->fw_major_version, ha->fw_minor_version,
2795 ha->fw_subminor_version);
1ca60e3b 2796
f73cb695 2797 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
6246b8a1
GM		 2798 ha->flags.fac_supported = 0;
2799 rval = QLA_SUCCESS;
2800 }
1d2874de
JC		 2801 }
2802 }
ca9e9c3e 2803failed:
1da177e4 2804 if (rval) {
7c3df132
SK		 2805 ql_log(ql_log_fatal, vha, 0x00cf,
2806 "Setup chip ****FAILED****.\n");
1da177e4
LT		 2807 }
2808
2809 return (rval);
2810}
2811
2812/**
2813 * qla2x00_init_response_q_entries() - Initializes response queue entries.
2814 * @ha: HA context
2815 *
2816 * Beginning of request ring has initialization control block already built
2817 * by nvram config routine.
2818 *
2819 * Returns 0 on success.
2820 */
73208dfd
AC		 2821void
2822qla2x00_init_response_q_entries(struct rsp_que *rsp)
1da177e4
LT		 2823{
2824 uint16_t cnt;
2825 response_t *pkt;
2826
2afa19a9
AC		 2827 rsp->ring_ptr = rsp->ring;
2828 rsp->ring_index = 0;
2829 rsp->status_srb = NULL;
e315cd28
AC		 2830 pkt = rsp->ring_ptr;
2831 for (cnt = 0; cnt < rsp->length; cnt++) {
1da177e4
LT		 2832 pkt->signature = RESPONSE_PROCESSED;
2833 pkt++;
2834 }
1da177e4
LT		 2835}
2836
2837/**
2838 * qla2x00_update_fw_options() - Read and process firmware options.
2839 * @ha: HA context
2840 *
2841 * Returns 0 on success.
2842 */
abbd8870 2843void
e315cd28 2844qla2x00_update_fw_options(scsi_qla_host_t *vha)
1da177e4
LT		 2845{
2846 uint16_t swing, emphasis, tx_sens, rx_sens;
e315cd28 2847 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2848
2849 memset(ha->fw_options, 0, sizeof(ha->fw_options));
e315cd28 2850 qla2x00_get_fw_options(vha, ha->fw_options);
1da177e4
LT		 2851
2852 if (IS_QLA2100(ha) || IS_QLA2200(ha))
2853 return;
2854
2855 /* Serial Link options. */
7c3df132
SK		 2856 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
2857 "Serial link options.\n");
2858 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
2859 (uint8_t *)&ha->fw_seriallink_options,
2860 sizeof(ha->fw_seriallink_options));
1da177e4
LT		 2861
2862 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
2863 if (ha->fw_seriallink_options[3] & BIT_2) {
2864 ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING;
2865
2866 /* 1G settings */
2867 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
2868 emphasis = (ha->fw_seriallink_options[2] &
2869 (BIT_4 | BIT_3)) >> 3;
2870 tx_sens = ha->fw_seriallink_options[0] &
fa2a1ce5 2871 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 2872 rx_sens = (ha->fw_seriallink_options[0] &
2873 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
2874 ha->fw_options[10] = (emphasis << 14) | (swing << 8);
2875 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
2876 if (rx_sens == 0x0)
2877 rx_sens = 0x3;
2878 ha->fw_options[10] |= (tx_sens << 4) | rx_sens;
2879 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
2880 ha->fw_options[10] |= BIT_5 |
2881 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
2882 (tx_sens & (BIT_1 | BIT_0));
2883
2884 /* 2G settings */
2885 swing = (ha->fw_seriallink_options[2] &
2886 (BIT_7 | BIT_6 | BIT_5)) >> 5;
2887 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
2888 tx_sens = ha->fw_seriallink_options[1] &
fa2a1ce5 2889 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 2890 rx_sens = (ha->fw_seriallink_options[1] &
2891 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
2892 ha->fw_options[11] = (emphasis << 14) | (swing << 8);
2893 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
2894 if (rx_sens == 0x0)
2895 rx_sens = 0x3;
2896 ha->fw_options[11] |= (tx_sens << 4) | rx_sens;
2897 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
2898 ha->fw_options[11] |= BIT_5 |
2899 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
2900 (tx_sens & (BIT_1 | BIT_0));
2901 }
2902
2903 /* FCP2 options. */
2904 /* Return command IOCBs without waiting for an ABTS to complete. */
2905 ha->fw_options[3] |= BIT_13;
2906
2907 /* LED scheme. */
2908 if (ha->flags.enable_led_scheme)
2909 ha->fw_options[2] |= BIT_12;
2910
48c02fde
AV		 2911 /* Detect ISP6312. */
2912 if (IS_QLA6312(ha))
2913 ha->fw_options[2] |= BIT_13;
2914
088d09d4
GM		 2915 /* Set Retry FLOGI in case of P2P connection */
2916 if (ha->operating_mode == P2P) {
2917 ha->fw_options[2] |= BIT_3;
2918 ql_dbg(ql_dbg_disc, vha, 0x2100,
2919 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
2920 __func__, ha->fw_options[2]);
2921 }
2922
1da177e4 2923 /* Update firmware options. */
e315cd28 2924 qla2x00_set_fw_options(vha, ha->fw_options);
1da177e4
LT		 2925}
2926
0107109e 2927void
e315cd28 2928qla24xx_update_fw_options(scsi_qla_host_t *vha)
0107109e
AV		 2929{
2930 int rval;
e315cd28 2931 struct qla_hw_data *ha = vha->hw;
0107109e 2932
7ec0effd 2933 if (IS_P3P_TYPE(ha))
a9083016
GM		 2934 return;
2935
f198cafa
HM		 2936 /* Hold status IOCBs until ABTS response received. */
2937 if (ql2xfwholdabts)
2938 ha->fw_options[3] |= BIT_12;
2939
088d09d4
GM		 2940 /* Set Retry FLOGI in case of P2P connection */
2941 if (ha->operating_mode == P2P) {
2942 ha->fw_options[2] |= BIT_3;
2943 ql_dbg(ql_dbg_disc, vha, 0x2101,
2944 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
2945 __func__, ha->fw_options[2]);
2946 }
2947
41dc529a
QT		 2948 /* Move PUREX, ABTS RX & RIDA to ATIOQ */
2949 if (ql2xmvasynctoatio) {
2950 if (qla_tgt_mode_enabled(vha) ||
2951 qla_dual_mode_enabled(vha))
2952 ha->fw_options[2] |= BIT_11;
2953 else
2954 ha->fw_options[2] &= ~BIT_11;
2955 }
2956
2957 ql_dbg(ql_dbg_init, vha, 0xffff,
2958 "%s, add FW options 1-3 = 0x%04x 0x%04x 0x%04x mode %x\n",
2959 __func__, ha->fw_options[1], ha->fw_options[2],
2960 ha->fw_options[3], vha->host->active_mode);
2961 qla2x00_set_fw_options(vha, ha->fw_options);
2962
0107109e 2963 /* Update Serial Link options. */
f94097ed 2964 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0)
0107109e
AV		 2965 return;
2966
e315cd28 2967 rval = qla2x00_set_serdes_params(vha,
f94097ed
AV		 2968 le16_to_cpu(ha->fw_seriallink_options24[1]),
2969 le16_to_cpu(ha->fw_seriallink_options24[2]),
2970 le16_to_cpu(ha->fw_seriallink_options24[3]));
0107109e 2971 if (rval != QLA_SUCCESS) {
7c3df132 2972 ql_log(ql_log_warn, vha, 0x0104,
0107109e
AV		 2973 "Unable to update Serial Link options (%x).\n", rval);
2974 }
2975}
2976
abbd8870 2977void
e315cd28 2978qla2x00_config_rings(struct scsi_qla_host *vha)
abbd8870 2979{
e315cd28 2980 struct qla_hw_data *ha = vha->hw;
3d71644c 2981 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
73208dfd
AC		 2982 struct req_que *req = ha->req_q_map[0];
2983 struct rsp_que *rsp = ha->rsp_q_map[0];
abbd8870
AV		 2984
2985 /* Setup ring parameters in initialization control block. */
ad950360
BVA		 2986 ha->init_cb->request_q_outpointer = cpu_to_le16(0);
2987 ha->init_cb->response_q_inpointer = cpu_to_le16(0);
e315cd28
AC		 2988 ha->init_cb->request_q_length = cpu_to_le16(req->length);
2989 ha->init_cb->response_q_length = cpu_to_le16(rsp->length);
2990 ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
2991 ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
2992 ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
2993 ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
abbd8870
AV		 2994
2995 WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0);
2996 WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0);
2997 WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0);
2998 WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0);
2999 RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */
3000}
3001
0107109e 3002void
e315cd28 3003qla24xx_config_rings(struct scsi_qla_host *vha)
0107109e 3004{
e315cd28 3005 struct qla_hw_data *ha = vha->hw;
118e2ef9 3006 device_reg_t *reg = ISP_QUE_REG(ha, 0);
73208dfd
AC		 3007 struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
3008 struct qla_msix_entry *msix;
0107109e 3009 struct init_cb_24xx *icb;
73208dfd
AC		 3010 uint16_t rid = 0;
3011 struct req_que *req = ha->req_q_map[0];
3012 struct rsp_que *rsp = ha->rsp_q_map[0];
0107109e 3013
6246b8a1 3014 /* Setup ring parameters in initialization control block. */
0107109e 3015 icb = (struct init_cb_24xx *)ha->init_cb;
ad950360
BVA		 3016 icb->request_q_outpointer = cpu_to_le16(0);
3017 icb->response_q_inpointer = cpu_to_le16(0);
e315cd28
AC		 3018 icb->request_q_length = cpu_to_le16(req->length);
3019 icb->response_q_length = cpu_to_le16(rsp->length);
3020 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
3021 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
3022 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
3023 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
0107109e 3024
2d70c103 3025 /* Setup ATIO queue dma pointers for target mode */
ad950360 3026 icb->atio_q_inpointer = cpu_to_le16(0);
2d70c103
NB		 3027 icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length);
3028 icb->atio_q_address[0] = cpu_to_le32(LSD(ha->tgt.atio_dma));
3029 icb->atio_q_address[1] = cpu_to_le32(MSD(ha->tgt.atio_dma));
3030
7c6300e3 3031 if (IS_SHADOW_REG_CAPABLE(ha))
ad950360 3032 icb->firmware_options_2 |= cpu_to_le32(BIT_30|BIT_29);
7c6300e3 3033
f73cb695 3034 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
ad950360
BVA		 3035 icb->qos = cpu_to_le16(QLA_DEFAULT_QUE_QOS);
3036 icb->rid = cpu_to_le16(rid);
73208dfd
AC		 3037 if (ha->flags.msix_enabled) {
3038 msix = &ha->msix_entries[1];
7c3df132
SK		 3039 ql_dbg(ql_dbg_init, vha, 0x00fd,
3040 "Registering vector 0x%x for base que.\n",
3041 msix->entry);
73208dfd
AC		 3042 icb->msix = cpu_to_le16(msix->entry);
3043 }
3044 /* Use alternate PCI bus number */
3045 if (MSB(rid))
ad950360 3046 icb->firmware_options_2 |= cpu_to_le32(BIT_19);
73208dfd
AC		 3047 /* Use alternate PCI devfn */
3048 if (LSB(rid))
ad950360 3049 icb->firmware_options_2 |= cpu_to_le32(BIT_18);
73208dfd 3050
3155754a 3051 /* Use Disable MSIX Handshake mode for capable adapters */
6246b8a1
GM		 3052 if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) &&
3053 (ha->flags.msix_enabled)) {
ad950360 3054 icb->firmware_options_2 &= cpu_to_le32(~BIT_22);
3155754a 3055 ha->flags.disable_msix_handshake = 1;
7c3df132
SK		 3056 ql_dbg(ql_dbg_init, vha, 0x00fe,
3057 "MSIX Handshake Disable Mode turned on.\n");
3155754a 3058 } else {
ad950360 3059 icb->firmware_options_2 |= cpu_to_le32(BIT_22);
3155754a 3060 }
ad950360 3061 icb->firmware_options_2 |= cpu_to_le32(BIT_23);
73208dfd
AC		 3062
3063 WRT_REG_DWORD(&reg->isp25mq.req_q_in, 0);
3064 WRT_REG_DWORD(&reg->isp25mq.req_q_out, 0);
3065 WRT_REG_DWORD(&reg->isp25mq.rsp_q_in, 0);
3066 WRT_REG_DWORD(&reg->isp25mq.rsp_q_out, 0);
3067 } else {
3068 WRT_REG_DWORD(&reg->isp24.req_q_in, 0);
3069 WRT_REG_DWORD(&reg->isp24.req_q_out, 0);
3070 WRT_REG_DWORD(&reg->isp24.rsp_q_in, 0);
3071 WRT_REG_DWORD(&reg->isp24.rsp_q_out, 0);
3072 }
aa230bc5 3073 qlt_24xx_config_rings(vha);
2d70c103 3074
73208dfd
AC		 3075 /* PCI posting */
3076 RD_REG_DWORD(&ioreg->hccr);
0107109e
AV		 3077}
3078
1da177e4
LT		 3079/**
3080 * qla2x00_init_rings() - Initializes firmware.
3081 * @ha: HA context
3082 *
3083 * Beginning of request ring has initialization control block already built
3084 * by nvram config routine.
3085 *
3086 * Returns 0 on success.
3087 */
8ae6d9c7 3088int
e315cd28 3089qla2x00_init_rings(scsi_qla_host_t *vha)
1da177e4
LT		 3090{
3091 int rval;
3092 unsigned long flags = 0;
29bdccbe 3093 int cnt, que;
e315cd28 3094 struct qla_hw_data *ha = vha->hw;
29bdccbe
AC		 3095 struct req_que *req;
3096 struct rsp_que *rsp;
2c3dfe3f
SJ		 3097 struct mid_init_cb_24xx *mid_init_cb =
3098 (struct mid_init_cb_24xx *) ha->init_cb;
1da177e4
LT		 3099
3100 spin_lock_irqsave(&ha->hardware_lock, flags);
3101
3102 /* Clear outstanding commands array. */
2afa19a9 3103 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 3104 req = ha->req_q_map[que];
cb43285f 3105 if (!req || !test_bit(que, ha->req_qid_map))
29bdccbe 3106 continue;
7c6300e3
JC		 3107 req->out_ptr = (void *)(req->ring + req->length);
3108 *req->out_ptr = 0;
8d93f550 3109 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++)
29bdccbe 3110 req->outstanding_cmds[cnt] = NULL;
1da177e4 3111
2afa19a9 3112 req->current_outstanding_cmd = 1;
1da177e4 3113
29bdccbe
AC		 3114 /* Initialize firmware. */
3115 req->ring_ptr = req->ring;
3116 req->ring_index = 0;
3117 req->cnt = req->length;
3118 }
1da177e4 3119
2afa19a9 3120 for (que = 0; que < ha->max_rsp_queues; que++) {
29bdccbe 3121 rsp = ha->rsp_q_map[que];
cb43285f 3122 if (!rsp || !test_bit(que, ha->rsp_qid_map))
29bdccbe 3123 continue;
7c6300e3
JC		 3124 rsp->in_ptr = (void *)(rsp->ring + rsp->length);
3125 *rsp->in_ptr = 0;
29bdccbe 3126 /* Initialize response queue entries */
8ae6d9c7
GM		 3127 if (IS_QLAFX00(ha))
3128 qlafx00_init_response_q_entries(rsp);
3129 else
3130 qla2x00_init_response_q_entries(rsp);
29bdccbe 3131 }
1da177e4 3132
2d70c103
NB		 3133 ha->tgt.atio_ring_ptr = ha->tgt.atio_ring;
3134 ha->tgt.atio_ring_index = 0;
3135 /* Initialize ATIO queue entries */
3136 qlt_init_atio_q_entries(vha);
3137
e315cd28 3138 ha->isp_ops->config_rings(vha);
1da177e4
LT		 3139
3140 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3141
8ae6d9c7
GM		 3142 ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n");
3143
3144 if (IS_QLAFX00(ha)) {
3145 rval = qlafx00_init_firmware(vha, ha->init_cb_size);
3146 goto next_check;
3147 }
3148
1da177e4 3149 /* Update any ISP specific firmware options before initialization. */
e315cd28 3150 ha->isp_ops->update_fw_options(vha);
1da177e4 3151
605aa2bc 3152 if (ha->flags.npiv_supported) {
45980cc2 3153 if (ha->operating_mode == LOOP && !IS_CNA_CAPABLE(ha))
605aa2bc 3154 ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
c48339de 3155 mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
605aa2bc
LC		 3156 }
3157
24a08138 3158 if (IS_FWI2_CAPABLE(ha)) {
ad950360 3159 mid_init_cb->options = cpu_to_le16(BIT_1);
24a08138 3160 mid_init_cb->init_cb.execution_throttle =
03e8c680 3161 cpu_to_le16(ha->cur_fw_xcb_count);
40f3862b
JC		 3162 ha->flags.dport_enabled =
3163 (mid_init_cb->init_cb.firmware_options_1 & BIT_7) != 0;
3164 ql_dbg(ql_dbg_init, vha, 0x0191, "DPORT Support: %s.\n",
3165 (ha->flags.dport_enabled) ? "enabled" : "disabled");
3166 /* FA-WWPN Status */
2486c627 3167 ha->flags.fawwpn_enabled =
40f3862b 3168 (mid_init_cb->init_cb.firmware_options_1 & BIT_6) != 0;
2486c627
HM		 3169 ql_dbg(ql_dbg_init, vha, 0x0141, "FA-WWPN Support: %s.\n",
3170 (ha->flags.fawwpn_enabled) ? "enabled" : "disabled");
24a08138 3171 }
2c3dfe3f 3172
e315cd28 3173 rval = qla2x00_init_firmware(vha, ha->init_cb_size);
8ae6d9c7 3174next_check:
1da177e4 3175 if (rval) {
7c3df132
SK		 3176 ql_log(ql_log_fatal, vha, 0x00d2,
3177 "Init Firmware **** FAILED ****.\n");
1da177e4 3178 } else {
7c3df132
SK		 3179 ql_dbg(ql_dbg_init, vha, 0x00d3,
3180 "Init Firmware -- success.\n");
1da177e4
LT		 3181 }
3182
3183 return (rval);
3184}
3185
3186/**
3187 * qla2x00_fw_ready() - Waits for firmware ready.
3188 * @ha: HA context
3189 *
3190 * Returns 0 on success.
3191 */
3192static int
e315cd28 3193qla2x00_fw_ready(scsi_qla_host_t *vha)
1da177e4
LT		 3194{
3195 int rval;
4d4df193 3196 unsigned long wtime, mtime, cs84xx_time;
1da177e4
LT		 3197 uint16_t min_wait; /* Minimum wait time if loop is down */
3198 uint16_t wait_time; /* Wait time if loop is coming ready */
b5a340dd 3199 uint16_t state[6];
e315cd28 3200 struct qla_hw_data *ha = vha->hw;
1da177e4 3201
8ae6d9c7
GM		 3202 if (IS_QLAFX00(vha->hw))
3203 return qlafx00_fw_ready(vha);
3204
1da177e4
LT		 3205 rval = QLA_SUCCESS;
3206
33461491
CD		 3207 /* Time to wait for loop down */
3208 if (IS_P3P_TYPE(ha))
3209 min_wait = 30;
3210 else
3211 min_wait = 20;
1da177e4
LT		 3212
3213 /*
3214 * Firmware should take at most one RATOV to login, plus 5 seconds for
3215 * our own processing.
3216 */
3217 if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) {
3218 wait_time = min_wait;
3219 }
3220
3221 /* Min wait time if loop down */
3222 mtime = jiffies + (min_wait * HZ);
3223
3224 /* wait time before firmware ready */
3225 wtime = jiffies + (wait_time * HZ);
3226
3227 /* Wait for ISP to finish LIP */
e315cd28 3228 if (!vha->flags.init_done)
7c3df132
SK		 3229 ql_log(ql_log_info, vha, 0x801e,
3230 "Waiting for LIP to complete.\n");
1da177e4
LT		 3231
3232 do {
5b939038 3233 memset(state, -1, sizeof(state));
e315cd28 3234 rval = qla2x00_get_firmware_state(vha, state);
1da177e4 3235 if (rval == QLA_SUCCESS) {
4d4df193 3236 if (state[0] < FSTATE_LOSS_OF_SYNC) {
e315cd28 3237 vha->device_flags &= ~DFLG_NO_CABLE;
1da177e4 3238 }
4d4df193 3239 if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) {
7c3df132
SK		 3240 ql_dbg(ql_dbg_taskm, vha, 0x801f,
3241 "fw_state=%x 84xx=%x.\n", state[0],
3242 state[2]);
4d4df193
HK		 3243 if ((state[2] & FSTATE_LOGGED_IN) &&
3244 (state[2] & FSTATE_WAITING_FOR_VERIFY)) {
7c3df132
SK		 3245 ql_dbg(ql_dbg_taskm, vha, 0x8028,
3246 "Sending verify iocb.\n");
4d4df193
HK		 3247
3248 cs84xx_time = jiffies;
e315cd28 3249 rval = qla84xx_init_chip(vha);
7c3df132
SK		 3250 if (rval != QLA_SUCCESS) {
3251 ql_log(ql_log_warn,
cfb0919c 3252 vha, 0x8007,
7c3df132 3253 "Init chip failed.\n");
4d4df193 3254 break;
7c3df132 3255 }
4d4df193
HK		 3256
3257 /* Add time taken to initialize. */
3258 cs84xx_time = jiffies - cs84xx_time;
3259 wtime += cs84xx_time;
3260 mtime += cs84xx_time;
cfb0919c 3261 ql_dbg(ql_dbg_taskm, vha, 0x8008,
7c3df132
SK		 3262 "Increasing wait time by %ld. "
3263 "New time %ld.\n", cs84xx_time,
3264 wtime);
4d4df193
HK		 3265 }
3266 } else if (state[0] == FSTATE_READY) {
7c3df132
SK		 3267 ql_dbg(ql_dbg_taskm, vha, 0x8037,
3268 "F/W Ready - OK.\n");
1da177e4 3269
e315cd28 3270 qla2x00_get_retry_cnt(vha, &ha->retry_count,
1da177e4
LT		 3271 &ha->login_timeout, &ha->r_a_tov);
3272
3273 rval = QLA_SUCCESS;
3274 break;
3275 }
3276
3277 rval = QLA_FUNCTION_FAILED;
3278
e315cd28 3279 if (atomic_read(&vha->loop_down_timer) &&
4d4df193 3280 state[0] != FSTATE_READY) {
1da177e4 3281 /* Loop down. Timeout on min_wait for states
fa2a1ce5
AV		 3282 * other than Wait for Login.
3283 */
1da177e4 3284 if (time_after_eq(jiffies, mtime)) {
7c3df132 3285 ql_log(ql_log_info, vha, 0x8038,
1da177e4
LT		 3286 "Cable is unplugged...\n");
3287
e315cd28 3288 vha->device_flags |= DFLG_NO_CABLE;
1da177e4
LT		 3289 break;
3290 }
3291 }
3292 } else {
3293 /* Mailbox cmd failed. Timeout on min_wait. */
cdbb0a4f 3294 if (time_after_eq(jiffies, mtime) ||
7190575f 3295 ha->flags.isp82xx_fw_hung)
1da177e4
LT		 3296 break;
3297 }
3298
3299 if (time_after_eq(jiffies, wtime))
3300 break;
3301
3302 /* Delay for a while */
3303 msleep(500);
1da177e4
LT		 3304 } while (1);
3305
7c3df132 3306 ql_dbg(ql_dbg_taskm, vha, 0x803a,
b5a340dd
JC		 3307 "fw_state=%x (%x, %x, %x, %x %x) curr time=%lx.\n", state[0],
3308 state[1], state[2], state[3], state[4], state[5], jiffies);
1da177e4 3309
cfb0919c 3310 if (rval && !(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132
SK		 3311 ql_log(ql_log_warn, vha, 0x803b,
3312 "Firmware ready **** FAILED ****.\n");
1da177e4
LT		 3313 }
3314
3315 return (rval);
3316}
3317
3318/*
3319* qla2x00_configure_hba
3320* Setup adapter context.
3321*
3322* Input:
3323* ha = adapter state pointer.
3324*
3325* Returns:
3326* 0 = success
3327*
3328* Context:
3329* Kernel context.
3330*/
3331static int
e315cd28 3332qla2x00_configure_hba(scsi_qla_host_t *vha)
1da177e4
LT		 3333{
3334 int rval;
3335 uint16_t loop_id;
3336 uint16_t topo;
2c3dfe3f 3337 uint16_t sw_cap;
1da177e4
LT		 3338 uint8_t al_pa;
3339 uint8_t area;
3340 uint8_t domain;
3341 char connect_type[22];
e315cd28 3342 struct qla_hw_data *ha = vha->hw;
f24b5cb8 3343 unsigned long flags;
61e1b269 3344 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 3345
3346 /* Get host addresses. */
e315cd28 3347 rval = qla2x00_get_adapter_id(vha,
2c3dfe3f 3348 &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
1da177e4 3349 if (rval != QLA_SUCCESS) {
e315cd28 3350 if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
6246b8a1 3351 IS_CNA_CAPABLE(ha) ||
33135aa2 3352 (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
7c3df132
SK		 3353 ql_dbg(ql_dbg_disc, vha, 0x2008,
3354 "Loop is in a transition state.\n");
33135aa2 3355 } else {
7c3df132
SK		 3356 ql_log(ql_log_warn, vha, 0x2009,
3357 "Unable to get host loop ID.\n");
61e1b269
JC		 3358 if (IS_FWI2_CAPABLE(ha) && (vha == base_vha) &&
3359 (rval == QLA_COMMAND_ERROR && loop_id == 0x1b)) {
3360 ql_log(ql_log_warn, vha, 0x1151,
3361 "Doing link init.\n");
3362 if (qla24xx_link_initialize(vha) == QLA_SUCCESS)
3363 return rval;
3364 }
e315cd28 3365 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
33135aa2 3366 }
1da177e4
LT		 3367 return (rval);
3368 }
3369
3370 if (topo == 4) {
7c3df132
SK		 3371 ql_log(ql_log_info, vha, 0x200a,
3372 "Cannot get topology - retrying.\n");
1da177e4
LT		 3373 return (QLA_FUNCTION_FAILED);
3374 }
3375
e315cd28 3376 vha->loop_id = loop_id;
1da177e4
LT		 3377
3378 /* initialize */
3379 ha->min_external_loopid = SNS_FIRST_LOOP_ID;
3380 ha->operating_mode = LOOP;
2c3dfe3f 3381 ha->switch_cap = 0;
1da177e4
LT		 3382
3383 switch (topo) {
3384 case 0:
7c3df132 3385 ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n");
1da177e4
LT		 3386 ha->current_topology = ISP_CFG_NL;
3387 strcpy(connect_type, "(Loop)");
3388 break;
3389
3390 case 1:
7c3df132 3391 ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n");
2c3dfe3f 3392 ha->switch_cap = sw_cap;
1da177e4
LT		 3393 ha->current_topology = ISP_CFG_FL;
3394 strcpy(connect_type, "(FL_Port)");
3395 break;
3396
3397 case 2:
7c3df132 3398 ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n");
1da177e4
LT		 3399 ha->operating_mode = P2P;
3400 ha->current_topology = ISP_CFG_N;
3401 strcpy(connect_type, "(N_Port-to-N_Port)");
3402 break;
3403
3404 case 3:
7c3df132 3405 ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n");
2c3dfe3f 3406 ha->switch_cap = sw_cap;
1da177e4
LT		 3407 ha->operating_mode = P2P;
3408 ha->current_topology = ISP_CFG_F;
3409 strcpy(connect_type, "(F_Port)");
3410 break;
3411
3412 default:
7c3df132
SK		 3413 ql_dbg(ql_dbg_disc, vha, 0x200f,
3414 "HBA in unknown topology %x, using NL.\n", topo);
1da177e4
LT		 3415 ha->current_topology = ISP_CFG_NL;
3416 strcpy(connect_type, "(Loop)");
3417 break;
3418 }
3419
3420 /* Save Host port and loop ID. */
3421 /* byte order - Big Endian */
e315cd28
AC		 3422 vha->d_id.b.domain = domain;
3423 vha->d_id.b.area = area;
3424 vha->d_id.b.al_pa = al_pa;
1da177e4 3425
f24b5cb8 3426 spin_lock_irqsave(&ha->vport_slock, flags);
2d70c103 3427 qlt_update_vp_map(vha, SET_AL_PA);
f24b5cb8 3428 spin_unlock_irqrestore(&ha->vport_slock, flags);
2d70c103 3429
e315cd28 3430 if (!vha->flags.init_done)
7c3df132
SK		 3431 ql_log(ql_log_info, vha, 0x2010,
3432 "Topology - %s, Host Loop address 0x%x.\n",
e315cd28 3433 connect_type, vha->loop_id);
1da177e4 3434
1da177e4
LT		 3435 return(rval);
3436}
3437
a9083016 3438inline void
e315cd28
AC		 3439qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
3440 char *def)
9bb9fcf2
AV		 3441{
3442 char *st, *en;
3443 uint16_t index;
e315cd28 3444 struct qla_hw_data *ha = vha->hw;
ab671149 3445 int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
6246b8a1 3446 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha);
9bb9fcf2
AV		 3447
3448 if (memcmp(model, BINZERO, len) != 0) {
3449 strncpy(ha->model_number, model, len);
3450 st = en = ha->model_number;
3451 en += len - 1;
3452 while (en > st) {
3453 if (*en != 0x20 && *en != 0x00)
3454 break;
3455 *en-- = '\0';
3456 }
3457
3458 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 3459 if (use_tbl &&
3460 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2 3461 index < QLA_MODEL_NAMES)
1ee27146
JC		 3462 strncpy(ha->model_desc,
3463 qla2x00_model_name[index * 2 + 1],
3464 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 3465 } else {
3466 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 3467 if (use_tbl &&
3468 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2
AV		 3469 index < QLA_MODEL_NAMES) {
3470 strcpy(ha->model_number,
3471 qla2x00_model_name[index * 2]);
1ee27146
JC		 3472 strncpy(ha->model_desc,
3473 qla2x00_model_name[index * 2 + 1],
3474 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 3475 } else {
3476 strcpy(ha->model_number, def);
3477 }
3478 }
1ee27146 3479 if (IS_FWI2_CAPABLE(ha))
e315cd28 3480 qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc,
1ee27146 3481 sizeof(ha->model_desc));
9bb9fcf2
AV		 3482}
3483
4e08df3f
DM		 3484/* On sparc systems, obtain port and node WWN from firmware
3485 * properties.
3486 */
e315cd28 3487static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv)
4e08df3f
DM		 3488{
3489#ifdef CONFIG_SPARC
e315cd28 3490 struct qla_hw_data *ha = vha->hw;
4e08df3f 3491 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 3492 struct device_node *dp = pci_device_to_OF_node(pdev);
3493 const u8 *val;
4e08df3f
DM		 3494 int len;
3495
3496 val = of_get_property(dp, "port-wwn", &len);
3497 if (val && len >= WWN_SIZE)
3498 memcpy(nv->port_name, val, WWN_SIZE);
3499
3500 val = of_get_property(dp, "node-wwn", &len);
3501 if (val && len >= WWN_SIZE)
3502 memcpy(nv->node_name, val, WWN_SIZE);
3503#endif
3504}
3505
1da177e4
LT		 3506/*
3507* NVRAM configuration for ISP 2xxx
3508*
3509* Input:
3510* ha = adapter block pointer.
3511*
3512* Output:
3513* initialization control block in response_ring
3514* host adapters parameters in host adapter block
3515*
3516* Returns:
3517* 0 = success.
3518*/
abbd8870 3519int
e315cd28 3520qla2x00_nvram_config(scsi_qla_host_t *vha)
1da177e4 3521{
4e08df3f 3522 int rval;
0107109e
AV		 3523 uint8_t chksum = 0;
3524 uint16_t cnt;
3525 uint8_t *dptr1, *dptr2;
e315cd28 3526 struct qla_hw_data *ha = vha->hw;
0107109e 3527 init_cb_t *icb = ha->init_cb;
281afe19
SJ		 3528 nvram_t *nv = ha->nvram;
3529 uint8_t *ptr = ha->nvram;
3d71644c 3530 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 3531
4e08df3f
DM		 3532 rval = QLA_SUCCESS;
3533
1da177e4 3534 /* Determine NVRAM starting address. */
0107109e 3535 ha->nvram_size = sizeof(nvram_t);
1da177e4
LT		 3536 ha->nvram_base = 0;
3537 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
3538 if ((RD_REG_WORD(&reg->ctrl_status) >> 14) == 1)
3539 ha->nvram_base = 0x80;
3540
3541 /* Get NVRAM data and calculate checksum. */
e315cd28 3542 ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size);
0107109e
AV		 3543 for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++)
3544 chksum += *ptr++;
1da177e4 3545
7c3df132
SK		 3546 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
3547 "Contents of NVRAM.\n");
3548 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
3549 (uint8_t *)nv, ha->nvram_size);
1da177e4
LT		 3550
3551 /* Bad NVRAM data, set defaults parameters. */
3552 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' ||
3553 nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) {
3554 /* Reset NVRAM data. */
7c3df132 3555 ql_log(ql_log_warn, vha, 0x0064,
9e336520 3556 "Inconsistent NVRAM "
7c3df132
SK		 3557 "detected: checksum=0x%x id=%c version=0x%x.\n",
3558 chksum, nv->id[0], nv->nvram_version);
3559 ql_log(ql_log_warn, vha, 0x0065,
3560 "Falling back to "
3561 "functioning (yet invalid -- WWPN) defaults.\n");
4e08df3f
DM		 3562
3563 /*
3564 * Set default initialization control block.
3565 */
3566 memset(nv, 0, ha->nvram_size);
3567 nv->parameter_block_version = ICB_VERSION;
3568
3569 if (IS_QLA23XX(ha)) {
3570 nv->firmware_options[0] = BIT_2 | BIT_1;
3571 nv->firmware_options[1] = BIT_7 | BIT_5;
3572 nv->add_firmware_options[0] = BIT_5;
3573 nv->add_firmware_options[1] = BIT_5 | BIT_4;
98aee70d 3574 nv->frame_payload_size = 2048;
4e08df3f
DM		 3575 nv->special_options[1] = BIT_7;
3576 } else if (IS_QLA2200(ha)) {
3577 nv->firmware_options[0] = BIT_2 | BIT_1;
3578 nv->firmware_options[1] = BIT_7 | BIT_5;
3579 nv->add_firmware_options[0] = BIT_5;
3580 nv->add_firmware_options[1] = BIT_5 | BIT_4;
98aee70d 3581 nv->frame_payload_size = 1024;
4e08df3f
DM		 3582 } else if (IS_QLA2100(ha)) {
3583 nv->firmware_options[0] = BIT_3 | BIT_1;
3584 nv->firmware_options[1] = BIT_5;
98aee70d 3585 nv->frame_payload_size = 1024;
4e08df3f
DM		 3586 }
3587
ad950360
BVA		 3588 nv->max_iocb_allocation = cpu_to_le16(256);
3589 nv->execution_throttle = cpu_to_le16(16);
4e08df3f
DM		 3590 nv->retry_count = 8;
3591 nv->retry_delay = 1;
3592
3593 nv->port_name[0] = 33;
3594 nv->port_name[3] = 224;
3595 nv->port_name[4] = 139;
3596
e315cd28 3597 qla2xxx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 3598
3599 nv->login_timeout = 4;
3600
3601 /*
3602 * Set default host adapter parameters
3603 */
3604 nv->host_p[1] = BIT_2;
3605 nv->reset_delay = 5;
3606 nv->port_down_retry_count = 8;
ad950360 3607 nv->max_luns_per_target = cpu_to_le16(8);
4e08df3f
DM		 3608 nv->link_down_timeout = 60;
3609
3610 rval = 1;
1da177e4
LT		 3611 }
3612
3613#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
3614 /*
3615 * The SN2 does not provide BIOS emulation which means you can't change
3616 * potentially bogus BIOS settings. Force the use of default settings
3617 * for link rate and frame size. Hope that the rest of the settings
3618 * are valid.
3619 */
3620 if (ia64_platform_is("sn2")) {
98aee70d 3621 nv->frame_payload_size = 2048;
1da177e4
LT		 3622 if (IS_QLA23XX(ha))
3623 nv->special_options[1] = BIT_7;
3624 }
3625#endif
3626
3627 /* Reset Initialization control block */
0107109e 3628 memset(icb, 0, ha->init_cb_size);
1da177e4
LT		 3629
3630 /*
3631 * Setup driver NVRAM options.
3632 */
3633 nv->firmware_options[0] |= (BIT_6 | BIT_1);
3634 nv->firmware_options[0] &= ~(BIT_5 | BIT_4);
3635 nv->firmware_options[1] |= (BIT_5 | BIT_0);
3636 nv->firmware_options[1] &= ~BIT_4;
3637
3638 if (IS_QLA23XX(ha)) {
3639 nv->firmware_options[0] |= BIT_2;
3640 nv->firmware_options[0] &= ~BIT_3;
2d70c103 3641 nv->special_options[0] &= ~BIT_6;
0107109e 3642 nv->add_firmware_options[1] |= BIT_5 | BIT_4;
1da177e4
LT		 3643
3644 if (IS_QLA2300(ha)) {
3645 if (ha->fb_rev == FPM_2310) {
3646 strcpy(ha->model_number, "QLA2310");
3647 } else {
3648 strcpy(ha->model_number, "QLA2300");
3649 }
3650 } else {
e315cd28 3651 qla2x00_set_model_info(vha, nv->model_number,
9bb9fcf2 3652 sizeof(nv->model_number), "QLA23xx");
1da177e4
LT		 3653 }
3654 } else if (IS_QLA2200(ha)) {
3655 nv->firmware_options[0] |= BIT_2;
3656 /*
3657 * 'Point-to-point preferred, else loop' is not a safe
3658 * connection mode setting.
3659 */
3660 if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
3661 (BIT_5 | BIT_4)) {
3662 /* Force 'loop preferred, else point-to-point'. */
3663 nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
3664 nv->add_firmware_options[0] |= BIT_5;
3665 }
3666 strcpy(ha->model_number, "QLA22xx");
3667 } else /*if (IS_QLA2100(ha))*/ {
3668 strcpy(ha->model_number, "QLA2100");
3669 }
3670
3671 /*
3672 * Copy over NVRAM RISC parameter block to initialization control block.
3673 */
3674 dptr1 = (uint8_t *)icb;
3675 dptr2 = (uint8_t *)&nv->parameter_block_version;
3676 cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;
3677 while (cnt--)
3678 *dptr1++ = *dptr2++;
3679
3680 /* Copy 2nd half. */
3681 dptr1 = (uint8_t *)icb->add_firmware_options;
3682 cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;
3683 while (cnt--)
3684 *dptr1++ = *dptr2++;
3685
5341e868
AV		 3686 /* Use alternate WWN? */
3687 if (nv->host_p[1] & BIT_7) {
3688 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
3689 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
3690 }
3691
1da177e4
LT		 3692 /* Prepare nodename */
3693 if ((icb->firmware_options[1] & BIT_6) == 0) {
3694 /*
3695 * Firmware will apply the following mask if the nodename was
3696 * not provided.
3697 */
3698 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
3699 icb->node_name[0] &= 0xF0;
3700 }
3701
3702 /*
3703 * Set host adapter parameters.
3704 */
3ce8866c
SK		 3705
3706 /*
3707 * BIT_7 in the host-parameters section allows for modification to
3708 * internal driver logging.
3709 */
0181944f 3710 if (nv->host_p[0] & BIT_7)
cfb0919c 3711 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
1da177e4
LT		 3712 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
3713 /* Always load RISC code on non ISP2[12]00 chips. */
3714 if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
3715 ha->flags.disable_risc_code_load = 0;
3716 ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0);
3717 ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
3718 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
06c22bd1 3719 ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
d4c760c2 3720 ha->flags.disable_serdes = 0;
1da177e4
LT		 3721
3722 ha->operating_mode =
3723 (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
3724
3725 memcpy(ha->fw_seriallink_options, nv->seriallink_options,
3726 sizeof(ha->fw_seriallink_options));
3727
3728 /* save HBA serial number */
3729 ha->serial0 = icb->port_name[5];
3730 ha->serial1 = icb->port_name[6];
3731 ha->serial2 = icb->port_name[7];
e315cd28
AC		 3732 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
3733 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
1da177e4 3734
ad950360 3735 icb->execution_throttle = cpu_to_le16(0xFFFF);
1da177e4
LT		 3736
3737 ha->retry_count = nv->retry_count;
3738
3739 /* Set minimum login_timeout to 4 seconds. */
5b91490e 3740 if (nv->login_timeout != ql2xlogintimeout)
1da177e4
LT		 3741 nv->login_timeout = ql2xlogintimeout;
3742 if (nv->login_timeout < 4)
3743 nv->login_timeout = 4;
3744 ha->login_timeout = nv->login_timeout;
1da177e4 3745
00a537b8
AV		 3746 /* Set minimum RATOV to 100 tenths of a second. */
3747 ha->r_a_tov = 100;
1da177e4 3748
1da177e4
LT		 3749 ha->loop_reset_delay = nv->reset_delay;
3750
1da177e4
LT		 3751 /* Link Down Timeout = 0:
3752 *
3753 * When Port Down timer expires we will start returning
3754 * I/O's to OS with "DID_NO_CONNECT".
3755 *
3756 * Link Down Timeout != 0:
3757 *
3758 * The driver waits for the link to come up after link down
3759 * before returning I/Os to OS with "DID_NO_CONNECT".
fa2a1ce5 3760 */
1da177e4
LT		 3761 if (nv->link_down_timeout == 0) {
3762 ha->loop_down_abort_time =
354d6b21 3763 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
1da177e4
LT		 3764 } else {
3765 ha->link_down_timeout = nv->link_down_timeout;
3766 ha->loop_down_abort_time =
3767 (LOOP_DOWN_TIME - ha->link_down_timeout);
fa2a1ce5 3768 }
1da177e4 3769
1da177e4
LT		 3770 /*
3771 * Need enough time to try and get the port back.
3772 */
3773 ha->port_down_retry_count = nv->port_down_retry_count;
3774 if (qlport_down_retry)
3775 ha->port_down_retry_count = qlport_down_retry;
3776 /* Set login_retry_count */
3777 ha->login_retry_count = nv->retry_count;
3778 if (ha->port_down_retry_count == nv->port_down_retry_count &&
3779 ha->port_down_retry_count > 3)
3780 ha->login_retry_count = ha->port_down_retry_count;
3781 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
3782 ha->login_retry_count = ha->port_down_retry_count;
3783 if (ql2xloginretrycount)
3784 ha->login_retry_count = ql2xloginretrycount;
3785
ad950360 3786 icb->lun_enables = cpu_to_le16(0);
1da177e4
LT		 3787 icb->command_resource_count = 0;
3788 icb->immediate_notify_resource_count = 0;
ad950360 3789 icb->timeout = cpu_to_le16(0);
1da177e4
LT		 3790
3791 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
3792 /* Enable RIO */
3793 icb->firmware_options[0] &= ~BIT_3;
3794 icb->add_firmware_options[0] &=
3795 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
3796 icb->add_firmware_options[0] |= BIT_2;
3797 icb->response_accumulation_timer = 3;
3798 icb->interrupt_delay_timer = 5;
3799
e315cd28 3800 vha->flags.process_response_queue = 1;
1da177e4 3801 } else {
4fdfefe5 3802 /* Enable ZIO. */
e315cd28 3803 if (!vha->flags.init_done) {
4fdfefe5
AV		 3804 ha->zio_mode = icb->add_firmware_options[0] &
3805 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
3806 ha->zio_timer = icb->interrupt_delay_timer ?
3807 icb->interrupt_delay_timer: 2;
3808 }
1da177e4
LT		 3809 icb->add_firmware_options[0] &=
3810 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
e315cd28 3811 vha->flags.process_response_queue = 0;
4fdfefe5 3812 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d
AV		 3813 ha->zio_mode = QLA_ZIO_MODE_6;
3814
7c3df132 3815 ql_log(ql_log_info, vha, 0x0068,
4fdfefe5
AV		 3816 "ZIO mode %d enabled; timer delay (%d us).\n",
3817 ha->zio_mode, ha->zio_timer * 100);
1da177e4 3818
4fdfefe5
AV		 3819 icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;
3820 icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;
e315cd28 3821 vha->flags.process_response_queue = 1;
1da177e4
LT		 3822 }
3823 }
3824
4e08df3f 3825 if (rval) {
7c3df132
SK		 3826 ql_log(ql_log_warn, vha, 0x0069,
3827 "NVRAM configuration failed.\n");
4e08df3f
DM		 3828 }
3829 return (rval);
1da177e4
LT		 3830}
3831
19a7b4ae
JSEC		 3832static void
3833qla2x00_rport_del(void *data)
3834{
3835 fc_port_t *fcport = data;
d97994dc 3836 struct fc_rport *rport;
044d78e1 3837 unsigned long flags;
d97994dc 3838
044d78e1 3839 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
ac280b67 3840 rport = fcport->drport ? fcport->drport: fcport->rport;
d97994dc 3841 fcport->drport = NULL;
044d78e1 3842 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
726b8548
QT		 3843 if (rport) {
3844 ql_dbg(ql_dbg_disc, fcport->vha, 0xffff,
3845 "%s %8phN. rport %p roles %x \n",
3846 __func__, fcport->port_name, rport,
3847 rport->roles);
3848
d97994dc 3849 fc_remote_port_delete(rport);
726b8548 3850 }
19a7b4ae
JSEC		 3851}
3852
1da177e4
LT		 3853/**
3854 * qla2x00_alloc_fcport() - Allocate a generic fcport.
3855 * @ha: HA context
3856 * @flags: allocation flags
3857 *
3858 * Returns a pointer to the allocated fcport, or NULL, if none available.
3859 */
9a069e19 3860fc_port_t *
e315cd28 3861qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags)
1da177e4
LT		 3862{
3863 fc_port_t *fcport;
3864
bbfbbbc1
MK		 3865 fcport = kzalloc(sizeof(fc_port_t), flags);
3866 if (!fcport)
3867 return NULL;
1da177e4
LT		 3868
3869 /* Setup fcport template structure. */
e315cd28 3870 fcport->vha = vha;
1da177e4
LT		 3871 fcport->port_type = FCT_UNKNOWN;
3872 fcport->loop_id = FC_NO_LOOP_ID;
ec426e10 3873 qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
ad3e0eda 3874 fcport->supported_classes = FC_COS_UNSPECIFIED;
1da177e4 3875
726b8548
QT		 3876 fcport->ct_desc.ct_sns = dma_alloc_coherent(&vha->hw->pdev->dev,
3877 sizeof(struct ct_sns_pkt), &fcport->ct_desc.ct_sns_dma,
6cb3216a 3878 flags);
726b8548
QT		 3879 fcport->disc_state = DSC_DELETED;
3880 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL;
3881 fcport->deleted = QLA_SESS_DELETED;
3882 fcport->login_retry = vha->hw->login_retry_count;
3883 fcport->login_retry = 5;
3884 fcport->logout_on_delete = 1;
3885
3886 if (!fcport->ct_desc.ct_sns) {
3887 ql_log(ql_log_warn, vha, 0xffff,
3888 "Failed to allocate ct_sns request.\n");
3889 kfree(fcport);
3890 fcport = NULL;
3891 }
3892 INIT_WORK(&fcport->del_work, qla24xx_delete_sess_fn);
3893 INIT_LIST_HEAD(&fcport->gnl_entry);
3894 INIT_LIST_HEAD(&fcport->list);
3895
bbfbbbc1 3896 return fcport;
1da177e4
LT		 3897}
3898
726b8548
QT		 3899void
3900qla2x00_free_fcport(fc_port_t *fcport)
3901{
3902 if (fcport->ct_desc.ct_sns) {
3903 dma_free_coherent(&fcport->vha->hw->pdev->dev,
3904 sizeof(struct ct_sns_pkt), fcport->ct_desc.ct_sns,
3905 fcport->ct_desc.ct_sns_dma);
3906
3907 fcport->ct_desc.ct_sns = NULL;
3908 }
3909 kfree(fcport);
3910}
3911
1da177e4
LT		 3912/*
3913 * qla2x00_configure_loop
3914 * Updates Fibre Channel Device Database with what is actually on loop.
3915 *
3916 * Input:
3917 * ha = adapter block pointer.
3918 *
3919 * Returns:
3920 * 0 = success.
3921 * 1 = error.
3922 * 2 = database was full and device was not configured.
3923 */
3924static int
e315cd28 3925qla2x00_configure_loop(scsi_qla_host_t *vha)
1da177e4
LT		 3926{
3927 int rval;
3928 unsigned long flags, save_flags;
e315cd28 3929 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3930 rval = QLA_SUCCESS;
3931
3932 /* Get Initiator ID */
e315cd28
AC		 3933 if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) {
3934 rval = qla2x00_configure_hba(vha);
1da177e4 3935 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3936 ql_dbg(ql_dbg_disc, vha, 0x2013,
3937 "Unable to configure HBA.\n");
1da177e4
LT		 3938 return (rval);
3939 }
3940 }
3941
e315cd28 3942 save_flags = flags = vha->dpc_flags;
7c3df132
SK		 3943 ql_dbg(ql_dbg_disc, vha, 0x2014,
3944 "Configure loop -- dpc flags = 0x%lx.\n", flags);
1da177e4
LT		 3945
3946 /*
3947 * If we have both an RSCN and PORT UPDATE pending then handle them
3948 * both at the same time.
3949 */
e315cd28
AC		 3950 clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
3951 clear_bit(RSCN_UPDATE, &vha->dpc_flags);
1da177e4 3952
3064ff39
MH		 3953 qla2x00_get_data_rate(vha);
3954
1da177e4
LT		 3955 /* Determine what we need to do */
3956 if (ha->current_topology == ISP_CFG_FL &&
3957 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
3958
1da177e4
LT		 3959 set_bit(RSCN_UPDATE, &flags);
3960
3961 } else if (ha->current_topology == ISP_CFG_F &&
3962 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
3963
1da177e4
LT		 3964 set_bit(RSCN_UPDATE, &flags);
3965 clear_bit(LOCAL_LOOP_UPDATE, &flags);
21333b48
AV		 3966
3967 } else if (ha->current_topology == ISP_CFG_N) {
3968 clear_bit(RSCN_UPDATE, &flags);
41dc529a
QT		 3969 } else if (ha->current_topology == ISP_CFG_NL) {
3970 clear_bit(RSCN_UPDATE, &flags);
3971 set_bit(LOCAL_LOOP_UPDATE, &flags);
e315cd28 3972 } else if (!vha->flags.online ||
1da177e4 3973 (test_bit(ABORT_ISP_ACTIVE, &flags))) {
1da177e4
LT		 3974 set_bit(RSCN_UPDATE, &flags);
3975 set_bit(LOCAL_LOOP_UPDATE, &flags);
3976 }
3977
3978 if (test_bit(LOCAL_LOOP_UPDATE, &flags)) {
7c3df132
SK		 3979 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
3980 ql_dbg(ql_dbg_disc, vha, 0x2015,
3981 "Loop resync needed, failing.\n");
1da177e4 3982 rval = QLA_FUNCTION_FAILED;
642ef983 3983 } else
e315cd28 3984 rval = qla2x00_configure_local_loop(vha);
1da177e4
LT		 3985 }
3986
3987 if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
7c3df132
SK		 3988 if (LOOP_TRANSITION(vha)) {
3989 ql_dbg(ql_dbg_disc, vha, 0x201e,
3990 "Needs RSCN update and loop transition.\n");
1da177e4 3991 rval = QLA_FUNCTION_FAILED;
7c3df132 3992 }
e315cd28
AC		 3993 else
3994 rval = qla2x00_configure_fabric(vha);
1da177e4
LT		 3995 }
3996
3997 if (rval == QLA_SUCCESS) {
e315cd28
AC		 3998 if (atomic_read(&vha->loop_down_timer) ||
3999 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4
LT		 4000 rval = QLA_FUNCTION_FAILED;
4001 } else {
e315cd28 4002 atomic_set(&vha->loop_state, LOOP_READY);
7c3df132
SK		 4003 ql_dbg(ql_dbg_disc, vha, 0x2069,
4004 "LOOP READY.\n");
3bb67df5
DKU		 4005
4006 /*
4007 * Process any ATIO queue entries that came in
4008 * while we weren't online.
4009 */
ead03855
QT		 4010 if (qla_tgt_mode_enabled(vha) ||
4011 qla_dual_mode_enabled(vha)) {
3bb67df5
DKU		 4012 if (IS_QLA27XX(ha) || IS_QLA83XX(ha)) {
4013 spin_lock_irqsave(&ha->tgt.atio_lock,
4014 flags);
4015 qlt_24xx_process_atio_queue(vha, 0);
4016 spin_unlock_irqrestore(
4017 &ha->tgt.atio_lock, flags);
4018 } else {
4019 spin_lock_irqsave(&ha->hardware_lock,
4020 flags);
4021 qlt_24xx_process_atio_queue(vha, 1);
4022 spin_unlock_irqrestore(
4023 &ha->hardware_lock, flags);
4024 }
4025 }
1da177e4
LT		 4026 }
4027 }
4028
4029 if (rval) {
7c3df132
SK		 4030 ql_dbg(ql_dbg_disc, vha, 0x206a,
4031 "%s *** FAILED ***.\n", __func__);
1da177e4 4032 } else {
7c3df132
SK		 4033 ql_dbg(ql_dbg_disc, vha, 0x206b,
4034 "%s: exiting normally.\n", __func__);
1da177e4
LT		 4035 }
4036
cc3ef7bc 4037 /* Restore state if a resync event occurred during processing */
e315cd28 4038 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4 4039 if (test_bit(LOCAL_LOOP_UPDATE, &save_flags))
e315cd28 4040 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
f4658b6c 4041 if (test_bit(RSCN_UPDATE, &save_flags)) {
e315cd28 4042 set_bit(RSCN_UPDATE, &vha->dpc_flags);
f4658b6c 4043 }
1da177e4
LT		 4044 }
4045
4046 return (rval);
4047}
4048
4049
4050
4051/*
4052 * qla2x00_configure_local_loop
4053 * Updates Fibre Channel Device Database with local loop devices.
4054 *
4055 * Input:
4056 * ha = adapter block pointer.
4057 *
4058 * Returns:
4059 * 0 = success.
4060 */
4061static int
e315cd28 4062qla2x00_configure_local_loop(scsi_qla_host_t *vha)
1da177e4
LT		 4063{
4064 int rval, rval2;
4065 int found_devs;
4066 int found;
4067 fc_port_t *fcport, *new_fcport;
4068
4069 uint16_t index;
4070 uint16_t entries;
4071 char *id_iter;
4072 uint16_t loop_id;
4073 uint8_t domain, area, al_pa;
e315cd28 4074 struct qla_hw_data *ha = vha->hw;
41dc529a 4075 unsigned long flags;
1da177e4
LT		 4076
4077 found_devs = 0;
4078 new_fcport = NULL;
642ef983 4079 entries = MAX_FIBRE_DEVICES_LOOP;
1da177e4 4080
1da177e4 4081 /* Get list of logged in devices. */
642ef983 4082 memset(ha->gid_list, 0, qla2x00_gid_list_size(ha));
e315cd28 4083 rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma,
1da177e4
LT		 4084 &entries);
4085 if (rval != QLA_SUCCESS)
4086 goto cleanup_allocation;
4087
7c3df132
SK		 4088 ql_dbg(ql_dbg_disc, vha, 0x2017,
4089 "Entries in ID list (%d).\n", entries);
4090 ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
4091 (uint8_t *)ha->gid_list,
4092 entries * sizeof(struct gid_list_info));
1da177e4
LT		 4093
4094 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 4095 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 4096 if (new_fcport == NULL) {
7c3df132
SK		 4097 ql_log(ql_log_warn, vha, 0x2018,
4098 "Memory allocation failed for fcport.\n");
1da177e4
LT		 4099 rval = QLA_MEMORY_ALLOC_FAILED;
4100 goto cleanup_allocation;
4101 }
4102 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
4103
4104 /*
4105 * Mark local devices that were present with FCF_DEVICE_LOST for now.
4106 */
e315cd28 4107 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 4108 if (atomic_read(&fcport->state) == FCS_ONLINE &&
4109 fcport->port_type != FCT_BROADCAST &&
4110 (fcport->flags & FCF_FABRIC_DEVICE) == 0) {
4111
7c3df132
SK		 4112 ql_dbg(ql_dbg_disc, vha, 0x2019,
4113 "Marking port lost loop_id=0x%04x.\n",
4114 fcport->loop_id);
1da177e4 4115
41dc529a 4116 qla2x00_mark_device_lost(vha, fcport, 0, 0);
1da177e4
LT		 4117 }
4118 }
4119
4120 /* Add devices to port list. */
4121 id_iter = (char *)ha->gid_list;
4122 for (index = 0; index < entries; index++) {
4123 domain = ((struct gid_list_info *)id_iter)->domain;
4124 area = ((struct gid_list_info *)id_iter)->area;
4125 al_pa = ((struct gid_list_info *)id_iter)->al_pa;
abbd8870 4126 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1da177e4
LT		 4127 loop_id = (uint16_t)
4128 ((struct gid_list_info *)id_iter)->loop_id_2100;
abbd8870 4129 else
1da177e4
LT		 4130 loop_id = le16_to_cpu(
4131 ((struct gid_list_info *)id_iter)->loop_id);
abbd8870 4132 id_iter += ha->gid_list_info_size;
1da177e4
LT		 4133
4134 /* Bypass reserved domain fields. */
4135 if ((domain & 0xf0) == 0xf0)
4136 continue;
4137
4138 /* Bypass if not same domain and area of adapter. */
f7d289f6 4139 if (area && domain &&
e315cd28 4140 (area != vha->d_id.b.area || domain != vha->d_id.b.domain))
1da177e4
LT		 4141 continue;
4142
4143 /* Bypass invalid local loop ID. */
4144 if (loop_id > LAST_LOCAL_LOOP_ID)
4145 continue;
4146
41dc529a 4147 memset(new_fcport->port_name, 0, WWN_SIZE);
370d550e 4148
1da177e4
LT		 4149 /* Fill in member data. */
4150 new_fcport->d_id.b.domain = domain;
4151 new_fcport->d_id.b.area = area;
4152 new_fcport->d_id.b.al_pa = al_pa;
4153 new_fcport->loop_id = loop_id;
41dc529a 4154
e315cd28 4155 rval2 = qla2x00_get_port_database(vha, new_fcport, 0);
1da177e4 4156 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 4157 ql_dbg(ql_dbg_disc, vha, 0x201a,
4158 "Failed to retrieve fcport information "
4159 "-- get_port_database=%x, loop_id=0x%04x.\n",
4160 rval2, new_fcport->loop_id);
4161 ql_dbg(ql_dbg_disc, vha, 0x201b,
4162 "Scheduling resync.\n");
e315cd28 4163 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4
LT		 4164 continue;
4165 }
4166
41dc529a 4167 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
1da177e4
LT		 4168 /* Check for matching device in port list. */
4169 found = 0;
4170 fcport = NULL;
e315cd28 4171 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 4172 if (memcmp(new_fcport->port_name, fcport->port_name,
4173 WWN_SIZE))
4174 continue;
4175
ddb9b126 4176 fcport->flags &= ~FCF_FABRIC_DEVICE;
1da177e4
LT		 4177 fcport->loop_id = new_fcport->loop_id;
4178 fcport->port_type = new_fcport->port_type;
4179 fcport->d_id.b24 = new_fcport->d_id.b24;
4180 memcpy(fcport->node_name, new_fcport->node_name,
4181 WWN_SIZE);
4182
41dc529a
QT		 4183 if (!fcport->login_succ) {
4184 vha->fcport_count++;
4185 fcport->login_succ = 1;
4186 fcport->disc_state = DSC_LOGIN_COMPLETE;
4187 }
4188
1da177e4
LT		 4189 found++;
4190 break;
4191 }
4192
4193 if (!found) {
4194 /* New device, add to fcports list. */
e315cd28 4195 list_add_tail(&new_fcport->list, &vha->vp_fcports);
1da177e4
LT		 4196
4197 /* Allocate a new replacement fcport. */
4198 fcport = new_fcport;
41dc529a
QT		 4199 if (!fcport->login_succ) {
4200 vha->fcport_count++;
4201 fcport->login_succ = 1;
4202 fcport->disc_state = DSC_LOGIN_COMPLETE;
4203 }
4204
4205 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
4206
e315cd28 4207 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
41dc529a 4208
1da177e4 4209 if (new_fcport == NULL) {
7c3df132
SK		 4210 ql_log(ql_log_warn, vha, 0x201c,
4211 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 4212 rval = QLA_MEMORY_ALLOC_FAILED;
4213 goto cleanup_allocation;
4214 }
41dc529a 4215 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
1da177e4
LT		 4216 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
4217 }
4218
41dc529a
QT		 4219 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
4220
d8b45213 4221 /* Base iIDMA settings on HBA port speed. */
a3cbdfad 4222 fcport->fp_speed = ha->link_data_rate;
d8b45213 4223
e315cd28 4224 qla2x00_update_fcport(vha, fcport);
1da177e4
LT		 4225
4226 found_devs++;
4227 }
4228
4229cleanup_allocation:
c9475cb0 4230 kfree(new_fcport);
1da177e4
LT		 4231
4232 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4233 ql_dbg(ql_dbg_disc, vha, 0x201d,
4234 "Configure local loop error exit: rval=%x.\n", rval);
1da177e4
LT		 4235 }
4236
1da177e4
LT		 4237 return (rval);
4238}
4239
d8b45213 4240static void
e315cd28 4241qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
d8b45213 4242{
d8b45213 4243 int rval;
93f2bd67 4244 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 4245 struct qla_hw_data *ha = vha->hw;
d8b45213 4246
c76f2c01 4247 if (!IS_IIDMA_CAPABLE(ha))
d8b45213
AV		 4248 return;
4249
c9afb9a2
GM		 4250 if (atomic_read(&fcport->state) != FCS_ONLINE)
4251 return;
4252
39bd9622
AV		 4253 if (fcport->fp_speed == PORT_SPEED_UNKNOWN ||
4254 fcport->fp_speed > ha->link_data_rate)
d8b45213
AV		 4255 return;
4256
e315cd28 4257 rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed,
a3cbdfad 4258 mb);
d8b45213 4259 if (rval != QLA_SUCCESS) {
7c3df132 4260 ql_dbg(ql_dbg_disc, vha, 0x2004,
7b833558
OK		 4261 "Unable to adjust iIDMA %8phN -- %04x %x %04x %04x.\n",
4262 fcport->port_name, rval, fcport->fp_speed, mb[0], mb[1]);
d8b45213 4263 } else {
7c3df132 4264 ql_dbg(ql_dbg_disc, vha, 0x2005,
7b833558 4265 "iIDMA adjusted to %s GB/s on %8phN.\n",
d0297c9a 4266 qla2x00_get_link_speed_str(ha, fcport->fp_speed),
7b833558 4267 fcport->port_name);
d8b45213
AV		 4268 }
4269}
4270
726b8548 4271/* qla2x00_reg_remote_port is reserved for Initiator Mode only.*/
23be331d 4272static void
e315cd28 4273qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport)
8482e118
AV		 4274{
4275 struct fc_rport_identifiers rport_ids;
bdf79621 4276 struct fc_rport *rport;
044d78e1 4277 unsigned long flags;
8482e118 4278
f8b02a85
AV		 4279 rport_ids.node_name = wwn_to_u64(fcport->node_name);
4280 rport_ids.port_name = wwn_to_u64(fcport->port_name);
8482e118
AV		 4281 rport_ids.port_id = fcport->d_id.b.domain << 16 |
4282 fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa;
77d74143 4283 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
e315cd28 4284 fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids);
77d74143 4285 if (!rport) {
7c3df132
SK		 4286 ql_log(ql_log_warn, vha, 0x2006,
4287 "Unable to allocate fc remote port.\n");
77d74143
AV		 4288 return;
4289 }
2d70c103 4290
044d78e1 4291 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
19a7b4ae 4292 *((fc_port_t **)rport->dd_data) = fcport;
044d78e1 4293 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
d97994dc 4294
ad3e0eda 4295 rport->supported_classes = fcport->supported_classes;
77d74143 4296
8482e118
AV		 4297 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
4298 if (fcport->port_type == FCT_INITIATOR)
4299 rport_ids.roles |= FC_RPORT_ROLE_FCP_INITIATOR;
4300 if (fcport->port_type == FCT_TARGET)
4301 rport_ids.roles |= FC_RPORT_ROLE_FCP_TARGET;
726b8548
QT		 4302
4303 ql_dbg(ql_dbg_disc, vha, 0xffff,
4304 "%s %8phN. rport %p is %s mode \n",
4305 __func__, fcport->port_name, rport,
4306 (fcport->port_type == FCT_TARGET) ? "tgt" : "ini");
4307
77d74143 4308 fc_remote_port_rolechg(rport, rport_ids.roles);
1da177e4
LT		 4309}
4310
23be331d
AB		 4311/*
4312 * qla2x00_update_fcport
4313 * Updates device on list.
4314 *
4315 * Input:
4316 * ha = adapter block pointer.
4317 * fcport = port structure pointer.
4318 *
4319 * Return:
4320 * 0 - Success
4321 * BIT_0 - error
4322 *
4323 * Context:
4324 * Kernel context.
4325 */
4326void
e315cd28 4327qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
23be331d 4328{
e315cd28 4329 fcport->vha = vha;
8ae6d9c7 4330
726b8548
QT		 4331 if (IS_SW_RESV_ADDR(fcport->d_id))
4332 return;
4333
4334 ql_dbg(ql_dbg_disc, vha, 0xffff, "%s %8phC \n",
4335 __func__, fcport->port_name);
4336
8ae6d9c7
GM		 4337 if (IS_QLAFX00(vha->hw)) {
4338 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
d20ed91b 4339 goto reg_port;
8ae6d9c7 4340 }
23be331d 4341 fcport->login_retry = 0;
5ff1d584 4342 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
726b8548
QT		 4343 fcport->disc_state = DSC_LOGIN_COMPLETE;
4344 fcport->deleted = 0;
4345 fcport->logout_on_delete = 1;
23be331d 4346
1f93da52 4347 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
e315cd28 4348 qla2x00_iidma_fcport(vha, fcport);
21090cbe 4349 qla24xx_update_fcport_fcp_prio(vha, fcport);
d20ed91b
AP		 4350
4351reg_port:
726b8548
QT		 4352 switch (vha->host->active_mode) {
4353 case MODE_INITIATOR:
d20ed91b 4354 qla2x00_reg_remote_port(vha, fcport);
726b8548
QT		 4355 break;
4356 case MODE_TARGET:
4357 if (!vha->vha_tgt.qla_tgt->tgt_stop &&
4358 !vha->vha_tgt.qla_tgt->tgt_stopped)
4359 qlt_fc_port_added(vha, fcport);
4360 break;
4361 case MODE_DUAL:
d20ed91b 4362 qla2x00_reg_remote_port(vha, fcport);
726b8548
QT		 4363 if (!vha->vha_tgt.qla_tgt->tgt_stop &&
4364 !vha->vha_tgt.qla_tgt->tgt_stopped)
4365 qlt_fc_port_added(vha, fcport);
4366 break;
4367 default:
4368 break;
d20ed91b 4369 }
23be331d
AB		 4370}
4371
1da177e4
LT		 4372/*
4373 * qla2x00_configure_fabric
4374 * Setup SNS devices with loop ID's.
4375 *
4376 * Input:
4377 * ha = adapter block pointer.
4378 *
4379 * Returns:
4380 * 0 = success.
4381 * BIT_0 = error
4382 */
4383static int
e315cd28 4384qla2x00_configure_fabric(scsi_qla_host_t *vha)
1da177e4 4385{
b3b02e6e 4386 int rval;
726b8548 4387 fc_port_t *fcport;
1da177e4 4388 uint16_t mb[MAILBOX_REGISTER_COUNT];
0107109e 4389 uint16_t loop_id;
1da177e4 4390 LIST_HEAD(new_fcports);
e315cd28 4391 struct qla_hw_data *ha = vha->hw;
df673274 4392 int discovery_gen;
1da177e4
LT		 4393
4394 /* If FL port exists, then SNS is present */
e428924c 4395 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 4396 loop_id = NPH_F_PORT;
4397 else
4398 loop_id = SNS_FL_PORT;
e315cd28 4399 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1);
1da177e4 4400 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4401 ql_dbg(ql_dbg_disc, vha, 0x201f,
4402 "MBX_GET_PORT_NAME failed, No FL Port.\n");
1da177e4 4403
e315cd28 4404 vha->device_flags &= ~SWITCH_FOUND;
1da177e4
LT		 4405 return (QLA_SUCCESS);
4406 }
e315cd28 4407 vha->device_flags |= SWITCH_FOUND;
1da177e4 4408
41dc529a
QT		 4409
4410 if (qla_tgt_mode_enabled(vha) || qla_dual_mode_enabled(vha)) {
4411 rval = qla2x00_send_change_request(vha, 0x3, 0);
4412 if (rval != QLA_SUCCESS)
4413 ql_log(ql_log_warn, vha, 0x121,
4414 "Failed to enable receiving of RSCN requests: 0x%x.\n",
4415 rval);
4416 }
4417
4418
1da177e4 4419 do {
726b8548
QT		 4420 qla2x00_mgmt_svr_login(vha);
4421
cca5335c
AV		 4422 /* FDMI support. */
4423 if (ql2xfdmienable &&
e315cd28
AC		 4424 test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags))
4425 qla2x00_fdmi_register(vha);
cca5335c 4426
1da177e4 4427 /* Ensure we are logged into the SNS. */
e428924c 4428 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 4429 loop_id = NPH_SNS;
4430 else
4431 loop_id = SIMPLE_NAME_SERVER;
0b91d116
CD		 4432 rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff,
4433 0xfc, mb, BIT_1|BIT_0);
4434 if (rval != QLA_SUCCESS) {
4435 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
e452ceb6 4436 return rval;
0b91d116 4437 }
1da177e4 4438 if (mb[0] != MBS_COMMAND_COMPLETE) {
7c3df132
SK		 4439 ql_dbg(ql_dbg_disc, vha, 0x2042,
4440 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x "
4441 "mb[6]=%x mb[7]=%x.\n", loop_id, mb[0], mb[1],
4442 mb[2], mb[6], mb[7]);
1da177e4
LT		 4443 return (QLA_SUCCESS);
4444 }
4445
e315cd28
AC		 4446 if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) {
4447 if (qla2x00_rft_id(vha)) {
1da177e4 4448 /* EMPTY */
7c3df132
SK		 4449 ql_dbg(ql_dbg_disc, vha, 0x2045,
4450 "Register FC-4 TYPE failed.\n");
1da177e4 4451 }
e315cd28 4452 if (qla2x00_rff_id(vha)) {
1da177e4 4453 /* EMPTY */
7c3df132
SK		 4454 ql_dbg(ql_dbg_disc, vha, 0x2049,
4455 "Register FC-4 Features failed.\n");
1da177e4 4456 }
e315cd28 4457 if (qla2x00_rnn_id(vha)) {
1da177e4 4458 /* EMPTY */
7c3df132
SK		 4459 ql_dbg(ql_dbg_disc, vha, 0x204f,
4460 "Register Node Name failed.\n");
e315cd28 4461 } else if (qla2x00_rsnn_nn(vha)) {
1da177e4 4462 /* EMPTY */
7c3df132
SK		 4463 ql_dbg(ql_dbg_disc, vha, 0x2053,
4464 "Register Symobilic Node Name failed.\n");
1da177e4
LT		 4465 }
4466 }
4467
827210ba
JC		 4468 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4469 fcport->scan_state = QLA_FCPORT_SCAN;
4470 }
4471
df673274
AP		 4472 /* Mark the time right before querying FW for connected ports.
4473 * This process is long, asynchronous and by the time it's done,
4474 * collected information might not be accurate anymore. E.g.
4475 * disconnected port might have re-connected and a brand new
4476 * session has been created. In this case session's generation
4477 * will be newer than discovery_gen. */
4478 qlt_do_generation_tick(vha, &discovery_gen);
4479
726b8548 4480 rval = qla2x00_find_all_fabric_devs(vha);
1da177e4
LT		 4481 if (rval != QLA_SUCCESS)
4482 break;
1da177e4
LT		 4483 } while (0);
4484
726b8548 4485 if (rval)
7c3df132
SK		 4486 ql_dbg(ql_dbg_disc, vha, 0x2068,
4487 "Configure fabric error exit rval=%d.\n", rval);
1da177e4
LT		 4488
4489 return (rval);
4490}
4491
1da177e4
LT		 4492/*
4493 * qla2x00_find_all_fabric_devs
4494 *
4495 * Input:
4496 * ha = adapter block pointer.
4497 * dev = database device entry pointer.
4498 *
4499 * Returns:
4500 * 0 = success.
4501 *
4502 * Context:
4503 * Kernel context.
4504 */
4505static int
726b8548 4506qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha)
1da177e4
LT		 4507{
4508 int rval;
4509 uint16_t loop_id;
726b8548 4510 fc_port_t *fcport, *new_fcport;
1da177e4
LT		 4511 int found;
4512
4513 sw_info_t *swl;
4514 int swl_idx;
4515 int first_dev, last_dev;
1516ef44 4516 port_id_t wrap = {}, nxt_d_id;
e315cd28 4517 struct qla_hw_data *ha = vha->hw;
bb4cf5b7 4518 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
726b8548 4519 unsigned long flags;
1da177e4
LT		 4520
4521 rval = QLA_SUCCESS;
4522
4523 /* Try GID_PT to get device list, else GAN. */
7a67735b 4524 if (!ha->swl)
642ef983 4525 ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t),
7a67735b
AV		 4526 GFP_KERNEL);
4527 swl = ha->swl;
bbfbbbc1 4528 if (!swl) {
1da177e4 4529 /*EMPTY*/
7c3df132
SK		 4530 ql_dbg(ql_dbg_disc, vha, 0x2054,
4531 "GID_PT allocations failed, fallback on GA_NXT.\n");
1da177e4 4532 } else {
642ef983 4533 memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t));
e315cd28 4534 if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) {
1da177e4 4535 swl = NULL;
e315cd28 4536 } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 4537 swl = NULL;
e315cd28 4538 } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 4539 swl = NULL;
726b8548
QT		 4540 } else if (qla2x00_gfpn_id(vha, swl) != QLA_SUCCESS) {
4541 swl = NULL;
1da177e4 4542 }
e8c72ba5
CD		 4543
4544 /* If other queries succeeded probe for FC-4 type */
4545 if (swl)
4546 qla2x00_gff_id(vha, swl);
1da177e4
LT		 4547 }
4548 swl_idx = 0;
4549
4550 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 4551 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 4552 if (new_fcport == NULL) {
7c3df132
SK		 4553 ql_log(ql_log_warn, vha, 0x205e,
4554 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 4555 return (QLA_MEMORY_ALLOC_FAILED);
4556 }
4557 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
1da177e4
LT		 4558 /* Set start port ID scan at adapter ID. */
4559 first_dev = 1;
4560 last_dev = 0;
4561
4562 /* Starting free loop ID. */
e315cd28
AC		 4563 loop_id = ha->min_external_loopid;
4564 for (; loop_id <= ha->max_loop_id; loop_id++) {
4565 if (qla2x00_is_reserved_id(vha, loop_id))
1da177e4
LT		 4566 continue;
4567
3a6478df
GM		 4568 if (ha->current_topology == ISP_CFG_FL &&
4569 (atomic_read(&vha->loop_down_timer) ||
4570 LOOP_TRANSITION(vha))) {
bb2d52b2
AV		 4571 atomic_set(&vha->loop_down_timer, 0);
4572 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
4573 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
1da177e4 4574 break;
bb2d52b2 4575 }
1da177e4
LT		 4576
4577 if (swl != NULL) {
4578 if (last_dev) {
4579 wrap.b24 = new_fcport->d_id.b24;
4580 } else {
4581 new_fcport->d_id.b24 = swl[swl_idx].d_id.b24;
4582 memcpy(new_fcport->node_name,
4583 swl[swl_idx].node_name, WWN_SIZE);
4584 memcpy(new_fcport->port_name,
4585 swl[swl_idx].port_name, WWN_SIZE);
d8b45213
AV		 4586 memcpy(new_fcport->fabric_port_name,
4587 swl[swl_idx].fabric_port_name, WWN_SIZE);
4588 new_fcport->fp_speed = swl[swl_idx].fp_speed;
e8c72ba5 4589 new_fcport->fc4_type = swl[swl_idx].fc4_type;
1da177e4
LT		 4590
4591 if (swl[swl_idx].d_id.b.rsvd_1 != 0) {
4592 last_dev = 1;
4593 }
4594 swl_idx++;
4595 }
4596 } else {
4597 /* Send GA_NXT to the switch */
e315cd28 4598 rval = qla2x00_ga_nxt(vha, new_fcport);
1da177e4 4599 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4600 ql_log(ql_log_warn, vha, 0x2064,
4601 "SNS scan failed -- assuming "
4602 "zero-entry result.\n");
1da177e4
LT		 4603 rval = QLA_SUCCESS;
4604 break;
4605 }
4606 }
4607
4608 /* If wrap on switch device list, exit. */
4609 if (first_dev) {
4610 wrap.b24 = new_fcport->d_id.b24;
4611 first_dev = 0;
4612 } else if (new_fcport->d_id.b24 == wrap.b24) {
7c3df132
SK		 4613 ql_dbg(ql_dbg_disc, vha, 0x2065,
4614 "Device wrap (%02x%02x%02x).\n",
4615 new_fcport->d_id.b.domain,
4616 new_fcport->d_id.b.area,
4617 new_fcport->d_id.b.al_pa);
1da177e4
LT		 4618 break;
4619 }
4620
2c3dfe3f 4621 /* Bypass if same physical adapter. */
e315cd28 4622 if (new_fcport->d_id.b24 == base_vha->d_id.b24)
1da177e4
LT		 4623 continue;
4624
2c3dfe3f 4625 /* Bypass virtual ports of the same host. */
bb4cf5b7
CD		 4626 if (qla2x00_is_a_vp_did(vha, new_fcport->d_id.b24))
4627 continue;
2c3dfe3f 4628
f7d289f6
AV		 4629 /* Bypass if same domain and area of adapter. */
4630 if (((new_fcport->d_id.b24 & 0xffff00) ==
e315cd28 4631 (vha->d_id.b24 & 0xffff00)) && ha->current_topology ==
f7d289f6
AV		 4632 ISP_CFG_FL)
4633 continue;
4634
1da177e4
LT		 4635 /* Bypass reserved domain fields. */
4636 if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0)
4637 continue;
4638
e8c72ba5 4639 /* Bypass ports whose FCP-4 type is not FCP_SCSI */
4da26e16
CD		 4640 if (ql2xgffidenable &&
4641 (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI &&
4642 new_fcport->fc4_type != FC4_TYPE_UNKNOWN))
e8c72ba5
CD		 4643 continue;
4644
726b8548
QT		 4645 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
4646
1da177e4
LT		 4647 /* Locate matching device in database. */
4648 found = 0;
e315cd28 4649 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 4650 if (memcmp(new_fcport->port_name, fcport->port_name,
4651 WWN_SIZE))
4652 continue;
4653
827210ba 4654 fcport->scan_state = QLA_FCPORT_FOUND;
b3b02e6e 4655
1da177e4
LT		 4656 found++;
4657
d8b45213
AV		 4658 /* Update port state. */
4659 memcpy(fcport->fabric_port_name,
4660 new_fcport->fabric_port_name, WWN_SIZE);
4661 fcport->fp_speed = new_fcport->fp_speed;
4662
1da177e4 4663 /*
b2032fd5
RD		 4664 * If address the same and state FCS_ONLINE
4665 * (or in target mode), nothing changed.
1da177e4
LT		 4666 */
4667 if (fcport->d_id.b24 == new_fcport->d_id.b24 &&
b2032fd5 4668 (atomic_read(&fcport->state) == FCS_ONLINE ||
726b8548 4669 (vha->host->active_mode == MODE_TARGET))) {
1da177e4
LT		 4670 break;
4671 }
4672
4673 /*
4674 * If device was not a fabric device before.
4675 */
4676 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) {
4677 fcport->d_id.b24 = new_fcport->d_id.b24;
5f16b331 4678 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 4679 fcport->flags |= (FCF_FABRIC_DEVICE |
4680 FCF_LOGIN_NEEDED);
1da177e4
LT		 4681 break;
4682 }
4683
4684 /*
4685 * Port ID changed or device was marked to be updated;
4686 * Log it out if still logged in and mark it for
4687 * relogin later.
4688 */
726b8548 4689 if (qla_tgt_mode_enabled(base_vha)) {
b2032fd5
RD		 4690 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf080,
4691 "port changed FC ID, %8phC"
4692 " old %x:%x:%x (loop_id 0x%04x)-> new %x:%x:%x\n",
4693 fcport->port_name,
4694 fcport->d_id.b.domain,
4695 fcport->d_id.b.area,
4696 fcport->d_id.b.al_pa,
4697 fcport->loop_id,
4698 new_fcport->d_id.b.domain,
4699 new_fcport->d_id.b.area,
4700 new_fcport->d_id.b.al_pa);
4701 fcport->d_id.b24 = new_fcport->d_id.b24;
4702 break;
4703 }
4704
1da177e4
LT		 4705 fcport->d_id.b24 = new_fcport->d_id.b24;
4706 fcport->flags |= FCF_LOGIN_NEEDED;
1da177e4
LT		 4707 break;
4708 }
4709
726b8548
QT		 4710 if (found) {
4711 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1da177e4 4712 continue;
726b8548 4713 }
1da177e4 4714 /* If device was not in our fcports list, then add it. */
b2032fd5 4715 new_fcport->scan_state = QLA_FCPORT_FOUND;
726b8548
QT		 4716 list_add_tail(&new_fcport->list, &vha->vp_fcports);
4717
4718 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
4719
1da177e4
LT		 4720
4721 /* Allocate a new replacement fcport. */
4722 nxt_d_id.b24 = new_fcport->d_id.b24;
e315cd28 4723 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 4724 if (new_fcport == NULL) {
7c3df132
SK		 4725 ql_log(ql_log_warn, vha, 0x2066,
4726 "Memory allocation failed for fcport.\n");
1da177e4
LT		 4727 return (QLA_MEMORY_ALLOC_FAILED);
4728 }
4729 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
4730 new_fcport->d_id.b24 = nxt_d_id.b24;
4731 }
4732
726b8548
QT		 4733 qla2x00_free_fcport(new_fcport);
4734
4735 /*
4736 * Logout all previous fabric dev marked lost, except FCP2 devices.
4737 */
4738 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4739 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4740 break;
4741
4742 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0 ||
4743 (fcport->flags & FCF_LOGIN_NEEDED) == 0)
4744 continue;
4745
4746 if (fcport->scan_state == QLA_FCPORT_SCAN) {
4747 if ((qla_dual_mode_enabled(vha) ||
4748 qla_ini_mode_enabled(vha)) &&
4749 atomic_read(&fcport->state) == FCS_ONLINE) {
4750 qla2x00_mark_device_lost(vha, fcport,
4751 ql2xplogiabsentdevice, 0);
4752 if (fcport->loop_id != FC_NO_LOOP_ID &&
4753 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
4754 fcport->port_type != FCT_INITIATOR &&
4755 fcport->port_type != FCT_BROADCAST) {
4756 ql_dbg(ql_dbg_disc, vha, 0xffff,
4757 "%s %d %8phC post del sess\n",
4758 __func__, __LINE__,
4759 fcport->port_name);
4760
4761 qlt_schedule_sess_for_deletion_lock
4762 (fcport);
4763 continue;
4764 }
4765 }
4766 }
1da177e4 4767
726b8548
QT		 4768 if (fcport->scan_state == QLA_FCPORT_FOUND)
4769 qla24xx_fcport_handle_login(vha, fcport);
4770 }
1da177e4
LT		 4771 return (rval);
4772}
4773
4774/*
4775 * qla2x00_find_new_loop_id
4776 * Scan through our port list and find a new usable loop ID.
4777 *
4778 * Input:
4779 * ha: adapter state pointer.
4780 * dev: port structure pointer.
4781 *
4782 * Returns:
4783 * qla2x00 local function return status code.
4784 *
4785 * Context:
4786 * Kernel context.
4787 */
03bcfb57 4788int
e315cd28 4789qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
1da177e4
LT		 4790{
4791 int rval;
e315cd28 4792 struct qla_hw_data *ha = vha->hw;
feafb7b1 4793 unsigned long flags = 0;
1da177e4
LT		 4794
4795 rval = QLA_SUCCESS;
4796
5f16b331 4797 spin_lock_irqsave(&ha->vport_slock, flags);
1da177e4 4798
5f16b331
CD		 4799 dev->loop_id = find_first_zero_bit(ha->loop_id_map,
4800 LOOPID_MAP_SIZE);
4801 if (dev->loop_id >= LOOPID_MAP_SIZE ||
4802 qla2x00_is_reserved_id(vha, dev->loop_id)) {
4803 dev->loop_id = FC_NO_LOOP_ID;
4804 rval = QLA_FUNCTION_FAILED;
4805 } else
4806 set_bit(dev->loop_id, ha->loop_id_map);
1da177e4 4807
5f16b331 4808 spin_unlock_irqrestore(&ha->vport_slock, flags);
1da177e4 4809
5f16b331
CD		 4810 if (rval == QLA_SUCCESS)
4811 ql_dbg(ql_dbg_disc, dev->vha, 0x2086,
4812 "Assigning new loopid=%x, portid=%x.\n",
4813 dev->loop_id, dev->d_id.b24);
4814 else
4815 ql_log(ql_log_warn, dev->vha, 0x2087,
4816 "No loop_id's available, portid=%x.\n",
4817 dev->d_id.b24);
1da177e4
LT		 4818
4819 return (rval);
4820}
4821
1da177e4
LT		 4822
4823/*
4824 * qla2x00_fabric_login
4825 * Issue fabric login command.
4826 *
4827 * Input:
4828 * ha = adapter block pointer.
4829 * device = pointer to FC device type structure.
4830 *
4831 * Returns:
4832 * 0 - Login successfully
4833 * 1 - Login failed
4834 * 2 - Initiator device
4835 * 3 - Fatal error
4836 */
4837int
e315cd28 4838qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 4839 uint16_t *next_loopid)
4840{
4841 int rval;
4842 int retry;
4843 uint16_t tmp_loopid;
4844 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 4845 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 4846
4847 retry = 0;
4848 tmp_loopid = 0;
4849
4850 for (;;) {
7c3df132
SK		 4851 ql_dbg(ql_dbg_disc, vha, 0x2000,
4852 "Trying Fabric Login w/loop id 0x%04x for port "
4853 "%02x%02x%02x.\n",
4854 fcport->loop_id, fcport->d_id.b.domain,
4855 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 4856
4857 /* Login fcport on switch. */
0b91d116 4858 rval = ha->isp_ops->fabric_login(vha, fcport->loop_id,
1da177e4
LT		 4859 fcport->d_id.b.domain, fcport->d_id.b.area,
4860 fcport->d_id.b.al_pa, mb, BIT_0);
0b91d116
CD		 4861 if (rval != QLA_SUCCESS) {
4862 return rval;
4863 }
1da177e4
LT		 4864 if (mb[0] == MBS_PORT_ID_USED) {
4865 /*
4866 * Device has another loop ID. The firmware team
0107109e
AV		 4867 * recommends the driver perform an implicit login with
4868 * the specified ID again. The ID we just used is save
4869 * here so we return with an ID that can be tried by
4870 * the next login.
1da177e4
LT		 4871 */
4872 retry++;
4873 tmp_loopid = fcport->loop_id;
4874 fcport->loop_id = mb[1];
4875
7c3df132
SK		 4876 ql_dbg(ql_dbg_disc, vha, 0x2001,
4877 "Fabric Login: port in use - next loop "
4878 "id=0x%04x, port id= %02x%02x%02x.\n",
1da177e4 4879 fcport->loop_id, fcport->d_id.b.domain,
7c3df132 4880 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 4881
4882 } else if (mb[0] == MBS_COMMAND_COMPLETE) {
4883 /*
4884 * Login succeeded.
4885 */
4886 if (retry) {
4887 /* A retry occurred before. */
4888 *next_loopid = tmp_loopid;
4889 } else {
4890 /*
4891 * No retry occurred before. Just increment the
4892 * ID value for next login.
4893 */
4894 *next_loopid = (fcport->loop_id + 1);
4895 }
4896
4897 if (mb[1] & BIT_0) {
4898 fcport->port_type = FCT_INITIATOR;
4899 } else {
4900 fcport->port_type = FCT_TARGET;
4901 if (mb[1] & BIT_1) {
8474f3a0 4902 fcport->flags |= FCF_FCP2_DEVICE;
1da177e4
LT		 4903 }
4904 }
4905
ad3e0eda
AV		 4906 if (mb[10] & BIT_0)
4907 fcport->supported_classes |= FC_COS_CLASS2;
4908 if (mb[10] & BIT_1)
4909 fcport->supported_classes |= FC_COS_CLASS3;
4910
2d70c103
NB		 4911 if (IS_FWI2_CAPABLE(ha)) {
4912 if (mb[10] & BIT_7)
4913 fcport->flags |=
4914 FCF_CONF_COMP_SUPPORTED;
4915 }
4916
1da177e4
LT		 4917 rval = QLA_SUCCESS;
4918 break;
4919 } else if (mb[0] == MBS_LOOP_ID_USED) {
4920 /*
4921 * Loop ID already used, try next loop ID.
4922 */
4923 fcport->loop_id++;
e315cd28 4924 rval = qla2x00_find_new_loop_id(vha, fcport);
1da177e4
LT		 4925 if (rval != QLA_SUCCESS) {
4926 /* Ran out of loop IDs to use */
4927 break;
4928 }
4929 } else if (mb[0] == MBS_COMMAND_ERROR) {
4930 /*
4931 * Firmware possibly timed out during login. If NO
4932 * retries are left to do then the device is declared
4933 * dead.
4934 */
4935 *next_loopid = fcport->loop_id;
e315cd28 4936 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 4937 fcport->d_id.b.domain, fcport->d_id.b.area,
4938 fcport->d_id.b.al_pa);
e315cd28 4939 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 4940
4941 rval = 1;
4942 break;
4943 } else {
4944 /*
4945 * unrecoverable / not handled error
4946 */
7c3df132
SK		 4947 ql_dbg(ql_dbg_disc, vha, 0x2002,
4948 "Failed=%x port_id=%02x%02x%02x loop_id=%x "
4949 "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain,
4950 fcport->d_id.b.area, fcport->d_id.b.al_pa,
4951 fcport->loop_id, jiffies);
1da177e4
LT		 4952
4953 *next_loopid = fcport->loop_id;
e315cd28 4954 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 4955 fcport->d_id.b.domain, fcport->d_id.b.area,
4956 fcport->d_id.b.al_pa);
5f16b331 4957 qla2x00_clear_loop_id(fcport);
0eedfcf0 4958 fcport->login_retry = 0;
1da177e4
LT		 4959
4960 rval = 3;
4961 break;
4962 }
4963 }
4964
4965 return (rval);
4966}
4967
4968/*
4969 * qla2x00_local_device_login
4970 * Issue local device login command.
4971 *
4972 * Input:
4973 * ha = adapter block pointer.
4974 * loop_id = loop id of device to login to.
4975 *
4976 * Returns (Where's the #define!!!!):
4977 * 0 - Login successfully
4978 * 1 - Login failed
4979 * 3 - Fatal error
4980 */
4981int
e315cd28 4982qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport)
1da177e4
LT		 4983{
4984 int rval;
4985 uint16_t mb[MAILBOX_REGISTER_COUNT];
4986
4987 memset(mb, 0, sizeof(mb));
e315cd28 4988 rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0);
1da177e4
LT		 4989 if (rval == QLA_SUCCESS) {
4990 /* Interrogate mailbox registers for any errors */
4991 if (mb[0] == MBS_COMMAND_ERROR)
4992 rval = 1;
4993 else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR)
4994 /* device not in PCB table */
4995 rval = 3;
4996 }
4997
4998 return (rval);
4999}
5000
5001/*
5002 * qla2x00_loop_resync
5003 * Resync with fibre channel devices.
5004 *
5005 * Input:
5006 * ha = adapter block pointer.
5007 *
5008 * Returns:
5009 * 0 = success
5010 */
5011int
e315cd28 5012qla2x00_loop_resync(scsi_qla_host_t *vha)
1da177e4 5013{
73208dfd 5014 int rval = QLA_SUCCESS;
1da177e4 5015 uint32_t wait_time;
67c2e93a
AC		 5016 struct req_que *req;
5017 struct rsp_que *rsp;
5018
d7459527 5019 req = vha->req;
67c2e93a 5020 rsp = req->rsp;
1da177e4 5021
e315cd28
AC		 5022 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
5023 if (vha->flags.online) {
5024 if (!(rval = qla2x00_fw_ready(vha))) {
1da177e4
LT		 5025 /* Wait at most MAX_TARGET RSCNs for a stable link. */
5026 wait_time = 256;
5027 do {
8ae6d9c7
GM		 5028 if (!IS_QLAFX00(vha->hw)) {
5029 /*
5030 * Issue a marker after FW becomes
5031 * ready.
5032 */
5033 qla2x00_marker(vha, req, rsp, 0, 0,
5034 MK_SYNC_ALL);
5035 vha->marker_needed = 0;
5036 }
1da177e4
LT		 5037
5038 /* Remap devices on Loop. */
e315cd28 5039 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4 5040
8ae6d9c7
GM		 5041 if (IS_QLAFX00(vha->hw))
5042 qlafx00_configure_devices(vha);
5043 else
5044 qla2x00_configure_loop(vha);
5045
1da177e4 5046 wait_time--;
e315cd28
AC		 5047 } while (!atomic_read(&vha->loop_down_timer) &&
5048 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
5049 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
5050 &vha->dpc_flags)));
1da177e4 5051 }
1da177e4
LT		 5052 }
5053
e315cd28 5054 if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
1da177e4 5055 return (QLA_FUNCTION_FAILED);
1da177e4 5056
e315cd28 5057 if (rval)
7c3df132
SK		 5058 ql_dbg(ql_dbg_disc, vha, 0x206c,
5059 "%s *** FAILED ***.\n", __func__);
1da177e4
LT		 5060
5061 return (rval);
5062}
5063
579d12b5
SK		 5064/*
5065* qla2x00_perform_loop_resync
5066* Description: This function will set the appropriate flags and call
5067* qla2x00_loop_resync. If successful loop will be resynced
5068* Arguments : scsi_qla_host_t pointer
5069* returm : Success or Failure
5070*/
5071
5072int qla2x00_perform_loop_resync(scsi_qla_host_t *ha)
5073{
5074 int32_t rval = 0;
5075
5076 if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) {
5077 /*Configure the flags so that resync happens properly*/
5078 atomic_set(&ha->loop_down_timer, 0);
5079 if (!(ha->device_flags & DFLG_NO_CABLE)) {
5080 atomic_set(&ha->loop_state, LOOP_UP);
5081 set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags);
5082 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
5083 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
5084
5085 rval = qla2x00_loop_resync(ha);
5086 } else
5087 atomic_set(&ha->loop_state, LOOP_DEAD);
5088
5089 clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags);
5090 }
5091
5092 return rval;
5093}
5094
d97994dc 5095void
67becc00 5096qla2x00_update_fcports(scsi_qla_host_t *base_vha)
d97994dc
AV		 5097{
5098 fc_port_t *fcport;
feafb7b1
AE		 5099 struct scsi_qla_host *vha;
5100 struct qla_hw_data *ha = base_vha->hw;
5101 unsigned long flags;
d97994dc 5102
feafb7b1 5103 spin_lock_irqsave(&ha->vport_slock, flags);
d97994dc 5104 /* Go with deferred removal of rport references. */
feafb7b1
AE		 5105 list_for_each_entry(vha, &base_vha->hw->vp_list, list) {
5106 atomic_inc(&vha->vref_count);
5107 list_for_each_entry(fcport, &vha->vp_fcports, list) {
8ae598d0 5108 if (fcport->drport &&
feafb7b1
AE		 5109 atomic_read(&fcport->state) != FCS_UNCONFIGURED) {
5110 spin_unlock_irqrestore(&ha->vport_slock, flags);
67becc00 5111 qla2x00_rport_del(fcport);
df673274 5112
feafb7b1
AE		 5113 spin_lock_irqsave(&ha->vport_slock, flags);
5114 }
5115 }
5116 atomic_dec(&vha->vref_count);
c4a9b538 5117 wake_up(&vha->vref_waitq);
feafb7b1
AE		 5118 }
5119 spin_unlock_irqrestore(&ha->vport_slock, flags);
d97994dc
AV		 5120}
5121
7d613ac6
SV		 5122/* Assumes idc_lock always held on entry */
5123void
5124qla83xx_reset_ownership(scsi_qla_host_t *vha)
5125{
5126 struct qla_hw_data *ha = vha->hw;
5127 uint32_t drv_presence, drv_presence_mask;
5128 uint32_t dev_part_info1, dev_part_info2, class_type;
5129 uint32_t class_type_mask = 0x3;
5130 uint16_t fcoe_other_function = 0xffff, i;
5131
7ec0effd
AD		 5132 if (IS_QLA8044(ha)) {
5133 drv_presence = qla8044_rd_direct(vha,
5134 QLA8044_CRB_DRV_ACTIVE_INDEX);
5135 dev_part_info1 = qla8044_rd_direct(vha,
5136 QLA8044_CRB_DEV_PART_INFO_INDEX);
5137 dev_part_info2 = qla8044_rd_direct(vha,
5138 QLA8044_CRB_DEV_PART_INFO2);
5139 } else {
5140 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5141 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1);
5142 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2);
5143 }
7d613ac6
SV		 5144 for (i = 0; i < 8; i++) {
5145 class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask);
5146 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
5147 (i != ha->portnum)) {
5148 fcoe_other_function = i;
5149 break;
5150 }
5151 }
5152 if (fcoe_other_function == 0xffff) {
5153 for (i = 0; i < 8; i++) {
5154 class_type = ((dev_part_info2 >> (i * 4)) &
5155 class_type_mask);
5156 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
5157 ((i + 8) != ha->portnum)) {
5158 fcoe_other_function = i + 8;
5159 break;
5160 }
5161 }
5162 }
5163 /*
5164 * Prepare drv-presence mask based on fcoe functions present.
5165 * However consider only valid physical fcoe function numbers (0-15).
5166 */
5167 drv_presence_mask = ~((1 << (ha->portnum)) |
5168 ((fcoe_other_function == 0xffff) ?
5169 0 : (1 << (fcoe_other_function))));
5170
5171 /* We are the reset owner iff:
5172 * - No other protocol drivers present.
5173 * - This is the lowest among fcoe functions. */
5174 if (!(drv_presence & drv_presence_mask) &&
5175 (ha->portnum < fcoe_other_function)) {
5176 ql_dbg(ql_dbg_p3p, vha, 0xb07f,
5177 "This host is Reset owner.\n");
5178 ha->flags.nic_core_reset_owner = 1;
5179 }
5180}
5181
fa492630 5182static int
7d613ac6
SV		 5183__qla83xx_set_drv_ack(scsi_qla_host_t *vha)
5184{
5185 int rval = QLA_SUCCESS;
5186 struct qla_hw_data *ha = vha->hw;
5187 uint32_t drv_ack;
5188
5189 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
5190 if (rval == QLA_SUCCESS) {
5191 drv_ack |= (1 << ha->portnum);
5192 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
5193 }
5194
5195 return rval;
5196}
5197
fa492630 5198static int
7d613ac6
SV		 5199__qla83xx_clear_drv_ack(scsi_qla_host_t *vha)
5200{
5201 int rval = QLA_SUCCESS;
5202 struct qla_hw_data *ha = vha->hw;
5203 uint32_t drv_ack;
5204
5205 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
5206 if (rval == QLA_SUCCESS) {
5207 drv_ack &= ~(1 << ha->portnum);
5208 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
5209 }
5210
5211 return rval;
5212}
5213
fa492630 5214static const char *
7d613ac6
SV		 5215qla83xx_dev_state_to_string(uint32_t dev_state)
5216{
5217 switch (dev_state) {
5218 case QLA8XXX_DEV_COLD:
5219 return "COLD/RE-INIT";
5220 case QLA8XXX_DEV_INITIALIZING:
5221 return "INITIALIZING";
5222 case QLA8XXX_DEV_READY:
5223 return "READY";
5224 case QLA8XXX_DEV_NEED_RESET:
5225 return "NEED RESET";
5226 case QLA8XXX_DEV_NEED_QUIESCENT:
5227 return "NEED QUIESCENT";
5228 case QLA8XXX_DEV_FAILED:
5229 return "FAILED";
5230 case QLA8XXX_DEV_QUIESCENT:
5231 return "QUIESCENT";
5232 default:
5233 return "Unknown";
5234 }
5235}
5236
5237/* Assumes idc-lock always held on entry */
5238void
5239qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type)
5240{
5241 struct qla_hw_data *ha = vha->hw;
5242 uint32_t idc_audit_reg = 0, duration_secs = 0;
5243
5244 switch (audit_type) {
5245 case IDC_AUDIT_TIMESTAMP:
5246 ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000);
5247 idc_audit_reg = (ha->portnum) |
5248 (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8);
5249 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
5250 break;
5251
5252 case IDC_AUDIT_COMPLETION:
5253 duration_secs = ((jiffies_to_msecs(jiffies) -
5254 jiffies_to_msecs(ha->idc_audit_ts)) / 1000);
5255 idc_audit_reg = (ha->portnum) |
5256 (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8);
5257 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
5258 break;
5259
5260 default:
5261 ql_log(ql_log_warn, vha, 0xb078,
5262 "Invalid audit type specified.\n");
5263 break;
5264 }
5265}
5266
5267/* Assumes idc_lock always held on entry */
fa492630 5268static int
7d613ac6
SV		 5269qla83xx_initiating_reset(scsi_qla_host_t *vha)
5270{
5271 struct qla_hw_data *ha = vha->hw;
5272 uint32_t idc_control, dev_state;
5273
5274 __qla83xx_get_idc_control(vha, &idc_control);
5275 if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) {
5276 ql_log(ql_log_info, vha, 0xb080,
5277 "NIC Core reset has been disabled. idc-control=0x%x\n",
5278 idc_control);
5279 return QLA_FUNCTION_FAILED;
5280 }
5281
5282 /* Set NEED-RESET iff in READY state and we are the reset-owner */
5283 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5284 if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) {
5285 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
5286 QLA8XXX_DEV_NEED_RESET);
5287 ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n");
5288 qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP);
5289 } else {
5290 const char *state = qla83xx_dev_state_to_string(dev_state);
5291 ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n", state);
5292
5293 /* SV: XXX: Is timeout required here? */
5294 /* Wait for IDC state change READY -> NEED_RESET */
5295 while (dev_state == QLA8XXX_DEV_READY) {
5296 qla83xx_idc_unlock(vha, 0);
5297 msleep(200);
5298 qla83xx_idc_lock(vha, 0);
5299 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5300 }
5301 }
5302
5303 /* Send IDC ack by writing to drv-ack register */
5304 __qla83xx_set_drv_ack(vha);
5305
5306 return QLA_SUCCESS;
5307}
5308
5309int
5310__qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control)
5311{
5312 return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
5313}
5314
7d613ac6
SV		 5315int
5316__qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control)
5317{
5318 return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
5319}
5320
fa492630 5321static int
7d613ac6
SV		 5322qla83xx_check_driver_presence(scsi_qla_host_t *vha)
5323{
5324 uint32_t drv_presence = 0;
5325 struct qla_hw_data *ha = vha->hw;
5326
5327 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5328 if (drv_presence & (1 << ha->portnum))
5329 return QLA_SUCCESS;
5330 else
5331 return QLA_TEST_FAILED;
5332}
5333
5334int
5335qla83xx_nic_core_reset(scsi_qla_host_t *vha)
5336{
5337 int rval = QLA_SUCCESS;
5338 struct qla_hw_data *ha = vha->hw;
5339
5340 ql_dbg(ql_dbg_p3p, vha, 0xb058,
5341 "Entered %s().\n", __func__);
5342
5343 if (vha->device_flags & DFLG_DEV_FAILED) {
5344 ql_log(ql_log_warn, vha, 0xb059,
5345 "Device in unrecoverable FAILED state.\n");
5346 return QLA_FUNCTION_FAILED;
5347 }
5348
5349 qla83xx_idc_lock(vha, 0);
5350
5351 if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) {
5352 ql_log(ql_log_warn, vha, 0xb05a,
5353 "Function=0x%x has been removed from IDC participation.\n",
5354 ha->portnum);
5355 rval = QLA_FUNCTION_FAILED;
5356 goto exit;
5357 }
5358
5359 qla83xx_reset_ownership(vha);
5360
5361 rval = qla83xx_initiating_reset(vha);
5362
5363 /*
5364 * Perform reset if we are the reset-owner,
5365 * else wait till IDC state changes to READY/FAILED.
5366 */
5367 if (rval == QLA_SUCCESS) {
5368 rval = qla83xx_idc_state_handler(vha);
5369
5370 if (rval == QLA_SUCCESS)
5371 ha->flags.nic_core_hung = 0;
5372 __qla83xx_clear_drv_ack(vha);
5373 }
5374
5375exit:
5376 qla83xx_idc_unlock(vha, 0);
5377
5378 ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__);
5379
5380 return rval;
5381}
5382
81178772
SK		 5383int
5384qla2xxx_mctp_dump(scsi_qla_host_t *vha)
5385{
5386 struct qla_hw_data *ha = vha->hw;
5387 int rval = QLA_FUNCTION_FAILED;
5388
5389 if (!IS_MCTP_CAPABLE(ha)) {
5390 /* This message can be removed from the final version */
5391 ql_log(ql_log_info, vha, 0x506d,
5392 "This board is not MCTP capable\n");
5393 return rval;
5394 }
5395
5396 if (!ha->mctp_dump) {
5397 ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev,
5398 MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL);
5399
5400 if (!ha->mctp_dump) {
5401 ql_log(ql_log_warn, vha, 0x506e,
5402 "Failed to allocate memory for mctp dump\n");
5403 return rval;
5404 }
5405 }
5406
5407#define MCTP_DUMP_STR_ADDR 0x00000000
5408 rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma,
5409 MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4);
5410 if (rval != QLA_SUCCESS) {
5411 ql_log(ql_log_warn, vha, 0x506f,
5412 "Failed to capture mctp dump\n");
5413 } else {
5414 ql_log(ql_log_info, vha, 0x5070,
5415 "Mctp dump capture for host (%ld/%p).\n",
5416 vha->host_no, ha->mctp_dump);
5417 ha->mctp_dumped = 1;
5418 }
5419
409ee0fe 5420 if (!ha->flags.nic_core_reset_hdlr_active && !ha->portnum) {
81178772
SK		 5421 ha->flags.nic_core_reset_hdlr_active = 1;
5422 rval = qla83xx_restart_nic_firmware(vha);
5423 if (rval)
5424 /* NIC Core reset failed. */
5425 ql_log(ql_log_warn, vha, 0x5071,
5426 "Failed to restart nic firmware\n");
5427 else
5428 ql_dbg(ql_dbg_p3p, vha, 0xb084,
5429 "Restarted NIC firmware successfully.\n");
5430 ha->flags.nic_core_reset_hdlr_active = 0;
5431 }
5432
5433 return rval;
5434
5435}
5436
579d12b5 5437/*
8fcd6b8b 5438* qla2x00_quiesce_io
579d12b5
SK		 5439* Description: This function will block the new I/Os
5440* Its not aborting any I/Os as context
5441* is not destroyed during quiescence
5442* Arguments: scsi_qla_host_t
5443* return : void
5444*/
5445void
8fcd6b8b 5446qla2x00_quiesce_io(scsi_qla_host_t *vha)
579d12b5
SK		 5447{
5448 struct qla_hw_data *ha = vha->hw;
5449 struct scsi_qla_host *vp;
5450
8fcd6b8b
CD		 5451 ql_dbg(ql_dbg_dpc, vha, 0x401d,
5452 "Quiescing I/O - ha=%p.\n", ha);
579d12b5
SK		 5453
5454 atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME);
5455 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
5456 atomic_set(&vha->loop_state, LOOP_DOWN);
5457 qla2x00_mark_all_devices_lost(vha, 0);
5458 list_for_each_entry(vp, &ha->vp_list, list)
8fcd6b8b 5459 qla2x00_mark_all_devices_lost(vp, 0);
579d12b5
SK		 5460 } else {
5461 if (!atomic_read(&vha->loop_down_timer))
5462 atomic_set(&vha->loop_down_timer,
5463 LOOP_DOWN_TIME);
5464 }
5465 /* Wait for pending cmds to complete */
5466 qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST);
5467}
5468
a9083016
GM		 5469void
5470qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
5471{
5472 struct qla_hw_data *ha = vha->hw;
579d12b5 5473 struct scsi_qla_host *vp;
feafb7b1 5474 unsigned long flags;
6aef87be 5475 fc_port_t *fcport;
a9083016 5476
e46ef004
SK		 5477 /* For ISP82XX, driver waits for completion of the commands.
5478 * online flag should be set.
5479 */
7ec0effd 5480 if (!(IS_P3P_TYPE(ha)))
e46ef004 5481 vha->flags.online = 0;
a9083016
GM		 5482 ha->flags.chip_reset_done = 0;
5483 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2be21fa2 5484 vha->qla_stats.total_isp_aborts++;
a9083016 5485
7c3df132
SK		 5486 ql_log(ql_log_info, vha, 0x00af,
5487 "Performing ISP error recovery - ha=%p.\n", ha);
a9083016 5488
e46ef004
SK		 5489 /* For ISP82XX, reset_chip is just disabling interrupts.
5490 * Driver waits for the completion of the commands.
5491 * the interrupts need to be enabled.
5492 */
7ec0effd 5493 if (!(IS_P3P_TYPE(ha)))
a9083016
GM		 5494 ha->isp_ops->reset_chip(vha);
5495
726b8548
QT		 5496 ha->chip_reset++;
5497
a9083016
GM		 5498 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
5499 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
5500 atomic_set(&vha->loop_state, LOOP_DOWN);
5501 qla2x00_mark_all_devices_lost(vha, 0);
feafb7b1
AE		 5502
5503 spin_lock_irqsave(&ha->vport_slock, flags);
579d12b5 5504 list_for_each_entry(vp, &ha->vp_list, list) {
feafb7b1
AE		 5505 atomic_inc(&vp->vref_count);
5506 spin_unlock_irqrestore(&ha->vport_slock, flags);
5507
a9083016 5508 qla2x00_mark_all_devices_lost(vp, 0);
feafb7b1
AE		 5509
5510 spin_lock_irqsave(&ha->vport_slock, flags);
5511 atomic_dec(&vp->vref_count);
5512 }
5513 spin_unlock_irqrestore(&ha->vport_slock, flags);
a9083016
GM		 5514 } else {
5515 if (!atomic_read(&vha->loop_down_timer))
5516 atomic_set(&vha->loop_down_timer,
5517 LOOP_DOWN_TIME);
5518 }
5519
6aef87be
AV		 5520 /* Clear all async request states across all VPs. */
5521 list_for_each_entry(fcport, &vha->vp_fcports, list)
5522 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
5523 spin_lock_irqsave(&ha->vport_slock, flags);
5524 list_for_each_entry(vp, &ha->vp_list, list) {
5525 atomic_inc(&vp->vref_count);
5526 spin_unlock_irqrestore(&ha->vport_slock, flags);
5527
5528 list_for_each_entry(fcport, &vp->vp_fcports, list)
5529 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
5530
5531 spin_lock_irqsave(&ha->vport_slock, flags);
5532 atomic_dec(&vp->vref_count);
5533 }
5534 spin_unlock_irqrestore(&ha->vport_slock, flags);
5535
bddd2d65
LC		 5536 if (!ha->flags.eeh_busy) {
5537 /* Make sure for ISP 82XX IO DMA is complete */
7ec0effd 5538 if (IS_P3P_TYPE(ha)) {
7190575f 5539 qla82xx_chip_reset_cleanup(vha);
7c3df132
SK		 5540 ql_log(ql_log_info, vha, 0x00b4,
5541 "Done chip reset cleanup.\n");
a9083016 5542
e46ef004
SK		 5543 /* Done waiting for pending commands.
5544 * Reset the online flag.
5545 */
5546 vha->flags.online = 0;
4d78c973 5547 }
a9083016 5548
bddd2d65
LC		 5549 /* Requeue all commands in outstanding command list. */
5550 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
5551 }
b6a029e1
AE		 5552 /* memory barrier */
5553 wmb();
a9083016
GM		 5554}
5555
1da177e4
LT		 5556/*
5557* qla2x00_abort_isp
5558* Resets ISP and aborts all outstanding commands.
5559*
5560* Input:
5561* ha = adapter block pointer.
5562*
5563* Returns:
5564* 0 = success
5565*/
5566int
e315cd28 5567qla2x00_abort_isp(scsi_qla_host_t *vha)
1da177e4 5568{
476e8978 5569 int rval;
1da177e4 5570 uint8_t status = 0;
e315cd28
AC		 5571 struct qla_hw_data *ha = vha->hw;
5572 struct scsi_qla_host *vp;
73208dfd 5573 struct req_que *req = ha->req_q_map[0];
feafb7b1 5574 unsigned long flags;
1da177e4 5575
e315cd28 5576 if (vha->flags.online) {
a9083016 5577 qla2x00_abort_isp_cleanup(vha);
1da177e4 5578
a6171297
SV		 5579 if (IS_QLA8031(ha)) {
5580 ql_dbg(ql_dbg_p3p, vha, 0xb05c,
5581 "Clearing fcoe driver presence.\n");
5582 if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS)
5583 ql_dbg(ql_dbg_p3p, vha, 0xb073,
5584 "Error while clearing DRV-Presence.\n");
5585 }
5586
85880801
AV		 5587 if (unlikely(pci_channel_offline(ha->pdev) &&
5588 ha->flags.pci_channel_io_perm_failure)) {
5589 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
5590 status = 0;
5591 return status;
5592 }
5593
73208dfd 5594 ha->isp_ops->get_flash_version(vha, req->ring);
30c47662 5595
e315cd28 5596 ha->isp_ops->nvram_config(vha);
1da177e4 5597
e315cd28
AC		 5598 if (!qla2x00_restart_isp(vha)) {
5599 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4 5600
e315cd28 5601 if (!atomic_read(&vha->loop_down_timer)) {
1da177e4
LT		 5602 /*
5603 * Issue marker command only when we are going
5604 * to start the I/O .
5605 */
e315cd28 5606 vha->marker_needed = 1;
1da177e4
LT		 5607 }
5608
e315cd28 5609 vha->flags.online = 1;
1da177e4 5610
fd34f556 5611 ha->isp_ops->enable_intrs(ha);
1da177e4 5612
fa2a1ce5 5613 ha->isp_abort_cnt = 0;
e315cd28 5614 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
476e8978 5615
6246b8a1
GM		 5616 if (IS_QLA81XX(ha) || IS_QLA8031(ha))
5617 qla2x00_get_fw_version(vha);
df613b96
AV		 5618 if (ha->fce) {
5619 ha->flags.fce_enabled = 1;
5620 memset(ha->fce, 0,
5621 fce_calc_size(ha->fce_bufs));
e315cd28 5622 rval = qla2x00_enable_fce_trace(vha,
df613b96
AV		 5623 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
5624 &ha->fce_bufs);
5625 if (rval) {
7c3df132 5626 ql_log(ql_log_warn, vha, 0x8033,
df613b96
AV		 5627 "Unable to reinitialize FCE "
5628 "(%d).\n", rval);
5629 ha->flags.fce_enabled = 0;
5630 }
5631 }
436a7b11
AV		 5632
5633 if (ha->eft) {
5634 memset(ha->eft, 0, EFT_SIZE);
e315cd28 5635 rval = qla2x00_enable_eft_trace(vha,
436a7b11
AV		 5636 ha->eft_dma, EFT_NUM_BUFFERS);
5637 if (rval) {
7c3df132 5638 ql_log(ql_log_warn, vha, 0x8034,
436a7b11
AV		 5639 "Unable to reinitialize EFT "
5640 "(%d).\n", rval);
5641 }
5642 }
1da177e4 5643 } else { /* failed the ISP abort */
e315cd28
AC		 5644 vha->flags.online = 1;
5645 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
1da177e4 5646 if (ha->isp_abort_cnt == 0) {
7c3df132
SK		 5647 ql_log(ql_log_fatal, vha, 0x8035,
5648 "ISP error recover failed - "
5649 "board disabled.\n");
fa2a1ce5 5650 /*
1da177e4
LT		 5651 * The next call disables the board
5652 * completely.
5653 */
e315cd28
AC		 5654 ha->isp_ops->reset_adapter(vha);
5655 vha->flags.online = 0;
1da177e4 5656 clear_bit(ISP_ABORT_RETRY,
e315cd28 5657 &vha->dpc_flags);
1da177e4
LT		 5658 status = 0;
5659 } else { /* schedule another ISP abort */
5660 ha->isp_abort_cnt--;
7c3df132
SK		 5661 ql_dbg(ql_dbg_taskm, vha, 0x8020,
5662 "ISP abort - retry remaining %d.\n",
5663 ha->isp_abort_cnt);
1da177e4
LT		 5664 status = 1;
5665 }
5666 } else {
5667 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
7c3df132
SK		 5668 ql_dbg(ql_dbg_taskm, vha, 0x8021,
5669 "ISP error recovery - retrying (%d) "
5670 "more times.\n", ha->isp_abort_cnt);
e315cd28 5671 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
1da177e4
LT		 5672 status = 1;
5673 }
5674 }
fa2a1ce5 5675
1da177e4
LT		 5676 }
5677
e315cd28 5678 if (!status) {
7c3df132 5679 ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__);
feafb7b1
AE		 5680
5681 spin_lock_irqsave(&ha->vport_slock, flags);
5682 list_for_each_entry(vp, &ha->vp_list, list) {
5683 if (vp->vp_idx) {
5684 atomic_inc(&vp->vref_count);
5685 spin_unlock_irqrestore(&ha->vport_slock, flags);
5686
e315cd28 5687 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 5688
5689 spin_lock_irqsave(&ha->vport_slock, flags);
5690 atomic_dec(&vp->vref_count);
5691 }
e315cd28 5692 }
feafb7b1
AE		 5693 spin_unlock_irqrestore(&ha->vport_slock, flags);
5694
7d613ac6
SV		 5695 if (IS_QLA8031(ha)) {
5696 ql_dbg(ql_dbg_p3p, vha, 0xb05d,
5697 "Setting back fcoe driver presence.\n");
5698 if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS)
5699 ql_dbg(ql_dbg_p3p, vha, 0xb074,
5700 "Error while setting DRV-Presence.\n");
5701 }
e315cd28 5702 } else {
d8424f68
JP		 5703 ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n",
5704 __func__);
1da177e4
LT		 5705 }
5706
5707 return(status);
5708}
5709
5710/*
5711* qla2x00_restart_isp
5712* restarts the ISP after a reset
5713*
5714* Input:
5715* ha = adapter block pointer.
5716*
5717* Returns:
5718* 0 = success
5719*/
5720static int
e315cd28 5721qla2x00_restart_isp(scsi_qla_host_t *vha)
1da177e4 5722{
c6b2fca8 5723 int status = 0;
e315cd28 5724 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 5725 struct req_que *req = ha->req_q_map[0];
5726 struct rsp_que *rsp = ha->rsp_q_map[0];
1da177e4
LT		 5727
5728 /* If firmware needs to be loaded */
e315cd28
AC		 5729 if (qla2x00_isp_firmware(vha)) {
5730 vha->flags.online = 0;
5731 status = ha->isp_ops->chip_diag(vha);
5732 if (!status)
5733 status = qla2x00_setup_chip(vha);
1da177e4
LT		 5734 }
5735
e315cd28
AC		 5736 if (!status && !(status = qla2x00_init_rings(vha))) {
5737 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
2533cf67 5738 ha->flags.chip_reset_done = 1;
7108b76e 5739
73208dfd
AC		 5740 /* Initialize the queues in use */
5741 qla25xx_init_queues(ha);
5742
e315cd28
AC		 5743 status = qla2x00_fw_ready(vha);
5744 if (!status) {
0107109e 5745 /* Issue a marker after FW becomes ready. */
73208dfd 5746 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
7108b76e 5747 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4
LT		 5748 }
5749
5750 /* if no cable then assume it's good */
e315cd28 5751 if ((vha->device_flags & DFLG_NO_CABLE))
1da177e4 5752 status = 0;
1da177e4
LT		 5753 }
5754 return (status);
5755}
5756
73208dfd
AC		 5757static int
5758qla25xx_init_queues(struct qla_hw_data *ha)
5759{
5760 struct rsp_que *rsp = NULL;
5761 struct req_que *req = NULL;
5762 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
5763 int ret = -1;
5764 int i;
5765
2afa19a9 5766 for (i = 1; i < ha->max_rsp_queues; i++) {
73208dfd 5767 rsp = ha->rsp_q_map[i];
cb43285f 5768 if (rsp && test_bit(i, ha->rsp_qid_map)) {
73208dfd 5769 rsp->options &= ~BIT_0;
618a7523 5770 ret = qla25xx_init_rsp_que(base_vha, rsp);
73208dfd 5771 if (ret != QLA_SUCCESS)
7c3df132
SK		 5772 ql_dbg(ql_dbg_init, base_vha, 0x00ff,
5773 "%s Rsp que: %d init failed.\n",
5774 __func__, rsp->id);
73208dfd 5775 else
7c3df132
SK		 5776 ql_dbg(ql_dbg_init, base_vha, 0x0100,
5777 "%s Rsp que: %d inited.\n",
5778 __func__, rsp->id);
73208dfd 5779 }
2afa19a9
AC		 5780 }
5781 for (i = 1; i < ha->max_req_queues; i++) {
73208dfd 5782 req = ha->req_q_map[i];
cb43285f
QT		 5783 if (req && test_bit(i, ha->req_qid_map)) {
5784 /* Clear outstanding commands array. */
73208dfd 5785 req->options &= ~BIT_0;
618a7523 5786 ret = qla25xx_init_req_que(base_vha, req);
73208dfd 5787 if (ret != QLA_SUCCESS)
7c3df132
SK		 5788 ql_dbg(ql_dbg_init, base_vha, 0x0101,
5789 "%s Req que: %d init failed.\n",
5790 __func__, req->id);
73208dfd 5791 else
7c3df132
SK		 5792 ql_dbg(ql_dbg_init, base_vha, 0x0102,
5793 "%s Req que: %d inited.\n",
5794 __func__, req->id);
73208dfd
AC		 5795 }
5796 }
5797 return ret;
5798}
5799
1da177e4
LT		 5800/*
5801* qla2x00_reset_adapter
5802* Reset adapter.
5803*
5804* Input:
5805* ha = adapter block pointer.
5806*/
abbd8870 5807void
e315cd28 5808qla2x00_reset_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 5809{
5810 unsigned long flags = 0;
e315cd28 5811 struct qla_hw_data *ha = vha->hw;
3d71644c 5812 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 5813
e315cd28 5814 vha->flags.online = 0;
fd34f556 5815 ha->isp_ops->disable_intrs(ha);
1da177e4 5816
1da177e4
LT		 5817 spin_lock_irqsave(&ha->hardware_lock, flags);
5818 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
5819 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
5820 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
5821 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
5822 spin_unlock_irqrestore(&ha->hardware_lock, flags);
5823}
0107109e
AV		 5824
5825void
e315cd28 5826qla24xx_reset_adapter(scsi_qla_host_t *vha)
0107109e
AV		 5827{
5828 unsigned long flags = 0;
e315cd28 5829 struct qla_hw_data *ha = vha->hw;
0107109e
AV		 5830 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
5831
7ec0effd 5832 if (IS_P3P_TYPE(ha))
a9083016
GM		 5833 return;
5834
e315cd28 5835 vha->flags.online = 0;
fd34f556 5836 ha->isp_ops->disable_intrs(ha);
0107109e
AV		 5837
5838 spin_lock_irqsave(&ha->hardware_lock, flags);
5839 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
5840 RD_REG_DWORD(&reg->hccr);
5841 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
5842 RD_REG_DWORD(&reg->hccr);
5843 spin_unlock_irqrestore(&ha->hardware_lock, flags);
09ff36d3
AV		 5844
5845 if (IS_NOPOLLING_TYPE(ha))
5846 ha->isp_ops->enable_intrs(ha);
0107109e
AV		 5847}
5848
4e08df3f
DM		 5849/* On sparc systems, obtain port and node WWN from firmware
5850 * properties.
5851 */
e315cd28
AC		 5852static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha,
5853 struct nvram_24xx *nv)
4e08df3f
DM		 5854{
5855#ifdef CONFIG_SPARC
e315cd28 5856 struct qla_hw_data *ha = vha->hw;
4e08df3f 5857 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 5858 struct device_node *dp = pci_device_to_OF_node(pdev);
5859 const u8 *val;
4e08df3f
DM		 5860 int len;
5861
5862 val = of_get_property(dp, "port-wwn", &len);
5863 if (val && len >= WWN_SIZE)
5864 memcpy(nv->port_name, val, WWN_SIZE);
5865
5866 val = of_get_property(dp, "node-wwn", &len);
5867 if (val && len >= WWN_SIZE)
5868 memcpy(nv->node_name, val, WWN_SIZE);
5869#endif
5870}
5871
0107109e 5872int
e315cd28 5873qla24xx_nvram_config(scsi_qla_host_t *vha)
0107109e 5874{
4e08df3f 5875 int rval;
0107109e
AV		 5876 struct init_cb_24xx *icb;
5877 struct nvram_24xx *nv;
5878 uint32_t *dptr;
5879 uint8_t *dptr1, *dptr2;
5880 uint32_t chksum;
5881 uint16_t cnt;
e315cd28 5882 struct qla_hw_data *ha = vha->hw;
0107109e 5883
4e08df3f 5884 rval = QLA_SUCCESS;
0107109e 5885 icb = (struct init_cb_24xx *)ha->init_cb;
281afe19 5886 nv = ha->nvram;
0107109e
AV		 5887
5888 /* Determine NVRAM starting address. */
f73cb695 5889 if (ha->port_no == 0) {
e5b68a61
AC		 5890 ha->nvram_base = FA_NVRAM_FUNC0_ADDR;
5891 ha->vpd_base = FA_NVRAM_VPD0_ADDR;
5892 } else {
0107109e 5893 ha->nvram_base = FA_NVRAM_FUNC1_ADDR;
6f641790
AV		 5894 ha->vpd_base = FA_NVRAM_VPD1_ADDR;
5895 }
f73cb695 5896
e5b68a61
AC		 5897 ha->nvram_size = sizeof(struct nvram_24xx);
5898 ha->vpd_size = FA_NVRAM_VPD_SIZE;
0107109e 5899
281afe19
SJ		 5900 /* Get VPD data into cache */
5901 ha->vpd = ha->nvram + VPD_OFFSET;
e315cd28 5902 ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd,
281afe19
SJ		 5903 ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
5904
5905 /* Get NVRAM data into cache and calculate checksum. */
0107109e 5906 dptr = (uint32_t *)nv;
e315cd28 5907 ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base,
0107109e 5908 ha->nvram_size);
da08ef5c
JC		 5909 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++)
5910 chksum += le32_to_cpu(*dptr);
0107109e 5911
7c3df132
SK		 5912 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
5913 "Contents of NVRAM\n");
5914 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
5915 (uint8_t *)nv, ha->nvram_size);
0107109e
AV		 5916
5917 /* Bad NVRAM data, set defaults parameters. */
5918 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
5919 || nv->id[3] != ' ' ||
ad950360 5920 nv->nvram_version < cpu_to_le16(ICB_VERSION)) {
0107109e 5921 /* Reset NVRAM data. */
7c3df132 5922 ql_log(ql_log_warn, vha, 0x006b,
9e336520 5923 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132
SK		 5924 "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version);
5925 ql_log(ql_log_warn, vha, 0x006c,
5926 "Falling back to functioning (yet invalid -- WWPN) "
5927 "defaults.\n");
4e08df3f
DM		 5928
5929 /*
5930 * Set default initialization control block.
5931 */
5932 memset(nv, 0, ha->nvram_size);
ad950360
BVA		 5933 nv->nvram_version = cpu_to_le16(ICB_VERSION);
5934 nv->version = cpu_to_le16(ICB_VERSION);
98aee70d 5935 nv->frame_payload_size = 2048;
ad950360
BVA		 5936 nv->execution_throttle = cpu_to_le16(0xFFFF);
5937 nv->exchange_count = cpu_to_le16(0);
5938 nv->hard_address = cpu_to_le16(124);
4e08df3f 5939 nv->port_name[0] = 0x21;
f73cb695 5940 nv->port_name[1] = 0x00 + ha->port_no + 1;
4e08df3f
DM		 5941 nv->port_name[2] = 0x00;
5942 nv->port_name[3] = 0xe0;
5943 nv->port_name[4] = 0x8b;
5944 nv->port_name[5] = 0x1c;
5945 nv->port_name[6] = 0x55;
5946 nv->port_name[7] = 0x86;
5947 nv->node_name[0] = 0x20;
5948 nv->node_name[1] = 0x00;
5949 nv->node_name[2] = 0x00;
5950 nv->node_name[3] = 0xe0;
5951 nv->node_name[4] = 0x8b;
5952 nv->node_name[5] = 0x1c;
5953 nv->node_name[6] = 0x55;
5954 nv->node_name[7] = 0x86;
e315cd28 5955 qla24xx_nvram_wwn_from_ofw(vha, nv);
ad950360
BVA		 5956 nv->login_retry_count = cpu_to_le16(8);
5957 nv->interrupt_delay_timer = cpu_to_le16(0);
5958 nv->login_timeout = cpu_to_le16(0);
4e08df3f 5959 nv->firmware_options_1 =
ad950360
BVA		 5960 cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
5961 nv->firmware_options_2 = cpu_to_le32(2 << 4);
5962 nv->firmware_options_2 |= cpu_to_le32(BIT_12);
5963 nv->firmware_options_3 = cpu_to_le32(2 << 13);
5964 nv->host_p = cpu_to_le32(BIT_11|BIT_10);
5965 nv->efi_parameters = cpu_to_le32(0);
4e08df3f 5966 nv->reset_delay = 5;
ad950360
BVA		 5967 nv->max_luns_per_target = cpu_to_le16(128);
5968 nv->port_down_retry_count = cpu_to_le16(30);
5969 nv->link_down_timeout = cpu_to_le16(30);
4e08df3f
DM		 5970
5971 rval = 1;
0107109e
AV		 5972 }
5973
726b8548 5974 if (qla_tgt_mode_enabled(vha)) {
2d70c103 5975 /* Don't enable full login after initial LIP */
ad950360 5976 nv->firmware_options_1 &= cpu_to_le32(~BIT_13);
2d70c103 5977 /* Don't enable LIP full login for initiator */
ad950360 5978 nv->host_p &= cpu_to_le32(~BIT_10);
2d70c103
NB		 5979 }
5980
5981 qlt_24xx_config_nvram_stage1(vha, nv);
5982
0107109e 5983 /* Reset Initialization control block */
e315cd28 5984 memset(icb, 0, ha->init_cb_size);
0107109e
AV		 5985
5986 /* Copy 1st segment. */
5987 dptr1 = (uint8_t *)icb;
5988 dptr2 = (uint8_t *)&nv->version;
5989 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
5990 while (cnt--)
5991 *dptr1++ = *dptr2++;
5992
5993 icb->login_retry_count = nv->login_retry_count;
3ea66e28 5994 icb->link_down_on_nos = nv->link_down_on_nos;
0107109e
AV		 5995
5996 /* Copy 2nd segment. */
5997 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
5998 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
5999 cnt = (uint8_t *)&icb->reserved_3 -
6000 (uint8_t *)&icb->interrupt_delay_timer;
6001 while (cnt--)
6002 *dptr1++ = *dptr2++;
6003
6004 /*
6005 * Setup driver NVRAM options.
6006 */
e315cd28 6007 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
9bb9fcf2 6008 "QLA2462");
0107109e 6009
2d70c103
NB		 6010 qlt_24xx_config_nvram_stage2(vha, icb);
6011
ad950360 6012 if (nv->host_p & cpu_to_le32(BIT_15)) {
2d70c103 6013 /* Use alternate WWN? */
5341e868
AV		 6014 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
6015 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
6016 }
6017
0107109e 6018 /* Prepare nodename */
ad950360 6019 if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) {
0107109e
AV		 6020 /*
6021 * Firmware will apply the following mask if the nodename was
6022 * not provided.
6023 */
6024 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
6025 icb->node_name[0] &= 0xF0;
6026 }
6027
6028 /* Set host adapter parameters. */
6029 ha->flags.disable_risc_code_load = 0;
0c8c39af
AV		 6030 ha->flags.enable_lip_reset = 0;
6031 ha->flags.enable_lip_full_login =
6032 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
6033 ha->flags.enable_target_reset =
6034 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
0107109e 6035 ha->flags.enable_led_scheme = 0;
d4c760c2 6036 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
0107109e 6037
fd0e7e4d
AV		 6038 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
6039 (BIT_6 | BIT_5 | BIT_4)) >> 4;
0107109e
AV		 6040
6041 memcpy(ha->fw_seriallink_options24, nv->seriallink_options,
6042 sizeof(ha->fw_seriallink_options24));
6043
6044 /* save HBA serial number */
6045 ha->serial0 = icb->port_name[5];
6046 ha->serial1 = icb->port_name[6];
6047 ha->serial2 = icb->port_name[7];
e315cd28
AC		 6048 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
6049 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
0107109e 6050
ad950360 6051 icb->execution_throttle = cpu_to_le16(0xFFFF);
bc8fb3cb 6052
0107109e
AV		 6053 ha->retry_count = le16_to_cpu(nv->login_retry_count);
6054
6055 /* Set minimum login_timeout to 4 seconds. */
6056 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
6057 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
6058 if (le16_to_cpu(nv->login_timeout) < 4)
ad950360 6059 nv->login_timeout = cpu_to_le16(4);
0107109e 6060 ha->login_timeout = le16_to_cpu(nv->login_timeout);
0107109e 6061
00a537b8
AV		 6062 /* Set minimum RATOV to 100 tenths of a second. */
6063 ha->r_a_tov = 100;
0107109e
AV		 6064
6065 ha->loop_reset_delay = nv->reset_delay;
6066
6067 /* Link Down Timeout = 0:
6068 *
6069 * When Port Down timer expires we will start returning
6070 * I/O's to OS with "DID_NO_CONNECT".
6071 *
6072 * Link Down Timeout != 0:
6073 *
6074 * The driver waits for the link to come up after link down
6075 * before returning I/Os to OS with "DID_NO_CONNECT".
6076 */
6077 if (le16_to_cpu(nv->link_down_timeout) == 0) {
6078 ha->loop_down_abort_time =
6079 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
6080 } else {
6081 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
6082 ha->loop_down_abort_time =
6083 (LOOP_DOWN_TIME - ha->link_down_timeout);
6084 }
6085
6086 /* Need enough time to try and get the port back. */
6087 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
6088 if (qlport_down_retry)
6089 ha->port_down_retry_count = qlport_down_retry;
6090
6091 /* Set login_retry_count */
6092 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
6093 if (ha->port_down_retry_count ==
6094 le16_to_cpu(nv->port_down_retry_count) &&
6095 ha->port_down_retry_count > 3)
6096 ha->login_retry_count = ha->port_down_retry_count;
6097 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
6098 ha->login_retry_count = ha->port_down_retry_count;
6099 if (ql2xloginretrycount)
6100 ha->login_retry_count = ql2xloginretrycount;
6101
4fdfefe5 6102 /* Enable ZIO. */
e315cd28 6103 if (!vha->flags.init_done) {
4fdfefe5
AV		 6104 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
6105 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
6106 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
6107 le16_to_cpu(icb->interrupt_delay_timer): 2;
6108 }
ad950360 6109 icb->firmware_options_2 &= cpu_to_le32(
4fdfefe5 6110 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
e315cd28 6111 vha->flags.process_response_queue = 0;
4fdfefe5 6112 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d
AV		 6113 ha->zio_mode = QLA_ZIO_MODE_6;
6114
7c3df132 6115 ql_log(ql_log_info, vha, 0x006f,
4fdfefe5
AV		 6116 "ZIO mode %d enabled; timer delay (%d us).\n",
6117 ha->zio_mode, ha->zio_timer * 100);
6118
6119 icb->firmware_options_2 |= cpu_to_le32(
6120 (uint32_t)ha->zio_mode);
6121 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
e315cd28 6122 vha->flags.process_response_queue = 1;
4fdfefe5
AV		 6123 }
6124
4e08df3f 6125 if (rval) {
7c3df132
SK		 6126 ql_log(ql_log_warn, vha, 0x0070,
6127 "NVRAM configuration failed.\n");
4e08df3f
DM		 6128 }
6129 return (rval);
0107109e
AV		 6130}
6131
4243c115
SC		 6132uint8_t qla27xx_find_valid_image(struct scsi_qla_host *vha)
6133{
6134 struct qla27xx_image_status pri_image_status, sec_image_status;
6135 uint8_t valid_pri_image, valid_sec_image;
6136 uint32_t *wptr;
6137 uint32_t cnt, chksum, size;
6138 struct qla_hw_data *ha = vha->hw;
6139
6140 valid_pri_image = valid_sec_image = 1;
6141 ha->active_image = 0;
6142 size = sizeof(struct qla27xx_image_status) / sizeof(uint32_t);
6143
6144 if (!ha->flt_region_img_status_pri) {
6145 valid_pri_image = 0;
6146 goto check_sec_image;
6147 }
6148
6149 qla24xx_read_flash_data(vha, (uint32_t *)(&pri_image_status),
6150 ha->flt_region_img_status_pri, size);
6151
6152 if (pri_image_status.signature != QLA27XX_IMG_STATUS_SIGN) {
6153 ql_dbg(ql_dbg_init, vha, 0x018b,
6154 "Primary image signature (0x%x) not valid\n",
6155 pri_image_status.signature);
6156 valid_pri_image = 0;
6157 goto check_sec_image;
6158 }
6159
6160 wptr = (uint32_t *)(&pri_image_status);
6161 cnt = size;
6162
da08ef5c
JC		 6163 for (chksum = 0; cnt--; wptr++)
6164 chksum += le32_to_cpu(*wptr);
41dc529a 6165
4243c115
SC		 6166 if (chksum) {
6167 ql_dbg(ql_dbg_init, vha, 0x018c,
6168 "Checksum validation failed for primary image (0x%x)\n",
6169 chksum);
6170 valid_pri_image = 0;
6171 }
6172
6173check_sec_image:
6174 if (!ha->flt_region_img_status_sec) {
6175 valid_sec_image = 0;
6176 goto check_valid_image;
6177 }
6178
6179 qla24xx_read_flash_data(vha, (uint32_t *)(&sec_image_status),
6180 ha->flt_region_img_status_sec, size);
6181
6182 if (sec_image_status.signature != QLA27XX_IMG_STATUS_SIGN) {
6183 ql_dbg(ql_dbg_init, vha, 0x018d,
6184 "Secondary image signature(0x%x) not valid\n",
6185 sec_image_status.signature);
6186 valid_sec_image = 0;
6187 goto check_valid_image;
6188 }
6189
6190 wptr = (uint32_t *)(&sec_image_status);
6191 cnt = size;
da08ef5c
JC		 6192 for (chksum = 0; cnt--; wptr++)
6193 chksum += le32_to_cpu(*wptr);
4243c115
SC		 6194 if (chksum) {
6195 ql_dbg(ql_dbg_init, vha, 0x018e,
6196 "Checksum validation failed for secondary image (0x%x)\n",
6197 chksum);
6198 valid_sec_image = 0;
6199 }
6200
6201check_valid_image:
6202 if (valid_pri_image && (pri_image_status.image_status_mask & 0x1))
6203 ha->active_image = QLA27XX_PRIMARY_IMAGE;
6204 if (valid_sec_image && (sec_image_status.image_status_mask & 0x1)) {
6205 if (!ha->active_image ||
6206 pri_image_status.generation_number <
6207 sec_image_status.generation_number)
6208 ha->active_image = QLA27XX_SECONDARY_IMAGE;
6209 }
6210
6211 ql_dbg(ql_dbg_init, vha, 0x018f, "%s image\n",
6212 ha->active_image == 0 ? "default bootld and fw" :
6213 ha->active_image == 1 ? "primary" :
6214 ha->active_image == 2 ? "secondary" :
6215 "Invalid");
6216
6217 return ha->active_image;
6218}
6219
413975a0 6220static int
cbc8eb67
AV		 6221qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
6222 uint32_t faddr)
d1c61909 6223{
73208dfd 6224 int rval = QLA_SUCCESS;
d1c61909 6225 int segments, fragment;
d1c61909
AV		 6226 uint32_t *dcode, dlen;
6227 uint32_t risc_addr;
6228 uint32_t risc_size;
6229 uint32_t i;
e315cd28 6230 struct qla_hw_data *ha = vha->hw;
73208dfd 6231 struct req_que *req = ha->req_q_map[0];
eaac30be 6232
7c3df132 6233 ql_dbg(ql_dbg_init, vha, 0x008b,
cfb0919c 6234 "FW: Loading firmware from flash (%x).\n", faddr);
eaac30be 6235
d1c61909
AV		 6236 rval = QLA_SUCCESS;
6237
6238 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 6239 dcode = (uint32_t *)req->ring;
d1c61909
AV		 6240 *srisc_addr = 0;
6241
4243c115
SC		 6242 if (IS_QLA27XX(ha) &&
6243 qla27xx_find_valid_image(vha) == QLA27XX_SECONDARY_IMAGE)
6244 faddr = ha->flt_region_fw_sec;
6245
d1c61909 6246 /* Validate firmware image by checking version. */
e315cd28 6247 qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
d1c61909
AV		 6248 for (i = 0; i < 4; i++)
6249 dcode[i] = be32_to_cpu(dcode[i]);
6250 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
6251 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
6252 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
6253 dcode[3] == 0)) {
7c3df132
SK		 6254 ql_log(ql_log_fatal, vha, 0x008c,
6255 "Unable to verify the integrity of flash firmware "
6256 "image.\n");
6257 ql_log(ql_log_fatal, vha, 0x008d,
6258 "Firmware data: %08x %08x %08x %08x.\n",
6259 dcode[0], dcode[1], dcode[2], dcode[3]);
d1c61909
AV		 6260
6261 return QLA_FUNCTION_FAILED;
6262 }
6263
6264 while (segments && rval == QLA_SUCCESS) {
6265 /* Read segment's load information. */
e315cd28 6266 qla24xx_read_flash_data(vha, dcode, faddr, 4);
d1c61909
AV		 6267
6268 risc_addr = be32_to_cpu(dcode[2]);
6269 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
6270 risc_size = be32_to_cpu(dcode[3]);
6271
6272 fragment = 0;
6273 while (risc_size > 0 && rval == QLA_SUCCESS) {
6274 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
6275 if (dlen > risc_size)
6276 dlen = risc_size;
6277
7c3df132
SK		 6278 ql_dbg(ql_dbg_init, vha, 0x008e,
6279 "Loading risc segment@ risc addr %x "
6280 "number of dwords 0x%x offset 0x%x.\n",
6281 risc_addr, dlen, faddr);
d1c61909 6282
e315cd28 6283 qla24xx_read_flash_data(vha, dcode, faddr, dlen);
d1c61909
AV		 6284 for (i = 0; i < dlen; i++)
6285 dcode[i] = swab32(dcode[i]);
6286
73208dfd 6287 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
d1c61909
AV		 6288 dlen);
6289 if (rval) {
7c3df132
SK		 6290 ql_log(ql_log_fatal, vha, 0x008f,
6291 "Failed to load segment %d of firmware.\n",
6292 fragment);
f261f7af 6293 return QLA_FUNCTION_FAILED;
d1c61909
AV		 6294 }
6295
6296 faddr += dlen;
6297 risc_addr += dlen;
6298 risc_size -= dlen;
6299 fragment++;
6300 }
6301
6302 /* Next segment. */
6303 segments--;
6304 }
6305
f73cb695
CD		 6306 if (!IS_QLA27XX(ha))
6307 return rval;
6308
6309 if (ha->fw_dump_template)
6310 vfree(ha->fw_dump_template);
6311 ha->fw_dump_template = NULL;
6312 ha->fw_dump_template_len = 0;
6313
6314 ql_dbg(ql_dbg_init, vha, 0x0161,
6315 "Loading fwdump template from %x\n", faddr);
6316 qla24xx_read_flash_data(vha, dcode, faddr, 7);
6317 risc_size = be32_to_cpu(dcode[2]);
6318 ql_dbg(ql_dbg_init, vha, 0x0162,
6319 "-> array size %x dwords\n", risc_size);
6320 if (risc_size == 0 || risc_size == ~0)
6321 goto default_template;
6322
6323 dlen = (risc_size - 8) * sizeof(*dcode);
6324 ql_dbg(ql_dbg_init, vha, 0x0163,
6325 "-> template allocating %x bytes...\n", dlen);
6326 ha->fw_dump_template = vmalloc(dlen);
6327 if (!ha->fw_dump_template) {
6328 ql_log(ql_log_warn, vha, 0x0164,
6329 "Failed fwdump template allocate %x bytes.\n", risc_size);
6330 goto default_template;
6331 }
6332
6333 faddr += 7;
6334 risc_size -= 8;
6335 dcode = ha->fw_dump_template;
6336 qla24xx_read_flash_data(vha, dcode, faddr, risc_size);
6337 for (i = 0; i < risc_size; i++)
6338 dcode[i] = le32_to_cpu(dcode[i]);
6339
6340 if (!qla27xx_fwdt_template_valid(dcode)) {
6341 ql_log(ql_log_warn, vha, 0x0165,
6342 "Failed fwdump template validate\n");
6343 goto default_template;
6344 }
6345
6346 dlen = qla27xx_fwdt_template_size(dcode);
6347 ql_dbg(ql_dbg_init, vha, 0x0166,
6348 "-> template size %x bytes\n", dlen);
6349 if (dlen > risc_size * sizeof(*dcode)) {
6350 ql_log(ql_log_warn, vha, 0x0167,
97ea702b
CD		 6351 "Failed fwdump template exceeds array by %x bytes\n",
6352 (uint32_t)(dlen - risc_size * sizeof(*dcode)));
f73cb695
CD		 6353 goto default_template;
6354 }
6355 ha->fw_dump_template_len = dlen;
6356 return rval;
6357
6358default_template:
6359 ql_log(ql_log_warn, vha, 0x0168, "Using default fwdump template\n");
6360 if (ha->fw_dump_template)
6361 vfree(ha->fw_dump_template);
6362 ha->fw_dump_template = NULL;
6363 ha->fw_dump_template_len = 0;
6364
6365 dlen = qla27xx_fwdt_template_default_size();
6366 ql_dbg(ql_dbg_init, vha, 0x0169,
6367 "-> template allocating %x bytes...\n", dlen);
6368 ha->fw_dump_template = vmalloc(dlen);
6369 if (!ha->fw_dump_template) {
6370 ql_log(ql_log_warn, vha, 0x016a,
6371 "Failed fwdump template allocate %x bytes.\n", risc_size);
6372 goto failed_template;
6373 }
6374
6375 dcode = ha->fw_dump_template;
6376 risc_size = dlen / sizeof(*dcode);
6377 memcpy(dcode, qla27xx_fwdt_template_default(), dlen);
6378 for (i = 0; i < risc_size; i++)
6379 dcode[i] = be32_to_cpu(dcode[i]);
6380
6381 if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) {
6382 ql_log(ql_log_warn, vha, 0x016b,
6383 "Failed fwdump template validate\n");
6384 goto failed_template;
6385 }
6386
6387 dlen = qla27xx_fwdt_template_size(ha->fw_dump_template);
6388 ql_dbg(ql_dbg_init, vha, 0x016c,
6389 "-> template size %x bytes\n", dlen);
6390 ha->fw_dump_template_len = dlen;
6391 return rval;
6392
6393failed_template:
6394 ql_log(ql_log_warn, vha, 0x016d, "Failed default fwdump template\n");
6395 if (ha->fw_dump_template)
6396 vfree(ha->fw_dump_template);
6397 ha->fw_dump_template = NULL;
6398 ha->fw_dump_template_len = 0;
d1c61909
AV		 6399 return rval;
6400}
6401
e9454a88 6402#define QLA_FW_URL "http://ldriver.qlogic.com/firmware/"
d1c61909 6403
0107109e 6404int
e315cd28 6405qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5433383e
AV		 6406{
6407 int rval;
6408 int i, fragment;
6409 uint16_t *wcode, *fwcode;
6410 uint32_t risc_addr, risc_size, fwclen, wlen, *seg;
6411 struct fw_blob *blob;
e315cd28 6412 struct qla_hw_data *ha = vha->hw;
73208dfd 6413 struct req_que *req = ha->req_q_map[0];
5433383e
AV		 6414
6415 /* Load firmware blob. */
e315cd28 6416 blob = qla2x00_request_firmware(vha);
5433383e 6417 if (!blob) {
7c3df132 6418 ql_log(ql_log_info, vha, 0x0083,
94bcf830 6419 "Firmware image unavailable.\n");
7c3df132
SK		 6420 ql_log(ql_log_info, vha, 0x0084,
6421 "Firmware images can be retrieved from: "QLA_FW_URL ".\n");
5433383e
AV		 6422 return QLA_FUNCTION_FAILED;
6423 }
6424
6425 rval = QLA_SUCCESS;
6426
73208dfd 6427 wcode = (uint16_t *)req->ring;
5433383e
AV		 6428 *srisc_addr = 0;
6429 fwcode = (uint16_t *)blob->fw->data;
6430 fwclen = 0;
6431
6432 /* Validate firmware image by checking version. */
6433 if (blob->fw->size < 8 * sizeof(uint16_t)) {
7c3df132 6434 ql_log(ql_log_fatal, vha, 0x0085,
5b5e0928 6435 "Unable to verify integrity of firmware image (%zd).\n",
5433383e
AV		 6436 blob->fw->size);
6437 goto fail_fw_integrity;
6438 }
6439 for (i = 0; i < 4; i++)
6440 wcode[i] = be16_to_cpu(fwcode[i + 4]);
6441 if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff &&
6442 wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 &&
6443 wcode[2] == 0 && wcode[3] == 0)) {
7c3df132
SK		 6444 ql_log(ql_log_fatal, vha, 0x0086,
6445 "Unable to verify integrity of firmware image.\n");
6446 ql_log(ql_log_fatal, vha, 0x0087,
6447 "Firmware data: %04x %04x %04x %04x.\n",
6448 wcode[0], wcode[1], wcode[2], wcode[3]);
5433383e
AV		 6449 goto fail_fw_integrity;
6450 }
6451
6452 seg = blob->segs;
6453 while (*seg && rval == QLA_SUCCESS) {
6454 risc_addr = *seg;
6455 *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr;
6456 risc_size = be16_to_cpu(fwcode[3]);
6457
6458 /* Validate firmware image size. */
6459 fwclen += risc_size * sizeof(uint16_t);
6460 if (blob->fw->size < fwclen) {
7c3df132 6461 ql_log(ql_log_fatal, vha, 0x0088,
5433383e 6462 "Unable to verify integrity of firmware image "
5b5e0928 6463 "(%zd).\n", blob->fw->size);
5433383e
AV		 6464 goto fail_fw_integrity;
6465 }
6466
6467 fragment = 0;
6468 while (risc_size > 0 && rval == QLA_SUCCESS) {
6469 wlen = (uint16_t)(ha->fw_transfer_size >> 1);
6470 if (wlen > risc_size)
6471 wlen = risc_size;
7c3df132
SK		 6472 ql_dbg(ql_dbg_init, vha, 0x0089,
6473 "Loading risc segment@ risc addr %x number of "
6474 "words 0x%x.\n", risc_addr, wlen);
5433383e
AV		 6475
6476 for (i = 0; i < wlen; i++)
6477 wcode[i] = swab16(fwcode[i]);
6478
73208dfd 6479 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
5433383e
AV		 6480 wlen);
6481 if (rval) {
7c3df132
SK		 6482 ql_log(ql_log_fatal, vha, 0x008a,
6483 "Failed to load segment %d of firmware.\n",
6484 fragment);
5433383e
AV		 6485 break;
6486 }
6487
6488 fwcode += wlen;
6489 risc_addr += wlen;
6490 risc_size -= wlen;
6491 fragment++;
6492 }
6493
6494 /* Next segment. */
6495 seg++;
6496 }
6497 return rval;
6498
6499fail_fw_integrity:
6500 return QLA_FUNCTION_FAILED;
6501}
6502
eaac30be
AV		 6503static int
6504qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
0107109e
AV		 6505{
6506 int rval;
6507 int segments, fragment;
6508 uint32_t *dcode, dlen;
6509 uint32_t risc_addr;
6510 uint32_t risc_size;
6511 uint32_t i;
5433383e 6512 struct fw_blob *blob;
f73cb695
CD		 6513 const uint32_t *fwcode;
6514 uint32_t fwclen;
e315cd28 6515 struct qla_hw_data *ha = vha->hw;
73208dfd 6516 struct req_que *req = ha->req_q_map[0];
0107109e 6517
5433383e 6518 /* Load firmware blob. */
e315cd28 6519 blob = qla2x00_request_firmware(vha);
5433383e 6520 if (!blob) {
7c3df132 6521 ql_log(ql_log_warn, vha, 0x0090,
94bcf830 6522 "Firmware image unavailable.\n");
7c3df132
SK		 6523 ql_log(ql_log_warn, vha, 0x0091,
6524 "Firmware images can be retrieved from: "
6525 QLA_FW_URL ".\n");
d1c61909 6526
eaac30be 6527 return QLA_FUNCTION_FAILED;
0107109e
AV		 6528 }
6529
cfb0919c
CD		 6530 ql_dbg(ql_dbg_init, vha, 0x0092,
6531 "FW: Loading via request-firmware.\n");
eaac30be 6532
0107109e
AV		 6533 rval = QLA_SUCCESS;
6534
6535 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 6536 dcode = (uint32_t *)req->ring;
0107109e 6537 *srisc_addr = 0;
5433383e 6538 fwcode = (uint32_t *)blob->fw->data;
0107109e
AV		 6539 fwclen = 0;
6540
6541 /* Validate firmware image by checking version. */
5433383e 6542 if (blob->fw->size < 8 * sizeof(uint32_t)) {
7c3df132 6543 ql_log(ql_log_fatal, vha, 0x0093,
5b5e0928 6544 "Unable to verify integrity of firmware image (%zd).\n",
5433383e 6545 blob->fw->size);
f73cb695 6546 return QLA_FUNCTION_FAILED;
0107109e
AV		 6547 }
6548 for (i = 0; i < 4; i++)
6549 dcode[i] = be32_to_cpu(fwcode[i + 4]);
6550 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
6551 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
6552 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
6553 dcode[3] == 0)) {
7c3df132 6554 ql_log(ql_log_fatal, vha, 0x0094,
5b5e0928 6555 "Unable to verify integrity of firmware image (%zd).\n",
7c3df132
SK		 6556 blob->fw->size);
6557 ql_log(ql_log_fatal, vha, 0x0095,
6558 "Firmware data: %08x %08x %08x %08x.\n",
6559 dcode[0], dcode[1], dcode[2], dcode[3]);
f73cb695 6560 return QLA_FUNCTION_FAILED;
0107109e
AV		 6561 }
6562
6563 while (segments && rval == QLA_SUCCESS) {
6564 risc_addr = be32_to_cpu(fwcode[2]);
6565 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
6566 risc_size = be32_to_cpu(fwcode[3]);
6567
6568 /* Validate firmware image size. */
6569 fwclen += risc_size * sizeof(uint32_t);
5433383e 6570 if (blob->fw->size < fwclen) {
7c3df132 6571 ql_log(ql_log_fatal, vha, 0x0096,
5433383e 6572 "Unable to verify integrity of firmware image "
5b5e0928 6573 "(%zd).\n", blob->fw->size);
f73cb695 6574 return QLA_FUNCTION_FAILED;
0107109e
AV		 6575 }
6576
6577 fragment = 0;
6578 while (risc_size > 0 && rval == QLA_SUCCESS) {
6579 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
6580 if (dlen > risc_size)
6581 dlen = risc_size;
6582
7c3df132
SK		 6583 ql_dbg(ql_dbg_init, vha, 0x0097,
6584 "Loading risc segment@ risc addr %x "
6585 "number of dwords 0x%x.\n", risc_addr, dlen);
0107109e
AV		 6586
6587 for (i = 0; i < dlen; i++)
6588 dcode[i] = swab32(fwcode[i]);
6589
73208dfd 6590 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
590f98e5 6591 dlen);
0107109e 6592 if (rval) {
7c3df132
SK		 6593 ql_log(ql_log_fatal, vha, 0x0098,
6594 "Failed to load segment %d of firmware.\n",
6595 fragment);
f261f7af 6596 return QLA_FUNCTION_FAILED;
0107109e
AV		 6597 }
6598
6599 fwcode += dlen;
6600 risc_addr += dlen;
6601 risc_size -= dlen;
6602 fragment++;
6603 }
6604
6605 /* Next segment. */
6606 segments--;
6607 }
f73cb695
CD		 6608
6609 if (!IS_QLA27XX(ha))
6610 return rval;
6611
6612 if (ha->fw_dump_template)
6613 vfree(ha->fw_dump_template);
6614 ha->fw_dump_template = NULL;
6615 ha->fw_dump_template_len = 0;
6616
6617 ql_dbg(ql_dbg_init, vha, 0x171,
97ea702b
CD		 6618 "Loading fwdump template from %x\n",
6619 (uint32_t)((void *)fwcode - (void *)blob->fw->data));
f73cb695
CD		 6620 risc_size = be32_to_cpu(fwcode[2]);
6621 ql_dbg(ql_dbg_init, vha, 0x172,
6622 "-> array size %x dwords\n", risc_size);
6623 if (risc_size == 0 || risc_size == ~0)
6624 goto default_template;
6625
6626 dlen = (risc_size - 8) * sizeof(*fwcode);
6627 ql_dbg(ql_dbg_init, vha, 0x0173,
6628 "-> template allocating %x bytes...\n", dlen);
6629 ha->fw_dump_template = vmalloc(dlen);
6630 if (!ha->fw_dump_template) {
6631 ql_log(ql_log_warn, vha, 0x0174,
6632 "Failed fwdump template allocate %x bytes.\n", risc_size);
6633 goto default_template;
6634 }
6635
6636 fwcode += 7;
6637 risc_size -= 8;
6638 dcode = ha->fw_dump_template;
6639 for (i = 0; i < risc_size; i++)
6640 dcode[i] = le32_to_cpu(fwcode[i]);
6641
6642 if (!qla27xx_fwdt_template_valid(dcode)) {
6643 ql_log(ql_log_warn, vha, 0x0175,
6644 "Failed fwdump template validate\n");
6645 goto default_template;
6646 }
6647
6648 dlen = qla27xx_fwdt_template_size(dcode);
6649 ql_dbg(ql_dbg_init, vha, 0x0176,
6650 "-> template size %x bytes\n", dlen);
6651 if (dlen > risc_size * sizeof(*fwcode)) {
6652 ql_log(ql_log_warn, vha, 0x0177,
97ea702b
CD		 6653 "Failed fwdump template exceeds array by %x bytes\n",
6654 (uint32_t)(dlen - risc_size * sizeof(*fwcode)));
f73cb695
CD		 6655 goto default_template;
6656 }
6657 ha->fw_dump_template_len = dlen;
0107109e
AV		 6658 return rval;
6659
f73cb695
CD		 6660default_template:
6661 ql_log(ql_log_warn, vha, 0x0178, "Using default fwdump template\n");
6662 if (ha->fw_dump_template)
6663 vfree(ha->fw_dump_template);
6664 ha->fw_dump_template = NULL;
6665 ha->fw_dump_template_len = 0;
6666
6667 dlen = qla27xx_fwdt_template_default_size();
6668 ql_dbg(ql_dbg_init, vha, 0x0179,
6669 "-> template allocating %x bytes...\n", dlen);
6670 ha->fw_dump_template = vmalloc(dlen);
6671 if (!ha->fw_dump_template) {
6672 ql_log(ql_log_warn, vha, 0x017a,
6673 "Failed fwdump template allocate %x bytes.\n", risc_size);
6674 goto failed_template;
6675 }
6676
6677 dcode = ha->fw_dump_template;
6678 risc_size = dlen / sizeof(*fwcode);
6679 fwcode = qla27xx_fwdt_template_default();
6680 for (i = 0; i < risc_size; i++)
6681 dcode[i] = be32_to_cpu(fwcode[i]);
6682
6683 if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) {
6684 ql_log(ql_log_warn, vha, 0x017b,
6685 "Failed fwdump template validate\n");
6686 goto failed_template;
6687 }
6688
6689 dlen = qla27xx_fwdt_template_size(ha->fw_dump_template);
6690 ql_dbg(ql_dbg_init, vha, 0x017c,
6691 "-> template size %x bytes\n", dlen);
6692 ha->fw_dump_template_len = dlen;
6693 return rval;
6694
6695failed_template:
6696 ql_log(ql_log_warn, vha, 0x017d, "Failed default fwdump template\n");
6697 if (ha->fw_dump_template)
6698 vfree(ha->fw_dump_template);
6699 ha->fw_dump_template = NULL;
6700 ha->fw_dump_template_len = 0;
6701 return rval;
0107109e 6702}
18c6c127 6703
eaac30be
AV		 6704int
6705qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
6706{
6707 int rval;
6708
e337d907
AV		 6709 if (ql2xfwloadbin == 1)
6710 return qla81xx_load_risc(vha, srisc_addr);
6711
eaac30be
AV		 6712 /*
6713 * FW Load priority:
6714 * 1) Firmware via request-firmware interface (.bin file).
6715 * 2) Firmware residing in flash.
6716 */
6717 rval = qla24xx_load_risc_blob(vha, srisc_addr);
6718 if (rval == QLA_SUCCESS)
6719 return rval;
6720
cbc8eb67
AV		 6721 return qla24xx_load_risc_flash(vha, srisc_addr,
6722 vha->hw->flt_region_fw);
eaac30be
AV		 6723}
6724
6725int
6726qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
6727{
6728 int rval;
cbc8eb67 6729 struct qla_hw_data *ha = vha->hw;
eaac30be 6730
e337d907 6731 if (ql2xfwloadbin == 2)
cbc8eb67 6732 goto try_blob_fw;
e337d907 6733
eaac30be
AV		 6734 /*
6735 * FW Load priority:
6736 * 1) Firmware residing in flash.
6737 * 2) Firmware via request-firmware interface (.bin file).
cbc8eb67 6738 * 3) Golden-Firmware residing in flash -- limited operation.
eaac30be 6739 */
cbc8eb67 6740 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
eaac30be
AV		 6741 if (rval == QLA_SUCCESS)
6742 return rval;
6743
cbc8eb67
AV		 6744try_blob_fw:
6745 rval = qla24xx_load_risc_blob(vha, srisc_addr);
6746 if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw)
6747 return rval;
6748
7c3df132
SK		 6749 ql_log(ql_log_info, vha, 0x0099,
6750 "Attempting to fallback to golden firmware.\n");
cbc8eb67
AV		 6751 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
6752 if (rval != QLA_SUCCESS)
6753 return rval;
6754
7c3df132 6755 ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n");
cbc8eb67 6756 ha->flags.running_gold_fw = 1;
cbc8eb67 6757 return rval;
eaac30be
AV		 6758}
6759
18c6c127 6760void
e315cd28 6761qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha)
18c6c127
AV		 6762{
6763 int ret, retries;
e315cd28 6764 struct qla_hw_data *ha = vha->hw;
18c6c127 6765
85880801
AV		 6766 if (ha->flags.pci_channel_io_perm_failure)
6767 return;
e428924c 6768 if (!IS_FWI2_CAPABLE(ha))
18c6c127 6769 return;
75edf81d
AV		 6770 if (!ha->fw_major_version)
6771 return;
18c6c127 6772
e315cd28 6773 ret = qla2x00_stop_firmware(vha);
7c7f1f29 6774 for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&
b469a7cb 6775 ret != QLA_INVALID_COMMAND && retries ; retries--) {
e315cd28
AC		 6776 ha->isp_ops->reset_chip(vha);
6777 if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS)
18c6c127 6778 continue;
e315cd28 6779 if (qla2x00_setup_chip(vha) != QLA_SUCCESS)
18c6c127 6780 continue;
7c3df132
SK		 6781 ql_log(ql_log_info, vha, 0x8015,
6782 "Attempting retry of stop-firmware command.\n");
e315cd28 6783 ret = qla2x00_stop_firmware(vha);
18c6c127
AV		 6784 }
6785}
2c3dfe3f
SJ		 6786
6787int
e315cd28 6788qla24xx_configure_vhba(scsi_qla_host_t *vha)
2c3dfe3f
SJ		 6789{
6790 int rval = QLA_SUCCESS;
0b91d116 6791 int rval2;
2c3dfe3f 6792 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28
AC		 6793 struct qla_hw_data *ha = vha->hw;
6794 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
67c2e93a
AC		 6795 struct req_que *req;
6796 struct rsp_que *rsp;
2c3dfe3f 6797
e315cd28 6798 if (!vha->vp_idx)
2c3dfe3f
SJ		 6799 return -EINVAL;
6800
e315cd28 6801 rval = qla2x00_fw_ready(base_vha);
d7459527
MH		 6802 if (vha->qpair)
6803 req = vha->qpair->req;
67c2e93a 6804 else
d7459527 6805 req = ha->req_q_map[0];
67c2e93a
AC		 6806 rsp = req->rsp;
6807
2c3dfe3f 6808 if (rval == QLA_SUCCESS) {
e315cd28 6809 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
73208dfd 6810 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
2c3dfe3f
SJ		 6811 }
6812
e315cd28 6813 vha->flags.management_server_logged_in = 0;
2c3dfe3f
SJ		 6814
6815 /* Login to SNS first */
0b91d116
CD		 6816 rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb,
6817 BIT_1);
6818 if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
6819 if (rval2 == QLA_MEMORY_ALLOC_FAILED)
6820 ql_dbg(ql_dbg_init, vha, 0x0120,
6821 "Failed SNS login: loop_id=%x, rval2=%d\n",
6822 NPH_SNS, rval2);
6823 else
6824 ql_dbg(ql_dbg_init, vha, 0x0103,
6825 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x "
6826 "mb[2]=%x mb[6]=%x mb[7]=%x.\n",
6827 NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]);
2c3dfe3f
SJ		 6828 return (QLA_FUNCTION_FAILED);
6829 }
6830
e315cd28
AC		 6831 atomic_set(&vha->loop_down_timer, 0);
6832 atomic_set(&vha->loop_state, LOOP_UP);
6833 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
6834 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
6835 rval = qla2x00_loop_resync(base_vha);
2c3dfe3f
SJ		 6836
6837 return rval;
6838}
4d4df193
HK		 6839
6840/* 84XX Support **************************************************************/
6841
6842static LIST_HEAD(qla_cs84xx_list);
6843static DEFINE_MUTEX(qla_cs84xx_mutex);
6844
6845static struct qla_chip_state_84xx *
e315cd28 6846qla84xx_get_chip(struct scsi_qla_host *vha)
4d4df193
HK		 6847{
6848 struct qla_chip_state_84xx *cs84xx;
e315cd28 6849 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 6850
6851 mutex_lock(&qla_cs84xx_mutex);
6852
6853 /* Find any shared 84xx chip. */
6854 list_for_each_entry(cs84xx, &qla_cs84xx_list, list) {
6855 if (cs84xx->bus == ha->pdev->bus) {
6856 kref_get(&cs84xx->kref);
6857 goto done;
6858 }
6859 }
6860
6861 cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL);
6862 if (!cs84xx)
6863 goto done;
6864
6865 kref_init(&cs84xx->kref);
6866 spin_lock_init(&cs84xx->access_lock);
6867 mutex_init(&cs84xx->fw_update_mutex);
6868 cs84xx->bus = ha->pdev->bus;
6869
6870 list_add_tail(&cs84xx->list, &qla_cs84xx_list);
6871done:
6872 mutex_unlock(&qla_cs84xx_mutex);
6873 return cs84xx;
6874}
6875
6876static void
6877__qla84xx_chip_release(struct kref *kref)
6878{
6879 struct qla_chip_state_84xx *cs84xx =
6880 container_of(kref, struct qla_chip_state_84xx, kref);
6881
6882 mutex_lock(&qla_cs84xx_mutex);
6883 list_del(&cs84xx->list);
6884 mutex_unlock(&qla_cs84xx_mutex);
6885 kfree(cs84xx);
6886}
6887
6888void
e315cd28 6889qla84xx_put_chip(struct scsi_qla_host *vha)
4d4df193 6890{
e315cd28 6891 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 6892 if (ha->cs84xx)
6893 kref_put(&ha->cs84xx->kref, __qla84xx_chip_release);
6894}
6895
6896static int
e315cd28 6897qla84xx_init_chip(scsi_qla_host_t *vha)
4d4df193
HK		 6898{
6899 int rval;
6900 uint16_t status[2];
e315cd28 6901 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 6902
6903 mutex_lock(&ha->cs84xx->fw_update_mutex);
6904
e315cd28 6905 rval = qla84xx_verify_chip(vha, status);
4d4df193
HK		 6906
6907 mutex_unlock(&ha->cs84xx->fw_update_mutex);
6908
6909 return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED:
6910 QLA_SUCCESS;
6911}
3a03eb79
AV		 6912
6913/* 81XX Support **************************************************************/
6914
6915int
6916qla81xx_nvram_config(scsi_qla_host_t *vha)
6917{
6918 int rval;
6919 struct init_cb_81xx *icb;
6920 struct nvram_81xx *nv;
6921 uint32_t *dptr;
6922 uint8_t *dptr1, *dptr2;
6923 uint32_t chksum;
6924 uint16_t cnt;
6925 struct qla_hw_data *ha = vha->hw;
6926
6927 rval = QLA_SUCCESS;
6928 icb = (struct init_cb_81xx *)ha->init_cb;
6929 nv = ha->nvram;
6930
6931 /* Determine NVRAM starting address. */
6932 ha->nvram_size = sizeof(struct nvram_81xx);
3a03eb79 6933 ha->vpd_size = FA_NVRAM_VPD_SIZE;
7ec0effd
AD		 6934 if (IS_P3P_TYPE(ha) || IS_QLA8031(ha))
6935 ha->vpd_size = FA_VPD_SIZE_82XX;
3a03eb79
AV		 6936
6937 /* Get VPD data into cache */
6938 ha->vpd = ha->nvram + VPD_OFFSET;
3d79038f
AV		 6939 ha->isp_ops->read_optrom(vha, ha->vpd, ha->flt_region_vpd << 2,
6940 ha->vpd_size);
3a03eb79
AV		 6941
6942 /* Get NVRAM data into cache and calculate checksum. */
3d79038f 6943 ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2,
3a03eb79 6944 ha->nvram_size);
3d79038f 6945 dptr = (uint32_t *)nv;
da08ef5c
JC		 6946 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++)
6947 chksum += le32_to_cpu(*dptr);
3a03eb79 6948
7c3df132
SK		 6949 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
6950 "Contents of NVRAM:\n");
6951 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
6952 (uint8_t *)nv, ha->nvram_size);
3a03eb79
AV		 6953
6954 /* Bad NVRAM data, set defaults parameters. */
6955 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
6956 || nv->id[3] != ' ' ||
ad950360 6957 nv->nvram_version < cpu_to_le16(ICB_VERSION)) {
3a03eb79 6958 /* Reset NVRAM data. */
7c3df132 6959 ql_log(ql_log_info, vha, 0x0073,
9e336520 6960 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132 6961 "version=0x%x.\n", chksum, nv->id[0],
3a03eb79 6962 le16_to_cpu(nv->nvram_version));
7c3df132
SK		 6963 ql_log(ql_log_info, vha, 0x0074,
6964 "Falling back to functioning (yet invalid -- WWPN) "
6965 "defaults.\n");
3a03eb79
AV		 6966
6967 /*
6968 * Set default initialization control block.
6969 */
6970 memset(nv, 0, ha->nvram_size);
ad950360
BVA		 6971 nv->nvram_version = cpu_to_le16(ICB_VERSION);
6972 nv->version = cpu_to_le16(ICB_VERSION);
98aee70d 6973 nv->frame_payload_size = 2048;
ad950360
BVA		 6974 nv->execution_throttle = cpu_to_le16(0xFFFF);
6975 nv->exchange_count = cpu_to_le16(0);
3a03eb79 6976 nv->port_name[0] = 0x21;
f73cb695 6977 nv->port_name[1] = 0x00 + ha->port_no + 1;
3a03eb79
AV		 6978 nv->port_name[2] = 0x00;
6979 nv->port_name[3] = 0xe0;
6980 nv->port_name[4] = 0x8b;
6981 nv->port_name[5] = 0x1c;
6982 nv->port_name[6] = 0x55;
6983 nv->port_name[7] = 0x86;
6984 nv->node_name[0] = 0x20;
6985 nv->node_name[1] = 0x00;
6986 nv->node_name[2] = 0x00;
6987 nv->node_name[3] = 0xe0;
6988 nv->node_name[4] = 0x8b;
6989 nv->node_name[5] = 0x1c;
6990 nv->node_name[6] = 0x55;
6991 nv->node_name[7] = 0x86;
ad950360
BVA		 6992 nv->login_retry_count = cpu_to_le16(8);
6993 nv->interrupt_delay_timer = cpu_to_le16(0);
6994 nv->login_timeout = cpu_to_le16(0);
3a03eb79 6995 nv->firmware_options_1 =
ad950360
BVA		 6996 cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
6997 nv->firmware_options_2 = cpu_to_le32(2 << 4);
6998 nv->firmware_options_2 |= cpu_to_le32(BIT_12);
6999 nv->firmware_options_3 = cpu_to_le32(2 << 13);
7000 nv->host_p = cpu_to_le32(BIT_11|BIT_10);
7001 nv->efi_parameters = cpu_to_le32(0);
3a03eb79 7002 nv->reset_delay = 5;
ad950360
BVA		 7003 nv->max_luns_per_target = cpu_to_le16(128);
7004 nv->port_down_retry_count = cpu_to_le16(30);
7005 nv->link_down_timeout = cpu_to_le16(180);
eeebcc92 7006 nv->enode_mac[0] = 0x00;
6246b8a1
GM		 7007 nv->enode_mac[1] = 0xC0;
7008 nv->enode_mac[2] = 0xDD;
3a03eb79
AV		 7009 nv->enode_mac[3] = 0x04;
7010 nv->enode_mac[4] = 0x05;
f73cb695 7011 nv->enode_mac[5] = 0x06 + ha->port_no + 1;
3a03eb79
AV		 7012
7013 rval = 1;
7014 }
7015
9e522cd8
AE		 7016 if (IS_T10_PI_CAPABLE(ha))
7017 nv->frame_payload_size &= ~7;
7018
aa230bc5
AE		 7019 qlt_81xx_config_nvram_stage1(vha, nv);
7020
3a03eb79 7021 /* Reset Initialization control block */
773120e4 7022 memset(icb, 0, ha->init_cb_size);
3a03eb79
AV		 7023
7024 /* Copy 1st segment. */
7025 dptr1 = (uint8_t *)icb;
7026 dptr2 = (uint8_t *)&nv->version;
7027 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
7028 while (cnt--)
7029 *dptr1++ = *dptr2++;
7030
7031 icb->login_retry_count = nv->login_retry_count;
7032
7033 /* Copy 2nd segment. */
7034 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
7035 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
7036 cnt = (uint8_t *)&icb->reserved_5 -
7037 (uint8_t *)&icb->interrupt_delay_timer;
7038 while (cnt--)
7039 *dptr1++ = *dptr2++;
7040
7041 memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac));
7042 /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */
7043 if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) {
69e5f1ea
AV		 7044 icb->enode_mac[0] = 0x00;
7045 icb->enode_mac[1] = 0xC0;
7046 icb->enode_mac[2] = 0xDD;
3a03eb79
AV		 7047 icb->enode_mac[3] = 0x04;
7048 icb->enode_mac[4] = 0x05;
f73cb695 7049 icb->enode_mac[5] = 0x06 + ha->port_no + 1;
3a03eb79
AV		 7050 }
7051
b64b0e8f
AV		 7052 /* Use extended-initialization control block. */
7053 memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb));
7054
3a03eb79
AV		 7055 /*
7056 * Setup driver NVRAM options.
7057 */
7058 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
a9083016 7059 "QLE8XXX");
3a03eb79 7060
aa230bc5
AE		 7061 qlt_81xx_config_nvram_stage2(vha, icb);
7062
3a03eb79 7063 /* Use alternate WWN? */
ad950360 7064 if (nv->host_p & cpu_to_le32(BIT_15)) {
3a03eb79
AV		 7065 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
7066 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
7067 }
7068
7069 /* Prepare nodename */
ad950360 7070 if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) {
3a03eb79
AV		 7071 /*
7072 * Firmware will apply the following mask if the nodename was
7073 * not provided.
7074 */
7075 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
7076 icb->node_name[0] &= 0xF0;
7077 }
7078
7079 /* Set host adapter parameters. */
7080 ha->flags.disable_risc_code_load = 0;
7081 ha->flags.enable_lip_reset = 0;
7082 ha->flags.enable_lip_full_login =
7083 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
7084 ha->flags.enable_target_reset =
7085 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
7086 ha->flags.enable_led_scheme = 0;
7087 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
7088
7089 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
7090 (BIT_6 | BIT_5 | BIT_4)) >> 4;
7091
7092 /* save HBA serial number */
7093 ha->serial0 = icb->port_name[5];
7094 ha->serial1 = icb->port_name[6];
7095 ha->serial2 = icb->port_name[7];
7096 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
7097 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
7098
ad950360 7099 icb->execution_throttle = cpu_to_le16(0xFFFF);
3a03eb79
AV		 7100
7101 ha->retry_count = le16_to_cpu(nv->login_retry_count);
7102
7103 /* Set minimum login_timeout to 4 seconds. */
7104 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
7105 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
7106 if (le16_to_cpu(nv->login_timeout) < 4)
ad950360 7107 nv->login_timeout = cpu_to_le16(4);
3a03eb79 7108 ha->login_timeout = le16_to_cpu(nv->login_timeout);
3a03eb79
AV		 7109
7110 /* Set minimum RATOV to 100 tenths of a second. */
7111 ha->r_a_tov = 100;
7112
7113 ha->loop_reset_delay = nv->reset_delay;
7114
7115 /* Link Down Timeout = 0:
7116 *
7ec0effd 7117 * When Port Down timer expires we will start returning
3a03eb79
AV		 7118 * I/O's to OS with "DID_NO_CONNECT".
7119 *
7120 * Link Down Timeout != 0:
7121 *
7122 * The driver waits for the link to come up after link down
7123 * before returning I/Os to OS with "DID_NO_CONNECT".
7124 */
7125 if (le16_to_cpu(nv->link_down_timeout) == 0) {
7126 ha->loop_down_abort_time =
7127 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
7128 } else {
7129 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
7130 ha->loop_down_abort_time =
7131 (LOOP_DOWN_TIME - ha->link_down_timeout);
7132 }
7133
7134 /* Need enough time to try and get the port back. */
7135 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
7136 if (qlport_down_retry)
7137 ha->port_down_retry_count = qlport_down_retry;
7138
7139 /* Set login_retry_count */
7140 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
7141 if (ha->port_down_retry_count ==
7142 le16_to_cpu(nv->port_down_retry_count) &&
7143 ha->port_down_retry_count > 3)
7144 ha->login_retry_count = ha->port_down_retry_count;
7145 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
7146 ha->login_retry_count = ha->port_down_retry_count;
7147 if (ql2xloginretrycount)
7148 ha->login_retry_count = ql2xloginretrycount;
7149
6246b8a1 7150 /* if not running MSI-X we need handshaking on interrupts */
f73cb695 7151 if (!vha->hw->flags.msix_enabled && (IS_QLA83XX(ha) || IS_QLA27XX(ha)))
ad950360 7152 icb->firmware_options_2 |= cpu_to_le32(BIT_22);
6246b8a1 7153
3a03eb79
AV		 7154 /* Enable ZIO. */
7155 if (!vha->flags.init_done) {
7156 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
7157 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
7158 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
7159 le16_to_cpu(icb->interrupt_delay_timer): 2;
7160 }
ad950360 7161 icb->firmware_options_2 &= cpu_to_le32(
3a03eb79
AV		 7162 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
7163 vha->flags.process_response_queue = 0;
7164 if (ha->zio_mode != QLA_ZIO_DISABLED) {
7165 ha->zio_mode = QLA_ZIO_MODE_6;
7166
7c3df132 7167 ql_log(ql_log_info, vha, 0x0075,
3a03eb79 7168 "ZIO mode %d enabled; timer delay (%d us).\n",
7c3df132
SK		 7169 ha->zio_mode,
7170 ha->zio_timer * 100);
3a03eb79
AV		 7171
7172 icb->firmware_options_2 |= cpu_to_le32(
7173 (uint32_t)ha->zio_mode);
7174 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
7175 vha->flags.process_response_queue = 1;
7176 }
7177
41dc529a
QT		 7178 /* enable RIDA Format2 */
7179 if (qla_tgt_mode_enabled(vha) || qla_dual_mode_enabled(vha))
7180 icb->firmware_options_3 |= BIT_0;
7181
3a03eb79 7182 if (rval) {
7c3df132
SK		 7183 ql_log(ql_log_warn, vha, 0x0076,
7184 "NVRAM configuration failed.\n");
3a03eb79
AV		 7185 }
7186 return (rval);
7187}
7188
a9083016
GM		 7189int
7190qla82xx_restart_isp(scsi_qla_host_t *vha)
7191{
7192 int status, rval;
a9083016
GM		 7193 struct qla_hw_data *ha = vha->hw;
7194 struct req_que *req = ha->req_q_map[0];
7195 struct rsp_que *rsp = ha->rsp_q_map[0];
7196 struct scsi_qla_host *vp;
feafb7b1 7197 unsigned long flags;
a9083016
GM		 7198
7199 status = qla2x00_init_rings(vha);
7200 if (!status) {
7201 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
7202 ha->flags.chip_reset_done = 1;
7203
7204 status = qla2x00_fw_ready(vha);
7205 if (!status) {
a9083016
GM		 7206 /* Issue a marker after FW becomes ready. */
7207 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
a9083016 7208 vha->flags.online = 1;
7108b76e 7209 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
a9083016
GM		 7210 }
7211
7212 /* if no cable then assume it's good */
7213 if ((vha->device_flags & DFLG_NO_CABLE))
7214 status = 0;
a9083016
GM		 7215 }
7216
7217 if (!status) {
7218 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
7219
7220 if (!atomic_read(&vha->loop_down_timer)) {
7221 /*
7222 * Issue marker command only when we are going
7223 * to start the I/O .
7224 */
7225 vha->marker_needed = 1;
7226 }
7227
a9083016
GM		 7228 ha->isp_ops->enable_intrs(ha);
7229
7230 ha->isp_abort_cnt = 0;
7231 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
7232
53296788 7233 /* Update the firmware version */
3173167f 7234 status = qla82xx_check_md_needed(vha);
53296788 7235
a9083016
GM		 7236 if (ha->fce) {
7237 ha->flags.fce_enabled = 1;
7238 memset(ha->fce, 0,
7239 fce_calc_size(ha->fce_bufs));
7240 rval = qla2x00_enable_fce_trace(vha,
7241 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
7242 &ha->fce_bufs);
7243 if (rval) {
cfb0919c 7244 ql_log(ql_log_warn, vha, 0x8001,
7c3df132
SK		 7245 "Unable to reinitialize FCE (%d).\n",
7246 rval);
a9083016
GM		 7247 ha->flags.fce_enabled = 0;
7248 }
7249 }
7250
7251 if (ha->eft) {
7252 memset(ha->eft, 0, EFT_SIZE);
7253 rval = qla2x00_enable_eft_trace(vha,
7254 ha->eft_dma, EFT_NUM_BUFFERS);
7255 if (rval) {
cfb0919c 7256 ql_log(ql_log_warn, vha, 0x8010,
7c3df132
SK		 7257 "Unable to reinitialize EFT (%d).\n",
7258 rval);
a9083016
GM		 7259 }
7260 }
a9083016
GM		 7261 }
7262
7263 if (!status) {
cfb0919c 7264 ql_dbg(ql_dbg_taskm, vha, 0x8011,
7c3df132 7265 "qla82xx_restart_isp succeeded.\n");
feafb7b1
AE		 7266
7267 spin_lock_irqsave(&ha->vport_slock, flags);
7268 list_for_each_entry(vp, &ha->vp_list, list) {
7269 if (vp->vp_idx) {
7270 atomic_inc(&vp->vref_count);
7271 spin_unlock_irqrestore(&ha->vport_slock, flags);
7272
a9083016 7273 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 7274
7275 spin_lock_irqsave(&ha->vport_slock, flags);
7276 atomic_dec(&vp->vref_count);
7277 }
a9083016 7278 }
feafb7b1
AE		 7279 spin_unlock_irqrestore(&ha->vport_slock, flags);
7280
a9083016 7281 } else {
cfb0919c 7282 ql_log(ql_log_warn, vha, 0x8016,
7c3df132 7283 "qla82xx_restart_isp **** FAILED ****.\n");
a9083016
GM		 7284 }
7285
7286 return status;
7287}
7288
3a03eb79 7289void
ae97c91e 7290qla81xx_update_fw_options(scsi_qla_host_t *vha)
3a03eb79 7291{
ae97c91e
AV		 7292 struct qla_hw_data *ha = vha->hw;
7293
f198cafa
HM		 7294 /* Hold status IOCBs until ABTS response received. */
7295 if (ql2xfwholdabts)
7296 ha->fw_options[3] |= BIT_12;
7297
088d09d4
GM		 7298 /* Set Retry FLOGI in case of P2P connection */
7299 if (ha->operating_mode == P2P) {
7300 ha->fw_options[2] |= BIT_3;
7301 ql_dbg(ql_dbg_disc, vha, 0x2103,
7302 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
7303 __func__, ha->fw_options[2]);
7304 }
7305
41dc529a
QT		 7306 /* Move PUREX, ABTS RX & RIDA to ATIOQ */
7307 if (ql2xmvasynctoatio) {
7308 if (qla_tgt_mode_enabled(vha) ||
7309 qla_dual_mode_enabled(vha))
7310 ha->fw_options[2] |= BIT_11;
7311 else
7312 ha->fw_options[2] &= ~BIT_11;
7313 }
7314
7315 if (ql2xetsenable) {
7316 /* Enable ETS Burst. */
7317 memset(ha->fw_options, 0, sizeof(ha->fw_options));
7318 ha->fw_options[2] |= BIT_9;
7319 }
7320
7321 ql_dbg(ql_dbg_init, vha, 0xffff,
7322 "%s, add FW options 1-3 = 0x%04x 0x%04x 0x%04x mode %x\n",
7323 __func__, ha->fw_options[1], ha->fw_options[2],
7324 ha->fw_options[3], vha->host->active_mode);
ae97c91e 7325
ae97c91e 7326 qla2x00_set_fw_options(vha, ha->fw_options);
3a03eb79 7327}
09ff701a
SR		 7328
7329/*
7330 * qla24xx_get_fcp_prio
7331 * Gets the fcp cmd priority value for the logged in port.
7332 * Looks for a match of the port descriptors within
7333 * each of the fcp prio config entries. If a match is found,
7334 * the tag (priority) value is returned.
7335 *
7336 * Input:
21090cbe 7337 * vha = scsi host structure pointer.
09ff701a
SR		 7338 * fcport = port structure pointer.
7339 *
7340 * Return:
6c452a45 7341 * non-zero (if found)
f28a0a96 7342 * -1 (if not found)
09ff701a
SR		 7343 *
7344 * Context:
7345 * Kernel context
7346 */
f28a0a96 7347static int
09ff701a
SR		 7348qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
7349{
7350 int i, entries;
7351 uint8_t pid_match, wwn_match;
f28a0a96 7352 int priority;
09ff701a
SR		 7353 uint32_t pid1, pid2;
7354 uint64_t wwn1, wwn2;
7355 struct qla_fcp_prio_entry *pri_entry;
7356 struct qla_hw_data *ha = vha->hw;
7357
7358 if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled)
f28a0a96 7359 return -1;
09ff701a 7360
f28a0a96 7361 priority = -1;
09ff701a
SR		 7362 entries = ha->fcp_prio_cfg->num_entries;
7363 pri_entry = &ha->fcp_prio_cfg->entry[0];
7364
7365 for (i = 0; i < entries; i++) {
7366 pid_match = wwn_match = 0;
7367
7368 if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) {
7369 pri_entry++;
7370 continue;
7371 }
7372
7373 /* check source pid for a match */
7374 if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) {
7375 pid1 = pri_entry->src_pid & INVALID_PORT_ID;
7376 pid2 = vha->d_id.b24 & INVALID_PORT_ID;
7377 if (pid1 == INVALID_PORT_ID)
7378 pid_match++;
7379 else if (pid1 == pid2)
7380 pid_match++;
7381 }
7382
7383 /* check destination pid for a match */
7384 if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) {
7385 pid1 = pri_entry->dst_pid & INVALID_PORT_ID;
7386 pid2 = fcport->d_id.b24 & INVALID_PORT_ID;
7387 if (pid1 == INVALID_PORT_ID)
7388 pid_match++;
7389 else if (pid1 == pid2)
7390 pid_match++;
7391 }
7392
7393 /* check source WWN for a match */
7394 if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) {
7395 wwn1 = wwn_to_u64(vha->port_name);
7396 wwn2 = wwn_to_u64(pri_entry->src_wwpn);
7397 if (wwn2 == (uint64_t)-1)
7398 wwn_match++;
7399 else if (wwn1 == wwn2)
7400 wwn_match++;
7401 }
7402
7403 /* check destination WWN for a match */
7404 if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) {
7405 wwn1 = wwn_to_u64(fcport->port_name);
7406 wwn2 = wwn_to_u64(pri_entry->dst_wwpn);
7407 if (wwn2 == (uint64_t)-1)
7408 wwn_match++;
7409 else if (wwn1 == wwn2)
7410 wwn_match++;
7411 }
7412
7413 if (pid_match == 2 || wwn_match == 2) {
7414 /* Found a matching entry */
7415 if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID)
7416 priority = pri_entry->tag;
7417 break;
7418 }
7419
7420 pri_entry++;
7421 }
7422
7423 return priority;
7424}
7425
7426/*
7427 * qla24xx_update_fcport_fcp_prio
7428 * Activates fcp priority for the logged in fc port
7429 *
7430 * Input:
21090cbe 7431 * vha = scsi host structure pointer.
09ff701a
SR		 7432 * fcp = port structure pointer.
7433 *
7434 * Return:
7435 * QLA_SUCCESS or QLA_FUNCTION_FAILED
7436 *
7437 * Context:
7438 * Kernel context.
7439 */
7440int
21090cbe 7441qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
09ff701a
SR		 7442{
7443 int ret;
f28a0a96 7444 int priority;
09ff701a
SR		 7445 uint16_t mb[5];
7446
21090cbe
MI		 7447 if (fcport->port_type != FCT_TARGET ||
7448 fcport->loop_id == FC_NO_LOOP_ID)
09ff701a
SR		 7449 return QLA_FUNCTION_FAILED;
7450
21090cbe 7451 priority = qla24xx_get_fcp_prio(vha, fcport);
f28a0a96
AV		 7452 if (priority < 0)
7453 return QLA_FUNCTION_FAILED;
7454
7ec0effd 7455 if (IS_P3P_TYPE(vha->hw)) {
a00f6296
SK		 7456 fcport->fcp_prio = priority & 0xf;
7457 return QLA_SUCCESS;
7458 }
7459
21090cbe 7460 ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb);
cfb0919c
CD		 7461 if (ret == QLA_SUCCESS) {
7462 if (fcport->fcp_prio != priority)
7463 ql_dbg(ql_dbg_user, vha, 0x709e,
7464 "Updated FCP_CMND priority - value=%d loop_id=%d "
7465 "port_id=%02x%02x%02x.\n", priority,
7466 fcport->loop_id, fcport->d_id.b.domain,
7467 fcport->d_id.b.area, fcport->d_id.b.al_pa);
a00f6296 7468 fcport->fcp_prio = priority & 0xf;
cfb0919c 7469 } else
7c3df132 7470 ql_dbg(ql_dbg_user, vha, 0x704f,
cfb0919c
CD		 7471 "Unable to update FCP_CMND priority - ret=0x%x for "
7472 "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id,
7473 fcport->d_id.b.domain, fcport->d_id.b.area,
7474 fcport->d_id.b.al_pa);
09ff701a
SR		 7475 return ret;
7476}
7477
7478/*
7479 * qla24xx_update_all_fcp_prio
7480 * Activates fcp priority for all the logged in ports
7481 *
7482 * Input:
7483 * ha = adapter block pointer.
7484 *
7485 * Return:
7486 * QLA_SUCCESS or QLA_FUNCTION_FAILED
7487 *
7488 * Context:
7489 * Kernel context.
7490 */
7491int
7492qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha)
7493{
7494 int ret;
7495 fc_port_t *fcport;
7496
7497 ret = QLA_FUNCTION_FAILED;
7498 /* We need to set priority for all logged in ports */
7499 list_for_each_entry(fcport, &vha->vp_fcports, list)
7500 ret = qla24xx_update_fcport_fcp_prio(vha, fcport);
7501
7502 return ret;
7503}
d7459527
MH		 7504
7505struct qla_qpair *qla2xxx_create_qpair(struct scsi_qla_host *vha, int qos, int vp_idx)
7506{
7507 int rsp_id = 0;
7508 int req_id = 0;
7509 int i;
7510 struct qla_hw_data *ha = vha->hw;
7511 uint16_t qpair_id = 0;
7512 struct qla_qpair *qpair = NULL;
7513 struct qla_msix_entry *msix;
7514
7515 if (!(ha->fw_attributes & BIT_6) || !ha->flags.msix_enabled) {
7516 ql_log(ql_log_warn, vha, 0x00181,
7517 "FW/Driver is not multi-queue capable.\n");
7518 return NULL;
7519 }
7520
7521 if (ql2xmqsupport) {
7522 qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
7523 if (qpair == NULL) {
7524 ql_log(ql_log_warn, vha, 0x0182,
7525 "Failed to allocate memory for queue pair.\n");
7526 return NULL;
7527 }
7528 memset(qpair, 0, sizeof(struct qla_qpair));
7529
7530 qpair->hw = vha->hw;
25ff6af1 7531 qpair->vha = vha;
d7459527
MH		 7532
7533 /* Assign available que pair id */
7534 mutex_lock(&ha->mq_lock);
7535 qpair_id = find_first_zero_bit(ha->qpair_qid_map, ha->max_qpairs);
7536 if (qpair_id >= ha->max_qpairs) {
7537 mutex_unlock(&ha->mq_lock);
7538 ql_log(ql_log_warn, vha, 0x0183,
7539 "No resources to create additional q pair.\n");
7540 goto fail_qid_map;
7541 }
7542 set_bit(qpair_id, ha->qpair_qid_map);
7543 ha->queue_pair_map[qpair_id] = qpair;
7544 qpair->id = qpair_id;
7545 qpair->vp_idx = vp_idx;
7546
7547 for (i = 0; i < ha->msix_count; i++) {
093df737 7548 msix = &ha->msix_entries[i];
d7459527
MH		 7549 if (msix->in_use)
7550 continue;
7551 qpair->msix = msix;
7552 ql_log(ql_dbg_multiq, vha, 0xc00f,
7553 "Vector %x selected for qpair\n", msix->vector);
7554 break;
7555 }
7556 if (!qpair->msix) {
7557 ql_log(ql_log_warn, vha, 0x0184,
7558 "Out of MSI-X vectors!.\n");
7559 goto fail_msix;
7560 }
7561
7562 qpair->msix->in_use = 1;
7563 list_add_tail(&qpair->qp_list_elem, &vha->qp_list);
7564
7565 mutex_unlock(&ha->mq_lock);
7566
7567 /* Create response queue first */
7568 rsp_id = qla25xx_create_rsp_que(ha, 0, 0, 0, qpair);
7569 if (!rsp_id) {
7570 ql_log(ql_log_warn, vha, 0x0185,
7571 "Failed to create response queue.\n");
7572 goto fail_rsp;
7573 }
7574
7575 qpair->rsp = ha->rsp_q_map[rsp_id];
7576
7577 /* Create request queue */
7578 req_id = qla25xx_create_req_que(ha, 0, vp_idx, 0, rsp_id, qos);
7579 if (!req_id) {
7580 ql_log(ql_log_warn, vha, 0x0186,
7581 "Failed to create request queue.\n");
7582 goto fail_req;
7583 }
7584
7585 qpair->req = ha->req_q_map[req_id];
7586 qpair->rsp->req = qpair->req;
7587
7588 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
7589 if (ha->fw_attributes & BIT_4)
7590 qpair->difdix_supported = 1;
7591 }
7592
7593 qpair->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
7594 if (!qpair->srb_mempool) {
7595 ql_log(ql_log_warn, vha, 0x0191,
7596 "Failed to create srb mempool for qpair %d\n",
7597 qpair->id);
7598 goto fail_mempool;
7599 }
7600
7601 /* Mark as online */
7602 qpair->online = 1;
7603
7604 if (!vha->flags.qpairs_available)
7605 vha->flags.qpairs_available = 1;
7606
7607 ql_dbg(ql_dbg_multiq, vha, 0xc00d,
7608 "Request/Response queue pair created, id %d\n",
7609 qpair->id);
7610 ql_dbg(ql_dbg_init, vha, 0x0187,
7611 "Request/Response queue pair created, id %d\n",
7612 qpair->id);
7613 }
7614 return qpair;
7615
7616fail_mempool:
7617fail_req:
7618 qla25xx_delete_rsp_que(vha, qpair->rsp);
7619fail_rsp:
7620 mutex_lock(&ha->mq_lock);
7621 qpair->msix->in_use = 0;
7622 list_del(&qpair->qp_list_elem);
7623 if (list_empty(&vha->qp_list))
7624 vha->flags.qpairs_available = 0;
7625fail_msix:
7626 ha->queue_pair_map[qpair_id] = NULL;
7627 clear_bit(qpair_id, ha->qpair_qid_map);
7628 mutex_unlock(&ha->mq_lock);
7629fail_qid_map:
7630 kfree(qpair);
7631 return NULL;
7632}
7633
7634int qla2xxx_delete_qpair(struct scsi_qla_host *vha, struct qla_qpair *qpair)
7635{
7636 int ret;
7637 struct qla_hw_data *ha = qpair->hw;
7638
7639 qpair->delete_in_progress = 1;
7640 while (atomic_read(&qpair->ref_count))
7641 msleep(500);
7642
7643 ret = qla25xx_delete_req_que(vha, qpair->req);
7644 if (ret != QLA_SUCCESS)
7645 goto fail;
7646 ret = qla25xx_delete_rsp_que(vha, qpair->rsp);
7647 if (ret != QLA_SUCCESS)
7648 goto fail;
7649
7650 mutex_lock(&ha->mq_lock);
7651 ha->queue_pair_map[qpair->id] = NULL;
7652 clear_bit(qpair->id, ha->qpair_qid_map);
7653 list_del(&qpair->qp_list_elem);
7654 if (list_empty(&vha->qp_list))
7655 vha->flags.qpairs_available = 0;
7656 mempool_destroy(qpair->srb_mempool);
7657 kfree(qpair);
7658 mutex_unlock(&ha->mq_lock);
7659
7660 return QLA_SUCCESS;
7661fail:
7662 return ret;
7663}
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