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Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
fa90c54f | 2 | * QLogic Fibre Channel HBA Driver |
bd21eaf9 | 3 | * Copyright (c) 2003-2014 QLogic Corporation |
1da177e4 | 4 | * |
fa90c54f | 5 | * See LICENSE.qla2xxx for copyright and licensing details. |
1da177e4 LT |
6 | */ |
7 | #include "qla_def.h" | |
73208dfd | 8 | #include "qla_gbl.h" |
1da177e4 LT |
9 | |
10 | #include <linux/delay.h> | |
5a0e3ad6 | 11 | #include <linux/slab.h> |
0107109e | 12 | #include <linux/vmalloc.h> |
1da177e4 LT |
13 | |
14 | #include "qla_devtbl.h" | |
15 | ||
4e08df3f DM |
16 | #ifdef CONFIG_SPARC |
17 | #include <asm/prom.h> | |
4e08df3f DM |
18 | #endif |
19 | ||
2d70c103 NB |
20 | #include <target/target_core_base.h> |
21 | #include "qla_target.h" | |
22 | ||
1da177e4 LT |
23 | /* |
24 | * QLogic ISP2x00 Hardware Support Function Prototypes. | |
25 | */ | |
1da177e4 | 26 | static int qla2x00_isp_firmware(scsi_qla_host_t *); |
1da177e4 | 27 | static int qla2x00_setup_chip(scsi_qla_host_t *); |
1da177e4 LT |
28 | static int qla2x00_fw_ready(scsi_qla_host_t *); |
29 | static int qla2x00_configure_hba(scsi_qla_host_t *); | |
1da177e4 LT |
30 | static int qla2x00_configure_loop(scsi_qla_host_t *); |
31 | static int qla2x00_configure_local_loop(scsi_qla_host_t *); | |
1da177e4 LT |
32 | static int qla2x00_configure_fabric(scsi_qla_host_t *); |
33 | static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *, struct list_head *); | |
1da177e4 LT |
34 | static int qla2x00_fabric_dev_login(scsi_qla_host_t *, fc_port_t *, |
35 | uint16_t *); | |
1da177e4 LT |
36 | |
37 | static int qla2x00_restart_isp(scsi_qla_host_t *); | |
1da177e4 | 38 | |
4d4df193 HK |
39 | static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *); |
40 | static int qla84xx_init_chip(scsi_qla_host_t *); | |
73208dfd | 41 | static int qla25xx_init_queues(struct qla_hw_data *); |
4d4df193 | 42 | |
ac280b67 AV |
43 | /* SRB Extensions ---------------------------------------------------------- */ |
44 | ||
9ba56b95 GM |
45 | void |
46 | qla2x00_sp_timeout(unsigned long __data) | |
ac280b67 AV |
47 | { |
48 | srb_t *sp = (srb_t *)__data; | |
4916392b | 49 | struct srb_iocb *iocb; |
ac280b67 AV |
50 | fc_port_t *fcport = sp->fcport; |
51 | struct qla_hw_data *ha = fcport->vha->hw; | |
52 | struct req_que *req; | |
53 | unsigned long flags; | |
54 | ||
55 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
56 | req = ha->req_q_map[0]; | |
57 | req->outstanding_cmds[sp->handle] = NULL; | |
9ba56b95 | 58 | iocb = &sp->u.iocb_cmd; |
4916392b | 59 | iocb->timeout(sp); |
9ba56b95 | 60 | sp->free(fcport->vha, sp); |
6ac52608 | 61 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
ac280b67 AV |
62 | } |
63 | ||
9ba56b95 GM |
64 | void |
65 | qla2x00_sp_free(void *data, void *ptr) | |
ac280b67 | 66 | { |
9ba56b95 GM |
67 | srb_t *sp = (srb_t *)ptr; |
68 | struct srb_iocb *iocb = &sp->u.iocb_cmd; | |
69 | struct scsi_qla_host *vha = (scsi_qla_host_t *)data; | |
ac280b67 | 70 | |
4d97cc53 | 71 | del_timer(&iocb->timer); |
b00ee7d7 | 72 | qla2x00_rel_sp(vha, sp); |
ac280b67 AV |
73 | } |
74 | ||
ac280b67 AV |
75 | /* Asynchronous Login/Logout Routines -------------------------------------- */ |
76 | ||
a9b6f722 | 77 | unsigned long |
5b91490e AV |
78 | qla2x00_get_async_timeout(struct scsi_qla_host *vha) |
79 | { | |
80 | unsigned long tmo; | |
81 | struct qla_hw_data *ha = vha->hw; | |
82 | ||
83 | /* Firmware should use switch negotiated r_a_tov for timeout. */ | |
84 | tmo = ha->r_a_tov / 10 * 2; | |
8ae6d9c7 GM |
85 | if (IS_QLAFX00(ha)) { |
86 | tmo = FX00_DEF_RATOV * 2; | |
87 | } else if (!IS_FWI2_CAPABLE(ha)) { | |
5b91490e AV |
88 | /* |
89 | * Except for earlier ISPs where the timeout is seeded from the | |
90 | * initialization control block. | |
91 | */ | |
92 | tmo = ha->login_timeout; | |
93 | } | |
94 | return tmo; | |
95 | } | |
ac280b67 AV |
96 | |
97 | static void | |
9ba56b95 | 98 | qla2x00_async_iocb_timeout(void *data) |
ac280b67 | 99 | { |
9ba56b95 | 100 | srb_t *sp = (srb_t *)data; |
ac280b67 | 101 | fc_port_t *fcport = sp->fcport; |
ac280b67 | 102 | |
7c3df132 | 103 | ql_dbg(ql_dbg_disc, fcport->vha, 0x2071, |
cfb0919c | 104 | "Async-%s timeout - hdl=%x portid=%02x%02x%02x.\n", |
9ba56b95 | 105 | sp->name, sp->handle, fcport->d_id.b.domain, fcport->d_id.b.area, |
7c3df132 | 106 | fcport->d_id.b.al_pa); |
ac280b67 | 107 | |
5ff1d584 | 108 | fcport->flags &= ~FCF_ASYNC_SENT; |
9ba56b95 GM |
109 | if (sp->type == SRB_LOGIN_CMD) { |
110 | struct srb_iocb *lio = &sp->u.iocb_cmd; | |
ac280b67 | 111 | qla2x00_post_async_logout_work(fcport->vha, fcport, NULL); |
6ac52608 AV |
112 | /* Retry as needed. */ |
113 | lio->u.logio.data[0] = MBS_COMMAND_ERROR; | |
114 | lio->u.logio.data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ? | |
115 | QLA_LOGIO_LOGIN_RETRIED : 0; | |
116 | qla2x00_post_async_login_done_work(fcport->vha, fcport, | |
117 | lio->u.logio.data); | |
a6ca8878 AP |
118 | } else if (sp->type == SRB_LOGOUT_CMD) { |
119 | qlt_logo_completion_handler(fcport, QLA_FUNCTION_TIMEOUT); | |
6ac52608 | 120 | } |
ac280b67 AV |
121 | } |
122 | ||
99b0bec7 | 123 | static void |
9ba56b95 | 124 | qla2x00_async_login_sp_done(void *data, void *ptr, int res) |
99b0bec7 | 125 | { |
9ba56b95 GM |
126 | srb_t *sp = (srb_t *)ptr; |
127 | struct srb_iocb *lio = &sp->u.iocb_cmd; | |
128 | struct scsi_qla_host *vha = (scsi_qla_host_t *)data; | |
129 | ||
130 | if (!test_bit(UNLOADING, &vha->dpc_flags)) | |
131 | qla2x00_post_async_login_done_work(sp->fcport->vha, sp->fcport, | |
132 | lio->u.logio.data); | |
133 | sp->free(sp->fcport->vha, sp); | |
99b0bec7 AV |
134 | } |
135 | ||
ac280b67 AV |
136 | int |
137 | qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport, | |
138 | uint16_t *data) | |
139 | { | |
ac280b67 | 140 | srb_t *sp; |
4916392b | 141 | struct srb_iocb *lio; |
ac280b67 AV |
142 | int rval; |
143 | ||
144 | rval = QLA_FUNCTION_FAILED; | |
9ba56b95 | 145 | sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); |
ac280b67 AV |
146 | if (!sp) |
147 | goto done; | |
148 | ||
9ba56b95 GM |
149 | sp->type = SRB_LOGIN_CMD; |
150 | sp->name = "login"; | |
151 | qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2); | |
152 | ||
153 | lio = &sp->u.iocb_cmd; | |
3822263e | 154 | lio->timeout = qla2x00_async_iocb_timeout; |
9ba56b95 | 155 | sp->done = qla2x00_async_login_sp_done; |
4916392b | 156 | lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI; |
ac280b67 | 157 | if (data[1] & QLA_LOGIO_LOGIN_RETRIED) |
4916392b | 158 | lio->u.logio.flags |= SRB_LOGIN_RETRIED; |
ac280b67 AV |
159 | rval = qla2x00_start_sp(sp); |
160 | if (rval != QLA_SUCCESS) | |
161 | goto done_free_sp; | |
162 | ||
7c3df132 | 163 | ql_dbg(ql_dbg_disc, vha, 0x2072, |
cfb0919c CD |
164 | "Async-login - hdl=%x, loopid=%x portid=%02x%02x%02x " |
165 | "retries=%d.\n", sp->handle, fcport->loop_id, | |
166 | fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa, | |
167 | fcport->login_retry); | |
ac280b67 AV |
168 | return rval; |
169 | ||
170 | done_free_sp: | |
9ba56b95 | 171 | sp->free(fcport->vha, sp); |
ac280b67 AV |
172 | done: |
173 | return rval; | |
174 | } | |
175 | ||
99b0bec7 | 176 | static void |
9ba56b95 | 177 | qla2x00_async_logout_sp_done(void *data, void *ptr, int res) |
99b0bec7 | 178 | { |
9ba56b95 GM |
179 | srb_t *sp = (srb_t *)ptr; |
180 | struct srb_iocb *lio = &sp->u.iocb_cmd; | |
181 | struct scsi_qla_host *vha = (scsi_qla_host_t *)data; | |
182 | ||
183 | if (!test_bit(UNLOADING, &vha->dpc_flags)) | |
184 | qla2x00_post_async_logout_done_work(sp->fcport->vha, sp->fcport, | |
185 | lio->u.logio.data); | |
186 | sp->free(sp->fcport->vha, sp); | |
99b0bec7 AV |
187 | } |
188 | ||
ac280b67 AV |
189 | int |
190 | qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport) | |
191 | { | |
ac280b67 | 192 | srb_t *sp; |
4916392b | 193 | struct srb_iocb *lio; |
ac280b67 AV |
194 | int rval; |
195 | ||
196 | rval = QLA_FUNCTION_FAILED; | |
9ba56b95 | 197 | sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); |
ac280b67 AV |
198 | if (!sp) |
199 | goto done; | |
200 | ||
9ba56b95 GM |
201 | sp->type = SRB_LOGOUT_CMD; |
202 | sp->name = "logout"; | |
203 | qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2); | |
204 | ||
205 | lio = &sp->u.iocb_cmd; | |
3822263e | 206 | lio->timeout = qla2x00_async_iocb_timeout; |
9ba56b95 | 207 | sp->done = qla2x00_async_logout_sp_done; |
ac280b67 AV |
208 | rval = qla2x00_start_sp(sp); |
209 | if (rval != QLA_SUCCESS) | |
210 | goto done_free_sp; | |
211 | ||
7c3df132 | 212 | ql_dbg(ql_dbg_disc, vha, 0x2070, |
cfb0919c CD |
213 | "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x.\n", |
214 | sp->handle, fcport->loop_id, fcport->d_id.b.domain, | |
215 | fcport->d_id.b.area, fcport->d_id.b.al_pa); | |
ac280b67 AV |
216 | return rval; |
217 | ||
218 | done_free_sp: | |
9ba56b95 | 219 | sp->free(fcport->vha, sp); |
ac280b67 AV |
220 | done: |
221 | return rval; | |
222 | } | |
223 | ||
5ff1d584 | 224 | static void |
9ba56b95 | 225 | qla2x00_async_adisc_sp_done(void *data, void *ptr, int res) |
5ff1d584 | 226 | { |
9ba56b95 GM |
227 | srb_t *sp = (srb_t *)ptr; |
228 | struct srb_iocb *lio = &sp->u.iocb_cmd; | |
229 | struct scsi_qla_host *vha = (scsi_qla_host_t *)data; | |
230 | ||
231 | if (!test_bit(UNLOADING, &vha->dpc_flags)) | |
232 | qla2x00_post_async_adisc_done_work(sp->fcport->vha, sp->fcport, | |
233 | lio->u.logio.data); | |
234 | sp->free(sp->fcport->vha, sp); | |
5ff1d584 AV |
235 | } |
236 | ||
237 | int | |
238 | qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport, | |
239 | uint16_t *data) | |
240 | { | |
5ff1d584 | 241 | srb_t *sp; |
4916392b | 242 | struct srb_iocb *lio; |
5ff1d584 AV |
243 | int rval; |
244 | ||
245 | rval = QLA_FUNCTION_FAILED; | |
9ba56b95 | 246 | sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); |
5ff1d584 AV |
247 | if (!sp) |
248 | goto done; | |
249 | ||
9ba56b95 GM |
250 | sp->type = SRB_ADISC_CMD; |
251 | sp->name = "adisc"; | |
252 | qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2); | |
253 | ||
254 | lio = &sp->u.iocb_cmd; | |
3822263e | 255 | lio->timeout = qla2x00_async_iocb_timeout; |
9ba56b95 | 256 | sp->done = qla2x00_async_adisc_sp_done; |
5ff1d584 | 257 | if (data[1] & QLA_LOGIO_LOGIN_RETRIED) |
4916392b | 258 | lio->u.logio.flags |= SRB_LOGIN_RETRIED; |
5ff1d584 AV |
259 | rval = qla2x00_start_sp(sp); |
260 | if (rval != QLA_SUCCESS) | |
261 | goto done_free_sp; | |
262 | ||
7c3df132 | 263 | ql_dbg(ql_dbg_disc, vha, 0x206f, |
cfb0919c CD |
264 | "Async-adisc - hdl=%x loopid=%x portid=%02x%02x%02x.\n", |
265 | sp->handle, fcport->loop_id, fcport->d_id.b.domain, | |
266 | fcport->d_id.b.area, fcport->d_id.b.al_pa); | |
5ff1d584 AV |
267 | return rval; |
268 | ||
269 | done_free_sp: | |
9ba56b95 | 270 | sp->free(fcport->vha, sp); |
5ff1d584 AV |
271 | done: |
272 | return rval; | |
273 | } | |
274 | ||
3822263e | 275 | static void |
faef62d1 | 276 | qla2x00_tmf_iocb_timeout(void *data) |
3822263e | 277 | { |
faef62d1 AB |
278 | srb_t *sp = (srb_t *)data; |
279 | struct srb_iocb *tmf = &sp->u.iocb_cmd; | |
3822263e | 280 | |
faef62d1 AB |
281 | tmf->u.tmf.comp_status = CS_TIMEOUT; |
282 | complete(&tmf->u.tmf.comp); | |
283 | } | |
9ba56b95 | 284 | |
faef62d1 AB |
285 | static void |
286 | qla2x00_tmf_sp_done(void *data, void *ptr, int res) | |
287 | { | |
288 | srb_t *sp = (srb_t *)ptr; | |
289 | struct srb_iocb *tmf = &sp->u.iocb_cmd; | |
290 | complete(&tmf->u.tmf.comp); | |
3822263e MI |
291 | } |
292 | ||
293 | int | |
faef62d1 | 294 | qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t flags, uint32_t lun, |
3822263e MI |
295 | uint32_t tag) |
296 | { | |
297 | struct scsi_qla_host *vha = fcport->vha; | |
faef62d1 | 298 | struct srb_iocb *tm_iocb; |
3822263e | 299 | srb_t *sp; |
faef62d1 | 300 | int rval = QLA_FUNCTION_FAILED; |
3822263e | 301 | |
9ba56b95 | 302 | sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); |
3822263e MI |
303 | if (!sp) |
304 | goto done; | |
305 | ||
faef62d1 | 306 | tm_iocb = &sp->u.iocb_cmd; |
9ba56b95 GM |
307 | sp->type = SRB_TM_CMD; |
308 | sp->name = "tmf"; | |
faef62d1 AB |
309 | qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha)); |
310 | tm_iocb->u.tmf.flags = flags; | |
311 | tm_iocb->u.tmf.lun = lun; | |
312 | tm_iocb->u.tmf.data = tag; | |
313 | sp->done = qla2x00_tmf_sp_done; | |
314 | tm_iocb->timeout = qla2x00_tmf_iocb_timeout; | |
315 | init_completion(&tm_iocb->u.tmf.comp); | |
3822263e MI |
316 | |
317 | rval = qla2x00_start_sp(sp); | |
318 | if (rval != QLA_SUCCESS) | |
319 | goto done_free_sp; | |
320 | ||
7c3df132 | 321 | ql_dbg(ql_dbg_taskm, vha, 0x802f, |
cfb0919c CD |
322 | "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n", |
323 | sp->handle, fcport->loop_id, fcport->d_id.b.domain, | |
324 | fcport->d_id.b.area, fcport->d_id.b.al_pa); | |
faef62d1 AB |
325 | |
326 | wait_for_completion(&tm_iocb->u.tmf.comp); | |
327 | ||
328 | rval = tm_iocb->u.tmf.comp_status == CS_COMPLETE ? | |
329 | QLA_SUCCESS : QLA_FUNCTION_FAILED; | |
330 | ||
331 | if ((rval != QLA_SUCCESS) || tm_iocb->u.tmf.data) { | |
332 | ql_dbg(ql_dbg_taskm, vha, 0x8030, | |
333 | "TM IOCB failed (%x).\n", rval); | |
334 | } | |
335 | ||
336 | if (!test_bit(UNLOADING, &vha->dpc_flags) && !IS_QLAFX00(vha->hw)) { | |
337 | flags = tm_iocb->u.tmf.flags; | |
338 | lun = (uint16_t)tm_iocb->u.tmf.lun; | |
339 | ||
340 | /* Issue Marker IOCB */ | |
341 | qla2x00_marker(vha, vha->hw->req_q_map[0], | |
342 | vha->hw->rsp_q_map[0], sp->fcport->loop_id, lun, | |
343 | flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID); | |
344 | } | |
3822263e MI |
345 | |
346 | done_free_sp: | |
faef62d1 | 347 | sp->free(vha, sp); |
3822263e MI |
348 | done: |
349 | return rval; | |
350 | } | |
351 | ||
4440e46d AB |
352 | static void |
353 | qla24xx_abort_iocb_timeout(void *data) | |
354 | { | |
355 | srb_t *sp = (srb_t *)data; | |
356 | struct srb_iocb *abt = &sp->u.iocb_cmd; | |
357 | ||
358 | abt->u.abt.comp_status = CS_TIMEOUT; | |
359 | complete(&abt->u.abt.comp); | |
360 | } | |
361 | ||
362 | static void | |
363 | qla24xx_abort_sp_done(void *data, void *ptr, int res) | |
364 | { | |
365 | srb_t *sp = (srb_t *)ptr; | |
366 | struct srb_iocb *abt = &sp->u.iocb_cmd; | |
367 | ||
368 | complete(&abt->u.abt.comp); | |
369 | } | |
370 | ||
371 | static int | |
372 | qla24xx_async_abort_cmd(srb_t *cmd_sp) | |
373 | { | |
374 | scsi_qla_host_t *vha = cmd_sp->fcport->vha; | |
375 | fc_port_t *fcport = cmd_sp->fcport; | |
376 | struct srb_iocb *abt_iocb; | |
377 | srb_t *sp; | |
378 | int rval = QLA_FUNCTION_FAILED; | |
379 | ||
380 | sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); | |
381 | if (!sp) | |
382 | goto done; | |
383 | ||
384 | abt_iocb = &sp->u.iocb_cmd; | |
385 | sp->type = SRB_ABT_CMD; | |
386 | sp->name = "abort"; | |
387 | qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha)); | |
388 | abt_iocb->u.abt.cmd_hndl = cmd_sp->handle; | |
389 | sp->done = qla24xx_abort_sp_done; | |
390 | abt_iocb->timeout = qla24xx_abort_iocb_timeout; | |
391 | init_completion(&abt_iocb->u.abt.comp); | |
392 | ||
393 | rval = qla2x00_start_sp(sp); | |
394 | if (rval != QLA_SUCCESS) | |
395 | goto done_free_sp; | |
396 | ||
397 | ql_dbg(ql_dbg_async, vha, 0x507c, | |
398 | "Abort command issued - hdl=%x, target_id=%x\n", | |
399 | cmd_sp->handle, fcport->tgt_id); | |
400 | ||
401 | wait_for_completion(&abt_iocb->u.abt.comp); | |
402 | ||
403 | rval = abt_iocb->u.abt.comp_status == CS_COMPLETE ? | |
404 | QLA_SUCCESS : QLA_FUNCTION_FAILED; | |
405 | ||
406 | done_free_sp: | |
407 | sp->free(vha, sp); | |
408 | done: | |
409 | return rval; | |
410 | } | |
411 | ||
412 | int | |
413 | qla24xx_async_abort_command(srb_t *sp) | |
414 | { | |
415 | unsigned long flags = 0; | |
416 | ||
417 | uint32_t handle; | |
418 | fc_port_t *fcport = sp->fcport; | |
419 | struct scsi_qla_host *vha = fcport->vha; | |
420 | struct qla_hw_data *ha = vha->hw; | |
421 | struct req_que *req = vha->req; | |
422 | ||
423 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
424 | for (handle = 1; handle < req->num_outstanding_cmds; handle++) { | |
425 | if (req->outstanding_cmds[handle] == sp) | |
426 | break; | |
427 | } | |
428 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
429 | if (handle == req->num_outstanding_cmds) { | |
430 | /* Command not found. */ | |
431 | return QLA_FUNCTION_FAILED; | |
432 | } | |
433 | if (sp->type == SRB_FXIOCB_DCMD) | |
434 | return qlafx00_fx_disc(vha, &vha->hw->mr.fcport, | |
435 | FXDISC_ABORT_IOCTL); | |
436 | ||
437 | return qla24xx_async_abort_cmd(sp); | |
438 | } | |
439 | ||
4916392b | 440 | void |
ac280b67 AV |
441 | qla2x00_async_login_done(struct scsi_qla_host *vha, fc_port_t *fcport, |
442 | uint16_t *data) | |
443 | { | |
444 | int rval; | |
ac280b67 AV |
445 | |
446 | switch (data[0]) { | |
447 | case MBS_COMMAND_COMPLETE: | |
a4f92a32 AV |
448 | /* |
449 | * Driver must validate login state - If PRLI not complete, | |
450 | * force a relogin attempt via implicit LOGO, PLOGI, and PRLI | |
451 | * requests. | |
452 | */ | |
453 | rval = qla2x00_get_port_database(vha, fcport, 0); | |
0eba25df AE |
454 | if (rval == QLA_NOT_LOGGED_IN) { |
455 | fcport->flags &= ~FCF_ASYNC_SENT; | |
456 | fcport->flags |= FCF_LOGIN_NEEDED; | |
457 | set_bit(RELOGIN_NEEDED, &vha->dpc_flags); | |
458 | break; | |
459 | } | |
460 | ||
a4f92a32 AV |
461 | if (rval != QLA_SUCCESS) { |
462 | qla2x00_post_async_logout_work(vha, fcport, NULL); | |
463 | qla2x00_post_async_login_work(vha, fcport, NULL); | |
464 | break; | |
465 | } | |
99b0bec7 | 466 | if (fcport->flags & FCF_FCP2_DEVICE) { |
5ff1d584 AV |
467 | qla2x00_post_async_adisc_work(vha, fcport, data); |
468 | break; | |
99b0bec7 AV |
469 | } |
470 | qla2x00_update_fcport(vha, fcport); | |
ac280b67 AV |
471 | break; |
472 | case MBS_COMMAND_ERROR: | |
5ff1d584 | 473 | fcport->flags &= ~FCF_ASYNC_SENT; |
ac280b67 AV |
474 | if (data[1] & QLA_LOGIO_LOGIN_RETRIED) |
475 | set_bit(RELOGIN_NEEDED, &vha->dpc_flags); | |
476 | else | |
80d79440 | 477 | qla2x00_mark_device_lost(vha, fcport, 1, 0); |
ac280b67 AV |
478 | break; |
479 | case MBS_PORT_ID_USED: | |
480 | fcport->loop_id = data[1]; | |
6ac52608 | 481 | qla2x00_post_async_logout_work(vha, fcport, NULL); |
ac280b67 AV |
482 | qla2x00_post_async_login_work(vha, fcport, NULL); |
483 | break; | |
484 | case MBS_LOOP_ID_USED: | |
485 | fcport->loop_id++; | |
486 | rval = qla2x00_find_new_loop_id(vha, fcport); | |
487 | if (rval != QLA_SUCCESS) { | |
5ff1d584 | 488 | fcport->flags &= ~FCF_ASYNC_SENT; |
80d79440 | 489 | qla2x00_mark_device_lost(vha, fcport, 1, 0); |
ac280b67 AV |
490 | break; |
491 | } | |
492 | qla2x00_post_async_login_work(vha, fcport, NULL); | |
493 | break; | |
494 | } | |
4916392b | 495 | return; |
ac280b67 AV |
496 | } |
497 | ||
4916392b | 498 | void |
ac280b67 AV |
499 | qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport, |
500 | uint16_t *data) | |
501 | { | |
a6ca8878 AP |
502 | /* Don't re-login in target mode */ |
503 | if (!fcport->tgt_session) | |
504 | qla2x00_mark_device_lost(vha, fcport, 1, 0); | |
505 | qlt_logo_completion_handler(fcport, data[0]); | |
4916392b | 506 | return; |
ac280b67 AV |
507 | } |
508 | ||
4916392b | 509 | void |
5ff1d584 AV |
510 | qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport, |
511 | uint16_t *data) | |
512 | { | |
513 | if (data[0] == MBS_COMMAND_COMPLETE) { | |
514 | qla2x00_update_fcport(vha, fcport); | |
515 | ||
4916392b | 516 | return; |
5ff1d584 AV |
517 | } |
518 | ||
519 | /* Retry login. */ | |
520 | fcport->flags &= ~FCF_ASYNC_SENT; | |
521 | if (data[1] & QLA_LOGIO_LOGIN_RETRIED) | |
522 | set_bit(RELOGIN_NEEDED, &vha->dpc_flags); | |
523 | else | |
80d79440 | 524 | qla2x00_mark_device_lost(vha, fcport, 1, 0); |
5ff1d584 | 525 | |
4916392b | 526 | return; |
5ff1d584 AV |
527 | } |
528 | ||
1da177e4 LT |
529 | /****************************************************************************/ |
530 | /* QLogic ISP2x00 Hardware Support Functions. */ | |
531 | /****************************************************************************/ | |
532 | ||
fa492630 | 533 | static int |
7d613ac6 SV |
534 | qla83xx_nic_core_fw_load(scsi_qla_host_t *vha) |
535 | { | |
536 | int rval = QLA_SUCCESS; | |
537 | struct qla_hw_data *ha = vha->hw; | |
538 | uint32_t idc_major_ver, idc_minor_ver; | |
711aa7f7 | 539 | uint16_t config[4]; |
7d613ac6 SV |
540 | |
541 | qla83xx_idc_lock(vha, 0); | |
542 | ||
543 | /* SV: TODO: Assign initialization timeout from | |
544 | * flash-info / other param | |
545 | */ | |
546 | ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT; | |
547 | ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT; | |
548 | ||
549 | /* Set our fcoe function presence */ | |
550 | if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) { | |
551 | ql_dbg(ql_dbg_p3p, vha, 0xb077, | |
552 | "Error while setting DRV-Presence.\n"); | |
553 | rval = QLA_FUNCTION_FAILED; | |
554 | goto exit; | |
555 | } | |
556 | ||
557 | /* Decide the reset ownership */ | |
558 | qla83xx_reset_ownership(vha); | |
559 | ||
560 | /* | |
561 | * On first protocol driver load: | |
562 | * Init-Owner: Set IDC-Major-Version and Clear IDC-Lock-Recovery | |
563 | * register. | |
564 | * Others: Check compatibility with current IDC Major version. | |
565 | */ | |
566 | qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver); | |
567 | if (ha->flags.nic_core_reset_owner) { | |
568 | /* Set IDC Major version */ | |
569 | idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION; | |
570 | qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver); | |
571 | ||
572 | /* Clearing IDC-Lock-Recovery register */ | |
573 | qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0); | |
574 | } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) { | |
575 | /* | |
576 | * Clear further IDC participation if we are not compatible with | |
577 | * the current IDC Major Version. | |
578 | */ | |
579 | ql_log(ql_log_warn, vha, 0xb07d, | |
580 | "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n", | |
581 | idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION); | |
582 | __qla83xx_clear_drv_presence(vha); | |
583 | rval = QLA_FUNCTION_FAILED; | |
584 | goto exit; | |
585 | } | |
586 | /* Each function sets its supported Minor version. */ | |
587 | qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver); | |
588 | idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2)); | |
589 | qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver); | |
590 | ||
711aa7f7 SK |
591 | if (ha->flags.nic_core_reset_owner) { |
592 | memset(config, 0, sizeof(config)); | |
593 | if (!qla81xx_get_port_config(vha, config)) | |
594 | qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, | |
595 | QLA8XXX_DEV_READY); | |
596 | } | |
597 | ||
7d613ac6 SV |
598 | rval = qla83xx_idc_state_handler(vha); |
599 | ||
600 | exit: | |
601 | qla83xx_idc_unlock(vha, 0); | |
602 | ||
603 | return rval; | |
604 | } | |
605 | ||
1da177e4 LT |
606 | /* |
607 | * qla2x00_initialize_adapter | |
608 | * Initialize board. | |
609 | * | |
610 | * Input: | |
611 | * ha = adapter block pointer. | |
612 | * | |
613 | * Returns: | |
614 | * 0 = success | |
615 | */ | |
616 | int | |
e315cd28 | 617 | qla2x00_initialize_adapter(scsi_qla_host_t *vha) |
1da177e4 LT |
618 | { |
619 | int rval; | |
e315cd28 | 620 | struct qla_hw_data *ha = vha->hw; |
73208dfd | 621 | struct req_que *req = ha->req_q_map[0]; |
2533cf67 | 622 | |
1da177e4 | 623 | /* Clear adapter flags. */ |
e315cd28 | 624 | vha->flags.online = 0; |
2533cf67 | 625 | ha->flags.chip_reset_done = 0; |
e315cd28 | 626 | vha->flags.reset_active = 0; |
85880801 AV |
627 | ha->flags.pci_channel_io_perm_failure = 0; |
628 | ha->flags.eeh_busy = 0; | |
fabbb8df | 629 | vha->qla_stats.jiffies_at_last_reset = get_jiffies_64(); |
e315cd28 AC |
630 | atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); |
631 | atomic_set(&vha->loop_state, LOOP_DOWN); | |
632 | vha->device_flags = DFLG_NO_CABLE; | |
633 | vha->dpc_flags = 0; | |
634 | vha->flags.management_server_logged_in = 0; | |
635 | vha->marker_needed = 0; | |
1da177e4 LT |
636 | ha->isp_abort_cnt = 0; |
637 | ha->beacon_blink_led = 0; | |
638 | ||
73208dfd AC |
639 | set_bit(0, ha->req_qid_map); |
640 | set_bit(0, ha->rsp_qid_map); | |
641 | ||
cfb0919c | 642 | ql_dbg(ql_dbg_init, vha, 0x0040, |
7c3df132 | 643 | "Configuring PCI space...\n"); |
e315cd28 | 644 | rval = ha->isp_ops->pci_config(vha); |
1da177e4 | 645 | if (rval) { |
7c3df132 SK |
646 | ql_log(ql_log_warn, vha, 0x0044, |
647 | "Unable to configure PCI space.\n"); | |
1da177e4 LT |
648 | return (rval); |
649 | } | |
650 | ||
e315cd28 | 651 | ha->isp_ops->reset_chip(vha); |
1da177e4 | 652 | |
e315cd28 | 653 | rval = qla2xxx_get_flash_info(vha); |
c00d8994 | 654 | if (rval) { |
7c3df132 SK |
655 | ql_log(ql_log_fatal, vha, 0x004f, |
656 | "Unable to validate FLASH data.\n"); | |
7ec0effd AD |
657 | return rval; |
658 | } | |
659 | ||
660 | if (IS_QLA8044(ha)) { | |
661 | qla8044_read_reset_template(vha); | |
662 | ||
663 | /* NOTE: If ql2xdontresethba==1, set IDC_CTRL DONTRESET_BIT0. | |
664 | * If DONRESET_BIT0 is set, drivers should not set dev_state | |
665 | * to NEED_RESET. But if NEED_RESET is set, drivers should | |
666 | * should honor the reset. */ | |
667 | if (ql2xdontresethba == 1) | |
668 | qla8044_set_idc_dontreset(vha); | |
c00d8994 AV |
669 | } |
670 | ||
73208dfd | 671 | ha->isp_ops->get_flash_version(vha, req->ring); |
cfb0919c | 672 | ql_dbg(ql_dbg_init, vha, 0x0061, |
7c3df132 | 673 | "Configure NVRAM parameters...\n"); |
0107109e | 674 | |
e315cd28 | 675 | ha->isp_ops->nvram_config(vha); |
1da177e4 | 676 | |
d4c760c2 AV |
677 | if (ha->flags.disable_serdes) { |
678 | /* Mask HBA via NVRAM settings? */ | |
7c3df132 | 679 | ql_log(ql_log_info, vha, 0x0077, |
7b833558 | 680 | "Masking HBA WWPN %8phN (via NVRAM).\n", vha->port_name); |
d4c760c2 AV |
681 | return QLA_FUNCTION_FAILED; |
682 | } | |
683 | ||
cfb0919c | 684 | ql_dbg(ql_dbg_init, vha, 0x0078, |
7c3df132 | 685 | "Verifying loaded RISC code...\n"); |
1da177e4 | 686 | |
e315cd28 AC |
687 | if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) { |
688 | rval = ha->isp_ops->chip_diag(vha); | |
d19044c3 AV |
689 | if (rval) |
690 | return (rval); | |
e315cd28 | 691 | rval = qla2x00_setup_chip(vha); |
d19044c3 AV |
692 | if (rval) |
693 | return (rval); | |
1da177e4 | 694 | } |
a9083016 | 695 | |
4d4df193 | 696 | if (IS_QLA84XX(ha)) { |
e315cd28 | 697 | ha->cs84xx = qla84xx_get_chip(vha); |
4d4df193 | 698 | if (!ha->cs84xx) { |
7c3df132 | 699 | ql_log(ql_log_warn, vha, 0x00d0, |
4d4df193 HK |
700 | "Unable to configure ISP84XX.\n"); |
701 | return QLA_FUNCTION_FAILED; | |
702 | } | |
703 | } | |
2d70c103 NB |
704 | |
705 | if (qla_ini_mode_enabled(vha)) | |
706 | rval = qla2x00_init_rings(vha); | |
707 | ||
2533cf67 | 708 | ha->flags.chip_reset_done = 1; |
1da177e4 | 709 | |
9a069e19 | 710 | if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) { |
6c452a45 | 711 | /* Issue verify 84xx FW IOCB to complete 84xx initialization */ |
9a069e19 GM |
712 | rval = qla84xx_init_chip(vha); |
713 | if (rval != QLA_SUCCESS) { | |
7c3df132 SK |
714 | ql_log(ql_log_warn, vha, 0x00d4, |
715 | "Unable to initialize ISP84XX.\n"); | |
8d2b21db | 716 | qla84xx_put_chip(vha); |
9a069e19 GM |
717 | } |
718 | } | |
719 | ||
7d613ac6 SV |
720 | /* Load the NIC Core f/w if we are the first protocol driver. */ |
721 | if (IS_QLA8031(ha)) { | |
722 | rval = qla83xx_nic_core_fw_load(vha); | |
723 | if (rval) | |
724 | ql_log(ql_log_warn, vha, 0x0124, | |
725 | "Error in initializing NIC Core f/w.\n"); | |
726 | } | |
727 | ||
2f0f3f4f MI |
728 | if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha)) |
729 | qla24xx_read_fcp_prio_cfg(vha); | |
09ff701a | 730 | |
c46e65c7 JC |
731 | if (IS_P3P_TYPE(ha)) |
732 | qla82xx_set_driver_version(vha, QLA2XXX_VERSION); | |
733 | else | |
734 | qla25xx_set_driver_version(vha, QLA2XXX_VERSION); | |
735 | ||
1da177e4 LT |
736 | return (rval); |
737 | } | |
738 | ||
739 | /** | |
abbd8870 | 740 | * qla2100_pci_config() - Setup ISP21xx PCI configuration registers. |
1da177e4 LT |
741 | * @ha: HA context |
742 | * | |
743 | * Returns 0 on success. | |
744 | */ | |
abbd8870 | 745 | int |
e315cd28 | 746 | qla2100_pci_config(scsi_qla_host_t *vha) |
1da177e4 | 747 | { |
a157b101 | 748 | uint16_t w; |
abbd8870 | 749 | unsigned long flags; |
e315cd28 | 750 | struct qla_hw_data *ha = vha->hw; |
3d71644c | 751 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
1da177e4 | 752 | |
1da177e4 | 753 | pci_set_master(ha->pdev); |
af6177d8 | 754 | pci_try_set_mwi(ha->pdev); |
1da177e4 | 755 | |
1da177e4 | 756 | pci_read_config_word(ha->pdev, PCI_COMMAND, &w); |
a157b101 | 757 | w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); |
abbd8870 AV |
758 | pci_write_config_word(ha->pdev, PCI_COMMAND, w); |
759 | ||
737faece | 760 | pci_disable_rom(ha->pdev); |
1da177e4 LT |
761 | |
762 | /* Get PCI bus information. */ | |
763 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
3d71644c | 764 | ha->pci_attr = RD_REG_WORD(®->ctrl_status); |
1da177e4 LT |
765 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
766 | ||
abbd8870 AV |
767 | return QLA_SUCCESS; |
768 | } | |
1da177e4 | 769 | |
abbd8870 AV |
770 | /** |
771 | * qla2300_pci_config() - Setup ISP23xx PCI configuration registers. | |
772 | * @ha: HA context | |
773 | * | |
774 | * Returns 0 on success. | |
775 | */ | |
776 | int | |
e315cd28 | 777 | qla2300_pci_config(scsi_qla_host_t *vha) |
abbd8870 | 778 | { |
a157b101 | 779 | uint16_t w; |
abbd8870 AV |
780 | unsigned long flags = 0; |
781 | uint32_t cnt; | |
e315cd28 | 782 | struct qla_hw_data *ha = vha->hw; |
3d71644c | 783 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
1da177e4 | 784 | |
abbd8870 | 785 | pci_set_master(ha->pdev); |
af6177d8 | 786 | pci_try_set_mwi(ha->pdev); |
1da177e4 | 787 | |
abbd8870 | 788 | pci_read_config_word(ha->pdev, PCI_COMMAND, &w); |
a157b101 | 789 | w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); |
1da177e4 | 790 | |
abbd8870 AV |
791 | if (IS_QLA2322(ha) || IS_QLA6322(ha)) |
792 | w &= ~PCI_COMMAND_INTX_DISABLE; | |
a157b101 | 793 | pci_write_config_word(ha->pdev, PCI_COMMAND, w); |
1da177e4 | 794 | |
abbd8870 AV |
795 | /* |
796 | * If this is a 2300 card and not 2312, reset the | |
797 | * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately, | |
798 | * the 2310 also reports itself as a 2300 so we need to get the | |
799 | * fb revision level -- a 6 indicates it really is a 2300 and | |
800 | * not a 2310. | |
801 | */ | |
802 | if (IS_QLA2300(ha)) { | |
803 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1da177e4 | 804 | |
abbd8870 | 805 | /* Pause RISC. */ |
3d71644c | 806 | WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); |
abbd8870 | 807 | for (cnt = 0; cnt < 30000; cnt++) { |
3d71644c | 808 | if ((RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) != 0) |
abbd8870 | 809 | break; |
1da177e4 | 810 | |
abbd8870 AV |
811 | udelay(10); |
812 | } | |
1da177e4 | 813 | |
abbd8870 | 814 | /* Select FPM registers. */ |
3d71644c AV |
815 | WRT_REG_WORD(®->ctrl_status, 0x20); |
816 | RD_REG_WORD(®->ctrl_status); | |
abbd8870 AV |
817 | |
818 | /* Get the fb rev level */ | |
3d71644c | 819 | ha->fb_rev = RD_FB_CMD_REG(ha, reg); |
abbd8870 AV |
820 | |
821 | if (ha->fb_rev == FPM_2300) | |
a157b101 | 822 | pci_clear_mwi(ha->pdev); |
abbd8870 AV |
823 | |
824 | /* Deselect FPM registers. */ | |
3d71644c AV |
825 | WRT_REG_WORD(®->ctrl_status, 0x0); |
826 | RD_REG_WORD(®->ctrl_status); | |
abbd8870 AV |
827 | |
828 | /* Release RISC module. */ | |
3d71644c | 829 | WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); |
abbd8870 | 830 | for (cnt = 0; cnt < 30000; cnt++) { |
3d71644c | 831 | if ((RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0) |
abbd8870 AV |
832 | break; |
833 | ||
834 | udelay(10); | |
1da177e4 | 835 | } |
1da177e4 | 836 | |
abbd8870 AV |
837 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
838 | } | |
1da177e4 | 839 | |
abbd8870 AV |
840 | pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80); |
841 | ||
737faece | 842 | pci_disable_rom(ha->pdev); |
1da177e4 | 843 | |
abbd8870 AV |
844 | /* Get PCI bus information. */ |
845 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
3d71644c | 846 | ha->pci_attr = RD_REG_WORD(®->ctrl_status); |
abbd8870 AV |
847 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
848 | ||
849 | return QLA_SUCCESS; | |
1da177e4 LT |
850 | } |
851 | ||
0107109e AV |
852 | /** |
853 | * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers. | |
854 | * @ha: HA context | |
855 | * | |
856 | * Returns 0 on success. | |
857 | */ | |
858 | int | |
e315cd28 | 859 | qla24xx_pci_config(scsi_qla_host_t *vha) |
0107109e | 860 | { |
a157b101 | 861 | uint16_t w; |
0107109e | 862 | unsigned long flags = 0; |
e315cd28 | 863 | struct qla_hw_data *ha = vha->hw; |
0107109e | 864 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
0107109e AV |
865 | |
866 | pci_set_master(ha->pdev); | |
af6177d8 | 867 | pci_try_set_mwi(ha->pdev); |
0107109e AV |
868 | |
869 | pci_read_config_word(ha->pdev, PCI_COMMAND, &w); | |
a157b101 | 870 | w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); |
0107109e AV |
871 | w &= ~PCI_COMMAND_INTX_DISABLE; |
872 | pci_write_config_word(ha->pdev, PCI_COMMAND, w); | |
873 | ||
874 | pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80); | |
875 | ||
876 | /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */ | |
f85ec187 AV |
877 | if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX)) |
878 | pcix_set_mmrbc(ha->pdev, 2048); | |
0107109e AV |
879 | |
880 | /* PCIe -- adjust Maximum Read Request Size (2048). */ | |
e67f1321 | 881 | if (pci_is_pcie(ha->pdev)) |
5ffd3a52 | 882 | pcie_set_readrq(ha->pdev, 4096); |
0107109e | 883 | |
737faece | 884 | pci_disable_rom(ha->pdev); |
0107109e | 885 | |
44c10138 | 886 | ha->chip_revision = ha->pdev->revision; |
a8488abe | 887 | |
0107109e AV |
888 | /* Get PCI bus information. */ |
889 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
890 | ha->pci_attr = RD_REG_DWORD(®->ctrl_status); | |
891 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
892 | ||
893 | return QLA_SUCCESS; | |
894 | } | |
895 | ||
c3a2f0df AV |
896 | /** |
897 | * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers. | |
898 | * @ha: HA context | |
899 | * | |
900 | * Returns 0 on success. | |
901 | */ | |
902 | int | |
e315cd28 | 903 | qla25xx_pci_config(scsi_qla_host_t *vha) |
c3a2f0df AV |
904 | { |
905 | uint16_t w; | |
e315cd28 | 906 | struct qla_hw_data *ha = vha->hw; |
c3a2f0df AV |
907 | |
908 | pci_set_master(ha->pdev); | |
909 | pci_try_set_mwi(ha->pdev); | |
910 | ||
911 | pci_read_config_word(ha->pdev, PCI_COMMAND, &w); | |
912 | w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); | |
913 | w &= ~PCI_COMMAND_INTX_DISABLE; | |
914 | pci_write_config_word(ha->pdev, PCI_COMMAND, w); | |
915 | ||
916 | /* PCIe -- adjust Maximum Read Request Size (2048). */ | |
e67f1321 | 917 | if (pci_is_pcie(ha->pdev)) |
5ffd3a52 | 918 | pcie_set_readrq(ha->pdev, 4096); |
c3a2f0df | 919 | |
737faece | 920 | pci_disable_rom(ha->pdev); |
c3a2f0df AV |
921 | |
922 | ha->chip_revision = ha->pdev->revision; | |
923 | ||
924 | return QLA_SUCCESS; | |
925 | } | |
926 | ||
1da177e4 LT |
927 | /** |
928 | * qla2x00_isp_firmware() - Choose firmware image. | |
929 | * @ha: HA context | |
930 | * | |
931 | * Returns 0 on success. | |
932 | */ | |
933 | static int | |
e315cd28 | 934 | qla2x00_isp_firmware(scsi_qla_host_t *vha) |
1da177e4 LT |
935 | { |
936 | int rval; | |
42e421b1 AV |
937 | uint16_t loop_id, topo, sw_cap; |
938 | uint8_t domain, area, al_pa; | |
e315cd28 | 939 | struct qla_hw_data *ha = vha->hw; |
1da177e4 LT |
940 | |
941 | /* Assume loading risc code */ | |
fa2a1ce5 | 942 | rval = QLA_FUNCTION_FAILED; |
1da177e4 LT |
943 | |
944 | if (ha->flags.disable_risc_code_load) { | |
7c3df132 | 945 | ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n"); |
1da177e4 LT |
946 | |
947 | /* Verify checksum of loaded RISC code. */ | |
e315cd28 | 948 | rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address); |
42e421b1 AV |
949 | if (rval == QLA_SUCCESS) { |
950 | /* And, verify we are not in ROM code. */ | |
e315cd28 | 951 | rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa, |
42e421b1 AV |
952 | &area, &domain, &topo, &sw_cap); |
953 | } | |
1da177e4 LT |
954 | } |
955 | ||
7c3df132 SK |
956 | if (rval) |
957 | ql_dbg(ql_dbg_init, vha, 0x007a, | |
958 | "**** Load RISC code ****.\n"); | |
1da177e4 LT |
959 | |
960 | return (rval); | |
961 | } | |
962 | ||
963 | /** | |
964 | * qla2x00_reset_chip() - Reset ISP chip. | |
965 | * @ha: HA context | |
966 | * | |
967 | * Returns 0 on success. | |
968 | */ | |
abbd8870 | 969 | void |
e315cd28 | 970 | qla2x00_reset_chip(scsi_qla_host_t *vha) |
1da177e4 LT |
971 | { |
972 | unsigned long flags = 0; | |
e315cd28 | 973 | struct qla_hw_data *ha = vha->hw; |
3d71644c | 974 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
1da177e4 | 975 | uint32_t cnt; |
1da177e4 LT |
976 | uint16_t cmd; |
977 | ||
85880801 AV |
978 | if (unlikely(pci_channel_offline(ha->pdev))) |
979 | return; | |
980 | ||
fd34f556 | 981 | ha->isp_ops->disable_intrs(ha); |
1da177e4 LT |
982 | |
983 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
984 | ||
985 | /* Turn off master enable */ | |
986 | cmd = 0; | |
987 | pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd); | |
988 | cmd &= ~PCI_COMMAND_MASTER; | |
989 | pci_write_config_word(ha->pdev, PCI_COMMAND, cmd); | |
990 | ||
991 | if (!IS_QLA2100(ha)) { | |
992 | /* Pause RISC. */ | |
993 | WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); | |
994 | if (IS_QLA2200(ha) || IS_QLA2300(ha)) { | |
995 | for (cnt = 0; cnt < 30000; cnt++) { | |
996 | if ((RD_REG_WORD(®->hccr) & | |
997 | HCCR_RISC_PAUSE) != 0) | |
998 | break; | |
999 | udelay(100); | |
1000 | } | |
1001 | } else { | |
1002 | RD_REG_WORD(®->hccr); /* PCI Posting. */ | |
1003 | udelay(10); | |
1004 | } | |
1005 | ||
1006 | /* Select FPM registers. */ | |
1007 | WRT_REG_WORD(®->ctrl_status, 0x20); | |
1008 | RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ | |
1009 | ||
1010 | /* FPM Soft Reset. */ | |
1011 | WRT_REG_WORD(®->fpm_diag_config, 0x100); | |
1012 | RD_REG_WORD(®->fpm_diag_config); /* PCI Posting. */ | |
1013 | ||
1014 | /* Toggle Fpm Reset. */ | |
1015 | if (!IS_QLA2200(ha)) { | |
1016 | WRT_REG_WORD(®->fpm_diag_config, 0x0); | |
1017 | RD_REG_WORD(®->fpm_diag_config); /* PCI Posting. */ | |
1018 | } | |
1019 | ||
1020 | /* Select frame buffer registers. */ | |
1021 | WRT_REG_WORD(®->ctrl_status, 0x10); | |
1022 | RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ | |
1023 | ||
1024 | /* Reset frame buffer FIFOs. */ | |
1025 | if (IS_QLA2200(ha)) { | |
1026 | WRT_FB_CMD_REG(ha, reg, 0xa000); | |
1027 | RD_FB_CMD_REG(ha, reg); /* PCI Posting. */ | |
1028 | } else { | |
1029 | WRT_FB_CMD_REG(ha, reg, 0x00fc); | |
1030 | ||
1031 | /* Read back fb_cmd until zero or 3 seconds max */ | |
1032 | for (cnt = 0; cnt < 3000; cnt++) { | |
1033 | if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0) | |
1034 | break; | |
1035 | udelay(100); | |
1036 | } | |
1037 | } | |
1038 | ||
1039 | /* Select RISC module registers. */ | |
1040 | WRT_REG_WORD(®->ctrl_status, 0); | |
1041 | RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ | |
1042 | ||
1043 | /* Reset RISC processor. */ | |
1044 | WRT_REG_WORD(®->hccr, HCCR_RESET_RISC); | |
1045 | RD_REG_WORD(®->hccr); /* PCI Posting. */ | |
1046 | ||
1047 | /* Release RISC processor. */ | |
1048 | WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); | |
1049 | RD_REG_WORD(®->hccr); /* PCI Posting. */ | |
1050 | } | |
1051 | ||
1052 | WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); | |
1053 | WRT_REG_WORD(®->hccr, HCCR_CLR_HOST_INT); | |
1054 | ||
1055 | /* Reset ISP chip. */ | |
1056 | WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); | |
1057 | ||
1058 | /* Wait for RISC to recover from reset. */ | |
1059 | if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) { | |
1060 | /* | |
1061 | * It is necessary to for a delay here since the card doesn't | |
1062 | * respond to PCI reads during a reset. On some architectures | |
1063 | * this will result in an MCA. | |
1064 | */ | |
1065 | udelay(20); | |
1066 | for (cnt = 30000; cnt; cnt--) { | |
1067 | if ((RD_REG_WORD(®->ctrl_status) & | |
1068 | CSR_ISP_SOFT_RESET) == 0) | |
1069 | break; | |
1070 | udelay(100); | |
1071 | } | |
1072 | } else | |
1073 | udelay(10); | |
1074 | ||
1075 | /* Reset RISC processor. */ | |
1076 | WRT_REG_WORD(®->hccr, HCCR_RESET_RISC); | |
1077 | ||
1078 | WRT_REG_WORD(®->semaphore, 0); | |
1079 | ||
1080 | /* Release RISC processor. */ | |
1081 | WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); | |
1082 | RD_REG_WORD(®->hccr); /* PCI Posting. */ | |
1083 | ||
1084 | if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) { | |
1085 | for (cnt = 0; cnt < 30000; cnt++) { | |
ffb39f03 | 1086 | if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY) |
1da177e4 | 1087 | break; |
1da177e4 LT |
1088 | |
1089 | udelay(100); | |
1090 | } | |
1091 | } else | |
1092 | udelay(100); | |
1093 | ||
1094 | /* Turn on master enable */ | |
1095 | cmd |= PCI_COMMAND_MASTER; | |
1096 | pci_write_config_word(ha->pdev, PCI_COMMAND, cmd); | |
1097 | ||
1098 | /* Disable RISC pause on FPM parity error. */ | |
1099 | if (!IS_QLA2100(ha)) { | |
1100 | WRT_REG_WORD(®->hccr, HCCR_DISABLE_PARITY_PAUSE); | |
1101 | RD_REG_WORD(®->hccr); /* PCI Posting. */ | |
1102 | } | |
1103 | ||
1104 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1105 | } | |
1106 | ||
b1d46989 MI |
1107 | /** |
1108 | * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC. | |
1109 | * | |
1110 | * Returns 0 on success. | |
1111 | */ | |
fa492630 | 1112 | static int |
b1d46989 MI |
1113 | qla81xx_reset_mpi(scsi_qla_host_t *vha) |
1114 | { | |
1115 | uint16_t mb[4] = {0x1010, 0, 1, 0}; | |
1116 | ||
6246b8a1 GM |
1117 | if (!IS_QLA81XX(vha->hw)) |
1118 | return QLA_SUCCESS; | |
1119 | ||
b1d46989 MI |
1120 | return qla81xx_write_mpi_register(vha, mb); |
1121 | } | |
1122 | ||
0107109e | 1123 | /** |
88c26663 | 1124 | * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC. |
0107109e AV |
1125 | * @ha: HA context |
1126 | * | |
1127 | * Returns 0 on success. | |
1128 | */ | |
d14e72fb | 1129 | static inline int |
e315cd28 | 1130 | qla24xx_reset_risc(scsi_qla_host_t *vha) |
0107109e AV |
1131 | { |
1132 | unsigned long flags = 0; | |
e315cd28 | 1133 | struct qla_hw_data *ha = vha->hw; |
0107109e | 1134 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
52c82823 | 1135 | uint32_t cnt; |
335a1cc9 | 1136 | uint16_t wd; |
b1d46989 | 1137 | static int abts_cnt; /* ISP abort retry counts */ |
d14e72fb | 1138 | int rval = QLA_SUCCESS; |
0107109e | 1139 | |
0107109e AV |
1140 | spin_lock_irqsave(&ha->hardware_lock, flags); |
1141 | ||
1142 | /* Reset RISC. */ | |
1143 | WRT_REG_DWORD(®->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); | |
1144 | for (cnt = 0; cnt < 30000; cnt++) { | |
1145 | if ((RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0) | |
1146 | break; | |
1147 | ||
1148 | udelay(10); | |
1149 | } | |
1150 | ||
d14e72fb HM |
1151 | if (!(RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE)) |
1152 | set_bit(DMA_SHUTDOWN_CMPL, &ha->fw_dump_cap_flags); | |
1153 | ||
1154 | ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017e, | |
1155 | "HCCR: 0x%x, Control Status %x, DMA active status:0x%x\n", | |
1156 | RD_REG_DWORD(®->hccr), | |
1157 | RD_REG_DWORD(®->ctrl_status), | |
1158 | (RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE)); | |
1159 | ||
0107109e AV |
1160 | WRT_REG_DWORD(®->ctrl_status, |
1161 | CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); | |
335a1cc9 | 1162 | pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); |
88c26663 | 1163 | |
335a1cc9 | 1164 | udelay(100); |
d14e72fb | 1165 | |
88c26663 | 1166 | /* Wait for firmware to complete NVRAM accesses. */ |
52c82823 | 1167 | RD_REG_WORD(®->mailbox0); |
d14e72fb HM |
1168 | for (cnt = 10000; RD_REG_WORD(®->mailbox0) != 0 && |
1169 | rval == QLA_SUCCESS; cnt--) { | |
88c26663 | 1170 | barrier(); |
d14e72fb HM |
1171 | if (cnt) |
1172 | udelay(5); | |
1173 | else | |
1174 | rval = QLA_FUNCTION_TIMEOUT; | |
88c26663 AV |
1175 | } |
1176 | ||
d14e72fb HM |
1177 | if (rval == QLA_SUCCESS) |
1178 | set_bit(ISP_MBX_RDY, &ha->fw_dump_cap_flags); | |
1179 | ||
1180 | ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017f, | |
1181 | "HCCR: 0x%x, MailBox0 Status 0x%x\n", | |
1182 | RD_REG_DWORD(®->hccr), | |
1183 | RD_REG_DWORD(®->mailbox0)); | |
1184 | ||
335a1cc9 | 1185 | /* Wait for soft-reset to complete. */ |
52c82823 | 1186 | RD_REG_DWORD(®->ctrl_status); |
d14e72fb | 1187 | for (cnt = 0; cnt < 6000000; cnt++) { |
0107109e | 1188 | barrier(); |
d14e72fb HM |
1189 | if ((RD_REG_DWORD(®->ctrl_status) & |
1190 | CSRX_ISP_SOFT_RESET) == 0) | |
1191 | break; | |
1192 | ||
1193 | udelay(5); | |
0107109e | 1194 | } |
d14e72fb HM |
1195 | if (!(RD_REG_DWORD(®->ctrl_status) & CSRX_ISP_SOFT_RESET)) |
1196 | set_bit(ISP_SOFT_RESET_CMPL, &ha->fw_dump_cap_flags); | |
1197 | ||
1198 | ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015d, | |
1199 | "HCCR: 0x%x, Soft Reset status: 0x%x\n", | |
1200 | RD_REG_DWORD(®->hccr), | |
1201 | RD_REG_DWORD(®->ctrl_status)); | |
0107109e | 1202 | |
b1d46989 MI |
1203 | /* If required, do an MPI FW reset now */ |
1204 | if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) { | |
1205 | if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) { | |
1206 | if (++abts_cnt < 5) { | |
1207 | set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); | |
1208 | set_bit(MPI_RESET_NEEDED, &vha->dpc_flags); | |
1209 | } else { | |
1210 | /* | |
1211 | * We exhausted the ISP abort retries. We have to | |
1212 | * set the board offline. | |
1213 | */ | |
1214 | abts_cnt = 0; | |
1215 | vha->flags.online = 0; | |
1216 | } | |
1217 | } | |
1218 | } | |
1219 | ||
0107109e AV |
1220 | WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_RESET); |
1221 | RD_REG_DWORD(®->hccr); | |
1222 | ||
1223 | WRT_REG_DWORD(®->hccr, HCCRX_REL_RISC_PAUSE); | |
1224 | RD_REG_DWORD(®->hccr); | |
1225 | ||
1226 | WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET); | |
1227 | RD_REG_DWORD(®->hccr); | |
1228 | ||
52c82823 | 1229 | RD_REG_WORD(®->mailbox0); |
d14e72fb HM |
1230 | for (cnt = 6000000; RD_REG_WORD(®->mailbox0) != 0 && |
1231 | rval == QLA_SUCCESS; cnt--) { | |
0107109e | 1232 | barrier(); |
d14e72fb HM |
1233 | if (cnt) |
1234 | udelay(5); | |
1235 | else | |
1236 | rval = QLA_FUNCTION_TIMEOUT; | |
0107109e | 1237 | } |
d14e72fb HM |
1238 | if (rval == QLA_SUCCESS) |
1239 | set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags); | |
1240 | ||
1241 | ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015e, | |
1242 | "Host Risc 0x%x, mailbox0 0x%x\n", | |
1243 | RD_REG_DWORD(®->hccr), | |
1244 | RD_REG_WORD(®->mailbox0)); | |
0107109e AV |
1245 | |
1246 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
124f85e6 | 1247 | |
d14e72fb HM |
1248 | ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015f, |
1249 | "Driver in %s mode\n", | |
1250 | IS_NOPOLLING_TYPE(ha) ? "Interrupt" : "Polling"); | |
1251 | ||
124f85e6 AV |
1252 | if (IS_NOPOLLING_TYPE(ha)) |
1253 | ha->isp_ops->enable_intrs(ha); | |
d14e72fb HM |
1254 | |
1255 | return rval; | |
0107109e AV |
1256 | } |
1257 | ||
4ea2c9c7 JC |
1258 | static void |
1259 | qla25xx_read_risc_sema_reg(scsi_qla_host_t *vha, uint32_t *data) | |
1260 | { | |
1261 | struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24; | |
1262 | ||
1263 | WRT_REG_DWORD(®->iobase_addr, RISC_REGISTER_BASE_OFFSET); | |
1264 | *data = RD_REG_DWORD(®->iobase_window + RISC_REGISTER_WINDOW_OFFET); | |
1265 | ||
1266 | } | |
1267 | ||
1268 | static void | |
1269 | qla25xx_write_risc_sema_reg(scsi_qla_host_t *vha, uint32_t data) | |
1270 | { | |
1271 | struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24; | |
1272 | ||
1273 | WRT_REG_DWORD(®->iobase_addr, RISC_REGISTER_BASE_OFFSET); | |
1274 | WRT_REG_DWORD(®->iobase_window + RISC_REGISTER_WINDOW_OFFET, data); | |
1275 | } | |
1276 | ||
1277 | static void | |
1278 | qla25xx_manipulate_risc_semaphore(scsi_qla_host_t *vha) | |
1279 | { | |
4ea2c9c7 JC |
1280 | uint32_t wd32 = 0; |
1281 | uint delta_msec = 100; | |
1282 | uint elapsed_msec = 0; | |
1283 | uint timeout_msec; | |
1284 | ulong n; | |
1285 | ||
cc790764 JC |
1286 | if (vha->hw->pdev->subsystem_device != 0x0175 && |
1287 | vha->hw->pdev->subsystem_device != 0x0240) | |
4ea2c9c7 JC |
1288 | return; |
1289 | ||
8dd7e3a5 JC |
1290 | WRT_REG_DWORD(&vha->hw->iobase->isp24.hccr, HCCRX_SET_RISC_PAUSE); |
1291 | udelay(100); | |
1292 | ||
4ea2c9c7 JC |
1293 | attempt: |
1294 | timeout_msec = TIMEOUT_SEMAPHORE; | |
1295 | n = timeout_msec / delta_msec; | |
1296 | while (n--) { | |
1297 | qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_SET); | |
1298 | qla25xx_read_risc_sema_reg(vha, &wd32); | |
1299 | if (wd32 & RISC_SEMAPHORE) | |
1300 | break; | |
1301 | msleep(delta_msec); | |
1302 | elapsed_msec += delta_msec; | |
1303 | if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED) | |
1304 | goto force; | |
1305 | } | |
1306 | ||
1307 | if (!(wd32 & RISC_SEMAPHORE)) | |
1308 | goto force; | |
1309 | ||
1310 | if (!(wd32 & RISC_SEMAPHORE_FORCE)) | |
1311 | goto acquired; | |
1312 | ||
1313 | qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_CLR); | |
1314 | timeout_msec = TIMEOUT_SEMAPHORE_FORCE; | |
1315 | n = timeout_msec / delta_msec; | |
1316 | while (n--) { | |
1317 | qla25xx_read_risc_sema_reg(vha, &wd32); | |
1318 | if (!(wd32 & RISC_SEMAPHORE_FORCE)) | |
1319 | break; | |
1320 | msleep(delta_msec); | |
1321 | elapsed_msec += delta_msec; | |
1322 | if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED) | |
1323 | goto force; | |
1324 | } | |
1325 | ||
1326 | if (wd32 & RISC_SEMAPHORE_FORCE) | |
1327 | qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_CLR); | |
1328 | ||
1329 | goto attempt; | |
1330 | ||
1331 | force: | |
1332 | qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_SET); | |
1333 | ||
1334 | acquired: | |
1335 | return; | |
1336 | } | |
1337 | ||
88c26663 AV |
1338 | /** |
1339 | * qla24xx_reset_chip() - Reset ISP24xx chip. | |
1340 | * @ha: HA context | |
1341 | * | |
1342 | * Returns 0 on success. | |
1343 | */ | |
1344 | void | |
e315cd28 | 1345 | qla24xx_reset_chip(scsi_qla_host_t *vha) |
88c26663 | 1346 | { |
e315cd28 | 1347 | struct qla_hw_data *ha = vha->hw; |
85880801 AV |
1348 | |
1349 | if (pci_channel_offline(ha->pdev) && | |
1350 | ha->flags.pci_channel_io_perm_failure) { | |
1351 | return; | |
1352 | } | |
1353 | ||
fd34f556 | 1354 | ha->isp_ops->disable_intrs(ha); |
88c26663 | 1355 | |
4ea2c9c7 JC |
1356 | qla25xx_manipulate_risc_semaphore(vha); |
1357 | ||
88c26663 | 1358 | /* Perform RISC reset. */ |
e315cd28 | 1359 | qla24xx_reset_risc(vha); |
88c26663 AV |
1360 | } |
1361 | ||
1da177e4 LT |
1362 | /** |
1363 | * qla2x00_chip_diag() - Test chip for proper operation. | |
1364 | * @ha: HA context | |
1365 | * | |
1366 | * Returns 0 on success. | |
1367 | */ | |
abbd8870 | 1368 | int |
e315cd28 | 1369 | qla2x00_chip_diag(scsi_qla_host_t *vha) |
1da177e4 LT |
1370 | { |
1371 | int rval; | |
e315cd28 | 1372 | struct qla_hw_data *ha = vha->hw; |
3d71644c | 1373 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
1da177e4 LT |
1374 | unsigned long flags = 0; |
1375 | uint16_t data; | |
1376 | uint32_t cnt; | |
1377 | uint16_t mb[5]; | |
73208dfd | 1378 | struct req_que *req = ha->req_q_map[0]; |
1da177e4 LT |
1379 | |
1380 | /* Assume a failed state */ | |
1381 | rval = QLA_FUNCTION_FAILED; | |
1382 | ||
7c3df132 SK |
1383 | ql_dbg(ql_dbg_init, vha, 0x007b, |
1384 | "Testing device at %lx.\n", (u_long)®->flash_address); | |
1da177e4 LT |
1385 | |
1386 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1387 | ||
1388 | /* Reset ISP chip. */ | |
1389 | WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); | |
1390 | ||
1391 | /* | |
1392 | * We need to have a delay here since the card will not respond while | |
1393 | * in reset causing an MCA on some architectures. | |
1394 | */ | |
1395 | udelay(20); | |
1396 | data = qla2x00_debounce_register(®->ctrl_status); | |
1397 | for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) { | |
1398 | udelay(5); | |
1399 | data = RD_REG_WORD(®->ctrl_status); | |
1400 | barrier(); | |
1401 | } | |
1402 | ||
1403 | if (!cnt) | |
1404 | goto chip_diag_failed; | |
1405 | ||
7c3df132 SK |
1406 | ql_dbg(ql_dbg_init, vha, 0x007c, |
1407 | "Reset register cleared by chip reset.\n"); | |
1da177e4 LT |
1408 | |
1409 | /* Reset RISC processor. */ | |
1410 | WRT_REG_WORD(®->hccr, HCCR_RESET_RISC); | |
1411 | WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); | |
1412 | ||
1413 | /* Workaround for QLA2312 PCI parity error */ | |
1414 | if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) { | |
1415 | data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0)); | |
1416 | for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) { | |
1417 | udelay(5); | |
1418 | data = RD_MAILBOX_REG(ha, reg, 0); | |
fa2a1ce5 | 1419 | barrier(); |
1da177e4 LT |
1420 | } |
1421 | } else | |
1422 | udelay(10); | |
1423 | ||
1424 | if (!cnt) | |
1425 | goto chip_diag_failed; | |
1426 | ||
1427 | /* Check product ID of chip */ | |
7c3df132 | 1428 | ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product Id of chip.\n"); |
1da177e4 LT |
1429 | |
1430 | mb[1] = RD_MAILBOX_REG(ha, reg, 1); | |
1431 | mb[2] = RD_MAILBOX_REG(ha, reg, 2); | |
1432 | mb[3] = RD_MAILBOX_REG(ha, reg, 3); | |
1433 | mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4)); | |
1434 | if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) || | |
1435 | mb[3] != PROD_ID_3) { | |
7c3df132 SK |
1436 | ql_log(ql_log_warn, vha, 0x0062, |
1437 | "Wrong product ID = 0x%x,0x%x,0x%x.\n", | |
1438 | mb[1], mb[2], mb[3]); | |
1da177e4 LT |
1439 | |
1440 | goto chip_diag_failed; | |
1441 | } | |
1442 | ha->product_id[0] = mb[1]; | |
1443 | ha->product_id[1] = mb[2]; | |
1444 | ha->product_id[2] = mb[3]; | |
1445 | ha->product_id[3] = mb[4]; | |
1446 | ||
1447 | /* Adjust fw RISC transfer size */ | |
73208dfd | 1448 | if (req->length > 1024) |
1da177e4 LT |
1449 | ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024; |
1450 | else | |
1451 | ha->fw_transfer_size = REQUEST_ENTRY_SIZE * | |
73208dfd | 1452 | req->length; |
1da177e4 LT |
1453 | |
1454 | if (IS_QLA2200(ha) && | |
1455 | RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) { | |
1456 | /* Limit firmware transfer size with a 2200A */ | |
7c3df132 | 1457 | ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n"); |
1da177e4 | 1458 | |
ea5b6382 | 1459 | ha->device_type |= DT_ISP2200A; |
1da177e4 LT |
1460 | ha->fw_transfer_size = 128; |
1461 | } | |
1462 | ||
1463 | /* Wrap Incoming Mailboxes Test. */ | |
1464 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1465 | ||
7c3df132 | 1466 | ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n"); |
e315cd28 | 1467 | rval = qla2x00_mbx_reg_test(vha); |
7c3df132 SK |
1468 | if (rval) |
1469 | ql_log(ql_log_warn, vha, 0x0080, | |
1470 | "Failed mailbox send register test.\n"); | |
1471 | else | |
1da177e4 LT |
1472 | /* Flag a successful rval */ |
1473 | rval = QLA_SUCCESS; | |
1da177e4 LT |
1474 | spin_lock_irqsave(&ha->hardware_lock, flags); |
1475 | ||
1476 | chip_diag_failed: | |
1477 | if (rval) | |
7c3df132 SK |
1478 | ql_log(ql_log_info, vha, 0x0081, |
1479 | "Chip diagnostics **** FAILED ****.\n"); | |
1da177e4 LT |
1480 | |
1481 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1482 | ||
1483 | return (rval); | |
1484 | } | |
1485 | ||
0107109e AV |
1486 | /** |
1487 | * qla24xx_chip_diag() - Test ISP24xx for proper operation. | |
1488 | * @ha: HA context | |
1489 | * | |
1490 | * Returns 0 on success. | |
1491 | */ | |
1492 | int | |
e315cd28 | 1493 | qla24xx_chip_diag(scsi_qla_host_t *vha) |
0107109e AV |
1494 | { |
1495 | int rval; | |
e315cd28 | 1496 | struct qla_hw_data *ha = vha->hw; |
73208dfd | 1497 | struct req_que *req = ha->req_q_map[0]; |
0107109e | 1498 | |
7ec0effd | 1499 | if (IS_P3P_TYPE(ha)) |
a9083016 GM |
1500 | return QLA_SUCCESS; |
1501 | ||
73208dfd | 1502 | ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length; |
0107109e | 1503 | |
e315cd28 | 1504 | rval = qla2x00_mbx_reg_test(vha); |
0107109e | 1505 | if (rval) { |
7c3df132 SK |
1506 | ql_log(ql_log_warn, vha, 0x0082, |
1507 | "Failed mailbox send register test.\n"); | |
0107109e AV |
1508 | } else { |
1509 | /* Flag a successful rval */ | |
1510 | rval = QLA_SUCCESS; | |
1511 | } | |
1512 | ||
1513 | return rval; | |
1514 | } | |
1515 | ||
a7a167bf | 1516 | void |
e315cd28 | 1517 | qla2x00_alloc_fw_dump(scsi_qla_host_t *vha) |
0107109e | 1518 | { |
a7a167bf AV |
1519 | int rval; |
1520 | uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size, | |
73208dfd | 1521 | eft_size, fce_size, mq_size; |
df613b96 AV |
1522 | dma_addr_t tc_dma; |
1523 | void *tc; | |
e315cd28 | 1524 | struct qla_hw_data *ha = vha->hw; |
73208dfd AC |
1525 | struct req_que *req = ha->req_q_map[0]; |
1526 | struct rsp_que *rsp = ha->rsp_q_map[0]; | |
a7a167bf AV |
1527 | |
1528 | if (ha->fw_dump) { | |
7c3df132 SK |
1529 | ql_dbg(ql_dbg_init, vha, 0x00bd, |
1530 | "Firmware dump already allocated.\n"); | |
a7a167bf AV |
1531 | return; |
1532 | } | |
d4e3e04d | 1533 | |
0107109e | 1534 | ha->fw_dumped = 0; |
61f098dd | 1535 | ha->fw_dump_cap_flags = 0; |
f73cb695 CD |
1536 | dump_size = fixed_size = mem_size = eft_size = fce_size = mq_size = 0; |
1537 | req_q_size = rsp_q_size = 0; | |
1538 | ||
1539 | if (IS_QLA27XX(ha)) | |
1540 | goto try_fce; | |
1541 | ||
d4e3e04d | 1542 | if (IS_QLA2100(ha) || IS_QLA2200(ha)) { |
a7a167bf | 1543 | fixed_size = sizeof(struct qla2100_fw_dump); |
d4e3e04d | 1544 | } else if (IS_QLA23XX(ha)) { |
a7a167bf AV |
1545 | fixed_size = offsetof(struct qla2300_fw_dump, data_ram); |
1546 | mem_size = (ha->fw_memory_size - 0x11000 + 1) * | |
1547 | sizeof(uint16_t); | |
e428924c | 1548 | } else if (IS_FWI2_CAPABLE(ha)) { |
b20f02e1 | 1549 | if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) |
6246b8a1 GM |
1550 | fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem); |
1551 | else if (IS_QLA81XX(ha)) | |
3a03eb79 AV |
1552 | fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem); |
1553 | else if (IS_QLA25XX(ha)) | |
1554 | fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem); | |
1555 | else | |
1556 | fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem); | |
f73cb695 | 1557 | |
a7a167bf AV |
1558 | mem_size = (ha->fw_memory_size - 0x100000 + 1) * |
1559 | sizeof(uint32_t); | |
050c9bb1 | 1560 | if (ha->mqenable) { |
b20f02e1 | 1561 | if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha)) |
6246b8a1 | 1562 | mq_size = sizeof(struct qla2xxx_mq_chain); |
050c9bb1 GM |
1563 | /* |
1564 | * Allocate maximum buffer size for all queues. | |
1565 | * Resizing must be done at end-of-dump processing. | |
1566 | */ | |
1567 | mq_size += ha->max_req_queues * | |
1568 | (req->length * sizeof(request_t)); | |
1569 | mq_size += ha->max_rsp_queues * | |
1570 | (rsp->length * sizeof(response_t)); | |
1571 | } | |
00876ae8 | 1572 | if (ha->tgt.atio_ring) |
2d70c103 | 1573 | mq_size += ha->tgt.atio_q_length * sizeof(request_t); |
df613b96 | 1574 | /* Allocate memory for Fibre Channel Event Buffer. */ |
f73cb695 CD |
1575 | if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) && |
1576 | !IS_QLA27XX(ha)) | |
436a7b11 | 1577 | goto try_eft; |
df613b96 | 1578 | |
f73cb695 CD |
1579 | try_fce: |
1580 | if (ha->fce) | |
1581 | dma_free_coherent(&ha->pdev->dev, | |
1582 | FCE_SIZE, ha->fce, ha->fce_dma); | |
1583 | ||
1584 | /* Allocate memory for Fibre Channel Event Buffer. */ | |
0ea85b50 JP |
1585 | tc = dma_zalloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma, |
1586 | GFP_KERNEL); | |
df613b96 | 1587 | if (!tc) { |
7c3df132 SK |
1588 | ql_log(ql_log_warn, vha, 0x00be, |
1589 | "Unable to allocate (%d KB) for FCE.\n", | |
1590 | FCE_SIZE / 1024); | |
17d98630 | 1591 | goto try_eft; |
df613b96 AV |
1592 | } |
1593 | ||
e315cd28 | 1594 | rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS, |
df613b96 AV |
1595 | ha->fce_mb, &ha->fce_bufs); |
1596 | if (rval) { | |
7c3df132 SK |
1597 | ql_log(ql_log_warn, vha, 0x00bf, |
1598 | "Unable to initialize FCE (%d).\n", rval); | |
df613b96 AV |
1599 | dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc, |
1600 | tc_dma); | |
1601 | ha->flags.fce_enabled = 0; | |
17d98630 | 1602 | goto try_eft; |
df613b96 | 1603 | } |
cfb0919c | 1604 | ql_dbg(ql_dbg_init, vha, 0x00c0, |
7c3df132 | 1605 | "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024); |
df613b96 | 1606 | |
7d9dade3 | 1607 | fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE; |
df613b96 AV |
1608 | ha->flags.fce_enabled = 1; |
1609 | ha->fce_dma = tc_dma; | |
1610 | ha->fce = tc; | |
f73cb695 | 1611 | |
436a7b11 | 1612 | try_eft: |
f73cb695 CD |
1613 | if (ha->eft) |
1614 | dma_free_coherent(&ha->pdev->dev, | |
1615 | EFT_SIZE, ha->eft, ha->eft_dma); | |
1616 | ||
436a7b11 | 1617 | /* Allocate memory for Extended Trace Buffer. */ |
0ea85b50 JP |
1618 | tc = dma_zalloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma, |
1619 | GFP_KERNEL); | |
436a7b11 | 1620 | if (!tc) { |
7c3df132 SK |
1621 | ql_log(ql_log_warn, vha, 0x00c1, |
1622 | "Unable to allocate (%d KB) for EFT.\n", | |
1623 | EFT_SIZE / 1024); | |
436a7b11 AV |
1624 | goto cont_alloc; |
1625 | } | |
1626 | ||
e315cd28 | 1627 | rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS); |
436a7b11 | 1628 | if (rval) { |
7c3df132 SK |
1629 | ql_log(ql_log_warn, vha, 0x00c2, |
1630 | "Unable to initialize EFT (%d).\n", rval); | |
436a7b11 AV |
1631 | dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc, |
1632 | tc_dma); | |
1633 | goto cont_alloc; | |
1634 | } | |
cfb0919c | 1635 | ql_dbg(ql_dbg_init, vha, 0x00c3, |
7c3df132 | 1636 | "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024); |
436a7b11 AV |
1637 | |
1638 | eft_size = EFT_SIZE; | |
1639 | ha->eft_dma = tc_dma; | |
1640 | ha->eft = tc; | |
d4e3e04d | 1641 | } |
f73cb695 | 1642 | |
a7a167bf | 1643 | cont_alloc: |
f73cb695 CD |
1644 | if (IS_QLA27XX(ha)) { |
1645 | if (!ha->fw_dump_template) { | |
1646 | ql_log(ql_log_warn, vha, 0x00ba, | |
1647 | "Failed missing fwdump template\n"); | |
1648 | return; | |
1649 | } | |
1650 | dump_size = qla27xx_fwdt_calculate_dump_size(vha); | |
1651 | ql_dbg(ql_dbg_init, vha, 0x00fa, | |
1652 | "-> allocating fwdump (%x bytes)...\n", dump_size); | |
1653 | goto allocate; | |
1654 | } | |
1655 | ||
73208dfd AC |
1656 | req_q_size = req->length * sizeof(request_t); |
1657 | rsp_q_size = rsp->length * sizeof(response_t); | |
a7a167bf | 1658 | dump_size = offsetof(struct qla2xxx_fw_dump, isp); |
2afa19a9 | 1659 | dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size; |
bb99de67 AV |
1660 | ha->chain_offset = dump_size; |
1661 | dump_size += mq_size + fce_size; | |
d4e3e04d | 1662 | |
f73cb695 | 1663 | allocate: |
d4e3e04d | 1664 | ha->fw_dump = vmalloc(dump_size); |
a7a167bf | 1665 | if (!ha->fw_dump) { |
7c3df132 SK |
1666 | ql_log(ql_log_warn, vha, 0x00c4, |
1667 | "Unable to allocate (%d KB) for firmware dump.\n", | |
1668 | dump_size / 1024); | |
a7a167bf | 1669 | |
e30d1756 MI |
1670 | if (ha->fce) { |
1671 | dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce, | |
1672 | ha->fce_dma); | |
1673 | ha->fce = NULL; | |
1674 | ha->fce_dma = 0; | |
1675 | } | |
1676 | ||
a7a167bf AV |
1677 | if (ha->eft) { |
1678 | dma_free_coherent(&ha->pdev->dev, eft_size, ha->eft, | |
1679 | ha->eft_dma); | |
1680 | ha->eft = NULL; | |
1681 | ha->eft_dma = 0; | |
1682 | } | |
1683 | return; | |
1684 | } | |
f73cb695 | 1685 | ha->fw_dump_len = dump_size; |
cfb0919c | 1686 | ql_dbg(ql_dbg_init, vha, 0x00c5, |
7c3df132 | 1687 | "Allocated (%d KB) for firmware dump.\n", dump_size / 1024); |
a7a167bf | 1688 | |
f73cb695 CD |
1689 | if (IS_QLA27XX(ha)) |
1690 | return; | |
1691 | ||
a7a167bf AV |
1692 | ha->fw_dump->signature[0] = 'Q'; |
1693 | ha->fw_dump->signature[1] = 'L'; | |
1694 | ha->fw_dump->signature[2] = 'G'; | |
1695 | ha->fw_dump->signature[3] = 'C'; | |
ad950360 | 1696 | ha->fw_dump->version = htonl(1); |
a7a167bf AV |
1697 | |
1698 | ha->fw_dump->fixed_size = htonl(fixed_size); | |
1699 | ha->fw_dump->mem_size = htonl(mem_size); | |
1700 | ha->fw_dump->req_q_size = htonl(req_q_size); | |
1701 | ha->fw_dump->rsp_q_size = htonl(rsp_q_size); | |
1702 | ||
1703 | ha->fw_dump->eft_size = htonl(eft_size); | |
1704 | ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma)); | |
1705 | ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma)); | |
1706 | ||
1707 | ha->fw_dump->header_size = | |
1708 | htonl(offsetof(struct qla2xxx_fw_dump, isp)); | |
0107109e AV |
1709 | } |
1710 | ||
18e7555a AV |
1711 | static int |
1712 | qla81xx_mpi_sync(scsi_qla_host_t *vha) | |
1713 | { | |
1714 | #define MPS_MASK 0xe0 | |
1715 | int rval; | |
1716 | uint16_t dc; | |
1717 | uint32_t dw; | |
18e7555a AV |
1718 | |
1719 | if (!IS_QLA81XX(vha->hw)) | |
1720 | return QLA_SUCCESS; | |
1721 | ||
1722 | rval = qla2x00_write_ram_word(vha, 0x7c00, 1); | |
1723 | if (rval != QLA_SUCCESS) { | |
7c3df132 SK |
1724 | ql_log(ql_log_warn, vha, 0x0105, |
1725 | "Unable to acquire semaphore.\n"); | |
18e7555a AV |
1726 | goto done; |
1727 | } | |
1728 | ||
1729 | pci_read_config_word(vha->hw->pdev, 0x54, &dc); | |
1730 | rval = qla2x00_read_ram_word(vha, 0x7a15, &dw); | |
1731 | if (rval != QLA_SUCCESS) { | |
7c3df132 | 1732 | ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n"); |
18e7555a AV |
1733 | goto done_release; |
1734 | } | |
1735 | ||
1736 | dc &= MPS_MASK; | |
1737 | if (dc == (dw & MPS_MASK)) | |
1738 | goto done_release; | |
1739 | ||
1740 | dw &= ~MPS_MASK; | |
1741 | dw |= dc; | |
1742 | rval = qla2x00_write_ram_word(vha, 0x7a15, dw); | |
1743 | if (rval != QLA_SUCCESS) { | |
7c3df132 | 1744 | ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n"); |
18e7555a AV |
1745 | } |
1746 | ||
1747 | done_release: | |
1748 | rval = qla2x00_write_ram_word(vha, 0x7c00, 0); | |
1749 | if (rval != QLA_SUCCESS) { | |
7c3df132 SK |
1750 | ql_log(ql_log_warn, vha, 0x006d, |
1751 | "Unable to release semaphore.\n"); | |
18e7555a AV |
1752 | } |
1753 | ||
1754 | done: | |
1755 | return rval; | |
1756 | } | |
1757 | ||
8d93f550 CD |
1758 | int |
1759 | qla2x00_alloc_outstanding_cmds(struct qla_hw_data *ha, struct req_que *req) | |
1760 | { | |
1761 | /* Don't try to reallocate the array */ | |
1762 | if (req->outstanding_cmds) | |
1763 | return QLA_SUCCESS; | |
1764 | ||
1765 | if (!IS_FWI2_CAPABLE(ha) || (ha->mqiobase && | |
1766 | (ql2xmultique_tag || ql2xmaxqueues > 1))) | |
1767 | req->num_outstanding_cmds = DEFAULT_OUTSTANDING_COMMANDS; | |
1768 | else { | |
03e8c680 QT |
1769 | if (ha->cur_fw_xcb_count <= ha->cur_fw_iocb_count) |
1770 | req->num_outstanding_cmds = ha->cur_fw_xcb_count; | |
8d93f550 | 1771 | else |
03e8c680 | 1772 | req->num_outstanding_cmds = ha->cur_fw_iocb_count; |
8d93f550 CD |
1773 | } |
1774 | ||
1775 | req->outstanding_cmds = kzalloc(sizeof(srb_t *) * | |
1776 | req->num_outstanding_cmds, GFP_KERNEL); | |
1777 | ||
1778 | if (!req->outstanding_cmds) { | |
1779 | /* | |
1780 | * Try to allocate a minimal size just so we can get through | |
1781 | * initialization. | |
1782 | */ | |
1783 | req->num_outstanding_cmds = MIN_OUTSTANDING_COMMANDS; | |
1784 | req->outstanding_cmds = kzalloc(sizeof(srb_t *) * | |
1785 | req->num_outstanding_cmds, GFP_KERNEL); | |
1786 | ||
1787 | if (!req->outstanding_cmds) { | |
1788 | ql_log(ql_log_fatal, NULL, 0x0126, | |
1789 | "Failed to allocate memory for " | |
1790 | "outstanding_cmds for req_que %p.\n", req); | |
1791 | req->num_outstanding_cmds = 0; | |
1792 | return QLA_FUNCTION_FAILED; | |
1793 | } | |
1794 | } | |
1795 | ||
1796 | return QLA_SUCCESS; | |
1797 | } | |
1798 | ||
1da177e4 LT |
1799 | /** |
1800 | * qla2x00_setup_chip() - Load and start RISC firmware. | |
1801 | * @ha: HA context | |
1802 | * | |
1803 | * Returns 0 on success. | |
1804 | */ | |
1805 | static int | |
e315cd28 | 1806 | qla2x00_setup_chip(scsi_qla_host_t *vha) |
1da177e4 | 1807 | { |
0107109e AV |
1808 | int rval; |
1809 | uint32_t srisc_address = 0; | |
e315cd28 | 1810 | struct qla_hw_data *ha = vha->hw; |
3db0652e AV |
1811 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
1812 | unsigned long flags; | |
dda772e8 | 1813 | uint16_t fw_major_version; |
3db0652e | 1814 | |
7ec0effd | 1815 | if (IS_P3P_TYPE(ha)) { |
a9083016 | 1816 | rval = ha->isp_ops->load_risc(vha, &srisc_address); |
14e303d9 AV |
1817 | if (rval == QLA_SUCCESS) { |
1818 | qla2x00_stop_firmware(vha); | |
a9083016 | 1819 | goto enable_82xx_npiv; |
14e303d9 | 1820 | } else |
b963752f | 1821 | goto failed; |
a9083016 GM |
1822 | } |
1823 | ||
3db0652e AV |
1824 | if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) { |
1825 | /* Disable SRAM, Instruction RAM and GP RAM parity. */ | |
1826 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1827 | WRT_REG_WORD(®->hccr, (HCCR_ENABLE_PARITY + 0x0)); | |
1828 | RD_REG_WORD(®->hccr); | |
1829 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1830 | } | |
1da177e4 | 1831 | |
18e7555a AV |
1832 | qla81xx_mpi_sync(vha); |
1833 | ||
1da177e4 | 1834 | /* Load firmware sequences */ |
e315cd28 | 1835 | rval = ha->isp_ops->load_risc(vha, &srisc_address); |
0107109e | 1836 | if (rval == QLA_SUCCESS) { |
7c3df132 SK |
1837 | ql_dbg(ql_dbg_init, vha, 0x00c9, |
1838 | "Verifying Checksum of loaded RISC code.\n"); | |
1da177e4 | 1839 | |
e315cd28 | 1840 | rval = qla2x00_verify_checksum(vha, srisc_address); |
1da177e4 LT |
1841 | if (rval == QLA_SUCCESS) { |
1842 | /* Start firmware execution. */ | |
7c3df132 SK |
1843 | ql_dbg(ql_dbg_init, vha, 0x00ca, |
1844 | "Starting firmware.\n"); | |
1da177e4 | 1845 | |
b0d6cabd HM |
1846 | if (ql2xexlogins) |
1847 | ha->flags.exlogins_enabled = 1; | |
1848 | ||
2f56a7f1 HM |
1849 | if (ql2xexchoffld) |
1850 | ha->flags.exchoffld_enabled = 1; | |
1851 | ||
e315cd28 | 1852 | rval = qla2x00_execute_fw(vha, srisc_address); |
1da177e4 | 1853 | /* Retrieve firmware information. */ |
dda772e8 | 1854 | if (rval == QLA_SUCCESS) { |
b0d6cabd HM |
1855 | rval = qla2x00_set_exlogins_buffer(vha); |
1856 | if (rval != QLA_SUCCESS) | |
1857 | goto failed; | |
1858 | ||
2f56a7f1 HM |
1859 | rval = qla2x00_set_exchoffld_buffer(vha); |
1860 | if (rval != QLA_SUCCESS) | |
1861 | goto failed; | |
1862 | ||
a9083016 | 1863 | enable_82xx_npiv: |
dda772e8 | 1864 | fw_major_version = ha->fw_major_version; |
7ec0effd | 1865 | if (IS_P3P_TYPE(ha)) |
3173167f | 1866 | qla82xx_check_md_needed(vha); |
6246b8a1 GM |
1867 | else |
1868 | rval = qla2x00_get_fw_version(vha); | |
ca9e9c3e AV |
1869 | if (rval != QLA_SUCCESS) |
1870 | goto failed; | |
2c3dfe3f | 1871 | ha->flags.npiv_supported = 0; |
e315cd28 | 1872 | if (IS_QLA2XXX_MIDTYPE(ha) && |
946fb891 | 1873 | (ha->fw_attributes & BIT_2)) { |
2c3dfe3f | 1874 | ha->flags.npiv_supported = 1; |
4d0ea247 SJ |
1875 | if ((!ha->max_npiv_vports) || |
1876 | ((ha->max_npiv_vports + 1) % | |
eb66dc60 | 1877 | MIN_MULTI_ID_FABRIC)) |
4d0ea247 | 1878 | ha->max_npiv_vports = |
eb66dc60 | 1879 | MIN_MULTI_ID_FABRIC - 1; |
4d0ea247 | 1880 | } |
03e8c680 | 1881 | qla2x00_get_resource_cnts(vha); |
d743de66 | 1882 | |
8d93f550 CD |
1883 | /* |
1884 | * Allocate the array of outstanding commands | |
1885 | * now that we know the firmware resources. | |
1886 | */ | |
1887 | rval = qla2x00_alloc_outstanding_cmds(ha, | |
1888 | vha->req); | |
1889 | if (rval != QLA_SUCCESS) | |
1890 | goto failed; | |
1891 | ||
be5ea3cf | 1892 | if (!fw_major_version && ql2xallocfwdump |
7ec0effd | 1893 | && !(IS_P3P_TYPE(ha))) |
08de2844 | 1894 | qla2x00_alloc_fw_dump(vha); |
3b6e5b9d CD |
1895 | } else { |
1896 | goto failed; | |
1da177e4 LT |
1897 | } |
1898 | } else { | |
7c3df132 SK |
1899 | ql_log(ql_log_fatal, vha, 0x00cd, |
1900 | "ISP Firmware failed checksum.\n"); | |
1901 | goto failed; | |
1da177e4 | 1902 | } |
c74d88a4 AV |
1903 | } else |
1904 | goto failed; | |
1da177e4 | 1905 | |
3db0652e AV |
1906 | if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) { |
1907 | /* Enable proper parity. */ | |
1908 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1909 | if (IS_QLA2300(ha)) | |
1910 | /* SRAM parity */ | |
1911 | WRT_REG_WORD(®->hccr, HCCR_ENABLE_PARITY + 0x1); | |
1912 | else | |
1913 | /* SRAM, Instruction RAM and GP RAM parity */ | |
1914 | WRT_REG_WORD(®->hccr, HCCR_ENABLE_PARITY + 0x7); | |
1915 | RD_REG_WORD(®->hccr); | |
1916 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1917 | } | |
1918 | ||
f3982d89 CD |
1919 | if (IS_QLA27XX(ha)) |
1920 | ha->flags.fac_supported = 1; | |
1921 | else if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) { | |
1d2874de JC |
1922 | uint32_t size; |
1923 | ||
1924 | rval = qla81xx_fac_get_sector_size(vha, &size); | |
1925 | if (rval == QLA_SUCCESS) { | |
1926 | ha->flags.fac_supported = 1; | |
1927 | ha->fdt_block_size = size << 2; | |
1928 | } else { | |
7c3df132 | 1929 | ql_log(ql_log_warn, vha, 0x00ce, |
1d2874de JC |
1930 | "Unsupported FAC firmware (%d.%02d.%02d).\n", |
1931 | ha->fw_major_version, ha->fw_minor_version, | |
1932 | ha->fw_subminor_version); | |
1ca60e3b | 1933 | |
f73cb695 | 1934 | if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) { |
6246b8a1 GM |
1935 | ha->flags.fac_supported = 0; |
1936 | rval = QLA_SUCCESS; | |
1937 | } | |
1d2874de JC |
1938 | } |
1939 | } | |
ca9e9c3e | 1940 | failed: |
1da177e4 | 1941 | if (rval) { |
7c3df132 SK |
1942 | ql_log(ql_log_fatal, vha, 0x00cf, |
1943 | "Setup chip ****FAILED****.\n"); | |
1da177e4 LT |
1944 | } |
1945 | ||
1946 | return (rval); | |
1947 | } | |
1948 | ||
1949 | /** | |
1950 | * qla2x00_init_response_q_entries() - Initializes response queue entries. | |
1951 | * @ha: HA context | |
1952 | * | |
1953 | * Beginning of request ring has initialization control block already built | |
1954 | * by nvram config routine. | |
1955 | * | |
1956 | * Returns 0 on success. | |
1957 | */ | |
73208dfd AC |
1958 | void |
1959 | qla2x00_init_response_q_entries(struct rsp_que *rsp) | |
1da177e4 LT |
1960 | { |
1961 | uint16_t cnt; | |
1962 | response_t *pkt; | |
1963 | ||
2afa19a9 AC |
1964 | rsp->ring_ptr = rsp->ring; |
1965 | rsp->ring_index = 0; | |
1966 | rsp->status_srb = NULL; | |
e315cd28 AC |
1967 | pkt = rsp->ring_ptr; |
1968 | for (cnt = 0; cnt < rsp->length; cnt++) { | |
1da177e4 LT |
1969 | pkt->signature = RESPONSE_PROCESSED; |
1970 | pkt++; | |
1971 | } | |
1da177e4 LT |
1972 | } |
1973 | ||
1974 | /** | |
1975 | * qla2x00_update_fw_options() - Read and process firmware options. | |
1976 | * @ha: HA context | |
1977 | * | |
1978 | * Returns 0 on success. | |
1979 | */ | |
abbd8870 | 1980 | void |
e315cd28 | 1981 | qla2x00_update_fw_options(scsi_qla_host_t *vha) |
1da177e4 LT |
1982 | { |
1983 | uint16_t swing, emphasis, tx_sens, rx_sens; | |
e315cd28 | 1984 | struct qla_hw_data *ha = vha->hw; |
1da177e4 LT |
1985 | |
1986 | memset(ha->fw_options, 0, sizeof(ha->fw_options)); | |
e315cd28 | 1987 | qla2x00_get_fw_options(vha, ha->fw_options); |
1da177e4 LT |
1988 | |
1989 | if (IS_QLA2100(ha) || IS_QLA2200(ha)) | |
1990 | return; | |
1991 | ||
1992 | /* Serial Link options. */ | |
7c3df132 SK |
1993 | ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115, |
1994 | "Serial link options.\n"); | |
1995 | ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109, | |
1996 | (uint8_t *)&ha->fw_seriallink_options, | |
1997 | sizeof(ha->fw_seriallink_options)); | |
1da177e4 LT |
1998 | |
1999 | ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING; | |
2000 | if (ha->fw_seriallink_options[3] & BIT_2) { | |
2001 | ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING; | |
2002 | ||
2003 | /* 1G settings */ | |
2004 | swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0); | |
2005 | emphasis = (ha->fw_seriallink_options[2] & | |
2006 | (BIT_4 | BIT_3)) >> 3; | |
2007 | tx_sens = ha->fw_seriallink_options[0] & | |
fa2a1ce5 | 2008 | (BIT_3 | BIT_2 | BIT_1 | BIT_0); |
1da177e4 LT |
2009 | rx_sens = (ha->fw_seriallink_options[0] & |
2010 | (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4; | |
2011 | ha->fw_options[10] = (emphasis << 14) | (swing << 8); | |
2012 | if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { | |
2013 | if (rx_sens == 0x0) | |
2014 | rx_sens = 0x3; | |
2015 | ha->fw_options[10] |= (tx_sens << 4) | rx_sens; | |
2016 | } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) | |
2017 | ha->fw_options[10] |= BIT_5 | | |
2018 | ((rx_sens & (BIT_1 | BIT_0)) << 2) | | |
2019 | (tx_sens & (BIT_1 | BIT_0)); | |
2020 | ||
2021 | /* 2G settings */ | |
2022 | swing = (ha->fw_seriallink_options[2] & | |
2023 | (BIT_7 | BIT_6 | BIT_5)) >> 5; | |
2024 | emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0); | |
2025 | tx_sens = ha->fw_seriallink_options[1] & | |
fa2a1ce5 | 2026 | (BIT_3 | BIT_2 | BIT_1 | BIT_0); |
1da177e4 LT |
2027 | rx_sens = (ha->fw_seriallink_options[1] & |
2028 | (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4; | |
2029 | ha->fw_options[11] = (emphasis << 14) | (swing << 8); | |
2030 | if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { | |
2031 | if (rx_sens == 0x0) | |
2032 | rx_sens = 0x3; | |
2033 | ha->fw_options[11] |= (tx_sens << 4) | rx_sens; | |
2034 | } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) | |
2035 | ha->fw_options[11] |= BIT_5 | | |
2036 | ((rx_sens & (BIT_1 | BIT_0)) << 2) | | |
2037 | (tx_sens & (BIT_1 | BIT_0)); | |
2038 | } | |
2039 | ||
2040 | /* FCP2 options. */ | |
2041 | /* Return command IOCBs without waiting for an ABTS to complete. */ | |
2042 | ha->fw_options[3] |= BIT_13; | |
2043 | ||
2044 | /* LED scheme. */ | |
2045 | if (ha->flags.enable_led_scheme) | |
2046 | ha->fw_options[2] |= BIT_12; | |
2047 | ||
48c02fde AV |
2048 | /* Detect ISP6312. */ |
2049 | if (IS_QLA6312(ha)) | |
2050 | ha->fw_options[2] |= BIT_13; | |
2051 | ||
1da177e4 | 2052 | /* Update firmware options. */ |
e315cd28 | 2053 | qla2x00_set_fw_options(vha, ha->fw_options); |
1da177e4 LT |
2054 | } |
2055 | ||
0107109e | 2056 | void |
e315cd28 | 2057 | qla24xx_update_fw_options(scsi_qla_host_t *vha) |
0107109e AV |
2058 | { |
2059 | int rval; | |
e315cd28 | 2060 | struct qla_hw_data *ha = vha->hw; |
0107109e | 2061 | |
7ec0effd | 2062 | if (IS_P3P_TYPE(ha)) |
a9083016 GM |
2063 | return; |
2064 | ||
0107109e | 2065 | /* Update Serial Link options. */ |
f94097ed | 2066 | if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0) |
0107109e AV |
2067 | return; |
2068 | ||
e315cd28 | 2069 | rval = qla2x00_set_serdes_params(vha, |
f94097ed AV |
2070 | le16_to_cpu(ha->fw_seriallink_options24[1]), |
2071 | le16_to_cpu(ha->fw_seriallink_options24[2]), | |
2072 | le16_to_cpu(ha->fw_seriallink_options24[3])); | |
0107109e | 2073 | if (rval != QLA_SUCCESS) { |
7c3df132 | 2074 | ql_log(ql_log_warn, vha, 0x0104, |
0107109e AV |
2075 | "Unable to update Serial Link options (%x).\n", rval); |
2076 | } | |
2077 | } | |
2078 | ||
abbd8870 | 2079 | void |
e315cd28 | 2080 | qla2x00_config_rings(struct scsi_qla_host *vha) |
abbd8870 | 2081 | { |
e315cd28 | 2082 | struct qla_hw_data *ha = vha->hw; |
3d71644c | 2083 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
73208dfd AC |
2084 | struct req_que *req = ha->req_q_map[0]; |
2085 | struct rsp_que *rsp = ha->rsp_q_map[0]; | |
abbd8870 AV |
2086 | |
2087 | /* Setup ring parameters in initialization control block. */ | |
ad950360 BVA |
2088 | ha->init_cb->request_q_outpointer = cpu_to_le16(0); |
2089 | ha->init_cb->response_q_inpointer = cpu_to_le16(0); | |
e315cd28 AC |
2090 | ha->init_cb->request_q_length = cpu_to_le16(req->length); |
2091 | ha->init_cb->response_q_length = cpu_to_le16(rsp->length); | |
2092 | ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma)); | |
2093 | ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma)); | |
2094 | ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma)); | |
2095 | ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma)); | |
abbd8870 AV |
2096 | |
2097 | WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0); | |
2098 | WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0); | |
2099 | WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0); | |
2100 | WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0); | |
2101 | RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */ | |
2102 | } | |
2103 | ||
0107109e | 2104 | void |
e315cd28 | 2105 | qla24xx_config_rings(struct scsi_qla_host *vha) |
0107109e | 2106 | { |
e315cd28 | 2107 | struct qla_hw_data *ha = vha->hw; |
118e2ef9 | 2108 | device_reg_t *reg = ISP_QUE_REG(ha, 0); |
73208dfd AC |
2109 | struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp; |
2110 | struct qla_msix_entry *msix; | |
0107109e | 2111 | struct init_cb_24xx *icb; |
73208dfd AC |
2112 | uint16_t rid = 0; |
2113 | struct req_que *req = ha->req_q_map[0]; | |
2114 | struct rsp_que *rsp = ha->rsp_q_map[0]; | |
0107109e | 2115 | |
6246b8a1 | 2116 | /* Setup ring parameters in initialization control block. */ |
0107109e | 2117 | icb = (struct init_cb_24xx *)ha->init_cb; |
ad950360 BVA |
2118 | icb->request_q_outpointer = cpu_to_le16(0); |
2119 | icb->response_q_inpointer = cpu_to_le16(0); | |
e315cd28 AC |
2120 | icb->request_q_length = cpu_to_le16(req->length); |
2121 | icb->response_q_length = cpu_to_le16(rsp->length); | |
2122 | icb->request_q_address[0] = cpu_to_le32(LSD(req->dma)); | |
2123 | icb->request_q_address[1] = cpu_to_le32(MSD(req->dma)); | |
2124 | icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma)); | |
2125 | icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma)); | |
0107109e | 2126 | |
2d70c103 | 2127 | /* Setup ATIO queue dma pointers for target mode */ |
ad950360 | 2128 | icb->atio_q_inpointer = cpu_to_le16(0); |
2d70c103 NB |
2129 | icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length); |
2130 | icb->atio_q_address[0] = cpu_to_le32(LSD(ha->tgt.atio_dma)); | |
2131 | icb->atio_q_address[1] = cpu_to_le32(MSD(ha->tgt.atio_dma)); | |
2132 | ||
7c6300e3 | 2133 | if (IS_SHADOW_REG_CAPABLE(ha)) |
ad950360 | 2134 | icb->firmware_options_2 |= cpu_to_le32(BIT_30|BIT_29); |
7c6300e3 | 2135 | |
f73cb695 | 2136 | if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) { |
ad950360 BVA |
2137 | icb->qos = cpu_to_le16(QLA_DEFAULT_QUE_QOS); |
2138 | icb->rid = cpu_to_le16(rid); | |
73208dfd AC |
2139 | if (ha->flags.msix_enabled) { |
2140 | msix = &ha->msix_entries[1]; | |
7c3df132 SK |
2141 | ql_dbg(ql_dbg_init, vha, 0x00fd, |
2142 | "Registering vector 0x%x for base que.\n", | |
2143 | msix->entry); | |
73208dfd AC |
2144 | icb->msix = cpu_to_le16(msix->entry); |
2145 | } | |
2146 | /* Use alternate PCI bus number */ | |
2147 | if (MSB(rid)) | |
ad950360 | 2148 | icb->firmware_options_2 |= cpu_to_le32(BIT_19); |
73208dfd AC |
2149 | /* Use alternate PCI devfn */ |
2150 | if (LSB(rid)) | |
ad950360 | 2151 | icb->firmware_options_2 |= cpu_to_le32(BIT_18); |
73208dfd | 2152 | |
3155754a | 2153 | /* Use Disable MSIX Handshake mode for capable adapters */ |
6246b8a1 GM |
2154 | if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) && |
2155 | (ha->flags.msix_enabled)) { | |
ad950360 | 2156 | icb->firmware_options_2 &= cpu_to_le32(~BIT_22); |
3155754a | 2157 | ha->flags.disable_msix_handshake = 1; |
7c3df132 SK |
2158 | ql_dbg(ql_dbg_init, vha, 0x00fe, |
2159 | "MSIX Handshake Disable Mode turned on.\n"); | |
3155754a | 2160 | } else { |
ad950360 | 2161 | icb->firmware_options_2 |= cpu_to_le32(BIT_22); |
3155754a | 2162 | } |
ad950360 | 2163 | icb->firmware_options_2 |= cpu_to_le32(BIT_23); |
73208dfd AC |
2164 | |
2165 | WRT_REG_DWORD(®->isp25mq.req_q_in, 0); | |
2166 | WRT_REG_DWORD(®->isp25mq.req_q_out, 0); | |
2167 | WRT_REG_DWORD(®->isp25mq.rsp_q_in, 0); | |
2168 | WRT_REG_DWORD(®->isp25mq.rsp_q_out, 0); | |
2169 | } else { | |
2170 | WRT_REG_DWORD(®->isp24.req_q_in, 0); | |
2171 | WRT_REG_DWORD(®->isp24.req_q_out, 0); | |
2172 | WRT_REG_DWORD(®->isp24.rsp_q_in, 0); | |
2173 | WRT_REG_DWORD(®->isp24.rsp_q_out, 0); | |
2174 | } | |
aa230bc5 | 2175 | qlt_24xx_config_rings(vha); |
2d70c103 | 2176 | |
73208dfd AC |
2177 | /* PCI posting */ |
2178 | RD_REG_DWORD(&ioreg->hccr); | |
0107109e AV |
2179 | } |
2180 | ||
1da177e4 LT |
2181 | /** |
2182 | * qla2x00_init_rings() - Initializes firmware. | |
2183 | * @ha: HA context | |
2184 | * | |
2185 | * Beginning of request ring has initialization control block already built | |
2186 | * by nvram config routine. | |
2187 | * | |
2188 | * Returns 0 on success. | |
2189 | */ | |
8ae6d9c7 | 2190 | int |
e315cd28 | 2191 | qla2x00_init_rings(scsi_qla_host_t *vha) |
1da177e4 LT |
2192 | { |
2193 | int rval; | |
2194 | unsigned long flags = 0; | |
29bdccbe | 2195 | int cnt, que; |
e315cd28 | 2196 | struct qla_hw_data *ha = vha->hw; |
29bdccbe AC |
2197 | struct req_que *req; |
2198 | struct rsp_que *rsp; | |
2c3dfe3f SJ |
2199 | struct mid_init_cb_24xx *mid_init_cb = |
2200 | (struct mid_init_cb_24xx *) ha->init_cb; | |
1da177e4 LT |
2201 | |
2202 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
2203 | ||
2204 | /* Clear outstanding commands array. */ | |
2afa19a9 | 2205 | for (que = 0; que < ha->max_req_queues; que++) { |
29bdccbe | 2206 | req = ha->req_q_map[que]; |
cb43285f | 2207 | if (!req || !test_bit(que, ha->req_qid_map)) |
29bdccbe | 2208 | continue; |
7c6300e3 JC |
2209 | req->out_ptr = (void *)(req->ring + req->length); |
2210 | *req->out_ptr = 0; | |
8d93f550 | 2211 | for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) |
29bdccbe | 2212 | req->outstanding_cmds[cnt] = NULL; |
1da177e4 | 2213 | |
2afa19a9 | 2214 | req->current_outstanding_cmd = 1; |
1da177e4 | 2215 | |
29bdccbe AC |
2216 | /* Initialize firmware. */ |
2217 | req->ring_ptr = req->ring; | |
2218 | req->ring_index = 0; | |
2219 | req->cnt = req->length; | |
2220 | } | |
1da177e4 | 2221 | |
2afa19a9 | 2222 | for (que = 0; que < ha->max_rsp_queues; que++) { |
29bdccbe | 2223 | rsp = ha->rsp_q_map[que]; |
cb43285f | 2224 | if (!rsp || !test_bit(que, ha->rsp_qid_map)) |
29bdccbe | 2225 | continue; |
7c6300e3 JC |
2226 | rsp->in_ptr = (void *)(rsp->ring + rsp->length); |
2227 | *rsp->in_ptr = 0; | |
29bdccbe | 2228 | /* Initialize response queue entries */ |
8ae6d9c7 GM |
2229 | if (IS_QLAFX00(ha)) |
2230 | qlafx00_init_response_q_entries(rsp); | |
2231 | else | |
2232 | qla2x00_init_response_q_entries(rsp); | |
29bdccbe | 2233 | } |
1da177e4 | 2234 | |
2d70c103 NB |
2235 | ha->tgt.atio_ring_ptr = ha->tgt.atio_ring; |
2236 | ha->tgt.atio_ring_index = 0; | |
2237 | /* Initialize ATIO queue entries */ | |
2238 | qlt_init_atio_q_entries(vha); | |
2239 | ||
e315cd28 | 2240 | ha->isp_ops->config_rings(vha); |
1da177e4 LT |
2241 | |
2242 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
2243 | ||
8ae6d9c7 GM |
2244 | ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n"); |
2245 | ||
2246 | if (IS_QLAFX00(ha)) { | |
2247 | rval = qlafx00_init_firmware(vha, ha->init_cb_size); | |
2248 | goto next_check; | |
2249 | } | |
2250 | ||
1da177e4 | 2251 | /* Update any ISP specific firmware options before initialization. */ |
e315cd28 | 2252 | ha->isp_ops->update_fw_options(vha); |
1da177e4 | 2253 | |
605aa2bc | 2254 | if (ha->flags.npiv_supported) { |
45980cc2 | 2255 | if (ha->operating_mode == LOOP && !IS_CNA_CAPABLE(ha)) |
605aa2bc | 2256 | ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1; |
c48339de | 2257 | mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports); |
605aa2bc LC |
2258 | } |
2259 | ||
24a08138 | 2260 | if (IS_FWI2_CAPABLE(ha)) { |
ad950360 | 2261 | mid_init_cb->options = cpu_to_le16(BIT_1); |
24a08138 | 2262 | mid_init_cb->init_cb.execution_throttle = |
03e8c680 | 2263 | cpu_to_le16(ha->cur_fw_xcb_count); |
25232cc9 HM |
2264 | /* D-Port Status */ |
2265 | if (IS_DPORT_CAPABLE(ha)) | |
2266 | mid_init_cb->init_cb.firmware_options_1 |= | |
2267 | cpu_to_le16(BIT_7); | |
2486c627 HM |
2268 | /* Enable FA-WWPN */ |
2269 | ha->flags.fawwpn_enabled = | |
2270 | (mid_init_cb->init_cb.firmware_options_1 & BIT_6) ? 1 : 0; | |
2271 | ql_dbg(ql_dbg_init, vha, 0x0141, "FA-WWPN Support: %s.\n", | |
2272 | (ha->flags.fawwpn_enabled) ? "enabled" : "disabled"); | |
24a08138 | 2273 | } |
2c3dfe3f | 2274 | |
e315cd28 | 2275 | rval = qla2x00_init_firmware(vha, ha->init_cb_size); |
8ae6d9c7 | 2276 | next_check: |
1da177e4 | 2277 | if (rval) { |
7c3df132 SK |
2278 | ql_log(ql_log_fatal, vha, 0x00d2, |
2279 | "Init Firmware **** FAILED ****.\n"); | |
1da177e4 | 2280 | } else { |
7c3df132 SK |
2281 | ql_dbg(ql_dbg_init, vha, 0x00d3, |
2282 | "Init Firmware -- success.\n"); | |
1da177e4 LT |
2283 | } |
2284 | ||
2285 | return (rval); | |
2286 | } | |
2287 | ||
2288 | /** | |
2289 | * qla2x00_fw_ready() - Waits for firmware ready. | |
2290 | * @ha: HA context | |
2291 | * | |
2292 | * Returns 0 on success. | |
2293 | */ | |
2294 | static int | |
e315cd28 | 2295 | qla2x00_fw_ready(scsi_qla_host_t *vha) |
1da177e4 LT |
2296 | { |
2297 | int rval; | |
4d4df193 | 2298 | unsigned long wtime, mtime, cs84xx_time; |
1da177e4 LT |
2299 | uint16_t min_wait; /* Minimum wait time if loop is down */ |
2300 | uint16_t wait_time; /* Wait time if loop is coming ready */ | |
b5a340dd | 2301 | uint16_t state[6]; |
e315cd28 | 2302 | struct qla_hw_data *ha = vha->hw; |
1da177e4 | 2303 | |
8ae6d9c7 GM |
2304 | if (IS_QLAFX00(vha->hw)) |
2305 | return qlafx00_fw_ready(vha); | |
2306 | ||
1da177e4 LT |
2307 | rval = QLA_SUCCESS; |
2308 | ||
33461491 CD |
2309 | /* Time to wait for loop down */ |
2310 | if (IS_P3P_TYPE(ha)) | |
2311 | min_wait = 30; | |
2312 | else | |
2313 | min_wait = 20; | |
1da177e4 LT |
2314 | |
2315 | /* | |
2316 | * Firmware should take at most one RATOV to login, plus 5 seconds for | |
2317 | * our own processing. | |
2318 | */ | |
2319 | if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) { | |
2320 | wait_time = min_wait; | |
2321 | } | |
2322 | ||
2323 | /* Min wait time if loop down */ | |
2324 | mtime = jiffies + (min_wait * HZ); | |
2325 | ||
2326 | /* wait time before firmware ready */ | |
2327 | wtime = jiffies + (wait_time * HZ); | |
2328 | ||
2329 | /* Wait for ISP to finish LIP */ | |
e315cd28 | 2330 | if (!vha->flags.init_done) |
7c3df132 SK |
2331 | ql_log(ql_log_info, vha, 0x801e, |
2332 | "Waiting for LIP to complete.\n"); | |
1da177e4 LT |
2333 | |
2334 | do { | |
5b939038 | 2335 | memset(state, -1, sizeof(state)); |
e315cd28 | 2336 | rval = qla2x00_get_firmware_state(vha, state); |
1da177e4 | 2337 | if (rval == QLA_SUCCESS) { |
4d4df193 | 2338 | if (state[0] < FSTATE_LOSS_OF_SYNC) { |
e315cd28 | 2339 | vha->device_flags &= ~DFLG_NO_CABLE; |
1da177e4 | 2340 | } |
4d4df193 | 2341 | if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) { |
7c3df132 SK |
2342 | ql_dbg(ql_dbg_taskm, vha, 0x801f, |
2343 | "fw_state=%x 84xx=%x.\n", state[0], | |
2344 | state[2]); | |
4d4df193 HK |
2345 | if ((state[2] & FSTATE_LOGGED_IN) && |
2346 | (state[2] & FSTATE_WAITING_FOR_VERIFY)) { | |
7c3df132 SK |
2347 | ql_dbg(ql_dbg_taskm, vha, 0x8028, |
2348 | "Sending verify iocb.\n"); | |
4d4df193 HK |
2349 | |
2350 | cs84xx_time = jiffies; | |
e315cd28 | 2351 | rval = qla84xx_init_chip(vha); |
7c3df132 SK |
2352 | if (rval != QLA_SUCCESS) { |
2353 | ql_log(ql_log_warn, | |
cfb0919c | 2354 | vha, 0x8007, |
7c3df132 | 2355 | "Init chip failed.\n"); |
4d4df193 | 2356 | break; |
7c3df132 | 2357 | } |
4d4df193 HK |
2358 | |
2359 | /* Add time taken to initialize. */ | |
2360 | cs84xx_time = jiffies - cs84xx_time; | |
2361 | wtime += cs84xx_time; | |
2362 | mtime += cs84xx_time; | |
cfb0919c | 2363 | ql_dbg(ql_dbg_taskm, vha, 0x8008, |
7c3df132 SK |
2364 | "Increasing wait time by %ld. " |
2365 | "New time %ld.\n", cs84xx_time, | |
2366 | wtime); | |
4d4df193 HK |
2367 | } |
2368 | } else if (state[0] == FSTATE_READY) { | |
7c3df132 SK |
2369 | ql_dbg(ql_dbg_taskm, vha, 0x8037, |
2370 | "F/W Ready - OK.\n"); | |
1da177e4 | 2371 | |
e315cd28 | 2372 | qla2x00_get_retry_cnt(vha, &ha->retry_count, |
1da177e4 LT |
2373 | &ha->login_timeout, &ha->r_a_tov); |
2374 | ||
2375 | rval = QLA_SUCCESS; | |
2376 | break; | |
2377 | } | |
2378 | ||
2379 | rval = QLA_FUNCTION_FAILED; | |
2380 | ||
e315cd28 | 2381 | if (atomic_read(&vha->loop_down_timer) && |
4d4df193 | 2382 | state[0] != FSTATE_READY) { |
1da177e4 | 2383 | /* Loop down. Timeout on min_wait for states |
fa2a1ce5 AV |
2384 | * other than Wait for Login. |
2385 | */ | |
1da177e4 | 2386 | if (time_after_eq(jiffies, mtime)) { |
7c3df132 | 2387 | ql_log(ql_log_info, vha, 0x8038, |
1da177e4 LT |
2388 | "Cable is unplugged...\n"); |
2389 | ||
e315cd28 | 2390 | vha->device_flags |= DFLG_NO_CABLE; |
1da177e4 LT |
2391 | break; |
2392 | } | |
2393 | } | |
2394 | } else { | |
2395 | /* Mailbox cmd failed. Timeout on min_wait. */ | |
cdbb0a4f | 2396 | if (time_after_eq(jiffies, mtime) || |
7190575f | 2397 | ha->flags.isp82xx_fw_hung) |
1da177e4 LT |
2398 | break; |
2399 | } | |
2400 | ||
2401 | if (time_after_eq(jiffies, wtime)) | |
2402 | break; | |
2403 | ||
2404 | /* Delay for a while */ | |
2405 | msleep(500); | |
1da177e4 LT |
2406 | } while (1); |
2407 | ||
7c3df132 | 2408 | ql_dbg(ql_dbg_taskm, vha, 0x803a, |
b5a340dd JC |
2409 | "fw_state=%x (%x, %x, %x, %x %x) curr time=%lx.\n", state[0], |
2410 | state[1], state[2], state[3], state[4], state[5], jiffies); | |
1da177e4 | 2411 | |
cfb0919c | 2412 | if (rval && !(vha->device_flags & DFLG_NO_CABLE)) { |
7c3df132 SK |
2413 | ql_log(ql_log_warn, vha, 0x803b, |
2414 | "Firmware ready **** FAILED ****.\n"); | |
1da177e4 LT |
2415 | } |
2416 | ||
2417 | return (rval); | |
2418 | } | |
2419 | ||
2420 | /* | |
2421 | * qla2x00_configure_hba | |
2422 | * Setup adapter context. | |
2423 | * | |
2424 | * Input: | |
2425 | * ha = adapter state pointer. | |
2426 | * | |
2427 | * Returns: | |
2428 | * 0 = success | |
2429 | * | |
2430 | * Context: | |
2431 | * Kernel context. | |
2432 | */ | |
2433 | static int | |
e315cd28 | 2434 | qla2x00_configure_hba(scsi_qla_host_t *vha) |
1da177e4 LT |
2435 | { |
2436 | int rval; | |
2437 | uint16_t loop_id; | |
2438 | uint16_t topo; | |
2c3dfe3f | 2439 | uint16_t sw_cap; |
1da177e4 LT |
2440 | uint8_t al_pa; |
2441 | uint8_t area; | |
2442 | uint8_t domain; | |
2443 | char connect_type[22]; | |
e315cd28 | 2444 | struct qla_hw_data *ha = vha->hw; |
f24b5cb8 | 2445 | unsigned long flags; |
61e1b269 | 2446 | scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); |
1da177e4 LT |
2447 | |
2448 | /* Get host addresses. */ | |
e315cd28 | 2449 | rval = qla2x00_get_adapter_id(vha, |
2c3dfe3f | 2450 | &loop_id, &al_pa, &area, &domain, &topo, &sw_cap); |
1da177e4 | 2451 | if (rval != QLA_SUCCESS) { |
e315cd28 | 2452 | if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) || |
6246b8a1 | 2453 | IS_CNA_CAPABLE(ha) || |
33135aa2 | 2454 | (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) { |
7c3df132 SK |
2455 | ql_dbg(ql_dbg_disc, vha, 0x2008, |
2456 | "Loop is in a transition state.\n"); | |
33135aa2 | 2457 | } else { |
7c3df132 SK |
2458 | ql_log(ql_log_warn, vha, 0x2009, |
2459 | "Unable to get host loop ID.\n"); | |
61e1b269 JC |
2460 | if (IS_FWI2_CAPABLE(ha) && (vha == base_vha) && |
2461 | (rval == QLA_COMMAND_ERROR && loop_id == 0x1b)) { | |
2462 | ql_log(ql_log_warn, vha, 0x1151, | |
2463 | "Doing link init.\n"); | |
2464 | if (qla24xx_link_initialize(vha) == QLA_SUCCESS) | |
2465 | return rval; | |
2466 | } | |
e315cd28 | 2467 | set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); |
33135aa2 | 2468 | } |
1da177e4 LT |
2469 | return (rval); |
2470 | } | |
2471 | ||
2472 | if (topo == 4) { | |
7c3df132 SK |
2473 | ql_log(ql_log_info, vha, 0x200a, |
2474 | "Cannot get topology - retrying.\n"); | |
1da177e4 LT |
2475 | return (QLA_FUNCTION_FAILED); |
2476 | } | |
2477 | ||
e315cd28 | 2478 | vha->loop_id = loop_id; |
1da177e4 LT |
2479 | |
2480 | /* initialize */ | |
2481 | ha->min_external_loopid = SNS_FIRST_LOOP_ID; | |
2482 | ha->operating_mode = LOOP; | |
2c3dfe3f | 2483 | ha->switch_cap = 0; |
1da177e4 LT |
2484 | |
2485 | switch (topo) { | |
2486 | case 0: | |
7c3df132 | 2487 | ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n"); |
1da177e4 LT |
2488 | ha->current_topology = ISP_CFG_NL; |
2489 | strcpy(connect_type, "(Loop)"); | |
2490 | break; | |
2491 | ||
2492 | case 1: | |
7c3df132 | 2493 | ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n"); |
2c3dfe3f | 2494 | ha->switch_cap = sw_cap; |
1da177e4 LT |
2495 | ha->current_topology = ISP_CFG_FL; |
2496 | strcpy(connect_type, "(FL_Port)"); | |
2497 | break; | |
2498 | ||
2499 | case 2: | |
7c3df132 | 2500 | ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n"); |
1da177e4 LT |
2501 | ha->operating_mode = P2P; |
2502 | ha->current_topology = ISP_CFG_N; | |
2503 | strcpy(connect_type, "(N_Port-to-N_Port)"); | |
2504 | break; | |
2505 | ||
2506 | case 3: | |
7c3df132 | 2507 | ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n"); |
2c3dfe3f | 2508 | ha->switch_cap = sw_cap; |
1da177e4 LT |
2509 | ha->operating_mode = P2P; |
2510 | ha->current_topology = ISP_CFG_F; | |
2511 | strcpy(connect_type, "(F_Port)"); | |
2512 | break; | |
2513 | ||
2514 | default: | |
7c3df132 SK |
2515 | ql_dbg(ql_dbg_disc, vha, 0x200f, |
2516 | "HBA in unknown topology %x, using NL.\n", topo); | |
1da177e4 LT |
2517 | ha->current_topology = ISP_CFG_NL; |
2518 | strcpy(connect_type, "(Loop)"); | |
2519 | break; | |
2520 | } | |
2521 | ||
2522 | /* Save Host port and loop ID. */ | |
2523 | /* byte order - Big Endian */ | |
e315cd28 AC |
2524 | vha->d_id.b.domain = domain; |
2525 | vha->d_id.b.area = area; | |
2526 | vha->d_id.b.al_pa = al_pa; | |
1da177e4 | 2527 | |
f24b5cb8 | 2528 | spin_lock_irqsave(&ha->vport_slock, flags); |
2d70c103 | 2529 | qlt_update_vp_map(vha, SET_AL_PA); |
f24b5cb8 | 2530 | spin_unlock_irqrestore(&ha->vport_slock, flags); |
2d70c103 | 2531 | |
e315cd28 | 2532 | if (!vha->flags.init_done) |
7c3df132 SK |
2533 | ql_log(ql_log_info, vha, 0x2010, |
2534 | "Topology - %s, Host Loop address 0x%x.\n", | |
e315cd28 | 2535 | connect_type, vha->loop_id); |
1da177e4 | 2536 | |
1da177e4 LT |
2537 | return(rval); |
2538 | } | |
2539 | ||
a9083016 | 2540 | inline void |
e315cd28 AC |
2541 | qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len, |
2542 | char *def) | |
9bb9fcf2 AV |
2543 | { |
2544 | char *st, *en; | |
2545 | uint16_t index; | |
e315cd28 | 2546 | struct qla_hw_data *ha = vha->hw; |
ab671149 | 2547 | int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && |
6246b8a1 | 2548 | !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha); |
9bb9fcf2 AV |
2549 | |
2550 | if (memcmp(model, BINZERO, len) != 0) { | |
2551 | strncpy(ha->model_number, model, len); | |
2552 | st = en = ha->model_number; | |
2553 | en += len - 1; | |
2554 | while (en > st) { | |
2555 | if (*en != 0x20 && *en != 0x00) | |
2556 | break; | |
2557 | *en-- = '\0'; | |
2558 | } | |
2559 | ||
2560 | index = (ha->pdev->subsystem_device & 0xff); | |
7d0dba17 AV |
2561 | if (use_tbl && |
2562 | ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC && | |
9bb9fcf2 | 2563 | index < QLA_MODEL_NAMES) |
1ee27146 JC |
2564 | strncpy(ha->model_desc, |
2565 | qla2x00_model_name[index * 2 + 1], | |
2566 | sizeof(ha->model_desc) - 1); | |
9bb9fcf2 AV |
2567 | } else { |
2568 | index = (ha->pdev->subsystem_device & 0xff); | |
7d0dba17 AV |
2569 | if (use_tbl && |
2570 | ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC && | |
9bb9fcf2 AV |
2571 | index < QLA_MODEL_NAMES) { |
2572 | strcpy(ha->model_number, | |
2573 | qla2x00_model_name[index * 2]); | |
1ee27146 JC |
2574 | strncpy(ha->model_desc, |
2575 | qla2x00_model_name[index * 2 + 1], | |
2576 | sizeof(ha->model_desc) - 1); | |
9bb9fcf2 AV |
2577 | } else { |
2578 | strcpy(ha->model_number, def); | |
2579 | } | |
2580 | } | |
1ee27146 | 2581 | if (IS_FWI2_CAPABLE(ha)) |
e315cd28 | 2582 | qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc, |
1ee27146 | 2583 | sizeof(ha->model_desc)); |
9bb9fcf2 AV |
2584 | } |
2585 | ||
4e08df3f DM |
2586 | /* On sparc systems, obtain port and node WWN from firmware |
2587 | * properties. | |
2588 | */ | |
e315cd28 | 2589 | static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv) |
4e08df3f DM |
2590 | { |
2591 | #ifdef CONFIG_SPARC | |
e315cd28 | 2592 | struct qla_hw_data *ha = vha->hw; |
4e08df3f | 2593 | struct pci_dev *pdev = ha->pdev; |
15576bc8 DM |
2594 | struct device_node *dp = pci_device_to_OF_node(pdev); |
2595 | const u8 *val; | |
4e08df3f DM |
2596 | int len; |
2597 | ||
2598 | val = of_get_property(dp, "port-wwn", &len); | |
2599 | if (val && len >= WWN_SIZE) | |
2600 | memcpy(nv->port_name, val, WWN_SIZE); | |
2601 | ||
2602 | val = of_get_property(dp, "node-wwn", &len); | |
2603 | if (val && len >= WWN_SIZE) | |
2604 | memcpy(nv->node_name, val, WWN_SIZE); | |
2605 | #endif | |
2606 | } | |
2607 | ||
1da177e4 LT |
2608 | /* |
2609 | * NVRAM configuration for ISP 2xxx | |
2610 | * | |
2611 | * Input: | |
2612 | * ha = adapter block pointer. | |
2613 | * | |
2614 | * Output: | |
2615 | * initialization control block in response_ring | |
2616 | * host adapters parameters in host adapter block | |
2617 | * | |
2618 | * Returns: | |
2619 | * 0 = success. | |
2620 | */ | |
abbd8870 | 2621 | int |
e315cd28 | 2622 | qla2x00_nvram_config(scsi_qla_host_t *vha) |
1da177e4 | 2623 | { |
4e08df3f | 2624 | int rval; |
0107109e AV |
2625 | uint8_t chksum = 0; |
2626 | uint16_t cnt; | |
2627 | uint8_t *dptr1, *dptr2; | |
e315cd28 | 2628 | struct qla_hw_data *ha = vha->hw; |
0107109e | 2629 | init_cb_t *icb = ha->init_cb; |
281afe19 SJ |
2630 | nvram_t *nv = ha->nvram; |
2631 | uint8_t *ptr = ha->nvram; | |
3d71644c | 2632 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
1da177e4 | 2633 | |
4e08df3f DM |
2634 | rval = QLA_SUCCESS; |
2635 | ||
1da177e4 | 2636 | /* Determine NVRAM starting address. */ |
0107109e | 2637 | ha->nvram_size = sizeof(nvram_t); |
1da177e4 LT |
2638 | ha->nvram_base = 0; |
2639 | if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) | |
2640 | if ((RD_REG_WORD(®->ctrl_status) >> 14) == 1) | |
2641 | ha->nvram_base = 0x80; | |
2642 | ||
2643 | /* Get NVRAM data and calculate checksum. */ | |
e315cd28 | 2644 | ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size); |
0107109e AV |
2645 | for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++) |
2646 | chksum += *ptr++; | |
1da177e4 | 2647 | |
7c3df132 SK |
2648 | ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f, |
2649 | "Contents of NVRAM.\n"); | |
2650 | ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110, | |
2651 | (uint8_t *)nv, ha->nvram_size); | |
1da177e4 LT |
2652 | |
2653 | /* Bad NVRAM data, set defaults parameters. */ | |
2654 | if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || | |
2655 | nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) { | |
2656 | /* Reset NVRAM data. */ | |
7c3df132 | 2657 | ql_log(ql_log_warn, vha, 0x0064, |
9e336520 | 2658 | "Inconsistent NVRAM " |
7c3df132 SK |
2659 | "detected: checksum=0x%x id=%c version=0x%x.\n", |
2660 | chksum, nv->id[0], nv->nvram_version); | |
2661 | ql_log(ql_log_warn, vha, 0x0065, | |
2662 | "Falling back to " | |
2663 | "functioning (yet invalid -- WWPN) defaults.\n"); | |
4e08df3f DM |
2664 | |
2665 | /* | |
2666 | * Set default initialization control block. | |
2667 | */ | |
2668 | memset(nv, 0, ha->nvram_size); | |
2669 | nv->parameter_block_version = ICB_VERSION; | |
2670 | ||
2671 | if (IS_QLA23XX(ha)) { | |
2672 | nv->firmware_options[0] = BIT_2 | BIT_1; | |
2673 | nv->firmware_options[1] = BIT_7 | BIT_5; | |
2674 | nv->add_firmware_options[0] = BIT_5; | |
2675 | nv->add_firmware_options[1] = BIT_5 | BIT_4; | |
98aee70d | 2676 | nv->frame_payload_size = 2048; |
4e08df3f DM |
2677 | nv->special_options[1] = BIT_7; |
2678 | } else if (IS_QLA2200(ha)) { | |
2679 | nv->firmware_options[0] = BIT_2 | BIT_1; | |
2680 | nv->firmware_options[1] = BIT_7 | BIT_5; | |
2681 | nv->add_firmware_options[0] = BIT_5; | |
2682 | nv->add_firmware_options[1] = BIT_5 | BIT_4; | |
98aee70d | 2683 | nv->frame_payload_size = 1024; |
4e08df3f DM |
2684 | } else if (IS_QLA2100(ha)) { |
2685 | nv->firmware_options[0] = BIT_3 | BIT_1; | |
2686 | nv->firmware_options[1] = BIT_5; | |
98aee70d | 2687 | nv->frame_payload_size = 1024; |
4e08df3f DM |
2688 | } |
2689 | ||
ad950360 BVA |
2690 | nv->max_iocb_allocation = cpu_to_le16(256); |
2691 | nv->execution_throttle = cpu_to_le16(16); | |
4e08df3f DM |
2692 | nv->retry_count = 8; |
2693 | nv->retry_delay = 1; | |
2694 | ||
2695 | nv->port_name[0] = 33; | |
2696 | nv->port_name[3] = 224; | |
2697 | nv->port_name[4] = 139; | |
2698 | ||
e315cd28 | 2699 | qla2xxx_nvram_wwn_from_ofw(vha, nv); |
4e08df3f DM |
2700 | |
2701 | nv->login_timeout = 4; | |
2702 | ||
2703 | /* | |
2704 | * Set default host adapter parameters | |
2705 | */ | |
2706 | nv->host_p[1] = BIT_2; | |
2707 | nv->reset_delay = 5; | |
2708 | nv->port_down_retry_count = 8; | |
ad950360 | 2709 | nv->max_luns_per_target = cpu_to_le16(8); |
4e08df3f DM |
2710 | nv->link_down_timeout = 60; |
2711 | ||
2712 | rval = 1; | |
1da177e4 LT |
2713 | } |
2714 | ||
2715 | #if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2) | |
2716 | /* | |
2717 | * The SN2 does not provide BIOS emulation which means you can't change | |
2718 | * potentially bogus BIOS settings. Force the use of default settings | |
2719 | * for link rate and frame size. Hope that the rest of the settings | |
2720 | * are valid. | |
2721 | */ | |
2722 | if (ia64_platform_is("sn2")) { | |
98aee70d | 2723 | nv->frame_payload_size = 2048; |
1da177e4 LT |
2724 | if (IS_QLA23XX(ha)) |
2725 | nv->special_options[1] = BIT_7; | |
2726 | } | |
2727 | #endif | |
2728 | ||
2729 | /* Reset Initialization control block */ | |
0107109e | 2730 | memset(icb, 0, ha->init_cb_size); |
1da177e4 LT |
2731 | |
2732 | /* | |
2733 | * Setup driver NVRAM options. | |
2734 | */ | |
2735 | nv->firmware_options[0] |= (BIT_6 | BIT_1); | |
2736 | nv->firmware_options[0] &= ~(BIT_5 | BIT_4); | |
2737 | nv->firmware_options[1] |= (BIT_5 | BIT_0); | |
2738 | nv->firmware_options[1] &= ~BIT_4; | |
2739 | ||
2740 | if (IS_QLA23XX(ha)) { | |
2741 | nv->firmware_options[0] |= BIT_2; | |
2742 | nv->firmware_options[0] &= ~BIT_3; | |
2d70c103 | 2743 | nv->special_options[0] &= ~BIT_6; |
0107109e | 2744 | nv->add_firmware_options[1] |= BIT_5 | BIT_4; |
1da177e4 LT |
2745 | |
2746 | if (IS_QLA2300(ha)) { | |
2747 | if (ha->fb_rev == FPM_2310) { | |
2748 | strcpy(ha->model_number, "QLA2310"); | |
2749 | } else { | |
2750 | strcpy(ha->model_number, "QLA2300"); | |
2751 | } | |
2752 | } else { | |
e315cd28 | 2753 | qla2x00_set_model_info(vha, nv->model_number, |
9bb9fcf2 | 2754 | sizeof(nv->model_number), "QLA23xx"); |
1da177e4 LT |
2755 | } |
2756 | } else if (IS_QLA2200(ha)) { | |
2757 | nv->firmware_options[0] |= BIT_2; | |
2758 | /* | |
2759 | * 'Point-to-point preferred, else loop' is not a safe | |
2760 | * connection mode setting. | |
2761 | */ | |
2762 | if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) == | |
2763 | (BIT_5 | BIT_4)) { | |
2764 | /* Force 'loop preferred, else point-to-point'. */ | |
2765 | nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4); | |
2766 | nv->add_firmware_options[0] |= BIT_5; | |
2767 | } | |
2768 | strcpy(ha->model_number, "QLA22xx"); | |
2769 | } else /*if (IS_QLA2100(ha))*/ { | |
2770 | strcpy(ha->model_number, "QLA2100"); | |
2771 | } | |
2772 | ||
2773 | /* | |
2774 | * Copy over NVRAM RISC parameter block to initialization control block. | |
2775 | */ | |
2776 | dptr1 = (uint8_t *)icb; | |
2777 | dptr2 = (uint8_t *)&nv->parameter_block_version; | |
2778 | cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version; | |
2779 | while (cnt--) | |
2780 | *dptr1++ = *dptr2++; | |
2781 | ||
2782 | /* Copy 2nd half. */ | |
2783 | dptr1 = (uint8_t *)icb->add_firmware_options; | |
2784 | cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options; | |
2785 | while (cnt--) | |
2786 | *dptr1++ = *dptr2++; | |
2787 | ||
5341e868 AV |
2788 | /* Use alternate WWN? */ |
2789 | if (nv->host_p[1] & BIT_7) { | |
2790 | memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE); | |
2791 | memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE); | |
2792 | } | |
2793 | ||
1da177e4 LT |
2794 | /* Prepare nodename */ |
2795 | if ((icb->firmware_options[1] & BIT_6) == 0) { | |
2796 | /* | |
2797 | * Firmware will apply the following mask if the nodename was | |
2798 | * not provided. | |
2799 | */ | |
2800 | memcpy(icb->node_name, icb->port_name, WWN_SIZE); | |
2801 | icb->node_name[0] &= 0xF0; | |
2802 | } | |
2803 | ||
2804 | /* | |
2805 | * Set host adapter parameters. | |
2806 | */ | |
3ce8866c SK |
2807 | |
2808 | /* | |
2809 | * BIT_7 in the host-parameters section allows for modification to | |
2810 | * internal driver logging. | |
2811 | */ | |
0181944f | 2812 | if (nv->host_p[0] & BIT_7) |
cfb0919c | 2813 | ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK; |
1da177e4 LT |
2814 | ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0); |
2815 | /* Always load RISC code on non ISP2[12]00 chips. */ | |
2816 | if (!IS_QLA2100(ha) && !IS_QLA2200(ha)) | |
2817 | ha->flags.disable_risc_code_load = 0; | |
2818 | ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0); | |
2819 | ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0); | |
2820 | ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0); | |
06c22bd1 | 2821 | ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0; |
d4c760c2 | 2822 | ha->flags.disable_serdes = 0; |
1da177e4 LT |
2823 | |
2824 | ha->operating_mode = | |
2825 | (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4; | |
2826 | ||
2827 | memcpy(ha->fw_seriallink_options, nv->seriallink_options, | |
2828 | sizeof(ha->fw_seriallink_options)); | |
2829 | ||
2830 | /* save HBA serial number */ | |
2831 | ha->serial0 = icb->port_name[5]; | |
2832 | ha->serial1 = icb->port_name[6]; | |
2833 | ha->serial2 = icb->port_name[7]; | |
e315cd28 AC |
2834 | memcpy(vha->node_name, icb->node_name, WWN_SIZE); |
2835 | memcpy(vha->port_name, icb->port_name, WWN_SIZE); | |
1da177e4 | 2836 | |
ad950360 | 2837 | icb->execution_throttle = cpu_to_le16(0xFFFF); |
1da177e4 LT |
2838 | |
2839 | ha->retry_count = nv->retry_count; | |
2840 | ||
2841 | /* Set minimum login_timeout to 4 seconds. */ | |
5b91490e | 2842 | if (nv->login_timeout != ql2xlogintimeout) |
1da177e4 LT |
2843 | nv->login_timeout = ql2xlogintimeout; |
2844 | if (nv->login_timeout < 4) | |
2845 | nv->login_timeout = 4; | |
2846 | ha->login_timeout = nv->login_timeout; | |
2847 | icb->login_timeout = nv->login_timeout; | |
2848 | ||
00a537b8 AV |
2849 | /* Set minimum RATOV to 100 tenths of a second. */ |
2850 | ha->r_a_tov = 100; | |
1da177e4 | 2851 | |
1da177e4 LT |
2852 | ha->loop_reset_delay = nv->reset_delay; |
2853 | ||
1da177e4 LT |
2854 | /* Link Down Timeout = 0: |
2855 | * | |
2856 | * When Port Down timer expires we will start returning | |
2857 | * I/O's to OS with "DID_NO_CONNECT". | |
2858 | * | |
2859 | * Link Down Timeout != 0: | |
2860 | * | |
2861 | * The driver waits for the link to come up after link down | |
2862 | * before returning I/Os to OS with "DID_NO_CONNECT". | |
fa2a1ce5 | 2863 | */ |
1da177e4 LT |
2864 | if (nv->link_down_timeout == 0) { |
2865 | ha->loop_down_abort_time = | |
354d6b21 | 2866 | (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT); |
1da177e4 LT |
2867 | } else { |
2868 | ha->link_down_timeout = nv->link_down_timeout; | |
2869 | ha->loop_down_abort_time = | |
2870 | (LOOP_DOWN_TIME - ha->link_down_timeout); | |
fa2a1ce5 | 2871 | } |
1da177e4 | 2872 | |
1da177e4 LT |
2873 | /* |
2874 | * Need enough time to try and get the port back. | |
2875 | */ | |
2876 | ha->port_down_retry_count = nv->port_down_retry_count; | |
2877 | if (qlport_down_retry) | |
2878 | ha->port_down_retry_count = qlport_down_retry; | |
2879 | /* Set login_retry_count */ | |
2880 | ha->login_retry_count = nv->retry_count; | |
2881 | if (ha->port_down_retry_count == nv->port_down_retry_count && | |
2882 | ha->port_down_retry_count > 3) | |
2883 | ha->login_retry_count = ha->port_down_retry_count; | |
2884 | else if (ha->port_down_retry_count > (int)ha->login_retry_count) | |
2885 | ha->login_retry_count = ha->port_down_retry_count; | |
2886 | if (ql2xloginretrycount) | |
2887 | ha->login_retry_count = ql2xloginretrycount; | |
2888 | ||
ad950360 | 2889 | icb->lun_enables = cpu_to_le16(0); |
1da177e4 LT |
2890 | icb->command_resource_count = 0; |
2891 | icb->immediate_notify_resource_count = 0; | |
ad950360 | 2892 | icb->timeout = cpu_to_le16(0); |
1da177e4 LT |
2893 | |
2894 | if (IS_QLA2100(ha) || IS_QLA2200(ha)) { | |
2895 | /* Enable RIO */ | |
2896 | icb->firmware_options[0] &= ~BIT_3; | |
2897 | icb->add_firmware_options[0] &= | |
2898 | ~(BIT_3 | BIT_2 | BIT_1 | BIT_0); | |
2899 | icb->add_firmware_options[0] |= BIT_2; | |
2900 | icb->response_accumulation_timer = 3; | |
2901 | icb->interrupt_delay_timer = 5; | |
2902 | ||
e315cd28 | 2903 | vha->flags.process_response_queue = 1; |
1da177e4 | 2904 | } else { |
4fdfefe5 | 2905 | /* Enable ZIO. */ |
e315cd28 | 2906 | if (!vha->flags.init_done) { |
4fdfefe5 AV |
2907 | ha->zio_mode = icb->add_firmware_options[0] & |
2908 | (BIT_3 | BIT_2 | BIT_1 | BIT_0); | |
2909 | ha->zio_timer = icb->interrupt_delay_timer ? | |
2910 | icb->interrupt_delay_timer: 2; | |
2911 | } | |
1da177e4 LT |
2912 | icb->add_firmware_options[0] &= |
2913 | ~(BIT_3 | BIT_2 | BIT_1 | BIT_0); | |
e315cd28 | 2914 | vha->flags.process_response_queue = 0; |
4fdfefe5 | 2915 | if (ha->zio_mode != QLA_ZIO_DISABLED) { |
4a59f71d AV |
2916 | ha->zio_mode = QLA_ZIO_MODE_6; |
2917 | ||
7c3df132 | 2918 | ql_log(ql_log_info, vha, 0x0068, |
4fdfefe5 AV |
2919 | "ZIO mode %d enabled; timer delay (%d us).\n", |
2920 | ha->zio_mode, ha->zio_timer * 100); | |
1da177e4 | 2921 | |
4fdfefe5 AV |
2922 | icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode; |
2923 | icb->interrupt_delay_timer = (uint8_t)ha->zio_timer; | |
e315cd28 | 2924 | vha->flags.process_response_queue = 1; |
1da177e4 LT |
2925 | } |
2926 | } | |
2927 | ||
4e08df3f | 2928 | if (rval) { |
7c3df132 SK |
2929 | ql_log(ql_log_warn, vha, 0x0069, |
2930 | "NVRAM configuration failed.\n"); | |
4e08df3f DM |
2931 | } |
2932 | return (rval); | |
1da177e4 LT |
2933 | } |
2934 | ||
19a7b4ae JSEC |
2935 | static void |
2936 | qla2x00_rport_del(void *data) | |
2937 | { | |
2938 | fc_port_t *fcport = data; | |
d97994dc | 2939 | struct fc_rport *rport; |
044d78e1 | 2940 | unsigned long flags; |
d97994dc | 2941 | |
044d78e1 | 2942 | spin_lock_irqsave(fcport->vha->host->host_lock, flags); |
ac280b67 | 2943 | rport = fcport->drport ? fcport->drport: fcport->rport; |
d97994dc | 2944 | fcport->drport = NULL; |
044d78e1 | 2945 | spin_unlock_irqrestore(fcport->vha->host->host_lock, flags); |
df673274 | 2946 | if (rport) |
d97994dc | 2947 | fc_remote_port_delete(rport); |
19a7b4ae JSEC |
2948 | } |
2949 | ||
1da177e4 LT |
2950 | /** |
2951 | * qla2x00_alloc_fcport() - Allocate a generic fcport. | |
2952 | * @ha: HA context | |
2953 | * @flags: allocation flags | |
2954 | * | |
2955 | * Returns a pointer to the allocated fcport, or NULL, if none available. | |
2956 | */ | |
9a069e19 | 2957 | fc_port_t * |
e315cd28 | 2958 | qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags) |
1da177e4 LT |
2959 | { |
2960 | fc_port_t *fcport; | |
2961 | ||
bbfbbbc1 MK |
2962 | fcport = kzalloc(sizeof(fc_port_t), flags); |
2963 | if (!fcport) | |
2964 | return NULL; | |
1da177e4 LT |
2965 | |
2966 | /* Setup fcport template structure. */ | |
e315cd28 | 2967 | fcport->vha = vha; |
1da177e4 LT |
2968 | fcport->port_type = FCT_UNKNOWN; |
2969 | fcport->loop_id = FC_NO_LOOP_ID; | |
ec426e10 | 2970 | qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED); |
ad3e0eda | 2971 | fcport->supported_classes = FC_COS_UNSPECIFIED; |
1da177e4 | 2972 | |
bbfbbbc1 | 2973 | return fcport; |
1da177e4 LT |
2974 | } |
2975 | ||
2976 | /* | |
2977 | * qla2x00_configure_loop | |
2978 | * Updates Fibre Channel Device Database with what is actually on loop. | |
2979 | * | |
2980 | * Input: | |
2981 | * ha = adapter block pointer. | |
2982 | * | |
2983 | * Returns: | |
2984 | * 0 = success. | |
2985 | * 1 = error. | |
2986 | * 2 = database was full and device was not configured. | |
2987 | */ | |
2988 | static int | |
e315cd28 | 2989 | qla2x00_configure_loop(scsi_qla_host_t *vha) |
1da177e4 LT |
2990 | { |
2991 | int rval; | |
2992 | unsigned long flags, save_flags; | |
e315cd28 | 2993 | struct qla_hw_data *ha = vha->hw; |
1da177e4 LT |
2994 | rval = QLA_SUCCESS; |
2995 | ||
2996 | /* Get Initiator ID */ | |
e315cd28 AC |
2997 | if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) { |
2998 | rval = qla2x00_configure_hba(vha); | |
1da177e4 | 2999 | if (rval != QLA_SUCCESS) { |
7c3df132 SK |
3000 | ql_dbg(ql_dbg_disc, vha, 0x2013, |
3001 | "Unable to configure HBA.\n"); | |
1da177e4 LT |
3002 | return (rval); |
3003 | } | |
3004 | } | |
3005 | ||
e315cd28 | 3006 | save_flags = flags = vha->dpc_flags; |
7c3df132 SK |
3007 | ql_dbg(ql_dbg_disc, vha, 0x2014, |
3008 | "Configure loop -- dpc flags = 0x%lx.\n", flags); | |
1da177e4 LT |
3009 | |
3010 | /* | |
3011 | * If we have both an RSCN and PORT UPDATE pending then handle them | |
3012 | * both at the same time. | |
3013 | */ | |
e315cd28 AC |
3014 | clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); |
3015 | clear_bit(RSCN_UPDATE, &vha->dpc_flags); | |
1da177e4 | 3016 | |
3064ff39 MH |
3017 | qla2x00_get_data_rate(vha); |
3018 | ||
1da177e4 LT |
3019 | /* Determine what we need to do */ |
3020 | if (ha->current_topology == ISP_CFG_FL && | |
3021 | (test_bit(LOCAL_LOOP_UPDATE, &flags))) { | |
3022 | ||
1da177e4 LT |
3023 | set_bit(RSCN_UPDATE, &flags); |
3024 | ||
3025 | } else if (ha->current_topology == ISP_CFG_F && | |
3026 | (test_bit(LOCAL_LOOP_UPDATE, &flags))) { | |
3027 | ||
1da177e4 LT |
3028 | set_bit(RSCN_UPDATE, &flags); |
3029 | clear_bit(LOCAL_LOOP_UPDATE, &flags); | |
21333b48 AV |
3030 | |
3031 | } else if (ha->current_topology == ISP_CFG_N) { | |
3032 | clear_bit(RSCN_UPDATE, &flags); | |
1da177e4 | 3033 | |
e315cd28 | 3034 | } else if (!vha->flags.online || |
1da177e4 LT |
3035 | (test_bit(ABORT_ISP_ACTIVE, &flags))) { |
3036 | ||
1da177e4 LT |
3037 | set_bit(RSCN_UPDATE, &flags); |
3038 | set_bit(LOCAL_LOOP_UPDATE, &flags); | |
3039 | } | |
3040 | ||
3041 | if (test_bit(LOCAL_LOOP_UPDATE, &flags)) { | |
7c3df132 SK |
3042 | if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) { |
3043 | ql_dbg(ql_dbg_disc, vha, 0x2015, | |
3044 | "Loop resync needed, failing.\n"); | |
1da177e4 | 3045 | rval = QLA_FUNCTION_FAILED; |
642ef983 | 3046 | } else |
e315cd28 | 3047 | rval = qla2x00_configure_local_loop(vha); |
1da177e4 LT |
3048 | } |
3049 | ||
3050 | if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) { | |
7c3df132 SK |
3051 | if (LOOP_TRANSITION(vha)) { |
3052 | ql_dbg(ql_dbg_disc, vha, 0x201e, | |
3053 | "Needs RSCN update and loop transition.\n"); | |
1da177e4 | 3054 | rval = QLA_FUNCTION_FAILED; |
7c3df132 | 3055 | } |
e315cd28 AC |
3056 | else |
3057 | rval = qla2x00_configure_fabric(vha); | |
1da177e4 LT |
3058 | } |
3059 | ||
3060 | if (rval == QLA_SUCCESS) { | |
e315cd28 AC |
3061 | if (atomic_read(&vha->loop_down_timer) || |
3062 | test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) { | |
1da177e4 LT |
3063 | rval = QLA_FUNCTION_FAILED; |
3064 | } else { | |
e315cd28 | 3065 | atomic_set(&vha->loop_state, LOOP_READY); |
7c3df132 SK |
3066 | ql_dbg(ql_dbg_disc, vha, 0x2069, |
3067 | "LOOP READY.\n"); | |
3bb67df5 DKU |
3068 | |
3069 | /* | |
3070 | * Process any ATIO queue entries that came in | |
3071 | * while we weren't online. | |
3072 | */ | |
3073 | if (qla_tgt_mode_enabled(vha)) { | |
3074 | if (IS_QLA27XX(ha) || IS_QLA83XX(ha)) { | |
3075 | spin_lock_irqsave(&ha->tgt.atio_lock, | |
3076 | flags); | |
3077 | qlt_24xx_process_atio_queue(vha, 0); | |
3078 | spin_unlock_irqrestore( | |
3079 | &ha->tgt.atio_lock, flags); | |
3080 | } else { | |
3081 | spin_lock_irqsave(&ha->hardware_lock, | |
3082 | flags); | |
3083 | qlt_24xx_process_atio_queue(vha, 1); | |
3084 | spin_unlock_irqrestore( | |
3085 | &ha->hardware_lock, flags); | |
3086 | } | |
3087 | } | |
1da177e4 LT |
3088 | } |
3089 | } | |
3090 | ||
3091 | if (rval) { | |
7c3df132 SK |
3092 | ql_dbg(ql_dbg_disc, vha, 0x206a, |
3093 | "%s *** FAILED ***.\n", __func__); | |
1da177e4 | 3094 | } else { |
7c3df132 SK |
3095 | ql_dbg(ql_dbg_disc, vha, 0x206b, |
3096 | "%s: exiting normally.\n", __func__); | |
1da177e4 LT |
3097 | } |
3098 | ||
cc3ef7bc | 3099 | /* Restore state if a resync event occurred during processing */ |
e315cd28 | 3100 | if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) { |
1da177e4 | 3101 | if (test_bit(LOCAL_LOOP_UPDATE, &save_flags)) |
e315cd28 | 3102 | set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); |
f4658b6c | 3103 | if (test_bit(RSCN_UPDATE, &save_flags)) { |
e315cd28 | 3104 | set_bit(RSCN_UPDATE, &vha->dpc_flags); |
f4658b6c | 3105 | } |
1da177e4 LT |
3106 | } |
3107 | ||
3108 | return (rval); | |
3109 | } | |
3110 | ||
3111 | ||
3112 | ||
3113 | /* | |
3114 | * qla2x00_configure_local_loop | |
3115 | * Updates Fibre Channel Device Database with local loop devices. | |
3116 | * | |
3117 | * Input: | |
3118 | * ha = adapter block pointer. | |
3119 | * | |
3120 | * Returns: | |
3121 | * 0 = success. | |
3122 | */ | |
3123 | static int | |
e315cd28 | 3124 | qla2x00_configure_local_loop(scsi_qla_host_t *vha) |
1da177e4 LT |
3125 | { |
3126 | int rval, rval2; | |
3127 | int found_devs; | |
3128 | int found; | |
3129 | fc_port_t *fcport, *new_fcport; | |
3130 | ||
3131 | uint16_t index; | |
3132 | uint16_t entries; | |
3133 | char *id_iter; | |
3134 | uint16_t loop_id; | |
3135 | uint8_t domain, area, al_pa; | |
e315cd28 | 3136 | struct qla_hw_data *ha = vha->hw; |
1da177e4 LT |
3137 | |
3138 | found_devs = 0; | |
3139 | new_fcport = NULL; | |
642ef983 | 3140 | entries = MAX_FIBRE_DEVICES_LOOP; |
1da177e4 | 3141 | |
1da177e4 | 3142 | /* Get list of logged in devices. */ |
642ef983 | 3143 | memset(ha->gid_list, 0, qla2x00_gid_list_size(ha)); |
e315cd28 | 3144 | rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma, |
1da177e4 LT |
3145 | &entries); |
3146 | if (rval != QLA_SUCCESS) | |
3147 | goto cleanup_allocation; | |
3148 | ||
7c3df132 SK |
3149 | ql_dbg(ql_dbg_disc, vha, 0x2017, |
3150 | "Entries in ID list (%d).\n", entries); | |
3151 | ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075, | |
3152 | (uint8_t *)ha->gid_list, | |
3153 | entries * sizeof(struct gid_list_info)); | |
1da177e4 LT |
3154 | |
3155 | /* Allocate temporary fcport for any new fcports discovered. */ | |
e315cd28 | 3156 | new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); |
1da177e4 | 3157 | if (new_fcport == NULL) { |
7c3df132 SK |
3158 | ql_log(ql_log_warn, vha, 0x2018, |
3159 | "Memory allocation failed for fcport.\n"); | |
1da177e4 LT |
3160 | rval = QLA_MEMORY_ALLOC_FAILED; |
3161 | goto cleanup_allocation; | |
3162 | } | |
3163 | new_fcport->flags &= ~FCF_FABRIC_DEVICE; | |
3164 | ||
3165 | /* | |
3166 | * Mark local devices that were present with FCF_DEVICE_LOST for now. | |
3167 | */ | |
e315cd28 | 3168 | list_for_each_entry(fcport, &vha->vp_fcports, list) { |
1da177e4 LT |
3169 | if (atomic_read(&fcport->state) == FCS_ONLINE && |
3170 | fcport->port_type != FCT_BROADCAST && | |
3171 | (fcport->flags & FCF_FABRIC_DEVICE) == 0) { | |
3172 | ||
7c3df132 SK |
3173 | ql_dbg(ql_dbg_disc, vha, 0x2019, |
3174 | "Marking port lost loop_id=0x%04x.\n", | |
3175 | fcport->loop_id); | |
1da177e4 | 3176 | |
ec426e10 | 3177 | qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); |
1da177e4 LT |
3178 | } |
3179 | } | |
3180 | ||
3181 | /* Add devices to port list. */ | |
3182 | id_iter = (char *)ha->gid_list; | |
3183 | for (index = 0; index < entries; index++) { | |
3184 | domain = ((struct gid_list_info *)id_iter)->domain; | |
3185 | area = ((struct gid_list_info *)id_iter)->area; | |
3186 | al_pa = ((struct gid_list_info *)id_iter)->al_pa; | |
abbd8870 | 3187 | if (IS_QLA2100(ha) || IS_QLA2200(ha)) |
1da177e4 LT |
3188 | loop_id = (uint16_t) |
3189 | ((struct gid_list_info *)id_iter)->loop_id_2100; | |
abbd8870 | 3190 | else |
1da177e4 LT |
3191 | loop_id = le16_to_cpu( |
3192 | ((struct gid_list_info *)id_iter)->loop_id); | |
abbd8870 | 3193 | id_iter += ha->gid_list_info_size; |
1da177e4 LT |
3194 | |
3195 | /* Bypass reserved domain fields. */ | |
3196 | if ((domain & 0xf0) == 0xf0) | |
3197 | continue; | |
3198 | ||
3199 | /* Bypass if not same domain and area of adapter. */ | |
f7d289f6 | 3200 | if (area && domain && |
e315cd28 | 3201 | (area != vha->d_id.b.area || domain != vha->d_id.b.domain)) |
1da177e4 LT |
3202 | continue; |
3203 | ||
3204 | /* Bypass invalid local loop ID. */ | |
3205 | if (loop_id > LAST_LOCAL_LOOP_ID) | |
3206 | continue; | |
3207 | ||
370d550e AE |
3208 | memset(new_fcport, 0, sizeof(fc_port_t)); |
3209 | ||
1da177e4 LT |
3210 | /* Fill in member data. */ |
3211 | new_fcport->d_id.b.domain = domain; | |
3212 | new_fcport->d_id.b.area = area; | |
3213 | new_fcport->d_id.b.al_pa = al_pa; | |
3214 | new_fcport->loop_id = loop_id; | |
e315cd28 | 3215 | rval2 = qla2x00_get_port_database(vha, new_fcport, 0); |
1da177e4 | 3216 | if (rval2 != QLA_SUCCESS) { |
7c3df132 SK |
3217 | ql_dbg(ql_dbg_disc, vha, 0x201a, |
3218 | "Failed to retrieve fcport information " | |
3219 | "-- get_port_database=%x, loop_id=0x%04x.\n", | |
3220 | rval2, new_fcport->loop_id); | |
3221 | ql_dbg(ql_dbg_disc, vha, 0x201b, | |
3222 | "Scheduling resync.\n"); | |
e315cd28 | 3223 | set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); |
1da177e4 LT |
3224 | continue; |
3225 | } | |
3226 | ||
3227 | /* Check for matching device in port list. */ | |
3228 | found = 0; | |
3229 | fcport = NULL; | |
e315cd28 | 3230 | list_for_each_entry(fcport, &vha->vp_fcports, list) { |
1da177e4 LT |
3231 | if (memcmp(new_fcport->port_name, fcport->port_name, |
3232 | WWN_SIZE)) | |
3233 | continue; | |
3234 | ||
ddb9b126 | 3235 | fcport->flags &= ~FCF_FABRIC_DEVICE; |
1da177e4 LT |
3236 | fcport->loop_id = new_fcport->loop_id; |
3237 | fcport->port_type = new_fcport->port_type; | |
3238 | fcport->d_id.b24 = new_fcport->d_id.b24; | |
3239 | memcpy(fcport->node_name, new_fcport->node_name, | |
3240 | WWN_SIZE); | |
3241 | ||
3242 | found++; | |
3243 | break; | |
3244 | } | |
3245 | ||
3246 | if (!found) { | |
3247 | /* New device, add to fcports list. */ | |
e315cd28 | 3248 | list_add_tail(&new_fcport->list, &vha->vp_fcports); |
1da177e4 LT |
3249 | |
3250 | /* Allocate a new replacement fcport. */ | |
3251 | fcport = new_fcport; | |
e315cd28 | 3252 | new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); |
1da177e4 | 3253 | if (new_fcport == NULL) { |
7c3df132 SK |
3254 | ql_log(ql_log_warn, vha, 0x201c, |
3255 | "Failed to allocate memory for fcport.\n"); | |
1da177e4 LT |
3256 | rval = QLA_MEMORY_ALLOC_FAILED; |
3257 | goto cleanup_allocation; | |
3258 | } | |
3259 | new_fcport->flags &= ~FCF_FABRIC_DEVICE; | |
3260 | } | |
3261 | ||
d8b45213 | 3262 | /* Base iIDMA settings on HBA port speed. */ |
a3cbdfad | 3263 | fcport->fp_speed = ha->link_data_rate; |
d8b45213 | 3264 | |
e315cd28 | 3265 | qla2x00_update_fcport(vha, fcport); |
1da177e4 LT |
3266 | |
3267 | found_devs++; | |
3268 | } | |
3269 | ||
3270 | cleanup_allocation: | |
c9475cb0 | 3271 | kfree(new_fcport); |
1da177e4 LT |
3272 | |
3273 | if (rval != QLA_SUCCESS) { | |
7c3df132 SK |
3274 | ql_dbg(ql_dbg_disc, vha, 0x201d, |
3275 | "Configure local loop error exit: rval=%x.\n", rval); | |
1da177e4 LT |
3276 | } |
3277 | ||
1da177e4 LT |
3278 | return (rval); |
3279 | } | |
3280 | ||
d8b45213 | 3281 | static void |
e315cd28 | 3282 | qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport) |
d8b45213 | 3283 | { |
d8b45213 | 3284 | int rval; |
93f2bd67 | 3285 | uint16_t mb[MAILBOX_REGISTER_COUNT]; |
e315cd28 | 3286 | struct qla_hw_data *ha = vha->hw; |
d8b45213 | 3287 | |
c76f2c01 | 3288 | if (!IS_IIDMA_CAPABLE(ha)) |
d8b45213 AV |
3289 | return; |
3290 | ||
c9afb9a2 GM |
3291 | if (atomic_read(&fcport->state) != FCS_ONLINE) |
3292 | return; | |
3293 | ||
39bd9622 AV |
3294 | if (fcport->fp_speed == PORT_SPEED_UNKNOWN || |
3295 | fcport->fp_speed > ha->link_data_rate) | |
d8b45213 AV |
3296 | return; |
3297 | ||
e315cd28 | 3298 | rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed, |
a3cbdfad | 3299 | mb); |
d8b45213 | 3300 | if (rval != QLA_SUCCESS) { |
7c3df132 | 3301 | ql_dbg(ql_dbg_disc, vha, 0x2004, |
7b833558 OK |
3302 | "Unable to adjust iIDMA %8phN -- %04x %x %04x %04x.\n", |
3303 | fcport->port_name, rval, fcport->fp_speed, mb[0], mb[1]); | |
d8b45213 | 3304 | } else { |
7c3df132 | 3305 | ql_dbg(ql_dbg_disc, vha, 0x2005, |
7b833558 | 3306 | "iIDMA adjusted to %s GB/s on %8phN.\n", |
d0297c9a | 3307 | qla2x00_get_link_speed_str(ha, fcport->fp_speed), |
7b833558 | 3308 | fcport->port_name); |
d8b45213 AV |
3309 | } |
3310 | } | |
3311 | ||
23be331d | 3312 | static void |
e315cd28 | 3313 | qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport) |
8482e118 AV |
3314 | { |
3315 | struct fc_rport_identifiers rport_ids; | |
bdf79621 | 3316 | struct fc_rport *rport; |
044d78e1 | 3317 | unsigned long flags; |
8482e118 | 3318 | |
f8b02a85 AV |
3319 | rport_ids.node_name = wwn_to_u64(fcport->node_name); |
3320 | rport_ids.port_name = wwn_to_u64(fcport->port_name); | |
8482e118 AV |
3321 | rport_ids.port_id = fcport->d_id.b.domain << 16 | |
3322 | fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa; | |
77d74143 | 3323 | rport_ids.roles = FC_RPORT_ROLE_UNKNOWN; |
e315cd28 | 3324 | fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids); |
77d74143 | 3325 | if (!rport) { |
7c3df132 SK |
3326 | ql_log(ql_log_warn, vha, 0x2006, |
3327 | "Unable to allocate fc remote port.\n"); | |
77d74143 AV |
3328 | return; |
3329 | } | |
2d70c103 NB |
3330 | /* |
3331 | * Create target mode FC NEXUS in qla_target.c if target mode is | |
3332 | * enabled.. | |
3333 | */ | |
ba9f6f64 | 3334 | |
2d70c103 NB |
3335 | qlt_fc_port_added(vha, fcport); |
3336 | ||
044d78e1 | 3337 | spin_lock_irqsave(fcport->vha->host->host_lock, flags); |
19a7b4ae | 3338 | *((fc_port_t **)rport->dd_data) = fcport; |
044d78e1 | 3339 | spin_unlock_irqrestore(fcport->vha->host->host_lock, flags); |
d97994dc | 3340 | |
ad3e0eda | 3341 | rport->supported_classes = fcport->supported_classes; |
77d74143 | 3342 | |
8482e118 AV |
3343 | rport_ids.roles = FC_RPORT_ROLE_UNKNOWN; |
3344 | if (fcport->port_type == FCT_INITIATOR) | |
3345 | rport_ids.roles |= FC_RPORT_ROLE_FCP_INITIATOR; | |
3346 | if (fcport->port_type == FCT_TARGET) | |
3347 | rport_ids.roles |= FC_RPORT_ROLE_FCP_TARGET; | |
77d74143 | 3348 | fc_remote_port_rolechg(rport, rport_ids.roles); |
1da177e4 LT |
3349 | } |
3350 | ||
23be331d AB |
3351 | /* |
3352 | * qla2x00_update_fcport | |
3353 | * Updates device on list. | |
3354 | * | |
3355 | * Input: | |
3356 | * ha = adapter block pointer. | |
3357 | * fcport = port structure pointer. | |
3358 | * | |
3359 | * Return: | |
3360 | * 0 - Success | |
3361 | * BIT_0 - error | |
3362 | * | |
3363 | * Context: | |
3364 | * Kernel context. | |
3365 | */ | |
3366 | void | |
e315cd28 | 3367 | qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport) |
23be331d | 3368 | { |
e315cd28 | 3369 | fcport->vha = vha; |
8ae6d9c7 GM |
3370 | |
3371 | if (IS_QLAFX00(vha->hw)) { | |
3372 | qla2x00_set_fcport_state(fcport, FCS_ONLINE); | |
d20ed91b | 3373 | goto reg_port; |
8ae6d9c7 | 3374 | } |
23be331d | 3375 | fcport->login_retry = 0; |
5ff1d584 | 3376 | fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); |
23be331d | 3377 | |
1f93da52 | 3378 | qla2x00_set_fcport_state(fcport, FCS_ONLINE); |
e315cd28 | 3379 | qla2x00_iidma_fcport(vha, fcport); |
21090cbe | 3380 | qla24xx_update_fcport_fcp_prio(vha, fcport); |
d20ed91b AP |
3381 | |
3382 | reg_port: | |
3383 | if (qla_ini_mode_enabled(vha)) | |
3384 | qla2x00_reg_remote_port(vha, fcport); | |
3385 | else { | |
3386 | /* | |
3387 | * Create target mode FC NEXUS in qla_target.c | |
3388 | */ | |
3389 | qlt_fc_port_added(vha, fcport); | |
3390 | } | |
23be331d AB |
3391 | } |
3392 | ||
1da177e4 LT |
3393 | /* |
3394 | * qla2x00_configure_fabric | |
3395 | * Setup SNS devices with loop ID's. | |
3396 | * | |
3397 | * Input: | |
3398 | * ha = adapter block pointer. | |
3399 | * | |
3400 | * Returns: | |
3401 | * 0 = success. | |
3402 | * BIT_0 = error | |
3403 | */ | |
3404 | static int | |
e315cd28 | 3405 | qla2x00_configure_fabric(scsi_qla_host_t *vha) |
1da177e4 | 3406 | { |
b3b02e6e | 3407 | int rval; |
e452ceb6 | 3408 | fc_port_t *fcport, *fcptemp; |
1da177e4 LT |
3409 | uint16_t next_loopid; |
3410 | uint16_t mb[MAILBOX_REGISTER_COUNT]; | |
0107109e | 3411 | uint16_t loop_id; |
1da177e4 | 3412 | LIST_HEAD(new_fcports); |
e315cd28 AC |
3413 | struct qla_hw_data *ha = vha->hw; |
3414 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); | |
df673274 | 3415 | int discovery_gen; |
1da177e4 LT |
3416 | |
3417 | /* If FL port exists, then SNS is present */ | |
e428924c | 3418 | if (IS_FWI2_CAPABLE(ha)) |
0107109e AV |
3419 | loop_id = NPH_F_PORT; |
3420 | else | |
3421 | loop_id = SNS_FL_PORT; | |
e315cd28 | 3422 | rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1); |
1da177e4 | 3423 | if (rval != QLA_SUCCESS) { |
7c3df132 SK |
3424 | ql_dbg(ql_dbg_disc, vha, 0x201f, |
3425 | "MBX_GET_PORT_NAME failed, No FL Port.\n"); | |
1da177e4 | 3426 | |
e315cd28 | 3427 | vha->device_flags &= ~SWITCH_FOUND; |
1da177e4 LT |
3428 | return (QLA_SUCCESS); |
3429 | } | |
e315cd28 | 3430 | vha->device_flags |= SWITCH_FOUND; |
1da177e4 | 3431 | |
1da177e4 | 3432 | do { |
cca5335c AV |
3433 | /* FDMI support. */ |
3434 | if (ql2xfdmienable && | |
e315cd28 AC |
3435 | test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags)) |
3436 | qla2x00_fdmi_register(vha); | |
cca5335c | 3437 | |
1da177e4 | 3438 | /* Ensure we are logged into the SNS. */ |
e428924c | 3439 | if (IS_FWI2_CAPABLE(ha)) |
0107109e AV |
3440 | loop_id = NPH_SNS; |
3441 | else | |
3442 | loop_id = SIMPLE_NAME_SERVER; | |
0b91d116 CD |
3443 | rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff, |
3444 | 0xfc, mb, BIT_1|BIT_0); | |
3445 | if (rval != QLA_SUCCESS) { | |
3446 | set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); | |
e452ceb6 | 3447 | return rval; |
0b91d116 | 3448 | } |
1da177e4 | 3449 | if (mb[0] != MBS_COMMAND_COMPLETE) { |
7c3df132 SK |
3450 | ql_dbg(ql_dbg_disc, vha, 0x2042, |
3451 | "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x " | |
3452 | "mb[6]=%x mb[7]=%x.\n", loop_id, mb[0], mb[1], | |
3453 | mb[2], mb[6], mb[7]); | |
1da177e4 LT |
3454 | return (QLA_SUCCESS); |
3455 | } | |
3456 | ||
e315cd28 AC |
3457 | if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) { |
3458 | if (qla2x00_rft_id(vha)) { | |
1da177e4 | 3459 | /* EMPTY */ |
7c3df132 SK |
3460 | ql_dbg(ql_dbg_disc, vha, 0x2045, |
3461 | "Register FC-4 TYPE failed.\n"); | |
1da177e4 | 3462 | } |
e315cd28 | 3463 | if (qla2x00_rff_id(vha)) { |
1da177e4 | 3464 | /* EMPTY */ |
7c3df132 SK |
3465 | ql_dbg(ql_dbg_disc, vha, 0x2049, |
3466 | "Register FC-4 Features failed.\n"); | |
1da177e4 | 3467 | } |
e315cd28 | 3468 | if (qla2x00_rnn_id(vha)) { |
1da177e4 | 3469 | /* EMPTY */ |
7c3df132 SK |
3470 | ql_dbg(ql_dbg_disc, vha, 0x204f, |
3471 | "Register Node Name failed.\n"); | |
e315cd28 | 3472 | } else if (qla2x00_rsnn_nn(vha)) { |
1da177e4 | 3473 | /* EMPTY */ |
7c3df132 SK |
3474 | ql_dbg(ql_dbg_disc, vha, 0x2053, |
3475 | "Register Symobilic Node Name failed.\n"); | |
1da177e4 LT |
3476 | } |
3477 | } | |
3478 | ||
827210ba JC |
3479 | #define QLA_FCPORT_SCAN 1 |
3480 | #define QLA_FCPORT_FOUND 2 | |
3481 | ||
3482 | list_for_each_entry(fcport, &vha->vp_fcports, list) { | |
3483 | fcport->scan_state = QLA_FCPORT_SCAN; | |
3484 | } | |
3485 | ||
df673274 AP |
3486 | /* Mark the time right before querying FW for connected ports. |
3487 | * This process is long, asynchronous and by the time it's done, | |
3488 | * collected information might not be accurate anymore. E.g. | |
3489 | * disconnected port might have re-connected and a brand new | |
3490 | * session has been created. In this case session's generation | |
3491 | * will be newer than discovery_gen. */ | |
3492 | qlt_do_generation_tick(vha, &discovery_gen); | |
3493 | ||
e315cd28 | 3494 | rval = qla2x00_find_all_fabric_devs(vha, &new_fcports); |
1da177e4 LT |
3495 | if (rval != QLA_SUCCESS) |
3496 | break; | |
3497 | ||
e452ceb6 JC |
3498 | /* |
3499 | * Logout all previous fabric devices marked lost, except | |
3500 | * FCP2 devices. | |
3501 | */ | |
e315cd28 AC |
3502 | list_for_each_entry(fcport, &vha->vp_fcports, list) { |
3503 | if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) | |
1da177e4 LT |
3504 | break; |
3505 | ||
3506 | if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) | |
3507 | continue; | |
3508 | ||
b2032fd5 RD |
3509 | if (fcport->scan_state == QLA_FCPORT_SCAN) { |
3510 | if (qla_ini_mode_enabled(base_vha) && | |
3511 | atomic_read(&fcport->state) == FCS_ONLINE) { | |
3512 | qla2x00_mark_device_lost(vha, fcport, | |
3513 | ql2xplogiabsentdevice, 0); | |
3514 | if (fcport->loop_id != FC_NO_LOOP_ID && | |
3515 | (fcport->flags & FCF_FCP2_DEVICE) == 0 && | |
3516 | fcport->port_type != FCT_INITIATOR && | |
3517 | fcport->port_type != FCT_BROADCAST) { | |
3518 | ha->isp_ops->fabric_logout(vha, | |
3519 | fcport->loop_id, | |
3520 | fcport->d_id.b.domain, | |
3521 | fcport->d_id.b.area, | |
3522 | fcport->d_id.b.al_pa); | |
3523 | qla2x00_clear_loop_id(fcport); | |
3524 | } | |
3525 | } else if (!qla_ini_mode_enabled(base_vha)) { | |
3526 | /* | |
3527 | * In target mode, explicitly kill | |
3528 | * sessions and log out of devices | |
3529 | * that are gone, so that we don't | |
3530 | * end up with an initiator using the | |
3531 | * wrong ACL (if the fabric recycles | |
3532 | * an FC address and we have a stale | |
3533 | * session around) and so that we don't | |
3534 | * report initiators that are no longer | |
3535 | * on the fabric. | |
3536 | */ | |
3537 | ql_dbg(ql_dbg_tgt_mgt, vha, 0xf077, | |
3538 | "port gone, logging out/killing session: " | |
3539 | "%8phC state 0x%x flags 0x%x fc4_type 0x%x " | |
3540 | "scan_state %d\n", | |
3541 | fcport->port_name, | |
3542 | atomic_read(&fcport->state), | |
3543 | fcport->flags, fcport->fc4_type, | |
3544 | fcport->scan_state); | |
df673274 AP |
3545 | qlt_fc_port_deleted(vha, fcport, |
3546 | discovery_gen); | |
1da177e4 LT |
3547 | } |
3548 | } | |
e452ceb6 | 3549 | } |
1da177e4 | 3550 | |
e452ceb6 JC |
3551 | /* Starting free loop ID. */ |
3552 | next_loopid = ha->min_external_loopid; | |
3553 | ||
3554 | /* | |
3555 | * Scan through our port list and login entries that need to be | |
3556 | * logged in. | |
3557 | */ | |
3558 | list_for_each_entry(fcport, &vha->vp_fcports, list) { | |
3559 | if (atomic_read(&vha->loop_down_timer) || | |
3560 | test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) | |
3561 | break; | |
3562 | ||
3563 | if ((fcport->flags & FCF_FABRIC_DEVICE) == 0 || | |
3564 | (fcport->flags & FCF_LOGIN_NEEDED) == 0) | |
3565 | continue; | |
3566 | ||
b2032fd5 RD |
3567 | /* |
3568 | * If we're not an initiator, skip looking for devices | |
3569 | * and logging in. There's no reason for us to do it, | |
3570 | * and it seems to actively cause problems in target | |
3571 | * mode if we race with the initiator logging into us | |
3572 | * (we might get the "port ID used" status back from | |
3573 | * our login command and log out the initiator, which | |
3574 | * seems to cause havoc). | |
3575 | */ | |
3576 | if (!qla_ini_mode_enabled(base_vha)) { | |
3577 | if (fcport->scan_state == QLA_FCPORT_FOUND) { | |
3578 | ql_dbg(ql_dbg_tgt_mgt, vha, 0xf078, | |
3579 | "port %8phC state 0x%x flags 0x%x fc4_type 0x%x " | |
3580 | "scan_state %d (initiator mode disabled; skipping " | |
3581 | "login)\n", fcport->port_name, | |
3582 | atomic_read(&fcport->state), | |
3583 | fcport->flags, fcport->fc4_type, | |
3584 | fcport->scan_state); | |
3585 | } | |
3586 | continue; | |
3587 | } | |
3588 | ||
e452ceb6 JC |
3589 | if (fcport->loop_id == FC_NO_LOOP_ID) { |
3590 | fcport->loop_id = next_loopid; | |
3591 | rval = qla2x00_find_new_loop_id( | |
3592 | base_vha, fcport); | |
3593 | if (rval != QLA_SUCCESS) { | |
3594 | /* Ran out of IDs to use */ | |
3595 | break; | |
1da177e4 LT |
3596 | } |
3597 | } | |
e452ceb6 JC |
3598 | /* Login and update database */ |
3599 | qla2x00_fabric_dev_login(vha, fcport, &next_loopid); | |
3600 | } | |
3601 | ||
3602 | /* Exit if out of loop IDs. */ | |
3603 | if (rval != QLA_SUCCESS) { | |
3604 | break; | |
3605 | } | |
3606 | ||
3607 | /* | |
3608 | * Login and add the new devices to our port list. | |
3609 | */ | |
3610 | list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) { | |
3611 | if (atomic_read(&vha->loop_down_timer) || | |
3612 | test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) | |
3613 | break; | |
3614 | ||
b2032fd5 RD |
3615 | /* |
3616 | * If we're not an initiator, skip looking for devices | |
3617 | * and logging in. There's no reason for us to do it, | |
3618 | * and it seems to actively cause problems in target | |
3619 | * mode if we race with the initiator logging into us | |
3620 | * (we might get the "port ID used" status back from | |
3621 | * our login command and log out the initiator, which | |
3622 | * seems to cause havoc). | |
3623 | */ | |
3624 | if (qla_ini_mode_enabled(base_vha)) { | |
3625 | /* Find a new loop ID to use. */ | |
3626 | fcport->loop_id = next_loopid; | |
3627 | rval = qla2x00_find_new_loop_id(base_vha, | |
3628 | fcport); | |
3629 | if (rval != QLA_SUCCESS) { | |
3630 | /* Ran out of IDs to use */ | |
3631 | break; | |
3632 | } | |
1da177e4 | 3633 | |
b2032fd5 RD |
3634 | /* Login and update database */ |
3635 | qla2x00_fabric_dev_login(vha, fcport, | |
3636 | &next_loopid); | |
3637 | } else { | |
3638 | ql_dbg(ql_dbg_tgt_mgt, vha, 0xf079, | |
3639 | "new port %8phC state 0x%x flags 0x%x fc4_type " | |
3640 | "0x%x scan_state %d (initiator mode disabled; " | |
3641 | "skipping login)\n", | |
3642 | fcport->port_name, | |
3643 | atomic_read(&fcport->state), | |
3644 | fcport->flags, fcport->fc4_type, | |
3645 | fcport->scan_state); | |
3646 | } | |
e452ceb6 JC |
3647 | |
3648 | list_move_tail(&fcport->list, &vha->vp_fcports); | |
1da177e4 LT |
3649 | } |
3650 | } while (0); | |
3651 | ||
e452ceb6 JC |
3652 | /* Free all new device structures not processed. */ |
3653 | list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) { | |
3654 | list_del(&fcport->list); | |
3655 | kfree(fcport); | |
3656 | } | |
3657 | ||
1da177e4 | 3658 | if (rval) { |
7c3df132 SK |
3659 | ql_dbg(ql_dbg_disc, vha, 0x2068, |
3660 | "Configure fabric error exit rval=%d.\n", rval); | |
1da177e4 LT |
3661 | } |
3662 | ||
3663 | return (rval); | |
3664 | } | |
3665 | ||
1da177e4 LT |
3666 | /* |
3667 | * qla2x00_find_all_fabric_devs | |
3668 | * | |
3669 | * Input: | |
3670 | * ha = adapter block pointer. | |
3671 | * dev = database device entry pointer. | |
3672 | * | |
3673 | * Returns: | |
3674 | * 0 = success. | |
3675 | * | |
3676 | * Context: | |
3677 | * Kernel context. | |
3678 | */ | |
3679 | static int | |
e315cd28 AC |
3680 | qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha, |
3681 | struct list_head *new_fcports) | |
1da177e4 LT |
3682 | { |
3683 | int rval; | |
3684 | uint16_t loop_id; | |
3685 | fc_port_t *fcport, *new_fcport, *fcptemp; | |
3686 | int found; | |
3687 | ||
3688 | sw_info_t *swl; | |
3689 | int swl_idx; | |
3690 | int first_dev, last_dev; | |
1516ef44 | 3691 | port_id_t wrap = {}, nxt_d_id; |
e315cd28 | 3692 | struct qla_hw_data *ha = vha->hw; |
bb4cf5b7 | 3693 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); |
1da177e4 LT |
3694 | |
3695 | rval = QLA_SUCCESS; | |
3696 | ||
3697 | /* Try GID_PT to get device list, else GAN. */ | |
7a67735b | 3698 | if (!ha->swl) |
642ef983 | 3699 | ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t), |
7a67735b AV |
3700 | GFP_KERNEL); |
3701 | swl = ha->swl; | |
bbfbbbc1 | 3702 | if (!swl) { |
1da177e4 | 3703 | /*EMPTY*/ |
7c3df132 SK |
3704 | ql_dbg(ql_dbg_disc, vha, 0x2054, |
3705 | "GID_PT allocations failed, fallback on GA_NXT.\n"); | |
1da177e4 | 3706 | } else { |
642ef983 | 3707 | memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t)); |
e315cd28 | 3708 | if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) { |
1da177e4 | 3709 | swl = NULL; |
e315cd28 | 3710 | } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) { |
1da177e4 | 3711 | swl = NULL; |
e315cd28 | 3712 | } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) { |
1da177e4 | 3713 | swl = NULL; |
e5896bd5 | 3714 | } else if (ql2xiidmaenable && |
e315cd28 AC |
3715 | qla2x00_gfpn_id(vha, swl) == QLA_SUCCESS) { |
3716 | qla2x00_gpsc(vha, swl); | |
1da177e4 | 3717 | } |
e8c72ba5 CD |
3718 | |
3719 | /* If other queries succeeded probe for FC-4 type */ | |
3720 | if (swl) | |
3721 | qla2x00_gff_id(vha, swl); | |
1da177e4 LT |
3722 | } |
3723 | swl_idx = 0; | |
3724 | ||
3725 | /* Allocate temporary fcport for any new fcports discovered. */ | |
e315cd28 | 3726 | new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); |
1da177e4 | 3727 | if (new_fcport == NULL) { |
7c3df132 SK |
3728 | ql_log(ql_log_warn, vha, 0x205e, |
3729 | "Failed to allocate memory for fcport.\n"); | |
1da177e4 LT |
3730 | return (QLA_MEMORY_ALLOC_FAILED); |
3731 | } | |
3732 | new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED); | |
1da177e4 LT |
3733 | /* Set start port ID scan at adapter ID. */ |
3734 | first_dev = 1; | |
3735 | last_dev = 0; | |
3736 | ||
3737 | /* Starting free loop ID. */ | |
e315cd28 AC |
3738 | loop_id = ha->min_external_loopid; |
3739 | for (; loop_id <= ha->max_loop_id; loop_id++) { | |
3740 | if (qla2x00_is_reserved_id(vha, loop_id)) | |
1da177e4 LT |
3741 | continue; |
3742 | ||
3a6478df GM |
3743 | if (ha->current_topology == ISP_CFG_FL && |
3744 | (atomic_read(&vha->loop_down_timer) || | |
3745 | LOOP_TRANSITION(vha))) { | |
bb2d52b2 AV |
3746 | atomic_set(&vha->loop_down_timer, 0); |
3747 | set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); | |
3748 | set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); | |
1da177e4 | 3749 | break; |
bb2d52b2 | 3750 | } |
1da177e4 LT |
3751 | |
3752 | if (swl != NULL) { | |
3753 | if (last_dev) { | |
3754 | wrap.b24 = new_fcport->d_id.b24; | |
3755 | } else { | |
3756 | new_fcport->d_id.b24 = swl[swl_idx].d_id.b24; | |
3757 | memcpy(new_fcport->node_name, | |
3758 | swl[swl_idx].node_name, WWN_SIZE); | |
3759 | memcpy(new_fcport->port_name, | |
3760 | swl[swl_idx].port_name, WWN_SIZE); | |
d8b45213 AV |
3761 | memcpy(new_fcport->fabric_port_name, |
3762 | swl[swl_idx].fabric_port_name, WWN_SIZE); | |
3763 | new_fcport->fp_speed = swl[swl_idx].fp_speed; | |
e8c72ba5 | 3764 | new_fcport->fc4_type = swl[swl_idx].fc4_type; |
1da177e4 LT |
3765 | |
3766 | if (swl[swl_idx].d_id.b.rsvd_1 != 0) { | |
3767 | last_dev = 1; | |
3768 | } | |
3769 | swl_idx++; | |
3770 | } | |
3771 | } else { | |
3772 | /* Send GA_NXT to the switch */ | |
e315cd28 | 3773 | rval = qla2x00_ga_nxt(vha, new_fcport); |
1da177e4 | 3774 | if (rval != QLA_SUCCESS) { |
7c3df132 SK |
3775 | ql_log(ql_log_warn, vha, 0x2064, |
3776 | "SNS scan failed -- assuming " | |
3777 | "zero-entry result.\n"); | |
1da177e4 LT |
3778 | list_for_each_entry_safe(fcport, fcptemp, |
3779 | new_fcports, list) { | |
3780 | list_del(&fcport->list); | |
3781 | kfree(fcport); | |
3782 | } | |
3783 | rval = QLA_SUCCESS; | |
3784 | break; | |
3785 | } | |
3786 | } | |
3787 | ||
3788 | /* If wrap on switch device list, exit. */ | |
3789 | if (first_dev) { | |
3790 | wrap.b24 = new_fcport->d_id.b24; | |
3791 | first_dev = 0; | |
3792 | } else if (new_fcport->d_id.b24 == wrap.b24) { | |
7c3df132 SK |
3793 | ql_dbg(ql_dbg_disc, vha, 0x2065, |
3794 | "Device wrap (%02x%02x%02x).\n", | |
3795 | new_fcport->d_id.b.domain, | |
3796 | new_fcport->d_id.b.area, | |
3797 | new_fcport->d_id.b.al_pa); | |
1da177e4 LT |
3798 | break; |
3799 | } | |
3800 | ||
2c3dfe3f | 3801 | /* Bypass if same physical adapter. */ |
e315cd28 | 3802 | if (new_fcport->d_id.b24 == base_vha->d_id.b24) |
1da177e4 LT |
3803 | continue; |
3804 | ||
2c3dfe3f | 3805 | /* Bypass virtual ports of the same host. */ |
bb4cf5b7 CD |
3806 | if (qla2x00_is_a_vp_did(vha, new_fcport->d_id.b24)) |
3807 | continue; | |
2c3dfe3f | 3808 | |
f7d289f6 AV |
3809 | /* Bypass if same domain and area of adapter. */ |
3810 | if (((new_fcport->d_id.b24 & 0xffff00) == | |
e315cd28 | 3811 | (vha->d_id.b24 & 0xffff00)) && ha->current_topology == |
f7d289f6 AV |
3812 | ISP_CFG_FL) |
3813 | continue; | |
3814 | ||
1da177e4 LT |
3815 | /* Bypass reserved domain fields. */ |
3816 | if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0) | |
3817 | continue; | |
3818 | ||
e8c72ba5 | 3819 | /* Bypass ports whose FCP-4 type is not FCP_SCSI */ |
4da26e16 CD |
3820 | if (ql2xgffidenable && |
3821 | (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI && | |
3822 | new_fcport->fc4_type != FC4_TYPE_UNKNOWN)) | |
e8c72ba5 CD |
3823 | continue; |
3824 | ||
1da177e4 LT |
3825 | /* Locate matching device in database. */ |
3826 | found = 0; | |
e315cd28 | 3827 | list_for_each_entry(fcport, &vha->vp_fcports, list) { |
1da177e4 LT |
3828 | if (memcmp(new_fcport->port_name, fcport->port_name, |
3829 | WWN_SIZE)) | |
3830 | continue; | |
3831 | ||
827210ba | 3832 | fcport->scan_state = QLA_FCPORT_FOUND; |
b3b02e6e | 3833 | |
1da177e4 LT |
3834 | found++; |
3835 | ||
d8b45213 AV |
3836 | /* Update port state. */ |
3837 | memcpy(fcport->fabric_port_name, | |
3838 | new_fcport->fabric_port_name, WWN_SIZE); | |
3839 | fcport->fp_speed = new_fcport->fp_speed; | |
3840 | ||
1da177e4 | 3841 | /* |
b2032fd5 RD |
3842 | * If address the same and state FCS_ONLINE |
3843 | * (or in target mode), nothing changed. | |
1da177e4 LT |
3844 | */ |
3845 | if (fcport->d_id.b24 == new_fcport->d_id.b24 && | |
b2032fd5 RD |
3846 | (atomic_read(&fcport->state) == FCS_ONLINE || |
3847 | !qla_ini_mode_enabled(base_vha))) { | |
1da177e4 LT |
3848 | break; |
3849 | } | |
3850 | ||
3851 | /* | |
3852 | * If device was not a fabric device before. | |
3853 | */ | |
3854 | if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) { | |
3855 | fcport->d_id.b24 = new_fcport->d_id.b24; | |
5f16b331 | 3856 | qla2x00_clear_loop_id(fcport); |
1da177e4 LT |
3857 | fcport->flags |= (FCF_FABRIC_DEVICE | |
3858 | FCF_LOGIN_NEEDED); | |
1da177e4 LT |
3859 | break; |
3860 | } | |
3861 | ||
3862 | /* | |
3863 | * Port ID changed or device was marked to be updated; | |
3864 | * Log it out if still logged in and mark it for | |
3865 | * relogin later. | |
3866 | */ | |
b2032fd5 RD |
3867 | if (!qla_ini_mode_enabled(base_vha)) { |
3868 | ql_dbg(ql_dbg_tgt_mgt, vha, 0xf080, | |
3869 | "port changed FC ID, %8phC" | |
3870 | " old %x:%x:%x (loop_id 0x%04x)-> new %x:%x:%x\n", | |
3871 | fcport->port_name, | |
3872 | fcport->d_id.b.domain, | |
3873 | fcport->d_id.b.area, | |
3874 | fcport->d_id.b.al_pa, | |
3875 | fcport->loop_id, | |
3876 | new_fcport->d_id.b.domain, | |
3877 | new_fcport->d_id.b.area, | |
3878 | new_fcport->d_id.b.al_pa); | |
3879 | fcport->d_id.b24 = new_fcport->d_id.b24; | |
3880 | break; | |
3881 | } | |
3882 | ||
1da177e4 LT |
3883 | fcport->d_id.b24 = new_fcport->d_id.b24; |
3884 | fcport->flags |= FCF_LOGIN_NEEDED; | |
3885 | if (fcport->loop_id != FC_NO_LOOP_ID && | |
f08b7251 | 3886 | (fcport->flags & FCF_FCP2_DEVICE) == 0 && |
0eba25df | 3887 | (fcport->flags & FCF_ASYNC_SENT) == 0 && |
1da177e4 LT |
3888 | fcport->port_type != FCT_INITIATOR && |
3889 | fcport->port_type != FCT_BROADCAST) { | |
e315cd28 | 3890 | ha->isp_ops->fabric_logout(vha, fcport->loop_id, |
1c7c6357 AV |
3891 | fcport->d_id.b.domain, fcport->d_id.b.area, |
3892 | fcport->d_id.b.al_pa); | |
5f16b331 | 3893 | qla2x00_clear_loop_id(fcport); |
1da177e4 LT |
3894 | } |
3895 | ||
3896 | break; | |
3897 | } | |
3898 | ||
3899 | if (found) | |
3900 | continue; | |
1da177e4 | 3901 | /* If device was not in our fcports list, then add it. */ |
b2032fd5 | 3902 | new_fcport->scan_state = QLA_FCPORT_FOUND; |
1da177e4 LT |
3903 | list_add_tail(&new_fcport->list, new_fcports); |
3904 | ||
3905 | /* Allocate a new replacement fcport. */ | |
3906 | nxt_d_id.b24 = new_fcport->d_id.b24; | |
e315cd28 | 3907 | new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); |
1da177e4 | 3908 | if (new_fcport == NULL) { |
7c3df132 SK |
3909 | ql_log(ql_log_warn, vha, 0x2066, |
3910 | "Memory allocation failed for fcport.\n"); | |
1da177e4 LT |
3911 | return (QLA_MEMORY_ALLOC_FAILED); |
3912 | } | |
3913 | new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED); | |
3914 | new_fcport->d_id.b24 = nxt_d_id.b24; | |
3915 | } | |
3916 | ||
c9475cb0 | 3917 | kfree(new_fcport); |
1da177e4 | 3918 | |
1da177e4 LT |
3919 | return (rval); |
3920 | } | |
3921 | ||
3922 | /* | |
3923 | * qla2x00_find_new_loop_id | |
3924 | * Scan through our port list and find a new usable loop ID. | |
3925 | * | |
3926 | * Input: | |
3927 | * ha: adapter state pointer. | |
3928 | * dev: port structure pointer. | |
3929 | * | |
3930 | * Returns: | |
3931 | * qla2x00 local function return status code. | |
3932 | * | |
3933 | * Context: | |
3934 | * Kernel context. | |
3935 | */ | |
03bcfb57 | 3936 | int |
e315cd28 | 3937 | qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev) |
1da177e4 LT |
3938 | { |
3939 | int rval; | |
e315cd28 | 3940 | struct qla_hw_data *ha = vha->hw; |
feafb7b1 | 3941 | unsigned long flags = 0; |
1da177e4 LT |
3942 | |
3943 | rval = QLA_SUCCESS; | |
3944 | ||
5f16b331 | 3945 | spin_lock_irqsave(&ha->vport_slock, flags); |
1da177e4 | 3946 | |
5f16b331 CD |
3947 | dev->loop_id = find_first_zero_bit(ha->loop_id_map, |
3948 | LOOPID_MAP_SIZE); | |
3949 | if (dev->loop_id >= LOOPID_MAP_SIZE || | |
3950 | qla2x00_is_reserved_id(vha, dev->loop_id)) { | |
3951 | dev->loop_id = FC_NO_LOOP_ID; | |
3952 | rval = QLA_FUNCTION_FAILED; | |
3953 | } else | |
3954 | set_bit(dev->loop_id, ha->loop_id_map); | |
1da177e4 | 3955 | |
5f16b331 | 3956 | spin_unlock_irqrestore(&ha->vport_slock, flags); |
1da177e4 | 3957 | |
5f16b331 CD |
3958 | if (rval == QLA_SUCCESS) |
3959 | ql_dbg(ql_dbg_disc, dev->vha, 0x2086, | |
3960 | "Assigning new loopid=%x, portid=%x.\n", | |
3961 | dev->loop_id, dev->d_id.b24); | |
3962 | else | |
3963 | ql_log(ql_log_warn, dev->vha, 0x2087, | |
3964 | "No loop_id's available, portid=%x.\n", | |
3965 | dev->d_id.b24); | |
1da177e4 LT |
3966 | |
3967 | return (rval); | |
3968 | } | |
3969 | ||
1da177e4 LT |
3970 | /* |
3971 | * qla2x00_fabric_dev_login | |
3972 | * Login fabric target device and update FC port database. | |
3973 | * | |
3974 | * Input: | |
3975 | * ha: adapter state pointer. | |
3976 | * fcport: port structure list pointer. | |
3977 | * next_loopid: contains value of a new loop ID that can be used | |
3978 | * by the next login attempt. | |
3979 | * | |
3980 | * Returns: | |
3981 | * qla2x00 local function return status code. | |
3982 | * | |
3983 | * Context: | |
3984 | * Kernel context. | |
3985 | */ | |
3986 | static int | |
e315cd28 | 3987 | qla2x00_fabric_dev_login(scsi_qla_host_t *vha, fc_port_t *fcport, |
1da177e4 LT |
3988 | uint16_t *next_loopid) |
3989 | { | |
3990 | int rval; | |
0107109e | 3991 | uint8_t opts; |
e315cd28 | 3992 | struct qla_hw_data *ha = vha->hw; |
1da177e4 LT |
3993 | |
3994 | rval = QLA_SUCCESS; | |
1da177e4 | 3995 | |
ac280b67 | 3996 | if (IS_ALOGIO_CAPABLE(ha)) { |
5ff1d584 AV |
3997 | if (fcport->flags & FCF_ASYNC_SENT) |
3998 | return rval; | |
3999 | fcport->flags |= FCF_ASYNC_SENT; | |
ac280b67 AV |
4000 | rval = qla2x00_post_async_login_work(vha, fcport, NULL); |
4001 | if (!rval) | |
4002 | return rval; | |
4003 | } | |
4004 | ||
5ff1d584 | 4005 | fcport->flags &= ~FCF_ASYNC_SENT; |
e315cd28 | 4006 | rval = qla2x00_fabric_login(vha, fcport, next_loopid); |
1da177e4 | 4007 | if (rval == QLA_SUCCESS) { |
f08b7251 | 4008 | /* Send an ADISC to FCP2 devices.*/ |
0107109e | 4009 | opts = 0; |
f08b7251 | 4010 | if (fcport->flags & FCF_FCP2_DEVICE) |
0107109e | 4011 | opts |= BIT_1; |
e315cd28 | 4012 | rval = qla2x00_get_port_database(vha, fcport, opts); |
1da177e4 | 4013 | if (rval != QLA_SUCCESS) { |
e315cd28 | 4014 | ha->isp_ops->fabric_logout(vha, fcport->loop_id, |
1c7c6357 AV |
4015 | fcport->d_id.b.domain, fcport->d_id.b.area, |
4016 | fcport->d_id.b.al_pa); | |
e315cd28 | 4017 | qla2x00_mark_device_lost(vha, fcport, 1, 0); |
1da177e4 | 4018 | } else { |
e315cd28 | 4019 | qla2x00_update_fcport(vha, fcport); |
1da177e4 | 4020 | } |
0b91d116 CD |
4021 | } else { |
4022 | /* Retry Login. */ | |
4023 | qla2x00_mark_device_lost(vha, fcport, 1, 0); | |
1da177e4 LT |
4024 | } |
4025 | ||
4026 | return (rval); | |
4027 | } | |
4028 | ||
4029 | /* | |
4030 | * qla2x00_fabric_login | |
4031 | * Issue fabric login command. | |
4032 | * | |
4033 | * Input: | |
4034 | * ha = adapter block pointer. | |
4035 | * device = pointer to FC device type structure. | |
4036 | * | |
4037 | * Returns: | |
4038 | * 0 - Login successfully | |
4039 | * 1 - Login failed | |
4040 | * 2 - Initiator device | |
4041 | * 3 - Fatal error | |
4042 | */ | |
4043 | int | |
e315cd28 | 4044 | qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport, |
1da177e4 LT |
4045 | uint16_t *next_loopid) |
4046 | { | |
4047 | int rval; | |
4048 | int retry; | |
4049 | uint16_t tmp_loopid; | |
4050 | uint16_t mb[MAILBOX_REGISTER_COUNT]; | |
e315cd28 | 4051 | struct qla_hw_data *ha = vha->hw; |
1da177e4 LT |
4052 | |
4053 | retry = 0; | |
4054 | tmp_loopid = 0; | |
4055 | ||
4056 | for (;;) { | |
7c3df132 SK |
4057 | ql_dbg(ql_dbg_disc, vha, 0x2000, |
4058 | "Trying Fabric Login w/loop id 0x%04x for port " | |
4059 | "%02x%02x%02x.\n", | |
4060 | fcport->loop_id, fcport->d_id.b.domain, | |
4061 | fcport->d_id.b.area, fcport->d_id.b.al_pa); | |
1da177e4 LT |
4062 | |
4063 | /* Login fcport on switch. */ | |
0b91d116 | 4064 | rval = ha->isp_ops->fabric_login(vha, fcport->loop_id, |
1da177e4 LT |
4065 | fcport->d_id.b.domain, fcport->d_id.b.area, |
4066 | fcport->d_id.b.al_pa, mb, BIT_0); | |
0b91d116 CD |
4067 | if (rval != QLA_SUCCESS) { |
4068 | return rval; | |
4069 | } | |
1da177e4 LT |
4070 | if (mb[0] == MBS_PORT_ID_USED) { |
4071 | /* | |
4072 | * Device has another loop ID. The firmware team | |
0107109e AV |
4073 | * recommends the driver perform an implicit login with |
4074 | * the specified ID again. The ID we just used is save | |
4075 | * here so we return with an ID that can be tried by | |
4076 | * the next login. | |
1da177e4 LT |
4077 | */ |
4078 | retry++; | |
4079 | tmp_loopid = fcport->loop_id; | |
4080 | fcport->loop_id = mb[1]; | |
4081 | ||
7c3df132 SK |
4082 | ql_dbg(ql_dbg_disc, vha, 0x2001, |
4083 | "Fabric Login: port in use - next loop " | |
4084 | "id=0x%04x, port id= %02x%02x%02x.\n", | |
1da177e4 | 4085 | fcport->loop_id, fcport->d_id.b.domain, |
7c3df132 | 4086 | fcport->d_id.b.area, fcport->d_id.b.al_pa); |
1da177e4 LT |
4087 | |
4088 | } else if (mb[0] == MBS_COMMAND_COMPLETE) { | |
4089 | /* | |
4090 | * Login succeeded. | |
4091 | */ | |
4092 | if (retry) { | |
4093 | /* A retry occurred before. */ | |
4094 | *next_loopid = tmp_loopid; | |
4095 | } else { | |
4096 | /* | |
4097 | * No retry occurred before. Just increment the | |
4098 | * ID value for next login. | |
4099 | */ | |
4100 | *next_loopid = (fcport->loop_id + 1); | |
4101 | } | |
4102 | ||
4103 | if (mb[1] & BIT_0) { | |
4104 | fcport->port_type = FCT_INITIATOR; | |
4105 | } else { | |
4106 | fcport->port_type = FCT_TARGET; | |
4107 | if (mb[1] & BIT_1) { | |
8474f3a0 | 4108 | fcport->flags |= FCF_FCP2_DEVICE; |
1da177e4 LT |
4109 | } |
4110 | } | |
4111 | ||
ad3e0eda AV |
4112 | if (mb[10] & BIT_0) |
4113 | fcport->supported_classes |= FC_COS_CLASS2; | |
4114 | if (mb[10] & BIT_1) | |
4115 | fcport->supported_classes |= FC_COS_CLASS3; | |
4116 | ||
2d70c103 NB |
4117 | if (IS_FWI2_CAPABLE(ha)) { |
4118 | if (mb[10] & BIT_7) | |
4119 | fcport->flags |= | |
4120 | FCF_CONF_COMP_SUPPORTED; | |
4121 | } | |
4122 | ||
1da177e4 LT |
4123 | rval = QLA_SUCCESS; |
4124 | break; | |
4125 | } else if (mb[0] == MBS_LOOP_ID_USED) { | |
4126 | /* | |
4127 | * Loop ID already used, try next loop ID. | |
4128 | */ | |
4129 | fcport->loop_id++; | |
e315cd28 | 4130 | rval = qla2x00_find_new_loop_id(vha, fcport); |
1da177e4 LT |
4131 | if (rval != QLA_SUCCESS) { |
4132 | /* Ran out of loop IDs to use */ | |
4133 | break; | |
4134 | } | |
4135 | } else if (mb[0] == MBS_COMMAND_ERROR) { | |
4136 | /* | |
4137 | * Firmware possibly timed out during login. If NO | |
4138 | * retries are left to do then the device is declared | |
4139 | * dead. | |
4140 | */ | |
4141 | *next_loopid = fcport->loop_id; | |
e315cd28 | 4142 | ha->isp_ops->fabric_logout(vha, fcport->loop_id, |
1c7c6357 AV |
4143 | fcport->d_id.b.domain, fcport->d_id.b.area, |
4144 | fcport->d_id.b.al_pa); | |
e315cd28 | 4145 | qla2x00_mark_device_lost(vha, fcport, 1, 0); |
1da177e4 LT |
4146 | |
4147 | rval = 1; | |
4148 | break; | |
4149 | } else { | |
4150 | /* | |
4151 | * unrecoverable / not handled error | |
4152 | */ | |
7c3df132 SK |
4153 | ql_dbg(ql_dbg_disc, vha, 0x2002, |
4154 | "Failed=%x port_id=%02x%02x%02x loop_id=%x " | |
4155 | "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain, | |
4156 | fcport->d_id.b.area, fcport->d_id.b.al_pa, | |
4157 | fcport->loop_id, jiffies); | |
1da177e4 LT |
4158 | |
4159 | *next_loopid = fcport->loop_id; | |
e315cd28 | 4160 | ha->isp_ops->fabric_logout(vha, fcport->loop_id, |
1c7c6357 AV |
4161 | fcport->d_id.b.domain, fcport->d_id.b.area, |
4162 | fcport->d_id.b.al_pa); | |
5f16b331 | 4163 | qla2x00_clear_loop_id(fcport); |
0eedfcf0 | 4164 | fcport->login_retry = 0; |
1da177e4 LT |
4165 | |
4166 | rval = 3; | |
4167 | break; | |
4168 | } | |
4169 | } | |
4170 | ||
4171 | return (rval); | |
4172 | } | |
4173 | ||
4174 | /* | |
4175 | * qla2x00_local_device_login | |
4176 | * Issue local device login command. | |
4177 | * | |
4178 | * Input: | |
4179 | * ha = adapter block pointer. | |
4180 | * loop_id = loop id of device to login to. | |
4181 | * | |
4182 | * Returns (Where's the #define!!!!): | |
4183 | * 0 - Login successfully | |
4184 | * 1 - Login failed | |
4185 | * 3 - Fatal error | |
4186 | */ | |
4187 | int | |
e315cd28 | 4188 | qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport) |
1da177e4 LT |
4189 | { |
4190 | int rval; | |
4191 | uint16_t mb[MAILBOX_REGISTER_COUNT]; | |
4192 | ||
4193 | memset(mb, 0, sizeof(mb)); | |
e315cd28 | 4194 | rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0); |
1da177e4 LT |
4195 | if (rval == QLA_SUCCESS) { |
4196 | /* Interrogate mailbox registers for any errors */ | |
4197 | if (mb[0] == MBS_COMMAND_ERROR) | |
4198 | rval = 1; | |
4199 | else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR) | |
4200 | /* device not in PCB table */ | |
4201 | rval = 3; | |
4202 | } | |
4203 | ||
4204 | return (rval); | |
4205 | } | |
4206 | ||
4207 | /* | |
4208 | * qla2x00_loop_resync | |
4209 | * Resync with fibre channel devices. | |
4210 | * | |
4211 | * Input: | |
4212 | * ha = adapter block pointer. | |
4213 | * | |
4214 | * Returns: | |
4215 | * 0 = success | |
4216 | */ | |
4217 | int | |
e315cd28 | 4218 | qla2x00_loop_resync(scsi_qla_host_t *vha) |
1da177e4 | 4219 | { |
73208dfd | 4220 | int rval = QLA_SUCCESS; |
1da177e4 | 4221 | uint32_t wait_time; |
67c2e93a AC |
4222 | struct req_que *req; |
4223 | struct rsp_que *rsp; | |
4224 | ||
7163ea81 | 4225 | if (vha->hw->flags.cpu_affinity_enabled) |
67c2e93a AC |
4226 | req = vha->hw->req_q_map[0]; |
4227 | else | |
4228 | req = vha->req; | |
4229 | rsp = req->rsp; | |
1da177e4 | 4230 | |
e315cd28 AC |
4231 | clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); |
4232 | if (vha->flags.online) { | |
4233 | if (!(rval = qla2x00_fw_ready(vha))) { | |
1da177e4 LT |
4234 | /* Wait at most MAX_TARGET RSCNs for a stable link. */ |
4235 | wait_time = 256; | |
4236 | do { | |
8ae6d9c7 GM |
4237 | if (!IS_QLAFX00(vha->hw)) { |
4238 | /* | |
4239 | * Issue a marker after FW becomes | |
4240 | * ready. | |
4241 | */ | |
4242 | qla2x00_marker(vha, req, rsp, 0, 0, | |
4243 | MK_SYNC_ALL); | |
4244 | vha->marker_needed = 0; | |
4245 | } | |
1da177e4 LT |
4246 | |
4247 | /* Remap devices on Loop. */ | |
e315cd28 | 4248 | clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); |
1da177e4 | 4249 | |
8ae6d9c7 GM |
4250 | if (IS_QLAFX00(vha->hw)) |
4251 | qlafx00_configure_devices(vha); | |
4252 | else | |
4253 | qla2x00_configure_loop(vha); | |
4254 | ||
1da177e4 | 4255 | wait_time--; |
e315cd28 AC |
4256 | } while (!atomic_read(&vha->loop_down_timer) && |
4257 | !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) | |
4258 | && wait_time && (test_bit(LOOP_RESYNC_NEEDED, | |
4259 | &vha->dpc_flags))); | |
1da177e4 | 4260 | } |
1da177e4 LT |
4261 | } |
4262 | ||
e315cd28 | 4263 | if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) |
1da177e4 | 4264 | return (QLA_FUNCTION_FAILED); |
1da177e4 | 4265 | |
e315cd28 | 4266 | if (rval) |
7c3df132 SK |
4267 | ql_dbg(ql_dbg_disc, vha, 0x206c, |
4268 | "%s *** FAILED ***.\n", __func__); | |
1da177e4 LT |
4269 | |
4270 | return (rval); | |
4271 | } | |
4272 | ||
579d12b5 SK |
4273 | /* |
4274 | * qla2x00_perform_loop_resync | |
4275 | * Description: This function will set the appropriate flags and call | |
4276 | * qla2x00_loop_resync. If successful loop will be resynced | |
4277 | * Arguments : scsi_qla_host_t pointer | |
4278 | * returm : Success or Failure | |
4279 | */ | |
4280 | ||
4281 | int qla2x00_perform_loop_resync(scsi_qla_host_t *ha) | |
4282 | { | |
4283 | int32_t rval = 0; | |
4284 | ||
4285 | if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) { | |
4286 | /*Configure the flags so that resync happens properly*/ | |
4287 | atomic_set(&ha->loop_down_timer, 0); | |
4288 | if (!(ha->device_flags & DFLG_NO_CABLE)) { | |
4289 | atomic_set(&ha->loop_state, LOOP_UP); | |
4290 | set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags); | |
4291 | set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags); | |
4292 | set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags); | |
4293 | ||
4294 | rval = qla2x00_loop_resync(ha); | |
4295 | } else | |
4296 | atomic_set(&ha->loop_state, LOOP_DEAD); | |
4297 | ||
4298 | clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags); | |
4299 | } | |
4300 | ||
4301 | return rval; | |
4302 | } | |
4303 | ||
d97994dc | 4304 | void |
67becc00 | 4305 | qla2x00_update_fcports(scsi_qla_host_t *base_vha) |
d97994dc AV |
4306 | { |
4307 | fc_port_t *fcport; | |
feafb7b1 AE |
4308 | struct scsi_qla_host *vha; |
4309 | struct qla_hw_data *ha = base_vha->hw; | |
4310 | unsigned long flags; | |
d97994dc | 4311 | |
feafb7b1 | 4312 | spin_lock_irqsave(&ha->vport_slock, flags); |
d97994dc | 4313 | /* Go with deferred removal of rport references. */ |
feafb7b1 AE |
4314 | list_for_each_entry(vha, &base_vha->hw->vp_list, list) { |
4315 | atomic_inc(&vha->vref_count); | |
4316 | list_for_each_entry(fcport, &vha->vp_fcports, list) { | |
8ae598d0 | 4317 | if (fcport->drport && |
feafb7b1 AE |
4318 | atomic_read(&fcport->state) != FCS_UNCONFIGURED) { |
4319 | spin_unlock_irqrestore(&ha->vport_slock, flags); | |
67becc00 | 4320 | qla2x00_rport_del(fcport); |
df673274 AP |
4321 | |
4322 | /* | |
4323 | * Release the target mode FC NEXUS in | |
4324 | * qla_target.c, if target mod is enabled. | |
4325 | */ | |
4326 | qlt_fc_port_deleted(vha, fcport, | |
4327 | base_vha->total_fcport_update_gen); | |
4328 | ||
feafb7b1 AE |
4329 | spin_lock_irqsave(&ha->vport_slock, flags); |
4330 | } | |
4331 | } | |
4332 | atomic_dec(&vha->vref_count); | |
4333 | } | |
4334 | spin_unlock_irqrestore(&ha->vport_slock, flags); | |
d97994dc AV |
4335 | } |
4336 | ||
7d613ac6 SV |
4337 | /* Assumes idc_lock always held on entry */ |
4338 | void | |
4339 | qla83xx_reset_ownership(scsi_qla_host_t *vha) | |
4340 | { | |
4341 | struct qla_hw_data *ha = vha->hw; | |
4342 | uint32_t drv_presence, drv_presence_mask; | |
4343 | uint32_t dev_part_info1, dev_part_info2, class_type; | |
4344 | uint32_t class_type_mask = 0x3; | |
4345 | uint16_t fcoe_other_function = 0xffff, i; | |
4346 | ||
7ec0effd AD |
4347 | if (IS_QLA8044(ha)) { |
4348 | drv_presence = qla8044_rd_direct(vha, | |
4349 | QLA8044_CRB_DRV_ACTIVE_INDEX); | |
4350 | dev_part_info1 = qla8044_rd_direct(vha, | |
4351 | QLA8044_CRB_DEV_PART_INFO_INDEX); | |
4352 | dev_part_info2 = qla8044_rd_direct(vha, | |
4353 | QLA8044_CRB_DEV_PART_INFO2); | |
4354 | } else { | |
4355 | qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); | |
4356 | qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1); | |
4357 | qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2); | |
4358 | } | |
7d613ac6 SV |
4359 | for (i = 0; i < 8; i++) { |
4360 | class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask); | |
4361 | if ((class_type == QLA83XX_CLASS_TYPE_FCOE) && | |
4362 | (i != ha->portnum)) { | |
4363 | fcoe_other_function = i; | |
4364 | break; | |
4365 | } | |
4366 | } | |
4367 | if (fcoe_other_function == 0xffff) { | |
4368 | for (i = 0; i < 8; i++) { | |
4369 | class_type = ((dev_part_info2 >> (i * 4)) & | |
4370 | class_type_mask); | |
4371 | if ((class_type == QLA83XX_CLASS_TYPE_FCOE) && | |
4372 | ((i + 8) != ha->portnum)) { | |
4373 | fcoe_other_function = i + 8; | |
4374 | break; | |
4375 | } | |
4376 | } | |
4377 | } | |
4378 | /* | |
4379 | * Prepare drv-presence mask based on fcoe functions present. | |
4380 | * However consider only valid physical fcoe function numbers (0-15). | |
4381 | */ | |
4382 | drv_presence_mask = ~((1 << (ha->portnum)) | | |
4383 | ((fcoe_other_function == 0xffff) ? | |
4384 | 0 : (1 << (fcoe_other_function)))); | |
4385 | ||
4386 | /* We are the reset owner iff: | |
4387 | * - No other protocol drivers present. | |
4388 | * - This is the lowest among fcoe functions. */ | |
4389 | if (!(drv_presence & drv_presence_mask) && | |
4390 | (ha->portnum < fcoe_other_function)) { | |
4391 | ql_dbg(ql_dbg_p3p, vha, 0xb07f, | |
4392 | "This host is Reset owner.\n"); | |
4393 | ha->flags.nic_core_reset_owner = 1; | |
4394 | } | |
4395 | } | |
4396 | ||
fa492630 | 4397 | static int |
7d613ac6 SV |
4398 | __qla83xx_set_drv_ack(scsi_qla_host_t *vha) |
4399 | { | |
4400 | int rval = QLA_SUCCESS; | |
4401 | struct qla_hw_data *ha = vha->hw; | |
4402 | uint32_t drv_ack; | |
4403 | ||
4404 | rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); | |
4405 | if (rval == QLA_SUCCESS) { | |
4406 | drv_ack |= (1 << ha->portnum); | |
4407 | rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack); | |
4408 | } | |
4409 | ||
4410 | return rval; | |
4411 | } | |
4412 | ||
fa492630 | 4413 | static int |
7d613ac6 SV |
4414 | __qla83xx_clear_drv_ack(scsi_qla_host_t *vha) |
4415 | { | |
4416 | int rval = QLA_SUCCESS; | |
4417 | struct qla_hw_data *ha = vha->hw; | |
4418 | uint32_t drv_ack; | |
4419 | ||
4420 | rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); | |
4421 | if (rval == QLA_SUCCESS) { | |
4422 | drv_ack &= ~(1 << ha->portnum); | |
4423 | rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack); | |
4424 | } | |
4425 | ||
4426 | return rval; | |
4427 | } | |
4428 | ||
fa492630 | 4429 | static const char * |
7d613ac6 SV |
4430 | qla83xx_dev_state_to_string(uint32_t dev_state) |
4431 | { | |
4432 | switch (dev_state) { | |
4433 | case QLA8XXX_DEV_COLD: | |
4434 | return "COLD/RE-INIT"; | |
4435 | case QLA8XXX_DEV_INITIALIZING: | |
4436 | return "INITIALIZING"; | |
4437 | case QLA8XXX_DEV_READY: | |
4438 | return "READY"; | |
4439 | case QLA8XXX_DEV_NEED_RESET: | |
4440 | return "NEED RESET"; | |
4441 | case QLA8XXX_DEV_NEED_QUIESCENT: | |
4442 | return "NEED QUIESCENT"; | |
4443 | case QLA8XXX_DEV_FAILED: | |
4444 | return "FAILED"; | |
4445 | case QLA8XXX_DEV_QUIESCENT: | |
4446 | return "QUIESCENT"; | |
4447 | default: | |
4448 | return "Unknown"; | |
4449 | } | |
4450 | } | |
4451 | ||
4452 | /* Assumes idc-lock always held on entry */ | |
4453 | void | |
4454 | qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type) | |
4455 | { | |
4456 | struct qla_hw_data *ha = vha->hw; | |
4457 | uint32_t idc_audit_reg = 0, duration_secs = 0; | |
4458 | ||
4459 | switch (audit_type) { | |
4460 | case IDC_AUDIT_TIMESTAMP: | |
4461 | ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000); | |
4462 | idc_audit_reg = (ha->portnum) | | |
4463 | (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8); | |
4464 | qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg); | |
4465 | break; | |
4466 | ||
4467 | case IDC_AUDIT_COMPLETION: | |
4468 | duration_secs = ((jiffies_to_msecs(jiffies) - | |
4469 | jiffies_to_msecs(ha->idc_audit_ts)) / 1000); | |
4470 | idc_audit_reg = (ha->portnum) | | |
4471 | (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8); | |
4472 | qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg); | |
4473 | break; | |
4474 | ||
4475 | default: | |
4476 | ql_log(ql_log_warn, vha, 0xb078, | |
4477 | "Invalid audit type specified.\n"); | |
4478 | break; | |
4479 | } | |
4480 | } | |
4481 | ||
4482 | /* Assumes idc_lock always held on entry */ | |
fa492630 | 4483 | static int |
7d613ac6 SV |
4484 | qla83xx_initiating_reset(scsi_qla_host_t *vha) |
4485 | { | |
4486 | struct qla_hw_data *ha = vha->hw; | |
4487 | uint32_t idc_control, dev_state; | |
4488 | ||
4489 | __qla83xx_get_idc_control(vha, &idc_control); | |
4490 | if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) { | |
4491 | ql_log(ql_log_info, vha, 0xb080, | |
4492 | "NIC Core reset has been disabled. idc-control=0x%x\n", | |
4493 | idc_control); | |
4494 | return QLA_FUNCTION_FAILED; | |
4495 | } | |
4496 | ||
4497 | /* Set NEED-RESET iff in READY state and we are the reset-owner */ | |
4498 | qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state); | |
4499 | if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) { | |
4500 | qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, | |
4501 | QLA8XXX_DEV_NEED_RESET); | |
4502 | ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n"); | |
4503 | qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP); | |
4504 | } else { | |
4505 | const char *state = qla83xx_dev_state_to_string(dev_state); | |
4506 | ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n", state); | |
4507 | ||
4508 | /* SV: XXX: Is timeout required here? */ | |
4509 | /* Wait for IDC state change READY -> NEED_RESET */ | |
4510 | while (dev_state == QLA8XXX_DEV_READY) { | |
4511 | qla83xx_idc_unlock(vha, 0); | |
4512 | msleep(200); | |
4513 | qla83xx_idc_lock(vha, 0); | |
4514 | qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state); | |
4515 | } | |
4516 | } | |
4517 | ||
4518 | /* Send IDC ack by writing to drv-ack register */ | |
4519 | __qla83xx_set_drv_ack(vha); | |
4520 | ||
4521 | return QLA_SUCCESS; | |
4522 | } | |
4523 | ||
4524 | int | |
4525 | __qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control) | |
4526 | { | |
4527 | return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control); | |
4528 | } | |
4529 | ||
7d613ac6 SV |
4530 | int |
4531 | __qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control) | |
4532 | { | |
4533 | return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control); | |
4534 | } | |
4535 | ||
fa492630 | 4536 | static int |
7d613ac6 SV |
4537 | qla83xx_check_driver_presence(scsi_qla_host_t *vha) |
4538 | { | |
4539 | uint32_t drv_presence = 0; | |
4540 | struct qla_hw_data *ha = vha->hw; | |
4541 | ||
4542 | qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); | |
4543 | if (drv_presence & (1 << ha->portnum)) | |
4544 | return QLA_SUCCESS; | |
4545 | else | |
4546 | return QLA_TEST_FAILED; | |
4547 | } | |
4548 | ||
4549 | int | |
4550 | qla83xx_nic_core_reset(scsi_qla_host_t *vha) | |
4551 | { | |
4552 | int rval = QLA_SUCCESS; | |
4553 | struct qla_hw_data *ha = vha->hw; | |
4554 | ||
4555 | ql_dbg(ql_dbg_p3p, vha, 0xb058, | |
4556 | "Entered %s().\n", __func__); | |
4557 | ||
4558 | if (vha->device_flags & DFLG_DEV_FAILED) { | |
4559 | ql_log(ql_log_warn, vha, 0xb059, | |
4560 | "Device in unrecoverable FAILED state.\n"); | |
4561 | return QLA_FUNCTION_FAILED; | |
4562 | } | |
4563 | ||
4564 | qla83xx_idc_lock(vha, 0); | |
4565 | ||
4566 | if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) { | |
4567 | ql_log(ql_log_warn, vha, 0xb05a, | |
4568 | "Function=0x%x has been removed from IDC participation.\n", | |
4569 | ha->portnum); | |
4570 | rval = QLA_FUNCTION_FAILED; | |
4571 | goto exit; | |
4572 | } | |
4573 | ||
4574 | qla83xx_reset_ownership(vha); | |
4575 | ||
4576 | rval = qla83xx_initiating_reset(vha); | |
4577 | ||
4578 | /* | |
4579 | * Perform reset if we are the reset-owner, | |
4580 | * else wait till IDC state changes to READY/FAILED. | |
4581 | */ | |
4582 | if (rval == QLA_SUCCESS) { | |
4583 | rval = qla83xx_idc_state_handler(vha); | |
4584 | ||
4585 | if (rval == QLA_SUCCESS) | |
4586 | ha->flags.nic_core_hung = 0; | |
4587 | __qla83xx_clear_drv_ack(vha); | |
4588 | } | |
4589 | ||
4590 | exit: | |
4591 | qla83xx_idc_unlock(vha, 0); | |
4592 | ||
4593 | ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__); | |
4594 | ||
4595 | return rval; | |
4596 | } | |
4597 | ||
81178772 SK |
4598 | int |
4599 | qla2xxx_mctp_dump(scsi_qla_host_t *vha) | |
4600 | { | |
4601 | struct qla_hw_data *ha = vha->hw; | |
4602 | int rval = QLA_FUNCTION_FAILED; | |
4603 | ||
4604 | if (!IS_MCTP_CAPABLE(ha)) { | |
4605 | /* This message can be removed from the final version */ | |
4606 | ql_log(ql_log_info, vha, 0x506d, | |
4607 | "This board is not MCTP capable\n"); | |
4608 | return rval; | |
4609 | } | |
4610 | ||
4611 | if (!ha->mctp_dump) { | |
4612 | ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev, | |
4613 | MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL); | |
4614 | ||
4615 | if (!ha->mctp_dump) { | |
4616 | ql_log(ql_log_warn, vha, 0x506e, | |
4617 | "Failed to allocate memory for mctp dump\n"); | |
4618 | return rval; | |
4619 | } | |
4620 | } | |
4621 | ||
4622 | #define MCTP_DUMP_STR_ADDR 0x00000000 | |
4623 | rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma, | |
4624 | MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4); | |
4625 | if (rval != QLA_SUCCESS) { | |
4626 | ql_log(ql_log_warn, vha, 0x506f, | |
4627 | "Failed to capture mctp dump\n"); | |
4628 | } else { | |
4629 | ql_log(ql_log_info, vha, 0x5070, | |
4630 | "Mctp dump capture for host (%ld/%p).\n", | |
4631 | vha->host_no, ha->mctp_dump); | |
4632 | ha->mctp_dumped = 1; | |
4633 | } | |
4634 | ||
409ee0fe | 4635 | if (!ha->flags.nic_core_reset_hdlr_active && !ha->portnum) { |
81178772 SK |
4636 | ha->flags.nic_core_reset_hdlr_active = 1; |
4637 | rval = qla83xx_restart_nic_firmware(vha); | |
4638 | if (rval) | |
4639 | /* NIC Core reset failed. */ | |
4640 | ql_log(ql_log_warn, vha, 0x5071, | |
4641 | "Failed to restart nic firmware\n"); | |
4642 | else | |
4643 | ql_dbg(ql_dbg_p3p, vha, 0xb084, | |
4644 | "Restarted NIC firmware successfully.\n"); | |
4645 | ha->flags.nic_core_reset_hdlr_active = 0; | |
4646 | } | |
4647 | ||
4648 | return rval; | |
4649 | ||
4650 | } | |
4651 | ||
579d12b5 | 4652 | /* |
8fcd6b8b | 4653 | * qla2x00_quiesce_io |
579d12b5 SK |
4654 | * Description: This function will block the new I/Os |
4655 | * Its not aborting any I/Os as context | |
4656 | * is not destroyed during quiescence | |
4657 | * Arguments: scsi_qla_host_t | |
4658 | * return : void | |
4659 | */ | |
4660 | void | |
8fcd6b8b | 4661 | qla2x00_quiesce_io(scsi_qla_host_t *vha) |
579d12b5 SK |
4662 | { |
4663 | struct qla_hw_data *ha = vha->hw; | |
4664 | struct scsi_qla_host *vp; | |
4665 | ||
8fcd6b8b CD |
4666 | ql_dbg(ql_dbg_dpc, vha, 0x401d, |
4667 | "Quiescing I/O - ha=%p.\n", ha); | |
579d12b5 SK |
4668 | |
4669 | atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME); | |
4670 | if (atomic_read(&vha->loop_state) != LOOP_DOWN) { | |
4671 | atomic_set(&vha->loop_state, LOOP_DOWN); | |
4672 | qla2x00_mark_all_devices_lost(vha, 0); | |
4673 | list_for_each_entry(vp, &ha->vp_list, list) | |
8fcd6b8b | 4674 | qla2x00_mark_all_devices_lost(vp, 0); |
579d12b5 SK |
4675 | } else { |
4676 | if (!atomic_read(&vha->loop_down_timer)) | |
4677 | atomic_set(&vha->loop_down_timer, | |
4678 | LOOP_DOWN_TIME); | |
4679 | } | |
4680 | /* Wait for pending cmds to complete */ | |
4681 | qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST); | |
4682 | } | |
4683 | ||
a9083016 GM |
4684 | void |
4685 | qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha) | |
4686 | { | |
4687 | struct qla_hw_data *ha = vha->hw; | |
579d12b5 | 4688 | struct scsi_qla_host *vp; |
feafb7b1 | 4689 | unsigned long flags; |
6aef87be | 4690 | fc_port_t *fcport; |
a9083016 | 4691 | |
e46ef004 SK |
4692 | /* For ISP82XX, driver waits for completion of the commands. |
4693 | * online flag should be set. | |
4694 | */ | |
7ec0effd | 4695 | if (!(IS_P3P_TYPE(ha))) |
e46ef004 | 4696 | vha->flags.online = 0; |
a9083016 GM |
4697 | ha->flags.chip_reset_done = 0; |
4698 | clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); | |
2be21fa2 | 4699 | vha->qla_stats.total_isp_aborts++; |
a9083016 | 4700 | |
7c3df132 SK |
4701 | ql_log(ql_log_info, vha, 0x00af, |
4702 | "Performing ISP error recovery - ha=%p.\n", ha); | |
a9083016 | 4703 | |
e46ef004 SK |
4704 | /* For ISP82XX, reset_chip is just disabling interrupts. |
4705 | * Driver waits for the completion of the commands. | |
4706 | * the interrupts need to be enabled. | |
4707 | */ | |
7ec0effd | 4708 | if (!(IS_P3P_TYPE(ha))) |
a9083016 GM |
4709 | ha->isp_ops->reset_chip(vha); |
4710 | ||
4711 | atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); | |
4712 | if (atomic_read(&vha->loop_state) != LOOP_DOWN) { | |
4713 | atomic_set(&vha->loop_state, LOOP_DOWN); | |
4714 | qla2x00_mark_all_devices_lost(vha, 0); | |
feafb7b1 AE |
4715 | |
4716 | spin_lock_irqsave(&ha->vport_slock, flags); | |
579d12b5 | 4717 | list_for_each_entry(vp, &ha->vp_list, list) { |
feafb7b1 AE |
4718 | atomic_inc(&vp->vref_count); |
4719 | spin_unlock_irqrestore(&ha->vport_slock, flags); | |
4720 | ||
a9083016 | 4721 | qla2x00_mark_all_devices_lost(vp, 0); |
feafb7b1 AE |
4722 | |
4723 | spin_lock_irqsave(&ha->vport_slock, flags); | |
4724 | atomic_dec(&vp->vref_count); | |
4725 | } | |
4726 | spin_unlock_irqrestore(&ha->vport_slock, flags); | |
a9083016 GM |
4727 | } else { |
4728 | if (!atomic_read(&vha->loop_down_timer)) | |
4729 | atomic_set(&vha->loop_down_timer, | |
4730 | LOOP_DOWN_TIME); | |
4731 | } | |
4732 | ||
6aef87be AV |
4733 | /* Clear all async request states across all VPs. */ |
4734 | list_for_each_entry(fcport, &vha->vp_fcports, list) | |
4735 | fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); | |
4736 | spin_lock_irqsave(&ha->vport_slock, flags); | |
4737 | list_for_each_entry(vp, &ha->vp_list, list) { | |
4738 | atomic_inc(&vp->vref_count); | |
4739 | spin_unlock_irqrestore(&ha->vport_slock, flags); | |
4740 | ||
4741 | list_for_each_entry(fcport, &vp->vp_fcports, list) | |
4742 | fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); | |
4743 | ||
4744 | spin_lock_irqsave(&ha->vport_slock, flags); | |
4745 | atomic_dec(&vp->vref_count); | |
4746 | } | |
4747 | spin_unlock_irqrestore(&ha->vport_slock, flags); | |
4748 | ||
bddd2d65 LC |
4749 | if (!ha->flags.eeh_busy) { |
4750 | /* Make sure for ISP 82XX IO DMA is complete */ | |
7ec0effd | 4751 | if (IS_P3P_TYPE(ha)) { |
7190575f | 4752 | qla82xx_chip_reset_cleanup(vha); |
7c3df132 SK |
4753 | ql_log(ql_log_info, vha, 0x00b4, |
4754 | "Done chip reset cleanup.\n"); | |
a9083016 | 4755 | |
e46ef004 SK |
4756 | /* Done waiting for pending commands. |
4757 | * Reset the online flag. | |
4758 | */ | |
4759 | vha->flags.online = 0; | |
4d78c973 | 4760 | } |
a9083016 | 4761 | |
bddd2d65 LC |
4762 | /* Requeue all commands in outstanding command list. */ |
4763 | qla2x00_abort_all_cmds(vha, DID_RESET << 16); | |
4764 | } | |
b6a029e1 AE |
4765 | |
4766 | ha->chip_reset++; | |
4767 | /* memory barrier */ | |
4768 | wmb(); | |
a9083016 GM |
4769 | } |
4770 | ||
1da177e4 LT |
4771 | /* |
4772 | * qla2x00_abort_isp | |
4773 | * Resets ISP and aborts all outstanding commands. | |
4774 | * | |
4775 | * Input: | |
4776 | * ha = adapter block pointer. | |
4777 | * | |
4778 | * Returns: | |
4779 | * 0 = success | |
4780 | */ | |
4781 | int | |
e315cd28 | 4782 | qla2x00_abort_isp(scsi_qla_host_t *vha) |
1da177e4 | 4783 | { |
476e8978 | 4784 | int rval; |
1da177e4 | 4785 | uint8_t status = 0; |
e315cd28 AC |
4786 | struct qla_hw_data *ha = vha->hw; |
4787 | struct scsi_qla_host *vp; | |
73208dfd | 4788 | struct req_que *req = ha->req_q_map[0]; |
feafb7b1 | 4789 | unsigned long flags; |
1da177e4 | 4790 | |
e315cd28 | 4791 | if (vha->flags.online) { |
a9083016 | 4792 | qla2x00_abort_isp_cleanup(vha); |
1da177e4 | 4793 | |
a6171297 SV |
4794 | if (IS_QLA8031(ha)) { |
4795 | ql_dbg(ql_dbg_p3p, vha, 0xb05c, | |
4796 | "Clearing fcoe driver presence.\n"); | |
4797 | if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS) | |
4798 | ql_dbg(ql_dbg_p3p, vha, 0xb073, | |
4799 | "Error while clearing DRV-Presence.\n"); | |
4800 | } | |
4801 | ||
85880801 AV |
4802 | if (unlikely(pci_channel_offline(ha->pdev) && |
4803 | ha->flags.pci_channel_io_perm_failure)) { | |
4804 | clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); | |
4805 | status = 0; | |
4806 | return status; | |
4807 | } | |
4808 | ||
73208dfd | 4809 | ha->isp_ops->get_flash_version(vha, req->ring); |
30c47662 | 4810 | |
e315cd28 | 4811 | ha->isp_ops->nvram_config(vha); |
1da177e4 | 4812 | |
e315cd28 AC |
4813 | if (!qla2x00_restart_isp(vha)) { |
4814 | clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); | |
1da177e4 | 4815 | |
e315cd28 | 4816 | if (!atomic_read(&vha->loop_down_timer)) { |
1da177e4 LT |
4817 | /* |
4818 | * Issue marker command only when we are going | |
4819 | * to start the I/O . | |
4820 | */ | |
e315cd28 | 4821 | vha->marker_needed = 1; |
1da177e4 LT |
4822 | } |
4823 | ||
e315cd28 | 4824 | vha->flags.online = 1; |
1da177e4 | 4825 | |
fd34f556 | 4826 | ha->isp_ops->enable_intrs(ha); |
1da177e4 | 4827 | |
fa2a1ce5 | 4828 | ha->isp_abort_cnt = 0; |
e315cd28 | 4829 | clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); |
476e8978 | 4830 | |
6246b8a1 GM |
4831 | if (IS_QLA81XX(ha) || IS_QLA8031(ha)) |
4832 | qla2x00_get_fw_version(vha); | |
df613b96 AV |
4833 | if (ha->fce) { |
4834 | ha->flags.fce_enabled = 1; | |
4835 | memset(ha->fce, 0, | |
4836 | fce_calc_size(ha->fce_bufs)); | |
e315cd28 | 4837 | rval = qla2x00_enable_fce_trace(vha, |
df613b96 AV |
4838 | ha->fce_dma, ha->fce_bufs, ha->fce_mb, |
4839 | &ha->fce_bufs); | |
4840 | if (rval) { | |
7c3df132 | 4841 | ql_log(ql_log_warn, vha, 0x8033, |
df613b96 AV |
4842 | "Unable to reinitialize FCE " |
4843 | "(%d).\n", rval); | |
4844 | ha->flags.fce_enabled = 0; | |
4845 | } | |
4846 | } | |
436a7b11 AV |
4847 | |
4848 | if (ha->eft) { | |
4849 | memset(ha->eft, 0, EFT_SIZE); | |
e315cd28 | 4850 | rval = qla2x00_enable_eft_trace(vha, |
436a7b11 AV |
4851 | ha->eft_dma, EFT_NUM_BUFFERS); |
4852 | if (rval) { | |
7c3df132 | 4853 | ql_log(ql_log_warn, vha, 0x8034, |
436a7b11 AV |
4854 | "Unable to reinitialize EFT " |
4855 | "(%d).\n", rval); | |
4856 | } | |
4857 | } | |
1da177e4 | 4858 | } else { /* failed the ISP abort */ |
e315cd28 AC |
4859 | vha->flags.online = 1; |
4860 | if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { | |
1da177e4 | 4861 | if (ha->isp_abort_cnt == 0) { |
7c3df132 SK |
4862 | ql_log(ql_log_fatal, vha, 0x8035, |
4863 | "ISP error recover failed - " | |
4864 | "board disabled.\n"); | |
fa2a1ce5 | 4865 | /* |
1da177e4 LT |
4866 | * The next call disables the board |
4867 | * completely. | |
4868 | */ | |
e315cd28 AC |
4869 | ha->isp_ops->reset_adapter(vha); |
4870 | vha->flags.online = 0; | |
1da177e4 | 4871 | clear_bit(ISP_ABORT_RETRY, |
e315cd28 | 4872 | &vha->dpc_flags); |
1da177e4 LT |
4873 | status = 0; |
4874 | } else { /* schedule another ISP abort */ | |
4875 | ha->isp_abort_cnt--; | |
7c3df132 SK |
4876 | ql_dbg(ql_dbg_taskm, vha, 0x8020, |
4877 | "ISP abort - retry remaining %d.\n", | |
4878 | ha->isp_abort_cnt); | |
1da177e4 LT |
4879 | status = 1; |
4880 | } | |
4881 | } else { | |
4882 | ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT; | |
7c3df132 SK |
4883 | ql_dbg(ql_dbg_taskm, vha, 0x8021, |
4884 | "ISP error recovery - retrying (%d) " | |
4885 | "more times.\n", ha->isp_abort_cnt); | |
e315cd28 | 4886 | set_bit(ISP_ABORT_RETRY, &vha->dpc_flags); |
1da177e4 LT |
4887 | status = 1; |
4888 | } | |
4889 | } | |
fa2a1ce5 | 4890 | |
1da177e4 LT |
4891 | } |
4892 | ||
e315cd28 | 4893 | if (!status) { |
7c3df132 | 4894 | ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__); |
feafb7b1 AE |
4895 | |
4896 | spin_lock_irqsave(&ha->vport_slock, flags); | |
4897 | list_for_each_entry(vp, &ha->vp_list, list) { | |
4898 | if (vp->vp_idx) { | |
4899 | atomic_inc(&vp->vref_count); | |
4900 | spin_unlock_irqrestore(&ha->vport_slock, flags); | |
4901 | ||
e315cd28 | 4902 | qla2x00_vp_abort_isp(vp); |
feafb7b1 AE |
4903 | |
4904 | spin_lock_irqsave(&ha->vport_slock, flags); | |
4905 | atomic_dec(&vp->vref_count); | |
4906 | } | |
e315cd28 | 4907 | } |
feafb7b1 AE |
4908 | spin_unlock_irqrestore(&ha->vport_slock, flags); |
4909 | ||
7d613ac6 SV |
4910 | if (IS_QLA8031(ha)) { |
4911 | ql_dbg(ql_dbg_p3p, vha, 0xb05d, | |
4912 | "Setting back fcoe driver presence.\n"); | |
4913 | if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS) | |
4914 | ql_dbg(ql_dbg_p3p, vha, 0xb074, | |
4915 | "Error while setting DRV-Presence.\n"); | |
4916 | } | |
e315cd28 | 4917 | } else { |
d8424f68 JP |
4918 | ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n", |
4919 | __func__); | |
1da177e4 LT |
4920 | } |
4921 | ||
4922 | return(status); | |
4923 | } | |
4924 | ||
4925 | /* | |
4926 | * qla2x00_restart_isp | |
4927 | * restarts the ISP after a reset | |
4928 | * | |
4929 | * Input: | |
4930 | * ha = adapter block pointer. | |
4931 | * | |
4932 | * Returns: | |
4933 | * 0 = success | |
4934 | */ | |
4935 | static int | |
e315cd28 | 4936 | qla2x00_restart_isp(scsi_qla_host_t *vha) |
1da177e4 | 4937 | { |
c6b2fca8 | 4938 | int status = 0; |
e315cd28 | 4939 | struct qla_hw_data *ha = vha->hw; |
73208dfd AC |
4940 | struct req_que *req = ha->req_q_map[0]; |
4941 | struct rsp_que *rsp = ha->rsp_q_map[0]; | |
1da177e4 LT |
4942 | |
4943 | /* If firmware needs to be loaded */ | |
e315cd28 AC |
4944 | if (qla2x00_isp_firmware(vha)) { |
4945 | vha->flags.online = 0; | |
4946 | status = ha->isp_ops->chip_diag(vha); | |
4947 | if (!status) | |
4948 | status = qla2x00_setup_chip(vha); | |
1da177e4 LT |
4949 | } |
4950 | ||
e315cd28 AC |
4951 | if (!status && !(status = qla2x00_init_rings(vha))) { |
4952 | clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); | |
2533cf67 | 4953 | ha->flags.chip_reset_done = 1; |
7108b76e | 4954 | |
73208dfd AC |
4955 | /* Initialize the queues in use */ |
4956 | qla25xx_init_queues(ha); | |
4957 | ||
e315cd28 AC |
4958 | status = qla2x00_fw_ready(vha); |
4959 | if (!status) { | |
0107109e | 4960 | /* Issue a marker after FW becomes ready. */ |
73208dfd | 4961 | qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL); |
0107109e | 4962 | |
7108b76e | 4963 | set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); |
1da177e4 LT |
4964 | } |
4965 | ||
4966 | /* if no cable then assume it's good */ | |
e315cd28 | 4967 | if ((vha->device_flags & DFLG_NO_CABLE)) |
1da177e4 | 4968 | status = 0; |
1da177e4 LT |
4969 | } |
4970 | return (status); | |
4971 | } | |
4972 | ||
73208dfd AC |
4973 | static int |
4974 | qla25xx_init_queues(struct qla_hw_data *ha) | |
4975 | { | |
4976 | struct rsp_que *rsp = NULL; | |
4977 | struct req_que *req = NULL; | |
4978 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); | |
4979 | int ret = -1; | |
4980 | int i; | |
4981 | ||
2afa19a9 | 4982 | for (i = 1; i < ha->max_rsp_queues; i++) { |
73208dfd | 4983 | rsp = ha->rsp_q_map[i]; |
cb43285f | 4984 | if (rsp && test_bit(i, ha->rsp_qid_map)) { |
73208dfd | 4985 | rsp->options &= ~BIT_0; |
618a7523 | 4986 | ret = qla25xx_init_rsp_que(base_vha, rsp); |
73208dfd | 4987 | if (ret != QLA_SUCCESS) |
7c3df132 SK |
4988 | ql_dbg(ql_dbg_init, base_vha, 0x00ff, |
4989 | "%s Rsp que: %d init failed.\n", | |
4990 | __func__, rsp->id); | |
73208dfd | 4991 | else |
7c3df132 SK |
4992 | ql_dbg(ql_dbg_init, base_vha, 0x0100, |
4993 | "%s Rsp que: %d inited.\n", | |
4994 | __func__, rsp->id); | |
73208dfd | 4995 | } |
2afa19a9 AC |
4996 | } |
4997 | for (i = 1; i < ha->max_req_queues; i++) { | |
73208dfd | 4998 | req = ha->req_q_map[i]; |
cb43285f QT |
4999 | if (req && test_bit(i, ha->req_qid_map)) { |
5000 | /* Clear outstanding commands array. */ | |
73208dfd | 5001 | req->options &= ~BIT_0; |
618a7523 | 5002 | ret = qla25xx_init_req_que(base_vha, req); |
73208dfd | 5003 | if (ret != QLA_SUCCESS) |
7c3df132 SK |
5004 | ql_dbg(ql_dbg_init, base_vha, 0x0101, |
5005 | "%s Req que: %d init failed.\n", | |
5006 | __func__, req->id); | |
73208dfd | 5007 | else |
7c3df132 SK |
5008 | ql_dbg(ql_dbg_init, base_vha, 0x0102, |
5009 | "%s Req que: %d inited.\n", | |
5010 | __func__, req->id); | |
73208dfd AC |
5011 | } |
5012 | } | |
5013 | return ret; | |
5014 | } | |
5015 | ||
1da177e4 LT |
5016 | /* |
5017 | * qla2x00_reset_adapter | |
5018 | * Reset adapter. | |
5019 | * | |
5020 | * Input: | |
5021 | * ha = adapter block pointer. | |
5022 | */ | |
abbd8870 | 5023 | void |
e315cd28 | 5024 | qla2x00_reset_adapter(scsi_qla_host_t *vha) |
1da177e4 LT |
5025 | { |
5026 | unsigned long flags = 0; | |
e315cd28 | 5027 | struct qla_hw_data *ha = vha->hw; |
3d71644c | 5028 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
1da177e4 | 5029 | |
e315cd28 | 5030 | vha->flags.online = 0; |
fd34f556 | 5031 | ha->isp_ops->disable_intrs(ha); |
1da177e4 | 5032 | |
1da177e4 LT |
5033 | spin_lock_irqsave(&ha->hardware_lock, flags); |
5034 | WRT_REG_WORD(®->hccr, HCCR_RESET_RISC); | |
5035 | RD_REG_WORD(®->hccr); /* PCI Posting. */ | |
5036 | WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); | |
5037 | RD_REG_WORD(®->hccr); /* PCI Posting. */ | |
5038 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
5039 | } | |
0107109e AV |
5040 | |
5041 | void | |
e315cd28 | 5042 | qla24xx_reset_adapter(scsi_qla_host_t *vha) |
0107109e AV |
5043 | { |
5044 | unsigned long flags = 0; | |
e315cd28 | 5045 | struct qla_hw_data *ha = vha->hw; |
0107109e AV |
5046 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
5047 | ||
7ec0effd | 5048 | if (IS_P3P_TYPE(ha)) |
a9083016 GM |
5049 | return; |
5050 | ||
e315cd28 | 5051 | vha->flags.online = 0; |
fd34f556 | 5052 | ha->isp_ops->disable_intrs(ha); |
0107109e AV |
5053 | |
5054 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
5055 | WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_RESET); | |
5056 | RD_REG_DWORD(®->hccr); | |
5057 | WRT_REG_DWORD(®->hccr, HCCRX_REL_RISC_PAUSE); | |
5058 | RD_REG_DWORD(®->hccr); | |
5059 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
09ff36d3 AV |
5060 | |
5061 | if (IS_NOPOLLING_TYPE(ha)) | |
5062 | ha->isp_ops->enable_intrs(ha); | |
0107109e AV |
5063 | } |
5064 | ||
4e08df3f DM |
5065 | /* On sparc systems, obtain port and node WWN from firmware |
5066 | * properties. | |
5067 | */ | |
e315cd28 AC |
5068 | static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, |
5069 | struct nvram_24xx *nv) | |
4e08df3f DM |
5070 | { |
5071 | #ifdef CONFIG_SPARC | |
e315cd28 | 5072 | struct qla_hw_data *ha = vha->hw; |
4e08df3f | 5073 | struct pci_dev *pdev = ha->pdev; |
15576bc8 DM |
5074 | struct device_node *dp = pci_device_to_OF_node(pdev); |
5075 | const u8 *val; | |
4e08df3f DM |
5076 | int len; |
5077 | ||
5078 | val = of_get_property(dp, "port-wwn", &len); | |
5079 | if (val && len >= WWN_SIZE) | |
5080 | memcpy(nv->port_name, val, WWN_SIZE); | |
5081 | ||
5082 | val = of_get_property(dp, "node-wwn", &len); | |
5083 | if (val && len >= WWN_SIZE) | |
5084 | memcpy(nv->node_name, val, WWN_SIZE); | |
5085 | #endif | |
5086 | } | |
5087 | ||
0107109e | 5088 | int |
e315cd28 | 5089 | qla24xx_nvram_config(scsi_qla_host_t *vha) |
0107109e | 5090 | { |
4e08df3f | 5091 | int rval; |
0107109e AV |
5092 | struct init_cb_24xx *icb; |
5093 | struct nvram_24xx *nv; | |
5094 | uint32_t *dptr; | |
5095 | uint8_t *dptr1, *dptr2; | |
5096 | uint32_t chksum; | |
5097 | uint16_t cnt; | |
e315cd28 | 5098 | struct qla_hw_data *ha = vha->hw; |
0107109e | 5099 | |
4e08df3f | 5100 | rval = QLA_SUCCESS; |
0107109e | 5101 | icb = (struct init_cb_24xx *)ha->init_cb; |
281afe19 | 5102 | nv = ha->nvram; |
0107109e AV |
5103 | |
5104 | /* Determine NVRAM starting address. */ | |
f73cb695 | 5105 | if (ha->port_no == 0) { |
e5b68a61 AC |
5106 | ha->nvram_base = FA_NVRAM_FUNC0_ADDR; |
5107 | ha->vpd_base = FA_NVRAM_VPD0_ADDR; | |
5108 | } else { | |
0107109e | 5109 | ha->nvram_base = FA_NVRAM_FUNC1_ADDR; |
6f641790 AV |
5110 | ha->vpd_base = FA_NVRAM_VPD1_ADDR; |
5111 | } | |
f73cb695 | 5112 | |
e5b68a61 AC |
5113 | ha->nvram_size = sizeof(struct nvram_24xx); |
5114 | ha->vpd_size = FA_NVRAM_VPD_SIZE; | |
0107109e | 5115 | |
281afe19 SJ |
5116 | /* Get VPD data into cache */ |
5117 | ha->vpd = ha->nvram + VPD_OFFSET; | |
e315cd28 | 5118 | ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd, |
281afe19 SJ |
5119 | ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4); |
5120 | ||
5121 | /* Get NVRAM data into cache and calculate checksum. */ | |
0107109e | 5122 | dptr = (uint32_t *)nv; |
e315cd28 | 5123 | ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base, |
0107109e AV |
5124 | ha->nvram_size); |
5125 | for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++) | |
5126 | chksum += le32_to_cpu(*dptr++); | |
5127 | ||
7c3df132 SK |
5128 | ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a, |
5129 | "Contents of NVRAM\n"); | |
5130 | ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d, | |
5131 | (uint8_t *)nv, ha->nvram_size); | |
0107109e AV |
5132 | |
5133 | /* Bad NVRAM data, set defaults parameters. */ | |
5134 | if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P' | |
5135 | || nv->id[3] != ' ' || | |
ad950360 | 5136 | nv->nvram_version < cpu_to_le16(ICB_VERSION)) { |
0107109e | 5137 | /* Reset NVRAM data. */ |
7c3df132 | 5138 | ql_log(ql_log_warn, vha, 0x006b, |
9e336520 | 5139 | "Inconsistent NVRAM detected: checksum=0x%x id=%c " |
7c3df132 SK |
5140 | "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version); |
5141 | ql_log(ql_log_warn, vha, 0x006c, | |
5142 | "Falling back to functioning (yet invalid -- WWPN) " | |
5143 | "defaults.\n"); | |
4e08df3f DM |
5144 | |
5145 | /* | |
5146 | * Set default initialization control block. | |
5147 | */ | |
5148 | memset(nv, 0, ha->nvram_size); | |
ad950360 BVA |
5149 | nv->nvram_version = cpu_to_le16(ICB_VERSION); |
5150 | nv->version = cpu_to_le16(ICB_VERSION); | |
98aee70d | 5151 | nv->frame_payload_size = 2048; |
ad950360 BVA |
5152 | nv->execution_throttle = cpu_to_le16(0xFFFF); |
5153 | nv->exchange_count = cpu_to_le16(0); | |
5154 | nv->hard_address = cpu_to_le16(124); | |
4e08df3f | 5155 | nv->port_name[0] = 0x21; |
f73cb695 | 5156 | nv->port_name[1] = 0x00 + ha->port_no + 1; |
4e08df3f DM |
5157 | nv->port_name[2] = 0x00; |
5158 | nv->port_name[3] = 0xe0; | |
5159 | nv->port_name[4] = 0x8b; | |
5160 | nv->port_name[5] = 0x1c; | |
5161 | nv->port_name[6] = 0x55; | |
5162 | nv->port_name[7] = 0x86; | |
5163 | nv->node_name[0] = 0x20; | |
5164 | nv->node_name[1] = 0x00; | |
5165 | nv->node_name[2] = 0x00; | |
5166 | nv->node_name[3] = 0xe0; | |
5167 | nv->node_name[4] = 0x8b; | |
5168 | nv->node_name[5] = 0x1c; | |
5169 | nv->node_name[6] = 0x55; | |
5170 | nv->node_name[7] = 0x86; | |
e315cd28 | 5171 | qla24xx_nvram_wwn_from_ofw(vha, nv); |
ad950360 BVA |
5172 | nv->login_retry_count = cpu_to_le16(8); |
5173 | nv->interrupt_delay_timer = cpu_to_le16(0); | |
5174 | nv->login_timeout = cpu_to_le16(0); | |
4e08df3f | 5175 | nv->firmware_options_1 = |
ad950360 BVA |
5176 | cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1); |
5177 | nv->firmware_options_2 = cpu_to_le32(2 << 4); | |
5178 | nv->firmware_options_2 |= cpu_to_le32(BIT_12); | |
5179 | nv->firmware_options_3 = cpu_to_le32(2 << 13); | |
5180 | nv->host_p = cpu_to_le32(BIT_11|BIT_10); | |
5181 | nv->efi_parameters = cpu_to_le32(0); | |
4e08df3f | 5182 | nv->reset_delay = 5; |
ad950360 BVA |
5183 | nv->max_luns_per_target = cpu_to_le16(128); |
5184 | nv->port_down_retry_count = cpu_to_le16(30); | |
5185 | nv->link_down_timeout = cpu_to_le16(30); | |
4e08df3f DM |
5186 | |
5187 | rval = 1; | |
0107109e AV |
5188 | } |
5189 | ||
2d70c103 NB |
5190 | if (!qla_ini_mode_enabled(vha)) { |
5191 | /* Don't enable full login after initial LIP */ | |
ad950360 | 5192 | nv->firmware_options_1 &= cpu_to_le32(~BIT_13); |
2d70c103 | 5193 | /* Don't enable LIP full login for initiator */ |
ad950360 | 5194 | nv->host_p &= cpu_to_le32(~BIT_10); |
2d70c103 NB |
5195 | } |
5196 | ||
5197 | qlt_24xx_config_nvram_stage1(vha, nv); | |
5198 | ||
0107109e | 5199 | /* Reset Initialization control block */ |
e315cd28 | 5200 | memset(icb, 0, ha->init_cb_size); |
0107109e AV |
5201 | |
5202 | /* Copy 1st segment. */ | |
5203 | dptr1 = (uint8_t *)icb; | |
5204 | dptr2 = (uint8_t *)&nv->version; | |
5205 | cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version; | |
5206 | while (cnt--) | |
5207 | *dptr1++ = *dptr2++; | |
5208 | ||
5209 | icb->login_retry_count = nv->login_retry_count; | |
3ea66e28 | 5210 | icb->link_down_on_nos = nv->link_down_on_nos; |
0107109e AV |
5211 | |
5212 | /* Copy 2nd segment. */ | |
5213 | dptr1 = (uint8_t *)&icb->interrupt_delay_timer; | |
5214 | dptr2 = (uint8_t *)&nv->interrupt_delay_timer; | |
5215 | cnt = (uint8_t *)&icb->reserved_3 - | |
5216 | (uint8_t *)&icb->interrupt_delay_timer; | |
5217 | while (cnt--) | |
5218 | *dptr1++ = *dptr2++; | |
5219 | ||
5220 | /* | |
5221 | * Setup driver NVRAM options. | |
5222 | */ | |
e315cd28 | 5223 | qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name), |
9bb9fcf2 | 5224 | "QLA2462"); |
0107109e | 5225 | |
2d70c103 NB |
5226 | qlt_24xx_config_nvram_stage2(vha, icb); |
5227 | ||
ad950360 | 5228 | if (nv->host_p & cpu_to_le32(BIT_15)) { |
2d70c103 | 5229 | /* Use alternate WWN? */ |
5341e868 AV |
5230 | memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE); |
5231 | memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE); | |
5232 | } | |
5233 | ||
0107109e | 5234 | /* Prepare nodename */ |
ad950360 | 5235 | if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) { |
0107109e AV |
5236 | /* |
5237 | * Firmware will apply the following mask if the nodename was | |
5238 | * not provided. | |
5239 | */ | |
5240 | memcpy(icb->node_name, icb->port_name, WWN_SIZE); | |
5241 | icb->node_name[0] &= 0xF0; | |
5242 | } | |
5243 | ||
5244 | /* Set host adapter parameters. */ | |
5245 | ha->flags.disable_risc_code_load = 0; | |
0c8c39af AV |
5246 | ha->flags.enable_lip_reset = 0; |
5247 | ha->flags.enable_lip_full_login = | |
5248 | le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0; | |
5249 | ha->flags.enable_target_reset = | |
5250 | le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0; | |
0107109e | 5251 | ha->flags.enable_led_scheme = 0; |
d4c760c2 | 5252 | ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0; |
0107109e | 5253 | |
fd0e7e4d AV |
5254 | ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) & |
5255 | (BIT_6 | BIT_5 | BIT_4)) >> 4; | |
0107109e AV |
5256 | |
5257 | memcpy(ha->fw_seriallink_options24, nv->seriallink_options, | |
5258 | sizeof(ha->fw_seriallink_options24)); | |
5259 | ||
5260 | /* save HBA serial number */ | |
5261 | ha->serial0 = icb->port_name[5]; | |
5262 | ha->serial1 = icb->port_name[6]; | |
5263 | ha->serial2 = icb->port_name[7]; | |
e315cd28 AC |
5264 | memcpy(vha->node_name, icb->node_name, WWN_SIZE); |
5265 | memcpy(vha->port_name, icb->port_name, WWN_SIZE); | |
0107109e | 5266 | |
ad950360 | 5267 | icb->execution_throttle = cpu_to_le16(0xFFFF); |
bc8fb3cb | 5268 | |
0107109e AV |
5269 | ha->retry_count = le16_to_cpu(nv->login_retry_count); |
5270 | ||
5271 | /* Set minimum login_timeout to 4 seconds. */ | |
5272 | if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout) | |
5273 | nv->login_timeout = cpu_to_le16(ql2xlogintimeout); | |
5274 | if (le16_to_cpu(nv->login_timeout) < 4) | |
ad950360 | 5275 | nv->login_timeout = cpu_to_le16(4); |
0107109e | 5276 | ha->login_timeout = le16_to_cpu(nv->login_timeout); |
c6852c4c | 5277 | icb->login_timeout = nv->login_timeout; |
0107109e | 5278 | |
00a537b8 AV |
5279 | /* Set minimum RATOV to 100 tenths of a second. */ |
5280 | ha->r_a_tov = 100; | |
0107109e AV |
5281 | |
5282 | ha->loop_reset_delay = nv->reset_delay; | |
5283 | ||
5284 | /* Link Down Timeout = 0: | |
5285 | * | |
5286 | * When Port Down timer expires we will start returning | |
5287 | * I/O's to OS with "DID_NO_CONNECT". | |
5288 | * | |
5289 | * Link Down Timeout != 0: | |
5290 | * | |
5291 | * The driver waits for the link to come up after link down | |
5292 | * before returning I/Os to OS with "DID_NO_CONNECT". | |
5293 | */ | |
5294 | if (le16_to_cpu(nv->link_down_timeout) == 0) { | |
5295 | ha->loop_down_abort_time = | |
5296 | (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT); | |
5297 | } else { | |
5298 | ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout); | |
5299 | ha->loop_down_abort_time = | |
5300 | (LOOP_DOWN_TIME - ha->link_down_timeout); | |
5301 | } | |
5302 | ||
5303 | /* Need enough time to try and get the port back. */ | |
5304 | ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count); | |
5305 | if (qlport_down_retry) | |
5306 | ha->port_down_retry_count = qlport_down_retry; | |
5307 | ||
5308 | /* Set login_retry_count */ | |
5309 | ha->login_retry_count = le16_to_cpu(nv->login_retry_count); | |
5310 | if (ha->port_down_retry_count == | |
5311 | le16_to_cpu(nv->port_down_retry_count) && | |
5312 | ha->port_down_retry_count > 3) | |
5313 | ha->login_retry_count = ha->port_down_retry_count; | |
5314 | else if (ha->port_down_retry_count > (int)ha->login_retry_count) | |
5315 | ha->login_retry_count = ha->port_down_retry_count; | |
5316 | if (ql2xloginretrycount) | |
5317 | ha->login_retry_count = ql2xloginretrycount; | |
5318 | ||
4fdfefe5 | 5319 | /* Enable ZIO. */ |
e315cd28 | 5320 | if (!vha->flags.init_done) { |
4fdfefe5 AV |
5321 | ha->zio_mode = le32_to_cpu(icb->firmware_options_2) & |
5322 | (BIT_3 | BIT_2 | BIT_1 | BIT_0); | |
5323 | ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ? | |
5324 | le16_to_cpu(icb->interrupt_delay_timer): 2; | |
5325 | } | |
ad950360 | 5326 | icb->firmware_options_2 &= cpu_to_le32( |
4fdfefe5 | 5327 | ~(BIT_3 | BIT_2 | BIT_1 | BIT_0)); |
e315cd28 | 5328 | vha->flags.process_response_queue = 0; |
4fdfefe5 | 5329 | if (ha->zio_mode != QLA_ZIO_DISABLED) { |
4a59f71d AV |
5330 | ha->zio_mode = QLA_ZIO_MODE_6; |
5331 | ||
7c3df132 | 5332 | ql_log(ql_log_info, vha, 0x006f, |
4fdfefe5 AV |
5333 | "ZIO mode %d enabled; timer delay (%d us).\n", |
5334 | ha->zio_mode, ha->zio_timer * 100); | |
5335 | ||
5336 | icb->firmware_options_2 |= cpu_to_le32( | |
5337 | (uint32_t)ha->zio_mode); | |
5338 | icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer); | |
e315cd28 | 5339 | vha->flags.process_response_queue = 1; |
4fdfefe5 AV |
5340 | } |
5341 | ||
4e08df3f | 5342 | if (rval) { |
7c3df132 SK |
5343 | ql_log(ql_log_warn, vha, 0x0070, |
5344 | "NVRAM configuration failed.\n"); | |
4e08df3f DM |
5345 | } |
5346 | return (rval); | |
0107109e AV |
5347 | } |
5348 | ||
413975a0 | 5349 | static int |
cbc8eb67 AV |
5350 | qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr, |
5351 | uint32_t faddr) | |
d1c61909 | 5352 | { |
73208dfd | 5353 | int rval = QLA_SUCCESS; |
d1c61909 | 5354 | int segments, fragment; |
d1c61909 AV |
5355 | uint32_t *dcode, dlen; |
5356 | uint32_t risc_addr; | |
5357 | uint32_t risc_size; | |
5358 | uint32_t i; | |
e315cd28 | 5359 | struct qla_hw_data *ha = vha->hw; |
73208dfd | 5360 | struct req_que *req = ha->req_q_map[0]; |
eaac30be | 5361 | |
7c3df132 | 5362 | ql_dbg(ql_dbg_init, vha, 0x008b, |
cfb0919c | 5363 | "FW: Loading firmware from flash (%x).\n", faddr); |
eaac30be | 5364 | |
d1c61909 AV |
5365 | rval = QLA_SUCCESS; |
5366 | ||
5367 | segments = FA_RISC_CODE_SEGMENTS; | |
73208dfd | 5368 | dcode = (uint32_t *)req->ring; |
d1c61909 AV |
5369 | *srisc_addr = 0; |
5370 | ||
5371 | /* Validate firmware image by checking version. */ | |
e315cd28 | 5372 | qla24xx_read_flash_data(vha, dcode, faddr + 4, 4); |
d1c61909 AV |
5373 | for (i = 0; i < 4; i++) |
5374 | dcode[i] = be32_to_cpu(dcode[i]); | |
5375 | if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff && | |
5376 | dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) || | |
5377 | (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 && | |
5378 | dcode[3] == 0)) { | |
7c3df132 SK |
5379 | ql_log(ql_log_fatal, vha, 0x008c, |
5380 | "Unable to verify the integrity of flash firmware " | |
5381 | "image.\n"); | |
5382 | ql_log(ql_log_fatal, vha, 0x008d, | |
5383 | "Firmware data: %08x %08x %08x %08x.\n", | |
5384 | dcode[0], dcode[1], dcode[2], dcode[3]); | |
d1c61909 AV |
5385 | |
5386 | return QLA_FUNCTION_FAILED; | |
5387 | } | |
5388 | ||
5389 | while (segments && rval == QLA_SUCCESS) { | |
5390 | /* Read segment's load information. */ | |
e315cd28 | 5391 | qla24xx_read_flash_data(vha, dcode, faddr, 4); |
d1c61909 AV |
5392 | |
5393 | risc_addr = be32_to_cpu(dcode[2]); | |
5394 | *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr; | |
5395 | risc_size = be32_to_cpu(dcode[3]); | |
5396 | ||
5397 | fragment = 0; | |
5398 | while (risc_size > 0 && rval == QLA_SUCCESS) { | |
5399 | dlen = (uint32_t)(ha->fw_transfer_size >> 2); | |
5400 | if (dlen > risc_size) | |
5401 | dlen = risc_size; | |
5402 | ||
7c3df132 SK |
5403 | ql_dbg(ql_dbg_init, vha, 0x008e, |
5404 | "Loading risc segment@ risc addr %x " | |
5405 | "number of dwords 0x%x offset 0x%x.\n", | |
5406 | risc_addr, dlen, faddr); | |
d1c61909 | 5407 | |
e315cd28 | 5408 | qla24xx_read_flash_data(vha, dcode, faddr, dlen); |
d1c61909 AV |
5409 | for (i = 0; i < dlen; i++) |
5410 | dcode[i] = swab32(dcode[i]); | |
5411 | ||
73208dfd | 5412 | rval = qla2x00_load_ram(vha, req->dma, risc_addr, |
d1c61909 AV |
5413 | dlen); |
5414 | if (rval) { | |
7c3df132 SK |
5415 | ql_log(ql_log_fatal, vha, 0x008f, |
5416 | "Failed to load segment %d of firmware.\n", | |
5417 | fragment); | |
f261f7af | 5418 | return QLA_FUNCTION_FAILED; |
d1c61909 AV |
5419 | } |
5420 | ||
5421 | faddr += dlen; | |
5422 | risc_addr += dlen; | |
5423 | risc_size -= dlen; | |
5424 | fragment++; | |
5425 | } | |
5426 | ||
5427 | /* Next segment. */ | |
5428 | segments--; | |
5429 | } | |
5430 | ||
f73cb695 CD |
5431 | if (!IS_QLA27XX(ha)) |
5432 | return rval; | |
5433 | ||
5434 | if (ha->fw_dump_template) | |
5435 | vfree(ha->fw_dump_template); | |
5436 | ha->fw_dump_template = NULL; | |
5437 | ha->fw_dump_template_len = 0; | |
5438 | ||
5439 | ql_dbg(ql_dbg_init, vha, 0x0161, | |
5440 | "Loading fwdump template from %x\n", faddr); | |
5441 | qla24xx_read_flash_data(vha, dcode, faddr, 7); | |
5442 | risc_size = be32_to_cpu(dcode[2]); | |
5443 | ql_dbg(ql_dbg_init, vha, 0x0162, | |
5444 | "-> array size %x dwords\n", risc_size); | |
5445 | if (risc_size == 0 || risc_size == ~0) | |
5446 | goto default_template; | |
5447 | ||
5448 | dlen = (risc_size - 8) * sizeof(*dcode); | |
5449 | ql_dbg(ql_dbg_init, vha, 0x0163, | |
5450 | "-> template allocating %x bytes...\n", dlen); | |
5451 | ha->fw_dump_template = vmalloc(dlen); | |
5452 | if (!ha->fw_dump_template) { | |
5453 | ql_log(ql_log_warn, vha, 0x0164, | |
5454 | "Failed fwdump template allocate %x bytes.\n", risc_size); | |
5455 | goto default_template; | |
5456 | } | |
5457 | ||
5458 | faddr += 7; | |
5459 | risc_size -= 8; | |
5460 | dcode = ha->fw_dump_template; | |
5461 | qla24xx_read_flash_data(vha, dcode, faddr, risc_size); | |
5462 | for (i = 0; i < risc_size; i++) | |
5463 | dcode[i] = le32_to_cpu(dcode[i]); | |
5464 | ||
5465 | if (!qla27xx_fwdt_template_valid(dcode)) { | |
5466 | ql_log(ql_log_warn, vha, 0x0165, | |
5467 | "Failed fwdump template validate\n"); | |
5468 | goto default_template; | |
5469 | } | |
5470 | ||
5471 | dlen = qla27xx_fwdt_template_size(dcode); | |
5472 | ql_dbg(ql_dbg_init, vha, 0x0166, | |
5473 | "-> template size %x bytes\n", dlen); | |
5474 | if (dlen > risc_size * sizeof(*dcode)) { | |
5475 | ql_log(ql_log_warn, vha, 0x0167, | |
97ea702b CD |
5476 | "Failed fwdump template exceeds array by %x bytes\n", |
5477 | (uint32_t)(dlen - risc_size * sizeof(*dcode))); | |
f73cb695 CD |
5478 | goto default_template; |
5479 | } | |
5480 | ha->fw_dump_template_len = dlen; | |
5481 | return rval; | |
5482 | ||
5483 | default_template: | |
5484 | ql_log(ql_log_warn, vha, 0x0168, "Using default fwdump template\n"); | |
5485 | if (ha->fw_dump_template) | |
5486 | vfree(ha->fw_dump_template); | |
5487 | ha->fw_dump_template = NULL; | |
5488 | ha->fw_dump_template_len = 0; | |
5489 | ||
5490 | dlen = qla27xx_fwdt_template_default_size(); | |
5491 | ql_dbg(ql_dbg_init, vha, 0x0169, | |
5492 | "-> template allocating %x bytes...\n", dlen); | |
5493 | ha->fw_dump_template = vmalloc(dlen); | |
5494 | if (!ha->fw_dump_template) { | |
5495 | ql_log(ql_log_warn, vha, 0x016a, | |
5496 | "Failed fwdump template allocate %x bytes.\n", risc_size); | |
5497 | goto failed_template; | |
5498 | } | |
5499 | ||
5500 | dcode = ha->fw_dump_template; | |
5501 | risc_size = dlen / sizeof(*dcode); | |
5502 | memcpy(dcode, qla27xx_fwdt_template_default(), dlen); | |
5503 | for (i = 0; i < risc_size; i++) | |
5504 | dcode[i] = be32_to_cpu(dcode[i]); | |
5505 | ||
5506 | if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) { | |
5507 | ql_log(ql_log_warn, vha, 0x016b, | |
5508 | "Failed fwdump template validate\n"); | |
5509 | goto failed_template; | |
5510 | } | |
5511 | ||
5512 | dlen = qla27xx_fwdt_template_size(ha->fw_dump_template); | |
5513 | ql_dbg(ql_dbg_init, vha, 0x016c, | |
5514 | "-> template size %x bytes\n", dlen); | |
5515 | ha->fw_dump_template_len = dlen; | |
5516 | return rval; | |
5517 | ||
5518 | failed_template: | |
5519 | ql_log(ql_log_warn, vha, 0x016d, "Failed default fwdump template\n"); | |
5520 | if (ha->fw_dump_template) | |
5521 | vfree(ha->fw_dump_template); | |
5522 | ha->fw_dump_template = NULL; | |
5523 | ha->fw_dump_template_len = 0; | |
d1c61909 AV |
5524 | return rval; |
5525 | } | |
5526 | ||
e9454a88 | 5527 | #define QLA_FW_URL "http://ldriver.qlogic.com/firmware/" |
d1c61909 | 5528 | |
0107109e | 5529 | int |
e315cd28 | 5530 | qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) |
5433383e AV |
5531 | { |
5532 | int rval; | |
5533 | int i, fragment; | |
5534 | uint16_t *wcode, *fwcode; | |
5535 | uint32_t risc_addr, risc_size, fwclen, wlen, *seg; | |
5536 | struct fw_blob *blob; | |
e315cd28 | 5537 | struct qla_hw_data *ha = vha->hw; |
73208dfd | 5538 | struct req_que *req = ha->req_q_map[0]; |
5433383e AV |
5539 | |
5540 | /* Load firmware blob. */ | |
e315cd28 | 5541 | blob = qla2x00_request_firmware(vha); |
5433383e | 5542 | if (!blob) { |
7c3df132 | 5543 | ql_log(ql_log_info, vha, 0x0083, |
94bcf830 | 5544 | "Firmware image unavailable.\n"); |
7c3df132 SK |
5545 | ql_log(ql_log_info, vha, 0x0084, |
5546 | "Firmware images can be retrieved from: "QLA_FW_URL ".\n"); | |
5433383e AV |
5547 | return QLA_FUNCTION_FAILED; |
5548 | } | |
5549 | ||
5550 | rval = QLA_SUCCESS; | |
5551 | ||
73208dfd | 5552 | wcode = (uint16_t *)req->ring; |
5433383e AV |
5553 | *srisc_addr = 0; |
5554 | fwcode = (uint16_t *)blob->fw->data; | |
5555 | fwclen = 0; | |
5556 | ||
5557 | /* Validate firmware image by checking version. */ | |
5558 | if (blob->fw->size < 8 * sizeof(uint16_t)) { | |
7c3df132 SK |
5559 | ql_log(ql_log_fatal, vha, 0x0085, |
5560 | "Unable to verify integrity of firmware image (%Zd).\n", | |
5433383e AV |
5561 | blob->fw->size); |
5562 | goto fail_fw_integrity; | |
5563 | } | |
5564 | for (i = 0; i < 4; i++) | |
5565 | wcode[i] = be16_to_cpu(fwcode[i + 4]); | |
5566 | if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff && | |
5567 | wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 && | |
5568 | wcode[2] == 0 && wcode[3] == 0)) { | |
7c3df132 SK |
5569 | ql_log(ql_log_fatal, vha, 0x0086, |
5570 | "Unable to verify integrity of firmware image.\n"); | |
5571 | ql_log(ql_log_fatal, vha, 0x0087, | |
5572 | "Firmware data: %04x %04x %04x %04x.\n", | |
5573 | wcode[0], wcode[1], wcode[2], wcode[3]); | |
5433383e AV |
5574 | goto fail_fw_integrity; |
5575 | } | |
5576 | ||
5577 | seg = blob->segs; | |
5578 | while (*seg && rval == QLA_SUCCESS) { | |
5579 | risc_addr = *seg; | |
5580 | *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr; | |
5581 | risc_size = be16_to_cpu(fwcode[3]); | |
5582 | ||
5583 | /* Validate firmware image size. */ | |
5584 | fwclen += risc_size * sizeof(uint16_t); | |
5585 | if (blob->fw->size < fwclen) { | |
7c3df132 | 5586 | ql_log(ql_log_fatal, vha, 0x0088, |
5433383e | 5587 | "Unable to verify integrity of firmware image " |
7c3df132 | 5588 | "(%Zd).\n", blob->fw->size); |
5433383e AV |
5589 | goto fail_fw_integrity; |
5590 | } | |
5591 | ||
5592 | fragment = 0; | |
5593 | while (risc_size > 0 && rval == QLA_SUCCESS) { | |
5594 | wlen = (uint16_t)(ha->fw_transfer_size >> 1); | |
5595 | if (wlen > risc_size) | |
5596 | wlen = risc_size; | |
7c3df132 SK |
5597 | ql_dbg(ql_dbg_init, vha, 0x0089, |
5598 | "Loading risc segment@ risc addr %x number of " | |
5599 | "words 0x%x.\n", risc_addr, wlen); | |
5433383e AV |
5600 | |
5601 | for (i = 0; i < wlen; i++) | |
5602 | wcode[i] = swab16(fwcode[i]); | |
5603 | ||
73208dfd | 5604 | rval = qla2x00_load_ram(vha, req->dma, risc_addr, |
5433383e AV |
5605 | wlen); |
5606 | if (rval) { | |
7c3df132 SK |
5607 | ql_log(ql_log_fatal, vha, 0x008a, |
5608 | "Failed to load segment %d of firmware.\n", | |
5609 | fragment); | |
5433383e AV |
5610 | break; |
5611 | } | |
5612 | ||
5613 | fwcode += wlen; | |
5614 | risc_addr += wlen; | |
5615 | risc_size -= wlen; | |
5616 | fragment++; | |
5617 | } | |
5618 | ||
5619 | /* Next segment. */ | |
5620 | seg++; | |
5621 | } | |
5622 | return rval; | |
5623 | ||
5624 | fail_fw_integrity: | |
5625 | return QLA_FUNCTION_FAILED; | |
5626 | } | |
5627 | ||
eaac30be AV |
5628 | static int |
5629 | qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr) | |
0107109e AV |
5630 | { |
5631 | int rval; | |
5632 | int segments, fragment; | |
5633 | uint32_t *dcode, dlen; | |
5634 | uint32_t risc_addr; | |
5635 | uint32_t risc_size; | |
5636 | uint32_t i; | |
5433383e | 5637 | struct fw_blob *blob; |
f73cb695 CD |
5638 | const uint32_t *fwcode; |
5639 | uint32_t fwclen; | |
e315cd28 | 5640 | struct qla_hw_data *ha = vha->hw; |
73208dfd | 5641 | struct req_que *req = ha->req_q_map[0]; |
0107109e | 5642 | |
5433383e | 5643 | /* Load firmware blob. */ |
e315cd28 | 5644 | blob = qla2x00_request_firmware(vha); |
5433383e | 5645 | if (!blob) { |
7c3df132 | 5646 | ql_log(ql_log_warn, vha, 0x0090, |
94bcf830 | 5647 | "Firmware image unavailable.\n"); |
7c3df132 SK |
5648 | ql_log(ql_log_warn, vha, 0x0091, |
5649 | "Firmware images can be retrieved from: " | |
5650 | QLA_FW_URL ".\n"); | |
d1c61909 | 5651 | |
eaac30be | 5652 | return QLA_FUNCTION_FAILED; |
0107109e AV |
5653 | } |
5654 | ||
cfb0919c CD |
5655 | ql_dbg(ql_dbg_init, vha, 0x0092, |
5656 | "FW: Loading via request-firmware.\n"); | |
eaac30be | 5657 | |
0107109e AV |
5658 | rval = QLA_SUCCESS; |
5659 | ||
5660 | segments = FA_RISC_CODE_SEGMENTS; | |
73208dfd | 5661 | dcode = (uint32_t *)req->ring; |
0107109e | 5662 | *srisc_addr = 0; |
5433383e | 5663 | fwcode = (uint32_t *)blob->fw->data; |
0107109e AV |
5664 | fwclen = 0; |
5665 | ||
5666 | /* Validate firmware image by checking version. */ | |
5433383e | 5667 | if (blob->fw->size < 8 * sizeof(uint32_t)) { |
7c3df132 SK |
5668 | ql_log(ql_log_fatal, vha, 0x0093, |
5669 | "Unable to verify integrity of firmware image (%Zd).\n", | |
5433383e | 5670 | blob->fw->size); |
f73cb695 | 5671 | return QLA_FUNCTION_FAILED; |
0107109e AV |
5672 | } |
5673 | for (i = 0; i < 4; i++) | |
5674 | dcode[i] = be32_to_cpu(fwcode[i + 4]); | |
5675 | if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff && | |
5676 | dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) || | |
5677 | (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 && | |
5678 | dcode[3] == 0)) { | |
7c3df132 SK |
5679 | ql_log(ql_log_fatal, vha, 0x0094, |
5680 | "Unable to verify integrity of firmware image (%Zd).\n", | |
5681 | blob->fw->size); | |
5682 | ql_log(ql_log_fatal, vha, 0x0095, | |
5683 | "Firmware data: %08x %08x %08x %08x.\n", | |
5684 | dcode[0], dcode[1], dcode[2], dcode[3]); | |
f73cb695 | 5685 | return QLA_FUNCTION_FAILED; |
0107109e AV |
5686 | } |
5687 | ||
5688 | while (segments && rval == QLA_SUCCESS) { | |
5689 | risc_addr = be32_to_cpu(fwcode[2]); | |
5690 | *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr; | |
5691 | risc_size = be32_to_cpu(fwcode[3]); | |
5692 | ||
5693 | /* Validate firmware image size. */ | |
5694 | fwclen += risc_size * sizeof(uint32_t); | |
5433383e | 5695 | if (blob->fw->size < fwclen) { |
7c3df132 | 5696 | ql_log(ql_log_fatal, vha, 0x0096, |
5433383e | 5697 | "Unable to verify integrity of firmware image " |
7c3df132 | 5698 | "(%Zd).\n", blob->fw->size); |
f73cb695 | 5699 | return QLA_FUNCTION_FAILED; |
0107109e AV |
5700 | } |
5701 | ||
5702 | fragment = 0; | |
5703 | while (risc_size > 0 && rval == QLA_SUCCESS) { | |
5704 | dlen = (uint32_t)(ha->fw_transfer_size >> 2); | |
5705 | if (dlen > risc_size) | |
5706 | dlen = risc_size; | |
5707 | ||
7c3df132 SK |
5708 | ql_dbg(ql_dbg_init, vha, 0x0097, |
5709 | "Loading risc segment@ risc addr %x " | |
5710 | "number of dwords 0x%x.\n", risc_addr, dlen); | |
0107109e AV |
5711 | |
5712 | for (i = 0; i < dlen; i++) | |
5713 | dcode[i] = swab32(fwcode[i]); | |
5714 | ||
73208dfd | 5715 | rval = qla2x00_load_ram(vha, req->dma, risc_addr, |
590f98e5 | 5716 | dlen); |
0107109e | 5717 | if (rval) { |
7c3df132 SK |
5718 | ql_log(ql_log_fatal, vha, 0x0098, |
5719 | "Failed to load segment %d of firmware.\n", | |
5720 | fragment); | |
f261f7af | 5721 | return QLA_FUNCTION_FAILED; |
0107109e AV |
5722 | } |
5723 | ||
5724 | fwcode += dlen; | |
5725 | risc_addr += dlen; | |
5726 | risc_size -= dlen; | |
5727 | fragment++; | |
5728 | } | |
5729 | ||
5730 | /* Next segment. */ | |
5731 | segments--; | |
5732 | } | |
f73cb695 CD |
5733 | |
5734 | if (!IS_QLA27XX(ha)) | |
5735 | return rval; | |
5736 | ||
5737 | if (ha->fw_dump_template) | |
5738 | vfree(ha->fw_dump_template); | |
5739 | ha->fw_dump_template = NULL; | |
5740 | ha->fw_dump_template_len = 0; | |
5741 | ||
5742 | ql_dbg(ql_dbg_init, vha, 0x171, | |
97ea702b CD |
5743 | "Loading fwdump template from %x\n", |
5744 | (uint32_t)((void *)fwcode - (void *)blob->fw->data)); | |
f73cb695 CD |
5745 | risc_size = be32_to_cpu(fwcode[2]); |
5746 | ql_dbg(ql_dbg_init, vha, 0x172, | |
5747 | "-> array size %x dwords\n", risc_size); | |
5748 | if (risc_size == 0 || risc_size == ~0) | |
5749 | goto default_template; | |
5750 | ||
5751 | dlen = (risc_size - 8) * sizeof(*fwcode); | |
5752 | ql_dbg(ql_dbg_init, vha, 0x0173, | |
5753 | "-> template allocating %x bytes...\n", dlen); | |
5754 | ha->fw_dump_template = vmalloc(dlen); | |
5755 | if (!ha->fw_dump_template) { | |
5756 | ql_log(ql_log_warn, vha, 0x0174, | |
5757 | "Failed fwdump template allocate %x bytes.\n", risc_size); | |
5758 | goto default_template; | |
5759 | } | |
5760 | ||
5761 | fwcode += 7; | |
5762 | risc_size -= 8; | |
5763 | dcode = ha->fw_dump_template; | |
5764 | for (i = 0; i < risc_size; i++) | |
5765 | dcode[i] = le32_to_cpu(fwcode[i]); | |
5766 | ||
5767 | if (!qla27xx_fwdt_template_valid(dcode)) { | |
5768 | ql_log(ql_log_warn, vha, 0x0175, | |
5769 | "Failed fwdump template validate\n"); | |
5770 | goto default_template; | |
5771 | } | |
5772 | ||
5773 | dlen = qla27xx_fwdt_template_size(dcode); | |
5774 | ql_dbg(ql_dbg_init, vha, 0x0176, | |
5775 | "-> template size %x bytes\n", dlen); | |
5776 | if (dlen > risc_size * sizeof(*fwcode)) { | |
5777 | ql_log(ql_log_warn, vha, 0x0177, | |
97ea702b CD |
5778 | "Failed fwdump template exceeds array by %x bytes\n", |
5779 | (uint32_t)(dlen - risc_size * sizeof(*fwcode))); | |
f73cb695 CD |
5780 | goto default_template; |
5781 | } | |
5782 | ha->fw_dump_template_len = dlen; | |
0107109e AV |
5783 | return rval; |
5784 | ||
f73cb695 CD |
5785 | default_template: |
5786 | ql_log(ql_log_warn, vha, 0x0178, "Using default fwdump template\n"); | |
5787 | if (ha->fw_dump_template) | |
5788 | vfree(ha->fw_dump_template); | |
5789 | ha->fw_dump_template = NULL; | |
5790 | ha->fw_dump_template_len = 0; | |
5791 | ||
5792 | dlen = qla27xx_fwdt_template_default_size(); | |
5793 | ql_dbg(ql_dbg_init, vha, 0x0179, | |
5794 | "-> template allocating %x bytes...\n", dlen); | |
5795 | ha->fw_dump_template = vmalloc(dlen); | |
5796 | if (!ha->fw_dump_template) { | |
5797 | ql_log(ql_log_warn, vha, 0x017a, | |
5798 | "Failed fwdump template allocate %x bytes.\n", risc_size); | |
5799 | goto failed_template; | |
5800 | } | |
5801 | ||
5802 | dcode = ha->fw_dump_template; | |
5803 | risc_size = dlen / sizeof(*fwcode); | |
5804 | fwcode = qla27xx_fwdt_template_default(); | |
5805 | for (i = 0; i < risc_size; i++) | |
5806 | dcode[i] = be32_to_cpu(fwcode[i]); | |
5807 | ||
5808 | if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) { | |
5809 | ql_log(ql_log_warn, vha, 0x017b, | |
5810 | "Failed fwdump template validate\n"); | |
5811 | goto failed_template; | |
5812 | } | |
5813 | ||
5814 | dlen = qla27xx_fwdt_template_size(ha->fw_dump_template); | |
5815 | ql_dbg(ql_dbg_init, vha, 0x017c, | |
5816 | "-> template size %x bytes\n", dlen); | |
5817 | ha->fw_dump_template_len = dlen; | |
5818 | return rval; | |
5819 | ||
5820 | failed_template: | |
5821 | ql_log(ql_log_warn, vha, 0x017d, "Failed default fwdump template\n"); | |
5822 | if (ha->fw_dump_template) | |
5823 | vfree(ha->fw_dump_template); | |
5824 | ha->fw_dump_template = NULL; | |
5825 | ha->fw_dump_template_len = 0; | |
5826 | return rval; | |
0107109e | 5827 | } |
18c6c127 | 5828 | |
eaac30be AV |
5829 | int |
5830 | qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) | |
5831 | { | |
5832 | int rval; | |
5833 | ||
e337d907 AV |
5834 | if (ql2xfwloadbin == 1) |
5835 | return qla81xx_load_risc(vha, srisc_addr); | |
5836 | ||
eaac30be AV |
5837 | /* |
5838 | * FW Load priority: | |
5839 | * 1) Firmware via request-firmware interface (.bin file). | |
5840 | * 2) Firmware residing in flash. | |
5841 | */ | |
5842 | rval = qla24xx_load_risc_blob(vha, srisc_addr); | |
5843 | if (rval == QLA_SUCCESS) | |
5844 | return rval; | |
5845 | ||
cbc8eb67 AV |
5846 | return qla24xx_load_risc_flash(vha, srisc_addr, |
5847 | vha->hw->flt_region_fw); | |
eaac30be AV |
5848 | } |
5849 | ||
5850 | int | |
5851 | qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) | |
5852 | { | |
5853 | int rval; | |
cbc8eb67 | 5854 | struct qla_hw_data *ha = vha->hw; |
eaac30be | 5855 | |
e337d907 | 5856 | if (ql2xfwloadbin == 2) |
cbc8eb67 | 5857 | goto try_blob_fw; |
e337d907 | 5858 | |
eaac30be AV |
5859 | /* |
5860 | * FW Load priority: | |
5861 | * 1) Firmware residing in flash. | |
5862 | * 2) Firmware via request-firmware interface (.bin file). | |
cbc8eb67 | 5863 | * 3) Golden-Firmware residing in flash -- limited operation. |
eaac30be | 5864 | */ |
cbc8eb67 | 5865 | rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw); |
eaac30be AV |
5866 | if (rval == QLA_SUCCESS) |
5867 | return rval; | |
5868 | ||
cbc8eb67 AV |
5869 | try_blob_fw: |
5870 | rval = qla24xx_load_risc_blob(vha, srisc_addr); | |
5871 | if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw) | |
5872 | return rval; | |
5873 | ||
7c3df132 SK |
5874 | ql_log(ql_log_info, vha, 0x0099, |
5875 | "Attempting to fallback to golden firmware.\n"); | |
cbc8eb67 AV |
5876 | rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw); |
5877 | if (rval != QLA_SUCCESS) | |
5878 | return rval; | |
5879 | ||
7c3df132 | 5880 | ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n"); |
cbc8eb67 | 5881 | ha->flags.running_gold_fw = 1; |
cbc8eb67 | 5882 | return rval; |
eaac30be AV |
5883 | } |
5884 | ||
18c6c127 | 5885 | void |
e315cd28 | 5886 | qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha) |
18c6c127 AV |
5887 | { |
5888 | int ret, retries; | |
e315cd28 | 5889 | struct qla_hw_data *ha = vha->hw; |
18c6c127 | 5890 | |
85880801 AV |
5891 | if (ha->flags.pci_channel_io_perm_failure) |
5892 | return; | |
e428924c | 5893 | if (!IS_FWI2_CAPABLE(ha)) |
18c6c127 | 5894 | return; |
75edf81d AV |
5895 | if (!ha->fw_major_version) |
5896 | return; | |
18c6c127 | 5897 | |
e315cd28 | 5898 | ret = qla2x00_stop_firmware(vha); |
7c7f1f29 | 5899 | for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT && |
b469a7cb | 5900 | ret != QLA_INVALID_COMMAND && retries ; retries--) { |
e315cd28 AC |
5901 | ha->isp_ops->reset_chip(vha); |
5902 | if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS) | |
18c6c127 | 5903 | continue; |
e315cd28 | 5904 | if (qla2x00_setup_chip(vha) != QLA_SUCCESS) |
18c6c127 | 5905 | continue; |
7c3df132 SK |
5906 | ql_log(ql_log_info, vha, 0x8015, |
5907 | "Attempting retry of stop-firmware command.\n"); | |
e315cd28 | 5908 | ret = qla2x00_stop_firmware(vha); |
18c6c127 AV |
5909 | } |
5910 | } | |
2c3dfe3f SJ |
5911 | |
5912 | int | |
e315cd28 | 5913 | qla24xx_configure_vhba(scsi_qla_host_t *vha) |
2c3dfe3f SJ |
5914 | { |
5915 | int rval = QLA_SUCCESS; | |
0b91d116 | 5916 | int rval2; |
2c3dfe3f | 5917 | uint16_t mb[MAILBOX_REGISTER_COUNT]; |
e315cd28 AC |
5918 | struct qla_hw_data *ha = vha->hw; |
5919 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); | |
67c2e93a AC |
5920 | struct req_que *req; |
5921 | struct rsp_que *rsp; | |
2c3dfe3f | 5922 | |
e315cd28 | 5923 | if (!vha->vp_idx) |
2c3dfe3f SJ |
5924 | return -EINVAL; |
5925 | ||
e315cd28 | 5926 | rval = qla2x00_fw_ready(base_vha); |
7163ea81 | 5927 | if (ha->flags.cpu_affinity_enabled) |
67c2e93a AC |
5928 | req = ha->req_q_map[0]; |
5929 | else | |
5930 | req = vha->req; | |
5931 | rsp = req->rsp; | |
5932 | ||
2c3dfe3f | 5933 | if (rval == QLA_SUCCESS) { |
e315cd28 | 5934 | clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); |
73208dfd | 5935 | qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL); |
2c3dfe3f SJ |
5936 | } |
5937 | ||
e315cd28 | 5938 | vha->flags.management_server_logged_in = 0; |
2c3dfe3f SJ |
5939 | |
5940 | /* Login to SNS first */ | |
0b91d116 CD |
5941 | rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb, |
5942 | BIT_1); | |
5943 | if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) { | |
5944 | if (rval2 == QLA_MEMORY_ALLOC_FAILED) | |
5945 | ql_dbg(ql_dbg_init, vha, 0x0120, | |
5946 | "Failed SNS login: loop_id=%x, rval2=%d\n", | |
5947 | NPH_SNS, rval2); | |
5948 | else | |
5949 | ql_dbg(ql_dbg_init, vha, 0x0103, | |
5950 | "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x " | |
5951 | "mb[2]=%x mb[6]=%x mb[7]=%x.\n", | |
5952 | NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]); | |
2c3dfe3f SJ |
5953 | return (QLA_FUNCTION_FAILED); |
5954 | } | |
5955 | ||
e315cd28 AC |
5956 | atomic_set(&vha->loop_down_timer, 0); |
5957 | atomic_set(&vha->loop_state, LOOP_UP); | |
5958 | set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); | |
5959 | set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); | |
5960 | rval = qla2x00_loop_resync(base_vha); | |
2c3dfe3f SJ |
5961 | |
5962 | return rval; | |
5963 | } | |
4d4df193 HK |
5964 | |
5965 | /* 84XX Support **************************************************************/ | |
5966 | ||
5967 | static LIST_HEAD(qla_cs84xx_list); | |
5968 | static DEFINE_MUTEX(qla_cs84xx_mutex); | |
5969 | ||
5970 | static struct qla_chip_state_84xx * | |
e315cd28 | 5971 | qla84xx_get_chip(struct scsi_qla_host *vha) |
4d4df193 HK |
5972 | { |
5973 | struct qla_chip_state_84xx *cs84xx; | |
e315cd28 | 5974 | struct qla_hw_data *ha = vha->hw; |
4d4df193 HK |
5975 | |
5976 | mutex_lock(&qla_cs84xx_mutex); | |
5977 | ||
5978 | /* Find any shared 84xx chip. */ | |
5979 | list_for_each_entry(cs84xx, &qla_cs84xx_list, list) { | |
5980 | if (cs84xx->bus == ha->pdev->bus) { | |
5981 | kref_get(&cs84xx->kref); | |
5982 | goto done; | |
5983 | } | |
5984 | } | |
5985 | ||
5986 | cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL); | |
5987 | if (!cs84xx) | |
5988 | goto done; | |
5989 | ||
5990 | kref_init(&cs84xx->kref); | |
5991 | spin_lock_init(&cs84xx->access_lock); | |
5992 | mutex_init(&cs84xx->fw_update_mutex); | |
5993 | cs84xx->bus = ha->pdev->bus; | |
5994 | ||
5995 | list_add_tail(&cs84xx->list, &qla_cs84xx_list); | |
5996 | done: | |
5997 | mutex_unlock(&qla_cs84xx_mutex); | |
5998 | return cs84xx; | |
5999 | } | |
6000 | ||
6001 | static void | |
6002 | __qla84xx_chip_release(struct kref *kref) | |
6003 | { | |
6004 | struct qla_chip_state_84xx *cs84xx = | |
6005 | container_of(kref, struct qla_chip_state_84xx, kref); | |
6006 | ||
6007 | mutex_lock(&qla_cs84xx_mutex); | |
6008 | list_del(&cs84xx->list); | |
6009 | mutex_unlock(&qla_cs84xx_mutex); | |
6010 | kfree(cs84xx); | |
6011 | } | |
6012 | ||
6013 | void | |
e315cd28 | 6014 | qla84xx_put_chip(struct scsi_qla_host *vha) |
4d4df193 | 6015 | { |
e315cd28 | 6016 | struct qla_hw_data *ha = vha->hw; |
4d4df193 HK |
6017 | if (ha->cs84xx) |
6018 | kref_put(&ha->cs84xx->kref, __qla84xx_chip_release); | |
6019 | } | |
6020 | ||
6021 | static int | |
e315cd28 | 6022 | qla84xx_init_chip(scsi_qla_host_t *vha) |
4d4df193 HK |
6023 | { |
6024 | int rval; | |
6025 | uint16_t status[2]; | |
e315cd28 | 6026 | struct qla_hw_data *ha = vha->hw; |
4d4df193 HK |
6027 | |
6028 | mutex_lock(&ha->cs84xx->fw_update_mutex); | |
6029 | ||
e315cd28 | 6030 | rval = qla84xx_verify_chip(vha, status); |
4d4df193 HK |
6031 | |
6032 | mutex_unlock(&ha->cs84xx->fw_update_mutex); | |
6033 | ||
6034 | return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED: | |
6035 | QLA_SUCCESS; | |
6036 | } | |
3a03eb79 AV |
6037 | |
6038 | /* 81XX Support **************************************************************/ | |
6039 | ||
6040 | int | |
6041 | qla81xx_nvram_config(scsi_qla_host_t *vha) | |
6042 | { | |
6043 | int rval; | |
6044 | struct init_cb_81xx *icb; | |
6045 | struct nvram_81xx *nv; | |
6046 | uint32_t *dptr; | |
6047 | uint8_t *dptr1, *dptr2; | |
6048 | uint32_t chksum; | |
6049 | uint16_t cnt; | |
6050 | struct qla_hw_data *ha = vha->hw; | |
6051 | ||
6052 | rval = QLA_SUCCESS; | |
6053 | icb = (struct init_cb_81xx *)ha->init_cb; | |
6054 | nv = ha->nvram; | |
6055 | ||
6056 | /* Determine NVRAM starting address. */ | |
6057 | ha->nvram_size = sizeof(struct nvram_81xx); | |
3a03eb79 | 6058 | ha->vpd_size = FA_NVRAM_VPD_SIZE; |
7ec0effd AD |
6059 | if (IS_P3P_TYPE(ha) || IS_QLA8031(ha)) |
6060 | ha->vpd_size = FA_VPD_SIZE_82XX; | |
3a03eb79 AV |
6061 | |
6062 | /* Get VPD data into cache */ | |
6063 | ha->vpd = ha->nvram + VPD_OFFSET; | |
3d79038f AV |
6064 | ha->isp_ops->read_optrom(vha, ha->vpd, ha->flt_region_vpd << 2, |
6065 | ha->vpd_size); | |
3a03eb79 AV |
6066 | |
6067 | /* Get NVRAM data into cache and calculate checksum. */ | |
3d79038f | 6068 | ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2, |
3a03eb79 | 6069 | ha->nvram_size); |
3d79038f | 6070 | dptr = (uint32_t *)nv; |
3a03eb79 AV |
6071 | for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++) |
6072 | chksum += le32_to_cpu(*dptr++); | |
6073 | ||
7c3df132 SK |
6074 | ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111, |
6075 | "Contents of NVRAM:\n"); | |
6076 | ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112, | |
6077 | (uint8_t *)nv, ha->nvram_size); | |
3a03eb79 AV |
6078 | |
6079 | /* Bad NVRAM data, set defaults parameters. */ | |
6080 | if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P' | |
6081 | || nv->id[3] != ' ' || | |
ad950360 | 6082 | nv->nvram_version < cpu_to_le16(ICB_VERSION)) { |
3a03eb79 | 6083 | /* Reset NVRAM data. */ |
7c3df132 | 6084 | ql_log(ql_log_info, vha, 0x0073, |
9e336520 | 6085 | "Inconsistent NVRAM detected: checksum=0x%x id=%c " |
7c3df132 | 6086 | "version=0x%x.\n", chksum, nv->id[0], |
3a03eb79 | 6087 | le16_to_cpu(nv->nvram_version)); |
7c3df132 SK |
6088 | ql_log(ql_log_info, vha, 0x0074, |
6089 | "Falling back to functioning (yet invalid -- WWPN) " | |
6090 | "defaults.\n"); | |
3a03eb79 AV |
6091 | |
6092 | /* | |
6093 | * Set default initialization control block. | |
6094 | */ | |
6095 | memset(nv, 0, ha->nvram_size); | |
ad950360 BVA |
6096 | nv->nvram_version = cpu_to_le16(ICB_VERSION); |
6097 | nv->version = cpu_to_le16(ICB_VERSION); | |
98aee70d | 6098 | nv->frame_payload_size = 2048; |
ad950360 BVA |
6099 | nv->execution_throttle = cpu_to_le16(0xFFFF); |
6100 | nv->exchange_count = cpu_to_le16(0); | |
3a03eb79 | 6101 | nv->port_name[0] = 0x21; |
f73cb695 | 6102 | nv->port_name[1] = 0x00 + ha->port_no + 1; |
3a03eb79 AV |
6103 | nv->port_name[2] = 0x00; |
6104 | nv->port_name[3] = 0xe0; | |
6105 | nv->port_name[4] = 0x8b; | |
6106 | nv->port_name[5] = 0x1c; | |
6107 | nv->port_name[6] = 0x55; | |
6108 | nv->port_name[7] = 0x86; | |
6109 | nv->node_name[0] = 0x20; | |
6110 | nv->node_name[1] = 0x00; | |
6111 | nv->node_name[2] = 0x00; | |
6112 | nv->node_name[3] = 0xe0; | |
6113 | nv->node_name[4] = 0x8b; | |
6114 | nv->node_name[5] = 0x1c; | |
6115 | nv->node_name[6] = 0x55; | |
6116 | nv->node_name[7] = 0x86; | |
ad950360 BVA |
6117 | nv->login_retry_count = cpu_to_le16(8); |
6118 | nv->interrupt_delay_timer = cpu_to_le16(0); | |
6119 | nv->login_timeout = cpu_to_le16(0); | |
3a03eb79 | 6120 | nv->firmware_options_1 = |
ad950360 BVA |
6121 | cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1); |
6122 | nv->firmware_options_2 = cpu_to_le32(2 << 4); | |
6123 | nv->firmware_options_2 |= cpu_to_le32(BIT_12); | |
6124 | nv->firmware_options_3 = cpu_to_le32(2 << 13); | |
6125 | nv->host_p = cpu_to_le32(BIT_11|BIT_10); | |
6126 | nv->efi_parameters = cpu_to_le32(0); | |
3a03eb79 | 6127 | nv->reset_delay = 5; |
ad950360 BVA |
6128 | nv->max_luns_per_target = cpu_to_le16(128); |
6129 | nv->port_down_retry_count = cpu_to_le16(30); | |
6130 | nv->link_down_timeout = cpu_to_le16(180); | |
eeebcc92 | 6131 | nv->enode_mac[0] = 0x00; |
6246b8a1 GM |
6132 | nv->enode_mac[1] = 0xC0; |
6133 | nv->enode_mac[2] = 0xDD; | |
3a03eb79 AV |
6134 | nv->enode_mac[3] = 0x04; |
6135 | nv->enode_mac[4] = 0x05; | |
f73cb695 | 6136 | nv->enode_mac[5] = 0x06 + ha->port_no + 1; |
3a03eb79 AV |
6137 | |
6138 | rval = 1; | |
6139 | } | |
6140 | ||
9e522cd8 AE |
6141 | if (IS_T10_PI_CAPABLE(ha)) |
6142 | nv->frame_payload_size &= ~7; | |
6143 | ||
aa230bc5 AE |
6144 | qlt_81xx_config_nvram_stage1(vha, nv); |
6145 | ||
3a03eb79 | 6146 | /* Reset Initialization control block */ |
773120e4 | 6147 | memset(icb, 0, ha->init_cb_size); |
3a03eb79 AV |
6148 | |
6149 | /* Copy 1st segment. */ | |
6150 | dptr1 = (uint8_t *)icb; | |
6151 | dptr2 = (uint8_t *)&nv->version; | |
6152 | cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version; | |
6153 | while (cnt--) | |
6154 | *dptr1++ = *dptr2++; | |
6155 | ||
6156 | icb->login_retry_count = nv->login_retry_count; | |
6157 | ||
6158 | /* Copy 2nd segment. */ | |
6159 | dptr1 = (uint8_t *)&icb->interrupt_delay_timer; | |
6160 | dptr2 = (uint8_t *)&nv->interrupt_delay_timer; | |
6161 | cnt = (uint8_t *)&icb->reserved_5 - | |
6162 | (uint8_t *)&icb->interrupt_delay_timer; | |
6163 | while (cnt--) | |
6164 | *dptr1++ = *dptr2++; | |
6165 | ||
6166 | memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac)); | |
6167 | /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */ | |
6168 | if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) { | |
69e5f1ea AV |
6169 | icb->enode_mac[0] = 0x00; |
6170 | icb->enode_mac[1] = 0xC0; | |
6171 | icb->enode_mac[2] = 0xDD; | |
3a03eb79 AV |
6172 | icb->enode_mac[3] = 0x04; |
6173 | icb->enode_mac[4] = 0x05; | |
f73cb695 | 6174 | icb->enode_mac[5] = 0x06 + ha->port_no + 1; |
3a03eb79 AV |
6175 | } |
6176 | ||
b64b0e8f AV |
6177 | /* Use extended-initialization control block. */ |
6178 | memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb)); | |
6179 | ||
3a03eb79 AV |
6180 | /* |
6181 | * Setup driver NVRAM options. | |
6182 | */ | |
6183 | qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name), | |
a9083016 | 6184 | "QLE8XXX"); |
3a03eb79 | 6185 | |
aa230bc5 AE |
6186 | qlt_81xx_config_nvram_stage2(vha, icb); |
6187 | ||
3a03eb79 | 6188 | /* Use alternate WWN? */ |
ad950360 | 6189 | if (nv->host_p & cpu_to_le32(BIT_15)) { |
3a03eb79 AV |
6190 | memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE); |
6191 | memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE); | |
6192 | } | |
6193 | ||
6194 | /* Prepare nodename */ | |
ad950360 | 6195 | if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) { |
3a03eb79 AV |
6196 | /* |
6197 | * Firmware will apply the following mask if the nodename was | |
6198 | * not provided. | |
6199 | */ | |
6200 | memcpy(icb->node_name, icb->port_name, WWN_SIZE); | |
6201 | icb->node_name[0] &= 0xF0; | |
6202 | } | |
6203 | ||
6204 | /* Set host adapter parameters. */ | |
6205 | ha->flags.disable_risc_code_load = 0; | |
6206 | ha->flags.enable_lip_reset = 0; | |
6207 | ha->flags.enable_lip_full_login = | |
6208 | le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0; | |
6209 | ha->flags.enable_target_reset = | |
6210 | le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0; | |
6211 | ha->flags.enable_led_scheme = 0; | |
6212 | ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0; | |
6213 | ||
6214 | ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) & | |
6215 | (BIT_6 | BIT_5 | BIT_4)) >> 4; | |
6216 | ||
6217 | /* save HBA serial number */ | |
6218 | ha->serial0 = icb->port_name[5]; | |
6219 | ha->serial1 = icb->port_name[6]; | |
6220 | ha->serial2 = icb->port_name[7]; | |
6221 | memcpy(vha->node_name, icb->node_name, WWN_SIZE); | |
6222 | memcpy(vha->port_name, icb->port_name, WWN_SIZE); | |
6223 | ||
ad950360 | 6224 | icb->execution_throttle = cpu_to_le16(0xFFFF); |
3a03eb79 AV |
6225 | |
6226 | ha->retry_count = le16_to_cpu(nv->login_retry_count); | |
6227 | ||
6228 | /* Set minimum login_timeout to 4 seconds. */ | |
6229 | if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout) | |
6230 | nv->login_timeout = cpu_to_le16(ql2xlogintimeout); | |
6231 | if (le16_to_cpu(nv->login_timeout) < 4) | |
ad950360 | 6232 | nv->login_timeout = cpu_to_le16(4); |
3a03eb79 AV |
6233 | ha->login_timeout = le16_to_cpu(nv->login_timeout); |
6234 | icb->login_timeout = nv->login_timeout; | |
6235 | ||
6236 | /* Set minimum RATOV to 100 tenths of a second. */ | |
6237 | ha->r_a_tov = 100; | |
6238 | ||
6239 | ha->loop_reset_delay = nv->reset_delay; | |
6240 | ||
6241 | /* Link Down Timeout = 0: | |
6242 | * | |
7ec0effd | 6243 | * When Port Down timer expires we will start returning |
3a03eb79 AV |
6244 | * I/O's to OS with "DID_NO_CONNECT". |
6245 | * | |
6246 | * Link Down Timeout != 0: | |
6247 | * | |
6248 | * The driver waits for the link to come up after link down | |
6249 | * before returning I/Os to OS with "DID_NO_CONNECT". | |
6250 | */ | |
6251 | if (le16_to_cpu(nv->link_down_timeout) == 0) { | |
6252 | ha->loop_down_abort_time = | |
6253 | (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT); | |
6254 | } else { | |
6255 | ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout); | |
6256 | ha->loop_down_abort_time = | |
6257 | (LOOP_DOWN_TIME - ha->link_down_timeout); | |
6258 | } | |
6259 | ||
6260 | /* Need enough time to try and get the port back. */ | |
6261 | ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count); | |
6262 | if (qlport_down_retry) | |
6263 | ha->port_down_retry_count = qlport_down_retry; | |
6264 | ||
6265 | /* Set login_retry_count */ | |
6266 | ha->login_retry_count = le16_to_cpu(nv->login_retry_count); | |
6267 | if (ha->port_down_retry_count == | |
6268 | le16_to_cpu(nv->port_down_retry_count) && | |
6269 | ha->port_down_retry_count > 3) | |
6270 | ha->login_retry_count = ha->port_down_retry_count; | |
6271 | else if (ha->port_down_retry_count > (int)ha->login_retry_count) | |
6272 | ha->login_retry_count = ha->port_down_retry_count; | |
6273 | if (ql2xloginretrycount) | |
6274 | ha->login_retry_count = ql2xloginretrycount; | |
6275 | ||
6246b8a1 | 6276 | /* if not running MSI-X we need handshaking on interrupts */ |
f73cb695 | 6277 | if (!vha->hw->flags.msix_enabled && (IS_QLA83XX(ha) || IS_QLA27XX(ha))) |
ad950360 | 6278 | icb->firmware_options_2 |= cpu_to_le32(BIT_22); |
6246b8a1 | 6279 | |
3a03eb79 AV |
6280 | /* Enable ZIO. */ |
6281 | if (!vha->flags.init_done) { | |
6282 | ha->zio_mode = le32_to_cpu(icb->firmware_options_2) & | |
6283 | (BIT_3 | BIT_2 | BIT_1 | BIT_0); | |
6284 | ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ? | |
6285 | le16_to_cpu(icb->interrupt_delay_timer): 2; | |
6286 | } | |
ad950360 | 6287 | icb->firmware_options_2 &= cpu_to_le32( |
3a03eb79 AV |
6288 | ~(BIT_3 | BIT_2 | BIT_1 | BIT_0)); |
6289 | vha->flags.process_response_queue = 0; | |
6290 | if (ha->zio_mode != QLA_ZIO_DISABLED) { | |
6291 | ha->zio_mode = QLA_ZIO_MODE_6; | |
6292 | ||
7c3df132 | 6293 | ql_log(ql_log_info, vha, 0x0075, |
3a03eb79 | 6294 | "ZIO mode %d enabled; timer delay (%d us).\n", |
7c3df132 SK |
6295 | ha->zio_mode, |
6296 | ha->zio_timer * 100); | |
3a03eb79 AV |
6297 | |
6298 | icb->firmware_options_2 |= cpu_to_le32( | |
6299 | (uint32_t)ha->zio_mode); | |
6300 | icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer); | |
6301 | vha->flags.process_response_queue = 1; | |
6302 | } | |
6303 | ||
6304 | if (rval) { | |
7c3df132 SK |
6305 | ql_log(ql_log_warn, vha, 0x0076, |
6306 | "NVRAM configuration failed.\n"); | |
3a03eb79 AV |
6307 | } |
6308 | return (rval); | |
6309 | } | |
6310 | ||
a9083016 GM |
6311 | int |
6312 | qla82xx_restart_isp(scsi_qla_host_t *vha) | |
6313 | { | |
6314 | int status, rval; | |
a9083016 GM |
6315 | struct qla_hw_data *ha = vha->hw; |
6316 | struct req_que *req = ha->req_q_map[0]; | |
6317 | struct rsp_que *rsp = ha->rsp_q_map[0]; | |
6318 | struct scsi_qla_host *vp; | |
feafb7b1 | 6319 | unsigned long flags; |
a9083016 GM |
6320 | |
6321 | status = qla2x00_init_rings(vha); | |
6322 | if (!status) { | |
6323 | clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); | |
6324 | ha->flags.chip_reset_done = 1; | |
6325 | ||
6326 | status = qla2x00_fw_ready(vha); | |
6327 | if (!status) { | |
a9083016 GM |
6328 | /* Issue a marker after FW becomes ready. */ |
6329 | qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL); | |
a9083016 | 6330 | vha->flags.online = 1; |
7108b76e | 6331 | set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); |
a9083016 GM |
6332 | } |
6333 | ||
6334 | /* if no cable then assume it's good */ | |
6335 | if ((vha->device_flags & DFLG_NO_CABLE)) | |
6336 | status = 0; | |
a9083016 GM |
6337 | } |
6338 | ||
6339 | if (!status) { | |
6340 | clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); | |
6341 | ||
6342 | if (!atomic_read(&vha->loop_down_timer)) { | |
6343 | /* | |
6344 | * Issue marker command only when we are going | |
6345 | * to start the I/O . | |
6346 | */ | |
6347 | vha->marker_needed = 1; | |
6348 | } | |
6349 | ||
a9083016 GM |
6350 | ha->isp_ops->enable_intrs(ha); |
6351 | ||
6352 | ha->isp_abort_cnt = 0; | |
6353 | clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); | |
6354 | ||
53296788 | 6355 | /* Update the firmware version */ |
3173167f | 6356 | status = qla82xx_check_md_needed(vha); |
53296788 | 6357 | |
a9083016 GM |
6358 | if (ha->fce) { |
6359 | ha->flags.fce_enabled = 1; | |
6360 | memset(ha->fce, 0, | |
6361 | fce_calc_size(ha->fce_bufs)); | |
6362 | rval = qla2x00_enable_fce_trace(vha, | |
6363 | ha->fce_dma, ha->fce_bufs, ha->fce_mb, | |
6364 | &ha->fce_bufs); | |
6365 | if (rval) { | |
cfb0919c | 6366 | ql_log(ql_log_warn, vha, 0x8001, |
7c3df132 SK |
6367 | "Unable to reinitialize FCE (%d).\n", |
6368 | rval); | |
a9083016 GM |
6369 | ha->flags.fce_enabled = 0; |
6370 | } | |
6371 | } | |
6372 | ||
6373 | if (ha->eft) { | |
6374 | memset(ha->eft, 0, EFT_SIZE); | |
6375 | rval = qla2x00_enable_eft_trace(vha, | |
6376 | ha->eft_dma, EFT_NUM_BUFFERS); | |
6377 | if (rval) { | |
cfb0919c | 6378 | ql_log(ql_log_warn, vha, 0x8010, |
7c3df132 SK |
6379 | "Unable to reinitialize EFT (%d).\n", |
6380 | rval); | |
a9083016 GM |
6381 | } |
6382 | } | |
a9083016 GM |
6383 | } |
6384 | ||
6385 | if (!status) { | |
cfb0919c | 6386 | ql_dbg(ql_dbg_taskm, vha, 0x8011, |
7c3df132 | 6387 | "qla82xx_restart_isp succeeded.\n"); |
feafb7b1 AE |
6388 | |
6389 | spin_lock_irqsave(&ha->vport_slock, flags); | |
6390 | list_for_each_entry(vp, &ha->vp_list, list) { | |
6391 | if (vp->vp_idx) { | |
6392 | atomic_inc(&vp->vref_count); | |
6393 | spin_unlock_irqrestore(&ha->vport_slock, flags); | |
6394 | ||
a9083016 | 6395 | qla2x00_vp_abort_isp(vp); |
feafb7b1 AE |
6396 | |
6397 | spin_lock_irqsave(&ha->vport_slock, flags); | |
6398 | atomic_dec(&vp->vref_count); | |
6399 | } | |
a9083016 | 6400 | } |
feafb7b1 AE |
6401 | spin_unlock_irqrestore(&ha->vport_slock, flags); |
6402 | ||
a9083016 | 6403 | } else { |
cfb0919c | 6404 | ql_log(ql_log_warn, vha, 0x8016, |
7c3df132 | 6405 | "qla82xx_restart_isp **** FAILED ****.\n"); |
a9083016 GM |
6406 | } |
6407 | ||
6408 | return status; | |
6409 | } | |
6410 | ||
3a03eb79 | 6411 | void |
ae97c91e | 6412 | qla81xx_update_fw_options(scsi_qla_host_t *vha) |
3a03eb79 | 6413 | { |
ae97c91e AV |
6414 | struct qla_hw_data *ha = vha->hw; |
6415 | ||
6416 | if (!ql2xetsenable) | |
6417 | return; | |
6418 | ||
6419 | /* Enable ETS Burst. */ | |
6420 | memset(ha->fw_options, 0, sizeof(ha->fw_options)); | |
6421 | ha->fw_options[2] |= BIT_9; | |
6422 | qla2x00_set_fw_options(vha, ha->fw_options); | |
3a03eb79 | 6423 | } |
09ff701a SR |
6424 | |
6425 | /* | |
6426 | * qla24xx_get_fcp_prio | |
6427 | * Gets the fcp cmd priority value for the logged in port. | |
6428 | * Looks for a match of the port descriptors within | |
6429 | * each of the fcp prio config entries. If a match is found, | |
6430 | * the tag (priority) value is returned. | |
6431 | * | |
6432 | * Input: | |
21090cbe | 6433 | * vha = scsi host structure pointer. |
09ff701a SR |
6434 | * fcport = port structure pointer. |
6435 | * | |
6436 | * Return: | |
6c452a45 | 6437 | * non-zero (if found) |
f28a0a96 | 6438 | * -1 (if not found) |
09ff701a SR |
6439 | * |
6440 | * Context: | |
6441 | * Kernel context | |
6442 | */ | |
f28a0a96 | 6443 | static int |
09ff701a SR |
6444 | qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport) |
6445 | { | |
6446 | int i, entries; | |
6447 | uint8_t pid_match, wwn_match; | |
f28a0a96 | 6448 | int priority; |
09ff701a SR |
6449 | uint32_t pid1, pid2; |
6450 | uint64_t wwn1, wwn2; | |
6451 | struct qla_fcp_prio_entry *pri_entry; | |
6452 | struct qla_hw_data *ha = vha->hw; | |
6453 | ||
6454 | if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled) | |
f28a0a96 | 6455 | return -1; |
09ff701a | 6456 | |
f28a0a96 | 6457 | priority = -1; |
09ff701a SR |
6458 | entries = ha->fcp_prio_cfg->num_entries; |
6459 | pri_entry = &ha->fcp_prio_cfg->entry[0]; | |
6460 | ||
6461 | for (i = 0; i < entries; i++) { | |
6462 | pid_match = wwn_match = 0; | |
6463 | ||
6464 | if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) { | |
6465 | pri_entry++; | |
6466 | continue; | |
6467 | } | |
6468 | ||
6469 | /* check source pid for a match */ | |
6470 | if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) { | |
6471 | pid1 = pri_entry->src_pid & INVALID_PORT_ID; | |
6472 | pid2 = vha->d_id.b24 & INVALID_PORT_ID; | |
6473 | if (pid1 == INVALID_PORT_ID) | |
6474 | pid_match++; | |
6475 | else if (pid1 == pid2) | |
6476 | pid_match++; | |
6477 | } | |
6478 | ||
6479 | /* check destination pid for a match */ | |
6480 | if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) { | |
6481 | pid1 = pri_entry->dst_pid & INVALID_PORT_ID; | |
6482 | pid2 = fcport->d_id.b24 & INVALID_PORT_ID; | |
6483 | if (pid1 == INVALID_PORT_ID) | |
6484 | pid_match++; | |
6485 | else if (pid1 == pid2) | |
6486 | pid_match++; | |
6487 | } | |
6488 | ||
6489 | /* check source WWN for a match */ | |
6490 | if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) { | |
6491 | wwn1 = wwn_to_u64(vha->port_name); | |
6492 | wwn2 = wwn_to_u64(pri_entry->src_wwpn); | |
6493 | if (wwn2 == (uint64_t)-1) | |
6494 | wwn_match++; | |
6495 | else if (wwn1 == wwn2) | |
6496 | wwn_match++; | |
6497 | } | |
6498 | ||
6499 | /* check destination WWN for a match */ | |
6500 | if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) { | |
6501 | wwn1 = wwn_to_u64(fcport->port_name); | |
6502 | wwn2 = wwn_to_u64(pri_entry->dst_wwpn); | |
6503 | if (wwn2 == (uint64_t)-1) | |
6504 | wwn_match++; | |
6505 | else if (wwn1 == wwn2) | |
6506 | wwn_match++; | |
6507 | } | |
6508 | ||
6509 | if (pid_match == 2 || wwn_match == 2) { | |
6510 | /* Found a matching entry */ | |
6511 | if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID) | |
6512 | priority = pri_entry->tag; | |
6513 | break; | |
6514 | } | |
6515 | ||
6516 | pri_entry++; | |
6517 | } | |
6518 | ||
6519 | return priority; | |
6520 | } | |
6521 | ||
6522 | /* | |
6523 | * qla24xx_update_fcport_fcp_prio | |
6524 | * Activates fcp priority for the logged in fc port | |
6525 | * | |
6526 | * Input: | |
21090cbe | 6527 | * vha = scsi host structure pointer. |
09ff701a SR |
6528 | * fcp = port structure pointer. |
6529 | * | |
6530 | * Return: | |
6531 | * QLA_SUCCESS or QLA_FUNCTION_FAILED | |
6532 | * | |
6533 | * Context: | |
6534 | * Kernel context. | |
6535 | */ | |
6536 | int | |
21090cbe | 6537 | qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport) |
09ff701a SR |
6538 | { |
6539 | int ret; | |
f28a0a96 | 6540 | int priority; |
09ff701a SR |
6541 | uint16_t mb[5]; |
6542 | ||
21090cbe MI |
6543 | if (fcport->port_type != FCT_TARGET || |
6544 | fcport->loop_id == FC_NO_LOOP_ID) | |
09ff701a SR |
6545 | return QLA_FUNCTION_FAILED; |
6546 | ||
21090cbe | 6547 | priority = qla24xx_get_fcp_prio(vha, fcport); |
f28a0a96 AV |
6548 | if (priority < 0) |
6549 | return QLA_FUNCTION_FAILED; | |
6550 | ||
7ec0effd | 6551 | if (IS_P3P_TYPE(vha->hw)) { |
a00f6296 SK |
6552 | fcport->fcp_prio = priority & 0xf; |
6553 | return QLA_SUCCESS; | |
6554 | } | |
6555 | ||
21090cbe | 6556 | ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb); |
cfb0919c CD |
6557 | if (ret == QLA_SUCCESS) { |
6558 | if (fcport->fcp_prio != priority) | |
6559 | ql_dbg(ql_dbg_user, vha, 0x709e, | |
6560 | "Updated FCP_CMND priority - value=%d loop_id=%d " | |
6561 | "port_id=%02x%02x%02x.\n", priority, | |
6562 | fcport->loop_id, fcport->d_id.b.domain, | |
6563 | fcport->d_id.b.area, fcport->d_id.b.al_pa); | |
a00f6296 | 6564 | fcport->fcp_prio = priority & 0xf; |
cfb0919c | 6565 | } else |
7c3df132 | 6566 | ql_dbg(ql_dbg_user, vha, 0x704f, |
cfb0919c CD |
6567 | "Unable to update FCP_CMND priority - ret=0x%x for " |
6568 | "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id, | |
6569 | fcport->d_id.b.domain, fcport->d_id.b.area, | |
6570 | fcport->d_id.b.al_pa); | |
09ff701a SR |
6571 | return ret; |
6572 | } | |
6573 | ||
6574 | /* | |
6575 | * qla24xx_update_all_fcp_prio | |
6576 | * Activates fcp priority for all the logged in ports | |
6577 | * | |
6578 | * Input: | |
6579 | * ha = adapter block pointer. | |
6580 | * | |
6581 | * Return: | |
6582 | * QLA_SUCCESS or QLA_FUNCTION_FAILED | |
6583 | * | |
6584 | * Context: | |
6585 | * Kernel context. | |
6586 | */ | |
6587 | int | |
6588 | qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha) | |
6589 | { | |
6590 | int ret; | |
6591 | fc_port_t *fcport; | |
6592 | ||
6593 | ret = QLA_FUNCTION_FAILED; | |
6594 | /* We need to set priority for all logged in ports */ | |
6595 | list_for_each_entry(fcport, &vha->vp_fcports, list) | |
6596 | ret = qla24xx_update_fcport_fcp_prio(vha, fcport); | |
6597 | ||
6598 | return ret; | |
6599 | } |