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Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
fa90c54f | 2 | * QLogic Fibre Channel HBA Driver |
1e63395c | 3 | * Copyright (c) 2003-2013 QLogic Corporation |
1da177e4 | 4 | * |
fa90c54f | 5 | * See LICENSE.qla2xxx for copyright and licensing details. |
1da177e4 LT |
6 | */ |
7 | #include "qla_def.h" | |
73208dfd | 8 | #include "qla_gbl.h" |
1da177e4 LT |
9 | |
10 | #include <linux/delay.h> | |
5a0e3ad6 | 11 | #include <linux/slab.h> |
0107109e | 12 | #include <linux/vmalloc.h> |
1da177e4 LT |
13 | |
14 | #include "qla_devtbl.h" | |
15 | ||
4e08df3f DM |
16 | #ifdef CONFIG_SPARC |
17 | #include <asm/prom.h> | |
4e08df3f DM |
18 | #endif |
19 | ||
2d70c103 NB |
20 | #include <target/target_core_base.h> |
21 | #include "qla_target.h" | |
22 | ||
1da177e4 LT |
23 | /* |
24 | * QLogic ISP2x00 Hardware Support Function Prototypes. | |
25 | */ | |
1da177e4 | 26 | static int qla2x00_isp_firmware(scsi_qla_host_t *); |
1da177e4 | 27 | static int qla2x00_setup_chip(scsi_qla_host_t *); |
1da177e4 LT |
28 | static int qla2x00_init_rings(scsi_qla_host_t *); |
29 | static int qla2x00_fw_ready(scsi_qla_host_t *); | |
30 | static int qla2x00_configure_hba(scsi_qla_host_t *); | |
1da177e4 LT |
31 | static int qla2x00_configure_loop(scsi_qla_host_t *); |
32 | static int qla2x00_configure_local_loop(scsi_qla_host_t *); | |
1da177e4 LT |
33 | static int qla2x00_configure_fabric(scsi_qla_host_t *); |
34 | static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *, struct list_head *); | |
1da177e4 LT |
35 | static int qla2x00_fabric_dev_login(scsi_qla_host_t *, fc_port_t *, |
36 | uint16_t *); | |
1da177e4 LT |
37 | |
38 | static int qla2x00_restart_isp(scsi_qla_host_t *); | |
1da177e4 | 39 | |
4d4df193 HK |
40 | static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *); |
41 | static int qla84xx_init_chip(scsi_qla_host_t *); | |
73208dfd | 42 | static int qla25xx_init_queues(struct qla_hw_data *); |
4d4df193 | 43 | |
ac280b67 AV |
44 | /* SRB Extensions ---------------------------------------------------------- */ |
45 | ||
9ba56b95 GM |
46 | void |
47 | qla2x00_sp_timeout(unsigned long __data) | |
ac280b67 AV |
48 | { |
49 | srb_t *sp = (srb_t *)__data; | |
4916392b | 50 | struct srb_iocb *iocb; |
ac280b67 AV |
51 | fc_port_t *fcport = sp->fcport; |
52 | struct qla_hw_data *ha = fcport->vha->hw; | |
53 | struct req_que *req; | |
54 | unsigned long flags; | |
55 | ||
56 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
57 | req = ha->req_q_map[0]; | |
58 | req->outstanding_cmds[sp->handle] = NULL; | |
9ba56b95 | 59 | iocb = &sp->u.iocb_cmd; |
4916392b | 60 | iocb->timeout(sp); |
9ba56b95 | 61 | sp->free(fcport->vha, sp); |
6ac52608 | 62 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
ac280b67 AV |
63 | } |
64 | ||
9ba56b95 GM |
65 | void |
66 | qla2x00_sp_free(void *data, void *ptr) | |
ac280b67 | 67 | { |
9ba56b95 GM |
68 | srb_t *sp = (srb_t *)ptr; |
69 | struct srb_iocb *iocb = &sp->u.iocb_cmd; | |
70 | struct scsi_qla_host *vha = (scsi_qla_host_t *)data; | |
ac280b67 | 71 | |
4d97cc53 | 72 | del_timer(&iocb->timer); |
b00ee7d7 | 73 | qla2x00_rel_sp(vha, sp); |
ac280b67 AV |
74 | } |
75 | ||
ac280b67 AV |
76 | /* Asynchronous Login/Logout Routines -------------------------------------- */ |
77 | ||
a9b6f722 | 78 | unsigned long |
5b91490e AV |
79 | qla2x00_get_async_timeout(struct scsi_qla_host *vha) |
80 | { | |
81 | unsigned long tmo; | |
82 | struct qla_hw_data *ha = vha->hw; | |
83 | ||
84 | /* Firmware should use switch negotiated r_a_tov for timeout. */ | |
85 | tmo = ha->r_a_tov / 10 * 2; | |
86 | if (!IS_FWI2_CAPABLE(ha)) { | |
87 | /* | |
88 | * Except for earlier ISPs where the timeout is seeded from the | |
89 | * initialization control block. | |
90 | */ | |
91 | tmo = ha->login_timeout; | |
92 | } | |
93 | return tmo; | |
94 | } | |
ac280b67 AV |
95 | |
96 | static void | |
9ba56b95 | 97 | qla2x00_async_iocb_timeout(void *data) |
ac280b67 | 98 | { |
9ba56b95 | 99 | srb_t *sp = (srb_t *)data; |
ac280b67 | 100 | fc_port_t *fcport = sp->fcport; |
ac280b67 | 101 | |
7c3df132 | 102 | ql_dbg(ql_dbg_disc, fcport->vha, 0x2071, |
cfb0919c | 103 | "Async-%s timeout - hdl=%x portid=%02x%02x%02x.\n", |
9ba56b95 | 104 | sp->name, sp->handle, fcport->d_id.b.domain, fcport->d_id.b.area, |
7c3df132 | 105 | fcport->d_id.b.al_pa); |
ac280b67 | 106 | |
5ff1d584 | 107 | fcport->flags &= ~FCF_ASYNC_SENT; |
9ba56b95 GM |
108 | if (sp->type == SRB_LOGIN_CMD) { |
109 | struct srb_iocb *lio = &sp->u.iocb_cmd; | |
ac280b67 | 110 | qla2x00_post_async_logout_work(fcport->vha, fcport, NULL); |
6ac52608 AV |
111 | /* Retry as needed. */ |
112 | lio->u.logio.data[0] = MBS_COMMAND_ERROR; | |
113 | lio->u.logio.data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ? | |
114 | QLA_LOGIO_LOGIN_RETRIED : 0; | |
115 | qla2x00_post_async_login_done_work(fcport->vha, fcport, | |
116 | lio->u.logio.data); | |
117 | } | |
ac280b67 AV |
118 | } |
119 | ||
99b0bec7 | 120 | static void |
9ba56b95 | 121 | qla2x00_async_login_sp_done(void *data, void *ptr, int res) |
99b0bec7 | 122 | { |
9ba56b95 GM |
123 | srb_t *sp = (srb_t *)ptr; |
124 | struct srb_iocb *lio = &sp->u.iocb_cmd; | |
125 | struct scsi_qla_host *vha = (scsi_qla_host_t *)data; | |
126 | ||
127 | if (!test_bit(UNLOADING, &vha->dpc_flags)) | |
128 | qla2x00_post_async_login_done_work(sp->fcport->vha, sp->fcport, | |
129 | lio->u.logio.data); | |
130 | sp->free(sp->fcport->vha, sp); | |
99b0bec7 AV |
131 | } |
132 | ||
ac280b67 AV |
133 | int |
134 | qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport, | |
135 | uint16_t *data) | |
136 | { | |
ac280b67 | 137 | srb_t *sp; |
4916392b | 138 | struct srb_iocb *lio; |
ac280b67 AV |
139 | int rval; |
140 | ||
141 | rval = QLA_FUNCTION_FAILED; | |
9ba56b95 | 142 | sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); |
ac280b67 AV |
143 | if (!sp) |
144 | goto done; | |
145 | ||
9ba56b95 GM |
146 | sp->type = SRB_LOGIN_CMD; |
147 | sp->name = "login"; | |
148 | qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2); | |
149 | ||
150 | lio = &sp->u.iocb_cmd; | |
3822263e | 151 | lio->timeout = qla2x00_async_iocb_timeout; |
9ba56b95 | 152 | sp->done = qla2x00_async_login_sp_done; |
4916392b | 153 | lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI; |
ac280b67 | 154 | if (data[1] & QLA_LOGIO_LOGIN_RETRIED) |
4916392b | 155 | lio->u.logio.flags |= SRB_LOGIN_RETRIED; |
ac280b67 AV |
156 | rval = qla2x00_start_sp(sp); |
157 | if (rval != QLA_SUCCESS) | |
158 | goto done_free_sp; | |
159 | ||
7c3df132 | 160 | ql_dbg(ql_dbg_disc, vha, 0x2072, |
cfb0919c CD |
161 | "Async-login - hdl=%x, loopid=%x portid=%02x%02x%02x " |
162 | "retries=%d.\n", sp->handle, fcport->loop_id, | |
163 | fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa, | |
164 | fcport->login_retry); | |
ac280b67 AV |
165 | return rval; |
166 | ||
167 | done_free_sp: | |
9ba56b95 | 168 | sp->free(fcport->vha, sp); |
ac280b67 AV |
169 | done: |
170 | return rval; | |
171 | } | |
172 | ||
99b0bec7 | 173 | static void |
9ba56b95 | 174 | qla2x00_async_logout_sp_done(void *data, void *ptr, int res) |
99b0bec7 | 175 | { |
9ba56b95 GM |
176 | srb_t *sp = (srb_t *)ptr; |
177 | struct srb_iocb *lio = &sp->u.iocb_cmd; | |
178 | struct scsi_qla_host *vha = (scsi_qla_host_t *)data; | |
179 | ||
180 | if (!test_bit(UNLOADING, &vha->dpc_flags)) | |
181 | qla2x00_post_async_logout_done_work(sp->fcport->vha, sp->fcport, | |
182 | lio->u.logio.data); | |
183 | sp->free(sp->fcport->vha, sp); | |
99b0bec7 AV |
184 | } |
185 | ||
ac280b67 AV |
186 | int |
187 | qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport) | |
188 | { | |
ac280b67 | 189 | srb_t *sp; |
4916392b | 190 | struct srb_iocb *lio; |
ac280b67 AV |
191 | int rval; |
192 | ||
193 | rval = QLA_FUNCTION_FAILED; | |
9ba56b95 | 194 | sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); |
ac280b67 AV |
195 | if (!sp) |
196 | goto done; | |
197 | ||
9ba56b95 GM |
198 | sp->type = SRB_LOGOUT_CMD; |
199 | sp->name = "logout"; | |
200 | qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2); | |
201 | ||
202 | lio = &sp->u.iocb_cmd; | |
3822263e | 203 | lio->timeout = qla2x00_async_iocb_timeout; |
9ba56b95 | 204 | sp->done = qla2x00_async_logout_sp_done; |
ac280b67 AV |
205 | rval = qla2x00_start_sp(sp); |
206 | if (rval != QLA_SUCCESS) | |
207 | goto done_free_sp; | |
208 | ||
7c3df132 | 209 | ql_dbg(ql_dbg_disc, vha, 0x2070, |
cfb0919c CD |
210 | "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x.\n", |
211 | sp->handle, fcport->loop_id, fcport->d_id.b.domain, | |
212 | fcport->d_id.b.area, fcport->d_id.b.al_pa); | |
ac280b67 AV |
213 | return rval; |
214 | ||
215 | done_free_sp: | |
9ba56b95 | 216 | sp->free(fcport->vha, sp); |
ac280b67 AV |
217 | done: |
218 | return rval; | |
219 | } | |
220 | ||
5ff1d584 | 221 | static void |
9ba56b95 | 222 | qla2x00_async_adisc_sp_done(void *data, void *ptr, int res) |
5ff1d584 | 223 | { |
9ba56b95 GM |
224 | srb_t *sp = (srb_t *)ptr; |
225 | struct srb_iocb *lio = &sp->u.iocb_cmd; | |
226 | struct scsi_qla_host *vha = (scsi_qla_host_t *)data; | |
227 | ||
228 | if (!test_bit(UNLOADING, &vha->dpc_flags)) | |
229 | qla2x00_post_async_adisc_done_work(sp->fcport->vha, sp->fcport, | |
230 | lio->u.logio.data); | |
231 | sp->free(sp->fcport->vha, sp); | |
5ff1d584 AV |
232 | } |
233 | ||
234 | int | |
235 | qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport, | |
236 | uint16_t *data) | |
237 | { | |
5ff1d584 | 238 | srb_t *sp; |
4916392b | 239 | struct srb_iocb *lio; |
5ff1d584 AV |
240 | int rval; |
241 | ||
242 | rval = QLA_FUNCTION_FAILED; | |
9ba56b95 | 243 | sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); |
5ff1d584 AV |
244 | if (!sp) |
245 | goto done; | |
246 | ||
9ba56b95 GM |
247 | sp->type = SRB_ADISC_CMD; |
248 | sp->name = "adisc"; | |
249 | qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2); | |
250 | ||
251 | lio = &sp->u.iocb_cmd; | |
3822263e | 252 | lio->timeout = qla2x00_async_iocb_timeout; |
9ba56b95 | 253 | sp->done = qla2x00_async_adisc_sp_done; |
5ff1d584 | 254 | if (data[1] & QLA_LOGIO_LOGIN_RETRIED) |
4916392b | 255 | lio->u.logio.flags |= SRB_LOGIN_RETRIED; |
5ff1d584 AV |
256 | rval = qla2x00_start_sp(sp); |
257 | if (rval != QLA_SUCCESS) | |
258 | goto done_free_sp; | |
259 | ||
7c3df132 | 260 | ql_dbg(ql_dbg_disc, vha, 0x206f, |
cfb0919c CD |
261 | "Async-adisc - hdl=%x loopid=%x portid=%02x%02x%02x.\n", |
262 | sp->handle, fcport->loop_id, fcport->d_id.b.domain, | |
263 | fcport->d_id.b.area, fcport->d_id.b.al_pa); | |
5ff1d584 AV |
264 | return rval; |
265 | ||
266 | done_free_sp: | |
9ba56b95 | 267 | sp->free(fcport->vha, sp); |
5ff1d584 AV |
268 | done: |
269 | return rval; | |
270 | } | |
271 | ||
3822263e | 272 | static void |
9ba56b95 | 273 | qla2x00_async_tm_cmd_done(void *data, void *ptr, int res) |
3822263e | 274 | { |
9ba56b95 GM |
275 | srb_t *sp = (srb_t *)ptr; |
276 | struct srb_iocb *iocb = &sp->u.iocb_cmd; | |
277 | struct scsi_qla_host *vha = (scsi_qla_host_t *)data; | |
278 | uint32_t flags; | |
279 | uint16_t lun; | |
280 | int rval; | |
3822263e | 281 | |
9ba56b95 GM |
282 | if (!test_bit(UNLOADING, &vha->dpc_flags)) { |
283 | flags = iocb->u.tmf.flags; | |
284 | lun = (uint16_t)iocb->u.tmf.lun; | |
285 | ||
286 | /* Issue Marker IOCB */ | |
287 | rval = qla2x00_marker(vha, vha->hw->req_q_map[0], | |
288 | vha->hw->rsp_q_map[0], sp->fcport->loop_id, lun, | |
289 | flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID); | |
290 | ||
291 | if ((rval != QLA_SUCCESS) || iocb->u.tmf.data) { | |
292 | ql_dbg(ql_dbg_taskm, vha, 0x8030, | |
293 | "TM IOCB failed (%x).\n", rval); | |
294 | } | |
295 | } | |
296 | sp->free(sp->fcport->vha, sp); | |
3822263e MI |
297 | } |
298 | ||
299 | int | |
9ba56b95 | 300 | qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t tm_flags, uint32_t lun, |
3822263e MI |
301 | uint32_t tag) |
302 | { | |
303 | struct scsi_qla_host *vha = fcport->vha; | |
3822263e | 304 | srb_t *sp; |
3822263e MI |
305 | struct srb_iocb *tcf; |
306 | int rval; | |
307 | ||
308 | rval = QLA_FUNCTION_FAILED; | |
9ba56b95 | 309 | sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); |
3822263e MI |
310 | if (!sp) |
311 | goto done; | |
312 | ||
9ba56b95 GM |
313 | sp->type = SRB_TM_CMD; |
314 | sp->name = "tmf"; | |
315 | qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2); | |
316 | ||
317 | tcf = &sp->u.iocb_cmd; | |
318 | tcf->u.tmf.flags = tm_flags; | |
3822263e MI |
319 | tcf->u.tmf.lun = lun; |
320 | tcf->u.tmf.data = tag; | |
321 | tcf->timeout = qla2x00_async_iocb_timeout; | |
9ba56b95 | 322 | sp->done = qla2x00_async_tm_cmd_done; |
3822263e MI |
323 | |
324 | rval = qla2x00_start_sp(sp); | |
325 | if (rval != QLA_SUCCESS) | |
326 | goto done_free_sp; | |
327 | ||
7c3df132 | 328 | ql_dbg(ql_dbg_taskm, vha, 0x802f, |
cfb0919c CD |
329 | "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n", |
330 | sp->handle, fcport->loop_id, fcport->d_id.b.domain, | |
331 | fcport->d_id.b.area, fcport->d_id.b.al_pa); | |
3822263e MI |
332 | return rval; |
333 | ||
334 | done_free_sp: | |
9ba56b95 | 335 | sp->free(fcport->vha, sp); |
3822263e MI |
336 | done: |
337 | return rval; | |
338 | } | |
339 | ||
4916392b | 340 | void |
ac280b67 AV |
341 | qla2x00_async_login_done(struct scsi_qla_host *vha, fc_port_t *fcport, |
342 | uint16_t *data) | |
343 | { | |
344 | int rval; | |
ac280b67 AV |
345 | |
346 | switch (data[0]) { | |
347 | case MBS_COMMAND_COMPLETE: | |
a4f92a32 AV |
348 | /* |
349 | * Driver must validate login state - If PRLI not complete, | |
350 | * force a relogin attempt via implicit LOGO, PLOGI, and PRLI | |
351 | * requests. | |
352 | */ | |
353 | rval = qla2x00_get_port_database(vha, fcport, 0); | |
0eba25df AE |
354 | if (rval == QLA_NOT_LOGGED_IN) { |
355 | fcport->flags &= ~FCF_ASYNC_SENT; | |
356 | fcport->flags |= FCF_LOGIN_NEEDED; | |
357 | set_bit(RELOGIN_NEEDED, &vha->dpc_flags); | |
358 | break; | |
359 | } | |
360 | ||
a4f92a32 AV |
361 | if (rval != QLA_SUCCESS) { |
362 | qla2x00_post_async_logout_work(vha, fcport, NULL); | |
363 | qla2x00_post_async_login_work(vha, fcport, NULL); | |
364 | break; | |
365 | } | |
99b0bec7 | 366 | if (fcport->flags & FCF_FCP2_DEVICE) { |
5ff1d584 AV |
367 | qla2x00_post_async_adisc_work(vha, fcport, data); |
368 | break; | |
99b0bec7 AV |
369 | } |
370 | qla2x00_update_fcport(vha, fcport); | |
ac280b67 AV |
371 | break; |
372 | case MBS_COMMAND_ERROR: | |
5ff1d584 | 373 | fcport->flags &= ~FCF_ASYNC_SENT; |
ac280b67 AV |
374 | if (data[1] & QLA_LOGIO_LOGIN_RETRIED) |
375 | set_bit(RELOGIN_NEEDED, &vha->dpc_flags); | |
376 | else | |
80d79440 | 377 | qla2x00_mark_device_lost(vha, fcport, 1, 0); |
ac280b67 AV |
378 | break; |
379 | case MBS_PORT_ID_USED: | |
380 | fcport->loop_id = data[1]; | |
6ac52608 | 381 | qla2x00_post_async_logout_work(vha, fcport, NULL); |
ac280b67 AV |
382 | qla2x00_post_async_login_work(vha, fcport, NULL); |
383 | break; | |
384 | case MBS_LOOP_ID_USED: | |
385 | fcport->loop_id++; | |
386 | rval = qla2x00_find_new_loop_id(vha, fcport); | |
387 | if (rval != QLA_SUCCESS) { | |
5ff1d584 | 388 | fcport->flags &= ~FCF_ASYNC_SENT; |
80d79440 | 389 | qla2x00_mark_device_lost(vha, fcport, 1, 0); |
ac280b67 AV |
390 | break; |
391 | } | |
392 | qla2x00_post_async_login_work(vha, fcport, NULL); | |
393 | break; | |
394 | } | |
4916392b | 395 | return; |
ac280b67 AV |
396 | } |
397 | ||
4916392b | 398 | void |
ac280b67 AV |
399 | qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport, |
400 | uint16_t *data) | |
401 | { | |
402 | qla2x00_mark_device_lost(vha, fcport, 1, 0); | |
4916392b | 403 | return; |
ac280b67 AV |
404 | } |
405 | ||
4916392b | 406 | void |
5ff1d584 AV |
407 | qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport, |
408 | uint16_t *data) | |
409 | { | |
410 | if (data[0] == MBS_COMMAND_COMPLETE) { | |
411 | qla2x00_update_fcport(vha, fcport); | |
412 | ||
4916392b | 413 | return; |
5ff1d584 AV |
414 | } |
415 | ||
416 | /* Retry login. */ | |
417 | fcport->flags &= ~FCF_ASYNC_SENT; | |
418 | if (data[1] & QLA_LOGIO_LOGIN_RETRIED) | |
419 | set_bit(RELOGIN_NEEDED, &vha->dpc_flags); | |
420 | else | |
80d79440 | 421 | qla2x00_mark_device_lost(vha, fcport, 1, 0); |
5ff1d584 | 422 | |
4916392b | 423 | return; |
5ff1d584 AV |
424 | } |
425 | ||
1da177e4 LT |
426 | /****************************************************************************/ |
427 | /* QLogic ISP2x00 Hardware Support Functions. */ | |
428 | /****************************************************************************/ | |
429 | ||
fa492630 | 430 | static int |
7d613ac6 SV |
431 | qla83xx_nic_core_fw_load(scsi_qla_host_t *vha) |
432 | { | |
433 | int rval = QLA_SUCCESS; | |
434 | struct qla_hw_data *ha = vha->hw; | |
435 | uint32_t idc_major_ver, idc_minor_ver; | |
711aa7f7 | 436 | uint16_t config[4]; |
7d613ac6 SV |
437 | |
438 | qla83xx_idc_lock(vha, 0); | |
439 | ||
440 | /* SV: TODO: Assign initialization timeout from | |
441 | * flash-info / other param | |
442 | */ | |
443 | ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT; | |
444 | ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT; | |
445 | ||
446 | /* Set our fcoe function presence */ | |
447 | if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) { | |
448 | ql_dbg(ql_dbg_p3p, vha, 0xb077, | |
449 | "Error while setting DRV-Presence.\n"); | |
450 | rval = QLA_FUNCTION_FAILED; | |
451 | goto exit; | |
452 | } | |
453 | ||
454 | /* Decide the reset ownership */ | |
455 | qla83xx_reset_ownership(vha); | |
456 | ||
457 | /* | |
458 | * On first protocol driver load: | |
459 | * Init-Owner: Set IDC-Major-Version and Clear IDC-Lock-Recovery | |
460 | * register. | |
461 | * Others: Check compatibility with current IDC Major version. | |
462 | */ | |
463 | qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver); | |
464 | if (ha->flags.nic_core_reset_owner) { | |
465 | /* Set IDC Major version */ | |
466 | idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION; | |
467 | qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver); | |
468 | ||
469 | /* Clearing IDC-Lock-Recovery register */ | |
470 | qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0); | |
471 | } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) { | |
472 | /* | |
473 | * Clear further IDC participation if we are not compatible with | |
474 | * the current IDC Major Version. | |
475 | */ | |
476 | ql_log(ql_log_warn, vha, 0xb07d, | |
477 | "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n", | |
478 | idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION); | |
479 | __qla83xx_clear_drv_presence(vha); | |
480 | rval = QLA_FUNCTION_FAILED; | |
481 | goto exit; | |
482 | } | |
483 | /* Each function sets its supported Minor version. */ | |
484 | qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver); | |
485 | idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2)); | |
486 | qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver); | |
487 | ||
711aa7f7 SK |
488 | if (ha->flags.nic_core_reset_owner) { |
489 | memset(config, 0, sizeof(config)); | |
490 | if (!qla81xx_get_port_config(vha, config)) | |
491 | qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, | |
492 | QLA8XXX_DEV_READY); | |
493 | } | |
494 | ||
7d613ac6 SV |
495 | rval = qla83xx_idc_state_handler(vha); |
496 | ||
497 | exit: | |
498 | qla83xx_idc_unlock(vha, 0); | |
499 | ||
500 | return rval; | |
501 | } | |
502 | ||
1da177e4 LT |
503 | /* |
504 | * qla2x00_initialize_adapter | |
505 | * Initialize board. | |
506 | * | |
507 | * Input: | |
508 | * ha = adapter block pointer. | |
509 | * | |
510 | * Returns: | |
511 | * 0 = success | |
512 | */ | |
513 | int | |
e315cd28 | 514 | qla2x00_initialize_adapter(scsi_qla_host_t *vha) |
1da177e4 LT |
515 | { |
516 | int rval; | |
e315cd28 | 517 | struct qla_hw_data *ha = vha->hw; |
73208dfd | 518 | struct req_que *req = ha->req_q_map[0]; |
2533cf67 | 519 | |
1da177e4 | 520 | /* Clear adapter flags. */ |
e315cd28 | 521 | vha->flags.online = 0; |
2533cf67 | 522 | ha->flags.chip_reset_done = 0; |
e315cd28 | 523 | vha->flags.reset_active = 0; |
85880801 AV |
524 | ha->flags.pci_channel_io_perm_failure = 0; |
525 | ha->flags.eeh_busy = 0; | |
794a5691 | 526 | ha->flags.thermal_supported = 1; |
e315cd28 AC |
527 | atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); |
528 | atomic_set(&vha->loop_state, LOOP_DOWN); | |
529 | vha->device_flags = DFLG_NO_CABLE; | |
530 | vha->dpc_flags = 0; | |
531 | vha->flags.management_server_logged_in = 0; | |
532 | vha->marker_needed = 0; | |
1da177e4 LT |
533 | ha->isp_abort_cnt = 0; |
534 | ha->beacon_blink_led = 0; | |
535 | ||
73208dfd AC |
536 | set_bit(0, ha->req_qid_map); |
537 | set_bit(0, ha->rsp_qid_map); | |
538 | ||
cfb0919c | 539 | ql_dbg(ql_dbg_init, vha, 0x0040, |
7c3df132 | 540 | "Configuring PCI space...\n"); |
e315cd28 | 541 | rval = ha->isp_ops->pci_config(vha); |
1da177e4 | 542 | if (rval) { |
7c3df132 SK |
543 | ql_log(ql_log_warn, vha, 0x0044, |
544 | "Unable to configure PCI space.\n"); | |
1da177e4 LT |
545 | return (rval); |
546 | } | |
547 | ||
e315cd28 | 548 | ha->isp_ops->reset_chip(vha); |
1da177e4 | 549 | |
e315cd28 | 550 | rval = qla2xxx_get_flash_info(vha); |
c00d8994 | 551 | if (rval) { |
7c3df132 SK |
552 | ql_log(ql_log_fatal, vha, 0x004f, |
553 | "Unable to validate FLASH data.\n"); | |
c00d8994 AV |
554 | return (rval); |
555 | } | |
556 | ||
73208dfd | 557 | ha->isp_ops->get_flash_version(vha, req->ring); |
cfb0919c | 558 | ql_dbg(ql_dbg_init, vha, 0x0061, |
7c3df132 | 559 | "Configure NVRAM parameters...\n"); |
0107109e | 560 | |
e315cd28 | 561 | ha->isp_ops->nvram_config(vha); |
1da177e4 | 562 | |
d4c760c2 AV |
563 | if (ha->flags.disable_serdes) { |
564 | /* Mask HBA via NVRAM settings? */ | |
7c3df132 SK |
565 | ql_log(ql_log_info, vha, 0x0077, |
566 | "Masking HBA WWPN " | |
d4c760c2 | 567 | "%02x%02x%02x%02x%02x%02x%02x%02x (via NVRAM).\n", |
e315cd28 AC |
568 | vha->port_name[0], vha->port_name[1], |
569 | vha->port_name[2], vha->port_name[3], | |
570 | vha->port_name[4], vha->port_name[5], | |
571 | vha->port_name[6], vha->port_name[7]); | |
d4c760c2 AV |
572 | return QLA_FUNCTION_FAILED; |
573 | } | |
574 | ||
cfb0919c | 575 | ql_dbg(ql_dbg_init, vha, 0x0078, |
7c3df132 | 576 | "Verifying loaded RISC code...\n"); |
1da177e4 | 577 | |
e315cd28 AC |
578 | if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) { |
579 | rval = ha->isp_ops->chip_diag(vha); | |
d19044c3 AV |
580 | if (rval) |
581 | return (rval); | |
e315cd28 | 582 | rval = qla2x00_setup_chip(vha); |
d19044c3 AV |
583 | if (rval) |
584 | return (rval); | |
1da177e4 | 585 | } |
a9083016 | 586 | |
4d4df193 | 587 | if (IS_QLA84XX(ha)) { |
e315cd28 | 588 | ha->cs84xx = qla84xx_get_chip(vha); |
4d4df193 | 589 | if (!ha->cs84xx) { |
7c3df132 | 590 | ql_log(ql_log_warn, vha, 0x00d0, |
4d4df193 HK |
591 | "Unable to configure ISP84XX.\n"); |
592 | return QLA_FUNCTION_FAILED; | |
593 | } | |
594 | } | |
2d70c103 NB |
595 | |
596 | if (qla_ini_mode_enabled(vha)) | |
597 | rval = qla2x00_init_rings(vha); | |
598 | ||
2533cf67 | 599 | ha->flags.chip_reset_done = 1; |
1da177e4 | 600 | |
9a069e19 | 601 | if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) { |
6c452a45 | 602 | /* Issue verify 84xx FW IOCB to complete 84xx initialization */ |
9a069e19 GM |
603 | rval = qla84xx_init_chip(vha); |
604 | if (rval != QLA_SUCCESS) { | |
7c3df132 SK |
605 | ql_log(ql_log_warn, vha, 0x00d4, |
606 | "Unable to initialize ISP84XX.\n"); | |
9a069e19 GM |
607 | qla84xx_put_chip(vha); |
608 | } | |
609 | } | |
610 | ||
7d613ac6 SV |
611 | /* Load the NIC Core f/w if we are the first protocol driver. */ |
612 | if (IS_QLA8031(ha)) { | |
613 | rval = qla83xx_nic_core_fw_load(vha); | |
614 | if (rval) | |
615 | ql_log(ql_log_warn, vha, 0x0124, | |
616 | "Error in initializing NIC Core f/w.\n"); | |
617 | } | |
618 | ||
2f0f3f4f MI |
619 | if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha)) |
620 | qla24xx_read_fcp_prio_cfg(vha); | |
09ff701a | 621 | |
1da177e4 LT |
622 | return (rval); |
623 | } | |
624 | ||
625 | /** | |
abbd8870 | 626 | * qla2100_pci_config() - Setup ISP21xx PCI configuration registers. |
1da177e4 LT |
627 | * @ha: HA context |
628 | * | |
629 | * Returns 0 on success. | |
630 | */ | |
abbd8870 | 631 | int |
e315cd28 | 632 | qla2100_pci_config(scsi_qla_host_t *vha) |
1da177e4 | 633 | { |
a157b101 | 634 | uint16_t w; |
abbd8870 | 635 | unsigned long flags; |
e315cd28 | 636 | struct qla_hw_data *ha = vha->hw; |
3d71644c | 637 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
1da177e4 | 638 | |
1da177e4 | 639 | pci_set_master(ha->pdev); |
af6177d8 | 640 | pci_try_set_mwi(ha->pdev); |
1da177e4 | 641 | |
1da177e4 | 642 | pci_read_config_word(ha->pdev, PCI_COMMAND, &w); |
a157b101 | 643 | w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); |
abbd8870 AV |
644 | pci_write_config_word(ha->pdev, PCI_COMMAND, w); |
645 | ||
737faece | 646 | pci_disable_rom(ha->pdev); |
1da177e4 LT |
647 | |
648 | /* Get PCI bus information. */ | |
649 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
3d71644c | 650 | ha->pci_attr = RD_REG_WORD(®->ctrl_status); |
1da177e4 LT |
651 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
652 | ||
abbd8870 AV |
653 | return QLA_SUCCESS; |
654 | } | |
1da177e4 | 655 | |
abbd8870 AV |
656 | /** |
657 | * qla2300_pci_config() - Setup ISP23xx PCI configuration registers. | |
658 | * @ha: HA context | |
659 | * | |
660 | * Returns 0 on success. | |
661 | */ | |
662 | int | |
e315cd28 | 663 | qla2300_pci_config(scsi_qla_host_t *vha) |
abbd8870 | 664 | { |
a157b101 | 665 | uint16_t w; |
abbd8870 AV |
666 | unsigned long flags = 0; |
667 | uint32_t cnt; | |
e315cd28 | 668 | struct qla_hw_data *ha = vha->hw; |
3d71644c | 669 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
1da177e4 | 670 | |
abbd8870 | 671 | pci_set_master(ha->pdev); |
af6177d8 | 672 | pci_try_set_mwi(ha->pdev); |
1da177e4 | 673 | |
abbd8870 | 674 | pci_read_config_word(ha->pdev, PCI_COMMAND, &w); |
a157b101 | 675 | w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); |
1da177e4 | 676 | |
abbd8870 AV |
677 | if (IS_QLA2322(ha) || IS_QLA6322(ha)) |
678 | w &= ~PCI_COMMAND_INTX_DISABLE; | |
a157b101 | 679 | pci_write_config_word(ha->pdev, PCI_COMMAND, w); |
1da177e4 | 680 | |
abbd8870 AV |
681 | /* |
682 | * If this is a 2300 card and not 2312, reset the | |
683 | * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately, | |
684 | * the 2310 also reports itself as a 2300 so we need to get the | |
685 | * fb revision level -- a 6 indicates it really is a 2300 and | |
686 | * not a 2310. | |
687 | */ | |
688 | if (IS_QLA2300(ha)) { | |
689 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1da177e4 | 690 | |
abbd8870 | 691 | /* Pause RISC. */ |
3d71644c | 692 | WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); |
abbd8870 | 693 | for (cnt = 0; cnt < 30000; cnt++) { |
3d71644c | 694 | if ((RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) != 0) |
abbd8870 | 695 | break; |
1da177e4 | 696 | |
abbd8870 AV |
697 | udelay(10); |
698 | } | |
1da177e4 | 699 | |
abbd8870 | 700 | /* Select FPM registers. */ |
3d71644c AV |
701 | WRT_REG_WORD(®->ctrl_status, 0x20); |
702 | RD_REG_WORD(®->ctrl_status); | |
abbd8870 AV |
703 | |
704 | /* Get the fb rev level */ | |
3d71644c | 705 | ha->fb_rev = RD_FB_CMD_REG(ha, reg); |
abbd8870 AV |
706 | |
707 | if (ha->fb_rev == FPM_2300) | |
a157b101 | 708 | pci_clear_mwi(ha->pdev); |
abbd8870 AV |
709 | |
710 | /* Deselect FPM registers. */ | |
3d71644c AV |
711 | WRT_REG_WORD(®->ctrl_status, 0x0); |
712 | RD_REG_WORD(®->ctrl_status); | |
abbd8870 AV |
713 | |
714 | /* Release RISC module. */ | |
3d71644c | 715 | WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); |
abbd8870 | 716 | for (cnt = 0; cnt < 30000; cnt++) { |
3d71644c | 717 | if ((RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0) |
abbd8870 AV |
718 | break; |
719 | ||
720 | udelay(10); | |
1da177e4 | 721 | } |
1da177e4 | 722 | |
abbd8870 AV |
723 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
724 | } | |
1da177e4 | 725 | |
abbd8870 AV |
726 | pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80); |
727 | ||
737faece | 728 | pci_disable_rom(ha->pdev); |
1da177e4 | 729 | |
abbd8870 AV |
730 | /* Get PCI bus information. */ |
731 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
3d71644c | 732 | ha->pci_attr = RD_REG_WORD(®->ctrl_status); |
abbd8870 AV |
733 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
734 | ||
735 | return QLA_SUCCESS; | |
1da177e4 LT |
736 | } |
737 | ||
0107109e AV |
738 | /** |
739 | * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers. | |
740 | * @ha: HA context | |
741 | * | |
742 | * Returns 0 on success. | |
743 | */ | |
744 | int | |
e315cd28 | 745 | qla24xx_pci_config(scsi_qla_host_t *vha) |
0107109e | 746 | { |
a157b101 | 747 | uint16_t w; |
0107109e | 748 | unsigned long flags = 0; |
e315cd28 | 749 | struct qla_hw_data *ha = vha->hw; |
0107109e | 750 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
0107109e AV |
751 | |
752 | pci_set_master(ha->pdev); | |
af6177d8 | 753 | pci_try_set_mwi(ha->pdev); |
0107109e AV |
754 | |
755 | pci_read_config_word(ha->pdev, PCI_COMMAND, &w); | |
a157b101 | 756 | w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); |
0107109e AV |
757 | w &= ~PCI_COMMAND_INTX_DISABLE; |
758 | pci_write_config_word(ha->pdev, PCI_COMMAND, w); | |
759 | ||
760 | pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80); | |
761 | ||
762 | /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */ | |
f85ec187 AV |
763 | if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX)) |
764 | pcix_set_mmrbc(ha->pdev, 2048); | |
0107109e AV |
765 | |
766 | /* PCIe -- adjust Maximum Read Request Size (2048). */ | |
e67f1321 | 767 | if (pci_is_pcie(ha->pdev)) |
5ffd3a52 | 768 | pcie_set_readrq(ha->pdev, 4096); |
0107109e | 769 | |
737faece | 770 | pci_disable_rom(ha->pdev); |
0107109e | 771 | |
44c10138 | 772 | ha->chip_revision = ha->pdev->revision; |
a8488abe | 773 | |
0107109e AV |
774 | /* Get PCI bus information. */ |
775 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
776 | ha->pci_attr = RD_REG_DWORD(®->ctrl_status); | |
777 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
778 | ||
779 | return QLA_SUCCESS; | |
780 | } | |
781 | ||
c3a2f0df AV |
782 | /** |
783 | * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers. | |
784 | * @ha: HA context | |
785 | * | |
786 | * Returns 0 on success. | |
787 | */ | |
788 | int | |
e315cd28 | 789 | qla25xx_pci_config(scsi_qla_host_t *vha) |
c3a2f0df AV |
790 | { |
791 | uint16_t w; | |
e315cd28 | 792 | struct qla_hw_data *ha = vha->hw; |
c3a2f0df AV |
793 | |
794 | pci_set_master(ha->pdev); | |
795 | pci_try_set_mwi(ha->pdev); | |
796 | ||
797 | pci_read_config_word(ha->pdev, PCI_COMMAND, &w); | |
798 | w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); | |
799 | w &= ~PCI_COMMAND_INTX_DISABLE; | |
800 | pci_write_config_word(ha->pdev, PCI_COMMAND, w); | |
801 | ||
802 | /* PCIe -- adjust Maximum Read Request Size (2048). */ | |
e67f1321 | 803 | if (pci_is_pcie(ha->pdev)) |
5ffd3a52 | 804 | pcie_set_readrq(ha->pdev, 4096); |
c3a2f0df | 805 | |
737faece | 806 | pci_disable_rom(ha->pdev); |
c3a2f0df AV |
807 | |
808 | ha->chip_revision = ha->pdev->revision; | |
809 | ||
810 | return QLA_SUCCESS; | |
811 | } | |
812 | ||
1da177e4 LT |
813 | /** |
814 | * qla2x00_isp_firmware() - Choose firmware image. | |
815 | * @ha: HA context | |
816 | * | |
817 | * Returns 0 on success. | |
818 | */ | |
819 | static int | |
e315cd28 | 820 | qla2x00_isp_firmware(scsi_qla_host_t *vha) |
1da177e4 LT |
821 | { |
822 | int rval; | |
42e421b1 AV |
823 | uint16_t loop_id, topo, sw_cap; |
824 | uint8_t domain, area, al_pa; | |
e315cd28 | 825 | struct qla_hw_data *ha = vha->hw; |
1da177e4 LT |
826 | |
827 | /* Assume loading risc code */ | |
fa2a1ce5 | 828 | rval = QLA_FUNCTION_FAILED; |
1da177e4 LT |
829 | |
830 | if (ha->flags.disable_risc_code_load) { | |
7c3df132 | 831 | ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n"); |
1da177e4 LT |
832 | |
833 | /* Verify checksum of loaded RISC code. */ | |
e315cd28 | 834 | rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address); |
42e421b1 AV |
835 | if (rval == QLA_SUCCESS) { |
836 | /* And, verify we are not in ROM code. */ | |
e315cd28 | 837 | rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa, |
42e421b1 AV |
838 | &area, &domain, &topo, &sw_cap); |
839 | } | |
1da177e4 LT |
840 | } |
841 | ||
7c3df132 SK |
842 | if (rval) |
843 | ql_dbg(ql_dbg_init, vha, 0x007a, | |
844 | "**** Load RISC code ****.\n"); | |
1da177e4 LT |
845 | |
846 | return (rval); | |
847 | } | |
848 | ||
849 | /** | |
850 | * qla2x00_reset_chip() - Reset ISP chip. | |
851 | * @ha: HA context | |
852 | * | |
853 | * Returns 0 on success. | |
854 | */ | |
abbd8870 | 855 | void |
e315cd28 | 856 | qla2x00_reset_chip(scsi_qla_host_t *vha) |
1da177e4 LT |
857 | { |
858 | unsigned long flags = 0; | |
e315cd28 | 859 | struct qla_hw_data *ha = vha->hw; |
3d71644c | 860 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
1da177e4 | 861 | uint32_t cnt; |
1da177e4 LT |
862 | uint16_t cmd; |
863 | ||
85880801 AV |
864 | if (unlikely(pci_channel_offline(ha->pdev))) |
865 | return; | |
866 | ||
fd34f556 | 867 | ha->isp_ops->disable_intrs(ha); |
1da177e4 LT |
868 | |
869 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
870 | ||
871 | /* Turn off master enable */ | |
872 | cmd = 0; | |
873 | pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd); | |
874 | cmd &= ~PCI_COMMAND_MASTER; | |
875 | pci_write_config_word(ha->pdev, PCI_COMMAND, cmd); | |
876 | ||
877 | if (!IS_QLA2100(ha)) { | |
878 | /* Pause RISC. */ | |
879 | WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); | |
880 | if (IS_QLA2200(ha) || IS_QLA2300(ha)) { | |
881 | for (cnt = 0; cnt < 30000; cnt++) { | |
882 | if ((RD_REG_WORD(®->hccr) & | |
883 | HCCR_RISC_PAUSE) != 0) | |
884 | break; | |
885 | udelay(100); | |
886 | } | |
887 | } else { | |
888 | RD_REG_WORD(®->hccr); /* PCI Posting. */ | |
889 | udelay(10); | |
890 | } | |
891 | ||
892 | /* Select FPM registers. */ | |
893 | WRT_REG_WORD(®->ctrl_status, 0x20); | |
894 | RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ | |
895 | ||
896 | /* FPM Soft Reset. */ | |
897 | WRT_REG_WORD(®->fpm_diag_config, 0x100); | |
898 | RD_REG_WORD(®->fpm_diag_config); /* PCI Posting. */ | |
899 | ||
900 | /* Toggle Fpm Reset. */ | |
901 | if (!IS_QLA2200(ha)) { | |
902 | WRT_REG_WORD(®->fpm_diag_config, 0x0); | |
903 | RD_REG_WORD(®->fpm_diag_config); /* PCI Posting. */ | |
904 | } | |
905 | ||
906 | /* Select frame buffer registers. */ | |
907 | WRT_REG_WORD(®->ctrl_status, 0x10); | |
908 | RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ | |
909 | ||
910 | /* Reset frame buffer FIFOs. */ | |
911 | if (IS_QLA2200(ha)) { | |
912 | WRT_FB_CMD_REG(ha, reg, 0xa000); | |
913 | RD_FB_CMD_REG(ha, reg); /* PCI Posting. */ | |
914 | } else { | |
915 | WRT_FB_CMD_REG(ha, reg, 0x00fc); | |
916 | ||
917 | /* Read back fb_cmd until zero or 3 seconds max */ | |
918 | for (cnt = 0; cnt < 3000; cnt++) { | |
919 | if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0) | |
920 | break; | |
921 | udelay(100); | |
922 | } | |
923 | } | |
924 | ||
925 | /* Select RISC module registers. */ | |
926 | WRT_REG_WORD(®->ctrl_status, 0); | |
927 | RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ | |
928 | ||
929 | /* Reset RISC processor. */ | |
930 | WRT_REG_WORD(®->hccr, HCCR_RESET_RISC); | |
931 | RD_REG_WORD(®->hccr); /* PCI Posting. */ | |
932 | ||
933 | /* Release RISC processor. */ | |
934 | WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); | |
935 | RD_REG_WORD(®->hccr); /* PCI Posting. */ | |
936 | } | |
937 | ||
938 | WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); | |
939 | WRT_REG_WORD(®->hccr, HCCR_CLR_HOST_INT); | |
940 | ||
941 | /* Reset ISP chip. */ | |
942 | WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); | |
943 | ||
944 | /* Wait for RISC to recover from reset. */ | |
945 | if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) { | |
946 | /* | |
947 | * It is necessary to for a delay here since the card doesn't | |
948 | * respond to PCI reads during a reset. On some architectures | |
949 | * this will result in an MCA. | |
950 | */ | |
951 | udelay(20); | |
952 | for (cnt = 30000; cnt; cnt--) { | |
953 | if ((RD_REG_WORD(®->ctrl_status) & | |
954 | CSR_ISP_SOFT_RESET) == 0) | |
955 | break; | |
956 | udelay(100); | |
957 | } | |
958 | } else | |
959 | udelay(10); | |
960 | ||
961 | /* Reset RISC processor. */ | |
962 | WRT_REG_WORD(®->hccr, HCCR_RESET_RISC); | |
963 | ||
964 | WRT_REG_WORD(®->semaphore, 0); | |
965 | ||
966 | /* Release RISC processor. */ | |
967 | WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); | |
968 | RD_REG_WORD(®->hccr); /* PCI Posting. */ | |
969 | ||
970 | if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) { | |
971 | for (cnt = 0; cnt < 30000; cnt++) { | |
ffb39f03 | 972 | if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY) |
1da177e4 | 973 | break; |
1da177e4 LT |
974 | |
975 | udelay(100); | |
976 | } | |
977 | } else | |
978 | udelay(100); | |
979 | ||
980 | /* Turn on master enable */ | |
981 | cmd |= PCI_COMMAND_MASTER; | |
982 | pci_write_config_word(ha->pdev, PCI_COMMAND, cmd); | |
983 | ||
984 | /* Disable RISC pause on FPM parity error. */ | |
985 | if (!IS_QLA2100(ha)) { | |
986 | WRT_REG_WORD(®->hccr, HCCR_DISABLE_PARITY_PAUSE); | |
987 | RD_REG_WORD(®->hccr); /* PCI Posting. */ | |
988 | } | |
989 | ||
990 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
991 | } | |
992 | ||
b1d46989 MI |
993 | /** |
994 | * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC. | |
995 | * | |
996 | * Returns 0 on success. | |
997 | */ | |
fa492630 | 998 | static int |
b1d46989 MI |
999 | qla81xx_reset_mpi(scsi_qla_host_t *vha) |
1000 | { | |
1001 | uint16_t mb[4] = {0x1010, 0, 1, 0}; | |
1002 | ||
6246b8a1 GM |
1003 | if (!IS_QLA81XX(vha->hw)) |
1004 | return QLA_SUCCESS; | |
1005 | ||
b1d46989 MI |
1006 | return qla81xx_write_mpi_register(vha, mb); |
1007 | } | |
1008 | ||
0107109e | 1009 | /** |
88c26663 | 1010 | * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC. |
0107109e AV |
1011 | * @ha: HA context |
1012 | * | |
1013 | * Returns 0 on success. | |
1014 | */ | |
88c26663 | 1015 | static inline void |
e315cd28 | 1016 | qla24xx_reset_risc(scsi_qla_host_t *vha) |
0107109e AV |
1017 | { |
1018 | unsigned long flags = 0; | |
e315cd28 | 1019 | struct qla_hw_data *ha = vha->hw; |
0107109e AV |
1020 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
1021 | uint32_t cnt, d2; | |
335a1cc9 | 1022 | uint16_t wd; |
b1d46989 | 1023 | static int abts_cnt; /* ISP abort retry counts */ |
0107109e | 1024 | |
0107109e AV |
1025 | spin_lock_irqsave(&ha->hardware_lock, flags); |
1026 | ||
1027 | /* Reset RISC. */ | |
1028 | WRT_REG_DWORD(®->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); | |
1029 | for (cnt = 0; cnt < 30000; cnt++) { | |
1030 | if ((RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0) | |
1031 | break; | |
1032 | ||
1033 | udelay(10); | |
1034 | } | |
1035 | ||
1036 | WRT_REG_DWORD(®->ctrl_status, | |
1037 | CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); | |
335a1cc9 | 1038 | pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); |
88c26663 | 1039 | |
335a1cc9 | 1040 | udelay(100); |
88c26663 | 1041 | /* Wait for firmware to complete NVRAM accesses. */ |
88c26663 AV |
1042 | d2 = (uint32_t) RD_REG_WORD(®->mailbox0); |
1043 | for (cnt = 10000 ; cnt && d2; cnt--) { | |
1044 | udelay(5); | |
1045 | d2 = (uint32_t) RD_REG_WORD(®->mailbox0); | |
1046 | barrier(); | |
1047 | } | |
1048 | ||
335a1cc9 | 1049 | /* Wait for soft-reset to complete. */ |
0107109e AV |
1050 | d2 = RD_REG_DWORD(®->ctrl_status); |
1051 | for (cnt = 6000000 ; cnt && (d2 & CSRX_ISP_SOFT_RESET); cnt--) { | |
1052 | udelay(5); | |
1053 | d2 = RD_REG_DWORD(®->ctrl_status); | |
1054 | barrier(); | |
1055 | } | |
1056 | ||
b1d46989 MI |
1057 | /* If required, do an MPI FW reset now */ |
1058 | if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) { | |
1059 | if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) { | |
1060 | if (++abts_cnt < 5) { | |
1061 | set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); | |
1062 | set_bit(MPI_RESET_NEEDED, &vha->dpc_flags); | |
1063 | } else { | |
1064 | /* | |
1065 | * We exhausted the ISP abort retries. We have to | |
1066 | * set the board offline. | |
1067 | */ | |
1068 | abts_cnt = 0; | |
1069 | vha->flags.online = 0; | |
1070 | } | |
1071 | } | |
1072 | } | |
1073 | ||
0107109e AV |
1074 | WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_RESET); |
1075 | RD_REG_DWORD(®->hccr); | |
1076 | ||
1077 | WRT_REG_DWORD(®->hccr, HCCRX_REL_RISC_PAUSE); | |
1078 | RD_REG_DWORD(®->hccr); | |
1079 | ||
1080 | WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET); | |
1081 | RD_REG_DWORD(®->hccr); | |
1082 | ||
1083 | d2 = (uint32_t) RD_REG_WORD(®->mailbox0); | |
1084 | for (cnt = 6000000 ; cnt && d2; cnt--) { | |
1085 | udelay(5); | |
1086 | d2 = (uint32_t) RD_REG_WORD(®->mailbox0); | |
1087 | barrier(); | |
1088 | } | |
1089 | ||
1090 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
124f85e6 AV |
1091 | |
1092 | if (IS_NOPOLLING_TYPE(ha)) | |
1093 | ha->isp_ops->enable_intrs(ha); | |
0107109e AV |
1094 | } |
1095 | ||
4ea2c9c7 JC |
1096 | static void |
1097 | qla25xx_read_risc_sema_reg(scsi_qla_host_t *vha, uint32_t *data) | |
1098 | { | |
1099 | struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24; | |
1100 | ||
1101 | WRT_REG_DWORD(®->iobase_addr, RISC_REGISTER_BASE_OFFSET); | |
1102 | *data = RD_REG_DWORD(®->iobase_window + RISC_REGISTER_WINDOW_OFFET); | |
1103 | ||
1104 | } | |
1105 | ||
1106 | static void | |
1107 | qla25xx_write_risc_sema_reg(scsi_qla_host_t *vha, uint32_t data) | |
1108 | { | |
1109 | struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24; | |
1110 | ||
1111 | WRT_REG_DWORD(®->iobase_addr, RISC_REGISTER_BASE_OFFSET); | |
1112 | WRT_REG_DWORD(®->iobase_window + RISC_REGISTER_WINDOW_OFFET, data); | |
1113 | } | |
1114 | ||
1115 | static void | |
1116 | qla25xx_manipulate_risc_semaphore(scsi_qla_host_t *vha) | |
1117 | { | |
1118 | struct qla_hw_data *ha = vha->hw; | |
1119 | uint32_t wd32 = 0; | |
1120 | uint delta_msec = 100; | |
1121 | uint elapsed_msec = 0; | |
1122 | uint timeout_msec; | |
1123 | ulong n; | |
1124 | ||
1125 | if (!IS_QLA25XX(ha) && !IS_QLA2031(ha)) | |
1126 | return; | |
1127 | ||
1128 | attempt: | |
1129 | timeout_msec = TIMEOUT_SEMAPHORE; | |
1130 | n = timeout_msec / delta_msec; | |
1131 | while (n--) { | |
1132 | qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_SET); | |
1133 | qla25xx_read_risc_sema_reg(vha, &wd32); | |
1134 | if (wd32 & RISC_SEMAPHORE) | |
1135 | break; | |
1136 | msleep(delta_msec); | |
1137 | elapsed_msec += delta_msec; | |
1138 | if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED) | |
1139 | goto force; | |
1140 | } | |
1141 | ||
1142 | if (!(wd32 & RISC_SEMAPHORE)) | |
1143 | goto force; | |
1144 | ||
1145 | if (!(wd32 & RISC_SEMAPHORE_FORCE)) | |
1146 | goto acquired; | |
1147 | ||
1148 | qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_CLR); | |
1149 | timeout_msec = TIMEOUT_SEMAPHORE_FORCE; | |
1150 | n = timeout_msec / delta_msec; | |
1151 | while (n--) { | |
1152 | qla25xx_read_risc_sema_reg(vha, &wd32); | |
1153 | if (!(wd32 & RISC_SEMAPHORE_FORCE)) | |
1154 | break; | |
1155 | msleep(delta_msec); | |
1156 | elapsed_msec += delta_msec; | |
1157 | if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED) | |
1158 | goto force; | |
1159 | } | |
1160 | ||
1161 | if (wd32 & RISC_SEMAPHORE_FORCE) | |
1162 | qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_CLR); | |
1163 | ||
1164 | goto attempt; | |
1165 | ||
1166 | force: | |
1167 | qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_SET); | |
1168 | ||
1169 | acquired: | |
1170 | return; | |
1171 | } | |
1172 | ||
88c26663 AV |
1173 | /** |
1174 | * qla24xx_reset_chip() - Reset ISP24xx chip. | |
1175 | * @ha: HA context | |
1176 | * | |
1177 | * Returns 0 on success. | |
1178 | */ | |
1179 | void | |
e315cd28 | 1180 | qla24xx_reset_chip(scsi_qla_host_t *vha) |
88c26663 | 1181 | { |
e315cd28 | 1182 | struct qla_hw_data *ha = vha->hw; |
85880801 AV |
1183 | |
1184 | if (pci_channel_offline(ha->pdev) && | |
1185 | ha->flags.pci_channel_io_perm_failure) { | |
1186 | return; | |
1187 | } | |
1188 | ||
fd34f556 | 1189 | ha->isp_ops->disable_intrs(ha); |
88c26663 | 1190 | |
4ea2c9c7 JC |
1191 | qla25xx_manipulate_risc_semaphore(vha); |
1192 | ||
88c26663 | 1193 | /* Perform RISC reset. */ |
e315cd28 | 1194 | qla24xx_reset_risc(vha); |
88c26663 AV |
1195 | } |
1196 | ||
1da177e4 LT |
1197 | /** |
1198 | * qla2x00_chip_diag() - Test chip for proper operation. | |
1199 | * @ha: HA context | |
1200 | * | |
1201 | * Returns 0 on success. | |
1202 | */ | |
abbd8870 | 1203 | int |
e315cd28 | 1204 | qla2x00_chip_diag(scsi_qla_host_t *vha) |
1da177e4 LT |
1205 | { |
1206 | int rval; | |
e315cd28 | 1207 | struct qla_hw_data *ha = vha->hw; |
3d71644c | 1208 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
1da177e4 LT |
1209 | unsigned long flags = 0; |
1210 | uint16_t data; | |
1211 | uint32_t cnt; | |
1212 | uint16_t mb[5]; | |
73208dfd | 1213 | struct req_que *req = ha->req_q_map[0]; |
1da177e4 LT |
1214 | |
1215 | /* Assume a failed state */ | |
1216 | rval = QLA_FUNCTION_FAILED; | |
1217 | ||
7c3df132 SK |
1218 | ql_dbg(ql_dbg_init, vha, 0x007b, |
1219 | "Testing device at %lx.\n", (u_long)®->flash_address); | |
1da177e4 LT |
1220 | |
1221 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1222 | ||
1223 | /* Reset ISP chip. */ | |
1224 | WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); | |
1225 | ||
1226 | /* | |
1227 | * We need to have a delay here since the card will not respond while | |
1228 | * in reset causing an MCA on some architectures. | |
1229 | */ | |
1230 | udelay(20); | |
1231 | data = qla2x00_debounce_register(®->ctrl_status); | |
1232 | for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) { | |
1233 | udelay(5); | |
1234 | data = RD_REG_WORD(®->ctrl_status); | |
1235 | barrier(); | |
1236 | } | |
1237 | ||
1238 | if (!cnt) | |
1239 | goto chip_diag_failed; | |
1240 | ||
7c3df132 SK |
1241 | ql_dbg(ql_dbg_init, vha, 0x007c, |
1242 | "Reset register cleared by chip reset.\n"); | |
1da177e4 LT |
1243 | |
1244 | /* Reset RISC processor. */ | |
1245 | WRT_REG_WORD(®->hccr, HCCR_RESET_RISC); | |
1246 | WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); | |
1247 | ||
1248 | /* Workaround for QLA2312 PCI parity error */ | |
1249 | if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) { | |
1250 | data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0)); | |
1251 | for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) { | |
1252 | udelay(5); | |
1253 | data = RD_MAILBOX_REG(ha, reg, 0); | |
fa2a1ce5 | 1254 | barrier(); |
1da177e4 LT |
1255 | } |
1256 | } else | |
1257 | udelay(10); | |
1258 | ||
1259 | if (!cnt) | |
1260 | goto chip_diag_failed; | |
1261 | ||
1262 | /* Check product ID of chip */ | |
7c3df132 | 1263 | ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product Id of chip.\n"); |
1da177e4 LT |
1264 | |
1265 | mb[1] = RD_MAILBOX_REG(ha, reg, 1); | |
1266 | mb[2] = RD_MAILBOX_REG(ha, reg, 2); | |
1267 | mb[3] = RD_MAILBOX_REG(ha, reg, 3); | |
1268 | mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4)); | |
1269 | if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) || | |
1270 | mb[3] != PROD_ID_3) { | |
7c3df132 SK |
1271 | ql_log(ql_log_warn, vha, 0x0062, |
1272 | "Wrong product ID = 0x%x,0x%x,0x%x.\n", | |
1273 | mb[1], mb[2], mb[3]); | |
1da177e4 LT |
1274 | |
1275 | goto chip_diag_failed; | |
1276 | } | |
1277 | ha->product_id[0] = mb[1]; | |
1278 | ha->product_id[1] = mb[2]; | |
1279 | ha->product_id[2] = mb[3]; | |
1280 | ha->product_id[3] = mb[4]; | |
1281 | ||
1282 | /* Adjust fw RISC transfer size */ | |
73208dfd | 1283 | if (req->length > 1024) |
1da177e4 LT |
1284 | ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024; |
1285 | else | |
1286 | ha->fw_transfer_size = REQUEST_ENTRY_SIZE * | |
73208dfd | 1287 | req->length; |
1da177e4 LT |
1288 | |
1289 | if (IS_QLA2200(ha) && | |
1290 | RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) { | |
1291 | /* Limit firmware transfer size with a 2200A */ | |
7c3df132 | 1292 | ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n"); |
1da177e4 | 1293 | |
ea5b6382 | 1294 | ha->device_type |= DT_ISP2200A; |
1da177e4 LT |
1295 | ha->fw_transfer_size = 128; |
1296 | } | |
1297 | ||
1298 | /* Wrap Incoming Mailboxes Test. */ | |
1299 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1300 | ||
7c3df132 | 1301 | ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n"); |
e315cd28 | 1302 | rval = qla2x00_mbx_reg_test(vha); |
7c3df132 SK |
1303 | if (rval) |
1304 | ql_log(ql_log_warn, vha, 0x0080, | |
1305 | "Failed mailbox send register test.\n"); | |
1306 | else | |
1da177e4 LT |
1307 | /* Flag a successful rval */ |
1308 | rval = QLA_SUCCESS; | |
1da177e4 LT |
1309 | spin_lock_irqsave(&ha->hardware_lock, flags); |
1310 | ||
1311 | chip_diag_failed: | |
1312 | if (rval) | |
7c3df132 SK |
1313 | ql_log(ql_log_info, vha, 0x0081, |
1314 | "Chip diagnostics **** FAILED ****.\n"); | |
1da177e4 LT |
1315 | |
1316 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1317 | ||
1318 | return (rval); | |
1319 | } | |
1320 | ||
0107109e AV |
1321 | /** |
1322 | * qla24xx_chip_diag() - Test ISP24xx for proper operation. | |
1323 | * @ha: HA context | |
1324 | * | |
1325 | * Returns 0 on success. | |
1326 | */ | |
1327 | int | |
e315cd28 | 1328 | qla24xx_chip_diag(scsi_qla_host_t *vha) |
0107109e AV |
1329 | { |
1330 | int rval; | |
e315cd28 | 1331 | struct qla_hw_data *ha = vha->hw; |
73208dfd | 1332 | struct req_que *req = ha->req_q_map[0]; |
0107109e | 1333 | |
a9083016 GM |
1334 | if (IS_QLA82XX(ha)) |
1335 | return QLA_SUCCESS; | |
1336 | ||
73208dfd | 1337 | ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length; |
0107109e | 1338 | |
e315cd28 | 1339 | rval = qla2x00_mbx_reg_test(vha); |
0107109e | 1340 | if (rval) { |
7c3df132 SK |
1341 | ql_log(ql_log_warn, vha, 0x0082, |
1342 | "Failed mailbox send register test.\n"); | |
0107109e AV |
1343 | } else { |
1344 | /* Flag a successful rval */ | |
1345 | rval = QLA_SUCCESS; | |
1346 | } | |
1347 | ||
1348 | return rval; | |
1349 | } | |
1350 | ||
a7a167bf | 1351 | void |
e315cd28 | 1352 | qla2x00_alloc_fw_dump(scsi_qla_host_t *vha) |
0107109e | 1353 | { |
a7a167bf AV |
1354 | int rval; |
1355 | uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size, | |
73208dfd | 1356 | eft_size, fce_size, mq_size; |
df613b96 AV |
1357 | dma_addr_t tc_dma; |
1358 | void *tc; | |
e315cd28 | 1359 | struct qla_hw_data *ha = vha->hw; |
73208dfd AC |
1360 | struct req_que *req = ha->req_q_map[0]; |
1361 | struct rsp_que *rsp = ha->rsp_q_map[0]; | |
a7a167bf AV |
1362 | |
1363 | if (ha->fw_dump) { | |
7c3df132 SK |
1364 | ql_dbg(ql_dbg_init, vha, 0x00bd, |
1365 | "Firmware dump already allocated.\n"); | |
a7a167bf AV |
1366 | return; |
1367 | } | |
d4e3e04d | 1368 | |
0107109e | 1369 | ha->fw_dumped = 0; |
73208dfd | 1370 | fixed_size = mem_size = eft_size = fce_size = mq_size = 0; |
d4e3e04d | 1371 | if (IS_QLA2100(ha) || IS_QLA2200(ha)) { |
a7a167bf | 1372 | fixed_size = sizeof(struct qla2100_fw_dump); |
d4e3e04d | 1373 | } else if (IS_QLA23XX(ha)) { |
a7a167bf AV |
1374 | fixed_size = offsetof(struct qla2300_fw_dump, data_ram); |
1375 | mem_size = (ha->fw_memory_size - 0x11000 + 1) * | |
1376 | sizeof(uint16_t); | |
e428924c | 1377 | } else if (IS_FWI2_CAPABLE(ha)) { |
6246b8a1 GM |
1378 | if (IS_QLA83XX(ha)) |
1379 | fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem); | |
1380 | else if (IS_QLA81XX(ha)) | |
3a03eb79 AV |
1381 | fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem); |
1382 | else if (IS_QLA25XX(ha)) | |
1383 | fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem); | |
1384 | else | |
1385 | fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem); | |
a7a167bf AV |
1386 | mem_size = (ha->fw_memory_size - 0x100000 + 1) * |
1387 | sizeof(uint32_t); | |
050c9bb1 | 1388 | if (ha->mqenable) { |
6246b8a1 GM |
1389 | if (!IS_QLA83XX(ha)) |
1390 | mq_size = sizeof(struct qla2xxx_mq_chain); | |
050c9bb1 GM |
1391 | /* |
1392 | * Allocate maximum buffer size for all queues. | |
1393 | * Resizing must be done at end-of-dump processing. | |
1394 | */ | |
1395 | mq_size += ha->max_req_queues * | |
1396 | (req->length * sizeof(request_t)); | |
1397 | mq_size += ha->max_rsp_queues * | |
1398 | (rsp->length * sizeof(response_t)); | |
1399 | } | |
2d70c103 NB |
1400 | if (ha->tgt.atio_q_length) |
1401 | mq_size += ha->tgt.atio_q_length * sizeof(request_t); | |
df613b96 | 1402 | /* Allocate memory for Fibre Channel Event Buffer. */ |
6246b8a1 | 1403 | if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha)) |
436a7b11 | 1404 | goto try_eft; |
df613b96 AV |
1405 | |
1406 | tc = dma_alloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma, | |
1407 | GFP_KERNEL); | |
1408 | if (!tc) { | |
7c3df132 SK |
1409 | ql_log(ql_log_warn, vha, 0x00be, |
1410 | "Unable to allocate (%d KB) for FCE.\n", | |
1411 | FCE_SIZE / 1024); | |
17d98630 | 1412 | goto try_eft; |
df613b96 AV |
1413 | } |
1414 | ||
1415 | memset(tc, 0, FCE_SIZE); | |
e315cd28 | 1416 | rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS, |
df613b96 AV |
1417 | ha->fce_mb, &ha->fce_bufs); |
1418 | if (rval) { | |
7c3df132 SK |
1419 | ql_log(ql_log_warn, vha, 0x00bf, |
1420 | "Unable to initialize FCE (%d).\n", rval); | |
df613b96 AV |
1421 | dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc, |
1422 | tc_dma); | |
1423 | ha->flags.fce_enabled = 0; | |
17d98630 | 1424 | goto try_eft; |
df613b96 | 1425 | } |
cfb0919c | 1426 | ql_dbg(ql_dbg_init, vha, 0x00c0, |
7c3df132 | 1427 | "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024); |
df613b96 | 1428 | |
7d9dade3 | 1429 | fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE; |
df613b96 AV |
1430 | ha->flags.fce_enabled = 1; |
1431 | ha->fce_dma = tc_dma; | |
1432 | ha->fce = tc; | |
436a7b11 AV |
1433 | try_eft: |
1434 | /* Allocate memory for Extended Trace Buffer. */ | |
1435 | tc = dma_alloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma, | |
1436 | GFP_KERNEL); | |
1437 | if (!tc) { | |
7c3df132 SK |
1438 | ql_log(ql_log_warn, vha, 0x00c1, |
1439 | "Unable to allocate (%d KB) for EFT.\n", | |
1440 | EFT_SIZE / 1024); | |
436a7b11 AV |
1441 | goto cont_alloc; |
1442 | } | |
1443 | ||
1444 | memset(tc, 0, EFT_SIZE); | |
e315cd28 | 1445 | rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS); |
436a7b11 | 1446 | if (rval) { |
7c3df132 SK |
1447 | ql_log(ql_log_warn, vha, 0x00c2, |
1448 | "Unable to initialize EFT (%d).\n", rval); | |
436a7b11 AV |
1449 | dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc, |
1450 | tc_dma); | |
1451 | goto cont_alloc; | |
1452 | } | |
cfb0919c | 1453 | ql_dbg(ql_dbg_init, vha, 0x00c3, |
7c3df132 | 1454 | "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024); |
436a7b11 AV |
1455 | |
1456 | eft_size = EFT_SIZE; | |
1457 | ha->eft_dma = tc_dma; | |
1458 | ha->eft = tc; | |
d4e3e04d | 1459 | } |
a7a167bf | 1460 | cont_alloc: |
73208dfd AC |
1461 | req_q_size = req->length * sizeof(request_t); |
1462 | rsp_q_size = rsp->length * sizeof(response_t); | |
a7a167bf AV |
1463 | |
1464 | dump_size = offsetof(struct qla2xxx_fw_dump, isp); | |
2afa19a9 | 1465 | dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size; |
bb99de67 AV |
1466 | ha->chain_offset = dump_size; |
1467 | dump_size += mq_size + fce_size; | |
d4e3e04d AV |
1468 | |
1469 | ha->fw_dump = vmalloc(dump_size); | |
a7a167bf | 1470 | if (!ha->fw_dump) { |
7c3df132 SK |
1471 | ql_log(ql_log_warn, vha, 0x00c4, |
1472 | "Unable to allocate (%d KB) for firmware dump.\n", | |
1473 | dump_size / 1024); | |
a7a167bf | 1474 | |
e30d1756 MI |
1475 | if (ha->fce) { |
1476 | dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce, | |
1477 | ha->fce_dma); | |
1478 | ha->fce = NULL; | |
1479 | ha->fce_dma = 0; | |
1480 | } | |
1481 | ||
a7a167bf AV |
1482 | if (ha->eft) { |
1483 | dma_free_coherent(&ha->pdev->dev, eft_size, ha->eft, | |
1484 | ha->eft_dma); | |
1485 | ha->eft = NULL; | |
1486 | ha->eft_dma = 0; | |
1487 | } | |
1488 | return; | |
1489 | } | |
cfb0919c | 1490 | ql_dbg(ql_dbg_init, vha, 0x00c5, |
7c3df132 | 1491 | "Allocated (%d KB) for firmware dump.\n", dump_size / 1024); |
a7a167bf AV |
1492 | |
1493 | ha->fw_dump_len = dump_size; | |
1494 | ha->fw_dump->signature[0] = 'Q'; | |
1495 | ha->fw_dump->signature[1] = 'L'; | |
1496 | ha->fw_dump->signature[2] = 'G'; | |
1497 | ha->fw_dump->signature[3] = 'C'; | |
1498 | ha->fw_dump->version = __constant_htonl(1); | |
1499 | ||
1500 | ha->fw_dump->fixed_size = htonl(fixed_size); | |
1501 | ha->fw_dump->mem_size = htonl(mem_size); | |
1502 | ha->fw_dump->req_q_size = htonl(req_q_size); | |
1503 | ha->fw_dump->rsp_q_size = htonl(rsp_q_size); | |
1504 | ||
1505 | ha->fw_dump->eft_size = htonl(eft_size); | |
1506 | ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma)); | |
1507 | ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma)); | |
1508 | ||
1509 | ha->fw_dump->header_size = | |
1510 | htonl(offsetof(struct qla2xxx_fw_dump, isp)); | |
0107109e AV |
1511 | } |
1512 | ||
18e7555a AV |
1513 | static int |
1514 | qla81xx_mpi_sync(scsi_qla_host_t *vha) | |
1515 | { | |
1516 | #define MPS_MASK 0xe0 | |
1517 | int rval; | |
1518 | uint16_t dc; | |
1519 | uint32_t dw; | |
18e7555a AV |
1520 | |
1521 | if (!IS_QLA81XX(vha->hw)) | |
1522 | return QLA_SUCCESS; | |
1523 | ||
1524 | rval = qla2x00_write_ram_word(vha, 0x7c00, 1); | |
1525 | if (rval != QLA_SUCCESS) { | |
7c3df132 SK |
1526 | ql_log(ql_log_warn, vha, 0x0105, |
1527 | "Unable to acquire semaphore.\n"); | |
18e7555a AV |
1528 | goto done; |
1529 | } | |
1530 | ||
1531 | pci_read_config_word(vha->hw->pdev, 0x54, &dc); | |
1532 | rval = qla2x00_read_ram_word(vha, 0x7a15, &dw); | |
1533 | if (rval != QLA_SUCCESS) { | |
7c3df132 | 1534 | ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n"); |
18e7555a AV |
1535 | goto done_release; |
1536 | } | |
1537 | ||
1538 | dc &= MPS_MASK; | |
1539 | if (dc == (dw & MPS_MASK)) | |
1540 | goto done_release; | |
1541 | ||
1542 | dw &= ~MPS_MASK; | |
1543 | dw |= dc; | |
1544 | rval = qla2x00_write_ram_word(vha, 0x7a15, dw); | |
1545 | if (rval != QLA_SUCCESS) { | |
7c3df132 | 1546 | ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n"); |
18e7555a AV |
1547 | } |
1548 | ||
1549 | done_release: | |
1550 | rval = qla2x00_write_ram_word(vha, 0x7c00, 0); | |
1551 | if (rval != QLA_SUCCESS) { | |
7c3df132 SK |
1552 | ql_log(ql_log_warn, vha, 0x006d, |
1553 | "Unable to release semaphore.\n"); | |
18e7555a AV |
1554 | } |
1555 | ||
1556 | done: | |
1557 | return rval; | |
1558 | } | |
1559 | ||
8d93f550 CD |
1560 | int |
1561 | qla2x00_alloc_outstanding_cmds(struct qla_hw_data *ha, struct req_que *req) | |
1562 | { | |
1563 | /* Don't try to reallocate the array */ | |
1564 | if (req->outstanding_cmds) | |
1565 | return QLA_SUCCESS; | |
1566 | ||
1567 | if (!IS_FWI2_CAPABLE(ha) || (ha->mqiobase && | |
1568 | (ql2xmultique_tag || ql2xmaxqueues > 1))) | |
1569 | req->num_outstanding_cmds = DEFAULT_OUTSTANDING_COMMANDS; | |
1570 | else { | |
1571 | if (ha->fw_xcb_count <= ha->fw_iocb_count) | |
1572 | req->num_outstanding_cmds = ha->fw_xcb_count; | |
1573 | else | |
1574 | req->num_outstanding_cmds = ha->fw_iocb_count; | |
1575 | } | |
1576 | ||
1577 | req->outstanding_cmds = kzalloc(sizeof(srb_t *) * | |
1578 | req->num_outstanding_cmds, GFP_KERNEL); | |
1579 | ||
1580 | if (!req->outstanding_cmds) { | |
1581 | /* | |
1582 | * Try to allocate a minimal size just so we can get through | |
1583 | * initialization. | |
1584 | */ | |
1585 | req->num_outstanding_cmds = MIN_OUTSTANDING_COMMANDS; | |
1586 | req->outstanding_cmds = kzalloc(sizeof(srb_t *) * | |
1587 | req->num_outstanding_cmds, GFP_KERNEL); | |
1588 | ||
1589 | if (!req->outstanding_cmds) { | |
1590 | ql_log(ql_log_fatal, NULL, 0x0126, | |
1591 | "Failed to allocate memory for " | |
1592 | "outstanding_cmds for req_que %p.\n", req); | |
1593 | req->num_outstanding_cmds = 0; | |
1594 | return QLA_FUNCTION_FAILED; | |
1595 | } | |
1596 | } | |
1597 | ||
1598 | return QLA_SUCCESS; | |
1599 | } | |
1600 | ||
1da177e4 LT |
1601 | /** |
1602 | * qla2x00_setup_chip() - Load and start RISC firmware. | |
1603 | * @ha: HA context | |
1604 | * | |
1605 | * Returns 0 on success. | |
1606 | */ | |
1607 | static int | |
e315cd28 | 1608 | qla2x00_setup_chip(scsi_qla_host_t *vha) |
1da177e4 | 1609 | { |
0107109e AV |
1610 | int rval; |
1611 | uint32_t srisc_address = 0; | |
e315cd28 | 1612 | struct qla_hw_data *ha = vha->hw; |
3db0652e AV |
1613 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
1614 | unsigned long flags; | |
dda772e8 | 1615 | uint16_t fw_major_version; |
3db0652e | 1616 | |
a9083016 GM |
1617 | if (IS_QLA82XX(ha)) { |
1618 | rval = ha->isp_ops->load_risc(vha, &srisc_address); | |
14e303d9 AV |
1619 | if (rval == QLA_SUCCESS) { |
1620 | qla2x00_stop_firmware(vha); | |
a9083016 | 1621 | goto enable_82xx_npiv; |
14e303d9 | 1622 | } else |
b963752f | 1623 | goto failed; |
a9083016 GM |
1624 | } |
1625 | ||
3db0652e AV |
1626 | if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) { |
1627 | /* Disable SRAM, Instruction RAM and GP RAM parity. */ | |
1628 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1629 | WRT_REG_WORD(®->hccr, (HCCR_ENABLE_PARITY + 0x0)); | |
1630 | RD_REG_WORD(®->hccr); | |
1631 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1632 | } | |
1da177e4 | 1633 | |
18e7555a AV |
1634 | qla81xx_mpi_sync(vha); |
1635 | ||
1da177e4 | 1636 | /* Load firmware sequences */ |
e315cd28 | 1637 | rval = ha->isp_ops->load_risc(vha, &srisc_address); |
0107109e | 1638 | if (rval == QLA_SUCCESS) { |
7c3df132 SK |
1639 | ql_dbg(ql_dbg_init, vha, 0x00c9, |
1640 | "Verifying Checksum of loaded RISC code.\n"); | |
1da177e4 | 1641 | |
e315cd28 | 1642 | rval = qla2x00_verify_checksum(vha, srisc_address); |
1da177e4 LT |
1643 | if (rval == QLA_SUCCESS) { |
1644 | /* Start firmware execution. */ | |
7c3df132 SK |
1645 | ql_dbg(ql_dbg_init, vha, 0x00ca, |
1646 | "Starting firmware.\n"); | |
1da177e4 | 1647 | |
e315cd28 | 1648 | rval = qla2x00_execute_fw(vha, srisc_address); |
1da177e4 | 1649 | /* Retrieve firmware information. */ |
dda772e8 | 1650 | if (rval == QLA_SUCCESS) { |
a9083016 | 1651 | enable_82xx_npiv: |
dda772e8 | 1652 | fw_major_version = ha->fw_major_version; |
3173167f GM |
1653 | if (IS_QLA82XX(ha)) |
1654 | qla82xx_check_md_needed(vha); | |
6246b8a1 GM |
1655 | else |
1656 | rval = qla2x00_get_fw_version(vha); | |
ca9e9c3e AV |
1657 | if (rval != QLA_SUCCESS) |
1658 | goto failed; | |
2c3dfe3f | 1659 | ha->flags.npiv_supported = 0; |
e315cd28 | 1660 | if (IS_QLA2XXX_MIDTYPE(ha) && |
946fb891 | 1661 | (ha->fw_attributes & BIT_2)) { |
2c3dfe3f | 1662 | ha->flags.npiv_supported = 1; |
4d0ea247 SJ |
1663 | if ((!ha->max_npiv_vports) || |
1664 | ((ha->max_npiv_vports + 1) % | |
eb66dc60 | 1665 | MIN_MULTI_ID_FABRIC)) |
4d0ea247 | 1666 | ha->max_npiv_vports = |
eb66dc60 | 1667 | MIN_MULTI_ID_FABRIC - 1; |
4d0ea247 | 1668 | } |
24a08138 | 1669 | qla2x00_get_resource_cnts(vha, NULL, |
8d93f550 | 1670 | &ha->fw_xcb_count, NULL, &ha->fw_iocb_count, |
f3a0a77e | 1671 | &ha->max_npiv_vports, NULL); |
d743de66 | 1672 | |
8d93f550 CD |
1673 | /* |
1674 | * Allocate the array of outstanding commands | |
1675 | * now that we know the firmware resources. | |
1676 | */ | |
1677 | rval = qla2x00_alloc_outstanding_cmds(ha, | |
1678 | vha->req); | |
1679 | if (rval != QLA_SUCCESS) | |
1680 | goto failed; | |
1681 | ||
be5ea3cf SK |
1682 | if (!fw_major_version && ql2xallocfwdump |
1683 | && !IS_QLA82XX(ha)) | |
08de2844 | 1684 | qla2x00_alloc_fw_dump(vha); |
1da177e4 LT |
1685 | } |
1686 | } else { | |
7c3df132 SK |
1687 | ql_log(ql_log_fatal, vha, 0x00cd, |
1688 | "ISP Firmware failed checksum.\n"); | |
1689 | goto failed; | |
1da177e4 | 1690 | } |
c74d88a4 AV |
1691 | } else |
1692 | goto failed; | |
1da177e4 | 1693 | |
3db0652e AV |
1694 | if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) { |
1695 | /* Enable proper parity. */ | |
1696 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1697 | if (IS_QLA2300(ha)) | |
1698 | /* SRAM parity */ | |
1699 | WRT_REG_WORD(®->hccr, HCCR_ENABLE_PARITY + 0x1); | |
1700 | else | |
1701 | /* SRAM, Instruction RAM and GP RAM parity */ | |
1702 | WRT_REG_WORD(®->hccr, HCCR_ENABLE_PARITY + 0x7); | |
1703 | RD_REG_WORD(®->hccr); | |
1704 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1705 | } | |
1706 | ||
6246b8a1 GM |
1707 | if (IS_QLA83XX(ha)) |
1708 | goto skip_fac_check; | |
1709 | ||
1d2874de JC |
1710 | if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) { |
1711 | uint32_t size; | |
1712 | ||
1713 | rval = qla81xx_fac_get_sector_size(vha, &size); | |
1714 | if (rval == QLA_SUCCESS) { | |
1715 | ha->flags.fac_supported = 1; | |
1716 | ha->fdt_block_size = size << 2; | |
1717 | } else { | |
7c3df132 | 1718 | ql_log(ql_log_warn, vha, 0x00ce, |
1d2874de JC |
1719 | "Unsupported FAC firmware (%d.%02d.%02d).\n", |
1720 | ha->fw_major_version, ha->fw_minor_version, | |
1721 | ha->fw_subminor_version); | |
6246b8a1 GM |
1722 | skip_fac_check: |
1723 | if (IS_QLA83XX(ha)) { | |
1724 | ha->flags.fac_supported = 0; | |
1725 | rval = QLA_SUCCESS; | |
1726 | } | |
1d2874de JC |
1727 | } |
1728 | } | |
ca9e9c3e | 1729 | failed: |
1da177e4 | 1730 | if (rval) { |
7c3df132 SK |
1731 | ql_log(ql_log_fatal, vha, 0x00cf, |
1732 | "Setup chip ****FAILED****.\n"); | |
1da177e4 LT |
1733 | } |
1734 | ||
1735 | return (rval); | |
1736 | } | |
1737 | ||
1738 | /** | |
1739 | * qla2x00_init_response_q_entries() - Initializes response queue entries. | |
1740 | * @ha: HA context | |
1741 | * | |
1742 | * Beginning of request ring has initialization control block already built | |
1743 | * by nvram config routine. | |
1744 | * | |
1745 | * Returns 0 on success. | |
1746 | */ | |
73208dfd AC |
1747 | void |
1748 | qla2x00_init_response_q_entries(struct rsp_que *rsp) | |
1da177e4 LT |
1749 | { |
1750 | uint16_t cnt; | |
1751 | response_t *pkt; | |
1752 | ||
2afa19a9 AC |
1753 | rsp->ring_ptr = rsp->ring; |
1754 | rsp->ring_index = 0; | |
1755 | rsp->status_srb = NULL; | |
e315cd28 AC |
1756 | pkt = rsp->ring_ptr; |
1757 | for (cnt = 0; cnt < rsp->length; cnt++) { | |
1da177e4 LT |
1758 | pkt->signature = RESPONSE_PROCESSED; |
1759 | pkt++; | |
1760 | } | |
1da177e4 LT |
1761 | } |
1762 | ||
1763 | /** | |
1764 | * qla2x00_update_fw_options() - Read and process firmware options. | |
1765 | * @ha: HA context | |
1766 | * | |
1767 | * Returns 0 on success. | |
1768 | */ | |
abbd8870 | 1769 | void |
e315cd28 | 1770 | qla2x00_update_fw_options(scsi_qla_host_t *vha) |
1da177e4 LT |
1771 | { |
1772 | uint16_t swing, emphasis, tx_sens, rx_sens; | |
e315cd28 | 1773 | struct qla_hw_data *ha = vha->hw; |
1da177e4 LT |
1774 | |
1775 | memset(ha->fw_options, 0, sizeof(ha->fw_options)); | |
e315cd28 | 1776 | qla2x00_get_fw_options(vha, ha->fw_options); |
1da177e4 LT |
1777 | |
1778 | if (IS_QLA2100(ha) || IS_QLA2200(ha)) | |
1779 | return; | |
1780 | ||
1781 | /* Serial Link options. */ | |
7c3df132 SK |
1782 | ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115, |
1783 | "Serial link options.\n"); | |
1784 | ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109, | |
1785 | (uint8_t *)&ha->fw_seriallink_options, | |
1786 | sizeof(ha->fw_seriallink_options)); | |
1da177e4 LT |
1787 | |
1788 | ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING; | |
1789 | if (ha->fw_seriallink_options[3] & BIT_2) { | |
1790 | ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING; | |
1791 | ||
1792 | /* 1G settings */ | |
1793 | swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0); | |
1794 | emphasis = (ha->fw_seriallink_options[2] & | |
1795 | (BIT_4 | BIT_3)) >> 3; | |
1796 | tx_sens = ha->fw_seriallink_options[0] & | |
fa2a1ce5 | 1797 | (BIT_3 | BIT_2 | BIT_1 | BIT_0); |
1da177e4 LT |
1798 | rx_sens = (ha->fw_seriallink_options[0] & |
1799 | (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4; | |
1800 | ha->fw_options[10] = (emphasis << 14) | (swing << 8); | |
1801 | if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { | |
1802 | if (rx_sens == 0x0) | |
1803 | rx_sens = 0x3; | |
1804 | ha->fw_options[10] |= (tx_sens << 4) | rx_sens; | |
1805 | } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) | |
1806 | ha->fw_options[10] |= BIT_5 | | |
1807 | ((rx_sens & (BIT_1 | BIT_0)) << 2) | | |
1808 | (tx_sens & (BIT_1 | BIT_0)); | |
1809 | ||
1810 | /* 2G settings */ | |
1811 | swing = (ha->fw_seriallink_options[2] & | |
1812 | (BIT_7 | BIT_6 | BIT_5)) >> 5; | |
1813 | emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0); | |
1814 | tx_sens = ha->fw_seriallink_options[1] & | |
fa2a1ce5 | 1815 | (BIT_3 | BIT_2 | BIT_1 | BIT_0); |
1da177e4 LT |
1816 | rx_sens = (ha->fw_seriallink_options[1] & |
1817 | (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4; | |
1818 | ha->fw_options[11] = (emphasis << 14) | (swing << 8); | |
1819 | if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { | |
1820 | if (rx_sens == 0x0) | |
1821 | rx_sens = 0x3; | |
1822 | ha->fw_options[11] |= (tx_sens << 4) | rx_sens; | |
1823 | } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) | |
1824 | ha->fw_options[11] |= BIT_5 | | |
1825 | ((rx_sens & (BIT_1 | BIT_0)) << 2) | | |
1826 | (tx_sens & (BIT_1 | BIT_0)); | |
1827 | } | |
1828 | ||
1829 | /* FCP2 options. */ | |
1830 | /* Return command IOCBs without waiting for an ABTS to complete. */ | |
1831 | ha->fw_options[3] |= BIT_13; | |
1832 | ||
1833 | /* LED scheme. */ | |
1834 | if (ha->flags.enable_led_scheme) | |
1835 | ha->fw_options[2] |= BIT_12; | |
1836 | ||
48c02fde AV |
1837 | /* Detect ISP6312. */ |
1838 | if (IS_QLA6312(ha)) | |
1839 | ha->fw_options[2] |= BIT_13; | |
1840 | ||
1da177e4 | 1841 | /* Update firmware options. */ |
e315cd28 | 1842 | qla2x00_set_fw_options(vha, ha->fw_options); |
1da177e4 LT |
1843 | } |
1844 | ||
0107109e | 1845 | void |
e315cd28 | 1846 | qla24xx_update_fw_options(scsi_qla_host_t *vha) |
0107109e AV |
1847 | { |
1848 | int rval; | |
e315cd28 | 1849 | struct qla_hw_data *ha = vha->hw; |
0107109e | 1850 | |
a9083016 GM |
1851 | if (IS_QLA82XX(ha)) |
1852 | return; | |
1853 | ||
0107109e | 1854 | /* Update Serial Link options. */ |
f94097ed | 1855 | if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0) |
0107109e AV |
1856 | return; |
1857 | ||
e315cd28 | 1858 | rval = qla2x00_set_serdes_params(vha, |
f94097ed AV |
1859 | le16_to_cpu(ha->fw_seriallink_options24[1]), |
1860 | le16_to_cpu(ha->fw_seriallink_options24[2]), | |
1861 | le16_to_cpu(ha->fw_seriallink_options24[3])); | |
0107109e | 1862 | if (rval != QLA_SUCCESS) { |
7c3df132 | 1863 | ql_log(ql_log_warn, vha, 0x0104, |
0107109e AV |
1864 | "Unable to update Serial Link options (%x).\n", rval); |
1865 | } | |
1866 | } | |
1867 | ||
abbd8870 | 1868 | void |
e315cd28 | 1869 | qla2x00_config_rings(struct scsi_qla_host *vha) |
abbd8870 | 1870 | { |
e315cd28 | 1871 | struct qla_hw_data *ha = vha->hw; |
3d71644c | 1872 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
73208dfd AC |
1873 | struct req_que *req = ha->req_q_map[0]; |
1874 | struct rsp_que *rsp = ha->rsp_q_map[0]; | |
abbd8870 AV |
1875 | |
1876 | /* Setup ring parameters in initialization control block. */ | |
1877 | ha->init_cb->request_q_outpointer = __constant_cpu_to_le16(0); | |
1878 | ha->init_cb->response_q_inpointer = __constant_cpu_to_le16(0); | |
e315cd28 AC |
1879 | ha->init_cb->request_q_length = cpu_to_le16(req->length); |
1880 | ha->init_cb->response_q_length = cpu_to_le16(rsp->length); | |
1881 | ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma)); | |
1882 | ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma)); | |
1883 | ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma)); | |
1884 | ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma)); | |
abbd8870 AV |
1885 | |
1886 | WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0); | |
1887 | WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0); | |
1888 | WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0); | |
1889 | WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0); | |
1890 | RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */ | |
1891 | } | |
1892 | ||
0107109e | 1893 | void |
e315cd28 | 1894 | qla24xx_config_rings(struct scsi_qla_host *vha) |
0107109e | 1895 | { |
e315cd28 | 1896 | struct qla_hw_data *ha = vha->hw; |
73208dfd AC |
1897 | device_reg_t __iomem *reg = ISP_QUE_REG(ha, 0); |
1898 | struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp; | |
1899 | struct qla_msix_entry *msix; | |
0107109e | 1900 | struct init_cb_24xx *icb; |
73208dfd AC |
1901 | uint16_t rid = 0; |
1902 | struct req_que *req = ha->req_q_map[0]; | |
1903 | struct rsp_que *rsp = ha->rsp_q_map[0]; | |
0107109e | 1904 | |
6246b8a1 | 1905 | /* Setup ring parameters in initialization control block. */ |
0107109e AV |
1906 | icb = (struct init_cb_24xx *)ha->init_cb; |
1907 | icb->request_q_outpointer = __constant_cpu_to_le16(0); | |
1908 | icb->response_q_inpointer = __constant_cpu_to_le16(0); | |
e315cd28 AC |
1909 | icb->request_q_length = cpu_to_le16(req->length); |
1910 | icb->response_q_length = cpu_to_le16(rsp->length); | |
1911 | icb->request_q_address[0] = cpu_to_le32(LSD(req->dma)); | |
1912 | icb->request_q_address[1] = cpu_to_le32(MSD(req->dma)); | |
1913 | icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma)); | |
1914 | icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma)); | |
0107109e | 1915 | |
2d70c103 NB |
1916 | /* Setup ATIO queue dma pointers for target mode */ |
1917 | icb->atio_q_inpointer = __constant_cpu_to_le16(0); | |
1918 | icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length); | |
1919 | icb->atio_q_address[0] = cpu_to_le32(LSD(ha->tgt.atio_dma)); | |
1920 | icb->atio_q_address[1] = cpu_to_le32(MSD(ha->tgt.atio_dma)); | |
1921 | ||
6246b8a1 | 1922 | if (ha->mqenable || IS_QLA83XX(ha)) { |
73208dfd AC |
1923 | icb->qos = __constant_cpu_to_le16(QLA_DEFAULT_QUE_QOS); |
1924 | icb->rid = __constant_cpu_to_le16(rid); | |
1925 | if (ha->flags.msix_enabled) { | |
1926 | msix = &ha->msix_entries[1]; | |
7c3df132 SK |
1927 | ql_dbg(ql_dbg_init, vha, 0x00fd, |
1928 | "Registering vector 0x%x for base que.\n", | |
1929 | msix->entry); | |
73208dfd AC |
1930 | icb->msix = cpu_to_le16(msix->entry); |
1931 | } | |
1932 | /* Use alternate PCI bus number */ | |
1933 | if (MSB(rid)) | |
1934 | icb->firmware_options_2 |= | |
1935 | __constant_cpu_to_le32(BIT_19); | |
1936 | /* Use alternate PCI devfn */ | |
1937 | if (LSB(rid)) | |
1938 | icb->firmware_options_2 |= | |
1939 | __constant_cpu_to_le32(BIT_18); | |
1940 | ||
3155754a | 1941 | /* Use Disable MSIX Handshake mode for capable adapters */ |
6246b8a1 GM |
1942 | if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) && |
1943 | (ha->flags.msix_enabled)) { | |
3155754a AC |
1944 | icb->firmware_options_2 &= |
1945 | __constant_cpu_to_le32(~BIT_22); | |
1946 | ha->flags.disable_msix_handshake = 1; | |
7c3df132 SK |
1947 | ql_dbg(ql_dbg_init, vha, 0x00fe, |
1948 | "MSIX Handshake Disable Mode turned on.\n"); | |
3155754a AC |
1949 | } else { |
1950 | icb->firmware_options_2 |= | |
1951 | __constant_cpu_to_le32(BIT_22); | |
1952 | } | |
73208dfd | 1953 | icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_23); |
73208dfd AC |
1954 | |
1955 | WRT_REG_DWORD(®->isp25mq.req_q_in, 0); | |
1956 | WRT_REG_DWORD(®->isp25mq.req_q_out, 0); | |
1957 | WRT_REG_DWORD(®->isp25mq.rsp_q_in, 0); | |
1958 | WRT_REG_DWORD(®->isp25mq.rsp_q_out, 0); | |
1959 | } else { | |
1960 | WRT_REG_DWORD(®->isp24.req_q_in, 0); | |
1961 | WRT_REG_DWORD(®->isp24.req_q_out, 0); | |
1962 | WRT_REG_DWORD(®->isp24.rsp_q_in, 0); | |
1963 | WRT_REG_DWORD(®->isp24.rsp_q_out, 0); | |
1964 | } | |
aa230bc5 | 1965 | qlt_24xx_config_rings(vha); |
2d70c103 | 1966 | |
73208dfd AC |
1967 | /* PCI posting */ |
1968 | RD_REG_DWORD(&ioreg->hccr); | |
0107109e AV |
1969 | } |
1970 | ||
1da177e4 LT |
1971 | /** |
1972 | * qla2x00_init_rings() - Initializes firmware. | |
1973 | * @ha: HA context | |
1974 | * | |
1975 | * Beginning of request ring has initialization control block already built | |
1976 | * by nvram config routine. | |
1977 | * | |
1978 | * Returns 0 on success. | |
1979 | */ | |
1980 | static int | |
e315cd28 | 1981 | qla2x00_init_rings(scsi_qla_host_t *vha) |
1da177e4 LT |
1982 | { |
1983 | int rval; | |
1984 | unsigned long flags = 0; | |
29bdccbe | 1985 | int cnt, que; |
e315cd28 | 1986 | struct qla_hw_data *ha = vha->hw; |
29bdccbe AC |
1987 | struct req_que *req; |
1988 | struct rsp_que *rsp; | |
2c3dfe3f SJ |
1989 | struct mid_init_cb_24xx *mid_init_cb = |
1990 | (struct mid_init_cb_24xx *) ha->init_cb; | |
1da177e4 LT |
1991 | |
1992 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1993 | ||
1994 | /* Clear outstanding commands array. */ | |
2afa19a9 | 1995 | for (que = 0; que < ha->max_req_queues; que++) { |
29bdccbe AC |
1996 | req = ha->req_q_map[que]; |
1997 | if (!req) | |
1998 | continue; | |
8d93f550 | 1999 | for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) |
29bdccbe | 2000 | req->outstanding_cmds[cnt] = NULL; |
1da177e4 | 2001 | |
2afa19a9 | 2002 | req->current_outstanding_cmd = 1; |
1da177e4 | 2003 | |
29bdccbe AC |
2004 | /* Initialize firmware. */ |
2005 | req->ring_ptr = req->ring; | |
2006 | req->ring_index = 0; | |
2007 | req->cnt = req->length; | |
2008 | } | |
1da177e4 | 2009 | |
2afa19a9 | 2010 | for (que = 0; que < ha->max_rsp_queues; que++) { |
29bdccbe AC |
2011 | rsp = ha->rsp_q_map[que]; |
2012 | if (!rsp) | |
2013 | continue; | |
29bdccbe AC |
2014 | /* Initialize response queue entries */ |
2015 | qla2x00_init_response_q_entries(rsp); | |
2016 | } | |
1da177e4 | 2017 | |
2d70c103 NB |
2018 | ha->tgt.atio_ring_ptr = ha->tgt.atio_ring; |
2019 | ha->tgt.atio_ring_index = 0; | |
2020 | /* Initialize ATIO queue entries */ | |
2021 | qlt_init_atio_q_entries(vha); | |
2022 | ||
e315cd28 | 2023 | ha->isp_ops->config_rings(vha); |
1da177e4 LT |
2024 | |
2025 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
2026 | ||
2027 | /* Update any ISP specific firmware options before initialization. */ | |
e315cd28 | 2028 | ha->isp_ops->update_fw_options(vha); |
1da177e4 | 2029 | |
7c3df132 | 2030 | ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n"); |
2c3dfe3f | 2031 | |
605aa2bc | 2032 | if (ha->flags.npiv_supported) { |
45980cc2 | 2033 | if (ha->operating_mode == LOOP && !IS_CNA_CAPABLE(ha)) |
605aa2bc | 2034 | ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1; |
c48339de | 2035 | mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports); |
605aa2bc LC |
2036 | } |
2037 | ||
24a08138 AV |
2038 | if (IS_FWI2_CAPABLE(ha)) { |
2039 | mid_init_cb->options = __constant_cpu_to_le16(BIT_1); | |
2040 | mid_init_cb->init_cb.execution_throttle = | |
2041 | cpu_to_le16(ha->fw_xcb_count); | |
2042 | } | |
2c3dfe3f | 2043 | |
e315cd28 | 2044 | rval = qla2x00_init_firmware(vha, ha->init_cb_size); |
1da177e4 | 2045 | if (rval) { |
7c3df132 SK |
2046 | ql_log(ql_log_fatal, vha, 0x00d2, |
2047 | "Init Firmware **** FAILED ****.\n"); | |
1da177e4 | 2048 | } else { |
7c3df132 SK |
2049 | ql_dbg(ql_dbg_init, vha, 0x00d3, |
2050 | "Init Firmware -- success.\n"); | |
1da177e4 LT |
2051 | } |
2052 | ||
2053 | return (rval); | |
2054 | } | |
2055 | ||
2056 | /** | |
2057 | * qla2x00_fw_ready() - Waits for firmware ready. | |
2058 | * @ha: HA context | |
2059 | * | |
2060 | * Returns 0 on success. | |
2061 | */ | |
2062 | static int | |
e315cd28 | 2063 | qla2x00_fw_ready(scsi_qla_host_t *vha) |
1da177e4 LT |
2064 | { |
2065 | int rval; | |
4d4df193 | 2066 | unsigned long wtime, mtime, cs84xx_time; |
1da177e4 LT |
2067 | uint16_t min_wait; /* Minimum wait time if loop is down */ |
2068 | uint16_t wait_time; /* Wait time if loop is coming ready */ | |
656e8912 | 2069 | uint16_t state[5]; |
e315cd28 | 2070 | struct qla_hw_data *ha = vha->hw; |
1da177e4 LT |
2071 | |
2072 | rval = QLA_SUCCESS; | |
2073 | ||
2074 | /* 20 seconds for loop down. */ | |
fa2a1ce5 | 2075 | min_wait = 20; |
1da177e4 LT |
2076 | |
2077 | /* | |
2078 | * Firmware should take at most one RATOV to login, plus 5 seconds for | |
2079 | * our own processing. | |
2080 | */ | |
2081 | if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) { | |
2082 | wait_time = min_wait; | |
2083 | } | |
2084 | ||
2085 | /* Min wait time if loop down */ | |
2086 | mtime = jiffies + (min_wait * HZ); | |
2087 | ||
2088 | /* wait time before firmware ready */ | |
2089 | wtime = jiffies + (wait_time * HZ); | |
2090 | ||
2091 | /* Wait for ISP to finish LIP */ | |
e315cd28 | 2092 | if (!vha->flags.init_done) |
7c3df132 SK |
2093 | ql_log(ql_log_info, vha, 0x801e, |
2094 | "Waiting for LIP to complete.\n"); | |
1da177e4 LT |
2095 | |
2096 | do { | |
5b939038 | 2097 | memset(state, -1, sizeof(state)); |
e315cd28 | 2098 | rval = qla2x00_get_firmware_state(vha, state); |
1da177e4 | 2099 | if (rval == QLA_SUCCESS) { |
4d4df193 | 2100 | if (state[0] < FSTATE_LOSS_OF_SYNC) { |
e315cd28 | 2101 | vha->device_flags &= ~DFLG_NO_CABLE; |
1da177e4 | 2102 | } |
4d4df193 | 2103 | if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) { |
7c3df132 SK |
2104 | ql_dbg(ql_dbg_taskm, vha, 0x801f, |
2105 | "fw_state=%x 84xx=%x.\n", state[0], | |
2106 | state[2]); | |
4d4df193 HK |
2107 | if ((state[2] & FSTATE_LOGGED_IN) && |
2108 | (state[2] & FSTATE_WAITING_FOR_VERIFY)) { | |
7c3df132 SK |
2109 | ql_dbg(ql_dbg_taskm, vha, 0x8028, |
2110 | "Sending verify iocb.\n"); | |
4d4df193 HK |
2111 | |
2112 | cs84xx_time = jiffies; | |
e315cd28 | 2113 | rval = qla84xx_init_chip(vha); |
7c3df132 SK |
2114 | if (rval != QLA_SUCCESS) { |
2115 | ql_log(ql_log_warn, | |
cfb0919c | 2116 | vha, 0x8007, |
7c3df132 | 2117 | "Init chip failed.\n"); |
4d4df193 | 2118 | break; |
7c3df132 | 2119 | } |
4d4df193 HK |
2120 | |
2121 | /* Add time taken to initialize. */ | |
2122 | cs84xx_time = jiffies - cs84xx_time; | |
2123 | wtime += cs84xx_time; | |
2124 | mtime += cs84xx_time; | |
cfb0919c | 2125 | ql_dbg(ql_dbg_taskm, vha, 0x8008, |
7c3df132 SK |
2126 | "Increasing wait time by %ld. " |
2127 | "New time %ld.\n", cs84xx_time, | |
2128 | wtime); | |
4d4df193 HK |
2129 | } |
2130 | } else if (state[0] == FSTATE_READY) { | |
7c3df132 SK |
2131 | ql_dbg(ql_dbg_taskm, vha, 0x8037, |
2132 | "F/W Ready - OK.\n"); | |
1da177e4 | 2133 | |
e315cd28 | 2134 | qla2x00_get_retry_cnt(vha, &ha->retry_count, |
1da177e4 LT |
2135 | &ha->login_timeout, &ha->r_a_tov); |
2136 | ||
2137 | rval = QLA_SUCCESS; | |
2138 | break; | |
2139 | } | |
2140 | ||
2141 | rval = QLA_FUNCTION_FAILED; | |
2142 | ||
e315cd28 | 2143 | if (atomic_read(&vha->loop_down_timer) && |
4d4df193 | 2144 | state[0] != FSTATE_READY) { |
1da177e4 | 2145 | /* Loop down. Timeout on min_wait for states |
fa2a1ce5 AV |
2146 | * other than Wait for Login. |
2147 | */ | |
1da177e4 | 2148 | if (time_after_eq(jiffies, mtime)) { |
7c3df132 | 2149 | ql_log(ql_log_info, vha, 0x8038, |
1da177e4 LT |
2150 | "Cable is unplugged...\n"); |
2151 | ||
e315cd28 | 2152 | vha->device_flags |= DFLG_NO_CABLE; |
1da177e4 LT |
2153 | break; |
2154 | } | |
2155 | } | |
2156 | } else { | |
2157 | /* Mailbox cmd failed. Timeout on min_wait. */ | |
cdbb0a4f | 2158 | if (time_after_eq(jiffies, mtime) || |
7190575f | 2159 | ha->flags.isp82xx_fw_hung) |
1da177e4 LT |
2160 | break; |
2161 | } | |
2162 | ||
2163 | if (time_after_eq(jiffies, wtime)) | |
2164 | break; | |
2165 | ||
2166 | /* Delay for a while */ | |
2167 | msleep(500); | |
1da177e4 LT |
2168 | } while (1); |
2169 | ||
7c3df132 SK |
2170 | ql_dbg(ql_dbg_taskm, vha, 0x803a, |
2171 | "fw_state=%x (%x, %x, %x, %x) " "curr time=%lx.\n", state[0], | |
2172 | state[1], state[2], state[3], state[4], jiffies); | |
1da177e4 | 2173 | |
cfb0919c | 2174 | if (rval && !(vha->device_flags & DFLG_NO_CABLE)) { |
7c3df132 SK |
2175 | ql_log(ql_log_warn, vha, 0x803b, |
2176 | "Firmware ready **** FAILED ****.\n"); | |
1da177e4 LT |
2177 | } |
2178 | ||
2179 | return (rval); | |
2180 | } | |
2181 | ||
2182 | /* | |
2183 | * qla2x00_configure_hba | |
2184 | * Setup adapter context. | |
2185 | * | |
2186 | * Input: | |
2187 | * ha = adapter state pointer. | |
2188 | * | |
2189 | * Returns: | |
2190 | * 0 = success | |
2191 | * | |
2192 | * Context: | |
2193 | * Kernel context. | |
2194 | */ | |
2195 | static int | |
e315cd28 | 2196 | qla2x00_configure_hba(scsi_qla_host_t *vha) |
1da177e4 LT |
2197 | { |
2198 | int rval; | |
2199 | uint16_t loop_id; | |
2200 | uint16_t topo; | |
2c3dfe3f | 2201 | uint16_t sw_cap; |
1da177e4 LT |
2202 | uint8_t al_pa; |
2203 | uint8_t area; | |
2204 | uint8_t domain; | |
2205 | char connect_type[22]; | |
e315cd28 | 2206 | struct qla_hw_data *ha = vha->hw; |
f24b5cb8 | 2207 | unsigned long flags; |
61e1b269 | 2208 | scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); |
1da177e4 LT |
2209 | |
2210 | /* Get host addresses. */ | |
e315cd28 | 2211 | rval = qla2x00_get_adapter_id(vha, |
2c3dfe3f | 2212 | &loop_id, &al_pa, &area, &domain, &topo, &sw_cap); |
1da177e4 | 2213 | if (rval != QLA_SUCCESS) { |
e315cd28 | 2214 | if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) || |
6246b8a1 | 2215 | IS_CNA_CAPABLE(ha) || |
33135aa2 | 2216 | (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) { |
7c3df132 SK |
2217 | ql_dbg(ql_dbg_disc, vha, 0x2008, |
2218 | "Loop is in a transition state.\n"); | |
33135aa2 | 2219 | } else { |
7c3df132 SK |
2220 | ql_log(ql_log_warn, vha, 0x2009, |
2221 | "Unable to get host loop ID.\n"); | |
61e1b269 JC |
2222 | if (IS_FWI2_CAPABLE(ha) && (vha == base_vha) && |
2223 | (rval == QLA_COMMAND_ERROR && loop_id == 0x1b)) { | |
2224 | ql_log(ql_log_warn, vha, 0x1151, | |
2225 | "Doing link init.\n"); | |
2226 | if (qla24xx_link_initialize(vha) == QLA_SUCCESS) | |
2227 | return rval; | |
2228 | } | |
e315cd28 | 2229 | set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); |
33135aa2 | 2230 | } |
1da177e4 LT |
2231 | return (rval); |
2232 | } | |
2233 | ||
2234 | if (topo == 4) { | |
7c3df132 SK |
2235 | ql_log(ql_log_info, vha, 0x200a, |
2236 | "Cannot get topology - retrying.\n"); | |
1da177e4 LT |
2237 | return (QLA_FUNCTION_FAILED); |
2238 | } | |
2239 | ||
e315cd28 | 2240 | vha->loop_id = loop_id; |
1da177e4 LT |
2241 | |
2242 | /* initialize */ | |
2243 | ha->min_external_loopid = SNS_FIRST_LOOP_ID; | |
2244 | ha->operating_mode = LOOP; | |
2c3dfe3f | 2245 | ha->switch_cap = 0; |
1da177e4 LT |
2246 | |
2247 | switch (topo) { | |
2248 | case 0: | |
7c3df132 | 2249 | ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n"); |
1da177e4 LT |
2250 | ha->current_topology = ISP_CFG_NL; |
2251 | strcpy(connect_type, "(Loop)"); | |
2252 | break; | |
2253 | ||
2254 | case 1: | |
7c3df132 | 2255 | ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n"); |
2c3dfe3f | 2256 | ha->switch_cap = sw_cap; |
1da177e4 LT |
2257 | ha->current_topology = ISP_CFG_FL; |
2258 | strcpy(connect_type, "(FL_Port)"); | |
2259 | break; | |
2260 | ||
2261 | case 2: | |
7c3df132 | 2262 | ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n"); |
1da177e4 LT |
2263 | ha->operating_mode = P2P; |
2264 | ha->current_topology = ISP_CFG_N; | |
2265 | strcpy(connect_type, "(N_Port-to-N_Port)"); | |
2266 | break; | |
2267 | ||
2268 | case 3: | |
7c3df132 | 2269 | ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n"); |
2c3dfe3f | 2270 | ha->switch_cap = sw_cap; |
1da177e4 LT |
2271 | ha->operating_mode = P2P; |
2272 | ha->current_topology = ISP_CFG_F; | |
2273 | strcpy(connect_type, "(F_Port)"); | |
2274 | break; | |
2275 | ||
2276 | default: | |
7c3df132 SK |
2277 | ql_dbg(ql_dbg_disc, vha, 0x200f, |
2278 | "HBA in unknown topology %x, using NL.\n", topo); | |
1da177e4 LT |
2279 | ha->current_topology = ISP_CFG_NL; |
2280 | strcpy(connect_type, "(Loop)"); | |
2281 | break; | |
2282 | } | |
2283 | ||
2284 | /* Save Host port and loop ID. */ | |
2285 | /* byte order - Big Endian */ | |
e315cd28 AC |
2286 | vha->d_id.b.domain = domain; |
2287 | vha->d_id.b.area = area; | |
2288 | vha->d_id.b.al_pa = al_pa; | |
1da177e4 | 2289 | |
f24b5cb8 | 2290 | spin_lock_irqsave(&ha->vport_slock, flags); |
2d70c103 | 2291 | qlt_update_vp_map(vha, SET_AL_PA); |
f24b5cb8 | 2292 | spin_unlock_irqrestore(&ha->vport_slock, flags); |
2d70c103 | 2293 | |
e315cd28 | 2294 | if (!vha->flags.init_done) |
7c3df132 SK |
2295 | ql_log(ql_log_info, vha, 0x2010, |
2296 | "Topology - %s, Host Loop address 0x%x.\n", | |
e315cd28 | 2297 | connect_type, vha->loop_id); |
1da177e4 LT |
2298 | |
2299 | if (rval) { | |
7c3df132 SK |
2300 | ql_log(ql_log_warn, vha, 0x2011, |
2301 | "%s FAILED\n", __func__); | |
1da177e4 | 2302 | } else { |
7c3df132 SK |
2303 | ql_dbg(ql_dbg_disc, vha, 0x2012, |
2304 | "%s success\n", __func__); | |
1da177e4 LT |
2305 | } |
2306 | ||
2307 | return(rval); | |
2308 | } | |
2309 | ||
a9083016 | 2310 | inline void |
e315cd28 AC |
2311 | qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len, |
2312 | char *def) | |
9bb9fcf2 AV |
2313 | { |
2314 | char *st, *en; | |
2315 | uint16_t index; | |
e315cd28 | 2316 | struct qla_hw_data *ha = vha->hw; |
ab671149 | 2317 | int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && |
6246b8a1 | 2318 | !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha); |
9bb9fcf2 AV |
2319 | |
2320 | if (memcmp(model, BINZERO, len) != 0) { | |
2321 | strncpy(ha->model_number, model, len); | |
2322 | st = en = ha->model_number; | |
2323 | en += len - 1; | |
2324 | while (en > st) { | |
2325 | if (*en != 0x20 && *en != 0x00) | |
2326 | break; | |
2327 | *en-- = '\0'; | |
2328 | } | |
2329 | ||
2330 | index = (ha->pdev->subsystem_device & 0xff); | |
7d0dba17 AV |
2331 | if (use_tbl && |
2332 | ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC && | |
9bb9fcf2 | 2333 | index < QLA_MODEL_NAMES) |
1ee27146 JC |
2334 | strncpy(ha->model_desc, |
2335 | qla2x00_model_name[index * 2 + 1], | |
2336 | sizeof(ha->model_desc) - 1); | |
9bb9fcf2 AV |
2337 | } else { |
2338 | index = (ha->pdev->subsystem_device & 0xff); | |
7d0dba17 AV |
2339 | if (use_tbl && |
2340 | ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC && | |
9bb9fcf2 AV |
2341 | index < QLA_MODEL_NAMES) { |
2342 | strcpy(ha->model_number, | |
2343 | qla2x00_model_name[index * 2]); | |
1ee27146 JC |
2344 | strncpy(ha->model_desc, |
2345 | qla2x00_model_name[index * 2 + 1], | |
2346 | sizeof(ha->model_desc) - 1); | |
9bb9fcf2 AV |
2347 | } else { |
2348 | strcpy(ha->model_number, def); | |
2349 | } | |
2350 | } | |
1ee27146 | 2351 | if (IS_FWI2_CAPABLE(ha)) |
e315cd28 | 2352 | qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc, |
1ee27146 | 2353 | sizeof(ha->model_desc)); |
9bb9fcf2 AV |
2354 | } |
2355 | ||
4e08df3f DM |
2356 | /* On sparc systems, obtain port and node WWN from firmware |
2357 | * properties. | |
2358 | */ | |
e315cd28 | 2359 | static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv) |
4e08df3f DM |
2360 | { |
2361 | #ifdef CONFIG_SPARC | |
e315cd28 | 2362 | struct qla_hw_data *ha = vha->hw; |
4e08df3f | 2363 | struct pci_dev *pdev = ha->pdev; |
15576bc8 DM |
2364 | struct device_node *dp = pci_device_to_OF_node(pdev); |
2365 | const u8 *val; | |
4e08df3f DM |
2366 | int len; |
2367 | ||
2368 | val = of_get_property(dp, "port-wwn", &len); | |
2369 | if (val && len >= WWN_SIZE) | |
2370 | memcpy(nv->port_name, val, WWN_SIZE); | |
2371 | ||
2372 | val = of_get_property(dp, "node-wwn", &len); | |
2373 | if (val && len >= WWN_SIZE) | |
2374 | memcpy(nv->node_name, val, WWN_SIZE); | |
2375 | #endif | |
2376 | } | |
2377 | ||
1da177e4 LT |
2378 | /* |
2379 | * NVRAM configuration for ISP 2xxx | |
2380 | * | |
2381 | * Input: | |
2382 | * ha = adapter block pointer. | |
2383 | * | |
2384 | * Output: | |
2385 | * initialization control block in response_ring | |
2386 | * host adapters parameters in host adapter block | |
2387 | * | |
2388 | * Returns: | |
2389 | * 0 = success. | |
2390 | */ | |
abbd8870 | 2391 | int |
e315cd28 | 2392 | qla2x00_nvram_config(scsi_qla_host_t *vha) |
1da177e4 | 2393 | { |
4e08df3f | 2394 | int rval; |
0107109e AV |
2395 | uint8_t chksum = 0; |
2396 | uint16_t cnt; | |
2397 | uint8_t *dptr1, *dptr2; | |
e315cd28 | 2398 | struct qla_hw_data *ha = vha->hw; |
0107109e | 2399 | init_cb_t *icb = ha->init_cb; |
281afe19 SJ |
2400 | nvram_t *nv = ha->nvram; |
2401 | uint8_t *ptr = ha->nvram; | |
3d71644c | 2402 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
1da177e4 | 2403 | |
4e08df3f DM |
2404 | rval = QLA_SUCCESS; |
2405 | ||
1da177e4 | 2406 | /* Determine NVRAM starting address. */ |
0107109e | 2407 | ha->nvram_size = sizeof(nvram_t); |
1da177e4 LT |
2408 | ha->nvram_base = 0; |
2409 | if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) | |
2410 | if ((RD_REG_WORD(®->ctrl_status) >> 14) == 1) | |
2411 | ha->nvram_base = 0x80; | |
2412 | ||
2413 | /* Get NVRAM data and calculate checksum. */ | |
e315cd28 | 2414 | ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size); |
0107109e AV |
2415 | for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++) |
2416 | chksum += *ptr++; | |
1da177e4 | 2417 | |
7c3df132 SK |
2418 | ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f, |
2419 | "Contents of NVRAM.\n"); | |
2420 | ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110, | |
2421 | (uint8_t *)nv, ha->nvram_size); | |
1da177e4 LT |
2422 | |
2423 | /* Bad NVRAM data, set defaults parameters. */ | |
2424 | if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || | |
2425 | nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) { | |
2426 | /* Reset NVRAM data. */ | |
7c3df132 | 2427 | ql_log(ql_log_warn, vha, 0x0064, |
9e336520 | 2428 | "Inconsistent NVRAM " |
7c3df132 SK |
2429 | "detected: checksum=0x%x id=%c version=0x%x.\n", |
2430 | chksum, nv->id[0], nv->nvram_version); | |
2431 | ql_log(ql_log_warn, vha, 0x0065, | |
2432 | "Falling back to " | |
2433 | "functioning (yet invalid -- WWPN) defaults.\n"); | |
4e08df3f DM |
2434 | |
2435 | /* | |
2436 | * Set default initialization control block. | |
2437 | */ | |
2438 | memset(nv, 0, ha->nvram_size); | |
2439 | nv->parameter_block_version = ICB_VERSION; | |
2440 | ||
2441 | if (IS_QLA23XX(ha)) { | |
2442 | nv->firmware_options[0] = BIT_2 | BIT_1; | |
2443 | nv->firmware_options[1] = BIT_7 | BIT_5; | |
2444 | nv->add_firmware_options[0] = BIT_5; | |
2445 | nv->add_firmware_options[1] = BIT_5 | BIT_4; | |
2446 | nv->frame_payload_size = __constant_cpu_to_le16(2048); | |
2447 | nv->special_options[1] = BIT_7; | |
2448 | } else if (IS_QLA2200(ha)) { | |
2449 | nv->firmware_options[0] = BIT_2 | BIT_1; | |
2450 | nv->firmware_options[1] = BIT_7 | BIT_5; | |
2451 | nv->add_firmware_options[0] = BIT_5; | |
2452 | nv->add_firmware_options[1] = BIT_5 | BIT_4; | |
2453 | nv->frame_payload_size = __constant_cpu_to_le16(1024); | |
2454 | } else if (IS_QLA2100(ha)) { | |
2455 | nv->firmware_options[0] = BIT_3 | BIT_1; | |
2456 | nv->firmware_options[1] = BIT_5; | |
2457 | nv->frame_payload_size = __constant_cpu_to_le16(1024); | |
2458 | } | |
2459 | ||
2460 | nv->max_iocb_allocation = __constant_cpu_to_le16(256); | |
2461 | nv->execution_throttle = __constant_cpu_to_le16(16); | |
2462 | nv->retry_count = 8; | |
2463 | nv->retry_delay = 1; | |
2464 | ||
2465 | nv->port_name[0] = 33; | |
2466 | nv->port_name[3] = 224; | |
2467 | nv->port_name[4] = 139; | |
2468 | ||
e315cd28 | 2469 | qla2xxx_nvram_wwn_from_ofw(vha, nv); |
4e08df3f DM |
2470 | |
2471 | nv->login_timeout = 4; | |
2472 | ||
2473 | /* | |
2474 | * Set default host adapter parameters | |
2475 | */ | |
2476 | nv->host_p[1] = BIT_2; | |
2477 | nv->reset_delay = 5; | |
2478 | nv->port_down_retry_count = 8; | |
2479 | nv->max_luns_per_target = __constant_cpu_to_le16(8); | |
2480 | nv->link_down_timeout = 60; | |
2481 | ||
2482 | rval = 1; | |
1da177e4 LT |
2483 | } |
2484 | ||
2485 | #if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2) | |
2486 | /* | |
2487 | * The SN2 does not provide BIOS emulation which means you can't change | |
2488 | * potentially bogus BIOS settings. Force the use of default settings | |
2489 | * for link rate and frame size. Hope that the rest of the settings | |
2490 | * are valid. | |
2491 | */ | |
2492 | if (ia64_platform_is("sn2")) { | |
2493 | nv->frame_payload_size = __constant_cpu_to_le16(2048); | |
2494 | if (IS_QLA23XX(ha)) | |
2495 | nv->special_options[1] = BIT_7; | |
2496 | } | |
2497 | #endif | |
2498 | ||
2499 | /* Reset Initialization control block */ | |
0107109e | 2500 | memset(icb, 0, ha->init_cb_size); |
1da177e4 LT |
2501 | |
2502 | /* | |
2503 | * Setup driver NVRAM options. | |
2504 | */ | |
2505 | nv->firmware_options[0] |= (BIT_6 | BIT_1); | |
2506 | nv->firmware_options[0] &= ~(BIT_5 | BIT_4); | |
2507 | nv->firmware_options[1] |= (BIT_5 | BIT_0); | |
2508 | nv->firmware_options[1] &= ~BIT_4; | |
2509 | ||
2510 | if (IS_QLA23XX(ha)) { | |
2511 | nv->firmware_options[0] |= BIT_2; | |
2512 | nv->firmware_options[0] &= ~BIT_3; | |
2d70c103 | 2513 | nv->special_options[0] &= ~BIT_6; |
0107109e | 2514 | nv->add_firmware_options[1] |= BIT_5 | BIT_4; |
1da177e4 LT |
2515 | |
2516 | if (IS_QLA2300(ha)) { | |
2517 | if (ha->fb_rev == FPM_2310) { | |
2518 | strcpy(ha->model_number, "QLA2310"); | |
2519 | } else { | |
2520 | strcpy(ha->model_number, "QLA2300"); | |
2521 | } | |
2522 | } else { | |
e315cd28 | 2523 | qla2x00_set_model_info(vha, nv->model_number, |
9bb9fcf2 | 2524 | sizeof(nv->model_number), "QLA23xx"); |
1da177e4 LT |
2525 | } |
2526 | } else if (IS_QLA2200(ha)) { | |
2527 | nv->firmware_options[0] |= BIT_2; | |
2528 | /* | |
2529 | * 'Point-to-point preferred, else loop' is not a safe | |
2530 | * connection mode setting. | |
2531 | */ | |
2532 | if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) == | |
2533 | (BIT_5 | BIT_4)) { | |
2534 | /* Force 'loop preferred, else point-to-point'. */ | |
2535 | nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4); | |
2536 | nv->add_firmware_options[0] |= BIT_5; | |
2537 | } | |
2538 | strcpy(ha->model_number, "QLA22xx"); | |
2539 | } else /*if (IS_QLA2100(ha))*/ { | |
2540 | strcpy(ha->model_number, "QLA2100"); | |
2541 | } | |
2542 | ||
2543 | /* | |
2544 | * Copy over NVRAM RISC parameter block to initialization control block. | |
2545 | */ | |
2546 | dptr1 = (uint8_t *)icb; | |
2547 | dptr2 = (uint8_t *)&nv->parameter_block_version; | |
2548 | cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version; | |
2549 | while (cnt--) | |
2550 | *dptr1++ = *dptr2++; | |
2551 | ||
2552 | /* Copy 2nd half. */ | |
2553 | dptr1 = (uint8_t *)icb->add_firmware_options; | |
2554 | cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options; | |
2555 | while (cnt--) | |
2556 | *dptr1++ = *dptr2++; | |
2557 | ||
5341e868 AV |
2558 | /* Use alternate WWN? */ |
2559 | if (nv->host_p[1] & BIT_7) { | |
2560 | memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE); | |
2561 | memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE); | |
2562 | } | |
2563 | ||
1da177e4 LT |
2564 | /* Prepare nodename */ |
2565 | if ((icb->firmware_options[1] & BIT_6) == 0) { | |
2566 | /* | |
2567 | * Firmware will apply the following mask if the nodename was | |
2568 | * not provided. | |
2569 | */ | |
2570 | memcpy(icb->node_name, icb->port_name, WWN_SIZE); | |
2571 | icb->node_name[0] &= 0xF0; | |
2572 | } | |
2573 | ||
2574 | /* | |
2575 | * Set host adapter parameters. | |
2576 | */ | |
3ce8866c SK |
2577 | |
2578 | /* | |
2579 | * BIT_7 in the host-parameters section allows for modification to | |
2580 | * internal driver logging. | |
2581 | */ | |
0181944f | 2582 | if (nv->host_p[0] & BIT_7) |
cfb0919c | 2583 | ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK; |
1da177e4 LT |
2584 | ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0); |
2585 | /* Always load RISC code on non ISP2[12]00 chips. */ | |
2586 | if (!IS_QLA2100(ha) && !IS_QLA2200(ha)) | |
2587 | ha->flags.disable_risc_code_load = 0; | |
2588 | ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0); | |
2589 | ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0); | |
2590 | ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0); | |
06c22bd1 | 2591 | ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0; |
d4c760c2 | 2592 | ha->flags.disable_serdes = 0; |
1da177e4 LT |
2593 | |
2594 | ha->operating_mode = | |
2595 | (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4; | |
2596 | ||
2597 | memcpy(ha->fw_seriallink_options, nv->seriallink_options, | |
2598 | sizeof(ha->fw_seriallink_options)); | |
2599 | ||
2600 | /* save HBA serial number */ | |
2601 | ha->serial0 = icb->port_name[5]; | |
2602 | ha->serial1 = icb->port_name[6]; | |
2603 | ha->serial2 = icb->port_name[7]; | |
e315cd28 AC |
2604 | memcpy(vha->node_name, icb->node_name, WWN_SIZE); |
2605 | memcpy(vha->port_name, icb->port_name, WWN_SIZE); | |
1da177e4 LT |
2606 | |
2607 | icb->execution_throttle = __constant_cpu_to_le16(0xFFFF); | |
2608 | ||
2609 | ha->retry_count = nv->retry_count; | |
2610 | ||
2611 | /* Set minimum login_timeout to 4 seconds. */ | |
5b91490e | 2612 | if (nv->login_timeout != ql2xlogintimeout) |
1da177e4 LT |
2613 | nv->login_timeout = ql2xlogintimeout; |
2614 | if (nv->login_timeout < 4) | |
2615 | nv->login_timeout = 4; | |
2616 | ha->login_timeout = nv->login_timeout; | |
2617 | icb->login_timeout = nv->login_timeout; | |
2618 | ||
00a537b8 AV |
2619 | /* Set minimum RATOV to 100 tenths of a second. */ |
2620 | ha->r_a_tov = 100; | |
1da177e4 | 2621 | |
1da177e4 LT |
2622 | ha->loop_reset_delay = nv->reset_delay; |
2623 | ||
1da177e4 LT |
2624 | /* Link Down Timeout = 0: |
2625 | * | |
2626 | * When Port Down timer expires we will start returning | |
2627 | * I/O's to OS with "DID_NO_CONNECT". | |
2628 | * | |
2629 | * Link Down Timeout != 0: | |
2630 | * | |
2631 | * The driver waits for the link to come up after link down | |
2632 | * before returning I/Os to OS with "DID_NO_CONNECT". | |
fa2a1ce5 | 2633 | */ |
1da177e4 LT |
2634 | if (nv->link_down_timeout == 0) { |
2635 | ha->loop_down_abort_time = | |
354d6b21 | 2636 | (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT); |
1da177e4 LT |
2637 | } else { |
2638 | ha->link_down_timeout = nv->link_down_timeout; | |
2639 | ha->loop_down_abort_time = | |
2640 | (LOOP_DOWN_TIME - ha->link_down_timeout); | |
fa2a1ce5 | 2641 | } |
1da177e4 | 2642 | |
1da177e4 LT |
2643 | /* |
2644 | * Need enough time to try and get the port back. | |
2645 | */ | |
2646 | ha->port_down_retry_count = nv->port_down_retry_count; | |
2647 | if (qlport_down_retry) | |
2648 | ha->port_down_retry_count = qlport_down_retry; | |
2649 | /* Set login_retry_count */ | |
2650 | ha->login_retry_count = nv->retry_count; | |
2651 | if (ha->port_down_retry_count == nv->port_down_retry_count && | |
2652 | ha->port_down_retry_count > 3) | |
2653 | ha->login_retry_count = ha->port_down_retry_count; | |
2654 | else if (ha->port_down_retry_count > (int)ha->login_retry_count) | |
2655 | ha->login_retry_count = ha->port_down_retry_count; | |
2656 | if (ql2xloginretrycount) | |
2657 | ha->login_retry_count = ql2xloginretrycount; | |
2658 | ||
1da177e4 LT |
2659 | icb->lun_enables = __constant_cpu_to_le16(0); |
2660 | icb->command_resource_count = 0; | |
2661 | icb->immediate_notify_resource_count = 0; | |
2662 | icb->timeout = __constant_cpu_to_le16(0); | |
2663 | ||
2664 | if (IS_QLA2100(ha) || IS_QLA2200(ha)) { | |
2665 | /* Enable RIO */ | |
2666 | icb->firmware_options[0] &= ~BIT_3; | |
2667 | icb->add_firmware_options[0] &= | |
2668 | ~(BIT_3 | BIT_2 | BIT_1 | BIT_0); | |
2669 | icb->add_firmware_options[0] |= BIT_2; | |
2670 | icb->response_accumulation_timer = 3; | |
2671 | icb->interrupt_delay_timer = 5; | |
2672 | ||
e315cd28 | 2673 | vha->flags.process_response_queue = 1; |
1da177e4 | 2674 | } else { |
4fdfefe5 | 2675 | /* Enable ZIO. */ |
e315cd28 | 2676 | if (!vha->flags.init_done) { |
4fdfefe5 AV |
2677 | ha->zio_mode = icb->add_firmware_options[0] & |
2678 | (BIT_3 | BIT_2 | BIT_1 | BIT_0); | |
2679 | ha->zio_timer = icb->interrupt_delay_timer ? | |
2680 | icb->interrupt_delay_timer: 2; | |
2681 | } | |
1da177e4 LT |
2682 | icb->add_firmware_options[0] &= |
2683 | ~(BIT_3 | BIT_2 | BIT_1 | BIT_0); | |
e315cd28 | 2684 | vha->flags.process_response_queue = 0; |
4fdfefe5 | 2685 | if (ha->zio_mode != QLA_ZIO_DISABLED) { |
4a59f71d AV |
2686 | ha->zio_mode = QLA_ZIO_MODE_6; |
2687 | ||
7c3df132 | 2688 | ql_log(ql_log_info, vha, 0x0068, |
4fdfefe5 AV |
2689 | "ZIO mode %d enabled; timer delay (%d us).\n", |
2690 | ha->zio_mode, ha->zio_timer * 100); | |
1da177e4 | 2691 | |
4fdfefe5 AV |
2692 | icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode; |
2693 | icb->interrupt_delay_timer = (uint8_t)ha->zio_timer; | |
e315cd28 | 2694 | vha->flags.process_response_queue = 1; |
1da177e4 LT |
2695 | } |
2696 | } | |
2697 | ||
4e08df3f | 2698 | if (rval) { |
7c3df132 SK |
2699 | ql_log(ql_log_warn, vha, 0x0069, |
2700 | "NVRAM configuration failed.\n"); | |
4e08df3f DM |
2701 | } |
2702 | return (rval); | |
1da177e4 LT |
2703 | } |
2704 | ||
19a7b4ae JSEC |
2705 | static void |
2706 | qla2x00_rport_del(void *data) | |
2707 | { | |
2708 | fc_port_t *fcport = data; | |
d97994dc | 2709 | struct fc_rport *rport; |
2d70c103 | 2710 | scsi_qla_host_t *vha = fcport->vha; |
044d78e1 | 2711 | unsigned long flags; |
d97994dc | 2712 | |
044d78e1 | 2713 | spin_lock_irqsave(fcport->vha->host->host_lock, flags); |
ac280b67 | 2714 | rport = fcport->drport ? fcport->drport: fcport->rport; |
d97994dc | 2715 | fcport->drport = NULL; |
044d78e1 | 2716 | spin_unlock_irqrestore(fcport->vha->host->host_lock, flags); |
2d70c103 | 2717 | if (rport) { |
d97994dc | 2718 | fc_remote_port_delete(rport); |
2d70c103 NB |
2719 | /* |
2720 | * Release the target mode FC NEXUS in qla_target.c code | |
2721 | * if target mod is enabled. | |
2722 | */ | |
2723 | qlt_fc_port_deleted(vha, fcport); | |
2724 | } | |
19a7b4ae JSEC |
2725 | } |
2726 | ||
1da177e4 LT |
2727 | /** |
2728 | * qla2x00_alloc_fcport() - Allocate a generic fcport. | |
2729 | * @ha: HA context | |
2730 | * @flags: allocation flags | |
2731 | * | |
2732 | * Returns a pointer to the allocated fcport, or NULL, if none available. | |
2733 | */ | |
9a069e19 | 2734 | fc_port_t * |
e315cd28 | 2735 | qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags) |
1da177e4 LT |
2736 | { |
2737 | fc_port_t *fcport; | |
2738 | ||
bbfbbbc1 MK |
2739 | fcport = kzalloc(sizeof(fc_port_t), flags); |
2740 | if (!fcport) | |
2741 | return NULL; | |
1da177e4 LT |
2742 | |
2743 | /* Setup fcport template structure. */ | |
e315cd28 | 2744 | fcport->vha = vha; |
1da177e4 LT |
2745 | fcport->port_type = FCT_UNKNOWN; |
2746 | fcport->loop_id = FC_NO_LOOP_ID; | |
ec426e10 | 2747 | qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED); |
ad3e0eda | 2748 | fcport->supported_classes = FC_COS_UNSPECIFIED; |
c0822b63 | 2749 | fcport->scan_state = QLA_FCPORT_SCAN_NONE; |
1da177e4 | 2750 | |
bbfbbbc1 | 2751 | return fcport; |
1da177e4 LT |
2752 | } |
2753 | ||
2754 | /* | |
2755 | * qla2x00_configure_loop | |
2756 | * Updates Fibre Channel Device Database with what is actually on loop. | |
2757 | * | |
2758 | * Input: | |
2759 | * ha = adapter block pointer. | |
2760 | * | |
2761 | * Returns: | |
2762 | * 0 = success. | |
2763 | * 1 = error. | |
2764 | * 2 = database was full and device was not configured. | |
2765 | */ | |
2766 | static int | |
e315cd28 | 2767 | qla2x00_configure_loop(scsi_qla_host_t *vha) |
1da177e4 LT |
2768 | { |
2769 | int rval; | |
2770 | unsigned long flags, save_flags; | |
e315cd28 | 2771 | struct qla_hw_data *ha = vha->hw; |
1da177e4 LT |
2772 | rval = QLA_SUCCESS; |
2773 | ||
2774 | /* Get Initiator ID */ | |
e315cd28 AC |
2775 | if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) { |
2776 | rval = qla2x00_configure_hba(vha); | |
1da177e4 | 2777 | if (rval != QLA_SUCCESS) { |
7c3df132 SK |
2778 | ql_dbg(ql_dbg_disc, vha, 0x2013, |
2779 | "Unable to configure HBA.\n"); | |
1da177e4 LT |
2780 | return (rval); |
2781 | } | |
2782 | } | |
2783 | ||
e315cd28 | 2784 | save_flags = flags = vha->dpc_flags; |
7c3df132 SK |
2785 | ql_dbg(ql_dbg_disc, vha, 0x2014, |
2786 | "Configure loop -- dpc flags = 0x%lx.\n", flags); | |
1da177e4 LT |
2787 | |
2788 | /* | |
2789 | * If we have both an RSCN and PORT UPDATE pending then handle them | |
2790 | * both at the same time. | |
2791 | */ | |
e315cd28 AC |
2792 | clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); |
2793 | clear_bit(RSCN_UPDATE, &vha->dpc_flags); | |
1da177e4 | 2794 | |
3064ff39 MH |
2795 | qla2x00_get_data_rate(vha); |
2796 | ||
1da177e4 LT |
2797 | /* Determine what we need to do */ |
2798 | if (ha->current_topology == ISP_CFG_FL && | |
2799 | (test_bit(LOCAL_LOOP_UPDATE, &flags))) { | |
2800 | ||
1da177e4 LT |
2801 | set_bit(RSCN_UPDATE, &flags); |
2802 | ||
2803 | } else if (ha->current_topology == ISP_CFG_F && | |
2804 | (test_bit(LOCAL_LOOP_UPDATE, &flags))) { | |
2805 | ||
1da177e4 LT |
2806 | set_bit(RSCN_UPDATE, &flags); |
2807 | clear_bit(LOCAL_LOOP_UPDATE, &flags); | |
21333b48 AV |
2808 | |
2809 | } else if (ha->current_topology == ISP_CFG_N) { | |
2810 | clear_bit(RSCN_UPDATE, &flags); | |
1da177e4 | 2811 | |
e315cd28 | 2812 | } else if (!vha->flags.online || |
1da177e4 LT |
2813 | (test_bit(ABORT_ISP_ACTIVE, &flags))) { |
2814 | ||
1da177e4 LT |
2815 | set_bit(RSCN_UPDATE, &flags); |
2816 | set_bit(LOCAL_LOOP_UPDATE, &flags); | |
2817 | } | |
2818 | ||
2819 | if (test_bit(LOCAL_LOOP_UPDATE, &flags)) { | |
7c3df132 SK |
2820 | if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) { |
2821 | ql_dbg(ql_dbg_disc, vha, 0x2015, | |
2822 | "Loop resync needed, failing.\n"); | |
1da177e4 | 2823 | rval = QLA_FUNCTION_FAILED; |
642ef983 | 2824 | } else |
e315cd28 | 2825 | rval = qla2x00_configure_local_loop(vha); |
1da177e4 LT |
2826 | } |
2827 | ||
2828 | if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) { | |
7c3df132 SK |
2829 | if (LOOP_TRANSITION(vha)) { |
2830 | ql_dbg(ql_dbg_disc, vha, 0x201e, | |
2831 | "Needs RSCN update and loop transition.\n"); | |
1da177e4 | 2832 | rval = QLA_FUNCTION_FAILED; |
7c3df132 | 2833 | } |
e315cd28 AC |
2834 | else |
2835 | rval = qla2x00_configure_fabric(vha); | |
1da177e4 LT |
2836 | } |
2837 | ||
2838 | if (rval == QLA_SUCCESS) { | |
e315cd28 AC |
2839 | if (atomic_read(&vha->loop_down_timer) || |
2840 | test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) { | |
1da177e4 LT |
2841 | rval = QLA_FUNCTION_FAILED; |
2842 | } else { | |
e315cd28 | 2843 | atomic_set(&vha->loop_state, LOOP_READY); |
7c3df132 SK |
2844 | ql_dbg(ql_dbg_disc, vha, 0x2069, |
2845 | "LOOP READY.\n"); | |
1da177e4 LT |
2846 | } |
2847 | } | |
2848 | ||
2849 | if (rval) { | |
7c3df132 SK |
2850 | ql_dbg(ql_dbg_disc, vha, 0x206a, |
2851 | "%s *** FAILED ***.\n", __func__); | |
1da177e4 | 2852 | } else { |
7c3df132 SK |
2853 | ql_dbg(ql_dbg_disc, vha, 0x206b, |
2854 | "%s: exiting normally.\n", __func__); | |
1da177e4 LT |
2855 | } |
2856 | ||
cc3ef7bc | 2857 | /* Restore state if a resync event occurred during processing */ |
e315cd28 | 2858 | if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) { |
1da177e4 | 2859 | if (test_bit(LOCAL_LOOP_UPDATE, &save_flags)) |
e315cd28 | 2860 | set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); |
f4658b6c | 2861 | if (test_bit(RSCN_UPDATE, &save_flags)) { |
e315cd28 | 2862 | set_bit(RSCN_UPDATE, &vha->dpc_flags); |
f4658b6c | 2863 | } |
1da177e4 LT |
2864 | } |
2865 | ||
2866 | return (rval); | |
2867 | } | |
2868 | ||
2869 | ||
2870 | ||
2871 | /* | |
2872 | * qla2x00_configure_local_loop | |
2873 | * Updates Fibre Channel Device Database with local loop devices. | |
2874 | * | |
2875 | * Input: | |
2876 | * ha = adapter block pointer. | |
2877 | * | |
2878 | * Returns: | |
2879 | * 0 = success. | |
2880 | */ | |
2881 | static int | |
e315cd28 | 2882 | qla2x00_configure_local_loop(scsi_qla_host_t *vha) |
1da177e4 LT |
2883 | { |
2884 | int rval, rval2; | |
2885 | int found_devs; | |
2886 | int found; | |
2887 | fc_port_t *fcport, *new_fcport; | |
2888 | ||
2889 | uint16_t index; | |
2890 | uint16_t entries; | |
2891 | char *id_iter; | |
2892 | uint16_t loop_id; | |
2893 | uint8_t domain, area, al_pa; | |
e315cd28 | 2894 | struct qla_hw_data *ha = vha->hw; |
1da177e4 LT |
2895 | |
2896 | found_devs = 0; | |
2897 | new_fcport = NULL; | |
642ef983 | 2898 | entries = MAX_FIBRE_DEVICES_LOOP; |
1da177e4 | 2899 | |
1da177e4 | 2900 | /* Get list of logged in devices. */ |
642ef983 | 2901 | memset(ha->gid_list, 0, qla2x00_gid_list_size(ha)); |
e315cd28 | 2902 | rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma, |
1da177e4 LT |
2903 | &entries); |
2904 | if (rval != QLA_SUCCESS) | |
2905 | goto cleanup_allocation; | |
2906 | ||
7c3df132 SK |
2907 | ql_dbg(ql_dbg_disc, vha, 0x2017, |
2908 | "Entries in ID list (%d).\n", entries); | |
2909 | ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075, | |
2910 | (uint8_t *)ha->gid_list, | |
2911 | entries * sizeof(struct gid_list_info)); | |
1da177e4 LT |
2912 | |
2913 | /* Allocate temporary fcport for any new fcports discovered. */ | |
e315cd28 | 2914 | new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); |
1da177e4 | 2915 | if (new_fcport == NULL) { |
7c3df132 SK |
2916 | ql_log(ql_log_warn, vha, 0x2018, |
2917 | "Memory allocation failed for fcport.\n"); | |
1da177e4 LT |
2918 | rval = QLA_MEMORY_ALLOC_FAILED; |
2919 | goto cleanup_allocation; | |
2920 | } | |
2921 | new_fcport->flags &= ~FCF_FABRIC_DEVICE; | |
2922 | ||
2923 | /* | |
2924 | * Mark local devices that were present with FCF_DEVICE_LOST for now. | |
2925 | */ | |
e315cd28 | 2926 | list_for_each_entry(fcport, &vha->vp_fcports, list) { |
1da177e4 LT |
2927 | if (atomic_read(&fcport->state) == FCS_ONLINE && |
2928 | fcport->port_type != FCT_BROADCAST && | |
2929 | (fcport->flags & FCF_FABRIC_DEVICE) == 0) { | |
2930 | ||
7c3df132 SK |
2931 | ql_dbg(ql_dbg_disc, vha, 0x2019, |
2932 | "Marking port lost loop_id=0x%04x.\n", | |
2933 | fcport->loop_id); | |
1da177e4 | 2934 | |
ec426e10 | 2935 | qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); |
1da177e4 LT |
2936 | } |
2937 | } | |
2938 | ||
2939 | /* Add devices to port list. */ | |
2940 | id_iter = (char *)ha->gid_list; | |
2941 | for (index = 0; index < entries; index++) { | |
2942 | domain = ((struct gid_list_info *)id_iter)->domain; | |
2943 | area = ((struct gid_list_info *)id_iter)->area; | |
2944 | al_pa = ((struct gid_list_info *)id_iter)->al_pa; | |
abbd8870 | 2945 | if (IS_QLA2100(ha) || IS_QLA2200(ha)) |
1da177e4 LT |
2946 | loop_id = (uint16_t) |
2947 | ((struct gid_list_info *)id_iter)->loop_id_2100; | |
abbd8870 | 2948 | else |
1da177e4 LT |
2949 | loop_id = le16_to_cpu( |
2950 | ((struct gid_list_info *)id_iter)->loop_id); | |
abbd8870 | 2951 | id_iter += ha->gid_list_info_size; |
1da177e4 LT |
2952 | |
2953 | /* Bypass reserved domain fields. */ | |
2954 | if ((domain & 0xf0) == 0xf0) | |
2955 | continue; | |
2956 | ||
2957 | /* Bypass if not same domain and area of adapter. */ | |
f7d289f6 | 2958 | if (area && domain && |
e315cd28 | 2959 | (area != vha->d_id.b.area || domain != vha->d_id.b.domain)) |
1da177e4 LT |
2960 | continue; |
2961 | ||
2962 | /* Bypass invalid local loop ID. */ | |
2963 | if (loop_id > LAST_LOCAL_LOOP_ID) | |
2964 | continue; | |
2965 | ||
370d550e AE |
2966 | memset(new_fcport, 0, sizeof(fc_port_t)); |
2967 | ||
1da177e4 LT |
2968 | /* Fill in member data. */ |
2969 | new_fcport->d_id.b.domain = domain; | |
2970 | new_fcport->d_id.b.area = area; | |
2971 | new_fcport->d_id.b.al_pa = al_pa; | |
2972 | new_fcport->loop_id = loop_id; | |
e315cd28 | 2973 | rval2 = qla2x00_get_port_database(vha, new_fcport, 0); |
1da177e4 | 2974 | if (rval2 != QLA_SUCCESS) { |
7c3df132 SK |
2975 | ql_dbg(ql_dbg_disc, vha, 0x201a, |
2976 | "Failed to retrieve fcport information " | |
2977 | "-- get_port_database=%x, loop_id=0x%04x.\n", | |
2978 | rval2, new_fcport->loop_id); | |
2979 | ql_dbg(ql_dbg_disc, vha, 0x201b, | |
2980 | "Scheduling resync.\n"); | |
e315cd28 | 2981 | set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); |
1da177e4 LT |
2982 | continue; |
2983 | } | |
2984 | ||
2985 | /* Check for matching device in port list. */ | |
2986 | found = 0; | |
2987 | fcport = NULL; | |
e315cd28 | 2988 | list_for_each_entry(fcport, &vha->vp_fcports, list) { |
1da177e4 LT |
2989 | if (memcmp(new_fcport->port_name, fcport->port_name, |
2990 | WWN_SIZE)) | |
2991 | continue; | |
2992 | ||
ddb9b126 | 2993 | fcport->flags &= ~FCF_FABRIC_DEVICE; |
1da177e4 LT |
2994 | fcport->loop_id = new_fcport->loop_id; |
2995 | fcport->port_type = new_fcport->port_type; | |
2996 | fcport->d_id.b24 = new_fcport->d_id.b24; | |
2997 | memcpy(fcport->node_name, new_fcport->node_name, | |
2998 | WWN_SIZE); | |
2999 | ||
3000 | found++; | |
3001 | break; | |
3002 | } | |
3003 | ||
3004 | if (!found) { | |
3005 | /* New device, add to fcports list. */ | |
e315cd28 | 3006 | list_add_tail(&new_fcport->list, &vha->vp_fcports); |
1da177e4 LT |
3007 | |
3008 | /* Allocate a new replacement fcport. */ | |
3009 | fcport = new_fcport; | |
e315cd28 | 3010 | new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); |
1da177e4 | 3011 | if (new_fcport == NULL) { |
7c3df132 SK |
3012 | ql_log(ql_log_warn, vha, 0x201c, |
3013 | "Failed to allocate memory for fcport.\n"); | |
1da177e4 LT |
3014 | rval = QLA_MEMORY_ALLOC_FAILED; |
3015 | goto cleanup_allocation; | |
3016 | } | |
3017 | new_fcport->flags &= ~FCF_FABRIC_DEVICE; | |
3018 | } | |
3019 | ||
d8b45213 | 3020 | /* Base iIDMA settings on HBA port speed. */ |
a3cbdfad | 3021 | fcport->fp_speed = ha->link_data_rate; |
d8b45213 | 3022 | |
e315cd28 | 3023 | qla2x00_update_fcport(vha, fcport); |
1da177e4 LT |
3024 | |
3025 | found_devs++; | |
3026 | } | |
3027 | ||
3028 | cleanup_allocation: | |
c9475cb0 | 3029 | kfree(new_fcport); |
1da177e4 LT |
3030 | |
3031 | if (rval != QLA_SUCCESS) { | |
7c3df132 SK |
3032 | ql_dbg(ql_dbg_disc, vha, 0x201d, |
3033 | "Configure local loop error exit: rval=%x.\n", rval); | |
1da177e4 LT |
3034 | } |
3035 | ||
1da177e4 LT |
3036 | return (rval); |
3037 | } | |
3038 | ||
d8b45213 | 3039 | static void |
e315cd28 | 3040 | qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport) |
d8b45213 | 3041 | { |
d8b45213 | 3042 | int rval; |
1bb39548 | 3043 | uint16_t mb[4]; |
e315cd28 | 3044 | struct qla_hw_data *ha = vha->hw; |
d8b45213 | 3045 | |
c76f2c01 | 3046 | if (!IS_IIDMA_CAPABLE(ha)) |
d8b45213 AV |
3047 | return; |
3048 | ||
c9afb9a2 GM |
3049 | if (atomic_read(&fcport->state) != FCS_ONLINE) |
3050 | return; | |
3051 | ||
39bd9622 AV |
3052 | if (fcport->fp_speed == PORT_SPEED_UNKNOWN || |
3053 | fcport->fp_speed > ha->link_data_rate) | |
d8b45213 AV |
3054 | return; |
3055 | ||
e315cd28 | 3056 | rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed, |
a3cbdfad | 3057 | mb); |
d8b45213 | 3058 | if (rval != QLA_SUCCESS) { |
7c3df132 SK |
3059 | ql_dbg(ql_dbg_disc, vha, 0x2004, |
3060 | "Unable to adjust iIDMA " | |
3061 | "%02x%02x%02x%02x%02x%02x%02x%02x -- %04x %x %04x " | |
3062 | "%04x.\n", fcport->port_name[0], fcport->port_name[1], | |
d8b45213 AV |
3063 | fcport->port_name[2], fcport->port_name[3], |
3064 | fcport->port_name[4], fcport->port_name[5], | |
3065 | fcport->port_name[6], fcport->port_name[7], rval, | |
7c3df132 | 3066 | fcport->fp_speed, mb[0], mb[1]); |
d8b45213 | 3067 | } else { |
7c3df132 SK |
3068 | ql_dbg(ql_dbg_disc, vha, 0x2005, |
3069 | "iIDMA adjusted to %s GB/s " | |
d0297c9a JC |
3070 | "on %02x%02x%02x%02x%02x%02x%02x%02x.\n", |
3071 | qla2x00_get_link_speed_str(ha, fcport->fp_speed), | |
7c3df132 SK |
3072 | fcport->port_name[0], fcport->port_name[1], |
3073 | fcport->port_name[2], fcport->port_name[3], | |
3074 | fcport->port_name[4], fcport->port_name[5], | |
3075 | fcport->port_name[6], fcport->port_name[7]); | |
d8b45213 AV |
3076 | } |
3077 | } | |
3078 | ||
23be331d | 3079 | static void |
e315cd28 | 3080 | qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport) |
8482e118 AV |
3081 | { |
3082 | struct fc_rport_identifiers rport_ids; | |
bdf79621 | 3083 | struct fc_rport *rport; |
044d78e1 | 3084 | unsigned long flags; |
8482e118 | 3085 | |
ac280b67 | 3086 | qla2x00_rport_del(fcport); |
8482e118 | 3087 | |
f8b02a85 AV |
3088 | rport_ids.node_name = wwn_to_u64(fcport->node_name); |
3089 | rport_ids.port_name = wwn_to_u64(fcport->port_name); | |
8482e118 AV |
3090 | rport_ids.port_id = fcport->d_id.b.domain << 16 | |
3091 | fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa; | |
77d74143 | 3092 | rport_ids.roles = FC_RPORT_ROLE_UNKNOWN; |
e315cd28 | 3093 | fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids); |
77d74143 | 3094 | if (!rport) { |
7c3df132 SK |
3095 | ql_log(ql_log_warn, vha, 0x2006, |
3096 | "Unable to allocate fc remote port.\n"); | |
77d74143 AV |
3097 | return; |
3098 | } | |
2d70c103 NB |
3099 | /* |
3100 | * Create target mode FC NEXUS in qla_target.c if target mode is | |
3101 | * enabled.. | |
3102 | */ | |
3103 | qlt_fc_port_added(vha, fcport); | |
3104 | ||
044d78e1 | 3105 | spin_lock_irqsave(fcport->vha->host->host_lock, flags); |
19a7b4ae | 3106 | *((fc_port_t **)rport->dd_data) = fcport; |
044d78e1 | 3107 | spin_unlock_irqrestore(fcport->vha->host->host_lock, flags); |
d97994dc | 3108 | |
ad3e0eda | 3109 | rport->supported_classes = fcport->supported_classes; |
77d74143 | 3110 | |
8482e118 AV |
3111 | rport_ids.roles = FC_RPORT_ROLE_UNKNOWN; |
3112 | if (fcport->port_type == FCT_INITIATOR) | |
3113 | rport_ids.roles |= FC_RPORT_ROLE_FCP_INITIATOR; | |
3114 | if (fcport->port_type == FCT_TARGET) | |
3115 | rport_ids.roles |= FC_RPORT_ROLE_FCP_TARGET; | |
77d74143 | 3116 | fc_remote_port_rolechg(rport, rport_ids.roles); |
1da177e4 LT |
3117 | } |
3118 | ||
23be331d AB |
3119 | /* |
3120 | * qla2x00_update_fcport | |
3121 | * Updates device on list. | |
3122 | * | |
3123 | * Input: | |
3124 | * ha = adapter block pointer. | |
3125 | * fcport = port structure pointer. | |
3126 | * | |
3127 | * Return: | |
3128 | * 0 - Success | |
3129 | * BIT_0 - error | |
3130 | * | |
3131 | * Context: | |
3132 | * Kernel context. | |
3133 | */ | |
3134 | void | |
e315cd28 | 3135 | qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport) |
23be331d | 3136 | { |
e315cd28 | 3137 | fcport->vha = vha; |
23be331d | 3138 | fcport->login_retry = 0; |
5ff1d584 | 3139 | fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); |
23be331d | 3140 | |
1f93da52 | 3141 | qla2x00_set_fcport_state(fcport, FCS_ONLINE); |
e315cd28 | 3142 | qla2x00_iidma_fcport(vha, fcport); |
21090cbe | 3143 | qla24xx_update_fcport_fcp_prio(vha, fcport); |
e315cd28 | 3144 | qla2x00_reg_remote_port(vha, fcport); |
23be331d AB |
3145 | } |
3146 | ||
1da177e4 LT |
3147 | /* |
3148 | * qla2x00_configure_fabric | |
3149 | * Setup SNS devices with loop ID's. | |
3150 | * | |
3151 | * Input: | |
3152 | * ha = adapter block pointer. | |
3153 | * | |
3154 | * Returns: | |
3155 | * 0 = success. | |
3156 | * BIT_0 = error | |
3157 | */ | |
3158 | static int | |
e315cd28 | 3159 | qla2x00_configure_fabric(scsi_qla_host_t *vha) |
1da177e4 | 3160 | { |
b3b02e6e | 3161 | int rval; |
e452ceb6 | 3162 | fc_port_t *fcport, *fcptemp; |
1da177e4 LT |
3163 | uint16_t next_loopid; |
3164 | uint16_t mb[MAILBOX_REGISTER_COUNT]; | |
0107109e | 3165 | uint16_t loop_id; |
1da177e4 | 3166 | LIST_HEAD(new_fcports); |
e315cd28 AC |
3167 | struct qla_hw_data *ha = vha->hw; |
3168 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); | |
1da177e4 LT |
3169 | |
3170 | /* If FL port exists, then SNS is present */ | |
e428924c | 3171 | if (IS_FWI2_CAPABLE(ha)) |
0107109e AV |
3172 | loop_id = NPH_F_PORT; |
3173 | else | |
3174 | loop_id = SNS_FL_PORT; | |
e315cd28 | 3175 | rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1); |
1da177e4 | 3176 | if (rval != QLA_SUCCESS) { |
7c3df132 SK |
3177 | ql_dbg(ql_dbg_disc, vha, 0x201f, |
3178 | "MBX_GET_PORT_NAME failed, No FL Port.\n"); | |
1da177e4 | 3179 | |
e315cd28 | 3180 | vha->device_flags &= ~SWITCH_FOUND; |
1da177e4 LT |
3181 | return (QLA_SUCCESS); |
3182 | } | |
e315cd28 | 3183 | vha->device_flags |= SWITCH_FOUND; |
1da177e4 | 3184 | |
1da177e4 | 3185 | do { |
cca5335c AV |
3186 | /* FDMI support. */ |
3187 | if (ql2xfdmienable && | |
e315cd28 AC |
3188 | test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags)) |
3189 | qla2x00_fdmi_register(vha); | |
cca5335c | 3190 | |
1da177e4 | 3191 | /* Ensure we are logged into the SNS. */ |
e428924c | 3192 | if (IS_FWI2_CAPABLE(ha)) |
0107109e AV |
3193 | loop_id = NPH_SNS; |
3194 | else | |
3195 | loop_id = SIMPLE_NAME_SERVER; | |
0b91d116 CD |
3196 | rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff, |
3197 | 0xfc, mb, BIT_1|BIT_0); | |
3198 | if (rval != QLA_SUCCESS) { | |
3199 | set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); | |
e452ceb6 | 3200 | return rval; |
0b91d116 | 3201 | } |
1da177e4 | 3202 | if (mb[0] != MBS_COMMAND_COMPLETE) { |
7c3df132 SK |
3203 | ql_dbg(ql_dbg_disc, vha, 0x2042, |
3204 | "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x " | |
3205 | "mb[6]=%x mb[7]=%x.\n", loop_id, mb[0], mb[1], | |
3206 | mb[2], mb[6], mb[7]); | |
1da177e4 LT |
3207 | return (QLA_SUCCESS); |
3208 | } | |
3209 | ||
e315cd28 AC |
3210 | if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) { |
3211 | if (qla2x00_rft_id(vha)) { | |
1da177e4 | 3212 | /* EMPTY */ |
7c3df132 SK |
3213 | ql_dbg(ql_dbg_disc, vha, 0x2045, |
3214 | "Register FC-4 TYPE failed.\n"); | |
1da177e4 | 3215 | } |
e315cd28 | 3216 | if (qla2x00_rff_id(vha)) { |
1da177e4 | 3217 | /* EMPTY */ |
7c3df132 SK |
3218 | ql_dbg(ql_dbg_disc, vha, 0x2049, |
3219 | "Register FC-4 Features failed.\n"); | |
1da177e4 | 3220 | } |
e315cd28 | 3221 | if (qla2x00_rnn_id(vha)) { |
1da177e4 | 3222 | /* EMPTY */ |
7c3df132 SK |
3223 | ql_dbg(ql_dbg_disc, vha, 0x204f, |
3224 | "Register Node Name failed.\n"); | |
e315cd28 | 3225 | } else if (qla2x00_rsnn_nn(vha)) { |
1da177e4 | 3226 | /* EMPTY */ |
7c3df132 SK |
3227 | ql_dbg(ql_dbg_disc, vha, 0x2053, |
3228 | "Register Symobilic Node Name failed.\n"); | |
1da177e4 LT |
3229 | } |
3230 | } | |
3231 | ||
e315cd28 | 3232 | rval = qla2x00_find_all_fabric_devs(vha, &new_fcports); |
1da177e4 LT |
3233 | if (rval != QLA_SUCCESS) |
3234 | break; | |
3235 | ||
e452ceb6 JC |
3236 | /* |
3237 | * Logout all previous fabric devices marked lost, except | |
3238 | * FCP2 devices. | |
3239 | */ | |
e315cd28 AC |
3240 | list_for_each_entry(fcport, &vha->vp_fcports, list) { |
3241 | if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) | |
1da177e4 LT |
3242 | break; |
3243 | ||
3244 | if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) | |
3245 | continue; | |
3246 | ||
c0822b63 | 3247 | if (fcport->scan_state != QLA_FCPORT_SCAN_FOUND && |
b3b02e6e | 3248 | atomic_read(&fcport->state) == FCS_ONLINE) { |
e315cd28 | 3249 | qla2x00_mark_device_lost(vha, fcport, |
d97994dc | 3250 | ql2xplogiabsentdevice, 0); |
1da177e4 | 3251 | if (fcport->loop_id != FC_NO_LOOP_ID && |
f08b7251 | 3252 | (fcport->flags & FCF_FCP2_DEVICE) == 0 && |
1da177e4 LT |
3253 | fcport->port_type != FCT_INITIATOR && |
3254 | fcport->port_type != FCT_BROADCAST) { | |
e315cd28 | 3255 | ha->isp_ops->fabric_logout(vha, |
1c7c6357 AV |
3256 | fcport->loop_id, |
3257 | fcport->d_id.b.domain, | |
3258 | fcport->d_id.b.area, | |
3259 | fcport->d_id.b.al_pa); | |
e452ceb6 | 3260 | fcport->loop_id = FC_NO_LOOP_ID; |
1da177e4 | 3261 | } |
c0822b63 | 3262 | continue; |
1da177e4 | 3263 | } |
c0822b63 | 3264 | fcport->scan_state = QLA_FCPORT_SCAN_NONE; |
e452ceb6 | 3265 | } |
1da177e4 | 3266 | |
e452ceb6 JC |
3267 | /* Starting free loop ID. */ |
3268 | next_loopid = ha->min_external_loopid; | |
3269 | ||
3270 | /* | |
3271 | * Scan through our port list and login entries that need to be | |
3272 | * logged in. | |
3273 | */ | |
3274 | list_for_each_entry(fcport, &vha->vp_fcports, list) { | |
3275 | if (atomic_read(&vha->loop_down_timer) || | |
3276 | test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) | |
3277 | break; | |
3278 | ||
3279 | if ((fcport->flags & FCF_FABRIC_DEVICE) == 0 || | |
3280 | (fcport->flags & FCF_LOGIN_NEEDED) == 0) | |
3281 | continue; | |
3282 | ||
3283 | if (fcport->loop_id == FC_NO_LOOP_ID) { | |
3284 | fcport->loop_id = next_loopid; | |
3285 | rval = qla2x00_find_new_loop_id( | |
3286 | base_vha, fcport); | |
3287 | if (rval != QLA_SUCCESS) { | |
3288 | /* Ran out of IDs to use */ | |
3289 | break; | |
1da177e4 LT |
3290 | } |
3291 | } | |
e452ceb6 JC |
3292 | /* Login and update database */ |
3293 | qla2x00_fabric_dev_login(vha, fcport, &next_loopid); | |
3294 | } | |
3295 | ||
3296 | /* Exit if out of loop IDs. */ | |
3297 | if (rval != QLA_SUCCESS) { | |
3298 | break; | |
3299 | } | |
3300 | ||
3301 | /* | |
3302 | * Login and add the new devices to our port list. | |
3303 | */ | |
3304 | list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) { | |
3305 | if (atomic_read(&vha->loop_down_timer) || | |
3306 | test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) | |
3307 | break; | |
3308 | ||
3309 | /* Find a new loop ID to use. */ | |
3310 | fcport->loop_id = next_loopid; | |
3311 | rval = qla2x00_find_new_loop_id(base_vha, fcport); | |
3312 | if (rval != QLA_SUCCESS) { | |
3313 | /* Ran out of IDs to use */ | |
3314 | break; | |
3315 | } | |
1da177e4 | 3316 | |
bdf79621 | 3317 | /* Login and update database */ |
e315cd28 | 3318 | qla2x00_fabric_dev_login(vha, fcport, &next_loopid); |
e452ceb6 JC |
3319 | |
3320 | list_move_tail(&fcport->list, &vha->vp_fcports); | |
1da177e4 LT |
3321 | } |
3322 | } while (0); | |
3323 | ||
e452ceb6 JC |
3324 | /* Free all new device structures not processed. */ |
3325 | list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) { | |
3326 | list_del(&fcport->list); | |
3327 | kfree(fcport); | |
3328 | } | |
3329 | ||
1da177e4 | 3330 | if (rval) { |
7c3df132 SK |
3331 | ql_dbg(ql_dbg_disc, vha, 0x2068, |
3332 | "Configure fabric error exit rval=%d.\n", rval); | |
1da177e4 LT |
3333 | } |
3334 | ||
3335 | return (rval); | |
3336 | } | |
3337 | ||
1da177e4 LT |
3338 | /* |
3339 | * qla2x00_find_all_fabric_devs | |
3340 | * | |
3341 | * Input: | |
3342 | * ha = adapter block pointer. | |
3343 | * dev = database device entry pointer. | |
3344 | * | |
3345 | * Returns: | |
3346 | * 0 = success. | |
3347 | * | |
3348 | * Context: | |
3349 | * Kernel context. | |
3350 | */ | |
3351 | static int | |
e315cd28 AC |
3352 | qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha, |
3353 | struct list_head *new_fcports) | |
1da177e4 LT |
3354 | { |
3355 | int rval; | |
3356 | uint16_t loop_id; | |
3357 | fc_port_t *fcport, *new_fcport, *fcptemp; | |
3358 | int found; | |
3359 | ||
3360 | sw_info_t *swl; | |
3361 | int swl_idx; | |
3362 | int first_dev, last_dev; | |
1516ef44 | 3363 | port_id_t wrap = {}, nxt_d_id; |
e315cd28 AC |
3364 | struct qla_hw_data *ha = vha->hw; |
3365 | struct scsi_qla_host *vp, *base_vha = pci_get_drvdata(ha->pdev); | |
ee546b6e | 3366 | struct scsi_qla_host *tvp; |
1da177e4 LT |
3367 | |
3368 | rval = QLA_SUCCESS; | |
3369 | ||
3370 | /* Try GID_PT to get device list, else GAN. */ | |
7a67735b | 3371 | if (!ha->swl) |
642ef983 | 3372 | ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t), |
7a67735b AV |
3373 | GFP_KERNEL); |
3374 | swl = ha->swl; | |
bbfbbbc1 | 3375 | if (!swl) { |
1da177e4 | 3376 | /*EMPTY*/ |
7c3df132 SK |
3377 | ql_dbg(ql_dbg_disc, vha, 0x2054, |
3378 | "GID_PT allocations failed, fallback on GA_NXT.\n"); | |
1da177e4 | 3379 | } else { |
642ef983 | 3380 | memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t)); |
e315cd28 | 3381 | if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) { |
1da177e4 | 3382 | swl = NULL; |
e315cd28 | 3383 | } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) { |
1da177e4 | 3384 | swl = NULL; |
e315cd28 | 3385 | } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) { |
1da177e4 | 3386 | swl = NULL; |
e5896bd5 | 3387 | } else if (ql2xiidmaenable && |
e315cd28 AC |
3388 | qla2x00_gfpn_id(vha, swl) == QLA_SUCCESS) { |
3389 | qla2x00_gpsc(vha, swl); | |
1da177e4 | 3390 | } |
e8c72ba5 CD |
3391 | |
3392 | /* If other queries succeeded probe for FC-4 type */ | |
3393 | if (swl) | |
3394 | qla2x00_gff_id(vha, swl); | |
1da177e4 LT |
3395 | } |
3396 | swl_idx = 0; | |
3397 | ||
3398 | /* Allocate temporary fcport for any new fcports discovered. */ | |
e315cd28 | 3399 | new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); |
1da177e4 | 3400 | if (new_fcport == NULL) { |
7c3df132 SK |
3401 | ql_log(ql_log_warn, vha, 0x205e, |
3402 | "Failed to allocate memory for fcport.\n"); | |
1da177e4 LT |
3403 | return (QLA_MEMORY_ALLOC_FAILED); |
3404 | } | |
3405 | new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED); | |
1da177e4 LT |
3406 | /* Set start port ID scan at adapter ID. */ |
3407 | first_dev = 1; | |
3408 | last_dev = 0; | |
3409 | ||
3410 | /* Starting free loop ID. */ | |
e315cd28 AC |
3411 | loop_id = ha->min_external_loopid; |
3412 | for (; loop_id <= ha->max_loop_id; loop_id++) { | |
3413 | if (qla2x00_is_reserved_id(vha, loop_id)) | |
1da177e4 LT |
3414 | continue; |
3415 | ||
3a6478df GM |
3416 | if (ha->current_topology == ISP_CFG_FL && |
3417 | (atomic_read(&vha->loop_down_timer) || | |
3418 | LOOP_TRANSITION(vha))) { | |
bb2d52b2 AV |
3419 | atomic_set(&vha->loop_down_timer, 0); |
3420 | set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); | |
3421 | set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); | |
1da177e4 | 3422 | break; |
bb2d52b2 | 3423 | } |
1da177e4 LT |
3424 | |
3425 | if (swl != NULL) { | |
3426 | if (last_dev) { | |
3427 | wrap.b24 = new_fcport->d_id.b24; | |
3428 | } else { | |
3429 | new_fcport->d_id.b24 = swl[swl_idx].d_id.b24; | |
3430 | memcpy(new_fcport->node_name, | |
3431 | swl[swl_idx].node_name, WWN_SIZE); | |
3432 | memcpy(new_fcport->port_name, | |
3433 | swl[swl_idx].port_name, WWN_SIZE); | |
d8b45213 AV |
3434 | memcpy(new_fcport->fabric_port_name, |
3435 | swl[swl_idx].fabric_port_name, WWN_SIZE); | |
3436 | new_fcport->fp_speed = swl[swl_idx].fp_speed; | |
e8c72ba5 | 3437 | new_fcport->fc4_type = swl[swl_idx].fc4_type; |
1da177e4 LT |
3438 | |
3439 | if (swl[swl_idx].d_id.b.rsvd_1 != 0) { | |
3440 | last_dev = 1; | |
3441 | } | |
3442 | swl_idx++; | |
3443 | } | |
3444 | } else { | |
3445 | /* Send GA_NXT to the switch */ | |
e315cd28 | 3446 | rval = qla2x00_ga_nxt(vha, new_fcport); |
1da177e4 | 3447 | if (rval != QLA_SUCCESS) { |
7c3df132 SK |
3448 | ql_log(ql_log_warn, vha, 0x2064, |
3449 | "SNS scan failed -- assuming " | |
3450 | "zero-entry result.\n"); | |
1da177e4 LT |
3451 | list_for_each_entry_safe(fcport, fcptemp, |
3452 | new_fcports, list) { | |
3453 | list_del(&fcport->list); | |
3454 | kfree(fcport); | |
3455 | } | |
3456 | rval = QLA_SUCCESS; | |
3457 | break; | |
3458 | } | |
3459 | } | |
3460 | ||
3461 | /* If wrap on switch device list, exit. */ | |
3462 | if (first_dev) { | |
3463 | wrap.b24 = new_fcport->d_id.b24; | |
3464 | first_dev = 0; | |
3465 | } else if (new_fcport->d_id.b24 == wrap.b24) { | |
7c3df132 SK |
3466 | ql_dbg(ql_dbg_disc, vha, 0x2065, |
3467 | "Device wrap (%02x%02x%02x).\n", | |
3468 | new_fcport->d_id.b.domain, | |
3469 | new_fcport->d_id.b.area, | |
3470 | new_fcport->d_id.b.al_pa); | |
1da177e4 LT |
3471 | break; |
3472 | } | |
3473 | ||
2c3dfe3f | 3474 | /* Bypass if same physical adapter. */ |
e315cd28 | 3475 | if (new_fcport->d_id.b24 == base_vha->d_id.b24) |
1da177e4 LT |
3476 | continue; |
3477 | ||
2c3dfe3f | 3478 | /* Bypass virtual ports of the same host. */ |
e315cd28 AC |
3479 | found = 0; |
3480 | if (ha->num_vhosts) { | |
feafb7b1 AE |
3481 | unsigned long flags; |
3482 | ||
3483 | spin_lock_irqsave(&ha->vport_slock, flags); | |
ee546b6e | 3484 | list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) { |
e315cd28 AC |
3485 | if (new_fcport->d_id.b24 == vp->d_id.b24) { |
3486 | found = 1; | |
2c3dfe3f | 3487 | break; |
e315cd28 | 3488 | } |
2c3dfe3f | 3489 | } |
feafb7b1 AE |
3490 | spin_unlock_irqrestore(&ha->vport_slock, flags); |
3491 | ||
e315cd28 | 3492 | if (found) |
2c3dfe3f SJ |
3493 | continue; |
3494 | } | |
3495 | ||
f7d289f6 AV |
3496 | /* Bypass if same domain and area of adapter. */ |
3497 | if (((new_fcport->d_id.b24 & 0xffff00) == | |
e315cd28 | 3498 | (vha->d_id.b24 & 0xffff00)) && ha->current_topology == |
f7d289f6 AV |
3499 | ISP_CFG_FL) |
3500 | continue; | |
3501 | ||
1da177e4 LT |
3502 | /* Bypass reserved domain fields. */ |
3503 | if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0) | |
3504 | continue; | |
3505 | ||
e8c72ba5 | 3506 | /* Bypass ports whose FCP-4 type is not FCP_SCSI */ |
4da26e16 CD |
3507 | if (ql2xgffidenable && |
3508 | (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI && | |
3509 | new_fcport->fc4_type != FC4_TYPE_UNKNOWN)) | |
e8c72ba5 CD |
3510 | continue; |
3511 | ||
1da177e4 LT |
3512 | /* Locate matching device in database. */ |
3513 | found = 0; | |
e315cd28 | 3514 | list_for_each_entry(fcport, &vha->vp_fcports, list) { |
1da177e4 LT |
3515 | if (memcmp(new_fcport->port_name, fcport->port_name, |
3516 | WWN_SIZE)) | |
3517 | continue; | |
3518 | ||
c0822b63 | 3519 | fcport->scan_state = QLA_FCPORT_SCAN_FOUND; |
b3b02e6e | 3520 | |
1da177e4 LT |
3521 | found++; |
3522 | ||
d8b45213 AV |
3523 | /* Update port state. */ |
3524 | memcpy(fcport->fabric_port_name, | |
3525 | new_fcport->fabric_port_name, WWN_SIZE); | |
3526 | fcport->fp_speed = new_fcport->fp_speed; | |
3527 | ||
1da177e4 LT |
3528 | /* |
3529 | * If address the same and state FCS_ONLINE, nothing | |
3530 | * changed. | |
3531 | */ | |
3532 | if (fcport->d_id.b24 == new_fcport->d_id.b24 && | |
3533 | atomic_read(&fcport->state) == FCS_ONLINE) { | |
3534 | break; | |
3535 | } | |
3536 | ||
3537 | /* | |
3538 | * If device was not a fabric device before. | |
3539 | */ | |
3540 | if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) { | |
3541 | fcport->d_id.b24 = new_fcport->d_id.b24; | |
5f16b331 | 3542 | qla2x00_clear_loop_id(fcport); |
1da177e4 LT |
3543 | fcport->flags |= (FCF_FABRIC_DEVICE | |
3544 | FCF_LOGIN_NEEDED); | |
1da177e4 LT |
3545 | break; |
3546 | } | |
3547 | ||
3548 | /* | |
3549 | * Port ID changed or device was marked to be updated; | |
3550 | * Log it out if still logged in and mark it for | |
3551 | * relogin later. | |
3552 | */ | |
3553 | fcport->d_id.b24 = new_fcport->d_id.b24; | |
3554 | fcport->flags |= FCF_LOGIN_NEEDED; | |
3555 | if (fcport->loop_id != FC_NO_LOOP_ID && | |
f08b7251 | 3556 | (fcport->flags & FCF_FCP2_DEVICE) == 0 && |
0eba25df | 3557 | (fcport->flags & FCF_ASYNC_SENT) == 0 && |
1da177e4 LT |
3558 | fcport->port_type != FCT_INITIATOR && |
3559 | fcport->port_type != FCT_BROADCAST) { | |
e315cd28 | 3560 | ha->isp_ops->fabric_logout(vha, fcport->loop_id, |
1c7c6357 AV |
3561 | fcport->d_id.b.domain, fcport->d_id.b.area, |
3562 | fcport->d_id.b.al_pa); | |
5f16b331 | 3563 | qla2x00_clear_loop_id(fcport); |
1da177e4 LT |
3564 | } |
3565 | ||
3566 | break; | |
3567 | } | |
3568 | ||
3569 | if (found) | |
3570 | continue; | |
1da177e4 LT |
3571 | /* If device was not in our fcports list, then add it. */ |
3572 | list_add_tail(&new_fcport->list, new_fcports); | |
3573 | ||
3574 | /* Allocate a new replacement fcport. */ | |
3575 | nxt_d_id.b24 = new_fcport->d_id.b24; | |
e315cd28 | 3576 | new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); |
1da177e4 | 3577 | if (new_fcport == NULL) { |
7c3df132 SK |
3578 | ql_log(ql_log_warn, vha, 0x2066, |
3579 | "Memory allocation failed for fcport.\n"); | |
1da177e4 LT |
3580 | return (QLA_MEMORY_ALLOC_FAILED); |
3581 | } | |
3582 | new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED); | |
3583 | new_fcport->d_id.b24 = nxt_d_id.b24; | |
3584 | } | |
3585 | ||
c9475cb0 | 3586 | kfree(new_fcport); |
1da177e4 | 3587 | |
1da177e4 LT |
3588 | return (rval); |
3589 | } | |
3590 | ||
3591 | /* | |
3592 | * qla2x00_find_new_loop_id | |
3593 | * Scan through our port list and find a new usable loop ID. | |
3594 | * | |
3595 | * Input: | |
3596 | * ha: adapter state pointer. | |
3597 | * dev: port structure pointer. | |
3598 | * | |
3599 | * Returns: | |
3600 | * qla2x00 local function return status code. | |
3601 | * | |
3602 | * Context: | |
3603 | * Kernel context. | |
3604 | */ | |
03bcfb57 | 3605 | int |
e315cd28 | 3606 | qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev) |
1da177e4 LT |
3607 | { |
3608 | int rval; | |
e315cd28 | 3609 | struct qla_hw_data *ha = vha->hw; |
feafb7b1 | 3610 | unsigned long flags = 0; |
1da177e4 LT |
3611 | |
3612 | rval = QLA_SUCCESS; | |
3613 | ||
5f16b331 | 3614 | spin_lock_irqsave(&ha->vport_slock, flags); |
1da177e4 | 3615 | |
5f16b331 CD |
3616 | dev->loop_id = find_first_zero_bit(ha->loop_id_map, |
3617 | LOOPID_MAP_SIZE); | |
3618 | if (dev->loop_id >= LOOPID_MAP_SIZE || | |
3619 | qla2x00_is_reserved_id(vha, dev->loop_id)) { | |
3620 | dev->loop_id = FC_NO_LOOP_ID; | |
3621 | rval = QLA_FUNCTION_FAILED; | |
3622 | } else | |
3623 | set_bit(dev->loop_id, ha->loop_id_map); | |
1da177e4 | 3624 | |
5f16b331 | 3625 | spin_unlock_irqrestore(&ha->vport_slock, flags); |
1da177e4 | 3626 | |
5f16b331 CD |
3627 | if (rval == QLA_SUCCESS) |
3628 | ql_dbg(ql_dbg_disc, dev->vha, 0x2086, | |
3629 | "Assigning new loopid=%x, portid=%x.\n", | |
3630 | dev->loop_id, dev->d_id.b24); | |
3631 | else | |
3632 | ql_log(ql_log_warn, dev->vha, 0x2087, | |
3633 | "No loop_id's available, portid=%x.\n", | |
3634 | dev->d_id.b24); | |
1da177e4 LT |
3635 | |
3636 | return (rval); | |
3637 | } | |
3638 | ||
1da177e4 LT |
3639 | /* |
3640 | * qla2x00_fabric_dev_login | |
3641 | * Login fabric target device and update FC port database. | |
3642 | * | |
3643 | * Input: | |
3644 | * ha: adapter state pointer. | |
3645 | * fcport: port structure list pointer. | |
3646 | * next_loopid: contains value of a new loop ID that can be used | |
3647 | * by the next login attempt. | |
3648 | * | |
3649 | * Returns: | |
3650 | * qla2x00 local function return status code. | |
3651 | * | |
3652 | * Context: | |
3653 | * Kernel context. | |
3654 | */ | |
3655 | static int | |
e315cd28 | 3656 | qla2x00_fabric_dev_login(scsi_qla_host_t *vha, fc_port_t *fcport, |
1da177e4 LT |
3657 | uint16_t *next_loopid) |
3658 | { | |
3659 | int rval; | |
3660 | int retry; | |
0107109e | 3661 | uint8_t opts; |
e315cd28 | 3662 | struct qla_hw_data *ha = vha->hw; |
1da177e4 LT |
3663 | |
3664 | rval = QLA_SUCCESS; | |
3665 | retry = 0; | |
3666 | ||
ac280b67 | 3667 | if (IS_ALOGIO_CAPABLE(ha)) { |
5ff1d584 AV |
3668 | if (fcport->flags & FCF_ASYNC_SENT) |
3669 | return rval; | |
3670 | fcport->flags |= FCF_ASYNC_SENT; | |
ac280b67 AV |
3671 | rval = qla2x00_post_async_login_work(vha, fcport, NULL); |
3672 | if (!rval) | |
3673 | return rval; | |
3674 | } | |
3675 | ||
5ff1d584 | 3676 | fcport->flags &= ~FCF_ASYNC_SENT; |
e315cd28 | 3677 | rval = qla2x00_fabric_login(vha, fcport, next_loopid); |
1da177e4 | 3678 | if (rval == QLA_SUCCESS) { |
f08b7251 | 3679 | /* Send an ADISC to FCP2 devices.*/ |
0107109e | 3680 | opts = 0; |
f08b7251 | 3681 | if (fcport->flags & FCF_FCP2_DEVICE) |
0107109e | 3682 | opts |= BIT_1; |
e315cd28 | 3683 | rval = qla2x00_get_port_database(vha, fcport, opts); |
1da177e4 | 3684 | if (rval != QLA_SUCCESS) { |
e315cd28 | 3685 | ha->isp_ops->fabric_logout(vha, fcport->loop_id, |
1c7c6357 AV |
3686 | fcport->d_id.b.domain, fcport->d_id.b.area, |
3687 | fcport->d_id.b.al_pa); | |
e315cd28 | 3688 | qla2x00_mark_device_lost(vha, fcport, 1, 0); |
1da177e4 | 3689 | } else { |
e315cd28 | 3690 | qla2x00_update_fcport(vha, fcport); |
1da177e4 | 3691 | } |
0b91d116 CD |
3692 | } else { |
3693 | /* Retry Login. */ | |
3694 | qla2x00_mark_device_lost(vha, fcport, 1, 0); | |
1da177e4 LT |
3695 | } |
3696 | ||
3697 | return (rval); | |
3698 | } | |
3699 | ||
3700 | /* | |
3701 | * qla2x00_fabric_login | |
3702 | * Issue fabric login command. | |
3703 | * | |
3704 | * Input: | |
3705 | * ha = adapter block pointer. | |
3706 | * device = pointer to FC device type structure. | |
3707 | * | |
3708 | * Returns: | |
3709 | * 0 - Login successfully | |
3710 | * 1 - Login failed | |
3711 | * 2 - Initiator device | |
3712 | * 3 - Fatal error | |
3713 | */ | |
3714 | int | |
e315cd28 | 3715 | qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport, |
1da177e4 LT |
3716 | uint16_t *next_loopid) |
3717 | { | |
3718 | int rval; | |
3719 | int retry; | |
3720 | uint16_t tmp_loopid; | |
3721 | uint16_t mb[MAILBOX_REGISTER_COUNT]; | |
e315cd28 | 3722 | struct qla_hw_data *ha = vha->hw; |
1da177e4 LT |
3723 | |
3724 | retry = 0; | |
3725 | tmp_loopid = 0; | |
3726 | ||
3727 | for (;;) { | |
7c3df132 SK |
3728 | ql_dbg(ql_dbg_disc, vha, 0x2000, |
3729 | "Trying Fabric Login w/loop id 0x%04x for port " | |
3730 | "%02x%02x%02x.\n", | |
3731 | fcport->loop_id, fcport->d_id.b.domain, | |
3732 | fcport->d_id.b.area, fcport->d_id.b.al_pa); | |
1da177e4 LT |
3733 | |
3734 | /* Login fcport on switch. */ | |
0b91d116 | 3735 | rval = ha->isp_ops->fabric_login(vha, fcport->loop_id, |
1da177e4 LT |
3736 | fcport->d_id.b.domain, fcport->d_id.b.area, |
3737 | fcport->d_id.b.al_pa, mb, BIT_0); | |
0b91d116 CD |
3738 | if (rval != QLA_SUCCESS) { |
3739 | return rval; | |
3740 | } | |
1da177e4 LT |
3741 | if (mb[0] == MBS_PORT_ID_USED) { |
3742 | /* | |
3743 | * Device has another loop ID. The firmware team | |
0107109e AV |
3744 | * recommends the driver perform an implicit login with |
3745 | * the specified ID again. The ID we just used is save | |
3746 | * here so we return with an ID that can be tried by | |
3747 | * the next login. | |
1da177e4 LT |
3748 | */ |
3749 | retry++; | |
3750 | tmp_loopid = fcport->loop_id; | |
3751 | fcport->loop_id = mb[1]; | |
3752 | ||
7c3df132 SK |
3753 | ql_dbg(ql_dbg_disc, vha, 0x2001, |
3754 | "Fabric Login: port in use - next loop " | |
3755 | "id=0x%04x, port id= %02x%02x%02x.\n", | |
1da177e4 | 3756 | fcport->loop_id, fcport->d_id.b.domain, |
7c3df132 | 3757 | fcport->d_id.b.area, fcport->d_id.b.al_pa); |
1da177e4 LT |
3758 | |
3759 | } else if (mb[0] == MBS_COMMAND_COMPLETE) { | |
3760 | /* | |
3761 | * Login succeeded. | |
3762 | */ | |
3763 | if (retry) { | |
3764 | /* A retry occurred before. */ | |
3765 | *next_loopid = tmp_loopid; | |
3766 | } else { | |
3767 | /* | |
3768 | * No retry occurred before. Just increment the | |
3769 | * ID value for next login. | |
3770 | */ | |
3771 | *next_loopid = (fcport->loop_id + 1); | |
3772 | } | |
3773 | ||
3774 | if (mb[1] & BIT_0) { | |
3775 | fcport->port_type = FCT_INITIATOR; | |
3776 | } else { | |
3777 | fcport->port_type = FCT_TARGET; | |
3778 | if (mb[1] & BIT_1) { | |
8474f3a0 | 3779 | fcport->flags |= FCF_FCP2_DEVICE; |
1da177e4 LT |
3780 | } |
3781 | } | |
3782 | ||
ad3e0eda AV |
3783 | if (mb[10] & BIT_0) |
3784 | fcport->supported_classes |= FC_COS_CLASS2; | |
3785 | if (mb[10] & BIT_1) | |
3786 | fcport->supported_classes |= FC_COS_CLASS3; | |
3787 | ||
2d70c103 NB |
3788 | if (IS_FWI2_CAPABLE(ha)) { |
3789 | if (mb[10] & BIT_7) | |
3790 | fcport->flags |= | |
3791 | FCF_CONF_COMP_SUPPORTED; | |
3792 | } | |
3793 | ||
1da177e4 LT |
3794 | rval = QLA_SUCCESS; |
3795 | break; | |
3796 | } else if (mb[0] == MBS_LOOP_ID_USED) { | |
3797 | /* | |
3798 | * Loop ID already used, try next loop ID. | |
3799 | */ | |
3800 | fcport->loop_id++; | |
e315cd28 | 3801 | rval = qla2x00_find_new_loop_id(vha, fcport); |
1da177e4 LT |
3802 | if (rval != QLA_SUCCESS) { |
3803 | /* Ran out of loop IDs to use */ | |
3804 | break; | |
3805 | } | |
3806 | } else if (mb[0] == MBS_COMMAND_ERROR) { | |
3807 | /* | |
3808 | * Firmware possibly timed out during login. If NO | |
3809 | * retries are left to do then the device is declared | |
3810 | * dead. | |
3811 | */ | |
3812 | *next_loopid = fcport->loop_id; | |
e315cd28 | 3813 | ha->isp_ops->fabric_logout(vha, fcport->loop_id, |
1c7c6357 AV |
3814 | fcport->d_id.b.domain, fcport->d_id.b.area, |
3815 | fcport->d_id.b.al_pa); | |
e315cd28 | 3816 | qla2x00_mark_device_lost(vha, fcport, 1, 0); |
1da177e4 LT |
3817 | |
3818 | rval = 1; | |
3819 | break; | |
3820 | } else { | |
3821 | /* | |
3822 | * unrecoverable / not handled error | |
3823 | */ | |
7c3df132 SK |
3824 | ql_dbg(ql_dbg_disc, vha, 0x2002, |
3825 | "Failed=%x port_id=%02x%02x%02x loop_id=%x " | |
3826 | "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain, | |
3827 | fcport->d_id.b.area, fcport->d_id.b.al_pa, | |
3828 | fcport->loop_id, jiffies); | |
1da177e4 LT |
3829 | |
3830 | *next_loopid = fcport->loop_id; | |
e315cd28 | 3831 | ha->isp_ops->fabric_logout(vha, fcport->loop_id, |
1c7c6357 AV |
3832 | fcport->d_id.b.domain, fcport->d_id.b.area, |
3833 | fcport->d_id.b.al_pa); | |
5f16b331 | 3834 | qla2x00_clear_loop_id(fcport); |
0eedfcf0 | 3835 | fcport->login_retry = 0; |
1da177e4 LT |
3836 | |
3837 | rval = 3; | |
3838 | break; | |
3839 | } | |
3840 | } | |
3841 | ||
3842 | return (rval); | |
3843 | } | |
3844 | ||
3845 | /* | |
3846 | * qla2x00_local_device_login | |
3847 | * Issue local device login command. | |
3848 | * | |
3849 | * Input: | |
3850 | * ha = adapter block pointer. | |
3851 | * loop_id = loop id of device to login to. | |
3852 | * | |
3853 | * Returns (Where's the #define!!!!): | |
3854 | * 0 - Login successfully | |
3855 | * 1 - Login failed | |
3856 | * 3 - Fatal error | |
3857 | */ | |
3858 | int | |
e315cd28 | 3859 | qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport) |
1da177e4 LT |
3860 | { |
3861 | int rval; | |
3862 | uint16_t mb[MAILBOX_REGISTER_COUNT]; | |
3863 | ||
3864 | memset(mb, 0, sizeof(mb)); | |
e315cd28 | 3865 | rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0); |
1da177e4 LT |
3866 | if (rval == QLA_SUCCESS) { |
3867 | /* Interrogate mailbox registers for any errors */ | |
3868 | if (mb[0] == MBS_COMMAND_ERROR) | |
3869 | rval = 1; | |
3870 | else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR) | |
3871 | /* device not in PCB table */ | |
3872 | rval = 3; | |
3873 | } | |
3874 | ||
3875 | return (rval); | |
3876 | } | |
3877 | ||
3878 | /* | |
3879 | * qla2x00_loop_resync | |
3880 | * Resync with fibre channel devices. | |
3881 | * | |
3882 | * Input: | |
3883 | * ha = adapter block pointer. | |
3884 | * | |
3885 | * Returns: | |
3886 | * 0 = success | |
3887 | */ | |
3888 | int | |
e315cd28 | 3889 | qla2x00_loop_resync(scsi_qla_host_t *vha) |
1da177e4 | 3890 | { |
73208dfd | 3891 | int rval = QLA_SUCCESS; |
1da177e4 | 3892 | uint32_t wait_time; |
67c2e93a AC |
3893 | struct req_que *req; |
3894 | struct rsp_que *rsp; | |
3895 | ||
7163ea81 | 3896 | if (vha->hw->flags.cpu_affinity_enabled) |
67c2e93a AC |
3897 | req = vha->hw->req_q_map[0]; |
3898 | else | |
3899 | req = vha->req; | |
3900 | rsp = req->rsp; | |
1da177e4 | 3901 | |
e315cd28 AC |
3902 | clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); |
3903 | if (vha->flags.online) { | |
3904 | if (!(rval = qla2x00_fw_ready(vha))) { | |
1da177e4 LT |
3905 | /* Wait at most MAX_TARGET RSCNs for a stable link. */ |
3906 | wait_time = 256; | |
3907 | do { | |
0107109e | 3908 | /* Issue a marker after FW becomes ready. */ |
73208dfd AC |
3909 | qla2x00_marker(vha, req, rsp, 0, 0, |
3910 | MK_SYNC_ALL); | |
e315cd28 | 3911 | vha->marker_needed = 0; |
1da177e4 LT |
3912 | |
3913 | /* Remap devices on Loop. */ | |
e315cd28 | 3914 | clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); |
1da177e4 | 3915 | |
e315cd28 | 3916 | qla2x00_configure_loop(vha); |
1da177e4 | 3917 | wait_time--; |
e315cd28 AC |
3918 | } while (!atomic_read(&vha->loop_down_timer) && |
3919 | !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) | |
3920 | && wait_time && (test_bit(LOOP_RESYNC_NEEDED, | |
3921 | &vha->dpc_flags))); | |
1da177e4 | 3922 | } |
1da177e4 LT |
3923 | } |
3924 | ||
e315cd28 | 3925 | if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) |
1da177e4 | 3926 | return (QLA_FUNCTION_FAILED); |
1da177e4 | 3927 | |
e315cd28 | 3928 | if (rval) |
7c3df132 SK |
3929 | ql_dbg(ql_dbg_disc, vha, 0x206c, |
3930 | "%s *** FAILED ***.\n", __func__); | |
1da177e4 LT |
3931 | |
3932 | return (rval); | |
3933 | } | |
3934 | ||
579d12b5 SK |
3935 | /* |
3936 | * qla2x00_perform_loop_resync | |
3937 | * Description: This function will set the appropriate flags and call | |
3938 | * qla2x00_loop_resync. If successful loop will be resynced | |
3939 | * Arguments : scsi_qla_host_t pointer | |
3940 | * returm : Success or Failure | |
3941 | */ | |
3942 | ||
3943 | int qla2x00_perform_loop_resync(scsi_qla_host_t *ha) | |
3944 | { | |
3945 | int32_t rval = 0; | |
3946 | ||
3947 | if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) { | |
3948 | /*Configure the flags so that resync happens properly*/ | |
3949 | atomic_set(&ha->loop_down_timer, 0); | |
3950 | if (!(ha->device_flags & DFLG_NO_CABLE)) { | |
3951 | atomic_set(&ha->loop_state, LOOP_UP); | |
3952 | set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags); | |
3953 | set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags); | |
3954 | set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags); | |
3955 | ||
3956 | rval = qla2x00_loop_resync(ha); | |
3957 | } else | |
3958 | atomic_set(&ha->loop_state, LOOP_DEAD); | |
3959 | ||
3960 | clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags); | |
3961 | } | |
3962 | ||
3963 | return rval; | |
3964 | } | |
3965 | ||
d97994dc | 3966 | void |
67becc00 | 3967 | qla2x00_update_fcports(scsi_qla_host_t *base_vha) |
d97994dc AV |
3968 | { |
3969 | fc_port_t *fcport; | |
feafb7b1 AE |
3970 | struct scsi_qla_host *vha; |
3971 | struct qla_hw_data *ha = base_vha->hw; | |
3972 | unsigned long flags; | |
d97994dc | 3973 | |
feafb7b1 | 3974 | spin_lock_irqsave(&ha->vport_slock, flags); |
d97994dc | 3975 | /* Go with deferred removal of rport references. */ |
feafb7b1 AE |
3976 | list_for_each_entry(vha, &base_vha->hw->vp_list, list) { |
3977 | atomic_inc(&vha->vref_count); | |
3978 | list_for_each_entry(fcport, &vha->vp_fcports, list) { | |
8ae598d0 | 3979 | if (fcport->drport && |
feafb7b1 AE |
3980 | atomic_read(&fcport->state) != FCS_UNCONFIGURED) { |
3981 | spin_unlock_irqrestore(&ha->vport_slock, flags); | |
3982 | ||
67becc00 | 3983 | qla2x00_rport_del(fcport); |
feafb7b1 AE |
3984 | |
3985 | spin_lock_irqsave(&ha->vport_slock, flags); | |
3986 | } | |
3987 | } | |
3988 | atomic_dec(&vha->vref_count); | |
3989 | } | |
3990 | spin_unlock_irqrestore(&ha->vport_slock, flags); | |
d97994dc AV |
3991 | } |
3992 | ||
7d613ac6 SV |
3993 | /* Assumes idc_lock always held on entry */ |
3994 | void | |
3995 | qla83xx_reset_ownership(scsi_qla_host_t *vha) | |
3996 | { | |
3997 | struct qla_hw_data *ha = vha->hw; | |
3998 | uint32_t drv_presence, drv_presence_mask; | |
3999 | uint32_t dev_part_info1, dev_part_info2, class_type; | |
4000 | uint32_t class_type_mask = 0x3; | |
4001 | uint16_t fcoe_other_function = 0xffff, i; | |
4002 | ||
4003 | qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); | |
4004 | ||
4005 | qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1); | |
4006 | qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2); | |
4007 | for (i = 0; i < 8; i++) { | |
4008 | class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask); | |
4009 | if ((class_type == QLA83XX_CLASS_TYPE_FCOE) && | |
4010 | (i != ha->portnum)) { | |
4011 | fcoe_other_function = i; | |
4012 | break; | |
4013 | } | |
4014 | } | |
4015 | if (fcoe_other_function == 0xffff) { | |
4016 | for (i = 0; i < 8; i++) { | |
4017 | class_type = ((dev_part_info2 >> (i * 4)) & | |
4018 | class_type_mask); | |
4019 | if ((class_type == QLA83XX_CLASS_TYPE_FCOE) && | |
4020 | ((i + 8) != ha->portnum)) { | |
4021 | fcoe_other_function = i + 8; | |
4022 | break; | |
4023 | } | |
4024 | } | |
4025 | } | |
4026 | /* | |
4027 | * Prepare drv-presence mask based on fcoe functions present. | |
4028 | * However consider only valid physical fcoe function numbers (0-15). | |
4029 | */ | |
4030 | drv_presence_mask = ~((1 << (ha->portnum)) | | |
4031 | ((fcoe_other_function == 0xffff) ? | |
4032 | 0 : (1 << (fcoe_other_function)))); | |
4033 | ||
4034 | /* We are the reset owner iff: | |
4035 | * - No other protocol drivers present. | |
4036 | * - This is the lowest among fcoe functions. */ | |
4037 | if (!(drv_presence & drv_presence_mask) && | |
4038 | (ha->portnum < fcoe_other_function)) { | |
4039 | ql_dbg(ql_dbg_p3p, vha, 0xb07f, | |
4040 | "This host is Reset owner.\n"); | |
4041 | ha->flags.nic_core_reset_owner = 1; | |
4042 | } | |
4043 | } | |
4044 | ||
fa492630 | 4045 | static int |
7d613ac6 SV |
4046 | __qla83xx_set_drv_ack(scsi_qla_host_t *vha) |
4047 | { | |
4048 | int rval = QLA_SUCCESS; | |
4049 | struct qla_hw_data *ha = vha->hw; | |
4050 | uint32_t drv_ack; | |
4051 | ||
4052 | rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); | |
4053 | if (rval == QLA_SUCCESS) { | |
4054 | drv_ack |= (1 << ha->portnum); | |
4055 | rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack); | |
4056 | } | |
4057 | ||
4058 | return rval; | |
4059 | } | |
4060 | ||
fa492630 | 4061 | static int |
7d613ac6 SV |
4062 | __qla83xx_clear_drv_ack(scsi_qla_host_t *vha) |
4063 | { | |
4064 | int rval = QLA_SUCCESS; | |
4065 | struct qla_hw_data *ha = vha->hw; | |
4066 | uint32_t drv_ack; | |
4067 | ||
4068 | rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); | |
4069 | if (rval == QLA_SUCCESS) { | |
4070 | drv_ack &= ~(1 << ha->portnum); | |
4071 | rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack); | |
4072 | } | |
4073 | ||
4074 | return rval; | |
4075 | } | |
4076 | ||
fa492630 | 4077 | static const char * |
7d613ac6 SV |
4078 | qla83xx_dev_state_to_string(uint32_t dev_state) |
4079 | { | |
4080 | switch (dev_state) { | |
4081 | case QLA8XXX_DEV_COLD: | |
4082 | return "COLD/RE-INIT"; | |
4083 | case QLA8XXX_DEV_INITIALIZING: | |
4084 | return "INITIALIZING"; | |
4085 | case QLA8XXX_DEV_READY: | |
4086 | return "READY"; | |
4087 | case QLA8XXX_DEV_NEED_RESET: | |
4088 | return "NEED RESET"; | |
4089 | case QLA8XXX_DEV_NEED_QUIESCENT: | |
4090 | return "NEED QUIESCENT"; | |
4091 | case QLA8XXX_DEV_FAILED: | |
4092 | return "FAILED"; | |
4093 | case QLA8XXX_DEV_QUIESCENT: | |
4094 | return "QUIESCENT"; | |
4095 | default: | |
4096 | return "Unknown"; | |
4097 | } | |
4098 | } | |
4099 | ||
4100 | /* Assumes idc-lock always held on entry */ | |
4101 | void | |
4102 | qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type) | |
4103 | { | |
4104 | struct qla_hw_data *ha = vha->hw; | |
4105 | uint32_t idc_audit_reg = 0, duration_secs = 0; | |
4106 | ||
4107 | switch (audit_type) { | |
4108 | case IDC_AUDIT_TIMESTAMP: | |
4109 | ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000); | |
4110 | idc_audit_reg = (ha->portnum) | | |
4111 | (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8); | |
4112 | qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg); | |
4113 | break; | |
4114 | ||
4115 | case IDC_AUDIT_COMPLETION: | |
4116 | duration_secs = ((jiffies_to_msecs(jiffies) - | |
4117 | jiffies_to_msecs(ha->idc_audit_ts)) / 1000); | |
4118 | idc_audit_reg = (ha->portnum) | | |
4119 | (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8); | |
4120 | qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg); | |
4121 | break; | |
4122 | ||
4123 | default: | |
4124 | ql_log(ql_log_warn, vha, 0xb078, | |
4125 | "Invalid audit type specified.\n"); | |
4126 | break; | |
4127 | } | |
4128 | } | |
4129 | ||
4130 | /* Assumes idc_lock always held on entry */ | |
fa492630 | 4131 | static int |
7d613ac6 SV |
4132 | qla83xx_initiating_reset(scsi_qla_host_t *vha) |
4133 | { | |
4134 | struct qla_hw_data *ha = vha->hw; | |
4135 | uint32_t idc_control, dev_state; | |
4136 | ||
4137 | __qla83xx_get_idc_control(vha, &idc_control); | |
4138 | if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) { | |
4139 | ql_log(ql_log_info, vha, 0xb080, | |
4140 | "NIC Core reset has been disabled. idc-control=0x%x\n", | |
4141 | idc_control); | |
4142 | return QLA_FUNCTION_FAILED; | |
4143 | } | |
4144 | ||
4145 | /* Set NEED-RESET iff in READY state and we are the reset-owner */ | |
4146 | qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state); | |
4147 | if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) { | |
4148 | qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, | |
4149 | QLA8XXX_DEV_NEED_RESET); | |
4150 | ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n"); | |
4151 | qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP); | |
4152 | } else { | |
4153 | const char *state = qla83xx_dev_state_to_string(dev_state); | |
4154 | ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n", state); | |
4155 | ||
4156 | /* SV: XXX: Is timeout required here? */ | |
4157 | /* Wait for IDC state change READY -> NEED_RESET */ | |
4158 | while (dev_state == QLA8XXX_DEV_READY) { | |
4159 | qla83xx_idc_unlock(vha, 0); | |
4160 | msleep(200); | |
4161 | qla83xx_idc_lock(vha, 0); | |
4162 | qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state); | |
4163 | } | |
4164 | } | |
4165 | ||
4166 | /* Send IDC ack by writing to drv-ack register */ | |
4167 | __qla83xx_set_drv_ack(vha); | |
4168 | ||
4169 | return QLA_SUCCESS; | |
4170 | } | |
4171 | ||
4172 | int | |
4173 | __qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control) | |
4174 | { | |
4175 | return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control); | |
4176 | } | |
4177 | ||
7d613ac6 SV |
4178 | int |
4179 | __qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control) | |
4180 | { | |
4181 | return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control); | |
4182 | } | |
4183 | ||
fa492630 | 4184 | static int |
7d613ac6 SV |
4185 | qla83xx_check_driver_presence(scsi_qla_host_t *vha) |
4186 | { | |
4187 | uint32_t drv_presence = 0; | |
4188 | struct qla_hw_data *ha = vha->hw; | |
4189 | ||
4190 | qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); | |
4191 | if (drv_presence & (1 << ha->portnum)) | |
4192 | return QLA_SUCCESS; | |
4193 | else | |
4194 | return QLA_TEST_FAILED; | |
4195 | } | |
4196 | ||
4197 | int | |
4198 | qla83xx_nic_core_reset(scsi_qla_host_t *vha) | |
4199 | { | |
4200 | int rval = QLA_SUCCESS; | |
4201 | struct qla_hw_data *ha = vha->hw; | |
4202 | ||
4203 | ql_dbg(ql_dbg_p3p, vha, 0xb058, | |
4204 | "Entered %s().\n", __func__); | |
4205 | ||
4206 | if (vha->device_flags & DFLG_DEV_FAILED) { | |
4207 | ql_log(ql_log_warn, vha, 0xb059, | |
4208 | "Device in unrecoverable FAILED state.\n"); | |
4209 | return QLA_FUNCTION_FAILED; | |
4210 | } | |
4211 | ||
4212 | qla83xx_idc_lock(vha, 0); | |
4213 | ||
4214 | if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) { | |
4215 | ql_log(ql_log_warn, vha, 0xb05a, | |
4216 | "Function=0x%x has been removed from IDC participation.\n", | |
4217 | ha->portnum); | |
4218 | rval = QLA_FUNCTION_FAILED; | |
4219 | goto exit; | |
4220 | } | |
4221 | ||
4222 | qla83xx_reset_ownership(vha); | |
4223 | ||
4224 | rval = qla83xx_initiating_reset(vha); | |
4225 | ||
4226 | /* | |
4227 | * Perform reset if we are the reset-owner, | |
4228 | * else wait till IDC state changes to READY/FAILED. | |
4229 | */ | |
4230 | if (rval == QLA_SUCCESS) { | |
4231 | rval = qla83xx_idc_state_handler(vha); | |
4232 | ||
4233 | if (rval == QLA_SUCCESS) | |
4234 | ha->flags.nic_core_hung = 0; | |
4235 | __qla83xx_clear_drv_ack(vha); | |
4236 | } | |
4237 | ||
4238 | exit: | |
4239 | qla83xx_idc_unlock(vha, 0); | |
4240 | ||
4241 | ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__); | |
4242 | ||
4243 | return rval; | |
4244 | } | |
4245 | ||
81178772 SK |
4246 | int |
4247 | qla2xxx_mctp_dump(scsi_qla_host_t *vha) | |
4248 | { | |
4249 | struct qla_hw_data *ha = vha->hw; | |
4250 | int rval = QLA_FUNCTION_FAILED; | |
4251 | ||
4252 | if (!IS_MCTP_CAPABLE(ha)) { | |
4253 | /* This message can be removed from the final version */ | |
4254 | ql_log(ql_log_info, vha, 0x506d, | |
4255 | "This board is not MCTP capable\n"); | |
4256 | return rval; | |
4257 | } | |
4258 | ||
4259 | if (!ha->mctp_dump) { | |
4260 | ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev, | |
4261 | MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL); | |
4262 | ||
4263 | if (!ha->mctp_dump) { | |
4264 | ql_log(ql_log_warn, vha, 0x506e, | |
4265 | "Failed to allocate memory for mctp dump\n"); | |
4266 | return rval; | |
4267 | } | |
4268 | } | |
4269 | ||
4270 | #define MCTP_DUMP_STR_ADDR 0x00000000 | |
4271 | rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma, | |
4272 | MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4); | |
4273 | if (rval != QLA_SUCCESS) { | |
4274 | ql_log(ql_log_warn, vha, 0x506f, | |
4275 | "Failed to capture mctp dump\n"); | |
4276 | } else { | |
4277 | ql_log(ql_log_info, vha, 0x5070, | |
4278 | "Mctp dump capture for host (%ld/%p).\n", | |
4279 | vha->host_no, ha->mctp_dump); | |
4280 | ha->mctp_dumped = 1; | |
4281 | } | |
4282 | ||
409ee0fe | 4283 | if (!ha->flags.nic_core_reset_hdlr_active && !ha->portnum) { |
81178772 SK |
4284 | ha->flags.nic_core_reset_hdlr_active = 1; |
4285 | rval = qla83xx_restart_nic_firmware(vha); | |
4286 | if (rval) | |
4287 | /* NIC Core reset failed. */ | |
4288 | ql_log(ql_log_warn, vha, 0x5071, | |
4289 | "Failed to restart nic firmware\n"); | |
4290 | else | |
4291 | ql_dbg(ql_dbg_p3p, vha, 0xb084, | |
4292 | "Restarted NIC firmware successfully.\n"); | |
4293 | ha->flags.nic_core_reset_hdlr_active = 0; | |
4294 | } | |
4295 | ||
4296 | return rval; | |
4297 | ||
4298 | } | |
4299 | ||
579d12b5 | 4300 | /* |
8fcd6b8b | 4301 | * qla2x00_quiesce_io |
579d12b5 SK |
4302 | * Description: This function will block the new I/Os |
4303 | * Its not aborting any I/Os as context | |
4304 | * is not destroyed during quiescence | |
4305 | * Arguments: scsi_qla_host_t | |
4306 | * return : void | |
4307 | */ | |
4308 | void | |
8fcd6b8b | 4309 | qla2x00_quiesce_io(scsi_qla_host_t *vha) |
579d12b5 SK |
4310 | { |
4311 | struct qla_hw_data *ha = vha->hw; | |
4312 | struct scsi_qla_host *vp; | |
4313 | ||
8fcd6b8b CD |
4314 | ql_dbg(ql_dbg_dpc, vha, 0x401d, |
4315 | "Quiescing I/O - ha=%p.\n", ha); | |
579d12b5 SK |
4316 | |
4317 | atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME); | |
4318 | if (atomic_read(&vha->loop_state) != LOOP_DOWN) { | |
4319 | atomic_set(&vha->loop_state, LOOP_DOWN); | |
4320 | qla2x00_mark_all_devices_lost(vha, 0); | |
4321 | list_for_each_entry(vp, &ha->vp_list, list) | |
8fcd6b8b | 4322 | qla2x00_mark_all_devices_lost(vp, 0); |
579d12b5 SK |
4323 | } else { |
4324 | if (!atomic_read(&vha->loop_down_timer)) | |
4325 | atomic_set(&vha->loop_down_timer, | |
4326 | LOOP_DOWN_TIME); | |
4327 | } | |
4328 | /* Wait for pending cmds to complete */ | |
4329 | qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST); | |
4330 | } | |
4331 | ||
a9083016 GM |
4332 | void |
4333 | qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha) | |
4334 | { | |
4335 | struct qla_hw_data *ha = vha->hw; | |
579d12b5 | 4336 | struct scsi_qla_host *vp; |
feafb7b1 | 4337 | unsigned long flags; |
6aef87be | 4338 | fc_port_t *fcport; |
a9083016 | 4339 | |
e46ef004 SK |
4340 | /* For ISP82XX, driver waits for completion of the commands. |
4341 | * online flag should be set. | |
4342 | */ | |
4343 | if (!IS_QLA82XX(ha)) | |
4344 | vha->flags.online = 0; | |
a9083016 GM |
4345 | ha->flags.chip_reset_done = 0; |
4346 | clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); | |
2be21fa2 | 4347 | vha->qla_stats.total_isp_aborts++; |
a9083016 | 4348 | |
7c3df132 SK |
4349 | ql_log(ql_log_info, vha, 0x00af, |
4350 | "Performing ISP error recovery - ha=%p.\n", ha); | |
a9083016 | 4351 | |
e46ef004 SK |
4352 | /* For ISP82XX, reset_chip is just disabling interrupts. |
4353 | * Driver waits for the completion of the commands. | |
4354 | * the interrupts need to be enabled. | |
4355 | */ | |
a9083016 GM |
4356 | if (!IS_QLA82XX(ha)) |
4357 | ha->isp_ops->reset_chip(vha); | |
4358 | ||
4359 | atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); | |
4360 | if (atomic_read(&vha->loop_state) != LOOP_DOWN) { | |
4361 | atomic_set(&vha->loop_state, LOOP_DOWN); | |
4362 | qla2x00_mark_all_devices_lost(vha, 0); | |
feafb7b1 AE |
4363 | |
4364 | spin_lock_irqsave(&ha->vport_slock, flags); | |
579d12b5 | 4365 | list_for_each_entry(vp, &ha->vp_list, list) { |
feafb7b1 AE |
4366 | atomic_inc(&vp->vref_count); |
4367 | spin_unlock_irqrestore(&ha->vport_slock, flags); | |
4368 | ||
a9083016 | 4369 | qla2x00_mark_all_devices_lost(vp, 0); |
feafb7b1 AE |
4370 | |
4371 | spin_lock_irqsave(&ha->vport_slock, flags); | |
4372 | atomic_dec(&vp->vref_count); | |
4373 | } | |
4374 | spin_unlock_irqrestore(&ha->vport_slock, flags); | |
a9083016 GM |
4375 | } else { |
4376 | if (!atomic_read(&vha->loop_down_timer)) | |
4377 | atomic_set(&vha->loop_down_timer, | |
4378 | LOOP_DOWN_TIME); | |
4379 | } | |
4380 | ||
6aef87be AV |
4381 | /* Clear all async request states across all VPs. */ |
4382 | list_for_each_entry(fcport, &vha->vp_fcports, list) | |
4383 | fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); | |
4384 | spin_lock_irqsave(&ha->vport_slock, flags); | |
4385 | list_for_each_entry(vp, &ha->vp_list, list) { | |
4386 | atomic_inc(&vp->vref_count); | |
4387 | spin_unlock_irqrestore(&ha->vport_slock, flags); | |
4388 | ||
4389 | list_for_each_entry(fcport, &vp->vp_fcports, list) | |
4390 | fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); | |
4391 | ||
4392 | spin_lock_irqsave(&ha->vport_slock, flags); | |
4393 | atomic_dec(&vp->vref_count); | |
4394 | } | |
4395 | spin_unlock_irqrestore(&ha->vport_slock, flags); | |
4396 | ||
bddd2d65 LC |
4397 | if (!ha->flags.eeh_busy) { |
4398 | /* Make sure for ISP 82XX IO DMA is complete */ | |
4399 | if (IS_QLA82XX(ha)) { | |
7190575f | 4400 | qla82xx_chip_reset_cleanup(vha); |
7c3df132 SK |
4401 | ql_log(ql_log_info, vha, 0x00b4, |
4402 | "Done chip reset cleanup.\n"); | |
a9083016 | 4403 | |
e46ef004 SK |
4404 | /* Done waiting for pending commands. |
4405 | * Reset the online flag. | |
4406 | */ | |
4407 | vha->flags.online = 0; | |
4d78c973 | 4408 | } |
a9083016 | 4409 | |
bddd2d65 LC |
4410 | /* Requeue all commands in outstanding command list. */ |
4411 | qla2x00_abort_all_cmds(vha, DID_RESET << 16); | |
4412 | } | |
a9083016 GM |
4413 | } |
4414 | ||
1da177e4 LT |
4415 | /* |
4416 | * qla2x00_abort_isp | |
4417 | * Resets ISP and aborts all outstanding commands. | |
4418 | * | |
4419 | * Input: | |
4420 | * ha = adapter block pointer. | |
4421 | * | |
4422 | * Returns: | |
4423 | * 0 = success | |
4424 | */ | |
4425 | int | |
e315cd28 | 4426 | qla2x00_abort_isp(scsi_qla_host_t *vha) |
1da177e4 | 4427 | { |
476e8978 | 4428 | int rval; |
1da177e4 | 4429 | uint8_t status = 0; |
e315cd28 AC |
4430 | struct qla_hw_data *ha = vha->hw; |
4431 | struct scsi_qla_host *vp; | |
73208dfd | 4432 | struct req_que *req = ha->req_q_map[0]; |
feafb7b1 | 4433 | unsigned long flags; |
1da177e4 | 4434 | |
e315cd28 | 4435 | if (vha->flags.online) { |
a9083016 | 4436 | qla2x00_abort_isp_cleanup(vha); |
1da177e4 | 4437 | |
a6171297 SV |
4438 | if (IS_QLA8031(ha)) { |
4439 | ql_dbg(ql_dbg_p3p, vha, 0xb05c, | |
4440 | "Clearing fcoe driver presence.\n"); | |
4441 | if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS) | |
4442 | ql_dbg(ql_dbg_p3p, vha, 0xb073, | |
4443 | "Error while clearing DRV-Presence.\n"); | |
4444 | } | |
4445 | ||
85880801 AV |
4446 | if (unlikely(pci_channel_offline(ha->pdev) && |
4447 | ha->flags.pci_channel_io_perm_failure)) { | |
4448 | clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); | |
4449 | status = 0; | |
4450 | return status; | |
4451 | } | |
4452 | ||
73208dfd | 4453 | ha->isp_ops->get_flash_version(vha, req->ring); |
30c47662 | 4454 | |
e315cd28 | 4455 | ha->isp_ops->nvram_config(vha); |
1da177e4 | 4456 | |
e315cd28 AC |
4457 | if (!qla2x00_restart_isp(vha)) { |
4458 | clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); | |
1da177e4 | 4459 | |
e315cd28 | 4460 | if (!atomic_read(&vha->loop_down_timer)) { |
1da177e4 LT |
4461 | /* |
4462 | * Issue marker command only when we are going | |
4463 | * to start the I/O . | |
4464 | */ | |
e315cd28 | 4465 | vha->marker_needed = 1; |
1da177e4 LT |
4466 | } |
4467 | ||
e315cd28 | 4468 | vha->flags.online = 1; |
1da177e4 | 4469 | |
fd34f556 | 4470 | ha->isp_ops->enable_intrs(ha); |
1da177e4 | 4471 | |
fa2a1ce5 | 4472 | ha->isp_abort_cnt = 0; |
e315cd28 | 4473 | clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); |
476e8978 | 4474 | |
6246b8a1 GM |
4475 | if (IS_QLA81XX(ha) || IS_QLA8031(ha)) |
4476 | qla2x00_get_fw_version(vha); | |
df613b96 AV |
4477 | if (ha->fce) { |
4478 | ha->flags.fce_enabled = 1; | |
4479 | memset(ha->fce, 0, | |
4480 | fce_calc_size(ha->fce_bufs)); | |
e315cd28 | 4481 | rval = qla2x00_enable_fce_trace(vha, |
df613b96 AV |
4482 | ha->fce_dma, ha->fce_bufs, ha->fce_mb, |
4483 | &ha->fce_bufs); | |
4484 | if (rval) { | |
7c3df132 | 4485 | ql_log(ql_log_warn, vha, 0x8033, |
df613b96 AV |
4486 | "Unable to reinitialize FCE " |
4487 | "(%d).\n", rval); | |
4488 | ha->flags.fce_enabled = 0; | |
4489 | } | |
4490 | } | |
436a7b11 AV |
4491 | |
4492 | if (ha->eft) { | |
4493 | memset(ha->eft, 0, EFT_SIZE); | |
e315cd28 | 4494 | rval = qla2x00_enable_eft_trace(vha, |
436a7b11 AV |
4495 | ha->eft_dma, EFT_NUM_BUFFERS); |
4496 | if (rval) { | |
7c3df132 | 4497 | ql_log(ql_log_warn, vha, 0x8034, |
436a7b11 AV |
4498 | "Unable to reinitialize EFT " |
4499 | "(%d).\n", rval); | |
4500 | } | |
4501 | } | |
1da177e4 | 4502 | } else { /* failed the ISP abort */ |
e315cd28 AC |
4503 | vha->flags.online = 1; |
4504 | if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { | |
1da177e4 | 4505 | if (ha->isp_abort_cnt == 0) { |
7c3df132 SK |
4506 | ql_log(ql_log_fatal, vha, 0x8035, |
4507 | "ISP error recover failed - " | |
4508 | "board disabled.\n"); | |
fa2a1ce5 | 4509 | /* |
1da177e4 LT |
4510 | * The next call disables the board |
4511 | * completely. | |
4512 | */ | |
e315cd28 AC |
4513 | ha->isp_ops->reset_adapter(vha); |
4514 | vha->flags.online = 0; | |
1da177e4 | 4515 | clear_bit(ISP_ABORT_RETRY, |
e315cd28 | 4516 | &vha->dpc_flags); |
1da177e4 LT |
4517 | status = 0; |
4518 | } else { /* schedule another ISP abort */ | |
4519 | ha->isp_abort_cnt--; | |
7c3df132 SK |
4520 | ql_dbg(ql_dbg_taskm, vha, 0x8020, |
4521 | "ISP abort - retry remaining %d.\n", | |
4522 | ha->isp_abort_cnt); | |
1da177e4 LT |
4523 | status = 1; |
4524 | } | |
4525 | } else { | |
4526 | ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT; | |
7c3df132 SK |
4527 | ql_dbg(ql_dbg_taskm, vha, 0x8021, |
4528 | "ISP error recovery - retrying (%d) " | |
4529 | "more times.\n", ha->isp_abort_cnt); | |
e315cd28 | 4530 | set_bit(ISP_ABORT_RETRY, &vha->dpc_flags); |
1da177e4 LT |
4531 | status = 1; |
4532 | } | |
4533 | } | |
fa2a1ce5 | 4534 | |
1da177e4 LT |
4535 | } |
4536 | ||
e315cd28 | 4537 | if (!status) { |
7c3df132 | 4538 | ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__); |
feafb7b1 AE |
4539 | |
4540 | spin_lock_irqsave(&ha->vport_slock, flags); | |
4541 | list_for_each_entry(vp, &ha->vp_list, list) { | |
4542 | if (vp->vp_idx) { | |
4543 | atomic_inc(&vp->vref_count); | |
4544 | spin_unlock_irqrestore(&ha->vport_slock, flags); | |
4545 | ||
e315cd28 | 4546 | qla2x00_vp_abort_isp(vp); |
feafb7b1 AE |
4547 | |
4548 | spin_lock_irqsave(&ha->vport_slock, flags); | |
4549 | atomic_dec(&vp->vref_count); | |
4550 | } | |
e315cd28 | 4551 | } |
feafb7b1 AE |
4552 | spin_unlock_irqrestore(&ha->vport_slock, flags); |
4553 | ||
7d613ac6 SV |
4554 | if (IS_QLA8031(ha)) { |
4555 | ql_dbg(ql_dbg_p3p, vha, 0xb05d, | |
4556 | "Setting back fcoe driver presence.\n"); | |
4557 | if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS) | |
4558 | ql_dbg(ql_dbg_p3p, vha, 0xb074, | |
4559 | "Error while setting DRV-Presence.\n"); | |
4560 | } | |
e315cd28 | 4561 | } else { |
d8424f68 JP |
4562 | ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n", |
4563 | __func__); | |
1da177e4 LT |
4564 | } |
4565 | ||
4566 | return(status); | |
4567 | } | |
4568 | ||
4569 | /* | |
4570 | * qla2x00_restart_isp | |
4571 | * restarts the ISP after a reset | |
4572 | * | |
4573 | * Input: | |
4574 | * ha = adapter block pointer. | |
4575 | * | |
4576 | * Returns: | |
4577 | * 0 = success | |
4578 | */ | |
4579 | static int | |
e315cd28 | 4580 | qla2x00_restart_isp(scsi_qla_host_t *vha) |
1da177e4 | 4581 | { |
c6b2fca8 | 4582 | int status = 0; |
1da177e4 | 4583 | uint32_t wait_time; |
e315cd28 | 4584 | struct qla_hw_data *ha = vha->hw; |
73208dfd AC |
4585 | struct req_que *req = ha->req_q_map[0]; |
4586 | struct rsp_que *rsp = ha->rsp_q_map[0]; | |
2d70c103 | 4587 | unsigned long flags; |
1da177e4 LT |
4588 | |
4589 | /* If firmware needs to be loaded */ | |
e315cd28 AC |
4590 | if (qla2x00_isp_firmware(vha)) { |
4591 | vha->flags.online = 0; | |
4592 | status = ha->isp_ops->chip_diag(vha); | |
4593 | if (!status) | |
4594 | status = qla2x00_setup_chip(vha); | |
1da177e4 LT |
4595 | } |
4596 | ||
e315cd28 AC |
4597 | if (!status && !(status = qla2x00_init_rings(vha))) { |
4598 | clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); | |
2533cf67 | 4599 | ha->flags.chip_reset_done = 1; |
73208dfd AC |
4600 | /* Initialize the queues in use */ |
4601 | qla25xx_init_queues(ha); | |
4602 | ||
e315cd28 AC |
4603 | status = qla2x00_fw_ready(vha); |
4604 | if (!status) { | |
7c3df132 SK |
4605 | ql_dbg(ql_dbg_taskm, vha, 0x8031, |
4606 | "Start configure loop status = %d.\n", status); | |
0107109e AV |
4607 | |
4608 | /* Issue a marker after FW becomes ready. */ | |
73208dfd | 4609 | qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL); |
0107109e | 4610 | |
e315cd28 | 4611 | vha->flags.online = 1; |
2d70c103 NB |
4612 | |
4613 | /* | |
4614 | * Process any ATIO queue entries that came in | |
4615 | * while we weren't online. | |
4616 | */ | |
4617 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
4618 | if (qla_tgt_mode_enabled(vha)) | |
4619 | qlt_24xx_process_atio_queue(vha); | |
4620 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
4621 | ||
1da177e4 LT |
4622 | /* Wait at most MAX_TARGET RSCNs for a stable link. */ |
4623 | wait_time = 256; | |
4624 | do { | |
e315cd28 AC |
4625 | clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); |
4626 | qla2x00_configure_loop(vha); | |
1da177e4 | 4627 | wait_time--; |
e315cd28 AC |
4628 | } while (!atomic_read(&vha->loop_down_timer) && |
4629 | !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) | |
4630 | && wait_time && (test_bit(LOOP_RESYNC_NEEDED, | |
4631 | &vha->dpc_flags))); | |
1da177e4 LT |
4632 | } |
4633 | ||
4634 | /* if no cable then assume it's good */ | |
e315cd28 | 4635 | if ((vha->device_flags & DFLG_NO_CABLE)) |
1da177e4 LT |
4636 | status = 0; |
4637 | ||
7c3df132 SK |
4638 | ql_dbg(ql_dbg_taskm, vha, 0x8032, |
4639 | "Configure loop done, status = 0x%x.\n", status); | |
1da177e4 LT |
4640 | } |
4641 | return (status); | |
4642 | } | |
4643 | ||
73208dfd AC |
4644 | static int |
4645 | qla25xx_init_queues(struct qla_hw_data *ha) | |
4646 | { | |
4647 | struct rsp_que *rsp = NULL; | |
4648 | struct req_que *req = NULL; | |
4649 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); | |
4650 | int ret = -1; | |
4651 | int i; | |
4652 | ||
2afa19a9 | 4653 | for (i = 1; i < ha->max_rsp_queues; i++) { |
73208dfd AC |
4654 | rsp = ha->rsp_q_map[i]; |
4655 | if (rsp) { | |
4656 | rsp->options &= ~BIT_0; | |
618a7523 | 4657 | ret = qla25xx_init_rsp_que(base_vha, rsp); |
73208dfd | 4658 | if (ret != QLA_SUCCESS) |
7c3df132 SK |
4659 | ql_dbg(ql_dbg_init, base_vha, 0x00ff, |
4660 | "%s Rsp que: %d init failed.\n", | |
4661 | __func__, rsp->id); | |
73208dfd | 4662 | else |
7c3df132 SK |
4663 | ql_dbg(ql_dbg_init, base_vha, 0x0100, |
4664 | "%s Rsp que: %d inited.\n", | |
4665 | __func__, rsp->id); | |
73208dfd | 4666 | } |
2afa19a9 AC |
4667 | } |
4668 | for (i = 1; i < ha->max_req_queues; i++) { | |
73208dfd AC |
4669 | req = ha->req_q_map[i]; |
4670 | if (req) { | |
29bdccbe | 4671 | /* Clear outstanding commands array. */ |
73208dfd | 4672 | req->options &= ~BIT_0; |
618a7523 | 4673 | ret = qla25xx_init_req_que(base_vha, req); |
73208dfd | 4674 | if (ret != QLA_SUCCESS) |
7c3df132 SK |
4675 | ql_dbg(ql_dbg_init, base_vha, 0x0101, |
4676 | "%s Req que: %d init failed.\n", | |
4677 | __func__, req->id); | |
73208dfd | 4678 | else |
7c3df132 SK |
4679 | ql_dbg(ql_dbg_init, base_vha, 0x0102, |
4680 | "%s Req que: %d inited.\n", | |
4681 | __func__, req->id); | |
73208dfd AC |
4682 | } |
4683 | } | |
4684 | return ret; | |
4685 | } | |
4686 | ||
1da177e4 LT |
4687 | /* |
4688 | * qla2x00_reset_adapter | |
4689 | * Reset adapter. | |
4690 | * | |
4691 | * Input: | |
4692 | * ha = adapter block pointer. | |
4693 | */ | |
abbd8870 | 4694 | void |
e315cd28 | 4695 | qla2x00_reset_adapter(scsi_qla_host_t *vha) |
1da177e4 LT |
4696 | { |
4697 | unsigned long flags = 0; | |
e315cd28 | 4698 | struct qla_hw_data *ha = vha->hw; |
3d71644c | 4699 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
1da177e4 | 4700 | |
e315cd28 | 4701 | vha->flags.online = 0; |
fd34f556 | 4702 | ha->isp_ops->disable_intrs(ha); |
1da177e4 | 4703 | |
1da177e4 LT |
4704 | spin_lock_irqsave(&ha->hardware_lock, flags); |
4705 | WRT_REG_WORD(®->hccr, HCCR_RESET_RISC); | |
4706 | RD_REG_WORD(®->hccr); /* PCI Posting. */ | |
4707 | WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); | |
4708 | RD_REG_WORD(®->hccr); /* PCI Posting. */ | |
4709 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
4710 | } | |
0107109e AV |
4711 | |
4712 | void | |
e315cd28 | 4713 | qla24xx_reset_adapter(scsi_qla_host_t *vha) |
0107109e AV |
4714 | { |
4715 | unsigned long flags = 0; | |
e315cd28 | 4716 | struct qla_hw_data *ha = vha->hw; |
0107109e AV |
4717 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
4718 | ||
a9083016 GM |
4719 | if (IS_QLA82XX(ha)) |
4720 | return; | |
4721 | ||
e315cd28 | 4722 | vha->flags.online = 0; |
fd34f556 | 4723 | ha->isp_ops->disable_intrs(ha); |
0107109e AV |
4724 | |
4725 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
4726 | WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_RESET); | |
4727 | RD_REG_DWORD(®->hccr); | |
4728 | WRT_REG_DWORD(®->hccr, HCCRX_REL_RISC_PAUSE); | |
4729 | RD_REG_DWORD(®->hccr); | |
4730 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
09ff36d3 AV |
4731 | |
4732 | if (IS_NOPOLLING_TYPE(ha)) | |
4733 | ha->isp_ops->enable_intrs(ha); | |
0107109e AV |
4734 | } |
4735 | ||
4e08df3f DM |
4736 | /* On sparc systems, obtain port and node WWN from firmware |
4737 | * properties. | |
4738 | */ | |
e315cd28 AC |
4739 | static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, |
4740 | struct nvram_24xx *nv) | |
4e08df3f DM |
4741 | { |
4742 | #ifdef CONFIG_SPARC | |
e315cd28 | 4743 | struct qla_hw_data *ha = vha->hw; |
4e08df3f | 4744 | struct pci_dev *pdev = ha->pdev; |
15576bc8 DM |
4745 | struct device_node *dp = pci_device_to_OF_node(pdev); |
4746 | const u8 *val; | |
4e08df3f DM |
4747 | int len; |
4748 | ||
4749 | val = of_get_property(dp, "port-wwn", &len); | |
4750 | if (val && len >= WWN_SIZE) | |
4751 | memcpy(nv->port_name, val, WWN_SIZE); | |
4752 | ||
4753 | val = of_get_property(dp, "node-wwn", &len); | |
4754 | if (val && len >= WWN_SIZE) | |
4755 | memcpy(nv->node_name, val, WWN_SIZE); | |
4756 | #endif | |
4757 | } | |
4758 | ||
0107109e | 4759 | int |
e315cd28 | 4760 | qla24xx_nvram_config(scsi_qla_host_t *vha) |
0107109e | 4761 | { |
4e08df3f | 4762 | int rval; |
0107109e AV |
4763 | struct init_cb_24xx *icb; |
4764 | struct nvram_24xx *nv; | |
4765 | uint32_t *dptr; | |
4766 | uint8_t *dptr1, *dptr2; | |
4767 | uint32_t chksum; | |
4768 | uint16_t cnt; | |
e315cd28 | 4769 | struct qla_hw_data *ha = vha->hw; |
0107109e | 4770 | |
4e08df3f | 4771 | rval = QLA_SUCCESS; |
0107109e | 4772 | icb = (struct init_cb_24xx *)ha->init_cb; |
281afe19 | 4773 | nv = ha->nvram; |
0107109e AV |
4774 | |
4775 | /* Determine NVRAM starting address. */ | |
e5b68a61 AC |
4776 | if (ha->flags.port0) { |
4777 | ha->nvram_base = FA_NVRAM_FUNC0_ADDR; | |
4778 | ha->vpd_base = FA_NVRAM_VPD0_ADDR; | |
4779 | } else { | |
0107109e | 4780 | ha->nvram_base = FA_NVRAM_FUNC1_ADDR; |
6f641790 AV |
4781 | ha->vpd_base = FA_NVRAM_VPD1_ADDR; |
4782 | } | |
e5b68a61 AC |
4783 | ha->nvram_size = sizeof(struct nvram_24xx); |
4784 | ha->vpd_size = FA_NVRAM_VPD_SIZE; | |
a9083016 GM |
4785 | if (IS_QLA82XX(ha)) |
4786 | ha->vpd_size = FA_VPD_SIZE_82XX; | |
0107109e | 4787 | |
281afe19 SJ |
4788 | /* Get VPD data into cache */ |
4789 | ha->vpd = ha->nvram + VPD_OFFSET; | |
e315cd28 | 4790 | ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd, |
281afe19 SJ |
4791 | ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4); |
4792 | ||
4793 | /* Get NVRAM data into cache and calculate checksum. */ | |
0107109e | 4794 | dptr = (uint32_t *)nv; |
e315cd28 | 4795 | ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base, |
0107109e AV |
4796 | ha->nvram_size); |
4797 | for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++) | |
4798 | chksum += le32_to_cpu(*dptr++); | |
4799 | ||
7c3df132 SK |
4800 | ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a, |
4801 | "Contents of NVRAM\n"); | |
4802 | ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d, | |
4803 | (uint8_t *)nv, ha->nvram_size); | |
0107109e AV |
4804 | |
4805 | /* Bad NVRAM data, set defaults parameters. */ | |
4806 | if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P' | |
4807 | || nv->id[3] != ' ' || | |
4808 | nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) { | |
4809 | /* Reset NVRAM data. */ | |
7c3df132 | 4810 | ql_log(ql_log_warn, vha, 0x006b, |
9e336520 | 4811 | "Inconsistent NVRAM detected: checksum=0x%x id=%c " |
7c3df132 SK |
4812 | "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version); |
4813 | ql_log(ql_log_warn, vha, 0x006c, | |
4814 | "Falling back to functioning (yet invalid -- WWPN) " | |
4815 | "defaults.\n"); | |
4e08df3f DM |
4816 | |
4817 | /* | |
4818 | * Set default initialization control block. | |
4819 | */ | |
4820 | memset(nv, 0, ha->nvram_size); | |
4821 | nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION); | |
4822 | nv->version = __constant_cpu_to_le16(ICB_VERSION); | |
4823 | nv->frame_payload_size = __constant_cpu_to_le16(2048); | |
4824 | nv->execution_throttle = __constant_cpu_to_le16(0xFFFF); | |
4825 | nv->exchange_count = __constant_cpu_to_le16(0); | |
4826 | nv->hard_address = __constant_cpu_to_le16(124); | |
4827 | nv->port_name[0] = 0x21; | |
e5b68a61 | 4828 | nv->port_name[1] = 0x00 + ha->port_no; |
4e08df3f DM |
4829 | nv->port_name[2] = 0x00; |
4830 | nv->port_name[3] = 0xe0; | |
4831 | nv->port_name[4] = 0x8b; | |
4832 | nv->port_name[5] = 0x1c; | |
4833 | nv->port_name[6] = 0x55; | |
4834 | nv->port_name[7] = 0x86; | |
4835 | nv->node_name[0] = 0x20; | |
4836 | nv->node_name[1] = 0x00; | |
4837 | nv->node_name[2] = 0x00; | |
4838 | nv->node_name[3] = 0xe0; | |
4839 | nv->node_name[4] = 0x8b; | |
4840 | nv->node_name[5] = 0x1c; | |
4841 | nv->node_name[6] = 0x55; | |
4842 | nv->node_name[7] = 0x86; | |
e315cd28 | 4843 | qla24xx_nvram_wwn_from_ofw(vha, nv); |
4e08df3f DM |
4844 | nv->login_retry_count = __constant_cpu_to_le16(8); |
4845 | nv->interrupt_delay_timer = __constant_cpu_to_le16(0); | |
4846 | nv->login_timeout = __constant_cpu_to_le16(0); | |
4847 | nv->firmware_options_1 = | |
4848 | __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1); | |
4849 | nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4); | |
4850 | nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12); | |
4851 | nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13); | |
4852 | nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10); | |
4853 | nv->efi_parameters = __constant_cpu_to_le32(0); | |
4854 | nv->reset_delay = 5; | |
4855 | nv->max_luns_per_target = __constant_cpu_to_le16(128); | |
4856 | nv->port_down_retry_count = __constant_cpu_to_le16(30); | |
4857 | nv->link_down_timeout = __constant_cpu_to_le16(30); | |
4858 | ||
4859 | rval = 1; | |
0107109e AV |
4860 | } |
4861 | ||
2d70c103 NB |
4862 | if (!qla_ini_mode_enabled(vha)) { |
4863 | /* Don't enable full login after initial LIP */ | |
4864 | nv->firmware_options_1 &= __constant_cpu_to_le32(~BIT_13); | |
4865 | /* Don't enable LIP full login for initiator */ | |
4866 | nv->host_p &= __constant_cpu_to_le32(~BIT_10); | |
4867 | } | |
4868 | ||
4869 | qlt_24xx_config_nvram_stage1(vha, nv); | |
4870 | ||
0107109e | 4871 | /* Reset Initialization control block */ |
e315cd28 | 4872 | memset(icb, 0, ha->init_cb_size); |
0107109e AV |
4873 | |
4874 | /* Copy 1st segment. */ | |
4875 | dptr1 = (uint8_t *)icb; | |
4876 | dptr2 = (uint8_t *)&nv->version; | |
4877 | cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version; | |
4878 | while (cnt--) | |
4879 | *dptr1++ = *dptr2++; | |
4880 | ||
4881 | icb->login_retry_count = nv->login_retry_count; | |
3ea66e28 | 4882 | icb->link_down_on_nos = nv->link_down_on_nos; |
0107109e AV |
4883 | |
4884 | /* Copy 2nd segment. */ | |
4885 | dptr1 = (uint8_t *)&icb->interrupt_delay_timer; | |
4886 | dptr2 = (uint8_t *)&nv->interrupt_delay_timer; | |
4887 | cnt = (uint8_t *)&icb->reserved_3 - | |
4888 | (uint8_t *)&icb->interrupt_delay_timer; | |
4889 | while (cnt--) | |
4890 | *dptr1++ = *dptr2++; | |
4891 | ||
4892 | /* | |
4893 | * Setup driver NVRAM options. | |
4894 | */ | |
e315cd28 | 4895 | qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name), |
9bb9fcf2 | 4896 | "QLA2462"); |
0107109e | 4897 | |
2d70c103 NB |
4898 | qlt_24xx_config_nvram_stage2(vha, icb); |
4899 | ||
5341e868 | 4900 | if (nv->host_p & __constant_cpu_to_le32(BIT_15)) { |
2d70c103 | 4901 | /* Use alternate WWN? */ |
5341e868 AV |
4902 | memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE); |
4903 | memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE); | |
4904 | } | |
4905 | ||
0107109e | 4906 | /* Prepare nodename */ |
fd0e7e4d | 4907 | if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) { |
0107109e AV |
4908 | /* |
4909 | * Firmware will apply the following mask if the nodename was | |
4910 | * not provided. | |
4911 | */ | |
4912 | memcpy(icb->node_name, icb->port_name, WWN_SIZE); | |
4913 | icb->node_name[0] &= 0xF0; | |
4914 | } | |
4915 | ||
4916 | /* Set host adapter parameters. */ | |
4917 | ha->flags.disable_risc_code_load = 0; | |
0c8c39af AV |
4918 | ha->flags.enable_lip_reset = 0; |
4919 | ha->flags.enable_lip_full_login = | |
4920 | le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0; | |
4921 | ha->flags.enable_target_reset = | |
4922 | le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0; | |
0107109e | 4923 | ha->flags.enable_led_scheme = 0; |
d4c760c2 | 4924 | ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0; |
0107109e | 4925 | |
fd0e7e4d AV |
4926 | ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) & |
4927 | (BIT_6 | BIT_5 | BIT_4)) >> 4; | |
0107109e AV |
4928 | |
4929 | memcpy(ha->fw_seriallink_options24, nv->seriallink_options, | |
4930 | sizeof(ha->fw_seriallink_options24)); | |
4931 | ||
4932 | /* save HBA serial number */ | |
4933 | ha->serial0 = icb->port_name[5]; | |
4934 | ha->serial1 = icb->port_name[6]; | |
4935 | ha->serial2 = icb->port_name[7]; | |
e315cd28 AC |
4936 | memcpy(vha->node_name, icb->node_name, WWN_SIZE); |
4937 | memcpy(vha->port_name, icb->port_name, WWN_SIZE); | |
0107109e | 4938 | |
bc8fb3cb AV |
4939 | icb->execution_throttle = __constant_cpu_to_le16(0xFFFF); |
4940 | ||
0107109e AV |
4941 | ha->retry_count = le16_to_cpu(nv->login_retry_count); |
4942 | ||
4943 | /* Set minimum login_timeout to 4 seconds. */ | |
4944 | if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout) | |
4945 | nv->login_timeout = cpu_to_le16(ql2xlogintimeout); | |
4946 | if (le16_to_cpu(nv->login_timeout) < 4) | |
4947 | nv->login_timeout = __constant_cpu_to_le16(4); | |
4948 | ha->login_timeout = le16_to_cpu(nv->login_timeout); | |
c6852c4c | 4949 | icb->login_timeout = nv->login_timeout; |
0107109e | 4950 | |
00a537b8 AV |
4951 | /* Set minimum RATOV to 100 tenths of a second. */ |
4952 | ha->r_a_tov = 100; | |
0107109e AV |
4953 | |
4954 | ha->loop_reset_delay = nv->reset_delay; | |
4955 | ||
4956 | /* Link Down Timeout = 0: | |
4957 | * | |
4958 | * When Port Down timer expires we will start returning | |
4959 | * I/O's to OS with "DID_NO_CONNECT". | |
4960 | * | |
4961 | * Link Down Timeout != 0: | |
4962 | * | |
4963 | * The driver waits for the link to come up after link down | |
4964 | * before returning I/Os to OS with "DID_NO_CONNECT". | |
4965 | */ | |
4966 | if (le16_to_cpu(nv->link_down_timeout) == 0) { | |
4967 | ha->loop_down_abort_time = | |
4968 | (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT); | |
4969 | } else { | |
4970 | ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout); | |
4971 | ha->loop_down_abort_time = | |
4972 | (LOOP_DOWN_TIME - ha->link_down_timeout); | |
4973 | } | |
4974 | ||
4975 | /* Need enough time to try and get the port back. */ | |
4976 | ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count); | |
4977 | if (qlport_down_retry) | |
4978 | ha->port_down_retry_count = qlport_down_retry; | |
4979 | ||
4980 | /* Set login_retry_count */ | |
4981 | ha->login_retry_count = le16_to_cpu(nv->login_retry_count); | |
4982 | if (ha->port_down_retry_count == | |
4983 | le16_to_cpu(nv->port_down_retry_count) && | |
4984 | ha->port_down_retry_count > 3) | |
4985 | ha->login_retry_count = ha->port_down_retry_count; | |
4986 | else if (ha->port_down_retry_count > (int)ha->login_retry_count) | |
4987 | ha->login_retry_count = ha->port_down_retry_count; | |
4988 | if (ql2xloginretrycount) | |
4989 | ha->login_retry_count = ql2xloginretrycount; | |
4990 | ||
4fdfefe5 | 4991 | /* Enable ZIO. */ |
e315cd28 | 4992 | if (!vha->flags.init_done) { |
4fdfefe5 AV |
4993 | ha->zio_mode = le32_to_cpu(icb->firmware_options_2) & |
4994 | (BIT_3 | BIT_2 | BIT_1 | BIT_0); | |
4995 | ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ? | |
4996 | le16_to_cpu(icb->interrupt_delay_timer): 2; | |
4997 | } | |
4998 | icb->firmware_options_2 &= __constant_cpu_to_le32( | |
4999 | ~(BIT_3 | BIT_2 | BIT_1 | BIT_0)); | |
e315cd28 | 5000 | vha->flags.process_response_queue = 0; |
4fdfefe5 | 5001 | if (ha->zio_mode != QLA_ZIO_DISABLED) { |
4a59f71d AV |
5002 | ha->zio_mode = QLA_ZIO_MODE_6; |
5003 | ||
7c3df132 | 5004 | ql_log(ql_log_info, vha, 0x006f, |
4fdfefe5 AV |
5005 | "ZIO mode %d enabled; timer delay (%d us).\n", |
5006 | ha->zio_mode, ha->zio_timer * 100); | |
5007 | ||
5008 | icb->firmware_options_2 |= cpu_to_le32( | |
5009 | (uint32_t)ha->zio_mode); | |
5010 | icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer); | |
e315cd28 | 5011 | vha->flags.process_response_queue = 1; |
4fdfefe5 AV |
5012 | } |
5013 | ||
4e08df3f | 5014 | if (rval) { |
7c3df132 SK |
5015 | ql_log(ql_log_warn, vha, 0x0070, |
5016 | "NVRAM configuration failed.\n"); | |
4e08df3f DM |
5017 | } |
5018 | return (rval); | |
0107109e AV |
5019 | } |
5020 | ||
413975a0 | 5021 | static int |
cbc8eb67 AV |
5022 | qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr, |
5023 | uint32_t faddr) | |
d1c61909 | 5024 | { |
73208dfd | 5025 | int rval = QLA_SUCCESS; |
d1c61909 | 5026 | int segments, fragment; |
d1c61909 AV |
5027 | uint32_t *dcode, dlen; |
5028 | uint32_t risc_addr; | |
5029 | uint32_t risc_size; | |
5030 | uint32_t i; | |
e315cd28 | 5031 | struct qla_hw_data *ha = vha->hw; |
73208dfd | 5032 | struct req_que *req = ha->req_q_map[0]; |
eaac30be | 5033 | |
7c3df132 | 5034 | ql_dbg(ql_dbg_init, vha, 0x008b, |
cfb0919c | 5035 | "FW: Loading firmware from flash (%x).\n", faddr); |
eaac30be | 5036 | |
d1c61909 AV |
5037 | rval = QLA_SUCCESS; |
5038 | ||
5039 | segments = FA_RISC_CODE_SEGMENTS; | |
73208dfd | 5040 | dcode = (uint32_t *)req->ring; |
d1c61909 AV |
5041 | *srisc_addr = 0; |
5042 | ||
5043 | /* Validate firmware image by checking version. */ | |
e315cd28 | 5044 | qla24xx_read_flash_data(vha, dcode, faddr + 4, 4); |
d1c61909 AV |
5045 | for (i = 0; i < 4; i++) |
5046 | dcode[i] = be32_to_cpu(dcode[i]); | |
5047 | if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff && | |
5048 | dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) || | |
5049 | (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 && | |
5050 | dcode[3] == 0)) { | |
7c3df132 SK |
5051 | ql_log(ql_log_fatal, vha, 0x008c, |
5052 | "Unable to verify the integrity of flash firmware " | |
5053 | "image.\n"); | |
5054 | ql_log(ql_log_fatal, vha, 0x008d, | |
5055 | "Firmware data: %08x %08x %08x %08x.\n", | |
5056 | dcode[0], dcode[1], dcode[2], dcode[3]); | |
d1c61909 AV |
5057 | |
5058 | return QLA_FUNCTION_FAILED; | |
5059 | } | |
5060 | ||
5061 | while (segments && rval == QLA_SUCCESS) { | |
5062 | /* Read segment's load information. */ | |
e315cd28 | 5063 | qla24xx_read_flash_data(vha, dcode, faddr, 4); |
d1c61909 AV |
5064 | |
5065 | risc_addr = be32_to_cpu(dcode[2]); | |
5066 | *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr; | |
5067 | risc_size = be32_to_cpu(dcode[3]); | |
5068 | ||
5069 | fragment = 0; | |
5070 | while (risc_size > 0 && rval == QLA_SUCCESS) { | |
5071 | dlen = (uint32_t)(ha->fw_transfer_size >> 2); | |
5072 | if (dlen > risc_size) | |
5073 | dlen = risc_size; | |
5074 | ||
7c3df132 SK |
5075 | ql_dbg(ql_dbg_init, vha, 0x008e, |
5076 | "Loading risc segment@ risc addr %x " | |
5077 | "number of dwords 0x%x offset 0x%x.\n", | |
5078 | risc_addr, dlen, faddr); | |
d1c61909 | 5079 | |
e315cd28 | 5080 | qla24xx_read_flash_data(vha, dcode, faddr, dlen); |
d1c61909 AV |
5081 | for (i = 0; i < dlen; i++) |
5082 | dcode[i] = swab32(dcode[i]); | |
5083 | ||
73208dfd | 5084 | rval = qla2x00_load_ram(vha, req->dma, risc_addr, |
d1c61909 AV |
5085 | dlen); |
5086 | if (rval) { | |
7c3df132 SK |
5087 | ql_log(ql_log_fatal, vha, 0x008f, |
5088 | "Failed to load segment %d of firmware.\n", | |
5089 | fragment); | |
d1c61909 AV |
5090 | break; |
5091 | } | |
5092 | ||
5093 | faddr += dlen; | |
5094 | risc_addr += dlen; | |
5095 | risc_size -= dlen; | |
5096 | fragment++; | |
5097 | } | |
5098 | ||
5099 | /* Next segment. */ | |
5100 | segments--; | |
5101 | } | |
5102 | ||
5103 | return rval; | |
5104 | } | |
5105 | ||
e9454a88 | 5106 | #define QLA_FW_URL "http://ldriver.qlogic.com/firmware/" |
d1c61909 | 5107 | |
0107109e | 5108 | int |
e315cd28 | 5109 | qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) |
5433383e AV |
5110 | { |
5111 | int rval; | |
5112 | int i, fragment; | |
5113 | uint16_t *wcode, *fwcode; | |
5114 | uint32_t risc_addr, risc_size, fwclen, wlen, *seg; | |
5115 | struct fw_blob *blob; | |
e315cd28 | 5116 | struct qla_hw_data *ha = vha->hw; |
73208dfd | 5117 | struct req_que *req = ha->req_q_map[0]; |
5433383e AV |
5118 | |
5119 | /* Load firmware blob. */ | |
e315cd28 | 5120 | blob = qla2x00_request_firmware(vha); |
5433383e | 5121 | if (!blob) { |
7c3df132 SK |
5122 | ql_log(ql_log_info, vha, 0x0083, |
5123 | "Fimware image unavailable.\n"); | |
5124 | ql_log(ql_log_info, vha, 0x0084, | |
5125 | "Firmware images can be retrieved from: "QLA_FW_URL ".\n"); | |
5433383e AV |
5126 | return QLA_FUNCTION_FAILED; |
5127 | } | |
5128 | ||
5129 | rval = QLA_SUCCESS; | |
5130 | ||
73208dfd | 5131 | wcode = (uint16_t *)req->ring; |
5433383e AV |
5132 | *srisc_addr = 0; |
5133 | fwcode = (uint16_t *)blob->fw->data; | |
5134 | fwclen = 0; | |
5135 | ||
5136 | /* Validate firmware image by checking version. */ | |
5137 | if (blob->fw->size < 8 * sizeof(uint16_t)) { | |
7c3df132 SK |
5138 | ql_log(ql_log_fatal, vha, 0x0085, |
5139 | "Unable to verify integrity of firmware image (%Zd).\n", | |
5433383e AV |
5140 | blob->fw->size); |
5141 | goto fail_fw_integrity; | |
5142 | } | |
5143 | for (i = 0; i < 4; i++) | |
5144 | wcode[i] = be16_to_cpu(fwcode[i + 4]); | |
5145 | if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff && | |
5146 | wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 && | |
5147 | wcode[2] == 0 && wcode[3] == 0)) { | |
7c3df132 SK |
5148 | ql_log(ql_log_fatal, vha, 0x0086, |
5149 | "Unable to verify integrity of firmware image.\n"); | |
5150 | ql_log(ql_log_fatal, vha, 0x0087, | |
5151 | "Firmware data: %04x %04x %04x %04x.\n", | |
5152 | wcode[0], wcode[1], wcode[2], wcode[3]); | |
5433383e AV |
5153 | goto fail_fw_integrity; |
5154 | } | |
5155 | ||
5156 | seg = blob->segs; | |
5157 | while (*seg && rval == QLA_SUCCESS) { | |
5158 | risc_addr = *seg; | |
5159 | *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr; | |
5160 | risc_size = be16_to_cpu(fwcode[3]); | |
5161 | ||
5162 | /* Validate firmware image size. */ | |
5163 | fwclen += risc_size * sizeof(uint16_t); | |
5164 | if (blob->fw->size < fwclen) { | |
7c3df132 | 5165 | ql_log(ql_log_fatal, vha, 0x0088, |
5433383e | 5166 | "Unable to verify integrity of firmware image " |
7c3df132 | 5167 | "(%Zd).\n", blob->fw->size); |
5433383e AV |
5168 | goto fail_fw_integrity; |
5169 | } | |
5170 | ||
5171 | fragment = 0; | |
5172 | while (risc_size > 0 && rval == QLA_SUCCESS) { | |
5173 | wlen = (uint16_t)(ha->fw_transfer_size >> 1); | |
5174 | if (wlen > risc_size) | |
5175 | wlen = risc_size; | |
7c3df132 SK |
5176 | ql_dbg(ql_dbg_init, vha, 0x0089, |
5177 | "Loading risc segment@ risc addr %x number of " | |
5178 | "words 0x%x.\n", risc_addr, wlen); | |
5433383e AV |
5179 | |
5180 | for (i = 0; i < wlen; i++) | |
5181 | wcode[i] = swab16(fwcode[i]); | |
5182 | ||
73208dfd | 5183 | rval = qla2x00_load_ram(vha, req->dma, risc_addr, |
5433383e AV |
5184 | wlen); |
5185 | if (rval) { | |
7c3df132 SK |
5186 | ql_log(ql_log_fatal, vha, 0x008a, |
5187 | "Failed to load segment %d of firmware.\n", | |
5188 | fragment); | |
5433383e AV |
5189 | break; |
5190 | } | |
5191 | ||
5192 | fwcode += wlen; | |
5193 | risc_addr += wlen; | |
5194 | risc_size -= wlen; | |
5195 | fragment++; | |
5196 | } | |
5197 | ||
5198 | /* Next segment. */ | |
5199 | seg++; | |
5200 | } | |
5201 | return rval; | |
5202 | ||
5203 | fail_fw_integrity: | |
5204 | return QLA_FUNCTION_FAILED; | |
5205 | } | |
5206 | ||
eaac30be AV |
5207 | static int |
5208 | qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr) | |
0107109e AV |
5209 | { |
5210 | int rval; | |
5211 | int segments, fragment; | |
5212 | uint32_t *dcode, dlen; | |
5213 | uint32_t risc_addr; | |
5214 | uint32_t risc_size; | |
5215 | uint32_t i; | |
5433383e | 5216 | struct fw_blob *blob; |
0107109e | 5217 | uint32_t *fwcode, fwclen; |
e315cd28 | 5218 | struct qla_hw_data *ha = vha->hw; |
73208dfd | 5219 | struct req_que *req = ha->req_q_map[0]; |
0107109e | 5220 | |
5433383e | 5221 | /* Load firmware blob. */ |
e315cd28 | 5222 | blob = qla2x00_request_firmware(vha); |
5433383e | 5223 | if (!blob) { |
7c3df132 SK |
5224 | ql_log(ql_log_warn, vha, 0x0090, |
5225 | "Fimware image unavailable.\n"); | |
5226 | ql_log(ql_log_warn, vha, 0x0091, | |
5227 | "Firmware images can be retrieved from: " | |
5228 | QLA_FW_URL ".\n"); | |
d1c61909 | 5229 | |
eaac30be | 5230 | return QLA_FUNCTION_FAILED; |
0107109e AV |
5231 | } |
5232 | ||
cfb0919c CD |
5233 | ql_dbg(ql_dbg_init, vha, 0x0092, |
5234 | "FW: Loading via request-firmware.\n"); | |
eaac30be | 5235 | |
0107109e AV |
5236 | rval = QLA_SUCCESS; |
5237 | ||
5238 | segments = FA_RISC_CODE_SEGMENTS; | |
73208dfd | 5239 | dcode = (uint32_t *)req->ring; |
0107109e | 5240 | *srisc_addr = 0; |
5433383e | 5241 | fwcode = (uint32_t *)blob->fw->data; |
0107109e AV |
5242 | fwclen = 0; |
5243 | ||
5244 | /* Validate firmware image by checking version. */ | |
5433383e | 5245 | if (blob->fw->size < 8 * sizeof(uint32_t)) { |
7c3df132 SK |
5246 | ql_log(ql_log_fatal, vha, 0x0093, |
5247 | "Unable to verify integrity of firmware image (%Zd).\n", | |
5433383e | 5248 | blob->fw->size); |
0107109e AV |
5249 | goto fail_fw_integrity; |
5250 | } | |
5251 | for (i = 0; i < 4; i++) | |
5252 | dcode[i] = be32_to_cpu(fwcode[i + 4]); | |
5253 | if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff && | |
5254 | dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) || | |
5255 | (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 && | |
5256 | dcode[3] == 0)) { | |
7c3df132 SK |
5257 | ql_log(ql_log_fatal, vha, 0x0094, |
5258 | "Unable to verify integrity of firmware image (%Zd).\n", | |
5259 | blob->fw->size); | |
5260 | ql_log(ql_log_fatal, vha, 0x0095, | |
5261 | "Firmware data: %08x %08x %08x %08x.\n", | |
5262 | dcode[0], dcode[1], dcode[2], dcode[3]); | |
0107109e AV |
5263 | goto fail_fw_integrity; |
5264 | } | |
5265 | ||
5266 | while (segments && rval == QLA_SUCCESS) { | |
5267 | risc_addr = be32_to_cpu(fwcode[2]); | |
5268 | *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr; | |
5269 | risc_size = be32_to_cpu(fwcode[3]); | |
5270 | ||
5271 | /* Validate firmware image size. */ | |
5272 | fwclen += risc_size * sizeof(uint32_t); | |
5433383e | 5273 | if (blob->fw->size < fwclen) { |
7c3df132 | 5274 | ql_log(ql_log_fatal, vha, 0x0096, |
5433383e | 5275 | "Unable to verify integrity of firmware image " |
7c3df132 | 5276 | "(%Zd).\n", blob->fw->size); |
5433383e | 5277 | |
0107109e AV |
5278 | goto fail_fw_integrity; |
5279 | } | |
5280 | ||
5281 | fragment = 0; | |
5282 | while (risc_size > 0 && rval == QLA_SUCCESS) { | |
5283 | dlen = (uint32_t)(ha->fw_transfer_size >> 2); | |
5284 | if (dlen > risc_size) | |
5285 | dlen = risc_size; | |
5286 | ||
7c3df132 SK |
5287 | ql_dbg(ql_dbg_init, vha, 0x0097, |
5288 | "Loading risc segment@ risc addr %x " | |
5289 | "number of dwords 0x%x.\n", risc_addr, dlen); | |
0107109e AV |
5290 | |
5291 | for (i = 0; i < dlen; i++) | |
5292 | dcode[i] = swab32(fwcode[i]); | |
5293 | ||
73208dfd | 5294 | rval = qla2x00_load_ram(vha, req->dma, risc_addr, |
590f98e5 | 5295 | dlen); |
0107109e | 5296 | if (rval) { |
7c3df132 SK |
5297 | ql_log(ql_log_fatal, vha, 0x0098, |
5298 | "Failed to load segment %d of firmware.\n", | |
5299 | fragment); | |
0107109e AV |
5300 | break; |
5301 | } | |
5302 | ||
5303 | fwcode += dlen; | |
5304 | risc_addr += dlen; | |
5305 | risc_size -= dlen; | |
5306 | fragment++; | |
5307 | } | |
5308 | ||
5309 | /* Next segment. */ | |
5310 | segments--; | |
5311 | } | |
0107109e AV |
5312 | return rval; |
5313 | ||
5314 | fail_fw_integrity: | |
0107109e | 5315 | return QLA_FUNCTION_FAILED; |
0107109e | 5316 | } |
18c6c127 | 5317 | |
eaac30be AV |
5318 | int |
5319 | qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) | |
5320 | { | |
5321 | int rval; | |
5322 | ||
e337d907 AV |
5323 | if (ql2xfwloadbin == 1) |
5324 | return qla81xx_load_risc(vha, srisc_addr); | |
5325 | ||
eaac30be AV |
5326 | /* |
5327 | * FW Load priority: | |
5328 | * 1) Firmware via request-firmware interface (.bin file). | |
5329 | * 2) Firmware residing in flash. | |
5330 | */ | |
5331 | rval = qla24xx_load_risc_blob(vha, srisc_addr); | |
5332 | if (rval == QLA_SUCCESS) | |
5333 | return rval; | |
5334 | ||
cbc8eb67 AV |
5335 | return qla24xx_load_risc_flash(vha, srisc_addr, |
5336 | vha->hw->flt_region_fw); | |
eaac30be AV |
5337 | } |
5338 | ||
5339 | int | |
5340 | qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) | |
5341 | { | |
5342 | int rval; | |
cbc8eb67 | 5343 | struct qla_hw_data *ha = vha->hw; |
eaac30be | 5344 | |
e337d907 | 5345 | if (ql2xfwloadbin == 2) |
cbc8eb67 | 5346 | goto try_blob_fw; |
e337d907 | 5347 | |
eaac30be AV |
5348 | /* |
5349 | * FW Load priority: | |
5350 | * 1) Firmware residing in flash. | |
5351 | * 2) Firmware via request-firmware interface (.bin file). | |
cbc8eb67 | 5352 | * 3) Golden-Firmware residing in flash -- limited operation. |
eaac30be | 5353 | */ |
cbc8eb67 | 5354 | rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw); |
eaac30be AV |
5355 | if (rval == QLA_SUCCESS) |
5356 | return rval; | |
5357 | ||
cbc8eb67 AV |
5358 | try_blob_fw: |
5359 | rval = qla24xx_load_risc_blob(vha, srisc_addr); | |
5360 | if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw) | |
5361 | return rval; | |
5362 | ||
7c3df132 SK |
5363 | ql_log(ql_log_info, vha, 0x0099, |
5364 | "Attempting to fallback to golden firmware.\n"); | |
cbc8eb67 AV |
5365 | rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw); |
5366 | if (rval != QLA_SUCCESS) | |
5367 | return rval; | |
5368 | ||
7c3df132 | 5369 | ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n"); |
cbc8eb67 | 5370 | ha->flags.running_gold_fw = 1; |
cbc8eb67 | 5371 | return rval; |
eaac30be AV |
5372 | } |
5373 | ||
18c6c127 | 5374 | void |
e315cd28 | 5375 | qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha) |
18c6c127 AV |
5376 | { |
5377 | int ret, retries; | |
e315cd28 | 5378 | struct qla_hw_data *ha = vha->hw; |
18c6c127 | 5379 | |
85880801 AV |
5380 | if (ha->flags.pci_channel_io_perm_failure) |
5381 | return; | |
e428924c | 5382 | if (!IS_FWI2_CAPABLE(ha)) |
18c6c127 | 5383 | return; |
75edf81d AV |
5384 | if (!ha->fw_major_version) |
5385 | return; | |
18c6c127 | 5386 | |
e315cd28 | 5387 | ret = qla2x00_stop_firmware(vha); |
7c7f1f29 | 5388 | for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT && |
b469a7cb | 5389 | ret != QLA_INVALID_COMMAND && retries ; retries--) { |
e315cd28 AC |
5390 | ha->isp_ops->reset_chip(vha); |
5391 | if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS) | |
18c6c127 | 5392 | continue; |
e315cd28 | 5393 | if (qla2x00_setup_chip(vha) != QLA_SUCCESS) |
18c6c127 | 5394 | continue; |
7c3df132 SK |
5395 | ql_log(ql_log_info, vha, 0x8015, |
5396 | "Attempting retry of stop-firmware command.\n"); | |
e315cd28 | 5397 | ret = qla2x00_stop_firmware(vha); |
18c6c127 AV |
5398 | } |
5399 | } | |
2c3dfe3f SJ |
5400 | |
5401 | int | |
e315cd28 | 5402 | qla24xx_configure_vhba(scsi_qla_host_t *vha) |
2c3dfe3f SJ |
5403 | { |
5404 | int rval = QLA_SUCCESS; | |
0b91d116 | 5405 | int rval2; |
2c3dfe3f | 5406 | uint16_t mb[MAILBOX_REGISTER_COUNT]; |
e315cd28 AC |
5407 | struct qla_hw_data *ha = vha->hw; |
5408 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); | |
67c2e93a AC |
5409 | struct req_que *req; |
5410 | struct rsp_que *rsp; | |
2c3dfe3f | 5411 | |
e315cd28 | 5412 | if (!vha->vp_idx) |
2c3dfe3f SJ |
5413 | return -EINVAL; |
5414 | ||
e315cd28 | 5415 | rval = qla2x00_fw_ready(base_vha); |
7163ea81 | 5416 | if (ha->flags.cpu_affinity_enabled) |
67c2e93a AC |
5417 | req = ha->req_q_map[0]; |
5418 | else | |
5419 | req = vha->req; | |
5420 | rsp = req->rsp; | |
5421 | ||
2c3dfe3f | 5422 | if (rval == QLA_SUCCESS) { |
e315cd28 | 5423 | clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); |
73208dfd | 5424 | qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL); |
2c3dfe3f SJ |
5425 | } |
5426 | ||
e315cd28 | 5427 | vha->flags.management_server_logged_in = 0; |
2c3dfe3f SJ |
5428 | |
5429 | /* Login to SNS first */ | |
0b91d116 CD |
5430 | rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb, |
5431 | BIT_1); | |
5432 | if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) { | |
5433 | if (rval2 == QLA_MEMORY_ALLOC_FAILED) | |
5434 | ql_dbg(ql_dbg_init, vha, 0x0120, | |
5435 | "Failed SNS login: loop_id=%x, rval2=%d\n", | |
5436 | NPH_SNS, rval2); | |
5437 | else | |
5438 | ql_dbg(ql_dbg_init, vha, 0x0103, | |
5439 | "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x " | |
5440 | "mb[2]=%x mb[6]=%x mb[7]=%x.\n", | |
5441 | NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]); | |
2c3dfe3f SJ |
5442 | return (QLA_FUNCTION_FAILED); |
5443 | } | |
5444 | ||
e315cd28 AC |
5445 | atomic_set(&vha->loop_down_timer, 0); |
5446 | atomic_set(&vha->loop_state, LOOP_UP); | |
5447 | set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); | |
5448 | set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); | |
5449 | rval = qla2x00_loop_resync(base_vha); | |
2c3dfe3f SJ |
5450 | |
5451 | return rval; | |
5452 | } | |
4d4df193 HK |
5453 | |
5454 | /* 84XX Support **************************************************************/ | |
5455 | ||
5456 | static LIST_HEAD(qla_cs84xx_list); | |
5457 | static DEFINE_MUTEX(qla_cs84xx_mutex); | |
5458 | ||
5459 | static struct qla_chip_state_84xx * | |
e315cd28 | 5460 | qla84xx_get_chip(struct scsi_qla_host *vha) |
4d4df193 HK |
5461 | { |
5462 | struct qla_chip_state_84xx *cs84xx; | |
e315cd28 | 5463 | struct qla_hw_data *ha = vha->hw; |
4d4df193 HK |
5464 | |
5465 | mutex_lock(&qla_cs84xx_mutex); | |
5466 | ||
5467 | /* Find any shared 84xx chip. */ | |
5468 | list_for_each_entry(cs84xx, &qla_cs84xx_list, list) { | |
5469 | if (cs84xx->bus == ha->pdev->bus) { | |
5470 | kref_get(&cs84xx->kref); | |
5471 | goto done; | |
5472 | } | |
5473 | } | |
5474 | ||
5475 | cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL); | |
5476 | if (!cs84xx) | |
5477 | goto done; | |
5478 | ||
5479 | kref_init(&cs84xx->kref); | |
5480 | spin_lock_init(&cs84xx->access_lock); | |
5481 | mutex_init(&cs84xx->fw_update_mutex); | |
5482 | cs84xx->bus = ha->pdev->bus; | |
5483 | ||
5484 | list_add_tail(&cs84xx->list, &qla_cs84xx_list); | |
5485 | done: | |
5486 | mutex_unlock(&qla_cs84xx_mutex); | |
5487 | return cs84xx; | |
5488 | } | |
5489 | ||
5490 | static void | |
5491 | __qla84xx_chip_release(struct kref *kref) | |
5492 | { | |
5493 | struct qla_chip_state_84xx *cs84xx = | |
5494 | container_of(kref, struct qla_chip_state_84xx, kref); | |
5495 | ||
5496 | mutex_lock(&qla_cs84xx_mutex); | |
5497 | list_del(&cs84xx->list); | |
5498 | mutex_unlock(&qla_cs84xx_mutex); | |
5499 | kfree(cs84xx); | |
5500 | } | |
5501 | ||
5502 | void | |
e315cd28 | 5503 | qla84xx_put_chip(struct scsi_qla_host *vha) |
4d4df193 | 5504 | { |
e315cd28 | 5505 | struct qla_hw_data *ha = vha->hw; |
4d4df193 HK |
5506 | if (ha->cs84xx) |
5507 | kref_put(&ha->cs84xx->kref, __qla84xx_chip_release); | |
5508 | } | |
5509 | ||
5510 | static int | |
e315cd28 | 5511 | qla84xx_init_chip(scsi_qla_host_t *vha) |
4d4df193 HK |
5512 | { |
5513 | int rval; | |
5514 | uint16_t status[2]; | |
e315cd28 | 5515 | struct qla_hw_data *ha = vha->hw; |
4d4df193 HK |
5516 | |
5517 | mutex_lock(&ha->cs84xx->fw_update_mutex); | |
5518 | ||
e315cd28 | 5519 | rval = qla84xx_verify_chip(vha, status); |
4d4df193 HK |
5520 | |
5521 | mutex_unlock(&ha->cs84xx->fw_update_mutex); | |
5522 | ||
5523 | return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED: | |
5524 | QLA_SUCCESS; | |
5525 | } | |
3a03eb79 AV |
5526 | |
5527 | /* 81XX Support **************************************************************/ | |
5528 | ||
5529 | int | |
5530 | qla81xx_nvram_config(scsi_qla_host_t *vha) | |
5531 | { | |
5532 | int rval; | |
5533 | struct init_cb_81xx *icb; | |
5534 | struct nvram_81xx *nv; | |
5535 | uint32_t *dptr; | |
5536 | uint8_t *dptr1, *dptr2; | |
5537 | uint32_t chksum; | |
5538 | uint16_t cnt; | |
5539 | struct qla_hw_data *ha = vha->hw; | |
5540 | ||
5541 | rval = QLA_SUCCESS; | |
5542 | icb = (struct init_cb_81xx *)ha->init_cb; | |
5543 | nv = ha->nvram; | |
5544 | ||
5545 | /* Determine NVRAM starting address. */ | |
5546 | ha->nvram_size = sizeof(struct nvram_81xx); | |
3a03eb79 | 5547 | ha->vpd_size = FA_NVRAM_VPD_SIZE; |
3a03eb79 AV |
5548 | |
5549 | /* Get VPD data into cache */ | |
5550 | ha->vpd = ha->nvram + VPD_OFFSET; | |
3d79038f AV |
5551 | ha->isp_ops->read_optrom(vha, ha->vpd, ha->flt_region_vpd << 2, |
5552 | ha->vpd_size); | |
3a03eb79 AV |
5553 | |
5554 | /* Get NVRAM data into cache and calculate checksum. */ | |
3d79038f | 5555 | ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2, |
3a03eb79 | 5556 | ha->nvram_size); |
3d79038f | 5557 | dptr = (uint32_t *)nv; |
3a03eb79 AV |
5558 | for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++) |
5559 | chksum += le32_to_cpu(*dptr++); | |
5560 | ||
7c3df132 SK |
5561 | ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111, |
5562 | "Contents of NVRAM:\n"); | |
5563 | ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112, | |
5564 | (uint8_t *)nv, ha->nvram_size); | |
3a03eb79 AV |
5565 | |
5566 | /* Bad NVRAM data, set defaults parameters. */ | |
5567 | if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P' | |
5568 | || nv->id[3] != ' ' || | |
5569 | nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) { | |
5570 | /* Reset NVRAM data. */ | |
7c3df132 | 5571 | ql_log(ql_log_info, vha, 0x0073, |
9e336520 | 5572 | "Inconsistent NVRAM detected: checksum=0x%x id=%c " |
7c3df132 | 5573 | "version=0x%x.\n", chksum, nv->id[0], |
3a03eb79 | 5574 | le16_to_cpu(nv->nvram_version)); |
7c3df132 SK |
5575 | ql_log(ql_log_info, vha, 0x0074, |
5576 | "Falling back to functioning (yet invalid -- WWPN) " | |
5577 | "defaults.\n"); | |
3a03eb79 AV |
5578 | |
5579 | /* | |
5580 | * Set default initialization control block. | |
5581 | */ | |
5582 | memset(nv, 0, ha->nvram_size); | |
5583 | nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION); | |
5584 | nv->version = __constant_cpu_to_le16(ICB_VERSION); | |
5585 | nv->frame_payload_size = __constant_cpu_to_le16(2048); | |
5586 | nv->execution_throttle = __constant_cpu_to_le16(0xFFFF); | |
5587 | nv->exchange_count = __constant_cpu_to_le16(0); | |
5588 | nv->port_name[0] = 0x21; | |
e5b68a61 | 5589 | nv->port_name[1] = 0x00 + ha->port_no; |
3a03eb79 AV |
5590 | nv->port_name[2] = 0x00; |
5591 | nv->port_name[3] = 0xe0; | |
5592 | nv->port_name[4] = 0x8b; | |
5593 | nv->port_name[5] = 0x1c; | |
5594 | nv->port_name[6] = 0x55; | |
5595 | nv->port_name[7] = 0x86; | |
5596 | nv->node_name[0] = 0x20; | |
5597 | nv->node_name[1] = 0x00; | |
5598 | nv->node_name[2] = 0x00; | |
5599 | nv->node_name[3] = 0xe0; | |
5600 | nv->node_name[4] = 0x8b; | |
5601 | nv->node_name[5] = 0x1c; | |
5602 | nv->node_name[6] = 0x55; | |
5603 | nv->node_name[7] = 0x86; | |
5604 | nv->login_retry_count = __constant_cpu_to_le16(8); | |
5605 | nv->interrupt_delay_timer = __constant_cpu_to_le16(0); | |
5606 | nv->login_timeout = __constant_cpu_to_le16(0); | |
5607 | nv->firmware_options_1 = | |
5608 | __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1); | |
5609 | nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4); | |
5610 | nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12); | |
5611 | nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13); | |
5612 | nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10); | |
5613 | nv->efi_parameters = __constant_cpu_to_le32(0); | |
5614 | nv->reset_delay = 5; | |
5615 | nv->max_luns_per_target = __constant_cpu_to_le16(128); | |
5616 | nv->port_down_retry_count = __constant_cpu_to_le16(30); | |
6246b8a1 | 5617 | nv->link_down_timeout = __constant_cpu_to_le16(180); |
eeebcc92 | 5618 | nv->enode_mac[0] = 0x00; |
6246b8a1 GM |
5619 | nv->enode_mac[1] = 0xC0; |
5620 | nv->enode_mac[2] = 0xDD; | |
3a03eb79 AV |
5621 | nv->enode_mac[3] = 0x04; |
5622 | nv->enode_mac[4] = 0x05; | |
e5b68a61 | 5623 | nv->enode_mac[5] = 0x06 + ha->port_no; |
3a03eb79 AV |
5624 | |
5625 | rval = 1; | |
5626 | } | |
5627 | ||
9e522cd8 AE |
5628 | if (IS_T10_PI_CAPABLE(ha)) |
5629 | nv->frame_payload_size &= ~7; | |
5630 | ||
aa230bc5 AE |
5631 | qlt_81xx_config_nvram_stage1(vha, nv); |
5632 | ||
3a03eb79 | 5633 | /* Reset Initialization control block */ |
773120e4 | 5634 | memset(icb, 0, ha->init_cb_size); |
3a03eb79 AV |
5635 | |
5636 | /* Copy 1st segment. */ | |
5637 | dptr1 = (uint8_t *)icb; | |
5638 | dptr2 = (uint8_t *)&nv->version; | |
5639 | cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version; | |
5640 | while (cnt--) | |
5641 | *dptr1++ = *dptr2++; | |
5642 | ||
5643 | icb->login_retry_count = nv->login_retry_count; | |
5644 | ||
5645 | /* Copy 2nd segment. */ | |
5646 | dptr1 = (uint8_t *)&icb->interrupt_delay_timer; | |
5647 | dptr2 = (uint8_t *)&nv->interrupt_delay_timer; | |
5648 | cnt = (uint8_t *)&icb->reserved_5 - | |
5649 | (uint8_t *)&icb->interrupt_delay_timer; | |
5650 | while (cnt--) | |
5651 | *dptr1++ = *dptr2++; | |
5652 | ||
5653 | memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac)); | |
5654 | /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */ | |
5655 | if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) { | |
69e5f1ea AV |
5656 | icb->enode_mac[0] = 0x00; |
5657 | icb->enode_mac[1] = 0xC0; | |
5658 | icb->enode_mac[2] = 0xDD; | |
3a03eb79 AV |
5659 | icb->enode_mac[3] = 0x04; |
5660 | icb->enode_mac[4] = 0x05; | |
e5b68a61 | 5661 | icb->enode_mac[5] = 0x06 + ha->port_no; |
3a03eb79 AV |
5662 | } |
5663 | ||
b64b0e8f AV |
5664 | /* Use extended-initialization control block. */ |
5665 | memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb)); | |
5666 | ||
3a03eb79 AV |
5667 | /* |
5668 | * Setup driver NVRAM options. | |
5669 | */ | |
5670 | qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name), | |
a9083016 | 5671 | "QLE8XXX"); |
3a03eb79 | 5672 | |
aa230bc5 AE |
5673 | qlt_81xx_config_nvram_stage2(vha, icb); |
5674 | ||
3a03eb79 AV |
5675 | /* Use alternate WWN? */ |
5676 | if (nv->host_p & __constant_cpu_to_le32(BIT_15)) { | |
5677 | memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE); | |
5678 | memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE); | |
5679 | } | |
5680 | ||
5681 | /* Prepare nodename */ | |
5682 | if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) { | |
5683 | /* | |
5684 | * Firmware will apply the following mask if the nodename was | |
5685 | * not provided. | |
5686 | */ | |
5687 | memcpy(icb->node_name, icb->port_name, WWN_SIZE); | |
5688 | icb->node_name[0] &= 0xF0; | |
5689 | } | |
5690 | ||
5691 | /* Set host adapter parameters. */ | |
5692 | ha->flags.disable_risc_code_load = 0; | |
5693 | ha->flags.enable_lip_reset = 0; | |
5694 | ha->flags.enable_lip_full_login = | |
5695 | le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0; | |
5696 | ha->flags.enable_target_reset = | |
5697 | le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0; | |
5698 | ha->flags.enable_led_scheme = 0; | |
5699 | ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0; | |
5700 | ||
5701 | ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) & | |
5702 | (BIT_6 | BIT_5 | BIT_4)) >> 4; | |
5703 | ||
5704 | /* save HBA serial number */ | |
5705 | ha->serial0 = icb->port_name[5]; | |
5706 | ha->serial1 = icb->port_name[6]; | |
5707 | ha->serial2 = icb->port_name[7]; | |
5708 | memcpy(vha->node_name, icb->node_name, WWN_SIZE); | |
5709 | memcpy(vha->port_name, icb->port_name, WWN_SIZE); | |
5710 | ||
5711 | icb->execution_throttle = __constant_cpu_to_le16(0xFFFF); | |
5712 | ||
5713 | ha->retry_count = le16_to_cpu(nv->login_retry_count); | |
5714 | ||
5715 | /* Set minimum login_timeout to 4 seconds. */ | |
5716 | if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout) | |
5717 | nv->login_timeout = cpu_to_le16(ql2xlogintimeout); | |
5718 | if (le16_to_cpu(nv->login_timeout) < 4) | |
5719 | nv->login_timeout = __constant_cpu_to_le16(4); | |
5720 | ha->login_timeout = le16_to_cpu(nv->login_timeout); | |
5721 | icb->login_timeout = nv->login_timeout; | |
5722 | ||
5723 | /* Set minimum RATOV to 100 tenths of a second. */ | |
5724 | ha->r_a_tov = 100; | |
5725 | ||
5726 | ha->loop_reset_delay = nv->reset_delay; | |
5727 | ||
5728 | /* Link Down Timeout = 0: | |
5729 | * | |
5730 | * When Port Down timer expires we will start returning | |
5731 | * I/O's to OS with "DID_NO_CONNECT". | |
5732 | * | |
5733 | * Link Down Timeout != 0: | |
5734 | * | |
5735 | * The driver waits for the link to come up after link down | |
5736 | * before returning I/Os to OS with "DID_NO_CONNECT". | |
5737 | */ | |
5738 | if (le16_to_cpu(nv->link_down_timeout) == 0) { | |
5739 | ha->loop_down_abort_time = | |
5740 | (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT); | |
5741 | } else { | |
5742 | ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout); | |
5743 | ha->loop_down_abort_time = | |
5744 | (LOOP_DOWN_TIME - ha->link_down_timeout); | |
5745 | } | |
5746 | ||
5747 | /* Need enough time to try and get the port back. */ | |
5748 | ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count); | |
5749 | if (qlport_down_retry) | |
5750 | ha->port_down_retry_count = qlport_down_retry; | |
5751 | ||
5752 | /* Set login_retry_count */ | |
5753 | ha->login_retry_count = le16_to_cpu(nv->login_retry_count); | |
5754 | if (ha->port_down_retry_count == | |
5755 | le16_to_cpu(nv->port_down_retry_count) && | |
5756 | ha->port_down_retry_count > 3) | |
5757 | ha->login_retry_count = ha->port_down_retry_count; | |
5758 | else if (ha->port_down_retry_count > (int)ha->login_retry_count) | |
5759 | ha->login_retry_count = ha->port_down_retry_count; | |
5760 | if (ql2xloginretrycount) | |
5761 | ha->login_retry_count = ql2xloginretrycount; | |
5762 | ||
6246b8a1 GM |
5763 | /* if not running MSI-X we need handshaking on interrupts */ |
5764 | if (!vha->hw->flags.msix_enabled && IS_QLA83XX(ha)) | |
5765 | icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_22); | |
5766 | ||
3a03eb79 AV |
5767 | /* Enable ZIO. */ |
5768 | if (!vha->flags.init_done) { | |
5769 | ha->zio_mode = le32_to_cpu(icb->firmware_options_2) & | |
5770 | (BIT_3 | BIT_2 | BIT_1 | BIT_0); | |
5771 | ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ? | |
5772 | le16_to_cpu(icb->interrupt_delay_timer): 2; | |
5773 | } | |
5774 | icb->firmware_options_2 &= __constant_cpu_to_le32( | |
5775 | ~(BIT_3 | BIT_2 | BIT_1 | BIT_0)); | |
5776 | vha->flags.process_response_queue = 0; | |
5777 | if (ha->zio_mode != QLA_ZIO_DISABLED) { | |
5778 | ha->zio_mode = QLA_ZIO_MODE_6; | |
5779 | ||
7c3df132 | 5780 | ql_log(ql_log_info, vha, 0x0075, |
3a03eb79 | 5781 | "ZIO mode %d enabled; timer delay (%d us).\n", |
7c3df132 SK |
5782 | ha->zio_mode, |
5783 | ha->zio_timer * 100); | |
3a03eb79 AV |
5784 | |
5785 | icb->firmware_options_2 |= cpu_to_le32( | |
5786 | (uint32_t)ha->zio_mode); | |
5787 | icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer); | |
5788 | vha->flags.process_response_queue = 1; | |
5789 | } | |
5790 | ||
5791 | if (rval) { | |
7c3df132 SK |
5792 | ql_log(ql_log_warn, vha, 0x0076, |
5793 | "NVRAM configuration failed.\n"); | |
3a03eb79 AV |
5794 | } |
5795 | return (rval); | |
5796 | } | |
5797 | ||
a9083016 GM |
5798 | int |
5799 | qla82xx_restart_isp(scsi_qla_host_t *vha) | |
5800 | { | |
5801 | int status, rval; | |
5802 | uint32_t wait_time; | |
5803 | struct qla_hw_data *ha = vha->hw; | |
5804 | struct req_que *req = ha->req_q_map[0]; | |
5805 | struct rsp_que *rsp = ha->rsp_q_map[0]; | |
5806 | struct scsi_qla_host *vp; | |
feafb7b1 | 5807 | unsigned long flags; |
a9083016 GM |
5808 | |
5809 | status = qla2x00_init_rings(vha); | |
5810 | if (!status) { | |
5811 | clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); | |
5812 | ha->flags.chip_reset_done = 1; | |
5813 | ||
5814 | status = qla2x00_fw_ready(vha); | |
5815 | if (!status) { | |
7c3df132 SK |
5816 | ql_log(ql_log_info, vha, 0x803c, |
5817 | "Start configure loop, status =%d.\n", status); | |
a9083016 GM |
5818 | |
5819 | /* Issue a marker after FW becomes ready. */ | |
5820 | qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL); | |
5821 | ||
5822 | vha->flags.online = 1; | |
5823 | /* Wait at most MAX_TARGET RSCNs for a stable link. */ | |
5824 | wait_time = 256; | |
5825 | do { | |
5826 | clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); | |
5827 | qla2x00_configure_loop(vha); | |
5828 | wait_time--; | |
5829 | } while (!atomic_read(&vha->loop_down_timer) && | |
5830 | !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) && | |
5831 | wait_time && | |
5832 | (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))); | |
5833 | } | |
5834 | ||
5835 | /* if no cable then assume it's good */ | |
5836 | if ((vha->device_flags & DFLG_NO_CABLE)) | |
5837 | status = 0; | |
5838 | ||
cfb0919c | 5839 | ql_log(ql_log_info, vha, 0x8000, |
7c3df132 | 5840 | "Configure loop done, status = 0x%x.\n", status); |
a9083016 GM |
5841 | } |
5842 | ||
5843 | if (!status) { | |
5844 | clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); | |
5845 | ||
5846 | if (!atomic_read(&vha->loop_down_timer)) { | |
5847 | /* | |
5848 | * Issue marker command only when we are going | |
5849 | * to start the I/O . | |
5850 | */ | |
5851 | vha->marker_needed = 1; | |
5852 | } | |
5853 | ||
5854 | vha->flags.online = 1; | |
5855 | ||
5856 | ha->isp_ops->enable_intrs(ha); | |
5857 | ||
5858 | ha->isp_abort_cnt = 0; | |
5859 | clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); | |
5860 | ||
53296788 | 5861 | /* Update the firmware version */ |
3173167f | 5862 | status = qla82xx_check_md_needed(vha); |
53296788 | 5863 | |
a9083016 GM |
5864 | if (ha->fce) { |
5865 | ha->flags.fce_enabled = 1; | |
5866 | memset(ha->fce, 0, | |
5867 | fce_calc_size(ha->fce_bufs)); | |
5868 | rval = qla2x00_enable_fce_trace(vha, | |
5869 | ha->fce_dma, ha->fce_bufs, ha->fce_mb, | |
5870 | &ha->fce_bufs); | |
5871 | if (rval) { | |
cfb0919c | 5872 | ql_log(ql_log_warn, vha, 0x8001, |
7c3df132 SK |
5873 | "Unable to reinitialize FCE (%d).\n", |
5874 | rval); | |
a9083016 GM |
5875 | ha->flags.fce_enabled = 0; |
5876 | } | |
5877 | } | |
5878 | ||
5879 | if (ha->eft) { | |
5880 | memset(ha->eft, 0, EFT_SIZE); | |
5881 | rval = qla2x00_enable_eft_trace(vha, | |
5882 | ha->eft_dma, EFT_NUM_BUFFERS); | |
5883 | if (rval) { | |
cfb0919c | 5884 | ql_log(ql_log_warn, vha, 0x8010, |
7c3df132 SK |
5885 | "Unable to reinitialize EFT (%d).\n", |
5886 | rval); | |
a9083016 GM |
5887 | } |
5888 | } | |
a9083016 GM |
5889 | } |
5890 | ||
5891 | if (!status) { | |
cfb0919c | 5892 | ql_dbg(ql_dbg_taskm, vha, 0x8011, |
7c3df132 | 5893 | "qla82xx_restart_isp succeeded.\n"); |
feafb7b1 AE |
5894 | |
5895 | spin_lock_irqsave(&ha->vport_slock, flags); | |
5896 | list_for_each_entry(vp, &ha->vp_list, list) { | |
5897 | if (vp->vp_idx) { | |
5898 | atomic_inc(&vp->vref_count); | |
5899 | spin_unlock_irqrestore(&ha->vport_slock, flags); | |
5900 | ||
a9083016 | 5901 | qla2x00_vp_abort_isp(vp); |
feafb7b1 AE |
5902 | |
5903 | spin_lock_irqsave(&ha->vport_slock, flags); | |
5904 | atomic_dec(&vp->vref_count); | |
5905 | } | |
a9083016 | 5906 | } |
feafb7b1 AE |
5907 | spin_unlock_irqrestore(&ha->vport_slock, flags); |
5908 | ||
a9083016 | 5909 | } else { |
cfb0919c | 5910 | ql_log(ql_log_warn, vha, 0x8016, |
7c3df132 | 5911 | "qla82xx_restart_isp **** FAILED ****.\n"); |
a9083016 GM |
5912 | } |
5913 | ||
5914 | return status; | |
5915 | } | |
5916 | ||
3a03eb79 | 5917 | void |
ae97c91e | 5918 | qla81xx_update_fw_options(scsi_qla_host_t *vha) |
3a03eb79 | 5919 | { |
ae97c91e AV |
5920 | struct qla_hw_data *ha = vha->hw; |
5921 | ||
5922 | if (!ql2xetsenable) | |
5923 | return; | |
5924 | ||
5925 | /* Enable ETS Burst. */ | |
5926 | memset(ha->fw_options, 0, sizeof(ha->fw_options)); | |
5927 | ha->fw_options[2] |= BIT_9; | |
5928 | qla2x00_set_fw_options(vha, ha->fw_options); | |
3a03eb79 | 5929 | } |
09ff701a SR |
5930 | |
5931 | /* | |
5932 | * qla24xx_get_fcp_prio | |
5933 | * Gets the fcp cmd priority value for the logged in port. | |
5934 | * Looks for a match of the port descriptors within | |
5935 | * each of the fcp prio config entries. If a match is found, | |
5936 | * the tag (priority) value is returned. | |
5937 | * | |
5938 | * Input: | |
21090cbe | 5939 | * vha = scsi host structure pointer. |
09ff701a SR |
5940 | * fcport = port structure pointer. |
5941 | * | |
5942 | * Return: | |
6c452a45 | 5943 | * non-zero (if found) |
f28a0a96 | 5944 | * -1 (if not found) |
09ff701a SR |
5945 | * |
5946 | * Context: | |
5947 | * Kernel context | |
5948 | */ | |
f28a0a96 | 5949 | static int |
09ff701a SR |
5950 | qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport) |
5951 | { | |
5952 | int i, entries; | |
5953 | uint8_t pid_match, wwn_match; | |
f28a0a96 | 5954 | int priority; |
09ff701a SR |
5955 | uint32_t pid1, pid2; |
5956 | uint64_t wwn1, wwn2; | |
5957 | struct qla_fcp_prio_entry *pri_entry; | |
5958 | struct qla_hw_data *ha = vha->hw; | |
5959 | ||
5960 | if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled) | |
f28a0a96 | 5961 | return -1; |
09ff701a | 5962 | |
f28a0a96 | 5963 | priority = -1; |
09ff701a SR |
5964 | entries = ha->fcp_prio_cfg->num_entries; |
5965 | pri_entry = &ha->fcp_prio_cfg->entry[0]; | |
5966 | ||
5967 | for (i = 0; i < entries; i++) { | |
5968 | pid_match = wwn_match = 0; | |
5969 | ||
5970 | if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) { | |
5971 | pri_entry++; | |
5972 | continue; | |
5973 | } | |
5974 | ||
5975 | /* check source pid for a match */ | |
5976 | if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) { | |
5977 | pid1 = pri_entry->src_pid & INVALID_PORT_ID; | |
5978 | pid2 = vha->d_id.b24 & INVALID_PORT_ID; | |
5979 | if (pid1 == INVALID_PORT_ID) | |
5980 | pid_match++; | |
5981 | else if (pid1 == pid2) | |
5982 | pid_match++; | |
5983 | } | |
5984 | ||
5985 | /* check destination pid for a match */ | |
5986 | if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) { | |
5987 | pid1 = pri_entry->dst_pid & INVALID_PORT_ID; | |
5988 | pid2 = fcport->d_id.b24 & INVALID_PORT_ID; | |
5989 | if (pid1 == INVALID_PORT_ID) | |
5990 | pid_match++; | |
5991 | else if (pid1 == pid2) | |
5992 | pid_match++; | |
5993 | } | |
5994 | ||
5995 | /* check source WWN for a match */ | |
5996 | if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) { | |
5997 | wwn1 = wwn_to_u64(vha->port_name); | |
5998 | wwn2 = wwn_to_u64(pri_entry->src_wwpn); | |
5999 | if (wwn2 == (uint64_t)-1) | |
6000 | wwn_match++; | |
6001 | else if (wwn1 == wwn2) | |
6002 | wwn_match++; | |
6003 | } | |
6004 | ||
6005 | /* check destination WWN for a match */ | |
6006 | if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) { | |
6007 | wwn1 = wwn_to_u64(fcport->port_name); | |
6008 | wwn2 = wwn_to_u64(pri_entry->dst_wwpn); | |
6009 | if (wwn2 == (uint64_t)-1) | |
6010 | wwn_match++; | |
6011 | else if (wwn1 == wwn2) | |
6012 | wwn_match++; | |
6013 | } | |
6014 | ||
6015 | if (pid_match == 2 || wwn_match == 2) { | |
6016 | /* Found a matching entry */ | |
6017 | if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID) | |
6018 | priority = pri_entry->tag; | |
6019 | break; | |
6020 | } | |
6021 | ||
6022 | pri_entry++; | |
6023 | } | |
6024 | ||
6025 | return priority; | |
6026 | } | |
6027 | ||
6028 | /* | |
6029 | * qla24xx_update_fcport_fcp_prio | |
6030 | * Activates fcp priority for the logged in fc port | |
6031 | * | |
6032 | * Input: | |
21090cbe | 6033 | * vha = scsi host structure pointer. |
09ff701a SR |
6034 | * fcp = port structure pointer. |
6035 | * | |
6036 | * Return: | |
6037 | * QLA_SUCCESS or QLA_FUNCTION_FAILED | |
6038 | * | |
6039 | * Context: | |
6040 | * Kernel context. | |
6041 | */ | |
6042 | int | |
21090cbe | 6043 | qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport) |
09ff701a SR |
6044 | { |
6045 | int ret; | |
f28a0a96 | 6046 | int priority; |
09ff701a SR |
6047 | uint16_t mb[5]; |
6048 | ||
21090cbe MI |
6049 | if (fcport->port_type != FCT_TARGET || |
6050 | fcport->loop_id == FC_NO_LOOP_ID) | |
09ff701a SR |
6051 | return QLA_FUNCTION_FAILED; |
6052 | ||
21090cbe | 6053 | priority = qla24xx_get_fcp_prio(vha, fcport); |
f28a0a96 AV |
6054 | if (priority < 0) |
6055 | return QLA_FUNCTION_FAILED; | |
6056 | ||
a00f6296 SK |
6057 | if (IS_QLA82XX(vha->hw)) { |
6058 | fcport->fcp_prio = priority & 0xf; | |
6059 | return QLA_SUCCESS; | |
6060 | } | |
6061 | ||
21090cbe | 6062 | ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb); |
cfb0919c CD |
6063 | if (ret == QLA_SUCCESS) { |
6064 | if (fcport->fcp_prio != priority) | |
6065 | ql_dbg(ql_dbg_user, vha, 0x709e, | |
6066 | "Updated FCP_CMND priority - value=%d loop_id=%d " | |
6067 | "port_id=%02x%02x%02x.\n", priority, | |
6068 | fcport->loop_id, fcport->d_id.b.domain, | |
6069 | fcport->d_id.b.area, fcport->d_id.b.al_pa); | |
a00f6296 | 6070 | fcport->fcp_prio = priority & 0xf; |
cfb0919c | 6071 | } else |
7c3df132 | 6072 | ql_dbg(ql_dbg_user, vha, 0x704f, |
cfb0919c CD |
6073 | "Unable to update FCP_CMND priority - ret=0x%x for " |
6074 | "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id, | |
6075 | fcport->d_id.b.domain, fcport->d_id.b.area, | |
6076 | fcport->d_id.b.al_pa); | |
09ff701a SR |
6077 | return ret; |
6078 | } | |
6079 | ||
6080 | /* | |
6081 | * qla24xx_update_all_fcp_prio | |
6082 | * Activates fcp priority for all the logged in ports | |
6083 | * | |
6084 | * Input: | |
6085 | * ha = adapter block pointer. | |
6086 | * | |
6087 | * Return: | |
6088 | * QLA_SUCCESS or QLA_FUNCTION_FAILED | |
6089 | * | |
6090 | * Context: | |
6091 | * Kernel context. | |
6092 | */ | |
6093 | int | |
6094 | qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha) | |
6095 | { | |
6096 | int ret; | |
6097 | fc_port_t *fcport; | |
6098 | ||
6099 | ret = QLA_FUNCTION_FAILED; | |
6100 | /* We need to set priority for all logged in ports */ | |
6101 | list_for_each_entry(fcport, &vha->vp_fcports, list) | |
6102 | ret = qla24xx_update_fcport_fcp_prio(vha, fcport); | |
6103 | ||
6104 | return ret; | |
6105 | } |