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qla2xxx: Add async new target notification
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / qla2xxx / qla_init.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
73208dfd 8#include "qla_gbl.h"
1da177e4
LT		 9
10#include <linux/delay.h>
5a0e3ad6 11#include <linux/slab.h>
0107109e 12#include <linux/vmalloc.h>
1da177e4
LT		 13
14#include "qla_devtbl.h"
15
4e08df3f
DM		 16#ifdef CONFIG_SPARC
17#include <asm/prom.h>
4e08df3f
DM		 18#endif
19
2d70c103
NB		 20#include <target/target_core_base.h>
21#include "qla_target.h"
22
1da177e4
LT		 23/*
24* QLogic ISP2x00 Hardware Support Function Prototypes.
25*/
1da177e4 26static int qla2x00_isp_firmware(scsi_qla_host_t *);
1da177e4 27static int qla2x00_setup_chip(scsi_qla_host_t *);
1da177e4
LT		 28static int qla2x00_fw_ready(scsi_qla_host_t *);
29static int qla2x00_configure_hba(scsi_qla_host_t *);
1da177e4
LT		 30static int qla2x00_configure_loop(scsi_qla_host_t *);
31static int qla2x00_configure_local_loop(scsi_qla_host_t *);
1da177e4 32static int qla2x00_configure_fabric(scsi_qla_host_t *);
726b8548 33static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *);
1da177e4 34static int qla2x00_restart_isp(scsi_qla_host_t *);
1da177e4 35
4d4df193
HK		 36static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *);
37static int qla84xx_init_chip(scsi_qla_host_t *);
73208dfd 38static int qla25xx_init_queues(struct qla_hw_data *);
726b8548
QT		 39static int qla24xx_post_gpdb_work(struct scsi_qla_host *, fc_port_t *, u8);
40static void qla24xx_handle_plogi_done_event(struct scsi_qla_host *,
41 struct event_arg *);
4d4df193 42
ac280b67
AV		 43/* SRB Extensions ---------------------------------------------------------- */
44
9ba56b95
GM		 45void
46qla2x00_sp_timeout(unsigned long __data)
ac280b67
AV		 47{
48 srb_t *sp = (srb_t *)__data;
4916392b 49 struct srb_iocb *iocb;
25ff6af1 50 scsi_qla_host_t *vha = sp->vha;
ac280b67
AV		 51 struct req_que *req;
52 unsigned long flags;
53
25ff6af1
JC		 54 spin_lock_irqsave(&vha->hw->hardware_lock, flags);
55 req = vha->hw->req_q_map[0];
ac280b67 56 req->outstanding_cmds[sp->handle] = NULL;
9ba56b95 57 iocb = &sp->u.iocb_cmd;
4916392b 58 iocb->timeout(sp);
25ff6af1
JC		 59 sp->free(sp);
60 spin_unlock_irqrestore(&vha->hw->hardware_lock, flags);
ac280b67
AV		 61}
62
9ba56b95 63void
25ff6af1 64qla2x00_sp_free(void *ptr)
ac280b67 65{
25ff6af1 66 srb_t *sp = ptr;
9ba56b95 67 struct srb_iocb *iocb = &sp->u.iocb_cmd;
ac280b67 68
4d97cc53 69 del_timer(&iocb->timer);
25ff6af1 70 qla2x00_rel_sp(sp);
ac280b67
AV		 71}
72
ac280b67
AV		 73/* Asynchronous Login/Logout Routines -------------------------------------- */
74
a9b6f722 75unsigned long
5b91490e
AV		 76qla2x00_get_async_timeout(struct scsi_qla_host *vha)
77{
78 unsigned long tmo;
79 struct qla_hw_data *ha = vha->hw;
80
81 /* Firmware should use switch negotiated r_a_tov for timeout. */
82 tmo = ha->r_a_tov / 10 * 2;
8ae6d9c7
GM		 83 if (IS_QLAFX00(ha)) {
84 tmo = FX00_DEF_RATOV * 2;
85 } else if (!IS_FWI2_CAPABLE(ha)) {
5b91490e
AV		 86 /*
87 * Except for earlier ISPs where the timeout is seeded from the
88 * initialization control block.
89 */
90 tmo = ha->login_timeout;
91 }
92 return tmo;
93}
ac280b67 94
726b8548 95void
9ba56b95 96qla2x00_async_iocb_timeout(void *data)
ac280b67 97{
25ff6af1 98 srb_t *sp = data;
ac280b67 99 fc_port_t *fcport = sp->fcport;
726b8548
QT		 100 struct srb_iocb *lio = &sp->u.iocb_cmd;
101 struct event_arg ea;
ac280b67 102
7c3df132 103 ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
726b8548
QT		 104 "Async-%s timeout - hdl=%x portid=%06x %8phC.\n",
105 sp->name, sp->handle, fcport->d_id.b24, fcport->port_name);
ac280b67 106
5ff1d584 107 fcport->flags &= ~FCF_ASYNC_SENT;
726b8548
QT		 108
109 switch (sp->type) {
110 case SRB_LOGIN_CMD:
6ac52608
AV		 111 /* Retry as needed. */
112 lio->u.logio.data[0] = MBS_COMMAND_ERROR;
113 lio->u.logio.data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
114 QLA_LOGIO_LOGIN_RETRIED : 0;
726b8548
QT		 115 memset(&ea, 0, sizeof(ea));
116 ea.event = FCME_PLOGI_DONE;
117 ea.fcport = sp->fcport;
118 ea.data[0] = lio->u.logio.data[0];
119 ea.data[1] = lio->u.logio.data[1];
120 ea.sp = sp;
121 qla24xx_handle_plogi_done_event(fcport->vha, &ea);
122 break;
123 case SRB_LOGOUT_CMD:
a6ca8878 124 qlt_logo_completion_handler(fcport, QLA_FUNCTION_TIMEOUT);
726b8548
QT		 125 break;
126 case SRB_CT_PTHRU_CMD:
127 case SRB_MB_IOCB:
128 case SRB_NACK_PLOGI:
129 case SRB_NACK_PRLI:
130 case SRB_NACK_LOGO:
25ff6af1 131 sp->done(sp, QLA_FUNCTION_TIMEOUT);
726b8548 132 break;
6ac52608 133 }
ac280b67
AV		 134}
135
99b0bec7 136static void
25ff6af1 137qla2x00_async_login_sp_done(void *ptr, int res)
99b0bec7 138{
25ff6af1
JC		 139 srb_t *sp = ptr;
140 struct scsi_qla_host *vha = sp->vha;
9ba56b95 141 struct srb_iocb *lio = &sp->u.iocb_cmd;
726b8548 142 struct event_arg ea;
9ba56b95 143
726b8548 144 ql_dbg(ql_dbg_disc, vha, 0xffff,
25ff6af1 145 "%s %8phC res %d \n", __func__, sp->fcport->port_name, res);
726b8548
QT		 146
147 sp->fcport->flags &= ~FCF_ASYNC_SENT;
148 if (!test_bit(UNLOADING, &vha->dpc_flags)) {
149 memset(&ea, 0, sizeof(ea));
150 ea.event = FCME_PLOGI_DONE;
151 ea.fcport = sp->fcport;
152 ea.data[0] = lio->u.logio.data[0];
153 ea.data[1] = lio->u.logio.data[1];
154 ea.iop[0] = lio->u.logio.iop[0];
155 ea.iop[1] = lio->u.logio.iop[1];
156 ea.sp = sp;
157 qla2x00_fcport_event_handler(vha, &ea);
158 }
9ba56b95 159
25ff6af1 160 sp->free(sp);
99b0bec7
AV		 161}
162
ac280b67
AV		 163int
164qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport,
165 uint16_t *data)
166{
ac280b67 167 srb_t *sp;
4916392b 168 struct srb_iocb *lio;
726b8548
QT		 169 int rval = QLA_FUNCTION_FAILED;
170
171 if (!vha->flags.online)
172 goto done;
173
174 if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) ||
175 (fcport->fw_login_state == DSC_LS_PLOGI_COMP) ||
176 (fcport->fw_login_state == DSC_LS_PRLI_PEND))
177 goto done;
ac280b67 178
9ba56b95 179 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 180 if (!sp)
181 goto done;
182
726b8548
QT		 183 fcport->flags |= FCF_ASYNC_SENT;
184 fcport->logout_completed = 0;
185
9ba56b95
GM		 186 sp->type = SRB_LOGIN_CMD;
187 sp->name = "login";
188 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
189
190 lio = &sp->u.iocb_cmd;
3822263e 191 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 192 sp->done = qla2x00_async_login_sp_done;
4916392b 193 lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI;
ac280b67 194 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 195 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
ac280b67 196 rval = qla2x00_start_sp(sp);
080c9517
CD		 197 if (rval != QLA_SUCCESS) {
198 fcport->flags &= ~FCF_ASYNC_SENT;
199 fcport->flags |= FCF_LOGIN_NEEDED;
200 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
ac280b67 201 goto done_free_sp;
080c9517 202 }
ac280b67 203
7c3df132 204 ql_dbg(ql_dbg_disc, vha, 0x2072,
726b8548
QT		 205 "Async-login - %8phC hdl=%x, loopid=%x portid=%02x%02x%02x "
206 "retries=%d.\n", fcport->port_name, sp->handle, fcport->loop_id,
cfb0919c
CD		 207 fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
208 fcport->login_retry);
ac280b67
AV		 209 return rval;
210
211done_free_sp:
25ff6af1 212 sp->free(sp);
ac280b67 213done:
726b8548 214 fcport->flags &= ~FCF_ASYNC_SENT;
ac280b67
AV		 215 return rval;
216}
217
99b0bec7 218static void
25ff6af1 219qla2x00_async_logout_sp_done(void *ptr, int res)
99b0bec7 220{
25ff6af1 221 srb_t *sp = ptr;
9ba56b95 222 struct srb_iocb *lio = &sp->u.iocb_cmd;
9ba56b95 223
726b8548 224 sp->fcport->flags &= ~FCF_ASYNC_SENT;
25ff6af1
JC		 225 if (!test_bit(UNLOADING, &sp->vha->dpc_flags))
226 qla2x00_post_async_logout_done_work(sp->vha, sp->fcport,
9ba56b95 227 lio->u.logio.data);
25ff6af1 228 sp->free(sp);
99b0bec7
AV		 229}
230
ac280b67
AV		 231int
232qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport)
233{
ac280b67 234 srb_t *sp;
4916392b 235 struct srb_iocb *lio;
ac280b67
AV		 236 int rval;
237
238 rval = QLA_FUNCTION_FAILED;
726b8548 239 fcport->flags |= FCF_ASYNC_SENT;
9ba56b95 240 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 241 if (!sp)
242 goto done;
243
9ba56b95
GM		 244 sp->type = SRB_LOGOUT_CMD;
245 sp->name = "logout";
246 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
247
248 lio = &sp->u.iocb_cmd;
3822263e 249 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 250 sp->done = qla2x00_async_logout_sp_done;
ac280b67
AV		 251 rval = qla2x00_start_sp(sp);
252 if (rval != QLA_SUCCESS)
253 goto done_free_sp;
254
7c3df132 255 ql_dbg(ql_dbg_disc, vha, 0x2070,
726b8548 256 "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x %8phC.\n",
cfb0919c 257 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
726b8548
QT		 258 fcport->d_id.b.area, fcport->d_id.b.al_pa,
259 fcport->port_name);
ac280b67
AV		 260 return rval;
261
262done_free_sp:
25ff6af1 263 sp->free(sp);
ac280b67 264done:
726b8548 265 fcport->flags &= ~FCF_ASYNC_SENT;
ac280b67
AV		 266 return rval;
267}
268
5ff1d584 269static void
25ff6af1 270qla2x00_async_adisc_sp_done(void *ptr, int res)
5ff1d584 271{
25ff6af1
JC		 272 srb_t *sp = ptr;
273 struct scsi_qla_host *vha = sp->vha;
9ba56b95 274 struct srb_iocb *lio = &sp->u.iocb_cmd;
9ba56b95
GM		 275
276 if (!test_bit(UNLOADING, &vha->dpc_flags))
25ff6af1 277 qla2x00_post_async_adisc_done_work(sp->vha, sp->fcport,
9ba56b95 278 lio->u.logio.data);
25ff6af1 279 sp->free(sp);
5ff1d584
AV		 280}
281
282int
283qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport,
284 uint16_t *data)
285{
5ff1d584 286 srb_t *sp;
4916392b 287 struct srb_iocb *lio;
5ff1d584
AV		 288 int rval;
289
290 rval = QLA_FUNCTION_FAILED;
726b8548 291 fcport->flags |= FCF_ASYNC_SENT;
9ba56b95 292 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
5ff1d584
AV		 293 if (!sp)
294 goto done;
295
9ba56b95
GM		 296 sp->type = SRB_ADISC_CMD;
297 sp->name = "adisc";
298 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
299
300 lio = &sp->u.iocb_cmd;
3822263e 301 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 302 sp->done = qla2x00_async_adisc_sp_done;
5ff1d584 303 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 304 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
5ff1d584
AV		 305 rval = qla2x00_start_sp(sp);
306 if (rval != QLA_SUCCESS)
307 goto done_free_sp;
308
7c3df132 309 ql_dbg(ql_dbg_disc, vha, 0x206f,
cfb0919c
CD		 310 "Async-adisc - hdl=%x loopid=%x portid=%02x%02x%02x.\n",
311 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
312 fcport->d_id.b.area, fcport->d_id.b.al_pa);
5ff1d584
AV		 313 return rval;
314
315done_free_sp:
25ff6af1 316 sp->free(sp);
5ff1d584 317done:
726b8548
QT		 318 fcport->flags &= ~FCF_ASYNC_SENT;
319 return rval;
320}
321
322static void qla24xx_handle_gnl_done_event(scsi_qla_host_t *vha,
323 struct event_arg *ea)
324{
325 fc_port_t *fcport, *conflict_fcport;
326 struct get_name_list_extended *e;
327 u16 i, n, found = 0, loop_id;
328 port_id_t id;
329 u64 wwn;
330 u8 opt = 0;
331
332 fcport = ea->fcport;
333
334 if (ea->rc) { /* rval */
335 if (fcport->login_retry == 0) {
336 fcport->login_retry = vha->hw->login_retry_count;
337 ql_dbg(ql_dbg_disc, vha, 0xffff,
338 "GNL failed Port login retry %8phN, retry cnt=%d.\n",
339 fcport->port_name, fcport->login_retry);
340 }
341 return;
342 }
343
344 if (fcport->last_rscn_gen != fcport->rscn_gen) {
345 ql_dbg(ql_dbg_disc, vha, 0xffff,
346 "%s %8phC rscn gen changed rscn %d|%d \n",
347 __func__, fcport->port_name,
348 fcport->last_rscn_gen, fcport->rscn_gen);
349 qla24xx_post_gidpn_work(vha, fcport);
350 return;
351 } else if (fcport->last_login_gen != fcport->login_gen) {
352 ql_dbg(ql_dbg_disc, vha, 0xffff,
353 "%s %8phC login gen changed login %d|%d \n",
354 __func__, fcport->port_name,
355 fcport->last_login_gen, fcport->login_gen);
356 return;
357 }
358
359 n = ea->data[0] / sizeof(struct get_name_list_extended);
360
361 ql_dbg(ql_dbg_disc, vha, 0xffff,
362 "%s %d %8phC n %d %02x%02x%02x lid %d \n",
363 __func__, __LINE__, fcport->port_name, n,
364 fcport->d_id.b.domain, fcport->d_id.b.area,
365 fcport->d_id.b.al_pa, fcport->loop_id);
366
367 for (i = 0; i < n; i++) {
368 e = &vha->gnl.l[i];
369 wwn = wwn_to_u64(e->port_name);
370
371 if (memcmp((u8 *)&wwn, fcport->port_name, WWN_SIZE))
372 continue;
373
374 found = 1;
375 id.b.domain = e->port_id[2];
376 id.b.area = e->port_id[1];
377 id.b.al_pa = e->port_id[0];
378 id.b.rsvd_1 = 0;
379
380 loop_id = le16_to_cpu(e->nport_handle);
381 loop_id = (loop_id & 0x7fff);
382
383 ql_dbg(ql_dbg_disc, vha, 0xffff,
384 "%s found %8phC CLS [%d|%d] ID[%02x%02x%02x|%02x%02x%02x] lid[%d|%d]\n",
385 __func__, fcport->port_name,
386 e->current_login_state, fcport->fw_login_state,
387 id.b.domain, id.b.area, id.b.al_pa,
388 fcport->d_id.b.domain, fcport->d_id.b.area,
389 fcport->d_id.b.al_pa, loop_id, fcport->loop_id);
390
391 if ((id.b24 != fcport->d_id.b24) ||
392 ((fcport->loop_id != FC_NO_LOOP_ID) &&
393 (fcport->loop_id != loop_id))) {
394 ql_dbg(ql_dbg_disc, vha, 0xffff,
395 "%s %d %8phC post del sess\n",
396 __func__, __LINE__, fcport->port_name);
397 qlt_schedule_sess_for_deletion(fcport, 1);
398 return;
399 }
400
401 fcport->loop_id = loop_id;
402
403 wwn = wwn_to_u64(fcport->port_name);
404 qlt_find_sess_invalidate_other(vha, wwn,
405 id, loop_id, &conflict_fcport);
406
407 if (conflict_fcport) {
408 /*
409 * Another share fcport share the same loop_id &
410 * nport id. Conflict fcport needs to finish
411 * cleanup before this fcport can proceed to login.
412 */
413 conflict_fcport->conflict = fcport;
414 fcport->login_pause = 1;
415 }
416
417 switch (e->current_login_state) {
418 case DSC_LS_PRLI_COMP:
419 ql_dbg(ql_dbg_disc, vha, 0xffff,
420 "%s %d %8phC post gpdb\n",
421 __func__, __LINE__, fcport->port_name);
422 opt = PDO_FORCE_ADISC;
423 qla24xx_post_gpdb_work(vha, fcport, opt);
424 break;
425
426 case DSC_LS_PORT_UNAVAIL:
427 default:
428 if (fcport->loop_id == FC_NO_LOOP_ID) {
429 qla2x00_find_new_loop_id(vha, fcport);
430 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL;
431 }
432 ql_dbg(ql_dbg_disc, vha, 0xffff,
433 "%s %d %8phC \n",
434 __func__, __LINE__, fcport->port_name);
435 qla24xx_fcport_handle_login(vha, fcport);
436 break;
437 }
438 }
439
440 if (!found) {
441 /* fw has no record of this port */
442 if (fcport->loop_id == FC_NO_LOOP_ID) {
443 qla2x00_find_new_loop_id(vha, fcport);
444 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL;
445 } else {
446 for (i = 0; i < n; i++) {
447 e = &vha->gnl.l[i];
448 id.b.domain = e->port_id[0];
449 id.b.area = e->port_id[1];
450 id.b.al_pa = e->port_id[2];
451 id.b.rsvd_1 = 0;
452 loop_id = le16_to_cpu(e->nport_handle);
453
454 if (fcport->d_id.b24 == id.b24) {
455 conflict_fcport =
456 qla2x00_find_fcport_by_wwpn(vha,
457 e->port_name, 0);
458
459 ql_dbg(ql_dbg_disc, vha, 0xffff,
460 "%s %d %8phC post del sess\n",
461 __func__, __LINE__,
462 conflict_fcport->port_name);
463 qlt_schedule_sess_for_deletion
464 (conflict_fcport, 1);
465 }
466
467 if (fcport->loop_id == loop_id) {
468 /* FW already picked this loop id for another fcport */
469 qla2x00_find_new_loop_id(vha, fcport);
470 }
471 }
472 }
473 qla24xx_fcport_handle_login(vha, fcport);
474 }
475} /* gnl_event */
476
477static void
25ff6af1 478qla24xx_async_gnl_sp_done(void *s, int res)
726b8548 479{
25ff6af1
JC		 480 struct srb *sp = s;
481 struct scsi_qla_host *vha = sp->vha;
726b8548
QT		 482 unsigned long flags;
483 struct fc_port *fcport = NULL, *tf;
484 u16 i, n = 0, loop_id;
485 struct event_arg ea;
486 struct get_name_list_extended *e;
487 u64 wwn;
488 struct list_head h;
489
490 ql_dbg(ql_dbg_disc, vha, 0xffff,
491 "Async done-%s res %x mb[1]=%x mb[2]=%x \n",
492 sp->name, res, sp->u.iocb_cmd.u.mbx.in_mb[1],
493 sp->u.iocb_cmd.u.mbx.in_mb[2]);
494
495 memset(&ea, 0, sizeof(ea));
496 ea.sp = sp;
497 ea.rc = res;
498 ea.event = FCME_GNL_DONE;
499
500 if (sp->u.iocb_cmd.u.mbx.in_mb[1] >=
501 sizeof(struct get_name_list_extended)) {
502 n = sp->u.iocb_cmd.u.mbx.in_mb[1] /
503 sizeof(struct get_name_list_extended);
504 ea.data[0] = sp->u.iocb_cmd.u.mbx.in_mb[1]; /* amnt xfered */
505 }
506
507 for (i = 0; i < n; i++) {
508 e = &vha->gnl.l[i];
509 loop_id = le16_to_cpu(e->nport_handle);
510 /* mask out reserve bit */
511 loop_id = (loop_id & 0x7fff);
512 set_bit(loop_id, vha->hw->loop_id_map);
513 wwn = wwn_to_u64(e->port_name);
514
515 ql_dbg(ql_dbg_disc + ql_dbg_verbose, vha, 0xffff,
516 "%s %8phC %02x:%02x:%02x state %d/%d lid %x \n",
517 __func__, (void *)&wwn, e->port_id[2], e->port_id[1],
518 e->port_id[0], e->current_login_state, e->last_login_state,
519 (loop_id & 0x7fff));
520 }
521
522 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
523 vha->gnl.sent = 0;
524
525 INIT_LIST_HEAD(&h);
526 fcport = tf = NULL;
527 if (!list_empty(&vha->gnl.fcports))
528 list_splice_init(&vha->gnl.fcports, &h);
529
530 list_for_each_entry_safe(fcport, tf, &h, gnl_entry) {
531 list_del_init(&fcport->gnl_entry);
532 fcport->flags &= ~FCF_ASYNC_SENT;
533 ea.fcport = fcport;
534
535 qla2x00_fcport_event_handler(vha, &ea);
536 }
537
538 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
539
25ff6af1 540 sp->free(sp);
726b8548
QT		 541}
542
543int qla24xx_async_gnl(struct scsi_qla_host *vha, fc_port_t *fcport)
544{
545 srb_t *sp;
546 struct srb_iocb *mbx;
547 int rval = QLA_FUNCTION_FAILED;
548 unsigned long flags;
549 u16 *mb;
550
551 if (!vha->flags.online)
552 goto done;
553
554 ql_dbg(ql_dbg_disc, vha, 0xffff,
555 "Async-gnlist WWPN %8phC \n", fcport->port_name);
556
557 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
558 fcport->flags |= FCF_ASYNC_SENT;
559 fcport->disc_state = DSC_GNL;
560 fcport->last_rscn_gen = fcport->rscn_gen;
561 fcport->last_login_gen = fcport->login_gen;
562
563 list_add_tail(&fcport->gnl_entry, &vha->gnl.fcports);
564 if (vha->gnl.sent) {
565 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
566 rval = QLA_SUCCESS;
567 goto done;
568 }
569 vha->gnl.sent = 1;
570 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
571
572 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
573 if (!sp)
574 goto done;
575 sp->type = SRB_MB_IOCB;
576 sp->name = "gnlist";
577 sp->gen1 = fcport->rscn_gen;
578 sp->gen2 = fcport->login_gen;
579
580 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha)+2);
581
582 mb = sp->u.iocb_cmd.u.mbx.out_mb;
583 mb[0] = MBC_PORT_NODE_NAME_LIST;
584 mb[1] = BIT_2 | BIT_3;
585 mb[2] = MSW(vha->gnl.ldma);
586 mb[3] = LSW(vha->gnl.ldma);
587 mb[6] = MSW(MSD(vha->gnl.ldma));
588 mb[7] = LSW(MSD(vha->gnl.ldma));
589 mb[8] = vha->gnl.size;
590 mb[9] = vha->vp_idx;
591
592 mbx = &sp->u.iocb_cmd;
593 mbx->timeout = qla2x00_async_iocb_timeout;
594
595 sp->done = qla24xx_async_gnl_sp_done;
596
597 rval = qla2x00_start_sp(sp);
598 if (rval != QLA_SUCCESS)
599 goto done_free_sp;
600
601 ql_dbg(ql_dbg_disc, vha, 0xffff,
602 "Async-%s - OUT WWPN %8phC hndl %x\n",
603 sp->name, fcport->port_name, sp->handle);
604
605 return rval;
606
607done_free_sp:
25ff6af1 608 sp->free(sp);
726b8548
QT		 609done:
610 fcport->flags &= ~FCF_ASYNC_SENT;
611 return rval;
612}
613
614int qla24xx_post_gnl_work(struct scsi_qla_host *vha, fc_port_t *fcport)
615{
616 struct qla_work_evt *e;
617
618 e = qla2x00_alloc_work(vha, QLA_EVT_GNL);
619 if (!e)
620 return QLA_FUNCTION_FAILED;
621
622 e->u.fcport.fcport = fcport;
623 return qla2x00_post_work(vha, e);
624}
625
626static
25ff6af1 627void qla24xx_async_gpdb_sp_done(void *s, int res)
726b8548 628{
25ff6af1
JC		 629 struct srb *sp = s;
630 struct scsi_qla_host *vha = sp->vha;
726b8548
QT		 631 struct qla_hw_data *ha = vha->hw;
632 uint64_t zero = 0;
633 struct port_database_24xx *pd;
634 fc_port_t *fcport = sp->fcport;
635 u16 *mb = sp->u.iocb_cmd.u.mbx.in_mb;
636 int rval = QLA_SUCCESS;
637 struct event_arg ea;
638
639 ql_dbg(ql_dbg_disc, vha, 0xffff,
640 "Async done-%s res %x, WWPN %8phC mb[1]=%x mb[2]=%x \n",
641 sp->name, res, fcport->port_name, mb[1], mb[2]);
642
643 fcport->flags &= ~FCF_ASYNC_SENT;
644
645 if (res) {
646 rval = res;
647 goto gpd_error_out;
648 }
649
650 pd = (struct port_database_24xx *)sp->u.iocb_cmd.u.mbx.in;
651
652 /* Check for logged in state. */
653 if (pd->current_login_state != PDS_PRLI_COMPLETE &&
654 pd->last_login_state != PDS_PRLI_COMPLETE) {
655 ql_dbg(ql_dbg_mbx, vha, 0xffff,
656 "Unable to verify login-state (%x/%x) for "
657 "loop_id %x.\n", pd->current_login_state,
658 pd->last_login_state, fcport->loop_id);
659 rval = QLA_FUNCTION_FAILED;
660 goto gpd_error_out;
661 }
662
663 if (fcport->loop_id == FC_NO_LOOP_ID ||
664 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
665 memcmp(fcport->port_name, pd->port_name, 8))) {
666 /* We lost the device mid way. */
667 rval = QLA_NOT_LOGGED_IN;
668 goto gpd_error_out;
669 }
670
671 /* Names are little-endian. */
672 memcpy(fcport->node_name, pd->node_name, WWN_SIZE);
673
674 /* Get port_id of device. */
675 fcport->d_id.b.domain = pd->port_id[0];
676 fcport->d_id.b.area = pd->port_id[1];
677 fcport->d_id.b.al_pa = pd->port_id[2];
678 fcport->d_id.b.rsvd_1 = 0;
679
680 /* If not target must be initiator or unknown type. */
681 if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0)
682 fcport->port_type = FCT_INITIATOR;
683 else
684 fcport->port_type = FCT_TARGET;
685
686 /* Passback COS information. */
687 fcport->supported_classes = (pd->flags & PDF_CLASS_2) ?
688 FC_COS_CLASS2 : FC_COS_CLASS3;
689
690 if (pd->prli_svc_param_word_3[0] & BIT_7) {
691 fcport->flags |= FCF_CONF_COMP_SUPPORTED;
692 fcport->conf_compl_supported = 1;
693 }
694
695gpd_error_out:
696 memset(&ea, 0, sizeof(ea));
697 ea.event = FCME_GPDB_DONE;
698 ea.rc = rval;
699 ea.fcport = fcport;
700 ea.sp = sp;
701
702 qla2x00_fcport_event_handler(vha, &ea);
703
704 dma_pool_free(ha->s_dma_pool, sp->u.iocb_cmd.u.mbx.in,
705 sp->u.iocb_cmd.u.mbx.in_dma);
706
25ff6af1 707 sp->free(sp);
726b8548
QT		 708}
709
710static int qla24xx_post_gpdb_work(struct scsi_qla_host *vha, fc_port_t *fcport,
711 u8 opt)
712{
713 struct qla_work_evt *e;
714
715 e = qla2x00_alloc_work(vha, QLA_EVT_GPDB);
716 if (!e)
717 return QLA_FUNCTION_FAILED;
718
719 e->u.fcport.fcport = fcport;
720 e->u.fcport.opt = opt;
721 return qla2x00_post_work(vha, e);
722}
723
724int qla24xx_async_gpdb(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt)
725{
726 srb_t *sp;
727 struct srb_iocb *mbx;
728 int rval = QLA_FUNCTION_FAILED;
729 u16 *mb;
730 dma_addr_t pd_dma;
731 struct port_database_24xx *pd;
732 struct qla_hw_data *ha = vha->hw;
733
734 if (!vha->flags.online)
735 goto done;
736
737 fcport->flags |= FCF_ASYNC_SENT;
738 fcport->disc_state = DSC_GPDB;
739
740 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
741 if (!sp)
742 goto done;
743
744 pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
745 if (pd == NULL) {
746 ql_log(ql_log_warn, vha, 0xffff,
747 "Failed to allocate port database structure.\n");
748 goto done_free_sp;
749 }
750 memset(pd, 0, max(PORT_DATABASE_SIZE, PORT_DATABASE_24XX_SIZE));
751
752 sp->type = SRB_MB_IOCB;
753 sp->name = "gpdb";
754 sp->gen1 = fcport->rscn_gen;
755 sp->gen2 = fcport->login_gen;
756 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
757
758 mb = sp->u.iocb_cmd.u.mbx.out_mb;
759 mb[0] = MBC_GET_PORT_DATABASE;
760 mb[1] = fcport->loop_id;
761 mb[2] = MSW(pd_dma);
762 mb[3] = LSW(pd_dma);
763 mb[6] = MSW(MSD(pd_dma));
764 mb[7] = LSW(MSD(pd_dma));
765 mb[9] = vha->vp_idx;
766 mb[10] = opt;
767
768 mbx = &sp->u.iocb_cmd;
769 mbx->timeout = qla2x00_async_iocb_timeout;
770 mbx->u.mbx.in = (void *)pd;
771 mbx->u.mbx.in_dma = pd_dma;
772
773 sp->done = qla24xx_async_gpdb_sp_done;
774
775 rval = qla2x00_start_sp(sp);
776 if (rval != QLA_SUCCESS)
777 goto done_free_sp;
778
779 ql_dbg(ql_dbg_disc, vha, 0xffff,
780 "Async-%s %8phC hndl %x opt %x\n",
781 sp->name, fcport->port_name, sp->handle, opt);
782
783 return rval;
784
785done_free_sp:
786 if (pd)
787 dma_pool_free(ha->s_dma_pool, pd, pd_dma);
788
25ff6af1 789 sp->free(sp);
726b8548
QT		 790done:
791 fcport->flags &= ~FCF_ASYNC_SENT;
792 qla24xx_post_gpdb_work(vha, fcport, opt);
5ff1d584
AV		 793 return rval;
794}
795
726b8548
QT		 796static
797void qla24xx_handle_gpdb_event(scsi_qla_host_t *vha, struct event_arg *ea)
798{
799 int rval = ea->rc;
800 fc_port_t *fcport = ea->fcport;
801 unsigned long flags;
802
803 fcport->flags &= ~FCF_ASYNC_SENT;
804
805 ql_dbg(ql_dbg_disc, vha, 0xffff,
806 "%s %8phC DS %d LS %d rval %d\n", __func__, fcport->port_name,
807 fcport->disc_state, fcport->fw_login_state, rval);
808
809 if (ea->sp->gen2 != fcport->login_gen) {
810 /* target side must have changed it. */
811 ql_dbg(ql_dbg_disc, vha, 0xffff,
812 "%s %8phC generation changed rscn %d|%d login %d|%d \n",
813 __func__, fcport->port_name, fcport->last_rscn_gen,
814 fcport->rscn_gen, fcport->last_login_gen,
815 fcport->login_gen);
816 return;
817 } else if (ea->sp->gen1 != fcport->rscn_gen) {
818 ql_dbg(ql_dbg_disc, vha, 0xffff, "%s %d %8phC post gidpn\n",
819 __func__, __LINE__, fcport->port_name);
820 qla24xx_post_gidpn_work(vha, fcport);
821 return;
822 }
823
824 if (rval != QLA_SUCCESS) {
825 ql_dbg(ql_dbg_disc, vha, 0xffff, "%s %d %8phC post del sess\n",
826 __func__, __LINE__, fcport->port_name);
827 qlt_schedule_sess_for_deletion_lock(fcport);
828 return;
829 }
830
831 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
832 ea->fcport->login_gen++;
833 ea->fcport->deleted = 0;
834 ea->fcport->logout_on_delete = 1;
835
836 if (!ea->fcport->login_succ && !IS_SW_RESV_ADDR(ea->fcport->d_id)) {
837 vha->fcport_count++;
838 ea->fcport->login_succ = 1;
839
840 if (!IS_IIDMA_CAPABLE(vha->hw) ||
841 !vha->hw->flags.gpsc_supported) {
842 ql_dbg(ql_dbg_disc, vha, 0xffff,
843 "%s %d %8phC post upd_fcport fcp_cnt %d\n",
844 __func__, __LINE__, fcport->port_name,
845 vha->fcport_count);
846
847 qla24xx_post_upd_fcport_work(vha, fcport);
848 } else {
849 ql_dbg(ql_dbg_disc, vha, 0xffff,
850 "%s %d %8phC post gpsc fcp_cnt %d\n",
851 __func__, __LINE__, fcport->port_name,
852 vha->fcport_count);
853
854 qla24xx_post_gpsc_work(vha, fcport);
855 }
856 }
857 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
858} /* gpdb event */
859
860int qla24xx_fcport_handle_login(struct scsi_qla_host *vha, fc_port_t *fcport)
861{
862 if (fcport->login_retry == 0)
863 return 0;
864
865 if (fcport->scan_state != QLA_FCPORT_FOUND)
866 return 0;
867
868 ql_dbg(ql_dbg_disc, vha, 0xffff,
869 "%s %8phC DS %d LS %d P %d fl %x confl %p rscn %d|%d login %d|%d retry %d lid %d\n",
870 __func__, fcport->port_name, fcport->disc_state,
871 fcport->fw_login_state, fcport->login_pause, fcport->flags,
872 fcport->conflict, fcport->last_rscn_gen, fcport->rscn_gen,
873 fcport->last_login_gen, fcport->login_gen, fcport->login_retry,
874 fcport->loop_id);
875
876 fcport->login_retry--;
877
878 if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) ||
726b8548
QT		 879 (fcport->fw_login_state == DSC_LS_PRLI_PEND))
880 return 0;
881
5b33469a
QT		 882 if (fcport->fw_login_state == DSC_LS_PLOGI_COMP) {
883 if (time_before_eq(jiffies, fcport->plogi_nack_done_deadline))
884 return 0;
885 }
886
726b8548
QT		 887 /* for pure Target Mode. Login will not be initiated */
888 if (vha->host->active_mode == MODE_TARGET)
889 return 0;
890
891 if (fcport->flags & FCF_ASYNC_SENT) {
892 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
893 return 0;
894 }
895
896 switch (fcport->disc_state) {
897 case DSC_DELETED:
898 if (fcport->loop_id == FC_NO_LOOP_ID) {
899 ql_dbg(ql_dbg_disc, vha, 0xffff,
900 "%s %d %8phC post gnl\n",
901 __func__, __LINE__, fcport->port_name);
902 qla24xx_async_gnl(vha, fcport);
903 } else {
904 ql_dbg(ql_dbg_disc, vha, 0xffff,
905 "%s %d %8phC post login\n",
906 __func__, __LINE__, fcport->port_name);
907 fcport->disc_state = DSC_LOGIN_PEND;
908 qla2x00_post_async_login_work(vha, fcport, NULL);
909 }
910 break;
911
912 case DSC_GNL:
913 if (fcport->login_pause) {
914 fcport->last_rscn_gen = fcport->rscn_gen;
915 fcport->last_login_gen = fcport->login_gen;
916 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
917 break;
918 }
919
920 if (fcport->flags & FCF_FCP2_DEVICE) {
921 u8 opt = PDO_FORCE_ADISC;
922
923 ql_dbg(ql_dbg_disc, vha, 0xffff,
924 "%s %d %8phC post gpdb\n",
925 __func__, __LINE__, fcport->port_name);
926
927 fcport->disc_state = DSC_GPDB;
928 qla24xx_post_gpdb_work(vha, fcport, opt);
929 } else {
930 ql_dbg(ql_dbg_disc, vha, 0xffff,
931 "%s %d %8phC post login \n",
932 __func__, __LINE__, fcport->port_name);
933 fcport->disc_state = DSC_LOGIN_PEND;
934 qla2x00_post_async_login_work(vha, fcport, NULL);
935 }
936
937 break;
938
939 case DSC_LOGIN_FAILED:
940 ql_dbg(ql_dbg_disc, vha, 0xffff,
941 "%s %d %8phC post gidpn \n",
942 __func__, __LINE__, fcport->port_name);
943
944 qla24xx_post_gidpn_work(vha, fcport);
945 break;
946
947 case DSC_LOGIN_COMPLETE:
948 /* recheck login state */
949 ql_dbg(ql_dbg_disc, vha, 0xffff,
950 "%s %d %8phC post gpdb \n",
951 __func__, __LINE__, fcport->port_name);
952
953 qla24xx_post_gpdb_work(vha, fcport, PDO_FORCE_ADISC);
954 break;
955
956 default:
957 break;
958 }
959
960 return 0;
961}
962
963static
964void qla24xx_handle_rscn_event(fc_port_t *fcport, struct event_arg *ea)
965{
966 fcport->rscn_gen++;
967
968 ql_dbg(ql_dbg_disc, fcport->vha, 0xffff,
969 "%s %8phC DS %d LS %d\n",
970 __func__, fcport->port_name, fcport->disc_state,
971 fcport->fw_login_state);
972
973 if (fcport->flags & FCF_ASYNC_SENT)
974 return;
975
976 switch (fcport->disc_state) {
977 case DSC_DELETED:
978 case DSC_LOGIN_COMPLETE:
979 qla24xx_post_gidpn_work(fcport->vha, fcport);
980 break;
981
982 default:
983 break;
984 }
985}
986
987int qla24xx_post_newsess_work(struct scsi_qla_host *vha, port_id_t *id,
988 u8 *port_name, void *pla)
989{
990 struct qla_work_evt *e;
991 e = qla2x00_alloc_work(vha, QLA_EVT_NEW_SESS);
992 if (!e)
993 return QLA_FUNCTION_FAILED;
994
995 e->u.new_sess.id = *id;
996 e->u.new_sess.pla = pla;
997 memcpy(e->u.new_sess.port_name, port_name, WWN_SIZE);
998
999 return qla2x00_post_work(vha, e);
1000}
1001
1002static
1003int qla24xx_handle_delete_done_event(scsi_qla_host_t *vha,
1004 struct event_arg *ea)
1005{
1006 fc_port_t *fcport = ea->fcport;
1007
1008 if (test_bit(UNLOADING, &vha->dpc_flags))
1009 return 0;
1010
1011 switch (vha->host->active_mode) {
1012 case MODE_INITIATOR:
1013 case MODE_DUAL:
1014 if (fcport->scan_state == QLA_FCPORT_FOUND)
1015 qla24xx_fcport_handle_login(vha, fcport);
1016 break;
1017
1018 case MODE_TARGET:
1019 default:
1020 /* no-op */
1021 break;
1022 }
1023
1024 return 0;
1025}
1026
1027static
1028void qla24xx_handle_relogin_event(scsi_qla_host_t *vha,
1029 struct event_arg *ea)
1030{
1031 fc_port_t *fcport = ea->fcport;
1032
1033 if (fcport->scan_state != QLA_FCPORT_FOUND) {
1034 fcport->login_retry++;
1035 return;
1036 }
1037
1038 ql_dbg(ql_dbg_disc, vha, 0xffff,
1039 "%s %8phC DS %d LS %d P %d del %d cnfl %p rscn %d|%d login %d|%d fl %x\n",
1040 __func__, fcport->port_name, fcport->disc_state,
1041 fcport->fw_login_state, fcport->login_pause,
1042 fcport->deleted, fcport->conflict,
1043 fcport->last_rscn_gen, fcport->rscn_gen,
1044 fcport->last_login_gen, fcport->login_gen,
1045 fcport->flags);
1046
1047 if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) ||
726b8548
QT		 1048 (fcport->fw_login_state == DSC_LS_PRLI_PEND))
1049 return;
1050
5b33469a
QT		 1051 if (fcport->fw_login_state == DSC_LS_PLOGI_COMP) {
1052 if (time_before_eq(jiffies, fcport->plogi_nack_done_deadline))
1053 return;
1054 }
1055
726b8548
QT		 1056 if (fcport->flags & FCF_ASYNC_SENT) {
1057 fcport->login_retry++;
1058 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1059 return;
1060 }
1061
1062 if (fcport->disc_state == DSC_DELETE_PEND) {
1063 fcport->login_retry++;
1064 return;
1065 }
1066
1067 if (fcport->last_rscn_gen != fcport->rscn_gen) {
1068 ql_dbg(ql_dbg_disc, vha, 0xffff, "%s %d %8phC post gidpn\n",
1069 __func__, __LINE__, fcport->port_name);
1070
1071 qla24xx_async_gidpn(vha, fcport);
1072 return;
1073 }
1074
1075 qla24xx_fcport_handle_login(vha, fcport);
1076}
1077
41dc529a 1078void qla2x00_fcport_event_handler(scsi_qla_host_t *vha, struct event_arg *ea)
726b8548 1079{
41dc529a
QT		 1080 fc_port_t *fcport, *f, *tf;
1081 uint32_t id = 0, mask, rid;
726b8548
QT		 1082 int rc;
1083
1084 switch (ea->event) {
1085 case FCME_RELOGIN:
1086 if (test_bit(UNLOADING, &vha->dpc_flags))
1087 return;
5ff1d584 1088
726b8548
QT		 1089 qla24xx_handle_relogin_event(vha, ea);
1090 break;
1091 case FCME_RSCN:
1092 if (test_bit(UNLOADING, &vha->dpc_flags))
1093 return;
41dc529a
QT		 1094 switch (ea->id.b.rsvd_1) {
1095 case RSCN_PORT_ADDR:
1096 fcport = qla2x00_find_fcport_by_nportid(vha, &ea->id, 1);
1097 if (!fcport) {
1098 /* cable moved */
1099 rc = qla24xx_post_gpnid_work(vha, &ea->id);
1100 if (rc) {
1101 ql_log(ql_log_warn, vha, 0xffff,
1102 "RSCN GPNID work failed %02x%02x%02x\n",
1103 ea->id.b.domain, ea->id.b.area,
1104 ea->id.b.al_pa);
1105 }
1106 } else {
1107 ea->fcport = fcport;
1108 qla24xx_handle_rscn_event(fcport, ea);
1109 }
1110 break;
1111 case RSCN_AREA_ADDR:
1112 case RSCN_DOM_ADDR:
1113 if (ea->id.b.rsvd_1 == RSCN_AREA_ADDR) {
1114 mask = 0xffff00;
1115 ql_log(ql_dbg_async, vha, 0xffff,
1116 "RSCN: Area 0x%06x was affected\n",
1117 ea->id.b24);
1118 } else {
1119 mask = 0xff0000;
1120 ql_log(ql_dbg_async, vha, 0xffff,
1121 "RSCN: Domain 0x%06x was affected\n",
1122 ea->id.b24);
1123 }
726b8548 1124
41dc529a
QT		 1125 rid = ea->id.b24 & mask;
1126 list_for_each_entry_safe(f, tf, &vha->vp_fcports,
1127 list) {
1128 id = f->d_id.b24 & mask;
1129 if (rid == id) {
1130 ea->fcport = f;
1131 qla24xx_handle_rscn_event(f, ea);
1132 }
726b8548 1133 }
41dc529a
QT		 1134 break;
1135 case RSCN_FAB_ADDR:
1136 default:
1137 ql_log(ql_log_warn, vha, 0xffff,
1138 "RSCN: Fabric was affected. Addr format %d\n",
1139 ea->id.b.rsvd_1);
1140 qla2x00_mark_all_devices_lost(vha, 1);
1141 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1142 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
726b8548
QT		 1143 }
1144 break;
1145 case FCME_GIDPN_DONE:
1146 qla24xx_handle_gidpn_event(vha, ea);
1147 break;
1148 case FCME_GNL_DONE:
1149 qla24xx_handle_gnl_done_event(vha, ea);
1150 break;
1151 case FCME_GPSC_DONE:
1152 qla24xx_post_upd_fcport_work(vha, ea->fcport);
1153 break;
1154 case FCME_PLOGI_DONE: /* Initiator side sent LLIOCB */
1155 qla24xx_handle_plogi_done_event(vha, ea);
1156 break;
1157 case FCME_GPDB_DONE:
1158 qla24xx_handle_gpdb_event(vha, ea);
1159 break;
1160 case FCME_GPNID_DONE:
1161 qla24xx_handle_gpnid_event(vha, ea);
1162 break;
1163 case FCME_DELETE_DONE:
1164 qla24xx_handle_delete_done_event(vha, ea);
1165 break;
1166 default:
1167 BUG_ON(1);
1168 break;
1169 }
5ff1d584
AV		 1170}
1171
3822263e 1172static void
faef62d1 1173qla2x00_tmf_iocb_timeout(void *data)
3822263e 1174{
25ff6af1 1175 srb_t *sp = data;
faef62d1 1176 struct srb_iocb *tmf = &sp->u.iocb_cmd;
3822263e 1177
faef62d1
AB		 1178 tmf->u.tmf.comp_status = CS_TIMEOUT;
1179 complete(&tmf->u.tmf.comp);
1180}
9ba56b95 1181
faef62d1 1182static void
25ff6af1 1183qla2x00_tmf_sp_done(void *ptr, int res)
faef62d1 1184{
25ff6af1 1185 srb_t *sp = ptr;
faef62d1 1186 struct srb_iocb *tmf = &sp->u.iocb_cmd;
25ff6af1 1187
faef62d1 1188 complete(&tmf->u.tmf.comp);
3822263e
MI		 1189}
1190
1191int
faef62d1 1192qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t flags, uint32_t lun,
3822263e
MI		 1193 uint32_t tag)
1194{
1195 struct scsi_qla_host *vha = fcport->vha;
faef62d1 1196 struct srb_iocb *tm_iocb;
3822263e 1197 srb_t *sp;
faef62d1 1198 int rval = QLA_FUNCTION_FAILED;
3822263e 1199
9ba56b95 1200 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
3822263e
MI		 1201 if (!sp)
1202 goto done;
1203
faef62d1 1204 tm_iocb = &sp->u.iocb_cmd;
9ba56b95
GM		 1205 sp->type = SRB_TM_CMD;
1206 sp->name = "tmf";
faef62d1
AB		 1207 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
1208 tm_iocb->u.tmf.flags = flags;
1209 tm_iocb->u.tmf.lun = lun;
1210 tm_iocb->u.tmf.data = tag;
1211 sp->done = qla2x00_tmf_sp_done;
1212 tm_iocb->timeout = qla2x00_tmf_iocb_timeout;
1213 init_completion(&tm_iocb->u.tmf.comp);
3822263e
MI		 1214
1215 rval = qla2x00_start_sp(sp);
1216 if (rval != QLA_SUCCESS)
1217 goto done_free_sp;
1218
7c3df132 1219 ql_dbg(ql_dbg_taskm, vha, 0x802f,
cfb0919c
CD		 1220 "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
1221 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
1222 fcport->d_id.b.area, fcport->d_id.b.al_pa);
faef62d1
AB		 1223
1224 wait_for_completion(&tm_iocb->u.tmf.comp);
1225
1226 rval = tm_iocb->u.tmf.comp_status == CS_COMPLETE ?
1227 QLA_SUCCESS : QLA_FUNCTION_FAILED;
1228
1229 if ((rval != QLA_SUCCESS) || tm_iocb->u.tmf.data) {
1230 ql_dbg(ql_dbg_taskm, vha, 0x8030,
1231 "TM IOCB failed (%x).\n", rval);
1232 }
1233
1234 if (!test_bit(UNLOADING, &vha->dpc_flags) && !IS_QLAFX00(vha->hw)) {
1235 flags = tm_iocb->u.tmf.flags;
1236 lun = (uint16_t)tm_iocb->u.tmf.lun;
1237
1238 /* Issue Marker IOCB */
1239 qla2x00_marker(vha, vha->hw->req_q_map[0],
1240 vha->hw->rsp_q_map[0], sp->fcport->loop_id, lun,
1241 flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
1242 }
3822263e
MI		 1243
1244done_free_sp:
25ff6af1 1245 sp->free(sp);
3822263e
MI		 1246done:
1247 return rval;
1248}
1249
4440e46d
AB		 1250static void
1251qla24xx_abort_iocb_timeout(void *data)
1252{
25ff6af1 1253 srb_t *sp = data;
4440e46d
AB		 1254 struct srb_iocb *abt = &sp->u.iocb_cmd;
1255
1256 abt->u.abt.comp_status = CS_TIMEOUT;
1257 complete(&abt->u.abt.comp);
1258}
1259
1260static void
25ff6af1 1261qla24xx_abort_sp_done(void *ptr, int res)
4440e46d 1262{
25ff6af1 1263 srb_t *sp = ptr;
4440e46d
AB		 1264 struct srb_iocb *abt = &sp->u.iocb_cmd;
1265
1266 complete(&abt->u.abt.comp);
1267}
1268
1269static int
1270qla24xx_async_abort_cmd(srb_t *cmd_sp)
1271{
25ff6af1 1272 scsi_qla_host_t *vha = cmd_sp->vha;
4440e46d
AB		 1273 fc_port_t *fcport = cmd_sp->fcport;
1274 struct srb_iocb *abt_iocb;
1275 srb_t *sp;
1276 int rval = QLA_FUNCTION_FAILED;
1277
1278 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
1279 if (!sp)
1280 goto done;
1281
1282 abt_iocb = &sp->u.iocb_cmd;
1283 sp->type = SRB_ABT_CMD;
1284 sp->name = "abort";
1285 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
1286 abt_iocb->u.abt.cmd_hndl = cmd_sp->handle;
1287 sp->done = qla24xx_abort_sp_done;
1288 abt_iocb->timeout = qla24xx_abort_iocb_timeout;
1289 init_completion(&abt_iocb->u.abt.comp);
1290
1291 rval = qla2x00_start_sp(sp);
1292 if (rval != QLA_SUCCESS)
1293 goto done_free_sp;
1294
1295 ql_dbg(ql_dbg_async, vha, 0x507c,
1296 "Abort command issued - hdl=%x, target_id=%x\n",
1297 cmd_sp->handle, fcport->tgt_id);
1298
1299 wait_for_completion(&abt_iocb->u.abt.comp);
1300
1301 rval = abt_iocb->u.abt.comp_status == CS_COMPLETE ?
1302 QLA_SUCCESS : QLA_FUNCTION_FAILED;
1303
1304done_free_sp:
25ff6af1 1305 sp->free(sp);
4440e46d
AB		 1306done:
1307 return rval;
1308}
1309
1310int
1311qla24xx_async_abort_command(srb_t *sp)
1312{
1313 unsigned long flags = 0;
1314
1315 uint32_t handle;
1316 fc_port_t *fcport = sp->fcport;
1317 struct scsi_qla_host *vha = fcport->vha;
1318 struct qla_hw_data *ha = vha->hw;
1319 struct req_que *req = vha->req;
1320
1321 spin_lock_irqsave(&ha->hardware_lock, flags);
1322 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
1323 if (req->outstanding_cmds[handle] == sp)
1324 break;
1325 }
1326 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1327 if (handle == req->num_outstanding_cmds) {
1328 /* Command not found. */
1329 return QLA_FUNCTION_FAILED;
1330 }
1331 if (sp->type == SRB_FXIOCB_DCMD)
1332 return qlafx00_fx_disc(vha, &vha->hw->mr.fcport,
1333 FXDISC_ABORT_IOCTL);
1334
1335 return qla24xx_async_abort_cmd(sp);
1336}
1337
726b8548
QT		 1338static void
1339qla24xx_handle_plogi_done_event(struct scsi_qla_host *vha, struct event_arg *ea)
ac280b67 1340{
726b8548 1341 port_id_t cid; /* conflict Nport id */
ac280b67 1342
726b8548 1343 switch (ea->data[0]) {
ac280b67 1344 case MBS_COMMAND_COMPLETE:
a4f92a32
AV		 1345 /*
1346 * Driver must validate login state - If PRLI not complete,
1347 * force a relogin attempt via implicit LOGO, PLOGI, and PRLI
1348 * requests.
1349 */
726b8548
QT		 1350 ql_dbg(ql_dbg_disc, vha, 0xffff,
1351 "%s %d %8phC post gpdb\n",
1352 __func__, __LINE__, ea->fcport->port_name);
1353 ea->fcport->chip_reset = vha->hw->chip_reset;
1354 ea->fcport->logout_on_delete = 1;
1355 qla24xx_post_gpdb_work(vha, ea->fcport, 0);
ac280b67
AV		 1356 break;
1357 case MBS_COMMAND_ERROR:
726b8548
QT		 1358 ql_dbg(ql_dbg_disc, vha, 0xffff, "%s %d %8phC cmd error %x\n",
1359 __func__, __LINE__, ea->fcport->port_name, ea->data[1]);
1360
1361 ea->fcport->flags &= ~FCF_ASYNC_SENT;
1362 ea->fcport->disc_state = DSC_LOGIN_FAILED;
1363 if (ea->data[1] & QLA_LOGIO_LOGIN_RETRIED)
ac280b67
AV		 1364 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1365 else
726b8548 1366 qla2x00_mark_device_lost(vha, ea->fcport, 1, 0);
ac280b67
AV		 1367 break;
1368 case MBS_LOOP_ID_USED:
726b8548
QT		 1369 /* data[1] = IO PARAM 1 = nport ID */
1370 cid.b.domain = (ea->iop[1] >> 16) & 0xff;
1371 cid.b.area = (ea->iop[1] >> 8) & 0xff;
1372 cid.b.al_pa = ea->iop[1] & 0xff;
1373 cid.b.rsvd_1 = 0;
1374
1375 ql_dbg(ql_dbg_disc, vha, 0xffff,
1376 "%s %d %8phC LoopID 0x%x in use post gnl\n",
1377 __func__, __LINE__, ea->fcport->port_name,
1378 ea->fcport->loop_id);
1379
1380 if (IS_SW_RESV_ADDR(cid)) {
1381 set_bit(ea->fcport->loop_id, vha->hw->loop_id_map);
1382 ea->fcport->loop_id = FC_NO_LOOP_ID;
1383 } else {
1384 qla2x00_clear_loop_id(ea->fcport);
ac280b67 1385 }
726b8548
QT		 1386 qla24xx_post_gnl_work(vha, ea->fcport);
1387 break;
1388 case MBS_PORT_ID_USED:
1389 ql_dbg(ql_dbg_disc, vha, 0xffff,
1390 "%s %d %8phC NPortId %02x%02x%02x inuse post gidpn\n",
1391 __func__, __LINE__, ea->fcport->port_name,
1392 ea->fcport->d_id.b.domain, ea->fcport->d_id.b.area,
1393 ea->fcport->d_id.b.al_pa);
1394
1395 qla2x00_clear_loop_id(ea->fcport);
1396 qla24xx_post_gidpn_work(vha, ea->fcport);
ac280b67
AV		 1397 break;
1398 }
4916392b 1399 return;
ac280b67
AV		 1400}
1401
4916392b 1402void
ac280b67
AV		 1403qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport,
1404 uint16_t *data)
1405{
726b8548 1406 qla2x00_mark_device_lost(vha, fcport, 1, 0);
a6ca8878 1407 qlt_logo_completion_handler(fcport, data[0]);
726b8548 1408 fcport->login_gen++;
4916392b 1409 return;
ac280b67
AV		 1410}
1411
4916392b 1412void
5ff1d584
AV		 1413qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport,
1414 uint16_t *data)
1415{
1416 if (data[0] == MBS_COMMAND_COMPLETE) {
1417 qla2x00_update_fcport(vha, fcport);
1418
4916392b 1419 return;
5ff1d584
AV		 1420 }
1421
1422 /* Retry login. */
1423 fcport->flags &= ~FCF_ASYNC_SENT;
1424 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
1425 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1426 else
80d79440 1427 qla2x00_mark_device_lost(vha, fcport, 1, 0);
5ff1d584 1428
4916392b 1429 return;
5ff1d584
AV		 1430}
1431
1da177e4
LT		 1432/****************************************************************************/
1433/* QLogic ISP2x00 Hardware Support Functions. */
1434/****************************************************************************/
1435
fa492630 1436static int
7d613ac6
SV		 1437qla83xx_nic_core_fw_load(scsi_qla_host_t *vha)
1438{
1439 int rval = QLA_SUCCESS;
1440 struct qla_hw_data *ha = vha->hw;
1441 uint32_t idc_major_ver, idc_minor_ver;
711aa7f7 1442 uint16_t config[4];
7d613ac6
SV		 1443
1444 qla83xx_idc_lock(vha, 0);
1445
1446 /* SV: TODO: Assign initialization timeout from
1447 * flash-info / other param
1448 */
1449 ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT;
1450 ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT;
1451
1452 /* Set our fcoe function presence */
1453 if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) {
1454 ql_dbg(ql_dbg_p3p, vha, 0xb077,
1455 "Error while setting DRV-Presence.\n");
1456 rval = QLA_FUNCTION_FAILED;
1457 goto exit;
1458 }
1459
1460 /* Decide the reset ownership */
1461 qla83xx_reset_ownership(vha);
1462
1463 /*
1464 * On first protocol driver load:
1465 * Init-Owner: Set IDC-Major-Version and Clear IDC-Lock-Recovery
1466 * register.
1467 * Others: Check compatibility with current IDC Major version.
1468 */
1469 qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver);
1470 if (ha->flags.nic_core_reset_owner) {
1471 /* Set IDC Major version */
1472 idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION;
1473 qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver);
1474
1475 /* Clearing IDC-Lock-Recovery register */
1476 qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0);
1477 } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) {
1478 /*
1479 * Clear further IDC participation if we are not compatible with
1480 * the current IDC Major Version.
1481 */
1482 ql_log(ql_log_warn, vha, 0xb07d,
1483 "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n",
1484 idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION);
1485 __qla83xx_clear_drv_presence(vha);
1486 rval = QLA_FUNCTION_FAILED;
1487 goto exit;
1488 }
1489 /* Each function sets its supported Minor version. */
1490 qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver);
1491 idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2));
1492 qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver);
1493
711aa7f7
SK		 1494 if (ha->flags.nic_core_reset_owner) {
1495 memset(config, 0, sizeof(config));
1496 if (!qla81xx_get_port_config(vha, config))
1497 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
1498 QLA8XXX_DEV_READY);
1499 }
1500
7d613ac6
SV		 1501 rval = qla83xx_idc_state_handler(vha);
1502
1503exit:
1504 qla83xx_idc_unlock(vha, 0);
1505
1506 return rval;
1507}
1508
1da177e4
LT		 1509/*
1510* qla2x00_initialize_adapter
1511* Initialize board.
1512*
1513* Input:
1514* ha = adapter block pointer.
1515*
1516* Returns:
1517* 0 = success
1518*/
1519int
e315cd28 1520qla2x00_initialize_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 1521{
1522 int rval;
e315cd28 1523 struct qla_hw_data *ha = vha->hw;
73208dfd 1524 struct req_que *req = ha->req_q_map[0];
2533cf67 1525
fc90adaf
JC		 1526 memset(&vha->qla_stats, 0, sizeof(vha->qla_stats));
1527 memset(&vha->fc_host_stat, 0, sizeof(vha->fc_host_stat));
1528
1da177e4 1529 /* Clear adapter flags. */
e315cd28 1530 vha->flags.online = 0;
2533cf67 1531 ha->flags.chip_reset_done = 0;
e315cd28 1532 vha->flags.reset_active = 0;
85880801
AV		 1533 ha->flags.pci_channel_io_perm_failure = 0;
1534 ha->flags.eeh_busy = 0;
fabbb8df 1535 vha->qla_stats.jiffies_at_last_reset = get_jiffies_64();
e315cd28
AC		 1536 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1537 atomic_set(&vha->loop_state, LOOP_DOWN);
1538 vha->device_flags = DFLG_NO_CABLE;
1539 vha->dpc_flags = 0;
1540 vha->flags.management_server_logged_in = 0;
1541 vha->marker_needed = 0;
1da177e4
LT		 1542 ha->isp_abort_cnt = 0;
1543 ha->beacon_blink_led = 0;
1544
73208dfd
AC		 1545 set_bit(0, ha->req_qid_map);
1546 set_bit(0, ha->rsp_qid_map);
1547
cfb0919c 1548 ql_dbg(ql_dbg_init, vha, 0x0040,
7c3df132 1549 "Configuring PCI space...\n");
e315cd28 1550 rval = ha->isp_ops->pci_config(vha);
1da177e4 1551 if (rval) {
7c3df132
SK		 1552 ql_log(ql_log_warn, vha, 0x0044,
1553 "Unable to configure PCI space.\n");
1da177e4
LT		 1554 return (rval);
1555 }
1556
e315cd28 1557 ha->isp_ops->reset_chip(vha);
1da177e4 1558
e315cd28 1559 rval = qla2xxx_get_flash_info(vha);
c00d8994 1560 if (rval) {
7c3df132
SK		 1561 ql_log(ql_log_fatal, vha, 0x004f,
1562 "Unable to validate FLASH data.\n");
7ec0effd
AD		 1563 return rval;
1564 }
1565
1566 if (IS_QLA8044(ha)) {
1567 qla8044_read_reset_template(vha);
1568
1569 /* NOTE: If ql2xdontresethba==1, set IDC_CTRL DONTRESET_BIT0.
1570 * If DONRESET_BIT0 is set, drivers should not set dev_state
1571 * to NEED_RESET. But if NEED_RESET is set, drivers should
1572 * should honor the reset. */
1573 if (ql2xdontresethba == 1)
1574 qla8044_set_idc_dontreset(vha);
c00d8994
AV		 1575 }
1576
73208dfd 1577 ha->isp_ops->get_flash_version(vha, req->ring);
cfb0919c 1578 ql_dbg(ql_dbg_init, vha, 0x0061,
7c3df132 1579 "Configure NVRAM parameters...\n");
0107109e 1580
e315cd28 1581 ha->isp_ops->nvram_config(vha);
1da177e4 1582
d4c760c2
AV		 1583 if (ha->flags.disable_serdes) {
1584 /* Mask HBA via NVRAM settings? */
7c3df132 1585 ql_log(ql_log_info, vha, 0x0077,
7b833558 1586 "Masking HBA WWPN %8phN (via NVRAM).\n", vha->port_name);
d4c760c2
AV		 1587 return QLA_FUNCTION_FAILED;
1588 }
1589
cfb0919c 1590 ql_dbg(ql_dbg_init, vha, 0x0078,
7c3df132 1591 "Verifying loaded RISC code...\n");
1da177e4 1592
e315cd28
AC		 1593 if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) {
1594 rval = ha->isp_ops->chip_diag(vha);
d19044c3
AV		 1595 if (rval)
1596 return (rval);
e315cd28 1597 rval = qla2x00_setup_chip(vha);
d19044c3
AV		 1598 if (rval)
1599 return (rval);
1da177e4 1600 }
a9083016 1601
4d4df193 1602 if (IS_QLA84XX(ha)) {
e315cd28 1603 ha->cs84xx = qla84xx_get_chip(vha);
4d4df193 1604 if (!ha->cs84xx) {
7c3df132 1605 ql_log(ql_log_warn, vha, 0x00d0,
4d4df193
HK		 1606 "Unable to configure ISP84XX.\n");
1607 return QLA_FUNCTION_FAILED;
1608 }
1609 }
2d70c103 1610
ead03855 1611 if (qla_ini_mode_enabled(vha) || qla_dual_mode_enabled(vha))
2d70c103
NB		 1612 rval = qla2x00_init_rings(vha);
1613
2533cf67 1614 ha->flags.chip_reset_done = 1;
1da177e4 1615
9a069e19 1616 if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) {
6c452a45 1617 /* Issue verify 84xx FW IOCB to complete 84xx initialization */
9a069e19
GM		 1618 rval = qla84xx_init_chip(vha);
1619 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1620 ql_log(ql_log_warn, vha, 0x00d4,
1621 "Unable to initialize ISP84XX.\n");
8d2b21db 1622 qla84xx_put_chip(vha);
9a069e19
GM		 1623 }
1624 }
1625
7d613ac6
SV		 1626 /* Load the NIC Core f/w if we are the first protocol driver. */
1627 if (IS_QLA8031(ha)) {
1628 rval = qla83xx_nic_core_fw_load(vha);
1629 if (rval)
1630 ql_log(ql_log_warn, vha, 0x0124,
1631 "Error in initializing NIC Core f/w.\n");
1632 }
1633
2f0f3f4f
MI		 1634 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
1635 qla24xx_read_fcp_prio_cfg(vha);
09ff701a 1636
c46e65c7
JC		 1637 if (IS_P3P_TYPE(ha))
1638 qla82xx_set_driver_version(vha, QLA2XXX_VERSION);
1639 else
1640 qla25xx_set_driver_version(vha, QLA2XXX_VERSION);
1641
1da177e4
LT		 1642 return (rval);
1643}
1644
1645/**
abbd8870 1646 * qla2100_pci_config() - Setup ISP21xx PCI configuration registers.
1da177e4
LT		 1647 * @ha: HA context
1648 *
1649 * Returns 0 on success.
1650 */
abbd8870 1651int
e315cd28 1652qla2100_pci_config(scsi_qla_host_t *vha)
1da177e4 1653{
a157b101 1654 uint16_t w;
abbd8870 1655 unsigned long flags;
e315cd28 1656 struct qla_hw_data *ha = vha->hw;
3d71644c 1657 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 1658
1da177e4 1659 pci_set_master(ha->pdev);
af6177d8 1660 pci_try_set_mwi(ha->pdev);
1da177e4 1661
1da177e4 1662 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 1663 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
abbd8870
AV		 1664 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1665
737faece 1666 pci_disable_rom(ha->pdev);
1da177e4
LT		 1667
1668 /* Get PCI bus information. */
1669 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 1670 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
1da177e4
LT		 1671 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1672
abbd8870
AV		 1673 return QLA_SUCCESS;
1674}
1da177e4 1675
abbd8870
AV		 1676/**
1677 * qla2300_pci_config() - Setup ISP23xx PCI configuration registers.
1678 * @ha: HA context
1679 *
1680 * Returns 0 on success.
1681 */
1682int
e315cd28 1683qla2300_pci_config(scsi_qla_host_t *vha)
abbd8870 1684{
a157b101 1685 uint16_t w;
abbd8870
AV		 1686 unsigned long flags = 0;
1687 uint32_t cnt;
e315cd28 1688 struct qla_hw_data *ha = vha->hw;
3d71644c 1689 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 1690
abbd8870 1691 pci_set_master(ha->pdev);
af6177d8 1692 pci_try_set_mwi(ha->pdev);
1da177e4 1693
abbd8870 1694 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 1695 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
1da177e4 1696
abbd8870
AV		 1697 if (IS_QLA2322(ha) || IS_QLA6322(ha))
1698 w &= ~PCI_COMMAND_INTX_DISABLE;
a157b101 1699 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1da177e4 1700
abbd8870
AV		 1701 /*
1702 * If this is a 2300 card and not 2312, reset the
1703 * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately,
1704 * the 2310 also reports itself as a 2300 so we need to get the
1705 * fb revision level -- a 6 indicates it really is a 2300 and
1706 * not a 2310.
1707 */
1708 if (IS_QLA2300(ha)) {
1709 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1710
abbd8870 1711 /* Pause RISC. */
3d71644c 1712 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
abbd8870 1713 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 1714 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
abbd8870 1715 break;
1da177e4 1716
abbd8870
AV		 1717 udelay(10);
1718 }
1da177e4 1719
abbd8870 1720 /* Select FPM registers. */
3d71644c
AV		 1721 WRT_REG_WORD(&reg->ctrl_status, 0x20);
1722 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 1723
1724 /* Get the fb rev level */
3d71644c 1725 ha->fb_rev = RD_FB_CMD_REG(ha, reg);
abbd8870
AV		 1726
1727 if (ha->fb_rev == FPM_2300)
a157b101 1728 pci_clear_mwi(ha->pdev);
abbd8870
AV		 1729
1730 /* Deselect FPM registers. */
3d71644c
AV		 1731 WRT_REG_WORD(&reg->ctrl_status, 0x0);
1732 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 1733
1734 /* Release RISC module. */
3d71644c 1735 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
abbd8870 1736 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 1737 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0)
abbd8870
AV		 1738 break;
1739
1740 udelay(10);
1da177e4 1741 }
1da177e4 1742
abbd8870
AV		 1743 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1744 }
1da177e4 1745
abbd8870
AV		 1746 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
1747
737faece 1748 pci_disable_rom(ha->pdev);
1da177e4 1749
abbd8870
AV		 1750 /* Get PCI bus information. */
1751 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 1752 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 1753 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1754
1755 return QLA_SUCCESS;
1da177e4
LT		 1756}
1757
0107109e
AV		 1758/**
1759 * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers.
1760 * @ha: HA context
1761 *
1762 * Returns 0 on success.
1763 */
1764int
e315cd28 1765qla24xx_pci_config(scsi_qla_host_t *vha)
0107109e 1766{
a157b101 1767 uint16_t w;
0107109e 1768 unsigned long flags = 0;
e315cd28 1769 struct qla_hw_data *ha = vha->hw;
0107109e 1770 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
0107109e
AV		 1771
1772 pci_set_master(ha->pdev);
af6177d8 1773 pci_try_set_mwi(ha->pdev);
0107109e
AV		 1774
1775 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 1776 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
0107109e
AV		 1777 w &= ~PCI_COMMAND_INTX_DISABLE;
1778 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1779
1780 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
1781
1782 /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */
f85ec187
AV		 1783 if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
1784 pcix_set_mmrbc(ha->pdev, 2048);
0107109e
AV		 1785
1786 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 1787 if (pci_is_pcie(ha->pdev))
5ffd3a52 1788 pcie_set_readrq(ha->pdev, 4096);
0107109e 1789
737faece 1790 pci_disable_rom(ha->pdev);
0107109e 1791
44c10138 1792 ha->chip_revision = ha->pdev->revision;
a8488abe 1793
0107109e
AV		 1794 /* Get PCI bus information. */
1795 spin_lock_irqsave(&ha->hardware_lock, flags);
1796 ha->pci_attr = RD_REG_DWORD(&reg->ctrl_status);
1797 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1798
1799 return QLA_SUCCESS;
1800}
1801
c3a2f0df
AV		 1802/**
1803 * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers.
1804 * @ha: HA context
1805 *
1806 * Returns 0 on success.
1807 */
1808int
e315cd28 1809qla25xx_pci_config(scsi_qla_host_t *vha)
c3a2f0df
AV		 1810{
1811 uint16_t w;
e315cd28 1812 struct qla_hw_data *ha = vha->hw;
c3a2f0df
AV		 1813
1814 pci_set_master(ha->pdev);
1815 pci_try_set_mwi(ha->pdev);
1816
1817 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
1818 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
1819 w &= ~PCI_COMMAND_INTX_DISABLE;
1820 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1821
1822 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 1823 if (pci_is_pcie(ha->pdev))
5ffd3a52 1824 pcie_set_readrq(ha->pdev, 4096);
c3a2f0df 1825
737faece 1826 pci_disable_rom(ha->pdev);
c3a2f0df
AV		 1827
1828 ha->chip_revision = ha->pdev->revision;
1829
1830 return QLA_SUCCESS;
1831}
1832
1da177e4
LT		 1833/**
1834 * qla2x00_isp_firmware() - Choose firmware image.
1835 * @ha: HA context
1836 *
1837 * Returns 0 on success.
1838 */
1839static int
e315cd28 1840qla2x00_isp_firmware(scsi_qla_host_t *vha)
1da177e4
LT		 1841{
1842 int rval;
42e421b1
AV		 1843 uint16_t loop_id, topo, sw_cap;
1844 uint8_t domain, area, al_pa;
e315cd28 1845 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 1846
1847 /* Assume loading risc code */
fa2a1ce5 1848 rval = QLA_FUNCTION_FAILED;
1da177e4
LT		 1849
1850 if (ha->flags.disable_risc_code_load) {
7c3df132 1851 ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n");
1da177e4
LT		 1852
1853 /* Verify checksum of loaded RISC code. */
e315cd28 1854 rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address);
42e421b1
AV		 1855 if (rval == QLA_SUCCESS) {
1856 /* And, verify we are not in ROM code. */
e315cd28 1857 rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa,
42e421b1
AV		 1858 &area, &domain, &topo, &sw_cap);
1859 }
1da177e4
LT		 1860 }
1861
7c3df132
SK		 1862 if (rval)
1863 ql_dbg(ql_dbg_init, vha, 0x007a,
1864 "**** Load RISC code ****.\n");
1da177e4
LT		 1865
1866 return (rval);
1867}
1868
1869/**
1870 * qla2x00_reset_chip() - Reset ISP chip.
1871 * @ha: HA context
1872 *
1873 * Returns 0 on success.
1874 */
abbd8870 1875void
e315cd28 1876qla2x00_reset_chip(scsi_qla_host_t *vha)
1da177e4
LT		 1877{
1878 unsigned long flags = 0;
e315cd28 1879 struct qla_hw_data *ha = vha->hw;
3d71644c 1880 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 1881 uint32_t cnt;
1da177e4
LT		 1882 uint16_t cmd;
1883
85880801
AV		 1884 if (unlikely(pci_channel_offline(ha->pdev)))
1885 return;
1886
fd34f556 1887 ha->isp_ops->disable_intrs(ha);
1da177e4
LT		 1888
1889 spin_lock_irqsave(&ha->hardware_lock, flags);
1890
1891 /* Turn off master enable */
1892 cmd = 0;
1893 pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd);
1894 cmd &= ~PCI_COMMAND_MASTER;
1895 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
1896
1897 if (!IS_QLA2100(ha)) {
1898 /* Pause RISC. */
1899 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1900 if (IS_QLA2200(ha) || IS_QLA2300(ha)) {
1901 for (cnt = 0; cnt < 30000; cnt++) {
1902 if ((RD_REG_WORD(&reg->hccr) &
1903 HCCR_RISC_PAUSE) != 0)
1904 break;
1905 udelay(100);
1906 }
1907 } else {
1908 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1909 udelay(10);
1910 }
1911
1912 /* Select FPM registers. */
1913 WRT_REG_WORD(&reg->ctrl_status, 0x20);
1914 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1915
1916 /* FPM Soft Reset. */
1917 WRT_REG_WORD(&reg->fpm_diag_config, 0x100);
1918 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
1919
1920 /* Toggle Fpm Reset. */
1921 if (!IS_QLA2200(ha)) {
1922 WRT_REG_WORD(&reg->fpm_diag_config, 0x0);
1923 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
1924 }
1925
1926 /* Select frame buffer registers. */
1927 WRT_REG_WORD(&reg->ctrl_status, 0x10);
1928 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1929
1930 /* Reset frame buffer FIFOs. */
1931 if (IS_QLA2200(ha)) {
1932 WRT_FB_CMD_REG(ha, reg, 0xa000);
1933 RD_FB_CMD_REG(ha, reg); /* PCI Posting. */
1934 } else {
1935 WRT_FB_CMD_REG(ha, reg, 0x00fc);
1936
1937 /* Read back fb_cmd until zero or 3 seconds max */
1938 for (cnt = 0; cnt < 3000; cnt++) {
1939 if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0)
1940 break;
1941 udelay(100);
1942 }
1943 }
1944
1945 /* Select RISC module registers. */
1946 WRT_REG_WORD(&reg->ctrl_status, 0);
1947 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1948
1949 /* Reset RISC processor. */
1950 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
1951 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1952
1953 /* Release RISC processor. */
1954 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
1955 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1956 }
1957
1958 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
1959 WRT_REG_WORD(&reg->hccr, HCCR_CLR_HOST_INT);
1960
1961 /* Reset ISP chip. */
1962 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1963
1964 /* Wait for RISC to recover from reset. */
1965 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1966 /*
1967 * It is necessary to for a delay here since the card doesn't
1968 * respond to PCI reads during a reset. On some architectures
1969 * this will result in an MCA.
1970 */
1971 udelay(20);
1972 for (cnt = 30000; cnt; cnt--) {
1973 if ((RD_REG_WORD(&reg->ctrl_status) &
1974 CSR_ISP_SOFT_RESET) == 0)
1975 break;
1976 udelay(100);
1977 }
1978 } else
1979 udelay(10);
1980
1981 /* Reset RISC processor. */
1982 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
1983
1984 WRT_REG_WORD(&reg->semaphore, 0);
1985
1986 /* Release RISC processor. */
1987 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
1988 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1989
1990 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1991 for (cnt = 0; cnt < 30000; cnt++) {
ffb39f03 1992 if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY)
1da177e4 1993 break;
1da177e4
LT		 1994
1995 udelay(100);
1996 }
1997 } else
1998 udelay(100);
1999
2000 /* Turn on master enable */
2001 cmd |= PCI_COMMAND_MASTER;
2002 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
2003
2004 /* Disable RISC pause on FPM parity error. */
2005 if (!IS_QLA2100(ha)) {
2006 WRT_REG_WORD(&reg->hccr, HCCR_DISABLE_PARITY_PAUSE);
2007 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
2008 }
2009
2010 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2011}
2012
b1d46989
MI		 2013/**
2014 * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC.
2015 *
2016 * Returns 0 on success.
2017 */
fa492630 2018static int
b1d46989
MI		 2019qla81xx_reset_mpi(scsi_qla_host_t *vha)
2020{
2021 uint16_t mb[4] = {0x1010, 0, 1, 0};
2022
6246b8a1
GM		 2023 if (!IS_QLA81XX(vha->hw))
2024 return QLA_SUCCESS;
2025
b1d46989
MI		 2026 return qla81xx_write_mpi_register(vha, mb);
2027}
2028
0107109e 2029/**
88c26663 2030 * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC.
0107109e
AV		 2031 * @ha: HA context
2032 *
2033 * Returns 0 on success.
2034 */
d14e72fb 2035static inline int
e315cd28 2036qla24xx_reset_risc(scsi_qla_host_t *vha)
0107109e
AV		 2037{
2038 unsigned long flags = 0;
e315cd28 2039 struct qla_hw_data *ha = vha->hw;
0107109e 2040 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
52c82823 2041 uint32_t cnt;
335a1cc9 2042 uint16_t wd;
b1d46989 2043 static int abts_cnt; /* ISP abort retry counts */
d14e72fb 2044 int rval = QLA_SUCCESS;
0107109e 2045
0107109e
AV		 2046 spin_lock_irqsave(&ha->hardware_lock, flags);
2047
2048 /* Reset RISC. */
2049 WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
2050 for (cnt = 0; cnt < 30000; cnt++) {
2051 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
2052 break;
2053
2054 udelay(10);
2055 }
2056
d14e72fb
HM		 2057 if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE))
2058 set_bit(DMA_SHUTDOWN_CMPL, &ha->fw_dump_cap_flags);
2059
2060 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017e,
2061 "HCCR: 0x%x, Control Status %x, DMA active status:0x%x\n",
2062 RD_REG_DWORD(&reg->hccr),
2063 RD_REG_DWORD(&reg->ctrl_status),
2064 (RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE));
2065
0107109e
AV		 2066 WRT_REG_DWORD(&reg->ctrl_status,
2067 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
335a1cc9 2068 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
88c26663 2069
335a1cc9 2070 udelay(100);
d14e72fb 2071
88c26663 2072 /* Wait for firmware to complete NVRAM accesses. */
52c82823 2073 RD_REG_WORD(&reg->mailbox0);
d14e72fb
HM		 2074 for (cnt = 10000; RD_REG_WORD(&reg->mailbox0) != 0 &&
2075 rval == QLA_SUCCESS; cnt--) {
88c26663 2076 barrier();
d14e72fb
HM		 2077 if (cnt)
2078 udelay(5);
2079 else
2080 rval = QLA_FUNCTION_TIMEOUT;
88c26663
AV		 2081 }
2082
d14e72fb
HM		 2083 if (rval == QLA_SUCCESS)
2084 set_bit(ISP_MBX_RDY, &ha->fw_dump_cap_flags);
2085
2086 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017f,
2087 "HCCR: 0x%x, MailBox0 Status 0x%x\n",
2088 RD_REG_DWORD(&reg->hccr),
2089 RD_REG_DWORD(&reg->mailbox0));
2090
335a1cc9 2091 /* Wait for soft-reset to complete. */
52c82823 2092 RD_REG_DWORD(&reg->ctrl_status);
200ffb15 2093 for (cnt = 0; cnt < 60; cnt++) {
0107109e 2094 barrier();
d14e72fb
HM		 2095 if ((RD_REG_DWORD(&reg->ctrl_status) &
2096 CSRX_ISP_SOFT_RESET) == 0)
2097 break;
2098
2099 udelay(5);
0107109e 2100 }
d14e72fb
HM		 2101 if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_ISP_SOFT_RESET))
2102 set_bit(ISP_SOFT_RESET_CMPL, &ha->fw_dump_cap_flags);
2103
2104 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015d,
2105 "HCCR: 0x%x, Soft Reset status: 0x%x\n",
2106 RD_REG_DWORD(&reg->hccr),
2107 RD_REG_DWORD(&reg->ctrl_status));
0107109e 2108
b1d46989
MI		 2109 /* If required, do an MPI FW reset now */
2110 if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
2111 if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
2112 if (++abts_cnt < 5) {
2113 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2114 set_bit(MPI_RESET_NEEDED, &vha->dpc_flags);
2115 } else {
2116 /*
2117 * We exhausted the ISP abort retries. We have to
2118 * set the board offline.
2119 */
2120 abts_cnt = 0;
2121 vha->flags.online = 0;
2122 }
2123 }
2124 }
2125
0107109e
AV		 2126 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
2127 RD_REG_DWORD(&reg->hccr);
2128
2129 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
2130 RD_REG_DWORD(&reg->hccr);
2131
2132 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
2133 RD_REG_DWORD(&reg->hccr);
2134
52c82823 2135 RD_REG_WORD(&reg->mailbox0);
200ffb15 2136 for (cnt = 60; RD_REG_WORD(&reg->mailbox0) != 0 &&
d14e72fb 2137 rval == QLA_SUCCESS; cnt--) {
0107109e 2138 barrier();
d14e72fb
HM		 2139 if (cnt)
2140 udelay(5);
2141 else
2142 rval = QLA_FUNCTION_TIMEOUT;
0107109e 2143 }
d14e72fb
HM		 2144 if (rval == QLA_SUCCESS)
2145 set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags);
2146
2147 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015e,
2148 "Host Risc 0x%x, mailbox0 0x%x\n",
2149 RD_REG_DWORD(&reg->hccr),
2150 RD_REG_WORD(&reg->mailbox0));
0107109e
AV		 2151
2152 spin_unlock_irqrestore(&ha->hardware_lock, flags);
124f85e6 2153
d14e72fb
HM		 2154 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015f,
2155 "Driver in %s mode\n",
2156 IS_NOPOLLING_TYPE(ha) ? "Interrupt" : "Polling");
2157
124f85e6
AV		 2158 if (IS_NOPOLLING_TYPE(ha))
2159 ha->isp_ops->enable_intrs(ha);
d14e72fb
HM		 2160
2161 return rval;
0107109e
AV		 2162}
2163
4ea2c9c7
JC		 2164static void
2165qla25xx_read_risc_sema_reg(scsi_qla_host_t *vha, uint32_t *data)
2166{
2167 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
2168
2169 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
2170 *data = RD_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET);
2171
2172}
2173
2174static void
2175qla25xx_write_risc_sema_reg(scsi_qla_host_t *vha, uint32_t data)
2176{
2177 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
2178
2179 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
2180 WRT_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET, data);
2181}
2182
2183static void
2184qla25xx_manipulate_risc_semaphore(scsi_qla_host_t *vha)
2185{
4ea2c9c7
JC		 2186 uint32_t wd32 = 0;
2187 uint delta_msec = 100;
2188 uint elapsed_msec = 0;
2189 uint timeout_msec;
2190 ulong n;
2191
cc790764
JC		 2192 if (vha->hw->pdev->subsystem_device != 0x0175 &&
2193 vha->hw->pdev->subsystem_device != 0x0240)
4ea2c9c7
JC		 2194 return;
2195
8dd7e3a5
JC		 2196 WRT_REG_DWORD(&vha->hw->iobase->isp24.hccr, HCCRX_SET_RISC_PAUSE);
2197 udelay(100);
2198
4ea2c9c7
JC		 2199attempt:
2200 timeout_msec = TIMEOUT_SEMAPHORE;
2201 n = timeout_msec / delta_msec;
2202 while (n--) {
2203 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_SET);
2204 qla25xx_read_risc_sema_reg(vha, &wd32);
2205 if (wd32 & RISC_SEMAPHORE)
2206 break;
2207 msleep(delta_msec);
2208 elapsed_msec += delta_msec;
2209 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
2210 goto force;
2211 }
2212
2213 if (!(wd32 & RISC_SEMAPHORE))
2214 goto force;
2215
2216 if (!(wd32 & RISC_SEMAPHORE_FORCE))
2217 goto acquired;
2218
2219 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_CLR);
2220 timeout_msec = TIMEOUT_SEMAPHORE_FORCE;
2221 n = timeout_msec / delta_msec;
2222 while (n--) {
2223 qla25xx_read_risc_sema_reg(vha, &wd32);
2224 if (!(wd32 & RISC_SEMAPHORE_FORCE))
2225 break;
2226 msleep(delta_msec);
2227 elapsed_msec += delta_msec;
2228 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
2229 goto force;
2230 }
2231
2232 if (wd32 & RISC_SEMAPHORE_FORCE)
2233 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_CLR);
2234
2235 goto attempt;
2236
2237force:
2238 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_SET);
2239
2240acquired:
2241 return;
2242}
2243
88c26663
AV		 2244/**
2245 * qla24xx_reset_chip() - Reset ISP24xx chip.
2246 * @ha: HA context
2247 *
2248 * Returns 0 on success.
2249 */
2250void
e315cd28 2251qla24xx_reset_chip(scsi_qla_host_t *vha)
88c26663 2252{
e315cd28 2253 struct qla_hw_data *ha = vha->hw;
85880801
AV		 2254
2255 if (pci_channel_offline(ha->pdev) &&
2256 ha->flags.pci_channel_io_perm_failure) {
2257 return;
2258 }
2259
fd34f556 2260 ha->isp_ops->disable_intrs(ha);
88c26663 2261
4ea2c9c7
JC		 2262 qla25xx_manipulate_risc_semaphore(vha);
2263
88c26663 2264 /* Perform RISC reset. */
e315cd28 2265 qla24xx_reset_risc(vha);
88c26663
AV		 2266}
2267
1da177e4
LT		 2268/**
2269 * qla2x00_chip_diag() - Test chip for proper operation.
2270 * @ha: HA context
2271 *
2272 * Returns 0 on success.
2273 */
abbd8870 2274int
e315cd28 2275qla2x00_chip_diag(scsi_qla_host_t *vha)
1da177e4
LT		 2276{
2277 int rval;
e315cd28 2278 struct qla_hw_data *ha = vha->hw;
3d71644c 2279 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 2280 unsigned long flags = 0;
2281 uint16_t data;
2282 uint32_t cnt;
2283 uint16_t mb[5];
73208dfd 2284 struct req_que *req = ha->req_q_map[0];
1da177e4
LT		 2285
2286 /* Assume a failed state */
2287 rval = QLA_FUNCTION_FAILED;
2288
7c3df132
SK		 2289 ql_dbg(ql_dbg_init, vha, 0x007b,
2290 "Testing device at %lx.\n", (u_long)&reg->flash_address);
1da177e4
LT		 2291
2292 spin_lock_irqsave(&ha->hardware_lock, flags);
2293
2294 /* Reset ISP chip. */
2295 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
2296
2297 /*
2298 * We need to have a delay here since the card will not respond while
2299 * in reset causing an MCA on some architectures.
2300 */
2301 udelay(20);
2302 data = qla2x00_debounce_register(&reg->ctrl_status);
2303 for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {
2304 udelay(5);
2305 data = RD_REG_WORD(&reg->ctrl_status);
2306 barrier();
2307 }
2308
2309 if (!cnt)
2310 goto chip_diag_failed;
2311
7c3df132
SK		 2312 ql_dbg(ql_dbg_init, vha, 0x007c,
2313 "Reset register cleared by chip reset.\n");
1da177e4
LT		 2314
2315 /* Reset RISC processor. */
2316 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
2317 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
2318
2319 /* Workaround for QLA2312 PCI parity error */
2320 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
2321 data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0));
2322 for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) {
2323 udelay(5);
2324 data = RD_MAILBOX_REG(ha, reg, 0);
fa2a1ce5 2325 barrier();
1da177e4
LT		 2326 }
2327 } else
2328 udelay(10);
2329
2330 if (!cnt)
2331 goto chip_diag_failed;
2332
2333 /* Check product ID of chip */
7c3df132 2334 ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product Id of chip.\n");
1da177e4
LT		 2335
2336 mb[1] = RD_MAILBOX_REG(ha, reg, 1);
2337 mb[2] = RD_MAILBOX_REG(ha, reg, 2);
2338 mb[3] = RD_MAILBOX_REG(ha, reg, 3);
2339 mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4));
2340 if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) ||
2341 mb[3] != PROD_ID_3) {
7c3df132
SK		 2342 ql_log(ql_log_warn, vha, 0x0062,
2343 "Wrong product ID = 0x%x,0x%x,0x%x.\n",
2344 mb[1], mb[2], mb[3]);
1da177e4
LT		 2345
2346 goto chip_diag_failed;
2347 }
2348 ha->product_id[0] = mb[1];
2349 ha->product_id[1] = mb[2];
2350 ha->product_id[2] = mb[3];
2351 ha->product_id[3] = mb[4];
2352
2353 /* Adjust fw RISC transfer size */
73208dfd 2354 if (req->length > 1024)
1da177e4
LT		 2355 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024;
2356 else
2357 ha->fw_transfer_size = REQUEST_ENTRY_SIZE *
73208dfd 2358 req->length;
1da177e4
LT		 2359
2360 if (IS_QLA2200(ha) &&
2361 RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) {
2362 /* Limit firmware transfer size with a 2200A */
7c3df132 2363 ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n");
1da177e4 2364
ea5b6382 2365 ha->device_type |= DT_ISP2200A;
1da177e4
LT		 2366 ha->fw_transfer_size = 128;
2367 }
2368
2369 /* Wrap Incoming Mailboxes Test. */
2370 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2371
7c3df132 2372 ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n");
e315cd28 2373 rval = qla2x00_mbx_reg_test(vha);
7c3df132
SK		 2374 if (rval)
2375 ql_log(ql_log_warn, vha, 0x0080,
2376 "Failed mailbox send register test.\n");
2377 else
1da177e4
LT		 2378 /* Flag a successful rval */
2379 rval = QLA_SUCCESS;
1da177e4
LT		 2380 spin_lock_irqsave(&ha->hardware_lock, flags);
2381
2382chip_diag_failed:
2383 if (rval)
7c3df132
SK		 2384 ql_log(ql_log_info, vha, 0x0081,
2385 "Chip diagnostics **** FAILED ****.\n");
1da177e4
LT		 2386
2387 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2388
2389 return (rval);
2390}
2391
0107109e
AV		 2392/**
2393 * qla24xx_chip_diag() - Test ISP24xx for proper operation.
2394 * @ha: HA context
2395 *
2396 * Returns 0 on success.
2397 */
2398int
e315cd28 2399qla24xx_chip_diag(scsi_qla_host_t *vha)
0107109e
AV		 2400{
2401 int rval;
e315cd28 2402 struct qla_hw_data *ha = vha->hw;
73208dfd 2403 struct req_que *req = ha->req_q_map[0];
0107109e 2404
7ec0effd 2405 if (IS_P3P_TYPE(ha))
a9083016
GM		 2406 return QLA_SUCCESS;
2407
73208dfd 2408 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
0107109e 2409
e315cd28 2410 rval = qla2x00_mbx_reg_test(vha);
0107109e 2411 if (rval) {
7c3df132
SK		 2412 ql_log(ql_log_warn, vha, 0x0082,
2413 "Failed mailbox send register test.\n");
0107109e
AV		 2414 } else {
2415 /* Flag a successful rval */
2416 rval = QLA_SUCCESS;
2417 }
2418
2419 return rval;
2420}
2421
a7a167bf 2422void
e315cd28 2423qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
0107109e 2424{
a7a167bf
AV		 2425 int rval;
2426 uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
73208dfd 2427 eft_size, fce_size, mq_size;
df613b96
AV		 2428 dma_addr_t tc_dma;
2429 void *tc;
e315cd28 2430 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 2431 struct req_que *req = ha->req_q_map[0];
2432 struct rsp_que *rsp = ha->rsp_q_map[0];
a7a167bf
AV		 2433
2434 if (ha->fw_dump) {
7c3df132
SK		 2435 ql_dbg(ql_dbg_init, vha, 0x00bd,
2436 "Firmware dump already allocated.\n");
a7a167bf
AV		 2437 return;
2438 }
d4e3e04d 2439
0107109e 2440 ha->fw_dumped = 0;
61f098dd 2441 ha->fw_dump_cap_flags = 0;
f73cb695
CD		 2442 dump_size = fixed_size = mem_size = eft_size = fce_size = mq_size = 0;
2443 req_q_size = rsp_q_size = 0;
2444
2445 if (IS_QLA27XX(ha))
2446 goto try_fce;
2447
d4e3e04d 2448 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
a7a167bf 2449 fixed_size = sizeof(struct qla2100_fw_dump);
d4e3e04d 2450 } else if (IS_QLA23XX(ha)) {
a7a167bf
AV		 2451 fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
2452 mem_size = (ha->fw_memory_size - 0x11000 + 1) *
2453 sizeof(uint16_t);
e428924c 2454 } else if (IS_FWI2_CAPABLE(ha)) {
b20f02e1 2455 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
6246b8a1
GM		 2456 fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem);
2457 else if (IS_QLA81XX(ha))
3a03eb79
AV		 2458 fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
2459 else if (IS_QLA25XX(ha))
2460 fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
2461 else
2462 fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
f73cb695 2463
a7a167bf
AV		 2464 mem_size = (ha->fw_memory_size - 0x100000 + 1) *
2465 sizeof(uint32_t);
050c9bb1 2466 if (ha->mqenable) {
b20f02e1 2467 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
6246b8a1 2468 mq_size = sizeof(struct qla2xxx_mq_chain);
050c9bb1
GM		 2469 /*
2470 * Allocate maximum buffer size for all queues.
2471 * Resizing must be done at end-of-dump processing.
2472 */
2473 mq_size += ha->max_req_queues *
2474 (req->length * sizeof(request_t));
2475 mq_size += ha->max_rsp_queues *
2476 (rsp->length * sizeof(response_t));
2477 }
00876ae8 2478 if (ha->tgt.atio_ring)
2d70c103 2479 mq_size += ha->tgt.atio_q_length * sizeof(request_t);
df613b96 2480 /* Allocate memory for Fibre Channel Event Buffer. */
f73cb695
CD		 2481 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
2482 !IS_QLA27XX(ha))
436a7b11 2483 goto try_eft;
df613b96 2484
f73cb695
CD		 2485try_fce:
2486 if (ha->fce)
2487 dma_free_coherent(&ha->pdev->dev,
2488 FCE_SIZE, ha->fce, ha->fce_dma);
2489
2490 /* Allocate memory for Fibre Channel Event Buffer. */
0ea85b50
JP		 2491 tc = dma_zalloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
2492 GFP_KERNEL);
df613b96 2493 if (!tc) {
7c3df132
SK		 2494 ql_log(ql_log_warn, vha, 0x00be,
2495 "Unable to allocate (%d KB) for FCE.\n",
2496 FCE_SIZE / 1024);
17d98630 2497 goto try_eft;
df613b96
AV		 2498 }
2499
e315cd28 2500 rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS,
df613b96
AV		 2501 ha->fce_mb, &ha->fce_bufs);
2502 if (rval) {
7c3df132
SK		 2503 ql_log(ql_log_warn, vha, 0x00bf,
2504 "Unable to initialize FCE (%d).\n", rval);
df613b96
AV		 2505 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc,
2506 tc_dma);
2507 ha->flags.fce_enabled = 0;
17d98630 2508 goto try_eft;
df613b96 2509 }
cfb0919c 2510 ql_dbg(ql_dbg_init, vha, 0x00c0,
7c3df132 2511 "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024);
df613b96 2512
7d9dade3 2513 fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE;
df613b96
AV		 2514 ha->flags.fce_enabled = 1;
2515 ha->fce_dma = tc_dma;
2516 ha->fce = tc;
f73cb695 2517
436a7b11 2518try_eft:
f73cb695
CD		 2519 if (ha->eft)
2520 dma_free_coherent(&ha->pdev->dev,
2521 EFT_SIZE, ha->eft, ha->eft_dma);
2522
436a7b11 2523 /* Allocate memory for Extended Trace Buffer. */
0ea85b50
JP		 2524 tc = dma_zalloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
2525 GFP_KERNEL);
436a7b11 2526 if (!tc) {
7c3df132
SK		 2527 ql_log(ql_log_warn, vha, 0x00c1,
2528 "Unable to allocate (%d KB) for EFT.\n",
2529 EFT_SIZE / 1024);
436a7b11
AV		 2530 goto cont_alloc;
2531 }
2532
e315cd28 2533 rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
436a7b11 2534 if (rval) {
7c3df132
SK		 2535 ql_log(ql_log_warn, vha, 0x00c2,
2536 "Unable to initialize EFT (%d).\n", rval);
436a7b11
AV		 2537 dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc,
2538 tc_dma);
2539 goto cont_alloc;
2540 }
cfb0919c 2541 ql_dbg(ql_dbg_init, vha, 0x00c3,
7c3df132 2542 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
436a7b11
AV		 2543
2544 eft_size = EFT_SIZE;
2545 ha->eft_dma = tc_dma;
2546 ha->eft = tc;
d4e3e04d 2547 }
f73cb695 2548
a7a167bf 2549cont_alloc:
f73cb695
CD		 2550 if (IS_QLA27XX(ha)) {
2551 if (!ha->fw_dump_template) {
2552 ql_log(ql_log_warn, vha, 0x00ba,
2553 "Failed missing fwdump template\n");
2554 return;
2555 }
2556 dump_size = qla27xx_fwdt_calculate_dump_size(vha);
2557 ql_dbg(ql_dbg_init, vha, 0x00fa,
2558 "-> allocating fwdump (%x bytes)...\n", dump_size);
2559 goto allocate;
2560 }
2561
73208dfd
AC		 2562 req_q_size = req->length * sizeof(request_t);
2563 rsp_q_size = rsp->length * sizeof(response_t);
a7a167bf 2564 dump_size = offsetof(struct qla2xxx_fw_dump, isp);
2afa19a9 2565 dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size;
bb99de67
AV		 2566 ha->chain_offset = dump_size;
2567 dump_size += mq_size + fce_size;
d4e3e04d 2568
f73cb695 2569allocate:
d4e3e04d 2570 ha->fw_dump = vmalloc(dump_size);
a7a167bf 2571 if (!ha->fw_dump) {
7c3df132
SK		 2572 ql_log(ql_log_warn, vha, 0x00c4,
2573 "Unable to allocate (%d KB) for firmware dump.\n",
2574 dump_size / 1024);
a7a167bf 2575
e30d1756
MI		 2576 if (ha->fce) {
2577 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
2578 ha->fce_dma);
2579 ha->fce = NULL;
2580 ha->fce_dma = 0;
2581 }
2582
a7a167bf
AV		 2583 if (ha->eft) {
2584 dma_free_coherent(&ha->pdev->dev, eft_size, ha->eft,
2585 ha->eft_dma);
2586 ha->eft = NULL;
2587 ha->eft_dma = 0;
2588 }
2589 return;
2590 }
f73cb695 2591 ha->fw_dump_len = dump_size;
cfb0919c 2592 ql_dbg(ql_dbg_init, vha, 0x00c5,
7c3df132 2593 "Allocated (%d KB) for firmware dump.\n", dump_size / 1024);
a7a167bf 2594
f73cb695
CD		 2595 if (IS_QLA27XX(ha))
2596 return;
2597
a7a167bf
AV		 2598 ha->fw_dump->signature[0] = 'Q';
2599 ha->fw_dump->signature[1] = 'L';
2600 ha->fw_dump->signature[2] = 'G';
2601 ha->fw_dump->signature[3] = 'C';
ad950360 2602 ha->fw_dump->version = htonl(1);
a7a167bf
AV		 2603
2604 ha->fw_dump->fixed_size = htonl(fixed_size);
2605 ha->fw_dump->mem_size = htonl(mem_size);
2606 ha->fw_dump->req_q_size = htonl(req_q_size);
2607 ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
2608
2609 ha->fw_dump->eft_size = htonl(eft_size);
2610 ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma));
2611 ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma));
2612
2613 ha->fw_dump->header_size =
2614 htonl(offsetof(struct qla2xxx_fw_dump, isp));
0107109e
AV		 2615}
2616
18e7555a
AV		 2617static int
2618qla81xx_mpi_sync(scsi_qla_host_t *vha)
2619{
2620#define MPS_MASK 0xe0
2621 int rval;
2622 uint16_t dc;
2623 uint32_t dw;
18e7555a
AV		 2624
2625 if (!IS_QLA81XX(vha->hw))
2626 return QLA_SUCCESS;
2627
2628 rval = qla2x00_write_ram_word(vha, 0x7c00, 1);
2629 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2630 ql_log(ql_log_warn, vha, 0x0105,
2631 "Unable to acquire semaphore.\n");
18e7555a
AV		 2632 goto done;
2633 }
2634
2635 pci_read_config_word(vha->hw->pdev, 0x54, &dc);
2636 rval = qla2x00_read_ram_word(vha, 0x7a15, &dw);
2637 if (rval != QLA_SUCCESS) {
7c3df132 2638 ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n");
18e7555a
AV		 2639 goto done_release;
2640 }
2641
2642 dc &= MPS_MASK;
2643 if (dc == (dw & MPS_MASK))
2644 goto done_release;
2645
2646 dw &= ~MPS_MASK;
2647 dw |= dc;
2648 rval = qla2x00_write_ram_word(vha, 0x7a15, dw);
2649 if (rval != QLA_SUCCESS) {
7c3df132 2650 ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n");
18e7555a
AV		 2651 }
2652
2653done_release:
2654 rval = qla2x00_write_ram_word(vha, 0x7c00, 0);
2655 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2656 ql_log(ql_log_warn, vha, 0x006d,
2657 "Unable to release semaphore.\n");
18e7555a
AV		 2658 }
2659
2660done:
2661 return rval;
2662}
2663
8d93f550
CD		 2664int
2665qla2x00_alloc_outstanding_cmds(struct qla_hw_data *ha, struct req_que *req)
2666{
2667 /* Don't try to reallocate the array */
2668 if (req->outstanding_cmds)
2669 return QLA_SUCCESS;
2670
d7459527 2671 if (!IS_FWI2_CAPABLE(ha))
8d93f550
CD		 2672 req->num_outstanding_cmds = DEFAULT_OUTSTANDING_COMMANDS;
2673 else {
03e8c680
QT		 2674 if (ha->cur_fw_xcb_count <= ha->cur_fw_iocb_count)
2675 req->num_outstanding_cmds = ha->cur_fw_xcb_count;
8d93f550 2676 else
03e8c680 2677 req->num_outstanding_cmds = ha->cur_fw_iocb_count;
8d93f550
CD		 2678 }
2679
2680 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
2681 req->num_outstanding_cmds, GFP_KERNEL);
2682
2683 if (!req->outstanding_cmds) {
2684 /*
2685 * Try to allocate a minimal size just so we can get through
2686 * initialization.
2687 */
2688 req->num_outstanding_cmds = MIN_OUTSTANDING_COMMANDS;
2689 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
2690 req->num_outstanding_cmds, GFP_KERNEL);
2691
2692 if (!req->outstanding_cmds) {
2693 ql_log(ql_log_fatal, NULL, 0x0126,
2694 "Failed to allocate memory for "
2695 "outstanding_cmds for req_que %p.\n", req);
2696 req->num_outstanding_cmds = 0;
2697 return QLA_FUNCTION_FAILED;
2698 }
2699 }
2700
2701 return QLA_SUCCESS;
2702}
2703
1da177e4
LT		 2704/**
2705 * qla2x00_setup_chip() - Load and start RISC firmware.
2706 * @ha: HA context
2707 *
2708 * Returns 0 on success.
2709 */
2710static int
e315cd28 2711qla2x00_setup_chip(scsi_qla_host_t *vha)
1da177e4 2712{
0107109e
AV		 2713 int rval;
2714 uint32_t srisc_address = 0;
e315cd28 2715 struct qla_hw_data *ha = vha->hw;
3db0652e
AV		 2716 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2717 unsigned long flags;
dda772e8 2718 uint16_t fw_major_version;
3db0652e 2719
7ec0effd 2720 if (IS_P3P_TYPE(ha)) {
a9083016 2721 rval = ha->isp_ops->load_risc(vha, &srisc_address);
14e303d9
AV		 2722 if (rval == QLA_SUCCESS) {
2723 qla2x00_stop_firmware(vha);
a9083016 2724 goto enable_82xx_npiv;
14e303d9 2725 } else
b963752f 2726 goto failed;
a9083016
GM		 2727 }
2728
3db0652e
AV		 2729 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
2730 /* Disable SRAM, Instruction RAM and GP RAM parity. */
2731 spin_lock_irqsave(&ha->hardware_lock, flags);
2732 WRT_REG_WORD(&reg->hccr, (HCCR_ENABLE_PARITY + 0x0));
2733 RD_REG_WORD(&reg->hccr);
2734 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2735 }
1da177e4 2736
18e7555a
AV		 2737 qla81xx_mpi_sync(vha);
2738
1da177e4 2739 /* Load firmware sequences */
e315cd28 2740 rval = ha->isp_ops->load_risc(vha, &srisc_address);
0107109e 2741 if (rval == QLA_SUCCESS) {
7c3df132
SK		 2742 ql_dbg(ql_dbg_init, vha, 0x00c9,
2743 "Verifying Checksum of loaded RISC code.\n");
1da177e4 2744
e315cd28 2745 rval = qla2x00_verify_checksum(vha, srisc_address);
1da177e4
LT		 2746 if (rval == QLA_SUCCESS) {
2747 /* Start firmware execution. */
7c3df132
SK		 2748 ql_dbg(ql_dbg_init, vha, 0x00ca,
2749 "Starting firmware.\n");
1da177e4 2750
b0d6cabd
HM		 2751 if (ql2xexlogins)
2752 ha->flags.exlogins_enabled = 1;
2753
2f56a7f1
HM		 2754 if (ql2xexchoffld)
2755 ha->flags.exchoffld_enabled = 1;
2756
e315cd28 2757 rval = qla2x00_execute_fw(vha, srisc_address);
1da177e4 2758 /* Retrieve firmware information. */
dda772e8 2759 if (rval == QLA_SUCCESS) {
b0d6cabd
HM		 2760 rval = qla2x00_set_exlogins_buffer(vha);
2761 if (rval != QLA_SUCCESS)
2762 goto failed;
2763
2f56a7f1
HM		 2764 rval = qla2x00_set_exchoffld_buffer(vha);
2765 if (rval != QLA_SUCCESS)
2766 goto failed;
2767
a9083016 2768enable_82xx_npiv:
dda772e8 2769 fw_major_version = ha->fw_major_version;
7ec0effd 2770 if (IS_P3P_TYPE(ha))
3173167f 2771 qla82xx_check_md_needed(vha);
6246b8a1
GM		 2772 else
2773 rval = qla2x00_get_fw_version(vha);
ca9e9c3e
AV		 2774 if (rval != QLA_SUCCESS)
2775 goto failed;
2c3dfe3f 2776 ha->flags.npiv_supported = 0;
e315cd28 2777 if (IS_QLA2XXX_MIDTYPE(ha) &&
946fb891 2778 (ha->fw_attributes & BIT_2)) {
2c3dfe3f 2779 ha->flags.npiv_supported = 1;
4d0ea247
SJ		 2780 if ((!ha->max_npiv_vports) ||
2781 ((ha->max_npiv_vports + 1) %
eb66dc60 2782 MIN_MULTI_ID_FABRIC))
4d0ea247 2783 ha->max_npiv_vports =
eb66dc60 2784 MIN_MULTI_ID_FABRIC - 1;
4d0ea247 2785 }
03e8c680 2786 qla2x00_get_resource_cnts(vha);
d743de66 2787
8d93f550
CD		 2788 /*
2789 * Allocate the array of outstanding commands
2790 * now that we know the firmware resources.
2791 */
2792 rval = qla2x00_alloc_outstanding_cmds(ha,
2793 vha->req);
2794 if (rval != QLA_SUCCESS)
2795 goto failed;
2796
be5ea3cf 2797 if (!fw_major_version && ql2xallocfwdump
7ec0effd 2798 && !(IS_P3P_TYPE(ha)))
08de2844 2799 qla2x00_alloc_fw_dump(vha);
3b6e5b9d
CD		 2800 } else {
2801 goto failed;
1da177e4
LT		 2802 }
2803 } else {
7c3df132
SK		 2804 ql_log(ql_log_fatal, vha, 0x00cd,
2805 "ISP Firmware failed checksum.\n");
2806 goto failed;
1da177e4 2807 }
c74d88a4
AV		 2808 } else
2809 goto failed;
1da177e4 2810
3db0652e
AV		 2811 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
2812 /* Enable proper parity. */
2813 spin_lock_irqsave(&ha->hardware_lock, flags);
2814 if (IS_QLA2300(ha))
2815 /* SRAM parity */
2816 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x1);
2817 else
2818 /* SRAM, Instruction RAM and GP RAM parity */
2819 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x7);
2820 RD_REG_WORD(&reg->hccr);
2821 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2822 }
2823
f3982d89
CD		 2824 if (IS_QLA27XX(ha))
2825 ha->flags.fac_supported = 1;
2826 else if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
1d2874de
JC		 2827 uint32_t size;
2828
2829 rval = qla81xx_fac_get_sector_size(vha, &size);
2830 if (rval == QLA_SUCCESS) {
2831 ha->flags.fac_supported = 1;
2832 ha->fdt_block_size = size << 2;
2833 } else {
7c3df132 2834 ql_log(ql_log_warn, vha, 0x00ce,
1d2874de
JC		 2835 "Unsupported FAC firmware (%d.%02d.%02d).\n",
2836 ha->fw_major_version, ha->fw_minor_version,
2837 ha->fw_subminor_version);
1ca60e3b 2838
f73cb695 2839 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
6246b8a1
GM		 2840 ha->flags.fac_supported = 0;
2841 rval = QLA_SUCCESS;
2842 }
1d2874de
JC		 2843 }
2844 }
ca9e9c3e 2845failed:
1da177e4 2846 if (rval) {
7c3df132
SK		 2847 ql_log(ql_log_fatal, vha, 0x00cf,
2848 "Setup chip ****FAILED****.\n");
1da177e4
LT		 2849 }
2850
2851 return (rval);
2852}
2853
2854/**
2855 * qla2x00_init_response_q_entries() - Initializes response queue entries.
2856 * @ha: HA context
2857 *
2858 * Beginning of request ring has initialization control block already built
2859 * by nvram config routine.
2860 *
2861 * Returns 0 on success.
2862 */
73208dfd
AC		 2863void
2864qla2x00_init_response_q_entries(struct rsp_que *rsp)
1da177e4
LT		 2865{
2866 uint16_t cnt;
2867 response_t *pkt;
2868
2afa19a9
AC		 2869 rsp->ring_ptr = rsp->ring;
2870 rsp->ring_index = 0;
2871 rsp->status_srb = NULL;
e315cd28
AC		 2872 pkt = rsp->ring_ptr;
2873 for (cnt = 0; cnt < rsp->length; cnt++) {
1da177e4
LT		 2874 pkt->signature = RESPONSE_PROCESSED;
2875 pkt++;
2876 }
1da177e4
LT		 2877}
2878
2879/**
2880 * qla2x00_update_fw_options() - Read and process firmware options.
2881 * @ha: HA context
2882 *
2883 * Returns 0 on success.
2884 */
abbd8870 2885void
e315cd28 2886qla2x00_update_fw_options(scsi_qla_host_t *vha)
1da177e4
LT		 2887{
2888 uint16_t swing, emphasis, tx_sens, rx_sens;
e315cd28 2889 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2890
2891 memset(ha->fw_options, 0, sizeof(ha->fw_options));
e315cd28 2892 qla2x00_get_fw_options(vha, ha->fw_options);
1da177e4
LT		 2893
2894 if (IS_QLA2100(ha) || IS_QLA2200(ha))
2895 return;
2896
2897 /* Serial Link options. */
7c3df132
SK		 2898 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
2899 "Serial link options.\n");
2900 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
2901 (uint8_t *)&ha->fw_seriallink_options,
2902 sizeof(ha->fw_seriallink_options));
1da177e4
LT		 2903
2904 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
2905 if (ha->fw_seriallink_options[3] & BIT_2) {
2906 ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING;
2907
2908 /* 1G settings */
2909 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
2910 emphasis = (ha->fw_seriallink_options[2] &
2911 (BIT_4 | BIT_3)) >> 3;
2912 tx_sens = ha->fw_seriallink_options[0] &
fa2a1ce5 2913 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 2914 rx_sens = (ha->fw_seriallink_options[0] &
2915 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
2916 ha->fw_options[10] = (emphasis << 14) | (swing << 8);
2917 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
2918 if (rx_sens == 0x0)
2919 rx_sens = 0x3;
2920 ha->fw_options[10] |= (tx_sens << 4) | rx_sens;
2921 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
2922 ha->fw_options[10] |= BIT_5 |
2923 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
2924 (tx_sens & (BIT_1 | BIT_0));
2925
2926 /* 2G settings */
2927 swing = (ha->fw_seriallink_options[2] &
2928 (BIT_7 | BIT_6 | BIT_5)) >> 5;
2929 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
2930 tx_sens = ha->fw_seriallink_options[1] &
fa2a1ce5 2931 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 2932 rx_sens = (ha->fw_seriallink_options[1] &
2933 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
2934 ha->fw_options[11] = (emphasis << 14) | (swing << 8);
2935 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
2936 if (rx_sens == 0x0)
2937 rx_sens = 0x3;
2938 ha->fw_options[11] |= (tx_sens << 4) | rx_sens;
2939 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
2940 ha->fw_options[11] |= BIT_5 |
2941 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
2942 (tx_sens & (BIT_1 | BIT_0));
2943 }
2944
2945 /* FCP2 options. */
2946 /* Return command IOCBs without waiting for an ABTS to complete. */
2947 ha->fw_options[3] |= BIT_13;
2948
2949 /* LED scheme. */
2950 if (ha->flags.enable_led_scheme)
2951 ha->fw_options[2] |= BIT_12;
2952
48c02fde
AV		 2953 /* Detect ISP6312. */
2954 if (IS_QLA6312(ha))
2955 ha->fw_options[2] |= BIT_13;
2956
088d09d4
GM		 2957 /* Set Retry FLOGI in case of P2P connection */
2958 if (ha->operating_mode == P2P) {
2959 ha->fw_options[2] |= BIT_3;
2960 ql_dbg(ql_dbg_disc, vha, 0x2100,
2961 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
2962 __func__, ha->fw_options[2]);
2963 }
2964
1da177e4 2965 /* Update firmware options. */
e315cd28 2966 qla2x00_set_fw_options(vha, ha->fw_options);
1da177e4
LT		 2967}
2968
0107109e 2969void
e315cd28 2970qla24xx_update_fw_options(scsi_qla_host_t *vha)
0107109e
AV		 2971{
2972 int rval;
e315cd28 2973 struct qla_hw_data *ha = vha->hw;
0107109e 2974
7ec0effd 2975 if (IS_P3P_TYPE(ha))
a9083016
GM		 2976 return;
2977
f198cafa
HM		 2978 /* Hold status IOCBs until ABTS response received. */
2979 if (ql2xfwholdabts)
2980 ha->fw_options[3] |= BIT_12;
2981
088d09d4
GM		 2982 /* Set Retry FLOGI in case of P2P connection */
2983 if (ha->operating_mode == P2P) {
2984 ha->fw_options[2] |= BIT_3;
2985 ql_dbg(ql_dbg_disc, vha, 0x2101,
2986 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
2987 __func__, ha->fw_options[2]);
2988 }
2989
41dc529a
QT		 2990 /* Move PUREX, ABTS RX & RIDA to ATIOQ */
2991 if (ql2xmvasynctoatio) {
2992 if (qla_tgt_mode_enabled(vha) ||
2993 qla_dual_mode_enabled(vha))
2994 ha->fw_options[2] |= BIT_11;
2995 else
2996 ha->fw_options[2] &= ~BIT_11;
2997 }
2998
2999 ql_dbg(ql_dbg_init, vha, 0xffff,
3000 "%s, add FW options 1-3 = 0x%04x 0x%04x 0x%04x mode %x\n",
3001 __func__, ha->fw_options[1], ha->fw_options[2],
3002 ha->fw_options[3], vha->host->active_mode);
3003 qla2x00_set_fw_options(vha, ha->fw_options);
3004
0107109e 3005 /* Update Serial Link options. */
f94097ed 3006 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0)
0107109e
AV		 3007 return;
3008
e315cd28 3009 rval = qla2x00_set_serdes_params(vha,
f94097ed
AV		 3010 le16_to_cpu(ha->fw_seriallink_options24[1]),
3011 le16_to_cpu(ha->fw_seriallink_options24[2]),
3012 le16_to_cpu(ha->fw_seriallink_options24[3]));
0107109e 3013 if (rval != QLA_SUCCESS) {
7c3df132 3014 ql_log(ql_log_warn, vha, 0x0104,
0107109e
AV		 3015 "Unable to update Serial Link options (%x).\n", rval);
3016 }
3017}
3018
abbd8870 3019void
e315cd28 3020qla2x00_config_rings(struct scsi_qla_host *vha)
abbd8870 3021{
e315cd28 3022 struct qla_hw_data *ha = vha->hw;
3d71644c 3023 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
73208dfd
AC		 3024 struct req_que *req = ha->req_q_map[0];
3025 struct rsp_que *rsp = ha->rsp_q_map[0];
abbd8870
AV		 3026
3027 /* Setup ring parameters in initialization control block. */
ad950360
BVA		 3028 ha->init_cb->request_q_outpointer = cpu_to_le16(0);
3029 ha->init_cb->response_q_inpointer = cpu_to_le16(0);
e315cd28
AC		 3030 ha->init_cb->request_q_length = cpu_to_le16(req->length);
3031 ha->init_cb->response_q_length = cpu_to_le16(rsp->length);
3032 ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
3033 ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
3034 ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
3035 ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
abbd8870
AV		 3036
3037 WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0);
3038 WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0);
3039 WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0);
3040 WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0);
3041 RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */
3042}
3043
0107109e 3044void
e315cd28 3045qla24xx_config_rings(struct scsi_qla_host *vha)
0107109e 3046{
e315cd28 3047 struct qla_hw_data *ha = vha->hw;
118e2ef9 3048 device_reg_t *reg = ISP_QUE_REG(ha, 0);
73208dfd
AC		 3049 struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
3050 struct qla_msix_entry *msix;
0107109e 3051 struct init_cb_24xx *icb;
73208dfd
AC		 3052 uint16_t rid = 0;
3053 struct req_que *req = ha->req_q_map[0];
3054 struct rsp_que *rsp = ha->rsp_q_map[0];
0107109e 3055
6246b8a1 3056 /* Setup ring parameters in initialization control block. */
0107109e 3057 icb = (struct init_cb_24xx *)ha->init_cb;
ad950360
BVA		 3058 icb->request_q_outpointer = cpu_to_le16(0);
3059 icb->response_q_inpointer = cpu_to_le16(0);
e315cd28
AC		 3060 icb->request_q_length = cpu_to_le16(req->length);
3061 icb->response_q_length = cpu_to_le16(rsp->length);
3062 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
3063 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
3064 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
3065 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
0107109e 3066
2d70c103 3067 /* Setup ATIO queue dma pointers for target mode */
ad950360 3068 icb->atio_q_inpointer = cpu_to_le16(0);
2d70c103
NB		 3069 icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length);
3070 icb->atio_q_address[0] = cpu_to_le32(LSD(ha->tgt.atio_dma));
3071 icb->atio_q_address[1] = cpu_to_le32(MSD(ha->tgt.atio_dma));
3072
7c6300e3 3073 if (IS_SHADOW_REG_CAPABLE(ha))
ad950360 3074 icb->firmware_options_2 |= cpu_to_le32(BIT_30|BIT_29);
7c6300e3 3075
f73cb695 3076 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
ad950360
BVA		 3077 icb->qos = cpu_to_le16(QLA_DEFAULT_QUE_QOS);
3078 icb->rid = cpu_to_le16(rid);
73208dfd
AC		 3079 if (ha->flags.msix_enabled) {
3080 msix = &ha->msix_entries[1];
7c3df132
SK		 3081 ql_dbg(ql_dbg_init, vha, 0x00fd,
3082 "Registering vector 0x%x for base que.\n",
3083 msix->entry);
73208dfd
AC		 3084 icb->msix = cpu_to_le16(msix->entry);
3085 }
3086 /* Use alternate PCI bus number */
3087 if (MSB(rid))
ad950360 3088 icb->firmware_options_2 |= cpu_to_le32(BIT_19);
73208dfd
AC		 3089 /* Use alternate PCI devfn */
3090 if (LSB(rid))
ad950360 3091 icb->firmware_options_2 |= cpu_to_le32(BIT_18);
73208dfd 3092
3155754a 3093 /* Use Disable MSIX Handshake mode for capable adapters */
6246b8a1
GM		 3094 if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) &&
3095 (ha->flags.msix_enabled)) {
ad950360 3096 icb->firmware_options_2 &= cpu_to_le32(~BIT_22);
3155754a 3097 ha->flags.disable_msix_handshake = 1;
7c3df132
SK		 3098 ql_dbg(ql_dbg_init, vha, 0x00fe,
3099 "MSIX Handshake Disable Mode turned on.\n");
3155754a 3100 } else {
ad950360 3101 icb->firmware_options_2 |= cpu_to_le32(BIT_22);
3155754a 3102 }
ad950360 3103 icb->firmware_options_2 |= cpu_to_le32(BIT_23);
73208dfd
AC		 3104
3105 WRT_REG_DWORD(&reg->isp25mq.req_q_in, 0);
3106 WRT_REG_DWORD(&reg->isp25mq.req_q_out, 0);
3107 WRT_REG_DWORD(&reg->isp25mq.rsp_q_in, 0);
3108 WRT_REG_DWORD(&reg->isp25mq.rsp_q_out, 0);
3109 } else {
3110 WRT_REG_DWORD(&reg->isp24.req_q_in, 0);
3111 WRT_REG_DWORD(&reg->isp24.req_q_out, 0);
3112 WRT_REG_DWORD(&reg->isp24.rsp_q_in, 0);
3113 WRT_REG_DWORD(&reg->isp24.rsp_q_out, 0);
3114 }
aa230bc5 3115 qlt_24xx_config_rings(vha);
2d70c103 3116
73208dfd
AC		 3117 /* PCI posting */
3118 RD_REG_DWORD(&ioreg->hccr);
0107109e
AV		 3119}
3120
1da177e4
LT		 3121/**
3122 * qla2x00_init_rings() - Initializes firmware.
3123 * @ha: HA context
3124 *
3125 * Beginning of request ring has initialization control block already built
3126 * by nvram config routine.
3127 *
3128 * Returns 0 on success.
3129 */
8ae6d9c7 3130int
e315cd28 3131qla2x00_init_rings(scsi_qla_host_t *vha)
1da177e4
LT		 3132{
3133 int rval;
3134 unsigned long flags = 0;
29bdccbe 3135 int cnt, que;
e315cd28 3136 struct qla_hw_data *ha = vha->hw;
29bdccbe
AC		 3137 struct req_que *req;
3138 struct rsp_que *rsp;
2c3dfe3f
SJ		 3139 struct mid_init_cb_24xx *mid_init_cb =
3140 (struct mid_init_cb_24xx *) ha->init_cb;
1da177e4
LT		 3141
3142 spin_lock_irqsave(&ha->hardware_lock, flags);
3143
3144 /* Clear outstanding commands array. */
2afa19a9 3145 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 3146 req = ha->req_q_map[que];
cb43285f 3147 if (!req || !test_bit(que, ha->req_qid_map))
29bdccbe 3148 continue;
7c6300e3
JC		 3149 req->out_ptr = (void *)(req->ring + req->length);
3150 *req->out_ptr = 0;
8d93f550 3151 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++)
29bdccbe 3152 req->outstanding_cmds[cnt] = NULL;
1da177e4 3153
2afa19a9 3154 req->current_outstanding_cmd = 1;
1da177e4 3155
29bdccbe
AC		 3156 /* Initialize firmware. */
3157 req->ring_ptr = req->ring;
3158 req->ring_index = 0;
3159 req->cnt = req->length;
3160 }
1da177e4 3161
2afa19a9 3162 for (que = 0; que < ha->max_rsp_queues; que++) {
29bdccbe 3163 rsp = ha->rsp_q_map[que];
cb43285f 3164 if (!rsp || !test_bit(que, ha->rsp_qid_map))
29bdccbe 3165 continue;
7c6300e3
JC		 3166 rsp->in_ptr = (void *)(rsp->ring + rsp->length);
3167 *rsp->in_ptr = 0;
29bdccbe 3168 /* Initialize response queue entries */
8ae6d9c7
GM		 3169 if (IS_QLAFX00(ha))
3170 qlafx00_init_response_q_entries(rsp);
3171 else
3172 qla2x00_init_response_q_entries(rsp);
29bdccbe 3173 }
1da177e4 3174
2d70c103
NB		 3175 ha->tgt.atio_ring_ptr = ha->tgt.atio_ring;
3176 ha->tgt.atio_ring_index = 0;
3177 /* Initialize ATIO queue entries */
3178 qlt_init_atio_q_entries(vha);
3179
e315cd28 3180 ha->isp_ops->config_rings(vha);
1da177e4
LT		 3181
3182 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3183
8ae6d9c7
GM		 3184 ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n");
3185
3186 if (IS_QLAFX00(ha)) {
3187 rval = qlafx00_init_firmware(vha, ha->init_cb_size);
3188 goto next_check;
3189 }
3190
1da177e4 3191 /* Update any ISP specific firmware options before initialization. */
e315cd28 3192 ha->isp_ops->update_fw_options(vha);
1da177e4 3193
605aa2bc 3194 if (ha->flags.npiv_supported) {
45980cc2 3195 if (ha->operating_mode == LOOP && !IS_CNA_CAPABLE(ha))
605aa2bc 3196 ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
c48339de 3197 mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
605aa2bc
LC		 3198 }
3199
24a08138 3200 if (IS_FWI2_CAPABLE(ha)) {
ad950360 3201 mid_init_cb->options = cpu_to_le16(BIT_1);
24a08138 3202 mid_init_cb->init_cb.execution_throttle =
03e8c680 3203 cpu_to_le16(ha->cur_fw_xcb_count);
40f3862b
JC		 3204 ha->flags.dport_enabled =
3205 (mid_init_cb->init_cb.firmware_options_1 & BIT_7) != 0;
3206 ql_dbg(ql_dbg_init, vha, 0x0191, "DPORT Support: %s.\n",
3207 (ha->flags.dport_enabled) ? "enabled" : "disabled");
3208 /* FA-WWPN Status */
2486c627 3209 ha->flags.fawwpn_enabled =
40f3862b 3210 (mid_init_cb->init_cb.firmware_options_1 & BIT_6) != 0;
2486c627
HM		 3211 ql_dbg(ql_dbg_init, vha, 0x0141, "FA-WWPN Support: %s.\n",
3212 (ha->flags.fawwpn_enabled) ? "enabled" : "disabled");
24a08138 3213 }
2c3dfe3f 3214
e315cd28 3215 rval = qla2x00_init_firmware(vha, ha->init_cb_size);
8ae6d9c7 3216next_check:
1da177e4 3217 if (rval) {
7c3df132
SK		 3218 ql_log(ql_log_fatal, vha, 0x00d2,
3219 "Init Firmware **** FAILED ****.\n");
1da177e4 3220 } else {
7c3df132
SK		 3221 ql_dbg(ql_dbg_init, vha, 0x00d3,
3222 "Init Firmware -- success.\n");
1da177e4
LT		 3223 }
3224
3225 return (rval);
3226}
3227
3228/**
3229 * qla2x00_fw_ready() - Waits for firmware ready.
3230 * @ha: HA context
3231 *
3232 * Returns 0 on success.
3233 */
3234static int
e315cd28 3235qla2x00_fw_ready(scsi_qla_host_t *vha)
1da177e4
LT		 3236{
3237 int rval;
4d4df193 3238 unsigned long wtime, mtime, cs84xx_time;
1da177e4
LT		 3239 uint16_t min_wait; /* Minimum wait time if loop is down */
3240 uint16_t wait_time; /* Wait time if loop is coming ready */
b5a340dd 3241 uint16_t state[6];
e315cd28 3242 struct qla_hw_data *ha = vha->hw;
1da177e4 3243
8ae6d9c7
GM		 3244 if (IS_QLAFX00(vha->hw))
3245 return qlafx00_fw_ready(vha);
3246
1da177e4
LT		 3247 rval = QLA_SUCCESS;
3248
33461491
CD		 3249 /* Time to wait for loop down */
3250 if (IS_P3P_TYPE(ha))
3251 min_wait = 30;
3252 else
3253 min_wait = 20;
1da177e4
LT		 3254
3255 /*
3256 * Firmware should take at most one RATOV to login, plus 5 seconds for
3257 * our own processing.
3258 */
3259 if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) {
3260 wait_time = min_wait;
3261 }
3262
3263 /* Min wait time if loop down */
3264 mtime = jiffies + (min_wait * HZ);
3265
3266 /* wait time before firmware ready */
3267 wtime = jiffies + (wait_time * HZ);
3268
3269 /* Wait for ISP to finish LIP */
e315cd28 3270 if (!vha->flags.init_done)
7c3df132
SK		 3271 ql_log(ql_log_info, vha, 0x801e,
3272 "Waiting for LIP to complete.\n");
1da177e4
LT		 3273
3274 do {
5b939038 3275 memset(state, -1, sizeof(state));
e315cd28 3276 rval = qla2x00_get_firmware_state(vha, state);
1da177e4 3277 if (rval == QLA_SUCCESS) {
4d4df193 3278 if (state[0] < FSTATE_LOSS_OF_SYNC) {
e315cd28 3279 vha->device_flags &= ~DFLG_NO_CABLE;
1da177e4 3280 }
4d4df193 3281 if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) {
7c3df132
SK		 3282 ql_dbg(ql_dbg_taskm, vha, 0x801f,
3283 "fw_state=%x 84xx=%x.\n", state[0],
3284 state[2]);
4d4df193
HK		 3285 if ((state[2] & FSTATE_LOGGED_IN) &&
3286 (state[2] & FSTATE_WAITING_FOR_VERIFY)) {
7c3df132
SK		 3287 ql_dbg(ql_dbg_taskm, vha, 0x8028,
3288 "Sending verify iocb.\n");
4d4df193
HK		 3289
3290 cs84xx_time = jiffies;
e315cd28 3291 rval = qla84xx_init_chip(vha);
7c3df132
SK		 3292 if (rval != QLA_SUCCESS) {
3293 ql_log(ql_log_warn,
cfb0919c 3294 vha, 0x8007,
7c3df132 3295 "Init chip failed.\n");
4d4df193 3296 break;
7c3df132 3297 }
4d4df193
HK		 3298
3299 /* Add time taken to initialize. */
3300 cs84xx_time = jiffies - cs84xx_time;
3301 wtime += cs84xx_time;
3302 mtime += cs84xx_time;
cfb0919c 3303 ql_dbg(ql_dbg_taskm, vha, 0x8008,
7c3df132
SK		 3304 "Increasing wait time by %ld. "
3305 "New time %ld.\n", cs84xx_time,
3306 wtime);
4d4df193
HK		 3307 }
3308 } else if (state[0] == FSTATE_READY) {
7c3df132
SK		 3309 ql_dbg(ql_dbg_taskm, vha, 0x8037,
3310 "F/W Ready - OK.\n");
1da177e4 3311
e315cd28 3312 qla2x00_get_retry_cnt(vha, &ha->retry_count,
1da177e4
LT		 3313 &ha->login_timeout, &ha->r_a_tov);
3314
3315 rval = QLA_SUCCESS;
3316 break;
3317 }
3318
3319 rval = QLA_FUNCTION_FAILED;
3320
e315cd28 3321 if (atomic_read(&vha->loop_down_timer) &&
4d4df193 3322 state[0] != FSTATE_READY) {
1da177e4 3323 /* Loop down. Timeout on min_wait for states
fa2a1ce5
AV		 3324 * other than Wait for Login.
3325 */
1da177e4 3326 if (time_after_eq(jiffies, mtime)) {
7c3df132 3327 ql_log(ql_log_info, vha, 0x8038,
1da177e4
LT		 3328 "Cable is unplugged...\n");
3329
e315cd28 3330 vha->device_flags |= DFLG_NO_CABLE;
1da177e4
LT		 3331 break;
3332 }
3333 }
3334 } else {
3335 /* Mailbox cmd failed. Timeout on min_wait. */
cdbb0a4f 3336 if (time_after_eq(jiffies, mtime) ||
7190575f 3337 ha->flags.isp82xx_fw_hung)
1da177e4
LT		 3338 break;
3339 }
3340
3341 if (time_after_eq(jiffies, wtime))
3342 break;
3343
3344 /* Delay for a while */
3345 msleep(500);
1da177e4
LT		 3346 } while (1);
3347
7c3df132 3348 ql_dbg(ql_dbg_taskm, vha, 0x803a,
b5a340dd
JC		 3349 "fw_state=%x (%x, %x, %x, %x %x) curr time=%lx.\n", state[0],
3350 state[1], state[2], state[3], state[4], state[5], jiffies);
1da177e4 3351
cfb0919c 3352 if (rval && !(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132
SK		 3353 ql_log(ql_log_warn, vha, 0x803b,
3354 "Firmware ready **** FAILED ****.\n");
1da177e4
LT		 3355 }
3356
3357 return (rval);
3358}
3359
3360/*
3361* qla2x00_configure_hba
3362* Setup adapter context.
3363*
3364* Input:
3365* ha = adapter state pointer.
3366*
3367* Returns:
3368* 0 = success
3369*
3370* Context:
3371* Kernel context.
3372*/
3373static int
e315cd28 3374qla2x00_configure_hba(scsi_qla_host_t *vha)
1da177e4
LT		 3375{
3376 int rval;
3377 uint16_t loop_id;
3378 uint16_t topo;
2c3dfe3f 3379 uint16_t sw_cap;
1da177e4
LT		 3380 uint8_t al_pa;
3381 uint8_t area;
3382 uint8_t domain;
3383 char connect_type[22];
e315cd28 3384 struct qla_hw_data *ha = vha->hw;
f24b5cb8 3385 unsigned long flags;
61e1b269 3386 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 3387
3388 /* Get host addresses. */
e315cd28 3389 rval = qla2x00_get_adapter_id(vha,
2c3dfe3f 3390 &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
1da177e4 3391 if (rval != QLA_SUCCESS) {
e315cd28 3392 if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
6246b8a1 3393 IS_CNA_CAPABLE(ha) ||
33135aa2 3394 (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
7c3df132
SK		 3395 ql_dbg(ql_dbg_disc, vha, 0x2008,
3396 "Loop is in a transition state.\n");
33135aa2 3397 } else {
7c3df132
SK		 3398 ql_log(ql_log_warn, vha, 0x2009,
3399 "Unable to get host loop ID.\n");
61e1b269
JC		 3400 if (IS_FWI2_CAPABLE(ha) && (vha == base_vha) &&
3401 (rval == QLA_COMMAND_ERROR && loop_id == 0x1b)) {
3402 ql_log(ql_log_warn, vha, 0x1151,
3403 "Doing link init.\n");
3404 if (qla24xx_link_initialize(vha) == QLA_SUCCESS)
3405 return rval;
3406 }
e315cd28 3407 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
33135aa2 3408 }
1da177e4
LT		 3409 return (rval);
3410 }
3411
3412 if (topo == 4) {
7c3df132
SK		 3413 ql_log(ql_log_info, vha, 0x200a,
3414 "Cannot get topology - retrying.\n");
1da177e4
LT		 3415 return (QLA_FUNCTION_FAILED);
3416 }
3417
e315cd28 3418 vha->loop_id = loop_id;
1da177e4
LT		 3419
3420 /* initialize */
3421 ha->min_external_loopid = SNS_FIRST_LOOP_ID;
3422 ha->operating_mode = LOOP;
2c3dfe3f 3423 ha->switch_cap = 0;
1da177e4
LT		 3424
3425 switch (topo) {
3426 case 0:
7c3df132 3427 ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n");
1da177e4
LT		 3428 ha->current_topology = ISP_CFG_NL;
3429 strcpy(connect_type, "(Loop)");
3430 break;
3431
3432 case 1:
7c3df132 3433 ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n");
2c3dfe3f 3434 ha->switch_cap = sw_cap;
1da177e4
LT		 3435 ha->current_topology = ISP_CFG_FL;
3436 strcpy(connect_type, "(FL_Port)");
3437 break;
3438
3439 case 2:
7c3df132 3440 ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n");
1da177e4
LT		 3441 ha->operating_mode = P2P;
3442 ha->current_topology = ISP_CFG_N;
3443 strcpy(connect_type, "(N_Port-to-N_Port)");
3444 break;
3445
3446 case 3:
7c3df132 3447 ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n");
2c3dfe3f 3448 ha->switch_cap = sw_cap;
1da177e4
LT		 3449 ha->operating_mode = P2P;
3450 ha->current_topology = ISP_CFG_F;
3451 strcpy(connect_type, "(F_Port)");
3452 break;
3453
3454 default:
7c3df132
SK		 3455 ql_dbg(ql_dbg_disc, vha, 0x200f,
3456 "HBA in unknown topology %x, using NL.\n", topo);
1da177e4
LT		 3457 ha->current_topology = ISP_CFG_NL;
3458 strcpy(connect_type, "(Loop)");
3459 break;
3460 }
3461
3462 /* Save Host port and loop ID. */
3463 /* byte order - Big Endian */
e315cd28
AC		 3464 vha->d_id.b.domain = domain;
3465 vha->d_id.b.area = area;
3466 vha->d_id.b.al_pa = al_pa;
1da177e4 3467
f24b5cb8 3468 spin_lock_irqsave(&ha->vport_slock, flags);
2d70c103 3469 qlt_update_vp_map(vha, SET_AL_PA);
f24b5cb8 3470 spin_unlock_irqrestore(&ha->vport_slock, flags);
2d70c103 3471
e315cd28 3472 if (!vha->flags.init_done)
7c3df132
SK		 3473 ql_log(ql_log_info, vha, 0x2010,
3474 "Topology - %s, Host Loop address 0x%x.\n",
e315cd28 3475 connect_type, vha->loop_id);
1da177e4 3476
1da177e4
LT		 3477 return(rval);
3478}
3479
a9083016 3480inline void
e315cd28
AC		 3481qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
3482 char *def)
9bb9fcf2
AV		 3483{
3484 char *st, *en;
3485 uint16_t index;
e315cd28 3486 struct qla_hw_data *ha = vha->hw;
ab671149 3487 int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
6246b8a1 3488 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha);
9bb9fcf2
AV		 3489
3490 if (memcmp(model, BINZERO, len) != 0) {
3491 strncpy(ha->model_number, model, len);
3492 st = en = ha->model_number;
3493 en += len - 1;
3494 while (en > st) {
3495 if (*en != 0x20 && *en != 0x00)
3496 break;
3497 *en-- = '\0';
3498 }
3499
3500 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 3501 if (use_tbl &&
3502 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2 3503 index < QLA_MODEL_NAMES)
1ee27146
JC		 3504 strncpy(ha->model_desc,
3505 qla2x00_model_name[index * 2 + 1],
3506 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 3507 } else {
3508 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 3509 if (use_tbl &&
3510 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2
AV		 3511 index < QLA_MODEL_NAMES) {
3512 strcpy(ha->model_number,
3513 qla2x00_model_name[index * 2]);
1ee27146
JC		 3514 strncpy(ha->model_desc,
3515 qla2x00_model_name[index * 2 + 1],
3516 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 3517 } else {
3518 strcpy(ha->model_number, def);
3519 }
3520 }
1ee27146 3521 if (IS_FWI2_CAPABLE(ha))
e315cd28 3522 qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc,
1ee27146 3523 sizeof(ha->model_desc));
9bb9fcf2
AV		 3524}
3525
4e08df3f
DM		 3526/* On sparc systems, obtain port and node WWN from firmware
3527 * properties.
3528 */
e315cd28 3529static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv)
4e08df3f
DM		 3530{
3531#ifdef CONFIG_SPARC
e315cd28 3532 struct qla_hw_data *ha = vha->hw;
4e08df3f 3533 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 3534 struct device_node *dp = pci_device_to_OF_node(pdev);
3535 const u8 *val;
4e08df3f
DM		 3536 int len;
3537
3538 val = of_get_property(dp, "port-wwn", &len);
3539 if (val && len >= WWN_SIZE)
3540 memcpy(nv->port_name, val, WWN_SIZE);
3541
3542 val = of_get_property(dp, "node-wwn", &len);
3543 if (val && len >= WWN_SIZE)
3544 memcpy(nv->node_name, val, WWN_SIZE);
3545#endif
3546}
3547
1da177e4
LT		 3548/*
3549* NVRAM configuration for ISP 2xxx
3550*
3551* Input:
3552* ha = adapter block pointer.
3553*
3554* Output:
3555* initialization control block in response_ring
3556* host adapters parameters in host adapter block
3557*
3558* Returns:
3559* 0 = success.
3560*/
abbd8870 3561int
e315cd28 3562qla2x00_nvram_config(scsi_qla_host_t *vha)
1da177e4 3563{
4e08df3f 3564 int rval;
0107109e
AV		 3565 uint8_t chksum = 0;
3566 uint16_t cnt;
3567 uint8_t *dptr1, *dptr2;
e315cd28 3568 struct qla_hw_data *ha = vha->hw;
0107109e 3569 init_cb_t *icb = ha->init_cb;
281afe19
SJ		 3570 nvram_t *nv = ha->nvram;
3571 uint8_t *ptr = ha->nvram;
3d71644c 3572 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 3573
4e08df3f
DM		 3574 rval = QLA_SUCCESS;
3575
1da177e4 3576 /* Determine NVRAM starting address. */
0107109e 3577 ha->nvram_size = sizeof(nvram_t);
1da177e4
LT		 3578 ha->nvram_base = 0;
3579 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
3580 if ((RD_REG_WORD(&reg->ctrl_status) >> 14) == 1)
3581 ha->nvram_base = 0x80;
3582
3583 /* Get NVRAM data and calculate checksum. */
e315cd28 3584 ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size);
0107109e
AV		 3585 for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++)
3586 chksum += *ptr++;
1da177e4 3587
7c3df132
SK		 3588 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
3589 "Contents of NVRAM.\n");
3590 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
3591 (uint8_t *)nv, ha->nvram_size);
1da177e4
LT		 3592
3593 /* Bad NVRAM data, set defaults parameters. */
3594 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' ||
3595 nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) {
3596 /* Reset NVRAM data. */
7c3df132 3597 ql_log(ql_log_warn, vha, 0x0064,
9e336520 3598 "Inconsistent NVRAM "
7c3df132
SK		 3599 "detected: checksum=0x%x id=%c version=0x%x.\n",
3600 chksum, nv->id[0], nv->nvram_version);
3601 ql_log(ql_log_warn, vha, 0x0065,
3602 "Falling back to "
3603 "functioning (yet invalid -- WWPN) defaults.\n");
4e08df3f
DM		 3604
3605 /*
3606 * Set default initialization control block.
3607 */
3608 memset(nv, 0, ha->nvram_size);
3609 nv->parameter_block_version = ICB_VERSION;
3610
3611 if (IS_QLA23XX(ha)) {
3612 nv->firmware_options[0] = BIT_2 | BIT_1;
3613 nv->firmware_options[1] = BIT_7 | BIT_5;
3614 nv->add_firmware_options[0] = BIT_5;
3615 nv->add_firmware_options[1] = BIT_5 | BIT_4;
98aee70d 3616 nv->frame_payload_size = 2048;
4e08df3f
DM		 3617 nv->special_options[1] = BIT_7;
3618 } else if (IS_QLA2200(ha)) {
3619 nv->firmware_options[0] = BIT_2 | BIT_1;
3620 nv->firmware_options[1] = BIT_7 | BIT_5;
3621 nv->add_firmware_options[0] = BIT_5;
3622 nv->add_firmware_options[1] = BIT_5 | BIT_4;
98aee70d 3623 nv->frame_payload_size = 1024;
4e08df3f
DM		 3624 } else if (IS_QLA2100(ha)) {
3625 nv->firmware_options[0] = BIT_3 | BIT_1;
3626 nv->firmware_options[1] = BIT_5;
98aee70d 3627 nv->frame_payload_size = 1024;
4e08df3f
DM		 3628 }
3629
ad950360
BVA		 3630 nv->max_iocb_allocation = cpu_to_le16(256);
3631 nv->execution_throttle = cpu_to_le16(16);
4e08df3f
DM		 3632 nv->retry_count = 8;
3633 nv->retry_delay = 1;
3634
3635 nv->port_name[0] = 33;
3636 nv->port_name[3] = 224;
3637 nv->port_name[4] = 139;
3638
e315cd28 3639 qla2xxx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 3640
3641 nv->login_timeout = 4;
3642
3643 /*
3644 * Set default host adapter parameters
3645 */
3646 nv->host_p[1] = BIT_2;
3647 nv->reset_delay = 5;
3648 nv->port_down_retry_count = 8;
ad950360 3649 nv->max_luns_per_target = cpu_to_le16(8);
4e08df3f
DM		 3650 nv->link_down_timeout = 60;
3651
3652 rval = 1;
1da177e4
LT		 3653 }
3654
3655#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
3656 /*
3657 * The SN2 does not provide BIOS emulation which means you can't change
3658 * potentially bogus BIOS settings. Force the use of default settings
3659 * for link rate and frame size. Hope that the rest of the settings
3660 * are valid.
3661 */
3662 if (ia64_platform_is("sn2")) {
98aee70d 3663 nv->frame_payload_size = 2048;
1da177e4
LT		 3664 if (IS_QLA23XX(ha))
3665 nv->special_options[1] = BIT_7;
3666 }
3667#endif
3668
3669 /* Reset Initialization control block */
0107109e 3670 memset(icb, 0, ha->init_cb_size);
1da177e4
LT		 3671
3672 /*
3673 * Setup driver NVRAM options.
3674 */
3675 nv->firmware_options[0] |= (BIT_6 | BIT_1);
3676 nv->firmware_options[0] &= ~(BIT_5 | BIT_4);
3677 nv->firmware_options[1] |= (BIT_5 | BIT_0);
3678 nv->firmware_options[1] &= ~BIT_4;
3679
3680 if (IS_QLA23XX(ha)) {
3681 nv->firmware_options[0] |= BIT_2;
3682 nv->firmware_options[0] &= ~BIT_3;
2d70c103 3683 nv->special_options[0] &= ~BIT_6;
0107109e 3684 nv->add_firmware_options[1] |= BIT_5 | BIT_4;
1da177e4
LT		 3685
3686 if (IS_QLA2300(ha)) {
3687 if (ha->fb_rev == FPM_2310) {
3688 strcpy(ha->model_number, "QLA2310");
3689 } else {
3690 strcpy(ha->model_number, "QLA2300");
3691 }
3692 } else {
e315cd28 3693 qla2x00_set_model_info(vha, nv->model_number,
9bb9fcf2 3694 sizeof(nv->model_number), "QLA23xx");
1da177e4
LT		 3695 }
3696 } else if (IS_QLA2200(ha)) {
3697 nv->firmware_options[0] |= BIT_2;
3698 /*
3699 * 'Point-to-point preferred, else loop' is not a safe
3700 * connection mode setting.
3701 */
3702 if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
3703 (BIT_5 | BIT_4)) {
3704 /* Force 'loop preferred, else point-to-point'. */
3705 nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
3706 nv->add_firmware_options[0] |= BIT_5;
3707 }
3708 strcpy(ha->model_number, "QLA22xx");
3709 } else /*if (IS_QLA2100(ha))*/ {
3710 strcpy(ha->model_number, "QLA2100");
3711 }
3712
3713 /*
3714 * Copy over NVRAM RISC parameter block to initialization control block.
3715 */
3716 dptr1 = (uint8_t *)icb;
3717 dptr2 = (uint8_t *)&nv->parameter_block_version;
3718 cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;
3719 while (cnt--)
3720 *dptr1++ = *dptr2++;
3721
3722 /* Copy 2nd half. */
3723 dptr1 = (uint8_t *)icb->add_firmware_options;
3724 cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;
3725 while (cnt--)
3726 *dptr1++ = *dptr2++;
3727
5341e868
AV		 3728 /* Use alternate WWN? */
3729 if (nv->host_p[1] & BIT_7) {
3730 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
3731 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
3732 }
3733
1da177e4
LT		 3734 /* Prepare nodename */
3735 if ((icb->firmware_options[1] & BIT_6) == 0) {
3736 /*
3737 * Firmware will apply the following mask if the nodename was
3738 * not provided.
3739 */
3740 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
3741 icb->node_name[0] &= 0xF0;
3742 }
3743
3744 /*
3745 * Set host adapter parameters.
3746 */
3ce8866c
SK		 3747
3748 /*
3749 * BIT_7 in the host-parameters section allows for modification to
3750 * internal driver logging.
3751 */
0181944f 3752 if (nv->host_p[0] & BIT_7)
cfb0919c 3753 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
1da177e4
LT		 3754 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
3755 /* Always load RISC code on non ISP2[12]00 chips. */
3756 if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
3757 ha->flags.disable_risc_code_load = 0;
3758 ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0);
3759 ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
3760 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
06c22bd1 3761 ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
d4c760c2 3762 ha->flags.disable_serdes = 0;
1da177e4
LT		 3763
3764 ha->operating_mode =
3765 (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
3766
3767 memcpy(ha->fw_seriallink_options, nv->seriallink_options,
3768 sizeof(ha->fw_seriallink_options));
3769
3770 /* save HBA serial number */
3771 ha->serial0 = icb->port_name[5];
3772 ha->serial1 = icb->port_name[6];
3773 ha->serial2 = icb->port_name[7];
e315cd28
AC		 3774 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
3775 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
1da177e4 3776
ad950360 3777 icb->execution_throttle = cpu_to_le16(0xFFFF);
1da177e4
LT		 3778
3779 ha->retry_count = nv->retry_count;
3780
3781 /* Set minimum login_timeout to 4 seconds. */
5b91490e 3782 if (nv->login_timeout != ql2xlogintimeout)
1da177e4
LT		 3783 nv->login_timeout = ql2xlogintimeout;
3784 if (nv->login_timeout < 4)
3785 nv->login_timeout = 4;
3786 ha->login_timeout = nv->login_timeout;
1da177e4 3787
00a537b8
AV		 3788 /* Set minimum RATOV to 100 tenths of a second. */
3789 ha->r_a_tov = 100;
1da177e4 3790
1da177e4
LT		 3791 ha->loop_reset_delay = nv->reset_delay;
3792
1da177e4
LT		 3793 /* Link Down Timeout = 0:
3794 *
3795 * When Port Down timer expires we will start returning
3796 * I/O's to OS with "DID_NO_CONNECT".
3797 *
3798 * Link Down Timeout != 0:
3799 *
3800 * The driver waits for the link to come up after link down
3801 * before returning I/Os to OS with "DID_NO_CONNECT".
fa2a1ce5 3802 */
1da177e4
LT		 3803 if (nv->link_down_timeout == 0) {
3804 ha->loop_down_abort_time =
354d6b21 3805 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
1da177e4
LT		 3806 } else {
3807 ha->link_down_timeout = nv->link_down_timeout;
3808 ha->loop_down_abort_time =
3809 (LOOP_DOWN_TIME - ha->link_down_timeout);
fa2a1ce5 3810 }
1da177e4 3811
1da177e4
LT		 3812 /*
3813 * Need enough time to try and get the port back.
3814 */
3815 ha->port_down_retry_count = nv->port_down_retry_count;
3816 if (qlport_down_retry)
3817 ha->port_down_retry_count = qlport_down_retry;
3818 /* Set login_retry_count */
3819 ha->login_retry_count = nv->retry_count;
3820 if (ha->port_down_retry_count == nv->port_down_retry_count &&
3821 ha->port_down_retry_count > 3)
3822 ha->login_retry_count = ha->port_down_retry_count;
3823 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
3824 ha->login_retry_count = ha->port_down_retry_count;
3825 if (ql2xloginretrycount)
3826 ha->login_retry_count = ql2xloginretrycount;
3827
ad950360 3828 icb->lun_enables = cpu_to_le16(0);
1da177e4
LT		 3829 icb->command_resource_count = 0;
3830 icb->immediate_notify_resource_count = 0;
ad950360 3831 icb->timeout = cpu_to_le16(0);
1da177e4
LT		 3832
3833 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
3834 /* Enable RIO */
3835 icb->firmware_options[0] &= ~BIT_3;
3836 icb->add_firmware_options[0] &=
3837 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
3838 icb->add_firmware_options[0] |= BIT_2;
3839 icb->response_accumulation_timer = 3;
3840 icb->interrupt_delay_timer = 5;
3841
e315cd28 3842 vha->flags.process_response_queue = 1;
1da177e4 3843 } else {
4fdfefe5 3844 /* Enable ZIO. */
e315cd28 3845 if (!vha->flags.init_done) {
4fdfefe5
AV		 3846 ha->zio_mode = icb->add_firmware_options[0] &
3847 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
3848 ha->zio_timer = icb->interrupt_delay_timer ?
3849 icb->interrupt_delay_timer: 2;
3850 }
1da177e4
LT		 3851 icb->add_firmware_options[0] &=
3852 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
e315cd28 3853 vha->flags.process_response_queue = 0;
4fdfefe5 3854 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d
AV		 3855 ha->zio_mode = QLA_ZIO_MODE_6;
3856
7c3df132 3857 ql_log(ql_log_info, vha, 0x0068,
4fdfefe5
AV		 3858 "ZIO mode %d enabled; timer delay (%d us).\n",
3859 ha->zio_mode, ha->zio_timer * 100);
1da177e4 3860
4fdfefe5
AV		 3861 icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;
3862 icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;
e315cd28 3863 vha->flags.process_response_queue = 1;
1da177e4
LT		 3864 }
3865 }
3866
4e08df3f 3867 if (rval) {
7c3df132
SK		 3868 ql_log(ql_log_warn, vha, 0x0069,
3869 "NVRAM configuration failed.\n");
4e08df3f
DM		 3870 }
3871 return (rval);
1da177e4
LT		 3872}
3873
19a7b4ae
JSEC		 3874static void
3875qla2x00_rport_del(void *data)
3876{
3877 fc_port_t *fcport = data;
d97994dc 3878 struct fc_rport *rport;
044d78e1 3879 unsigned long flags;
d97994dc 3880
044d78e1 3881 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
ac280b67 3882 rport = fcport->drport ? fcport->drport: fcport->rport;
d97994dc 3883 fcport->drport = NULL;
044d78e1 3884 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
726b8548
QT		 3885 if (rport) {
3886 ql_dbg(ql_dbg_disc, fcport->vha, 0xffff,
3887 "%s %8phN. rport %p roles %x \n",
3888 __func__, fcport->port_name, rport,
3889 rport->roles);
3890
d97994dc 3891 fc_remote_port_delete(rport);
726b8548 3892 }
19a7b4ae
JSEC		 3893}
3894
1da177e4
LT		 3895/**
3896 * qla2x00_alloc_fcport() - Allocate a generic fcport.
3897 * @ha: HA context
3898 * @flags: allocation flags
3899 *
3900 * Returns a pointer to the allocated fcport, or NULL, if none available.
3901 */
9a069e19 3902fc_port_t *
e315cd28 3903qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags)
1da177e4
LT		 3904{
3905 fc_port_t *fcport;
3906
bbfbbbc1
MK		 3907 fcport = kzalloc(sizeof(fc_port_t), flags);
3908 if (!fcport)
3909 return NULL;
1da177e4
LT		 3910
3911 /* Setup fcport template structure. */
e315cd28 3912 fcport->vha = vha;
1da177e4
LT		 3913 fcport->port_type = FCT_UNKNOWN;
3914 fcport->loop_id = FC_NO_LOOP_ID;
ec426e10 3915 qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
ad3e0eda 3916 fcport->supported_classes = FC_COS_UNSPECIFIED;
1da177e4 3917
726b8548
QT		 3918 fcport->ct_desc.ct_sns = dma_alloc_coherent(&vha->hw->pdev->dev,
3919 sizeof(struct ct_sns_pkt), &fcport->ct_desc.ct_sns_dma,
6cb3216a 3920 flags);
726b8548
QT		 3921 fcport->disc_state = DSC_DELETED;
3922 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL;
3923 fcport->deleted = QLA_SESS_DELETED;
3924 fcport->login_retry = vha->hw->login_retry_count;
3925 fcport->login_retry = 5;
3926 fcport->logout_on_delete = 1;
3927
3928 if (!fcport->ct_desc.ct_sns) {
3929 ql_log(ql_log_warn, vha, 0xffff,
3930 "Failed to allocate ct_sns request.\n");
3931 kfree(fcport);
3932 fcport = NULL;
3933 }
3934 INIT_WORK(&fcport->del_work, qla24xx_delete_sess_fn);
3935 INIT_LIST_HEAD(&fcport->gnl_entry);
3936 INIT_LIST_HEAD(&fcport->list);
3937
bbfbbbc1 3938 return fcport;
1da177e4
LT		 3939}
3940
726b8548
QT		 3941void
3942qla2x00_free_fcport(fc_port_t *fcport)
3943{
3944 if (fcport->ct_desc.ct_sns) {
3945 dma_free_coherent(&fcport->vha->hw->pdev->dev,
3946 sizeof(struct ct_sns_pkt), fcport->ct_desc.ct_sns,
3947 fcport->ct_desc.ct_sns_dma);
3948
3949 fcport->ct_desc.ct_sns = NULL;
3950 }
3951 kfree(fcport);
3952}
3953
1da177e4
LT		 3954/*
3955 * qla2x00_configure_loop
3956 * Updates Fibre Channel Device Database with what is actually on loop.
3957 *
3958 * Input:
3959 * ha = adapter block pointer.
3960 *
3961 * Returns:
3962 * 0 = success.
3963 * 1 = error.
3964 * 2 = database was full and device was not configured.
3965 */
3966static int
e315cd28 3967qla2x00_configure_loop(scsi_qla_host_t *vha)
1da177e4
LT		 3968{
3969 int rval;
3970 unsigned long flags, save_flags;
e315cd28 3971 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3972 rval = QLA_SUCCESS;
3973
3974 /* Get Initiator ID */
e315cd28
AC		 3975 if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) {
3976 rval = qla2x00_configure_hba(vha);
1da177e4 3977 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3978 ql_dbg(ql_dbg_disc, vha, 0x2013,
3979 "Unable to configure HBA.\n");
1da177e4
LT		 3980 return (rval);
3981 }
3982 }
3983
e315cd28 3984 save_flags = flags = vha->dpc_flags;
7c3df132
SK		 3985 ql_dbg(ql_dbg_disc, vha, 0x2014,
3986 "Configure loop -- dpc flags = 0x%lx.\n", flags);
1da177e4
LT		 3987
3988 /*
3989 * If we have both an RSCN and PORT UPDATE pending then handle them
3990 * both at the same time.
3991 */
e315cd28
AC		 3992 clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
3993 clear_bit(RSCN_UPDATE, &vha->dpc_flags);
1da177e4 3994
3064ff39
MH		 3995 qla2x00_get_data_rate(vha);
3996
1da177e4
LT		 3997 /* Determine what we need to do */
3998 if (ha->current_topology == ISP_CFG_FL &&
3999 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
4000
1da177e4
LT		 4001 set_bit(RSCN_UPDATE, &flags);
4002
4003 } else if (ha->current_topology == ISP_CFG_F &&
4004 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
4005
1da177e4
LT		 4006 set_bit(RSCN_UPDATE, &flags);
4007 clear_bit(LOCAL_LOOP_UPDATE, &flags);
21333b48
AV		 4008
4009 } else if (ha->current_topology == ISP_CFG_N) {
4010 clear_bit(RSCN_UPDATE, &flags);
41dc529a
QT		 4011 } else if (ha->current_topology == ISP_CFG_NL) {
4012 clear_bit(RSCN_UPDATE, &flags);
4013 set_bit(LOCAL_LOOP_UPDATE, &flags);
e315cd28 4014 } else if (!vha->flags.online ||
1da177e4 4015 (test_bit(ABORT_ISP_ACTIVE, &flags))) {
1da177e4
LT		 4016 set_bit(RSCN_UPDATE, &flags);
4017 set_bit(LOCAL_LOOP_UPDATE, &flags);
4018 }
4019
4020 if (test_bit(LOCAL_LOOP_UPDATE, &flags)) {
7c3df132
SK		 4021 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
4022 ql_dbg(ql_dbg_disc, vha, 0x2015,
4023 "Loop resync needed, failing.\n");
1da177e4 4024 rval = QLA_FUNCTION_FAILED;
642ef983 4025 } else
e315cd28 4026 rval = qla2x00_configure_local_loop(vha);
1da177e4
LT		 4027 }
4028
4029 if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
7c3df132
SK		 4030 if (LOOP_TRANSITION(vha)) {
4031 ql_dbg(ql_dbg_disc, vha, 0x201e,
4032 "Needs RSCN update and loop transition.\n");
1da177e4 4033 rval = QLA_FUNCTION_FAILED;
7c3df132 4034 }
e315cd28
AC		 4035 else
4036 rval = qla2x00_configure_fabric(vha);
1da177e4
LT		 4037 }
4038
4039 if (rval == QLA_SUCCESS) {
e315cd28
AC		 4040 if (atomic_read(&vha->loop_down_timer) ||
4041 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4
LT		 4042 rval = QLA_FUNCTION_FAILED;
4043 } else {
e315cd28 4044 atomic_set(&vha->loop_state, LOOP_READY);
7c3df132
SK		 4045 ql_dbg(ql_dbg_disc, vha, 0x2069,
4046 "LOOP READY.\n");
3bb67df5
DKU		 4047
4048 /*
4049 * Process any ATIO queue entries that came in
4050 * while we weren't online.
4051 */
ead03855
QT		 4052 if (qla_tgt_mode_enabled(vha) ||
4053 qla_dual_mode_enabled(vha)) {
3bb67df5
DKU		 4054 if (IS_QLA27XX(ha) || IS_QLA83XX(ha)) {
4055 spin_lock_irqsave(&ha->tgt.atio_lock,
4056 flags);
4057 qlt_24xx_process_atio_queue(vha, 0);
4058 spin_unlock_irqrestore(
4059 &ha->tgt.atio_lock, flags);
4060 } else {
4061 spin_lock_irqsave(&ha->hardware_lock,
4062 flags);
4063 qlt_24xx_process_atio_queue(vha, 1);
4064 spin_unlock_irqrestore(
4065 &ha->hardware_lock, flags);
4066 }
4067 }
1da177e4
LT		 4068 }
4069 }
4070
4071 if (rval) {
7c3df132
SK		 4072 ql_dbg(ql_dbg_disc, vha, 0x206a,
4073 "%s *** FAILED ***.\n", __func__);
1da177e4 4074 } else {
7c3df132
SK		 4075 ql_dbg(ql_dbg_disc, vha, 0x206b,
4076 "%s: exiting normally.\n", __func__);
1da177e4
LT		 4077 }
4078
cc3ef7bc 4079 /* Restore state if a resync event occurred during processing */
e315cd28 4080 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4 4081 if (test_bit(LOCAL_LOOP_UPDATE, &save_flags))
e315cd28 4082 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
f4658b6c 4083 if (test_bit(RSCN_UPDATE, &save_flags)) {
e315cd28 4084 set_bit(RSCN_UPDATE, &vha->dpc_flags);
f4658b6c 4085 }
1da177e4
LT		 4086 }
4087
4088 return (rval);
4089}
4090
4091
4092
4093/*
4094 * qla2x00_configure_local_loop
4095 * Updates Fibre Channel Device Database with local loop devices.
4096 *
4097 * Input:
4098 * ha = adapter block pointer.
4099 *
4100 * Returns:
4101 * 0 = success.
4102 */
4103static int
e315cd28 4104qla2x00_configure_local_loop(scsi_qla_host_t *vha)
1da177e4
LT		 4105{
4106 int rval, rval2;
4107 int found_devs;
4108 int found;
4109 fc_port_t *fcport, *new_fcport;
4110
4111 uint16_t index;
4112 uint16_t entries;
4113 char *id_iter;
4114 uint16_t loop_id;
4115 uint8_t domain, area, al_pa;
e315cd28 4116 struct qla_hw_data *ha = vha->hw;
41dc529a 4117 unsigned long flags;
1da177e4
LT		 4118
4119 found_devs = 0;
4120 new_fcport = NULL;
642ef983 4121 entries = MAX_FIBRE_DEVICES_LOOP;
1da177e4 4122
1da177e4 4123 /* Get list of logged in devices. */
642ef983 4124 memset(ha->gid_list, 0, qla2x00_gid_list_size(ha));
e315cd28 4125 rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma,
1da177e4
LT		 4126 &entries);
4127 if (rval != QLA_SUCCESS)
4128 goto cleanup_allocation;
4129
7c3df132
SK		 4130 ql_dbg(ql_dbg_disc, vha, 0x2017,
4131 "Entries in ID list (%d).\n", entries);
4132 ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
4133 (uint8_t *)ha->gid_list,
4134 entries * sizeof(struct gid_list_info));
1da177e4
LT		 4135
4136 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 4137 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 4138 if (new_fcport == NULL) {
7c3df132
SK		 4139 ql_log(ql_log_warn, vha, 0x2018,
4140 "Memory allocation failed for fcport.\n");
1da177e4
LT		 4141 rval = QLA_MEMORY_ALLOC_FAILED;
4142 goto cleanup_allocation;
4143 }
4144 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
4145
4146 /*
4147 * Mark local devices that were present with FCF_DEVICE_LOST for now.
4148 */
e315cd28 4149 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 4150 if (atomic_read(&fcport->state) == FCS_ONLINE &&
4151 fcport->port_type != FCT_BROADCAST &&
4152 (fcport->flags & FCF_FABRIC_DEVICE) == 0) {
4153
7c3df132
SK		 4154 ql_dbg(ql_dbg_disc, vha, 0x2019,
4155 "Marking port lost loop_id=0x%04x.\n",
4156 fcport->loop_id);
1da177e4 4157
41dc529a 4158 qla2x00_mark_device_lost(vha, fcport, 0, 0);
1da177e4
LT		 4159 }
4160 }
4161
4162 /* Add devices to port list. */
4163 id_iter = (char *)ha->gid_list;
4164 for (index = 0; index < entries; index++) {
4165 domain = ((struct gid_list_info *)id_iter)->domain;
4166 area = ((struct gid_list_info *)id_iter)->area;
4167 al_pa = ((struct gid_list_info *)id_iter)->al_pa;
abbd8870 4168 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1da177e4
LT		 4169 loop_id = (uint16_t)
4170 ((struct gid_list_info *)id_iter)->loop_id_2100;
abbd8870 4171 else
1da177e4
LT		 4172 loop_id = le16_to_cpu(
4173 ((struct gid_list_info *)id_iter)->loop_id);
abbd8870 4174 id_iter += ha->gid_list_info_size;
1da177e4
LT		 4175
4176 /* Bypass reserved domain fields. */
4177 if ((domain & 0xf0) == 0xf0)
4178 continue;
4179
4180 /* Bypass if not same domain and area of adapter. */
f7d289f6 4181 if (area && domain &&
e315cd28 4182 (area != vha->d_id.b.area || domain != vha->d_id.b.domain))
1da177e4
LT		 4183 continue;
4184
4185 /* Bypass invalid local loop ID. */
4186 if (loop_id > LAST_LOCAL_LOOP_ID)
4187 continue;
4188
41dc529a 4189 memset(new_fcport->port_name, 0, WWN_SIZE);
370d550e 4190
1da177e4
LT		 4191 /* Fill in member data. */
4192 new_fcport->d_id.b.domain = domain;
4193 new_fcport->d_id.b.area = area;
4194 new_fcport->d_id.b.al_pa = al_pa;
4195 new_fcport->loop_id = loop_id;
41dc529a 4196
e315cd28 4197 rval2 = qla2x00_get_port_database(vha, new_fcport, 0);
1da177e4 4198 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 4199 ql_dbg(ql_dbg_disc, vha, 0x201a,
4200 "Failed to retrieve fcport information "
4201 "-- get_port_database=%x, loop_id=0x%04x.\n",
4202 rval2, new_fcport->loop_id);
4203 ql_dbg(ql_dbg_disc, vha, 0x201b,
4204 "Scheduling resync.\n");
e315cd28 4205 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4
LT		 4206 continue;
4207 }
4208
41dc529a 4209 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
1da177e4
LT		 4210 /* Check for matching device in port list. */
4211 found = 0;
4212 fcport = NULL;
e315cd28 4213 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 4214 if (memcmp(new_fcport->port_name, fcport->port_name,
4215 WWN_SIZE))
4216 continue;
4217
ddb9b126 4218 fcport->flags &= ~FCF_FABRIC_DEVICE;
1da177e4
LT		 4219 fcport->loop_id = new_fcport->loop_id;
4220 fcport->port_type = new_fcport->port_type;
4221 fcport->d_id.b24 = new_fcport->d_id.b24;
4222 memcpy(fcport->node_name, new_fcport->node_name,
4223 WWN_SIZE);
4224
41dc529a
QT		 4225 if (!fcport->login_succ) {
4226 vha->fcport_count++;
4227 fcport->login_succ = 1;
4228 fcport->disc_state = DSC_LOGIN_COMPLETE;
4229 }
4230
1da177e4
LT		 4231 found++;
4232 break;
4233 }
4234
4235 if (!found) {
4236 /* New device, add to fcports list. */
e315cd28 4237 list_add_tail(&new_fcport->list, &vha->vp_fcports);
1da177e4
LT		 4238
4239 /* Allocate a new replacement fcport. */
4240 fcport = new_fcport;
41dc529a
QT		 4241 if (!fcport->login_succ) {
4242 vha->fcport_count++;
4243 fcport->login_succ = 1;
4244 fcport->disc_state = DSC_LOGIN_COMPLETE;
4245 }
4246
4247 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
4248
e315cd28 4249 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
41dc529a 4250
1da177e4 4251 if (new_fcport == NULL) {
7c3df132
SK		 4252 ql_log(ql_log_warn, vha, 0x201c,
4253 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 4254 rval = QLA_MEMORY_ALLOC_FAILED;
4255 goto cleanup_allocation;
4256 }
41dc529a 4257 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
1da177e4
LT		 4258 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
4259 }
4260
41dc529a
QT		 4261 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
4262
d8b45213 4263 /* Base iIDMA settings on HBA port speed. */
a3cbdfad 4264 fcport->fp_speed = ha->link_data_rate;
d8b45213 4265
e315cd28 4266 qla2x00_update_fcport(vha, fcport);
1da177e4
LT		 4267
4268 found_devs++;
4269 }
4270
4271cleanup_allocation:
c9475cb0 4272 kfree(new_fcport);
1da177e4
LT		 4273
4274 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4275 ql_dbg(ql_dbg_disc, vha, 0x201d,
4276 "Configure local loop error exit: rval=%x.\n", rval);
1da177e4
LT		 4277 }
4278
1da177e4
LT		 4279 return (rval);
4280}
4281
d8b45213 4282static void
e315cd28 4283qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
d8b45213 4284{
d8b45213 4285 int rval;
93f2bd67 4286 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 4287 struct qla_hw_data *ha = vha->hw;
d8b45213 4288
c76f2c01 4289 if (!IS_IIDMA_CAPABLE(ha))
d8b45213
AV		 4290 return;
4291
c9afb9a2
GM		 4292 if (atomic_read(&fcport->state) != FCS_ONLINE)
4293 return;
4294
39bd9622
AV		 4295 if (fcport->fp_speed == PORT_SPEED_UNKNOWN ||
4296 fcport->fp_speed > ha->link_data_rate)
d8b45213
AV		 4297 return;
4298
e315cd28 4299 rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed,
a3cbdfad 4300 mb);
d8b45213 4301 if (rval != QLA_SUCCESS) {
7c3df132 4302 ql_dbg(ql_dbg_disc, vha, 0x2004,
7b833558
OK		 4303 "Unable to adjust iIDMA %8phN -- %04x %x %04x %04x.\n",
4304 fcport->port_name, rval, fcport->fp_speed, mb[0], mb[1]);
d8b45213 4305 } else {
7c3df132 4306 ql_dbg(ql_dbg_disc, vha, 0x2005,
7b833558 4307 "iIDMA adjusted to %s GB/s on %8phN.\n",
d0297c9a 4308 qla2x00_get_link_speed_str(ha, fcport->fp_speed),
7b833558 4309 fcport->port_name);
d8b45213
AV		 4310 }
4311}
4312
726b8548 4313/* qla2x00_reg_remote_port is reserved for Initiator Mode only.*/
23be331d 4314static void
e315cd28 4315qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport)
8482e118
AV		 4316{
4317 struct fc_rport_identifiers rport_ids;
bdf79621 4318 struct fc_rport *rport;
044d78e1 4319 unsigned long flags;
8482e118 4320
f8b02a85
AV		 4321 rport_ids.node_name = wwn_to_u64(fcport->node_name);
4322 rport_ids.port_name = wwn_to_u64(fcport->port_name);
8482e118
AV		 4323 rport_ids.port_id = fcport->d_id.b.domain << 16 |
4324 fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa;
77d74143 4325 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
e315cd28 4326 fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids);
77d74143 4327 if (!rport) {
7c3df132
SK		 4328 ql_log(ql_log_warn, vha, 0x2006,
4329 "Unable to allocate fc remote port.\n");
77d74143
AV		 4330 return;
4331 }
2d70c103 4332
044d78e1 4333 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
19a7b4ae 4334 *((fc_port_t **)rport->dd_data) = fcport;
044d78e1 4335 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
d97994dc 4336
ad3e0eda 4337 rport->supported_classes = fcport->supported_classes;
77d74143 4338
8482e118
AV		 4339 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
4340 if (fcport->port_type == FCT_INITIATOR)
4341 rport_ids.roles |= FC_RPORT_ROLE_FCP_INITIATOR;
4342 if (fcport->port_type == FCT_TARGET)
4343 rport_ids.roles |= FC_RPORT_ROLE_FCP_TARGET;
726b8548
QT		 4344
4345 ql_dbg(ql_dbg_disc, vha, 0xffff,
4346 "%s %8phN. rport %p is %s mode \n",
4347 __func__, fcport->port_name, rport,
4348 (fcport->port_type == FCT_TARGET) ? "tgt" : "ini");
4349
77d74143 4350 fc_remote_port_rolechg(rport, rport_ids.roles);
1da177e4
LT		 4351}
4352
23be331d
AB		 4353/*
4354 * qla2x00_update_fcport
4355 * Updates device on list.
4356 *
4357 * Input:
4358 * ha = adapter block pointer.
4359 * fcport = port structure pointer.
4360 *
4361 * Return:
4362 * 0 - Success
4363 * BIT_0 - error
4364 *
4365 * Context:
4366 * Kernel context.
4367 */
4368void
e315cd28 4369qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
23be331d 4370{
e315cd28 4371 fcport->vha = vha;
8ae6d9c7 4372
726b8548
QT		 4373 if (IS_SW_RESV_ADDR(fcport->d_id))
4374 return;
4375
4376 ql_dbg(ql_dbg_disc, vha, 0xffff, "%s %8phC \n",
4377 __func__, fcport->port_name);
4378
8ae6d9c7
GM		 4379 if (IS_QLAFX00(vha->hw)) {
4380 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
d20ed91b 4381 goto reg_port;
8ae6d9c7 4382 }
23be331d 4383 fcport->login_retry = 0;
5ff1d584 4384 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
726b8548
QT		 4385 fcport->disc_state = DSC_LOGIN_COMPLETE;
4386 fcport->deleted = 0;
4387 fcport->logout_on_delete = 1;
23be331d 4388
1f93da52 4389 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
e315cd28 4390 qla2x00_iidma_fcport(vha, fcport);
21090cbe 4391 qla24xx_update_fcport_fcp_prio(vha, fcport);
d20ed91b
AP		 4392
4393reg_port:
726b8548
QT		 4394 switch (vha->host->active_mode) {
4395 case MODE_INITIATOR:
d20ed91b 4396 qla2x00_reg_remote_port(vha, fcport);
726b8548
QT		 4397 break;
4398 case MODE_TARGET:
4399 if (!vha->vha_tgt.qla_tgt->tgt_stop &&
4400 !vha->vha_tgt.qla_tgt->tgt_stopped)
4401 qlt_fc_port_added(vha, fcport);
4402 break;
4403 case MODE_DUAL:
d20ed91b 4404 qla2x00_reg_remote_port(vha, fcport);
726b8548
QT		 4405 if (!vha->vha_tgt.qla_tgt->tgt_stop &&
4406 !vha->vha_tgt.qla_tgt->tgt_stopped)
4407 qlt_fc_port_added(vha, fcport);
4408 break;
4409 default:
4410 break;
d20ed91b 4411 }
23be331d
AB		 4412}
4413
1da177e4
LT		 4414/*
4415 * qla2x00_configure_fabric
4416 * Setup SNS devices with loop ID's.
4417 *
4418 * Input:
4419 * ha = adapter block pointer.
4420 *
4421 * Returns:
4422 * 0 = success.
4423 * BIT_0 = error
4424 */
4425static int
e315cd28 4426qla2x00_configure_fabric(scsi_qla_host_t *vha)
1da177e4 4427{
b3b02e6e 4428 int rval;
726b8548 4429 fc_port_t *fcport;
1da177e4 4430 uint16_t mb[MAILBOX_REGISTER_COUNT];
0107109e 4431 uint16_t loop_id;
1da177e4 4432 LIST_HEAD(new_fcports);
e315cd28 4433 struct qla_hw_data *ha = vha->hw;
df673274 4434 int discovery_gen;
1da177e4
LT		 4435
4436 /* If FL port exists, then SNS is present */
e428924c 4437 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 4438 loop_id = NPH_F_PORT;
4439 else
4440 loop_id = SNS_FL_PORT;
e315cd28 4441 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1);
1da177e4 4442 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4443 ql_dbg(ql_dbg_disc, vha, 0x201f,
4444 "MBX_GET_PORT_NAME failed, No FL Port.\n");
1da177e4 4445
e315cd28 4446 vha->device_flags &= ~SWITCH_FOUND;
1da177e4
LT		 4447 return (QLA_SUCCESS);
4448 }
e315cd28 4449 vha->device_flags |= SWITCH_FOUND;
1da177e4 4450
41dc529a
QT		 4451
4452 if (qla_tgt_mode_enabled(vha) || qla_dual_mode_enabled(vha)) {
4453 rval = qla2x00_send_change_request(vha, 0x3, 0);
4454 if (rval != QLA_SUCCESS)
4455 ql_log(ql_log_warn, vha, 0x121,
4456 "Failed to enable receiving of RSCN requests: 0x%x.\n",
4457 rval);
4458 }
4459
4460
1da177e4 4461 do {
726b8548
QT		 4462 qla2x00_mgmt_svr_login(vha);
4463
cca5335c
AV		 4464 /* FDMI support. */
4465 if (ql2xfdmienable &&
e315cd28
AC		 4466 test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags))
4467 qla2x00_fdmi_register(vha);
cca5335c 4468
1da177e4 4469 /* Ensure we are logged into the SNS. */
e428924c 4470 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 4471 loop_id = NPH_SNS;
4472 else
4473 loop_id = SIMPLE_NAME_SERVER;
0b91d116
CD		 4474 rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff,
4475 0xfc, mb, BIT_1|BIT_0);
4476 if (rval != QLA_SUCCESS) {
4477 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
e452ceb6 4478 return rval;
0b91d116 4479 }
1da177e4 4480 if (mb[0] != MBS_COMMAND_COMPLETE) {
7c3df132
SK		 4481 ql_dbg(ql_dbg_disc, vha, 0x2042,
4482 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x "
4483 "mb[6]=%x mb[7]=%x.\n", loop_id, mb[0], mb[1],
4484 mb[2], mb[6], mb[7]);
1da177e4
LT		 4485 return (QLA_SUCCESS);
4486 }
4487
e315cd28
AC		 4488 if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) {
4489 if (qla2x00_rft_id(vha)) {
1da177e4 4490 /* EMPTY */
7c3df132
SK		 4491 ql_dbg(ql_dbg_disc, vha, 0x2045,
4492 "Register FC-4 TYPE failed.\n");
1da177e4 4493 }
e315cd28 4494 if (qla2x00_rff_id(vha)) {
1da177e4 4495 /* EMPTY */
7c3df132
SK		 4496 ql_dbg(ql_dbg_disc, vha, 0x2049,
4497 "Register FC-4 Features failed.\n");
1da177e4 4498 }
e315cd28 4499 if (qla2x00_rnn_id(vha)) {
1da177e4 4500 /* EMPTY */
7c3df132
SK		 4501 ql_dbg(ql_dbg_disc, vha, 0x204f,
4502 "Register Node Name failed.\n");
e315cd28 4503 } else if (qla2x00_rsnn_nn(vha)) {
1da177e4 4504 /* EMPTY */
7c3df132
SK		 4505 ql_dbg(ql_dbg_disc, vha, 0x2053,
4506 "Register Symobilic Node Name failed.\n");
1da177e4
LT		 4507 }
4508 }
4509
827210ba
JC		 4510 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4511 fcport->scan_state = QLA_FCPORT_SCAN;
4512 }
4513
df673274
AP		 4514 /* Mark the time right before querying FW for connected ports.
4515 * This process is long, asynchronous and by the time it's done,
4516 * collected information might not be accurate anymore. E.g.
4517 * disconnected port might have re-connected and a brand new
4518 * session has been created. In this case session's generation
4519 * will be newer than discovery_gen. */
4520 qlt_do_generation_tick(vha, &discovery_gen);
4521
726b8548 4522 rval = qla2x00_find_all_fabric_devs(vha);
1da177e4
LT		 4523 if (rval != QLA_SUCCESS)
4524 break;
1da177e4
LT		 4525 } while (0);
4526
726b8548 4527 if (rval)
7c3df132
SK		 4528 ql_dbg(ql_dbg_disc, vha, 0x2068,
4529 "Configure fabric error exit rval=%d.\n", rval);
1da177e4
LT		 4530
4531 return (rval);
4532}
4533
1da177e4
LT		 4534/*
4535 * qla2x00_find_all_fabric_devs
4536 *
4537 * Input:
4538 * ha = adapter block pointer.
4539 * dev = database device entry pointer.
4540 *
4541 * Returns:
4542 * 0 = success.
4543 *
4544 * Context:
4545 * Kernel context.
4546 */
4547static int
726b8548 4548qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha)
1da177e4
LT		 4549{
4550 int rval;
4551 uint16_t loop_id;
726b8548 4552 fc_port_t *fcport, *new_fcport;
1da177e4
LT		 4553 int found;
4554
4555 sw_info_t *swl;
4556 int swl_idx;
4557 int first_dev, last_dev;
1516ef44 4558 port_id_t wrap = {}, nxt_d_id;
e315cd28 4559 struct qla_hw_data *ha = vha->hw;
bb4cf5b7 4560 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
726b8548 4561 unsigned long flags;
1da177e4
LT		 4562
4563 rval = QLA_SUCCESS;
4564
4565 /* Try GID_PT to get device list, else GAN. */
7a67735b 4566 if (!ha->swl)
642ef983 4567 ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t),
7a67735b
AV		 4568 GFP_KERNEL);
4569 swl = ha->swl;
bbfbbbc1 4570 if (!swl) {
1da177e4 4571 /*EMPTY*/
7c3df132
SK		 4572 ql_dbg(ql_dbg_disc, vha, 0x2054,
4573 "GID_PT allocations failed, fallback on GA_NXT.\n");
1da177e4 4574 } else {
642ef983 4575 memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t));
e315cd28 4576 if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) {
1da177e4 4577 swl = NULL;
e315cd28 4578 } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 4579 swl = NULL;
e315cd28 4580 } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 4581 swl = NULL;
726b8548
QT		 4582 } else if (qla2x00_gfpn_id(vha, swl) != QLA_SUCCESS) {
4583 swl = NULL;
1da177e4 4584 }
e8c72ba5
CD		 4585
4586 /* If other queries succeeded probe for FC-4 type */
4587 if (swl)
4588 qla2x00_gff_id(vha, swl);
1da177e4
LT		 4589 }
4590 swl_idx = 0;
4591
4592 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 4593 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 4594 if (new_fcport == NULL) {
7c3df132
SK		 4595 ql_log(ql_log_warn, vha, 0x205e,
4596 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 4597 return (QLA_MEMORY_ALLOC_FAILED);
4598 }
4599 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
1da177e4
LT		 4600 /* Set start port ID scan at adapter ID. */
4601 first_dev = 1;
4602 last_dev = 0;
4603
4604 /* Starting free loop ID. */
e315cd28
AC		 4605 loop_id = ha->min_external_loopid;
4606 for (; loop_id <= ha->max_loop_id; loop_id++) {
4607 if (qla2x00_is_reserved_id(vha, loop_id))
1da177e4
LT		 4608 continue;
4609
3a6478df
GM		 4610 if (ha->current_topology == ISP_CFG_FL &&
4611 (atomic_read(&vha->loop_down_timer) ||
4612 LOOP_TRANSITION(vha))) {
bb2d52b2
AV		 4613 atomic_set(&vha->loop_down_timer, 0);
4614 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
4615 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
1da177e4 4616 break;
bb2d52b2 4617 }
1da177e4
LT		 4618
4619 if (swl != NULL) {
4620 if (last_dev) {
4621 wrap.b24 = new_fcport->d_id.b24;
4622 } else {
4623 new_fcport->d_id.b24 = swl[swl_idx].d_id.b24;
4624 memcpy(new_fcport->node_name,
4625 swl[swl_idx].node_name, WWN_SIZE);
4626 memcpy(new_fcport->port_name,
4627 swl[swl_idx].port_name, WWN_SIZE);
d8b45213
AV		 4628 memcpy(new_fcport->fabric_port_name,
4629 swl[swl_idx].fabric_port_name, WWN_SIZE);
4630 new_fcport->fp_speed = swl[swl_idx].fp_speed;
e8c72ba5 4631 new_fcport->fc4_type = swl[swl_idx].fc4_type;
1da177e4
LT		 4632
4633 if (swl[swl_idx].d_id.b.rsvd_1 != 0) {
4634 last_dev = 1;
4635 }
4636 swl_idx++;
4637 }
4638 } else {
4639 /* Send GA_NXT to the switch */
e315cd28 4640 rval = qla2x00_ga_nxt(vha, new_fcport);
1da177e4 4641 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4642 ql_log(ql_log_warn, vha, 0x2064,
4643 "SNS scan failed -- assuming "
4644 "zero-entry result.\n");
1da177e4
LT		 4645 rval = QLA_SUCCESS;
4646 break;
4647 }
4648 }
4649
4650 /* If wrap on switch device list, exit. */
4651 if (first_dev) {
4652 wrap.b24 = new_fcport->d_id.b24;
4653 first_dev = 0;
4654 } else if (new_fcport->d_id.b24 == wrap.b24) {
7c3df132
SK		 4655 ql_dbg(ql_dbg_disc, vha, 0x2065,
4656 "Device wrap (%02x%02x%02x).\n",
4657 new_fcport->d_id.b.domain,
4658 new_fcport->d_id.b.area,
4659 new_fcport->d_id.b.al_pa);
1da177e4
LT		 4660 break;
4661 }
4662
2c3dfe3f 4663 /* Bypass if same physical adapter. */
e315cd28 4664 if (new_fcport->d_id.b24 == base_vha->d_id.b24)
1da177e4
LT		 4665 continue;
4666
2c3dfe3f 4667 /* Bypass virtual ports of the same host. */
bb4cf5b7
CD		 4668 if (qla2x00_is_a_vp_did(vha, new_fcport->d_id.b24))
4669 continue;
2c3dfe3f 4670
f7d289f6
AV		 4671 /* Bypass if same domain and area of adapter. */
4672 if (((new_fcport->d_id.b24 & 0xffff00) ==
e315cd28 4673 (vha->d_id.b24 & 0xffff00)) && ha->current_topology ==
f7d289f6
AV		 4674 ISP_CFG_FL)
4675 continue;
4676
1da177e4
LT		 4677 /* Bypass reserved domain fields. */
4678 if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0)
4679 continue;
4680
e8c72ba5 4681 /* Bypass ports whose FCP-4 type is not FCP_SCSI */
4da26e16
CD		 4682 if (ql2xgffidenable &&
4683 (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI &&
4684 new_fcport->fc4_type != FC4_TYPE_UNKNOWN))
e8c72ba5
CD		 4685 continue;
4686
726b8548
QT		 4687 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
4688
1da177e4
LT		 4689 /* Locate matching device in database. */
4690 found = 0;
e315cd28 4691 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 4692 if (memcmp(new_fcport->port_name, fcport->port_name,
4693 WWN_SIZE))
4694 continue;
4695
827210ba 4696 fcport->scan_state = QLA_FCPORT_FOUND;
b3b02e6e 4697
1da177e4
LT		 4698 found++;
4699
d8b45213
AV		 4700 /* Update port state. */
4701 memcpy(fcport->fabric_port_name,
4702 new_fcport->fabric_port_name, WWN_SIZE);
4703 fcport->fp_speed = new_fcport->fp_speed;
4704
1da177e4 4705 /*
b2032fd5
RD		 4706 * If address the same and state FCS_ONLINE
4707 * (or in target mode), nothing changed.
1da177e4
LT		 4708 */
4709 if (fcport->d_id.b24 == new_fcport->d_id.b24 &&
b2032fd5 4710 (atomic_read(&fcport->state) == FCS_ONLINE ||
726b8548 4711 (vha->host->active_mode == MODE_TARGET))) {
1da177e4
LT		 4712 break;
4713 }
4714
4715 /*
4716 * If device was not a fabric device before.
4717 */
4718 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) {
4719 fcport->d_id.b24 = new_fcport->d_id.b24;
5f16b331 4720 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 4721 fcport->flags |= (FCF_FABRIC_DEVICE |
4722 FCF_LOGIN_NEEDED);
1da177e4
LT		 4723 break;
4724 }
4725
4726 /*
4727 * Port ID changed or device was marked to be updated;
4728 * Log it out if still logged in and mark it for
4729 * relogin later.
4730 */
726b8548 4731 if (qla_tgt_mode_enabled(base_vha)) {
b2032fd5
RD		 4732 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf080,
4733 "port changed FC ID, %8phC"
4734 " old %x:%x:%x (loop_id 0x%04x)-> new %x:%x:%x\n",
4735 fcport->port_name,
4736 fcport->d_id.b.domain,
4737 fcport->d_id.b.area,
4738 fcport->d_id.b.al_pa,
4739 fcport->loop_id,
4740 new_fcport->d_id.b.domain,
4741 new_fcport->d_id.b.area,
4742 new_fcport->d_id.b.al_pa);
4743 fcport->d_id.b24 = new_fcport->d_id.b24;
4744 break;
4745 }
4746
1da177e4
LT		 4747 fcport->d_id.b24 = new_fcport->d_id.b24;
4748 fcport->flags |= FCF_LOGIN_NEEDED;
1da177e4
LT		 4749 break;
4750 }
4751
726b8548
QT		 4752 if (found) {
4753 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1da177e4 4754 continue;
726b8548 4755 }
1da177e4 4756 /* If device was not in our fcports list, then add it. */
b2032fd5 4757 new_fcport->scan_state = QLA_FCPORT_FOUND;
726b8548
QT		 4758 list_add_tail(&new_fcport->list, &vha->vp_fcports);
4759
4760 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
4761
1da177e4
LT		 4762
4763 /* Allocate a new replacement fcport. */
4764 nxt_d_id.b24 = new_fcport->d_id.b24;
e315cd28 4765 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 4766 if (new_fcport == NULL) {
7c3df132
SK		 4767 ql_log(ql_log_warn, vha, 0x2066,
4768 "Memory allocation failed for fcport.\n");
1da177e4
LT		 4769 return (QLA_MEMORY_ALLOC_FAILED);
4770 }
4771 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
4772 new_fcport->d_id.b24 = nxt_d_id.b24;
4773 }
4774
726b8548
QT		 4775 qla2x00_free_fcport(new_fcport);
4776
4777 /*
4778 * Logout all previous fabric dev marked lost, except FCP2 devices.
4779 */
4780 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4781 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4782 break;
4783
4784 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0 ||
4785 (fcport->flags & FCF_LOGIN_NEEDED) == 0)
4786 continue;
4787
4788 if (fcport->scan_state == QLA_FCPORT_SCAN) {
4789 if ((qla_dual_mode_enabled(vha) ||
4790 qla_ini_mode_enabled(vha)) &&
4791 atomic_read(&fcport->state) == FCS_ONLINE) {
4792 qla2x00_mark_device_lost(vha, fcport,
4793 ql2xplogiabsentdevice, 0);
4794 if (fcport->loop_id != FC_NO_LOOP_ID &&
4795 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
4796 fcport->port_type != FCT_INITIATOR &&
4797 fcport->port_type != FCT_BROADCAST) {
4798 ql_dbg(ql_dbg_disc, vha, 0xffff,
4799 "%s %d %8phC post del sess\n",
4800 __func__, __LINE__,
4801 fcport->port_name);
4802
4803 qlt_schedule_sess_for_deletion_lock
4804 (fcport);
4805 continue;
4806 }
4807 }
4808 }
1da177e4 4809
726b8548
QT		 4810 if (fcport->scan_state == QLA_FCPORT_FOUND)
4811 qla24xx_fcport_handle_login(vha, fcport);
4812 }
1da177e4
LT		 4813 return (rval);
4814}
4815
4816/*
4817 * qla2x00_find_new_loop_id
4818 * Scan through our port list and find a new usable loop ID.
4819 *
4820 * Input:
4821 * ha: adapter state pointer.
4822 * dev: port structure pointer.
4823 *
4824 * Returns:
4825 * qla2x00 local function return status code.
4826 *
4827 * Context:
4828 * Kernel context.
4829 */
03bcfb57 4830int
e315cd28 4831qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
1da177e4
LT		 4832{
4833 int rval;
e315cd28 4834 struct qla_hw_data *ha = vha->hw;
feafb7b1 4835 unsigned long flags = 0;
1da177e4
LT		 4836
4837 rval = QLA_SUCCESS;
4838
5f16b331 4839 spin_lock_irqsave(&ha->vport_slock, flags);
1da177e4 4840
5f16b331
CD		 4841 dev->loop_id = find_first_zero_bit(ha->loop_id_map,
4842 LOOPID_MAP_SIZE);
4843 if (dev->loop_id >= LOOPID_MAP_SIZE ||
4844 qla2x00_is_reserved_id(vha, dev->loop_id)) {
4845 dev->loop_id = FC_NO_LOOP_ID;
4846 rval = QLA_FUNCTION_FAILED;
4847 } else
4848 set_bit(dev->loop_id, ha->loop_id_map);
1da177e4 4849
5f16b331 4850 spin_unlock_irqrestore(&ha->vport_slock, flags);
1da177e4 4851
5f16b331
CD		 4852 if (rval == QLA_SUCCESS)
4853 ql_dbg(ql_dbg_disc, dev->vha, 0x2086,
4854 "Assigning new loopid=%x, portid=%x.\n",
4855 dev->loop_id, dev->d_id.b24);
4856 else
4857 ql_log(ql_log_warn, dev->vha, 0x2087,
4858 "No loop_id's available, portid=%x.\n",
4859 dev->d_id.b24);
1da177e4
LT		 4860
4861 return (rval);
4862}
4863
1da177e4
LT		 4864
4865/*
4866 * qla2x00_fabric_login
4867 * Issue fabric login command.
4868 *
4869 * Input:
4870 * ha = adapter block pointer.
4871 * device = pointer to FC device type structure.
4872 *
4873 * Returns:
4874 * 0 - Login successfully
4875 * 1 - Login failed
4876 * 2 - Initiator device
4877 * 3 - Fatal error
4878 */
4879int
e315cd28 4880qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 4881 uint16_t *next_loopid)
4882{
4883 int rval;
4884 int retry;
4885 uint16_t tmp_loopid;
4886 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 4887 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 4888
4889 retry = 0;
4890 tmp_loopid = 0;
4891
4892 for (;;) {
7c3df132
SK		 4893 ql_dbg(ql_dbg_disc, vha, 0x2000,
4894 "Trying Fabric Login w/loop id 0x%04x for port "
4895 "%02x%02x%02x.\n",
4896 fcport->loop_id, fcport->d_id.b.domain,
4897 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 4898
4899 /* Login fcport on switch. */
0b91d116 4900 rval = ha->isp_ops->fabric_login(vha, fcport->loop_id,
1da177e4
LT		 4901 fcport->d_id.b.domain, fcport->d_id.b.area,
4902 fcport->d_id.b.al_pa, mb, BIT_0);
0b91d116
CD		 4903 if (rval != QLA_SUCCESS) {
4904 return rval;
4905 }
1da177e4
LT		 4906 if (mb[0] == MBS_PORT_ID_USED) {
4907 /*
4908 * Device has another loop ID. The firmware team
0107109e
AV		 4909 * recommends the driver perform an implicit login with
4910 * the specified ID again. The ID we just used is save
4911 * here so we return with an ID that can be tried by
4912 * the next login.
1da177e4
LT		 4913 */
4914 retry++;
4915 tmp_loopid = fcport->loop_id;
4916 fcport->loop_id = mb[1];
4917
7c3df132
SK		 4918 ql_dbg(ql_dbg_disc, vha, 0x2001,
4919 "Fabric Login: port in use - next loop "
4920 "id=0x%04x, port id= %02x%02x%02x.\n",
1da177e4 4921 fcport->loop_id, fcport->d_id.b.domain,
7c3df132 4922 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 4923
4924 } else if (mb[0] == MBS_COMMAND_COMPLETE) {
4925 /*
4926 * Login succeeded.
4927 */
4928 if (retry) {
4929 /* A retry occurred before. */
4930 *next_loopid = tmp_loopid;
4931 } else {
4932 /*
4933 * No retry occurred before. Just increment the
4934 * ID value for next login.
4935 */
4936 *next_loopid = (fcport->loop_id + 1);
4937 }
4938
4939 if (mb[1] & BIT_0) {
4940 fcport->port_type = FCT_INITIATOR;
4941 } else {
4942 fcport->port_type = FCT_TARGET;
4943 if (mb[1] & BIT_1) {
8474f3a0 4944 fcport->flags |= FCF_FCP2_DEVICE;
1da177e4
LT		 4945 }
4946 }
4947
ad3e0eda
AV		 4948 if (mb[10] & BIT_0)
4949 fcport->supported_classes |= FC_COS_CLASS2;
4950 if (mb[10] & BIT_1)
4951 fcport->supported_classes |= FC_COS_CLASS3;
4952
2d70c103
NB		 4953 if (IS_FWI2_CAPABLE(ha)) {
4954 if (mb[10] & BIT_7)
4955 fcport->flags |=
4956 FCF_CONF_COMP_SUPPORTED;
4957 }
4958
1da177e4
LT		 4959 rval = QLA_SUCCESS;
4960 break;
4961 } else if (mb[0] == MBS_LOOP_ID_USED) {
4962 /*
4963 * Loop ID already used, try next loop ID.
4964 */
4965 fcport->loop_id++;
e315cd28 4966 rval = qla2x00_find_new_loop_id(vha, fcport);
1da177e4
LT		 4967 if (rval != QLA_SUCCESS) {
4968 /* Ran out of loop IDs to use */
4969 break;
4970 }
4971 } else if (mb[0] == MBS_COMMAND_ERROR) {
4972 /*
4973 * Firmware possibly timed out during login. If NO
4974 * retries are left to do then the device is declared
4975 * dead.
4976 */
4977 *next_loopid = fcport->loop_id;
e315cd28 4978 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 4979 fcport->d_id.b.domain, fcport->d_id.b.area,
4980 fcport->d_id.b.al_pa);
e315cd28 4981 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 4982
4983 rval = 1;
4984 break;
4985 } else {
4986 /*
4987 * unrecoverable / not handled error
4988 */
7c3df132
SK		 4989 ql_dbg(ql_dbg_disc, vha, 0x2002,
4990 "Failed=%x port_id=%02x%02x%02x loop_id=%x "
4991 "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain,
4992 fcport->d_id.b.area, fcport->d_id.b.al_pa,
4993 fcport->loop_id, jiffies);
1da177e4
LT		 4994
4995 *next_loopid = fcport->loop_id;
e315cd28 4996 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 4997 fcport->d_id.b.domain, fcport->d_id.b.area,
4998 fcport->d_id.b.al_pa);
5f16b331 4999 qla2x00_clear_loop_id(fcport);
0eedfcf0 5000 fcport->login_retry = 0;
1da177e4
LT		 5001
5002 rval = 3;
5003 break;
5004 }
5005 }
5006
5007 return (rval);
5008}
5009
5010/*
5011 * qla2x00_local_device_login
5012 * Issue local device login command.
5013 *
5014 * Input:
5015 * ha = adapter block pointer.
5016 * loop_id = loop id of device to login to.
5017 *
5018 * Returns (Where's the #define!!!!):
5019 * 0 - Login successfully
5020 * 1 - Login failed
5021 * 3 - Fatal error
5022 */
5023int
e315cd28 5024qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport)
1da177e4
LT		 5025{
5026 int rval;
5027 uint16_t mb[MAILBOX_REGISTER_COUNT];
5028
5029 memset(mb, 0, sizeof(mb));
e315cd28 5030 rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0);
1da177e4
LT		 5031 if (rval == QLA_SUCCESS) {
5032 /* Interrogate mailbox registers for any errors */
5033 if (mb[0] == MBS_COMMAND_ERROR)
5034 rval = 1;
5035 else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR)
5036 /* device not in PCB table */
5037 rval = 3;
5038 }
5039
5040 return (rval);
5041}
5042
5043/*
5044 * qla2x00_loop_resync
5045 * Resync with fibre channel devices.
5046 *
5047 * Input:
5048 * ha = adapter block pointer.
5049 *
5050 * Returns:
5051 * 0 = success
5052 */
5053int
e315cd28 5054qla2x00_loop_resync(scsi_qla_host_t *vha)
1da177e4 5055{
73208dfd 5056 int rval = QLA_SUCCESS;
1da177e4 5057 uint32_t wait_time;
67c2e93a
AC		 5058 struct req_que *req;
5059 struct rsp_que *rsp;
5060
d7459527 5061 req = vha->req;
67c2e93a 5062 rsp = req->rsp;
1da177e4 5063
e315cd28
AC		 5064 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
5065 if (vha->flags.online) {
5066 if (!(rval = qla2x00_fw_ready(vha))) {
1da177e4
LT		 5067 /* Wait at most MAX_TARGET RSCNs for a stable link. */
5068 wait_time = 256;
5069 do {
8ae6d9c7
GM		 5070 if (!IS_QLAFX00(vha->hw)) {
5071 /*
5072 * Issue a marker after FW becomes
5073 * ready.
5074 */
5075 qla2x00_marker(vha, req, rsp, 0, 0,
5076 MK_SYNC_ALL);
5077 vha->marker_needed = 0;
5078 }
1da177e4
LT		 5079
5080 /* Remap devices on Loop. */
e315cd28 5081 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4 5082
8ae6d9c7
GM		 5083 if (IS_QLAFX00(vha->hw))
5084 qlafx00_configure_devices(vha);
5085 else
5086 qla2x00_configure_loop(vha);
5087
1da177e4 5088 wait_time--;
e315cd28
AC		 5089 } while (!atomic_read(&vha->loop_down_timer) &&
5090 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
5091 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
5092 &vha->dpc_flags)));
1da177e4 5093 }
1da177e4
LT		 5094 }
5095
e315cd28 5096 if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
1da177e4 5097 return (QLA_FUNCTION_FAILED);
1da177e4 5098
e315cd28 5099 if (rval)
7c3df132
SK		 5100 ql_dbg(ql_dbg_disc, vha, 0x206c,
5101 "%s *** FAILED ***.\n", __func__);
1da177e4
LT		 5102
5103 return (rval);
5104}
5105
579d12b5
SK		 5106/*
5107* qla2x00_perform_loop_resync
5108* Description: This function will set the appropriate flags and call
5109* qla2x00_loop_resync. If successful loop will be resynced
5110* Arguments : scsi_qla_host_t pointer
5111* returm : Success or Failure
5112*/
5113
5114int qla2x00_perform_loop_resync(scsi_qla_host_t *ha)
5115{
5116 int32_t rval = 0;
5117
5118 if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) {
5119 /*Configure the flags so that resync happens properly*/
5120 atomic_set(&ha->loop_down_timer, 0);
5121 if (!(ha->device_flags & DFLG_NO_CABLE)) {
5122 atomic_set(&ha->loop_state, LOOP_UP);
5123 set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags);
5124 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
5125 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
5126
5127 rval = qla2x00_loop_resync(ha);
5128 } else
5129 atomic_set(&ha->loop_state, LOOP_DEAD);
5130
5131 clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags);
5132 }
5133
5134 return rval;
5135}
5136
d97994dc 5137void
67becc00 5138qla2x00_update_fcports(scsi_qla_host_t *base_vha)
d97994dc
AV		 5139{
5140 fc_port_t *fcport;
feafb7b1
AE		 5141 struct scsi_qla_host *vha;
5142 struct qla_hw_data *ha = base_vha->hw;
5143 unsigned long flags;
d97994dc 5144
feafb7b1 5145 spin_lock_irqsave(&ha->vport_slock, flags);
d97994dc 5146 /* Go with deferred removal of rport references. */
feafb7b1
AE		 5147 list_for_each_entry(vha, &base_vha->hw->vp_list, list) {
5148 atomic_inc(&vha->vref_count);
5149 list_for_each_entry(fcport, &vha->vp_fcports, list) {
8ae598d0 5150 if (fcport->drport &&
feafb7b1
AE		 5151 atomic_read(&fcport->state) != FCS_UNCONFIGURED) {
5152 spin_unlock_irqrestore(&ha->vport_slock, flags);
67becc00 5153 qla2x00_rport_del(fcport);
df673274 5154
feafb7b1
AE		 5155 spin_lock_irqsave(&ha->vport_slock, flags);
5156 }
5157 }
5158 atomic_dec(&vha->vref_count);
c4a9b538 5159 wake_up(&vha->vref_waitq);
feafb7b1
AE		 5160 }
5161 spin_unlock_irqrestore(&ha->vport_slock, flags);
d97994dc
AV		 5162}
5163
7d613ac6
SV		 5164/* Assumes idc_lock always held on entry */
5165void
5166qla83xx_reset_ownership(scsi_qla_host_t *vha)
5167{
5168 struct qla_hw_data *ha = vha->hw;
5169 uint32_t drv_presence, drv_presence_mask;
5170 uint32_t dev_part_info1, dev_part_info2, class_type;
5171 uint32_t class_type_mask = 0x3;
5172 uint16_t fcoe_other_function = 0xffff, i;
5173
7ec0effd
AD		 5174 if (IS_QLA8044(ha)) {
5175 drv_presence = qla8044_rd_direct(vha,
5176 QLA8044_CRB_DRV_ACTIVE_INDEX);
5177 dev_part_info1 = qla8044_rd_direct(vha,
5178 QLA8044_CRB_DEV_PART_INFO_INDEX);
5179 dev_part_info2 = qla8044_rd_direct(vha,
5180 QLA8044_CRB_DEV_PART_INFO2);
5181 } else {
5182 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5183 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1);
5184 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2);
5185 }
7d613ac6
SV		 5186 for (i = 0; i < 8; i++) {
5187 class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask);
5188 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
5189 (i != ha->portnum)) {
5190 fcoe_other_function = i;
5191 break;
5192 }
5193 }
5194 if (fcoe_other_function == 0xffff) {
5195 for (i = 0; i < 8; i++) {
5196 class_type = ((dev_part_info2 >> (i * 4)) &
5197 class_type_mask);
5198 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
5199 ((i + 8) != ha->portnum)) {
5200 fcoe_other_function = i + 8;
5201 break;
5202 }
5203 }
5204 }
5205 /*
5206 * Prepare drv-presence mask based on fcoe functions present.
5207 * However consider only valid physical fcoe function numbers (0-15).
5208 */
5209 drv_presence_mask = ~((1 << (ha->portnum)) |
5210 ((fcoe_other_function == 0xffff) ?
5211 0 : (1 << (fcoe_other_function))));
5212
5213 /* We are the reset owner iff:
5214 * - No other protocol drivers present.
5215 * - This is the lowest among fcoe functions. */
5216 if (!(drv_presence & drv_presence_mask) &&
5217 (ha->portnum < fcoe_other_function)) {
5218 ql_dbg(ql_dbg_p3p, vha, 0xb07f,
5219 "This host is Reset owner.\n");
5220 ha->flags.nic_core_reset_owner = 1;
5221 }
5222}
5223
fa492630 5224static int
7d613ac6
SV		 5225__qla83xx_set_drv_ack(scsi_qla_host_t *vha)
5226{
5227 int rval = QLA_SUCCESS;
5228 struct qla_hw_data *ha = vha->hw;
5229 uint32_t drv_ack;
5230
5231 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
5232 if (rval == QLA_SUCCESS) {
5233 drv_ack |= (1 << ha->portnum);
5234 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
5235 }
5236
5237 return rval;
5238}
5239
fa492630 5240static int
7d613ac6
SV		 5241__qla83xx_clear_drv_ack(scsi_qla_host_t *vha)
5242{
5243 int rval = QLA_SUCCESS;
5244 struct qla_hw_data *ha = vha->hw;
5245 uint32_t drv_ack;
5246
5247 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
5248 if (rval == QLA_SUCCESS) {
5249 drv_ack &= ~(1 << ha->portnum);
5250 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
5251 }
5252
5253 return rval;
5254}
5255
fa492630 5256static const char *
7d613ac6
SV		 5257qla83xx_dev_state_to_string(uint32_t dev_state)
5258{
5259 switch (dev_state) {
5260 case QLA8XXX_DEV_COLD:
5261 return "COLD/RE-INIT";
5262 case QLA8XXX_DEV_INITIALIZING:
5263 return "INITIALIZING";
5264 case QLA8XXX_DEV_READY:
5265 return "READY";
5266 case QLA8XXX_DEV_NEED_RESET:
5267 return "NEED RESET";
5268 case QLA8XXX_DEV_NEED_QUIESCENT:
5269 return "NEED QUIESCENT";
5270 case QLA8XXX_DEV_FAILED:
5271 return "FAILED";
5272 case QLA8XXX_DEV_QUIESCENT:
5273 return "QUIESCENT";
5274 default:
5275 return "Unknown";
5276 }
5277}
5278
5279/* Assumes idc-lock always held on entry */
5280void
5281qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type)
5282{
5283 struct qla_hw_data *ha = vha->hw;
5284 uint32_t idc_audit_reg = 0, duration_secs = 0;
5285
5286 switch (audit_type) {
5287 case IDC_AUDIT_TIMESTAMP:
5288 ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000);
5289 idc_audit_reg = (ha->portnum) |
5290 (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8);
5291 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
5292 break;
5293
5294 case IDC_AUDIT_COMPLETION:
5295 duration_secs = ((jiffies_to_msecs(jiffies) -
5296 jiffies_to_msecs(ha->idc_audit_ts)) / 1000);
5297 idc_audit_reg = (ha->portnum) |
5298 (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8);
5299 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
5300 break;
5301
5302 default:
5303 ql_log(ql_log_warn, vha, 0xb078,
5304 "Invalid audit type specified.\n");
5305 break;
5306 }
5307}
5308
5309/* Assumes idc_lock always held on entry */
fa492630 5310static int
7d613ac6
SV		 5311qla83xx_initiating_reset(scsi_qla_host_t *vha)
5312{
5313 struct qla_hw_data *ha = vha->hw;
5314 uint32_t idc_control, dev_state;
5315
5316 __qla83xx_get_idc_control(vha, &idc_control);
5317 if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) {
5318 ql_log(ql_log_info, vha, 0xb080,
5319 "NIC Core reset has been disabled. idc-control=0x%x\n",
5320 idc_control);
5321 return QLA_FUNCTION_FAILED;
5322 }
5323
5324 /* Set NEED-RESET iff in READY state and we are the reset-owner */
5325 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5326 if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) {
5327 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
5328 QLA8XXX_DEV_NEED_RESET);
5329 ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n");
5330 qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP);
5331 } else {
5332 const char *state = qla83xx_dev_state_to_string(dev_state);
5333 ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n", state);
5334
5335 /* SV: XXX: Is timeout required here? */
5336 /* Wait for IDC state change READY -> NEED_RESET */
5337 while (dev_state == QLA8XXX_DEV_READY) {
5338 qla83xx_idc_unlock(vha, 0);
5339 msleep(200);
5340 qla83xx_idc_lock(vha, 0);
5341 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5342 }
5343 }
5344
5345 /* Send IDC ack by writing to drv-ack register */
5346 __qla83xx_set_drv_ack(vha);
5347
5348 return QLA_SUCCESS;
5349}
5350
5351int
5352__qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control)
5353{
5354 return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
5355}
5356
7d613ac6
SV		 5357int
5358__qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control)
5359{
5360 return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
5361}
5362
fa492630 5363static int
7d613ac6
SV		 5364qla83xx_check_driver_presence(scsi_qla_host_t *vha)
5365{
5366 uint32_t drv_presence = 0;
5367 struct qla_hw_data *ha = vha->hw;
5368
5369 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5370 if (drv_presence & (1 << ha->portnum))
5371 return QLA_SUCCESS;
5372 else
5373 return QLA_TEST_FAILED;
5374}
5375
5376int
5377qla83xx_nic_core_reset(scsi_qla_host_t *vha)
5378{
5379 int rval = QLA_SUCCESS;
5380 struct qla_hw_data *ha = vha->hw;
5381
5382 ql_dbg(ql_dbg_p3p, vha, 0xb058,
5383 "Entered %s().\n", __func__);
5384
5385 if (vha->device_flags & DFLG_DEV_FAILED) {
5386 ql_log(ql_log_warn, vha, 0xb059,
5387 "Device in unrecoverable FAILED state.\n");
5388 return QLA_FUNCTION_FAILED;
5389 }
5390
5391 qla83xx_idc_lock(vha, 0);
5392
5393 if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) {
5394 ql_log(ql_log_warn, vha, 0xb05a,
5395 "Function=0x%x has been removed from IDC participation.\n",
5396 ha->portnum);
5397 rval = QLA_FUNCTION_FAILED;
5398 goto exit;
5399 }
5400
5401 qla83xx_reset_ownership(vha);
5402
5403 rval = qla83xx_initiating_reset(vha);
5404
5405 /*
5406 * Perform reset if we are the reset-owner,
5407 * else wait till IDC state changes to READY/FAILED.
5408 */
5409 if (rval == QLA_SUCCESS) {
5410 rval = qla83xx_idc_state_handler(vha);
5411
5412 if (rval == QLA_SUCCESS)
5413 ha->flags.nic_core_hung = 0;
5414 __qla83xx_clear_drv_ack(vha);
5415 }
5416
5417exit:
5418 qla83xx_idc_unlock(vha, 0);
5419
5420 ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__);
5421
5422 return rval;
5423}
5424
81178772
SK		 5425int
5426qla2xxx_mctp_dump(scsi_qla_host_t *vha)
5427{
5428 struct qla_hw_data *ha = vha->hw;
5429 int rval = QLA_FUNCTION_FAILED;
5430
5431 if (!IS_MCTP_CAPABLE(ha)) {
5432 /* This message can be removed from the final version */
5433 ql_log(ql_log_info, vha, 0x506d,
5434 "This board is not MCTP capable\n");
5435 return rval;
5436 }
5437
5438 if (!ha->mctp_dump) {
5439 ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev,
5440 MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL);
5441
5442 if (!ha->mctp_dump) {
5443 ql_log(ql_log_warn, vha, 0x506e,
5444 "Failed to allocate memory for mctp dump\n");
5445 return rval;
5446 }
5447 }
5448
5449#define MCTP_DUMP_STR_ADDR 0x00000000
5450 rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma,
5451 MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4);
5452 if (rval != QLA_SUCCESS) {
5453 ql_log(ql_log_warn, vha, 0x506f,
5454 "Failed to capture mctp dump\n");
5455 } else {
5456 ql_log(ql_log_info, vha, 0x5070,
5457 "Mctp dump capture for host (%ld/%p).\n",
5458 vha->host_no, ha->mctp_dump);
5459 ha->mctp_dumped = 1;
5460 }
5461
409ee0fe 5462 if (!ha->flags.nic_core_reset_hdlr_active && !ha->portnum) {
81178772
SK		 5463 ha->flags.nic_core_reset_hdlr_active = 1;
5464 rval = qla83xx_restart_nic_firmware(vha);
5465 if (rval)
5466 /* NIC Core reset failed. */
5467 ql_log(ql_log_warn, vha, 0x5071,
5468 "Failed to restart nic firmware\n");
5469 else
5470 ql_dbg(ql_dbg_p3p, vha, 0xb084,
5471 "Restarted NIC firmware successfully.\n");
5472 ha->flags.nic_core_reset_hdlr_active = 0;
5473 }
5474
5475 return rval;
5476
5477}
5478
579d12b5 5479/*
8fcd6b8b 5480* qla2x00_quiesce_io
579d12b5
SK		 5481* Description: This function will block the new I/Os
5482* Its not aborting any I/Os as context
5483* is not destroyed during quiescence
5484* Arguments: scsi_qla_host_t
5485* return : void
5486*/
5487void
8fcd6b8b 5488qla2x00_quiesce_io(scsi_qla_host_t *vha)
579d12b5
SK		 5489{
5490 struct qla_hw_data *ha = vha->hw;
5491 struct scsi_qla_host *vp;
5492
8fcd6b8b
CD		 5493 ql_dbg(ql_dbg_dpc, vha, 0x401d,
5494 "Quiescing I/O - ha=%p.\n", ha);
579d12b5
SK		 5495
5496 atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME);
5497 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
5498 atomic_set(&vha->loop_state, LOOP_DOWN);
5499 qla2x00_mark_all_devices_lost(vha, 0);
5500 list_for_each_entry(vp, &ha->vp_list, list)
8fcd6b8b 5501 qla2x00_mark_all_devices_lost(vp, 0);
579d12b5
SK		 5502 } else {
5503 if (!atomic_read(&vha->loop_down_timer))
5504 atomic_set(&vha->loop_down_timer,
5505 LOOP_DOWN_TIME);
5506 }
5507 /* Wait for pending cmds to complete */
5508 qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST);
5509}
5510
a9083016
GM		 5511void
5512qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
5513{
5514 struct qla_hw_data *ha = vha->hw;
579d12b5 5515 struct scsi_qla_host *vp;
feafb7b1 5516 unsigned long flags;
6aef87be 5517 fc_port_t *fcport;
a9083016 5518
e46ef004
SK		 5519 /* For ISP82XX, driver waits for completion of the commands.
5520 * online flag should be set.
5521 */
7ec0effd 5522 if (!(IS_P3P_TYPE(ha)))
e46ef004 5523 vha->flags.online = 0;
a9083016
GM		 5524 ha->flags.chip_reset_done = 0;
5525 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2be21fa2 5526 vha->qla_stats.total_isp_aborts++;
a9083016 5527
7c3df132
SK		 5528 ql_log(ql_log_info, vha, 0x00af,
5529 "Performing ISP error recovery - ha=%p.\n", ha);
a9083016 5530
e46ef004
SK		 5531 /* For ISP82XX, reset_chip is just disabling interrupts.
5532 * Driver waits for the completion of the commands.
5533 * the interrupts need to be enabled.
5534 */
7ec0effd 5535 if (!(IS_P3P_TYPE(ha)))
a9083016
GM		 5536 ha->isp_ops->reset_chip(vha);
5537
726b8548
QT		 5538 ha->chip_reset++;
5539
a9083016
GM		 5540 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
5541 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
5542 atomic_set(&vha->loop_state, LOOP_DOWN);
5543 qla2x00_mark_all_devices_lost(vha, 0);
feafb7b1
AE		 5544
5545 spin_lock_irqsave(&ha->vport_slock, flags);
579d12b5 5546 list_for_each_entry(vp, &ha->vp_list, list) {
feafb7b1
AE		 5547 atomic_inc(&vp->vref_count);
5548 spin_unlock_irqrestore(&ha->vport_slock, flags);
5549
a9083016 5550 qla2x00_mark_all_devices_lost(vp, 0);
feafb7b1
AE		 5551
5552 spin_lock_irqsave(&ha->vport_slock, flags);
5553 atomic_dec(&vp->vref_count);
5554 }
5555 spin_unlock_irqrestore(&ha->vport_slock, flags);
a9083016
GM		 5556 } else {
5557 if (!atomic_read(&vha->loop_down_timer))
5558 atomic_set(&vha->loop_down_timer,
5559 LOOP_DOWN_TIME);
5560 }
5561
6aef87be
AV		 5562 /* Clear all async request states across all VPs. */
5563 list_for_each_entry(fcport, &vha->vp_fcports, list)
5564 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
5565 spin_lock_irqsave(&ha->vport_slock, flags);
5566 list_for_each_entry(vp, &ha->vp_list, list) {
5567 atomic_inc(&vp->vref_count);
5568 spin_unlock_irqrestore(&ha->vport_slock, flags);
5569
5570 list_for_each_entry(fcport, &vp->vp_fcports, list)
5571 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
5572
5573 spin_lock_irqsave(&ha->vport_slock, flags);
5574 atomic_dec(&vp->vref_count);
5575 }
5576 spin_unlock_irqrestore(&ha->vport_slock, flags);
5577
bddd2d65
LC		 5578 if (!ha->flags.eeh_busy) {
5579 /* Make sure for ISP 82XX IO DMA is complete */
7ec0effd 5580 if (IS_P3P_TYPE(ha)) {
7190575f 5581 qla82xx_chip_reset_cleanup(vha);
7c3df132
SK		 5582 ql_log(ql_log_info, vha, 0x00b4,
5583 "Done chip reset cleanup.\n");
a9083016 5584
e46ef004
SK		 5585 /* Done waiting for pending commands.
5586 * Reset the online flag.
5587 */
5588 vha->flags.online = 0;
4d78c973 5589 }
a9083016 5590
bddd2d65
LC		 5591 /* Requeue all commands in outstanding command list. */
5592 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
5593 }
b6a029e1
AE		 5594 /* memory barrier */
5595 wmb();
a9083016
GM		 5596}
5597
1da177e4
LT		 5598/*
5599* qla2x00_abort_isp
5600* Resets ISP and aborts all outstanding commands.
5601*
5602* Input:
5603* ha = adapter block pointer.
5604*
5605* Returns:
5606* 0 = success
5607*/
5608int
e315cd28 5609qla2x00_abort_isp(scsi_qla_host_t *vha)
1da177e4 5610{
476e8978 5611 int rval;
1da177e4 5612 uint8_t status = 0;
e315cd28
AC		 5613 struct qla_hw_data *ha = vha->hw;
5614 struct scsi_qla_host *vp;
73208dfd 5615 struct req_que *req = ha->req_q_map[0];
feafb7b1 5616 unsigned long flags;
1da177e4 5617
e315cd28 5618 if (vha->flags.online) {
a9083016 5619 qla2x00_abort_isp_cleanup(vha);
1da177e4 5620
a6171297
SV		 5621 if (IS_QLA8031(ha)) {
5622 ql_dbg(ql_dbg_p3p, vha, 0xb05c,
5623 "Clearing fcoe driver presence.\n");
5624 if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS)
5625 ql_dbg(ql_dbg_p3p, vha, 0xb073,
5626 "Error while clearing DRV-Presence.\n");
5627 }
5628
85880801
AV		 5629 if (unlikely(pci_channel_offline(ha->pdev) &&
5630 ha->flags.pci_channel_io_perm_failure)) {
5631 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
5632 status = 0;
5633 return status;
5634 }
5635
73208dfd 5636 ha->isp_ops->get_flash_version(vha, req->ring);
30c47662 5637
e315cd28 5638 ha->isp_ops->nvram_config(vha);
1da177e4 5639
e315cd28
AC		 5640 if (!qla2x00_restart_isp(vha)) {
5641 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4 5642
e315cd28 5643 if (!atomic_read(&vha->loop_down_timer)) {
1da177e4
LT		 5644 /*
5645 * Issue marker command only when we are going
5646 * to start the I/O .
5647 */
e315cd28 5648 vha->marker_needed = 1;
1da177e4
LT		 5649 }
5650
e315cd28 5651 vha->flags.online = 1;
1da177e4 5652
fd34f556 5653 ha->isp_ops->enable_intrs(ha);
1da177e4 5654
fa2a1ce5 5655 ha->isp_abort_cnt = 0;
e315cd28 5656 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
476e8978 5657
6246b8a1
GM		 5658 if (IS_QLA81XX(ha) || IS_QLA8031(ha))
5659 qla2x00_get_fw_version(vha);
df613b96
AV		 5660 if (ha->fce) {
5661 ha->flags.fce_enabled = 1;
5662 memset(ha->fce, 0,
5663 fce_calc_size(ha->fce_bufs));
e315cd28 5664 rval = qla2x00_enable_fce_trace(vha,
df613b96
AV		 5665 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
5666 &ha->fce_bufs);
5667 if (rval) {
7c3df132 5668 ql_log(ql_log_warn, vha, 0x8033,
df613b96
AV		 5669 "Unable to reinitialize FCE "
5670 "(%d).\n", rval);
5671 ha->flags.fce_enabled = 0;
5672 }
5673 }
436a7b11
AV		 5674
5675 if (ha->eft) {
5676 memset(ha->eft, 0, EFT_SIZE);
e315cd28 5677 rval = qla2x00_enable_eft_trace(vha,
436a7b11
AV		 5678 ha->eft_dma, EFT_NUM_BUFFERS);
5679 if (rval) {
7c3df132 5680 ql_log(ql_log_warn, vha, 0x8034,
436a7b11
AV		 5681 "Unable to reinitialize EFT "
5682 "(%d).\n", rval);
5683 }
5684 }
1da177e4 5685 } else { /* failed the ISP abort */
e315cd28
AC		 5686 vha->flags.online = 1;
5687 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
1da177e4 5688 if (ha->isp_abort_cnt == 0) {
7c3df132
SK		 5689 ql_log(ql_log_fatal, vha, 0x8035,
5690 "ISP error recover failed - "
5691 "board disabled.\n");
fa2a1ce5 5692 /*
1da177e4
LT		 5693 * The next call disables the board
5694 * completely.
5695 */
e315cd28
AC		 5696 ha->isp_ops->reset_adapter(vha);
5697 vha->flags.online = 0;
1da177e4 5698 clear_bit(ISP_ABORT_RETRY,
e315cd28 5699 &vha->dpc_flags);
1da177e4
LT		 5700 status = 0;
5701 } else { /* schedule another ISP abort */
5702 ha->isp_abort_cnt--;
7c3df132
SK		 5703 ql_dbg(ql_dbg_taskm, vha, 0x8020,
5704 "ISP abort - retry remaining %d.\n",
5705 ha->isp_abort_cnt);
1da177e4
LT		 5706 status = 1;
5707 }
5708 } else {
5709 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
7c3df132
SK		 5710 ql_dbg(ql_dbg_taskm, vha, 0x8021,
5711 "ISP error recovery - retrying (%d) "
5712 "more times.\n", ha->isp_abort_cnt);
e315cd28 5713 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
1da177e4
LT		 5714 status = 1;
5715 }
5716 }
fa2a1ce5 5717
1da177e4
LT		 5718 }
5719
e315cd28 5720 if (!status) {
7c3df132 5721 ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__);
feafb7b1
AE		 5722
5723 spin_lock_irqsave(&ha->vport_slock, flags);
5724 list_for_each_entry(vp, &ha->vp_list, list) {
5725 if (vp->vp_idx) {
5726 atomic_inc(&vp->vref_count);
5727 spin_unlock_irqrestore(&ha->vport_slock, flags);
5728
e315cd28 5729 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 5730
5731 spin_lock_irqsave(&ha->vport_slock, flags);
5732 atomic_dec(&vp->vref_count);
5733 }
e315cd28 5734 }
feafb7b1
AE		 5735 spin_unlock_irqrestore(&ha->vport_slock, flags);
5736
7d613ac6
SV		 5737 if (IS_QLA8031(ha)) {
5738 ql_dbg(ql_dbg_p3p, vha, 0xb05d,
5739 "Setting back fcoe driver presence.\n");
5740 if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS)
5741 ql_dbg(ql_dbg_p3p, vha, 0xb074,
5742 "Error while setting DRV-Presence.\n");
5743 }
e315cd28 5744 } else {
d8424f68
JP		 5745 ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n",
5746 __func__);
1da177e4
LT		 5747 }
5748
5749 return(status);
5750}
5751
5752/*
5753* qla2x00_restart_isp
5754* restarts the ISP after a reset
5755*
5756* Input:
5757* ha = adapter block pointer.
5758*
5759* Returns:
5760* 0 = success
5761*/
5762static int
e315cd28 5763qla2x00_restart_isp(scsi_qla_host_t *vha)
1da177e4 5764{
c6b2fca8 5765 int status = 0;
e315cd28 5766 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 5767 struct req_que *req = ha->req_q_map[0];
5768 struct rsp_que *rsp = ha->rsp_q_map[0];
1da177e4
LT		 5769
5770 /* If firmware needs to be loaded */
e315cd28
AC		 5771 if (qla2x00_isp_firmware(vha)) {
5772 vha->flags.online = 0;
5773 status = ha->isp_ops->chip_diag(vha);
5774 if (!status)
5775 status = qla2x00_setup_chip(vha);
1da177e4
LT		 5776 }
5777
e315cd28
AC		 5778 if (!status && !(status = qla2x00_init_rings(vha))) {
5779 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
2533cf67 5780 ha->flags.chip_reset_done = 1;
7108b76e 5781
73208dfd
AC		 5782 /* Initialize the queues in use */
5783 qla25xx_init_queues(ha);
5784
e315cd28
AC		 5785 status = qla2x00_fw_ready(vha);
5786 if (!status) {
0107109e 5787 /* Issue a marker after FW becomes ready. */
73208dfd 5788 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
7108b76e 5789 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4
LT		 5790 }
5791
5792 /* if no cable then assume it's good */
e315cd28 5793 if ((vha->device_flags & DFLG_NO_CABLE))
1da177e4 5794 status = 0;
1da177e4
LT		 5795 }
5796 return (status);
5797}
5798
73208dfd
AC		 5799static int
5800qla25xx_init_queues(struct qla_hw_data *ha)
5801{
5802 struct rsp_que *rsp = NULL;
5803 struct req_que *req = NULL;
5804 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
5805 int ret = -1;
5806 int i;
5807
2afa19a9 5808 for (i = 1; i < ha->max_rsp_queues; i++) {
73208dfd 5809 rsp = ha->rsp_q_map[i];
cb43285f 5810 if (rsp && test_bit(i, ha->rsp_qid_map)) {
73208dfd 5811 rsp->options &= ~BIT_0;
618a7523 5812 ret = qla25xx_init_rsp_que(base_vha, rsp);
73208dfd 5813 if (ret != QLA_SUCCESS)
7c3df132
SK		 5814 ql_dbg(ql_dbg_init, base_vha, 0x00ff,
5815 "%s Rsp que: %d init failed.\n",
5816 __func__, rsp->id);
73208dfd 5817 else
7c3df132
SK		 5818 ql_dbg(ql_dbg_init, base_vha, 0x0100,
5819 "%s Rsp que: %d inited.\n",
5820 __func__, rsp->id);
73208dfd 5821 }
2afa19a9
AC		 5822 }
5823 for (i = 1; i < ha->max_req_queues; i++) {
73208dfd 5824 req = ha->req_q_map[i];
cb43285f
QT		 5825 if (req && test_bit(i, ha->req_qid_map)) {
5826 /* Clear outstanding commands array. */
73208dfd 5827 req->options &= ~BIT_0;
618a7523 5828 ret = qla25xx_init_req_que(base_vha, req);
73208dfd 5829 if (ret != QLA_SUCCESS)
7c3df132
SK		 5830 ql_dbg(ql_dbg_init, base_vha, 0x0101,
5831 "%s Req que: %d init failed.\n",
5832 __func__, req->id);
73208dfd 5833 else
7c3df132
SK		 5834 ql_dbg(ql_dbg_init, base_vha, 0x0102,
5835 "%s Req que: %d inited.\n",
5836 __func__, req->id);
73208dfd
AC		 5837 }
5838 }
5839 return ret;
5840}
5841
1da177e4
LT		 5842/*
5843* qla2x00_reset_adapter
5844* Reset adapter.
5845*
5846* Input:
5847* ha = adapter block pointer.
5848*/
abbd8870 5849void
e315cd28 5850qla2x00_reset_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 5851{
5852 unsigned long flags = 0;
e315cd28 5853 struct qla_hw_data *ha = vha->hw;
3d71644c 5854 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 5855
e315cd28 5856 vha->flags.online = 0;
fd34f556 5857 ha->isp_ops->disable_intrs(ha);
1da177e4 5858
1da177e4
LT		 5859 spin_lock_irqsave(&ha->hardware_lock, flags);
5860 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
5861 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
5862 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
5863 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
5864 spin_unlock_irqrestore(&ha->hardware_lock, flags);
5865}
0107109e
AV		 5866
5867void
e315cd28 5868qla24xx_reset_adapter(scsi_qla_host_t *vha)
0107109e
AV		 5869{
5870 unsigned long flags = 0;
e315cd28 5871 struct qla_hw_data *ha = vha->hw;
0107109e
AV		 5872 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
5873
7ec0effd 5874 if (IS_P3P_TYPE(ha))
a9083016
GM		 5875 return;
5876
e315cd28 5877 vha->flags.online = 0;
fd34f556 5878 ha->isp_ops->disable_intrs(ha);
0107109e
AV		 5879
5880 spin_lock_irqsave(&ha->hardware_lock, flags);
5881 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
5882 RD_REG_DWORD(&reg->hccr);
5883 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
5884 RD_REG_DWORD(&reg->hccr);
5885 spin_unlock_irqrestore(&ha->hardware_lock, flags);
09ff36d3
AV		 5886
5887 if (IS_NOPOLLING_TYPE(ha))
5888 ha->isp_ops->enable_intrs(ha);
0107109e
AV		 5889}
5890
4e08df3f
DM		 5891/* On sparc systems, obtain port and node WWN from firmware
5892 * properties.
5893 */
e315cd28
AC		 5894static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha,
5895 struct nvram_24xx *nv)
4e08df3f
DM		 5896{
5897#ifdef CONFIG_SPARC
e315cd28 5898 struct qla_hw_data *ha = vha->hw;
4e08df3f 5899 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 5900 struct device_node *dp = pci_device_to_OF_node(pdev);
5901 const u8 *val;
4e08df3f
DM		 5902 int len;
5903
5904 val = of_get_property(dp, "port-wwn", &len);
5905 if (val && len >= WWN_SIZE)
5906 memcpy(nv->port_name, val, WWN_SIZE);
5907
5908 val = of_get_property(dp, "node-wwn", &len);
5909 if (val && len >= WWN_SIZE)
5910 memcpy(nv->node_name, val, WWN_SIZE);
5911#endif
5912}
5913
0107109e 5914int
e315cd28 5915qla24xx_nvram_config(scsi_qla_host_t *vha)
0107109e 5916{
4e08df3f 5917 int rval;
0107109e
AV		 5918 struct init_cb_24xx *icb;
5919 struct nvram_24xx *nv;
5920 uint32_t *dptr;
5921 uint8_t *dptr1, *dptr2;
5922 uint32_t chksum;
5923 uint16_t cnt;
e315cd28 5924 struct qla_hw_data *ha = vha->hw;
0107109e 5925
4e08df3f 5926 rval = QLA_SUCCESS;
0107109e 5927 icb = (struct init_cb_24xx *)ha->init_cb;
281afe19 5928 nv = ha->nvram;
0107109e
AV		 5929
5930 /* Determine NVRAM starting address. */
f73cb695 5931 if (ha->port_no == 0) {
e5b68a61
AC		 5932 ha->nvram_base = FA_NVRAM_FUNC0_ADDR;
5933 ha->vpd_base = FA_NVRAM_VPD0_ADDR;
5934 } else {
0107109e 5935 ha->nvram_base = FA_NVRAM_FUNC1_ADDR;
6f641790
AV		 5936 ha->vpd_base = FA_NVRAM_VPD1_ADDR;
5937 }
f73cb695 5938
e5b68a61
AC		 5939 ha->nvram_size = sizeof(struct nvram_24xx);
5940 ha->vpd_size = FA_NVRAM_VPD_SIZE;
0107109e 5941
281afe19
SJ		 5942 /* Get VPD data into cache */
5943 ha->vpd = ha->nvram + VPD_OFFSET;
e315cd28 5944 ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd,
281afe19
SJ		 5945 ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
5946
5947 /* Get NVRAM data into cache and calculate checksum. */
0107109e 5948 dptr = (uint32_t *)nv;
e315cd28 5949 ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base,
0107109e 5950 ha->nvram_size);
da08ef5c
JC		 5951 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++)
5952 chksum += le32_to_cpu(*dptr);
0107109e 5953
7c3df132
SK		 5954 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
5955 "Contents of NVRAM\n");
5956 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
5957 (uint8_t *)nv, ha->nvram_size);
0107109e
AV		 5958
5959 /* Bad NVRAM data, set defaults parameters. */
5960 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
5961 || nv->id[3] != ' ' ||
ad950360 5962 nv->nvram_version < cpu_to_le16(ICB_VERSION)) {
0107109e 5963 /* Reset NVRAM data. */
7c3df132 5964 ql_log(ql_log_warn, vha, 0x006b,
9e336520 5965 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132
SK		 5966 "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version);
5967 ql_log(ql_log_warn, vha, 0x006c,
5968 "Falling back to functioning (yet invalid -- WWPN) "
5969 "defaults.\n");
4e08df3f
DM		 5970
5971 /*
5972 * Set default initialization control block.
5973 */
5974 memset(nv, 0, ha->nvram_size);
ad950360
BVA		 5975 nv->nvram_version = cpu_to_le16(ICB_VERSION);
5976 nv->version = cpu_to_le16(ICB_VERSION);
98aee70d 5977 nv->frame_payload_size = 2048;
ad950360
BVA		 5978 nv->execution_throttle = cpu_to_le16(0xFFFF);
5979 nv->exchange_count = cpu_to_le16(0);
5980 nv->hard_address = cpu_to_le16(124);
4e08df3f 5981 nv->port_name[0] = 0x21;
f73cb695 5982 nv->port_name[1] = 0x00 + ha->port_no + 1;
4e08df3f
DM		 5983 nv->port_name[2] = 0x00;
5984 nv->port_name[3] = 0xe0;
5985 nv->port_name[4] = 0x8b;
5986 nv->port_name[5] = 0x1c;
5987 nv->port_name[6] = 0x55;
5988 nv->port_name[7] = 0x86;
5989 nv->node_name[0] = 0x20;
5990 nv->node_name[1] = 0x00;
5991 nv->node_name[2] = 0x00;
5992 nv->node_name[3] = 0xe0;
5993 nv->node_name[4] = 0x8b;
5994 nv->node_name[5] = 0x1c;
5995 nv->node_name[6] = 0x55;
5996 nv->node_name[7] = 0x86;
e315cd28 5997 qla24xx_nvram_wwn_from_ofw(vha, nv);
ad950360
BVA		 5998 nv->login_retry_count = cpu_to_le16(8);
5999 nv->interrupt_delay_timer = cpu_to_le16(0);
6000 nv->login_timeout = cpu_to_le16(0);
4e08df3f 6001 nv->firmware_options_1 =
ad950360
BVA		 6002 cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
6003 nv->firmware_options_2 = cpu_to_le32(2 << 4);
6004 nv->firmware_options_2 |= cpu_to_le32(BIT_12);
6005 nv->firmware_options_3 = cpu_to_le32(2 << 13);
6006 nv->host_p = cpu_to_le32(BIT_11|BIT_10);
6007 nv->efi_parameters = cpu_to_le32(0);
4e08df3f 6008 nv->reset_delay = 5;
ad950360
BVA		 6009 nv->max_luns_per_target = cpu_to_le16(128);
6010 nv->port_down_retry_count = cpu_to_le16(30);
6011 nv->link_down_timeout = cpu_to_le16(30);
4e08df3f
DM		 6012
6013 rval = 1;
0107109e
AV		 6014 }
6015
726b8548 6016 if (qla_tgt_mode_enabled(vha)) {
2d70c103 6017 /* Don't enable full login after initial LIP */
ad950360 6018 nv->firmware_options_1 &= cpu_to_le32(~BIT_13);
2d70c103 6019 /* Don't enable LIP full login for initiator */
ad950360 6020 nv->host_p &= cpu_to_le32(~BIT_10);
2d70c103
NB		 6021 }
6022
6023 qlt_24xx_config_nvram_stage1(vha, nv);
6024
0107109e 6025 /* Reset Initialization control block */
e315cd28 6026 memset(icb, 0, ha->init_cb_size);
0107109e
AV		 6027
6028 /* Copy 1st segment. */
6029 dptr1 = (uint8_t *)icb;
6030 dptr2 = (uint8_t *)&nv->version;
6031 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
6032 while (cnt--)
6033 *dptr1++ = *dptr2++;
6034
6035 icb->login_retry_count = nv->login_retry_count;
3ea66e28 6036 icb->link_down_on_nos = nv->link_down_on_nos;
0107109e
AV		 6037
6038 /* Copy 2nd segment. */
6039 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
6040 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
6041 cnt = (uint8_t *)&icb->reserved_3 -
6042 (uint8_t *)&icb->interrupt_delay_timer;
6043 while (cnt--)
6044 *dptr1++ = *dptr2++;
6045
6046 /*
6047 * Setup driver NVRAM options.
6048 */
e315cd28 6049 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
9bb9fcf2 6050 "QLA2462");
0107109e 6051
2d70c103
NB		 6052 qlt_24xx_config_nvram_stage2(vha, icb);
6053
ad950360 6054 if (nv->host_p & cpu_to_le32(BIT_15)) {
2d70c103 6055 /* Use alternate WWN? */
5341e868
AV		 6056 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
6057 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
6058 }
6059
0107109e 6060 /* Prepare nodename */
ad950360 6061 if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) {
0107109e
AV		 6062 /*
6063 * Firmware will apply the following mask if the nodename was
6064 * not provided.
6065 */
6066 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
6067 icb->node_name[0] &= 0xF0;
6068 }
6069
6070 /* Set host adapter parameters. */
6071 ha->flags.disable_risc_code_load = 0;
0c8c39af
AV		 6072 ha->flags.enable_lip_reset = 0;
6073 ha->flags.enable_lip_full_login =
6074 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
6075 ha->flags.enable_target_reset =
6076 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
0107109e 6077 ha->flags.enable_led_scheme = 0;
d4c760c2 6078 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
0107109e 6079
fd0e7e4d
AV		 6080 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
6081 (BIT_6 | BIT_5 | BIT_4)) >> 4;
0107109e
AV		 6082
6083 memcpy(ha->fw_seriallink_options24, nv->seriallink_options,
6084 sizeof(ha->fw_seriallink_options24));
6085
6086 /* save HBA serial number */
6087 ha->serial0 = icb->port_name[5];
6088 ha->serial1 = icb->port_name[6];
6089 ha->serial2 = icb->port_name[7];
e315cd28
AC		 6090 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
6091 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
0107109e 6092
ad950360 6093 icb->execution_throttle = cpu_to_le16(0xFFFF);
bc8fb3cb 6094
0107109e
AV		 6095 ha->retry_count = le16_to_cpu(nv->login_retry_count);
6096
6097 /* Set minimum login_timeout to 4 seconds. */
6098 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
6099 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
6100 if (le16_to_cpu(nv->login_timeout) < 4)
ad950360 6101 nv->login_timeout = cpu_to_le16(4);
0107109e 6102 ha->login_timeout = le16_to_cpu(nv->login_timeout);
0107109e 6103
00a537b8
AV		 6104 /* Set minimum RATOV to 100 tenths of a second. */
6105 ha->r_a_tov = 100;
0107109e
AV		 6106
6107 ha->loop_reset_delay = nv->reset_delay;
6108
6109 /* Link Down Timeout = 0:
6110 *
6111 * When Port Down timer expires we will start returning
6112 * I/O's to OS with "DID_NO_CONNECT".
6113 *
6114 * Link Down Timeout != 0:
6115 *
6116 * The driver waits for the link to come up after link down
6117 * before returning I/Os to OS with "DID_NO_CONNECT".
6118 */
6119 if (le16_to_cpu(nv->link_down_timeout) == 0) {
6120 ha->loop_down_abort_time =
6121 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
6122 } else {
6123 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
6124 ha->loop_down_abort_time =
6125 (LOOP_DOWN_TIME - ha->link_down_timeout);
6126 }
6127
6128 /* Need enough time to try and get the port back. */
6129 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
6130 if (qlport_down_retry)
6131 ha->port_down_retry_count = qlport_down_retry;
6132
6133 /* Set login_retry_count */
6134 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
6135 if (ha->port_down_retry_count ==
6136 le16_to_cpu(nv->port_down_retry_count) &&
6137 ha->port_down_retry_count > 3)
6138 ha->login_retry_count = ha->port_down_retry_count;
6139 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
6140 ha->login_retry_count = ha->port_down_retry_count;
6141 if (ql2xloginretrycount)
6142 ha->login_retry_count = ql2xloginretrycount;
6143
4fdfefe5 6144 /* Enable ZIO. */
e315cd28 6145 if (!vha->flags.init_done) {
4fdfefe5
AV		 6146 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
6147 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
6148 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
6149 le16_to_cpu(icb->interrupt_delay_timer): 2;
6150 }
ad950360 6151 icb->firmware_options_2 &= cpu_to_le32(
4fdfefe5 6152 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
e315cd28 6153 vha->flags.process_response_queue = 0;
4fdfefe5 6154 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d
AV		 6155 ha->zio_mode = QLA_ZIO_MODE_6;
6156
7c3df132 6157 ql_log(ql_log_info, vha, 0x006f,
4fdfefe5
AV		 6158 "ZIO mode %d enabled; timer delay (%d us).\n",
6159 ha->zio_mode, ha->zio_timer * 100);
6160
6161 icb->firmware_options_2 |= cpu_to_le32(
6162 (uint32_t)ha->zio_mode);
6163 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
e315cd28 6164 vha->flags.process_response_queue = 1;
4fdfefe5
AV		 6165 }
6166
4e08df3f 6167 if (rval) {
7c3df132
SK		 6168 ql_log(ql_log_warn, vha, 0x0070,
6169 "NVRAM configuration failed.\n");
4e08df3f
DM		 6170 }
6171 return (rval);
0107109e
AV		 6172}
6173
4243c115
SC		 6174uint8_t qla27xx_find_valid_image(struct scsi_qla_host *vha)
6175{
6176 struct qla27xx_image_status pri_image_status, sec_image_status;
6177 uint8_t valid_pri_image, valid_sec_image;
6178 uint32_t *wptr;
6179 uint32_t cnt, chksum, size;
6180 struct qla_hw_data *ha = vha->hw;
6181
6182 valid_pri_image = valid_sec_image = 1;
6183 ha->active_image = 0;
6184 size = sizeof(struct qla27xx_image_status) / sizeof(uint32_t);
6185
6186 if (!ha->flt_region_img_status_pri) {
6187 valid_pri_image = 0;
6188 goto check_sec_image;
6189 }
6190
6191 qla24xx_read_flash_data(vha, (uint32_t *)(&pri_image_status),
6192 ha->flt_region_img_status_pri, size);
6193
6194 if (pri_image_status.signature != QLA27XX_IMG_STATUS_SIGN) {
6195 ql_dbg(ql_dbg_init, vha, 0x018b,
6196 "Primary image signature (0x%x) not valid\n",
6197 pri_image_status.signature);
6198 valid_pri_image = 0;
6199 goto check_sec_image;
6200 }
6201
6202 wptr = (uint32_t *)(&pri_image_status);
6203 cnt = size;
6204
da08ef5c
JC		 6205 for (chksum = 0; cnt--; wptr++)
6206 chksum += le32_to_cpu(*wptr);
41dc529a 6207
4243c115
SC		 6208 if (chksum) {
6209 ql_dbg(ql_dbg_init, vha, 0x018c,
6210 "Checksum validation failed for primary image (0x%x)\n",
6211 chksum);
6212 valid_pri_image = 0;
6213 }
6214
6215check_sec_image:
6216 if (!ha->flt_region_img_status_sec) {
6217 valid_sec_image = 0;
6218 goto check_valid_image;
6219 }
6220
6221 qla24xx_read_flash_data(vha, (uint32_t *)(&sec_image_status),
6222 ha->flt_region_img_status_sec, size);
6223
6224 if (sec_image_status.signature != QLA27XX_IMG_STATUS_SIGN) {
6225 ql_dbg(ql_dbg_init, vha, 0x018d,
6226 "Secondary image signature(0x%x) not valid\n",
6227 sec_image_status.signature);
6228 valid_sec_image = 0;
6229 goto check_valid_image;
6230 }
6231
6232 wptr = (uint32_t *)(&sec_image_status);
6233 cnt = size;
da08ef5c
JC		 6234 for (chksum = 0; cnt--; wptr++)
6235 chksum += le32_to_cpu(*wptr);
4243c115
SC		 6236 if (chksum) {
6237 ql_dbg(ql_dbg_init, vha, 0x018e,
6238 "Checksum validation failed for secondary image (0x%x)\n",
6239 chksum);
6240 valid_sec_image = 0;
6241 }
6242
6243check_valid_image:
6244 if (valid_pri_image && (pri_image_status.image_status_mask & 0x1))
6245 ha->active_image = QLA27XX_PRIMARY_IMAGE;
6246 if (valid_sec_image && (sec_image_status.image_status_mask & 0x1)) {
6247 if (!ha->active_image ||
6248 pri_image_status.generation_number <
6249 sec_image_status.generation_number)
6250 ha->active_image = QLA27XX_SECONDARY_IMAGE;
6251 }
6252
6253 ql_dbg(ql_dbg_init, vha, 0x018f, "%s image\n",
6254 ha->active_image == 0 ? "default bootld and fw" :
6255 ha->active_image == 1 ? "primary" :
6256 ha->active_image == 2 ? "secondary" :
6257 "Invalid");
6258
6259 return ha->active_image;
6260}
6261
413975a0 6262static int
cbc8eb67
AV		 6263qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
6264 uint32_t faddr)
d1c61909 6265{
73208dfd 6266 int rval = QLA_SUCCESS;
d1c61909 6267 int segments, fragment;
d1c61909
AV		 6268 uint32_t *dcode, dlen;
6269 uint32_t risc_addr;
6270 uint32_t risc_size;
6271 uint32_t i;
e315cd28 6272 struct qla_hw_data *ha = vha->hw;
73208dfd 6273 struct req_que *req = ha->req_q_map[0];
eaac30be 6274
7c3df132 6275 ql_dbg(ql_dbg_init, vha, 0x008b,
cfb0919c 6276 "FW: Loading firmware from flash (%x).\n", faddr);
eaac30be 6277
d1c61909
AV		 6278 rval = QLA_SUCCESS;
6279
6280 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 6281 dcode = (uint32_t *)req->ring;
d1c61909
AV		 6282 *srisc_addr = 0;
6283
4243c115
SC		 6284 if (IS_QLA27XX(ha) &&
6285 qla27xx_find_valid_image(vha) == QLA27XX_SECONDARY_IMAGE)
6286 faddr = ha->flt_region_fw_sec;
6287
d1c61909 6288 /* Validate firmware image by checking version. */
e315cd28 6289 qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
d1c61909
AV		 6290 for (i = 0; i < 4; i++)
6291 dcode[i] = be32_to_cpu(dcode[i]);
6292 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
6293 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
6294 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
6295 dcode[3] == 0)) {
7c3df132
SK		 6296 ql_log(ql_log_fatal, vha, 0x008c,
6297 "Unable to verify the integrity of flash firmware "
6298 "image.\n");
6299 ql_log(ql_log_fatal, vha, 0x008d,
6300 "Firmware data: %08x %08x %08x %08x.\n",
6301 dcode[0], dcode[1], dcode[2], dcode[3]);
d1c61909
AV		 6302
6303 return QLA_FUNCTION_FAILED;
6304 }
6305
6306 while (segments && rval == QLA_SUCCESS) {
6307 /* Read segment's load information. */
e315cd28 6308 qla24xx_read_flash_data(vha, dcode, faddr, 4);
d1c61909
AV		 6309
6310 risc_addr = be32_to_cpu(dcode[2]);
6311 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
6312 risc_size = be32_to_cpu(dcode[3]);
6313
6314 fragment = 0;
6315 while (risc_size > 0 && rval == QLA_SUCCESS) {
6316 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
6317 if (dlen > risc_size)
6318 dlen = risc_size;
6319
7c3df132
SK		 6320 ql_dbg(ql_dbg_init, vha, 0x008e,
6321 "Loading risc segment@ risc addr %x "
6322 "number of dwords 0x%x offset 0x%x.\n",
6323 risc_addr, dlen, faddr);
d1c61909 6324
e315cd28 6325 qla24xx_read_flash_data(vha, dcode, faddr, dlen);
d1c61909
AV		 6326 for (i = 0; i < dlen; i++)
6327 dcode[i] = swab32(dcode[i]);
6328
73208dfd 6329 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
d1c61909
AV		 6330 dlen);
6331 if (rval) {
7c3df132
SK		 6332 ql_log(ql_log_fatal, vha, 0x008f,
6333 "Failed to load segment %d of firmware.\n",
6334 fragment);
f261f7af 6335 return QLA_FUNCTION_FAILED;
d1c61909
AV		 6336 }
6337
6338 faddr += dlen;
6339 risc_addr += dlen;
6340 risc_size -= dlen;
6341 fragment++;
6342 }
6343
6344 /* Next segment. */
6345 segments--;
6346 }
6347
f73cb695
CD		 6348 if (!IS_QLA27XX(ha))
6349 return rval;
6350
6351 if (ha->fw_dump_template)
6352 vfree(ha->fw_dump_template);
6353 ha->fw_dump_template = NULL;
6354 ha->fw_dump_template_len = 0;
6355
6356 ql_dbg(ql_dbg_init, vha, 0x0161,
6357 "Loading fwdump template from %x\n", faddr);
6358 qla24xx_read_flash_data(vha, dcode, faddr, 7);
6359 risc_size = be32_to_cpu(dcode[2]);
6360 ql_dbg(ql_dbg_init, vha, 0x0162,
6361 "-> array size %x dwords\n", risc_size);
6362 if (risc_size == 0 || risc_size == ~0)
6363 goto default_template;
6364
6365 dlen = (risc_size - 8) * sizeof(*dcode);
6366 ql_dbg(ql_dbg_init, vha, 0x0163,
6367 "-> template allocating %x bytes...\n", dlen);
6368 ha->fw_dump_template = vmalloc(dlen);
6369 if (!ha->fw_dump_template) {
6370 ql_log(ql_log_warn, vha, 0x0164,
6371 "Failed fwdump template allocate %x bytes.\n", risc_size);
6372 goto default_template;
6373 }
6374
6375 faddr += 7;
6376 risc_size -= 8;
6377 dcode = ha->fw_dump_template;
6378 qla24xx_read_flash_data(vha, dcode, faddr, risc_size);
6379 for (i = 0; i < risc_size; i++)
6380 dcode[i] = le32_to_cpu(dcode[i]);
6381
6382 if (!qla27xx_fwdt_template_valid(dcode)) {
6383 ql_log(ql_log_warn, vha, 0x0165,
6384 "Failed fwdump template validate\n");
6385 goto default_template;
6386 }
6387
6388 dlen = qla27xx_fwdt_template_size(dcode);
6389 ql_dbg(ql_dbg_init, vha, 0x0166,
6390 "-> template size %x bytes\n", dlen);
6391 if (dlen > risc_size * sizeof(*dcode)) {
6392 ql_log(ql_log_warn, vha, 0x0167,
97ea702b
CD		 6393 "Failed fwdump template exceeds array by %x bytes\n",
6394 (uint32_t)(dlen - risc_size * sizeof(*dcode)));
f73cb695
CD		 6395 goto default_template;
6396 }
6397 ha->fw_dump_template_len = dlen;
6398 return rval;
6399
6400default_template:
6401 ql_log(ql_log_warn, vha, 0x0168, "Using default fwdump template\n");
6402 if (ha->fw_dump_template)
6403 vfree(ha->fw_dump_template);
6404 ha->fw_dump_template = NULL;
6405 ha->fw_dump_template_len = 0;
6406
6407 dlen = qla27xx_fwdt_template_default_size();
6408 ql_dbg(ql_dbg_init, vha, 0x0169,
6409 "-> template allocating %x bytes...\n", dlen);
6410 ha->fw_dump_template = vmalloc(dlen);
6411 if (!ha->fw_dump_template) {
6412 ql_log(ql_log_warn, vha, 0x016a,
6413 "Failed fwdump template allocate %x bytes.\n", risc_size);
6414 goto failed_template;
6415 }
6416
6417 dcode = ha->fw_dump_template;
6418 risc_size = dlen / sizeof(*dcode);
6419 memcpy(dcode, qla27xx_fwdt_template_default(), dlen);
6420 for (i = 0; i < risc_size; i++)
6421 dcode[i] = be32_to_cpu(dcode[i]);
6422
6423 if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) {
6424 ql_log(ql_log_warn, vha, 0x016b,
6425 "Failed fwdump template validate\n");
6426 goto failed_template;
6427 }
6428
6429 dlen = qla27xx_fwdt_template_size(ha->fw_dump_template);
6430 ql_dbg(ql_dbg_init, vha, 0x016c,
6431 "-> template size %x bytes\n", dlen);
6432 ha->fw_dump_template_len = dlen;
6433 return rval;
6434
6435failed_template:
6436 ql_log(ql_log_warn, vha, 0x016d, "Failed default fwdump template\n");
6437 if (ha->fw_dump_template)
6438 vfree(ha->fw_dump_template);
6439 ha->fw_dump_template = NULL;
6440 ha->fw_dump_template_len = 0;
d1c61909
AV		 6441 return rval;
6442}
6443
e9454a88 6444#define QLA_FW_URL "http://ldriver.qlogic.com/firmware/"
d1c61909 6445
0107109e 6446int
e315cd28 6447qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5433383e
AV		 6448{
6449 int rval;
6450 int i, fragment;
6451 uint16_t *wcode, *fwcode;
6452 uint32_t risc_addr, risc_size, fwclen, wlen, *seg;
6453 struct fw_blob *blob;
e315cd28 6454 struct qla_hw_data *ha = vha->hw;
73208dfd 6455 struct req_que *req = ha->req_q_map[0];
5433383e
AV		 6456
6457 /* Load firmware blob. */
e315cd28 6458 blob = qla2x00_request_firmware(vha);
5433383e 6459 if (!blob) {
7c3df132 6460 ql_log(ql_log_info, vha, 0x0083,
94bcf830 6461 "Firmware image unavailable.\n");
7c3df132
SK		 6462 ql_log(ql_log_info, vha, 0x0084,
6463 "Firmware images can be retrieved from: "QLA_FW_URL ".\n");
5433383e
AV		 6464 return QLA_FUNCTION_FAILED;
6465 }
6466
6467 rval = QLA_SUCCESS;
6468
73208dfd 6469 wcode = (uint16_t *)req->ring;
5433383e
AV		 6470 *srisc_addr = 0;
6471 fwcode = (uint16_t *)blob->fw->data;
6472 fwclen = 0;
6473
6474 /* Validate firmware image by checking version. */
6475 if (blob->fw->size < 8 * sizeof(uint16_t)) {
7c3df132 6476 ql_log(ql_log_fatal, vha, 0x0085,
5b5e0928 6477 "Unable to verify integrity of firmware image (%zd).\n",
5433383e
AV		 6478 blob->fw->size);
6479 goto fail_fw_integrity;
6480 }
6481 for (i = 0; i < 4; i++)
6482 wcode[i] = be16_to_cpu(fwcode[i + 4]);
6483 if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff &&
6484 wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 &&
6485 wcode[2] == 0 && wcode[3] == 0)) {
7c3df132
SK		 6486 ql_log(ql_log_fatal, vha, 0x0086,
6487 "Unable to verify integrity of firmware image.\n");
6488 ql_log(ql_log_fatal, vha, 0x0087,
6489 "Firmware data: %04x %04x %04x %04x.\n",
6490 wcode[0], wcode[1], wcode[2], wcode[3]);
5433383e
AV		 6491 goto fail_fw_integrity;
6492 }
6493
6494 seg = blob->segs;
6495 while (*seg && rval == QLA_SUCCESS) {
6496 risc_addr = *seg;
6497 *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr;
6498 risc_size = be16_to_cpu(fwcode[3]);
6499
6500 /* Validate firmware image size. */
6501 fwclen += risc_size * sizeof(uint16_t);
6502 if (blob->fw->size < fwclen) {
7c3df132 6503 ql_log(ql_log_fatal, vha, 0x0088,
5433383e 6504 "Unable to verify integrity of firmware image "
5b5e0928 6505 "(%zd).\n", blob->fw->size);
5433383e
AV		 6506 goto fail_fw_integrity;
6507 }
6508
6509 fragment = 0;
6510 while (risc_size > 0 && rval == QLA_SUCCESS) {
6511 wlen = (uint16_t)(ha->fw_transfer_size >> 1);
6512 if (wlen > risc_size)
6513 wlen = risc_size;
7c3df132
SK		 6514 ql_dbg(ql_dbg_init, vha, 0x0089,
6515 "Loading risc segment@ risc addr %x number of "
6516 "words 0x%x.\n", risc_addr, wlen);
5433383e
AV		 6517
6518 for (i = 0; i < wlen; i++)
6519 wcode[i] = swab16(fwcode[i]);
6520
73208dfd 6521 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
5433383e
AV		 6522 wlen);
6523 if (rval) {
7c3df132
SK		 6524 ql_log(ql_log_fatal, vha, 0x008a,
6525 "Failed to load segment %d of firmware.\n",
6526 fragment);
5433383e
AV		 6527 break;
6528 }
6529
6530 fwcode += wlen;
6531 risc_addr += wlen;
6532 risc_size -= wlen;
6533 fragment++;
6534 }
6535
6536 /* Next segment. */
6537 seg++;
6538 }
6539 return rval;
6540
6541fail_fw_integrity:
6542 return QLA_FUNCTION_FAILED;
6543}
6544
eaac30be
AV		 6545static int
6546qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
0107109e
AV		 6547{
6548 int rval;
6549 int segments, fragment;
6550 uint32_t *dcode, dlen;
6551 uint32_t risc_addr;
6552 uint32_t risc_size;
6553 uint32_t i;
5433383e 6554 struct fw_blob *blob;
f73cb695
CD		 6555 const uint32_t *fwcode;
6556 uint32_t fwclen;
e315cd28 6557 struct qla_hw_data *ha = vha->hw;
73208dfd 6558 struct req_que *req = ha->req_q_map[0];
0107109e 6559
5433383e 6560 /* Load firmware blob. */
e315cd28 6561 blob = qla2x00_request_firmware(vha);
5433383e 6562 if (!blob) {
7c3df132 6563 ql_log(ql_log_warn, vha, 0x0090,
94bcf830 6564 "Firmware image unavailable.\n");
7c3df132
SK		 6565 ql_log(ql_log_warn, vha, 0x0091,
6566 "Firmware images can be retrieved from: "
6567 QLA_FW_URL ".\n");
d1c61909 6568
eaac30be 6569 return QLA_FUNCTION_FAILED;
0107109e
AV		 6570 }
6571
cfb0919c
CD		 6572 ql_dbg(ql_dbg_init, vha, 0x0092,
6573 "FW: Loading via request-firmware.\n");
eaac30be 6574
0107109e
AV		 6575 rval = QLA_SUCCESS;
6576
6577 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 6578 dcode = (uint32_t *)req->ring;
0107109e 6579 *srisc_addr = 0;
5433383e 6580 fwcode = (uint32_t *)blob->fw->data;
0107109e
AV		 6581 fwclen = 0;
6582
6583 /* Validate firmware image by checking version. */
5433383e 6584 if (blob->fw->size < 8 * sizeof(uint32_t)) {
7c3df132 6585 ql_log(ql_log_fatal, vha, 0x0093,
5b5e0928 6586 "Unable to verify integrity of firmware image (%zd).\n",
5433383e 6587 blob->fw->size);
f73cb695 6588 return QLA_FUNCTION_FAILED;
0107109e
AV		 6589 }
6590 for (i = 0; i < 4; i++)
6591 dcode[i] = be32_to_cpu(fwcode[i + 4]);
6592 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
6593 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
6594 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
6595 dcode[3] == 0)) {
7c3df132 6596 ql_log(ql_log_fatal, vha, 0x0094,
5b5e0928 6597 "Unable to verify integrity of firmware image (%zd).\n",
7c3df132
SK		 6598 blob->fw->size);
6599 ql_log(ql_log_fatal, vha, 0x0095,
6600 "Firmware data: %08x %08x %08x %08x.\n",
6601 dcode[0], dcode[1], dcode[2], dcode[3]);
f73cb695 6602 return QLA_FUNCTION_FAILED;
0107109e
AV		 6603 }
6604
6605 while (segments && rval == QLA_SUCCESS) {
6606 risc_addr = be32_to_cpu(fwcode[2]);
6607 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
6608 risc_size = be32_to_cpu(fwcode[3]);
6609
6610 /* Validate firmware image size. */
6611 fwclen += risc_size * sizeof(uint32_t);
5433383e 6612 if (blob->fw->size < fwclen) {
7c3df132 6613 ql_log(ql_log_fatal, vha, 0x0096,
5433383e 6614 "Unable to verify integrity of firmware image "
5b5e0928 6615 "(%zd).\n", blob->fw->size);
f73cb695 6616 return QLA_FUNCTION_FAILED;
0107109e
AV		 6617 }
6618
6619 fragment = 0;
6620 while (risc_size > 0 && rval == QLA_SUCCESS) {
6621 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
6622 if (dlen > risc_size)
6623 dlen = risc_size;
6624
7c3df132
SK		 6625 ql_dbg(ql_dbg_init, vha, 0x0097,
6626 "Loading risc segment@ risc addr %x "
6627 "number of dwords 0x%x.\n", risc_addr, dlen);
0107109e
AV		 6628
6629 for (i = 0; i < dlen; i++)
6630 dcode[i] = swab32(fwcode[i]);
6631
73208dfd 6632 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
590f98e5 6633 dlen);
0107109e 6634 if (rval) {
7c3df132
SK		 6635 ql_log(ql_log_fatal, vha, 0x0098,
6636 "Failed to load segment %d of firmware.\n",
6637 fragment);
f261f7af 6638 return QLA_FUNCTION_FAILED;
0107109e
AV		 6639 }
6640
6641 fwcode += dlen;
6642 risc_addr += dlen;
6643 risc_size -= dlen;
6644 fragment++;
6645 }
6646
6647 /* Next segment. */
6648 segments--;
6649 }
f73cb695
CD		 6650
6651 if (!IS_QLA27XX(ha))
6652 return rval;
6653
6654 if (ha->fw_dump_template)
6655 vfree(ha->fw_dump_template);
6656 ha->fw_dump_template = NULL;
6657 ha->fw_dump_template_len = 0;
6658
6659 ql_dbg(ql_dbg_init, vha, 0x171,
97ea702b
CD		 6660 "Loading fwdump template from %x\n",
6661 (uint32_t)((void *)fwcode - (void *)blob->fw->data));
f73cb695
CD		 6662 risc_size = be32_to_cpu(fwcode[2]);
6663 ql_dbg(ql_dbg_init, vha, 0x172,
6664 "-> array size %x dwords\n", risc_size);
6665 if (risc_size == 0 || risc_size == ~0)
6666 goto default_template;
6667
6668 dlen = (risc_size - 8) * sizeof(*fwcode);
6669 ql_dbg(ql_dbg_init, vha, 0x0173,
6670 "-> template allocating %x bytes...\n", dlen);
6671 ha->fw_dump_template = vmalloc(dlen);
6672 if (!ha->fw_dump_template) {
6673 ql_log(ql_log_warn, vha, 0x0174,
6674 "Failed fwdump template allocate %x bytes.\n", risc_size);
6675 goto default_template;
6676 }
6677
6678 fwcode += 7;
6679 risc_size -= 8;
6680 dcode = ha->fw_dump_template;
6681 for (i = 0; i < risc_size; i++)
6682 dcode[i] = le32_to_cpu(fwcode[i]);
6683
6684 if (!qla27xx_fwdt_template_valid(dcode)) {
6685 ql_log(ql_log_warn, vha, 0x0175,
6686 "Failed fwdump template validate\n");
6687 goto default_template;
6688 }
6689
6690 dlen = qla27xx_fwdt_template_size(dcode);
6691 ql_dbg(ql_dbg_init, vha, 0x0176,
6692 "-> template size %x bytes\n", dlen);
6693 if (dlen > risc_size * sizeof(*fwcode)) {
6694 ql_log(ql_log_warn, vha, 0x0177,
97ea702b
CD		 6695 "Failed fwdump template exceeds array by %x bytes\n",
6696 (uint32_t)(dlen - risc_size * sizeof(*fwcode)));
f73cb695
CD		 6697 goto default_template;
6698 }
6699 ha->fw_dump_template_len = dlen;
0107109e
AV		 6700 return rval;
6701
f73cb695
CD		 6702default_template:
6703 ql_log(ql_log_warn, vha, 0x0178, "Using default fwdump template\n");
6704 if (ha->fw_dump_template)
6705 vfree(ha->fw_dump_template);
6706 ha->fw_dump_template = NULL;
6707 ha->fw_dump_template_len = 0;
6708
6709 dlen = qla27xx_fwdt_template_default_size();
6710 ql_dbg(ql_dbg_init, vha, 0x0179,
6711 "-> template allocating %x bytes...\n", dlen);
6712 ha->fw_dump_template = vmalloc(dlen);
6713 if (!ha->fw_dump_template) {
6714 ql_log(ql_log_warn, vha, 0x017a,
6715 "Failed fwdump template allocate %x bytes.\n", risc_size);
6716 goto failed_template;
6717 }
6718
6719 dcode = ha->fw_dump_template;
6720 risc_size = dlen / sizeof(*fwcode);
6721 fwcode = qla27xx_fwdt_template_default();
6722 for (i = 0; i < risc_size; i++)
6723 dcode[i] = be32_to_cpu(fwcode[i]);
6724
6725 if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) {
6726 ql_log(ql_log_warn, vha, 0x017b,
6727 "Failed fwdump template validate\n");
6728 goto failed_template;
6729 }
6730
6731 dlen = qla27xx_fwdt_template_size(ha->fw_dump_template);
6732 ql_dbg(ql_dbg_init, vha, 0x017c,
6733 "-> template size %x bytes\n", dlen);
6734 ha->fw_dump_template_len = dlen;
6735 return rval;
6736
6737failed_template:
6738 ql_log(ql_log_warn, vha, 0x017d, "Failed default fwdump template\n");
6739 if (ha->fw_dump_template)
6740 vfree(ha->fw_dump_template);
6741 ha->fw_dump_template = NULL;
6742 ha->fw_dump_template_len = 0;
6743 return rval;
0107109e 6744}
18c6c127 6745
eaac30be
AV		 6746int
6747qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
6748{
6749 int rval;
6750
e337d907
AV		 6751 if (ql2xfwloadbin == 1)
6752 return qla81xx_load_risc(vha, srisc_addr);
6753
eaac30be
AV		 6754 /*
6755 * FW Load priority:
6756 * 1) Firmware via request-firmware interface (.bin file).
6757 * 2) Firmware residing in flash.
6758 */
6759 rval = qla24xx_load_risc_blob(vha, srisc_addr);
6760 if (rval == QLA_SUCCESS)
6761 return rval;
6762
cbc8eb67
AV		 6763 return qla24xx_load_risc_flash(vha, srisc_addr,
6764 vha->hw->flt_region_fw);
eaac30be
AV		 6765}
6766
6767int
6768qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
6769{
6770 int rval;
cbc8eb67 6771 struct qla_hw_data *ha = vha->hw;
eaac30be 6772
e337d907 6773 if (ql2xfwloadbin == 2)
cbc8eb67 6774 goto try_blob_fw;
e337d907 6775
eaac30be
AV		 6776 /*
6777 * FW Load priority:
6778 * 1) Firmware residing in flash.
6779 * 2) Firmware via request-firmware interface (.bin file).
cbc8eb67 6780 * 3) Golden-Firmware residing in flash -- limited operation.
eaac30be 6781 */
cbc8eb67 6782 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
eaac30be
AV		 6783 if (rval == QLA_SUCCESS)
6784 return rval;
6785
cbc8eb67
AV		 6786try_blob_fw:
6787 rval = qla24xx_load_risc_blob(vha, srisc_addr);
6788 if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw)
6789 return rval;
6790
7c3df132
SK		 6791 ql_log(ql_log_info, vha, 0x0099,
6792 "Attempting to fallback to golden firmware.\n");
cbc8eb67
AV		 6793 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
6794 if (rval != QLA_SUCCESS)
6795 return rval;
6796
7c3df132 6797 ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n");
cbc8eb67 6798 ha->flags.running_gold_fw = 1;
cbc8eb67 6799 return rval;
eaac30be
AV		 6800}
6801
18c6c127 6802void
e315cd28 6803qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha)
18c6c127
AV		 6804{
6805 int ret, retries;
e315cd28 6806 struct qla_hw_data *ha = vha->hw;
18c6c127 6807
85880801
AV		 6808 if (ha->flags.pci_channel_io_perm_failure)
6809 return;
e428924c 6810 if (!IS_FWI2_CAPABLE(ha))
18c6c127 6811 return;
75edf81d
AV		 6812 if (!ha->fw_major_version)
6813 return;
18c6c127 6814
e315cd28 6815 ret = qla2x00_stop_firmware(vha);
7c7f1f29 6816 for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&
b469a7cb 6817 ret != QLA_INVALID_COMMAND && retries ; retries--) {
e315cd28
AC		 6818 ha->isp_ops->reset_chip(vha);
6819 if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS)
18c6c127 6820 continue;
e315cd28 6821 if (qla2x00_setup_chip(vha) != QLA_SUCCESS)
18c6c127 6822 continue;
7c3df132
SK		 6823 ql_log(ql_log_info, vha, 0x8015,
6824 "Attempting retry of stop-firmware command.\n");
e315cd28 6825 ret = qla2x00_stop_firmware(vha);
18c6c127
AV		 6826 }
6827}
2c3dfe3f
SJ		 6828
6829int
e315cd28 6830qla24xx_configure_vhba(scsi_qla_host_t *vha)
2c3dfe3f
SJ		 6831{
6832 int rval = QLA_SUCCESS;
0b91d116 6833 int rval2;
2c3dfe3f 6834 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28
AC		 6835 struct qla_hw_data *ha = vha->hw;
6836 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
67c2e93a
AC		 6837 struct req_que *req;
6838 struct rsp_que *rsp;
2c3dfe3f 6839
e315cd28 6840 if (!vha->vp_idx)
2c3dfe3f
SJ		 6841 return -EINVAL;
6842
e315cd28 6843 rval = qla2x00_fw_ready(base_vha);
d7459527
MH		 6844 if (vha->qpair)
6845 req = vha->qpair->req;
67c2e93a 6846 else
d7459527 6847 req = ha->req_q_map[0];
67c2e93a
AC		 6848 rsp = req->rsp;
6849
2c3dfe3f 6850 if (rval == QLA_SUCCESS) {
e315cd28 6851 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
73208dfd 6852 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
2c3dfe3f
SJ		 6853 }
6854
e315cd28 6855 vha->flags.management_server_logged_in = 0;
2c3dfe3f
SJ		 6856
6857 /* Login to SNS first */
0b91d116
CD		 6858 rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb,
6859 BIT_1);
6860 if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
6861 if (rval2 == QLA_MEMORY_ALLOC_FAILED)
6862 ql_dbg(ql_dbg_init, vha, 0x0120,
6863 "Failed SNS login: loop_id=%x, rval2=%d\n",
6864 NPH_SNS, rval2);
6865 else
6866 ql_dbg(ql_dbg_init, vha, 0x0103,
6867 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x "
6868 "mb[2]=%x mb[6]=%x mb[7]=%x.\n",
6869 NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]);
2c3dfe3f
SJ		 6870 return (QLA_FUNCTION_FAILED);
6871 }
6872
e315cd28
AC		 6873 atomic_set(&vha->loop_down_timer, 0);
6874 atomic_set(&vha->loop_state, LOOP_UP);
6875 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
6876 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
6877 rval = qla2x00_loop_resync(base_vha);
2c3dfe3f
SJ		 6878
6879 return rval;
6880}
4d4df193
HK		 6881
6882/* 84XX Support **************************************************************/
6883
6884static LIST_HEAD(qla_cs84xx_list);
6885static DEFINE_MUTEX(qla_cs84xx_mutex);
6886
6887static struct qla_chip_state_84xx *
e315cd28 6888qla84xx_get_chip(struct scsi_qla_host *vha)
4d4df193
HK		 6889{
6890 struct qla_chip_state_84xx *cs84xx;
e315cd28 6891 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 6892
6893 mutex_lock(&qla_cs84xx_mutex);
6894
6895 /* Find any shared 84xx chip. */
6896 list_for_each_entry(cs84xx, &qla_cs84xx_list, list) {
6897 if (cs84xx->bus == ha->pdev->bus) {
6898 kref_get(&cs84xx->kref);
6899 goto done;
6900 }
6901 }
6902
6903 cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL);
6904 if (!cs84xx)
6905 goto done;
6906
6907 kref_init(&cs84xx->kref);
6908 spin_lock_init(&cs84xx->access_lock);
6909 mutex_init(&cs84xx->fw_update_mutex);
6910 cs84xx->bus = ha->pdev->bus;
6911
6912 list_add_tail(&cs84xx->list, &qla_cs84xx_list);
6913done:
6914 mutex_unlock(&qla_cs84xx_mutex);
6915 return cs84xx;
6916}
6917
6918static void
6919__qla84xx_chip_release(struct kref *kref)
6920{
6921 struct qla_chip_state_84xx *cs84xx =
6922 container_of(kref, struct qla_chip_state_84xx, kref);
6923
6924 mutex_lock(&qla_cs84xx_mutex);
6925 list_del(&cs84xx->list);
6926 mutex_unlock(&qla_cs84xx_mutex);
6927 kfree(cs84xx);
6928}
6929
6930void
e315cd28 6931qla84xx_put_chip(struct scsi_qla_host *vha)
4d4df193 6932{
e315cd28 6933 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 6934 if (ha->cs84xx)
6935 kref_put(&ha->cs84xx->kref, __qla84xx_chip_release);
6936}
6937
6938static int
e315cd28 6939qla84xx_init_chip(scsi_qla_host_t *vha)
4d4df193
HK		 6940{
6941 int rval;
6942 uint16_t status[2];
e315cd28 6943 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 6944
6945 mutex_lock(&ha->cs84xx->fw_update_mutex);
6946
e315cd28 6947 rval = qla84xx_verify_chip(vha, status);
4d4df193
HK		 6948
6949 mutex_unlock(&ha->cs84xx->fw_update_mutex);
6950
6951 return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED:
6952 QLA_SUCCESS;
6953}
3a03eb79
AV		 6954
6955/* 81XX Support **************************************************************/
6956
6957int
6958qla81xx_nvram_config(scsi_qla_host_t *vha)
6959{
6960 int rval;
6961 struct init_cb_81xx *icb;
6962 struct nvram_81xx *nv;
6963 uint32_t *dptr;
6964 uint8_t *dptr1, *dptr2;
6965 uint32_t chksum;
6966 uint16_t cnt;
6967 struct qla_hw_data *ha = vha->hw;
6968
6969 rval = QLA_SUCCESS;
6970 icb = (struct init_cb_81xx *)ha->init_cb;
6971 nv = ha->nvram;
6972
6973 /* Determine NVRAM starting address. */
6974 ha->nvram_size = sizeof(struct nvram_81xx);
3a03eb79 6975 ha->vpd_size = FA_NVRAM_VPD_SIZE;
7ec0effd
AD		 6976 if (IS_P3P_TYPE(ha) || IS_QLA8031(ha))
6977 ha->vpd_size = FA_VPD_SIZE_82XX;
3a03eb79
AV		 6978
6979 /* Get VPD data into cache */
6980 ha->vpd = ha->nvram + VPD_OFFSET;
3d79038f
AV		 6981 ha->isp_ops->read_optrom(vha, ha->vpd, ha->flt_region_vpd << 2,
6982 ha->vpd_size);
3a03eb79
AV		 6983
6984 /* Get NVRAM data into cache and calculate checksum. */
3d79038f 6985 ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2,
3a03eb79 6986 ha->nvram_size);
3d79038f 6987 dptr = (uint32_t *)nv;
da08ef5c
JC		 6988 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++)
6989 chksum += le32_to_cpu(*dptr);
3a03eb79 6990
7c3df132
SK		 6991 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
6992 "Contents of NVRAM:\n");
6993 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
6994 (uint8_t *)nv, ha->nvram_size);
3a03eb79
AV		 6995
6996 /* Bad NVRAM data, set defaults parameters. */
6997 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
6998 || nv->id[3] != ' ' ||
ad950360 6999 nv->nvram_version < cpu_to_le16(ICB_VERSION)) {
3a03eb79 7000 /* Reset NVRAM data. */
7c3df132 7001 ql_log(ql_log_info, vha, 0x0073,
9e336520 7002 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132 7003 "version=0x%x.\n", chksum, nv->id[0],
3a03eb79 7004 le16_to_cpu(nv->nvram_version));
7c3df132
SK		 7005 ql_log(ql_log_info, vha, 0x0074,
7006 "Falling back to functioning (yet invalid -- WWPN) "
7007 "defaults.\n");
3a03eb79
AV		 7008
7009 /*
7010 * Set default initialization control block.
7011 */
7012 memset(nv, 0, ha->nvram_size);
ad950360
BVA		 7013 nv->nvram_version = cpu_to_le16(ICB_VERSION);
7014 nv->version = cpu_to_le16(ICB_VERSION);
98aee70d 7015 nv->frame_payload_size = 2048;
ad950360
BVA		 7016 nv->execution_throttle = cpu_to_le16(0xFFFF);
7017 nv->exchange_count = cpu_to_le16(0);
3a03eb79 7018 nv->port_name[0] = 0x21;
f73cb695 7019 nv->port_name[1] = 0x00 + ha->port_no + 1;
3a03eb79
AV		 7020 nv->port_name[2] = 0x00;
7021 nv->port_name[3] = 0xe0;
7022 nv->port_name[4] = 0x8b;
7023 nv->port_name[5] = 0x1c;
7024 nv->port_name[6] = 0x55;
7025 nv->port_name[7] = 0x86;
7026 nv->node_name[0] = 0x20;
7027 nv->node_name[1] = 0x00;
7028 nv->node_name[2] = 0x00;
7029 nv->node_name[3] = 0xe0;
7030 nv->node_name[4] = 0x8b;
7031 nv->node_name[5] = 0x1c;
7032 nv->node_name[6] = 0x55;
7033 nv->node_name[7] = 0x86;
ad950360
BVA		 7034 nv->login_retry_count = cpu_to_le16(8);
7035 nv->interrupt_delay_timer = cpu_to_le16(0);
7036 nv->login_timeout = cpu_to_le16(0);
3a03eb79 7037 nv->firmware_options_1 =
ad950360
BVA		 7038 cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
7039 nv->firmware_options_2 = cpu_to_le32(2 << 4);
7040 nv->firmware_options_2 |= cpu_to_le32(BIT_12);
7041 nv->firmware_options_3 = cpu_to_le32(2 << 13);
7042 nv->host_p = cpu_to_le32(BIT_11|BIT_10);
7043 nv->efi_parameters = cpu_to_le32(0);
3a03eb79 7044 nv->reset_delay = 5;
ad950360
BVA		 7045 nv->max_luns_per_target = cpu_to_le16(128);
7046 nv->port_down_retry_count = cpu_to_le16(30);
7047 nv->link_down_timeout = cpu_to_le16(180);
eeebcc92 7048 nv->enode_mac[0] = 0x00;
6246b8a1
GM		 7049 nv->enode_mac[1] = 0xC0;
7050 nv->enode_mac[2] = 0xDD;
3a03eb79
AV		 7051 nv->enode_mac[3] = 0x04;
7052 nv->enode_mac[4] = 0x05;
f73cb695 7053 nv->enode_mac[5] = 0x06 + ha->port_no + 1;
3a03eb79
AV		 7054
7055 rval = 1;
7056 }
7057
9e522cd8
AE		 7058 if (IS_T10_PI_CAPABLE(ha))
7059 nv->frame_payload_size &= ~7;
7060
aa230bc5
AE		 7061 qlt_81xx_config_nvram_stage1(vha, nv);
7062
3a03eb79 7063 /* Reset Initialization control block */
773120e4 7064 memset(icb, 0, ha->init_cb_size);
3a03eb79
AV		 7065
7066 /* Copy 1st segment. */
7067 dptr1 = (uint8_t *)icb;
7068 dptr2 = (uint8_t *)&nv->version;
7069 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
7070 while (cnt--)
7071 *dptr1++ = *dptr2++;
7072
7073 icb->login_retry_count = nv->login_retry_count;
7074
7075 /* Copy 2nd segment. */
7076 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
7077 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
7078 cnt = (uint8_t *)&icb->reserved_5 -
7079 (uint8_t *)&icb->interrupt_delay_timer;
7080 while (cnt--)
7081 *dptr1++ = *dptr2++;
7082
7083 memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac));
7084 /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */
7085 if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) {
69e5f1ea
AV		 7086 icb->enode_mac[0] = 0x00;
7087 icb->enode_mac[1] = 0xC0;
7088 icb->enode_mac[2] = 0xDD;
3a03eb79
AV		 7089 icb->enode_mac[3] = 0x04;
7090 icb->enode_mac[4] = 0x05;
f73cb695 7091 icb->enode_mac[5] = 0x06 + ha->port_no + 1;
3a03eb79
AV		 7092 }
7093
b64b0e8f
AV		 7094 /* Use extended-initialization control block. */
7095 memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb));
7096
3a03eb79
AV		 7097 /*
7098 * Setup driver NVRAM options.
7099 */
7100 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
a9083016 7101 "QLE8XXX");
3a03eb79 7102
aa230bc5
AE		 7103 qlt_81xx_config_nvram_stage2(vha, icb);
7104
3a03eb79 7105 /* Use alternate WWN? */
ad950360 7106 if (nv->host_p & cpu_to_le32(BIT_15)) {
3a03eb79
AV		 7107 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
7108 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
7109 }
7110
7111 /* Prepare nodename */
ad950360 7112 if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) {
3a03eb79
AV		 7113 /*
7114 * Firmware will apply the following mask if the nodename was
7115 * not provided.
7116 */
7117 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
7118 icb->node_name[0] &= 0xF0;
7119 }
7120
7121 /* Set host adapter parameters. */
7122 ha->flags.disable_risc_code_load = 0;
7123 ha->flags.enable_lip_reset = 0;
7124 ha->flags.enable_lip_full_login =
7125 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
7126 ha->flags.enable_target_reset =
7127 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
7128 ha->flags.enable_led_scheme = 0;
7129 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
7130
7131 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
7132 (BIT_6 | BIT_5 | BIT_4)) >> 4;
7133
7134 /* save HBA serial number */
7135 ha->serial0 = icb->port_name[5];
7136 ha->serial1 = icb->port_name[6];
7137 ha->serial2 = icb->port_name[7];
7138 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
7139 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
7140
ad950360 7141 icb->execution_throttle = cpu_to_le16(0xFFFF);
3a03eb79
AV		 7142
7143 ha->retry_count = le16_to_cpu(nv->login_retry_count);
7144
7145 /* Set minimum login_timeout to 4 seconds. */
7146 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
7147 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
7148 if (le16_to_cpu(nv->login_timeout) < 4)
ad950360 7149 nv->login_timeout = cpu_to_le16(4);
3a03eb79 7150 ha->login_timeout = le16_to_cpu(nv->login_timeout);
3a03eb79
AV		 7151
7152 /* Set minimum RATOV to 100 tenths of a second. */
7153 ha->r_a_tov = 100;
7154
7155 ha->loop_reset_delay = nv->reset_delay;
7156
7157 /* Link Down Timeout = 0:
7158 *
7ec0effd 7159 * When Port Down timer expires we will start returning
3a03eb79
AV		 7160 * I/O's to OS with "DID_NO_CONNECT".
7161 *
7162 * Link Down Timeout != 0:
7163 *
7164 * The driver waits for the link to come up after link down
7165 * before returning I/Os to OS with "DID_NO_CONNECT".
7166 */
7167 if (le16_to_cpu(nv->link_down_timeout) == 0) {
7168 ha->loop_down_abort_time =
7169 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
7170 } else {
7171 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
7172 ha->loop_down_abort_time =
7173 (LOOP_DOWN_TIME - ha->link_down_timeout);
7174 }
7175
7176 /* Need enough time to try and get the port back. */
7177 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
7178 if (qlport_down_retry)
7179 ha->port_down_retry_count = qlport_down_retry;
7180
7181 /* Set login_retry_count */
7182 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
7183 if (ha->port_down_retry_count ==
7184 le16_to_cpu(nv->port_down_retry_count) &&
7185 ha->port_down_retry_count > 3)
7186 ha->login_retry_count = ha->port_down_retry_count;
7187 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
7188 ha->login_retry_count = ha->port_down_retry_count;
7189 if (ql2xloginretrycount)
7190 ha->login_retry_count = ql2xloginretrycount;
7191
6246b8a1 7192 /* if not running MSI-X we need handshaking on interrupts */
f73cb695 7193 if (!vha->hw->flags.msix_enabled && (IS_QLA83XX(ha) || IS_QLA27XX(ha)))
ad950360 7194 icb->firmware_options_2 |= cpu_to_le32(BIT_22);
6246b8a1 7195
3a03eb79
AV		 7196 /* Enable ZIO. */
7197 if (!vha->flags.init_done) {
7198 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
7199 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
7200 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
7201 le16_to_cpu(icb->interrupt_delay_timer): 2;
7202 }
ad950360 7203 icb->firmware_options_2 &= cpu_to_le32(
3a03eb79
AV		 7204 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
7205 vha->flags.process_response_queue = 0;
7206 if (ha->zio_mode != QLA_ZIO_DISABLED) {
7207 ha->zio_mode = QLA_ZIO_MODE_6;
7208
7c3df132 7209 ql_log(ql_log_info, vha, 0x0075,
3a03eb79 7210 "ZIO mode %d enabled; timer delay (%d us).\n",
7c3df132
SK		 7211 ha->zio_mode,
7212 ha->zio_timer * 100);
3a03eb79
AV		 7213
7214 icb->firmware_options_2 |= cpu_to_le32(
7215 (uint32_t)ha->zio_mode);
7216 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
7217 vha->flags.process_response_queue = 1;
7218 }
7219
41dc529a
QT		 7220 /* enable RIDA Format2 */
7221 if (qla_tgt_mode_enabled(vha) || qla_dual_mode_enabled(vha))
7222 icb->firmware_options_3 |= BIT_0;
7223
3a03eb79 7224 if (rval) {
7c3df132
SK		 7225 ql_log(ql_log_warn, vha, 0x0076,
7226 "NVRAM configuration failed.\n");
3a03eb79
AV		 7227 }
7228 return (rval);
7229}
7230
a9083016
GM		 7231int
7232qla82xx_restart_isp(scsi_qla_host_t *vha)
7233{
7234 int status, rval;
a9083016
GM		 7235 struct qla_hw_data *ha = vha->hw;
7236 struct req_que *req = ha->req_q_map[0];
7237 struct rsp_que *rsp = ha->rsp_q_map[0];
7238 struct scsi_qla_host *vp;
feafb7b1 7239 unsigned long flags;
a9083016
GM		 7240
7241 status = qla2x00_init_rings(vha);
7242 if (!status) {
7243 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
7244 ha->flags.chip_reset_done = 1;
7245
7246 status = qla2x00_fw_ready(vha);
7247 if (!status) {
a9083016
GM		 7248 /* Issue a marker after FW becomes ready. */
7249 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
a9083016 7250 vha->flags.online = 1;
7108b76e 7251 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
a9083016
GM		 7252 }
7253
7254 /* if no cable then assume it's good */
7255 if ((vha->device_flags & DFLG_NO_CABLE))
7256 status = 0;
a9083016
GM		 7257 }
7258
7259 if (!status) {
7260 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
7261
7262 if (!atomic_read(&vha->loop_down_timer)) {
7263 /*
7264 * Issue marker command only when we are going
7265 * to start the I/O .
7266 */
7267 vha->marker_needed = 1;
7268 }
7269
a9083016
GM		 7270 ha->isp_ops->enable_intrs(ha);
7271
7272 ha->isp_abort_cnt = 0;
7273 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
7274
53296788 7275 /* Update the firmware version */
3173167f 7276 status = qla82xx_check_md_needed(vha);
53296788 7277
a9083016
GM		 7278 if (ha->fce) {
7279 ha->flags.fce_enabled = 1;
7280 memset(ha->fce, 0,
7281 fce_calc_size(ha->fce_bufs));
7282 rval = qla2x00_enable_fce_trace(vha,
7283 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
7284 &ha->fce_bufs);
7285 if (rval) {
cfb0919c 7286 ql_log(ql_log_warn, vha, 0x8001,
7c3df132
SK		 7287 "Unable to reinitialize FCE (%d).\n",
7288 rval);
a9083016
GM		 7289 ha->flags.fce_enabled = 0;
7290 }
7291 }
7292
7293 if (ha->eft) {
7294 memset(ha->eft, 0, EFT_SIZE);
7295 rval = qla2x00_enable_eft_trace(vha,
7296 ha->eft_dma, EFT_NUM_BUFFERS);
7297 if (rval) {
cfb0919c 7298 ql_log(ql_log_warn, vha, 0x8010,
7c3df132
SK		 7299 "Unable to reinitialize EFT (%d).\n",
7300 rval);
a9083016
GM		 7301 }
7302 }
a9083016
GM		 7303 }
7304
7305 if (!status) {
cfb0919c 7306 ql_dbg(ql_dbg_taskm, vha, 0x8011,
7c3df132 7307 "qla82xx_restart_isp succeeded.\n");
feafb7b1
AE		 7308
7309 spin_lock_irqsave(&ha->vport_slock, flags);
7310 list_for_each_entry(vp, &ha->vp_list, list) {
7311 if (vp->vp_idx) {
7312 atomic_inc(&vp->vref_count);
7313 spin_unlock_irqrestore(&ha->vport_slock, flags);
7314
a9083016 7315 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 7316
7317 spin_lock_irqsave(&ha->vport_slock, flags);
7318 atomic_dec(&vp->vref_count);
7319 }
a9083016 7320 }
feafb7b1
AE		 7321 spin_unlock_irqrestore(&ha->vport_slock, flags);
7322
a9083016 7323 } else {
cfb0919c 7324 ql_log(ql_log_warn, vha, 0x8016,
7c3df132 7325 "qla82xx_restart_isp **** FAILED ****.\n");
a9083016
GM		 7326 }
7327
7328 return status;
7329}
7330
3a03eb79 7331void
ae97c91e 7332qla81xx_update_fw_options(scsi_qla_host_t *vha)
3a03eb79 7333{
ae97c91e
AV		 7334 struct qla_hw_data *ha = vha->hw;
7335
f198cafa
HM		 7336 /* Hold status IOCBs until ABTS response received. */
7337 if (ql2xfwholdabts)
7338 ha->fw_options[3] |= BIT_12;
7339
088d09d4
GM		 7340 /* Set Retry FLOGI in case of P2P connection */
7341 if (ha->operating_mode == P2P) {
7342 ha->fw_options[2] |= BIT_3;
7343 ql_dbg(ql_dbg_disc, vha, 0x2103,
7344 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
7345 __func__, ha->fw_options[2]);
7346 }
7347
41dc529a
QT		 7348 /* Move PUREX, ABTS RX & RIDA to ATIOQ */
7349 if (ql2xmvasynctoatio) {
7350 if (qla_tgt_mode_enabled(vha) ||
7351 qla_dual_mode_enabled(vha))
7352 ha->fw_options[2] |= BIT_11;
7353 else
7354 ha->fw_options[2] &= ~BIT_11;
7355 }
7356
7357 if (ql2xetsenable) {
7358 /* Enable ETS Burst. */
7359 memset(ha->fw_options, 0, sizeof(ha->fw_options));
7360 ha->fw_options[2] |= BIT_9;
7361 }
7362
7363 ql_dbg(ql_dbg_init, vha, 0xffff,
7364 "%s, add FW options 1-3 = 0x%04x 0x%04x 0x%04x mode %x\n",
7365 __func__, ha->fw_options[1], ha->fw_options[2],
7366 ha->fw_options[3], vha->host->active_mode);
ae97c91e 7367
ae97c91e 7368 qla2x00_set_fw_options(vha, ha->fw_options);
3a03eb79 7369}
09ff701a
SR		 7370
7371/*
7372 * qla24xx_get_fcp_prio
7373 * Gets the fcp cmd priority value for the logged in port.
7374 * Looks for a match of the port descriptors within
7375 * each of the fcp prio config entries. If a match is found,
7376 * the tag (priority) value is returned.
7377 *
7378 * Input:
21090cbe 7379 * vha = scsi host structure pointer.
09ff701a
SR		 7380 * fcport = port structure pointer.
7381 *
7382 * Return:
6c452a45 7383 * non-zero (if found)
f28a0a96 7384 * -1 (if not found)
09ff701a
SR		 7385 *
7386 * Context:
7387 * Kernel context
7388 */
f28a0a96 7389static int
09ff701a
SR		 7390qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
7391{
7392 int i, entries;
7393 uint8_t pid_match, wwn_match;
f28a0a96 7394 int priority;
09ff701a
SR		 7395 uint32_t pid1, pid2;
7396 uint64_t wwn1, wwn2;
7397 struct qla_fcp_prio_entry *pri_entry;
7398 struct qla_hw_data *ha = vha->hw;
7399
7400 if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled)
f28a0a96 7401 return -1;
09ff701a 7402
f28a0a96 7403 priority = -1;
09ff701a
SR		 7404 entries = ha->fcp_prio_cfg->num_entries;
7405 pri_entry = &ha->fcp_prio_cfg->entry[0];
7406
7407 for (i = 0; i < entries; i++) {
7408 pid_match = wwn_match = 0;
7409
7410 if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) {
7411 pri_entry++;
7412 continue;
7413 }
7414
7415 /* check source pid for a match */
7416 if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) {
7417 pid1 = pri_entry->src_pid & INVALID_PORT_ID;
7418 pid2 = vha->d_id.b24 & INVALID_PORT_ID;
7419 if (pid1 == INVALID_PORT_ID)
7420 pid_match++;
7421 else if (pid1 == pid2)
7422 pid_match++;
7423 }
7424
7425 /* check destination pid for a match */
7426 if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) {
7427 pid1 = pri_entry->dst_pid & INVALID_PORT_ID;
7428 pid2 = fcport->d_id.b24 & INVALID_PORT_ID;
7429 if (pid1 == INVALID_PORT_ID)
7430 pid_match++;
7431 else if (pid1 == pid2)
7432 pid_match++;
7433 }
7434
7435 /* check source WWN for a match */
7436 if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) {
7437 wwn1 = wwn_to_u64(vha->port_name);
7438 wwn2 = wwn_to_u64(pri_entry->src_wwpn);
7439 if (wwn2 == (uint64_t)-1)
7440 wwn_match++;
7441 else if (wwn1 == wwn2)
7442 wwn_match++;
7443 }
7444
7445 /* check destination WWN for a match */
7446 if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) {
7447 wwn1 = wwn_to_u64(fcport->port_name);
7448 wwn2 = wwn_to_u64(pri_entry->dst_wwpn);
7449 if (wwn2 == (uint64_t)-1)
7450 wwn_match++;
7451 else if (wwn1 == wwn2)
7452 wwn_match++;
7453 }
7454
7455 if (pid_match == 2 || wwn_match == 2) {
7456 /* Found a matching entry */
7457 if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID)
7458 priority = pri_entry->tag;
7459 break;
7460 }
7461
7462 pri_entry++;
7463 }
7464
7465 return priority;
7466}
7467
7468/*
7469 * qla24xx_update_fcport_fcp_prio
7470 * Activates fcp priority for the logged in fc port
7471 *
7472 * Input:
21090cbe 7473 * vha = scsi host structure pointer.
09ff701a
SR		 7474 * fcp = port structure pointer.
7475 *
7476 * Return:
7477 * QLA_SUCCESS or QLA_FUNCTION_FAILED
7478 *
7479 * Context:
7480 * Kernel context.
7481 */
7482int
21090cbe 7483qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
09ff701a
SR		 7484{
7485 int ret;
f28a0a96 7486 int priority;
09ff701a
SR		 7487 uint16_t mb[5];
7488
21090cbe
MI		 7489 if (fcport->port_type != FCT_TARGET ||
7490 fcport->loop_id == FC_NO_LOOP_ID)
09ff701a
SR		 7491 return QLA_FUNCTION_FAILED;
7492
21090cbe 7493 priority = qla24xx_get_fcp_prio(vha, fcport);
f28a0a96
AV		 7494 if (priority < 0)
7495 return QLA_FUNCTION_FAILED;
7496
7ec0effd 7497 if (IS_P3P_TYPE(vha->hw)) {
a00f6296
SK		 7498 fcport->fcp_prio = priority & 0xf;
7499 return QLA_SUCCESS;
7500 }
7501
21090cbe 7502 ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb);
cfb0919c
CD		 7503 if (ret == QLA_SUCCESS) {
7504 if (fcport->fcp_prio != priority)
7505 ql_dbg(ql_dbg_user, vha, 0x709e,
7506 "Updated FCP_CMND priority - value=%d loop_id=%d "
7507 "port_id=%02x%02x%02x.\n", priority,
7508 fcport->loop_id, fcport->d_id.b.domain,
7509 fcport->d_id.b.area, fcport->d_id.b.al_pa);
a00f6296 7510 fcport->fcp_prio = priority & 0xf;
cfb0919c 7511 } else
7c3df132 7512 ql_dbg(ql_dbg_user, vha, 0x704f,
cfb0919c
CD		 7513 "Unable to update FCP_CMND priority - ret=0x%x for "
7514 "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id,
7515 fcport->d_id.b.domain, fcport->d_id.b.area,
7516 fcport->d_id.b.al_pa);
09ff701a
SR		 7517 return ret;
7518}
7519
7520/*
7521 * qla24xx_update_all_fcp_prio
7522 * Activates fcp priority for all the logged in ports
7523 *
7524 * Input:
7525 * ha = adapter block pointer.
7526 *
7527 * Return:
7528 * QLA_SUCCESS or QLA_FUNCTION_FAILED
7529 *
7530 * Context:
7531 * Kernel context.
7532 */
7533int
7534qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha)
7535{
7536 int ret;
7537 fc_port_t *fcport;
7538
7539 ret = QLA_FUNCTION_FAILED;
7540 /* We need to set priority for all logged in ports */
7541 list_for_each_entry(fcport, &vha->vp_fcports, list)
7542 ret = qla24xx_update_fcport_fcp_prio(vha, fcport);
7543
7544 return ret;
7545}
d7459527
MH		 7546
7547struct qla_qpair *qla2xxx_create_qpair(struct scsi_qla_host *vha, int qos, int vp_idx)
7548{
7549 int rsp_id = 0;
7550 int req_id = 0;
7551 int i;
7552 struct qla_hw_data *ha = vha->hw;
7553 uint16_t qpair_id = 0;
7554 struct qla_qpair *qpair = NULL;
7555 struct qla_msix_entry *msix;
7556
7557 if (!(ha->fw_attributes & BIT_6) || !ha->flags.msix_enabled) {
7558 ql_log(ql_log_warn, vha, 0x00181,
7559 "FW/Driver is not multi-queue capable.\n");
7560 return NULL;
7561 }
7562
7563 if (ql2xmqsupport) {
7564 qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
7565 if (qpair == NULL) {
7566 ql_log(ql_log_warn, vha, 0x0182,
7567 "Failed to allocate memory for queue pair.\n");
7568 return NULL;
7569 }
7570 memset(qpair, 0, sizeof(struct qla_qpair));
7571
7572 qpair->hw = vha->hw;
25ff6af1 7573 qpair->vha = vha;
d7459527
MH		 7574
7575 /* Assign available que pair id */
7576 mutex_lock(&ha->mq_lock);
7577 qpair_id = find_first_zero_bit(ha->qpair_qid_map, ha->max_qpairs);
7578 if (qpair_id >= ha->max_qpairs) {
7579 mutex_unlock(&ha->mq_lock);
7580 ql_log(ql_log_warn, vha, 0x0183,
7581 "No resources to create additional q pair.\n");
7582 goto fail_qid_map;
7583 }
7584 set_bit(qpair_id, ha->qpair_qid_map);
7585 ha->queue_pair_map[qpair_id] = qpair;
7586 qpair->id = qpair_id;
7587 qpair->vp_idx = vp_idx;
7588
7589 for (i = 0; i < ha->msix_count; i++) {
093df737 7590 msix = &ha->msix_entries[i];
d7459527
MH		 7591 if (msix->in_use)
7592 continue;
7593 qpair->msix = msix;
7594 ql_log(ql_dbg_multiq, vha, 0xc00f,
7595 "Vector %x selected for qpair\n", msix->vector);
7596 break;
7597 }
7598 if (!qpair->msix) {
7599 ql_log(ql_log_warn, vha, 0x0184,
7600 "Out of MSI-X vectors!.\n");
7601 goto fail_msix;
7602 }
7603
7604 qpair->msix->in_use = 1;
7605 list_add_tail(&qpair->qp_list_elem, &vha->qp_list);
7606
7607 mutex_unlock(&ha->mq_lock);
7608
7609 /* Create response queue first */
7610 rsp_id = qla25xx_create_rsp_que(ha, 0, 0, 0, qpair);
7611 if (!rsp_id) {
7612 ql_log(ql_log_warn, vha, 0x0185,
7613 "Failed to create response queue.\n");
7614 goto fail_rsp;
7615 }
7616
7617 qpair->rsp = ha->rsp_q_map[rsp_id];
7618
7619 /* Create request queue */
7620 req_id = qla25xx_create_req_que(ha, 0, vp_idx, 0, rsp_id, qos);
7621 if (!req_id) {
7622 ql_log(ql_log_warn, vha, 0x0186,
7623 "Failed to create request queue.\n");
7624 goto fail_req;
7625 }
7626
7627 qpair->req = ha->req_q_map[req_id];
7628 qpair->rsp->req = qpair->req;
7629
7630 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
7631 if (ha->fw_attributes & BIT_4)
7632 qpair->difdix_supported = 1;
7633 }
7634
7635 qpair->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
7636 if (!qpair->srb_mempool) {
7637 ql_log(ql_log_warn, vha, 0x0191,
7638 "Failed to create srb mempool for qpair %d\n",
7639 qpair->id);
7640 goto fail_mempool;
7641 }
7642
7643 /* Mark as online */
7644 qpair->online = 1;
7645
7646 if (!vha->flags.qpairs_available)
7647 vha->flags.qpairs_available = 1;
7648
7649 ql_dbg(ql_dbg_multiq, vha, 0xc00d,
7650 "Request/Response queue pair created, id %d\n",
7651 qpair->id);
7652 ql_dbg(ql_dbg_init, vha, 0x0187,
7653 "Request/Response queue pair created, id %d\n",
7654 qpair->id);
7655 }
7656 return qpair;
7657
7658fail_mempool:
7659fail_req:
7660 qla25xx_delete_rsp_que(vha, qpair->rsp);
7661fail_rsp:
7662 mutex_lock(&ha->mq_lock);
7663 qpair->msix->in_use = 0;
7664 list_del(&qpair->qp_list_elem);
7665 if (list_empty(&vha->qp_list))
7666 vha->flags.qpairs_available = 0;
7667fail_msix:
7668 ha->queue_pair_map[qpair_id] = NULL;
7669 clear_bit(qpair_id, ha->qpair_qid_map);
7670 mutex_unlock(&ha->mq_lock);
7671fail_qid_map:
7672 kfree(qpair);
7673 return NULL;
7674}
7675
7676int qla2xxx_delete_qpair(struct scsi_qla_host *vha, struct qla_qpair *qpair)
7677{
7678 int ret;
7679 struct qla_hw_data *ha = qpair->hw;
7680
7681 qpair->delete_in_progress = 1;
7682 while (atomic_read(&qpair->ref_count))
7683 msleep(500);
7684
7685 ret = qla25xx_delete_req_que(vha, qpair->req);
7686 if (ret != QLA_SUCCESS)
7687 goto fail;
7688 ret = qla25xx_delete_rsp_que(vha, qpair->rsp);
7689 if (ret != QLA_SUCCESS)
7690 goto fail;
7691
7692 mutex_lock(&ha->mq_lock);
7693 ha->queue_pair_map[qpair->id] = NULL;
7694 clear_bit(qpair->id, ha->qpair_qid_map);
7695 list_del(&qpair->qp_list_elem);
7696 if (list_empty(&vha->qp_list))
7697 vha->flags.qpairs_available = 0;
7698 mempool_destroy(qpair->srb_mempool);
7699 kfree(qpair);
7700 mutex_unlock(&ha->mq_lock);
7701
7702 return QLA_SUCCESS;
7703fail:
7704 return ret;
7705}
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