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[SCSI] qla2xxx: Fix Task Management command asynchronous handling
[mirror_ubuntu-zesty-kernel.git] / drivers / scsi / qla2xxx / qla_init.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
1e63395c 3 * Copyright (c) 2003-2013 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
73208dfd 8#include "qla_gbl.h"
1da177e4
LT		 9
10#include <linux/delay.h>
5a0e3ad6 11#include <linux/slab.h>
0107109e 12#include <linux/vmalloc.h>
1da177e4
LT		 13
14#include "qla_devtbl.h"
15
4e08df3f
DM		 16#ifdef CONFIG_SPARC
17#include <asm/prom.h>
4e08df3f
DM		 18#endif
19
2d70c103
NB		 20#include <target/target_core_base.h>
21#include "qla_target.h"
22
1da177e4
LT		 23/*
24* QLogic ISP2x00 Hardware Support Function Prototypes.
25*/
1da177e4 26static int qla2x00_isp_firmware(scsi_qla_host_t *);
1da177e4 27static int qla2x00_setup_chip(scsi_qla_host_t *);
1da177e4
LT		 28static int qla2x00_fw_ready(scsi_qla_host_t *);
29static int qla2x00_configure_hba(scsi_qla_host_t *);
1da177e4
LT		 30static int qla2x00_configure_loop(scsi_qla_host_t *);
31static int qla2x00_configure_local_loop(scsi_qla_host_t *);
1da177e4
LT		 32static int qla2x00_configure_fabric(scsi_qla_host_t *);
33static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *, struct list_head *);
1da177e4
LT		 34static int qla2x00_fabric_dev_login(scsi_qla_host_t *, fc_port_t *,
35 uint16_t *);
1da177e4
LT		 36
37static int qla2x00_restart_isp(scsi_qla_host_t *);
1da177e4 38
4d4df193
HK		 39static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *);
40static int qla84xx_init_chip(scsi_qla_host_t *);
73208dfd 41static int qla25xx_init_queues(struct qla_hw_data *);
4d4df193 42
ac280b67
AV		 43/* SRB Extensions ---------------------------------------------------------- */
44
9ba56b95
GM		 45void
46qla2x00_sp_timeout(unsigned long __data)
ac280b67
AV		 47{
48 srb_t *sp = (srb_t *)__data;
4916392b 49 struct srb_iocb *iocb;
ac280b67
AV		 50 fc_port_t *fcport = sp->fcport;
51 struct qla_hw_data *ha = fcport->vha->hw;
52 struct req_que *req;
53 unsigned long flags;
54
55 spin_lock_irqsave(&ha->hardware_lock, flags);
56 req = ha->req_q_map[0];
57 req->outstanding_cmds[sp->handle] = NULL;
9ba56b95 58 iocb = &sp->u.iocb_cmd;
4916392b 59 iocb->timeout(sp);
9ba56b95 60 sp->free(fcport->vha, sp);
6ac52608 61 spin_unlock_irqrestore(&ha->hardware_lock, flags);
ac280b67
AV		 62}
63
9ba56b95
GM		 64void
65qla2x00_sp_free(void *data, void *ptr)
ac280b67 66{
9ba56b95
GM		 67 srb_t *sp = (srb_t *)ptr;
68 struct srb_iocb *iocb = &sp->u.iocb_cmd;
69 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
ac280b67 70
4d97cc53 71 del_timer(&iocb->timer);
b00ee7d7 72 qla2x00_rel_sp(vha, sp);
ac280b67
AV		 73}
74
ac280b67
AV		 75/* Asynchronous Login/Logout Routines -------------------------------------- */
76
a9b6f722 77unsigned long
5b91490e
AV		 78qla2x00_get_async_timeout(struct scsi_qla_host *vha)
79{
80 unsigned long tmo;
81 struct qla_hw_data *ha = vha->hw;
82
83 /* Firmware should use switch negotiated r_a_tov for timeout. */
84 tmo = ha->r_a_tov / 10 * 2;
8ae6d9c7
GM		 85 if (IS_QLAFX00(ha)) {
86 tmo = FX00_DEF_RATOV * 2;
87 } else if (!IS_FWI2_CAPABLE(ha)) {
5b91490e
AV		 88 /*
89 * Except for earlier ISPs where the timeout is seeded from the
90 * initialization control block.
91 */
92 tmo = ha->login_timeout;
93 }
94 return tmo;
95}
ac280b67
AV		 96
97static void
9ba56b95 98qla2x00_async_iocb_timeout(void *data)
ac280b67 99{
9ba56b95 100 srb_t *sp = (srb_t *)data;
ac280b67 101 fc_port_t *fcport = sp->fcport;
ac280b67 102
7c3df132 103 ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
cfb0919c 104 "Async-%s timeout - hdl=%x portid=%02x%02x%02x.\n",
9ba56b95 105 sp->name, sp->handle, fcport->d_id.b.domain, fcport->d_id.b.area,
7c3df132 106 fcport->d_id.b.al_pa);
ac280b67 107
5ff1d584 108 fcport->flags &= ~FCF_ASYNC_SENT;
9ba56b95
GM		 109 if (sp->type == SRB_LOGIN_CMD) {
110 struct srb_iocb *lio = &sp->u.iocb_cmd;
ac280b67 111 qla2x00_post_async_logout_work(fcport->vha, fcport, NULL);
6ac52608
AV		 112 /* Retry as needed. */
113 lio->u.logio.data[0] = MBS_COMMAND_ERROR;
114 lio->u.logio.data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
115 QLA_LOGIO_LOGIN_RETRIED : 0;
116 qla2x00_post_async_login_done_work(fcport->vha, fcport,
117 lio->u.logio.data);
118 }
ac280b67
AV		 119}
120
99b0bec7 121static void
9ba56b95 122qla2x00_async_login_sp_done(void *data, void *ptr, int res)
99b0bec7 123{
9ba56b95
GM		 124 srb_t *sp = (srb_t *)ptr;
125 struct srb_iocb *lio = &sp->u.iocb_cmd;
126 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
127
128 if (!test_bit(UNLOADING, &vha->dpc_flags))
129 qla2x00_post_async_login_done_work(sp->fcport->vha, sp->fcport,
130 lio->u.logio.data);
131 sp->free(sp->fcport->vha, sp);
99b0bec7
AV		 132}
133
ac280b67
AV		 134int
135qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport,
136 uint16_t *data)
137{
ac280b67 138 srb_t *sp;
4916392b 139 struct srb_iocb *lio;
ac280b67
AV		 140 int rval;
141
142 rval = QLA_FUNCTION_FAILED;
9ba56b95 143 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 144 if (!sp)
145 goto done;
146
9ba56b95
GM		 147 sp->type = SRB_LOGIN_CMD;
148 sp->name = "login";
149 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
150
151 lio = &sp->u.iocb_cmd;
3822263e 152 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 153 sp->done = qla2x00_async_login_sp_done;
4916392b 154 lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI;
ac280b67 155 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 156 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
ac280b67
AV		 157 rval = qla2x00_start_sp(sp);
158 if (rval != QLA_SUCCESS)
159 goto done_free_sp;
160
7c3df132 161 ql_dbg(ql_dbg_disc, vha, 0x2072,
cfb0919c
CD		 162 "Async-login - hdl=%x, loopid=%x portid=%02x%02x%02x "
163 "retries=%d.\n", sp->handle, fcport->loop_id,
164 fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
165 fcport->login_retry);
ac280b67
AV		 166 return rval;
167
168done_free_sp:
9ba56b95 169 sp->free(fcport->vha, sp);
ac280b67
AV		 170done:
171 return rval;
172}
173
99b0bec7 174static void
9ba56b95 175qla2x00_async_logout_sp_done(void *data, void *ptr, int res)
99b0bec7 176{
9ba56b95
GM		 177 srb_t *sp = (srb_t *)ptr;
178 struct srb_iocb *lio = &sp->u.iocb_cmd;
179 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
180
181 if (!test_bit(UNLOADING, &vha->dpc_flags))
182 qla2x00_post_async_logout_done_work(sp->fcport->vha, sp->fcport,
183 lio->u.logio.data);
184 sp->free(sp->fcport->vha, sp);
99b0bec7
AV		 185}
186
ac280b67
AV		 187int
188qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport)
189{
ac280b67 190 srb_t *sp;
4916392b 191 struct srb_iocb *lio;
ac280b67
AV		 192 int rval;
193
194 rval = QLA_FUNCTION_FAILED;
9ba56b95 195 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 196 if (!sp)
197 goto done;
198
9ba56b95
GM		 199 sp->type = SRB_LOGOUT_CMD;
200 sp->name = "logout";
201 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
202
203 lio = &sp->u.iocb_cmd;
3822263e 204 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 205 sp->done = qla2x00_async_logout_sp_done;
ac280b67
AV		 206 rval = qla2x00_start_sp(sp);
207 if (rval != QLA_SUCCESS)
208 goto done_free_sp;
209
7c3df132 210 ql_dbg(ql_dbg_disc, vha, 0x2070,
cfb0919c
CD		 211 "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
212 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
213 fcport->d_id.b.area, fcport->d_id.b.al_pa);
ac280b67
AV		 214 return rval;
215
216done_free_sp:
9ba56b95 217 sp->free(fcport->vha, sp);
ac280b67
AV		 218done:
219 return rval;
220}
221
5ff1d584 222static void
9ba56b95 223qla2x00_async_adisc_sp_done(void *data, void *ptr, int res)
5ff1d584 224{
9ba56b95
GM		 225 srb_t *sp = (srb_t *)ptr;
226 struct srb_iocb *lio = &sp->u.iocb_cmd;
227 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
228
229 if (!test_bit(UNLOADING, &vha->dpc_flags))
230 qla2x00_post_async_adisc_done_work(sp->fcport->vha, sp->fcport,
231 lio->u.logio.data);
232 sp->free(sp->fcport->vha, sp);
5ff1d584
AV		 233}
234
235int
236qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport,
237 uint16_t *data)
238{
5ff1d584 239 srb_t *sp;
4916392b 240 struct srb_iocb *lio;
5ff1d584
AV		 241 int rval;
242
243 rval = QLA_FUNCTION_FAILED;
9ba56b95 244 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
5ff1d584
AV		 245 if (!sp)
246 goto done;
247
9ba56b95
GM		 248 sp->type = SRB_ADISC_CMD;
249 sp->name = "adisc";
250 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
251
252 lio = &sp->u.iocb_cmd;
3822263e 253 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 254 sp->done = qla2x00_async_adisc_sp_done;
5ff1d584 255 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 256 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
5ff1d584
AV		 257 rval = qla2x00_start_sp(sp);
258 if (rval != QLA_SUCCESS)
259 goto done_free_sp;
260
7c3df132 261 ql_dbg(ql_dbg_disc, vha, 0x206f,
cfb0919c
CD		 262 "Async-adisc - hdl=%x loopid=%x portid=%02x%02x%02x.\n",
263 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
264 fcport->d_id.b.area, fcport->d_id.b.al_pa);
5ff1d584
AV		 265 return rval;
266
267done_free_sp:
9ba56b95 268 sp->free(fcport->vha, sp);
5ff1d584
AV		 269done:
270 return rval;
271}
272
3822263e 273static void
faef62d1 274qla2x00_tmf_iocb_timeout(void *data)
3822263e 275{
faef62d1
AB		 276 srb_t *sp = (srb_t *)data;
277 struct srb_iocb *tmf = &sp->u.iocb_cmd;
3822263e 278
faef62d1
AB		 279 tmf->u.tmf.comp_status = CS_TIMEOUT;
280 complete(&tmf->u.tmf.comp);
281}
9ba56b95 282
faef62d1
AB		 283static void
284qla2x00_tmf_sp_done(void *data, void *ptr, int res)
285{
286 srb_t *sp = (srb_t *)ptr;
287 struct srb_iocb *tmf = &sp->u.iocb_cmd;
288 complete(&tmf->u.tmf.comp);
3822263e
MI		 289}
290
291int
faef62d1 292qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t flags, uint32_t lun,
3822263e
MI		 293 uint32_t tag)
294{
295 struct scsi_qla_host *vha = fcport->vha;
faef62d1 296 struct srb_iocb *tm_iocb;
3822263e 297 srb_t *sp;
faef62d1 298 int rval = QLA_FUNCTION_FAILED;
3822263e 299
9ba56b95 300 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
3822263e
MI		 301 if (!sp)
302 goto done;
303
faef62d1 304 tm_iocb = &sp->u.iocb_cmd;
9ba56b95
GM		 305 sp->type = SRB_TM_CMD;
306 sp->name = "tmf";
faef62d1
AB		 307 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
308 tm_iocb->u.tmf.flags = flags;
309 tm_iocb->u.tmf.lun = lun;
310 tm_iocb->u.tmf.data = tag;
311 sp->done = qla2x00_tmf_sp_done;
312 tm_iocb->timeout = qla2x00_tmf_iocb_timeout;
313 init_completion(&tm_iocb->u.tmf.comp);
3822263e
MI		 314
315 rval = qla2x00_start_sp(sp);
316 if (rval != QLA_SUCCESS)
317 goto done_free_sp;
318
7c3df132 319 ql_dbg(ql_dbg_taskm, vha, 0x802f,
cfb0919c
CD		 320 "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
321 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
322 fcport->d_id.b.area, fcport->d_id.b.al_pa);
faef62d1
AB		 323
324 wait_for_completion(&tm_iocb->u.tmf.comp);
325
326 rval = tm_iocb->u.tmf.comp_status == CS_COMPLETE ?
327 QLA_SUCCESS : QLA_FUNCTION_FAILED;
328
329 if ((rval != QLA_SUCCESS) || tm_iocb->u.tmf.data) {
330 ql_dbg(ql_dbg_taskm, vha, 0x8030,
331 "TM IOCB failed (%x).\n", rval);
332 }
333
334 if (!test_bit(UNLOADING, &vha->dpc_flags) && !IS_QLAFX00(vha->hw)) {
335 flags = tm_iocb->u.tmf.flags;
336 lun = (uint16_t)tm_iocb->u.tmf.lun;
337
338 /* Issue Marker IOCB */
339 qla2x00_marker(vha, vha->hw->req_q_map[0],
340 vha->hw->rsp_q_map[0], sp->fcport->loop_id, lun,
341 flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
342 }
3822263e
MI		 343
344done_free_sp:
faef62d1 345 sp->free(vha, sp);
3822263e
MI		 346done:
347 return rval;
348}
349
4916392b 350void
ac280b67
AV		 351qla2x00_async_login_done(struct scsi_qla_host *vha, fc_port_t *fcport,
352 uint16_t *data)
353{
354 int rval;
ac280b67
AV		 355
356 switch (data[0]) {
357 case MBS_COMMAND_COMPLETE:
a4f92a32
AV		 358 /*
359 * Driver must validate login state - If PRLI not complete,
360 * force a relogin attempt via implicit LOGO, PLOGI, and PRLI
361 * requests.
362 */
363 rval = qla2x00_get_port_database(vha, fcport, 0);
0eba25df
AE		 364 if (rval == QLA_NOT_LOGGED_IN) {
365 fcport->flags &= ~FCF_ASYNC_SENT;
366 fcport->flags |= FCF_LOGIN_NEEDED;
367 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
368 break;
369 }
370
a4f92a32
AV		 371 if (rval != QLA_SUCCESS) {
372 qla2x00_post_async_logout_work(vha, fcport, NULL);
373 qla2x00_post_async_login_work(vha, fcport, NULL);
374 break;
375 }
99b0bec7 376 if (fcport->flags & FCF_FCP2_DEVICE) {
5ff1d584
AV		 377 qla2x00_post_async_adisc_work(vha, fcport, data);
378 break;
99b0bec7
AV		 379 }
380 qla2x00_update_fcport(vha, fcport);
ac280b67
AV		 381 break;
382 case MBS_COMMAND_ERROR:
5ff1d584 383 fcport->flags &= ~FCF_ASYNC_SENT;
ac280b67
AV		 384 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
385 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
386 else
80d79440 387 qla2x00_mark_device_lost(vha, fcport, 1, 0);
ac280b67
AV		 388 break;
389 case MBS_PORT_ID_USED:
390 fcport->loop_id = data[1];
6ac52608 391 qla2x00_post_async_logout_work(vha, fcport, NULL);
ac280b67
AV		 392 qla2x00_post_async_login_work(vha, fcport, NULL);
393 break;
394 case MBS_LOOP_ID_USED:
395 fcport->loop_id++;
396 rval = qla2x00_find_new_loop_id(vha, fcport);
397 if (rval != QLA_SUCCESS) {
5ff1d584 398 fcport->flags &= ~FCF_ASYNC_SENT;
80d79440 399 qla2x00_mark_device_lost(vha, fcport, 1, 0);
ac280b67
AV		 400 break;
401 }
402 qla2x00_post_async_login_work(vha, fcport, NULL);
403 break;
404 }
4916392b 405 return;
ac280b67
AV		 406}
407
4916392b 408void
ac280b67
AV		 409qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport,
410 uint16_t *data)
411{
412 qla2x00_mark_device_lost(vha, fcport, 1, 0);
4916392b 413 return;
ac280b67
AV		 414}
415
4916392b 416void
5ff1d584
AV		 417qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport,
418 uint16_t *data)
419{
420 if (data[0] == MBS_COMMAND_COMPLETE) {
421 qla2x00_update_fcport(vha, fcport);
422
4916392b 423 return;
5ff1d584
AV		 424 }
425
426 /* Retry login. */
427 fcport->flags &= ~FCF_ASYNC_SENT;
428 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
429 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
430 else
80d79440 431 qla2x00_mark_device_lost(vha, fcport, 1, 0);
5ff1d584 432
4916392b 433 return;
5ff1d584
AV		 434}
435
1da177e4
LT		 436/****************************************************************************/
437/* QLogic ISP2x00 Hardware Support Functions. */
438/****************************************************************************/
439
fa492630 440static int
7d613ac6
SV		 441qla83xx_nic_core_fw_load(scsi_qla_host_t *vha)
442{
443 int rval = QLA_SUCCESS;
444 struct qla_hw_data *ha = vha->hw;
445 uint32_t idc_major_ver, idc_minor_ver;
711aa7f7 446 uint16_t config[4];
7d613ac6
SV		 447
448 qla83xx_idc_lock(vha, 0);
449
450 /* SV: TODO: Assign initialization timeout from
451 * flash-info / other param
452 */
453 ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT;
454 ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT;
455
456 /* Set our fcoe function presence */
457 if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) {
458 ql_dbg(ql_dbg_p3p, vha, 0xb077,
459 "Error while setting DRV-Presence.\n");
460 rval = QLA_FUNCTION_FAILED;
461 goto exit;
462 }
463
464 /* Decide the reset ownership */
465 qla83xx_reset_ownership(vha);
466
467 /*
468 * On first protocol driver load:
469 * Init-Owner: Set IDC-Major-Version and Clear IDC-Lock-Recovery
470 * register.
471 * Others: Check compatibility with current IDC Major version.
472 */
473 qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver);
474 if (ha->flags.nic_core_reset_owner) {
475 /* Set IDC Major version */
476 idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION;
477 qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver);
478
479 /* Clearing IDC-Lock-Recovery register */
480 qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0);
481 } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) {
482 /*
483 * Clear further IDC participation if we are not compatible with
484 * the current IDC Major Version.
485 */
486 ql_log(ql_log_warn, vha, 0xb07d,
487 "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n",
488 idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION);
489 __qla83xx_clear_drv_presence(vha);
490 rval = QLA_FUNCTION_FAILED;
491 goto exit;
492 }
493 /* Each function sets its supported Minor version. */
494 qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver);
495 idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2));
496 qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver);
497
711aa7f7
SK		 498 if (ha->flags.nic_core_reset_owner) {
499 memset(config, 0, sizeof(config));
500 if (!qla81xx_get_port_config(vha, config))
501 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
502 QLA8XXX_DEV_READY);
503 }
504
7d613ac6
SV		 505 rval = qla83xx_idc_state_handler(vha);
506
507exit:
508 qla83xx_idc_unlock(vha, 0);
509
510 return rval;
511}
512
1da177e4
LT		 513/*
514* qla2x00_initialize_adapter
515* Initialize board.
516*
517* Input:
518* ha = adapter block pointer.
519*
520* Returns:
521* 0 = success
522*/
523int
e315cd28 524qla2x00_initialize_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 525{
526 int rval;
e315cd28 527 struct qla_hw_data *ha = vha->hw;
73208dfd 528 struct req_que *req = ha->req_q_map[0];
2533cf67 529
1da177e4 530 /* Clear adapter flags. */
e315cd28 531 vha->flags.online = 0;
2533cf67 532 ha->flags.chip_reset_done = 0;
e315cd28 533 vha->flags.reset_active = 0;
85880801
AV		 534 ha->flags.pci_channel_io_perm_failure = 0;
535 ha->flags.eeh_busy = 0;
fabbb8df 536 vha->qla_stats.jiffies_at_last_reset = get_jiffies_64();
e315cd28
AC		 537 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
538 atomic_set(&vha->loop_state, LOOP_DOWN);
539 vha->device_flags = DFLG_NO_CABLE;
540 vha->dpc_flags = 0;
541 vha->flags.management_server_logged_in = 0;
542 vha->marker_needed = 0;
1da177e4
LT		 543 ha->isp_abort_cnt = 0;
544 ha->beacon_blink_led = 0;
545
73208dfd
AC		 546 set_bit(0, ha->req_qid_map);
547 set_bit(0, ha->rsp_qid_map);
548
cfb0919c 549 ql_dbg(ql_dbg_init, vha, 0x0040,
7c3df132 550 "Configuring PCI space...\n");
e315cd28 551 rval = ha->isp_ops->pci_config(vha);
1da177e4 552 if (rval) {
7c3df132
SK		 553 ql_log(ql_log_warn, vha, 0x0044,
554 "Unable to configure PCI space.\n");
1da177e4
LT		 555 return (rval);
556 }
557
e315cd28 558 ha->isp_ops->reset_chip(vha);
1da177e4 559
e315cd28 560 rval = qla2xxx_get_flash_info(vha);
c00d8994 561 if (rval) {
7c3df132
SK		 562 ql_log(ql_log_fatal, vha, 0x004f,
563 "Unable to validate FLASH data.\n");
7ec0effd
AD		 564 return rval;
565 }
566
567 if (IS_QLA8044(ha)) {
568 qla8044_read_reset_template(vha);
569
570 /* NOTE: If ql2xdontresethba==1, set IDC_CTRL DONTRESET_BIT0.
571 * If DONRESET_BIT0 is set, drivers should not set dev_state
572 * to NEED_RESET. But if NEED_RESET is set, drivers should
573 * should honor the reset. */
574 if (ql2xdontresethba == 1)
575 qla8044_set_idc_dontreset(vha);
c00d8994
AV		 576 }
577
73208dfd 578 ha->isp_ops->get_flash_version(vha, req->ring);
cfb0919c 579 ql_dbg(ql_dbg_init, vha, 0x0061,
7c3df132 580 "Configure NVRAM parameters...\n");
0107109e 581
e315cd28 582 ha->isp_ops->nvram_config(vha);
1da177e4 583
d4c760c2
AV		 584 if (ha->flags.disable_serdes) {
585 /* Mask HBA via NVRAM settings? */
7c3df132 586 ql_log(ql_log_info, vha, 0x0077,
7b833558 587 "Masking HBA WWPN %8phN (via NVRAM).\n", vha->port_name);
d4c760c2
AV		 588 return QLA_FUNCTION_FAILED;
589 }
590
cfb0919c 591 ql_dbg(ql_dbg_init, vha, 0x0078,
7c3df132 592 "Verifying loaded RISC code...\n");
1da177e4 593
e315cd28
AC		 594 if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) {
595 rval = ha->isp_ops->chip_diag(vha);
d19044c3
AV		 596 if (rval)
597 return (rval);
e315cd28 598 rval = qla2x00_setup_chip(vha);
d19044c3
AV		 599 if (rval)
600 return (rval);
1da177e4 601 }
a9083016 602
4d4df193 603 if (IS_QLA84XX(ha)) {
e315cd28 604 ha->cs84xx = qla84xx_get_chip(vha);
4d4df193 605 if (!ha->cs84xx) {
7c3df132 606 ql_log(ql_log_warn, vha, 0x00d0,
4d4df193
HK		 607 "Unable to configure ISP84XX.\n");
608 return QLA_FUNCTION_FAILED;
609 }
610 }
2d70c103
NB		 611
612 if (qla_ini_mode_enabled(vha))
613 rval = qla2x00_init_rings(vha);
614
2533cf67 615 ha->flags.chip_reset_done = 1;
1da177e4 616
9a069e19 617 if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) {
6c452a45 618 /* Issue verify 84xx FW IOCB to complete 84xx initialization */
9a069e19
GM		 619 rval = qla84xx_init_chip(vha);
620 if (rval != QLA_SUCCESS) {
7c3df132
SK		 621 ql_log(ql_log_warn, vha, 0x00d4,
622 "Unable to initialize ISP84XX.\n");
9a069e19
GM		 623 qla84xx_put_chip(vha);
624 }
625 }
626
7d613ac6
SV		 627 /* Load the NIC Core f/w if we are the first protocol driver. */
628 if (IS_QLA8031(ha)) {
629 rval = qla83xx_nic_core_fw_load(vha);
630 if (rval)
631 ql_log(ql_log_warn, vha, 0x0124,
632 "Error in initializing NIC Core f/w.\n");
633 }
634
2f0f3f4f
MI		 635 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
636 qla24xx_read_fcp_prio_cfg(vha);
09ff701a 637
c46e65c7
JC		 638 if (IS_P3P_TYPE(ha))
639 qla82xx_set_driver_version(vha, QLA2XXX_VERSION);
640 else
641 qla25xx_set_driver_version(vha, QLA2XXX_VERSION);
642
1da177e4
LT		 643 return (rval);
644}
645
646/**
abbd8870 647 * qla2100_pci_config() - Setup ISP21xx PCI configuration registers.
1da177e4
LT		 648 * @ha: HA context
649 *
650 * Returns 0 on success.
651 */
abbd8870 652int
e315cd28 653qla2100_pci_config(scsi_qla_host_t *vha)
1da177e4 654{
a157b101 655 uint16_t w;
abbd8870 656 unsigned long flags;
e315cd28 657 struct qla_hw_data *ha = vha->hw;
3d71644c 658 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 659
1da177e4 660 pci_set_master(ha->pdev);
af6177d8 661 pci_try_set_mwi(ha->pdev);
1da177e4 662
1da177e4 663 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 664 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
abbd8870
AV		 665 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
666
737faece 667 pci_disable_rom(ha->pdev);
1da177e4
LT		 668
669 /* Get PCI bus information. */
670 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 671 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
1da177e4
LT		 672 spin_unlock_irqrestore(&ha->hardware_lock, flags);
673
abbd8870
AV		 674 return QLA_SUCCESS;
675}
1da177e4 676
abbd8870
AV		 677/**
678 * qla2300_pci_config() - Setup ISP23xx PCI configuration registers.
679 * @ha: HA context
680 *
681 * Returns 0 on success.
682 */
683int
e315cd28 684qla2300_pci_config(scsi_qla_host_t *vha)
abbd8870 685{
a157b101 686 uint16_t w;
abbd8870
AV		 687 unsigned long flags = 0;
688 uint32_t cnt;
e315cd28 689 struct qla_hw_data *ha = vha->hw;
3d71644c 690 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 691
abbd8870 692 pci_set_master(ha->pdev);
af6177d8 693 pci_try_set_mwi(ha->pdev);
1da177e4 694
abbd8870 695 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 696 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
1da177e4 697
abbd8870
AV		 698 if (IS_QLA2322(ha) || IS_QLA6322(ha))
699 w &= ~PCI_COMMAND_INTX_DISABLE;
a157b101 700 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1da177e4 701
abbd8870
AV		 702 /*
703 * If this is a 2300 card and not 2312, reset the
704 * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately,
705 * the 2310 also reports itself as a 2300 so we need to get the
706 * fb revision level -- a 6 indicates it really is a 2300 and
707 * not a 2310.
708 */
709 if (IS_QLA2300(ha)) {
710 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 711
abbd8870 712 /* Pause RISC. */
3d71644c 713 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
abbd8870 714 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 715 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
abbd8870 716 break;
1da177e4 717
abbd8870
AV		 718 udelay(10);
719 }
1da177e4 720
abbd8870 721 /* Select FPM registers. */
3d71644c
AV		 722 WRT_REG_WORD(&reg->ctrl_status, 0x20);
723 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 724
725 /* Get the fb rev level */
3d71644c 726 ha->fb_rev = RD_FB_CMD_REG(ha, reg);
abbd8870
AV		 727
728 if (ha->fb_rev == FPM_2300)
a157b101 729 pci_clear_mwi(ha->pdev);
abbd8870
AV		 730
731 /* Deselect FPM registers. */
3d71644c
AV		 732 WRT_REG_WORD(&reg->ctrl_status, 0x0);
733 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 734
735 /* Release RISC module. */
3d71644c 736 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
abbd8870 737 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 738 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0)
abbd8870
AV		 739 break;
740
741 udelay(10);
1da177e4 742 }
1da177e4 743
abbd8870
AV		 744 spin_unlock_irqrestore(&ha->hardware_lock, flags);
745 }
1da177e4 746
abbd8870
AV		 747 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
748
737faece 749 pci_disable_rom(ha->pdev);
1da177e4 750
abbd8870
AV		 751 /* Get PCI bus information. */
752 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 753 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 754 spin_unlock_irqrestore(&ha->hardware_lock, flags);
755
756 return QLA_SUCCESS;
1da177e4
LT		 757}
758
0107109e
AV		 759/**
760 * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers.
761 * @ha: HA context
762 *
763 * Returns 0 on success.
764 */
765int
e315cd28 766qla24xx_pci_config(scsi_qla_host_t *vha)
0107109e 767{
a157b101 768 uint16_t w;
0107109e 769 unsigned long flags = 0;
e315cd28 770 struct qla_hw_data *ha = vha->hw;
0107109e 771 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
0107109e
AV		 772
773 pci_set_master(ha->pdev);
af6177d8 774 pci_try_set_mwi(ha->pdev);
0107109e
AV		 775
776 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 777 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
0107109e
AV		 778 w &= ~PCI_COMMAND_INTX_DISABLE;
779 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
780
781 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
782
783 /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */
f85ec187
AV		 784 if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
785 pcix_set_mmrbc(ha->pdev, 2048);
0107109e
AV		 786
787 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 788 if (pci_is_pcie(ha->pdev))
5ffd3a52 789 pcie_set_readrq(ha->pdev, 4096);
0107109e 790
737faece 791 pci_disable_rom(ha->pdev);
0107109e 792
44c10138 793 ha->chip_revision = ha->pdev->revision;
a8488abe 794
0107109e
AV		 795 /* Get PCI bus information. */
796 spin_lock_irqsave(&ha->hardware_lock, flags);
797 ha->pci_attr = RD_REG_DWORD(&reg->ctrl_status);
798 spin_unlock_irqrestore(&ha->hardware_lock, flags);
799
800 return QLA_SUCCESS;
801}
802
c3a2f0df
AV		 803/**
804 * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers.
805 * @ha: HA context
806 *
807 * Returns 0 on success.
808 */
809int
e315cd28 810qla25xx_pci_config(scsi_qla_host_t *vha)
c3a2f0df
AV		 811{
812 uint16_t w;
e315cd28 813 struct qla_hw_data *ha = vha->hw;
c3a2f0df
AV		 814
815 pci_set_master(ha->pdev);
816 pci_try_set_mwi(ha->pdev);
817
818 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
819 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
820 w &= ~PCI_COMMAND_INTX_DISABLE;
821 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
822
823 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 824 if (pci_is_pcie(ha->pdev))
5ffd3a52 825 pcie_set_readrq(ha->pdev, 4096);
c3a2f0df 826
737faece 827 pci_disable_rom(ha->pdev);
c3a2f0df
AV		 828
829 ha->chip_revision = ha->pdev->revision;
830
831 return QLA_SUCCESS;
832}
833
1da177e4
LT		 834/**
835 * qla2x00_isp_firmware() - Choose firmware image.
836 * @ha: HA context
837 *
838 * Returns 0 on success.
839 */
840static int
e315cd28 841qla2x00_isp_firmware(scsi_qla_host_t *vha)
1da177e4
LT		 842{
843 int rval;
42e421b1
AV		 844 uint16_t loop_id, topo, sw_cap;
845 uint8_t domain, area, al_pa;
e315cd28 846 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 847
848 /* Assume loading risc code */
fa2a1ce5 849 rval = QLA_FUNCTION_FAILED;
1da177e4
LT		 850
851 if (ha->flags.disable_risc_code_load) {
7c3df132 852 ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n");
1da177e4
LT		 853
854 /* Verify checksum of loaded RISC code. */
e315cd28 855 rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address);
42e421b1
AV		 856 if (rval == QLA_SUCCESS) {
857 /* And, verify we are not in ROM code. */
e315cd28 858 rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa,
42e421b1
AV		 859 &area, &domain, &topo, &sw_cap);
860 }
1da177e4
LT		 861 }
862
7c3df132
SK		 863 if (rval)
864 ql_dbg(ql_dbg_init, vha, 0x007a,
865 "**** Load RISC code ****.\n");
1da177e4
LT		 866
867 return (rval);
868}
869
870/**
871 * qla2x00_reset_chip() - Reset ISP chip.
872 * @ha: HA context
873 *
874 * Returns 0 on success.
875 */
abbd8870 876void
e315cd28 877qla2x00_reset_chip(scsi_qla_host_t *vha)
1da177e4
LT		 878{
879 unsigned long flags = 0;
e315cd28 880 struct qla_hw_data *ha = vha->hw;
3d71644c 881 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 882 uint32_t cnt;
1da177e4
LT		 883 uint16_t cmd;
884
85880801
AV		 885 if (unlikely(pci_channel_offline(ha->pdev)))
886 return;
887
fd34f556 888 ha->isp_ops->disable_intrs(ha);
1da177e4
LT		 889
890 spin_lock_irqsave(&ha->hardware_lock, flags);
891
892 /* Turn off master enable */
893 cmd = 0;
894 pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd);
895 cmd &= ~PCI_COMMAND_MASTER;
896 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
897
898 if (!IS_QLA2100(ha)) {
899 /* Pause RISC. */
900 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
901 if (IS_QLA2200(ha) || IS_QLA2300(ha)) {
902 for (cnt = 0; cnt < 30000; cnt++) {
903 if ((RD_REG_WORD(&reg->hccr) &
904 HCCR_RISC_PAUSE) != 0)
905 break;
906 udelay(100);
907 }
908 } else {
909 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
910 udelay(10);
911 }
912
913 /* Select FPM registers. */
914 WRT_REG_WORD(&reg->ctrl_status, 0x20);
915 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
916
917 /* FPM Soft Reset. */
918 WRT_REG_WORD(&reg->fpm_diag_config, 0x100);
919 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
920
921 /* Toggle Fpm Reset. */
922 if (!IS_QLA2200(ha)) {
923 WRT_REG_WORD(&reg->fpm_diag_config, 0x0);
924 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
925 }
926
927 /* Select frame buffer registers. */
928 WRT_REG_WORD(&reg->ctrl_status, 0x10);
929 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
930
931 /* Reset frame buffer FIFOs. */
932 if (IS_QLA2200(ha)) {
933 WRT_FB_CMD_REG(ha, reg, 0xa000);
934 RD_FB_CMD_REG(ha, reg); /* PCI Posting. */
935 } else {
936 WRT_FB_CMD_REG(ha, reg, 0x00fc);
937
938 /* Read back fb_cmd until zero or 3 seconds max */
939 for (cnt = 0; cnt < 3000; cnt++) {
940 if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0)
941 break;
942 udelay(100);
943 }
944 }
945
946 /* Select RISC module registers. */
947 WRT_REG_WORD(&reg->ctrl_status, 0);
948 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
949
950 /* Reset RISC processor. */
951 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
952 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
953
954 /* Release RISC processor. */
955 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
956 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
957 }
958
959 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
960 WRT_REG_WORD(&reg->hccr, HCCR_CLR_HOST_INT);
961
962 /* Reset ISP chip. */
963 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
964
965 /* Wait for RISC to recover from reset. */
966 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
967 /*
968 * It is necessary to for a delay here since the card doesn't
969 * respond to PCI reads during a reset. On some architectures
970 * this will result in an MCA.
971 */
972 udelay(20);
973 for (cnt = 30000; cnt; cnt--) {
974 if ((RD_REG_WORD(&reg->ctrl_status) &
975 CSR_ISP_SOFT_RESET) == 0)
976 break;
977 udelay(100);
978 }
979 } else
980 udelay(10);
981
982 /* Reset RISC processor. */
983 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
984
985 WRT_REG_WORD(&reg->semaphore, 0);
986
987 /* Release RISC processor. */
988 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
989 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
990
991 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
992 for (cnt = 0; cnt < 30000; cnt++) {
ffb39f03 993 if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY)
1da177e4 994 break;
1da177e4
LT		 995
996 udelay(100);
997 }
998 } else
999 udelay(100);
1000
1001 /* Turn on master enable */
1002 cmd |= PCI_COMMAND_MASTER;
1003 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
1004
1005 /* Disable RISC pause on FPM parity error. */
1006 if (!IS_QLA2100(ha)) {
1007 WRT_REG_WORD(&reg->hccr, HCCR_DISABLE_PARITY_PAUSE);
1008 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1009 }
1010
1011 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1012}
1013
b1d46989
MI		 1014/**
1015 * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC.
1016 *
1017 * Returns 0 on success.
1018 */
fa492630 1019static int
b1d46989
MI		 1020qla81xx_reset_mpi(scsi_qla_host_t *vha)
1021{
1022 uint16_t mb[4] = {0x1010, 0, 1, 0};
1023
6246b8a1
GM		 1024 if (!IS_QLA81XX(vha->hw))
1025 return QLA_SUCCESS;
1026
b1d46989
MI		 1027 return qla81xx_write_mpi_register(vha, mb);
1028}
1029
0107109e 1030/**
88c26663 1031 * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC.
0107109e
AV		 1032 * @ha: HA context
1033 *
1034 * Returns 0 on success.
1035 */
88c26663 1036static inline void
e315cd28 1037qla24xx_reset_risc(scsi_qla_host_t *vha)
0107109e
AV		 1038{
1039 unsigned long flags = 0;
e315cd28 1040 struct qla_hw_data *ha = vha->hw;
0107109e
AV		 1041 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1042 uint32_t cnt, d2;
335a1cc9 1043 uint16_t wd;
b1d46989 1044 static int abts_cnt; /* ISP abort retry counts */
0107109e 1045
0107109e
AV		 1046 spin_lock_irqsave(&ha->hardware_lock, flags);
1047
1048 /* Reset RISC. */
1049 WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
1050 for (cnt = 0; cnt < 30000; cnt++) {
1051 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
1052 break;
1053
1054 udelay(10);
1055 }
1056
1057 WRT_REG_DWORD(&reg->ctrl_status,
1058 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
335a1cc9 1059 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
88c26663 1060
335a1cc9 1061 udelay(100);
88c26663 1062 /* Wait for firmware to complete NVRAM accesses. */
88c26663
AV		 1063 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1064 for (cnt = 10000 ; cnt && d2; cnt--) {
1065 udelay(5);
1066 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1067 barrier();
1068 }
1069
335a1cc9 1070 /* Wait for soft-reset to complete. */
0107109e
AV		 1071 d2 = RD_REG_DWORD(&reg->ctrl_status);
1072 for (cnt = 6000000 ; cnt && (d2 & CSRX_ISP_SOFT_RESET); cnt--) {
1073 udelay(5);
1074 d2 = RD_REG_DWORD(&reg->ctrl_status);
1075 barrier();
1076 }
1077
b1d46989
MI		 1078 /* If required, do an MPI FW reset now */
1079 if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
1080 if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
1081 if (++abts_cnt < 5) {
1082 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1083 set_bit(MPI_RESET_NEEDED, &vha->dpc_flags);
1084 } else {
1085 /*
1086 * We exhausted the ISP abort retries. We have to
1087 * set the board offline.
1088 */
1089 abts_cnt = 0;
1090 vha->flags.online = 0;
1091 }
1092 }
1093 }
1094
0107109e
AV		 1095 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
1096 RD_REG_DWORD(&reg->hccr);
1097
1098 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
1099 RD_REG_DWORD(&reg->hccr);
1100
1101 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
1102 RD_REG_DWORD(&reg->hccr);
1103
1104 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1105 for (cnt = 6000000 ; cnt && d2; cnt--) {
1106 udelay(5);
1107 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1108 barrier();
1109 }
1110
1111 spin_unlock_irqrestore(&ha->hardware_lock, flags);
124f85e6
AV		 1112
1113 if (IS_NOPOLLING_TYPE(ha))
1114 ha->isp_ops->enable_intrs(ha);
0107109e
AV		 1115}
1116
4ea2c9c7
JC		 1117static void
1118qla25xx_read_risc_sema_reg(scsi_qla_host_t *vha, uint32_t *data)
1119{
1120 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
1121
1122 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
1123 *data = RD_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET);
1124
1125}
1126
1127static void
1128qla25xx_write_risc_sema_reg(scsi_qla_host_t *vha, uint32_t data)
1129{
1130 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
1131
1132 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
1133 WRT_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET, data);
1134}
1135
1136static void
1137qla25xx_manipulate_risc_semaphore(scsi_qla_host_t *vha)
1138{
1139 struct qla_hw_data *ha = vha->hw;
1140 uint32_t wd32 = 0;
1141 uint delta_msec = 100;
1142 uint elapsed_msec = 0;
1143 uint timeout_msec;
1144 ulong n;
1145
1146 if (!IS_QLA25XX(ha) && !IS_QLA2031(ha))
1147 return;
1148
1149attempt:
1150 timeout_msec = TIMEOUT_SEMAPHORE;
1151 n = timeout_msec / delta_msec;
1152 while (n--) {
1153 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_SET);
1154 qla25xx_read_risc_sema_reg(vha, &wd32);
1155 if (wd32 & RISC_SEMAPHORE)
1156 break;
1157 msleep(delta_msec);
1158 elapsed_msec += delta_msec;
1159 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
1160 goto force;
1161 }
1162
1163 if (!(wd32 & RISC_SEMAPHORE))
1164 goto force;
1165
1166 if (!(wd32 & RISC_SEMAPHORE_FORCE))
1167 goto acquired;
1168
1169 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_CLR);
1170 timeout_msec = TIMEOUT_SEMAPHORE_FORCE;
1171 n = timeout_msec / delta_msec;
1172 while (n--) {
1173 qla25xx_read_risc_sema_reg(vha, &wd32);
1174 if (!(wd32 & RISC_SEMAPHORE_FORCE))
1175 break;
1176 msleep(delta_msec);
1177 elapsed_msec += delta_msec;
1178 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
1179 goto force;
1180 }
1181
1182 if (wd32 & RISC_SEMAPHORE_FORCE)
1183 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_CLR);
1184
1185 goto attempt;
1186
1187force:
1188 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_SET);
1189
1190acquired:
1191 return;
1192}
1193
88c26663
AV		 1194/**
1195 * qla24xx_reset_chip() - Reset ISP24xx chip.
1196 * @ha: HA context
1197 *
1198 * Returns 0 on success.
1199 */
1200void
e315cd28 1201qla24xx_reset_chip(scsi_qla_host_t *vha)
88c26663 1202{
e315cd28 1203 struct qla_hw_data *ha = vha->hw;
85880801
AV		 1204
1205 if (pci_channel_offline(ha->pdev) &&
1206 ha->flags.pci_channel_io_perm_failure) {
1207 return;
1208 }
1209
fd34f556 1210 ha->isp_ops->disable_intrs(ha);
88c26663 1211
4ea2c9c7
JC		 1212 qla25xx_manipulate_risc_semaphore(vha);
1213
88c26663 1214 /* Perform RISC reset. */
e315cd28 1215 qla24xx_reset_risc(vha);
88c26663
AV		 1216}
1217
1da177e4
LT		 1218/**
1219 * qla2x00_chip_diag() - Test chip for proper operation.
1220 * @ha: HA context
1221 *
1222 * Returns 0 on success.
1223 */
abbd8870 1224int
e315cd28 1225qla2x00_chip_diag(scsi_qla_host_t *vha)
1da177e4
LT		 1226{
1227 int rval;
e315cd28 1228 struct qla_hw_data *ha = vha->hw;
3d71644c 1229 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 1230 unsigned long flags = 0;
1231 uint16_t data;
1232 uint32_t cnt;
1233 uint16_t mb[5];
73208dfd 1234 struct req_que *req = ha->req_q_map[0];
1da177e4
LT		 1235
1236 /* Assume a failed state */
1237 rval = QLA_FUNCTION_FAILED;
1238
7c3df132
SK		 1239 ql_dbg(ql_dbg_init, vha, 0x007b,
1240 "Testing device at %lx.\n", (u_long)&reg->flash_address);
1da177e4
LT		 1241
1242 spin_lock_irqsave(&ha->hardware_lock, flags);
1243
1244 /* Reset ISP chip. */
1245 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1246
1247 /*
1248 * We need to have a delay here since the card will not respond while
1249 * in reset causing an MCA on some architectures.
1250 */
1251 udelay(20);
1252 data = qla2x00_debounce_register(&reg->ctrl_status);
1253 for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {
1254 udelay(5);
1255 data = RD_REG_WORD(&reg->ctrl_status);
1256 barrier();
1257 }
1258
1259 if (!cnt)
1260 goto chip_diag_failed;
1261
7c3df132
SK		 1262 ql_dbg(ql_dbg_init, vha, 0x007c,
1263 "Reset register cleared by chip reset.\n");
1da177e4
LT		 1264
1265 /* Reset RISC processor. */
1266 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
1267 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
1268
1269 /* Workaround for QLA2312 PCI parity error */
1270 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1271 data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0));
1272 for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) {
1273 udelay(5);
1274 data = RD_MAILBOX_REG(ha, reg, 0);
fa2a1ce5 1275 barrier();
1da177e4
LT		 1276 }
1277 } else
1278 udelay(10);
1279
1280 if (!cnt)
1281 goto chip_diag_failed;
1282
1283 /* Check product ID of chip */
7c3df132 1284 ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product Id of chip.\n");
1da177e4
LT		 1285
1286 mb[1] = RD_MAILBOX_REG(ha, reg, 1);
1287 mb[2] = RD_MAILBOX_REG(ha, reg, 2);
1288 mb[3] = RD_MAILBOX_REG(ha, reg, 3);
1289 mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4));
1290 if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) ||
1291 mb[3] != PROD_ID_3) {
7c3df132
SK		 1292 ql_log(ql_log_warn, vha, 0x0062,
1293 "Wrong product ID = 0x%x,0x%x,0x%x.\n",
1294 mb[1], mb[2], mb[3]);
1da177e4
LT		 1295
1296 goto chip_diag_failed;
1297 }
1298 ha->product_id[0] = mb[1];
1299 ha->product_id[1] = mb[2];
1300 ha->product_id[2] = mb[3];
1301 ha->product_id[3] = mb[4];
1302
1303 /* Adjust fw RISC transfer size */
73208dfd 1304 if (req->length > 1024)
1da177e4
LT		 1305 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024;
1306 else
1307 ha->fw_transfer_size = REQUEST_ENTRY_SIZE *
73208dfd 1308 req->length;
1da177e4
LT		 1309
1310 if (IS_QLA2200(ha) &&
1311 RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) {
1312 /* Limit firmware transfer size with a 2200A */
7c3df132 1313 ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n");
1da177e4 1314
ea5b6382 1315 ha->device_type |= DT_ISP2200A;
1da177e4
LT		 1316 ha->fw_transfer_size = 128;
1317 }
1318
1319 /* Wrap Incoming Mailboxes Test. */
1320 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1321
7c3df132 1322 ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n");
e315cd28 1323 rval = qla2x00_mbx_reg_test(vha);
7c3df132
SK		 1324 if (rval)
1325 ql_log(ql_log_warn, vha, 0x0080,
1326 "Failed mailbox send register test.\n");
1327 else
1da177e4
LT		 1328 /* Flag a successful rval */
1329 rval = QLA_SUCCESS;
1da177e4
LT		 1330 spin_lock_irqsave(&ha->hardware_lock, flags);
1331
1332chip_diag_failed:
1333 if (rval)
7c3df132
SK		 1334 ql_log(ql_log_info, vha, 0x0081,
1335 "Chip diagnostics **** FAILED ****.\n");
1da177e4
LT		 1336
1337 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1338
1339 return (rval);
1340}
1341
0107109e
AV		 1342/**
1343 * qla24xx_chip_diag() - Test ISP24xx for proper operation.
1344 * @ha: HA context
1345 *
1346 * Returns 0 on success.
1347 */
1348int
e315cd28 1349qla24xx_chip_diag(scsi_qla_host_t *vha)
0107109e
AV		 1350{
1351 int rval;
e315cd28 1352 struct qla_hw_data *ha = vha->hw;
73208dfd 1353 struct req_que *req = ha->req_q_map[0];
0107109e 1354
7ec0effd 1355 if (IS_P3P_TYPE(ha))
a9083016
GM		 1356 return QLA_SUCCESS;
1357
73208dfd 1358 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
0107109e 1359
e315cd28 1360 rval = qla2x00_mbx_reg_test(vha);
0107109e 1361 if (rval) {
7c3df132
SK		 1362 ql_log(ql_log_warn, vha, 0x0082,
1363 "Failed mailbox send register test.\n");
0107109e
AV		 1364 } else {
1365 /* Flag a successful rval */
1366 rval = QLA_SUCCESS;
1367 }
1368
1369 return rval;
1370}
1371
a7a167bf 1372void
e315cd28 1373qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
0107109e 1374{
a7a167bf
AV		 1375 int rval;
1376 uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
73208dfd 1377 eft_size, fce_size, mq_size;
df613b96
AV		 1378 dma_addr_t tc_dma;
1379 void *tc;
e315cd28 1380 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 1381 struct req_que *req = ha->req_q_map[0];
1382 struct rsp_que *rsp = ha->rsp_q_map[0];
a7a167bf
AV		 1383
1384 if (ha->fw_dump) {
7c3df132
SK		 1385 ql_dbg(ql_dbg_init, vha, 0x00bd,
1386 "Firmware dump already allocated.\n");
a7a167bf
AV		 1387 return;
1388 }
d4e3e04d 1389
0107109e 1390 ha->fw_dumped = 0;
f73cb695
CD		 1391 dump_size = fixed_size = mem_size = eft_size = fce_size = mq_size = 0;
1392 req_q_size = rsp_q_size = 0;
1393
1394 if (IS_QLA27XX(ha))
1395 goto try_fce;
1396
d4e3e04d 1397 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
a7a167bf 1398 fixed_size = sizeof(struct qla2100_fw_dump);
d4e3e04d 1399 } else if (IS_QLA23XX(ha)) {
a7a167bf
AV		 1400 fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
1401 mem_size = (ha->fw_memory_size - 0x11000 + 1) *
1402 sizeof(uint16_t);
e428924c 1403 } else if (IS_FWI2_CAPABLE(ha)) {
6246b8a1
GM		 1404 if (IS_QLA83XX(ha))
1405 fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem);
1406 else if (IS_QLA81XX(ha))
3a03eb79
AV		 1407 fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
1408 else if (IS_QLA25XX(ha))
1409 fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
1410 else
1411 fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
f73cb695 1412
a7a167bf
AV		 1413 mem_size = (ha->fw_memory_size - 0x100000 + 1) *
1414 sizeof(uint32_t);
050c9bb1 1415 if (ha->mqenable) {
6246b8a1
GM		 1416 if (!IS_QLA83XX(ha))
1417 mq_size = sizeof(struct qla2xxx_mq_chain);
050c9bb1
GM		 1418 /*
1419 * Allocate maximum buffer size for all queues.
1420 * Resizing must be done at end-of-dump processing.
1421 */
1422 mq_size += ha->max_req_queues *
1423 (req->length * sizeof(request_t));
1424 mq_size += ha->max_rsp_queues *
1425 (rsp->length * sizeof(response_t));
1426 }
00876ae8 1427 if (ha->tgt.atio_ring)
2d70c103 1428 mq_size += ha->tgt.atio_q_length * sizeof(request_t);
df613b96 1429 /* Allocate memory for Fibre Channel Event Buffer. */
f73cb695
CD		 1430 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
1431 !IS_QLA27XX(ha))
436a7b11 1432 goto try_eft;
df613b96 1433
f73cb695
CD		 1434try_fce:
1435 if (ha->fce)
1436 dma_free_coherent(&ha->pdev->dev,
1437 FCE_SIZE, ha->fce, ha->fce_dma);
1438
1439 /* Allocate memory for Fibre Channel Event Buffer. */
df613b96
AV		 1440 tc = dma_alloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
1441 GFP_KERNEL);
1442 if (!tc) {
7c3df132
SK		 1443 ql_log(ql_log_warn, vha, 0x00be,
1444 "Unable to allocate (%d KB) for FCE.\n",
1445 FCE_SIZE / 1024);
17d98630 1446 goto try_eft;
df613b96
AV		 1447 }
1448
1449 memset(tc, 0, FCE_SIZE);
e315cd28 1450 rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS,
df613b96
AV		 1451 ha->fce_mb, &ha->fce_bufs);
1452 if (rval) {
7c3df132
SK		 1453 ql_log(ql_log_warn, vha, 0x00bf,
1454 "Unable to initialize FCE (%d).\n", rval);
df613b96
AV		 1455 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc,
1456 tc_dma);
1457 ha->flags.fce_enabled = 0;
17d98630 1458 goto try_eft;
df613b96 1459 }
cfb0919c 1460 ql_dbg(ql_dbg_init, vha, 0x00c0,
7c3df132 1461 "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024);
df613b96 1462
7d9dade3 1463 fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE;
df613b96
AV		 1464 ha->flags.fce_enabled = 1;
1465 ha->fce_dma = tc_dma;
1466 ha->fce = tc;
f73cb695 1467
436a7b11 1468try_eft:
f73cb695
CD		 1469 if (ha->eft)
1470 dma_free_coherent(&ha->pdev->dev,
1471 EFT_SIZE, ha->eft, ha->eft_dma);
1472
436a7b11
AV		 1473 /* Allocate memory for Extended Trace Buffer. */
1474 tc = dma_alloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
1475 GFP_KERNEL);
1476 if (!tc) {
7c3df132
SK		 1477 ql_log(ql_log_warn, vha, 0x00c1,
1478 "Unable to allocate (%d KB) for EFT.\n",
1479 EFT_SIZE / 1024);
436a7b11
AV		 1480 goto cont_alloc;
1481 }
1482
1483 memset(tc, 0, EFT_SIZE);
e315cd28 1484 rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
436a7b11 1485 if (rval) {
7c3df132
SK		 1486 ql_log(ql_log_warn, vha, 0x00c2,
1487 "Unable to initialize EFT (%d).\n", rval);
436a7b11
AV		 1488 dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc,
1489 tc_dma);
1490 goto cont_alloc;
1491 }
cfb0919c 1492 ql_dbg(ql_dbg_init, vha, 0x00c3,
7c3df132 1493 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
436a7b11
AV		 1494
1495 eft_size = EFT_SIZE;
1496 ha->eft_dma = tc_dma;
1497 ha->eft = tc;
d4e3e04d 1498 }
f73cb695 1499
a7a167bf 1500cont_alloc:
f73cb695
CD		 1501 if (IS_QLA27XX(ha)) {
1502 if (!ha->fw_dump_template) {
1503 ql_log(ql_log_warn, vha, 0x00ba,
1504 "Failed missing fwdump template\n");
1505 return;
1506 }
1507 dump_size = qla27xx_fwdt_calculate_dump_size(vha);
1508 ql_dbg(ql_dbg_init, vha, 0x00fa,
1509 "-> allocating fwdump (%x bytes)...\n", dump_size);
1510 goto allocate;
1511 }
1512
73208dfd
AC		 1513 req_q_size = req->length * sizeof(request_t);
1514 rsp_q_size = rsp->length * sizeof(response_t);
a7a167bf 1515 dump_size = offsetof(struct qla2xxx_fw_dump, isp);
2afa19a9 1516 dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size;
bb99de67
AV		 1517 ha->chain_offset = dump_size;
1518 dump_size += mq_size + fce_size;
d4e3e04d 1519
f73cb695 1520allocate:
d4e3e04d 1521 ha->fw_dump = vmalloc(dump_size);
a7a167bf 1522 if (!ha->fw_dump) {
7c3df132
SK		 1523 ql_log(ql_log_warn, vha, 0x00c4,
1524 "Unable to allocate (%d KB) for firmware dump.\n",
1525 dump_size / 1024);
a7a167bf 1526
e30d1756
MI		 1527 if (ha->fce) {
1528 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
1529 ha->fce_dma);
1530 ha->fce = NULL;
1531 ha->fce_dma = 0;
1532 }
1533
a7a167bf
AV		 1534 if (ha->eft) {
1535 dma_free_coherent(&ha->pdev->dev, eft_size, ha->eft,
1536 ha->eft_dma);
1537 ha->eft = NULL;
1538 ha->eft_dma = 0;
1539 }
1540 return;
1541 }
f73cb695 1542 ha->fw_dump_len = dump_size;
cfb0919c 1543 ql_dbg(ql_dbg_init, vha, 0x00c5,
7c3df132 1544 "Allocated (%d KB) for firmware dump.\n", dump_size / 1024);
a7a167bf 1545
f73cb695
CD		 1546 if (IS_QLA27XX(ha))
1547 return;
1548
a7a167bf
AV		 1549 ha->fw_dump->signature[0] = 'Q';
1550 ha->fw_dump->signature[1] = 'L';
1551 ha->fw_dump->signature[2] = 'G';
1552 ha->fw_dump->signature[3] = 'C';
1553 ha->fw_dump->version = __constant_htonl(1);
1554
1555 ha->fw_dump->fixed_size = htonl(fixed_size);
1556 ha->fw_dump->mem_size = htonl(mem_size);
1557 ha->fw_dump->req_q_size = htonl(req_q_size);
1558 ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
1559
1560 ha->fw_dump->eft_size = htonl(eft_size);
1561 ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma));
1562 ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma));
1563
1564 ha->fw_dump->header_size =
1565 htonl(offsetof(struct qla2xxx_fw_dump, isp));
0107109e
AV		 1566}
1567
18e7555a
AV		 1568static int
1569qla81xx_mpi_sync(scsi_qla_host_t *vha)
1570{
1571#define MPS_MASK 0xe0
1572 int rval;
1573 uint16_t dc;
1574 uint32_t dw;
18e7555a
AV		 1575
1576 if (!IS_QLA81XX(vha->hw))
1577 return QLA_SUCCESS;
1578
1579 rval = qla2x00_write_ram_word(vha, 0x7c00, 1);
1580 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1581 ql_log(ql_log_warn, vha, 0x0105,
1582 "Unable to acquire semaphore.\n");
18e7555a
AV		 1583 goto done;
1584 }
1585
1586 pci_read_config_word(vha->hw->pdev, 0x54, &dc);
1587 rval = qla2x00_read_ram_word(vha, 0x7a15, &dw);
1588 if (rval != QLA_SUCCESS) {
7c3df132 1589 ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n");
18e7555a
AV		 1590 goto done_release;
1591 }
1592
1593 dc &= MPS_MASK;
1594 if (dc == (dw & MPS_MASK))
1595 goto done_release;
1596
1597 dw &= ~MPS_MASK;
1598 dw |= dc;
1599 rval = qla2x00_write_ram_word(vha, 0x7a15, dw);
1600 if (rval != QLA_SUCCESS) {
7c3df132 1601 ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n");
18e7555a
AV		 1602 }
1603
1604done_release:
1605 rval = qla2x00_write_ram_word(vha, 0x7c00, 0);
1606 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1607 ql_log(ql_log_warn, vha, 0x006d,
1608 "Unable to release semaphore.\n");
18e7555a
AV		 1609 }
1610
1611done:
1612 return rval;
1613}
1614
8d93f550
CD		 1615int
1616qla2x00_alloc_outstanding_cmds(struct qla_hw_data *ha, struct req_que *req)
1617{
1618 /* Don't try to reallocate the array */
1619 if (req->outstanding_cmds)
1620 return QLA_SUCCESS;
1621
1622 if (!IS_FWI2_CAPABLE(ha) || (ha->mqiobase &&
1623 (ql2xmultique_tag || ql2xmaxqueues > 1)))
1624 req->num_outstanding_cmds = DEFAULT_OUTSTANDING_COMMANDS;
1625 else {
1626 if (ha->fw_xcb_count <= ha->fw_iocb_count)
1627 req->num_outstanding_cmds = ha->fw_xcb_count;
1628 else
1629 req->num_outstanding_cmds = ha->fw_iocb_count;
1630 }
1631
1632 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
1633 req->num_outstanding_cmds, GFP_KERNEL);
1634
1635 if (!req->outstanding_cmds) {
1636 /*
1637 * Try to allocate a minimal size just so we can get through
1638 * initialization.
1639 */
1640 req->num_outstanding_cmds = MIN_OUTSTANDING_COMMANDS;
1641 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
1642 req->num_outstanding_cmds, GFP_KERNEL);
1643
1644 if (!req->outstanding_cmds) {
1645 ql_log(ql_log_fatal, NULL, 0x0126,
1646 "Failed to allocate memory for "
1647 "outstanding_cmds for req_que %p.\n", req);
1648 req->num_outstanding_cmds = 0;
1649 return QLA_FUNCTION_FAILED;
1650 }
1651 }
1652
1653 return QLA_SUCCESS;
1654}
1655
1da177e4
LT		 1656/**
1657 * qla2x00_setup_chip() - Load and start RISC firmware.
1658 * @ha: HA context
1659 *
1660 * Returns 0 on success.
1661 */
1662static int
e315cd28 1663qla2x00_setup_chip(scsi_qla_host_t *vha)
1da177e4 1664{
0107109e
AV		 1665 int rval;
1666 uint32_t srisc_address = 0;
e315cd28 1667 struct qla_hw_data *ha = vha->hw;
3db0652e
AV		 1668 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1669 unsigned long flags;
dda772e8 1670 uint16_t fw_major_version;
3db0652e 1671
7ec0effd 1672 if (IS_P3P_TYPE(ha)) {
a9083016 1673 rval = ha->isp_ops->load_risc(vha, &srisc_address);
14e303d9
AV		 1674 if (rval == QLA_SUCCESS) {
1675 qla2x00_stop_firmware(vha);
a9083016 1676 goto enable_82xx_npiv;
14e303d9 1677 } else
b963752f 1678 goto failed;
a9083016
GM		 1679 }
1680
3db0652e
AV		 1681 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1682 /* Disable SRAM, Instruction RAM and GP RAM parity. */
1683 spin_lock_irqsave(&ha->hardware_lock, flags);
1684 WRT_REG_WORD(&reg->hccr, (HCCR_ENABLE_PARITY + 0x0));
1685 RD_REG_WORD(&reg->hccr);
1686 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1687 }
1da177e4 1688
18e7555a
AV		 1689 qla81xx_mpi_sync(vha);
1690
1da177e4 1691 /* Load firmware sequences */
e315cd28 1692 rval = ha->isp_ops->load_risc(vha, &srisc_address);
0107109e 1693 if (rval == QLA_SUCCESS) {
7c3df132
SK		 1694 ql_dbg(ql_dbg_init, vha, 0x00c9,
1695 "Verifying Checksum of loaded RISC code.\n");
1da177e4 1696
e315cd28 1697 rval = qla2x00_verify_checksum(vha, srisc_address);
1da177e4
LT		 1698 if (rval == QLA_SUCCESS) {
1699 /* Start firmware execution. */
7c3df132
SK		 1700 ql_dbg(ql_dbg_init, vha, 0x00ca,
1701 "Starting firmware.\n");
1da177e4 1702
e315cd28 1703 rval = qla2x00_execute_fw(vha, srisc_address);
1da177e4 1704 /* Retrieve firmware information. */
dda772e8 1705 if (rval == QLA_SUCCESS) {
a9083016 1706enable_82xx_npiv:
dda772e8 1707 fw_major_version = ha->fw_major_version;
7ec0effd 1708 if (IS_P3P_TYPE(ha))
3173167f 1709 qla82xx_check_md_needed(vha);
6246b8a1
GM		 1710 else
1711 rval = qla2x00_get_fw_version(vha);
ca9e9c3e
AV		 1712 if (rval != QLA_SUCCESS)
1713 goto failed;
2c3dfe3f 1714 ha->flags.npiv_supported = 0;
e315cd28 1715 if (IS_QLA2XXX_MIDTYPE(ha) &&
946fb891 1716 (ha->fw_attributes & BIT_2)) {
2c3dfe3f 1717 ha->flags.npiv_supported = 1;
4d0ea247
SJ		 1718 if ((!ha->max_npiv_vports) ||
1719 ((ha->max_npiv_vports + 1) %
eb66dc60 1720 MIN_MULTI_ID_FABRIC))
4d0ea247 1721 ha->max_npiv_vports =
eb66dc60 1722 MIN_MULTI_ID_FABRIC - 1;
4d0ea247 1723 }
24a08138 1724 qla2x00_get_resource_cnts(vha, NULL,
8d93f550 1725 &ha->fw_xcb_count, NULL, &ha->fw_iocb_count,
f3a0a77e 1726 &ha->max_npiv_vports, NULL);
d743de66 1727
8d93f550
CD		 1728 /*
1729 * Allocate the array of outstanding commands
1730 * now that we know the firmware resources.
1731 */
1732 rval = qla2x00_alloc_outstanding_cmds(ha,
1733 vha->req);
1734 if (rval != QLA_SUCCESS)
1735 goto failed;
1736
be5ea3cf 1737 if (!fw_major_version && ql2xallocfwdump
7ec0effd 1738 && !(IS_P3P_TYPE(ha)))
08de2844 1739 qla2x00_alloc_fw_dump(vha);
3b6e5b9d
CD		 1740 } else {
1741 goto failed;
1da177e4
LT		 1742 }
1743 } else {
7c3df132
SK		 1744 ql_log(ql_log_fatal, vha, 0x00cd,
1745 "ISP Firmware failed checksum.\n");
1746 goto failed;
1da177e4 1747 }
c74d88a4
AV		 1748 } else
1749 goto failed;
1da177e4 1750
3db0652e
AV		 1751 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1752 /* Enable proper parity. */
1753 spin_lock_irqsave(&ha->hardware_lock, flags);
1754 if (IS_QLA2300(ha))
1755 /* SRAM parity */
1756 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x1);
1757 else
1758 /* SRAM, Instruction RAM and GP RAM parity */
1759 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x7);
1760 RD_REG_WORD(&reg->hccr);
1761 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1762 }
1763
1d2874de
JC		 1764 if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
1765 uint32_t size;
1766
1767 rval = qla81xx_fac_get_sector_size(vha, &size);
1768 if (rval == QLA_SUCCESS) {
1769 ha->flags.fac_supported = 1;
1770 ha->fdt_block_size = size << 2;
1771 } else {
7c3df132 1772 ql_log(ql_log_warn, vha, 0x00ce,
1d2874de
JC		 1773 "Unsupported FAC firmware (%d.%02d.%02d).\n",
1774 ha->fw_major_version, ha->fw_minor_version,
1775 ha->fw_subminor_version);
1ca60e3b 1776
f73cb695 1777 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
6246b8a1
GM		 1778 ha->flags.fac_supported = 0;
1779 rval = QLA_SUCCESS;
1780 }
1d2874de
JC		 1781 }
1782 }
ca9e9c3e 1783failed:
1da177e4 1784 if (rval) {
7c3df132
SK		 1785 ql_log(ql_log_fatal, vha, 0x00cf,
1786 "Setup chip ****FAILED****.\n");
1da177e4
LT		 1787 }
1788
1789 return (rval);
1790}
1791
1792/**
1793 * qla2x00_init_response_q_entries() - Initializes response queue entries.
1794 * @ha: HA context
1795 *
1796 * Beginning of request ring has initialization control block already built
1797 * by nvram config routine.
1798 *
1799 * Returns 0 on success.
1800 */
73208dfd
AC		 1801void
1802qla2x00_init_response_q_entries(struct rsp_que *rsp)
1da177e4
LT		 1803{
1804 uint16_t cnt;
1805 response_t *pkt;
1806
2afa19a9
AC		 1807 rsp->ring_ptr = rsp->ring;
1808 rsp->ring_index = 0;
1809 rsp->status_srb = NULL;
e315cd28
AC		 1810 pkt = rsp->ring_ptr;
1811 for (cnt = 0; cnt < rsp->length; cnt++) {
1da177e4
LT		 1812 pkt->signature = RESPONSE_PROCESSED;
1813 pkt++;
1814 }
1da177e4
LT		 1815}
1816
1817/**
1818 * qla2x00_update_fw_options() - Read and process firmware options.
1819 * @ha: HA context
1820 *
1821 * Returns 0 on success.
1822 */
abbd8870 1823void
e315cd28 1824qla2x00_update_fw_options(scsi_qla_host_t *vha)
1da177e4
LT		 1825{
1826 uint16_t swing, emphasis, tx_sens, rx_sens;
e315cd28 1827 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 1828
1829 memset(ha->fw_options, 0, sizeof(ha->fw_options));
e315cd28 1830 qla2x00_get_fw_options(vha, ha->fw_options);
1da177e4
LT		 1831
1832 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1833 return;
1834
1835 /* Serial Link options. */
7c3df132
SK		 1836 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
1837 "Serial link options.\n");
1838 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
1839 (uint8_t *)&ha->fw_seriallink_options,
1840 sizeof(ha->fw_seriallink_options));
1da177e4
LT		 1841
1842 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1843 if (ha->fw_seriallink_options[3] & BIT_2) {
1844 ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING;
1845
1846 /* 1G settings */
1847 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
1848 emphasis = (ha->fw_seriallink_options[2] &
1849 (BIT_4 | BIT_3)) >> 3;
1850 tx_sens = ha->fw_seriallink_options[0] &
fa2a1ce5 1851 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 1852 rx_sens = (ha->fw_seriallink_options[0] &
1853 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
1854 ha->fw_options[10] = (emphasis << 14) | (swing << 8);
1855 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
1856 if (rx_sens == 0x0)
1857 rx_sens = 0x3;
1858 ha->fw_options[10] |= (tx_sens << 4) | rx_sens;
1859 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
1860 ha->fw_options[10] |= BIT_5 |
1861 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
1862 (tx_sens & (BIT_1 | BIT_0));
1863
1864 /* 2G settings */
1865 swing = (ha->fw_seriallink_options[2] &
1866 (BIT_7 | BIT_6 | BIT_5)) >> 5;
1867 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
1868 tx_sens = ha->fw_seriallink_options[1] &
fa2a1ce5 1869 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 1870 rx_sens = (ha->fw_seriallink_options[1] &
1871 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
1872 ha->fw_options[11] = (emphasis << 14) | (swing << 8);
1873 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
1874 if (rx_sens == 0x0)
1875 rx_sens = 0x3;
1876 ha->fw_options[11] |= (tx_sens << 4) | rx_sens;
1877 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
1878 ha->fw_options[11] |= BIT_5 |
1879 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
1880 (tx_sens & (BIT_1 | BIT_0));
1881 }
1882
1883 /* FCP2 options. */
1884 /* Return command IOCBs without waiting for an ABTS to complete. */
1885 ha->fw_options[3] |= BIT_13;
1886
1887 /* LED scheme. */
1888 if (ha->flags.enable_led_scheme)
1889 ha->fw_options[2] |= BIT_12;
1890
48c02fde
AV		 1891 /* Detect ISP6312. */
1892 if (IS_QLA6312(ha))
1893 ha->fw_options[2] |= BIT_13;
1894
1da177e4 1895 /* Update firmware options. */
e315cd28 1896 qla2x00_set_fw_options(vha, ha->fw_options);
1da177e4
LT		 1897}
1898
0107109e 1899void
e315cd28 1900qla24xx_update_fw_options(scsi_qla_host_t *vha)
0107109e
AV		 1901{
1902 int rval;
e315cd28 1903 struct qla_hw_data *ha = vha->hw;
0107109e 1904
7ec0effd 1905 if (IS_P3P_TYPE(ha))
a9083016
GM		 1906 return;
1907
0107109e 1908 /* Update Serial Link options. */
f94097ed 1909 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0)
0107109e
AV		 1910 return;
1911
e315cd28 1912 rval = qla2x00_set_serdes_params(vha,
f94097ed
AV		 1913 le16_to_cpu(ha->fw_seriallink_options24[1]),
1914 le16_to_cpu(ha->fw_seriallink_options24[2]),
1915 le16_to_cpu(ha->fw_seriallink_options24[3]));
0107109e 1916 if (rval != QLA_SUCCESS) {
7c3df132 1917 ql_log(ql_log_warn, vha, 0x0104,
0107109e
AV		 1918 "Unable to update Serial Link options (%x).\n", rval);
1919 }
1920}
1921
abbd8870 1922void
e315cd28 1923qla2x00_config_rings(struct scsi_qla_host *vha)
abbd8870 1924{
e315cd28 1925 struct qla_hw_data *ha = vha->hw;
3d71644c 1926 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
73208dfd
AC		 1927 struct req_que *req = ha->req_q_map[0];
1928 struct rsp_que *rsp = ha->rsp_q_map[0];
abbd8870
AV		 1929
1930 /* Setup ring parameters in initialization control block. */
1931 ha->init_cb->request_q_outpointer = __constant_cpu_to_le16(0);
1932 ha->init_cb->response_q_inpointer = __constant_cpu_to_le16(0);
e315cd28
AC		 1933 ha->init_cb->request_q_length = cpu_to_le16(req->length);
1934 ha->init_cb->response_q_length = cpu_to_le16(rsp->length);
1935 ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
1936 ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
1937 ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
1938 ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
abbd8870
AV		 1939
1940 WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0);
1941 WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0);
1942 WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0);
1943 WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0);
1944 RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */
1945}
1946
0107109e 1947void
e315cd28 1948qla24xx_config_rings(struct scsi_qla_host *vha)
0107109e 1949{
e315cd28 1950 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 1951 device_reg_t __iomem *reg = ISP_QUE_REG(ha, 0);
1952 struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
1953 struct qla_msix_entry *msix;
0107109e 1954 struct init_cb_24xx *icb;
73208dfd
AC		 1955 uint16_t rid = 0;
1956 struct req_que *req = ha->req_q_map[0];
1957 struct rsp_que *rsp = ha->rsp_q_map[0];
0107109e 1958
6246b8a1 1959 /* Setup ring parameters in initialization control block. */
0107109e
AV		 1960 icb = (struct init_cb_24xx *)ha->init_cb;
1961 icb->request_q_outpointer = __constant_cpu_to_le16(0);
1962 icb->response_q_inpointer = __constant_cpu_to_le16(0);
e315cd28
AC		 1963 icb->request_q_length = cpu_to_le16(req->length);
1964 icb->response_q_length = cpu_to_le16(rsp->length);
1965 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
1966 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
1967 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
1968 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
0107109e 1969
2d70c103
NB		 1970 /* Setup ATIO queue dma pointers for target mode */
1971 icb->atio_q_inpointer = __constant_cpu_to_le16(0);
1972 icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length);
1973 icb->atio_q_address[0] = cpu_to_le32(LSD(ha->tgt.atio_dma));
1974 icb->atio_q_address[1] = cpu_to_le32(MSD(ha->tgt.atio_dma));
1975
f73cb695 1976 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
73208dfd
AC		 1977 icb->qos = __constant_cpu_to_le16(QLA_DEFAULT_QUE_QOS);
1978 icb->rid = __constant_cpu_to_le16(rid);
1979 if (ha->flags.msix_enabled) {
1980 msix = &ha->msix_entries[1];
7c3df132
SK		 1981 ql_dbg(ql_dbg_init, vha, 0x00fd,
1982 "Registering vector 0x%x for base que.\n",
1983 msix->entry);
73208dfd
AC		 1984 icb->msix = cpu_to_le16(msix->entry);
1985 }
1986 /* Use alternate PCI bus number */
1987 if (MSB(rid))
1988 icb->firmware_options_2 |=
1989 __constant_cpu_to_le32(BIT_19);
1990 /* Use alternate PCI devfn */
1991 if (LSB(rid))
1992 icb->firmware_options_2 |=
1993 __constant_cpu_to_le32(BIT_18);
1994
3155754a 1995 /* Use Disable MSIX Handshake mode for capable adapters */
6246b8a1
GM		 1996 if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) &&
1997 (ha->flags.msix_enabled)) {
3155754a
AC		 1998 icb->firmware_options_2 &=
1999 __constant_cpu_to_le32(~BIT_22);
2000 ha->flags.disable_msix_handshake = 1;
7c3df132
SK		 2001 ql_dbg(ql_dbg_init, vha, 0x00fe,
2002 "MSIX Handshake Disable Mode turned on.\n");
3155754a
AC		 2003 } else {
2004 icb->firmware_options_2 |=
2005 __constant_cpu_to_le32(BIT_22);
2006 }
73208dfd 2007 icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_23);
73208dfd
AC		 2008
2009 WRT_REG_DWORD(&reg->isp25mq.req_q_in, 0);
2010 WRT_REG_DWORD(&reg->isp25mq.req_q_out, 0);
2011 WRT_REG_DWORD(&reg->isp25mq.rsp_q_in, 0);
2012 WRT_REG_DWORD(&reg->isp25mq.rsp_q_out, 0);
2013 } else {
2014 WRT_REG_DWORD(&reg->isp24.req_q_in, 0);
2015 WRT_REG_DWORD(&reg->isp24.req_q_out, 0);
2016 WRT_REG_DWORD(&reg->isp24.rsp_q_in, 0);
2017 WRT_REG_DWORD(&reg->isp24.rsp_q_out, 0);
2018 }
aa230bc5 2019 qlt_24xx_config_rings(vha);
2d70c103 2020
73208dfd
AC		 2021 /* PCI posting */
2022 RD_REG_DWORD(&ioreg->hccr);
0107109e
AV		 2023}
2024
1da177e4
LT		 2025/**
2026 * qla2x00_init_rings() - Initializes firmware.
2027 * @ha: HA context
2028 *
2029 * Beginning of request ring has initialization control block already built
2030 * by nvram config routine.
2031 *
2032 * Returns 0 on success.
2033 */
8ae6d9c7 2034int
e315cd28 2035qla2x00_init_rings(scsi_qla_host_t *vha)
1da177e4
LT		 2036{
2037 int rval;
2038 unsigned long flags = 0;
29bdccbe 2039 int cnt, que;
e315cd28 2040 struct qla_hw_data *ha = vha->hw;
29bdccbe
AC		 2041 struct req_que *req;
2042 struct rsp_que *rsp;
2c3dfe3f
SJ		 2043 struct mid_init_cb_24xx *mid_init_cb =
2044 (struct mid_init_cb_24xx *) ha->init_cb;
1da177e4
LT		 2045
2046 spin_lock_irqsave(&ha->hardware_lock, flags);
2047
2048 /* Clear outstanding commands array. */
2afa19a9 2049 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe
AC		 2050 req = ha->req_q_map[que];
2051 if (!req)
2052 continue;
8d93f550 2053 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++)
29bdccbe 2054 req->outstanding_cmds[cnt] = NULL;
1da177e4 2055
2afa19a9 2056 req->current_outstanding_cmd = 1;
1da177e4 2057
29bdccbe
AC		 2058 /* Initialize firmware. */
2059 req->ring_ptr = req->ring;
2060 req->ring_index = 0;
2061 req->cnt = req->length;
2062 }
1da177e4 2063
2afa19a9 2064 for (que = 0; que < ha->max_rsp_queues; que++) {
29bdccbe
AC		 2065 rsp = ha->rsp_q_map[que];
2066 if (!rsp)
2067 continue;
29bdccbe 2068 /* Initialize response queue entries */
8ae6d9c7
GM		 2069 if (IS_QLAFX00(ha))
2070 qlafx00_init_response_q_entries(rsp);
2071 else
2072 qla2x00_init_response_q_entries(rsp);
29bdccbe 2073 }
1da177e4 2074
2d70c103
NB		 2075 ha->tgt.atio_ring_ptr = ha->tgt.atio_ring;
2076 ha->tgt.atio_ring_index = 0;
2077 /* Initialize ATIO queue entries */
2078 qlt_init_atio_q_entries(vha);
2079
e315cd28 2080 ha->isp_ops->config_rings(vha);
1da177e4
LT		 2081
2082 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2083
8ae6d9c7
GM		 2084 ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n");
2085
2086 if (IS_QLAFX00(ha)) {
2087 rval = qlafx00_init_firmware(vha, ha->init_cb_size);
2088 goto next_check;
2089 }
2090
1da177e4 2091 /* Update any ISP specific firmware options before initialization. */
e315cd28 2092 ha->isp_ops->update_fw_options(vha);
1da177e4 2093
605aa2bc 2094 if (ha->flags.npiv_supported) {
45980cc2 2095 if (ha->operating_mode == LOOP && !IS_CNA_CAPABLE(ha))
605aa2bc 2096 ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
c48339de 2097 mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
605aa2bc
LC		 2098 }
2099
24a08138
AV		 2100 if (IS_FWI2_CAPABLE(ha)) {
2101 mid_init_cb->options = __constant_cpu_to_le16(BIT_1);
2102 mid_init_cb->init_cb.execution_throttle =
2103 cpu_to_le16(ha->fw_xcb_count);
2104 }
2c3dfe3f 2105
e315cd28 2106 rval = qla2x00_init_firmware(vha, ha->init_cb_size);
8ae6d9c7 2107next_check:
1da177e4 2108 if (rval) {
7c3df132
SK		 2109 ql_log(ql_log_fatal, vha, 0x00d2,
2110 "Init Firmware **** FAILED ****.\n");
1da177e4 2111 } else {
7c3df132
SK		 2112 ql_dbg(ql_dbg_init, vha, 0x00d3,
2113 "Init Firmware -- success.\n");
1da177e4
LT		 2114 }
2115
2116 return (rval);
2117}
2118
2119/**
2120 * qla2x00_fw_ready() - Waits for firmware ready.
2121 * @ha: HA context
2122 *
2123 * Returns 0 on success.
2124 */
2125static int
e315cd28 2126qla2x00_fw_ready(scsi_qla_host_t *vha)
1da177e4
LT		 2127{
2128 int rval;
4d4df193 2129 unsigned long wtime, mtime, cs84xx_time;
1da177e4
LT		 2130 uint16_t min_wait; /* Minimum wait time if loop is down */
2131 uint16_t wait_time; /* Wait time if loop is coming ready */
656e8912 2132 uint16_t state[5];
e315cd28 2133 struct qla_hw_data *ha = vha->hw;
1da177e4 2134
8ae6d9c7
GM		 2135 if (IS_QLAFX00(vha->hw))
2136 return qlafx00_fw_ready(vha);
2137
1da177e4
LT		 2138 rval = QLA_SUCCESS;
2139
2140 /* 20 seconds for loop down. */
fa2a1ce5 2141 min_wait = 20;
1da177e4
LT		 2142
2143 /*
2144 * Firmware should take at most one RATOV to login, plus 5 seconds for
2145 * our own processing.
2146 */
2147 if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) {
2148 wait_time = min_wait;
2149 }
2150
2151 /* Min wait time if loop down */
2152 mtime = jiffies + (min_wait * HZ);
2153
2154 /* wait time before firmware ready */
2155 wtime = jiffies + (wait_time * HZ);
2156
2157 /* Wait for ISP to finish LIP */
e315cd28 2158 if (!vha->flags.init_done)
7c3df132
SK		 2159 ql_log(ql_log_info, vha, 0x801e,
2160 "Waiting for LIP to complete.\n");
1da177e4
LT		 2161
2162 do {
5b939038 2163 memset(state, -1, sizeof(state));
e315cd28 2164 rval = qla2x00_get_firmware_state(vha, state);
1da177e4 2165 if (rval == QLA_SUCCESS) {
4d4df193 2166 if (state[0] < FSTATE_LOSS_OF_SYNC) {
e315cd28 2167 vha->device_flags &= ~DFLG_NO_CABLE;
1da177e4 2168 }
4d4df193 2169 if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) {
7c3df132
SK		 2170 ql_dbg(ql_dbg_taskm, vha, 0x801f,
2171 "fw_state=%x 84xx=%x.\n", state[0],
2172 state[2]);
4d4df193
HK		 2173 if ((state[2] & FSTATE_LOGGED_IN) &&
2174 (state[2] & FSTATE_WAITING_FOR_VERIFY)) {
7c3df132
SK		 2175 ql_dbg(ql_dbg_taskm, vha, 0x8028,
2176 "Sending verify iocb.\n");
4d4df193
HK		 2177
2178 cs84xx_time = jiffies;
e315cd28 2179 rval = qla84xx_init_chip(vha);
7c3df132
SK		 2180 if (rval != QLA_SUCCESS) {
2181 ql_log(ql_log_warn,
cfb0919c 2182 vha, 0x8007,
7c3df132 2183 "Init chip failed.\n");
4d4df193 2184 break;
7c3df132 2185 }
4d4df193
HK		 2186
2187 /* Add time taken to initialize. */
2188 cs84xx_time = jiffies - cs84xx_time;
2189 wtime += cs84xx_time;
2190 mtime += cs84xx_time;
cfb0919c 2191 ql_dbg(ql_dbg_taskm, vha, 0x8008,
7c3df132
SK		 2192 "Increasing wait time by %ld. "
2193 "New time %ld.\n", cs84xx_time,
2194 wtime);
4d4df193
HK		 2195 }
2196 } else if (state[0] == FSTATE_READY) {
7c3df132
SK		 2197 ql_dbg(ql_dbg_taskm, vha, 0x8037,
2198 "F/W Ready - OK.\n");
1da177e4 2199
e315cd28 2200 qla2x00_get_retry_cnt(vha, &ha->retry_count,
1da177e4
LT		 2201 &ha->login_timeout, &ha->r_a_tov);
2202
2203 rval = QLA_SUCCESS;
2204 break;
2205 }
2206
2207 rval = QLA_FUNCTION_FAILED;
2208
e315cd28 2209 if (atomic_read(&vha->loop_down_timer) &&
4d4df193 2210 state[0] != FSTATE_READY) {
1da177e4 2211 /* Loop down. Timeout on min_wait for states
fa2a1ce5
AV		 2212 * other than Wait for Login.
2213 */
1da177e4 2214 if (time_after_eq(jiffies, mtime)) {
7c3df132 2215 ql_log(ql_log_info, vha, 0x8038,
1da177e4
LT		 2216 "Cable is unplugged...\n");
2217
e315cd28 2218 vha->device_flags |= DFLG_NO_CABLE;
1da177e4
LT		 2219 break;
2220 }
2221 }
2222 } else {
2223 /* Mailbox cmd failed. Timeout on min_wait. */
cdbb0a4f 2224 if (time_after_eq(jiffies, mtime) ||
7190575f 2225 ha->flags.isp82xx_fw_hung)
1da177e4
LT		 2226 break;
2227 }
2228
2229 if (time_after_eq(jiffies, wtime))
2230 break;
2231
2232 /* Delay for a while */
2233 msleep(500);
1da177e4
LT		 2234 } while (1);
2235
7c3df132
SK		 2236 ql_dbg(ql_dbg_taskm, vha, 0x803a,
2237 "fw_state=%x (%x, %x, %x, %x) " "curr time=%lx.\n", state[0],
2238 state[1], state[2], state[3], state[4], jiffies);
1da177e4 2239
cfb0919c 2240 if (rval && !(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132
SK		 2241 ql_log(ql_log_warn, vha, 0x803b,
2242 "Firmware ready **** FAILED ****.\n");
1da177e4
LT		 2243 }
2244
2245 return (rval);
2246}
2247
2248/*
2249* qla2x00_configure_hba
2250* Setup adapter context.
2251*
2252* Input:
2253* ha = adapter state pointer.
2254*
2255* Returns:
2256* 0 = success
2257*
2258* Context:
2259* Kernel context.
2260*/
2261static int
e315cd28 2262qla2x00_configure_hba(scsi_qla_host_t *vha)
1da177e4
LT		 2263{
2264 int rval;
2265 uint16_t loop_id;
2266 uint16_t topo;
2c3dfe3f 2267 uint16_t sw_cap;
1da177e4
LT		 2268 uint8_t al_pa;
2269 uint8_t area;
2270 uint8_t domain;
2271 char connect_type[22];
e315cd28 2272 struct qla_hw_data *ha = vha->hw;
f24b5cb8 2273 unsigned long flags;
61e1b269 2274 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 2275
2276 /* Get host addresses. */
e315cd28 2277 rval = qla2x00_get_adapter_id(vha,
2c3dfe3f 2278 &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
1da177e4 2279 if (rval != QLA_SUCCESS) {
e315cd28 2280 if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
6246b8a1 2281 IS_CNA_CAPABLE(ha) ||
33135aa2 2282 (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
7c3df132
SK		 2283 ql_dbg(ql_dbg_disc, vha, 0x2008,
2284 "Loop is in a transition state.\n");
33135aa2 2285 } else {
7c3df132
SK		 2286 ql_log(ql_log_warn, vha, 0x2009,
2287 "Unable to get host loop ID.\n");
61e1b269
JC		 2288 if (IS_FWI2_CAPABLE(ha) && (vha == base_vha) &&
2289 (rval == QLA_COMMAND_ERROR && loop_id == 0x1b)) {
2290 ql_log(ql_log_warn, vha, 0x1151,
2291 "Doing link init.\n");
2292 if (qla24xx_link_initialize(vha) == QLA_SUCCESS)
2293 return rval;
2294 }
e315cd28 2295 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
33135aa2 2296 }
1da177e4
LT		 2297 return (rval);
2298 }
2299
2300 if (topo == 4) {
7c3df132
SK		 2301 ql_log(ql_log_info, vha, 0x200a,
2302 "Cannot get topology - retrying.\n");
1da177e4
LT		 2303 return (QLA_FUNCTION_FAILED);
2304 }
2305
e315cd28 2306 vha->loop_id = loop_id;
1da177e4
LT		 2307
2308 /* initialize */
2309 ha->min_external_loopid = SNS_FIRST_LOOP_ID;
2310 ha->operating_mode = LOOP;
2c3dfe3f 2311 ha->switch_cap = 0;
1da177e4
LT		 2312
2313 switch (topo) {
2314 case 0:
7c3df132 2315 ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n");
1da177e4
LT		 2316 ha->current_topology = ISP_CFG_NL;
2317 strcpy(connect_type, "(Loop)");
2318 break;
2319
2320 case 1:
7c3df132 2321 ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n");
2c3dfe3f 2322 ha->switch_cap = sw_cap;
1da177e4
LT		 2323 ha->current_topology = ISP_CFG_FL;
2324 strcpy(connect_type, "(FL_Port)");
2325 break;
2326
2327 case 2:
7c3df132 2328 ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n");
1da177e4
LT		 2329 ha->operating_mode = P2P;
2330 ha->current_topology = ISP_CFG_N;
2331 strcpy(connect_type, "(N_Port-to-N_Port)");
2332 break;
2333
2334 case 3:
7c3df132 2335 ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n");
2c3dfe3f 2336 ha->switch_cap = sw_cap;
1da177e4
LT		 2337 ha->operating_mode = P2P;
2338 ha->current_topology = ISP_CFG_F;
2339 strcpy(connect_type, "(F_Port)");
2340 break;
2341
2342 default:
7c3df132
SK		 2343 ql_dbg(ql_dbg_disc, vha, 0x200f,
2344 "HBA in unknown topology %x, using NL.\n", topo);
1da177e4
LT		 2345 ha->current_topology = ISP_CFG_NL;
2346 strcpy(connect_type, "(Loop)");
2347 break;
2348 }
2349
2350 /* Save Host port and loop ID. */
2351 /* byte order - Big Endian */
e315cd28
AC		 2352 vha->d_id.b.domain = domain;
2353 vha->d_id.b.area = area;
2354 vha->d_id.b.al_pa = al_pa;
1da177e4 2355
f24b5cb8 2356 spin_lock_irqsave(&ha->vport_slock, flags);
2d70c103 2357 qlt_update_vp_map(vha, SET_AL_PA);
f24b5cb8 2358 spin_unlock_irqrestore(&ha->vport_slock, flags);
2d70c103 2359
e315cd28 2360 if (!vha->flags.init_done)
7c3df132
SK		 2361 ql_log(ql_log_info, vha, 0x2010,
2362 "Topology - %s, Host Loop address 0x%x.\n",
e315cd28 2363 connect_type, vha->loop_id);
1da177e4 2364
1da177e4
LT		 2365 return(rval);
2366}
2367
a9083016 2368inline void
e315cd28
AC		 2369qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
2370 char *def)
9bb9fcf2
AV		 2371{
2372 char *st, *en;
2373 uint16_t index;
e315cd28 2374 struct qla_hw_data *ha = vha->hw;
ab671149 2375 int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
6246b8a1 2376 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha);
9bb9fcf2
AV		 2377
2378 if (memcmp(model, BINZERO, len) != 0) {
2379 strncpy(ha->model_number, model, len);
2380 st = en = ha->model_number;
2381 en += len - 1;
2382 while (en > st) {
2383 if (*en != 0x20 && *en != 0x00)
2384 break;
2385 *en-- = '\0';
2386 }
2387
2388 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 2389 if (use_tbl &&
2390 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2 2391 index < QLA_MODEL_NAMES)
1ee27146
JC		 2392 strncpy(ha->model_desc,
2393 qla2x00_model_name[index * 2 + 1],
2394 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 2395 } else {
2396 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 2397 if (use_tbl &&
2398 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2
AV		 2399 index < QLA_MODEL_NAMES) {
2400 strcpy(ha->model_number,
2401 qla2x00_model_name[index * 2]);
1ee27146
JC		 2402 strncpy(ha->model_desc,
2403 qla2x00_model_name[index * 2 + 1],
2404 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 2405 } else {
2406 strcpy(ha->model_number, def);
2407 }
2408 }
1ee27146 2409 if (IS_FWI2_CAPABLE(ha))
e315cd28 2410 qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc,
1ee27146 2411 sizeof(ha->model_desc));
9bb9fcf2
AV		 2412}
2413
4e08df3f
DM		 2414/* On sparc systems, obtain port and node WWN from firmware
2415 * properties.
2416 */
e315cd28 2417static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv)
4e08df3f
DM		 2418{
2419#ifdef CONFIG_SPARC
e315cd28 2420 struct qla_hw_data *ha = vha->hw;
4e08df3f 2421 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 2422 struct device_node *dp = pci_device_to_OF_node(pdev);
2423 const u8 *val;
4e08df3f
DM		 2424 int len;
2425
2426 val = of_get_property(dp, "port-wwn", &len);
2427 if (val && len >= WWN_SIZE)
2428 memcpy(nv->port_name, val, WWN_SIZE);
2429
2430 val = of_get_property(dp, "node-wwn", &len);
2431 if (val && len >= WWN_SIZE)
2432 memcpy(nv->node_name, val, WWN_SIZE);
2433#endif
2434}
2435
1da177e4
LT		 2436/*
2437* NVRAM configuration for ISP 2xxx
2438*
2439* Input:
2440* ha = adapter block pointer.
2441*
2442* Output:
2443* initialization control block in response_ring
2444* host adapters parameters in host adapter block
2445*
2446* Returns:
2447* 0 = success.
2448*/
abbd8870 2449int
e315cd28 2450qla2x00_nvram_config(scsi_qla_host_t *vha)
1da177e4 2451{
4e08df3f 2452 int rval;
0107109e
AV		 2453 uint8_t chksum = 0;
2454 uint16_t cnt;
2455 uint8_t *dptr1, *dptr2;
e315cd28 2456 struct qla_hw_data *ha = vha->hw;
0107109e 2457 init_cb_t *icb = ha->init_cb;
281afe19
SJ		 2458 nvram_t *nv = ha->nvram;
2459 uint8_t *ptr = ha->nvram;
3d71644c 2460 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 2461
4e08df3f
DM		 2462 rval = QLA_SUCCESS;
2463
1da177e4 2464 /* Determine NVRAM starting address. */
0107109e 2465 ha->nvram_size = sizeof(nvram_t);
1da177e4
LT		 2466 ha->nvram_base = 0;
2467 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
2468 if ((RD_REG_WORD(&reg->ctrl_status) >> 14) == 1)
2469 ha->nvram_base = 0x80;
2470
2471 /* Get NVRAM data and calculate checksum. */
e315cd28 2472 ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size);
0107109e
AV		 2473 for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++)
2474 chksum += *ptr++;
1da177e4 2475
7c3df132
SK		 2476 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
2477 "Contents of NVRAM.\n");
2478 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
2479 (uint8_t *)nv, ha->nvram_size);
1da177e4
LT		 2480
2481 /* Bad NVRAM data, set defaults parameters. */
2482 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' ||
2483 nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) {
2484 /* Reset NVRAM data. */
7c3df132 2485 ql_log(ql_log_warn, vha, 0x0064,
9e336520 2486 "Inconsistent NVRAM "
7c3df132
SK		 2487 "detected: checksum=0x%x id=%c version=0x%x.\n",
2488 chksum, nv->id[0], nv->nvram_version);
2489 ql_log(ql_log_warn, vha, 0x0065,
2490 "Falling back to "
2491 "functioning (yet invalid -- WWPN) defaults.\n");
4e08df3f
DM		 2492
2493 /*
2494 * Set default initialization control block.
2495 */
2496 memset(nv, 0, ha->nvram_size);
2497 nv->parameter_block_version = ICB_VERSION;
2498
2499 if (IS_QLA23XX(ha)) {
2500 nv->firmware_options[0] = BIT_2 | BIT_1;
2501 nv->firmware_options[1] = BIT_7 | BIT_5;
2502 nv->add_firmware_options[0] = BIT_5;
2503 nv->add_firmware_options[1] = BIT_5 | BIT_4;
2504 nv->frame_payload_size = __constant_cpu_to_le16(2048);
2505 nv->special_options[1] = BIT_7;
2506 } else if (IS_QLA2200(ha)) {
2507 nv->firmware_options[0] = BIT_2 | BIT_1;
2508 nv->firmware_options[1] = BIT_7 | BIT_5;
2509 nv->add_firmware_options[0] = BIT_5;
2510 nv->add_firmware_options[1] = BIT_5 | BIT_4;
2511 nv->frame_payload_size = __constant_cpu_to_le16(1024);
2512 } else if (IS_QLA2100(ha)) {
2513 nv->firmware_options[0] = BIT_3 | BIT_1;
2514 nv->firmware_options[1] = BIT_5;
2515 nv->frame_payload_size = __constant_cpu_to_le16(1024);
2516 }
2517
2518 nv->max_iocb_allocation = __constant_cpu_to_le16(256);
2519 nv->execution_throttle = __constant_cpu_to_le16(16);
2520 nv->retry_count = 8;
2521 nv->retry_delay = 1;
2522
2523 nv->port_name[0] = 33;
2524 nv->port_name[3] = 224;
2525 nv->port_name[4] = 139;
2526
e315cd28 2527 qla2xxx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 2528
2529 nv->login_timeout = 4;
2530
2531 /*
2532 * Set default host adapter parameters
2533 */
2534 nv->host_p[1] = BIT_2;
2535 nv->reset_delay = 5;
2536 nv->port_down_retry_count = 8;
2537 nv->max_luns_per_target = __constant_cpu_to_le16(8);
2538 nv->link_down_timeout = 60;
2539
2540 rval = 1;
1da177e4
LT		 2541 }
2542
2543#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
2544 /*
2545 * The SN2 does not provide BIOS emulation which means you can't change
2546 * potentially bogus BIOS settings. Force the use of default settings
2547 * for link rate and frame size. Hope that the rest of the settings
2548 * are valid.
2549 */
2550 if (ia64_platform_is("sn2")) {
2551 nv->frame_payload_size = __constant_cpu_to_le16(2048);
2552 if (IS_QLA23XX(ha))
2553 nv->special_options[1] = BIT_7;
2554 }
2555#endif
2556
2557 /* Reset Initialization control block */
0107109e 2558 memset(icb, 0, ha->init_cb_size);
1da177e4
LT		 2559
2560 /*
2561 * Setup driver NVRAM options.
2562 */
2563 nv->firmware_options[0] |= (BIT_6 | BIT_1);
2564 nv->firmware_options[0] &= ~(BIT_5 | BIT_4);
2565 nv->firmware_options[1] |= (BIT_5 | BIT_0);
2566 nv->firmware_options[1] &= ~BIT_4;
2567
2568 if (IS_QLA23XX(ha)) {
2569 nv->firmware_options[0] |= BIT_2;
2570 nv->firmware_options[0] &= ~BIT_3;
2d70c103 2571 nv->special_options[0] &= ~BIT_6;
0107109e 2572 nv->add_firmware_options[1] |= BIT_5 | BIT_4;
1da177e4
LT		 2573
2574 if (IS_QLA2300(ha)) {
2575 if (ha->fb_rev == FPM_2310) {
2576 strcpy(ha->model_number, "QLA2310");
2577 } else {
2578 strcpy(ha->model_number, "QLA2300");
2579 }
2580 } else {
e315cd28 2581 qla2x00_set_model_info(vha, nv->model_number,
9bb9fcf2 2582 sizeof(nv->model_number), "QLA23xx");
1da177e4
LT		 2583 }
2584 } else if (IS_QLA2200(ha)) {
2585 nv->firmware_options[0] |= BIT_2;
2586 /*
2587 * 'Point-to-point preferred, else loop' is not a safe
2588 * connection mode setting.
2589 */
2590 if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
2591 (BIT_5 | BIT_4)) {
2592 /* Force 'loop preferred, else point-to-point'. */
2593 nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
2594 nv->add_firmware_options[0] |= BIT_5;
2595 }
2596 strcpy(ha->model_number, "QLA22xx");
2597 } else /*if (IS_QLA2100(ha))*/ {
2598 strcpy(ha->model_number, "QLA2100");
2599 }
2600
2601 /*
2602 * Copy over NVRAM RISC parameter block to initialization control block.
2603 */
2604 dptr1 = (uint8_t *)icb;
2605 dptr2 = (uint8_t *)&nv->parameter_block_version;
2606 cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;
2607 while (cnt--)
2608 *dptr1++ = *dptr2++;
2609
2610 /* Copy 2nd half. */
2611 dptr1 = (uint8_t *)icb->add_firmware_options;
2612 cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;
2613 while (cnt--)
2614 *dptr1++ = *dptr2++;
2615
5341e868
AV		 2616 /* Use alternate WWN? */
2617 if (nv->host_p[1] & BIT_7) {
2618 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
2619 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
2620 }
2621
1da177e4
LT		 2622 /* Prepare nodename */
2623 if ((icb->firmware_options[1] & BIT_6) == 0) {
2624 /*
2625 * Firmware will apply the following mask if the nodename was
2626 * not provided.
2627 */
2628 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
2629 icb->node_name[0] &= 0xF0;
2630 }
2631
2632 /*
2633 * Set host adapter parameters.
2634 */
3ce8866c
SK		 2635
2636 /*
2637 * BIT_7 in the host-parameters section allows for modification to
2638 * internal driver logging.
2639 */
0181944f 2640 if (nv->host_p[0] & BIT_7)
cfb0919c 2641 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
1da177e4
LT		 2642 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
2643 /* Always load RISC code on non ISP2[12]00 chips. */
2644 if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
2645 ha->flags.disable_risc_code_load = 0;
2646 ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0);
2647 ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
2648 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
06c22bd1 2649 ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
d4c760c2 2650 ha->flags.disable_serdes = 0;
1da177e4
LT		 2651
2652 ha->operating_mode =
2653 (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
2654
2655 memcpy(ha->fw_seriallink_options, nv->seriallink_options,
2656 sizeof(ha->fw_seriallink_options));
2657
2658 /* save HBA serial number */
2659 ha->serial0 = icb->port_name[5];
2660 ha->serial1 = icb->port_name[6];
2661 ha->serial2 = icb->port_name[7];
e315cd28
AC		 2662 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
2663 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
1da177e4
LT		 2664
2665 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
2666
2667 ha->retry_count = nv->retry_count;
2668
2669 /* Set minimum login_timeout to 4 seconds. */
5b91490e 2670 if (nv->login_timeout != ql2xlogintimeout)
1da177e4
LT		 2671 nv->login_timeout = ql2xlogintimeout;
2672 if (nv->login_timeout < 4)
2673 nv->login_timeout = 4;
2674 ha->login_timeout = nv->login_timeout;
2675 icb->login_timeout = nv->login_timeout;
2676
00a537b8
AV		 2677 /* Set minimum RATOV to 100 tenths of a second. */
2678 ha->r_a_tov = 100;
1da177e4 2679
1da177e4
LT		 2680 ha->loop_reset_delay = nv->reset_delay;
2681
1da177e4
LT		 2682 /* Link Down Timeout = 0:
2683 *
2684 * When Port Down timer expires we will start returning
2685 * I/O's to OS with "DID_NO_CONNECT".
2686 *
2687 * Link Down Timeout != 0:
2688 *
2689 * The driver waits for the link to come up after link down
2690 * before returning I/Os to OS with "DID_NO_CONNECT".
fa2a1ce5 2691 */
1da177e4
LT		 2692 if (nv->link_down_timeout == 0) {
2693 ha->loop_down_abort_time =
354d6b21 2694 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
1da177e4
LT		 2695 } else {
2696 ha->link_down_timeout = nv->link_down_timeout;
2697 ha->loop_down_abort_time =
2698 (LOOP_DOWN_TIME - ha->link_down_timeout);
fa2a1ce5 2699 }
1da177e4 2700
1da177e4
LT		 2701 /*
2702 * Need enough time to try and get the port back.
2703 */
2704 ha->port_down_retry_count = nv->port_down_retry_count;
2705 if (qlport_down_retry)
2706 ha->port_down_retry_count = qlport_down_retry;
2707 /* Set login_retry_count */
2708 ha->login_retry_count = nv->retry_count;
2709 if (ha->port_down_retry_count == nv->port_down_retry_count &&
2710 ha->port_down_retry_count > 3)
2711 ha->login_retry_count = ha->port_down_retry_count;
2712 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
2713 ha->login_retry_count = ha->port_down_retry_count;
2714 if (ql2xloginretrycount)
2715 ha->login_retry_count = ql2xloginretrycount;
2716
1da177e4
LT		 2717 icb->lun_enables = __constant_cpu_to_le16(0);
2718 icb->command_resource_count = 0;
2719 icb->immediate_notify_resource_count = 0;
2720 icb->timeout = __constant_cpu_to_le16(0);
2721
2722 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
2723 /* Enable RIO */
2724 icb->firmware_options[0] &= ~BIT_3;
2725 icb->add_firmware_options[0] &=
2726 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
2727 icb->add_firmware_options[0] |= BIT_2;
2728 icb->response_accumulation_timer = 3;
2729 icb->interrupt_delay_timer = 5;
2730
e315cd28 2731 vha->flags.process_response_queue = 1;
1da177e4 2732 } else {
4fdfefe5 2733 /* Enable ZIO. */
e315cd28 2734 if (!vha->flags.init_done) {
4fdfefe5
AV		 2735 ha->zio_mode = icb->add_firmware_options[0] &
2736 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
2737 ha->zio_timer = icb->interrupt_delay_timer ?
2738 icb->interrupt_delay_timer: 2;
2739 }
1da177e4
LT		 2740 icb->add_firmware_options[0] &=
2741 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
e315cd28 2742 vha->flags.process_response_queue = 0;
4fdfefe5 2743 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d
AV		 2744 ha->zio_mode = QLA_ZIO_MODE_6;
2745
7c3df132 2746 ql_log(ql_log_info, vha, 0x0068,
4fdfefe5
AV		 2747 "ZIO mode %d enabled; timer delay (%d us).\n",
2748 ha->zio_mode, ha->zio_timer * 100);
1da177e4 2749
4fdfefe5
AV		 2750 icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;
2751 icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;
e315cd28 2752 vha->flags.process_response_queue = 1;
1da177e4
LT		 2753 }
2754 }
2755
4e08df3f 2756 if (rval) {
7c3df132
SK		 2757 ql_log(ql_log_warn, vha, 0x0069,
2758 "NVRAM configuration failed.\n");
4e08df3f
DM		 2759 }
2760 return (rval);
1da177e4
LT		 2761}
2762
19a7b4ae
JSEC		 2763static void
2764qla2x00_rport_del(void *data)
2765{
2766 fc_port_t *fcport = data;
d97994dc 2767 struct fc_rport *rport;
2d70c103 2768 scsi_qla_host_t *vha = fcport->vha;
044d78e1 2769 unsigned long flags;
d97994dc 2770
044d78e1 2771 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
ac280b67 2772 rport = fcport->drport ? fcport->drport: fcport->rport;
d97994dc 2773 fcport->drport = NULL;
044d78e1 2774 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
2d70c103 2775 if (rport) {
d97994dc 2776 fc_remote_port_delete(rport);
2d70c103
NB		 2777 /*
2778 * Release the target mode FC NEXUS in qla_target.c code
2779 * if target mod is enabled.
2780 */
2781 qlt_fc_port_deleted(vha, fcport);
2782 }
19a7b4ae
JSEC		 2783}
2784
1da177e4
LT		 2785/**
2786 * qla2x00_alloc_fcport() - Allocate a generic fcport.
2787 * @ha: HA context
2788 * @flags: allocation flags
2789 *
2790 * Returns a pointer to the allocated fcport, or NULL, if none available.
2791 */
9a069e19 2792fc_port_t *
e315cd28 2793qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags)
1da177e4
LT		 2794{
2795 fc_port_t *fcport;
2796
bbfbbbc1
MK		 2797 fcport = kzalloc(sizeof(fc_port_t), flags);
2798 if (!fcport)
2799 return NULL;
1da177e4
LT		 2800
2801 /* Setup fcport template structure. */
e315cd28 2802 fcport->vha = vha;
1da177e4
LT		 2803 fcport->port_type = FCT_UNKNOWN;
2804 fcport->loop_id = FC_NO_LOOP_ID;
ec426e10 2805 qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
ad3e0eda 2806 fcport->supported_classes = FC_COS_UNSPECIFIED;
1da177e4 2807
bbfbbbc1 2808 return fcport;
1da177e4
LT		 2809}
2810
2811/*
2812 * qla2x00_configure_loop
2813 * Updates Fibre Channel Device Database with what is actually on loop.
2814 *
2815 * Input:
2816 * ha = adapter block pointer.
2817 *
2818 * Returns:
2819 * 0 = success.
2820 * 1 = error.
2821 * 2 = database was full and device was not configured.
2822 */
2823static int
e315cd28 2824qla2x00_configure_loop(scsi_qla_host_t *vha)
1da177e4
LT		 2825{
2826 int rval;
2827 unsigned long flags, save_flags;
e315cd28 2828 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2829 rval = QLA_SUCCESS;
2830
2831 /* Get Initiator ID */
e315cd28
AC		 2832 if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) {
2833 rval = qla2x00_configure_hba(vha);
1da177e4 2834 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2835 ql_dbg(ql_dbg_disc, vha, 0x2013,
2836 "Unable to configure HBA.\n");
1da177e4
LT		 2837 return (rval);
2838 }
2839 }
2840
e315cd28 2841 save_flags = flags = vha->dpc_flags;
7c3df132
SK		 2842 ql_dbg(ql_dbg_disc, vha, 0x2014,
2843 "Configure loop -- dpc flags = 0x%lx.\n", flags);
1da177e4
LT		 2844
2845 /*
2846 * If we have both an RSCN and PORT UPDATE pending then handle them
2847 * both at the same time.
2848 */
e315cd28
AC		 2849 clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2850 clear_bit(RSCN_UPDATE, &vha->dpc_flags);
1da177e4 2851
3064ff39
MH		 2852 qla2x00_get_data_rate(vha);
2853
1da177e4
LT		 2854 /* Determine what we need to do */
2855 if (ha->current_topology == ISP_CFG_FL &&
2856 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
2857
1da177e4
LT		 2858 set_bit(RSCN_UPDATE, &flags);
2859
2860 } else if (ha->current_topology == ISP_CFG_F &&
2861 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
2862
1da177e4
LT		 2863 set_bit(RSCN_UPDATE, &flags);
2864 clear_bit(LOCAL_LOOP_UPDATE, &flags);
21333b48
AV		 2865
2866 } else if (ha->current_topology == ISP_CFG_N) {
2867 clear_bit(RSCN_UPDATE, &flags);
1da177e4 2868
e315cd28 2869 } else if (!vha->flags.online ||
1da177e4
LT		 2870 (test_bit(ABORT_ISP_ACTIVE, &flags))) {
2871
1da177e4
LT		 2872 set_bit(RSCN_UPDATE, &flags);
2873 set_bit(LOCAL_LOOP_UPDATE, &flags);
2874 }
2875
2876 if (test_bit(LOCAL_LOOP_UPDATE, &flags)) {
7c3df132
SK		 2877 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
2878 ql_dbg(ql_dbg_disc, vha, 0x2015,
2879 "Loop resync needed, failing.\n");
1da177e4 2880 rval = QLA_FUNCTION_FAILED;
642ef983 2881 } else
e315cd28 2882 rval = qla2x00_configure_local_loop(vha);
1da177e4
LT		 2883 }
2884
2885 if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
7c3df132
SK		 2886 if (LOOP_TRANSITION(vha)) {
2887 ql_dbg(ql_dbg_disc, vha, 0x201e,
2888 "Needs RSCN update and loop transition.\n");
1da177e4 2889 rval = QLA_FUNCTION_FAILED;
7c3df132 2890 }
e315cd28
AC		 2891 else
2892 rval = qla2x00_configure_fabric(vha);
1da177e4
LT		 2893 }
2894
2895 if (rval == QLA_SUCCESS) {
e315cd28
AC		 2896 if (atomic_read(&vha->loop_down_timer) ||
2897 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4
LT		 2898 rval = QLA_FUNCTION_FAILED;
2899 } else {
e315cd28 2900 atomic_set(&vha->loop_state, LOOP_READY);
7c3df132
SK		 2901 ql_dbg(ql_dbg_disc, vha, 0x2069,
2902 "LOOP READY.\n");
1da177e4
LT		 2903 }
2904 }
2905
2906 if (rval) {
7c3df132
SK		 2907 ql_dbg(ql_dbg_disc, vha, 0x206a,
2908 "%s *** FAILED ***.\n", __func__);
1da177e4 2909 } else {
7c3df132
SK		 2910 ql_dbg(ql_dbg_disc, vha, 0x206b,
2911 "%s: exiting normally.\n", __func__);
1da177e4
LT		 2912 }
2913
cc3ef7bc 2914 /* Restore state if a resync event occurred during processing */
e315cd28 2915 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4 2916 if (test_bit(LOCAL_LOOP_UPDATE, &save_flags))
e315cd28 2917 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
f4658b6c 2918 if (test_bit(RSCN_UPDATE, &save_flags)) {
e315cd28 2919 set_bit(RSCN_UPDATE, &vha->dpc_flags);
f4658b6c 2920 }
1da177e4
LT		 2921 }
2922
2923 return (rval);
2924}
2925
2926
2927
2928/*
2929 * qla2x00_configure_local_loop
2930 * Updates Fibre Channel Device Database with local loop devices.
2931 *
2932 * Input:
2933 * ha = adapter block pointer.
2934 *
2935 * Returns:
2936 * 0 = success.
2937 */
2938static int
e315cd28 2939qla2x00_configure_local_loop(scsi_qla_host_t *vha)
1da177e4
LT		 2940{
2941 int rval, rval2;
2942 int found_devs;
2943 int found;
2944 fc_port_t *fcport, *new_fcport;
2945
2946 uint16_t index;
2947 uint16_t entries;
2948 char *id_iter;
2949 uint16_t loop_id;
2950 uint8_t domain, area, al_pa;
e315cd28 2951 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2952
2953 found_devs = 0;
2954 new_fcport = NULL;
642ef983 2955 entries = MAX_FIBRE_DEVICES_LOOP;
1da177e4 2956
1da177e4 2957 /* Get list of logged in devices. */
642ef983 2958 memset(ha->gid_list, 0, qla2x00_gid_list_size(ha));
e315cd28 2959 rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma,
1da177e4
LT		 2960 &entries);
2961 if (rval != QLA_SUCCESS)
2962 goto cleanup_allocation;
2963
7c3df132
SK		 2964 ql_dbg(ql_dbg_disc, vha, 0x2017,
2965 "Entries in ID list (%d).\n", entries);
2966 ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
2967 (uint8_t *)ha->gid_list,
2968 entries * sizeof(struct gid_list_info));
1da177e4
LT		 2969
2970 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 2971 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 2972 if (new_fcport == NULL) {
7c3df132
SK		 2973 ql_log(ql_log_warn, vha, 0x2018,
2974 "Memory allocation failed for fcport.\n");
1da177e4
LT		 2975 rval = QLA_MEMORY_ALLOC_FAILED;
2976 goto cleanup_allocation;
2977 }
2978 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
2979
2980 /*
2981 * Mark local devices that were present with FCF_DEVICE_LOST for now.
2982 */
e315cd28 2983 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 2984 if (atomic_read(&fcport->state) == FCS_ONLINE &&
2985 fcport->port_type != FCT_BROADCAST &&
2986 (fcport->flags & FCF_FABRIC_DEVICE) == 0) {
2987
7c3df132
SK		 2988 ql_dbg(ql_dbg_disc, vha, 0x2019,
2989 "Marking port lost loop_id=0x%04x.\n",
2990 fcport->loop_id);
1da177e4 2991
ec426e10 2992 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 2993 }
2994 }
2995
2996 /* Add devices to port list. */
2997 id_iter = (char *)ha->gid_list;
2998 for (index = 0; index < entries; index++) {
2999 domain = ((struct gid_list_info *)id_iter)->domain;
3000 area = ((struct gid_list_info *)id_iter)->area;
3001 al_pa = ((struct gid_list_info *)id_iter)->al_pa;
abbd8870 3002 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1da177e4
LT		 3003 loop_id = (uint16_t)
3004 ((struct gid_list_info *)id_iter)->loop_id_2100;
abbd8870 3005 else
1da177e4
LT		 3006 loop_id = le16_to_cpu(
3007 ((struct gid_list_info *)id_iter)->loop_id);
abbd8870 3008 id_iter += ha->gid_list_info_size;
1da177e4
LT		 3009
3010 /* Bypass reserved domain fields. */
3011 if ((domain & 0xf0) == 0xf0)
3012 continue;
3013
3014 /* Bypass if not same domain and area of adapter. */
f7d289f6 3015 if (area && domain &&
e315cd28 3016 (area != vha->d_id.b.area || domain != vha->d_id.b.domain))
1da177e4
LT		 3017 continue;
3018
3019 /* Bypass invalid local loop ID. */
3020 if (loop_id > LAST_LOCAL_LOOP_ID)
3021 continue;
3022
370d550e
AE		 3023 memset(new_fcport, 0, sizeof(fc_port_t));
3024
1da177e4
LT		 3025 /* Fill in member data. */
3026 new_fcport->d_id.b.domain = domain;
3027 new_fcport->d_id.b.area = area;
3028 new_fcport->d_id.b.al_pa = al_pa;
3029 new_fcport->loop_id = loop_id;
e315cd28 3030 rval2 = qla2x00_get_port_database(vha, new_fcport, 0);
1da177e4 3031 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 3032 ql_dbg(ql_dbg_disc, vha, 0x201a,
3033 "Failed to retrieve fcport information "
3034 "-- get_port_database=%x, loop_id=0x%04x.\n",
3035 rval2, new_fcport->loop_id);
3036 ql_dbg(ql_dbg_disc, vha, 0x201b,
3037 "Scheduling resync.\n");
e315cd28 3038 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4
LT		 3039 continue;
3040 }
3041
3042 /* Check for matching device in port list. */
3043 found = 0;
3044 fcport = NULL;
e315cd28 3045 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 3046 if (memcmp(new_fcport->port_name, fcport->port_name,
3047 WWN_SIZE))
3048 continue;
3049
ddb9b126 3050 fcport->flags &= ~FCF_FABRIC_DEVICE;
1da177e4
LT		 3051 fcport->loop_id = new_fcport->loop_id;
3052 fcport->port_type = new_fcport->port_type;
3053 fcport->d_id.b24 = new_fcport->d_id.b24;
3054 memcpy(fcport->node_name, new_fcport->node_name,
3055 WWN_SIZE);
3056
3057 found++;
3058 break;
3059 }
3060
3061 if (!found) {
3062 /* New device, add to fcports list. */
e315cd28 3063 list_add_tail(&new_fcport->list, &vha->vp_fcports);
1da177e4
LT		 3064
3065 /* Allocate a new replacement fcport. */
3066 fcport = new_fcport;
e315cd28 3067 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3068 if (new_fcport == NULL) {
7c3df132
SK		 3069 ql_log(ql_log_warn, vha, 0x201c,
3070 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 3071 rval = QLA_MEMORY_ALLOC_FAILED;
3072 goto cleanup_allocation;
3073 }
3074 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
3075 }
3076
d8b45213 3077 /* Base iIDMA settings on HBA port speed. */
a3cbdfad 3078 fcport->fp_speed = ha->link_data_rate;
d8b45213 3079
e315cd28 3080 qla2x00_update_fcport(vha, fcport);
1da177e4
LT		 3081
3082 found_devs++;
3083 }
3084
3085cleanup_allocation:
c9475cb0 3086 kfree(new_fcport);
1da177e4
LT		 3087
3088 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3089 ql_dbg(ql_dbg_disc, vha, 0x201d,
3090 "Configure local loop error exit: rval=%x.\n", rval);
1da177e4
LT		 3091 }
3092
1da177e4
LT		 3093 return (rval);
3094}
3095
d8b45213 3096static void
e315cd28 3097qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
d8b45213 3098{
d8b45213 3099 int rval;
1bb39548 3100 uint16_t mb[4];
e315cd28 3101 struct qla_hw_data *ha = vha->hw;
d8b45213 3102
c76f2c01 3103 if (!IS_IIDMA_CAPABLE(ha))
d8b45213
AV		 3104 return;
3105
c9afb9a2
GM		 3106 if (atomic_read(&fcport->state) != FCS_ONLINE)
3107 return;
3108
39bd9622
AV		 3109 if (fcport->fp_speed == PORT_SPEED_UNKNOWN ||
3110 fcport->fp_speed > ha->link_data_rate)
d8b45213
AV		 3111 return;
3112
e315cd28 3113 rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed,
a3cbdfad 3114 mb);
d8b45213 3115 if (rval != QLA_SUCCESS) {
7c3df132 3116 ql_dbg(ql_dbg_disc, vha, 0x2004,
7b833558
OK		 3117 "Unable to adjust iIDMA %8phN -- %04x %x %04x %04x.\n",
3118 fcport->port_name, rval, fcport->fp_speed, mb[0], mb[1]);
d8b45213 3119 } else {
7c3df132 3120 ql_dbg(ql_dbg_disc, vha, 0x2005,
7b833558 3121 "iIDMA adjusted to %s GB/s on %8phN.\n",
d0297c9a 3122 qla2x00_get_link_speed_str(ha, fcport->fp_speed),
7b833558 3123 fcport->port_name);
d8b45213
AV		 3124 }
3125}
3126
23be331d 3127static void
e315cd28 3128qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport)
8482e118
AV		 3129{
3130 struct fc_rport_identifiers rport_ids;
bdf79621 3131 struct fc_rport *rport;
044d78e1 3132 unsigned long flags;
8482e118 3133
ac280b67 3134 qla2x00_rport_del(fcport);
8482e118 3135
f8b02a85
AV		 3136 rport_ids.node_name = wwn_to_u64(fcport->node_name);
3137 rport_ids.port_name = wwn_to_u64(fcport->port_name);
8482e118
AV		 3138 rport_ids.port_id = fcport->d_id.b.domain << 16 |
3139 fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa;
77d74143 3140 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
e315cd28 3141 fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids);
77d74143 3142 if (!rport) {
7c3df132
SK		 3143 ql_log(ql_log_warn, vha, 0x2006,
3144 "Unable to allocate fc remote port.\n");
77d74143
AV		 3145 return;
3146 }
2d70c103
NB		 3147 /*
3148 * Create target mode FC NEXUS in qla_target.c if target mode is
3149 * enabled..
3150 */
3151 qlt_fc_port_added(vha, fcport);
3152
044d78e1 3153 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
19a7b4ae 3154 *((fc_port_t **)rport->dd_data) = fcport;
044d78e1 3155 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
d97994dc 3156
ad3e0eda 3157 rport->supported_classes = fcport->supported_classes;
77d74143 3158
8482e118
AV		 3159 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
3160 if (fcport->port_type == FCT_INITIATOR)
3161 rport_ids.roles |= FC_RPORT_ROLE_FCP_INITIATOR;
3162 if (fcport->port_type == FCT_TARGET)
3163 rport_ids.roles |= FC_RPORT_ROLE_FCP_TARGET;
77d74143 3164 fc_remote_port_rolechg(rport, rport_ids.roles);
1da177e4
LT		 3165}
3166
23be331d
AB		 3167/*
3168 * qla2x00_update_fcport
3169 * Updates device on list.
3170 *
3171 * Input:
3172 * ha = adapter block pointer.
3173 * fcport = port structure pointer.
3174 *
3175 * Return:
3176 * 0 - Success
3177 * BIT_0 - error
3178 *
3179 * Context:
3180 * Kernel context.
3181 */
3182void
e315cd28 3183qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
23be331d 3184{
e315cd28 3185 fcport->vha = vha;
8ae6d9c7
GM		 3186
3187 if (IS_QLAFX00(vha->hw)) {
3188 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
3189 qla2x00_reg_remote_port(vha, fcport);
3190 return;
3191 }
23be331d 3192 fcport->login_retry = 0;
5ff1d584 3193 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
23be331d 3194
1f93da52 3195 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
e315cd28 3196 qla2x00_iidma_fcport(vha, fcport);
21090cbe 3197 qla24xx_update_fcport_fcp_prio(vha, fcport);
e315cd28 3198 qla2x00_reg_remote_port(vha, fcport);
23be331d
AB		 3199}
3200
1da177e4
LT		 3201/*
3202 * qla2x00_configure_fabric
3203 * Setup SNS devices with loop ID's.
3204 *
3205 * Input:
3206 * ha = adapter block pointer.
3207 *
3208 * Returns:
3209 * 0 = success.
3210 * BIT_0 = error
3211 */
3212static int
e315cd28 3213qla2x00_configure_fabric(scsi_qla_host_t *vha)
1da177e4 3214{
b3b02e6e 3215 int rval;
e452ceb6 3216 fc_port_t *fcport, *fcptemp;
1da177e4
LT		 3217 uint16_t next_loopid;
3218 uint16_t mb[MAILBOX_REGISTER_COUNT];
0107109e 3219 uint16_t loop_id;
1da177e4 3220 LIST_HEAD(new_fcports);
e315cd28
AC		 3221 struct qla_hw_data *ha = vha->hw;
3222 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 3223
3224 /* If FL port exists, then SNS is present */
e428924c 3225 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 3226 loop_id = NPH_F_PORT;
3227 else
3228 loop_id = SNS_FL_PORT;
e315cd28 3229 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1);
1da177e4 3230 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3231 ql_dbg(ql_dbg_disc, vha, 0x201f,
3232 "MBX_GET_PORT_NAME failed, No FL Port.\n");
1da177e4 3233
e315cd28 3234 vha->device_flags &= ~SWITCH_FOUND;
1da177e4
LT		 3235 return (QLA_SUCCESS);
3236 }
e315cd28 3237 vha->device_flags |= SWITCH_FOUND;
1da177e4 3238
1da177e4 3239 do {
cca5335c
AV		 3240 /* FDMI support. */
3241 if (ql2xfdmienable &&
e315cd28
AC		 3242 test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags))
3243 qla2x00_fdmi_register(vha);
cca5335c 3244
1da177e4 3245 /* Ensure we are logged into the SNS. */
e428924c 3246 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 3247 loop_id = NPH_SNS;
3248 else
3249 loop_id = SIMPLE_NAME_SERVER;
0b91d116
CD		 3250 rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff,
3251 0xfc, mb, BIT_1|BIT_0);
3252 if (rval != QLA_SUCCESS) {
3253 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
e452ceb6 3254 return rval;
0b91d116 3255 }
1da177e4 3256 if (mb[0] != MBS_COMMAND_COMPLETE) {
7c3df132
SK		 3257 ql_dbg(ql_dbg_disc, vha, 0x2042,
3258 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x "
3259 "mb[6]=%x mb[7]=%x.\n", loop_id, mb[0], mb[1],
3260 mb[2], mb[6], mb[7]);
1da177e4
LT		 3261 return (QLA_SUCCESS);
3262 }
3263
e315cd28
AC		 3264 if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) {
3265 if (qla2x00_rft_id(vha)) {
1da177e4 3266 /* EMPTY */
7c3df132
SK		 3267 ql_dbg(ql_dbg_disc, vha, 0x2045,
3268 "Register FC-4 TYPE failed.\n");
1da177e4 3269 }
e315cd28 3270 if (qla2x00_rff_id(vha)) {
1da177e4 3271 /* EMPTY */
7c3df132
SK		 3272 ql_dbg(ql_dbg_disc, vha, 0x2049,
3273 "Register FC-4 Features failed.\n");
1da177e4 3274 }
e315cd28 3275 if (qla2x00_rnn_id(vha)) {
1da177e4 3276 /* EMPTY */
7c3df132
SK		 3277 ql_dbg(ql_dbg_disc, vha, 0x204f,
3278 "Register Node Name failed.\n");
e315cd28 3279 } else if (qla2x00_rsnn_nn(vha)) {
1da177e4 3280 /* EMPTY */
7c3df132
SK		 3281 ql_dbg(ql_dbg_disc, vha, 0x2053,
3282 "Register Symobilic Node Name failed.\n");
1da177e4
LT		 3283 }
3284 }
3285
827210ba
JC		 3286#define QLA_FCPORT_SCAN 1
3287#define QLA_FCPORT_FOUND 2
3288
3289 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3290 fcport->scan_state = QLA_FCPORT_SCAN;
3291 }
3292
e315cd28 3293 rval = qla2x00_find_all_fabric_devs(vha, &new_fcports);
1da177e4
LT		 3294 if (rval != QLA_SUCCESS)
3295 break;
3296
e452ceb6
JC		 3297 /*
3298 * Logout all previous fabric devices marked lost, except
3299 * FCP2 devices.
3300 */
e315cd28
AC		 3301 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3302 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
1da177e4
LT		 3303 break;
3304
3305 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0)
3306 continue;
3307
827210ba 3308 if (fcport->scan_state == QLA_FCPORT_SCAN &&
b3b02e6e 3309 atomic_read(&fcport->state) == FCS_ONLINE) {
e315cd28 3310 qla2x00_mark_device_lost(vha, fcport,
d97994dc 3311 ql2xplogiabsentdevice, 0);
1da177e4 3312 if (fcport->loop_id != FC_NO_LOOP_ID &&
f08b7251 3313 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
1da177e4
LT		 3314 fcport->port_type != FCT_INITIATOR &&
3315 fcport->port_type != FCT_BROADCAST) {
e315cd28 3316 ha->isp_ops->fabric_logout(vha,
1c7c6357
AV		 3317 fcport->loop_id,
3318 fcport->d_id.b.domain,
3319 fcport->d_id.b.area,
3320 fcport->d_id.b.al_pa);
e452ceb6 3321 fcport->loop_id = FC_NO_LOOP_ID;
1da177e4
LT		 3322 }
3323 }
e452ceb6 3324 }
1da177e4 3325
e452ceb6
JC		 3326 /* Starting free loop ID. */
3327 next_loopid = ha->min_external_loopid;
3328
3329 /*
3330 * Scan through our port list and login entries that need to be
3331 * logged in.
3332 */
3333 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3334 if (atomic_read(&vha->loop_down_timer) ||
3335 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3336 break;
3337
3338 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0 ||
3339 (fcport->flags & FCF_LOGIN_NEEDED) == 0)
3340 continue;
3341
3342 if (fcport->loop_id == FC_NO_LOOP_ID) {
3343 fcport->loop_id = next_loopid;
3344 rval = qla2x00_find_new_loop_id(
3345 base_vha, fcport);
3346 if (rval != QLA_SUCCESS) {
3347 /* Ran out of IDs to use */
3348 break;
1da177e4
LT		 3349 }
3350 }
e452ceb6
JC		 3351 /* Login and update database */
3352 qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
3353 }
3354
3355 /* Exit if out of loop IDs. */
3356 if (rval != QLA_SUCCESS) {
3357 break;
3358 }
3359
3360 /*
3361 * Login and add the new devices to our port list.
3362 */
3363 list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) {
3364 if (atomic_read(&vha->loop_down_timer) ||
3365 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3366 break;
3367
3368 /* Find a new loop ID to use. */
3369 fcport->loop_id = next_loopid;
3370 rval = qla2x00_find_new_loop_id(base_vha, fcport);
3371 if (rval != QLA_SUCCESS) {
3372 /* Ran out of IDs to use */
3373 break;
3374 }
1da177e4 3375
bdf79621 3376 /* Login and update database */
e315cd28 3377 qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
e452ceb6
JC		 3378
3379 list_move_tail(&fcport->list, &vha->vp_fcports);
1da177e4
LT		 3380 }
3381 } while (0);
3382
e452ceb6
JC		 3383 /* Free all new device structures not processed. */
3384 list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) {
3385 list_del(&fcport->list);
3386 kfree(fcport);
3387 }
3388
1da177e4 3389 if (rval) {
7c3df132
SK		 3390 ql_dbg(ql_dbg_disc, vha, 0x2068,
3391 "Configure fabric error exit rval=%d.\n", rval);
1da177e4
LT		 3392 }
3393
3394 return (rval);
3395}
3396
1da177e4
LT		 3397/*
3398 * qla2x00_find_all_fabric_devs
3399 *
3400 * Input:
3401 * ha = adapter block pointer.
3402 * dev = database device entry pointer.
3403 *
3404 * Returns:
3405 * 0 = success.
3406 *
3407 * Context:
3408 * Kernel context.
3409 */
3410static int
e315cd28
AC		 3411qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha,
3412 struct list_head *new_fcports)
1da177e4
LT		 3413{
3414 int rval;
3415 uint16_t loop_id;
3416 fc_port_t *fcport, *new_fcport, *fcptemp;
3417 int found;
3418
3419 sw_info_t *swl;
3420 int swl_idx;
3421 int first_dev, last_dev;
1516ef44 3422 port_id_t wrap = {}, nxt_d_id;
e315cd28 3423 struct qla_hw_data *ha = vha->hw;
bb4cf5b7 3424 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 3425
3426 rval = QLA_SUCCESS;
3427
3428 /* Try GID_PT to get device list, else GAN. */
7a67735b 3429 if (!ha->swl)
642ef983 3430 ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t),
7a67735b
AV		 3431 GFP_KERNEL);
3432 swl = ha->swl;
bbfbbbc1 3433 if (!swl) {
1da177e4 3434 /*EMPTY*/
7c3df132
SK		 3435 ql_dbg(ql_dbg_disc, vha, 0x2054,
3436 "GID_PT allocations failed, fallback on GA_NXT.\n");
1da177e4 3437 } else {
642ef983 3438 memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t));
e315cd28 3439 if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) {
1da177e4 3440 swl = NULL;
e315cd28 3441 } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 3442 swl = NULL;
e315cd28 3443 } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 3444 swl = NULL;
e5896bd5 3445 } else if (ql2xiidmaenable &&
e315cd28
AC		 3446 qla2x00_gfpn_id(vha, swl) == QLA_SUCCESS) {
3447 qla2x00_gpsc(vha, swl);
1da177e4 3448 }
e8c72ba5
CD		 3449
3450 /* If other queries succeeded probe for FC-4 type */
3451 if (swl)
3452 qla2x00_gff_id(vha, swl);
1da177e4
LT		 3453 }
3454 swl_idx = 0;
3455
3456 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 3457 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3458 if (new_fcport == NULL) {
7c3df132
SK		 3459 ql_log(ql_log_warn, vha, 0x205e,
3460 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 3461 return (QLA_MEMORY_ALLOC_FAILED);
3462 }
3463 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
1da177e4
LT		 3464 /* Set start port ID scan at adapter ID. */
3465 first_dev = 1;
3466 last_dev = 0;
3467
3468 /* Starting free loop ID. */
e315cd28
AC		 3469 loop_id = ha->min_external_loopid;
3470 for (; loop_id <= ha->max_loop_id; loop_id++) {
3471 if (qla2x00_is_reserved_id(vha, loop_id))
1da177e4
LT		 3472 continue;
3473
3a6478df
GM		 3474 if (ha->current_topology == ISP_CFG_FL &&
3475 (atomic_read(&vha->loop_down_timer) ||
3476 LOOP_TRANSITION(vha))) {
bb2d52b2
AV		 3477 atomic_set(&vha->loop_down_timer, 0);
3478 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
3479 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
1da177e4 3480 break;
bb2d52b2 3481 }
1da177e4
LT		 3482
3483 if (swl != NULL) {
3484 if (last_dev) {
3485 wrap.b24 = new_fcport->d_id.b24;
3486 } else {
3487 new_fcport->d_id.b24 = swl[swl_idx].d_id.b24;
3488 memcpy(new_fcport->node_name,
3489 swl[swl_idx].node_name, WWN_SIZE);
3490 memcpy(new_fcport->port_name,
3491 swl[swl_idx].port_name, WWN_SIZE);
d8b45213
AV		 3492 memcpy(new_fcport->fabric_port_name,
3493 swl[swl_idx].fabric_port_name, WWN_SIZE);
3494 new_fcport->fp_speed = swl[swl_idx].fp_speed;
e8c72ba5 3495 new_fcport->fc4_type = swl[swl_idx].fc4_type;
1da177e4
LT		 3496
3497 if (swl[swl_idx].d_id.b.rsvd_1 != 0) {
3498 last_dev = 1;
3499 }
3500 swl_idx++;
3501 }
3502 } else {
3503 /* Send GA_NXT to the switch */
e315cd28 3504 rval = qla2x00_ga_nxt(vha, new_fcport);
1da177e4 3505 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3506 ql_log(ql_log_warn, vha, 0x2064,
3507 "SNS scan failed -- assuming "
3508 "zero-entry result.\n");
1da177e4
LT		 3509 list_for_each_entry_safe(fcport, fcptemp,
3510 new_fcports, list) {
3511 list_del(&fcport->list);
3512 kfree(fcport);
3513 }
3514 rval = QLA_SUCCESS;
3515 break;
3516 }
3517 }
3518
3519 /* If wrap on switch device list, exit. */
3520 if (first_dev) {
3521 wrap.b24 = new_fcport->d_id.b24;
3522 first_dev = 0;
3523 } else if (new_fcport->d_id.b24 == wrap.b24) {
7c3df132
SK		 3524 ql_dbg(ql_dbg_disc, vha, 0x2065,
3525 "Device wrap (%02x%02x%02x).\n",
3526 new_fcport->d_id.b.domain,
3527 new_fcport->d_id.b.area,
3528 new_fcport->d_id.b.al_pa);
1da177e4
LT		 3529 break;
3530 }
3531
2c3dfe3f 3532 /* Bypass if same physical adapter. */
e315cd28 3533 if (new_fcport->d_id.b24 == base_vha->d_id.b24)
1da177e4
LT		 3534 continue;
3535
2c3dfe3f 3536 /* Bypass virtual ports of the same host. */
bb4cf5b7
CD		 3537 if (qla2x00_is_a_vp_did(vha, new_fcport->d_id.b24))
3538 continue;
2c3dfe3f 3539
f7d289f6
AV		 3540 /* Bypass if same domain and area of adapter. */
3541 if (((new_fcport->d_id.b24 & 0xffff00) ==
e315cd28 3542 (vha->d_id.b24 & 0xffff00)) && ha->current_topology ==
f7d289f6
AV		 3543 ISP_CFG_FL)
3544 continue;
3545
1da177e4
LT		 3546 /* Bypass reserved domain fields. */
3547 if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0)
3548 continue;
3549
e8c72ba5 3550 /* Bypass ports whose FCP-4 type is not FCP_SCSI */
4da26e16
CD		 3551 if (ql2xgffidenable &&
3552 (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI &&
3553 new_fcport->fc4_type != FC4_TYPE_UNKNOWN))
e8c72ba5
CD		 3554 continue;
3555
1da177e4
LT		 3556 /* Locate matching device in database. */
3557 found = 0;
e315cd28 3558 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 3559 if (memcmp(new_fcport->port_name, fcport->port_name,
3560 WWN_SIZE))
3561 continue;
3562
827210ba 3563 fcport->scan_state = QLA_FCPORT_FOUND;
b3b02e6e 3564
1da177e4
LT		 3565 found++;
3566
d8b45213
AV		 3567 /* Update port state. */
3568 memcpy(fcport->fabric_port_name,
3569 new_fcport->fabric_port_name, WWN_SIZE);
3570 fcport->fp_speed = new_fcport->fp_speed;
3571
1da177e4
LT		 3572 /*
3573 * If address the same and state FCS_ONLINE, nothing
3574 * changed.
3575 */
3576 if (fcport->d_id.b24 == new_fcport->d_id.b24 &&
3577 atomic_read(&fcport->state) == FCS_ONLINE) {
3578 break;
3579 }
3580
3581 /*
3582 * If device was not a fabric device before.
3583 */
3584 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) {
3585 fcport->d_id.b24 = new_fcport->d_id.b24;
5f16b331 3586 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 3587 fcport->flags |= (FCF_FABRIC_DEVICE |
3588 FCF_LOGIN_NEEDED);
1da177e4
LT		 3589 break;
3590 }
3591
3592 /*
3593 * Port ID changed or device was marked to be updated;
3594 * Log it out if still logged in and mark it for
3595 * relogin later.
3596 */
3597 fcport->d_id.b24 = new_fcport->d_id.b24;
3598 fcport->flags |= FCF_LOGIN_NEEDED;
3599 if (fcport->loop_id != FC_NO_LOOP_ID &&
f08b7251 3600 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
0eba25df 3601 (fcport->flags & FCF_ASYNC_SENT) == 0 &&
1da177e4
LT		 3602 fcport->port_type != FCT_INITIATOR &&
3603 fcport->port_type != FCT_BROADCAST) {
e315cd28 3604 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3605 fcport->d_id.b.domain, fcport->d_id.b.area,
3606 fcport->d_id.b.al_pa);
5f16b331 3607 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 3608 }
3609
3610 break;
3611 }
3612
3613 if (found)
3614 continue;
1da177e4
LT		 3615 /* If device was not in our fcports list, then add it. */
3616 list_add_tail(&new_fcport->list, new_fcports);
3617
3618 /* Allocate a new replacement fcport. */
3619 nxt_d_id.b24 = new_fcport->d_id.b24;
e315cd28 3620 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3621 if (new_fcport == NULL) {
7c3df132
SK		 3622 ql_log(ql_log_warn, vha, 0x2066,
3623 "Memory allocation failed for fcport.\n");
1da177e4
LT		 3624 return (QLA_MEMORY_ALLOC_FAILED);
3625 }
3626 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
3627 new_fcport->d_id.b24 = nxt_d_id.b24;
3628 }
3629
c9475cb0 3630 kfree(new_fcport);
1da177e4 3631
1da177e4
LT		 3632 return (rval);
3633}
3634
3635/*
3636 * qla2x00_find_new_loop_id
3637 * Scan through our port list and find a new usable loop ID.
3638 *
3639 * Input:
3640 * ha: adapter state pointer.
3641 * dev: port structure pointer.
3642 *
3643 * Returns:
3644 * qla2x00 local function return status code.
3645 *
3646 * Context:
3647 * Kernel context.
3648 */
03bcfb57 3649int
e315cd28 3650qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
1da177e4
LT		 3651{
3652 int rval;
e315cd28 3653 struct qla_hw_data *ha = vha->hw;
feafb7b1 3654 unsigned long flags = 0;
1da177e4
LT		 3655
3656 rval = QLA_SUCCESS;
3657
5f16b331 3658 spin_lock_irqsave(&ha->vport_slock, flags);
1da177e4 3659
5f16b331
CD		 3660 dev->loop_id = find_first_zero_bit(ha->loop_id_map,
3661 LOOPID_MAP_SIZE);
3662 if (dev->loop_id >= LOOPID_MAP_SIZE ||
3663 qla2x00_is_reserved_id(vha, dev->loop_id)) {
3664 dev->loop_id = FC_NO_LOOP_ID;
3665 rval = QLA_FUNCTION_FAILED;
3666 } else
3667 set_bit(dev->loop_id, ha->loop_id_map);
1da177e4 3668
5f16b331 3669 spin_unlock_irqrestore(&ha->vport_slock, flags);
1da177e4 3670
5f16b331
CD		 3671 if (rval == QLA_SUCCESS)
3672 ql_dbg(ql_dbg_disc, dev->vha, 0x2086,
3673 "Assigning new loopid=%x, portid=%x.\n",
3674 dev->loop_id, dev->d_id.b24);
3675 else
3676 ql_log(ql_log_warn, dev->vha, 0x2087,
3677 "No loop_id's available, portid=%x.\n",
3678 dev->d_id.b24);
1da177e4
LT		 3679
3680 return (rval);
3681}
3682
1da177e4
LT		 3683/*
3684 * qla2x00_fabric_dev_login
3685 * Login fabric target device and update FC port database.
3686 *
3687 * Input:
3688 * ha: adapter state pointer.
3689 * fcport: port structure list pointer.
3690 * next_loopid: contains value of a new loop ID that can be used
3691 * by the next login attempt.
3692 *
3693 * Returns:
3694 * qla2x00 local function return status code.
3695 *
3696 * Context:
3697 * Kernel context.
3698 */
3699static int
e315cd28 3700qla2x00_fabric_dev_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 3701 uint16_t *next_loopid)
3702{
3703 int rval;
3704 int retry;
0107109e 3705 uint8_t opts;
e315cd28 3706 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3707
3708 rval = QLA_SUCCESS;
3709 retry = 0;
3710
ac280b67 3711 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584
AV		 3712 if (fcport->flags & FCF_ASYNC_SENT)
3713 return rval;
3714 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 3715 rval = qla2x00_post_async_login_work(vha, fcport, NULL);
3716 if (!rval)
3717 return rval;
3718 }
3719
5ff1d584 3720 fcport->flags &= ~FCF_ASYNC_SENT;
e315cd28 3721 rval = qla2x00_fabric_login(vha, fcport, next_loopid);
1da177e4 3722 if (rval == QLA_SUCCESS) {
f08b7251 3723 /* Send an ADISC to FCP2 devices.*/
0107109e 3724 opts = 0;
f08b7251 3725 if (fcport->flags & FCF_FCP2_DEVICE)
0107109e 3726 opts |= BIT_1;
e315cd28 3727 rval = qla2x00_get_port_database(vha, fcport, opts);
1da177e4 3728 if (rval != QLA_SUCCESS) {
e315cd28 3729 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3730 fcport->d_id.b.domain, fcport->d_id.b.area,
3731 fcport->d_id.b.al_pa);
e315cd28 3732 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4 3733 } else {
e315cd28 3734 qla2x00_update_fcport(vha, fcport);
1da177e4 3735 }
0b91d116
CD		 3736 } else {
3737 /* Retry Login. */
3738 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 3739 }
3740
3741 return (rval);
3742}
3743
3744/*
3745 * qla2x00_fabric_login
3746 * Issue fabric login command.
3747 *
3748 * Input:
3749 * ha = adapter block pointer.
3750 * device = pointer to FC device type structure.
3751 *
3752 * Returns:
3753 * 0 - Login successfully
3754 * 1 - Login failed
3755 * 2 - Initiator device
3756 * 3 - Fatal error
3757 */
3758int
e315cd28 3759qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 3760 uint16_t *next_loopid)
3761{
3762 int rval;
3763 int retry;
3764 uint16_t tmp_loopid;
3765 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 3766 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3767
3768 retry = 0;
3769 tmp_loopid = 0;
3770
3771 for (;;) {
7c3df132
SK		 3772 ql_dbg(ql_dbg_disc, vha, 0x2000,
3773 "Trying Fabric Login w/loop id 0x%04x for port "
3774 "%02x%02x%02x.\n",
3775 fcport->loop_id, fcport->d_id.b.domain,
3776 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 3777
3778 /* Login fcport on switch. */
0b91d116 3779 rval = ha->isp_ops->fabric_login(vha, fcport->loop_id,
1da177e4
LT		 3780 fcport->d_id.b.domain, fcport->d_id.b.area,
3781 fcport->d_id.b.al_pa, mb, BIT_0);
0b91d116
CD		 3782 if (rval != QLA_SUCCESS) {
3783 return rval;
3784 }
1da177e4
LT		 3785 if (mb[0] == MBS_PORT_ID_USED) {
3786 /*
3787 * Device has another loop ID. The firmware team
0107109e
AV		 3788 * recommends the driver perform an implicit login with
3789 * the specified ID again. The ID we just used is save
3790 * here so we return with an ID that can be tried by
3791 * the next login.
1da177e4
LT		 3792 */
3793 retry++;
3794 tmp_loopid = fcport->loop_id;
3795 fcport->loop_id = mb[1];
3796
7c3df132
SK		 3797 ql_dbg(ql_dbg_disc, vha, 0x2001,
3798 "Fabric Login: port in use - next loop "
3799 "id=0x%04x, port id= %02x%02x%02x.\n",
1da177e4 3800 fcport->loop_id, fcport->d_id.b.domain,
7c3df132 3801 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 3802
3803 } else if (mb[0] == MBS_COMMAND_COMPLETE) {
3804 /*
3805 * Login succeeded.
3806 */
3807 if (retry) {
3808 /* A retry occurred before. */
3809 *next_loopid = tmp_loopid;
3810 } else {
3811 /*
3812 * No retry occurred before. Just increment the
3813 * ID value for next login.
3814 */
3815 *next_loopid = (fcport->loop_id + 1);
3816 }
3817
3818 if (mb[1] & BIT_0) {
3819 fcport->port_type = FCT_INITIATOR;
3820 } else {
3821 fcport->port_type = FCT_TARGET;
3822 if (mb[1] & BIT_1) {
8474f3a0 3823 fcport->flags |= FCF_FCP2_DEVICE;
1da177e4
LT		 3824 }
3825 }
3826
ad3e0eda
AV		 3827 if (mb[10] & BIT_0)
3828 fcport->supported_classes |= FC_COS_CLASS2;
3829 if (mb[10] & BIT_1)
3830 fcport->supported_classes |= FC_COS_CLASS3;
3831
2d70c103
NB		 3832 if (IS_FWI2_CAPABLE(ha)) {
3833 if (mb[10] & BIT_7)
3834 fcport->flags |=
3835 FCF_CONF_COMP_SUPPORTED;
3836 }
3837
1da177e4
LT		 3838 rval = QLA_SUCCESS;
3839 break;
3840 } else if (mb[0] == MBS_LOOP_ID_USED) {
3841 /*
3842 * Loop ID already used, try next loop ID.
3843 */
3844 fcport->loop_id++;
e315cd28 3845 rval = qla2x00_find_new_loop_id(vha, fcport);
1da177e4
LT		 3846 if (rval != QLA_SUCCESS) {
3847 /* Ran out of loop IDs to use */
3848 break;
3849 }
3850 } else if (mb[0] == MBS_COMMAND_ERROR) {
3851 /*
3852 * Firmware possibly timed out during login. If NO
3853 * retries are left to do then the device is declared
3854 * dead.
3855 */
3856 *next_loopid = fcport->loop_id;
e315cd28 3857 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3858 fcport->d_id.b.domain, fcport->d_id.b.area,
3859 fcport->d_id.b.al_pa);
e315cd28 3860 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 3861
3862 rval = 1;
3863 break;
3864 } else {
3865 /*
3866 * unrecoverable / not handled error
3867 */
7c3df132
SK		 3868 ql_dbg(ql_dbg_disc, vha, 0x2002,
3869 "Failed=%x port_id=%02x%02x%02x loop_id=%x "
3870 "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain,
3871 fcport->d_id.b.area, fcport->d_id.b.al_pa,
3872 fcport->loop_id, jiffies);
1da177e4
LT		 3873
3874 *next_loopid = fcport->loop_id;
e315cd28 3875 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3876 fcport->d_id.b.domain, fcport->d_id.b.area,
3877 fcport->d_id.b.al_pa);
5f16b331 3878 qla2x00_clear_loop_id(fcport);
0eedfcf0 3879 fcport->login_retry = 0;
1da177e4
LT		 3880
3881 rval = 3;
3882 break;
3883 }
3884 }
3885
3886 return (rval);
3887}
3888
3889/*
3890 * qla2x00_local_device_login
3891 * Issue local device login command.
3892 *
3893 * Input:
3894 * ha = adapter block pointer.
3895 * loop_id = loop id of device to login to.
3896 *
3897 * Returns (Where's the #define!!!!):
3898 * 0 - Login successfully
3899 * 1 - Login failed
3900 * 3 - Fatal error
3901 */
3902int
e315cd28 3903qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport)
1da177e4
LT		 3904{
3905 int rval;
3906 uint16_t mb[MAILBOX_REGISTER_COUNT];
3907
3908 memset(mb, 0, sizeof(mb));
e315cd28 3909 rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0);
1da177e4
LT		 3910 if (rval == QLA_SUCCESS) {
3911 /* Interrogate mailbox registers for any errors */
3912 if (mb[0] == MBS_COMMAND_ERROR)
3913 rval = 1;
3914 else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR)
3915 /* device not in PCB table */
3916 rval = 3;
3917 }
3918
3919 return (rval);
3920}
3921
3922/*
3923 * qla2x00_loop_resync
3924 * Resync with fibre channel devices.
3925 *
3926 * Input:
3927 * ha = adapter block pointer.
3928 *
3929 * Returns:
3930 * 0 = success
3931 */
3932int
e315cd28 3933qla2x00_loop_resync(scsi_qla_host_t *vha)
1da177e4 3934{
73208dfd 3935 int rval = QLA_SUCCESS;
1da177e4 3936 uint32_t wait_time;
67c2e93a
AC		 3937 struct req_que *req;
3938 struct rsp_que *rsp;
3939
7163ea81 3940 if (vha->hw->flags.cpu_affinity_enabled)
67c2e93a
AC		 3941 req = vha->hw->req_q_map[0];
3942 else
3943 req = vha->req;
3944 rsp = req->rsp;
1da177e4 3945
e315cd28
AC		 3946 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
3947 if (vha->flags.online) {
3948 if (!(rval = qla2x00_fw_ready(vha))) {
1da177e4
LT		 3949 /* Wait at most MAX_TARGET RSCNs for a stable link. */
3950 wait_time = 256;
3951 do {
8ae6d9c7
GM		 3952 if (!IS_QLAFX00(vha->hw)) {
3953 /*
3954 * Issue a marker after FW becomes
3955 * ready.
3956 */
3957 qla2x00_marker(vha, req, rsp, 0, 0,
3958 MK_SYNC_ALL);
3959 vha->marker_needed = 0;
3960 }
1da177e4
LT		 3961
3962 /* Remap devices on Loop. */
e315cd28 3963 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4 3964
8ae6d9c7
GM		 3965 if (IS_QLAFX00(vha->hw))
3966 qlafx00_configure_devices(vha);
3967 else
3968 qla2x00_configure_loop(vha);
3969
1da177e4 3970 wait_time--;
e315cd28
AC		 3971 } while (!atomic_read(&vha->loop_down_timer) &&
3972 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
3973 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
3974 &vha->dpc_flags)));
1da177e4 3975 }
1da177e4
LT		 3976 }
3977
e315cd28 3978 if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
1da177e4 3979 return (QLA_FUNCTION_FAILED);
1da177e4 3980
e315cd28 3981 if (rval)
7c3df132
SK		 3982 ql_dbg(ql_dbg_disc, vha, 0x206c,
3983 "%s *** FAILED ***.\n", __func__);
1da177e4
LT		 3984
3985 return (rval);
3986}
3987
579d12b5
SK		 3988/*
3989* qla2x00_perform_loop_resync
3990* Description: This function will set the appropriate flags and call
3991* qla2x00_loop_resync. If successful loop will be resynced
3992* Arguments : scsi_qla_host_t pointer
3993* returm : Success or Failure
3994*/
3995
3996int qla2x00_perform_loop_resync(scsi_qla_host_t *ha)
3997{
3998 int32_t rval = 0;
3999
4000 if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) {
4001 /*Configure the flags so that resync happens properly*/
4002 atomic_set(&ha->loop_down_timer, 0);
4003 if (!(ha->device_flags & DFLG_NO_CABLE)) {
4004 atomic_set(&ha->loop_state, LOOP_UP);
4005 set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags);
4006 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
4007 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
4008
4009 rval = qla2x00_loop_resync(ha);
4010 } else
4011 atomic_set(&ha->loop_state, LOOP_DEAD);
4012
4013 clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags);
4014 }
4015
4016 return rval;
4017}
4018
d97994dc 4019void
67becc00 4020qla2x00_update_fcports(scsi_qla_host_t *base_vha)
d97994dc
AV		 4021{
4022 fc_port_t *fcport;
feafb7b1
AE		 4023 struct scsi_qla_host *vha;
4024 struct qla_hw_data *ha = base_vha->hw;
4025 unsigned long flags;
d97994dc 4026
feafb7b1 4027 spin_lock_irqsave(&ha->vport_slock, flags);
d97994dc 4028 /* Go with deferred removal of rport references. */
feafb7b1
AE		 4029 list_for_each_entry(vha, &base_vha->hw->vp_list, list) {
4030 atomic_inc(&vha->vref_count);
4031 list_for_each_entry(fcport, &vha->vp_fcports, list) {
8ae598d0 4032 if (fcport->drport &&
feafb7b1
AE		 4033 atomic_read(&fcport->state) != FCS_UNCONFIGURED) {
4034 spin_unlock_irqrestore(&ha->vport_slock, flags);
67becc00 4035 qla2x00_rport_del(fcport);
feafb7b1
AE		 4036 spin_lock_irqsave(&ha->vport_slock, flags);
4037 }
4038 }
4039 atomic_dec(&vha->vref_count);
4040 }
4041 spin_unlock_irqrestore(&ha->vport_slock, flags);
d97994dc
AV		 4042}
4043
7d613ac6
SV		 4044/* Assumes idc_lock always held on entry */
4045void
4046qla83xx_reset_ownership(scsi_qla_host_t *vha)
4047{
4048 struct qla_hw_data *ha = vha->hw;
4049 uint32_t drv_presence, drv_presence_mask;
4050 uint32_t dev_part_info1, dev_part_info2, class_type;
4051 uint32_t class_type_mask = 0x3;
4052 uint16_t fcoe_other_function = 0xffff, i;
4053
7ec0effd
AD		 4054 if (IS_QLA8044(ha)) {
4055 drv_presence = qla8044_rd_direct(vha,
4056 QLA8044_CRB_DRV_ACTIVE_INDEX);
4057 dev_part_info1 = qla8044_rd_direct(vha,
4058 QLA8044_CRB_DEV_PART_INFO_INDEX);
4059 dev_part_info2 = qla8044_rd_direct(vha,
4060 QLA8044_CRB_DEV_PART_INFO2);
4061 } else {
4062 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4063 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1);
4064 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2);
4065 }
7d613ac6
SV		 4066 for (i = 0; i < 8; i++) {
4067 class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask);
4068 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
4069 (i != ha->portnum)) {
4070 fcoe_other_function = i;
4071 break;
4072 }
4073 }
4074 if (fcoe_other_function == 0xffff) {
4075 for (i = 0; i < 8; i++) {
4076 class_type = ((dev_part_info2 >> (i * 4)) &
4077 class_type_mask);
4078 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
4079 ((i + 8) != ha->portnum)) {
4080 fcoe_other_function = i + 8;
4081 break;
4082 }
4083 }
4084 }
4085 /*
4086 * Prepare drv-presence mask based on fcoe functions present.
4087 * However consider only valid physical fcoe function numbers (0-15).
4088 */
4089 drv_presence_mask = ~((1 << (ha->portnum)) |
4090 ((fcoe_other_function == 0xffff) ?
4091 0 : (1 << (fcoe_other_function))));
4092
4093 /* We are the reset owner iff:
4094 * - No other protocol drivers present.
4095 * - This is the lowest among fcoe functions. */
4096 if (!(drv_presence & drv_presence_mask) &&
4097 (ha->portnum < fcoe_other_function)) {
4098 ql_dbg(ql_dbg_p3p, vha, 0xb07f,
4099 "This host is Reset owner.\n");
4100 ha->flags.nic_core_reset_owner = 1;
4101 }
4102}
4103
fa492630 4104static int
7d613ac6
SV		 4105__qla83xx_set_drv_ack(scsi_qla_host_t *vha)
4106{
4107 int rval = QLA_SUCCESS;
4108 struct qla_hw_data *ha = vha->hw;
4109 uint32_t drv_ack;
4110
4111 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4112 if (rval == QLA_SUCCESS) {
4113 drv_ack |= (1 << ha->portnum);
4114 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
4115 }
4116
4117 return rval;
4118}
4119
fa492630 4120static int
7d613ac6
SV		 4121__qla83xx_clear_drv_ack(scsi_qla_host_t *vha)
4122{
4123 int rval = QLA_SUCCESS;
4124 struct qla_hw_data *ha = vha->hw;
4125 uint32_t drv_ack;
4126
4127 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4128 if (rval == QLA_SUCCESS) {
4129 drv_ack &= ~(1 << ha->portnum);
4130 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
4131 }
4132
4133 return rval;
4134}
4135
fa492630 4136static const char *
7d613ac6
SV		 4137qla83xx_dev_state_to_string(uint32_t dev_state)
4138{
4139 switch (dev_state) {
4140 case QLA8XXX_DEV_COLD:
4141 return "COLD/RE-INIT";
4142 case QLA8XXX_DEV_INITIALIZING:
4143 return "INITIALIZING";
4144 case QLA8XXX_DEV_READY:
4145 return "READY";
4146 case QLA8XXX_DEV_NEED_RESET:
4147 return "NEED RESET";
4148 case QLA8XXX_DEV_NEED_QUIESCENT:
4149 return "NEED QUIESCENT";
4150 case QLA8XXX_DEV_FAILED:
4151 return "FAILED";
4152 case QLA8XXX_DEV_QUIESCENT:
4153 return "QUIESCENT";
4154 default:
4155 return "Unknown";
4156 }
4157}
4158
4159/* Assumes idc-lock always held on entry */
4160void
4161qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type)
4162{
4163 struct qla_hw_data *ha = vha->hw;
4164 uint32_t idc_audit_reg = 0, duration_secs = 0;
4165
4166 switch (audit_type) {
4167 case IDC_AUDIT_TIMESTAMP:
4168 ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000);
4169 idc_audit_reg = (ha->portnum) |
4170 (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8);
4171 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
4172 break;
4173
4174 case IDC_AUDIT_COMPLETION:
4175 duration_secs = ((jiffies_to_msecs(jiffies) -
4176 jiffies_to_msecs(ha->idc_audit_ts)) / 1000);
4177 idc_audit_reg = (ha->portnum) |
4178 (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8);
4179 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
4180 break;
4181
4182 default:
4183 ql_log(ql_log_warn, vha, 0xb078,
4184 "Invalid audit type specified.\n");
4185 break;
4186 }
4187}
4188
4189/* Assumes idc_lock always held on entry */
fa492630 4190static int
7d613ac6
SV		 4191qla83xx_initiating_reset(scsi_qla_host_t *vha)
4192{
4193 struct qla_hw_data *ha = vha->hw;
4194 uint32_t idc_control, dev_state;
4195
4196 __qla83xx_get_idc_control(vha, &idc_control);
4197 if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) {
4198 ql_log(ql_log_info, vha, 0xb080,
4199 "NIC Core reset has been disabled. idc-control=0x%x\n",
4200 idc_control);
4201 return QLA_FUNCTION_FAILED;
4202 }
4203
4204 /* Set NEED-RESET iff in READY state and we are the reset-owner */
4205 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4206 if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) {
4207 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
4208 QLA8XXX_DEV_NEED_RESET);
4209 ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n");
4210 qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP);
4211 } else {
4212 const char *state = qla83xx_dev_state_to_string(dev_state);
4213 ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n", state);
4214
4215 /* SV: XXX: Is timeout required here? */
4216 /* Wait for IDC state change READY -> NEED_RESET */
4217 while (dev_state == QLA8XXX_DEV_READY) {
4218 qla83xx_idc_unlock(vha, 0);
4219 msleep(200);
4220 qla83xx_idc_lock(vha, 0);
4221 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4222 }
4223 }
4224
4225 /* Send IDC ack by writing to drv-ack register */
4226 __qla83xx_set_drv_ack(vha);
4227
4228 return QLA_SUCCESS;
4229}
4230
4231int
4232__qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control)
4233{
4234 return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
4235}
4236
7d613ac6
SV		 4237int
4238__qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control)
4239{
4240 return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
4241}
4242
fa492630 4243static int
7d613ac6
SV		 4244qla83xx_check_driver_presence(scsi_qla_host_t *vha)
4245{
4246 uint32_t drv_presence = 0;
4247 struct qla_hw_data *ha = vha->hw;
4248
4249 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4250 if (drv_presence & (1 << ha->portnum))
4251 return QLA_SUCCESS;
4252 else
4253 return QLA_TEST_FAILED;
4254}
4255
4256int
4257qla83xx_nic_core_reset(scsi_qla_host_t *vha)
4258{
4259 int rval = QLA_SUCCESS;
4260 struct qla_hw_data *ha = vha->hw;
4261
4262 ql_dbg(ql_dbg_p3p, vha, 0xb058,
4263 "Entered %s().\n", __func__);
4264
4265 if (vha->device_flags & DFLG_DEV_FAILED) {
4266 ql_log(ql_log_warn, vha, 0xb059,
4267 "Device in unrecoverable FAILED state.\n");
4268 return QLA_FUNCTION_FAILED;
4269 }
4270
4271 qla83xx_idc_lock(vha, 0);
4272
4273 if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) {
4274 ql_log(ql_log_warn, vha, 0xb05a,
4275 "Function=0x%x has been removed from IDC participation.\n",
4276 ha->portnum);
4277 rval = QLA_FUNCTION_FAILED;
4278 goto exit;
4279 }
4280
4281 qla83xx_reset_ownership(vha);
4282
4283 rval = qla83xx_initiating_reset(vha);
4284
4285 /*
4286 * Perform reset if we are the reset-owner,
4287 * else wait till IDC state changes to READY/FAILED.
4288 */
4289 if (rval == QLA_SUCCESS) {
4290 rval = qla83xx_idc_state_handler(vha);
4291
4292 if (rval == QLA_SUCCESS)
4293 ha->flags.nic_core_hung = 0;
4294 __qla83xx_clear_drv_ack(vha);
4295 }
4296
4297exit:
4298 qla83xx_idc_unlock(vha, 0);
4299
4300 ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__);
4301
4302 return rval;
4303}
4304
81178772
SK		 4305int
4306qla2xxx_mctp_dump(scsi_qla_host_t *vha)
4307{
4308 struct qla_hw_data *ha = vha->hw;
4309 int rval = QLA_FUNCTION_FAILED;
4310
4311 if (!IS_MCTP_CAPABLE(ha)) {
4312 /* This message can be removed from the final version */
4313 ql_log(ql_log_info, vha, 0x506d,
4314 "This board is not MCTP capable\n");
4315 return rval;
4316 }
4317
4318 if (!ha->mctp_dump) {
4319 ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev,
4320 MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL);
4321
4322 if (!ha->mctp_dump) {
4323 ql_log(ql_log_warn, vha, 0x506e,
4324 "Failed to allocate memory for mctp dump\n");
4325 return rval;
4326 }
4327 }
4328
4329#define MCTP_DUMP_STR_ADDR 0x00000000
4330 rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma,
4331 MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4);
4332 if (rval != QLA_SUCCESS) {
4333 ql_log(ql_log_warn, vha, 0x506f,
4334 "Failed to capture mctp dump\n");
4335 } else {
4336 ql_log(ql_log_info, vha, 0x5070,
4337 "Mctp dump capture for host (%ld/%p).\n",
4338 vha->host_no, ha->mctp_dump);
4339 ha->mctp_dumped = 1;
4340 }
4341
409ee0fe 4342 if (!ha->flags.nic_core_reset_hdlr_active && !ha->portnum) {
81178772
SK		 4343 ha->flags.nic_core_reset_hdlr_active = 1;
4344 rval = qla83xx_restart_nic_firmware(vha);
4345 if (rval)
4346 /* NIC Core reset failed. */
4347 ql_log(ql_log_warn, vha, 0x5071,
4348 "Failed to restart nic firmware\n");
4349 else
4350 ql_dbg(ql_dbg_p3p, vha, 0xb084,
4351 "Restarted NIC firmware successfully.\n");
4352 ha->flags.nic_core_reset_hdlr_active = 0;
4353 }
4354
4355 return rval;
4356
4357}
4358
579d12b5 4359/*
8fcd6b8b 4360* qla2x00_quiesce_io
579d12b5
SK		 4361* Description: This function will block the new I/Os
4362* Its not aborting any I/Os as context
4363* is not destroyed during quiescence
4364* Arguments: scsi_qla_host_t
4365* return : void
4366*/
4367void
8fcd6b8b 4368qla2x00_quiesce_io(scsi_qla_host_t *vha)
579d12b5
SK		 4369{
4370 struct qla_hw_data *ha = vha->hw;
4371 struct scsi_qla_host *vp;
4372
8fcd6b8b
CD		 4373 ql_dbg(ql_dbg_dpc, vha, 0x401d,
4374 "Quiescing I/O - ha=%p.\n", ha);
579d12b5
SK		 4375
4376 atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME);
4377 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
4378 atomic_set(&vha->loop_state, LOOP_DOWN);
4379 qla2x00_mark_all_devices_lost(vha, 0);
4380 list_for_each_entry(vp, &ha->vp_list, list)
8fcd6b8b 4381 qla2x00_mark_all_devices_lost(vp, 0);
579d12b5
SK		 4382 } else {
4383 if (!atomic_read(&vha->loop_down_timer))
4384 atomic_set(&vha->loop_down_timer,
4385 LOOP_DOWN_TIME);
4386 }
4387 /* Wait for pending cmds to complete */
4388 qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST);
4389}
4390
a9083016
GM		 4391void
4392qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
4393{
4394 struct qla_hw_data *ha = vha->hw;
579d12b5 4395 struct scsi_qla_host *vp;
feafb7b1 4396 unsigned long flags;
6aef87be 4397 fc_port_t *fcport;
a9083016 4398
e46ef004
SK		 4399 /* For ISP82XX, driver waits for completion of the commands.
4400 * online flag should be set.
4401 */
7ec0effd 4402 if (!(IS_P3P_TYPE(ha)))
e46ef004 4403 vha->flags.online = 0;
a9083016
GM		 4404 ha->flags.chip_reset_done = 0;
4405 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2be21fa2 4406 vha->qla_stats.total_isp_aborts++;
a9083016 4407
7c3df132
SK		 4408 ql_log(ql_log_info, vha, 0x00af,
4409 "Performing ISP error recovery - ha=%p.\n", ha);
a9083016 4410
e46ef004
SK		 4411 /* For ISP82XX, reset_chip is just disabling interrupts.
4412 * Driver waits for the completion of the commands.
4413 * the interrupts need to be enabled.
4414 */
7ec0effd 4415 if (!(IS_P3P_TYPE(ha)))
a9083016
GM		 4416 ha->isp_ops->reset_chip(vha);
4417
4418 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
4419 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
4420 atomic_set(&vha->loop_state, LOOP_DOWN);
4421 qla2x00_mark_all_devices_lost(vha, 0);
feafb7b1
AE		 4422
4423 spin_lock_irqsave(&ha->vport_slock, flags);
579d12b5 4424 list_for_each_entry(vp, &ha->vp_list, list) {
feafb7b1
AE		 4425 atomic_inc(&vp->vref_count);
4426 spin_unlock_irqrestore(&ha->vport_slock, flags);
4427
a9083016 4428 qla2x00_mark_all_devices_lost(vp, 0);
feafb7b1
AE		 4429
4430 spin_lock_irqsave(&ha->vport_slock, flags);
4431 atomic_dec(&vp->vref_count);
4432 }
4433 spin_unlock_irqrestore(&ha->vport_slock, flags);
a9083016
GM		 4434 } else {
4435 if (!atomic_read(&vha->loop_down_timer))
4436 atomic_set(&vha->loop_down_timer,
4437 LOOP_DOWN_TIME);
4438 }
4439
6aef87be
AV		 4440 /* Clear all async request states across all VPs. */
4441 list_for_each_entry(fcport, &vha->vp_fcports, list)
4442 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
4443 spin_lock_irqsave(&ha->vport_slock, flags);
4444 list_for_each_entry(vp, &ha->vp_list, list) {
4445 atomic_inc(&vp->vref_count);
4446 spin_unlock_irqrestore(&ha->vport_slock, flags);
4447
4448 list_for_each_entry(fcport, &vp->vp_fcports, list)
4449 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
4450
4451 spin_lock_irqsave(&ha->vport_slock, flags);
4452 atomic_dec(&vp->vref_count);
4453 }
4454 spin_unlock_irqrestore(&ha->vport_slock, flags);
4455
bddd2d65
LC		 4456 if (!ha->flags.eeh_busy) {
4457 /* Make sure for ISP 82XX IO DMA is complete */
7ec0effd 4458 if (IS_P3P_TYPE(ha)) {
7190575f 4459 qla82xx_chip_reset_cleanup(vha);
7c3df132
SK		 4460 ql_log(ql_log_info, vha, 0x00b4,
4461 "Done chip reset cleanup.\n");
a9083016 4462
e46ef004
SK		 4463 /* Done waiting for pending commands.
4464 * Reset the online flag.
4465 */
4466 vha->flags.online = 0;
4d78c973 4467 }
a9083016 4468
bddd2d65
LC		 4469 /* Requeue all commands in outstanding command list. */
4470 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
4471 }
a9083016
GM		 4472}
4473
1da177e4
LT		 4474/*
4475* qla2x00_abort_isp
4476* Resets ISP and aborts all outstanding commands.
4477*
4478* Input:
4479* ha = adapter block pointer.
4480*
4481* Returns:
4482* 0 = success
4483*/
4484int
e315cd28 4485qla2x00_abort_isp(scsi_qla_host_t *vha)
1da177e4 4486{
476e8978 4487 int rval;
1da177e4 4488 uint8_t status = 0;
e315cd28
AC		 4489 struct qla_hw_data *ha = vha->hw;
4490 struct scsi_qla_host *vp;
73208dfd 4491 struct req_que *req = ha->req_q_map[0];
feafb7b1 4492 unsigned long flags;
1da177e4 4493
e315cd28 4494 if (vha->flags.online) {
a9083016 4495 qla2x00_abort_isp_cleanup(vha);
1da177e4 4496
a6171297
SV		 4497 if (IS_QLA8031(ha)) {
4498 ql_dbg(ql_dbg_p3p, vha, 0xb05c,
4499 "Clearing fcoe driver presence.\n");
4500 if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS)
4501 ql_dbg(ql_dbg_p3p, vha, 0xb073,
4502 "Error while clearing DRV-Presence.\n");
4503 }
4504
85880801
AV		 4505 if (unlikely(pci_channel_offline(ha->pdev) &&
4506 ha->flags.pci_channel_io_perm_failure)) {
4507 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
4508 status = 0;
4509 return status;
4510 }
4511
73208dfd 4512 ha->isp_ops->get_flash_version(vha, req->ring);
30c47662 4513
e315cd28 4514 ha->isp_ops->nvram_config(vha);
1da177e4 4515
e315cd28
AC		 4516 if (!qla2x00_restart_isp(vha)) {
4517 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4 4518
e315cd28 4519 if (!atomic_read(&vha->loop_down_timer)) {
1da177e4
LT		 4520 /*
4521 * Issue marker command only when we are going
4522 * to start the I/O .
4523 */
e315cd28 4524 vha->marker_needed = 1;
1da177e4
LT		 4525 }
4526
e315cd28 4527 vha->flags.online = 1;
1da177e4 4528
fd34f556 4529 ha->isp_ops->enable_intrs(ha);
1da177e4 4530
fa2a1ce5 4531 ha->isp_abort_cnt = 0;
e315cd28 4532 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
476e8978 4533
6246b8a1
GM		 4534 if (IS_QLA81XX(ha) || IS_QLA8031(ha))
4535 qla2x00_get_fw_version(vha);
df613b96
AV		 4536 if (ha->fce) {
4537 ha->flags.fce_enabled = 1;
4538 memset(ha->fce, 0,
4539 fce_calc_size(ha->fce_bufs));
e315cd28 4540 rval = qla2x00_enable_fce_trace(vha,
df613b96
AV		 4541 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
4542 &ha->fce_bufs);
4543 if (rval) {
7c3df132 4544 ql_log(ql_log_warn, vha, 0x8033,
df613b96
AV		 4545 "Unable to reinitialize FCE "
4546 "(%d).\n", rval);
4547 ha->flags.fce_enabled = 0;
4548 }
4549 }
436a7b11
AV		 4550
4551 if (ha->eft) {
4552 memset(ha->eft, 0, EFT_SIZE);
e315cd28 4553 rval = qla2x00_enable_eft_trace(vha,
436a7b11
AV		 4554 ha->eft_dma, EFT_NUM_BUFFERS);
4555 if (rval) {
7c3df132 4556 ql_log(ql_log_warn, vha, 0x8034,
436a7b11
AV		 4557 "Unable to reinitialize EFT "
4558 "(%d).\n", rval);
4559 }
4560 }
1da177e4 4561 } else { /* failed the ISP abort */
e315cd28
AC		 4562 vha->flags.online = 1;
4563 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
1da177e4 4564 if (ha->isp_abort_cnt == 0) {
7c3df132
SK		 4565 ql_log(ql_log_fatal, vha, 0x8035,
4566 "ISP error recover failed - "
4567 "board disabled.\n");
fa2a1ce5 4568 /*
1da177e4
LT		 4569 * The next call disables the board
4570 * completely.
4571 */
e315cd28
AC		 4572 ha->isp_ops->reset_adapter(vha);
4573 vha->flags.online = 0;
1da177e4 4574 clear_bit(ISP_ABORT_RETRY,
e315cd28 4575 &vha->dpc_flags);
1da177e4
LT		 4576 status = 0;
4577 } else { /* schedule another ISP abort */
4578 ha->isp_abort_cnt--;
7c3df132
SK		 4579 ql_dbg(ql_dbg_taskm, vha, 0x8020,
4580 "ISP abort - retry remaining %d.\n",
4581 ha->isp_abort_cnt);
1da177e4
LT		 4582 status = 1;
4583 }
4584 } else {
4585 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
7c3df132
SK		 4586 ql_dbg(ql_dbg_taskm, vha, 0x8021,
4587 "ISP error recovery - retrying (%d) "
4588 "more times.\n", ha->isp_abort_cnt);
e315cd28 4589 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
1da177e4
LT		 4590 status = 1;
4591 }
4592 }
fa2a1ce5 4593
1da177e4
LT		 4594 }
4595
e315cd28 4596 if (!status) {
7c3df132 4597 ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__);
feafb7b1
AE		 4598
4599 spin_lock_irqsave(&ha->vport_slock, flags);
4600 list_for_each_entry(vp, &ha->vp_list, list) {
4601 if (vp->vp_idx) {
4602 atomic_inc(&vp->vref_count);
4603 spin_unlock_irqrestore(&ha->vport_slock, flags);
4604
e315cd28 4605 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 4606
4607 spin_lock_irqsave(&ha->vport_slock, flags);
4608 atomic_dec(&vp->vref_count);
4609 }
e315cd28 4610 }
feafb7b1
AE		 4611 spin_unlock_irqrestore(&ha->vport_slock, flags);
4612
7d613ac6
SV		 4613 if (IS_QLA8031(ha)) {
4614 ql_dbg(ql_dbg_p3p, vha, 0xb05d,
4615 "Setting back fcoe driver presence.\n");
4616 if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS)
4617 ql_dbg(ql_dbg_p3p, vha, 0xb074,
4618 "Error while setting DRV-Presence.\n");
4619 }
e315cd28 4620 } else {
d8424f68
JP		 4621 ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n",
4622 __func__);
1da177e4
LT		 4623 }
4624
4625 return(status);
4626}
4627
4628/*
4629* qla2x00_restart_isp
4630* restarts the ISP after a reset
4631*
4632* Input:
4633* ha = adapter block pointer.
4634*
4635* Returns:
4636* 0 = success
4637*/
4638static int
e315cd28 4639qla2x00_restart_isp(scsi_qla_host_t *vha)
1da177e4 4640{
c6b2fca8 4641 int status = 0;
1da177e4 4642 uint32_t wait_time;
e315cd28 4643 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 4644 struct req_que *req = ha->req_q_map[0];
4645 struct rsp_que *rsp = ha->rsp_q_map[0];
2d70c103 4646 unsigned long flags;
1da177e4
LT		 4647
4648 /* If firmware needs to be loaded */
e315cd28
AC		 4649 if (qla2x00_isp_firmware(vha)) {
4650 vha->flags.online = 0;
4651 status = ha->isp_ops->chip_diag(vha);
4652 if (!status)
4653 status = qla2x00_setup_chip(vha);
1da177e4
LT		 4654 }
4655
e315cd28
AC		 4656 if (!status && !(status = qla2x00_init_rings(vha))) {
4657 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
2533cf67 4658 ha->flags.chip_reset_done = 1;
73208dfd
AC		 4659 /* Initialize the queues in use */
4660 qla25xx_init_queues(ha);
4661
e315cd28
AC		 4662 status = qla2x00_fw_ready(vha);
4663 if (!status) {
7c3df132
SK		 4664 ql_dbg(ql_dbg_taskm, vha, 0x8031,
4665 "Start configure loop status = %d.\n", status);
0107109e
AV		 4666
4667 /* Issue a marker after FW becomes ready. */
73208dfd 4668 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
0107109e 4669
e315cd28 4670 vha->flags.online = 1;
2d70c103
NB		 4671
4672 /*
4673 * Process any ATIO queue entries that came in
4674 * while we weren't online.
4675 */
4676 spin_lock_irqsave(&ha->hardware_lock, flags);
4677 if (qla_tgt_mode_enabled(vha))
4678 qlt_24xx_process_atio_queue(vha);
4679 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4680
1da177e4
LT		 4681 /* Wait at most MAX_TARGET RSCNs for a stable link. */
4682 wait_time = 256;
4683 do {
e315cd28
AC		 4684 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
4685 qla2x00_configure_loop(vha);
1da177e4 4686 wait_time--;
e315cd28
AC		 4687 } while (!atomic_read(&vha->loop_down_timer) &&
4688 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
4689 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
4690 &vha->dpc_flags)));
1da177e4
LT		 4691 }
4692
4693 /* if no cable then assume it's good */
e315cd28 4694 if ((vha->device_flags & DFLG_NO_CABLE))
1da177e4
LT		 4695 status = 0;
4696
7c3df132
SK		 4697 ql_dbg(ql_dbg_taskm, vha, 0x8032,
4698 "Configure loop done, status = 0x%x.\n", status);
1da177e4
LT		 4699 }
4700 return (status);
4701}
4702
73208dfd
AC		 4703static int
4704qla25xx_init_queues(struct qla_hw_data *ha)
4705{
4706 struct rsp_que *rsp = NULL;
4707 struct req_que *req = NULL;
4708 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
4709 int ret = -1;
4710 int i;
4711
2afa19a9 4712 for (i = 1; i < ha->max_rsp_queues; i++) {
73208dfd
AC		 4713 rsp = ha->rsp_q_map[i];
4714 if (rsp) {
4715 rsp->options &= ~BIT_0;
618a7523 4716 ret = qla25xx_init_rsp_que(base_vha, rsp);
73208dfd 4717 if (ret != QLA_SUCCESS)
7c3df132
SK		 4718 ql_dbg(ql_dbg_init, base_vha, 0x00ff,
4719 "%s Rsp que: %d init failed.\n",
4720 __func__, rsp->id);
73208dfd 4721 else
7c3df132
SK		 4722 ql_dbg(ql_dbg_init, base_vha, 0x0100,
4723 "%s Rsp que: %d inited.\n",
4724 __func__, rsp->id);
73208dfd 4725 }
2afa19a9
AC		 4726 }
4727 for (i = 1; i < ha->max_req_queues; i++) {
73208dfd
AC		 4728 req = ha->req_q_map[i];
4729 if (req) {
29bdccbe 4730 /* Clear outstanding commands array. */
73208dfd 4731 req->options &= ~BIT_0;
618a7523 4732 ret = qla25xx_init_req_que(base_vha, req);
73208dfd 4733 if (ret != QLA_SUCCESS)
7c3df132
SK		 4734 ql_dbg(ql_dbg_init, base_vha, 0x0101,
4735 "%s Req que: %d init failed.\n",
4736 __func__, req->id);
73208dfd 4737 else
7c3df132
SK		 4738 ql_dbg(ql_dbg_init, base_vha, 0x0102,
4739 "%s Req que: %d inited.\n",
4740 __func__, req->id);
73208dfd
AC		 4741 }
4742 }
4743 return ret;
4744}
4745
1da177e4
LT		 4746/*
4747* qla2x00_reset_adapter
4748* Reset adapter.
4749*
4750* Input:
4751* ha = adapter block pointer.
4752*/
abbd8870 4753void
e315cd28 4754qla2x00_reset_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 4755{
4756 unsigned long flags = 0;
e315cd28 4757 struct qla_hw_data *ha = vha->hw;
3d71644c 4758 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 4759
e315cd28 4760 vha->flags.online = 0;
fd34f556 4761 ha->isp_ops->disable_intrs(ha);
1da177e4 4762
1da177e4
LT		 4763 spin_lock_irqsave(&ha->hardware_lock, flags);
4764 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
4765 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
4766 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
4767 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
4768 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4769}
0107109e
AV		 4770
4771void
e315cd28 4772qla24xx_reset_adapter(scsi_qla_host_t *vha)
0107109e
AV		 4773{
4774 unsigned long flags = 0;
e315cd28 4775 struct qla_hw_data *ha = vha->hw;
0107109e
AV		 4776 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
4777
7ec0effd 4778 if (IS_P3P_TYPE(ha))
a9083016
GM		 4779 return;
4780
e315cd28 4781 vha->flags.online = 0;
fd34f556 4782 ha->isp_ops->disable_intrs(ha);
0107109e
AV		 4783
4784 spin_lock_irqsave(&ha->hardware_lock, flags);
4785 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
4786 RD_REG_DWORD(&reg->hccr);
4787 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
4788 RD_REG_DWORD(&reg->hccr);
4789 spin_unlock_irqrestore(&ha->hardware_lock, flags);
09ff36d3
AV		 4790
4791 if (IS_NOPOLLING_TYPE(ha))
4792 ha->isp_ops->enable_intrs(ha);
0107109e
AV		 4793}
4794
4e08df3f
DM		 4795/* On sparc systems, obtain port and node WWN from firmware
4796 * properties.
4797 */
e315cd28
AC		 4798static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha,
4799 struct nvram_24xx *nv)
4e08df3f
DM		 4800{
4801#ifdef CONFIG_SPARC
e315cd28 4802 struct qla_hw_data *ha = vha->hw;
4e08df3f 4803 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 4804 struct device_node *dp = pci_device_to_OF_node(pdev);
4805 const u8 *val;
4e08df3f
DM		 4806 int len;
4807
4808 val = of_get_property(dp, "port-wwn", &len);
4809 if (val && len >= WWN_SIZE)
4810 memcpy(nv->port_name, val, WWN_SIZE);
4811
4812 val = of_get_property(dp, "node-wwn", &len);
4813 if (val && len >= WWN_SIZE)
4814 memcpy(nv->node_name, val, WWN_SIZE);
4815#endif
4816}
4817
0107109e 4818int
e315cd28 4819qla24xx_nvram_config(scsi_qla_host_t *vha)
0107109e 4820{
4e08df3f 4821 int rval;
0107109e
AV		 4822 struct init_cb_24xx *icb;
4823 struct nvram_24xx *nv;
4824 uint32_t *dptr;
4825 uint8_t *dptr1, *dptr2;
4826 uint32_t chksum;
4827 uint16_t cnt;
e315cd28 4828 struct qla_hw_data *ha = vha->hw;
0107109e 4829
4e08df3f 4830 rval = QLA_SUCCESS;
0107109e 4831 icb = (struct init_cb_24xx *)ha->init_cb;
281afe19 4832 nv = ha->nvram;
0107109e
AV		 4833
4834 /* Determine NVRAM starting address. */
f73cb695 4835 if (ha->port_no == 0) {
e5b68a61
AC		 4836 ha->nvram_base = FA_NVRAM_FUNC0_ADDR;
4837 ha->vpd_base = FA_NVRAM_VPD0_ADDR;
4838 } else {
0107109e 4839 ha->nvram_base = FA_NVRAM_FUNC1_ADDR;
6f641790
AV		 4840 ha->vpd_base = FA_NVRAM_VPD1_ADDR;
4841 }
f73cb695 4842
e5b68a61
AC		 4843 ha->nvram_size = sizeof(struct nvram_24xx);
4844 ha->vpd_size = FA_NVRAM_VPD_SIZE;
0107109e 4845
281afe19
SJ		 4846 /* Get VPD data into cache */
4847 ha->vpd = ha->nvram + VPD_OFFSET;
e315cd28 4848 ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd,
281afe19
SJ		 4849 ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
4850
4851 /* Get NVRAM data into cache and calculate checksum. */
0107109e 4852 dptr = (uint32_t *)nv;
e315cd28 4853 ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base,
0107109e
AV		 4854 ha->nvram_size);
4855 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
4856 chksum += le32_to_cpu(*dptr++);
4857
7c3df132
SK		 4858 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
4859 "Contents of NVRAM\n");
4860 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
4861 (uint8_t *)nv, ha->nvram_size);
0107109e
AV		 4862
4863 /* Bad NVRAM data, set defaults parameters. */
4864 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
4865 || nv->id[3] != ' ' ||
4866 nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
4867 /* Reset NVRAM data. */
7c3df132 4868 ql_log(ql_log_warn, vha, 0x006b,
9e336520 4869 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132
SK		 4870 "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version);
4871 ql_log(ql_log_warn, vha, 0x006c,
4872 "Falling back to functioning (yet invalid -- WWPN) "
4873 "defaults.\n");
4e08df3f
DM		 4874
4875 /*
4876 * Set default initialization control block.
4877 */
4878 memset(nv, 0, ha->nvram_size);
4879 nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
4880 nv->version = __constant_cpu_to_le16(ICB_VERSION);
4881 nv->frame_payload_size = __constant_cpu_to_le16(2048);
4882 nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
4883 nv->exchange_count = __constant_cpu_to_le16(0);
4884 nv->hard_address = __constant_cpu_to_le16(124);
4885 nv->port_name[0] = 0x21;
f73cb695 4886 nv->port_name[1] = 0x00 + ha->port_no + 1;
4e08df3f
DM		 4887 nv->port_name[2] = 0x00;
4888 nv->port_name[3] = 0xe0;
4889 nv->port_name[4] = 0x8b;
4890 nv->port_name[5] = 0x1c;
4891 nv->port_name[6] = 0x55;
4892 nv->port_name[7] = 0x86;
4893 nv->node_name[0] = 0x20;
4894 nv->node_name[1] = 0x00;
4895 nv->node_name[2] = 0x00;
4896 nv->node_name[3] = 0xe0;
4897 nv->node_name[4] = 0x8b;
4898 nv->node_name[5] = 0x1c;
4899 nv->node_name[6] = 0x55;
4900 nv->node_name[7] = 0x86;
e315cd28 4901 qla24xx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 4902 nv->login_retry_count = __constant_cpu_to_le16(8);
4903 nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
4904 nv->login_timeout = __constant_cpu_to_le16(0);
4905 nv->firmware_options_1 =
4906 __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
4907 nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
4908 nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
4909 nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
4910 nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
4911 nv->efi_parameters = __constant_cpu_to_le32(0);
4912 nv->reset_delay = 5;
4913 nv->max_luns_per_target = __constant_cpu_to_le16(128);
4914 nv->port_down_retry_count = __constant_cpu_to_le16(30);
4915 nv->link_down_timeout = __constant_cpu_to_le16(30);
4916
4917 rval = 1;
0107109e
AV		 4918 }
4919
2d70c103
NB		 4920 if (!qla_ini_mode_enabled(vha)) {
4921 /* Don't enable full login after initial LIP */
4922 nv->firmware_options_1 &= __constant_cpu_to_le32(~BIT_13);
4923 /* Don't enable LIP full login for initiator */
4924 nv->host_p &= __constant_cpu_to_le32(~BIT_10);
4925 }
4926
4927 qlt_24xx_config_nvram_stage1(vha, nv);
4928
0107109e 4929 /* Reset Initialization control block */
e315cd28 4930 memset(icb, 0, ha->init_cb_size);
0107109e
AV		 4931
4932 /* Copy 1st segment. */
4933 dptr1 = (uint8_t *)icb;
4934 dptr2 = (uint8_t *)&nv->version;
4935 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
4936 while (cnt--)
4937 *dptr1++ = *dptr2++;
4938
4939 icb->login_retry_count = nv->login_retry_count;
3ea66e28 4940 icb->link_down_on_nos = nv->link_down_on_nos;
0107109e
AV		 4941
4942 /* Copy 2nd segment. */
4943 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
4944 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
4945 cnt = (uint8_t *)&icb->reserved_3 -
4946 (uint8_t *)&icb->interrupt_delay_timer;
4947 while (cnt--)
4948 *dptr1++ = *dptr2++;
4949
4950 /*
4951 * Setup driver NVRAM options.
4952 */
e315cd28 4953 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
9bb9fcf2 4954 "QLA2462");
0107109e 4955
2d70c103
NB		 4956 qlt_24xx_config_nvram_stage2(vha, icb);
4957
5341e868 4958 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
2d70c103 4959 /* Use alternate WWN? */
5341e868
AV		 4960 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
4961 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
4962 }
4963
0107109e 4964 /* Prepare nodename */
fd0e7e4d 4965 if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
0107109e
AV		 4966 /*
4967 * Firmware will apply the following mask if the nodename was
4968 * not provided.
4969 */
4970 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
4971 icb->node_name[0] &= 0xF0;
4972 }
4973
4974 /* Set host adapter parameters. */
4975 ha->flags.disable_risc_code_load = 0;
0c8c39af
AV		 4976 ha->flags.enable_lip_reset = 0;
4977 ha->flags.enable_lip_full_login =
4978 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
4979 ha->flags.enable_target_reset =
4980 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
0107109e 4981 ha->flags.enable_led_scheme = 0;
d4c760c2 4982 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
0107109e 4983
fd0e7e4d
AV		 4984 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
4985 (BIT_6 | BIT_5 | BIT_4)) >> 4;
0107109e
AV		 4986
4987 memcpy(ha->fw_seriallink_options24, nv->seriallink_options,
4988 sizeof(ha->fw_seriallink_options24));
4989
4990 /* save HBA serial number */
4991 ha->serial0 = icb->port_name[5];
4992 ha->serial1 = icb->port_name[6];
4993 ha->serial2 = icb->port_name[7];
e315cd28
AC		 4994 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
4995 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
0107109e 4996
bc8fb3cb
AV		 4997 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
4998
0107109e
AV		 4999 ha->retry_count = le16_to_cpu(nv->login_retry_count);
5000
5001 /* Set minimum login_timeout to 4 seconds. */
5002 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
5003 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
5004 if (le16_to_cpu(nv->login_timeout) < 4)
5005 nv->login_timeout = __constant_cpu_to_le16(4);
5006 ha->login_timeout = le16_to_cpu(nv->login_timeout);
c6852c4c 5007 icb->login_timeout = nv->login_timeout;
0107109e 5008
00a537b8
AV		 5009 /* Set minimum RATOV to 100 tenths of a second. */
5010 ha->r_a_tov = 100;
0107109e
AV		 5011
5012 ha->loop_reset_delay = nv->reset_delay;
5013
5014 /* Link Down Timeout = 0:
5015 *
5016 * When Port Down timer expires we will start returning
5017 * I/O's to OS with "DID_NO_CONNECT".
5018 *
5019 * Link Down Timeout != 0:
5020 *
5021 * The driver waits for the link to come up after link down
5022 * before returning I/Os to OS with "DID_NO_CONNECT".
5023 */
5024 if (le16_to_cpu(nv->link_down_timeout) == 0) {
5025 ha->loop_down_abort_time =
5026 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
5027 } else {
5028 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
5029 ha->loop_down_abort_time =
5030 (LOOP_DOWN_TIME - ha->link_down_timeout);
5031 }
5032
5033 /* Need enough time to try and get the port back. */
5034 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
5035 if (qlport_down_retry)
5036 ha->port_down_retry_count = qlport_down_retry;
5037
5038 /* Set login_retry_count */
5039 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
5040 if (ha->port_down_retry_count ==
5041 le16_to_cpu(nv->port_down_retry_count) &&
5042 ha->port_down_retry_count > 3)
5043 ha->login_retry_count = ha->port_down_retry_count;
5044 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
5045 ha->login_retry_count = ha->port_down_retry_count;
5046 if (ql2xloginretrycount)
5047 ha->login_retry_count = ql2xloginretrycount;
5048
4fdfefe5 5049 /* Enable ZIO. */
e315cd28 5050 if (!vha->flags.init_done) {
4fdfefe5
AV		 5051 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
5052 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
5053 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
5054 le16_to_cpu(icb->interrupt_delay_timer): 2;
5055 }
5056 icb->firmware_options_2 &= __constant_cpu_to_le32(
5057 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
e315cd28 5058 vha->flags.process_response_queue = 0;
4fdfefe5 5059 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d
AV		 5060 ha->zio_mode = QLA_ZIO_MODE_6;
5061
7c3df132 5062 ql_log(ql_log_info, vha, 0x006f,
4fdfefe5
AV		 5063 "ZIO mode %d enabled; timer delay (%d us).\n",
5064 ha->zio_mode, ha->zio_timer * 100);
5065
5066 icb->firmware_options_2 |= cpu_to_le32(
5067 (uint32_t)ha->zio_mode);
5068 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
e315cd28 5069 vha->flags.process_response_queue = 1;
4fdfefe5
AV		 5070 }
5071
4e08df3f 5072 if (rval) {
7c3df132
SK		 5073 ql_log(ql_log_warn, vha, 0x0070,
5074 "NVRAM configuration failed.\n");
4e08df3f
DM		 5075 }
5076 return (rval);
0107109e
AV		 5077}
5078
413975a0 5079static int
cbc8eb67
AV		 5080qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
5081 uint32_t faddr)
d1c61909 5082{
73208dfd 5083 int rval = QLA_SUCCESS;
d1c61909 5084 int segments, fragment;
d1c61909
AV		 5085 uint32_t *dcode, dlen;
5086 uint32_t risc_addr;
5087 uint32_t risc_size;
5088 uint32_t i;
e315cd28 5089 struct qla_hw_data *ha = vha->hw;
73208dfd 5090 struct req_que *req = ha->req_q_map[0];
eaac30be 5091
7c3df132 5092 ql_dbg(ql_dbg_init, vha, 0x008b,
cfb0919c 5093 "FW: Loading firmware from flash (%x).\n", faddr);
eaac30be 5094
d1c61909
AV		 5095 rval = QLA_SUCCESS;
5096
5097 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 5098 dcode = (uint32_t *)req->ring;
d1c61909
AV		 5099 *srisc_addr = 0;
5100
5101 /* Validate firmware image by checking version. */
e315cd28 5102 qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
d1c61909
AV		 5103 for (i = 0; i < 4; i++)
5104 dcode[i] = be32_to_cpu(dcode[i]);
5105 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
5106 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
5107 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
5108 dcode[3] == 0)) {
7c3df132
SK		 5109 ql_log(ql_log_fatal, vha, 0x008c,
5110 "Unable to verify the integrity of flash firmware "
5111 "image.\n");
5112 ql_log(ql_log_fatal, vha, 0x008d,
5113 "Firmware data: %08x %08x %08x %08x.\n",
5114 dcode[0], dcode[1], dcode[2], dcode[3]);
d1c61909
AV		 5115
5116 return QLA_FUNCTION_FAILED;
5117 }
5118
5119 while (segments && rval == QLA_SUCCESS) {
5120 /* Read segment's load information. */
e315cd28 5121 qla24xx_read_flash_data(vha, dcode, faddr, 4);
d1c61909
AV		 5122
5123 risc_addr = be32_to_cpu(dcode[2]);
5124 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
5125 risc_size = be32_to_cpu(dcode[3]);
5126
5127 fragment = 0;
5128 while (risc_size > 0 && rval == QLA_SUCCESS) {
5129 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
5130 if (dlen > risc_size)
5131 dlen = risc_size;
5132
7c3df132
SK		 5133 ql_dbg(ql_dbg_init, vha, 0x008e,
5134 "Loading risc segment@ risc addr %x "
5135 "number of dwords 0x%x offset 0x%x.\n",
5136 risc_addr, dlen, faddr);
d1c61909 5137
e315cd28 5138 qla24xx_read_flash_data(vha, dcode, faddr, dlen);
d1c61909
AV		 5139 for (i = 0; i < dlen; i++)
5140 dcode[i] = swab32(dcode[i]);
5141
73208dfd 5142 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
d1c61909
AV		 5143 dlen);
5144 if (rval) {
7c3df132
SK		 5145 ql_log(ql_log_fatal, vha, 0x008f,
5146 "Failed to load segment %d of firmware.\n",
5147 fragment);
d1c61909
AV		 5148 break;
5149 }
5150
5151 faddr += dlen;
5152 risc_addr += dlen;
5153 risc_size -= dlen;
5154 fragment++;
5155 }
5156
5157 /* Next segment. */
5158 segments--;
5159 }
5160
f73cb695
CD		 5161 if (!IS_QLA27XX(ha))
5162 return rval;
5163
5164 if (ha->fw_dump_template)
5165 vfree(ha->fw_dump_template);
5166 ha->fw_dump_template = NULL;
5167 ha->fw_dump_template_len = 0;
5168
5169 ql_dbg(ql_dbg_init, vha, 0x0161,
5170 "Loading fwdump template from %x\n", faddr);
5171 qla24xx_read_flash_data(vha, dcode, faddr, 7);
5172 risc_size = be32_to_cpu(dcode[2]);
5173 ql_dbg(ql_dbg_init, vha, 0x0162,
5174 "-> array size %x dwords\n", risc_size);
5175 if (risc_size == 0 || risc_size == ~0)
5176 goto default_template;
5177
5178 dlen = (risc_size - 8) * sizeof(*dcode);
5179 ql_dbg(ql_dbg_init, vha, 0x0163,
5180 "-> template allocating %x bytes...\n", dlen);
5181 ha->fw_dump_template = vmalloc(dlen);
5182 if (!ha->fw_dump_template) {
5183 ql_log(ql_log_warn, vha, 0x0164,
5184 "Failed fwdump template allocate %x bytes.\n", risc_size);
5185 goto default_template;
5186 }
5187
5188 faddr += 7;
5189 risc_size -= 8;
5190 dcode = ha->fw_dump_template;
5191 qla24xx_read_flash_data(vha, dcode, faddr, risc_size);
5192 for (i = 0; i < risc_size; i++)
5193 dcode[i] = le32_to_cpu(dcode[i]);
5194
5195 if (!qla27xx_fwdt_template_valid(dcode)) {
5196 ql_log(ql_log_warn, vha, 0x0165,
5197 "Failed fwdump template validate\n");
5198 goto default_template;
5199 }
5200
5201 dlen = qla27xx_fwdt_template_size(dcode);
5202 ql_dbg(ql_dbg_init, vha, 0x0166,
5203 "-> template size %x bytes\n", dlen);
5204 if (dlen > risc_size * sizeof(*dcode)) {
5205 ql_log(ql_log_warn, vha, 0x0167,
5206 "Failed fwdump template exceeds array by %lx bytes\n",
5207 dlen - risc_size * sizeof(*dcode));
5208 goto default_template;
5209 }
5210 ha->fw_dump_template_len = dlen;
5211 return rval;
5212
5213default_template:
5214 ql_log(ql_log_warn, vha, 0x0168, "Using default fwdump template\n");
5215 if (ha->fw_dump_template)
5216 vfree(ha->fw_dump_template);
5217 ha->fw_dump_template = NULL;
5218 ha->fw_dump_template_len = 0;
5219
5220 dlen = qla27xx_fwdt_template_default_size();
5221 ql_dbg(ql_dbg_init, vha, 0x0169,
5222 "-> template allocating %x bytes...\n", dlen);
5223 ha->fw_dump_template = vmalloc(dlen);
5224 if (!ha->fw_dump_template) {
5225 ql_log(ql_log_warn, vha, 0x016a,
5226 "Failed fwdump template allocate %x bytes.\n", risc_size);
5227 goto failed_template;
5228 }
5229
5230 dcode = ha->fw_dump_template;
5231 risc_size = dlen / sizeof(*dcode);
5232 memcpy(dcode, qla27xx_fwdt_template_default(), dlen);
5233 for (i = 0; i < risc_size; i++)
5234 dcode[i] = be32_to_cpu(dcode[i]);
5235
5236 if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) {
5237 ql_log(ql_log_warn, vha, 0x016b,
5238 "Failed fwdump template validate\n");
5239 goto failed_template;
5240 }
5241
5242 dlen = qla27xx_fwdt_template_size(ha->fw_dump_template);
5243 ql_dbg(ql_dbg_init, vha, 0x016c,
5244 "-> template size %x bytes\n", dlen);
5245 ha->fw_dump_template_len = dlen;
5246 return rval;
5247
5248failed_template:
5249 ql_log(ql_log_warn, vha, 0x016d, "Failed default fwdump template\n");
5250 if (ha->fw_dump_template)
5251 vfree(ha->fw_dump_template);
5252 ha->fw_dump_template = NULL;
5253 ha->fw_dump_template_len = 0;
d1c61909
AV		 5254 return rval;
5255}
5256
e9454a88 5257#define QLA_FW_URL "http://ldriver.qlogic.com/firmware/"
d1c61909 5258
0107109e 5259int
e315cd28 5260qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5433383e
AV		 5261{
5262 int rval;
5263 int i, fragment;
5264 uint16_t *wcode, *fwcode;
5265 uint32_t risc_addr, risc_size, fwclen, wlen, *seg;
5266 struct fw_blob *blob;
e315cd28 5267 struct qla_hw_data *ha = vha->hw;
73208dfd 5268 struct req_que *req = ha->req_q_map[0];
5433383e
AV		 5269
5270 /* Load firmware blob. */
e315cd28 5271 blob = qla2x00_request_firmware(vha);
5433383e 5272 if (!blob) {
7c3df132
SK		 5273 ql_log(ql_log_info, vha, 0x0083,
5274 "Fimware image unavailable.\n");
5275 ql_log(ql_log_info, vha, 0x0084,
5276 "Firmware images can be retrieved from: "QLA_FW_URL ".\n");
5433383e
AV		 5277 return QLA_FUNCTION_FAILED;
5278 }
5279
5280 rval = QLA_SUCCESS;
5281
73208dfd 5282 wcode = (uint16_t *)req->ring;
5433383e
AV		 5283 *srisc_addr = 0;
5284 fwcode = (uint16_t *)blob->fw->data;
5285 fwclen = 0;
5286
5287 /* Validate firmware image by checking version. */
5288 if (blob->fw->size < 8 * sizeof(uint16_t)) {
7c3df132
SK		 5289 ql_log(ql_log_fatal, vha, 0x0085,
5290 "Unable to verify integrity of firmware image (%Zd).\n",
5433383e
AV		 5291 blob->fw->size);
5292 goto fail_fw_integrity;
5293 }
5294 for (i = 0; i < 4; i++)
5295 wcode[i] = be16_to_cpu(fwcode[i + 4]);
5296 if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff &&
5297 wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 &&
5298 wcode[2] == 0 && wcode[3] == 0)) {
7c3df132
SK		 5299 ql_log(ql_log_fatal, vha, 0x0086,
5300 "Unable to verify integrity of firmware image.\n");
5301 ql_log(ql_log_fatal, vha, 0x0087,
5302 "Firmware data: %04x %04x %04x %04x.\n",
5303 wcode[0], wcode[1], wcode[2], wcode[3]);
5433383e
AV		 5304 goto fail_fw_integrity;
5305 }
5306
5307 seg = blob->segs;
5308 while (*seg && rval == QLA_SUCCESS) {
5309 risc_addr = *seg;
5310 *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr;
5311 risc_size = be16_to_cpu(fwcode[3]);
5312
5313 /* Validate firmware image size. */
5314 fwclen += risc_size * sizeof(uint16_t);
5315 if (blob->fw->size < fwclen) {
7c3df132 5316 ql_log(ql_log_fatal, vha, 0x0088,
5433383e 5317 "Unable to verify integrity of firmware image "
7c3df132 5318 "(%Zd).\n", blob->fw->size);
5433383e
AV		 5319 goto fail_fw_integrity;
5320 }
5321
5322 fragment = 0;
5323 while (risc_size > 0 && rval == QLA_SUCCESS) {
5324 wlen = (uint16_t)(ha->fw_transfer_size >> 1);
5325 if (wlen > risc_size)
5326 wlen = risc_size;
7c3df132
SK		 5327 ql_dbg(ql_dbg_init, vha, 0x0089,
5328 "Loading risc segment@ risc addr %x number of "
5329 "words 0x%x.\n", risc_addr, wlen);
5433383e
AV		 5330
5331 for (i = 0; i < wlen; i++)
5332 wcode[i] = swab16(fwcode[i]);
5333
73208dfd 5334 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
5433383e
AV		 5335 wlen);
5336 if (rval) {
7c3df132
SK		 5337 ql_log(ql_log_fatal, vha, 0x008a,
5338 "Failed to load segment %d of firmware.\n",
5339 fragment);
5433383e
AV		 5340 break;
5341 }
5342
5343 fwcode += wlen;
5344 risc_addr += wlen;
5345 risc_size -= wlen;
5346 fragment++;
5347 }
5348
5349 /* Next segment. */
5350 seg++;
5351 }
5352 return rval;
5353
5354fail_fw_integrity:
5355 return QLA_FUNCTION_FAILED;
5356}
5357
eaac30be
AV		 5358static int
5359qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
0107109e
AV		 5360{
5361 int rval;
5362 int segments, fragment;
5363 uint32_t *dcode, dlen;
5364 uint32_t risc_addr;
5365 uint32_t risc_size;
5366 uint32_t i;
5433383e 5367 struct fw_blob *blob;
f73cb695
CD		 5368 const uint32_t *fwcode;
5369 uint32_t fwclen;
e315cd28 5370 struct qla_hw_data *ha = vha->hw;
73208dfd 5371 struct req_que *req = ha->req_q_map[0];
0107109e 5372
5433383e 5373 /* Load firmware blob. */
e315cd28 5374 blob = qla2x00_request_firmware(vha);
5433383e 5375 if (!blob) {
7c3df132
SK		 5376 ql_log(ql_log_warn, vha, 0x0090,
5377 "Fimware image unavailable.\n");
5378 ql_log(ql_log_warn, vha, 0x0091,
5379 "Firmware images can be retrieved from: "
5380 QLA_FW_URL ".\n");
d1c61909 5381
eaac30be 5382 return QLA_FUNCTION_FAILED;
0107109e
AV		 5383 }
5384
cfb0919c
CD		 5385 ql_dbg(ql_dbg_init, vha, 0x0092,
5386 "FW: Loading via request-firmware.\n");
eaac30be 5387
0107109e
AV		 5388 rval = QLA_SUCCESS;
5389
5390 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 5391 dcode = (uint32_t *)req->ring;
0107109e 5392 *srisc_addr = 0;
5433383e 5393 fwcode = (uint32_t *)blob->fw->data;
0107109e
AV		 5394 fwclen = 0;
5395
5396 /* Validate firmware image by checking version. */
5433383e 5397 if (blob->fw->size < 8 * sizeof(uint32_t)) {
7c3df132
SK		 5398 ql_log(ql_log_fatal, vha, 0x0093,
5399 "Unable to verify integrity of firmware image (%Zd).\n",
5433383e 5400 blob->fw->size);
f73cb695 5401 return QLA_FUNCTION_FAILED;
0107109e
AV		 5402 }
5403 for (i = 0; i < 4; i++)
5404 dcode[i] = be32_to_cpu(fwcode[i + 4]);
5405 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
5406 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
5407 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
5408 dcode[3] == 0)) {
7c3df132
SK		 5409 ql_log(ql_log_fatal, vha, 0x0094,
5410 "Unable to verify integrity of firmware image (%Zd).\n",
5411 blob->fw->size);
5412 ql_log(ql_log_fatal, vha, 0x0095,
5413 "Firmware data: %08x %08x %08x %08x.\n",
5414 dcode[0], dcode[1], dcode[2], dcode[3]);
f73cb695 5415 return QLA_FUNCTION_FAILED;
0107109e
AV		 5416 }
5417
5418 while (segments && rval == QLA_SUCCESS) {
5419 risc_addr = be32_to_cpu(fwcode[2]);
5420 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
5421 risc_size = be32_to_cpu(fwcode[3]);
5422
5423 /* Validate firmware image size. */
5424 fwclen += risc_size * sizeof(uint32_t);
5433383e 5425 if (blob->fw->size < fwclen) {
7c3df132 5426 ql_log(ql_log_fatal, vha, 0x0096,
5433383e 5427 "Unable to verify integrity of firmware image "
7c3df132 5428 "(%Zd).\n", blob->fw->size);
f73cb695 5429 return QLA_FUNCTION_FAILED;
0107109e
AV		 5430 }
5431
5432 fragment = 0;
5433 while (risc_size > 0 && rval == QLA_SUCCESS) {
5434 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
5435 if (dlen > risc_size)
5436 dlen = risc_size;
5437
7c3df132
SK		 5438 ql_dbg(ql_dbg_init, vha, 0x0097,
5439 "Loading risc segment@ risc addr %x "
5440 "number of dwords 0x%x.\n", risc_addr, dlen);
0107109e
AV		 5441
5442 for (i = 0; i < dlen; i++)
5443 dcode[i] = swab32(fwcode[i]);
5444
73208dfd 5445 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
590f98e5 5446 dlen);
0107109e 5447 if (rval) {
7c3df132
SK		 5448 ql_log(ql_log_fatal, vha, 0x0098,
5449 "Failed to load segment %d of firmware.\n",
5450 fragment);
0107109e
AV		 5451 break;
5452 }
5453
5454 fwcode += dlen;
5455 risc_addr += dlen;
5456 risc_size -= dlen;
5457 fragment++;
5458 }
5459
5460 /* Next segment. */
5461 segments--;
5462 }
f73cb695
CD		 5463
5464 if (!IS_QLA27XX(ha))
5465 return rval;
5466
5467 if (ha->fw_dump_template)
5468 vfree(ha->fw_dump_template);
5469 ha->fw_dump_template = NULL;
5470 ha->fw_dump_template_len = 0;
5471
5472 ql_dbg(ql_dbg_init, vha, 0x171,
5473 "Loading fwdump template from %lx\n",
5474 (void *)fwcode - (void *)blob->fw->data);
5475 risc_size = be32_to_cpu(fwcode[2]);
5476 ql_dbg(ql_dbg_init, vha, 0x172,
5477 "-> array size %x dwords\n", risc_size);
5478 if (risc_size == 0 || risc_size == ~0)
5479 goto default_template;
5480
5481 dlen = (risc_size - 8) * sizeof(*fwcode);
5482 ql_dbg(ql_dbg_init, vha, 0x0173,
5483 "-> template allocating %x bytes...\n", dlen);
5484 ha->fw_dump_template = vmalloc(dlen);
5485 if (!ha->fw_dump_template) {
5486 ql_log(ql_log_warn, vha, 0x0174,
5487 "Failed fwdump template allocate %x bytes.\n", risc_size);
5488 goto default_template;
5489 }
5490
5491 fwcode += 7;
5492 risc_size -= 8;
5493 dcode = ha->fw_dump_template;
5494 for (i = 0; i < risc_size; i++)
5495 dcode[i] = le32_to_cpu(fwcode[i]);
5496
5497 if (!qla27xx_fwdt_template_valid(dcode)) {
5498 ql_log(ql_log_warn, vha, 0x0175,
5499 "Failed fwdump template validate\n");
5500 goto default_template;
5501 }
5502
5503 dlen = qla27xx_fwdt_template_size(dcode);
5504 ql_dbg(ql_dbg_init, vha, 0x0176,
5505 "-> template size %x bytes\n", dlen);
5506 if (dlen > risc_size * sizeof(*fwcode)) {
5507 ql_log(ql_log_warn, vha, 0x0177,
5508 "Failed fwdump template exceeds array by %lx bytes\n",
5509 dlen - risc_size * sizeof(*fwcode));
5510 goto default_template;
5511 }
5512 ha->fw_dump_template_len = dlen;
0107109e
AV		 5513 return rval;
5514
f73cb695
CD		 5515default_template:
5516 ql_log(ql_log_warn, vha, 0x0178, "Using default fwdump template\n");
5517 if (ha->fw_dump_template)
5518 vfree(ha->fw_dump_template);
5519 ha->fw_dump_template = NULL;
5520 ha->fw_dump_template_len = 0;
5521
5522 dlen = qla27xx_fwdt_template_default_size();
5523 ql_dbg(ql_dbg_init, vha, 0x0179,
5524 "-> template allocating %x bytes...\n", dlen);
5525 ha->fw_dump_template = vmalloc(dlen);
5526 if (!ha->fw_dump_template) {
5527 ql_log(ql_log_warn, vha, 0x017a,
5528 "Failed fwdump template allocate %x bytes.\n", risc_size);
5529 goto failed_template;
5530 }
5531
5532 dcode = ha->fw_dump_template;
5533 risc_size = dlen / sizeof(*fwcode);
5534 fwcode = qla27xx_fwdt_template_default();
5535 for (i = 0; i < risc_size; i++)
5536 dcode[i] = be32_to_cpu(fwcode[i]);
5537
5538 if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) {
5539 ql_log(ql_log_warn, vha, 0x017b,
5540 "Failed fwdump template validate\n");
5541 goto failed_template;
5542 }
5543
5544 dlen = qla27xx_fwdt_template_size(ha->fw_dump_template);
5545 ql_dbg(ql_dbg_init, vha, 0x017c,
5546 "-> template size %x bytes\n", dlen);
5547 ha->fw_dump_template_len = dlen;
5548 return rval;
5549
5550failed_template:
5551 ql_log(ql_log_warn, vha, 0x017d, "Failed default fwdump template\n");
5552 if (ha->fw_dump_template)
5553 vfree(ha->fw_dump_template);
5554 ha->fw_dump_template = NULL;
5555 ha->fw_dump_template_len = 0;
5556 return rval;
0107109e 5557}
18c6c127 5558
eaac30be
AV		 5559int
5560qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5561{
5562 int rval;
5563
e337d907
AV		 5564 if (ql2xfwloadbin == 1)
5565 return qla81xx_load_risc(vha, srisc_addr);
5566
eaac30be
AV		 5567 /*
5568 * FW Load priority:
5569 * 1) Firmware via request-firmware interface (.bin file).
5570 * 2) Firmware residing in flash.
5571 */
5572 rval = qla24xx_load_risc_blob(vha, srisc_addr);
5573 if (rval == QLA_SUCCESS)
5574 return rval;
5575
cbc8eb67
AV		 5576 return qla24xx_load_risc_flash(vha, srisc_addr,
5577 vha->hw->flt_region_fw);
eaac30be
AV		 5578}
5579
5580int
5581qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5582{
5583 int rval;
cbc8eb67 5584 struct qla_hw_data *ha = vha->hw;
eaac30be 5585
e337d907 5586 if (ql2xfwloadbin == 2)
cbc8eb67 5587 goto try_blob_fw;
e337d907 5588
eaac30be
AV		 5589 /*
5590 * FW Load priority:
5591 * 1) Firmware residing in flash.
5592 * 2) Firmware via request-firmware interface (.bin file).
cbc8eb67 5593 * 3) Golden-Firmware residing in flash -- limited operation.
eaac30be 5594 */
cbc8eb67 5595 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
eaac30be
AV		 5596 if (rval == QLA_SUCCESS)
5597 return rval;
5598
cbc8eb67
AV		 5599try_blob_fw:
5600 rval = qla24xx_load_risc_blob(vha, srisc_addr);
5601 if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw)
5602 return rval;
5603
7c3df132
SK		 5604 ql_log(ql_log_info, vha, 0x0099,
5605 "Attempting to fallback to golden firmware.\n");
cbc8eb67
AV		 5606 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
5607 if (rval != QLA_SUCCESS)
5608 return rval;
5609
7c3df132 5610 ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n");
cbc8eb67 5611 ha->flags.running_gold_fw = 1;
cbc8eb67 5612 return rval;
eaac30be
AV		 5613}
5614
18c6c127 5615void
e315cd28 5616qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha)
18c6c127
AV		 5617{
5618 int ret, retries;
e315cd28 5619 struct qla_hw_data *ha = vha->hw;
18c6c127 5620
85880801
AV		 5621 if (ha->flags.pci_channel_io_perm_failure)
5622 return;
e428924c 5623 if (!IS_FWI2_CAPABLE(ha))
18c6c127 5624 return;
75edf81d
AV		 5625 if (!ha->fw_major_version)
5626 return;
18c6c127 5627
e315cd28 5628 ret = qla2x00_stop_firmware(vha);
7c7f1f29 5629 for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&
b469a7cb 5630 ret != QLA_INVALID_COMMAND && retries ; retries--) {
e315cd28
AC		 5631 ha->isp_ops->reset_chip(vha);
5632 if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS)
18c6c127 5633 continue;
e315cd28 5634 if (qla2x00_setup_chip(vha) != QLA_SUCCESS)
18c6c127 5635 continue;
7c3df132
SK		 5636 ql_log(ql_log_info, vha, 0x8015,
5637 "Attempting retry of stop-firmware command.\n");
e315cd28 5638 ret = qla2x00_stop_firmware(vha);
18c6c127
AV		 5639 }
5640}
2c3dfe3f
SJ		 5641
5642int
e315cd28 5643qla24xx_configure_vhba(scsi_qla_host_t *vha)
2c3dfe3f
SJ		 5644{
5645 int rval = QLA_SUCCESS;
0b91d116 5646 int rval2;
2c3dfe3f 5647 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28
AC		 5648 struct qla_hw_data *ha = vha->hw;
5649 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
67c2e93a
AC		 5650 struct req_que *req;
5651 struct rsp_que *rsp;
2c3dfe3f 5652
e315cd28 5653 if (!vha->vp_idx)
2c3dfe3f
SJ		 5654 return -EINVAL;
5655
e315cd28 5656 rval = qla2x00_fw_ready(base_vha);
7163ea81 5657 if (ha->flags.cpu_affinity_enabled)
67c2e93a
AC		 5658 req = ha->req_q_map[0];
5659 else
5660 req = vha->req;
5661 rsp = req->rsp;
5662
2c3dfe3f 5663 if (rval == QLA_SUCCESS) {
e315cd28 5664 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
73208dfd 5665 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
2c3dfe3f
SJ		 5666 }
5667
e315cd28 5668 vha->flags.management_server_logged_in = 0;
2c3dfe3f
SJ		 5669
5670 /* Login to SNS first */
0b91d116
CD		 5671 rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb,
5672 BIT_1);
5673 if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
5674 if (rval2 == QLA_MEMORY_ALLOC_FAILED)
5675 ql_dbg(ql_dbg_init, vha, 0x0120,
5676 "Failed SNS login: loop_id=%x, rval2=%d\n",
5677 NPH_SNS, rval2);
5678 else
5679 ql_dbg(ql_dbg_init, vha, 0x0103,
5680 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x "
5681 "mb[2]=%x mb[6]=%x mb[7]=%x.\n",
5682 NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]);
2c3dfe3f
SJ		 5683 return (QLA_FUNCTION_FAILED);
5684 }
5685
e315cd28
AC		 5686 atomic_set(&vha->loop_down_timer, 0);
5687 atomic_set(&vha->loop_state, LOOP_UP);
5688 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5689 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
5690 rval = qla2x00_loop_resync(base_vha);
2c3dfe3f
SJ		 5691
5692 return rval;
5693}
4d4df193
HK		 5694
5695/* 84XX Support **************************************************************/
5696
5697static LIST_HEAD(qla_cs84xx_list);
5698static DEFINE_MUTEX(qla_cs84xx_mutex);
5699
5700static struct qla_chip_state_84xx *
e315cd28 5701qla84xx_get_chip(struct scsi_qla_host *vha)
4d4df193
HK		 5702{
5703 struct qla_chip_state_84xx *cs84xx;
e315cd28 5704 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5705
5706 mutex_lock(&qla_cs84xx_mutex);
5707
5708 /* Find any shared 84xx chip. */
5709 list_for_each_entry(cs84xx, &qla_cs84xx_list, list) {
5710 if (cs84xx->bus == ha->pdev->bus) {
5711 kref_get(&cs84xx->kref);
5712 goto done;
5713 }
5714 }
5715
5716 cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL);
5717 if (!cs84xx)
5718 goto done;
5719
5720 kref_init(&cs84xx->kref);
5721 spin_lock_init(&cs84xx->access_lock);
5722 mutex_init(&cs84xx->fw_update_mutex);
5723 cs84xx->bus = ha->pdev->bus;
5724
5725 list_add_tail(&cs84xx->list, &qla_cs84xx_list);
5726done:
5727 mutex_unlock(&qla_cs84xx_mutex);
5728 return cs84xx;
5729}
5730
5731static void
5732__qla84xx_chip_release(struct kref *kref)
5733{
5734 struct qla_chip_state_84xx *cs84xx =
5735 container_of(kref, struct qla_chip_state_84xx, kref);
5736
5737 mutex_lock(&qla_cs84xx_mutex);
5738 list_del(&cs84xx->list);
5739 mutex_unlock(&qla_cs84xx_mutex);
5740 kfree(cs84xx);
5741}
5742
5743void
e315cd28 5744qla84xx_put_chip(struct scsi_qla_host *vha)
4d4df193 5745{
e315cd28 5746 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5747 if (ha->cs84xx)
5748 kref_put(&ha->cs84xx->kref, __qla84xx_chip_release);
5749}
5750
5751static int
e315cd28 5752qla84xx_init_chip(scsi_qla_host_t *vha)
4d4df193
HK		 5753{
5754 int rval;
5755 uint16_t status[2];
e315cd28 5756 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5757
5758 mutex_lock(&ha->cs84xx->fw_update_mutex);
5759
e315cd28 5760 rval = qla84xx_verify_chip(vha, status);
4d4df193
HK		 5761
5762 mutex_unlock(&ha->cs84xx->fw_update_mutex);
5763
5764 return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED:
5765 QLA_SUCCESS;
5766}
3a03eb79
AV		 5767
5768/* 81XX Support **************************************************************/
5769
5770int
5771qla81xx_nvram_config(scsi_qla_host_t *vha)
5772{
5773 int rval;
5774 struct init_cb_81xx *icb;
5775 struct nvram_81xx *nv;
5776 uint32_t *dptr;
5777 uint8_t *dptr1, *dptr2;
5778 uint32_t chksum;
5779 uint16_t cnt;
5780 struct qla_hw_data *ha = vha->hw;
5781
5782 rval = QLA_SUCCESS;
5783 icb = (struct init_cb_81xx *)ha->init_cb;
5784 nv = ha->nvram;
5785
5786 /* Determine NVRAM starting address. */
5787 ha->nvram_size = sizeof(struct nvram_81xx);
3a03eb79 5788 ha->vpd_size = FA_NVRAM_VPD_SIZE;
7ec0effd
AD		 5789 if (IS_P3P_TYPE(ha) || IS_QLA8031(ha))
5790 ha->vpd_size = FA_VPD_SIZE_82XX;
3a03eb79
AV		 5791
5792 /* Get VPD data into cache */
5793 ha->vpd = ha->nvram + VPD_OFFSET;
3d79038f
AV		 5794 ha->isp_ops->read_optrom(vha, ha->vpd, ha->flt_region_vpd << 2,
5795 ha->vpd_size);
3a03eb79
AV		 5796
5797 /* Get NVRAM data into cache and calculate checksum. */
3d79038f 5798 ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2,
3a03eb79 5799 ha->nvram_size);
3d79038f 5800 dptr = (uint32_t *)nv;
3a03eb79
AV		 5801 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
5802 chksum += le32_to_cpu(*dptr++);
5803
7c3df132
SK		 5804 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
5805 "Contents of NVRAM:\n");
5806 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
5807 (uint8_t *)nv, ha->nvram_size);
3a03eb79
AV		 5808
5809 /* Bad NVRAM data, set defaults parameters. */
5810 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
5811 || nv->id[3] != ' ' ||
5812 nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
5813 /* Reset NVRAM data. */
7c3df132 5814 ql_log(ql_log_info, vha, 0x0073,
9e336520 5815 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132 5816 "version=0x%x.\n", chksum, nv->id[0],
3a03eb79 5817 le16_to_cpu(nv->nvram_version));
7c3df132
SK		 5818 ql_log(ql_log_info, vha, 0x0074,
5819 "Falling back to functioning (yet invalid -- WWPN) "
5820 "defaults.\n");
3a03eb79
AV		 5821
5822 /*
5823 * Set default initialization control block.
5824 */
5825 memset(nv, 0, ha->nvram_size);
5826 nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
5827 nv->version = __constant_cpu_to_le16(ICB_VERSION);
5828 nv->frame_payload_size = __constant_cpu_to_le16(2048);
5829 nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
5830 nv->exchange_count = __constant_cpu_to_le16(0);
5831 nv->port_name[0] = 0x21;
f73cb695 5832 nv->port_name[1] = 0x00 + ha->port_no + 1;
3a03eb79
AV		 5833 nv->port_name[2] = 0x00;
5834 nv->port_name[3] = 0xe0;
5835 nv->port_name[4] = 0x8b;
5836 nv->port_name[5] = 0x1c;
5837 nv->port_name[6] = 0x55;
5838 nv->port_name[7] = 0x86;
5839 nv->node_name[0] = 0x20;
5840 nv->node_name[1] = 0x00;
5841 nv->node_name[2] = 0x00;
5842 nv->node_name[3] = 0xe0;
5843 nv->node_name[4] = 0x8b;
5844 nv->node_name[5] = 0x1c;
5845 nv->node_name[6] = 0x55;
5846 nv->node_name[7] = 0x86;
5847 nv->login_retry_count = __constant_cpu_to_le16(8);
5848 nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
5849 nv->login_timeout = __constant_cpu_to_le16(0);
5850 nv->firmware_options_1 =
5851 __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
5852 nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
5853 nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
5854 nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
5855 nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
5856 nv->efi_parameters = __constant_cpu_to_le32(0);
5857 nv->reset_delay = 5;
5858 nv->max_luns_per_target = __constant_cpu_to_le16(128);
5859 nv->port_down_retry_count = __constant_cpu_to_le16(30);
6246b8a1 5860 nv->link_down_timeout = __constant_cpu_to_le16(180);
eeebcc92 5861 nv->enode_mac[0] = 0x00;
6246b8a1
GM		 5862 nv->enode_mac[1] = 0xC0;
5863 nv->enode_mac[2] = 0xDD;
3a03eb79
AV		 5864 nv->enode_mac[3] = 0x04;
5865 nv->enode_mac[4] = 0x05;
f73cb695 5866 nv->enode_mac[5] = 0x06 + ha->port_no + 1;
3a03eb79
AV		 5867
5868 rval = 1;
5869 }
5870
9e522cd8
AE		 5871 if (IS_T10_PI_CAPABLE(ha))
5872 nv->frame_payload_size &= ~7;
5873
aa230bc5
AE		 5874 qlt_81xx_config_nvram_stage1(vha, nv);
5875
3a03eb79 5876 /* Reset Initialization control block */
773120e4 5877 memset(icb, 0, ha->init_cb_size);
3a03eb79
AV		 5878
5879 /* Copy 1st segment. */
5880 dptr1 = (uint8_t *)icb;
5881 dptr2 = (uint8_t *)&nv->version;
5882 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
5883 while (cnt--)
5884 *dptr1++ = *dptr2++;
5885
5886 icb->login_retry_count = nv->login_retry_count;
5887
5888 /* Copy 2nd segment. */
5889 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
5890 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
5891 cnt = (uint8_t *)&icb->reserved_5 -
5892 (uint8_t *)&icb->interrupt_delay_timer;
5893 while (cnt--)
5894 *dptr1++ = *dptr2++;
5895
5896 memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac));
5897 /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */
5898 if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) {
69e5f1ea
AV		 5899 icb->enode_mac[0] = 0x00;
5900 icb->enode_mac[1] = 0xC0;
5901 icb->enode_mac[2] = 0xDD;
3a03eb79
AV		 5902 icb->enode_mac[3] = 0x04;
5903 icb->enode_mac[4] = 0x05;
f73cb695 5904 icb->enode_mac[5] = 0x06 + ha->port_no + 1;
3a03eb79
AV		 5905 }
5906
b64b0e8f
AV		 5907 /* Use extended-initialization control block. */
5908 memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb));
5909
3a03eb79
AV		 5910 /*
5911 * Setup driver NVRAM options.
5912 */
5913 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
a9083016 5914 "QLE8XXX");
3a03eb79 5915
aa230bc5
AE		 5916 qlt_81xx_config_nvram_stage2(vha, icb);
5917
3a03eb79
AV		 5918 /* Use alternate WWN? */
5919 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
5920 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
5921 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
5922 }
5923
5924 /* Prepare nodename */
5925 if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
5926 /*
5927 * Firmware will apply the following mask if the nodename was
5928 * not provided.
5929 */
5930 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
5931 icb->node_name[0] &= 0xF0;
5932 }
5933
5934 /* Set host adapter parameters. */
5935 ha->flags.disable_risc_code_load = 0;
5936 ha->flags.enable_lip_reset = 0;
5937 ha->flags.enable_lip_full_login =
5938 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
5939 ha->flags.enable_target_reset =
5940 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
5941 ha->flags.enable_led_scheme = 0;
5942 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
5943
5944 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
5945 (BIT_6 | BIT_5 | BIT_4)) >> 4;
5946
5947 /* save HBA serial number */
5948 ha->serial0 = icb->port_name[5];
5949 ha->serial1 = icb->port_name[6];
5950 ha->serial2 = icb->port_name[7];
5951 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
5952 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
5953
5954 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
5955
5956 ha->retry_count = le16_to_cpu(nv->login_retry_count);
5957
5958 /* Set minimum login_timeout to 4 seconds. */
5959 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
5960 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
5961 if (le16_to_cpu(nv->login_timeout) < 4)
5962 nv->login_timeout = __constant_cpu_to_le16(4);
5963 ha->login_timeout = le16_to_cpu(nv->login_timeout);
5964 icb->login_timeout = nv->login_timeout;
5965
5966 /* Set minimum RATOV to 100 tenths of a second. */
5967 ha->r_a_tov = 100;
5968
5969 ha->loop_reset_delay = nv->reset_delay;
5970
5971 /* Link Down Timeout = 0:
5972 *
7ec0effd 5973 * When Port Down timer expires we will start returning
3a03eb79
AV		 5974 * I/O's to OS with "DID_NO_CONNECT".
5975 *
5976 * Link Down Timeout != 0:
5977 *
5978 * The driver waits for the link to come up after link down
5979 * before returning I/Os to OS with "DID_NO_CONNECT".
5980 */
5981 if (le16_to_cpu(nv->link_down_timeout) == 0) {
5982 ha->loop_down_abort_time =
5983 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
5984 } else {
5985 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
5986 ha->loop_down_abort_time =
5987 (LOOP_DOWN_TIME - ha->link_down_timeout);
5988 }
5989
5990 /* Need enough time to try and get the port back. */
5991 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
5992 if (qlport_down_retry)
5993 ha->port_down_retry_count = qlport_down_retry;
5994
5995 /* Set login_retry_count */
5996 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
5997 if (ha->port_down_retry_count ==
5998 le16_to_cpu(nv->port_down_retry_count) &&
5999 ha->port_down_retry_count > 3)
6000 ha->login_retry_count = ha->port_down_retry_count;
6001 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
6002 ha->login_retry_count = ha->port_down_retry_count;
6003 if (ql2xloginretrycount)
6004 ha->login_retry_count = ql2xloginretrycount;
6005
6246b8a1 6006 /* if not running MSI-X we need handshaking on interrupts */
f73cb695 6007 if (!vha->hw->flags.msix_enabled && (IS_QLA83XX(ha) || IS_QLA27XX(ha)))
6246b8a1
GM		 6008 icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_22);
6009
3a03eb79
AV		 6010 /* Enable ZIO. */
6011 if (!vha->flags.init_done) {
6012 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
6013 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
6014 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
6015 le16_to_cpu(icb->interrupt_delay_timer): 2;
6016 }
6017 icb->firmware_options_2 &= __constant_cpu_to_le32(
6018 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
6019 vha->flags.process_response_queue = 0;
6020 if (ha->zio_mode != QLA_ZIO_DISABLED) {
6021 ha->zio_mode = QLA_ZIO_MODE_6;
6022
7c3df132 6023 ql_log(ql_log_info, vha, 0x0075,
3a03eb79 6024 "ZIO mode %d enabled; timer delay (%d us).\n",
7c3df132
SK		 6025 ha->zio_mode,
6026 ha->zio_timer * 100);
3a03eb79
AV		 6027
6028 icb->firmware_options_2 |= cpu_to_le32(
6029 (uint32_t)ha->zio_mode);
6030 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
6031 vha->flags.process_response_queue = 1;
6032 }
6033
6034 if (rval) {
7c3df132
SK		 6035 ql_log(ql_log_warn, vha, 0x0076,
6036 "NVRAM configuration failed.\n");
3a03eb79
AV		 6037 }
6038 return (rval);
6039}
6040
a9083016
GM		 6041int
6042qla82xx_restart_isp(scsi_qla_host_t *vha)
6043{
6044 int status, rval;
6045 uint32_t wait_time;
6046 struct qla_hw_data *ha = vha->hw;
6047 struct req_que *req = ha->req_q_map[0];
6048 struct rsp_que *rsp = ha->rsp_q_map[0];
6049 struct scsi_qla_host *vp;
feafb7b1 6050 unsigned long flags;
a9083016
GM		 6051
6052 status = qla2x00_init_rings(vha);
6053 if (!status) {
6054 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
6055 ha->flags.chip_reset_done = 1;
6056
6057 status = qla2x00_fw_ready(vha);
6058 if (!status) {
7c3df132
SK		 6059 ql_log(ql_log_info, vha, 0x803c,
6060 "Start configure loop, status =%d.\n", status);
a9083016
GM		 6061
6062 /* Issue a marker after FW becomes ready. */
6063 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
6064
6065 vha->flags.online = 1;
6066 /* Wait at most MAX_TARGET RSCNs for a stable link. */
6067 wait_time = 256;
6068 do {
6069 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
6070 qla2x00_configure_loop(vha);
6071 wait_time--;
6072 } while (!atomic_read(&vha->loop_down_timer) &&
6073 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) &&
6074 wait_time &&
6075 (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)));
6076 }
6077
6078 /* if no cable then assume it's good */
6079 if ((vha->device_flags & DFLG_NO_CABLE))
6080 status = 0;
6081
cfb0919c 6082 ql_log(ql_log_info, vha, 0x8000,
7c3df132 6083 "Configure loop done, status = 0x%x.\n", status);
a9083016
GM		 6084 }
6085
6086 if (!status) {
6087 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
6088
6089 if (!atomic_read(&vha->loop_down_timer)) {
6090 /*
6091 * Issue marker command only when we are going
6092 * to start the I/O .
6093 */
6094 vha->marker_needed = 1;
6095 }
6096
6097 vha->flags.online = 1;
6098
6099 ha->isp_ops->enable_intrs(ha);
6100
6101 ha->isp_abort_cnt = 0;
6102 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
6103
53296788 6104 /* Update the firmware version */
3173167f 6105 status = qla82xx_check_md_needed(vha);
53296788 6106
a9083016
GM		 6107 if (ha->fce) {
6108 ha->flags.fce_enabled = 1;
6109 memset(ha->fce, 0,
6110 fce_calc_size(ha->fce_bufs));
6111 rval = qla2x00_enable_fce_trace(vha,
6112 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
6113 &ha->fce_bufs);
6114 if (rval) {
cfb0919c 6115 ql_log(ql_log_warn, vha, 0x8001,
7c3df132
SK		 6116 "Unable to reinitialize FCE (%d).\n",
6117 rval);
a9083016
GM		 6118 ha->flags.fce_enabled = 0;
6119 }
6120 }
6121
6122 if (ha->eft) {
6123 memset(ha->eft, 0, EFT_SIZE);
6124 rval = qla2x00_enable_eft_trace(vha,
6125 ha->eft_dma, EFT_NUM_BUFFERS);
6126 if (rval) {
cfb0919c 6127 ql_log(ql_log_warn, vha, 0x8010,
7c3df132
SK		 6128 "Unable to reinitialize EFT (%d).\n",
6129 rval);
a9083016
GM		 6130 }
6131 }
a9083016
GM		 6132 }
6133
6134 if (!status) {
cfb0919c 6135 ql_dbg(ql_dbg_taskm, vha, 0x8011,
7c3df132 6136 "qla82xx_restart_isp succeeded.\n");
feafb7b1
AE		 6137
6138 spin_lock_irqsave(&ha->vport_slock, flags);
6139 list_for_each_entry(vp, &ha->vp_list, list) {
6140 if (vp->vp_idx) {
6141 atomic_inc(&vp->vref_count);
6142 spin_unlock_irqrestore(&ha->vport_slock, flags);
6143
a9083016 6144 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 6145
6146 spin_lock_irqsave(&ha->vport_slock, flags);
6147 atomic_dec(&vp->vref_count);
6148 }
a9083016 6149 }
feafb7b1
AE		 6150 spin_unlock_irqrestore(&ha->vport_slock, flags);
6151
a9083016 6152 } else {
cfb0919c 6153 ql_log(ql_log_warn, vha, 0x8016,
7c3df132 6154 "qla82xx_restart_isp **** FAILED ****.\n");
a9083016
GM		 6155 }
6156
6157 return status;
6158}
6159
3a03eb79 6160void
ae97c91e 6161qla81xx_update_fw_options(scsi_qla_host_t *vha)
3a03eb79 6162{
ae97c91e
AV		 6163 struct qla_hw_data *ha = vha->hw;
6164
6165 if (!ql2xetsenable)
6166 return;
6167
6168 /* Enable ETS Burst. */
6169 memset(ha->fw_options, 0, sizeof(ha->fw_options));
6170 ha->fw_options[2] |= BIT_9;
6171 qla2x00_set_fw_options(vha, ha->fw_options);
3a03eb79 6172}
09ff701a
SR		 6173
6174/*
6175 * qla24xx_get_fcp_prio
6176 * Gets the fcp cmd priority value for the logged in port.
6177 * Looks for a match of the port descriptors within
6178 * each of the fcp prio config entries. If a match is found,
6179 * the tag (priority) value is returned.
6180 *
6181 * Input:
21090cbe 6182 * vha = scsi host structure pointer.
09ff701a
SR		 6183 * fcport = port structure pointer.
6184 *
6185 * Return:
6c452a45 6186 * non-zero (if found)
f28a0a96 6187 * -1 (if not found)
09ff701a
SR		 6188 *
6189 * Context:
6190 * Kernel context
6191 */
f28a0a96 6192static int
09ff701a
SR		 6193qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
6194{
6195 int i, entries;
6196 uint8_t pid_match, wwn_match;
f28a0a96 6197 int priority;
09ff701a
SR		 6198 uint32_t pid1, pid2;
6199 uint64_t wwn1, wwn2;
6200 struct qla_fcp_prio_entry *pri_entry;
6201 struct qla_hw_data *ha = vha->hw;
6202
6203 if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled)
f28a0a96 6204 return -1;
09ff701a 6205
f28a0a96 6206 priority = -1;
09ff701a
SR		 6207 entries = ha->fcp_prio_cfg->num_entries;
6208 pri_entry = &ha->fcp_prio_cfg->entry[0];
6209
6210 for (i = 0; i < entries; i++) {
6211 pid_match = wwn_match = 0;
6212
6213 if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) {
6214 pri_entry++;
6215 continue;
6216 }
6217
6218 /* check source pid for a match */
6219 if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) {
6220 pid1 = pri_entry->src_pid & INVALID_PORT_ID;
6221 pid2 = vha->d_id.b24 & INVALID_PORT_ID;
6222 if (pid1 == INVALID_PORT_ID)
6223 pid_match++;
6224 else if (pid1 == pid2)
6225 pid_match++;
6226 }
6227
6228 /* check destination pid for a match */
6229 if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) {
6230 pid1 = pri_entry->dst_pid & INVALID_PORT_ID;
6231 pid2 = fcport->d_id.b24 & INVALID_PORT_ID;
6232 if (pid1 == INVALID_PORT_ID)
6233 pid_match++;
6234 else if (pid1 == pid2)
6235 pid_match++;
6236 }
6237
6238 /* check source WWN for a match */
6239 if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) {
6240 wwn1 = wwn_to_u64(vha->port_name);
6241 wwn2 = wwn_to_u64(pri_entry->src_wwpn);
6242 if (wwn2 == (uint64_t)-1)
6243 wwn_match++;
6244 else if (wwn1 == wwn2)
6245 wwn_match++;
6246 }
6247
6248 /* check destination WWN for a match */
6249 if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) {
6250 wwn1 = wwn_to_u64(fcport->port_name);
6251 wwn2 = wwn_to_u64(pri_entry->dst_wwpn);
6252 if (wwn2 == (uint64_t)-1)
6253 wwn_match++;
6254 else if (wwn1 == wwn2)
6255 wwn_match++;
6256 }
6257
6258 if (pid_match == 2 || wwn_match == 2) {
6259 /* Found a matching entry */
6260 if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID)
6261 priority = pri_entry->tag;
6262 break;
6263 }
6264
6265 pri_entry++;
6266 }
6267
6268 return priority;
6269}
6270
6271/*
6272 * qla24xx_update_fcport_fcp_prio
6273 * Activates fcp priority for the logged in fc port
6274 *
6275 * Input:
21090cbe 6276 * vha = scsi host structure pointer.
09ff701a
SR		 6277 * fcp = port structure pointer.
6278 *
6279 * Return:
6280 * QLA_SUCCESS or QLA_FUNCTION_FAILED
6281 *
6282 * Context:
6283 * Kernel context.
6284 */
6285int
21090cbe 6286qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
09ff701a
SR		 6287{
6288 int ret;
f28a0a96 6289 int priority;
09ff701a
SR		 6290 uint16_t mb[5];
6291
21090cbe
MI		 6292 if (fcport->port_type != FCT_TARGET ||
6293 fcport->loop_id == FC_NO_LOOP_ID)
09ff701a
SR		 6294 return QLA_FUNCTION_FAILED;
6295
21090cbe 6296 priority = qla24xx_get_fcp_prio(vha, fcport);
f28a0a96
AV		 6297 if (priority < 0)
6298 return QLA_FUNCTION_FAILED;
6299
7ec0effd 6300 if (IS_P3P_TYPE(vha->hw)) {
a00f6296
SK		 6301 fcport->fcp_prio = priority & 0xf;
6302 return QLA_SUCCESS;
6303 }
6304
21090cbe 6305 ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb);
cfb0919c
CD		 6306 if (ret == QLA_SUCCESS) {
6307 if (fcport->fcp_prio != priority)
6308 ql_dbg(ql_dbg_user, vha, 0x709e,
6309 "Updated FCP_CMND priority - value=%d loop_id=%d "
6310 "port_id=%02x%02x%02x.\n", priority,
6311 fcport->loop_id, fcport->d_id.b.domain,
6312 fcport->d_id.b.area, fcport->d_id.b.al_pa);
a00f6296 6313 fcport->fcp_prio = priority & 0xf;
cfb0919c 6314 } else
7c3df132 6315 ql_dbg(ql_dbg_user, vha, 0x704f,
cfb0919c
CD		 6316 "Unable to update FCP_CMND priority - ret=0x%x for "
6317 "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id,
6318 fcport->d_id.b.domain, fcport->d_id.b.area,
6319 fcport->d_id.b.al_pa);
09ff701a
SR		 6320 return ret;
6321}
6322
6323/*
6324 * qla24xx_update_all_fcp_prio
6325 * Activates fcp priority for all the logged in ports
6326 *
6327 * Input:
6328 * ha = adapter block pointer.
6329 *
6330 * Return:
6331 * QLA_SUCCESS or QLA_FUNCTION_FAILED
6332 *
6333 * Context:
6334 * Kernel context.
6335 */
6336int
6337qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha)
6338{
6339 int ret;
6340 fc_port_t *fcport;
6341
6342 ret = QLA_FUNCTION_FAILED;
6343 /* We need to set priority for all logged in ports */
6344 list_for_each_entry(fcport, &vha->vp_fcports, list)
6345 ret = qla24xx_update_fcport_fcp_prio(vha, fcport);
6346
6347 return ret;
6348}
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