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Commit | Line | Data |
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1da177e4 | 1 | /* |
fa90c54f | 2 | * QLogic Fibre Channel HBA Driver |
bd21eaf9 | 3 | * Copyright (c) 2003-2014 QLogic Corporation |
1da177e4 | 4 | * |
fa90c54f | 5 | * See LICENSE.qla2xxx for copyright and licensing details. |
1da177e4 LT |
6 | */ |
7 | ||
f83adb61 | 8 | #include "qla_target.h" |
8ae6d9c7 GM |
9 | /** |
10 | * qla24xx_calc_iocbs() - Determine number of Command Type 3 and | |
11 | * Continuation Type 1 IOCBs to allocate. | |
12 | * | |
2db6228d | 13 | * @vha: HA context |
8ae6d9c7 GM |
14 | * @dsds: number of data segment decriptors needed |
15 | * | |
16 | * Returns the number of IOCB entries needed to store @dsds. | |
17 | */ | |
18 | static inline uint16_t | |
19 | qla24xx_calc_iocbs(scsi_qla_host_t *vha, uint16_t dsds) | |
20 | { | |
21 | uint16_t iocbs; | |
22 | ||
23 | iocbs = 1; | |
24 | if (dsds > 1) { | |
25 | iocbs += (dsds - 1) / 5; | |
26 | if ((dsds - 1) % 5) | |
27 | iocbs++; | |
28 | } | |
29 | return iocbs; | |
30 | } | |
31 | ||
1da177e4 LT |
32 | /* |
33 | * qla2x00_debounce_register | |
34 | * Debounce register. | |
35 | * | |
36 | * Input: | |
37 | * port = register address. | |
38 | * | |
39 | * Returns: | |
40 | * register value. | |
41 | */ | |
42 | static __inline__ uint16_t | |
fa2a1ce5 | 43 | qla2x00_debounce_register(volatile uint16_t __iomem *addr) |
1da177e4 LT |
44 | { |
45 | volatile uint16_t first; | |
46 | volatile uint16_t second; | |
47 | ||
48 | do { | |
04474d3a | 49 | first = rd_reg_word(addr); |
1da177e4 LT |
50 | barrier(); |
51 | cpu_relax(); | |
04474d3a | 52 | second = rd_reg_word(addr); |
1da177e4 LT |
53 | } while (first != second); |
54 | ||
55 | return (first); | |
56 | } | |
57 | ||
fa2a1ce5 | 58 | static inline void |
e315cd28 | 59 | qla2x00_poll(struct rsp_que *rsp) |
1da177e4 | 60 | { |
e315cd28 | 61 | struct qla_hw_data *ha = rsp->hw; |
b3a8aa90 | 62 | |
7ec0effd | 63 | if (IS_P3P_TYPE(ha)) |
a9083016 GM |
64 | qla82xx_poll(0, rsp); |
65 | else | |
66 | ha->isp_ops->intr_handler(0, rsp); | |
1da177e4 LT |
67 | } |
68 | ||
2b6c0cee AV |
69 | static inline uint8_t * |
70 | host_to_fcp_swap(uint8_t *fcp, uint32_t bsize) | |
71 | { | |
72 | uint32_t *ifcp = (uint32_t *) fcp; | |
73 | uint32_t *ofcp = (uint32_t *) fcp; | |
74 | uint32_t iter = bsize >> 2; | |
75 | ||
76 | for (; iter ; iter--) | |
77 | *ofcp++ = swab32(*ifcp++); | |
78 | ||
79 | return fcp; | |
80 | } | |
3d71644c | 81 | |
8ae6d9c7 GM |
82 | static inline void |
83 | host_to_adap(uint8_t *src, uint8_t *dst, uint32_t bsize) | |
84 | { | |
85 | uint32_t *isrc = (uint32_t *) src; | |
1f8deefe | 86 | __le32 *odest = (__le32 *) dst; |
8ae6d9c7 GM |
87 | uint32_t iter = bsize >> 2; |
88 | ||
da08ef5c JC |
89 | for ( ; iter--; isrc++) |
90 | *odest++ = cpu_to_le32(*isrc); | |
8ae6d9c7 GM |
91 | } |
92 | ||
bad75002 | 93 | static inline void |
d5ff0eed | 94 | qla2x00_clean_dsd_pool(struct qla_hw_data *ha, struct crc_context *ctx) |
bad75002 | 95 | { |
d5ff0eed | 96 | struct dsd_dma *dsd, *tdsd; |
bad75002 AE |
97 | |
98 | /* clean up allocated prev pool */ | |
d5ff0eed JC |
99 | list_for_each_entry_safe(dsd, tdsd, &ctx->dsd_list, list) { |
100 | dma_pool_free(ha->dl_dma_pool, dsd->dsd_addr, | |
101 | dsd->dsd_list_dma); | |
102 | list_del(&dsd->list); | |
103 | kfree(dsd); | |
bad75002 | 104 | } |
9ba56b95 | 105 | INIT_LIST_HEAD(&ctx->dsd_list); |
bad75002 | 106 | } |
ec426e10 | 107 | |
27258a57 SS |
108 | static inline void |
109 | qla2x00_set_fcport_disc_state(fc_port_t *fcport, int state) | |
110 | { | |
111 | int old_val; | |
112 | uint8_t shiftbits, mask; | |
113 | ||
114 | /* This will have to change when the max no. of states > 16 */ | |
115 | shiftbits = 4; | |
116 | mask = (1 << shiftbits) - 1; | |
117 | ||
118 | fcport->disc_state = state; | |
119 | while (1) { | |
120 | old_val = atomic_read(&fcport->shadow_disc_state); | |
121 | if (old_val == atomic_cmpxchg(&fcport->shadow_disc_state, | |
122 | old_val, (old_val << shiftbits) | state)) { | |
123 | ql_dbg(ql_dbg_disc, fcport->vha, 0x2134, | |
124 | "FCPort %8phC disc_state transition: %s to %s - portid=%06x.\n", | |
125 | fcport->port_name, port_dstate_str[old_val & mask], | |
126 | port_dstate_str[state], fcport->d_id.b24); | |
127 | return; | |
128 | } | |
129 | } | |
130 | } | |
131 | ||
8cb2049c | 132 | static inline int |
e02587d7 | 133 | qla2x00_hba_err_chk_enabled(srb_t *sp) |
8cb2049c | 134 | { |
e02587d7 AE |
135 | /* |
136 | * Uncomment when corresponding SCSI changes are done. | |
137 | * | |
138 | if (!sp->cmd->prot_chk) | |
139 | return 0; | |
140 | * | |
141 | */ | |
9ba56b95 | 142 | switch (scsi_get_prot_op(GET_CMD_SP(sp))) { |
8cb2049c AE |
143 | case SCSI_PROT_READ_STRIP: |
144 | case SCSI_PROT_WRITE_INSERT: | |
145 | if (ql2xenablehba_err_chk >= 1) | |
146 | return 1; | |
147 | break; | |
148 | case SCSI_PROT_READ_PASS: | |
149 | case SCSI_PROT_WRITE_PASS: | |
150 | if (ql2xenablehba_err_chk >= 2) | |
151 | return 1; | |
152 | break; | |
153 | case SCSI_PROT_READ_INSERT: | |
154 | case SCSI_PROT_WRITE_STRIP: | |
155 | return 1; | |
156 | } | |
157 | return 0; | |
158 | } | |
d051a5aa AV |
159 | |
160 | static inline int | |
161 | qla2x00_reset_active(scsi_qla_host_t *vha) | |
162 | { | |
163 | scsi_qla_host_t *base_vha = pci_get_drvdata(vha->hw->pdev); | |
164 | ||
165 | /* Test appropriate base-vha and vha flags. */ | |
166 | return test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) || | |
167 | test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || | |
168 | test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || | |
169 | test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || | |
170 | test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags); | |
171 | } | |
9ba56b95 | 172 | |
22ebde16 QT |
173 | static inline int |
174 | qla2x00_chip_is_down(scsi_qla_host_t *vha) | |
175 | { | |
176 | return (qla2x00_reset_active(vha) || !vha->hw->flags.fw_started); | |
177 | } | |
178 | ||
bdb61b9b BVA |
179 | static void qla2xxx_init_sp(srb_t *sp, scsi_qla_host_t *vha, |
180 | struct qla_qpair *qpair, fc_port_t *fcport) | |
181 | { | |
182 | memset(sp, 0, sizeof(*sp)); | |
183 | sp->fcport = fcport; | |
184 | sp->iocbs = 1; | |
185 | sp->vha = vha; | |
186 | sp->qpair = qpair; | |
187 | sp->cmd_type = TYPE_SRB; | |
188 | INIT_LIST_HEAD(&sp->elem); | |
189 | } | |
190 | ||
d7459527 | 191 | static inline srb_t * |
6a629468 QT |
192 | qla2xxx_get_qpair_sp(scsi_qla_host_t *vha, struct qla_qpair *qpair, |
193 | fc_port_t *fcport, gfp_t flag) | |
d7459527 MH |
194 | { |
195 | srb_t *sp = NULL; | |
196 | uint8_t bail; | |
197 | ||
198 | QLA_QPAIR_MARK_BUSY(qpair, bail); | |
199 | if (unlikely(bail)) | |
200 | return NULL; | |
201 | ||
202 | sp = mempool_alloc(qpair->srb_mempool, flag); | |
bdb61b9b BVA |
203 | if (sp) |
204 | qla2xxx_init_sp(sp, vha, qpair, fcport); | |
205 | else | |
d7459527 MH |
206 | QLA_QPAIR_MARK_NOT_BUSY(qpair); |
207 | return sp; | |
208 | } | |
209 | ||
210 | static inline void | |
211 | qla2xxx_rel_qpair_sp(struct qla_qpair *qpair, srb_t *sp) | |
212 | { | |
ae6ccb0f | 213 | sp->qpair = NULL; |
d7459527 MH |
214 | mempool_free(sp, qpair->srb_mempool); |
215 | QLA_QPAIR_MARK_NOT_BUSY(qpair); | |
216 | } | |
217 | ||
9ba56b95 GM |
218 | static inline srb_t * |
219 | qla2x00_get_sp(scsi_qla_host_t *vha, fc_port_t *fcport, gfp_t flag) | |
220 | { | |
221 | srb_t *sp = NULL; | |
9ba56b95 | 222 | uint8_t bail; |
6a629468 | 223 | struct qla_qpair *qpair; |
9ba56b95 GM |
224 | |
225 | QLA_VHA_MARK_BUSY(vha, bail); | |
226 | if (unlikely(bail)) | |
227 | return NULL; | |
228 | ||
6a629468 QT |
229 | qpair = vha->hw->base_qpair; |
230 | sp = qla2xxx_get_qpair_sp(vha, qpair, fcport, flag); | |
9ba56b95 GM |
231 | if (!sp) |
232 | goto done; | |
233 | ||
726b8548 | 234 | sp->vha = vha; |
9ba56b95 GM |
235 | done: |
236 | if (!sp) | |
237 | QLA_VHA_MARK_NOT_BUSY(vha); | |
238 | return sp; | |
239 | } | |
240 | ||
b00ee7d7 | 241 | static inline void |
25ff6af1 | 242 | qla2x00_rel_sp(srb_t *sp) |
b00ee7d7 | 243 | { |
25ff6af1 | 244 | QLA_VHA_MARK_NOT_BUSY(sp->vha); |
6a629468 | 245 | qla2xxx_rel_qpair_sp(sp->qpair, sp); |
b00ee7d7 CD |
246 | } |
247 | ||
642ef983 CD |
248 | static inline int |
249 | qla2x00_gid_list_size(struct qla_hw_data *ha) | |
250 | { | |
8ae6d9c7 GM |
251 | if (IS_QLAFX00(ha)) |
252 | return sizeof(uint32_t) * 32; | |
253 | else | |
254 | return sizeof(struct gid_list_info) * ha->max_fibre_devices; | |
642ef983 | 255 | } |
3c290d0b | 256 | |
36439832 | 257 | static inline void |
258 | qla2x00_handle_mbx_completion(struct qla_hw_data *ha, int status) | |
259 | { | |
260 | if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) && | |
261 | (status & MBX_INTERRUPT) && ha->flags.mbox_int) { | |
262 | set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); | |
263 | clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags); | |
264 | complete(&ha->mbx_intr_comp); | |
265 | } | |
266 | } | |
e05fe292 CD |
267 | |
268 | static inline void | |
269 | qla2x00_set_retry_delay_timestamp(fc_port_t *fcport, uint16_t retry_delay) | |
270 | { | |
271 | if (retry_delay) | |
272 | fcport->retry_delay_timestamp = jiffies + | |
273 | (retry_delay * HZ / 10); | |
274 | } | |
99e1b683 QT |
275 | |
276 | static inline bool | |
277 | qla_is_exch_offld_enabled(struct scsi_qla_host *vha) | |
278 | { | |
279 | if (qla_ini_mode_enabled(vha) && | |
0645cb83 | 280 | (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT)) |
99e1b683 QT |
281 | return true; |
282 | else if (qla_tgt_mode_enabled(vha) && | |
0645cb83 | 283 | (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT)) |
99e1b683 QT |
284 | return true; |
285 | else if (qla_dual_mode_enabled(vha) && | |
0645cb83 | 286 | ((vha->ql2xiniexchg + vha->ql2xexchoffld) > FW_DEF_EXCHANGES_CNT)) |
99e1b683 QT |
287 | return true; |
288 | else | |
289 | return false; | |
290 | } | |
e326d22a QT |
291 | |
292 | static inline void | |
293 | qla_cpu_update(struct qla_qpair *qpair, uint16_t cpuid) | |
294 | { | |
295 | qpair->cpuid = cpuid; | |
296 | ||
297 | if (!list_empty(&qpair->hints_list)) { | |
298 | struct qla_qpair_hint *h; | |
299 | ||
300 | list_for_each_entry(h, &qpair->hints_list, hint_elem) | |
301 | h->cpuid = qpair->cpuid; | |
302 | } | |
303 | } | |
304 | ||
305 | static inline struct qla_qpair_hint * | |
306 | qla_qpair_to_hint(struct qla_tgt *tgt, struct qla_qpair *qpair) | |
307 | { | |
308 | struct qla_qpair_hint *h; | |
309 | u16 i; | |
310 | ||
311 | for (i = 0; i < tgt->ha->max_qpairs + 1; i++) { | |
312 | h = &tgt->qphints[i]; | |
313 | if (h->qpair == qpair) | |
314 | return h; | |
315 | } | |
316 | ||
317 | return NULL; | |
318 | } | |
8abfa9e2 QT |
319 | |
320 | static inline void | |
321 | qla_83xx_start_iocbs(struct qla_qpair *qpair) | |
322 | { | |
323 | struct req_que *req = qpair->req; | |
324 | ||
325 | req->ring_index++; | |
326 | if (req->ring_index == req->length) { | |
327 | req->ring_index = 0; | |
328 | req->ring_ptr = req->ring; | |
329 | } else | |
330 | req->ring_ptr++; | |
331 | ||
04474d3a | 332 | wrt_reg_dword(req->req_q_in, req->ring_index); |
8abfa9e2 | 333 | } |
84ed362a MH |
334 | |
335 | static inline int | |
336 | qla2xxx_get_fc4_priority(struct scsi_qla_host *vha) | |
337 | { | |
338 | uint32_t data; | |
339 | ||
340 | data = | |
341 | ((uint8_t *)vha->hw->nvram)[NVRAM_DUAL_FCP_NVME_FLAG_OFFSET]; | |
342 | ||
343 | ||
a10c8803 | 344 | return (data >> 6) & BIT_0 ? FC4_PRIORITY_FCP : FC4_PRIORITY_NVME; |
84ed362a | 345 | } |