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77adf3f0 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
1da177e4 | 2 | /* |
fa90c54f | 3 | * QLogic Fibre Channel HBA Driver |
bd21eaf9 | 4 | * Copyright (c) 2003-2014 QLogic Corporation |
1da177e4 LT |
5 | */ |
6 | ||
f83adb61 | 7 | #include "qla_target.h" |
8ae6d9c7 GM |
8 | /** |
9 | * qla24xx_calc_iocbs() - Determine number of Command Type 3 and | |
10 | * Continuation Type 1 IOCBs to allocate. | |
11 | * | |
2db6228d | 12 | * @vha: HA context |
0a19a725 | 13 | * @dsds: number of data segment descriptors needed |
8ae6d9c7 GM |
14 | * |
15 | * Returns the number of IOCB entries needed to store @dsds. | |
16 | */ | |
17 | static inline uint16_t | |
18 | qla24xx_calc_iocbs(scsi_qla_host_t *vha, uint16_t dsds) | |
19 | { | |
20 | uint16_t iocbs; | |
21 | ||
22 | iocbs = 1; | |
23 | if (dsds > 1) { | |
24 | iocbs += (dsds - 1) / 5; | |
25 | if ((dsds - 1) % 5) | |
26 | iocbs++; | |
27 | } | |
28 | return iocbs; | |
29 | } | |
30 | ||
1da177e4 LT |
31 | /* |
32 | * qla2x00_debounce_register | |
33 | * Debounce register. | |
34 | * | |
35 | * Input: | |
36 | * port = register address. | |
37 | * | |
38 | * Returns: | |
39 | * register value. | |
40 | */ | |
41 | static __inline__ uint16_t | |
21038b09 | 42 | qla2x00_debounce_register(volatile __le16 __iomem *addr) |
1da177e4 LT |
43 | { |
44 | volatile uint16_t first; | |
45 | volatile uint16_t second; | |
46 | ||
47 | do { | |
04474d3a | 48 | first = rd_reg_word(addr); |
1da177e4 LT |
49 | barrier(); |
50 | cpu_relax(); | |
04474d3a | 51 | second = rd_reg_word(addr); |
1da177e4 LT |
52 | } while (first != second); |
53 | ||
54 | return (first); | |
55 | } | |
56 | ||
fa2a1ce5 | 57 | static inline void |
e315cd28 | 58 | qla2x00_poll(struct rsp_que *rsp) |
1da177e4 | 59 | { |
e315cd28 | 60 | struct qla_hw_data *ha = rsp->hw; |
b3a8aa90 | 61 | |
7ec0effd | 62 | if (IS_P3P_TYPE(ha)) |
a9083016 GM |
63 | qla82xx_poll(0, rsp); |
64 | else | |
65 | ha->isp_ops->intr_handler(0, rsp); | |
1da177e4 LT |
66 | } |
67 | ||
2b6c0cee AV |
68 | static inline uint8_t * |
69 | host_to_fcp_swap(uint8_t *fcp, uint32_t bsize) | |
70 | { | |
71 | uint32_t *ifcp = (uint32_t *) fcp; | |
72 | uint32_t *ofcp = (uint32_t *) fcp; | |
73 | uint32_t iter = bsize >> 2; | |
74 | ||
75 | for (; iter ; iter--) | |
76 | *ofcp++ = swab32(*ifcp++); | |
77 | ||
78 | return fcp; | |
79 | } | |
3d71644c | 80 | |
8ae6d9c7 GM |
81 | static inline void |
82 | host_to_adap(uint8_t *src, uint8_t *dst, uint32_t bsize) | |
83 | { | |
84 | uint32_t *isrc = (uint32_t *) src; | |
1f8deefe | 85 | __le32 *odest = (__le32 *) dst; |
8ae6d9c7 GM |
86 | uint32_t iter = bsize >> 2; |
87 | ||
da08ef5c JC |
88 | for ( ; iter--; isrc++) |
89 | *odest++ = cpu_to_le32(*isrc); | |
8ae6d9c7 GM |
90 | } |
91 | ||
bad75002 | 92 | static inline void |
d5ff0eed | 93 | qla2x00_clean_dsd_pool(struct qla_hw_data *ha, struct crc_context *ctx) |
bad75002 | 94 | { |
d5ff0eed | 95 | struct dsd_dma *dsd, *tdsd; |
bad75002 AE |
96 | |
97 | /* clean up allocated prev pool */ | |
d5ff0eed JC |
98 | list_for_each_entry_safe(dsd, tdsd, &ctx->dsd_list, list) { |
99 | dma_pool_free(ha->dl_dma_pool, dsd->dsd_addr, | |
100 | dsd->dsd_list_dma); | |
101 | list_del(&dsd->list); | |
102 | kfree(dsd); | |
bad75002 | 103 | } |
9ba56b95 | 104 | INIT_LIST_HEAD(&ctx->dsd_list); |
bad75002 | 105 | } |
ec426e10 | 106 | |
27258a57 SS |
107 | static inline void |
108 | qla2x00_set_fcport_disc_state(fc_port_t *fcport, int state) | |
109 | { | |
110 | int old_val; | |
111 | uint8_t shiftbits, mask; | |
112 | ||
113 | /* This will have to change when the max no. of states > 16 */ | |
114 | shiftbits = 4; | |
115 | mask = (1 << shiftbits) - 1; | |
116 | ||
117 | fcport->disc_state = state; | |
118 | while (1) { | |
119 | old_val = atomic_read(&fcport->shadow_disc_state); | |
120 | if (old_val == atomic_cmpxchg(&fcport->shadow_disc_state, | |
121 | old_val, (old_val << shiftbits) | state)) { | |
122 | ql_dbg(ql_dbg_disc, fcport->vha, 0x2134, | |
123 | "FCPort %8phC disc_state transition: %s to %s - portid=%06x.\n", | |
124 | fcport->port_name, port_dstate_str[old_val & mask], | |
125 | port_dstate_str[state], fcport->d_id.b24); | |
126 | return; | |
127 | } | |
128 | } | |
129 | } | |
130 | ||
8cb2049c | 131 | static inline int |
e02587d7 | 132 | qla2x00_hba_err_chk_enabled(srb_t *sp) |
8cb2049c | 133 | { |
e02587d7 AE |
134 | /* |
135 | * Uncomment when corresponding SCSI changes are done. | |
136 | * | |
137 | if (!sp->cmd->prot_chk) | |
138 | return 0; | |
139 | * | |
140 | */ | |
9ba56b95 | 141 | switch (scsi_get_prot_op(GET_CMD_SP(sp))) { |
8cb2049c AE |
142 | case SCSI_PROT_READ_STRIP: |
143 | case SCSI_PROT_WRITE_INSERT: | |
144 | if (ql2xenablehba_err_chk >= 1) | |
145 | return 1; | |
146 | break; | |
147 | case SCSI_PROT_READ_PASS: | |
148 | case SCSI_PROT_WRITE_PASS: | |
149 | if (ql2xenablehba_err_chk >= 2) | |
150 | return 1; | |
151 | break; | |
152 | case SCSI_PROT_READ_INSERT: | |
153 | case SCSI_PROT_WRITE_STRIP: | |
154 | return 1; | |
155 | } | |
156 | return 0; | |
157 | } | |
d051a5aa AV |
158 | |
159 | static inline int | |
160 | qla2x00_reset_active(scsi_qla_host_t *vha) | |
161 | { | |
162 | scsi_qla_host_t *base_vha = pci_get_drvdata(vha->hw->pdev); | |
163 | ||
164 | /* Test appropriate base-vha and vha flags. */ | |
165 | return test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) || | |
166 | test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || | |
167 | test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || | |
168 | test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || | |
169 | test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags); | |
170 | } | |
9ba56b95 | 171 | |
22ebde16 QT |
172 | static inline int |
173 | qla2x00_chip_is_down(scsi_qla_host_t *vha) | |
174 | { | |
175 | return (qla2x00_reset_active(vha) || !vha->hw->flags.fw_started); | |
176 | } | |
177 | ||
bdb61b9b BVA |
178 | static void qla2xxx_init_sp(srb_t *sp, scsi_qla_host_t *vha, |
179 | struct qla_qpair *qpair, fc_port_t *fcport) | |
180 | { | |
181 | memset(sp, 0, sizeof(*sp)); | |
182 | sp->fcport = fcport; | |
183 | sp->iocbs = 1; | |
184 | sp->vha = vha; | |
185 | sp->qpair = qpair; | |
186 | sp->cmd_type = TYPE_SRB; | |
187 | INIT_LIST_HEAD(&sp->elem); | |
188 | } | |
189 | ||
d7459527 | 190 | static inline srb_t * |
6a629468 QT |
191 | qla2xxx_get_qpair_sp(scsi_qla_host_t *vha, struct qla_qpair *qpair, |
192 | fc_port_t *fcport, gfp_t flag) | |
d7459527 MH |
193 | { |
194 | srb_t *sp = NULL; | |
195 | uint8_t bail; | |
196 | ||
197 | QLA_QPAIR_MARK_BUSY(qpair, bail); | |
198 | if (unlikely(bail)) | |
199 | return NULL; | |
200 | ||
201 | sp = mempool_alloc(qpair->srb_mempool, flag); | |
bdb61b9b BVA |
202 | if (sp) |
203 | qla2xxx_init_sp(sp, vha, qpair, fcport); | |
204 | else | |
d7459527 MH |
205 | QLA_QPAIR_MARK_NOT_BUSY(qpair); |
206 | return sp; | |
207 | } | |
208 | ||
209 | static inline void | |
210 | qla2xxx_rel_qpair_sp(struct qla_qpair *qpair, srb_t *sp) | |
211 | { | |
ae6ccb0f | 212 | sp->qpair = NULL; |
d7459527 MH |
213 | mempool_free(sp, qpair->srb_mempool); |
214 | QLA_QPAIR_MARK_NOT_BUSY(qpair); | |
215 | } | |
216 | ||
9ba56b95 GM |
217 | static inline srb_t * |
218 | qla2x00_get_sp(scsi_qla_host_t *vha, fc_port_t *fcport, gfp_t flag) | |
219 | { | |
220 | srb_t *sp = NULL; | |
9ba56b95 | 221 | uint8_t bail; |
6a629468 | 222 | struct qla_qpair *qpair; |
9ba56b95 GM |
223 | |
224 | QLA_VHA_MARK_BUSY(vha, bail); | |
225 | if (unlikely(bail)) | |
226 | return NULL; | |
227 | ||
6a629468 QT |
228 | qpair = vha->hw->base_qpair; |
229 | sp = qla2xxx_get_qpair_sp(vha, qpair, fcport, flag); | |
9ba56b95 GM |
230 | if (!sp) |
231 | goto done; | |
232 | ||
726b8548 | 233 | sp->vha = vha; |
9ba56b95 GM |
234 | done: |
235 | if (!sp) | |
236 | QLA_VHA_MARK_NOT_BUSY(vha); | |
237 | return sp; | |
238 | } | |
239 | ||
b00ee7d7 | 240 | static inline void |
25ff6af1 | 241 | qla2x00_rel_sp(srb_t *sp) |
b00ee7d7 | 242 | { |
25ff6af1 | 243 | QLA_VHA_MARK_NOT_BUSY(sp->vha); |
6a629468 | 244 | qla2xxx_rel_qpair_sp(sp->qpair, sp); |
b00ee7d7 CD |
245 | } |
246 | ||
642ef983 CD |
247 | static inline int |
248 | qla2x00_gid_list_size(struct qla_hw_data *ha) | |
249 | { | |
8ae6d9c7 GM |
250 | if (IS_QLAFX00(ha)) |
251 | return sizeof(uint32_t) * 32; | |
252 | else | |
253 | return sizeof(struct gid_list_info) * ha->max_fibre_devices; | |
642ef983 | 254 | } |
3c290d0b | 255 | |
36439832 | 256 | static inline void |
257 | qla2x00_handle_mbx_completion(struct qla_hw_data *ha, int status) | |
258 | { | |
259 | if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) && | |
260 | (status & MBX_INTERRUPT) && ha->flags.mbox_int) { | |
261 | set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); | |
262 | clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags); | |
263 | complete(&ha->mbx_intr_comp); | |
264 | } | |
265 | } | |
e05fe292 CD |
266 | |
267 | static inline void | |
268 | qla2x00_set_retry_delay_timestamp(fc_port_t *fcport, uint16_t retry_delay) | |
269 | { | |
270 | if (retry_delay) | |
271 | fcport->retry_delay_timestamp = jiffies + | |
272 | (retry_delay * HZ / 10); | |
273 | } | |
99e1b683 QT |
274 | |
275 | static inline bool | |
276 | qla_is_exch_offld_enabled(struct scsi_qla_host *vha) | |
277 | { | |
278 | if (qla_ini_mode_enabled(vha) && | |
0645cb83 | 279 | (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT)) |
99e1b683 QT |
280 | return true; |
281 | else if (qla_tgt_mode_enabled(vha) && | |
0645cb83 | 282 | (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT)) |
99e1b683 QT |
283 | return true; |
284 | else if (qla_dual_mode_enabled(vha) && | |
0645cb83 | 285 | ((vha->ql2xiniexchg + vha->ql2xexchoffld) > FW_DEF_EXCHANGES_CNT)) |
99e1b683 QT |
286 | return true; |
287 | else | |
288 | return false; | |
289 | } | |
e326d22a QT |
290 | |
291 | static inline void | |
292 | qla_cpu_update(struct qla_qpair *qpair, uint16_t cpuid) | |
293 | { | |
294 | qpair->cpuid = cpuid; | |
295 | ||
296 | if (!list_empty(&qpair->hints_list)) { | |
297 | struct qla_qpair_hint *h; | |
298 | ||
299 | list_for_each_entry(h, &qpair->hints_list, hint_elem) | |
300 | h->cpuid = qpair->cpuid; | |
301 | } | |
302 | } | |
303 | ||
304 | static inline struct qla_qpair_hint * | |
305 | qla_qpair_to_hint(struct qla_tgt *tgt, struct qla_qpair *qpair) | |
306 | { | |
307 | struct qla_qpair_hint *h; | |
308 | u16 i; | |
309 | ||
310 | for (i = 0; i < tgt->ha->max_qpairs + 1; i++) { | |
311 | h = &tgt->qphints[i]; | |
312 | if (h->qpair == qpair) | |
313 | return h; | |
314 | } | |
315 | ||
316 | return NULL; | |
317 | } | |
8abfa9e2 QT |
318 | |
319 | static inline void | |
320 | qla_83xx_start_iocbs(struct qla_qpair *qpair) | |
321 | { | |
322 | struct req_que *req = qpair->req; | |
323 | ||
324 | req->ring_index++; | |
325 | if (req->ring_index == req->length) { | |
326 | req->ring_index = 0; | |
327 | req->ring_ptr = req->ring; | |
328 | } else | |
329 | req->ring_ptr++; | |
330 | ||
04474d3a | 331 | wrt_reg_dword(req->req_q_in, req->ring_index); |
8abfa9e2 | 332 | } |
84ed362a MH |
333 | |
334 | static inline int | |
335 | qla2xxx_get_fc4_priority(struct scsi_qla_host *vha) | |
336 | { | |
337 | uint32_t data; | |
338 | ||
339 | data = | |
340 | ((uint8_t *)vha->hw->nvram)[NVRAM_DUAL_FCP_NVME_FLAG_OFFSET]; | |
341 | ||
342 | ||
a10c8803 | 343 | return (data >> 6) & BIT_0 ? FC4_PRIORITY_FCP : FC4_PRIORITY_NVME; |
84ed362a | 344 | } |