]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/scsi/qla2xxx/qla_mbx.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
qla4xxx: Use kmemdup instead of kmalloc + memcpy
[mirror_ubuntu-artful-kernel.git] / drivers / scsi / qla2xxx / qla_mbx.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
2d70c103 8#include "qla_target.h"
1da177e4
LT		 9
10#include <linux/delay.h>
5a0e3ad6 11#include <linux/gfp.h>
1da177e4 12
1da177e4
LT		 13
14/*
15 * qla2x00_mailbox_command
16 * Issue mailbox command and waits for completion.
17 *
18 * Input:
19 * ha = adapter block pointer.
20 * mcp = driver internal mbx struct pointer.
21 *
22 * Output:
23 * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data.
24 *
25 * Returns:
26 * 0 : QLA_SUCCESS = cmd performed success
27 * 1 : QLA_FUNCTION_FAILED (error encountered)
28 * 6 : QLA_FUNCTION_TIMEOUT (timeout condition encountered)
29 *
30 * Context:
31 * Kernel context.
32 */
33static int
7b867cf7 34qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp)
1da177e4
LT		 35{
36 int rval;
37 unsigned long flags = 0;
f73cb695 38 device_reg_t *reg;
1c7c6357 39 uint8_t abort_active;
2c3dfe3f 40 uint8_t io_lock_on;
cdbb0a4f 41 uint16_t command = 0;
1da177e4
LT		 42 uint16_t *iptr;
43 uint16_t __iomem *optr;
44 uint32_t cnt;
45 uint32_t mboxes;
1da177e4 46 unsigned long wait_time;
7b867cf7
AC		 47 struct qla_hw_data *ha = vha->hw;
48 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
2c3dfe3f 49
5e19ed90 50 ql_dbg(ql_dbg_mbx, vha, 0x1000, "Entered %s.\n", __func__);
7c3df132
SK		 51
52 if (ha->pdev->error_state > pci_channel_io_frozen) {
5e19ed90 53 ql_log(ql_log_warn, vha, 0x1001,
7c3df132
SK		 54 "error_state is greater than pci_channel_io_frozen, "
55 "exiting.\n");
b9b12f73 56 return QLA_FUNCTION_TIMEOUT;
7c3df132 57 }
b9b12f73 58
a9083016 59 if (vha->device_flags & DFLG_DEV_FAILED) {
5e19ed90 60 ql_log(ql_log_warn, vha, 0x1002,
7c3df132 61 "Device in failed state, exiting.\n");
a9083016
GM		 62 return QLA_FUNCTION_TIMEOUT;
63 }
64
2c3dfe3f 65 reg = ha->iobase;
7b867cf7 66 io_lock_on = base_vha->flags.init_done;
1da177e4
LT		 67
68 rval = QLA_SUCCESS;
7b867cf7 69 abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1c7c6357 70
1da177e4 71
85880801 72 if (ha->flags.pci_channel_io_perm_failure) {
5e19ed90 73 ql_log(ql_log_warn, vha, 0x1003,
7c3df132 74 "Perm failure on EEH timeout MBX, exiting.\n");
85880801
AV		 75 return QLA_FUNCTION_TIMEOUT;
76 }
77
7ec0effd 78 if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) {
862cd01e
GM		 79 /* Setting Link-Down error */
80 mcp->mb[0] = MBS_LINK_DOWN_ERROR;
5e19ed90 81 ql_log(ql_log_warn, vha, 0x1004,
7c3df132 82 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
1806fcd5 83 return QLA_FUNCTION_TIMEOUT;
862cd01e
GM		 84 }
85
1da177e4 86 /*
1c7c6357
AV		 87 * Wait for active mailbox commands to finish by waiting at most tov
88 * seconds. This is to serialize actual issuing of mailbox cmds during
89 * non ISP abort time.
1da177e4 90 */
8eca3f39
AV		 91 if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) {
92 /* Timeout occurred. Return error. */
5e19ed90 93 ql_log(ql_log_warn, vha, 0x1005,
d8c0d546
CD		 94 "Cmd access timeout, cmd=0x%x, Exiting.\n",
95 mcp->mb[0]);
8eca3f39 96 return QLA_FUNCTION_TIMEOUT;
1da177e4
LT		 97 }
98
99 ha->flags.mbox_busy = 1;
100 /* Save mailbox command for debug */
101 ha->mcp = mcp;
102
5e19ed90 103 ql_dbg(ql_dbg_mbx, vha, 0x1006,
7c3df132 104 "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]);
1da177e4
LT		 105
106 spin_lock_irqsave(&ha->hardware_lock, flags);
107
108 /* Load mailbox registers. */
7ec0effd 109 if (IS_P3P_TYPE(ha))
a9083016 110 optr = (uint16_t __iomem *)&reg->isp82.mailbox_in[0];
7ec0effd 111 else if (IS_FWI2_CAPABLE(ha) && !(IS_P3P_TYPE(ha)))
1c7c6357
AV		 112 optr = (uint16_t __iomem *)&reg->isp24.mailbox0;
113 else
114 optr = (uint16_t __iomem *)MAILBOX_REG(ha, &reg->isp, 0);
1da177e4
LT		 115
116 iptr = mcp->mb;
117 command = mcp->mb[0];
118 mboxes = mcp->out_mb;
119
0e31a2c8
JC		 120 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1111,
121 "Mailbox registers (OUT):\n");
1da177e4
LT		 122 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
123 if (IS_QLA2200(ha) && cnt == 8)
1c7c6357
AV		 124 optr =
125 (uint16_t __iomem *)MAILBOX_REG(ha, &reg->isp, 8);
0e31a2c8
JC		 126 if (mboxes & BIT_0) {
127 ql_dbg(ql_dbg_mbx, vha, 0x1112,
128 "mbox[%d]<-0x%04x\n", cnt, *iptr);
1da177e4 129 WRT_REG_WORD(optr, *iptr);
0e31a2c8 130 }
1da177e4
LT		 131
132 mboxes >>= 1;
133 optr++;
134 iptr++;
135 }
136
5e19ed90 137 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1117,
7c3df132 138 "I/O Address = %p.\n", optr);
1da177e4
LT		 139
140 /* Issue set host interrupt command to send cmd out. */
141 ha->flags.mbox_int = 0;
142 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
143
144 /* Unlock mbx registers and wait for interrupt */
5e19ed90 145 ql_dbg(ql_dbg_mbx, vha, 0x100f,
7c3df132
SK		 146 "Going to unlock irq & waiting for interrupts. "
147 "jiffies=%lx.\n", jiffies);
1da177e4
LT		 148
149 /* Wait for mbx cmd completion until timeout */
150
124f85e6 151 if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) {
1da177e4
LT		 152 set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
153
7ec0effd 154 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 155 if (RD_REG_DWORD(&reg->isp82.hint) &
156 HINT_MBX_INT_PENDING) {
157 spin_unlock_irqrestore(&ha->hardware_lock,
158 flags);
8937f2f1 159 ha->flags.mbox_busy = 0;
5e19ed90 160 ql_dbg(ql_dbg_mbx, vha, 0x1010,
7c3df132 161 "Pending mailbox timeout, exiting.\n");
cdbb0a4f
SV		 162 rval = QLA_FUNCTION_TIMEOUT;
163 goto premature_exit;
a9083016
GM		 164 }
165 WRT_REG_DWORD(&reg->isp82.hint, HINT_MBX_INT_PENDING);
166 } else if (IS_FWI2_CAPABLE(ha))
1c7c6357
AV		 167 WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
168 else
169 WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT);
1da177e4
LT		 170 spin_unlock_irqrestore(&ha->hardware_lock, flags);
171
754d1243
GM		 172 if (!wait_for_completion_timeout(&ha->mbx_intr_comp,
173 mcp->tov * HZ)) {
174 ql_dbg(ql_dbg_mbx, vha, 0x117a,
175 "cmd=%x Timeout.\n", command);
176 spin_lock_irqsave(&ha->hardware_lock, flags);
177 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
178 spin_unlock_irqrestore(&ha->hardware_lock, flags);
179 }
1da177e4 180 } else {
5e19ed90 181 ql_dbg(ql_dbg_mbx, vha, 0x1011,
7c3df132 182 "Cmd=%x Polling Mode.\n", command);
1da177e4 183
7ec0effd 184 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 185 if (RD_REG_DWORD(&reg->isp82.hint) &
186 HINT_MBX_INT_PENDING) {
187 spin_unlock_irqrestore(&ha->hardware_lock,
188 flags);
8937f2f1 189 ha->flags.mbox_busy = 0;
5e19ed90 190 ql_dbg(ql_dbg_mbx, vha, 0x1012,
7c3df132 191 "Pending mailbox timeout, exiting.\n");
cdbb0a4f
SV		 192 rval = QLA_FUNCTION_TIMEOUT;
193 goto premature_exit;
a9083016
GM		 194 }
195 WRT_REG_DWORD(&reg->isp82.hint, HINT_MBX_INT_PENDING);
196 } else if (IS_FWI2_CAPABLE(ha))
1c7c6357
AV		 197 WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
198 else
199 WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT);
1da177e4 200 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4
LT		 201
202 wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */
203 while (!ha->flags.mbox_int) {
204 if (time_after(jiffies, wait_time))
205 break;
206
207 /* Check for pending interrupts. */
73208dfd 208 qla2x00_poll(ha->rsp_q_map[0]);
1da177e4 209
85880801
AV		 210 if (!ha->flags.mbox_int &&
211 !(IS_QLA2200(ha) &&
212 command == MBC_LOAD_RISC_RAM_EXTENDED))
59989831 213 msleep(10);
1da177e4 214 } /* while */
5e19ed90 215 ql_dbg(ql_dbg_mbx, vha, 0x1013,
7c3df132
SK		 216 "Waited %d sec.\n",
217 (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ));
1da177e4
LT		 218 }
219
1da177e4
LT		 220 /* Check whether we timed out */
221 if (ha->flags.mbox_int) {
222 uint16_t *iptr2;
223
5e19ed90 224 ql_dbg(ql_dbg_mbx, vha, 0x1014,
7c3df132 225 "Cmd=%x completed.\n", command);
1da177e4
LT		 226
227 /* Got interrupt. Clear the flag. */
228 ha->flags.mbox_int = 0;
229 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
230
7ec0effd 231 if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) {
cdbb0a4f
SV		 232 ha->flags.mbox_busy = 0;
233 /* Setting Link-Down error */
234 mcp->mb[0] = MBS_LINK_DOWN_ERROR;
235 ha->mcp = NULL;
236 rval = QLA_FUNCTION_FAILED;
5e19ed90 237 ql_log(ql_log_warn, vha, 0x1015,
7c3df132 238 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
cdbb0a4f
SV		 239 goto premature_exit;
240 }
241
354d6b21 242 if (ha->mailbox_out[0] != MBS_COMMAND_COMPLETE)
1da177e4 243 rval = QLA_FUNCTION_FAILED;
1da177e4
LT		 244
245 /* Load return mailbox registers. */
246 iptr2 = mcp->mb;
247 iptr = (uint16_t *)&ha->mailbox_out[0];
248 mboxes = mcp->in_mb;
0e31a2c8
JC		 249
250 ql_dbg(ql_dbg_mbx, vha, 0x1113,
251 "Mailbox registers (IN):\n");
1da177e4 252 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
0e31a2c8 253 if (mboxes & BIT_0) {
1da177e4 254 *iptr2 = *iptr;
0e31a2c8
JC		 255 ql_dbg(ql_dbg_mbx, vha, 0x1114,
256 "mbox[%d]->0x%04x\n", cnt, *iptr2);
257 }
1da177e4
LT		 258
259 mboxes >>= 1;
260 iptr2++;
261 iptr++;
262 }
263 } else {
264
1c7c6357
AV		 265 uint16_t mb0;
266 uint32_t ictrl;
267
e428924c 268 if (IS_FWI2_CAPABLE(ha)) {
1c7c6357
AV		 269 mb0 = RD_REG_WORD(&reg->isp24.mailbox0);
270 ictrl = RD_REG_DWORD(&reg->isp24.ictrl);
271 } else {
cca5335c 272 mb0 = RD_MAILBOX_REG(ha, &reg->isp, 0);
1c7c6357
AV		 273 ictrl = RD_REG_WORD(&reg->isp.ictrl);
274 }
5e19ed90 275 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1119,
5f28d2d7
SK		 276 "MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx "
277 "mb[0]=0x%x\n", command, ictrl, jiffies, mb0);
5e19ed90 278 ql_dump_regs(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1019);
1da177e4 279
f55bfc88
CD		 280 /*
281 * Attempt to capture a firmware dump for further analysis
b8eb4136
CD		 282 * of the current firmware state. We do not need to do this
283 * if we are intentionally generating a dump.
f55bfc88 284 */
b8eb4136
CD		 285 if (mcp->mb[0] != MBC_GEN_SYSTEM_ERROR)
286 ha->isp_ops->fw_dump(vha, 0);
f55bfc88 287
1da177e4
LT		 288 rval = QLA_FUNCTION_TIMEOUT;
289 }
290
1da177e4
LT		 291 ha->flags.mbox_busy = 0;
292
293 /* Clean up */
294 ha->mcp = NULL;
295
124f85e6 296 if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) {
5e19ed90 297 ql_dbg(ql_dbg_mbx, vha, 0x101a,
7c3df132 298 "Checking for additional resp interrupt.\n");
1da177e4
LT		 299
300 /* polling mode for non isp_abort commands. */
73208dfd 301 qla2x00_poll(ha->rsp_q_map[0]);
1da177e4
LT		 302 }
303
1c7c6357
AV		 304 if (rval == QLA_FUNCTION_TIMEOUT &&
305 mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) {
85880801
AV		 306 if (!io_lock_on || (mcp->flags & IOCTL_CMD) ||
307 ha->flags.eeh_busy) {
1da177e4 308 /* not in dpc. schedule it for dpc to take over. */
5e19ed90 309 ql_dbg(ql_dbg_mbx, vha, 0x101b,
7c3df132 310 "Timeout, schedule isp_abort_needed.\n");
cdbb0a4f
SV		 311
312 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
313 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
314 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
63154916
GM		 315 if (IS_QLA82XX(ha)) {
316 ql_dbg(ql_dbg_mbx, vha, 0x112a,
317 "disabling pause transmit on port "
318 "0 & 1.\n");
319 qla82xx_wr_32(ha,
320 QLA82XX_CRB_NIU + 0x98,
321 CRB_NIU_XG_PAUSE_CTL_P0|
322 CRB_NIU_XG_PAUSE_CTL_P1);
323 }
7c3df132 324 ql_log(ql_log_info, base_vha, 0x101c,
24d9ee85 325 "Mailbox cmd timeout occurred, cmd=0x%x, "
d8c0d546
CD		 326 "mb[0]=0x%x, eeh_busy=0x%x. Scheduling ISP "
327 "abort.\n", command, mcp->mb[0],
328 ha->flags.eeh_busy);
cdbb0a4f
SV		 329 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
330 qla2xxx_wake_dpc(vha);
331 }
1da177e4 332 } else if (!abort_active) {
1da177e4 333 /* call abort directly since we are in the DPC thread */
5e19ed90 334 ql_dbg(ql_dbg_mbx, vha, 0x101d,
7c3df132 335 "Timeout, calling abort_isp.\n");
cdbb0a4f
SV		 336
337 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
338 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
339 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
63154916
GM		 340 if (IS_QLA82XX(ha)) {
341 ql_dbg(ql_dbg_mbx, vha, 0x112b,
342 "disabling pause transmit on port "
343 "0 & 1.\n");
344 qla82xx_wr_32(ha,
345 QLA82XX_CRB_NIU + 0x98,
346 CRB_NIU_XG_PAUSE_CTL_P0|
347 CRB_NIU_XG_PAUSE_CTL_P1);
348 }
7c3df132 349 ql_log(ql_log_info, base_vha, 0x101e,
24d9ee85 350 "Mailbox cmd timeout occurred, cmd=0x%x, "
d8c0d546
CD		 351 "mb[0]=0x%x. Scheduling ISP abort ",
352 command, mcp->mb[0]);
cdbb0a4f
SV		 353 set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
354 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
d3360960
GM		 355 /* Allow next mbx cmd to come in. */
356 complete(&ha->mbx_cmd_comp);
cdbb0a4f
SV		 357 if (ha->isp_ops->abort_isp(vha)) {
358 /* Failed. retry later. */
359 set_bit(ISP_ABORT_NEEDED,
360 &vha->dpc_flags);
361 }
362 clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
5e19ed90 363 ql_dbg(ql_dbg_mbx, vha, 0x101f,
7c3df132 364 "Finished abort_isp.\n");
d3360960 365 goto mbx_done;
1da177e4 366 }
1da177e4
LT		 367 }
368 }
369
cdbb0a4f 370premature_exit:
1da177e4 371 /* Allow next mbx cmd to come in. */
8eca3f39 372 complete(&ha->mbx_cmd_comp);
1da177e4 373
d3360960 374mbx_done:
1da177e4 375 if (rval) {
09543c09 376 ql_log(ql_log_warn, base_vha, 0x1020,
6246b8a1
GM		 377 "**** Failed mbx[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x, cmd=%x ****.\n",
378 mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3], command);
1da177e4 379 } else {
7c3df132 380 ql_dbg(ql_dbg_mbx, base_vha, 0x1021, "Done %s.\n", __func__);
1da177e4
LT		 381 }
382
1da177e4
LT		 383 return rval;
384}
385
1da177e4 386int
7b867cf7 387qla2x00_load_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t risc_addr,
590f98e5 388 uint32_t risc_code_size)
1da177e4
LT		 389{
390 int rval;
7b867cf7 391 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 392 mbx_cmd_t mc;
393 mbx_cmd_t *mcp = &mc;
1da177e4 394
5f28d2d7
SK		 395 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1022,
396 "Entered %s.\n", __func__);
1da177e4 397
e428924c 398 if (MSW(risc_addr) || IS_FWI2_CAPABLE(ha)) {
590f98e5
AV		 399 mcp->mb[0] = MBC_LOAD_RISC_RAM_EXTENDED;
400 mcp->mb[8] = MSW(risc_addr);
401 mcp->out_mb = MBX_8|MBX_0;
1da177e4 402 } else {
590f98e5
AV		 403 mcp->mb[0] = MBC_LOAD_RISC_RAM;
404 mcp->out_mb = MBX_0;
1da177e4 405 }
1da177e4
LT		 406 mcp->mb[1] = LSW(risc_addr);
407 mcp->mb[2] = MSW(req_dma);
408 mcp->mb[3] = LSW(req_dma);
1da177e4
LT		 409 mcp->mb[6] = MSW(MSD(req_dma));
410 mcp->mb[7] = LSW(MSD(req_dma));
590f98e5 411 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
e428924c 412 if (IS_FWI2_CAPABLE(ha)) {
1c7c6357
AV		 413 mcp->mb[4] = MSW(risc_code_size);
414 mcp->mb[5] = LSW(risc_code_size);
415 mcp->out_mb |= MBX_5|MBX_4;
416 } else {
417 mcp->mb[4] = LSW(risc_code_size);
418 mcp->out_mb |= MBX_4;
419 }
420
1da177e4 421 mcp->in_mb = MBX_0;
b93480e3 422 mcp->tov = MBX_TOV_SECONDS;
1da177e4 423 mcp->flags = 0;
7b867cf7 424 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4 425
1da177e4 426 if (rval != QLA_SUCCESS) {
7c3df132
SK		 427 ql_dbg(ql_dbg_mbx, vha, 0x1023,
428 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
1da177e4 429 } else {
5f28d2d7
SK		 430 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1024,
431 "Done %s.\n", __func__);
1da177e4
LT		 432 }
433
434 return rval;
435}
436
cad454b1 437#define EXTENDED_BB_CREDITS BIT_0
1da177e4
LT		 438/*
439 * qla2x00_execute_fw
1c7c6357 440 * Start adapter firmware.
1da177e4
LT		 441 *
442 * Input:
1c7c6357
AV		 443 * ha = adapter block pointer.
444 * TARGET_QUEUE_LOCK must be released.
445 * ADAPTER_STATE_LOCK must be released.
1da177e4
LT		 446 *
447 * Returns:
1c7c6357 448 * qla2x00 local function return status code.
1da177e4
LT		 449 *
450 * Context:
1c7c6357 451 * Kernel context.
1da177e4
LT		 452 */
453int
7b867cf7 454qla2x00_execute_fw(scsi_qla_host_t *vha, uint32_t risc_addr)
1da177e4
LT		 455{
456 int rval;
7b867cf7 457 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 458 mbx_cmd_t mc;
459 mbx_cmd_t *mcp = &mc;
460
5f28d2d7
SK		 461 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1025,
462 "Entered %s.\n", __func__);
1da177e4
LT		 463
464 mcp->mb[0] = MBC_EXECUTE_FIRMWARE;
1c7c6357
AV		 465 mcp->out_mb = MBX_0;
466 mcp->in_mb = MBX_0;
e428924c 467 if (IS_FWI2_CAPABLE(ha)) {
1c7c6357
AV		 468 mcp->mb[1] = MSW(risc_addr);
469 mcp->mb[2] = LSW(risc_addr);
470 mcp->mb[3] = 0;
f73cb695
CD		 471 if (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) ||
472 IS_QLA27XX(ha)) {
cad454b1
SV		 473 struct nvram_81xx *nv = ha->nvram;
474 mcp->mb[4] = (nv->enhanced_features &
475 EXTENDED_BB_CREDITS);
476 } else
477 mcp->mb[4] = 0;
8b3253d1 478 mcp->out_mb |= MBX_4|MBX_3|MBX_2|MBX_1;
1c7c6357
AV		 479 mcp->in_mb |= MBX_1;
480 } else {
481 mcp->mb[1] = LSW(risc_addr);
482 mcp->out_mb |= MBX_1;
483 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
484 mcp->mb[2] = 0;
485 mcp->out_mb |= MBX_2;
486 }
1da177e4
LT		 487 }
488
b93480e3 489 mcp->tov = MBX_TOV_SECONDS;
1da177e4 490 mcp->flags = 0;
7b867cf7 491 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4 492
1c7c6357 493 if (rval != QLA_SUCCESS) {
7c3df132
SK		 494 ql_dbg(ql_dbg_mbx, vha, 0x1026,
495 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
1c7c6357 496 } else {
e428924c 497 if (IS_FWI2_CAPABLE(ha)) {
5f28d2d7 498 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1027,
7c3df132 499 "Done exchanges=%x.\n", mcp->mb[1]);
1c7c6357 500 } else {
5f28d2d7
SK		 501 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1028,
502 "Done %s.\n", __func__);
1c7c6357
AV		 503 }
504 }
1da177e4
LT		 505
506 return rval;
507}
508
509/*
510 * qla2x00_get_fw_version
511 * Get firmware version.
512 *
513 * Input:
514 * ha: adapter state pointer.
515 * major: pointer for major number.
516 * minor: pointer for minor number.
517 * subminor: pointer for subminor number.
518 *
519 * Returns:
520 * qla2x00 local function return status code.
521 *
522 * Context:
523 * Kernel context.
524 */
ca9e9c3e 525int
6246b8a1 526qla2x00_get_fw_version(scsi_qla_host_t *vha)
1da177e4
LT		 527{
528 int rval;
529 mbx_cmd_t mc;
530 mbx_cmd_t *mcp = &mc;
6246b8a1 531 struct qla_hw_data *ha = vha->hw;
1da177e4 532
5f28d2d7
SK		 533 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1029,
534 "Entered %s.\n", __func__);
1da177e4
LT		 535
536 mcp->mb[0] = MBC_GET_FIRMWARE_VERSION;
537 mcp->out_mb = MBX_0;
538 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
7ec0effd 539 if (IS_QLA81XX(vha->hw) || IS_QLA8031(ha) || IS_QLA8044(ha))
55a96158 540 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8;
fb0effee 541 if (IS_FWI2_CAPABLE(ha))
6246b8a1 542 mcp->in_mb |= MBX_17|MBX_16|MBX_15;
f73cb695
CD		 543 if (IS_QLA27XX(ha))
544 mcp->in_mb |= MBX_21|MBX_20|MBX_19|MBX_18;
1da177e4 545 mcp->flags = 0;
b93480e3 546 mcp->tov = MBX_TOV_SECONDS;
7b867cf7 547 rval = qla2x00_mailbox_command(vha, mcp);
ca9e9c3e
AV		 548 if (rval != QLA_SUCCESS)
549 goto failed;
1da177e4
LT		 550
551 /* Return mailbox data. */
6246b8a1
GM		 552 ha->fw_major_version = mcp->mb[1];
553 ha->fw_minor_version = mcp->mb[2];
554 ha->fw_subminor_version = mcp->mb[3];
555 ha->fw_attributes = mcp->mb[6];
7b867cf7 556 if (IS_QLA2100(vha->hw) || IS_QLA2200(vha->hw))
6246b8a1 557 ha->fw_memory_size = 0x1FFFF; /* Defaults to 128KB. */
1da177e4 558 else
6246b8a1 559 ha->fw_memory_size = (mcp->mb[5] << 16) | mcp->mb[4];
7ec0effd 560 if (IS_QLA81XX(vha->hw) || IS_QLA8031(vha->hw) || IS_QLA8044(ha)) {
6246b8a1
GM		 561 ha->mpi_version[0] = mcp->mb[10] & 0xff;
562 ha->mpi_version[1] = mcp->mb[11] >> 8;
563 ha->mpi_version[2] = mcp->mb[11] & 0xff;
564 ha->mpi_capabilities = (mcp->mb[12] << 16) | mcp->mb[13];
565 ha->phy_version[0] = mcp->mb[8] & 0xff;
566 ha->phy_version[1] = mcp->mb[9] >> 8;
567 ha->phy_version[2] = mcp->mb[9] & 0xff;
568 }
81178772
SK		 569 if (IS_FWI2_CAPABLE(ha)) {
570 ha->fw_attributes_h = mcp->mb[15];
571 ha->fw_attributes_ext[0] = mcp->mb[16];
572 ha->fw_attributes_ext[1] = mcp->mb[17];
573 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1139,
574 "%s: FW_attributes Upper: 0x%x, Lower: 0x%x.\n",
575 __func__, mcp->mb[15], mcp->mb[6]);
576 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x112f,
577 "%s: Ext_FwAttributes Upper: 0x%x, Lower: 0x%x.\n",
578 __func__, mcp->mb[17], mcp->mb[16]);
3a03eb79 579 }
f73cb695
CD		 580 if (IS_QLA27XX(ha)) {
581 ha->fw_shared_ram_start = (mcp->mb[19] << 16) | mcp->mb[18];
582 ha->fw_shared_ram_end = (mcp->mb[21] << 16) | mcp->mb[20];
583 }
6246b8a1 584
ca9e9c3e 585failed:
1da177e4
LT		 586 if (rval != QLA_SUCCESS) {
587 /*EMPTY*/
7c3df132 588 ql_dbg(ql_dbg_mbx, vha, 0x102a, "Failed=%x.\n", rval);
1da177e4
LT		 589 } else {
590 /*EMPTY*/
5f28d2d7
SK		 591 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102b,
592 "Done %s.\n", __func__);
1da177e4 593 }
ca9e9c3e 594 return rval;
1da177e4
LT		 595}
596
597/*
598 * qla2x00_get_fw_options
599 * Set firmware options.
600 *
601 * Input:
602 * ha = adapter block pointer.
603 * fwopt = pointer for firmware options.
604 *
605 * Returns:
606 * qla2x00 local function return status code.
607 *
608 * Context:
609 * Kernel context.
610 */
611int
7b867cf7 612qla2x00_get_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
1da177e4
LT		 613{
614 int rval;
615 mbx_cmd_t mc;
616 mbx_cmd_t *mcp = &mc;
617
5f28d2d7
SK		 618 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102c,
619 "Entered %s.\n", __func__);
1da177e4
LT		 620
621 mcp->mb[0] = MBC_GET_FIRMWARE_OPTION;
622 mcp->out_mb = MBX_0;
623 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
b93480e3 624 mcp->tov = MBX_TOV_SECONDS;
1da177e4 625 mcp->flags = 0;
7b867cf7 626 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 627
628 if (rval != QLA_SUCCESS) {
629 /*EMPTY*/
7c3df132 630 ql_dbg(ql_dbg_mbx, vha, 0x102d, "Failed=%x.\n", rval);
1da177e4 631 } else {
1c7c6357 632 fwopts[0] = mcp->mb[0];
1da177e4
LT		 633 fwopts[1] = mcp->mb[1];
634 fwopts[2] = mcp->mb[2];
635 fwopts[3] = mcp->mb[3];
636
5f28d2d7
SK		 637 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102e,
638 "Done %s.\n", __func__);
1da177e4
LT		 639 }
640
641 return rval;
642}
643
644
645/*
646 * qla2x00_set_fw_options
647 * Set firmware options.
648 *
649 * Input:
650 * ha = adapter block pointer.
651 * fwopt = pointer for firmware options.
652 *
653 * Returns:
654 * qla2x00 local function return status code.
655 *
656 * Context:
657 * Kernel context.
658 */
659int
7b867cf7 660qla2x00_set_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
1da177e4
LT		 661{
662 int rval;
663 mbx_cmd_t mc;
664 mbx_cmd_t *mcp = &mc;
665
5f28d2d7
SK		 666 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102f,
667 "Entered %s.\n", __func__);
1da177e4
LT		 668
669 mcp->mb[0] = MBC_SET_FIRMWARE_OPTION;
670 mcp->mb[1] = fwopts[1];
671 mcp->mb[2] = fwopts[2];
672 mcp->mb[3] = fwopts[3];
1c7c6357 673 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1da177e4 674 mcp->in_mb = MBX_0;
7b867cf7 675 if (IS_FWI2_CAPABLE(vha->hw)) {
1c7c6357
AV		 676 mcp->in_mb |= MBX_1;
677 } else {
678 mcp->mb[10] = fwopts[10];
679 mcp->mb[11] = fwopts[11];
680 mcp->mb[12] = 0; /* Undocumented, but used */
681 mcp->out_mb |= MBX_12|MBX_11|MBX_10;
682 }
b93480e3 683 mcp->tov = MBX_TOV_SECONDS;
1da177e4 684 mcp->flags = 0;
7b867cf7 685 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4 686
1c7c6357
AV		 687 fwopts[0] = mcp->mb[0];
688
1da177e4
LT		 689 if (rval != QLA_SUCCESS) {
690 /*EMPTY*/
7c3df132
SK		 691 ql_dbg(ql_dbg_mbx, vha, 0x1030,
692 "Failed=%x (%x/%x).\n", rval, mcp->mb[0], mcp->mb[1]);
1da177e4
LT		 693 } else {
694 /*EMPTY*/
5f28d2d7
SK		 695 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1031,
696 "Done %s.\n", __func__);
1da177e4
LT		 697 }
698
699 return rval;
700}
701
702/*
703 * qla2x00_mbx_reg_test
704 * Mailbox register wrap test.
705 *
706 * Input:
707 * ha = adapter block pointer.
708 * TARGET_QUEUE_LOCK must be released.
709 * ADAPTER_STATE_LOCK must be released.
710 *
711 * Returns:
712 * qla2x00 local function return status code.
713 *
714 * Context:
715 * Kernel context.
716 */
717int
7b867cf7 718qla2x00_mbx_reg_test(scsi_qla_host_t *vha)
1da177e4
LT		 719{
720 int rval;
721 mbx_cmd_t mc;
722 mbx_cmd_t *mcp = &mc;
723
5f28d2d7
SK		 724 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1032,
725 "Entered %s.\n", __func__);
1da177e4
LT		 726
727 mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST;
728 mcp->mb[1] = 0xAAAA;
729 mcp->mb[2] = 0x5555;
730 mcp->mb[3] = 0xAA55;
731 mcp->mb[4] = 0x55AA;
732 mcp->mb[5] = 0xA5A5;
733 mcp->mb[6] = 0x5A5A;
734 mcp->mb[7] = 0x2525;
735 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
736 mcp->in_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
b93480e3 737 mcp->tov = MBX_TOV_SECONDS;
1da177e4 738 mcp->flags = 0;
7b867cf7 739 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 740
741 if (rval == QLA_SUCCESS) {
742 if (mcp->mb[1] != 0xAAAA || mcp->mb[2] != 0x5555 ||
743 mcp->mb[3] != 0xAA55 || mcp->mb[4] != 0x55AA)
744 rval = QLA_FUNCTION_FAILED;
745 if (mcp->mb[5] != 0xA5A5 || mcp->mb[6] != 0x5A5A ||
746 mcp->mb[7] != 0x2525)
747 rval = QLA_FUNCTION_FAILED;
748 }
749
750 if (rval != QLA_SUCCESS) {
751 /*EMPTY*/
7c3df132 752 ql_dbg(ql_dbg_mbx, vha, 0x1033, "Failed=%x.\n", rval);
1da177e4
LT		 753 } else {
754 /*EMPTY*/
5f28d2d7
SK		 755 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1034,
756 "Done %s.\n", __func__);
1da177e4
LT		 757 }
758
759 return rval;
760}
761
762/*
763 * qla2x00_verify_checksum
764 * Verify firmware checksum.
765 *
766 * Input:
767 * ha = adapter block pointer.
768 * TARGET_QUEUE_LOCK must be released.
769 * ADAPTER_STATE_LOCK must be released.
770 *
771 * Returns:
772 * qla2x00 local function return status code.
773 *
774 * Context:
775 * Kernel context.
776 */
777int
7b867cf7 778qla2x00_verify_checksum(scsi_qla_host_t *vha, uint32_t risc_addr)
1da177e4
LT		 779{
780 int rval;
781 mbx_cmd_t mc;
782 mbx_cmd_t *mcp = &mc;
783
5f28d2d7
SK		 784 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1035,
785 "Entered %s.\n", __func__);
1da177e4
LT		 786
787 mcp->mb[0] = MBC_VERIFY_CHECKSUM;
1c7c6357
AV		 788 mcp->out_mb = MBX_0;
789 mcp->in_mb = MBX_0;
7b867cf7 790 if (IS_FWI2_CAPABLE(vha->hw)) {
1c7c6357
AV		 791 mcp->mb[1] = MSW(risc_addr);
792 mcp->mb[2] = LSW(risc_addr);
793 mcp->out_mb |= MBX_2|MBX_1;
794 mcp->in_mb |= MBX_2|MBX_1;
795 } else {
796 mcp->mb[1] = LSW(risc_addr);
797 mcp->out_mb |= MBX_1;
798 mcp->in_mb |= MBX_1;
799 }
800
b93480e3 801 mcp->tov = MBX_TOV_SECONDS;
1da177e4 802 mcp->flags = 0;
7b867cf7 803 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 804
805 if (rval != QLA_SUCCESS) {
7c3df132
SK		 806 ql_dbg(ql_dbg_mbx, vha, 0x1036,
807 "Failed=%x chm sum=%x.\n", rval, IS_FWI2_CAPABLE(vha->hw) ?
808 (mcp->mb[2] << 16) | mcp->mb[1] : mcp->mb[1]);
1da177e4 809 } else {
5f28d2d7
SK		 810 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1037,
811 "Done %s.\n", __func__);
1da177e4
LT		 812 }
813
814 return rval;
815}
816
817/*
818 * qla2x00_issue_iocb
819 * Issue IOCB using mailbox command
820 *
821 * Input:
822 * ha = adapter state pointer.
823 * buffer = buffer pointer.
824 * phys_addr = physical address of buffer.
825 * size = size of buffer.
826 * TARGET_QUEUE_LOCK must be released.
827 * ADAPTER_STATE_LOCK must be released.
828 *
829 * Returns:
830 * qla2x00 local function return status code.
831 *
832 * Context:
833 * Kernel context.
834 */
6e98016c 835int
7b867cf7 836qla2x00_issue_iocb_timeout(scsi_qla_host_t *vha, void *buffer,
4d4df193 837 dma_addr_t phys_addr, size_t size, uint32_t tov)
1da177e4
LT		 838{
839 int rval;
840 mbx_cmd_t mc;
841 mbx_cmd_t *mcp = &mc;
842
5f28d2d7
SK		 843 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1038,
844 "Entered %s.\n", __func__);
7c3df132 845
1da177e4
LT		 846 mcp->mb[0] = MBC_IOCB_COMMAND_A64;
847 mcp->mb[1] = 0;
848 mcp->mb[2] = MSW(phys_addr);
849 mcp->mb[3] = LSW(phys_addr);
850 mcp->mb[6] = MSW(MSD(phys_addr));
851 mcp->mb[7] = LSW(MSD(phys_addr));
852 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
853 mcp->in_mb = MBX_2|MBX_0;
4d4df193 854 mcp->tov = tov;
1da177e4 855 mcp->flags = 0;
7b867cf7 856 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 857
858 if (rval != QLA_SUCCESS) {
859 /*EMPTY*/
7c3df132 860 ql_dbg(ql_dbg_mbx, vha, 0x1039, "Failed=%x.\n", rval);
1da177e4 861 } else {
8c958a99
AV		 862 sts_entry_t *sts_entry = (sts_entry_t *) buffer;
863
864 /* Mask reserved bits. */
865 sts_entry->entry_status &=
7b867cf7 866 IS_FWI2_CAPABLE(vha->hw) ? RF_MASK_24XX : RF_MASK;
5f28d2d7
SK		 867 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103a,
868 "Done %s.\n", __func__);
1da177e4
LT		 869 }
870
871 return rval;
872}
873
4d4df193 874int
7b867cf7 875qla2x00_issue_iocb(scsi_qla_host_t *vha, void *buffer, dma_addr_t phys_addr,
4d4df193
HK		 876 size_t size)
877{
7b867cf7 878 return qla2x00_issue_iocb_timeout(vha, buffer, phys_addr, size,
4d4df193
HK		 879 MBX_TOV_SECONDS);
880}
881
1da177e4
LT		 882/*
883 * qla2x00_abort_command
884 * Abort command aborts a specified IOCB.
885 *
886 * Input:
887 * ha = adapter block pointer.
888 * sp = SB structure pointer.
889 *
890 * Returns:
891 * qla2x00 local function return status code.
892 *
893 * Context:
894 * Kernel context.
895 */
896int
2afa19a9 897qla2x00_abort_command(srb_t *sp)
1da177e4
LT		 898{
899 unsigned long flags = 0;
1da177e4 900 int rval;
73208dfd 901 uint32_t handle = 0;
1da177e4
LT		 902 mbx_cmd_t mc;
903 mbx_cmd_t *mcp = &mc;
2afa19a9
AC		 904 fc_port_t *fcport = sp->fcport;
905 scsi_qla_host_t *vha = fcport->vha;
7b867cf7 906 struct qla_hw_data *ha = vha->hw;
2afa19a9 907 struct req_que *req = vha->req;
9ba56b95 908 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
1da177e4 909
5f28d2d7
SK		 910 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103b,
911 "Entered %s.\n", __func__);
1da177e4 912
c9c5ced9 913 spin_lock_irqsave(&ha->hardware_lock, flags);
8d93f550 914 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
7b867cf7 915 if (req->outstanding_cmds[handle] == sp)
1da177e4
LT		 916 break;
917 }
c9c5ced9 918 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 919
8d93f550 920 if (handle == req->num_outstanding_cmds) {
1da177e4
LT		 921 /* command not found */
922 return QLA_FUNCTION_FAILED;
923 }
924
925 mcp->mb[0] = MBC_ABORT_COMMAND;
926 if (HAS_EXTENDED_IDS(ha))
927 mcp->mb[1] = fcport->loop_id;
928 else
929 mcp->mb[1] = fcport->loop_id << 8;
930 mcp->mb[2] = (uint16_t)handle;
931 mcp->mb[3] = (uint16_t)(handle >> 16);
9ba56b95 932 mcp->mb[6] = (uint16_t)cmd->device->lun;
1da177e4
LT		 933 mcp->out_mb = MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
934 mcp->in_mb = MBX_0;
b93480e3 935 mcp->tov = MBX_TOV_SECONDS;
1da177e4 936 mcp->flags = 0;
7b867cf7 937 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 938
939 if (rval != QLA_SUCCESS) {
7c3df132 940 ql_dbg(ql_dbg_mbx, vha, 0x103c, "Failed=%x.\n", rval);
1da177e4 941 } else {
5f28d2d7
SK		 942 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103d,
943 "Done %s.\n", __func__);
1da177e4
LT		 944 }
945
946 return rval;
947}
948
1da177e4 949int
2afa19a9 950qla2x00_abort_target(struct fc_port *fcport, unsigned int l, int tag)
1da177e4 951{
523ec773 952 int rval, rval2;
1da177e4
LT		 953 mbx_cmd_t mc;
954 mbx_cmd_t *mcp = &mc;
7b867cf7 955 scsi_qla_host_t *vha;
73208dfd
AC		 956 struct req_que *req;
957 struct rsp_que *rsp;
1da177e4 958
523ec773 959 l = l;
7b867cf7 960 vha = fcport->vha;
7c3df132 961
5f28d2d7
SK		 962 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103e,
963 "Entered %s.\n", __func__);
7c3df132 964
7e2b895b
GM		 965 req = vha->hw->req_q_map[0];
966 rsp = req->rsp;
1da177e4 967 mcp->mb[0] = MBC_ABORT_TARGET;
523ec773 968 mcp->out_mb = MBX_9|MBX_2|MBX_1|MBX_0;
7b867cf7 969 if (HAS_EXTENDED_IDS(vha->hw)) {
1da177e4
LT		 970 mcp->mb[1] = fcport->loop_id;
971 mcp->mb[10] = 0;
972 mcp->out_mb |= MBX_10;
973 } else {
974 mcp->mb[1] = fcport->loop_id << 8;
975 }
7b867cf7
AC		 976 mcp->mb[2] = vha->hw->loop_reset_delay;
977 mcp->mb[9] = vha->vp_idx;
1da177e4
LT		 978
979 mcp->in_mb = MBX_0;
b93480e3 980 mcp->tov = MBX_TOV_SECONDS;
1da177e4 981 mcp->flags = 0;
7b867cf7 982 rval = qla2x00_mailbox_command(vha, mcp);
523ec773 983 if (rval != QLA_SUCCESS) {
5f28d2d7
SK		 984 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103f,
985 "Failed=%x.\n", rval);
523ec773
AV		 986 }
987
988 /* Issue marker IOCB. */
73208dfd
AC		 989 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, 0,
990 MK_SYNC_ID);
523ec773 991 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 992 ql_dbg(ql_dbg_mbx, vha, 0x1040,
993 "Failed to issue marker IOCB (%x).\n", rval2);
523ec773 994 } else {
5f28d2d7
SK		 995 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1041,
996 "Done %s.\n", __func__);
523ec773
AV		 997 }
998
999 return rval;
1000}
1001
1002int
2afa19a9 1003qla2x00_lun_reset(struct fc_port *fcport, unsigned int l, int tag)
523ec773
AV		 1004{
1005 int rval, rval2;
1006 mbx_cmd_t mc;
1007 mbx_cmd_t *mcp = &mc;
7b867cf7 1008 scsi_qla_host_t *vha;
73208dfd
AC		 1009 struct req_que *req;
1010 struct rsp_que *rsp;
523ec773 1011
7b867cf7 1012 vha = fcport->vha;
7c3df132 1013
5f28d2d7
SK		 1014 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1042,
1015 "Entered %s.\n", __func__);
7c3df132 1016
7e2b895b
GM		 1017 req = vha->hw->req_q_map[0];
1018 rsp = req->rsp;
523ec773
AV		 1019 mcp->mb[0] = MBC_LUN_RESET;
1020 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
7b867cf7 1021 if (HAS_EXTENDED_IDS(vha->hw))
523ec773
AV		 1022 mcp->mb[1] = fcport->loop_id;
1023 else
1024 mcp->mb[1] = fcport->loop_id << 8;
1025 mcp->mb[2] = l;
1026 mcp->mb[3] = 0;
7b867cf7 1027 mcp->mb[9] = vha->vp_idx;
1da177e4 1028
523ec773 1029 mcp->in_mb = MBX_0;
b93480e3 1030 mcp->tov = MBX_TOV_SECONDS;
523ec773 1031 mcp->flags = 0;
7b867cf7 1032 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4 1033 if (rval != QLA_SUCCESS) {
7c3df132 1034 ql_dbg(ql_dbg_mbx, vha, 0x1043, "Failed=%x.\n", rval);
523ec773
AV		 1035 }
1036
1037 /* Issue marker IOCB. */
73208dfd
AC		 1038 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l,
1039 MK_SYNC_ID_LUN);
523ec773 1040 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 1041 ql_dbg(ql_dbg_mbx, vha, 0x1044,
1042 "Failed to issue marker IOCB (%x).\n", rval2);
1da177e4 1043 } else {
5f28d2d7
SK		 1044 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1045,
1045 "Done %s.\n", __func__);
1da177e4
LT		 1046 }
1047
1048 return rval;
1049}
1da177e4 1050
1da177e4
LT		 1051/*
1052 * qla2x00_get_adapter_id
1053 * Get adapter ID and topology.
1054 *
1055 * Input:
1056 * ha = adapter block pointer.
1057 * id = pointer for loop ID.
1058 * al_pa = pointer for AL_PA.
1059 * area = pointer for area.
1060 * domain = pointer for domain.
1061 * top = pointer for topology.
1062 * TARGET_QUEUE_LOCK must be released.
1063 * ADAPTER_STATE_LOCK must be released.
1064 *
1065 * Returns:
1066 * qla2x00 local function return status code.
1067 *
1068 * Context:
1069 * Kernel context.
1070 */
1071int
7b867cf7 1072qla2x00_get_adapter_id(scsi_qla_host_t *vha, uint16_t *id, uint8_t *al_pa,
2c3dfe3f 1073 uint8_t *area, uint8_t *domain, uint16_t *top, uint16_t *sw_cap)
1da177e4
LT		 1074{
1075 int rval;
1076 mbx_cmd_t mc;
1077 mbx_cmd_t *mcp = &mc;
1078
5f28d2d7
SK		 1079 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1046,
1080 "Entered %s.\n", __func__);
1da177e4
LT		 1081
1082 mcp->mb[0] = MBC_GET_ADAPTER_LOOP_ID;
7b867cf7 1083 mcp->mb[9] = vha->vp_idx;
eb66dc60 1084 mcp->out_mb = MBX_9|MBX_0;
2c3dfe3f 1085 mcp->in_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
6246b8a1 1086 if (IS_CNA_CAPABLE(vha->hw))
bad7001c 1087 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10;
b93480e3 1088 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1089 mcp->flags = 0;
7b867cf7 1090 rval = qla2x00_mailbox_command(vha, mcp);
33135aa2
RA		 1091 if (mcp->mb[0] == MBS_COMMAND_ERROR)
1092 rval = QLA_COMMAND_ERROR;
42e421b1
AV		 1093 else if (mcp->mb[0] == MBS_INVALID_COMMAND)
1094 rval = QLA_INVALID_COMMAND;
1da177e4
LT		 1095
1096 /* Return data. */
1097 *id = mcp->mb[1];
1098 *al_pa = LSB(mcp->mb[2]);
1099 *area = MSB(mcp->mb[2]);
1100 *domain = LSB(mcp->mb[3]);
1101 *top = mcp->mb[6];
2c3dfe3f 1102 *sw_cap = mcp->mb[7];
1da177e4
LT		 1103
1104 if (rval != QLA_SUCCESS) {
1105 /*EMPTY*/
7c3df132 1106 ql_dbg(ql_dbg_mbx, vha, 0x1047, "Failed=%x.\n", rval);
1da177e4 1107 } else {
5f28d2d7
SK		 1108 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1048,
1109 "Done %s.\n", __func__);
bad7001c 1110
6246b8a1 1111 if (IS_CNA_CAPABLE(vha->hw)) {
bad7001c
AV		 1112 vha->fcoe_vlan_id = mcp->mb[9] & 0xfff;
1113 vha->fcoe_fcf_idx = mcp->mb[10];
1114 vha->fcoe_vn_port_mac[5] = mcp->mb[11] >> 8;
1115 vha->fcoe_vn_port_mac[4] = mcp->mb[11] & 0xff;
1116 vha->fcoe_vn_port_mac[3] = mcp->mb[12] >> 8;
1117 vha->fcoe_vn_port_mac[2] = mcp->mb[12] & 0xff;
1118 vha->fcoe_vn_port_mac[1] = mcp->mb[13] >> 8;
1119 vha->fcoe_vn_port_mac[0] = mcp->mb[13] & 0xff;
1120 }
1da177e4
LT		 1121 }
1122
1123 return rval;
1124}
1125
1126/*
1127 * qla2x00_get_retry_cnt
1128 * Get current firmware login retry count and delay.
1129 *
1130 * Input:
1131 * ha = adapter block pointer.
1132 * retry_cnt = pointer to login retry count.
1133 * tov = pointer to login timeout value.
1134 *
1135 * Returns:
1136 * qla2x00 local function return status code.
1137 *
1138 * Context:
1139 * Kernel context.
1140 */
1141int
7b867cf7 1142qla2x00_get_retry_cnt(scsi_qla_host_t *vha, uint8_t *retry_cnt, uint8_t *tov,
1da177e4
LT		 1143 uint16_t *r_a_tov)
1144{
1145 int rval;
1146 uint16_t ratov;
1147 mbx_cmd_t mc;
1148 mbx_cmd_t *mcp = &mc;
1149
5f28d2d7
SK		 1150 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1049,
1151 "Entered %s.\n", __func__);
1da177e4
LT		 1152
1153 mcp->mb[0] = MBC_GET_RETRY_COUNT;
1154 mcp->out_mb = MBX_0;
1155 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
b93480e3 1156 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1157 mcp->flags = 0;
7b867cf7 1158 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1159
1160 if (rval != QLA_SUCCESS) {
1161 /*EMPTY*/
7c3df132
SK		 1162 ql_dbg(ql_dbg_mbx, vha, 0x104a,
1163 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
1da177e4
LT		 1164 } else {
1165 /* Convert returned data and check our values. */
1166 *r_a_tov = mcp->mb[3] / 2;
1167 ratov = (mcp->mb[3]/2) / 10; /* mb[3] value is in 100ms */
1168 if (mcp->mb[1] * ratov > (*retry_cnt) * (*tov)) {
1169 /* Update to the larger values */
1170 *retry_cnt = (uint8_t)mcp->mb[1];
1171 *tov = ratov;
1172 }
1173
5f28d2d7 1174 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104b,
7c3df132 1175 "Done %s mb3=%d ratov=%d.\n", __func__, mcp->mb[3], ratov);
1da177e4
LT		 1176 }
1177
1178 return rval;
1179}
1180
1181/*
1182 * qla2x00_init_firmware
1183 * Initialize adapter firmware.
1184 *
1185 * Input:
1186 * ha = adapter block pointer.
1187 * dptr = Initialization control block pointer.
1188 * size = size of initialization control block.
1189 * TARGET_QUEUE_LOCK must be released.
1190 * ADAPTER_STATE_LOCK must be released.
1191 *
1192 * Returns:
1193 * qla2x00 local function return status code.
1194 *
1195 * Context:
1196 * Kernel context.
1197 */
1198int
7b867cf7 1199qla2x00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
1da177e4
LT		 1200{
1201 int rval;
1202 mbx_cmd_t mc;
1203 mbx_cmd_t *mcp = &mc;
7b867cf7 1204 struct qla_hw_data *ha = vha->hw;
1da177e4 1205
5f28d2d7
SK		 1206 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104c,
1207 "Entered %s.\n", __func__);
1da177e4 1208
7ec0effd 1209 if (IS_P3P_TYPE(ha) && ql2xdbwr)
a9083016
GM		 1210 qla82xx_wr_32(ha, ha->nxdb_wr_ptr,
1211 (0x04 | (ha->portnum << 5) | (0 << 8) | (0 << 16)));
1212
e6e074f1 1213 if (ha->flags.npiv_supported)
2c3dfe3f
SJ		 1214 mcp->mb[0] = MBC_MID_INITIALIZE_FIRMWARE;
1215 else
1216 mcp->mb[0] = MBC_INITIALIZE_FIRMWARE;
1217
b64b0e8f 1218 mcp->mb[1] = 0;
1da177e4
LT		 1219 mcp->mb[2] = MSW(ha->init_cb_dma);
1220 mcp->mb[3] = LSW(ha->init_cb_dma);
1da177e4
LT		 1221 mcp->mb[6] = MSW(MSD(ha->init_cb_dma));
1222 mcp->mb[7] = LSW(MSD(ha->init_cb_dma));
b64b0e8f 1223 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
4ef21bd4 1224 if (ha->ex_init_cb && ha->ex_init_cb->ex_version) {
b64b0e8f
AV		 1225 mcp->mb[1] = BIT_0;
1226 mcp->mb[10] = MSW(ha->ex_init_cb_dma);
1227 mcp->mb[11] = LSW(ha->ex_init_cb_dma);
1228 mcp->mb[12] = MSW(MSD(ha->ex_init_cb_dma));
1229 mcp->mb[13] = LSW(MSD(ha->ex_init_cb_dma));
1230 mcp->mb[14] = sizeof(*ha->ex_init_cb);
1231 mcp->out_mb |= MBX_14|MBX_13|MBX_12|MBX_11|MBX_10;
1232 }
6246b8a1
GM		 1233 /* 1 and 2 should normally be captured. */
1234 mcp->in_mb = MBX_2|MBX_1|MBX_0;
f73cb695 1235 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
6246b8a1
GM		 1236 /* mb3 is additional info about the installed SFP. */
1237 mcp->in_mb |= MBX_3;
1da177e4
LT		 1238 mcp->buf_size = size;
1239 mcp->flags = MBX_DMA_OUT;
b93480e3 1240 mcp->tov = MBX_TOV_SECONDS;
7b867cf7 1241 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1242
1243 if (rval != QLA_SUCCESS) {
1244 /*EMPTY*/
7c3df132 1245 ql_dbg(ql_dbg_mbx, vha, 0x104d,
6246b8a1
GM		 1246 "Failed=%x mb[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x,.\n",
1247 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3]);
1da177e4
LT		 1248 } else {
1249 /*EMPTY*/
5f28d2d7
SK		 1250 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104e,
1251 "Done %s.\n", __func__);
1da177e4
LT		 1252 }
1253
1254 return rval;
1255}
1256
2d70c103
NB		 1257/*
1258 * qla2x00_get_node_name_list
1259 * Issue get node name list mailbox command, kmalloc()
1260 * and return the resulting list. Caller must kfree() it!
1261 *
1262 * Input:
1263 * ha = adapter state pointer.
1264 * out_data = resulting list
1265 * out_len = length of the resulting list
1266 *
1267 * Returns:
1268 * qla2x00 local function return status code.
1269 *
1270 * Context:
1271 * Kernel context.
1272 */
1273int
1274qla2x00_get_node_name_list(scsi_qla_host_t *vha, void **out_data, int *out_len)
1275{
1276 struct qla_hw_data *ha = vha->hw;
1277 struct qla_port_24xx_data *list = NULL;
1278 void *pmap;
1279 mbx_cmd_t mc;
1280 dma_addr_t pmap_dma;
1281 ulong dma_size;
1282 int rval, left;
1283
1284 left = 1;
1285 while (left > 0) {
1286 dma_size = left * sizeof(*list);
1287 pmap = dma_alloc_coherent(&ha->pdev->dev, dma_size,
1288 &pmap_dma, GFP_KERNEL);
1289 if (!pmap) {
1290 ql_log(ql_log_warn, vha, 0x113f,
1291 "%s(%ld): DMA Alloc failed of %ld\n",
1292 __func__, vha->host_no, dma_size);
1293 rval = QLA_MEMORY_ALLOC_FAILED;
1294 goto out;
1295 }
1296
1297 mc.mb[0] = MBC_PORT_NODE_NAME_LIST;
1298 mc.mb[1] = BIT_1 | BIT_3;
1299 mc.mb[2] = MSW(pmap_dma);
1300 mc.mb[3] = LSW(pmap_dma);
1301 mc.mb[6] = MSW(MSD(pmap_dma));
1302 mc.mb[7] = LSW(MSD(pmap_dma));
1303 mc.mb[8] = dma_size;
1304 mc.out_mb = MBX_0|MBX_1|MBX_2|MBX_3|MBX_6|MBX_7|MBX_8;
1305 mc.in_mb = MBX_0|MBX_1;
1306 mc.tov = 30;
1307 mc.flags = MBX_DMA_IN;
1308
1309 rval = qla2x00_mailbox_command(vha, &mc);
1310 if (rval != QLA_SUCCESS) {
1311 if ((mc.mb[0] == MBS_COMMAND_ERROR) &&
1312 (mc.mb[1] == 0xA)) {
1313 left += le16_to_cpu(mc.mb[2]) /
1314 sizeof(struct qla_port_24xx_data);
1315 goto restart;
1316 }
1317 goto out_free;
1318 }
1319
1320 left = 0;
1321
1322 list = kzalloc(dma_size, GFP_KERNEL);
1323 if (!list) {
1324 ql_log(ql_log_warn, vha, 0x1140,
1325 "%s(%ld): failed to allocate node names list "
1326 "structure.\n", __func__, vha->host_no);
1327 rval = QLA_MEMORY_ALLOC_FAILED;
1328 goto out_free;
1329 }
1330
1331 memcpy(list, pmap, dma_size);
1332restart:
1333 dma_free_coherent(&ha->pdev->dev, dma_size, pmap, pmap_dma);
1334 }
1335
1336 *out_data = list;
1337 *out_len = dma_size;
1338
1339out:
1340 return rval;
1341
1342out_free:
1343 dma_free_coherent(&ha->pdev->dev, dma_size, pmap, pmap_dma);
1344 return rval;
1345}
1346
1da177e4
LT		 1347/*
1348 * qla2x00_get_port_database
1349 * Issue normal/enhanced get port database mailbox command
1350 * and copy device name as necessary.
1351 *
1352 * Input:
1353 * ha = adapter state pointer.
1354 * dev = structure pointer.
1355 * opt = enhanced cmd option byte.
1356 *
1357 * Returns:
1358 * qla2x00 local function return status code.
1359 *
1360 * Context:
1361 * Kernel context.
1362 */
1363int
7b867cf7 1364qla2x00_get_port_database(scsi_qla_host_t *vha, fc_port_t *fcport, uint8_t opt)
1da177e4
LT		 1365{
1366 int rval;
1367 mbx_cmd_t mc;
1368 mbx_cmd_t *mcp = &mc;
1369 port_database_t *pd;
1c7c6357 1370 struct port_database_24xx *pd24;
1da177e4 1371 dma_addr_t pd_dma;
7b867cf7 1372 struct qla_hw_data *ha = vha->hw;
1da177e4 1373
5f28d2d7
SK		 1374 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104f,
1375 "Entered %s.\n", __func__);
1da177e4 1376
1c7c6357
AV		 1377 pd24 = NULL;
1378 pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
1da177e4 1379 if (pd == NULL) {
7c3df132
SK		 1380 ql_log(ql_log_warn, vha, 0x1050,
1381 "Failed to allocate port database structure.\n");
1da177e4
LT		 1382 return QLA_MEMORY_ALLOC_FAILED;
1383 }
1c7c6357 1384 memset(pd, 0, max(PORT_DATABASE_SIZE, PORT_DATABASE_24XX_SIZE));
1da177e4 1385
1c7c6357 1386 mcp->mb[0] = MBC_GET_PORT_DATABASE;
e428924c 1387 if (opt != 0 && !IS_FWI2_CAPABLE(ha))
1da177e4 1388 mcp->mb[0] = MBC_ENHANCED_GET_PORT_DATABASE;
1da177e4
LT		 1389 mcp->mb[2] = MSW(pd_dma);
1390 mcp->mb[3] = LSW(pd_dma);
1391 mcp->mb[6] = MSW(MSD(pd_dma));
1392 mcp->mb[7] = LSW(MSD(pd_dma));
7b867cf7 1393 mcp->mb[9] = vha->vp_idx;
2c3dfe3f 1394 mcp->out_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
1da177e4 1395 mcp->in_mb = MBX_0;
e428924c 1396 if (IS_FWI2_CAPABLE(ha)) {
1c7c6357
AV		 1397 mcp->mb[1] = fcport->loop_id;
1398 mcp->mb[10] = opt;
1399 mcp->out_mb |= MBX_10|MBX_1;
1400 mcp->in_mb |= MBX_1;
1401 } else if (HAS_EXTENDED_IDS(ha)) {
1402 mcp->mb[1] = fcport->loop_id;
1403 mcp->mb[10] = opt;
1404 mcp->out_mb |= MBX_10|MBX_1;
1405 } else {
1406 mcp->mb[1] = fcport->loop_id << 8 | opt;
1407 mcp->out_mb |= MBX_1;
1408 }
e428924c
AV		 1409 mcp->buf_size = IS_FWI2_CAPABLE(ha) ?
1410 PORT_DATABASE_24XX_SIZE : PORT_DATABASE_SIZE;
1da177e4
LT		 1411 mcp->flags = MBX_DMA_IN;
1412 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
7b867cf7 1413 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1414 if (rval != QLA_SUCCESS)
1415 goto gpd_error_out;
1416
e428924c 1417 if (IS_FWI2_CAPABLE(ha)) {
0eba25df 1418 uint64_t zero = 0;
1c7c6357
AV		 1419 pd24 = (struct port_database_24xx *) pd;
1420
1421 /* Check for logged in state. */
1422 if (pd24->current_login_state != PDS_PRLI_COMPLETE &&
1423 pd24->last_login_state != PDS_PRLI_COMPLETE) {
7c3df132
SK		 1424 ql_dbg(ql_dbg_mbx, vha, 0x1051,
1425 "Unable to verify login-state (%x/%x) for "
1426 "loop_id %x.\n", pd24->current_login_state,
1427 pd24->last_login_state, fcport->loop_id);
1c7c6357
AV		 1428 rval = QLA_FUNCTION_FAILED;
1429 goto gpd_error_out;
1430 }
1da177e4 1431
0eba25df
AE		 1432 if (fcport->loop_id == FC_NO_LOOP_ID ||
1433 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
1434 memcmp(fcport->port_name, pd24->port_name, 8))) {
1435 /* We lost the device mid way. */
1436 rval = QLA_NOT_LOGGED_IN;
1437 goto gpd_error_out;
1438 }
1439
1c7c6357
AV		 1440 /* Names are little-endian. */
1441 memcpy(fcport->node_name, pd24->node_name, WWN_SIZE);
1442 memcpy(fcport->port_name, pd24->port_name, WWN_SIZE);
1443
1444 /* Get port_id of device. */
1445 fcport->d_id.b.domain = pd24->port_id[0];
1446 fcport->d_id.b.area = pd24->port_id[1];
1447 fcport->d_id.b.al_pa = pd24->port_id[2];
1448 fcport->d_id.b.rsvd_1 = 0;
1449
1450 /* If not target must be initiator or unknown type. */
1451 if ((pd24->prli_svc_param_word_3[0] & BIT_4) == 0)
1452 fcport->port_type = FCT_INITIATOR;
1453 else
1454 fcport->port_type = FCT_TARGET;
2d70c103
NB		 1455
1456 /* Passback COS information. */
1457 fcport->supported_classes = (pd24->flags & PDF_CLASS_2) ?
1458 FC_COS_CLASS2 : FC_COS_CLASS3;
1459
1460 if (pd24->prli_svc_param_word_3[0] & BIT_7)
1461 fcport->flags |= FCF_CONF_COMP_SUPPORTED;
1c7c6357 1462 } else {
0eba25df
AE		 1463 uint64_t zero = 0;
1464
1c7c6357
AV		 1465 /* Check for logged in state. */
1466 if (pd->master_state != PD_STATE_PORT_LOGGED_IN &&
1467 pd->slave_state != PD_STATE_PORT_LOGGED_IN) {
7c3df132
SK		 1468 ql_dbg(ql_dbg_mbx, vha, 0x100a,
1469 "Unable to verify login-state (%x/%x) - "
1470 "portid=%02x%02x%02x.\n", pd->master_state,
1471 pd->slave_state, fcport->d_id.b.domain,
1472 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1c7c6357
AV		 1473 rval = QLA_FUNCTION_FAILED;
1474 goto gpd_error_out;
1475 }
1da177e4 1476
0eba25df
AE		 1477 if (fcport->loop_id == FC_NO_LOOP_ID ||
1478 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
1479 memcmp(fcport->port_name, pd->port_name, 8))) {
1480 /* We lost the device mid way. */
1481 rval = QLA_NOT_LOGGED_IN;
1482 goto gpd_error_out;
1483 }
1484
1c7c6357
AV		 1485 /* Names are little-endian. */
1486 memcpy(fcport->node_name, pd->node_name, WWN_SIZE);
1487 memcpy(fcport->port_name, pd->port_name, WWN_SIZE);
1488
1489 /* Get port_id of device. */
1490 fcport->d_id.b.domain = pd->port_id[0];
1491 fcport->d_id.b.area = pd->port_id[3];
1492 fcport->d_id.b.al_pa = pd->port_id[2];
1493 fcport->d_id.b.rsvd_1 = 0;
1494
1c7c6357
AV		 1495 /* If not target must be initiator or unknown type. */
1496 if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0)
1497 fcport->port_type = FCT_INITIATOR;
1498 else
1499 fcport->port_type = FCT_TARGET;
ad3e0eda
AV		 1500
1501 /* Passback COS information. */
1502 fcport->supported_classes = (pd->options & BIT_4) ?
1503 FC_COS_CLASS2: FC_COS_CLASS3;
1c7c6357 1504 }
1da177e4
LT		 1505
1506gpd_error_out:
1507 dma_pool_free(ha->s_dma_pool, pd, pd_dma);
1508
1509 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1510 ql_dbg(ql_dbg_mbx, vha, 0x1052,
1511 "Failed=%x mb[0]=%x mb[1]=%x.\n", rval,
1512 mcp->mb[0], mcp->mb[1]);
1da177e4 1513 } else {
5f28d2d7
SK		 1514 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1053,
1515 "Done %s.\n", __func__);
1da177e4
LT		 1516 }
1517
1518 return rval;
1519}
1520
1521/*
1522 * qla2x00_get_firmware_state
1523 * Get adapter firmware state.
1524 *
1525 * Input:
1526 * ha = adapter block pointer.
1527 * dptr = pointer for firmware state.
1528 * TARGET_QUEUE_LOCK must be released.
1529 * ADAPTER_STATE_LOCK must be released.
1530 *
1531 * Returns:
1532 * qla2x00 local function return status code.
1533 *
1534 * Context:
1535 * Kernel context.
1536 */
1537int
7b867cf7 1538qla2x00_get_firmware_state(scsi_qla_host_t *vha, uint16_t *states)
1da177e4
LT		 1539{
1540 int rval;
1541 mbx_cmd_t mc;
1542 mbx_cmd_t *mcp = &mc;
1543
5f28d2d7
SK		 1544 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1054,
1545 "Entered %s.\n", __func__);
1da177e4
LT		 1546
1547 mcp->mb[0] = MBC_GET_FIRMWARE_STATE;
1548 mcp->out_mb = MBX_0;
9d2683c0
AV		 1549 if (IS_FWI2_CAPABLE(vha->hw))
1550 mcp->in_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
1551 else
1552 mcp->in_mb = MBX_1|MBX_0;
b93480e3 1553 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1554 mcp->flags = 0;
7b867cf7 1555 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4 1556
4d4df193
HK		 1557 /* Return firmware states. */
1558 states[0] = mcp->mb[1];
9d2683c0
AV		 1559 if (IS_FWI2_CAPABLE(vha->hw)) {
1560 states[1] = mcp->mb[2];
1561 states[2] = mcp->mb[3];
1562 states[3] = mcp->mb[4];
1563 states[4] = mcp->mb[5];
1564 }
1da177e4
LT		 1565
1566 if (rval != QLA_SUCCESS) {
1567 /*EMPTY*/
7c3df132 1568 ql_dbg(ql_dbg_mbx, vha, 0x1055, "Failed=%x.\n", rval);
1da177e4
LT		 1569 } else {
1570 /*EMPTY*/
5f28d2d7
SK		 1571 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1056,
1572 "Done %s.\n", __func__);
1da177e4
LT		 1573 }
1574
1575 return rval;
1576}
1577
1578/*
1579 * qla2x00_get_port_name
1580 * Issue get port name mailbox command.
1581 * Returned name is in big endian format.
1582 *
1583 * Input:
1584 * ha = adapter block pointer.
1585 * loop_id = loop ID of device.
1586 * name = pointer for name.
1587 * TARGET_QUEUE_LOCK must be released.
1588 * ADAPTER_STATE_LOCK must be released.
1589 *
1590 * Returns:
1591 * qla2x00 local function return status code.
1592 *
1593 * Context:
1594 * Kernel context.
1595 */
1596int
7b867cf7 1597qla2x00_get_port_name(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t *name,
1da177e4
LT		 1598 uint8_t opt)
1599{
1600 int rval;
1601 mbx_cmd_t mc;
1602 mbx_cmd_t *mcp = &mc;
1603
5f28d2d7
SK		 1604 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1057,
1605 "Entered %s.\n", __func__);
1da177e4
LT		 1606
1607 mcp->mb[0] = MBC_GET_PORT_NAME;
7b867cf7 1608 mcp->mb[9] = vha->vp_idx;
2c3dfe3f 1609 mcp->out_mb = MBX_9|MBX_1|MBX_0;
7b867cf7 1610 if (HAS_EXTENDED_IDS(vha->hw)) {
1da177e4
LT		 1611 mcp->mb[1] = loop_id;
1612 mcp->mb[10] = opt;
1613 mcp->out_mb |= MBX_10;
1614 } else {
1615 mcp->mb[1] = loop_id << 8 | opt;
1616 }
1617
1618 mcp->in_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
b93480e3 1619 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1620 mcp->flags = 0;
7b867cf7 1621 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1622
1623 if (rval != QLA_SUCCESS) {
1624 /*EMPTY*/
7c3df132 1625 ql_dbg(ql_dbg_mbx, vha, 0x1058, "Failed=%x.\n", rval);
1da177e4
LT		 1626 } else {
1627 if (name != NULL) {
1628 /* This function returns name in big endian. */
1196ae02
RL		 1629 name[0] = MSB(mcp->mb[2]);
1630 name[1] = LSB(mcp->mb[2]);
1631 name[2] = MSB(mcp->mb[3]);
1632 name[3] = LSB(mcp->mb[3]);
1633 name[4] = MSB(mcp->mb[6]);
1634 name[5] = LSB(mcp->mb[6]);
1635 name[6] = MSB(mcp->mb[7]);
1636 name[7] = LSB(mcp->mb[7]);
1da177e4
LT		 1637 }
1638
5f28d2d7
SK		 1639 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1059,
1640 "Done %s.\n", __func__);
1da177e4
LT		 1641 }
1642
1643 return rval;
1644}
1645
61e1b269
JC		 1646/*
1647 * qla24xx_link_initialization
1648 * Issue link initialization mailbox command.
1649 *
1650 * Input:
1651 * ha = adapter block pointer.
1652 * TARGET_QUEUE_LOCK must be released.
1653 * ADAPTER_STATE_LOCK must be released.
1654 *
1655 * Returns:
1656 * qla2x00 local function return status code.
1657 *
1658 * Context:
1659 * Kernel context.
1660 */
1661int
1662qla24xx_link_initialize(scsi_qla_host_t *vha)
1663{
1664 int rval;
1665 mbx_cmd_t mc;
1666 mbx_cmd_t *mcp = &mc;
1667
1668 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1152,
1669 "Entered %s.\n", __func__);
1670
1671 if (!IS_FWI2_CAPABLE(vha->hw) || IS_CNA_CAPABLE(vha->hw))
1672 return QLA_FUNCTION_FAILED;
1673
1674 mcp->mb[0] = MBC_LINK_INITIALIZATION;
5a5c27b6
JC		 1675 mcp->mb[1] = BIT_4;
1676 if (vha->hw->operating_mode == LOOP)
1677 mcp->mb[1] |= BIT_6;
1678 else
1679 mcp->mb[1] |= BIT_5;
61e1b269
JC		 1680 mcp->mb[2] = 0;
1681 mcp->mb[3] = 0;
1682 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1683 mcp->in_mb = MBX_0;
1684 mcp->tov = MBX_TOV_SECONDS;
1685 mcp->flags = 0;
1686 rval = qla2x00_mailbox_command(vha, mcp);
1687
1688 if (rval != QLA_SUCCESS) {
1689 ql_dbg(ql_dbg_mbx, vha, 0x1153, "Failed=%x.\n", rval);
1690 } else {
1691 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1154,
1692 "Done %s.\n", __func__);
1693 }
1694
1695 return rval;
1696}
1697
1da177e4
LT		 1698/*
1699 * qla2x00_lip_reset
1700 * Issue LIP reset mailbox command.
1701 *
1702 * Input:
1703 * ha = adapter block pointer.
1704 * TARGET_QUEUE_LOCK must be released.
1705 * ADAPTER_STATE_LOCK must be released.
1706 *
1707 * Returns:
1708 * qla2x00 local function return status code.
1709 *
1710 * Context:
1711 * Kernel context.
1712 */
1713int
7b867cf7 1714qla2x00_lip_reset(scsi_qla_host_t *vha)
1da177e4
LT		 1715{
1716 int rval;
1717 mbx_cmd_t mc;
1718 mbx_cmd_t *mcp = &mc;
1719
5f28d2d7
SK		 1720 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105a,
1721 "Entered %s.\n", __func__);
1da177e4 1722
6246b8a1 1723 if (IS_CNA_CAPABLE(vha->hw)) {
3a03eb79
AV		 1724 /* Logout across all FCFs. */
1725 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
1726 mcp->mb[1] = BIT_1;
1727 mcp->mb[2] = 0;
1728 mcp->out_mb = MBX_2|MBX_1|MBX_0;
1729 } else if (IS_FWI2_CAPABLE(vha->hw)) {
1c7c6357 1730 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
0c8c39af
AV		 1731 mcp->mb[1] = BIT_6;
1732 mcp->mb[2] = 0;
7b867cf7 1733 mcp->mb[3] = vha->hw->loop_reset_delay;
1c7c6357 1734 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1da177e4 1735 } else {
1c7c6357
AV		 1736 mcp->mb[0] = MBC_LIP_RESET;
1737 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
7b867cf7 1738 if (HAS_EXTENDED_IDS(vha->hw)) {
1c7c6357
AV		 1739 mcp->mb[1] = 0x00ff;
1740 mcp->mb[10] = 0;
1741 mcp->out_mb |= MBX_10;
1742 } else {
1743 mcp->mb[1] = 0xff00;
1744 }
7b867cf7 1745 mcp->mb[2] = vha->hw->loop_reset_delay;
1c7c6357 1746 mcp->mb[3] = 0;
1da177e4 1747 }
1da177e4 1748 mcp->in_mb = MBX_0;
b93480e3 1749 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1750 mcp->flags = 0;
7b867cf7 1751 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1752
1753 if (rval != QLA_SUCCESS) {
1754 /*EMPTY*/
7c3df132 1755 ql_dbg(ql_dbg_mbx, vha, 0x105b, "Failed=%x.\n", rval);
1da177e4
LT		 1756 } else {
1757 /*EMPTY*/
5f28d2d7
SK		 1758 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105c,
1759 "Done %s.\n", __func__);
1da177e4
LT		 1760 }
1761
1762 return rval;
1763}
1764
1765/*
1766 * qla2x00_send_sns
1767 * Send SNS command.
1768 *
1769 * Input:
1770 * ha = adapter block pointer.
1771 * sns = pointer for command.
1772 * cmd_size = command size.
1773 * buf_size = response/command size.
1774 * TARGET_QUEUE_LOCK must be released.
1775 * ADAPTER_STATE_LOCK must be released.
1776 *
1777 * Returns:
1778 * qla2x00 local function return status code.
1779 *
1780 * Context:
1781 * Kernel context.
1782 */
1783int
7b867cf7 1784qla2x00_send_sns(scsi_qla_host_t *vha, dma_addr_t sns_phys_address,
1da177e4
LT		 1785 uint16_t cmd_size, size_t buf_size)
1786{
1787 int rval;
1788 mbx_cmd_t mc;
1789 mbx_cmd_t *mcp = &mc;
1790
5f28d2d7
SK		 1791 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105d,
1792 "Entered %s.\n", __func__);
1da177e4 1793
5f28d2d7 1794 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105e,
7c3df132
SK		 1795 "Retry cnt=%d ratov=%d total tov=%d.\n",
1796 vha->hw->retry_count, vha->hw->login_timeout, mcp->tov);
1da177e4
LT		 1797
1798 mcp->mb[0] = MBC_SEND_SNS_COMMAND;
1799 mcp->mb[1] = cmd_size;
1800 mcp->mb[2] = MSW(sns_phys_address);
1801 mcp->mb[3] = LSW(sns_phys_address);
1802 mcp->mb[6] = MSW(MSD(sns_phys_address));
1803 mcp->mb[7] = LSW(MSD(sns_phys_address));
1804 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1805 mcp->in_mb = MBX_0|MBX_1;
1806 mcp->buf_size = buf_size;
1807 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN;
7b867cf7
AC		 1808 mcp->tov = (vha->hw->login_timeout * 2) + (vha->hw->login_timeout / 2);
1809 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1810
1811 if (rval != QLA_SUCCESS) {
1812 /*EMPTY*/
7c3df132
SK		 1813 ql_dbg(ql_dbg_mbx, vha, 0x105f,
1814 "Failed=%x mb[0]=%x mb[1]=%x.\n",
1815 rval, mcp->mb[0], mcp->mb[1]);
1da177e4
LT		 1816 } else {
1817 /*EMPTY*/
5f28d2d7
SK		 1818 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1060,
1819 "Done %s.\n", __func__);
1da177e4
LT		 1820 }
1821
1822 return rval;
1823}
1824
1c7c6357 1825int
7b867cf7 1826qla24xx_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
1c7c6357
AV		 1827 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
1828{
1829 int rval;
1830
1831 struct logio_entry_24xx *lg;
1832 dma_addr_t lg_dma;
1833 uint32_t iop[2];
7b867cf7 1834 struct qla_hw_data *ha = vha->hw;
2afa19a9
AC		 1835 struct req_que *req;
1836 struct rsp_que *rsp;
1c7c6357 1837
5f28d2d7
SK		 1838 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1061,
1839 "Entered %s.\n", __func__);
1c7c6357 1840
7163ea81 1841 if (ha->flags.cpu_affinity_enabled)
68ca949c
AC		 1842 req = ha->req_q_map[0];
1843 else
1844 req = vha->req;
2afa19a9
AC		 1845 rsp = req->rsp;
1846
1c7c6357
AV		 1847 lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
1848 if (lg == NULL) {
7c3df132
SK		 1849 ql_log(ql_log_warn, vha, 0x1062,
1850 "Failed to allocate login IOCB.\n");
1c7c6357
AV		 1851 return QLA_MEMORY_ALLOC_FAILED;
1852 }
1853 memset(lg, 0, sizeof(struct logio_entry_24xx));
1854
1855 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
1856 lg->entry_count = 1;
2afa19a9 1857 lg->handle = MAKE_HANDLE(req->id, lg->handle);
1c7c6357
AV		 1858 lg->nport_handle = cpu_to_le16(loop_id);
1859 lg->control_flags = __constant_cpu_to_le16(LCF_COMMAND_PLOGI);
1860 if (opt & BIT_0)
1861 lg->control_flags |= __constant_cpu_to_le16(LCF_COND_PLOGI);
8baa51a6
AV		 1862 if (opt & BIT_1)
1863 lg->control_flags |= __constant_cpu_to_le16(LCF_SKIP_PRLI);
1c7c6357
AV		 1864 lg->port_id[0] = al_pa;
1865 lg->port_id[1] = area;
1866 lg->port_id[2] = domain;
7b867cf7 1867 lg->vp_index = vha->vp_idx;
7f45dd0b
AV		 1868 rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0,
1869 (ha->r_a_tov / 10 * 2) + 2);
1c7c6357 1870 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1871 ql_dbg(ql_dbg_mbx, vha, 0x1063,
1872 "Failed to issue login IOCB (%x).\n", rval);
1c7c6357 1873 } else if (lg->entry_status != 0) {
7c3df132
SK		 1874 ql_dbg(ql_dbg_mbx, vha, 0x1064,
1875 "Failed to complete IOCB -- error status (%x).\n",
1876 lg->entry_status);
1c7c6357
AV		 1877 rval = QLA_FUNCTION_FAILED;
1878 } else if (lg->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
1879 iop[0] = le32_to_cpu(lg->io_parameter[0]);
1880 iop[1] = le32_to_cpu(lg->io_parameter[1]);
1881
7c3df132
SK		 1882 ql_dbg(ql_dbg_mbx, vha, 0x1065,
1883 "Failed to complete IOCB -- completion status (%x) "
1884 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
1885 iop[0], iop[1]);
1c7c6357
AV		 1886
1887 switch (iop[0]) {
1888 case LSC_SCODE_PORTID_USED:
1889 mb[0] = MBS_PORT_ID_USED;
1890 mb[1] = LSW(iop[1]);
1891 break;
1892 case LSC_SCODE_NPORT_USED:
1893 mb[0] = MBS_LOOP_ID_USED;
1894 break;
1895 case LSC_SCODE_NOLINK:
1896 case LSC_SCODE_NOIOCB:
1897 case LSC_SCODE_NOXCB:
1898 case LSC_SCODE_CMD_FAILED:
1899 case LSC_SCODE_NOFABRIC:
1900 case LSC_SCODE_FW_NOT_READY:
1901 case LSC_SCODE_NOT_LOGGED_IN:
1902 case LSC_SCODE_NOPCB:
1903 case LSC_SCODE_ELS_REJECT:
1904 case LSC_SCODE_CMD_PARAM_ERR:
1905 case LSC_SCODE_NONPORT:
1906 case LSC_SCODE_LOGGED_IN:
1907 case LSC_SCODE_NOFLOGI_ACC:
1908 default:
1909 mb[0] = MBS_COMMAND_ERROR;
1910 break;
1911 }
1912 } else {
5f28d2d7
SK		 1913 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1066,
1914 "Done %s.\n", __func__);
1c7c6357
AV		 1915
1916 iop[0] = le32_to_cpu(lg->io_parameter[0]);
1917
1918 mb[0] = MBS_COMMAND_COMPLETE;
1919 mb[1] = 0;
1920 if (iop[0] & BIT_4) {
1921 if (iop[0] & BIT_8)
1922 mb[1] |= BIT_1;
1923 } else
1924 mb[1] = BIT_0;
ad3e0eda
AV		 1925
1926 /* Passback COS information. */
1927 mb[10] = 0;
1928 if (lg->io_parameter[7] || lg->io_parameter[8])
1929 mb[10] |= BIT_0; /* Class 2. */
1930 if (lg->io_parameter[9] || lg->io_parameter[10])
1931 mb[10] |= BIT_1; /* Class 3. */
2d70c103
NB		 1932 if (lg->io_parameter[0] & __constant_cpu_to_le32(BIT_7))
1933 mb[10] |= BIT_7; /* Confirmed Completion
1934 * Allowed
1935 */
1c7c6357
AV		 1936 }
1937
1938 dma_pool_free(ha->s_dma_pool, lg, lg_dma);
1939
1940 return rval;
1941}
1942
1da177e4
LT		 1943/*
1944 * qla2x00_login_fabric
1945 * Issue login fabric port mailbox command.
1946 *
1947 * Input:
1948 * ha = adapter block pointer.
1949 * loop_id = device loop ID.
1950 * domain = device domain.
1951 * area = device area.
1952 * al_pa = device AL_PA.
1953 * status = pointer for return status.
1954 * opt = command options.
1955 * TARGET_QUEUE_LOCK must be released.
1956 * ADAPTER_STATE_LOCK must be released.
1957 *
1958 * Returns:
1959 * qla2x00 local function return status code.
1960 *
1961 * Context:
1962 * Kernel context.
1963 */
1964int
7b867cf7 1965qla2x00_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
1da177e4
LT		 1966 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
1967{
1968 int rval;
1969 mbx_cmd_t mc;
1970 mbx_cmd_t *mcp = &mc;
7b867cf7 1971 struct qla_hw_data *ha = vha->hw;
1da177e4 1972
5f28d2d7
SK		 1973 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1067,
1974 "Entered %s.\n", __func__);
1da177e4
LT		 1975
1976 mcp->mb[0] = MBC_LOGIN_FABRIC_PORT;
1977 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1978 if (HAS_EXTENDED_IDS(ha)) {
1979 mcp->mb[1] = loop_id;
1980 mcp->mb[10] = opt;
1981 mcp->out_mb |= MBX_10;
1982 } else {
1983 mcp->mb[1] = (loop_id << 8) | opt;
1984 }
1985 mcp->mb[2] = domain;
1986 mcp->mb[3] = area << 8 | al_pa;
1987
1988 mcp->in_mb = MBX_7|MBX_6|MBX_2|MBX_1|MBX_0;
1989 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
1990 mcp->flags = 0;
7b867cf7 1991 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1992
1993 /* Return mailbox statuses. */
1994 if (mb != NULL) {
1995 mb[0] = mcp->mb[0];
1996 mb[1] = mcp->mb[1];
1997 mb[2] = mcp->mb[2];
1998 mb[6] = mcp->mb[6];
1999 mb[7] = mcp->mb[7];
ad3e0eda
AV		 2000 /* COS retrieved from Get-Port-Database mailbox command. */
2001 mb[10] = 0;
1da177e4
LT		 2002 }
2003
2004 if (rval != QLA_SUCCESS) {
2005 /* RLU tmp code: need to change main mailbox_command function to
2006 * return ok even when the mailbox completion value is not
2007 * SUCCESS. The caller needs to be responsible to interpret
2008 * the return values of this mailbox command if we're not
2009 * to change too much of the existing code.
2010 */
2011 if (mcp->mb[0] == 0x4001 || mcp->mb[0] == 0x4002 ||
2012 mcp->mb[0] == 0x4003 || mcp->mb[0] == 0x4005 ||
2013 mcp->mb[0] == 0x4006)
2014 rval = QLA_SUCCESS;
2015
2016 /*EMPTY*/
7c3df132
SK		 2017 ql_dbg(ql_dbg_mbx, vha, 0x1068,
2018 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
2019 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
1da177e4
LT		 2020 } else {
2021 /*EMPTY*/
5f28d2d7
SK		 2022 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1069,
2023 "Done %s.\n", __func__);
1da177e4
LT		 2024 }
2025
2026 return rval;
2027}
2028
2029/*
2030 * qla2x00_login_local_device
2031 * Issue login loop port mailbox command.
fa2a1ce5 2032 *
1da177e4
LT		 2033 * Input:
2034 * ha = adapter block pointer.
2035 * loop_id = device loop ID.
2036 * opt = command options.
fa2a1ce5 2037 *
1da177e4
LT		 2038 * Returns:
2039 * Return status code.
fa2a1ce5 2040 *
1da177e4
LT		 2041 * Context:
2042 * Kernel context.
fa2a1ce5 2043 *
1da177e4
LT		 2044 */
2045int
7b867cf7 2046qla2x00_login_local_device(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 2047 uint16_t *mb_ret, uint8_t opt)
2048{
2049 int rval;
2050 mbx_cmd_t mc;
2051 mbx_cmd_t *mcp = &mc;
7b867cf7 2052 struct qla_hw_data *ha = vha->hw;
1da177e4 2053
5f28d2d7
SK		 2054 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106a,
2055 "Entered %s.\n", __func__);
7c3df132 2056
e428924c 2057 if (IS_FWI2_CAPABLE(ha))
7b867cf7 2058 return qla24xx_login_fabric(vha, fcport->loop_id,
9a52a57c
AV		 2059 fcport->d_id.b.domain, fcport->d_id.b.area,
2060 fcport->d_id.b.al_pa, mb_ret, opt);
2061
1da177e4
LT		 2062 mcp->mb[0] = MBC_LOGIN_LOOP_PORT;
2063 if (HAS_EXTENDED_IDS(ha))
9a52a57c 2064 mcp->mb[1] = fcport->loop_id;
1da177e4 2065 else
9a52a57c 2066 mcp->mb[1] = fcport->loop_id << 8;
1da177e4
LT		 2067 mcp->mb[2] = opt;
2068 mcp->out_mb = MBX_2|MBX_1|MBX_0;
2069 mcp->in_mb = MBX_7|MBX_6|MBX_1|MBX_0;
2070 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
2071 mcp->flags = 0;
7b867cf7 2072 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2073
2074 /* Return mailbox statuses. */
2075 if (mb_ret != NULL) {
2076 mb_ret[0] = mcp->mb[0];
2077 mb_ret[1] = mcp->mb[1];
2078 mb_ret[6] = mcp->mb[6];
2079 mb_ret[7] = mcp->mb[7];
2080 }
2081
2082 if (rval != QLA_SUCCESS) {
2083 /* AV tmp code: need to change main mailbox_command function to
2084 * return ok even when the mailbox completion value is not
2085 * SUCCESS. The caller needs to be responsible to interpret
2086 * the return values of this mailbox command if we're not
2087 * to change too much of the existing code.
2088 */
2089 if (mcp->mb[0] == 0x4005 || mcp->mb[0] == 0x4006)
2090 rval = QLA_SUCCESS;
2091
7c3df132
SK		 2092 ql_dbg(ql_dbg_mbx, vha, 0x106b,
2093 "Failed=%x mb[0]=%x mb[1]=%x mb[6]=%x mb[7]=%x.\n",
2094 rval, mcp->mb[0], mcp->mb[1], mcp->mb[6], mcp->mb[7]);
1da177e4
LT		 2095 } else {
2096 /*EMPTY*/
5f28d2d7
SK		 2097 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106c,
2098 "Done %s.\n", __func__);
1da177e4
LT		 2099 }
2100
2101 return (rval);
2102}
2103
1c7c6357 2104int
7b867cf7 2105qla24xx_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
1c7c6357
AV		 2106 uint8_t area, uint8_t al_pa)
2107{
2108 int rval;
2109 struct logio_entry_24xx *lg;
2110 dma_addr_t lg_dma;
7b867cf7 2111 struct qla_hw_data *ha = vha->hw;
2afa19a9
AC		 2112 struct req_que *req;
2113 struct rsp_que *rsp;
1c7c6357 2114
5f28d2d7
SK		 2115 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106d,
2116 "Entered %s.\n", __func__);
1c7c6357
AV		 2117
2118 lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
2119 if (lg == NULL) {
7c3df132
SK		 2120 ql_log(ql_log_warn, vha, 0x106e,
2121 "Failed to allocate logout IOCB.\n");
1c7c6357
AV		 2122 return QLA_MEMORY_ALLOC_FAILED;
2123 }
2124 memset(lg, 0, sizeof(struct logio_entry_24xx));
2125
2afa19a9
AC		 2126 if (ql2xmaxqueues > 1)
2127 req = ha->req_q_map[0];
2128 else
2129 req = vha->req;
2130 rsp = req->rsp;
1c7c6357
AV		 2131 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
2132 lg->entry_count = 1;
2afa19a9 2133 lg->handle = MAKE_HANDLE(req->id, lg->handle);
1c7c6357
AV		 2134 lg->nport_handle = cpu_to_le16(loop_id);
2135 lg->control_flags =
c8d6691b
AV		 2136 __constant_cpu_to_le16(LCF_COMMAND_LOGO|LCF_IMPL_LOGO|
2137 LCF_FREE_NPORT);
1c7c6357
AV		 2138 lg->port_id[0] = al_pa;
2139 lg->port_id[1] = area;
2140 lg->port_id[2] = domain;
7b867cf7 2141 lg->vp_index = vha->vp_idx;
7f45dd0b
AV		 2142 rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0,
2143 (ha->r_a_tov / 10 * 2) + 2);
1c7c6357 2144 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2145 ql_dbg(ql_dbg_mbx, vha, 0x106f,
2146 "Failed to issue logout IOCB (%x).\n", rval);
1c7c6357 2147 } else if (lg->entry_status != 0) {
7c3df132
SK		 2148 ql_dbg(ql_dbg_mbx, vha, 0x1070,
2149 "Failed to complete IOCB -- error status (%x).\n",
2150 lg->entry_status);
1c7c6357
AV		 2151 rval = QLA_FUNCTION_FAILED;
2152 } else if (lg->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
7c3df132
SK		 2153 ql_dbg(ql_dbg_mbx, vha, 0x1071,
2154 "Failed to complete IOCB -- completion status (%x) "
2155 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
1c7c6357 2156 le32_to_cpu(lg->io_parameter[0]),
7c3df132 2157 le32_to_cpu(lg->io_parameter[1]));
1c7c6357
AV		 2158 } else {
2159 /*EMPTY*/
5f28d2d7
SK		 2160 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1072,
2161 "Done %s.\n", __func__);
1c7c6357
AV		 2162 }
2163
2164 dma_pool_free(ha->s_dma_pool, lg, lg_dma);
2165
2166 return rval;
2167}
2168
1da177e4
LT		 2169/*
2170 * qla2x00_fabric_logout
2171 * Issue logout fabric port mailbox command.
2172 *
2173 * Input:
2174 * ha = adapter block pointer.
2175 * loop_id = device loop ID.
2176 * TARGET_QUEUE_LOCK must be released.
2177 * ADAPTER_STATE_LOCK must be released.
2178 *
2179 * Returns:
2180 * qla2x00 local function return status code.
2181 *
2182 * Context:
2183 * Kernel context.
2184 */
2185int
7b867cf7 2186qla2x00_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
1c7c6357 2187 uint8_t area, uint8_t al_pa)
1da177e4
LT		 2188{
2189 int rval;
2190 mbx_cmd_t mc;
2191 mbx_cmd_t *mcp = &mc;
2192
5f28d2d7
SK		 2193 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1073,
2194 "Entered %s.\n", __func__);
1da177e4
LT		 2195
2196 mcp->mb[0] = MBC_LOGOUT_FABRIC_PORT;
2197 mcp->out_mb = MBX_1|MBX_0;
7b867cf7 2198 if (HAS_EXTENDED_IDS(vha->hw)) {
1da177e4
LT		 2199 mcp->mb[1] = loop_id;
2200 mcp->mb[10] = 0;
2201 mcp->out_mb |= MBX_10;
2202 } else {
2203 mcp->mb[1] = loop_id << 8;
2204 }
2205
2206 mcp->in_mb = MBX_1|MBX_0;
b93480e3 2207 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2208 mcp->flags = 0;
7b867cf7 2209 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2210
2211 if (rval != QLA_SUCCESS) {
2212 /*EMPTY*/
7c3df132
SK		 2213 ql_dbg(ql_dbg_mbx, vha, 0x1074,
2214 "Failed=%x mb[1]=%x.\n", rval, mcp->mb[1]);
1da177e4
LT		 2215 } else {
2216 /*EMPTY*/
5f28d2d7
SK		 2217 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1075,
2218 "Done %s.\n", __func__);
1da177e4
LT		 2219 }
2220
2221 return rval;
2222}
2223
2224/*
2225 * qla2x00_full_login_lip
2226 * Issue full login LIP mailbox command.
2227 *
2228 * Input:
2229 * ha = adapter block pointer.
2230 * TARGET_QUEUE_LOCK must be released.
2231 * ADAPTER_STATE_LOCK must be released.
2232 *
2233 * Returns:
2234 * qla2x00 local function return status code.
2235 *
2236 * Context:
2237 * Kernel context.
2238 */
2239int
7b867cf7 2240qla2x00_full_login_lip(scsi_qla_host_t *vha)
1da177e4
LT		 2241{
2242 int rval;
2243 mbx_cmd_t mc;
2244 mbx_cmd_t *mcp = &mc;
2245
5f28d2d7
SK		 2246 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1076,
2247 "Entered %s.\n", __func__);
1da177e4
LT		 2248
2249 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
7b867cf7 2250 mcp->mb[1] = IS_FWI2_CAPABLE(vha->hw) ? BIT_3 : 0;
0c8c39af 2251 mcp->mb[2] = 0;
1da177e4
LT		 2252 mcp->mb[3] = 0;
2253 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
2254 mcp->in_mb = MBX_0;
b93480e3 2255 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2256 mcp->flags = 0;
7b867cf7 2257 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2258
2259 if (rval != QLA_SUCCESS) {
2260 /*EMPTY*/
7c3df132 2261 ql_dbg(ql_dbg_mbx, vha, 0x1077, "Failed=%x.\n", rval);
1da177e4
LT		 2262 } else {
2263 /*EMPTY*/
5f28d2d7
SK		 2264 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1078,
2265 "Done %s.\n", __func__);
1da177e4
LT		 2266 }
2267
2268 return rval;
2269}
2270
2271/*
2272 * qla2x00_get_id_list
2273 *
2274 * Input:
2275 * ha = adapter block pointer.
2276 *
2277 * Returns:
2278 * qla2x00 local function return status code.
2279 *
2280 * Context:
2281 * Kernel context.
2282 */
2283int
7b867cf7 2284qla2x00_get_id_list(scsi_qla_host_t *vha, void *id_list, dma_addr_t id_list_dma,
1da177e4
LT		 2285 uint16_t *entries)
2286{
2287 int rval;
2288 mbx_cmd_t mc;
2289 mbx_cmd_t *mcp = &mc;
2290
5f28d2d7
SK		 2291 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1079,
2292 "Entered %s.\n", __func__);
1da177e4
LT		 2293
2294 if (id_list == NULL)
2295 return QLA_FUNCTION_FAILED;
2296
2297 mcp->mb[0] = MBC_GET_ID_LIST;
1c7c6357 2298 mcp->out_mb = MBX_0;
7b867cf7 2299 if (IS_FWI2_CAPABLE(vha->hw)) {
1c7c6357
AV		 2300 mcp->mb[2] = MSW(id_list_dma);
2301 mcp->mb[3] = LSW(id_list_dma);
2302 mcp->mb[6] = MSW(MSD(id_list_dma));
2303 mcp->mb[7] = LSW(MSD(id_list_dma));
247ec457 2304 mcp->mb[8] = 0;
7b867cf7 2305 mcp->mb[9] = vha->vp_idx;
2c3dfe3f 2306 mcp->out_mb |= MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2;
1c7c6357
AV		 2307 } else {
2308 mcp->mb[1] = MSW(id_list_dma);
2309 mcp->mb[2] = LSW(id_list_dma);
2310 mcp->mb[3] = MSW(MSD(id_list_dma));
2311 mcp->mb[6] = LSW(MSD(id_list_dma));
2312 mcp->out_mb |= MBX_6|MBX_3|MBX_2|MBX_1;
2313 }
1da177e4 2314 mcp->in_mb = MBX_1|MBX_0;
b93480e3 2315 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2316 mcp->flags = 0;
7b867cf7 2317 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2318
2319 if (rval != QLA_SUCCESS) {
2320 /*EMPTY*/
7c3df132 2321 ql_dbg(ql_dbg_mbx, vha, 0x107a, "Failed=%x.\n", rval);
1da177e4
LT		 2322 } else {
2323 *entries = mcp->mb[1];
5f28d2d7
SK		 2324 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107b,
2325 "Done %s.\n", __func__);
1da177e4
LT		 2326 }
2327
2328 return rval;
2329}
2330
2331/*
2332 * qla2x00_get_resource_cnts
2333 * Get current firmware resource counts.
2334 *
2335 * Input:
2336 * ha = adapter block pointer.
2337 *
2338 * Returns:
2339 * qla2x00 local function return status code.
2340 *
2341 * Context:
2342 * Kernel context.
2343 */
2344int
7b867cf7 2345qla2x00_get_resource_cnts(scsi_qla_host_t *vha, uint16_t *cur_xchg_cnt,
4d0ea247 2346 uint16_t *orig_xchg_cnt, uint16_t *cur_iocb_cnt,
f3a0a77e 2347 uint16_t *orig_iocb_cnt, uint16_t *max_npiv_vports, uint16_t *max_fcfs)
1da177e4
LT		 2348{
2349 int rval;
2350 mbx_cmd_t mc;
2351 mbx_cmd_t *mcp = &mc;
2352
5f28d2d7
SK		 2353 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107c,
2354 "Entered %s.\n", __func__);
1da177e4
LT		 2355
2356 mcp->mb[0] = MBC_GET_RESOURCE_COUNTS;
2357 mcp->out_mb = MBX_0;
4d0ea247 2358 mcp->in_mb = MBX_11|MBX_10|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
f73cb695 2359 if (IS_QLA81XX(vha->hw) || IS_QLA83XX(vha->hw) || IS_QLA27XX(vha->hw))
f3a0a77e 2360 mcp->in_mb |= MBX_12;
b93480e3 2361 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2362 mcp->flags = 0;
7b867cf7 2363 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2364
2365 if (rval != QLA_SUCCESS) {
2366 /*EMPTY*/
7c3df132
SK		 2367 ql_dbg(ql_dbg_mbx, vha, 0x107d,
2368 "Failed mb[0]=%x.\n", mcp->mb[0]);
1da177e4 2369 } else {
5f28d2d7 2370 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107e,
7c3df132
SK		 2371 "Done %s mb1=%x mb2=%x mb3=%x mb6=%x mb7=%x mb10=%x "
2372 "mb11=%x mb12=%x.\n", __func__, mcp->mb[1], mcp->mb[2],
2373 mcp->mb[3], mcp->mb[6], mcp->mb[7], mcp->mb[10],
2374 mcp->mb[11], mcp->mb[12]);
1da177e4
LT		 2375
2376 if (cur_xchg_cnt)
2377 *cur_xchg_cnt = mcp->mb[3];
2378 if (orig_xchg_cnt)
2379 *orig_xchg_cnt = mcp->mb[6];
2380 if (cur_iocb_cnt)
2381 *cur_iocb_cnt = mcp->mb[7];
2382 if (orig_iocb_cnt)
2383 *orig_iocb_cnt = mcp->mb[10];
7b867cf7 2384 if (vha->hw->flags.npiv_supported && max_npiv_vports)
4d0ea247 2385 *max_npiv_vports = mcp->mb[11];
6246b8a1 2386 if ((IS_QLA81XX(vha->hw) || IS_QLA83XX(vha->hw)) && max_fcfs)
f3a0a77e 2387 *max_fcfs = mcp->mb[12];
1da177e4
LT		 2388 }
2389
2390 return (rval);
2391}
2392
1da177e4
LT		 2393/*
2394 * qla2x00_get_fcal_position_map
2395 * Get FCAL (LILP) position map using mailbox command
2396 *
2397 * Input:
2398 * ha = adapter state pointer.
2399 * pos_map = buffer pointer (can be NULL).
2400 *
2401 * Returns:
2402 * qla2x00 local function return status code.
2403 *
2404 * Context:
2405 * Kernel context.
2406 */
2407int
7b867cf7 2408qla2x00_get_fcal_position_map(scsi_qla_host_t *vha, char *pos_map)
1da177e4
LT		 2409{
2410 int rval;
2411 mbx_cmd_t mc;
2412 mbx_cmd_t *mcp = &mc;
2413 char *pmap;
2414 dma_addr_t pmap_dma;
7b867cf7 2415 struct qla_hw_data *ha = vha->hw;
1da177e4 2416
5f28d2d7
SK		 2417 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107f,
2418 "Entered %s.\n", __func__);
7c3df132 2419
4b89258c 2420 pmap = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pmap_dma);
1da177e4 2421 if (pmap == NULL) {
7c3df132
SK		 2422 ql_log(ql_log_warn, vha, 0x1080,
2423 "Memory alloc failed.\n");
1da177e4
LT		 2424 return QLA_MEMORY_ALLOC_FAILED;
2425 }
2426 memset(pmap, 0, FCAL_MAP_SIZE);
2427
2428 mcp->mb[0] = MBC_GET_FC_AL_POSITION_MAP;
2429 mcp->mb[2] = MSW(pmap_dma);
2430 mcp->mb[3] = LSW(pmap_dma);
2431 mcp->mb[6] = MSW(MSD(pmap_dma));
2432 mcp->mb[7] = LSW(MSD(pmap_dma));
2433 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
2434 mcp->in_mb = MBX_1|MBX_0;
2435 mcp->buf_size = FCAL_MAP_SIZE;
2436 mcp->flags = MBX_DMA_IN;
2437 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
7b867cf7 2438 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2439
2440 if (rval == QLA_SUCCESS) {
5f28d2d7 2441 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1081,
7c3df132
SK		 2442 "mb0/mb1=%x/%X FC/AL position map size (%x).\n",
2443 mcp->mb[0], mcp->mb[1], (unsigned)pmap[0]);
2444 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111d,
2445 pmap, pmap[0] + 1);
1da177e4
LT		 2446
2447 if (pos_map)
2448 memcpy(pos_map, pmap, FCAL_MAP_SIZE);
2449 }
2450 dma_pool_free(ha->s_dma_pool, pmap, pmap_dma);
2451
2452 if (rval != QLA_SUCCESS) {
7c3df132 2453 ql_dbg(ql_dbg_mbx, vha, 0x1082, "Failed=%x.\n", rval);
1da177e4 2454 } else {
5f28d2d7
SK		 2455 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1083,
2456 "Done %s.\n", __func__);
1da177e4
LT		 2457 }
2458
2459 return rval;
2460}
392e2f65
AV		 2461
2462/*
2463 * qla2x00_get_link_status
2464 *
2465 * Input:
2466 * ha = adapter block pointer.
2467 * loop_id = device loop ID.
2468 * ret_buf = pointer to link status return buffer.
2469 *
2470 * Returns:
2471 * 0 = success.
2472 * BIT_0 = mem alloc error.
2473 * BIT_1 = mailbox error.
2474 */
2475int
7b867cf7 2476qla2x00_get_link_status(scsi_qla_host_t *vha, uint16_t loop_id,
43ef0580 2477 struct link_statistics *stats, dma_addr_t stats_dma)
392e2f65
AV		 2478{
2479 int rval;
2480 mbx_cmd_t mc;
2481 mbx_cmd_t *mcp = &mc;
43ef0580 2482 uint32_t *siter, *diter, dwords;
7b867cf7 2483 struct qla_hw_data *ha = vha->hw;
392e2f65 2484
5f28d2d7
SK		 2485 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1084,
2486 "Entered %s.\n", __func__);
392e2f65 2487
392e2f65 2488 mcp->mb[0] = MBC_GET_LINK_STATUS;
43ef0580
AV		 2489 mcp->mb[2] = MSW(stats_dma);
2490 mcp->mb[3] = LSW(stats_dma);
2491 mcp->mb[6] = MSW(MSD(stats_dma));
2492 mcp->mb[7] = LSW(MSD(stats_dma));
392e2f65
AV		 2493 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
2494 mcp->in_mb = MBX_0;
e428924c 2495 if (IS_FWI2_CAPABLE(ha)) {
392e2f65
AV		 2496 mcp->mb[1] = loop_id;
2497 mcp->mb[4] = 0;
2498 mcp->mb[10] = 0;
2499 mcp->out_mb |= MBX_10|MBX_4|MBX_1;
2500 mcp->in_mb |= MBX_1;
2501 } else if (HAS_EXTENDED_IDS(ha)) {
2502 mcp->mb[1] = loop_id;
2503 mcp->mb[10] = 0;
2504 mcp->out_mb |= MBX_10|MBX_1;
2505 } else {
2506 mcp->mb[1] = loop_id << 8;
2507 mcp->out_mb |= MBX_1;
2508 }
b93480e3 2509 mcp->tov = MBX_TOV_SECONDS;
392e2f65 2510 mcp->flags = IOCTL_CMD;
7b867cf7 2511 rval = qla2x00_mailbox_command(vha, mcp);
392e2f65
AV		 2512
2513 if (rval == QLA_SUCCESS) {
2514 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
7c3df132
SK		 2515 ql_dbg(ql_dbg_mbx, vha, 0x1085,
2516 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
43ef0580 2517 rval = QLA_FUNCTION_FAILED;
392e2f65 2518 } else {
43ef0580 2519 /* Copy over data -- firmware data is LE. */
5f28d2d7
SK		 2520 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1086,
2521 "Done %s.\n", __func__);
43ef0580
AV		 2522 dwords = offsetof(struct link_statistics, unused1) / 4;
2523 siter = diter = &stats->link_fail_cnt;
2524 while (dwords--)
2525 *diter++ = le32_to_cpu(*siter++);
392e2f65
AV		 2526 }
2527 } else {
2528 /* Failed. */
7c3df132 2529 ql_dbg(ql_dbg_mbx, vha, 0x1087, "Failed=%x.\n", rval);
392e2f65
AV		 2530 }
2531
392e2f65
AV		 2532 return rval;
2533}
2534
2535int
7b867cf7 2536qla24xx_get_isp_stats(scsi_qla_host_t *vha, struct link_statistics *stats,
43ef0580 2537 dma_addr_t stats_dma)
1c7c6357
AV		 2538{
2539 int rval;
2540 mbx_cmd_t mc;
2541 mbx_cmd_t *mcp = &mc;
43ef0580 2542 uint32_t *siter, *diter, dwords;
1c7c6357 2543
5f28d2d7
SK		 2544 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1088,
2545 "Entered %s.\n", __func__);
1c7c6357 2546
1c7c6357 2547 mcp->mb[0] = MBC_GET_LINK_PRIV_STATS;
43ef0580
AV		 2548 mcp->mb[2] = MSW(stats_dma);
2549 mcp->mb[3] = LSW(stats_dma);
2550 mcp->mb[6] = MSW(MSD(stats_dma));
2551 mcp->mb[7] = LSW(MSD(stats_dma));
2552 mcp->mb[8] = sizeof(struct link_statistics) / 4;
7b867cf7 2553 mcp->mb[9] = vha->vp_idx;
1c7c6357 2554 mcp->mb[10] = 0;
43ef0580 2555 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
1c7c6357 2556 mcp->in_mb = MBX_2|MBX_1|MBX_0;
b93480e3 2557 mcp->tov = MBX_TOV_SECONDS;
1c7c6357 2558 mcp->flags = IOCTL_CMD;
7b867cf7 2559 rval = qla2x00_mailbox_command(vha, mcp);
1c7c6357
AV		 2560
2561 if (rval == QLA_SUCCESS) {
2562 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
7c3df132
SK		 2563 ql_dbg(ql_dbg_mbx, vha, 0x1089,
2564 "Failed mb[0]=%x.\n", mcp->mb[0]);
43ef0580 2565 rval = QLA_FUNCTION_FAILED;
1c7c6357 2566 } else {
5f28d2d7
SK		 2567 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108a,
2568 "Done %s.\n", __func__);
1c7c6357 2569 /* Copy over data -- firmware data is LE. */
43ef0580
AV		 2570 dwords = sizeof(struct link_statistics) / 4;
2571 siter = diter = &stats->link_fail_cnt;
1c7c6357 2572 while (dwords--)
43ef0580 2573 *diter++ = le32_to_cpu(*siter++);
1c7c6357
AV		 2574 }
2575 } else {
2576 /* Failed. */
7c3df132 2577 ql_dbg(ql_dbg_mbx, vha, 0x108b, "Failed=%x.\n", rval);
1c7c6357
AV		 2578 }
2579
1c7c6357
AV		 2580 return rval;
2581}
1c7c6357
AV		 2582
2583int
2afa19a9 2584qla24xx_abort_command(srb_t *sp)
1c7c6357
AV		 2585{
2586 int rval;
1c7c6357
AV		 2587 unsigned long flags = 0;
2588
2589 struct abort_entry_24xx *abt;
2590 dma_addr_t abt_dma;
2591 uint32_t handle;
2afa19a9
AC		 2592 fc_port_t *fcport = sp->fcport;
2593 struct scsi_qla_host *vha = fcport->vha;
7b867cf7 2594 struct qla_hw_data *ha = vha->hw;
67c2e93a 2595 struct req_que *req = vha->req;
1c7c6357 2596
5f28d2d7
SK		 2597 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108c,
2598 "Entered %s.\n", __func__);
1c7c6357 2599
4440e46d
AB		 2600 if (ql2xasynctmfenable)
2601 return qla24xx_async_abort_command(sp);
2602
7b867cf7 2603 spin_lock_irqsave(&ha->hardware_lock, flags);
8d93f550 2604 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
7b867cf7 2605 if (req->outstanding_cmds[handle] == sp)
1c7c6357
AV		 2606 break;
2607 }
7b867cf7 2608 spin_unlock_irqrestore(&ha->hardware_lock, flags);
8d93f550 2609 if (handle == req->num_outstanding_cmds) {
1c7c6357
AV		 2610 /* Command not found. */
2611 return QLA_FUNCTION_FAILED;
2612 }
2613
2614 abt = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &abt_dma);
2615 if (abt == NULL) {
7c3df132
SK		 2616 ql_log(ql_log_warn, vha, 0x108d,
2617 "Failed to allocate abort IOCB.\n");
1c7c6357
AV		 2618 return QLA_MEMORY_ALLOC_FAILED;
2619 }
2620 memset(abt, 0, sizeof(struct abort_entry_24xx));
2621
2622 abt->entry_type = ABORT_IOCB_TYPE;
2623 abt->entry_count = 1;
2afa19a9 2624 abt->handle = MAKE_HANDLE(req->id, abt->handle);
1c7c6357 2625 abt->nport_handle = cpu_to_le16(fcport->loop_id);
a74ec14f 2626 abt->handle_to_abort = MAKE_HANDLE(req->id, handle);
1c7c6357
AV		 2627 abt->port_id[0] = fcport->d_id.b.al_pa;
2628 abt->port_id[1] = fcport->d_id.b.area;
2629 abt->port_id[2] = fcport->d_id.b.domain;
c6d39e23 2630 abt->vp_index = fcport->vha->vp_idx;
73208dfd
AC		 2631
2632 abt->req_que_no = cpu_to_le16(req->id);
2633
7b867cf7 2634 rval = qla2x00_issue_iocb(vha, abt, abt_dma, 0);
1c7c6357 2635 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2636 ql_dbg(ql_dbg_mbx, vha, 0x108e,
2637 "Failed to issue IOCB (%x).\n", rval);
1c7c6357 2638 } else if (abt->entry_status != 0) {
7c3df132
SK		 2639 ql_dbg(ql_dbg_mbx, vha, 0x108f,
2640 "Failed to complete IOCB -- error status (%x).\n",
2641 abt->entry_status);
1c7c6357
AV		 2642 rval = QLA_FUNCTION_FAILED;
2643 } else if (abt->nport_handle != __constant_cpu_to_le16(0)) {
7c3df132
SK		 2644 ql_dbg(ql_dbg_mbx, vha, 0x1090,
2645 "Failed to complete IOCB -- completion status (%x).\n",
2646 le16_to_cpu(abt->nport_handle));
f934c9d0
CD		 2647 if (abt->nport_handle == CS_IOCB_ERROR)
2648 rval = QLA_FUNCTION_PARAMETER_ERROR;
2649 else
2650 rval = QLA_FUNCTION_FAILED;
1c7c6357 2651 } else {
5f28d2d7
SK		 2652 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1091,
2653 "Done %s.\n", __func__);
1c7c6357
AV		 2654 }
2655
2656 dma_pool_free(ha->s_dma_pool, abt, abt_dma);
2657
2658 return rval;
2659}
2660
2661struct tsk_mgmt_cmd {
2662 union {
2663 struct tsk_mgmt_entry tsk;
2664 struct sts_entry_24xx sts;
2665 } p;
2666};
2667
523ec773
AV		 2668static int
2669__qla24xx_issue_tmf(char *name, uint32_t type, struct fc_port *fcport,
2afa19a9 2670 unsigned int l, int tag)
1c7c6357 2671{
523ec773 2672 int rval, rval2;
1c7c6357 2673 struct tsk_mgmt_cmd *tsk;
9ca1d01f 2674 struct sts_entry_24xx *sts;
1c7c6357 2675 dma_addr_t tsk_dma;
7b867cf7
AC		 2676 scsi_qla_host_t *vha;
2677 struct qla_hw_data *ha;
73208dfd
AC		 2678 struct req_que *req;
2679 struct rsp_que *rsp;
1c7c6357 2680
7b867cf7
AC		 2681 vha = fcport->vha;
2682 ha = vha->hw;
2afa19a9 2683 req = vha->req;
7c3df132 2684
5f28d2d7
SK		 2685 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1092,
2686 "Entered %s.\n", __func__);
7c3df132 2687
7163ea81 2688 if (ha->flags.cpu_affinity_enabled)
68ca949c
AC		 2689 rsp = ha->rsp_q_map[tag + 1];
2690 else
2691 rsp = req->rsp;
7b867cf7 2692 tsk = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &tsk_dma);
1c7c6357 2693 if (tsk == NULL) {
7c3df132
SK		 2694 ql_log(ql_log_warn, vha, 0x1093,
2695 "Failed to allocate task management IOCB.\n");
1c7c6357
AV		 2696 return QLA_MEMORY_ALLOC_FAILED;
2697 }
2698 memset(tsk, 0, sizeof(struct tsk_mgmt_cmd));
2699
2700 tsk->p.tsk.entry_type = TSK_MGMT_IOCB_TYPE;
2701 tsk->p.tsk.entry_count = 1;
2afa19a9 2702 tsk->p.tsk.handle = MAKE_HANDLE(req->id, tsk->p.tsk.handle);
1c7c6357 2703 tsk->p.tsk.nport_handle = cpu_to_le16(fcport->loop_id);
00a537b8 2704 tsk->p.tsk.timeout = cpu_to_le16(ha->r_a_tov / 10 * 2);
523ec773 2705 tsk->p.tsk.control_flags = cpu_to_le32(type);
1c7c6357
AV		 2706 tsk->p.tsk.port_id[0] = fcport->d_id.b.al_pa;
2707 tsk->p.tsk.port_id[1] = fcport->d_id.b.area;
2708 tsk->p.tsk.port_id[2] = fcport->d_id.b.domain;
c6d39e23 2709 tsk->p.tsk.vp_index = fcport->vha->vp_idx;
523ec773
AV		 2710 if (type == TCF_LUN_RESET) {
2711 int_to_scsilun(l, &tsk->p.tsk.lun);
2712 host_to_fcp_swap((uint8_t *)&tsk->p.tsk.lun,
2713 sizeof(tsk->p.tsk.lun));
2714 }
2c3dfe3f 2715
9ca1d01f 2716 sts = &tsk->p.sts;
7b867cf7 2717 rval = qla2x00_issue_iocb(vha, tsk, tsk_dma, 0);
1c7c6357 2718 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2719 ql_dbg(ql_dbg_mbx, vha, 0x1094,
2720 "Failed to issue %s reset IOCB (%x).\n", name, rval);
9ca1d01f 2721 } else if (sts->entry_status != 0) {
7c3df132
SK		 2722 ql_dbg(ql_dbg_mbx, vha, 0x1095,
2723 "Failed to complete IOCB -- error status (%x).\n",
2724 sts->entry_status);
1c7c6357 2725 rval = QLA_FUNCTION_FAILED;
9ca1d01f 2726 } else if (sts->comp_status !=
1c7c6357 2727 __constant_cpu_to_le16(CS_COMPLETE)) {
7c3df132
SK		 2728 ql_dbg(ql_dbg_mbx, vha, 0x1096,
2729 "Failed to complete IOCB -- completion status (%x).\n",
2730 le16_to_cpu(sts->comp_status));
9ca1d01f 2731 rval = QLA_FUNCTION_FAILED;
97dec564
AV		 2732 } else if (le16_to_cpu(sts->scsi_status) &
2733 SS_RESPONSE_INFO_LEN_VALID) {
2734 if (le32_to_cpu(sts->rsp_data_len) < 4) {
5f28d2d7 2735 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1097,
7c3df132
SK		 2736 "Ignoring inconsistent data length -- not enough "
2737 "response info (%d).\n",
2738 le32_to_cpu(sts->rsp_data_len));
97dec564 2739 } else if (sts->data[3]) {
7c3df132
SK		 2740 ql_dbg(ql_dbg_mbx, vha, 0x1098,
2741 "Failed to complete IOCB -- response (%x).\n",
2742 sts->data[3]);
97dec564
AV		 2743 rval = QLA_FUNCTION_FAILED;
2744 }
1c7c6357
AV		 2745 }
2746
2747 /* Issue marker IOCB. */
73208dfd 2748 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l,
523ec773
AV		 2749 type == TCF_LUN_RESET ? MK_SYNC_ID_LUN: MK_SYNC_ID);
2750 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 2751 ql_dbg(ql_dbg_mbx, vha, 0x1099,
2752 "Failed to issue marker IOCB (%x).\n", rval2);
1c7c6357 2753 } else {
5f28d2d7
SK		 2754 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109a,
2755 "Done %s.\n", __func__);
1c7c6357
AV		 2756 }
2757
7b867cf7 2758 dma_pool_free(ha->s_dma_pool, tsk, tsk_dma);
1c7c6357
AV		 2759
2760 return rval;
2761}
2762
523ec773 2763int
2afa19a9 2764qla24xx_abort_target(struct fc_port *fcport, unsigned int l, int tag)
523ec773 2765{
3822263e
MI		 2766 struct qla_hw_data *ha = fcport->vha->hw;
2767
2768 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
2769 return qla2x00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag);
2770
2afa19a9 2771 return __qla24xx_issue_tmf("Target", TCF_TARGET_RESET, fcport, l, tag);
523ec773
AV		 2772}
2773
2774int
2afa19a9 2775qla24xx_lun_reset(struct fc_port *fcport, unsigned int l, int tag)
523ec773 2776{
3822263e
MI		 2777 struct qla_hw_data *ha = fcport->vha->hw;
2778
2779 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
2780 return qla2x00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag);
2781
2afa19a9 2782 return __qla24xx_issue_tmf("Lun", TCF_LUN_RESET, fcport, l, tag);
523ec773
AV		 2783}
2784
1c7c6357 2785int
7b867cf7 2786qla2x00_system_error(scsi_qla_host_t *vha)
1c7c6357
AV		 2787{
2788 int rval;
2789 mbx_cmd_t mc;
2790 mbx_cmd_t *mcp = &mc;
7b867cf7 2791 struct qla_hw_data *ha = vha->hw;
1c7c6357 2792
68af0811 2793 if (!IS_QLA23XX(ha) && !IS_FWI2_CAPABLE(ha))
1c7c6357
AV		 2794 return QLA_FUNCTION_FAILED;
2795
5f28d2d7
SK		 2796 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109b,
2797 "Entered %s.\n", __func__);
1c7c6357
AV		 2798
2799 mcp->mb[0] = MBC_GEN_SYSTEM_ERROR;
2800 mcp->out_mb = MBX_0;
2801 mcp->in_mb = MBX_0;
2802 mcp->tov = 5;
2803 mcp->flags = 0;
7b867cf7 2804 rval = qla2x00_mailbox_command(vha, mcp);
1c7c6357
AV		 2805
2806 if (rval != QLA_SUCCESS) {
7c3df132 2807 ql_dbg(ql_dbg_mbx, vha, 0x109c, "Failed=%x.\n", rval);
1c7c6357 2808 } else {
5f28d2d7
SK		 2809 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109d,
2810 "Done %s.\n", __func__);
1c7c6357
AV		 2811 }
2812
2813 return rval;
2814}
2815
db64e930
JC		 2816int
2817qla2x00_write_serdes_word(scsi_qla_host_t *vha, uint16_t addr, uint16_t data)
2818{
2819 int rval;
2820 mbx_cmd_t mc;
2821 mbx_cmd_t *mcp = &mc;
2822
2823 if (!IS_QLA2031(vha->hw))
2824 return QLA_FUNCTION_FAILED;
2825
2826 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1182,
2827 "Entered %s.\n", __func__);
2828
2829 mcp->mb[0] = MBC_WRITE_SERDES;
2830 mcp->mb[1] = addr;
2831 mcp->mb[2] = data & 0xff;
2832 mcp->mb[3] = 0;
2833 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
2834 mcp->in_mb = MBX_0;
2835 mcp->tov = MBX_TOV_SECONDS;
2836 mcp->flags = 0;
2837 rval = qla2x00_mailbox_command(vha, mcp);
2838
2839 if (rval != QLA_SUCCESS) {
2840 ql_dbg(ql_dbg_mbx, vha, 0x1183,
2841 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
2842 } else {
2843 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1184,
2844 "Done %s.\n", __func__);
2845 }
2846
2847 return rval;
2848}
2849
2850int
2851qla2x00_read_serdes_word(scsi_qla_host_t *vha, uint16_t addr, uint16_t *data)
2852{
2853 int rval;
2854 mbx_cmd_t mc;
2855 mbx_cmd_t *mcp = &mc;
2856
2857 if (!IS_QLA2031(vha->hw))
2858 return QLA_FUNCTION_FAILED;
2859
2860 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1185,
2861 "Entered %s.\n", __func__);
2862
2863 mcp->mb[0] = MBC_READ_SERDES;
2864 mcp->mb[1] = addr;
2865 mcp->mb[3] = 0;
2866 mcp->out_mb = MBX_3|MBX_1|MBX_0;
2867 mcp->in_mb = MBX_1|MBX_0;
2868 mcp->tov = MBX_TOV_SECONDS;
2869 mcp->flags = 0;
2870 rval = qla2x00_mailbox_command(vha, mcp);
2871
2872 *data = mcp->mb[1] & 0xff;
2873
2874 if (rval != QLA_SUCCESS) {
2875 ql_dbg(ql_dbg_mbx, vha, 0x1186,
2876 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
2877 } else {
2878 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1187,
2879 "Done %s.\n", __func__);
2880 }
2881
2882 return rval;
2883}
2884
e8887c51
JC		 2885int
2886qla8044_write_serdes_word(scsi_qla_host_t *vha, uint32_t addr, uint32_t data)
2887{
2888 int rval;
2889 mbx_cmd_t mc;
2890 mbx_cmd_t *mcp = &mc;
2891
2892 if (!IS_QLA8044(vha->hw))
2893 return QLA_FUNCTION_FAILED;
2894
2895 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1186,
2896 "Entered %s.\n", __func__);
2897
2898 mcp->mb[0] = MBC_SET_GET_ETH_SERDES_REG;
2899 mcp->mb[1] = HCS_WRITE_SERDES;
2900 mcp->mb[3] = LSW(addr);
2901 mcp->mb[4] = MSW(addr);
2902 mcp->mb[5] = LSW(data);
2903 mcp->mb[6] = MSW(data);
2904 mcp->out_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_1|MBX_0;
2905 mcp->in_mb = MBX_0;
2906 mcp->tov = MBX_TOV_SECONDS;
2907 mcp->flags = 0;
2908 rval = qla2x00_mailbox_command(vha, mcp);
2909
2910 if (rval != QLA_SUCCESS) {
2911 ql_dbg(ql_dbg_mbx, vha, 0x1187,
2912 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
2913 } else {
2914 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1188,
2915 "Done %s.\n", __func__);
2916 }
2917
2918 return rval;
2919}
2920
2921int
2922qla8044_read_serdes_word(scsi_qla_host_t *vha, uint32_t addr, uint32_t *data)
2923{
2924 int rval;
2925 mbx_cmd_t mc;
2926 mbx_cmd_t *mcp = &mc;
2927
2928 if (!IS_QLA8044(vha->hw))
2929 return QLA_FUNCTION_FAILED;
2930
2931 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1189,
2932 "Entered %s.\n", __func__);
2933
2934 mcp->mb[0] = MBC_SET_GET_ETH_SERDES_REG;
2935 mcp->mb[1] = HCS_READ_SERDES;
2936 mcp->mb[3] = LSW(addr);
2937 mcp->mb[4] = MSW(addr);
2938 mcp->out_mb = MBX_4|MBX_3|MBX_1|MBX_0;
2939 mcp->in_mb = MBX_2|MBX_1|MBX_0;
2940 mcp->tov = MBX_TOV_SECONDS;
2941 mcp->flags = 0;
2942 rval = qla2x00_mailbox_command(vha, mcp);
2943
2944 *data = mcp->mb[2] << 16 | mcp->mb[1];
2945
2946 if (rval != QLA_SUCCESS) {
2947 ql_dbg(ql_dbg_mbx, vha, 0x118a,
2948 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
2949 } else {
2950 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118b,
2951 "Done %s.\n", __func__);
2952 }
2953
2954 return rval;
2955}
2956
1c7c6357
AV		 2957/**
2958 * qla2x00_set_serdes_params() -
2959 * @ha: HA context
2960 *
2961 * Returns
2962 */
2963int
7b867cf7 2964qla2x00_set_serdes_params(scsi_qla_host_t *vha, uint16_t sw_em_1g,
1c7c6357
AV		 2965 uint16_t sw_em_2g, uint16_t sw_em_4g)
2966{
2967 int rval;
2968 mbx_cmd_t mc;
2969 mbx_cmd_t *mcp = &mc;
2970
5f28d2d7
SK		 2971 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109e,
2972 "Entered %s.\n", __func__);
1c7c6357
AV		 2973
2974 mcp->mb[0] = MBC_SERDES_PARAMS;
2975 mcp->mb[1] = BIT_0;
fdbc6833
AV		 2976 mcp->mb[2] = sw_em_1g | BIT_15;
2977 mcp->mb[3] = sw_em_2g | BIT_15;
2978 mcp->mb[4] = sw_em_4g | BIT_15;
1c7c6357
AV		 2979 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
2980 mcp->in_mb = MBX_0;
b93480e3 2981 mcp->tov = MBX_TOV_SECONDS;
1c7c6357 2982 mcp->flags = 0;
7b867cf7 2983 rval = qla2x00_mailbox_command(vha, mcp);
1c7c6357
AV		 2984
2985 if (rval != QLA_SUCCESS) {
2986 /*EMPTY*/
7c3df132
SK		 2987 ql_dbg(ql_dbg_mbx, vha, 0x109f,
2988 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
1c7c6357
AV		 2989 } else {
2990 /*EMPTY*/
5f28d2d7
SK		 2991 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a0,
2992 "Done %s.\n", __func__);
1c7c6357
AV		 2993 }
2994
2995 return rval;
2996}
f6ef3b18
AV		 2997
2998int
7b867cf7 2999qla2x00_stop_firmware(scsi_qla_host_t *vha)
f6ef3b18
AV		 3000{
3001 int rval;
3002 mbx_cmd_t mc;
3003 mbx_cmd_t *mcp = &mc;
3004
7b867cf7 3005 if (!IS_FWI2_CAPABLE(vha->hw))
f6ef3b18
AV		 3006 return QLA_FUNCTION_FAILED;
3007
5f28d2d7
SK		 3008 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a1,
3009 "Entered %s.\n", __func__);
f6ef3b18
AV		 3010
3011 mcp->mb[0] = MBC_STOP_FIRMWARE;
4ba988db
AV		 3012 mcp->mb[1] = 0;
3013 mcp->out_mb = MBX_1|MBX_0;
f6ef3b18
AV		 3014 mcp->in_mb = MBX_0;
3015 mcp->tov = 5;
3016 mcp->flags = 0;
7b867cf7 3017 rval = qla2x00_mailbox_command(vha, mcp);
f6ef3b18
AV		 3018
3019 if (rval != QLA_SUCCESS) {
7c3df132 3020 ql_dbg(ql_dbg_mbx, vha, 0x10a2, "Failed=%x.\n", rval);
b469a7cb
AV		 3021 if (mcp->mb[0] == MBS_INVALID_COMMAND)
3022 rval = QLA_INVALID_COMMAND;
f6ef3b18 3023 } else {
5f28d2d7
SK		 3024 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a3,
3025 "Done %s.\n", __func__);
f6ef3b18
AV		 3026 }
3027
3028 return rval;
3029}
a7a167bf
AV		 3030
3031int
7b867cf7 3032qla2x00_enable_eft_trace(scsi_qla_host_t *vha, dma_addr_t eft_dma,
a7a167bf
AV		 3033 uint16_t buffers)
3034{
3035 int rval;
3036 mbx_cmd_t mc;
3037 mbx_cmd_t *mcp = &mc;
3038
5f28d2d7
SK		 3039 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a4,
3040 "Entered %s.\n", __func__);
7c3df132 3041
7b867cf7 3042 if (!IS_FWI2_CAPABLE(vha->hw))
a7a167bf
AV		 3043 return QLA_FUNCTION_FAILED;
3044
85880801
AV		 3045 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3046 return QLA_FUNCTION_FAILED;
3047
a7a167bf 3048 mcp->mb[0] = MBC_TRACE_CONTROL;
00b6bd25
AV		 3049 mcp->mb[1] = TC_EFT_ENABLE;
3050 mcp->mb[2] = LSW(eft_dma);
3051 mcp->mb[3] = MSW(eft_dma);
3052 mcp->mb[4] = LSW(MSD(eft_dma));
3053 mcp->mb[5] = MSW(MSD(eft_dma));
3054 mcp->mb[6] = buffers;
3055 mcp->mb[7] = TC_AEN_DISABLE;
3056 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
a7a167bf 3057 mcp->in_mb = MBX_1|MBX_0;
b93480e3 3058 mcp->tov = MBX_TOV_SECONDS;
a7a167bf 3059 mcp->flags = 0;
7b867cf7 3060 rval = qla2x00_mailbox_command(vha, mcp);
00b6bd25 3061 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3062 ql_dbg(ql_dbg_mbx, vha, 0x10a5,
3063 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3064 rval, mcp->mb[0], mcp->mb[1]);
00b6bd25 3065 } else {
5f28d2d7
SK		 3066 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a6,
3067 "Done %s.\n", __func__);
00b6bd25
AV		 3068 }
3069
3070 return rval;
3071}
a7a167bf 3072
00b6bd25 3073int
7b867cf7 3074qla2x00_disable_eft_trace(scsi_qla_host_t *vha)
00b6bd25
AV		 3075{
3076 int rval;
3077 mbx_cmd_t mc;
3078 mbx_cmd_t *mcp = &mc;
3079
5f28d2d7
SK		 3080 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a7,
3081 "Entered %s.\n", __func__);
7c3df132 3082
7b867cf7 3083 if (!IS_FWI2_CAPABLE(vha->hw))
00b6bd25
AV		 3084 return QLA_FUNCTION_FAILED;
3085
85880801
AV		 3086 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3087 return QLA_FUNCTION_FAILED;
3088
00b6bd25
AV		 3089 mcp->mb[0] = MBC_TRACE_CONTROL;
3090 mcp->mb[1] = TC_EFT_DISABLE;
3091 mcp->out_mb = MBX_1|MBX_0;
3092 mcp->in_mb = MBX_1|MBX_0;
b93480e3 3093 mcp->tov = MBX_TOV_SECONDS;
00b6bd25 3094 mcp->flags = 0;
7b867cf7 3095 rval = qla2x00_mailbox_command(vha, mcp);
a7a167bf 3096 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3097 ql_dbg(ql_dbg_mbx, vha, 0x10a8,
3098 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3099 rval, mcp->mb[0], mcp->mb[1]);
a7a167bf 3100 } else {
5f28d2d7
SK		 3101 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a9,
3102 "Done %s.\n", __func__);
a7a167bf
AV		 3103 }
3104
3105 return rval;
3106}
3107
df613b96 3108int
7b867cf7 3109qla2x00_enable_fce_trace(scsi_qla_host_t *vha, dma_addr_t fce_dma,
df613b96
AV		 3110 uint16_t buffers, uint16_t *mb, uint32_t *dwords)
3111{
3112 int rval;
3113 mbx_cmd_t mc;
3114 mbx_cmd_t *mcp = &mc;
3115
5f28d2d7
SK		 3116 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10aa,
3117 "Entered %s.\n", __func__);
7c3df132 3118
6246b8a1 3119 if (!IS_QLA25XX(vha->hw) && !IS_QLA81XX(vha->hw) &&
f73cb695 3120 !IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw))
df613b96
AV		 3121 return QLA_FUNCTION_FAILED;
3122
85880801
AV		 3123 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3124 return QLA_FUNCTION_FAILED;
3125
df613b96
AV		 3126 mcp->mb[0] = MBC_TRACE_CONTROL;
3127 mcp->mb[1] = TC_FCE_ENABLE;
3128 mcp->mb[2] = LSW(fce_dma);
3129 mcp->mb[3] = MSW(fce_dma);
3130 mcp->mb[4] = LSW(MSD(fce_dma));
3131 mcp->mb[5] = MSW(MSD(fce_dma));
3132 mcp->mb[6] = buffers;
3133 mcp->mb[7] = TC_AEN_DISABLE;
3134 mcp->mb[8] = 0;
3135 mcp->mb[9] = TC_FCE_DEFAULT_RX_SIZE;
3136 mcp->mb[10] = TC_FCE_DEFAULT_TX_SIZE;
3137 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
3138 MBX_1|MBX_0;
3139 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
b93480e3 3140 mcp->tov = MBX_TOV_SECONDS;
df613b96 3141 mcp->flags = 0;
7b867cf7 3142 rval = qla2x00_mailbox_command(vha, mcp);
df613b96 3143 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3144 ql_dbg(ql_dbg_mbx, vha, 0x10ab,
3145 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3146 rval, mcp->mb[0], mcp->mb[1]);
df613b96 3147 } else {
5f28d2d7
SK		 3148 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ac,
3149 "Done %s.\n", __func__);
df613b96
AV		 3150
3151 if (mb)
3152 memcpy(mb, mcp->mb, 8 * sizeof(*mb));
3153 if (dwords)
fa0926df 3154 *dwords = buffers;
df613b96
AV		 3155 }
3156
3157 return rval;
3158}
3159
3160int
7b867cf7 3161qla2x00_disable_fce_trace(scsi_qla_host_t *vha, uint64_t *wr, uint64_t *rd)
df613b96
AV		 3162{
3163 int rval;
3164 mbx_cmd_t mc;
3165 mbx_cmd_t *mcp = &mc;
3166
5f28d2d7
SK		 3167 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ad,
3168 "Entered %s.\n", __func__);
7c3df132 3169
7b867cf7 3170 if (!IS_FWI2_CAPABLE(vha->hw))
df613b96
AV		 3171 return QLA_FUNCTION_FAILED;
3172
85880801
AV		 3173 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3174 return QLA_FUNCTION_FAILED;
3175
df613b96
AV		 3176 mcp->mb[0] = MBC_TRACE_CONTROL;
3177 mcp->mb[1] = TC_FCE_DISABLE;
3178 mcp->mb[2] = TC_FCE_DISABLE_TRACE;
3179 mcp->out_mb = MBX_2|MBX_1|MBX_0;
3180 mcp->in_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
3181 MBX_1|MBX_0;
b93480e3 3182 mcp->tov = MBX_TOV_SECONDS;
df613b96 3183 mcp->flags = 0;
7b867cf7 3184 rval = qla2x00_mailbox_command(vha, mcp);
df613b96 3185 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3186 ql_dbg(ql_dbg_mbx, vha, 0x10ae,
3187 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3188 rval, mcp->mb[0], mcp->mb[1]);
df613b96 3189 } else {
5f28d2d7
SK		 3190 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10af,
3191 "Done %s.\n", __func__);
df613b96
AV		 3192
3193 if (wr)
3194 *wr = (uint64_t) mcp->mb[5] << 48 |
3195 (uint64_t) mcp->mb[4] << 32 |
3196 (uint64_t) mcp->mb[3] << 16 |
3197 (uint64_t) mcp->mb[2];
3198 if (rd)
3199 *rd = (uint64_t) mcp->mb[9] << 48 |
3200 (uint64_t) mcp->mb[8] << 32 |
3201 (uint64_t) mcp->mb[7] << 16 |
3202 (uint64_t) mcp->mb[6];
3203 }
3204
3205 return rval;
3206}
3207
6e98016c
GM		 3208int
3209qla2x00_get_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
3210 uint16_t *port_speed, uint16_t *mb)
3211{
3212 int rval;
3213 mbx_cmd_t mc;
3214 mbx_cmd_t *mcp = &mc;
3215
5f28d2d7
SK		 3216 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b0,
3217 "Entered %s.\n", __func__);
7c3df132 3218
6e98016c
GM		 3219 if (!IS_IIDMA_CAPABLE(vha->hw))
3220 return QLA_FUNCTION_FAILED;
3221
6e98016c
GM		 3222 mcp->mb[0] = MBC_PORT_PARAMS;
3223 mcp->mb[1] = loop_id;
3224 mcp->mb[2] = mcp->mb[3] = 0;
3225 mcp->mb[9] = vha->vp_idx;
3226 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
3227 mcp->in_mb = MBX_3|MBX_1|MBX_0;
3228 mcp->tov = MBX_TOV_SECONDS;
3229 mcp->flags = 0;
3230 rval = qla2x00_mailbox_command(vha, mcp);
3231
3232 /* Return mailbox statuses. */
3233 if (mb != NULL) {
3234 mb[0] = mcp->mb[0];
3235 mb[1] = mcp->mb[1];
3236 mb[3] = mcp->mb[3];
3237 }
3238
3239 if (rval != QLA_SUCCESS) {
7c3df132 3240 ql_dbg(ql_dbg_mbx, vha, 0x10b1, "Failed=%x.\n", rval);
6e98016c 3241 } else {
5f28d2d7
SK		 3242 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b2,
3243 "Done %s.\n", __func__);
6e98016c
GM		 3244 if (port_speed)
3245 *port_speed = mcp->mb[3];
3246 }
3247
3248 return rval;
3249}
3250
d8b45213 3251int
7b867cf7 3252qla2x00_set_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
d8b45213
AV		 3253 uint16_t port_speed, uint16_t *mb)
3254{
3255 int rval;
3256 mbx_cmd_t mc;
3257 mbx_cmd_t *mcp = &mc;
3258
5f28d2d7
SK		 3259 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b3,
3260 "Entered %s.\n", __func__);
7c3df132 3261
7b867cf7 3262 if (!IS_IIDMA_CAPABLE(vha->hw))
d8b45213
AV		 3263 return QLA_FUNCTION_FAILED;
3264
d8b45213
AV		 3265 mcp->mb[0] = MBC_PORT_PARAMS;
3266 mcp->mb[1] = loop_id;
3267 mcp->mb[2] = BIT_0;
6246b8a1 3268 if (IS_CNA_CAPABLE(vha->hw))
1bb39548
HZ		 3269 mcp->mb[3] = port_speed & (BIT_5|BIT_4|BIT_3|BIT_2|BIT_1|BIT_0);
3270 else
3271 mcp->mb[3] = port_speed & (BIT_2|BIT_1|BIT_0);
3272 mcp->mb[9] = vha->vp_idx;
3273 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
3274 mcp->in_mb = MBX_3|MBX_1|MBX_0;
b93480e3 3275 mcp->tov = MBX_TOV_SECONDS;
d8b45213 3276 mcp->flags = 0;
7b867cf7 3277 rval = qla2x00_mailbox_command(vha, mcp);
d8b45213
AV		 3278
3279 /* Return mailbox statuses. */
3280 if (mb != NULL) {
3281 mb[0] = mcp->mb[0];
3282 mb[1] = mcp->mb[1];
3283 mb[3] = mcp->mb[3];
d8b45213
AV		 3284 }
3285
3286 if (rval != QLA_SUCCESS) {
5f28d2d7
SK		 3287 ql_dbg(ql_dbg_mbx, vha, 0x10b4,
3288 "Failed=%x.\n", rval);
d8b45213 3289 } else {
5f28d2d7
SK		 3290 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b5,
3291 "Done %s.\n", __func__);
d8b45213
AV		 3292 }
3293
3294 return rval;
3295}
2c3dfe3f 3296
2c3dfe3f 3297void
7b867cf7 3298qla24xx_report_id_acquisition(scsi_qla_host_t *vha,
2c3dfe3f
SJ		 3299 struct vp_rpt_id_entry_24xx *rptid_entry)
3300{
3301 uint8_t vp_idx;
c6852c4c 3302 uint16_t stat = le16_to_cpu(rptid_entry->vp_idx);
7b867cf7
AC		 3303 struct qla_hw_data *ha = vha->hw;
3304 scsi_qla_host_t *vp;
feafb7b1 3305 unsigned long flags;
4ac8d4ca 3306 int found;
2c3dfe3f 3307
5f28d2d7
SK		 3308 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b6,
3309 "Entered %s.\n", __func__);
7c3df132 3310
2c3dfe3f
SJ		 3311 if (rptid_entry->entry_status != 0)
3312 return;
2c3dfe3f
SJ		 3313
3314 if (rptid_entry->format == 0) {
5f28d2d7 3315 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b7,
7c3df132
SK		 3316 "Format 0 : Number of VPs setup %d, number of "
3317 "VPs acquired %d.\n",
3318 MSB(le16_to_cpu(rptid_entry->vp_count)),
3319 LSB(le16_to_cpu(rptid_entry->vp_count)));
5f28d2d7 3320 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b8,
7c3df132
SK		 3321 "Primary port id %02x%02x%02x.\n",
3322 rptid_entry->port_id[2], rptid_entry->port_id[1],
3323 rptid_entry->port_id[0]);
2c3dfe3f 3324 } else if (rptid_entry->format == 1) {
c6852c4c 3325 vp_idx = LSB(stat);
5f28d2d7 3326 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b9,
7c3df132
SK		 3327 "Format 1: VP[%d] enabled - status %d - with "
3328 "port id %02x%02x%02x.\n", vp_idx, MSB(stat),
2c3dfe3f 3329 rptid_entry->port_id[2], rptid_entry->port_id[1],
7c3df132 3330 rptid_entry->port_id[0]);
531a82d1
AV		 3331
3332 vp = vha;
3333 if (vp_idx == 0 && (MSB(stat) != 1))
3334 goto reg_needed;
2c3dfe3f 3335
681e014b 3336 if (MSB(stat) != 0 && MSB(stat) != 2) {
7c3df132
SK		 3337 ql_dbg(ql_dbg_mbx, vha, 0x10ba,
3338 "Could not acquire ID for VP[%d].\n", vp_idx);
2c3dfe3f 3339 return;
81eb9b49 3340 }
2c3dfe3f 3341
4ac8d4ca 3342 found = 0;
feafb7b1 3343 spin_lock_irqsave(&ha->vport_slock, flags);
4ac8d4ca
AV		 3344 list_for_each_entry(vp, &ha->vp_list, list) {
3345 if (vp_idx == vp->vp_idx) {
3346 found = 1;
2c3dfe3f 3347 break;
4ac8d4ca
AV		 3348 }
3349 }
feafb7b1
AE		 3350 spin_unlock_irqrestore(&ha->vport_slock, flags);
3351
4ac8d4ca 3352 if (!found)
2c3dfe3f
SJ		 3353 return;
3354
7b867cf7
AC		 3355 vp->d_id.b.domain = rptid_entry->port_id[2];
3356 vp->d_id.b.area = rptid_entry->port_id[1];
3357 vp->d_id.b.al_pa = rptid_entry->port_id[0];
2c3dfe3f
SJ		 3358
3359 /*
3360 * Cannot configure here as we are still sitting on the
3361 * response queue. Handle it in dpc context.
3362 */
7b867cf7 3363 set_bit(VP_IDX_ACQUIRED, &vp->vp_flags);
2c3dfe3f 3364
531a82d1
AV		 3365reg_needed:
3366 set_bit(REGISTER_FC4_NEEDED, &vp->dpc_flags);
3367 set_bit(REGISTER_FDMI_NEEDED, &vp->dpc_flags);
3368 set_bit(VP_DPC_NEEDED, &vha->dpc_flags);
7b867cf7 3369 qla2xxx_wake_dpc(vha);
2c3dfe3f
SJ		 3370 }
3371}
3372
3373/*
3374 * qla24xx_modify_vp_config
3375 * Change VP configuration for vha
3376 *
3377 * Input:
3378 * vha = adapter block pointer.
3379 *
3380 * Returns:
3381 * qla2xxx local function return status code.
3382 *
3383 * Context:
3384 * Kernel context.
3385 */
3386int
3387qla24xx_modify_vp_config(scsi_qla_host_t *vha)
3388{
3389 int rval;
3390 struct vp_config_entry_24xx *vpmod;
3391 dma_addr_t vpmod_dma;
7b867cf7
AC		 3392 struct qla_hw_data *ha = vha->hw;
3393 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2c3dfe3f
SJ		 3394
3395 /* This can be called by the parent */
2c3dfe3f 3396
5f28d2d7
SK		 3397 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10bb,
3398 "Entered %s.\n", __func__);
7c3df132 3399
7b867cf7 3400 vpmod = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vpmod_dma);
2c3dfe3f 3401 if (!vpmod) {
7c3df132
SK		 3402 ql_log(ql_log_warn, vha, 0x10bc,
3403 "Failed to allocate modify VP IOCB.\n");
2c3dfe3f
SJ		 3404 return QLA_MEMORY_ALLOC_FAILED;
3405 }
3406
3407 memset(vpmod, 0, sizeof(struct vp_config_entry_24xx));
3408 vpmod->entry_type = VP_CONFIG_IOCB_TYPE;
3409 vpmod->entry_count = 1;
3410 vpmod->command = VCT_COMMAND_MOD_ENABLE_VPS;
3411 vpmod->vp_count = 1;
3412 vpmod->vp_index1 = vha->vp_idx;
3413 vpmod->options_idx1 = BIT_3|BIT_4|BIT_5;
2d70c103
NB		 3414
3415 qlt_modify_vp_config(vha, vpmod);
3416
2c3dfe3f
SJ		 3417 memcpy(vpmod->node_name_idx1, vha->node_name, WWN_SIZE);
3418 memcpy(vpmod->port_name_idx1, vha->port_name, WWN_SIZE);
3419 vpmod->entry_count = 1;
3420
7b867cf7 3421 rval = qla2x00_issue_iocb(base_vha, vpmod, vpmod_dma, 0);
2c3dfe3f 3422 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3423 ql_dbg(ql_dbg_mbx, vha, 0x10bd,
3424 "Failed to issue VP config IOCB (%x).\n", rval);
2c3dfe3f 3425 } else if (vpmod->comp_status != 0) {
7c3df132
SK		 3426 ql_dbg(ql_dbg_mbx, vha, 0x10be,
3427 "Failed to complete IOCB -- error status (%x).\n",
3428 vpmod->comp_status);
2c3dfe3f
SJ		 3429 rval = QLA_FUNCTION_FAILED;
3430 } else if (vpmod->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
7c3df132
SK		 3431 ql_dbg(ql_dbg_mbx, vha, 0x10bf,
3432 "Failed to complete IOCB -- completion status (%x).\n",
3433 le16_to_cpu(vpmod->comp_status));
2c3dfe3f
SJ		 3434 rval = QLA_FUNCTION_FAILED;
3435 } else {
3436 /* EMPTY */
5f28d2d7
SK		 3437 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c0,
3438 "Done %s.\n", __func__);
2c3dfe3f
SJ		 3439 fc_vport_set_state(vha->fc_vport, FC_VPORT_INITIALIZING);
3440 }
7b867cf7 3441 dma_pool_free(ha->s_dma_pool, vpmod, vpmod_dma);
2c3dfe3f
SJ		 3442
3443 return rval;
3444}
3445
3446/*
3447 * qla24xx_control_vp
3448 * Enable a virtual port for given host
3449 *
3450 * Input:
3451 * ha = adapter block pointer.
3452 * vhba = virtual adapter (unused)
3453 * index = index number for enabled VP
3454 *
3455 * Returns:
3456 * qla2xxx local function return status code.
3457 *
3458 * Context:
3459 * Kernel context.
3460 */
3461int
3462qla24xx_control_vp(scsi_qla_host_t *vha, int cmd)
3463{
3464 int rval;
3465 int map, pos;
3466 struct vp_ctrl_entry_24xx *vce;
3467 dma_addr_t vce_dma;
7b867cf7 3468 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 3469 int vp_index = vha->vp_idx;
7b867cf7 3470 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2c3dfe3f 3471
5f28d2d7 3472 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c1,
7c3df132 3473 "Entered %s enabling index %d.\n", __func__, vp_index);
2c3dfe3f 3474
eb66dc60 3475 if (vp_index == 0 || vp_index >= ha->max_npiv_vports)
2c3dfe3f
SJ		 3476 return QLA_PARAMETER_ERROR;
3477
3478 vce = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vce_dma);
3479 if (!vce) {
7c3df132
SK		 3480 ql_log(ql_log_warn, vha, 0x10c2,
3481 "Failed to allocate VP control IOCB.\n");
2c3dfe3f
SJ		 3482 return QLA_MEMORY_ALLOC_FAILED;
3483 }
3484 memset(vce, 0, sizeof(struct vp_ctrl_entry_24xx));
3485
3486 vce->entry_type = VP_CTRL_IOCB_TYPE;
3487 vce->entry_count = 1;
3488 vce->command = cpu_to_le16(cmd);
3489 vce->vp_count = __constant_cpu_to_le16(1);
3490
3491 /* index map in firmware starts with 1; decrement index
3492 * this is ok as we never use index 0
3493 */
3494 map = (vp_index - 1) / 8;
3495 pos = (vp_index - 1) & 7;
6c2f527c 3496 mutex_lock(&ha->vport_lock);
2c3dfe3f 3497 vce->vp_idx_map[map] |= 1 << pos;
6c2f527c 3498 mutex_unlock(&ha->vport_lock);
2c3dfe3f 3499
7b867cf7 3500 rval = qla2x00_issue_iocb(base_vha, vce, vce_dma, 0);
2c3dfe3f 3501 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3502 ql_dbg(ql_dbg_mbx, vha, 0x10c3,
3503 "Failed to issue VP control IOCB (%x).\n", rval);
2c3dfe3f 3504 } else if (vce->entry_status != 0) {
7c3df132
SK		 3505 ql_dbg(ql_dbg_mbx, vha, 0x10c4,
3506 "Failed to complete IOCB -- error status (%x).\n",
2c3dfe3f
SJ		 3507 vce->entry_status);
3508 rval = QLA_FUNCTION_FAILED;
3509 } else if (vce->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
7c3df132
SK		 3510 ql_dbg(ql_dbg_mbx, vha, 0x10c5,
3511 "Failed to complet IOCB -- completion status (%x).\n",
2c3dfe3f
SJ		 3512 le16_to_cpu(vce->comp_status));
3513 rval = QLA_FUNCTION_FAILED;
3514 } else {
5f28d2d7
SK		 3515 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c6,
3516 "Done %s.\n", __func__);
2c3dfe3f
SJ		 3517 }
3518
3519 dma_pool_free(ha->s_dma_pool, vce, vce_dma);
3520
3521 return rval;
3522}
3523
3524/*
3525 * qla2x00_send_change_request
3526 * Receive or disable RSCN request from fabric controller
3527 *
3528 * Input:
3529 * ha = adapter block pointer
3530 * format = registration format:
3531 * 0 - Reserved
3532 * 1 - Fabric detected registration
3533 * 2 - N_port detected registration
3534 * 3 - Full registration
3535 * FF - clear registration
3536 * vp_idx = Virtual port index
3537 *
3538 * Returns:
3539 * qla2x00 local function return status code.
3540 *
3541 * Context:
3542 * Kernel Context
3543 */
3544
3545int
7b867cf7 3546qla2x00_send_change_request(scsi_qla_host_t *vha, uint16_t format,
2c3dfe3f
SJ		 3547 uint16_t vp_idx)
3548{
3549 int rval;
3550 mbx_cmd_t mc;
3551 mbx_cmd_t *mcp = &mc;
3552
5f28d2d7
SK		 3553 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c7,
3554 "Entered %s.\n", __func__);
7c3df132 3555
2c3dfe3f
SJ		 3556 mcp->mb[0] = MBC_SEND_CHANGE_REQUEST;
3557 mcp->mb[1] = format;
3558 mcp->mb[9] = vp_idx;
3559 mcp->out_mb = MBX_9|MBX_1|MBX_0;
3560 mcp->in_mb = MBX_0|MBX_1;
3561 mcp->tov = MBX_TOV_SECONDS;
3562 mcp->flags = 0;
7b867cf7 3563 rval = qla2x00_mailbox_command(vha, mcp);
2c3dfe3f
SJ		 3564
3565 if (rval == QLA_SUCCESS) {
3566 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
3567 rval = BIT_1;
3568 }
3569 } else
3570 rval = BIT_1;
3571
3572 return rval;
3573}
338c9161
AV		 3574
3575int
7b867cf7 3576qla2x00_dump_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr,
338c9161
AV		 3577 uint32_t size)
3578{
3579 int rval;
3580 mbx_cmd_t mc;
3581 mbx_cmd_t *mcp = &mc;
3582
5f28d2d7
SK		 3583 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1009,
3584 "Entered %s.\n", __func__);
338c9161 3585
7b867cf7 3586 if (MSW(addr) || IS_FWI2_CAPABLE(vha->hw)) {
338c9161
AV		 3587 mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED;
3588 mcp->mb[8] = MSW(addr);
3589 mcp->out_mb = MBX_8|MBX_0;
3590 } else {
3591 mcp->mb[0] = MBC_DUMP_RISC_RAM;
3592 mcp->out_mb = MBX_0;
3593 }
3594 mcp->mb[1] = LSW(addr);
3595 mcp->mb[2] = MSW(req_dma);
3596 mcp->mb[3] = LSW(req_dma);
3597 mcp->mb[6] = MSW(MSD(req_dma));
3598 mcp->mb[7] = LSW(MSD(req_dma));
3599 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
7b867cf7 3600 if (IS_FWI2_CAPABLE(vha->hw)) {
338c9161
AV		 3601 mcp->mb[4] = MSW(size);
3602 mcp->mb[5] = LSW(size);
3603 mcp->out_mb |= MBX_5|MBX_4;
3604 } else {
3605 mcp->mb[4] = LSW(size);
3606 mcp->out_mb |= MBX_4;
3607 }
3608
3609 mcp->in_mb = MBX_0;
b93480e3 3610 mcp->tov = MBX_TOV_SECONDS;
338c9161 3611 mcp->flags = 0;
7b867cf7 3612 rval = qla2x00_mailbox_command(vha, mcp);
338c9161
AV		 3613
3614 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3615 ql_dbg(ql_dbg_mbx, vha, 0x1008,
3616 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
338c9161 3617 } else {
5f28d2d7
SK		 3618 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1007,
3619 "Done %s.\n", __func__);
338c9161
AV		 3620 }
3621
3622 return rval;
3623}
4d4df193
HK		 3624/* 84XX Support **************************************************************/
3625
3626struct cs84xx_mgmt_cmd {
3627 union {
3628 struct verify_chip_entry_84xx req;
3629 struct verify_chip_rsp_84xx rsp;
3630 } p;
3631};
3632
3633int
7b867cf7 3634qla84xx_verify_chip(struct scsi_qla_host *vha, uint16_t *status)
4d4df193
HK		 3635{
3636 int rval, retry;
3637 struct cs84xx_mgmt_cmd *mn;
3638 dma_addr_t mn_dma;
3639 uint16_t options;
3640 unsigned long flags;
7b867cf7 3641 struct qla_hw_data *ha = vha->hw;
4d4df193 3642
5f28d2d7
SK		 3643 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c8,
3644 "Entered %s.\n", __func__);
4d4df193
HK		 3645
3646 mn = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &mn_dma);
3647 if (mn == NULL) {
4d4df193
HK		 3648 return QLA_MEMORY_ALLOC_FAILED;
3649 }
3650
3651 /* Force Update? */
3652 options = ha->cs84xx->fw_update ? VCO_FORCE_UPDATE : 0;
3653 /* Diagnostic firmware? */
3654 /* options |= MENLO_DIAG_FW; */
3655 /* We update the firmware with only one data sequence. */
3656 options |= VCO_END_OF_DATA;
3657
4d4df193 3658 do {
c1ec1f1b 3659 retry = 0;
4d4df193
HK		 3660 memset(mn, 0, sizeof(*mn));
3661 mn->p.req.entry_type = VERIFY_CHIP_IOCB_TYPE;
3662 mn->p.req.entry_count = 1;
3663 mn->p.req.options = cpu_to_le16(options);
3664
7c3df132
SK		 3665 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111c,
3666 "Dump of Verify Request.\n");
3667 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111e,
3668 (uint8_t *)mn, sizeof(*mn));
4d4df193 3669
7b867cf7 3670 rval = qla2x00_issue_iocb_timeout(vha, mn, mn_dma, 0, 120);
4d4df193 3671 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3672 ql_dbg(ql_dbg_mbx, vha, 0x10cb,
3673 "Failed to issue verify IOCB (%x).\n", rval);
4d4df193
HK		 3674 goto verify_done;
3675 }
3676
7c3df132
SK		 3677 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1110,
3678 "Dump of Verify Response.\n");
3679 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1118,
3680 (uint8_t *)mn, sizeof(*mn));
4d4df193
HK		 3681
3682 status[0] = le16_to_cpu(mn->p.rsp.comp_status);
3683 status[1] = status[0] == CS_VCS_CHIP_FAILURE ?
3684 le16_to_cpu(mn->p.rsp.failure_code) : 0;
5f28d2d7 3685 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ce,
7c3df132 3686 "cs=%x fc=%x.\n", status[0], status[1]);
4d4df193
HK		 3687
3688 if (status[0] != CS_COMPLETE) {
3689 rval = QLA_FUNCTION_FAILED;
3690 if (!(options & VCO_DONT_UPDATE_FW)) {
7c3df132
SK		 3691 ql_dbg(ql_dbg_mbx, vha, 0x10cf,
3692 "Firmware update failed. Retrying "
3693 "without update firmware.\n");
4d4df193
HK		 3694 options |= VCO_DONT_UPDATE_FW;
3695 options &= ~VCO_FORCE_UPDATE;
3696 retry = 1;
3697 }
3698 } else {
5f28d2d7 3699 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d0,
7c3df132
SK		 3700 "Firmware updated to %x.\n",
3701 le32_to_cpu(mn->p.rsp.fw_ver));
4d4df193
HK		 3702
3703 /* NOTE: we only update OP firmware. */
3704 spin_lock_irqsave(&ha->cs84xx->access_lock, flags);
3705 ha->cs84xx->op_fw_version =
3706 le32_to_cpu(mn->p.rsp.fw_ver);
3707 spin_unlock_irqrestore(&ha->cs84xx->access_lock,
3708 flags);
3709 }
3710 } while (retry);
3711
3712verify_done:
3713 dma_pool_free(ha->s_dma_pool, mn, mn_dma);
3714
3715 if (rval != QLA_SUCCESS) {
5f28d2d7
SK		 3716 ql_dbg(ql_dbg_mbx, vha, 0x10d1,
3717 "Failed=%x.\n", rval);
4d4df193 3718 } else {
5f28d2d7
SK		 3719 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d2,
3720 "Done %s.\n", __func__);
4d4df193
HK		 3721 }
3722
3723 return rval;
3724}
73208dfd
AC		 3725
3726int
618a7523 3727qla25xx_init_req_que(struct scsi_qla_host *vha, struct req_que *req)
73208dfd
AC		 3728{
3729 int rval;
3730 unsigned long flags;
3731 mbx_cmd_t mc;
3732 mbx_cmd_t *mcp = &mc;
73208dfd
AC		 3733 struct qla_hw_data *ha = vha->hw;
3734
5f28d2d7
SK		 3735 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d3,
3736 "Entered %s.\n", __func__);
7c3df132 3737
7c6300e3
JC		 3738 if (IS_SHADOW_REG_CAPABLE(ha))
3739 req->options |= BIT_13;
3740
73208dfd 3741 mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
618a7523 3742 mcp->mb[1] = req->options;
73208dfd
AC		 3743 mcp->mb[2] = MSW(LSD(req->dma));
3744 mcp->mb[3] = LSW(LSD(req->dma));
3745 mcp->mb[6] = MSW(MSD(req->dma));
3746 mcp->mb[7] = LSW(MSD(req->dma));
3747 mcp->mb[5] = req->length;
3748 if (req->rsp)
3749 mcp->mb[10] = req->rsp->id;
3750 mcp->mb[12] = req->qos;
3751 mcp->mb[11] = req->vp_idx;
3752 mcp->mb[13] = req->rid;
f73cb695 3753 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
6246b8a1 3754 mcp->mb[15] = 0;
73208dfd 3755
73208dfd
AC		 3756 mcp->mb[4] = req->id;
3757 /* que in ptr index */
3758 mcp->mb[8] = 0;
3759 /* que out ptr index */
7c6300e3 3760 mcp->mb[9] = *req->out_ptr = 0;
73208dfd
AC		 3761 mcp->out_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|MBX_7|
3762 MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
3763 mcp->in_mb = MBX_0;
3764 mcp->flags = MBX_DMA_OUT;
6246b8a1
GM		 3765 mcp->tov = MBX_TOV_SECONDS * 2;
3766
f73cb695 3767 if (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha))
6246b8a1 3768 mcp->in_mb |= MBX_1;
ba4828b7 3769 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
6246b8a1
GM		 3770 mcp->out_mb |= MBX_15;
3771 /* debug q create issue in SR-IOV */
3772 mcp->in_mb |= MBX_9 | MBX_8 | MBX_7;
3773 }
73208dfd
AC		 3774
3775 spin_lock_irqsave(&ha->hardware_lock, flags);
618a7523 3776 if (!(req->options & BIT_0)) {
da9b1d5c 3777 WRT_REG_DWORD(req->req_q_in, 0);
29db41c3 3778 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
da9b1d5c 3779 WRT_REG_DWORD(req->req_q_out, 0);
73208dfd
AC		 3780 }
3781 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3782
17d98630 3783 rval = qla2x00_mailbox_command(vha, mcp);
7c3df132
SK		 3784 if (rval != QLA_SUCCESS) {
3785 ql_dbg(ql_dbg_mbx, vha, 0x10d4,
3786 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3787 } else {
5f28d2d7
SK		 3788 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d5,
3789 "Done %s.\n", __func__);
7c3df132
SK		 3790 }
3791
73208dfd
AC		 3792 return rval;
3793}
3794
3795int
618a7523 3796qla25xx_init_rsp_que(struct scsi_qla_host *vha, struct rsp_que *rsp)
73208dfd
AC		 3797{
3798 int rval;
3799 unsigned long flags;
3800 mbx_cmd_t mc;
3801 mbx_cmd_t *mcp = &mc;
73208dfd
AC		 3802 struct qla_hw_data *ha = vha->hw;
3803
5f28d2d7
SK		 3804 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d6,
3805 "Entered %s.\n", __func__);
7c3df132 3806
7c6300e3
JC		 3807 if (IS_SHADOW_REG_CAPABLE(ha))
3808 rsp->options |= BIT_13;
3809
73208dfd 3810 mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
618a7523 3811 mcp->mb[1] = rsp->options;
73208dfd
AC		 3812 mcp->mb[2] = MSW(LSD(rsp->dma));
3813 mcp->mb[3] = LSW(LSD(rsp->dma));
3814 mcp->mb[6] = MSW(MSD(rsp->dma));
3815 mcp->mb[7] = LSW(MSD(rsp->dma));
3816 mcp->mb[5] = rsp->length;
444786d7 3817 mcp->mb[14] = rsp->msix->entry;
73208dfd 3818 mcp->mb[13] = rsp->rid;
f73cb695 3819 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
6246b8a1 3820 mcp->mb[15] = 0;
73208dfd 3821
73208dfd
AC		 3822 mcp->mb[4] = rsp->id;
3823 /* que in ptr index */
7c6300e3 3824 mcp->mb[8] = *rsp->in_ptr = 0;
73208dfd
AC		 3825 /* que out ptr index */
3826 mcp->mb[9] = 0;
2afa19a9 3827 mcp->out_mb = MBX_14|MBX_13|MBX_9|MBX_8|MBX_7
73208dfd
AC		 3828 |MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
3829 mcp->in_mb = MBX_0;
3830 mcp->flags = MBX_DMA_OUT;
6246b8a1
GM		 3831 mcp->tov = MBX_TOV_SECONDS * 2;
3832
3833 if (IS_QLA81XX(ha)) {
3834 mcp->out_mb |= MBX_12|MBX_11|MBX_10;
3835 mcp->in_mb |= MBX_1;
f73cb695 3836 } else if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
6246b8a1
GM		 3837 mcp->out_mb |= MBX_15|MBX_12|MBX_11|MBX_10;
3838 mcp->in_mb |= MBX_1;
3839 /* debug q create issue in SR-IOV */
3840 mcp->in_mb |= MBX_9 | MBX_8 | MBX_7;
3841 }
73208dfd
AC		 3842
3843 spin_lock_irqsave(&ha->hardware_lock, flags);
618a7523 3844 if (!(rsp->options & BIT_0)) {
da9b1d5c 3845 WRT_REG_DWORD(rsp->rsp_q_out, 0);
6246b8a1 3846 if (!IS_QLA83XX(ha))
da9b1d5c 3847 WRT_REG_DWORD(rsp->rsp_q_in, 0);
73208dfd
AC		 3848 }
3849
3850 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3851
17d98630 3852 rval = qla2x00_mailbox_command(vha, mcp);
7c3df132
SK		 3853 if (rval != QLA_SUCCESS) {
3854 ql_dbg(ql_dbg_mbx, vha, 0x10d7,
3855 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3856 } else {
5f28d2d7
SK		 3857 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d8,
3858 "Done %s.\n", __func__);
7c3df132
SK		 3859 }
3860
73208dfd
AC		 3861 return rval;
3862}
3863
8a659571
AV		 3864int
3865qla81xx_idc_ack(scsi_qla_host_t *vha, uint16_t *mb)
3866{
3867 int rval;
3868 mbx_cmd_t mc;
3869 mbx_cmd_t *mcp = &mc;
3870
5f28d2d7
SK		 3871 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d9,
3872 "Entered %s.\n", __func__);
8a659571
AV		 3873
3874 mcp->mb[0] = MBC_IDC_ACK;
3875 memcpy(&mcp->mb[1], mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
3876 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
3877 mcp->in_mb = MBX_0;
3878 mcp->tov = MBX_TOV_SECONDS;
3879 mcp->flags = 0;
3880 rval = qla2x00_mailbox_command(vha, mcp);
3881
3882 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3883 ql_dbg(ql_dbg_mbx, vha, 0x10da,
3884 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
8a659571 3885 } else {
5f28d2d7
SK		 3886 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10db,
3887 "Done %s.\n", __func__);
8a659571
AV		 3888 }
3889
3890 return rval;
3891}
1d2874de
JC		 3892
3893int
3894qla81xx_fac_get_sector_size(scsi_qla_host_t *vha, uint32_t *sector_size)
3895{
3896 int rval;
3897 mbx_cmd_t mc;
3898 mbx_cmd_t *mcp = &mc;
3899
5f28d2d7
SK		 3900 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10dc,
3901 "Entered %s.\n", __func__);
7c3df132 3902
f73cb695
CD		 3903 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
3904 !IS_QLA27XX(vha->hw))
1d2874de
JC		 3905 return QLA_FUNCTION_FAILED;
3906
1d2874de
JC		 3907 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
3908 mcp->mb[1] = FAC_OPT_CMD_GET_SECTOR_SIZE;
3909 mcp->out_mb = MBX_1|MBX_0;
3910 mcp->in_mb = MBX_1|MBX_0;
3911 mcp->tov = MBX_TOV_SECONDS;
3912 mcp->flags = 0;
3913 rval = qla2x00_mailbox_command(vha, mcp);
3914
3915 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3916 ql_dbg(ql_dbg_mbx, vha, 0x10dd,
3917 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3918 rval, mcp->mb[0], mcp->mb[1]);
1d2874de 3919 } else {
5f28d2d7
SK		 3920 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10de,
3921 "Done %s.\n", __func__);
1d2874de
JC		 3922 *sector_size = mcp->mb[1];
3923 }
3924
3925 return rval;
3926}
3927
3928int
3929qla81xx_fac_do_write_enable(scsi_qla_host_t *vha, int enable)
3930{
3931 int rval;
3932 mbx_cmd_t mc;
3933 mbx_cmd_t *mcp = &mc;
3934
f73cb695
CD		 3935 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
3936 !IS_QLA27XX(vha->hw))
1d2874de
JC		 3937 return QLA_FUNCTION_FAILED;
3938
5f28d2d7
SK		 3939 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10df,
3940 "Entered %s.\n", __func__);
1d2874de
JC		 3941
3942 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
3943 mcp->mb[1] = enable ? FAC_OPT_CMD_WRITE_ENABLE :
3944 FAC_OPT_CMD_WRITE_PROTECT;
3945 mcp->out_mb = MBX_1|MBX_0;
3946 mcp->in_mb = MBX_1|MBX_0;
3947 mcp->tov = MBX_TOV_SECONDS;
3948 mcp->flags = 0;
3949 rval = qla2x00_mailbox_command(vha, mcp);
3950
3951 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3952 ql_dbg(ql_dbg_mbx, vha, 0x10e0,
3953 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3954 rval, mcp->mb[0], mcp->mb[1]);
1d2874de 3955 } else {
5f28d2d7
SK		 3956 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e1,
3957 "Done %s.\n", __func__);
1d2874de
JC		 3958 }
3959
3960 return rval;
3961}
3962
3963int
3964qla81xx_fac_erase_sector(scsi_qla_host_t *vha, uint32_t start, uint32_t finish)
3965{
3966 int rval;
3967 mbx_cmd_t mc;
3968 mbx_cmd_t *mcp = &mc;
3969
f73cb695
CD		 3970 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
3971 !IS_QLA27XX(vha->hw))
1d2874de
JC		 3972 return QLA_FUNCTION_FAILED;
3973
5f28d2d7
SK		 3974 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e2,
3975 "Entered %s.\n", __func__);
1d2874de
JC		 3976
3977 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
3978 mcp->mb[1] = FAC_OPT_CMD_ERASE_SECTOR;
3979 mcp->mb[2] = LSW(start);
3980 mcp->mb[3] = MSW(start);
3981 mcp->mb[4] = LSW(finish);
3982 mcp->mb[5] = MSW(finish);
3983 mcp->out_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
3984 mcp->in_mb = MBX_2|MBX_1|MBX_0;
3985 mcp->tov = MBX_TOV_SECONDS;
3986 mcp->flags = 0;
3987 rval = qla2x00_mailbox_command(vha, mcp);
3988
3989 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3990 ql_dbg(ql_dbg_mbx, vha, 0x10e3,
3991 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
3992 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
1d2874de 3993 } else {
5f28d2d7
SK		 3994 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e4,
3995 "Done %s.\n", __func__);
1d2874de
JC		 3996 }
3997
3998 return rval;
3999}
6e181be5
LC		 4000
4001int
4002qla81xx_restart_mpi_firmware(scsi_qla_host_t *vha)
4003{
4004 int rval = 0;
4005 mbx_cmd_t mc;
4006 mbx_cmd_t *mcp = &mc;
4007
5f28d2d7
SK		 4008 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e5,
4009 "Entered %s.\n", __func__);
6e181be5
LC		 4010
4011 mcp->mb[0] = MBC_RESTART_MPI_FW;
4012 mcp->out_mb = MBX_0;
4013 mcp->in_mb = MBX_0|MBX_1;
4014 mcp->tov = MBX_TOV_SECONDS;
4015 mcp->flags = 0;
4016 rval = qla2x00_mailbox_command(vha, mcp);
4017
4018 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4019 ql_dbg(ql_dbg_mbx, vha, 0x10e6,
4020 "Failed=%x mb[0]=%x mb[1]=%x.\n",
4021 rval, mcp->mb[0], mcp->mb[1]);
6e181be5 4022 } else {
5f28d2d7
SK		 4023 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e7,
4024 "Done %s.\n", __func__);
6e181be5
LC		 4025 }
4026
4027 return rval;
4028}
ad0ecd61 4029
c46e65c7
JC		 4030int
4031qla82xx_set_driver_version(scsi_qla_host_t *vha, char *version)
4032{
4033 int rval;
4034 mbx_cmd_t mc;
4035 mbx_cmd_t *mcp = &mc;
4036 int i;
4037 int len;
4038 uint16_t *str;
4039 struct qla_hw_data *ha = vha->hw;
4040
4041 if (!IS_P3P_TYPE(ha))
4042 return QLA_FUNCTION_FAILED;
4043
4044 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117b,
4045 "Entered %s.\n", __func__);
4046
4047 str = (void *)version;
4048 len = strlen(version);
4049
4050 mcp->mb[0] = MBC_SET_RNID_PARAMS;
4051 mcp->mb[1] = RNID_TYPE_SET_VERSION << 8;
4052 mcp->out_mb = MBX_1|MBX_0;
4053 for (i = 4; i < 16 && len; i++, str++, len -= 2) {
4054 mcp->mb[i] = cpu_to_le16p(str);
4055 mcp->out_mb |= 1<<i;
4056 }
4057 for (; i < 16; i++) {
4058 mcp->mb[i] = 0;
4059 mcp->out_mb |= 1<<i;
4060 }
4061 mcp->in_mb = MBX_1|MBX_0;
4062 mcp->tov = MBX_TOV_SECONDS;
4063 mcp->flags = 0;
4064 rval = qla2x00_mailbox_command(vha, mcp);
4065
4066 if (rval != QLA_SUCCESS) {
4067 ql_dbg(ql_dbg_mbx, vha, 0x117c,
4068 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
4069 } else {
4070 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117d,
4071 "Done %s.\n", __func__);
4072 }
4073
4074 return rval;
4075}
4076
4077int
4078qla25xx_set_driver_version(scsi_qla_host_t *vha, char *version)
4079{
4080 int rval;
4081 mbx_cmd_t mc;
4082 mbx_cmd_t *mcp = &mc;
4083 int len;
4084 uint16_t dwlen;
4085 uint8_t *str;
4086 dma_addr_t str_dma;
4087 struct qla_hw_data *ha = vha->hw;
4088
4089 if (!IS_FWI2_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA81XX(ha) ||
4090 IS_P3P_TYPE(ha))
4091 return QLA_FUNCTION_FAILED;
4092
4093 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117e,
4094 "Entered %s.\n", __func__);
4095
4096 str = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &str_dma);
4097 if (!str) {
4098 ql_log(ql_log_warn, vha, 0x117f,
4099 "Failed to allocate driver version param.\n");
4100 return QLA_MEMORY_ALLOC_FAILED;
4101 }
4102
4103 memcpy(str, "\x7\x3\x11\x0", 4);
4104 dwlen = str[0];
4105 len = dwlen * 4 - 4;
4106 memset(str + 4, 0, len);
4107 if (len > strlen(version))
4108 len = strlen(version);
4109 memcpy(str + 4, version, len);
4110
4111 mcp->mb[0] = MBC_SET_RNID_PARAMS;
4112 mcp->mb[1] = RNID_TYPE_SET_VERSION << 8 | dwlen;
4113 mcp->mb[2] = MSW(LSD(str_dma));
4114 mcp->mb[3] = LSW(LSD(str_dma));
4115 mcp->mb[6] = MSW(MSD(str_dma));
4116 mcp->mb[7] = LSW(MSD(str_dma));
4117 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
4118 mcp->in_mb = MBX_1|MBX_0;
4119 mcp->tov = MBX_TOV_SECONDS;
4120 mcp->flags = 0;
4121 rval = qla2x00_mailbox_command(vha, mcp);
4122
4123 if (rval != QLA_SUCCESS) {
4124 ql_dbg(ql_dbg_mbx, vha, 0x1180,
4125 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
4126 } else {
4127 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1181,
4128 "Done %s.\n", __func__);
4129 }
4130
4131 dma_pool_free(ha->s_dma_pool, str, str_dma);
4132
4133 return rval;
4134}
4135
fe52f6e1
JC		 4136static int
4137qla2x00_read_asic_temperature(scsi_qla_host_t *vha, uint16_t *temp)
4138{
4139 int rval;
4140 mbx_cmd_t mc;
4141 mbx_cmd_t *mcp = &mc;
4142
4143 if (!IS_FWI2_CAPABLE(vha->hw))
4144 return QLA_FUNCTION_FAILED;
4145
4146 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1159,
4147 "Entered %s.\n", __func__);
4148
4149 mcp->mb[0] = MBC_GET_RNID_PARAMS;
4150 mcp->mb[1] = RNID_TYPE_ASIC_TEMP << 8;
4151 mcp->out_mb = MBX_1|MBX_0;
4152 mcp->in_mb = MBX_1|MBX_0;
4153 mcp->tov = MBX_TOV_SECONDS;
4154 mcp->flags = 0;
4155 rval = qla2x00_mailbox_command(vha, mcp);
4156 *temp = mcp->mb[1];
4157
4158 if (rval != QLA_SUCCESS) {
4159 ql_dbg(ql_dbg_mbx, vha, 0x115a,
4160 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
4161 } else {
4162 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x115b,
4163 "Done %s.\n", __func__);
4164 }
4165
4166 return rval;
4167}
4168
ad0ecd61 4169int
6766df9e
JC		 4170qla2x00_read_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
4171 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
ad0ecd61
JC		 4172{
4173 int rval;
4174 mbx_cmd_t mc;
4175 mbx_cmd_t *mcp = &mc;
6766df9e
JC		 4176 struct qla_hw_data *ha = vha->hw;
4177
5f28d2d7
SK		 4178 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e8,
4179 "Entered %s.\n", __func__);
7c3df132 4180
6766df9e
JC		 4181 if (!IS_FWI2_CAPABLE(ha))
4182 return QLA_FUNCTION_FAILED;
ad0ecd61 4183
6766df9e
JC		 4184 if (len == 1)
4185 opt |= BIT_0;
4186
ad0ecd61
JC		 4187 mcp->mb[0] = MBC_READ_SFP;
4188 mcp->mb[1] = dev;
4189 mcp->mb[2] = MSW(sfp_dma);
4190 mcp->mb[3] = LSW(sfp_dma);
4191 mcp->mb[6] = MSW(MSD(sfp_dma));
4192 mcp->mb[7] = LSW(MSD(sfp_dma));
4193 mcp->mb[8] = len;
6766df9e 4194 mcp->mb[9] = off;
ad0ecd61
JC		 4195 mcp->mb[10] = opt;
4196 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1bff6cc8 4197 mcp->in_mb = MBX_1|MBX_0;
ad0ecd61
JC		 4198 mcp->tov = MBX_TOV_SECONDS;
4199 mcp->flags = 0;
4200 rval = qla2x00_mailbox_command(vha, mcp);
4201
4202 if (opt & BIT_0)
6766df9e 4203 *sfp = mcp->mb[1];
ad0ecd61
JC		 4204
4205 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4206 ql_dbg(ql_dbg_mbx, vha, 0x10e9,
4207 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
ad0ecd61 4208 } else {
5f28d2d7
SK		 4209 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea,
4210 "Done %s.\n", __func__);
ad0ecd61
JC		 4211 }
4212
4213 return rval;
4214}
4215
4216int
6766df9e
JC		 4217qla2x00_write_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
4218 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
ad0ecd61
JC		 4219{
4220 int rval;
4221 mbx_cmd_t mc;
4222 mbx_cmd_t *mcp = &mc;
6766df9e
JC		 4223 struct qla_hw_data *ha = vha->hw;
4224
5f28d2d7
SK		 4225 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10eb,
4226 "Entered %s.\n", __func__);
7c3df132 4227
6766df9e
JC		 4228 if (!IS_FWI2_CAPABLE(ha))
4229 return QLA_FUNCTION_FAILED;
ad0ecd61 4230
6766df9e
JC		 4231 if (len == 1)
4232 opt |= BIT_0;
4233
ad0ecd61 4234 if (opt & BIT_0)
6766df9e 4235 len = *sfp;
ad0ecd61
JC		 4236
4237 mcp->mb[0] = MBC_WRITE_SFP;
4238 mcp->mb[1] = dev;
4239 mcp->mb[2] = MSW(sfp_dma);
4240 mcp->mb[3] = LSW(sfp_dma);
4241 mcp->mb[6] = MSW(MSD(sfp_dma));
4242 mcp->mb[7] = LSW(MSD(sfp_dma));
4243 mcp->mb[8] = len;
6766df9e 4244 mcp->mb[9] = off;
ad0ecd61
JC		 4245 mcp->mb[10] = opt;
4246 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
6766df9e 4247 mcp->in_mb = MBX_1|MBX_0;
ad0ecd61
JC		 4248 mcp->tov = MBX_TOV_SECONDS;
4249 mcp->flags = 0;
4250 rval = qla2x00_mailbox_command(vha, mcp);
4251
4252 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4253 ql_dbg(ql_dbg_mbx, vha, 0x10ec,
4254 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
ad0ecd61 4255 } else {
5f28d2d7
SK		 4256 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ed,
4257 "Done %s.\n", __func__);
ad0ecd61
JC		 4258 }
4259
4260 return rval;
4261}
ce0423f4
AV		 4262
4263int
4264qla2x00_get_xgmac_stats(scsi_qla_host_t *vha, dma_addr_t stats_dma,
4265 uint16_t size_in_bytes, uint16_t *actual_size)
4266{
4267 int rval;
4268 mbx_cmd_t mc;
4269 mbx_cmd_t *mcp = &mc;
4270
5f28d2d7
SK		 4271 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ee,
4272 "Entered %s.\n", __func__);
7c3df132 4273
6246b8a1 4274 if (!IS_CNA_CAPABLE(vha->hw))
ce0423f4
AV		 4275 return QLA_FUNCTION_FAILED;
4276
ce0423f4
AV		 4277 mcp->mb[0] = MBC_GET_XGMAC_STATS;
4278 mcp->mb[2] = MSW(stats_dma);
4279 mcp->mb[3] = LSW(stats_dma);
4280 mcp->mb[6] = MSW(MSD(stats_dma));
4281 mcp->mb[7] = LSW(MSD(stats_dma));
4282 mcp->mb[8] = size_in_bytes >> 2;
4283 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
4284 mcp->in_mb = MBX_2|MBX_1|MBX_0;
4285 mcp->tov = MBX_TOV_SECONDS;
4286 mcp->flags = 0;
4287 rval = qla2x00_mailbox_command(vha, mcp);
4288
4289 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4290 ql_dbg(ql_dbg_mbx, vha, 0x10ef,
4291 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
4292 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
ce0423f4 4293 } else {
5f28d2d7
SK		 4294 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f0,
4295 "Done %s.\n", __func__);
7c3df132 4296
ce0423f4
AV		 4297
4298 *actual_size = mcp->mb[2] << 2;
4299 }
4300
4301 return rval;
4302}
11bbc1d8
AV		 4303
4304int
4305qla2x00_get_dcbx_params(scsi_qla_host_t *vha, dma_addr_t tlv_dma,
4306 uint16_t size)
4307{
4308 int rval;
4309 mbx_cmd_t mc;
4310 mbx_cmd_t *mcp = &mc;
4311
5f28d2d7
SK		 4312 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f1,
4313 "Entered %s.\n", __func__);
7c3df132 4314
6246b8a1 4315 if (!IS_CNA_CAPABLE(vha->hw))
11bbc1d8
AV		 4316 return QLA_FUNCTION_FAILED;
4317
11bbc1d8
AV		 4318 mcp->mb[0] = MBC_GET_DCBX_PARAMS;
4319 mcp->mb[1] = 0;
4320 mcp->mb[2] = MSW(tlv_dma);
4321 mcp->mb[3] = LSW(tlv_dma);
4322 mcp->mb[6] = MSW(MSD(tlv_dma));
4323 mcp->mb[7] = LSW(MSD(tlv_dma));
4324 mcp->mb[8] = size;
4325 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
4326 mcp->in_mb = MBX_2|MBX_1|MBX_0;
4327 mcp->tov = MBX_TOV_SECONDS;
4328 mcp->flags = 0;
4329 rval = qla2x00_mailbox_command(vha, mcp);
4330
4331 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4332 ql_dbg(ql_dbg_mbx, vha, 0x10f2,
4333 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
4334 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
11bbc1d8 4335 } else {
5f28d2d7
SK		 4336 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f3,
4337 "Done %s.\n", __func__);
11bbc1d8
AV		 4338 }
4339
4340 return rval;
4341}
18e7555a
AV		 4342
4343int
4344qla2x00_read_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t *data)
4345{
4346 int rval;
4347 mbx_cmd_t mc;
4348 mbx_cmd_t *mcp = &mc;
4349
5f28d2d7
SK		 4350 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f4,
4351 "Entered %s.\n", __func__);
7c3df132 4352
18e7555a
AV		 4353 if (!IS_FWI2_CAPABLE(vha->hw))
4354 return QLA_FUNCTION_FAILED;
4355
18e7555a
AV		 4356 mcp->mb[0] = MBC_READ_RAM_EXTENDED;
4357 mcp->mb[1] = LSW(risc_addr);
4358 mcp->mb[8] = MSW(risc_addr);
4359 mcp->out_mb = MBX_8|MBX_1|MBX_0;
4360 mcp->in_mb = MBX_3|MBX_2|MBX_0;
4361 mcp->tov = 30;
4362 mcp->flags = 0;
4363 rval = qla2x00_mailbox_command(vha, mcp);
4364 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4365 ql_dbg(ql_dbg_mbx, vha, 0x10f5,
4366 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
18e7555a 4367 } else {
5f28d2d7
SK		 4368 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f6,
4369 "Done %s.\n", __func__);
18e7555a
AV		 4370 *data = mcp->mb[3] << 16 | mcp->mb[2];
4371 }
4372
4373 return rval;
4374}
4375
9a069e19 4376int
a9083016
GM		 4377qla2x00_loopback_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
4378 uint16_t *mresp)
9a069e19
GM		 4379{
4380 int rval;
4381 mbx_cmd_t mc;
4382 mbx_cmd_t *mcp = &mc;
9a069e19 4383
5f28d2d7
SK		 4384 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f7,
4385 "Entered %s.\n", __func__);
9a069e19
GM		 4386
4387 memset(mcp->mb, 0 , sizeof(mcp->mb));
4388 mcp->mb[0] = MBC_DIAGNOSTIC_LOOP_BACK;
4389 mcp->mb[1] = mreq->options | BIT_6; // BIT_6 specifies 64 bit addressing
4390
4391 /* transfer count */
4392 mcp->mb[10] = LSW(mreq->transfer_size);
4393 mcp->mb[11] = MSW(mreq->transfer_size);
4394
4395 /* send data address */
4396 mcp->mb[14] = LSW(mreq->send_dma);
4397 mcp->mb[15] = MSW(mreq->send_dma);
4398 mcp->mb[20] = LSW(MSD(mreq->send_dma));
4399 mcp->mb[21] = MSW(MSD(mreq->send_dma));
4400
25985edc 4401 /* receive data address */
9a069e19
GM		 4402 mcp->mb[16] = LSW(mreq->rcv_dma);
4403 mcp->mb[17] = MSW(mreq->rcv_dma);
4404 mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
4405 mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
4406
4407 /* Iteration count */
1b98b421
JC		 4408 mcp->mb[18] = LSW(mreq->iteration_count);
4409 mcp->mb[19] = MSW(mreq->iteration_count);
9a069e19
GM		 4410
4411 mcp->out_mb = MBX_21|MBX_20|MBX_19|MBX_18|MBX_17|MBX_16|MBX_15|
4412 MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
6246b8a1 4413 if (IS_CNA_CAPABLE(vha->hw))
9a069e19
GM		 4414 mcp->out_mb |= MBX_2;
4415 mcp->in_mb = MBX_19|MBX_18|MBX_3|MBX_2|MBX_1|MBX_0;
4416
4417 mcp->buf_size = mreq->transfer_size;
4418 mcp->tov = MBX_TOV_SECONDS;
4419 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
4420
4421 rval = qla2x00_mailbox_command(vha, mcp);
4422
4423 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4424 ql_dbg(ql_dbg_mbx, vha, 0x10f8,
4425 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[18]=%x "
4426 "mb[19]=%x.\n", rval, mcp->mb[0], mcp->mb[1], mcp->mb[2],
4427 mcp->mb[3], mcp->mb[18], mcp->mb[19]);
9a069e19 4428 } else {
5f28d2d7
SK		 4429 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f9,
4430 "Done %s.\n", __func__);
9a069e19
GM		 4431 }
4432
4433 /* Copy mailbox information */
4434 memcpy( mresp, mcp->mb, 64);
9a069e19
GM		 4435 return rval;
4436}
4437
4438int
a9083016
GM		 4439qla2x00_echo_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
4440 uint16_t *mresp)
9a069e19
GM		 4441{
4442 int rval;
4443 mbx_cmd_t mc;
4444 mbx_cmd_t *mcp = &mc;
4445 struct qla_hw_data *ha = vha->hw;
4446
5f28d2d7
SK		 4447 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fa,
4448 "Entered %s.\n", __func__);
9a069e19
GM		 4449
4450 memset(mcp->mb, 0 , sizeof(mcp->mb));
4451 mcp->mb[0] = MBC_DIAGNOSTIC_ECHO;
4452 mcp->mb[1] = mreq->options | BIT_6; /* BIT_6 specifies 64bit address */
6246b8a1 4453 if (IS_CNA_CAPABLE(ha)) {
9a069e19 4454 mcp->mb[1] |= BIT_15;
a9083016
GM		 4455 mcp->mb[2] = vha->fcoe_fcf_idx;
4456 }
9a069e19
GM		 4457 mcp->mb[16] = LSW(mreq->rcv_dma);
4458 mcp->mb[17] = MSW(mreq->rcv_dma);
4459 mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
4460 mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
4461
4462 mcp->mb[10] = LSW(mreq->transfer_size);
4463
4464 mcp->mb[14] = LSW(mreq->send_dma);
4465 mcp->mb[15] = MSW(mreq->send_dma);
4466 mcp->mb[20] = LSW(MSD(mreq->send_dma));
4467 mcp->mb[21] = MSW(MSD(mreq->send_dma));
4468
4469 mcp->out_mb = MBX_21|MBX_20|MBX_17|MBX_16|MBX_15|
4470 MBX_14|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
6246b8a1 4471 if (IS_CNA_CAPABLE(ha))
9a069e19
GM		 4472 mcp->out_mb |= MBX_2;
4473
4474 mcp->in_mb = MBX_0;
6246b8a1
GM		 4475 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha) ||
4476 IS_CNA_CAPABLE(ha) || IS_QLA2031(ha))
9a069e19 4477 mcp->in_mb |= MBX_1;
6246b8a1 4478 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha))
9a069e19
GM		 4479 mcp->in_mb |= MBX_3;
4480
4481 mcp->tov = MBX_TOV_SECONDS;
4482 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
4483 mcp->buf_size = mreq->transfer_size;
4484
4485 rval = qla2x00_mailbox_command(vha, mcp);
4486
4487 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4488 ql_dbg(ql_dbg_mbx, vha, 0x10fb,
4489 "Failed=%x mb[0]=%x mb[1]=%x.\n",
4490 rval, mcp->mb[0], mcp->mb[1]);
9a069e19 4491 } else {
5f28d2d7
SK		 4492 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fc,
4493 "Done %s.\n", __func__);
9a069e19
GM		 4494 }
4495
4496 /* Copy mailbox information */
6dbdda4d 4497 memcpy(mresp, mcp->mb, 64);
9a069e19
GM		 4498 return rval;
4499}
6dbdda4d 4500
9a069e19 4501int
7c3df132 4502qla84xx_reset_chip(scsi_qla_host_t *vha, uint16_t enable_diagnostic)
9a069e19
GM		 4503{
4504 int rval;
4505 mbx_cmd_t mc;
4506 mbx_cmd_t *mcp = &mc;
4507
5f28d2d7 4508 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fd,
7c3df132 4509 "Entered %s enable_diag=%d.\n", __func__, enable_diagnostic);
9a069e19
GM		 4510
4511 mcp->mb[0] = MBC_ISP84XX_RESET;
4512 mcp->mb[1] = enable_diagnostic;
4513 mcp->out_mb = MBX_1|MBX_0;
4514 mcp->in_mb = MBX_1|MBX_0;
4515 mcp->tov = MBX_TOV_SECONDS;
4516 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
7c3df132 4517 rval = qla2x00_mailbox_command(vha, mcp);
9a069e19 4518
9a069e19 4519 if (rval != QLA_SUCCESS)
7c3df132 4520 ql_dbg(ql_dbg_mbx, vha, 0x10fe, "Failed=%x.\n", rval);
9a069e19 4521 else
5f28d2d7
SK		 4522 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ff,
4523 "Done %s.\n", __func__);
9a069e19
GM		 4524
4525 return rval;
4526}
4527
18e7555a
AV		 4528int
4529qla2x00_write_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t data)
4530{
4531 int rval;
4532 mbx_cmd_t mc;
4533 mbx_cmd_t *mcp = &mc;
4534
5f28d2d7
SK		 4535 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1100,
4536 "Entered %s.\n", __func__);
7c3df132 4537
18e7555a 4538 if (!IS_FWI2_CAPABLE(vha->hw))
6c452a45 4539 return QLA_FUNCTION_FAILED;
18e7555a 4540
18e7555a
AV		 4541 mcp->mb[0] = MBC_WRITE_RAM_WORD_EXTENDED;
4542 mcp->mb[1] = LSW(risc_addr);
4543 mcp->mb[2] = LSW(data);
4544 mcp->mb[3] = MSW(data);
4545 mcp->mb[8] = MSW(risc_addr);
4546 mcp->out_mb = MBX_8|MBX_3|MBX_2|MBX_1|MBX_0;
4547 mcp->in_mb = MBX_0;
4548 mcp->tov = 30;
4549 mcp->flags = 0;
4550 rval = qla2x00_mailbox_command(vha, mcp);
4551 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4552 ql_dbg(ql_dbg_mbx, vha, 0x1101,
4553 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
18e7555a 4554 } else {
5f28d2d7
SK		 4555 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1102,
4556 "Done %s.\n", __func__);
18e7555a
AV		 4557 }
4558
4559 return rval;
4560}
3064ff39 4561
b1d46989
MI		 4562int
4563qla81xx_write_mpi_register(scsi_qla_host_t *vha, uint16_t *mb)
4564{
4565 int rval;
4566 uint32_t stat, timer;
4567 uint16_t mb0 = 0;
4568 struct qla_hw_data *ha = vha->hw;
4569 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
4570
4571 rval = QLA_SUCCESS;
4572
5f28d2d7
SK		 4573 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1103,
4574 "Entered %s.\n", __func__);
b1d46989
MI		 4575
4576 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
4577
4578 /* Write the MBC data to the registers */
4579 WRT_REG_WORD(&reg->mailbox0, MBC_WRITE_MPI_REGISTER);
4580 WRT_REG_WORD(&reg->mailbox1, mb[0]);
4581 WRT_REG_WORD(&reg->mailbox2, mb[1]);
4582 WRT_REG_WORD(&reg->mailbox3, mb[2]);
4583 WRT_REG_WORD(&reg->mailbox4, mb[3]);
4584
4585 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
4586
4587 /* Poll for MBC interrupt */
4588 for (timer = 6000000; timer; timer--) {
4589 /* Check for pending interrupts. */
4590 stat = RD_REG_DWORD(&reg->host_status);
4591 if (stat & HSRX_RISC_INT) {
4592 stat &= 0xff;
4593
4594 if (stat == 0x1 || stat == 0x2 ||
4595 stat == 0x10 || stat == 0x11) {
4596 set_bit(MBX_INTERRUPT,
4597 &ha->mbx_cmd_flags);
4598 mb0 = RD_REG_WORD(&reg->mailbox0);
4599 WRT_REG_DWORD(&reg->hccr,
4600 HCCRX_CLR_RISC_INT);
4601 RD_REG_DWORD(&reg->hccr);
4602 break;
4603 }
4604 }
4605 udelay(5);
4606 }
4607
4608 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags))
4609 rval = mb0 & MBS_MASK;
4610 else
4611 rval = QLA_FUNCTION_FAILED;
4612
4613 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4614 ql_dbg(ql_dbg_mbx, vha, 0x1104,
4615 "Failed=%x mb[0]=%x.\n", rval, mb[0]);
b1d46989 4616 } else {
5f28d2d7
SK		 4617 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1105,
4618 "Done %s.\n", __func__);
b1d46989
MI		 4619 }
4620
4621 return rval;
4622}
6246b8a1 4623
3064ff39
MH		 4624int
4625qla2x00_get_data_rate(scsi_qla_host_t *vha)
4626{
4627 int rval;
4628 mbx_cmd_t mc;
4629 mbx_cmd_t *mcp = &mc;
4630 struct qla_hw_data *ha = vha->hw;
4631
5f28d2d7
SK		 4632 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1106,
4633 "Entered %s.\n", __func__);
7c3df132 4634
3064ff39
MH		 4635 if (!IS_FWI2_CAPABLE(ha))
4636 return QLA_FUNCTION_FAILED;
4637
3064ff39
MH		 4638 mcp->mb[0] = MBC_DATA_RATE;
4639 mcp->mb[1] = 0;
4640 mcp->out_mb = MBX_1|MBX_0;
4641 mcp->in_mb = MBX_2|MBX_1|MBX_0;
f73cb695 4642 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
6246b8a1 4643 mcp->in_mb |= MBX_3;
3064ff39
MH		 4644 mcp->tov = MBX_TOV_SECONDS;
4645 mcp->flags = 0;
4646 rval = qla2x00_mailbox_command(vha, mcp);
4647 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4648 ql_dbg(ql_dbg_mbx, vha, 0x1107,
4649 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3064ff39 4650 } else {
5f28d2d7
SK		 4651 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1108,
4652 "Done %s.\n", __func__);
3064ff39
MH		 4653 if (mcp->mb[1] != 0x7)
4654 ha->link_data_rate = mcp->mb[1];
4655 }
4656
4657 return rval;
4658}
09ff701a 4659
23f2ebd1
SR		 4660int
4661qla81xx_get_port_config(scsi_qla_host_t *vha, uint16_t *mb)
4662{
4663 int rval;
4664 mbx_cmd_t mc;
4665 mbx_cmd_t *mcp = &mc;
4666 struct qla_hw_data *ha = vha->hw;
4667
5f28d2d7
SK		 4668 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1109,
4669 "Entered %s.\n", __func__);
23f2ebd1 4670
f73cb695
CD		 4671 if (!IS_QLA81XX(ha) && !IS_QLA83XX(ha) && !IS_QLA8044(ha) &&
4672 !IS_QLA27XX(ha))
23f2ebd1
SR		 4673 return QLA_FUNCTION_FAILED;
4674 mcp->mb[0] = MBC_GET_PORT_CONFIG;
4675 mcp->out_mb = MBX_0;
4676 mcp->in_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4677 mcp->tov = MBX_TOV_SECONDS;
4678 mcp->flags = 0;
4679
4680 rval = qla2x00_mailbox_command(vha, mcp);
4681
4682 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4683 ql_dbg(ql_dbg_mbx, vha, 0x110a,
4684 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
23f2ebd1
SR		 4685 } else {
4686 /* Copy all bits to preserve original value */
4687 memcpy(mb, &mcp->mb[1], sizeof(uint16_t) * 4);
4688
5f28d2d7
SK		 4689 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110b,
4690 "Done %s.\n", __func__);
23f2ebd1
SR		 4691 }
4692 return rval;
4693}
4694
4695int
4696qla81xx_set_port_config(scsi_qla_host_t *vha, uint16_t *mb)
4697{
4698 int rval;
4699 mbx_cmd_t mc;
4700 mbx_cmd_t *mcp = &mc;
4701
5f28d2d7
SK		 4702 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110c,
4703 "Entered %s.\n", __func__);
23f2ebd1
SR		 4704
4705 mcp->mb[0] = MBC_SET_PORT_CONFIG;
4706 /* Copy all bits to preserve original setting */
4707 memcpy(&mcp->mb[1], mb, sizeof(uint16_t) * 4);
4708 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4709 mcp->in_mb = MBX_0;
4710 mcp->tov = MBX_TOV_SECONDS;
4711 mcp->flags = 0;
4712 rval = qla2x00_mailbox_command(vha, mcp);
4713
4714 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4715 ql_dbg(ql_dbg_mbx, vha, 0x110d,
4716 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
23f2ebd1 4717 } else
5f28d2d7
SK		 4718 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110e,
4719 "Done %s.\n", __func__);
23f2ebd1
SR		 4720
4721 return rval;
4722}
4723
4724
09ff701a
SR		 4725int
4726qla24xx_set_fcp_prio(scsi_qla_host_t *vha, uint16_t loop_id, uint16_t priority,
4727 uint16_t *mb)
4728{
4729 int rval;
4730 mbx_cmd_t mc;
4731 mbx_cmd_t *mcp = &mc;
4732 struct qla_hw_data *ha = vha->hw;
4733
5f28d2d7
SK		 4734 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110f,
4735 "Entered %s.\n", __func__);
7c3df132 4736
09ff701a
SR		 4737 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha))
4738 return QLA_FUNCTION_FAILED;
4739
09ff701a
SR		 4740 mcp->mb[0] = MBC_PORT_PARAMS;
4741 mcp->mb[1] = loop_id;
4742 if (ha->flags.fcp_prio_enabled)
4743 mcp->mb[2] = BIT_1;
4744 else
4745 mcp->mb[2] = BIT_2;
4746 mcp->mb[4] = priority & 0xf;
4747 mcp->mb[9] = vha->vp_idx;
4748 mcp->out_mb = MBX_9|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4749 mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0;
4750 mcp->tov = 30;
4751 mcp->flags = 0;
4752 rval = qla2x00_mailbox_command(vha, mcp);
4753 if (mb != NULL) {
4754 mb[0] = mcp->mb[0];
4755 mb[1] = mcp->mb[1];
4756 mb[3] = mcp->mb[3];
4757 mb[4] = mcp->mb[4];
4758 }
4759
4760 if (rval != QLA_SUCCESS) {
7c3df132 4761 ql_dbg(ql_dbg_mbx, vha, 0x10cd, "Failed=%x.\n", rval);
09ff701a 4762 } else {
5f28d2d7
SK		 4763 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10cc,
4764 "Done %s.\n", __func__);
09ff701a
SR		 4765 }
4766
4767 return rval;
4768}
a9083016 4769
794a5691 4770int
fe52f6e1 4771qla2x00_get_thermal_temp(scsi_qla_host_t *vha, uint16_t *temp)
794a5691 4772{
fe52f6e1 4773 int rval = QLA_FUNCTION_FAILED;
794a5691 4774 struct qla_hw_data *ha = vha->hw;
fe52f6e1 4775 uint8_t byte;
794a5691 4776
1ae47cf3
JC		 4777 if (!IS_FWI2_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA81XX(ha)) {
4778 ql_dbg(ql_dbg_mbx, vha, 0x1150,
4779 "Thermal not supported by this card.\n");
4780 return rval;
4781 }
4782
4783 if (IS_QLA25XX(ha)) {
4784 if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
4785 ha->pdev->subsystem_device == 0x0175) {
4786 rval = qla2x00_read_sfp(vha, 0, &byte,
4787 0x98, 0x1, 1, BIT_13|BIT_0);
4788 *temp = byte;
4789 return rval;
4790 }
4791 if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
4792 ha->pdev->subsystem_device == 0x338e) {
4793 rval = qla2x00_read_sfp(vha, 0, &byte,
4794 0x98, 0x1, 1, BIT_15|BIT_14|BIT_0);
4795 *temp = byte;
4796 return rval;
4797 }
4798 ql_dbg(ql_dbg_mbx, vha, 0x10c9,
4799 "Thermal not supported by this card.\n");
4800 return rval;
794a5691 4801 }
794a5691 4802
1ae47cf3
JC		 4803 if (IS_QLA82XX(ha)) {
4804 *temp = qla82xx_read_temperature(vha);
4805 rval = QLA_SUCCESS;
4806 return rval;
4807 } else if (IS_QLA8044(ha)) {
4808 *temp = qla8044_read_temperature(vha);
4809 rval = QLA_SUCCESS;
4810 return rval;
794a5691 4811 }
794a5691 4812
1ae47cf3 4813 rval = qla2x00_read_asic_temperature(vha, temp);
794a5691
AV		 4814 return rval;
4815}
4816
a9083016
GM		 4817int
4818qla82xx_mbx_intr_enable(scsi_qla_host_t *vha)
4819{
4820 int rval;
4821 struct qla_hw_data *ha = vha->hw;
4822 mbx_cmd_t mc;
4823 mbx_cmd_t *mcp = &mc;
4824
5f28d2d7
SK		 4825 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1017,
4826 "Entered %s.\n", __func__);
7c3df132 4827
a9083016
GM		 4828 if (!IS_FWI2_CAPABLE(ha))
4829 return QLA_FUNCTION_FAILED;
4830
a9083016 4831 memset(mcp, 0, sizeof(mbx_cmd_t));
3711333d 4832 mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
a9083016
GM		 4833 mcp->mb[1] = 1;
4834
4835 mcp->out_mb = MBX_1|MBX_0;
4836 mcp->in_mb = MBX_0;
4837 mcp->tov = 30;
4838 mcp->flags = 0;
4839
4840 rval = qla2x00_mailbox_command(vha, mcp);
4841 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4842 ql_dbg(ql_dbg_mbx, vha, 0x1016,
4843 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
a9083016 4844 } else {
5f28d2d7
SK		 4845 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100e,
4846 "Done %s.\n", __func__);
a9083016
GM		 4847 }
4848
4849 return rval;
4850}
4851
4852int
4853qla82xx_mbx_intr_disable(scsi_qla_host_t *vha)
4854{
4855 int rval;
4856 struct qla_hw_data *ha = vha->hw;
4857 mbx_cmd_t mc;
4858 mbx_cmd_t *mcp = &mc;
4859
5f28d2d7
SK		 4860 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100d,
4861 "Entered %s.\n", __func__);
7c3df132 4862
7ec0effd 4863 if (!IS_P3P_TYPE(ha))
a9083016
GM		 4864 return QLA_FUNCTION_FAILED;
4865
a9083016 4866 memset(mcp, 0, sizeof(mbx_cmd_t));
3711333d 4867 mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
a9083016
GM		 4868 mcp->mb[1] = 0;
4869
4870 mcp->out_mb = MBX_1|MBX_0;
4871 mcp->in_mb = MBX_0;
4872 mcp->tov = 30;
4873 mcp->flags = 0;
4874
4875 rval = qla2x00_mailbox_command(vha, mcp);
4876 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4877 ql_dbg(ql_dbg_mbx, vha, 0x100c,
4878 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
a9083016 4879 } else {
5f28d2d7
SK		 4880 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100b,
4881 "Done %s.\n", __func__);
a9083016
GM		 4882 }
4883
4884 return rval;
4885}
08de2844
GM		 4886
4887int
4888qla82xx_md_get_template_size(scsi_qla_host_t *vha)
4889{
4890 struct qla_hw_data *ha = vha->hw;
4891 mbx_cmd_t mc;
4892 mbx_cmd_t *mcp = &mc;
4893 int rval = QLA_FUNCTION_FAILED;
4894
5f28d2d7
SK		 4895 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111f,
4896 "Entered %s.\n", __func__);
08de2844
GM		 4897
4898 memset(mcp->mb, 0 , sizeof(mcp->mb));
4899 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
4900 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
4901 mcp->mb[2] = LSW(RQST_TMPLT_SIZE);
4902 mcp->mb[3] = MSW(RQST_TMPLT_SIZE);
4903
4904 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
4905 mcp->in_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
4906 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4907
4908 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
4909 mcp->tov = MBX_TOV_SECONDS;
4910 rval = qla2x00_mailbox_command(vha, mcp);
4911
4912 /* Always copy back return mailbox values. */
4913 if (rval != QLA_SUCCESS) {
4914 ql_dbg(ql_dbg_mbx, vha, 0x1120,
4915 "mailbox command FAILED=0x%x, subcode=%x.\n",
4916 (mcp->mb[1] << 16) | mcp->mb[0],
4917 (mcp->mb[3] << 16) | mcp->mb[2]);
4918 } else {
5f28d2d7
SK		 4919 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1121,
4920 "Done %s.\n", __func__);
08de2844
GM		 4921 ha->md_template_size = ((mcp->mb[3] << 16) | mcp->mb[2]);
4922 if (!ha->md_template_size) {
4923 ql_dbg(ql_dbg_mbx, vha, 0x1122,
4924 "Null template size obtained.\n");
4925 rval = QLA_FUNCTION_FAILED;
4926 }
4927 }
4928 return rval;
4929}
4930
4931int
4932qla82xx_md_get_template(scsi_qla_host_t *vha)
4933{
4934 struct qla_hw_data *ha = vha->hw;
4935 mbx_cmd_t mc;
4936 mbx_cmd_t *mcp = &mc;
4937 int rval = QLA_FUNCTION_FAILED;
4938
5f28d2d7
SK		 4939 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1123,
4940 "Entered %s.\n", __func__);
08de2844
GM		 4941
4942 ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev,
4943 ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL);
4944 if (!ha->md_tmplt_hdr) {
4945 ql_log(ql_log_warn, vha, 0x1124,
4946 "Unable to allocate memory for Minidump template.\n");
4947 return rval;
4948 }
4949
4950 memset(mcp->mb, 0 , sizeof(mcp->mb));
4951 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
4952 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
4953 mcp->mb[2] = LSW(RQST_TMPLT);
4954 mcp->mb[3] = MSW(RQST_TMPLT);
4955 mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma));
4956 mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma));
4957 mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma));
4958 mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma));
4959 mcp->mb[8] = LSW(ha->md_template_size);
4960 mcp->mb[9] = MSW(ha->md_template_size);
4961
4962 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
4963 mcp->tov = MBX_TOV_SECONDS;
4964 mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8|
4965 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4966 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
4967 rval = qla2x00_mailbox_command(vha, mcp);
4968
4969 if (rval != QLA_SUCCESS) {
4970 ql_dbg(ql_dbg_mbx, vha, 0x1125,
4971 "mailbox command FAILED=0x%x, subcode=%x.\n",
4972 ((mcp->mb[1] << 16) | mcp->mb[0]),
4973 ((mcp->mb[3] << 16) | mcp->mb[2]));
4974 } else
5f28d2d7
SK		 4975 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1126,
4976 "Done %s.\n", __func__);
08de2844
GM		 4977 return rval;
4978}
999916dc 4979
7ec0effd
AD		 4980int
4981qla8044_md_get_template(scsi_qla_host_t *vha)
4982{
4983 struct qla_hw_data *ha = vha->hw;
4984 mbx_cmd_t mc;
4985 mbx_cmd_t *mcp = &mc;
4986 int rval = QLA_FUNCTION_FAILED;
4987 int offset = 0, size = MINIDUMP_SIZE_36K;
4988 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11f,
4989 "Entered %s.\n", __func__);
4990
4991 ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev,
4992 ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL);
4993 if (!ha->md_tmplt_hdr) {
4994 ql_log(ql_log_warn, vha, 0xb11b,
4995 "Unable to allocate memory for Minidump template.\n");
4996 return rval;
4997 }
4998
4999 memset(mcp->mb, 0 , sizeof(mcp->mb));
5000 while (offset < ha->md_template_size) {
5001 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5002 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5003 mcp->mb[2] = LSW(RQST_TMPLT);
5004 mcp->mb[3] = MSW(RQST_TMPLT);
5005 mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma + offset));
5006 mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma + offset));
5007 mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma + offset));
5008 mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma + offset));
5009 mcp->mb[8] = LSW(size);
5010 mcp->mb[9] = MSW(size);
5011 mcp->mb[10] = offset & 0x0000FFFF;
5012 mcp->mb[11] = offset & 0xFFFF0000;
5013 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
5014 mcp->tov = MBX_TOV_SECONDS;
5015 mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8|
5016 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5017 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
5018 rval = qla2x00_mailbox_command(vha, mcp);
5019
5020 if (rval != QLA_SUCCESS) {
5021 ql_dbg(ql_dbg_mbx, vha, 0xb11c,
5022 "mailbox command FAILED=0x%x, subcode=%x.\n",
5023 ((mcp->mb[1] << 16) | mcp->mb[0]),
5024 ((mcp->mb[3] << 16) | mcp->mb[2]));
5025 return rval;
5026 } else
5027 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11d,
5028 "Done %s.\n", __func__);
5029 offset = offset + size;
5030 }
5031 return rval;
5032}
5033
6246b8a1
GM		 5034int
5035qla81xx_set_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg)
5036{
5037 int rval;
5038 struct qla_hw_data *ha = vha->hw;
5039 mbx_cmd_t mc;
5040 mbx_cmd_t *mcp = &mc;
5041
5042 if (!IS_QLA81XX(ha) && !IS_QLA8031(ha))
5043 return QLA_FUNCTION_FAILED;
5044
5f28d2d7
SK		 5045 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1133,
5046 "Entered %s.\n", __func__);
6246b8a1
GM		 5047
5048 memset(mcp, 0, sizeof(mbx_cmd_t));
5049 mcp->mb[0] = MBC_SET_LED_CONFIG;
5050 mcp->mb[1] = led_cfg[0];
5051 mcp->mb[2] = led_cfg[1];
5052 if (IS_QLA8031(ha)) {
5053 mcp->mb[3] = led_cfg[2];
5054 mcp->mb[4] = led_cfg[3];
5055 mcp->mb[5] = led_cfg[4];
5056 mcp->mb[6] = led_cfg[5];
5057 }
5058
5059 mcp->out_mb = MBX_2|MBX_1|MBX_0;
5060 if (IS_QLA8031(ha))
5061 mcp->out_mb |= MBX_6|MBX_5|MBX_4|MBX_3;
5062 mcp->in_mb = MBX_0;
5063 mcp->tov = 30;
5064 mcp->flags = 0;
5065
5066 rval = qla2x00_mailbox_command(vha, mcp);
5067 if (rval != QLA_SUCCESS) {
5068 ql_dbg(ql_dbg_mbx, vha, 0x1134,
5069 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5070 } else {
5f28d2d7
SK		 5071 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1135,
5072 "Done %s.\n", __func__);
6246b8a1
GM		 5073 }
5074
5075 return rval;
5076}
5077
5078int
5079qla81xx_get_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg)
5080{
5081 int rval;
5082 struct qla_hw_data *ha = vha->hw;
5083 mbx_cmd_t mc;
5084 mbx_cmd_t *mcp = &mc;
5085
5086 if (!IS_QLA81XX(ha) && !IS_QLA8031(ha))
5087 return QLA_FUNCTION_FAILED;
5088
5f28d2d7
SK		 5089 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1136,
5090 "Entered %s.\n", __func__);
6246b8a1
GM		 5091
5092 memset(mcp, 0, sizeof(mbx_cmd_t));
5093 mcp->mb[0] = MBC_GET_LED_CONFIG;
5094
5095 mcp->out_mb = MBX_0;
5096 mcp->in_mb = MBX_2|MBX_1|MBX_0;
5097 if (IS_QLA8031(ha))
5098 mcp->in_mb |= MBX_6|MBX_5|MBX_4|MBX_3;
5099 mcp->tov = 30;
5100 mcp->flags = 0;
5101
5102 rval = qla2x00_mailbox_command(vha, mcp);
5103 if (rval != QLA_SUCCESS) {
5104 ql_dbg(ql_dbg_mbx, vha, 0x1137,
5105 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5106 } else {
5107 led_cfg[0] = mcp->mb[1];
5108 led_cfg[1] = mcp->mb[2];
5109 if (IS_QLA8031(ha)) {
5110 led_cfg[2] = mcp->mb[3];
5111 led_cfg[3] = mcp->mb[4];
5112 led_cfg[4] = mcp->mb[5];
5113 led_cfg[5] = mcp->mb[6];
5114 }
5f28d2d7
SK		 5115 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1138,
5116 "Done %s.\n", __func__);
6246b8a1
GM		 5117 }
5118
5119 return rval;
5120}
5121
999916dc
SK		 5122int
5123qla82xx_mbx_beacon_ctl(scsi_qla_host_t *vha, int enable)
5124{
5125 int rval;
5126 struct qla_hw_data *ha = vha->hw;
5127 mbx_cmd_t mc;
5128 mbx_cmd_t *mcp = &mc;
5129
7ec0effd 5130 if (!IS_P3P_TYPE(ha))
999916dc
SK		 5131 return QLA_FUNCTION_FAILED;
5132
5f28d2d7 5133 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1127,
999916dc
SK		 5134 "Entered %s.\n", __func__);
5135
5136 memset(mcp, 0, sizeof(mbx_cmd_t));
5137 mcp->mb[0] = MBC_SET_LED_CONFIG;
5138 if (enable)
5139 mcp->mb[7] = 0xE;
5140 else
5141 mcp->mb[7] = 0xD;
5142
5143 mcp->out_mb = MBX_7|MBX_0;
5144 mcp->in_mb = MBX_0;
6246b8a1 5145 mcp->tov = MBX_TOV_SECONDS;
999916dc
SK		 5146 mcp->flags = 0;
5147
5148 rval = qla2x00_mailbox_command(vha, mcp);
5149 if (rval != QLA_SUCCESS) {
5150 ql_dbg(ql_dbg_mbx, vha, 0x1128,
5151 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5152 } else {
5f28d2d7 5153 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1129,
999916dc
SK		 5154 "Done %s.\n", __func__);
5155 }
5156
5157 return rval;
5158}
6246b8a1
GM		 5159
5160int
7d613ac6 5161qla83xx_wr_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t data)
6246b8a1
GM		 5162{
5163 int rval;
5164 struct qla_hw_data *ha = vha->hw;
5165 mbx_cmd_t mc;
5166 mbx_cmd_t *mcp = &mc;
5167
f73cb695 5168 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
6246b8a1
GM		 5169 return QLA_FUNCTION_FAILED;
5170
5f28d2d7
SK		 5171 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1130,
5172 "Entered %s.\n", __func__);
6246b8a1
GM		 5173
5174 mcp->mb[0] = MBC_WRITE_REMOTE_REG;
5175 mcp->mb[1] = LSW(reg);
5176 mcp->mb[2] = MSW(reg);
5177 mcp->mb[3] = LSW(data);
5178 mcp->mb[4] = MSW(data);
5179 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5180
5181 mcp->in_mb = MBX_1|MBX_0;
5182 mcp->tov = MBX_TOV_SECONDS;
5183 mcp->flags = 0;
5184 rval = qla2x00_mailbox_command(vha, mcp);
5185
5186 if (rval != QLA_SUCCESS) {
5187 ql_dbg(ql_dbg_mbx, vha, 0x1131,
5188 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5189 } else {
5f28d2d7 5190 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1132,
6246b8a1
GM		 5191 "Done %s.\n", __func__);
5192 }
af11f64d 5193
6246b8a1
GM		 5194 return rval;
5195}
af11f64d
AV		 5196
5197int
5198qla2x00_port_logout(scsi_qla_host_t *vha, struct fc_port *fcport)
5199{
5200 int rval;
5201 struct qla_hw_data *ha = vha->hw;
5202 mbx_cmd_t mc;
5203 mbx_cmd_t *mcp = &mc;
5204
5205 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
5f28d2d7 5206 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113b,
af11f64d
AV		 5207 "Implicit LOGO Unsupported.\n");
5208 return QLA_FUNCTION_FAILED;
5209 }
5210
5211
5f28d2d7
SK		 5212 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113c,
5213 "Entering %s.\n", __func__);
af11f64d
AV		 5214
5215 /* Perform Implicit LOGO. */
5216 mcp->mb[0] = MBC_PORT_LOGOUT;
5217 mcp->mb[1] = fcport->loop_id;
5218 mcp->mb[10] = BIT_15;
5219 mcp->out_mb = MBX_10|MBX_1|MBX_0;
5220 mcp->in_mb = MBX_0;
5221 mcp->tov = MBX_TOV_SECONDS;
5222 mcp->flags = 0;
5223 rval = qla2x00_mailbox_command(vha, mcp);
5224 if (rval != QLA_SUCCESS)
5225 ql_dbg(ql_dbg_mbx, vha, 0x113d,
5226 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5227 else
5f28d2d7
SK		 5228 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113e,
5229 "Done %s.\n", __func__);
af11f64d
AV		 5230
5231 return rval;
5232}
5233
7d613ac6
SV		 5234int
5235qla83xx_rd_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t *data)
5236{
5237 int rval;
5238 mbx_cmd_t mc;
5239 mbx_cmd_t *mcp = &mc;
5240 struct qla_hw_data *ha = vha->hw;
5241 unsigned long retry_max_time = jiffies + (2 * HZ);
5242
f73cb695 5243 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
7d613ac6
SV		 5244 return QLA_FUNCTION_FAILED;
5245
5246 ql_dbg(ql_dbg_mbx, vha, 0x114b, "Entered %s.\n", __func__);
5247
5248retry_rd_reg:
5249 mcp->mb[0] = MBC_READ_REMOTE_REG;
5250 mcp->mb[1] = LSW(reg);
5251 mcp->mb[2] = MSW(reg);
5252 mcp->out_mb = MBX_2|MBX_1|MBX_0;
5253 mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0;
5254 mcp->tov = MBX_TOV_SECONDS;
5255 mcp->flags = 0;
5256 rval = qla2x00_mailbox_command(vha, mcp);
5257
5258 if (rval != QLA_SUCCESS) {
5259 ql_dbg(ql_dbg_mbx, vha, 0x114c,
5260 "Failed=%x mb[0]=%x mb[1]=%x.\n",
5261 rval, mcp->mb[0], mcp->mb[1]);
5262 } else {
5263 *data = (mcp->mb[3] | (mcp->mb[4] << 16));
5264 if (*data == QLA8XXX_BAD_VALUE) {
5265 /*
5266 * During soft-reset CAMRAM register reads might
5267 * return 0xbad0bad0. So retry for MAX of 2 sec
5268 * while reading camram registers.
5269 */
5270 if (time_after(jiffies, retry_max_time)) {
5271 ql_dbg(ql_dbg_mbx, vha, 0x1141,
5272 "Failure to read CAMRAM register. "
5273 "data=0x%x.\n", *data);
5274 return QLA_FUNCTION_FAILED;
5275 }
5276 msleep(100);
5277 goto retry_rd_reg;
5278 }
5279 ql_dbg(ql_dbg_mbx, vha, 0x1142, "Done %s.\n", __func__);
5280 }
5281
5282 return rval;
5283}
5284
5285int
5286qla83xx_restart_nic_firmware(scsi_qla_host_t *vha)
5287{
5288 int rval;
5289 mbx_cmd_t mc;
5290 mbx_cmd_t *mcp = &mc;
5291 struct qla_hw_data *ha = vha->hw;
5292
5293 if (!IS_QLA83XX(ha))
5294 return QLA_FUNCTION_FAILED;
5295
5296 ql_dbg(ql_dbg_mbx, vha, 0x1143, "Entered %s.\n", __func__);
5297
5298 mcp->mb[0] = MBC_RESTART_NIC_FIRMWARE;
5299 mcp->out_mb = MBX_0;
5300 mcp->in_mb = MBX_1|MBX_0;
5301 mcp->tov = MBX_TOV_SECONDS;
5302 mcp->flags = 0;
5303 rval = qla2x00_mailbox_command(vha, mcp);
5304
5305 if (rval != QLA_SUCCESS) {
5306 ql_dbg(ql_dbg_mbx, vha, 0x1144,
5307 "Failed=%x mb[0]=%x mb[1]=%x.\n",
5308 rval, mcp->mb[0], mcp->mb[1]);
5309 ha->isp_ops->fw_dump(vha, 0);
5310 } else {
5311 ql_dbg(ql_dbg_mbx, vha, 0x1145, "Done %s.\n", __func__);
5312 }
5313
5314 return rval;
5315}
5316
5317int
5318qla83xx_access_control(scsi_qla_host_t *vha, uint16_t options,
5319 uint32_t start_addr, uint32_t end_addr, uint16_t *sector_size)
5320{
5321 int rval;
5322 mbx_cmd_t mc;
5323 mbx_cmd_t *mcp = &mc;
5324 uint8_t subcode = (uint8_t)options;
5325 struct qla_hw_data *ha = vha->hw;
5326
5327 if (!IS_QLA8031(ha))
5328 return QLA_FUNCTION_FAILED;
5329
5330 ql_dbg(ql_dbg_mbx, vha, 0x1146, "Entered %s.\n", __func__);
5331
5332 mcp->mb[0] = MBC_SET_ACCESS_CONTROL;
5333 mcp->mb[1] = options;
5334 mcp->out_mb = MBX_1|MBX_0;
5335 if (subcode & BIT_2) {
5336 mcp->mb[2] = LSW(start_addr);
5337 mcp->mb[3] = MSW(start_addr);
5338 mcp->mb[4] = LSW(end_addr);
5339 mcp->mb[5] = MSW(end_addr);
5340 mcp->out_mb |= MBX_5|MBX_4|MBX_3|MBX_2;
5341 }
5342 mcp->in_mb = MBX_2|MBX_1|MBX_0;
5343 if (!(subcode & (BIT_2 | BIT_5)))
5344 mcp->in_mb |= MBX_4|MBX_3;
5345 mcp->tov = MBX_TOV_SECONDS;
5346 mcp->flags = 0;
5347 rval = qla2x00_mailbox_command(vha, mcp);
5348
5349 if (rval != QLA_SUCCESS) {
5350 ql_dbg(ql_dbg_mbx, vha, 0x1147,
5351 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[4]=%x.\n",
5352 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3],
5353 mcp->mb[4]);
5354 ha->isp_ops->fw_dump(vha, 0);
5355 } else {
5356 if (subcode & BIT_5)
5357 *sector_size = mcp->mb[1];
5358 else if (subcode & (BIT_6 | BIT_7)) {
5359 ql_dbg(ql_dbg_mbx, vha, 0x1148,
5360 "Driver-lock id=%x%x", mcp->mb[4], mcp->mb[3]);
5361 } else if (subcode & (BIT_3 | BIT_4)) {
5362 ql_dbg(ql_dbg_mbx, vha, 0x1149,
5363 "Flash-lock id=%x%x", mcp->mb[4], mcp->mb[3]);
5364 }
5365 ql_dbg(ql_dbg_mbx, vha, 0x114a, "Done %s.\n", __func__);
5366 }
5367
5368 return rval;
5369}
81178772
SK		 5370
5371int
5372qla2x00_dump_mctp_data(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr,
5373 uint32_t size)
5374{
5375 int rval;
5376 mbx_cmd_t mc;
5377 mbx_cmd_t *mcp = &mc;
5378
5379 if (!IS_MCTP_CAPABLE(vha->hw))
5380 return QLA_FUNCTION_FAILED;
5381
5382 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114f,
5383 "Entered %s.\n", __func__);
5384
5385 mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED;
5386 mcp->mb[1] = LSW(addr);
5387 mcp->mb[2] = MSW(req_dma);
5388 mcp->mb[3] = LSW(req_dma);
5389 mcp->mb[4] = MSW(size);
5390 mcp->mb[5] = LSW(size);
5391 mcp->mb[6] = MSW(MSD(req_dma));
5392 mcp->mb[7] = LSW(MSD(req_dma));
5393 mcp->mb[8] = MSW(addr);
5394 /* Setting RAM ID to valid */
5395 mcp->mb[10] |= BIT_7;
5396 /* For MCTP RAM ID is 0x40 */
5397 mcp->mb[10] |= 0x40;
5398
5399 mcp->out_mb |= MBX_10|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|
5400 MBX_0;
5401
5402 mcp->in_mb = MBX_0;
5403 mcp->tov = MBX_TOV_SECONDS;
5404 mcp->flags = 0;
5405 rval = qla2x00_mailbox_command(vha, mcp);
5406
5407 if (rval != QLA_SUCCESS) {
5408 ql_dbg(ql_dbg_mbx, vha, 0x114e,
5409 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5410 } else {
5411 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114d,
5412 "Done %s.\n", __func__);
5413 }
5414
5415 return rval;
5416}
Ubuntu Artful kernel mirror