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UBUNTU: Ubuntu-5.11.0-22.23
[mirror_ubuntu-hirsute-kernel.git] / drivers / scsi / qla2xxx / qla_mbx.c
CommitLineData
77adf3f0 1// SPDX-License-Identifier: GPL-2.0-only
1da177e4 2/*
fa90c54f 3 * QLogic Fibre Channel HBA Driver
bd21eaf9 4 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4
LT		 5 */
6#include "qla_def.h"
2d70c103 7#include "qla_target.h"
1da177e4
LT		 8
9#include <linux/delay.h>
5a0e3ad6 10#include <linux/gfp.h>
1da177e4 11
15f30a57
QT		 12static struct mb_cmd_name {
13 uint16_t cmd;
14 const char *str;
15} mb_str[] = {
16 {MBC_GET_PORT_DATABASE, "GPDB"},
17 {MBC_GET_ID_LIST, "GIDList"},
18 {MBC_GET_LINK_PRIV_STATS, "Stats"},
94d83e36 19 {MBC_GET_RESOURCE_COUNTS, "ResCnt"},
15f30a57
QT		 20};
21
22static const char *mb_to_str(uint16_t cmd)
23{
24 int i;
25 struct mb_cmd_name *e;
26
27 for (i = 0; i < ARRAY_SIZE(mb_str); i++) {
28 e = mb_str + i;
29 if (cmd == e->cmd)
30 return e->str;
31 }
32 return "unknown";
33}
34
ca825828 35static struct rom_cmd {
77ddb94a 36 uint16_t cmd;
37} rom_cmds[] = {
38 { MBC_LOAD_RAM },
39 { MBC_EXECUTE_FIRMWARE },
40 { MBC_READ_RAM_WORD },
41 { MBC_MAILBOX_REGISTER_TEST },
42 { MBC_VERIFY_CHECKSUM },
43 { MBC_GET_FIRMWARE_VERSION },
44 { MBC_LOAD_RISC_RAM },
45 { MBC_DUMP_RISC_RAM },
46 { MBC_LOAD_RISC_RAM_EXTENDED },
47 { MBC_DUMP_RISC_RAM_EXTENDED },
48 { MBC_WRITE_RAM_WORD_EXTENDED },
49 { MBC_READ_RAM_EXTENDED },
50 { MBC_GET_RESOURCE_COUNTS },
51 { MBC_SET_FIRMWARE_OPTION },
52 { MBC_MID_INITIALIZE_FIRMWARE },
53 { MBC_GET_FIRMWARE_STATE },
54 { MBC_GET_MEM_OFFLOAD_CNTRL_STAT },
55 { MBC_GET_RETRY_COUNT },
56 { MBC_TRACE_CONTROL },
b7edfa23 57 { MBC_INITIALIZE_MULTIQ },
1608cc4a
QT		 58 { MBC_IOCB_COMMAND_A64 },
59 { MBC_GET_ADAPTER_LOOP_ID },
e4e3a2ce 60 { MBC_READ_SFP },
62e9dd17 61 { MBC_SET_RNID_PARAMS },
8777e431 62 { MBC_GET_RNID_PARAMS },
8b4673ba 63 { MBC_GET_SET_ZIO_THRESHOLD },
77ddb94a 64};
65
66static int is_rom_cmd(uint16_t cmd)
67{
68 int i;
69 struct rom_cmd *wc;
70
71 for (i = 0; i < ARRAY_SIZE(rom_cmds); i++) {
72 wc = rom_cmds + i;
73 if (wc->cmd == cmd)
74 return 1;
75 }
76
77 return 0;
78}
1da177e4
LT		 79
80/*
81 * qla2x00_mailbox_command
82 * Issue mailbox command and waits for completion.
83 *
84 * Input:
85 * ha = adapter block pointer.
86 * mcp = driver internal mbx struct pointer.
87 *
88 * Output:
89 * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data.
90 *
91 * Returns:
92 * 0 : QLA_SUCCESS = cmd performed success
93 * 1 : QLA_FUNCTION_FAILED (error encountered)
94 * 6 : QLA_FUNCTION_TIMEOUT (timeout condition encountered)
95 *
96 * Context:
97 * Kernel context.
98 */
99static int
7b867cf7 100qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp)
1da177e4 101{
d14e72fb 102 int rval, i;
1da177e4 103 unsigned long flags = 0;
f73cb695 104 device_reg_t *reg;
1c7c6357 105 uint8_t abort_active;
2c3dfe3f 106 uint8_t io_lock_on;
cdbb0a4f 107 uint16_t command = 0;
1da177e4 108 uint16_t *iptr;
37139da1 109 __le16 __iomem *optr;
1da177e4
LT		 110 uint32_t cnt;
111 uint32_t mboxes;
1da177e4 112 unsigned long wait_time;
7b867cf7
AC		 113 struct qla_hw_data *ha = vha->hw;
114 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
b2000805 115 u32 chip_reset;
2c3dfe3f 116
d14e72fb 117
5e19ed90 118 ql_dbg(ql_dbg_mbx, vha, 0x1000, "Entered %s.\n", __func__);
7c3df132 119
471298ca 120 if (ha->pdev->error_state == pci_channel_io_perm_failure) {
5e19ed90 121 ql_log(ql_log_warn, vha, 0x1001,
471298ca 122 "PCI channel failed permanently, exiting.\n");
b9b12f73 123 return QLA_FUNCTION_TIMEOUT;
7c3df132 124 }
b9b12f73 125
a9083016 126 if (vha->device_flags & DFLG_DEV_FAILED) {
5e19ed90 127 ql_log(ql_log_warn, vha, 0x1002,
7c3df132 128 "Device in failed state, exiting.\n");
a9083016
GM		 129 return QLA_FUNCTION_TIMEOUT;
130 }
131
c2a5d94f 132 /* if PCI error, then avoid mbx processing.*/
ba175891
SC		 133 if (test_bit(PFLG_DISCONNECTED, &base_vha->dpc_flags) &&
134 test_bit(UNLOADING, &base_vha->dpc_flags)) {
83548fe2 135 ql_log(ql_log_warn, vha, 0xd04e,
783e0dc4
SC		 136 "PCI error, exiting.\n");
137 return QLA_FUNCTION_TIMEOUT;
c2a5d94f 138 }
783e0dc4 139
2c3dfe3f 140 reg = ha->iobase;
7b867cf7 141 io_lock_on = base_vha->flags.init_done;
1da177e4
LT		 142
143 rval = QLA_SUCCESS;
7b867cf7 144 abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
b2000805 145 chip_reset = ha->chip_reset;
1da177e4 146
85880801 147 if (ha->flags.pci_channel_io_perm_failure) {
5e19ed90 148 ql_log(ql_log_warn, vha, 0x1003,
7c3df132 149 "Perm failure on EEH timeout MBX, exiting.\n");
85880801
AV		 150 return QLA_FUNCTION_TIMEOUT;
151 }
152
7ec0effd 153 if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) {
862cd01e
GM		 154 /* Setting Link-Down error */
155 mcp->mb[0] = MBS_LINK_DOWN_ERROR;
5e19ed90 156 ql_log(ql_log_warn, vha, 0x1004,
7c3df132 157 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
1806fcd5 158 return QLA_FUNCTION_TIMEOUT;
862cd01e
GM		 159 }
160
77ddb94a 161 /* check if ISP abort is active and return cmd with timeout */
162 if ((test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
163 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
164 test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) &&
165 !is_rom_cmd(mcp->mb[0])) {
166 ql_log(ql_log_info, vha, 0x1005,
167 "Cmd 0x%x aborted with timeout since ISP Abort is pending\n",
168 mcp->mb[0]);
169 return QLA_FUNCTION_TIMEOUT;
170 }
171
b2000805 172 atomic_inc(&ha->num_pend_mbx_stage1);
1da177e4 173 /*
1c7c6357
AV		 174 * Wait for active mailbox commands to finish by waiting at most tov
175 * seconds. This is to serialize actual issuing of mailbox cmds during
176 * non ISP abort time.
1da177e4 177 */
8eca3f39
AV		 178 if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) {
179 /* Timeout occurred. Return error. */
83548fe2 180 ql_log(ql_log_warn, vha, 0xd035,
d8c0d546
CD		 181 "Cmd access timeout, cmd=0x%x, Exiting.\n",
182 mcp->mb[0]);
b2000805 183 atomic_dec(&ha->num_pend_mbx_stage1);
8eca3f39 184 return QLA_FUNCTION_TIMEOUT;
1da177e4 185 }
b2000805
QT		 186 atomic_dec(&ha->num_pend_mbx_stage1);
187 if (ha->flags.purge_mbox || chip_reset != ha->chip_reset) {
188 rval = QLA_ABORTED;
189 goto premature_exit;
190 }
1da177e4 191
b6faaaf7 192
1da177e4
LT		 193 /* Save mailbox command for debug */
194 ha->mcp = mcp;
195
5e19ed90 196 ql_dbg(ql_dbg_mbx, vha, 0x1006,
7c3df132 197 "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]);
1da177e4
LT		 198
199 spin_lock_irqsave(&ha->hardware_lock, flags);
200
b6faaaf7
QT		 201 if (ha->flags.purge_mbox || chip_reset != ha->chip_reset ||
202 ha->flags.mbox_busy) {
b2000805 203 rval = QLA_ABORTED;
b2000805
QT		 204 spin_unlock_irqrestore(&ha->hardware_lock, flags);
205 goto premature_exit;
206 }
b6faaaf7 207 ha->flags.mbox_busy = 1;
b2000805 208
1da177e4 209 /* Load mailbox registers. */
7ec0effd 210 if (IS_P3P_TYPE(ha))
7ffa5b93 211 optr = &reg->isp82.mailbox_in[0];
7ec0effd 212 else if (IS_FWI2_CAPABLE(ha) && !(IS_P3P_TYPE(ha)))
7ffa5b93 213 optr = &reg->isp24.mailbox0;
1c7c6357 214 else
7ffa5b93 215 optr = MAILBOX_REG(ha, &reg->isp, 0);
1da177e4
LT		 216
217 iptr = mcp->mb;
218 command = mcp->mb[0];
219 mboxes = mcp->out_mb;
220
7b711623 221 ql_dbg(ql_dbg_mbx, vha, 0x1111,
0e31a2c8 222 "Mailbox registers (OUT):\n");
1da177e4
LT		 223 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
224 if (IS_QLA2200(ha) && cnt == 8)
7ffa5b93 225 optr = MAILBOX_REG(ha, &reg->isp, 8);
0e31a2c8
JC		 226 if (mboxes & BIT_0) {
227 ql_dbg(ql_dbg_mbx, vha, 0x1112,
228 "mbox[%d]<-0x%04x\n", cnt, *iptr);
04474d3a 229 wrt_reg_word(optr, *iptr);
0e31a2c8 230 }
1da177e4
LT		 231
232 mboxes >>= 1;
233 optr++;
234 iptr++;
235 }
236
5e19ed90 237 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1117,
7c3df132 238 "I/O Address = %p.\n", optr);
1da177e4
LT		 239
240 /* Issue set host interrupt command to send cmd out. */
241 ha->flags.mbox_int = 0;
242 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
243
244 /* Unlock mbx registers and wait for interrupt */
5e19ed90 245 ql_dbg(ql_dbg_mbx, vha, 0x100f,
7c3df132
SK		 246 "Going to unlock irq & waiting for interrupts. "
247 "jiffies=%lx.\n", jiffies);
1da177e4
LT		 248
249 /* Wait for mbx cmd completion until timeout */
b2000805 250 atomic_inc(&ha->num_pend_mbx_stage2);
124f85e6 251 if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) {
1da177e4
LT		 252 set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
253
32a13df2 254 if (IS_P3P_TYPE(ha))
04474d3a 255 wrt_reg_dword(&reg->isp82.hint, HINT_MBX_INT_PENDING);
32a13df2 256 else if (IS_FWI2_CAPABLE(ha))
04474d3a 257 wrt_reg_dword(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
1c7c6357 258 else
04474d3a 259 wrt_reg_word(&reg->isp.hccr, HCCR_SET_HOST_INT);
1da177e4
LT		 260 spin_unlock_irqrestore(&ha->hardware_lock, flags);
261
77ddb94a 262 wait_time = jiffies;
b2000805 263 atomic_inc(&ha->num_pend_mbx_stage3);
754d1243
GM		 264 if (!wait_for_completion_timeout(&ha->mbx_intr_comp,
265 mcp->tov * HZ)) {
b6faaaf7
QT		 266 if (chip_reset != ha->chip_reset) {
267 spin_lock_irqsave(&ha->hardware_lock, flags);
268 ha->flags.mbox_busy = 0;
269 spin_unlock_irqrestore(&ha->hardware_lock,
270 flags);
271 atomic_dec(&ha->num_pend_mbx_stage2);
272 atomic_dec(&ha->num_pend_mbx_stage3);
273 rval = QLA_ABORTED;
274 goto premature_exit;
275 }
754d1243
GM		 276 ql_dbg(ql_dbg_mbx, vha, 0x117a,
277 "cmd=%x Timeout.\n", command);
278 spin_lock_irqsave(&ha->hardware_lock, flags);
279 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
280 spin_unlock_irqrestore(&ha->hardware_lock, flags);
b2000805
QT		 281
282 } else if (ha->flags.purge_mbox ||
283 chip_reset != ha->chip_reset) {
b6faaaf7 284 spin_lock_irqsave(&ha->hardware_lock, flags);
b2000805 285 ha->flags.mbox_busy = 0;
b6faaaf7 286 spin_unlock_irqrestore(&ha->hardware_lock, flags);
b2000805
QT		 287 atomic_dec(&ha->num_pend_mbx_stage2);
288 atomic_dec(&ha->num_pend_mbx_stage3);
289 rval = QLA_ABORTED;
290 goto premature_exit;
754d1243 291 }
b2000805
QT		 292 atomic_dec(&ha->num_pend_mbx_stage3);
293
77ddb94a 294 if (time_after(jiffies, wait_time + 5 * HZ))
295 ql_log(ql_log_warn, vha, 0x1015, "cmd=0x%x, waited %d msecs\n",
296 command, jiffies_to_msecs(jiffies - wait_time));
1da177e4 297 } else {
5e19ed90 298 ql_dbg(ql_dbg_mbx, vha, 0x1011,
7c3df132 299 "Cmd=%x Polling Mode.\n", command);
1da177e4 300
7ec0effd 301 if (IS_P3P_TYPE(ha)) {
04474d3a 302 if (rd_reg_dword(&reg->isp82.hint) &
a9083016 303 HINT_MBX_INT_PENDING) {
b6faaaf7 304 ha->flags.mbox_busy = 0;
a9083016
GM		 305 spin_unlock_irqrestore(&ha->hardware_lock,
306 flags);
b2000805 307 atomic_dec(&ha->num_pend_mbx_stage2);
5e19ed90 308 ql_dbg(ql_dbg_mbx, vha, 0x1012,
7c3df132 309 "Pending mailbox timeout, exiting.\n");
cdbb0a4f
SV		 310 rval = QLA_FUNCTION_TIMEOUT;
311 goto premature_exit;
a9083016 312 }
04474d3a 313 wrt_reg_dword(&reg->isp82.hint, HINT_MBX_INT_PENDING);
a9083016 314 } else if (IS_FWI2_CAPABLE(ha))
04474d3a 315 wrt_reg_dword(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
1c7c6357 316 else
04474d3a 317 wrt_reg_word(&reg->isp.hccr, HCCR_SET_HOST_INT);
1da177e4 318 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4
LT		 319
320 wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */
321 while (!ha->flags.mbox_int) {
b2000805
QT		 322 if (ha->flags.purge_mbox ||
323 chip_reset != ha->chip_reset) {
b6faaaf7 324 spin_lock_irqsave(&ha->hardware_lock, flags);
b2000805 325 ha->flags.mbox_busy = 0;
b6faaaf7
QT		 326 spin_unlock_irqrestore(&ha->hardware_lock,
327 flags);
b2000805
QT		 328 atomic_dec(&ha->num_pend_mbx_stage2);
329 rval = QLA_ABORTED;
330 goto premature_exit;
331 }
332
1da177e4
LT		 333 if (time_after(jiffies, wait_time))
334 break;
335
336 /* Check for pending interrupts. */
73208dfd 337 qla2x00_poll(ha->rsp_q_map[0]);
1da177e4 338
85880801
AV		 339 if (!ha->flags.mbox_int &&
340 !(IS_QLA2200(ha) &&
341 command == MBC_LOAD_RISC_RAM_EXTENDED))
59989831 342 msleep(10);
1da177e4 343 } /* while */
5e19ed90 344 ql_dbg(ql_dbg_mbx, vha, 0x1013,
7c3df132
SK		 345 "Waited %d sec.\n",
346 (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ));
1da177e4 347 }
b2000805 348 atomic_dec(&ha->num_pend_mbx_stage2);
1da177e4 349
1da177e4
LT		 350 /* Check whether we timed out */
351 if (ha->flags.mbox_int) {
352 uint16_t *iptr2;
353
5e19ed90 354 ql_dbg(ql_dbg_mbx, vha, 0x1014,
7c3df132 355 "Cmd=%x completed.\n", command);
1da177e4
LT		 356
357 /* Got interrupt. Clear the flag. */
358 ha->flags.mbox_int = 0;
359 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
360
7ec0effd 361 if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) {
b6faaaf7 362 spin_lock_irqsave(&ha->hardware_lock, flags);
cdbb0a4f 363 ha->flags.mbox_busy = 0;
b6faaaf7
QT		 364 spin_unlock_irqrestore(&ha->hardware_lock, flags);
365
cdbb0a4f
SV		 366 /* Setting Link-Down error */
367 mcp->mb[0] = MBS_LINK_DOWN_ERROR;
368 ha->mcp = NULL;
369 rval = QLA_FUNCTION_FAILED;
83548fe2 370 ql_log(ql_log_warn, vha, 0xd048,
7c3df132 371 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
cdbb0a4f
SV		 372 goto premature_exit;
373 }
374
b3e9772d
BVA		 375 if (ha->mailbox_out[0] != MBS_COMMAND_COMPLETE) {
376 ql_dbg(ql_dbg_mbx, vha, 0x11ff,
377 "mb_out[0] = %#x <> %#x\n", ha->mailbox_out[0],
378 MBS_COMMAND_COMPLETE);
1da177e4 379 rval = QLA_FUNCTION_FAILED;
b3e9772d 380 }
1da177e4
LT		 381
382 /* Load return mailbox registers. */
383 iptr2 = mcp->mb;
384 iptr = (uint16_t *)&ha->mailbox_out[0];
385 mboxes = mcp->in_mb;
0e31a2c8
JC		 386
387 ql_dbg(ql_dbg_mbx, vha, 0x1113,
388 "Mailbox registers (IN):\n");
1da177e4 389 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
0e31a2c8 390 if (mboxes & BIT_0) {
1da177e4 391 *iptr2 = *iptr;
0e31a2c8
JC		 392 ql_dbg(ql_dbg_mbx, vha, 0x1114,
393 "mbox[%d]->0x%04x\n", cnt, *iptr2);
394 }
1da177e4
LT		 395
396 mboxes >>= 1;
397 iptr2++;
398 iptr++;
399 }
400 } else {
401
8d3c9c23
QT		 402 uint16_t mb[8];
403 uint32_t ictrl, host_status, hccr;
783e0dc4 404 uint16_t w;
1c7c6357 405
e428924c 406 if (IS_FWI2_CAPABLE(ha)) {
04474d3a
BVA		 407 mb[0] = rd_reg_word(&reg->isp24.mailbox0);
408 mb[1] = rd_reg_word(&reg->isp24.mailbox1);
409 mb[2] = rd_reg_word(&reg->isp24.mailbox2);
410 mb[3] = rd_reg_word(&reg->isp24.mailbox3);
411 mb[7] = rd_reg_word(&reg->isp24.mailbox7);
412 ictrl = rd_reg_dword(&reg->isp24.ictrl);
413 host_status = rd_reg_dword(&reg->isp24.host_status);
414 hccr = rd_reg_dword(&reg->isp24.hccr);
8d3c9c23 415
83548fe2 416 ql_log(ql_log_warn, vha, 0xd04c,
8d3c9c23
QT		 417 "MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx "
418 "mb[0-3]=[0x%x 0x%x 0x%x 0x%x] mb7 0x%x host_status 0x%x hccr 0x%x\n",
419 command, ictrl, jiffies, mb[0], mb[1], mb[2], mb[3],
420 mb[7], host_status, hccr);
421
1c7c6357 422 } else {
8d3c9c23 423 mb[0] = RD_MAILBOX_REG(ha, &reg->isp, 0);
04474d3a 424 ictrl = rd_reg_word(&reg->isp.ictrl);
8d3c9c23
QT		 425 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1119,
426 "MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx "
427 "mb[0]=0x%x\n", command, ictrl, jiffies, mb[0]);
1c7c6357 428 }
5e19ed90 429 ql_dump_regs(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1019);
1da177e4 430
783e0dc4
SC		 431 /* Capture FW dump only, if PCI device active */
432 if (!pci_channel_offline(vha->hw->pdev)) {
433 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
b2000805
QT		 434 if (w == 0xffff || ictrl == 0xffffffff ||
435 (chip_reset != ha->chip_reset)) {
783e0dc4
SC		 436 /* This is special case if there is unload
437 * of driver happening and if PCI device go
438 * into bad state due to PCI error condition
439 * then only PCI ERR flag would be set.
440 * we will do premature exit for above case.
441 */
b6faaaf7 442 spin_lock_irqsave(&ha->hardware_lock, flags);
783e0dc4 443 ha->flags.mbox_busy = 0;
b6faaaf7
QT		 444 spin_unlock_irqrestore(&ha->hardware_lock,
445 flags);
783e0dc4
SC		 446 rval = QLA_FUNCTION_TIMEOUT;
447 goto premature_exit;
448 }
f55bfc88 449
783e0dc4
SC		 450 /* Attempt to capture firmware dump for further
451 * anallysis of the current formware state. we do not
452 * need to do this if we are intentionally generating
453 * a dump
454 */
455 if (mcp->mb[0] != MBC_GEN_SYSTEM_ERROR)
8ae17876 456 qla2xxx_dump_fw(vha);
783e0dc4
SC		 457 rval = QLA_FUNCTION_TIMEOUT;
458 }
1da177e4 459 }
b6faaaf7 460 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 461 ha->flags.mbox_busy = 0;
b6faaaf7 462 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4
LT		 463
464 /* Clean up */
465 ha->mcp = NULL;
466
124f85e6 467 if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) {
5e19ed90 468 ql_dbg(ql_dbg_mbx, vha, 0x101a,
7c3df132 469 "Checking for additional resp interrupt.\n");
1da177e4
LT		 470
471 /* polling mode for non isp_abort commands. */
73208dfd 472 qla2x00_poll(ha->rsp_q_map[0]);
1da177e4
LT		 473 }
474
1c7c6357
AV		 475 if (rval == QLA_FUNCTION_TIMEOUT &&
476 mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) {
85880801
AV		 477 if (!io_lock_on || (mcp->flags & IOCTL_CMD) ||
478 ha->flags.eeh_busy) {
1da177e4 479 /* not in dpc. schedule it for dpc to take over. */
5e19ed90 480 ql_dbg(ql_dbg_mbx, vha, 0x101b,
7c3df132 481 "Timeout, schedule isp_abort_needed.\n");
cdbb0a4f
SV		 482
483 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
484 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
485 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
63154916
GM		 486 if (IS_QLA82XX(ha)) {
487 ql_dbg(ql_dbg_mbx, vha, 0x112a,
488 "disabling pause transmit on port "
489 "0 & 1.\n");
490 qla82xx_wr_32(ha,
491 QLA82XX_CRB_NIU + 0x98,
492 CRB_NIU_XG_PAUSE_CTL_P0|
493 CRB_NIU_XG_PAUSE_CTL_P1);
494 }
7c3df132 495 ql_log(ql_log_info, base_vha, 0x101c,
24d9ee85 496 "Mailbox cmd timeout occurred, cmd=0x%x, "
d8c0d546
CD		 497 "mb[0]=0x%x, eeh_busy=0x%x. Scheduling ISP "
498 "abort.\n", command, mcp->mb[0],
499 ha->flags.eeh_busy);
cdbb0a4f
SV		 500 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
501 qla2xxx_wake_dpc(vha);
502 }
710bc78f 503 } else if (current == ha->dpc_thread) {
1da177e4 504 /* call abort directly since we are in the DPC thread */
5e19ed90 505 ql_dbg(ql_dbg_mbx, vha, 0x101d,
7c3df132 506 "Timeout, calling abort_isp.\n");
cdbb0a4f
SV		 507
508 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
509 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
510 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
63154916
GM		 511 if (IS_QLA82XX(ha)) {
512 ql_dbg(ql_dbg_mbx, vha, 0x112b,
513 "disabling pause transmit on port "
514 "0 & 1.\n");
515 qla82xx_wr_32(ha,
516 QLA82XX_CRB_NIU + 0x98,
517 CRB_NIU_XG_PAUSE_CTL_P0|
518 CRB_NIU_XG_PAUSE_CTL_P1);
519 }
7c3df132 520 ql_log(ql_log_info, base_vha, 0x101e,
24d9ee85 521 "Mailbox cmd timeout occurred, cmd=0x%x, "
d8c0d546
CD		 522 "mb[0]=0x%x. Scheduling ISP abort ",
523 command, mcp->mb[0]);
cdbb0a4f
SV		 524 set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
525 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
d3360960
GM		 526 /* Allow next mbx cmd to come in. */
527 complete(&ha->mbx_cmd_comp);
cdbb0a4f
SV		 528 if (ha->isp_ops->abort_isp(vha)) {
529 /* Failed. retry later. */
530 set_bit(ISP_ABORT_NEEDED,
531 &vha->dpc_flags);
532 }
533 clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
5e19ed90 534 ql_dbg(ql_dbg_mbx, vha, 0x101f,
7c3df132 535 "Finished abort_isp.\n");
d3360960 536 goto mbx_done;
1da177e4 537 }
1da177e4
LT		 538 }
539 }
540
cdbb0a4f 541premature_exit:
1da177e4 542 /* Allow next mbx cmd to come in. */
8eca3f39 543 complete(&ha->mbx_cmd_comp);
1da177e4 544
d3360960 545mbx_done:
b2000805
QT		 546 if (rval == QLA_ABORTED) {
547 ql_log(ql_log_info, vha, 0xd035,
548 "Chip Reset in progress. Purging Mbox cmd=0x%x.\n",
549 mcp->mb[0]);
550 } else if (rval) {
050dc76a 551 if (ql2xextended_error_logging & (ql_dbg_disc|ql_dbg_mbx)) {
3f918ffa 552 pr_warn("%s [%s]-%04x:%ld: **** Failed=%x", QL_MSGHDR,
050dc76a 553 dev_name(&ha->pdev->dev), 0x1020+0x800,
3f918ffa 554 vha->host_no, rval);
050dc76a
JC		 555 mboxes = mcp->in_mb;
556 cnt = 4;
557 for (i = 0; i < ha->mbx_count && cnt; i++, mboxes >>= 1)
558 if (mboxes & BIT_0) {
559 printk(" mb[%u]=%x", i, mcp->mb[i]);
560 cnt--;
561 }
562 pr_warn(" cmd=%x ****\n", command);
563 }
f7e59e99
MR		 564 if (IS_FWI2_CAPABLE(ha) && !(IS_P3P_TYPE(ha))) {
565 ql_dbg(ql_dbg_mbx, vha, 0x1198,
566 "host_status=%#x intr_ctrl=%#x intr_status=%#x\n",
04474d3a
BVA		 567 rd_reg_dword(&reg->isp24.host_status),
568 rd_reg_dword(&reg->isp24.ictrl),
569 rd_reg_dword(&reg->isp24.istatus));
f7e59e99
MR		 570 } else {
571 ql_dbg(ql_dbg_mbx, vha, 0x1206,
572 "ctrl_status=%#x ictrl=%#x istatus=%#x\n",
04474d3a
BVA		 573 rd_reg_word(&reg->isp.ctrl_status),
574 rd_reg_word(&reg->isp.ictrl),
575 rd_reg_word(&reg->isp.istatus));
f7e59e99 576 }
1da177e4 577 } else {
7c3df132 578 ql_dbg(ql_dbg_mbx, base_vha, 0x1021, "Done %s.\n", __func__);
1da177e4
LT		 579 }
580
1da177e4
LT		 581 return rval;
582}
583
1da177e4 584int
7b867cf7 585qla2x00_load_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t risc_addr,
590f98e5 586 uint32_t risc_code_size)
1da177e4
LT		 587{
588 int rval;
7b867cf7 589 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 590 mbx_cmd_t mc;
591 mbx_cmd_t *mcp = &mc;
1da177e4 592
5f28d2d7
SK		 593 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1022,
594 "Entered %s.\n", __func__);
1da177e4 595
e428924c 596 if (MSW(risc_addr) || IS_FWI2_CAPABLE(ha)) {
590f98e5
AV		 597 mcp->mb[0] = MBC_LOAD_RISC_RAM_EXTENDED;
598 mcp->mb[8] = MSW(risc_addr);
599 mcp->out_mb = MBX_8|MBX_0;
1da177e4 600 } else {
590f98e5
AV		 601 mcp->mb[0] = MBC_LOAD_RISC_RAM;
602 mcp->out_mb = MBX_0;
1da177e4 603 }
1da177e4
LT		 604 mcp->mb[1] = LSW(risc_addr);
605 mcp->mb[2] = MSW(req_dma);
606 mcp->mb[3] = LSW(req_dma);
1da177e4
LT		 607 mcp->mb[6] = MSW(MSD(req_dma));
608 mcp->mb[7] = LSW(MSD(req_dma));
590f98e5 609 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
e428924c 610 if (IS_FWI2_CAPABLE(ha)) {
1c7c6357
AV		 611 mcp->mb[4] = MSW(risc_code_size);
612 mcp->mb[5] = LSW(risc_code_size);
613 mcp->out_mb |= MBX_5|MBX_4;
614 } else {
615 mcp->mb[4] = LSW(risc_code_size);
616 mcp->out_mb |= MBX_4;
617 }
618
2a3192a3 619 mcp->in_mb = MBX_1|MBX_0;
b93480e3 620 mcp->tov = MBX_TOV_SECONDS;
1da177e4 621 mcp->flags = 0;
7b867cf7 622 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4 623
1da177e4 624 if (rval != QLA_SUCCESS) {
7c3df132 625 ql_dbg(ql_dbg_mbx, vha, 0x1023,
2a3192a3
JC		 626 "Failed=%x mb[0]=%x mb[1]=%x.\n",
627 rval, mcp->mb[0], mcp->mb[1]);
1da177e4 628 } else {
5f28d2d7
SK		 629 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1024,
630 "Done %s.\n", __func__);
1da177e4
LT		 631 }
632
633 return rval;
634}
635
e84067d7
DG		 636#define NVME_ENABLE_FLAG BIT_3
637
1da177e4
LT		 638/*
639 * qla2x00_execute_fw
1c7c6357 640 * Start adapter firmware.
1da177e4
LT		 641 *
642 * Input:
1c7c6357
AV		 643 * ha = adapter block pointer.
644 * TARGET_QUEUE_LOCK must be released.
645 * ADAPTER_STATE_LOCK must be released.
1da177e4
LT		 646 *
647 * Returns:
1c7c6357 648 * qla2x00 local function return status code.
1da177e4
LT		 649 *
650 * Context:
1c7c6357 651 * Kernel context.
1da177e4
LT		 652 */
653int
7b867cf7 654qla2x00_execute_fw(scsi_qla_host_t *vha, uint32_t risc_addr)
1da177e4
LT		 655{
656 int rval;
7b867cf7 657 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 658 mbx_cmd_t mc;
659 mbx_cmd_t *mcp = &mc;
cad9c2d2
QT		 660 u8 semaphore = 0;
661#define EXE_FW_FORCE_SEMAPHORE BIT_7
662 u8 retry = 3;
1da177e4 663
5f28d2d7
SK		 664 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1025,
665 "Entered %s.\n", __func__);
1da177e4 666
cad9c2d2 667again:
1da177e4 668 mcp->mb[0] = MBC_EXECUTE_FIRMWARE;
1c7c6357
AV		 669 mcp->out_mb = MBX_0;
670 mcp->in_mb = MBX_0;
e428924c 671 if (IS_FWI2_CAPABLE(ha)) {
1c7c6357
AV		 672 mcp->mb[1] = MSW(risc_addr);
673 mcp->mb[2] = LSW(risc_addr);
674 mcp->mb[3] = 0;
e4e3a2ce 675 mcp->mb[4] = 0;
c2ff2a36 676 mcp->mb[11] = 0;
b0f18eee
AV		 677
678 /* Enable BPM? */
679 if (ha->flags.lr_detected) {
680 mcp->mb[4] = BIT_0;
681 if (IS_BPM_RANGE_CAPABLE(ha))
682 mcp->mb[4] |=
683 ha->lr_distance << LR_DIST_FW_POS;
e4e3a2ce 684 }
b0d6cabd 685
ecc89f25 686 if (ql2xnvmeenable && (IS_QLA27XX(ha) || IS_QLA28XX(ha)))
e84067d7
DG		 687 mcp->mb[4] |= NVME_ENABLE_FLAG;
688
ecc89f25 689 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
92d4408e
SC		 690 struct nvram_81xx *nv = ha->nvram;
691 /* set minimum speed if specified in nvram */
72a92df2
JC		 692 if (nv->min_supported_speed >= 2 &&
693 nv->min_supported_speed <= 5) {
92d4408e 694 mcp->mb[4] |= BIT_4;
72a92df2 695 mcp->mb[11] |= nv->min_supported_speed & 0xF;
92d4408e
SC		 696 mcp->out_mb |= MBX_11;
697 mcp->in_mb |= BIT_5;
72a92df2
JC		 698 vha->min_supported_speed =
699 nv->min_supported_speed;
92d4408e
SC		 700 }
701 }
702
b0d6cabd
HM		 703 if (ha->flags.exlogins_enabled)
704 mcp->mb[4] |= ENABLE_EXTENDED_LOGIN;
705
2f56a7f1
HM		 706 if (ha->flags.exchoffld_enabled)
707 mcp->mb[4] |= ENABLE_EXCHANGE_OFFLD;
708
cad9c2d2
QT		 709 if (semaphore)
710 mcp->mb[11] |= EXE_FW_FORCE_SEMAPHORE;
711
c2ff2a36 712 mcp->out_mb |= MBX_4 | MBX_3 | MBX_2 | MBX_1 | MBX_11;
1f4c7c38 713 mcp->in_mb |= MBX_3 | MBX_2 | MBX_1;
1c7c6357
AV		 714 } else {
715 mcp->mb[1] = LSW(risc_addr);
716 mcp->out_mb |= MBX_1;
717 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
718 mcp->mb[2] = 0;
719 mcp->out_mb |= MBX_2;
720 }
1da177e4
LT		 721 }
722
b93480e3 723 mcp->tov = MBX_TOV_SECONDS;
1da177e4 724 mcp->flags = 0;
7b867cf7 725 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4 726
1c7c6357 727 if (rval != QLA_SUCCESS) {
cad9c2d2
QT		 728 if (IS_QLA28XX(ha) && rval == QLA_COMMAND_ERROR &&
729 mcp->mb[1] == 0x27 && retry) {
730 semaphore = 1;
731 retry--;
732 ql_dbg(ql_dbg_async, vha, 0x1026,
733 "Exe FW: force semaphore.\n");
734 goto again;
735 }
736
7c3df132
SK		 737 ql_dbg(ql_dbg_mbx, vha, 0x1026,
738 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
72a92df2
JC		 739 return rval;
740 }
741
742 if (!IS_FWI2_CAPABLE(ha))
743 goto done;
744
745 ha->fw_ability_mask = mcp->mb[3] << 16 | mcp->mb[2];
746 ql_dbg(ql_dbg_mbx, vha, 0x119a,
747 "fw_ability_mask=%x.\n", ha->fw_ability_mask);
748 ql_dbg(ql_dbg_mbx, vha, 0x1027, "exchanges=%x.\n", mcp->mb[1]);
749 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
750 ha->max_supported_speed = mcp->mb[2] & (BIT_0|BIT_1);
751 ql_dbg(ql_dbg_mbx, vha, 0x119b, "max_supported_speed=%s.\n",
752 ha->max_supported_speed == 0 ? "16Gps" :
753 ha->max_supported_speed == 1 ? "32Gps" :
754 ha->max_supported_speed == 2 ? "64Gps" : "unknown");
755 if (vha->min_supported_speed) {
756 ha->min_supported_speed = mcp->mb[5] &
757 (BIT_0 | BIT_1 | BIT_2);
758 ql_dbg(ql_dbg_mbx, vha, 0x119c,
759 "min_supported_speed=%s.\n",
760 ha->min_supported_speed == 6 ? "64Gps" :
761 ha->min_supported_speed == 5 ? "32Gps" :
762 ha->min_supported_speed == 4 ? "16Gps" :
763 ha->min_supported_speed == 3 ? "8Gps" :
764 ha->min_supported_speed == 2 ? "4Gps" : "unknown");
1c7c6357
AV		 765 }
766 }
1da177e4 767
72a92df2
JC		 768done:
769 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1028,
770 "Done %s.\n", __func__);
771
1da177e4
LT		 772 return rval;
773}
774
b0d6cabd
HM		 775/*
776 * qla_get_exlogin_status
777 * Get extended login status
778 * uses the memory offload control/status Mailbox
779 *
780 * Input:
781 * ha: adapter state pointer.
782 * fwopt: firmware options
783 *
784 * Returns:
785 * qla2x00 local function status
786 *
787 * Context:
788 * Kernel context.
789 */
790#define FETCH_XLOGINS_STAT 0x8
791int
792qla_get_exlogin_status(scsi_qla_host_t *vha, uint16_t *buf_sz,
793 uint16_t *ex_logins_cnt)
794{
795 int rval;
796 mbx_cmd_t mc;
797 mbx_cmd_t *mcp = &mc;
798
799 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118f,
800 "Entered %s\n", __func__);
801
802 memset(mcp->mb, 0 , sizeof(mcp->mb));
803 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT;
804 mcp->mb[1] = FETCH_XLOGINS_STAT;
805 mcp->out_mb = MBX_1|MBX_0;
806 mcp->in_mb = MBX_10|MBX_4|MBX_0;
807 mcp->tov = MBX_TOV_SECONDS;
808 mcp->flags = 0;
809
810 rval = qla2x00_mailbox_command(vha, mcp);
811 if (rval != QLA_SUCCESS) {
812 ql_dbg(ql_dbg_mbx, vha, 0x1115, "Failed=%x.\n", rval);
813 } else {
814 *buf_sz = mcp->mb[4];
815 *ex_logins_cnt = mcp->mb[10];
816
817 ql_log(ql_log_info, vha, 0x1190,
818 "buffer size 0x%x, exchange login count=%d\n",
819 mcp->mb[4], mcp->mb[10]);
820
821 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1116,
822 "Done %s.\n", __func__);
823 }
824
825 return rval;
826}
827
828/*
829 * qla_set_exlogin_mem_cfg
830 * set extended login memory configuration
831 * Mbx needs to be issues before init_cb is set
832 *
833 * Input:
834 * ha: adapter state pointer.
835 * buffer: buffer pointer
836 * phys_addr: physical address of buffer
837 * size: size of buffer
838 * TARGET_QUEUE_LOCK must be released
839 * ADAPTER_STATE_LOCK must be release
840 *
841 * Returns:
842 * qla2x00 local funxtion status code.
843 *
844 * Context:
845 * Kernel context.
846 */
d38cb849 847#define CONFIG_XLOGINS_MEM 0x9
b0d6cabd
HM		 848int
849qla_set_exlogin_mem_cfg(scsi_qla_host_t *vha, dma_addr_t phys_addr)
850{
851 int rval;
852 mbx_cmd_t mc;
853 mbx_cmd_t *mcp = &mc;
854 struct qla_hw_data *ha = vha->hw;
b0d6cabd
HM		 855
856 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111a,
857 "Entered %s.\n", __func__);
858
859 memset(mcp->mb, 0 , sizeof(mcp->mb));
860 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT;
861 mcp->mb[1] = CONFIG_XLOGINS_MEM;
862 mcp->mb[2] = MSW(phys_addr);
863 mcp->mb[3] = LSW(phys_addr);
864 mcp->mb[6] = MSW(MSD(phys_addr));
865 mcp->mb[7] = LSW(MSD(phys_addr));
866 mcp->mb[8] = MSW(ha->exlogin_size);
867 mcp->mb[9] = LSW(ha->exlogin_size);
868 mcp->out_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
869 mcp->in_mb = MBX_11|MBX_0;
870 mcp->tov = MBX_TOV_SECONDS;
871 mcp->flags = 0;
872 rval = qla2x00_mailbox_command(vha, mcp);
873 if (rval != QLA_SUCCESS) {
d38cb849
QT		 874 ql_dbg(ql_dbg_mbx, vha, 0x111b,
875 "EXlogin Failed=%x. MB0=%x MB11=%x\n",
876 rval, mcp->mb[0], mcp->mb[11]);
b0d6cabd 877 } else {
b0d6cabd
HM		 878 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118c,
879 "Done %s.\n", __func__);
880 }
881
882 return rval;
883}
884
2f56a7f1
HM		 885/*
886 * qla_get_exchoffld_status
887 * Get exchange offload status
888 * uses the memory offload control/status Mailbox
889 *
890 * Input:
891 * ha: adapter state pointer.
892 * fwopt: firmware options
893 *
894 * Returns:
895 * qla2x00 local function status
896 *
897 * Context:
898 * Kernel context.
899 */
900#define FETCH_XCHOFFLD_STAT 0x2
901int
902qla_get_exchoffld_status(scsi_qla_host_t *vha, uint16_t *buf_sz,
903 uint16_t *ex_logins_cnt)
904{
905 int rval;
906 mbx_cmd_t mc;
907 mbx_cmd_t *mcp = &mc;
908
909 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1019,
910 "Entered %s\n", __func__);
911
912 memset(mcp->mb, 0 , sizeof(mcp->mb));
913 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT;
914 mcp->mb[1] = FETCH_XCHOFFLD_STAT;
915 mcp->out_mb = MBX_1|MBX_0;
916 mcp->in_mb = MBX_10|MBX_4|MBX_0;
917 mcp->tov = MBX_TOV_SECONDS;
918 mcp->flags = 0;
919
920 rval = qla2x00_mailbox_command(vha, mcp);
921 if (rval != QLA_SUCCESS) {
922 ql_dbg(ql_dbg_mbx, vha, 0x1155, "Failed=%x.\n", rval);
923 } else {
924 *buf_sz = mcp->mb[4];
925 *ex_logins_cnt = mcp->mb[10];
926
927 ql_log(ql_log_info, vha, 0x118e,
928 "buffer size 0x%x, exchange offload count=%d\n",
929 mcp->mb[4], mcp->mb[10]);
930
931 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1156,
932 "Done %s.\n", __func__);
933 }
934
935 return rval;
936}
937
938/*
939 * qla_set_exchoffld_mem_cfg
940 * Set exchange offload memory configuration
941 * Mbx needs to be issues before init_cb is set
942 *
943 * Input:
944 * ha: adapter state pointer.
945 * buffer: buffer pointer
946 * phys_addr: physical address of buffer
947 * size: size of buffer
948 * TARGET_QUEUE_LOCK must be released
949 * ADAPTER_STATE_LOCK must be release
950 *
951 * Returns:
952 * qla2x00 local funxtion status code.
953 *
954 * Context:
955 * Kernel context.
956 */
957#define CONFIG_XCHOFFLD_MEM 0x3
958int
99e1b683 959qla_set_exchoffld_mem_cfg(scsi_qla_host_t *vha)
2f56a7f1
HM		 960{
961 int rval;
962 mbx_cmd_t mc;
963 mbx_cmd_t *mcp = &mc;
964 struct qla_hw_data *ha = vha->hw;
965
966 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1157,
967 "Entered %s.\n", __func__);
968
969 memset(mcp->mb, 0 , sizeof(mcp->mb));
970 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT;
971 mcp->mb[1] = CONFIG_XCHOFFLD_MEM;
99e1b683
QT		 972 mcp->mb[2] = MSW(ha->exchoffld_buf_dma);
973 mcp->mb[3] = LSW(ha->exchoffld_buf_dma);
974 mcp->mb[6] = MSW(MSD(ha->exchoffld_buf_dma));
975 mcp->mb[7] = LSW(MSD(ha->exchoffld_buf_dma));
976 mcp->mb[8] = MSW(ha->exchoffld_size);
977 mcp->mb[9] = LSW(ha->exchoffld_size);
2f56a7f1
HM		 978 mcp->out_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
979 mcp->in_mb = MBX_11|MBX_0;
980 mcp->tov = MBX_TOV_SECONDS;
981 mcp->flags = 0;
982 rval = qla2x00_mailbox_command(vha, mcp);
983 if (rval != QLA_SUCCESS) {
984 /*EMPTY*/
985 ql_dbg(ql_dbg_mbx, vha, 0x1158, "Failed=%x.\n", rval);
986 } else {
987 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1192,
988 "Done %s.\n", __func__);
989 }
990
991 return rval;
992}
993
1da177e4
LT		 994/*
995 * qla2x00_get_fw_version
996 * Get firmware version.
997 *
998 * Input:
999 * ha: adapter state pointer.
1000 * major: pointer for major number.
1001 * minor: pointer for minor number.
1002 * subminor: pointer for subminor number.
1003 *
1004 * Returns:
1005 * qla2x00 local function return status code.
1006 *
1007 * Context:
1008 * Kernel context.
1009 */
ca9e9c3e 1010int
6246b8a1 1011qla2x00_get_fw_version(scsi_qla_host_t *vha)
1da177e4
LT		 1012{
1013 int rval;
1014 mbx_cmd_t mc;
1015 mbx_cmd_t *mcp = &mc;
6246b8a1 1016 struct qla_hw_data *ha = vha->hw;
1da177e4 1017
5f28d2d7
SK		 1018 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1029,
1019 "Entered %s.\n", __func__);
1da177e4
LT		 1020
1021 mcp->mb[0] = MBC_GET_FIRMWARE_VERSION;
1022 mcp->out_mb = MBX_0;
1023 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
7ec0effd 1024 if (IS_QLA81XX(vha->hw) || IS_QLA8031(ha) || IS_QLA8044(ha))
55a96158 1025 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8;
fb0effee 1026 if (IS_FWI2_CAPABLE(ha))
6246b8a1 1027 mcp->in_mb |= MBX_17|MBX_16|MBX_15;
ecc89f25 1028 if (IS_QLA27XX(ha) || IS_QLA28XX(ha))
ad1ef177
JC		 1029 mcp->in_mb |=
1030 MBX_25|MBX_24|MBX_23|MBX_22|MBX_21|MBX_20|MBX_19|MBX_18|
2a3192a3 1031 MBX_14|MBX_13|MBX_11|MBX_10|MBX_9|MBX_8|MBX_7;
03aa868c 1032
1da177e4 1033 mcp->flags = 0;
b93480e3 1034 mcp->tov = MBX_TOV_SECONDS;
7b867cf7 1035 rval = qla2x00_mailbox_command(vha, mcp);
ca9e9c3e
AV		 1036 if (rval != QLA_SUCCESS)
1037 goto failed;
1da177e4
LT		 1038
1039 /* Return mailbox data. */
6246b8a1
GM		 1040 ha->fw_major_version = mcp->mb[1];
1041 ha->fw_minor_version = mcp->mb[2];
1042 ha->fw_subminor_version = mcp->mb[3];
1043 ha->fw_attributes = mcp->mb[6];
7b867cf7 1044 if (IS_QLA2100(vha->hw) || IS_QLA2200(vha->hw))
6246b8a1 1045 ha->fw_memory_size = 0x1FFFF; /* Defaults to 128KB. */
1da177e4 1046 else
6246b8a1 1047 ha->fw_memory_size = (mcp->mb[5] << 16) | mcp->mb[4];
03aa868c 1048
7ec0effd 1049 if (IS_QLA81XX(vha->hw) || IS_QLA8031(vha->hw) || IS_QLA8044(ha)) {
6246b8a1
GM		 1050 ha->mpi_version[0] = mcp->mb[10] & 0xff;
1051 ha->mpi_version[1] = mcp->mb[11] >> 8;
1052 ha->mpi_version[2] = mcp->mb[11] & 0xff;
1053 ha->mpi_capabilities = (mcp->mb[12] << 16) | mcp->mb[13];
1054 ha->phy_version[0] = mcp->mb[8] & 0xff;
1055 ha->phy_version[1] = mcp->mb[9] >> 8;
1056 ha->phy_version[2] = mcp->mb[9] & 0xff;
1057 }
03aa868c 1058
81178772
SK		 1059 if (IS_FWI2_CAPABLE(ha)) {
1060 ha->fw_attributes_h = mcp->mb[15];
1061 ha->fw_attributes_ext[0] = mcp->mb[16];
1062 ha->fw_attributes_ext[1] = mcp->mb[17];
1063 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1139,
1064 "%s: FW_attributes Upper: 0x%x, Lower: 0x%x.\n",
1065 __func__, mcp->mb[15], mcp->mb[6]);
1066 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x112f,
1067 "%s: Ext_FwAttributes Upper: 0x%x, Lower: 0x%x.\n",
1068 __func__, mcp->mb[17], mcp->mb[16]);
2f56a7f1 1069
b0d6cabd
HM		 1070 if (ha->fw_attributes_h & 0x4)
1071 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118d,
1072 "%s: Firmware supports Extended Login 0x%x\n",
1073 __func__, ha->fw_attributes_h);
2f56a7f1
HM		 1074
1075 if (ha->fw_attributes_h & 0x8)
1076 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1191,
1077 "%s: Firmware supports Exchange Offload 0x%x\n",
1078 __func__, ha->fw_attributes_h);
e84067d7 1079
deeae7a6
DG		 1080 /*
1081 * FW supports nvme and driver load parameter requested nvme.
1082 * BIT 26 of fw_attributes indicates NVMe support.
1083 */
171e4909
GM		 1084 if ((ha->fw_attributes_h &
1085 (FW_ATTR_H_NVME | FW_ATTR_H_NVME_UPDATED)) &&
1086 ql2xnvmeenable) {
03aaa89f
DT		 1087 if (ha->fw_attributes_h & FW_ATTR_H_NVME_FBURST)
1088 vha->flags.nvme_first_burst = 1;
1089
e84067d7 1090 vha->flags.nvme_enabled = 1;
1cbc0efc
DT		 1091 ql_log(ql_log_info, vha, 0xd302,
1092 "%s: FC-NVMe is Enabled (0x%x)\n",
1093 __func__, ha->fw_attributes_h);
1094 }
cf3c54fb
SK		 1095
1096 /* BIT_13 of Extended FW Attributes informs about NVMe2 support */
1097 if (ha->fw_attributes_ext[0] & FW_ATTR_EXT0_NVME2) {
1098 ql_log(ql_log_info, vha, 0xd302,
1099 "Firmware supports NVMe2 0x%x\n",
1100 ha->fw_attributes_ext[0]);
1101 vha->flags.nvme2_enabled = 1;
1102 }
3a03eb79 1103 }
03aa868c 1104
ecc89f25 1105 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
2a3192a3
JC		 1106 ha->serdes_version[0] = mcp->mb[7] & 0xff;
1107 ha->serdes_version[1] = mcp->mb[8] >> 8;
1108 ha->serdes_version[2] = mcp->mb[8] & 0xff;
03aa868c
SC		 1109 ha->mpi_version[0] = mcp->mb[10] & 0xff;
1110 ha->mpi_version[1] = mcp->mb[11] >> 8;
1111 ha->mpi_version[2] = mcp->mb[11] & 0xff;
1112 ha->pep_version[0] = mcp->mb[13] & 0xff;
1113 ha->pep_version[1] = mcp->mb[14] >> 8;
1114 ha->pep_version[2] = mcp->mb[14] & 0xff;
f73cb695
CD		 1115 ha->fw_shared_ram_start = (mcp->mb[19] << 16) | mcp->mb[18];
1116 ha->fw_shared_ram_end = (mcp->mb[21] << 16) | mcp->mb[20];
ad1ef177
JC		 1117 ha->fw_ddr_ram_start = (mcp->mb[23] << 16) | mcp->mb[22];
1118 ha->fw_ddr_ram_end = (mcp->mb[25] << 16) | mcp->mb[24];
3f006ac3 1119 if (IS_QLA28XX(ha)) {
4ba836f6 1120 if (mcp->mb[16] & BIT_10)
3f006ac3 1121 ha->flags.secure_fw = 1;
4ba836f6
MH		 1122
1123 ql_log(ql_log_info, vha, 0xffff,
1124 "Secure Flash Update in FW: %s\n",
1125 (ha->flags.secure_fw) ? "Supported" :
1126 "Not Supported");
3f006ac3 1127 }
9f2475fe
SS		 1128
1129 if (ha->flags.scm_supported_a &&
1130 (ha->fw_attributes_ext[0] & FW_ATTR_EXT0_SCM_SUPPORTED)) {
1131 ha->flags.scm_supported_f = 1;
8a78dd6e 1132 ha->sf_init_cb->flags |= cpu_to_le16(BIT_13);
9f2475fe
SS		 1133 }
1134 ql_log(ql_log_info, vha, 0x11a3, "SCM in FW: %s\n",
1135 (ha->flags.scm_supported_f) ? "Supported" :
1136 "Not Supported");
cf3c54fb
SK		 1137
1138 if (vha->flags.nvme2_enabled) {
1139 /* set BIT_15 of special feature control block for SLER */
8a78dd6e 1140 ha->sf_init_cb->flags |= cpu_to_le16(BIT_15);
cf3c54fb 1141 /* set BIT_14 of special feature control block for PI CTRL*/
8a78dd6e 1142 ha->sf_init_cb->flags |= cpu_to_le16(BIT_14);
cf3c54fb 1143 }
f73cb695 1144 }
6246b8a1 1145
ca9e9c3e 1146failed:
1da177e4
LT		 1147 if (rval != QLA_SUCCESS) {
1148 /*EMPTY*/
7c3df132 1149 ql_dbg(ql_dbg_mbx, vha, 0x102a, "Failed=%x.\n", rval);
1da177e4
LT		 1150 } else {
1151 /*EMPTY*/
5f28d2d7
SK		 1152 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102b,
1153 "Done %s.\n", __func__);
1da177e4 1154 }
ca9e9c3e 1155 return rval;
1da177e4
LT		 1156}
1157
1158/*
1159 * qla2x00_get_fw_options
1160 * Set firmware options.
1161 *
1162 * Input:
1163 * ha = adapter block pointer.
1164 * fwopt = pointer for firmware options.
1165 *
1166 * Returns:
1167 * qla2x00 local function return status code.
1168 *
1169 * Context:
1170 * Kernel context.
1171 */
1172int
7b867cf7 1173qla2x00_get_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
1da177e4
LT		 1174{
1175 int rval;
1176 mbx_cmd_t mc;
1177 mbx_cmd_t *mcp = &mc;
1178
5f28d2d7
SK		 1179 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102c,
1180 "Entered %s.\n", __func__);
1da177e4
LT		 1181
1182 mcp->mb[0] = MBC_GET_FIRMWARE_OPTION;
1183 mcp->out_mb = MBX_0;
1184 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
b93480e3 1185 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1186 mcp->flags = 0;
7b867cf7 1187 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1188
1189 if (rval != QLA_SUCCESS) {
1190 /*EMPTY*/
7c3df132 1191 ql_dbg(ql_dbg_mbx, vha, 0x102d, "Failed=%x.\n", rval);
1da177e4 1192 } else {
1c7c6357 1193 fwopts[0] = mcp->mb[0];
1da177e4
LT		 1194 fwopts[1] = mcp->mb[1];
1195 fwopts[2] = mcp->mb[2];
1196 fwopts[3] = mcp->mb[3];
1197
5f28d2d7
SK		 1198 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102e,
1199 "Done %s.\n", __func__);
1da177e4
LT		 1200 }
1201
1202 return rval;
1203}
1204
1205
1206/*
1207 * qla2x00_set_fw_options
1208 * Set firmware options.
1209 *
1210 * Input:
1211 * ha = adapter block pointer.
1212 * fwopt = pointer for firmware options.
1213 *
1214 * Returns:
1215 * qla2x00 local function return status code.
1216 *
1217 * Context:
1218 * Kernel context.
1219 */
1220int
7b867cf7 1221qla2x00_set_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
1da177e4
LT		 1222{
1223 int rval;
1224 mbx_cmd_t mc;
1225 mbx_cmd_t *mcp = &mc;
1226
5f28d2d7
SK		 1227 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102f,
1228 "Entered %s.\n", __func__);
1da177e4
LT		 1229
1230 mcp->mb[0] = MBC_SET_FIRMWARE_OPTION;
1231 mcp->mb[1] = fwopts[1];
1232 mcp->mb[2] = fwopts[2];
1233 mcp->mb[3] = fwopts[3];
1c7c6357 1234 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1da177e4 1235 mcp->in_mb = MBX_0;
7b867cf7 1236 if (IS_FWI2_CAPABLE(vha->hw)) {
1c7c6357 1237 mcp->in_mb |= MBX_1;
2da52737
QT		 1238 mcp->mb[10] = fwopts[10];
1239 mcp->out_mb |= MBX_10;
1c7c6357
AV		 1240 } else {
1241 mcp->mb[10] = fwopts[10];
1242 mcp->mb[11] = fwopts[11];
1243 mcp->mb[12] = 0; /* Undocumented, but used */
1244 mcp->out_mb |= MBX_12|MBX_11|MBX_10;
1245 }
b93480e3 1246 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1247 mcp->flags = 0;
7b867cf7 1248 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4 1249
1c7c6357
AV		 1250 fwopts[0] = mcp->mb[0];
1251
1da177e4
LT		 1252 if (rval != QLA_SUCCESS) {
1253 /*EMPTY*/
7c3df132
SK		 1254 ql_dbg(ql_dbg_mbx, vha, 0x1030,
1255 "Failed=%x (%x/%x).\n", rval, mcp->mb[0], mcp->mb[1]);
1da177e4
LT		 1256 } else {
1257 /*EMPTY*/
5f28d2d7
SK		 1258 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1031,
1259 "Done %s.\n", __func__);
1da177e4
LT		 1260 }
1261
1262 return rval;
1263}
1264
1265/*
1266 * qla2x00_mbx_reg_test
1267 * Mailbox register wrap test.
1268 *
1269 * Input:
1270 * ha = adapter block pointer.
1271 * TARGET_QUEUE_LOCK must be released.
1272 * ADAPTER_STATE_LOCK must be released.
1273 *
1274 * Returns:
1275 * qla2x00 local function return status code.
1276 *
1277 * Context:
1278 * Kernel context.
1279 */
1280int
7b867cf7 1281qla2x00_mbx_reg_test(scsi_qla_host_t *vha)
1da177e4
LT		 1282{
1283 int rval;
1284 mbx_cmd_t mc;
1285 mbx_cmd_t *mcp = &mc;
1286
5f28d2d7
SK		 1287 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1032,
1288 "Entered %s.\n", __func__);
1da177e4
LT		 1289
1290 mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST;
1291 mcp->mb[1] = 0xAAAA;
1292 mcp->mb[2] = 0x5555;
1293 mcp->mb[3] = 0xAA55;
1294 mcp->mb[4] = 0x55AA;
1295 mcp->mb[5] = 0xA5A5;
1296 mcp->mb[6] = 0x5A5A;
1297 mcp->mb[7] = 0x2525;
1298 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
1299 mcp->in_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
b93480e3 1300 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1301 mcp->flags = 0;
7b867cf7 1302 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1303
1304 if (rval == QLA_SUCCESS) {
1305 if (mcp->mb[1] != 0xAAAA || mcp->mb[2] != 0x5555 ||
1306 mcp->mb[3] != 0xAA55 || mcp->mb[4] != 0x55AA)
1307 rval = QLA_FUNCTION_FAILED;
1308 if (mcp->mb[5] != 0xA5A5 || mcp->mb[6] != 0x5A5A ||
1309 mcp->mb[7] != 0x2525)
1310 rval = QLA_FUNCTION_FAILED;
1311 }
1312
1313 if (rval != QLA_SUCCESS) {
1314 /*EMPTY*/
7c3df132 1315 ql_dbg(ql_dbg_mbx, vha, 0x1033, "Failed=%x.\n", rval);
1da177e4
LT		 1316 } else {
1317 /*EMPTY*/
5f28d2d7
SK		 1318 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1034,
1319 "Done %s.\n", __func__);
1da177e4
LT		 1320 }
1321
1322 return rval;
1323}
1324
1325/*
1326 * qla2x00_verify_checksum
1327 * Verify firmware checksum.
1328 *
1329 * Input:
1330 * ha = adapter block pointer.
1331 * TARGET_QUEUE_LOCK must be released.
1332 * ADAPTER_STATE_LOCK must be released.
1333 *
1334 * Returns:
1335 * qla2x00 local function return status code.
1336 *
1337 * Context:
1338 * Kernel context.
1339 */
1340int
7b867cf7 1341qla2x00_verify_checksum(scsi_qla_host_t *vha, uint32_t risc_addr)
1da177e4
LT		 1342{
1343 int rval;
1344 mbx_cmd_t mc;
1345 mbx_cmd_t *mcp = &mc;
1346
5f28d2d7
SK		 1347 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1035,
1348 "Entered %s.\n", __func__);
1da177e4
LT		 1349
1350 mcp->mb[0] = MBC_VERIFY_CHECKSUM;
1c7c6357
AV		 1351 mcp->out_mb = MBX_0;
1352 mcp->in_mb = MBX_0;
7b867cf7 1353 if (IS_FWI2_CAPABLE(vha->hw)) {
1c7c6357
AV		 1354 mcp->mb[1] = MSW(risc_addr);
1355 mcp->mb[2] = LSW(risc_addr);
1356 mcp->out_mb |= MBX_2|MBX_1;
1357 mcp->in_mb |= MBX_2|MBX_1;
1358 } else {
1359 mcp->mb[1] = LSW(risc_addr);
1360 mcp->out_mb |= MBX_1;
1361 mcp->in_mb |= MBX_1;
1362 }
1363
b93480e3 1364 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1365 mcp->flags = 0;
7b867cf7 1366 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1367
1368 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1369 ql_dbg(ql_dbg_mbx, vha, 0x1036,
1370 "Failed=%x chm sum=%x.\n", rval, IS_FWI2_CAPABLE(vha->hw) ?
1371 (mcp->mb[2] << 16) | mcp->mb[1] : mcp->mb[1]);
1da177e4 1372 } else {
5f28d2d7
SK		 1373 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1037,
1374 "Done %s.\n", __func__);
1da177e4
LT		 1375 }
1376
1377 return rval;
1378}
1379
1380/*
1381 * qla2x00_issue_iocb
1382 * Issue IOCB using mailbox command
1383 *
1384 * Input:
1385 * ha = adapter state pointer.
1386 * buffer = buffer pointer.
1387 * phys_addr = physical address of buffer.
1388 * size = size of buffer.
1389 * TARGET_QUEUE_LOCK must be released.
1390 * ADAPTER_STATE_LOCK must be released.
1391 *
1392 * Returns:
1393 * qla2x00 local function return status code.
1394 *
1395 * Context:
1396 * Kernel context.
1397 */
6e98016c 1398int
7b867cf7 1399qla2x00_issue_iocb_timeout(scsi_qla_host_t *vha, void *buffer,
4d4df193 1400 dma_addr_t phys_addr, size_t size, uint32_t tov)
1da177e4
LT		 1401{
1402 int rval;
1403 mbx_cmd_t mc;
1404 mbx_cmd_t *mcp = &mc;
1405
ab391abd 1406 if (!vha->hw->flags.fw_started)
345f574d
HM		 1407 return QLA_INVALID_COMMAND;
1408
5f28d2d7
SK		 1409 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1038,
1410 "Entered %s.\n", __func__);
7c3df132 1411
1da177e4
LT		 1412 mcp->mb[0] = MBC_IOCB_COMMAND_A64;
1413 mcp->mb[1] = 0;
818c7f87
JC		 1414 mcp->mb[2] = MSW(LSD(phys_addr));
1415 mcp->mb[3] = LSW(LSD(phys_addr));
1da177e4
LT		 1416 mcp->mb[6] = MSW(MSD(phys_addr));
1417 mcp->mb[7] = LSW(MSD(phys_addr));
1418 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
818c7f87 1419 mcp->in_mb = MBX_1|MBX_0;
4d4df193 1420 mcp->tov = tov;
1da177e4 1421 mcp->flags = 0;
7b867cf7 1422 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1423
1424 if (rval != QLA_SUCCESS) {
1425 /*EMPTY*/
7c3df132 1426 ql_dbg(ql_dbg_mbx, vha, 0x1039, "Failed=%x.\n", rval);
1da177e4 1427 } else {
818c7f87 1428 sts_entry_t *sts_entry = buffer;
8c958a99
AV		 1429
1430 /* Mask reserved bits. */
1431 sts_entry->entry_status &=
7b867cf7 1432 IS_FWI2_CAPABLE(vha->hw) ? RF_MASK_24XX : RF_MASK;
5f28d2d7 1433 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103a,
818c7f87
JC		 1434 "Done %s (status=%x).\n", __func__,
1435 sts_entry->entry_status);
1da177e4
LT		 1436 }
1437
1438 return rval;
1439}
1440
4d4df193 1441int
7b867cf7 1442qla2x00_issue_iocb(scsi_qla_host_t *vha, void *buffer, dma_addr_t phys_addr,
4d4df193
HK		 1443 size_t size)
1444{
7b867cf7 1445 return qla2x00_issue_iocb_timeout(vha, buffer, phys_addr, size,
4d4df193
HK		 1446 MBX_TOV_SECONDS);
1447}
1448
1da177e4
LT		 1449/*
1450 * qla2x00_abort_command
1451 * Abort command aborts a specified IOCB.
1452 *
1453 * Input:
1454 * ha = adapter block pointer.
1455 * sp = SB structure pointer.
1456 *
1457 * Returns:
1458 * qla2x00 local function return status code.
1459 *
1460 * Context:
1461 * Kernel context.
1462 */
1463int
2afa19a9 1464qla2x00_abort_command(srb_t *sp)
1da177e4
LT		 1465{
1466 unsigned long flags = 0;
1da177e4 1467 int rval;
73208dfd 1468 uint32_t handle = 0;
1da177e4
LT		 1469 mbx_cmd_t mc;
1470 mbx_cmd_t *mcp = &mc;
2afa19a9
AC		 1471 fc_port_t *fcport = sp->fcport;
1472 scsi_qla_host_t *vha = fcport->vha;
7b867cf7 1473 struct qla_hw_data *ha = vha->hw;
d7459527 1474 struct req_que *req;
9ba56b95 1475 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
1da177e4 1476
5f28d2d7
SK		 1477 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103b,
1478 "Entered %s.\n", __func__);
1da177e4 1479
345f574d 1480 if (sp->qpair)
d7459527
MH		 1481 req = sp->qpair->req;
1482 else
1483 req = vha->req;
1484
c9c5ced9 1485 spin_lock_irqsave(&ha->hardware_lock, flags);
8d93f550 1486 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
7b867cf7 1487 if (req->outstanding_cmds[handle] == sp)
1da177e4
LT		 1488 break;
1489 }
c9c5ced9 1490 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 1491
8d93f550 1492 if (handle == req->num_outstanding_cmds) {
1da177e4
LT		 1493 /* command not found */
1494 return QLA_FUNCTION_FAILED;
1495 }
1496
1497 mcp->mb[0] = MBC_ABORT_COMMAND;
1498 if (HAS_EXTENDED_IDS(ha))
1499 mcp->mb[1] = fcport->loop_id;
1500 else
1501 mcp->mb[1] = fcport->loop_id << 8;
1502 mcp->mb[2] = (uint16_t)handle;
1503 mcp->mb[3] = (uint16_t)(handle >> 16);
9ba56b95 1504 mcp->mb[6] = (uint16_t)cmd->device->lun;
1da177e4
LT		 1505 mcp->out_mb = MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1506 mcp->in_mb = MBX_0;
b93480e3 1507 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1508 mcp->flags = 0;
7b867cf7 1509 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1510
1511 if (rval != QLA_SUCCESS) {
7c3df132 1512 ql_dbg(ql_dbg_mbx, vha, 0x103c, "Failed=%x.\n", rval);
1da177e4 1513 } else {
5f28d2d7
SK		 1514 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103d,
1515 "Done %s.\n", __func__);
1da177e4
LT		 1516 }
1517
1518 return rval;
1519}
1520
1da177e4 1521int
9cb78c16 1522qla2x00_abort_target(struct fc_port *fcport, uint64_t l, int tag)
1da177e4 1523{
523ec773 1524 int rval, rval2;
1da177e4
LT		 1525 mbx_cmd_t mc;
1526 mbx_cmd_t *mcp = &mc;
7b867cf7 1527 scsi_qla_host_t *vha;
1da177e4 1528
7b867cf7 1529 vha = fcport->vha;
7c3df132 1530
5f28d2d7
SK		 1531 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103e,
1532 "Entered %s.\n", __func__);
7c3df132 1533
1da177e4 1534 mcp->mb[0] = MBC_ABORT_TARGET;
523ec773 1535 mcp->out_mb = MBX_9|MBX_2|MBX_1|MBX_0;
7b867cf7 1536 if (HAS_EXTENDED_IDS(vha->hw)) {
1da177e4
LT		 1537 mcp->mb[1] = fcport->loop_id;
1538 mcp->mb[10] = 0;
1539 mcp->out_mb |= MBX_10;
1540 } else {
1541 mcp->mb[1] = fcport->loop_id << 8;
1542 }
7b867cf7
AC		 1543 mcp->mb[2] = vha->hw->loop_reset_delay;
1544 mcp->mb[9] = vha->vp_idx;
1da177e4
LT		 1545
1546 mcp->in_mb = MBX_0;
b93480e3 1547 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1548 mcp->flags = 0;
7b867cf7 1549 rval = qla2x00_mailbox_command(vha, mcp);
523ec773 1550 if (rval != QLA_SUCCESS) {
5f28d2d7
SK		 1551 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103f,
1552 "Failed=%x.\n", rval);
523ec773
AV		 1553 }
1554
1555 /* Issue marker IOCB. */
9eb9c6dc 1556 rval2 = qla2x00_marker(vha, vha->hw->base_qpair, fcport->loop_id, 0,
73208dfd 1557 MK_SYNC_ID);
523ec773 1558 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 1559 ql_dbg(ql_dbg_mbx, vha, 0x1040,
1560 "Failed to issue marker IOCB (%x).\n", rval2);
523ec773 1561 } else {
5f28d2d7
SK		 1562 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1041,
1563 "Done %s.\n", __func__);
523ec773
AV		 1564 }
1565
1566 return rval;
1567}
1568
1569int
9cb78c16 1570qla2x00_lun_reset(struct fc_port *fcport, uint64_t l, int tag)
523ec773
AV		 1571{
1572 int rval, rval2;
1573 mbx_cmd_t mc;
1574 mbx_cmd_t *mcp = &mc;
7b867cf7 1575 scsi_qla_host_t *vha;
523ec773 1576
7b867cf7 1577 vha = fcport->vha;
7c3df132 1578
5f28d2d7
SK		 1579 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1042,
1580 "Entered %s.\n", __func__);
7c3df132 1581
523ec773
AV		 1582 mcp->mb[0] = MBC_LUN_RESET;
1583 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
7b867cf7 1584 if (HAS_EXTENDED_IDS(vha->hw))
523ec773
AV		 1585 mcp->mb[1] = fcport->loop_id;
1586 else
1587 mcp->mb[1] = fcport->loop_id << 8;
9cb78c16 1588 mcp->mb[2] = (u32)l;
523ec773 1589 mcp->mb[3] = 0;
7b867cf7 1590 mcp->mb[9] = vha->vp_idx;
1da177e4 1591
523ec773 1592 mcp->in_mb = MBX_0;
b93480e3 1593 mcp->tov = MBX_TOV_SECONDS;
523ec773 1594 mcp->flags = 0;
7b867cf7 1595 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4 1596 if (rval != QLA_SUCCESS) {
7c3df132 1597 ql_dbg(ql_dbg_mbx, vha, 0x1043, "Failed=%x.\n", rval);
523ec773
AV		 1598 }
1599
1600 /* Issue marker IOCB. */
9eb9c6dc 1601 rval2 = qla2x00_marker(vha, vha->hw->base_qpair, fcport->loop_id, l,
73208dfd 1602 MK_SYNC_ID_LUN);
523ec773 1603 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 1604 ql_dbg(ql_dbg_mbx, vha, 0x1044,
1605 "Failed to issue marker IOCB (%x).\n", rval2);
1da177e4 1606 } else {
5f28d2d7
SK		 1607 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1045,
1608 "Done %s.\n", __func__);
1da177e4
LT		 1609 }
1610
1611 return rval;
1612}
1da177e4 1613
1da177e4
LT		 1614/*
1615 * qla2x00_get_adapter_id
1616 * Get adapter ID and topology.
1617 *
1618 * Input:
1619 * ha = adapter block pointer.
1620 * id = pointer for loop ID.
1621 * al_pa = pointer for AL_PA.
1622 * area = pointer for area.
1623 * domain = pointer for domain.
1624 * top = pointer for topology.
1625 * TARGET_QUEUE_LOCK must be released.
1626 * ADAPTER_STATE_LOCK must be released.
1627 *
1628 * Returns:
1629 * qla2x00 local function return status code.
1630 *
1631 * Context:
1632 * Kernel context.
1633 */
1634int
7b867cf7 1635qla2x00_get_adapter_id(scsi_qla_host_t *vha, uint16_t *id, uint8_t *al_pa,
2c3dfe3f 1636 uint8_t *area, uint8_t *domain, uint16_t *top, uint16_t *sw_cap)
1da177e4
LT		 1637{
1638 int rval;
1639 mbx_cmd_t mc;
1640 mbx_cmd_t *mcp = &mc;
1641
5f28d2d7
SK		 1642 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1046,
1643 "Entered %s.\n", __func__);
1da177e4
LT		 1644
1645 mcp->mb[0] = MBC_GET_ADAPTER_LOOP_ID;
7b867cf7 1646 mcp->mb[9] = vha->vp_idx;
eb66dc60 1647 mcp->out_mb = MBX_9|MBX_0;
2c3dfe3f 1648 mcp->in_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
6246b8a1 1649 if (IS_CNA_CAPABLE(vha->hw))
bad7001c 1650 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10;
7c9c4766
JC		 1651 if (IS_FWI2_CAPABLE(vha->hw))
1652 mcp->in_mb |= MBX_19|MBX_18|MBX_17|MBX_16;
9f2475fe 1653 if (IS_QLA27XX(vha->hw) || IS_QLA28XX(vha->hw)) {
969a6199 1654 mcp->in_mb |= MBX_15;
9f2475fe
SS		 1655 mcp->out_mb |= MBX_7|MBX_21|MBX_22|MBX_23;
1656 }
1657
b93480e3 1658 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1659 mcp->flags = 0;
7b867cf7 1660 rval = qla2x00_mailbox_command(vha, mcp);
33135aa2
RA		 1661 if (mcp->mb[0] == MBS_COMMAND_ERROR)
1662 rval = QLA_COMMAND_ERROR;
42e421b1
AV		 1663 else if (mcp->mb[0] == MBS_INVALID_COMMAND)
1664 rval = QLA_INVALID_COMMAND;
1da177e4
LT		 1665
1666 /* Return data. */
1667 *id = mcp->mb[1];
1668 *al_pa = LSB(mcp->mb[2]);
1669 *area = MSB(mcp->mb[2]);
1670 *domain = LSB(mcp->mb[3]);
1671 *top = mcp->mb[6];
2c3dfe3f 1672 *sw_cap = mcp->mb[7];
1da177e4
LT		 1673
1674 if (rval != QLA_SUCCESS) {
1675 /*EMPTY*/
7c3df132 1676 ql_dbg(ql_dbg_mbx, vha, 0x1047, "Failed=%x.\n", rval);
1da177e4 1677 } else {
5f28d2d7
SK		 1678 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1048,
1679 "Done %s.\n", __func__);
bad7001c 1680
6246b8a1 1681 if (IS_CNA_CAPABLE(vha->hw)) {
bad7001c
AV		 1682 vha->fcoe_vlan_id = mcp->mb[9] & 0xfff;
1683 vha->fcoe_fcf_idx = mcp->mb[10];
1684 vha->fcoe_vn_port_mac[5] = mcp->mb[11] >> 8;
1685 vha->fcoe_vn_port_mac[4] = mcp->mb[11] & 0xff;
1686 vha->fcoe_vn_port_mac[3] = mcp->mb[12] >> 8;
1687 vha->fcoe_vn_port_mac[2] = mcp->mb[12] & 0xff;
1688 vha->fcoe_vn_port_mac[1] = mcp->mb[13] >> 8;
1689 vha->fcoe_vn_port_mac[0] = mcp->mb[13] & 0xff;
1690 }
7c9c4766 1691 /* If FA-WWN supported */
d6b9b42b
SK		 1692 if (IS_FAWWN_CAPABLE(vha->hw)) {
1693 if (mcp->mb[7] & BIT_14) {
1694 vha->port_name[0] = MSB(mcp->mb[16]);
1695 vha->port_name[1] = LSB(mcp->mb[16]);
1696 vha->port_name[2] = MSB(mcp->mb[17]);
1697 vha->port_name[3] = LSB(mcp->mb[17]);
1698 vha->port_name[4] = MSB(mcp->mb[18]);
1699 vha->port_name[5] = LSB(mcp->mb[18]);
1700 vha->port_name[6] = MSB(mcp->mb[19]);
1701 vha->port_name[7] = LSB(mcp->mb[19]);
1702 fc_host_port_name(vha->host) =
1703 wwn_to_u64(vha->port_name);
1704 ql_dbg(ql_dbg_mbx, vha, 0x10ca,
1705 "FA-WWN acquired %016llx\n",
1706 wwn_to_u64(vha->port_name));
1707 }
7c9c4766 1708 }
969a6199 1709
9f2475fe 1710 if (IS_QLA27XX(vha->hw) || IS_QLA28XX(vha->hw)) {
969a6199 1711 vha->bbcr = mcp->mb[15];
9f2475fe
SS		 1712 if (mcp->mb[7] & SCM_EDC_ACC_RECEIVED) {
1713 ql_log(ql_log_info, vha, 0x11a4,
1714 "SCM: EDC ELS completed, flags 0x%x\n",
1715 mcp->mb[21]);
1716 }
1717 if (mcp->mb[7] & SCM_RDF_ACC_RECEIVED) {
1718 vha->hw->flags.scm_enabled = 1;
1719 vha->scm_fabric_connection_flags |=
1720 SCM_FLAG_RDF_COMPLETED;
1721 ql_log(ql_log_info, vha, 0x11a5,
1722 "SCM: RDF ELS completed, flags 0x%x\n",
1723 mcp->mb[23]);
1724 }
1725 }
1da177e4
LT		 1726 }
1727
1728 return rval;
1729}
1730
1731/*
1732 * qla2x00_get_retry_cnt
1733 * Get current firmware login retry count and delay.
1734 *
1735 * Input:
1736 * ha = adapter block pointer.
1737 * retry_cnt = pointer to login retry count.
1738 * tov = pointer to login timeout value.
1739 *
1740 * Returns:
1741 * qla2x00 local function return status code.
1742 *
1743 * Context:
1744 * Kernel context.
1745 */
1746int
7b867cf7 1747qla2x00_get_retry_cnt(scsi_qla_host_t *vha, uint8_t *retry_cnt, uint8_t *tov,
1da177e4
LT		 1748 uint16_t *r_a_tov)
1749{
1750 int rval;
1751 uint16_t ratov;
1752 mbx_cmd_t mc;
1753 mbx_cmd_t *mcp = &mc;
1754
5f28d2d7
SK		 1755 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1049,
1756 "Entered %s.\n", __func__);
1da177e4
LT		 1757
1758 mcp->mb[0] = MBC_GET_RETRY_COUNT;
1759 mcp->out_mb = MBX_0;
1760 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
b93480e3 1761 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1762 mcp->flags = 0;
7b867cf7 1763 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1764
1765 if (rval != QLA_SUCCESS) {
1766 /*EMPTY*/
7c3df132
SK		 1767 ql_dbg(ql_dbg_mbx, vha, 0x104a,
1768 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
1da177e4
LT		 1769 } else {
1770 /* Convert returned data and check our values. */
1771 *r_a_tov = mcp->mb[3] / 2;
1772 ratov = (mcp->mb[3]/2) / 10; /* mb[3] value is in 100ms */
1773 if (mcp->mb[1] * ratov > (*retry_cnt) * (*tov)) {
1774 /* Update to the larger values */
1775 *retry_cnt = (uint8_t)mcp->mb[1];
1776 *tov = ratov;
1777 }
1778
5f28d2d7 1779 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104b,
7c3df132 1780 "Done %s mb3=%d ratov=%d.\n", __func__, mcp->mb[3], ratov);
1da177e4
LT		 1781 }
1782
1783 return rval;
1784}
1785
1786/*
1787 * qla2x00_init_firmware
1788 * Initialize adapter firmware.
1789 *
1790 * Input:
1791 * ha = adapter block pointer.
1792 * dptr = Initialization control block pointer.
1793 * size = size of initialization control block.
1794 * TARGET_QUEUE_LOCK must be released.
1795 * ADAPTER_STATE_LOCK must be released.
1796 *
1797 * Returns:
1798 * qla2x00 local function return status code.
1799 *
1800 * Context:
1801 * Kernel context.
1802 */
1803int
7b867cf7 1804qla2x00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
1da177e4
LT		 1805{
1806 int rval;
1807 mbx_cmd_t mc;
1808 mbx_cmd_t *mcp = &mc;
7b867cf7 1809 struct qla_hw_data *ha = vha->hw;
1da177e4 1810
5f28d2d7
SK		 1811 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104c,
1812 "Entered %s.\n", __func__);
1da177e4 1813
7ec0effd 1814 if (IS_P3P_TYPE(ha) && ql2xdbwr)
8dfa4b5a 1815 qla82xx_wr_32(ha, (uintptr_t __force)ha->nxdb_wr_ptr,
a9083016
GM		 1816 (0x04 | (ha->portnum << 5) | (0 << 8) | (0 << 16)));
1817
e6e074f1 1818 if (ha->flags.npiv_supported)
2c3dfe3f
SJ		 1819 mcp->mb[0] = MBC_MID_INITIALIZE_FIRMWARE;
1820 else
1821 mcp->mb[0] = MBC_INITIALIZE_FIRMWARE;
1822
b64b0e8f 1823 mcp->mb[1] = 0;
1da177e4
LT		 1824 mcp->mb[2] = MSW(ha->init_cb_dma);
1825 mcp->mb[3] = LSW(ha->init_cb_dma);
1da177e4
LT		 1826 mcp->mb[6] = MSW(MSD(ha->init_cb_dma));
1827 mcp->mb[7] = LSW(MSD(ha->init_cb_dma));
b64b0e8f 1828 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
4ef21bd4 1829 if (ha->ex_init_cb && ha->ex_init_cb->ex_version) {
b64b0e8f
AV		 1830 mcp->mb[1] = BIT_0;
1831 mcp->mb[10] = MSW(ha->ex_init_cb_dma);
1832 mcp->mb[11] = LSW(ha->ex_init_cb_dma);
1833 mcp->mb[12] = MSW(MSD(ha->ex_init_cb_dma));
1834 mcp->mb[13] = LSW(MSD(ha->ex_init_cb_dma));
1835 mcp->mb[14] = sizeof(*ha->ex_init_cb);
1836 mcp->out_mb |= MBX_14|MBX_13|MBX_12|MBX_11|MBX_10;
1837 }
9f2475fe 1838
cf3c54fb 1839 if (ha->flags.scm_supported_f || vha->flags.nvme2_enabled) {
9f2475fe
SS		 1840 mcp->mb[1] |= BIT_1;
1841 mcp->mb[16] = MSW(ha->sf_init_cb_dma);
1842 mcp->mb[17] = LSW(ha->sf_init_cb_dma);
1843 mcp->mb[18] = MSW(MSD(ha->sf_init_cb_dma));
1844 mcp->mb[19] = LSW(MSD(ha->sf_init_cb_dma));
1845 mcp->mb[15] = sizeof(*ha->sf_init_cb);
1846 mcp->out_mb |= MBX_19|MBX_18|MBX_17|MBX_16|MBX_15;
1847 }
1848
6246b8a1
GM		 1849 /* 1 and 2 should normally be captured. */
1850 mcp->in_mb = MBX_2|MBX_1|MBX_0;
ecc89f25 1851 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
6246b8a1
GM		 1852 /* mb3 is additional info about the installed SFP. */
1853 mcp->in_mb |= MBX_3;
1da177e4
LT		 1854 mcp->buf_size = size;
1855 mcp->flags = MBX_DMA_OUT;
b93480e3 1856 mcp->tov = MBX_TOV_SECONDS;
7b867cf7 1857 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1858
1859 if (rval != QLA_SUCCESS) {
1860 /*EMPTY*/
7c3df132 1861 ql_dbg(ql_dbg_mbx, vha, 0x104d,
f8f97b0c 1862 "Failed=%x mb[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x.\n",
6246b8a1 1863 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3]);
f8f97b0c
JC		 1864 if (ha->init_cb) {
1865 ql_dbg(ql_dbg_mbx, vha, 0x104d, "init_cb:\n");
1866 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha,
1867 0x0104d, ha->init_cb, sizeof(*ha->init_cb));
1868 }
1869 if (ha->ex_init_cb && ha->ex_init_cb->ex_version) {
1870 ql_dbg(ql_dbg_mbx, vha, 0x104d, "ex_init_cb:\n");
1871 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha,
1872 0x0104d, ha->ex_init_cb, sizeof(*ha->ex_init_cb));
1873 }
1da177e4 1874 } else {
ecc89f25 1875 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
92d4408e
SC		 1876 if (mcp->mb[2] == 6 || mcp->mb[3] == 2)
1877 ql_dbg(ql_dbg_mbx, vha, 0x119d,
1878 "Invalid SFP/Validation Failed\n");
1879 }
5f28d2d7
SK		 1880 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104e,
1881 "Done %s.\n", __func__);
1da177e4
LT		 1882 }
1883
1884 return rval;
1885}
1886
2d70c103 1887
1da177e4
LT		 1888/*
1889 * qla2x00_get_port_database
1890 * Issue normal/enhanced get port database mailbox command
1891 * and copy device name as necessary.
1892 *
1893 * Input:
1894 * ha = adapter state pointer.
1895 * dev = structure pointer.
1896 * opt = enhanced cmd option byte.
1897 *
1898 * Returns:
1899 * qla2x00 local function return status code.
1900 *
1901 * Context:
1902 * Kernel context.
1903 */
1904int
7b867cf7 1905qla2x00_get_port_database(scsi_qla_host_t *vha, fc_port_t *fcport, uint8_t opt)
1da177e4
LT		 1906{
1907 int rval;
1908 mbx_cmd_t mc;
1909 mbx_cmd_t *mcp = &mc;
1910 port_database_t *pd;
1c7c6357 1911 struct port_database_24xx *pd24;
1da177e4 1912 dma_addr_t pd_dma;
7b867cf7 1913 struct qla_hw_data *ha = vha->hw;
1da177e4 1914
5f28d2d7
SK		 1915 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104f,
1916 "Entered %s.\n", __func__);
1da177e4 1917
1c7c6357 1918 pd24 = NULL;
08eb7f45 1919 pd = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
1da177e4 1920 if (pd == NULL) {
7c3df132
SK		 1921 ql_log(ql_log_warn, vha, 0x1050,
1922 "Failed to allocate port database structure.\n");
edd05de1 1923 fcport->query = 0;
1da177e4
LT		 1924 return QLA_MEMORY_ALLOC_FAILED;
1925 }
1da177e4 1926
1c7c6357 1927 mcp->mb[0] = MBC_GET_PORT_DATABASE;
e428924c 1928 if (opt != 0 && !IS_FWI2_CAPABLE(ha))
1da177e4 1929 mcp->mb[0] = MBC_ENHANCED_GET_PORT_DATABASE;
1da177e4
LT		 1930 mcp->mb[2] = MSW(pd_dma);
1931 mcp->mb[3] = LSW(pd_dma);
1932 mcp->mb[6] = MSW(MSD(pd_dma));
1933 mcp->mb[7] = LSW(MSD(pd_dma));
7b867cf7 1934 mcp->mb[9] = vha->vp_idx;
2c3dfe3f 1935 mcp->out_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
1da177e4 1936 mcp->in_mb = MBX_0;
e428924c 1937 if (IS_FWI2_CAPABLE(ha)) {
1c7c6357
AV		 1938 mcp->mb[1] = fcport->loop_id;
1939 mcp->mb[10] = opt;
1940 mcp->out_mb |= MBX_10|MBX_1;
1941 mcp->in_mb |= MBX_1;
1942 } else if (HAS_EXTENDED_IDS(ha)) {
1943 mcp->mb[1] = fcport->loop_id;
1944 mcp->mb[10] = opt;
1945 mcp->out_mb |= MBX_10|MBX_1;
1946 } else {
1947 mcp->mb[1] = fcport->loop_id << 8 | opt;
1948 mcp->out_mb |= MBX_1;
1949 }
e428924c
AV		 1950 mcp->buf_size = IS_FWI2_CAPABLE(ha) ?
1951 PORT_DATABASE_24XX_SIZE : PORT_DATABASE_SIZE;
1da177e4
LT		 1952 mcp->flags = MBX_DMA_IN;
1953 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
7b867cf7 1954 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1955 if (rval != QLA_SUCCESS)
1956 goto gpd_error_out;
1957
e428924c 1958 if (IS_FWI2_CAPABLE(ha)) {
0eba25df 1959 uint64_t zero = 0;
c0c462c8
DG		 1960 u8 current_login_state, last_login_state;
1961
1c7c6357
AV		 1962 pd24 = (struct port_database_24xx *) pd;
1963
1964 /* Check for logged in state. */
84ed362a 1965 if (NVME_TARGET(ha, fcport)) {
c0c462c8
DG		 1966 current_login_state = pd24->current_login_state >> 4;
1967 last_login_state = pd24->last_login_state >> 4;
1968 } else {
1969 current_login_state = pd24->current_login_state & 0xf;
1970 last_login_state = pd24->last_login_state & 0xf;
1971 }
1972 fcport->current_login_state = pd24->current_login_state;
1973 fcport->last_login_state = pd24->last_login_state;
1974
1975 /* Check for logged in state. */
1976 if (current_login_state != PDS_PRLI_COMPLETE &&
1977 last_login_state != PDS_PRLI_COMPLETE) {
1978 ql_dbg(ql_dbg_mbx, vha, 0x119a,
1979 "Unable to verify login-state (%x/%x) for loop_id %x.\n",
1980 current_login_state, last_login_state,
1981 fcport->loop_id);
1c7c6357 1982 rval = QLA_FUNCTION_FAILED;
c0c462c8
DG		 1983
1984 if (!fcport->query)
1985 goto gpd_error_out;
1c7c6357 1986 }
1da177e4 1987
0eba25df
AE		 1988 if (fcport->loop_id == FC_NO_LOOP_ID ||
1989 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
1990 memcmp(fcport->port_name, pd24->port_name, 8))) {
1991 /* We lost the device mid way. */
1992 rval = QLA_NOT_LOGGED_IN;
1993 goto gpd_error_out;
1994 }
1995
1c7c6357
AV		 1996 /* Names are little-endian. */
1997 memcpy(fcport->node_name, pd24->node_name, WWN_SIZE);
1998 memcpy(fcport->port_name, pd24->port_name, WWN_SIZE);
1999
2000 /* Get port_id of device. */
2001 fcport->d_id.b.domain = pd24->port_id[0];
2002 fcport->d_id.b.area = pd24->port_id[1];
2003 fcport->d_id.b.al_pa = pd24->port_id[2];
2004 fcport->d_id.b.rsvd_1 = 0;
2005
2006 /* If not target must be initiator or unknown type. */
2007 if ((pd24->prli_svc_param_word_3[0] & BIT_4) == 0)
2008 fcport->port_type = FCT_INITIATOR;
2009 else
2010 fcport->port_type = FCT_TARGET;
2d70c103
NB		 2011
2012 /* Passback COS information. */
2013 fcport->supported_classes = (pd24->flags & PDF_CLASS_2) ?
2014 FC_COS_CLASS2 : FC_COS_CLASS3;
2015
2016 if (pd24->prli_svc_param_word_3[0] & BIT_7)
2017 fcport->flags |= FCF_CONF_COMP_SUPPORTED;
1c7c6357 2018 } else {
0eba25df
AE		 2019 uint64_t zero = 0;
2020
1c7c6357
AV		 2021 /* Check for logged in state. */
2022 if (pd->master_state != PD_STATE_PORT_LOGGED_IN &&
2023 pd->slave_state != PD_STATE_PORT_LOGGED_IN) {
7c3df132
SK		 2024 ql_dbg(ql_dbg_mbx, vha, 0x100a,
2025 "Unable to verify login-state (%x/%x) - "
2026 "portid=%02x%02x%02x.\n", pd->master_state,
2027 pd->slave_state, fcport->d_id.b.domain,
2028 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1c7c6357
AV		 2029 rval = QLA_FUNCTION_FAILED;
2030 goto gpd_error_out;
2031 }
1da177e4 2032
0eba25df
AE		 2033 if (fcport->loop_id == FC_NO_LOOP_ID ||
2034 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
2035 memcmp(fcport->port_name, pd->port_name, 8))) {
2036 /* We lost the device mid way. */
2037 rval = QLA_NOT_LOGGED_IN;
2038 goto gpd_error_out;
2039 }
2040
1c7c6357
AV		 2041 /* Names are little-endian. */
2042 memcpy(fcport->node_name, pd->node_name, WWN_SIZE);
2043 memcpy(fcport->port_name, pd->port_name, WWN_SIZE);
2044
2045 /* Get port_id of device. */
2046 fcport->d_id.b.domain = pd->port_id[0];
2047 fcport->d_id.b.area = pd->port_id[3];
2048 fcport->d_id.b.al_pa = pd->port_id[2];
2049 fcport->d_id.b.rsvd_1 = 0;
2050
1c7c6357
AV		 2051 /* If not target must be initiator or unknown type. */
2052 if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0)
2053 fcport->port_type = FCT_INITIATOR;
2054 else
2055 fcport->port_type = FCT_TARGET;
ad3e0eda
AV		 2056
2057 /* Passback COS information. */
2058 fcport->supported_classes = (pd->options & BIT_4) ?
58e2753c 2059 FC_COS_CLASS2 : FC_COS_CLASS3;
1c7c6357 2060 }
1da177e4
LT		 2061
2062gpd_error_out:
2063 dma_pool_free(ha->s_dma_pool, pd, pd_dma);
edd05de1 2064 fcport->query = 0;
1da177e4
LT		 2065
2066 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2067 ql_dbg(ql_dbg_mbx, vha, 0x1052,
2068 "Failed=%x mb[0]=%x mb[1]=%x.\n", rval,
2069 mcp->mb[0], mcp->mb[1]);
1da177e4 2070 } else {
5f28d2d7
SK		 2071 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1053,
2072 "Done %s.\n", __func__);
1da177e4
LT		 2073 }
2074
2075 return rval;
2076}
2077
818c7f87
JC		 2078int
2079qla24xx_get_port_database(scsi_qla_host_t *vha, u16 nport_handle,
2080 struct port_database_24xx *pdb)
2081{
2082 mbx_cmd_t mc;
2083 mbx_cmd_t *mcp = &mc;
2084 dma_addr_t pdb_dma;
2085 int rval;
2086
2087 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1115,
2088 "Entered %s.\n", __func__);
2089
2090 memset(pdb, 0, sizeof(*pdb));
2091
2092 pdb_dma = dma_map_single(&vha->hw->pdev->dev, pdb,
2093 sizeof(*pdb), DMA_FROM_DEVICE);
2094 if (!pdb_dma) {
2095 ql_log(ql_log_warn, vha, 0x1116, "Failed to map dma buffer.\n");
2096 return QLA_MEMORY_ALLOC_FAILED;
2097 }
2098
2099 mcp->mb[0] = MBC_GET_PORT_DATABASE;
2100 mcp->mb[1] = nport_handle;
2101 mcp->mb[2] = MSW(LSD(pdb_dma));
2102 mcp->mb[3] = LSW(LSD(pdb_dma));
2103 mcp->mb[6] = MSW(MSD(pdb_dma));
2104 mcp->mb[7] = LSW(MSD(pdb_dma));
2105 mcp->mb[9] = 0;
2106 mcp->mb[10] = 0;
2107 mcp->out_mb = MBX_10|MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
2108 mcp->in_mb = MBX_1|MBX_0;
2109 mcp->buf_size = sizeof(*pdb);
2110 mcp->flags = MBX_DMA_IN;
2111 mcp->tov = vha->hw->login_timeout * 2;
2112 rval = qla2x00_mailbox_command(vha, mcp);
2113
2114 if (rval != QLA_SUCCESS) {
2115 ql_dbg(ql_dbg_mbx, vha, 0x111a,
2116 "Failed=%x mb[0]=%x mb[1]=%x.\n",
2117 rval, mcp->mb[0], mcp->mb[1]);
2118 } else {
2119 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111b,
2120 "Done %s.\n", __func__);
2121 }
2122
2123 dma_unmap_single(&vha->hw->pdev->dev, pdb_dma,
2124 sizeof(*pdb), DMA_FROM_DEVICE);
2125
2126 return rval;
2127}
2128
1da177e4
LT		 2129/*
2130 * qla2x00_get_firmware_state
2131 * Get adapter firmware state.
2132 *
2133 * Input:
2134 * ha = adapter block pointer.
2135 * dptr = pointer for firmware state.
2136 * TARGET_QUEUE_LOCK must be released.
2137 * ADAPTER_STATE_LOCK must be released.
2138 *
2139 * Returns:
2140 * qla2x00 local function return status code.
2141 *
2142 * Context:
2143 * Kernel context.
2144 */
2145int
7b867cf7 2146qla2x00_get_firmware_state(scsi_qla_host_t *vha, uint16_t *states)
1da177e4
LT		 2147{
2148 int rval;
2149 mbx_cmd_t mc;
2150 mbx_cmd_t *mcp = &mc;
92d4408e 2151 struct qla_hw_data *ha = vha->hw;
1da177e4 2152
5f28d2d7
SK		 2153 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1054,
2154 "Entered %s.\n", __func__);
1da177e4
LT		 2155
2156 mcp->mb[0] = MBC_GET_FIRMWARE_STATE;
2157 mcp->out_mb = MBX_0;
9d2683c0 2158 if (IS_FWI2_CAPABLE(vha->hw))
b5a340dd 2159 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
9d2683c0
AV		 2160 else
2161 mcp->in_mb = MBX_1|MBX_0;
b93480e3 2162 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2163 mcp->flags = 0;
7b867cf7 2164 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4 2165
4d4df193
HK		 2166 /* Return firmware states. */
2167 states[0] = mcp->mb[1];
9d2683c0
AV		 2168 if (IS_FWI2_CAPABLE(vha->hw)) {
2169 states[1] = mcp->mb[2];
ec891462 2170 states[2] = mcp->mb[3]; /* SFP info */
9d2683c0
AV		 2171 states[3] = mcp->mb[4];
2172 states[4] = mcp->mb[5];
b5a340dd 2173 states[5] = mcp->mb[6]; /* DPORT status */
9d2683c0 2174 }
1da177e4
LT		 2175
2176 if (rval != QLA_SUCCESS) {
2177 /*EMPTY*/
7c3df132 2178 ql_dbg(ql_dbg_mbx, vha, 0x1055, "Failed=%x.\n", rval);
1da177e4 2179 } else {
ecc89f25 2180 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
92d4408e
SC		 2181 if (mcp->mb[2] == 6 || mcp->mb[3] == 2)
2182 ql_dbg(ql_dbg_mbx, vha, 0x119e,
2183 "Invalid SFP/Validation Failed\n");
2184 }
5f28d2d7
SK		 2185 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1056,
2186 "Done %s.\n", __func__);
1da177e4
LT		 2187 }
2188
2189 return rval;
2190}
2191
2192/*
2193 * qla2x00_get_port_name
2194 * Issue get port name mailbox command.
2195 * Returned name is in big endian format.
2196 *
2197 * Input:
2198 * ha = adapter block pointer.
2199 * loop_id = loop ID of device.
2200 * name = pointer for name.
2201 * TARGET_QUEUE_LOCK must be released.
2202 * ADAPTER_STATE_LOCK must be released.
2203 *
2204 * Returns:
2205 * qla2x00 local function return status code.
2206 *
2207 * Context:
2208 * Kernel context.
2209 */
2210int
7b867cf7 2211qla2x00_get_port_name(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t *name,
1da177e4
LT		 2212 uint8_t opt)
2213{
2214 int rval;
2215 mbx_cmd_t mc;
2216 mbx_cmd_t *mcp = &mc;
2217
5f28d2d7
SK		 2218 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1057,
2219 "Entered %s.\n", __func__);
1da177e4
LT		 2220
2221 mcp->mb[0] = MBC_GET_PORT_NAME;
7b867cf7 2222 mcp->mb[9] = vha->vp_idx;
2c3dfe3f 2223 mcp->out_mb = MBX_9|MBX_1|MBX_0;
7b867cf7 2224 if (HAS_EXTENDED_IDS(vha->hw)) {
1da177e4
LT		 2225 mcp->mb[1] = loop_id;
2226 mcp->mb[10] = opt;
2227 mcp->out_mb |= MBX_10;
2228 } else {
2229 mcp->mb[1] = loop_id << 8 | opt;
2230 }
2231
2232 mcp->in_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
b93480e3 2233 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2234 mcp->flags = 0;
7b867cf7 2235 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2236
2237 if (rval != QLA_SUCCESS) {
2238 /*EMPTY*/
7c3df132 2239 ql_dbg(ql_dbg_mbx, vha, 0x1058, "Failed=%x.\n", rval);
1da177e4
LT		 2240 } else {
2241 if (name != NULL) {
2242 /* This function returns name in big endian. */
1196ae02
RL		 2243 name[0] = MSB(mcp->mb[2]);
2244 name[1] = LSB(mcp->mb[2]);
2245 name[2] = MSB(mcp->mb[3]);
2246 name[3] = LSB(mcp->mb[3]);
2247 name[4] = MSB(mcp->mb[6]);
2248 name[5] = LSB(mcp->mb[6]);
2249 name[6] = MSB(mcp->mb[7]);
2250 name[7] = LSB(mcp->mb[7]);
1da177e4
LT		 2251 }
2252
5f28d2d7
SK		 2253 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1059,
2254 "Done %s.\n", __func__);
1da177e4
LT		 2255 }
2256
2257 return rval;
2258}
2259
61e1b269
JC		 2260/*
2261 * qla24xx_link_initialization
2262 * Issue link initialization mailbox command.
2263 *
2264 * Input:
2265 * ha = adapter block pointer.
2266 * TARGET_QUEUE_LOCK must be released.
2267 * ADAPTER_STATE_LOCK must be released.
2268 *
2269 * Returns:
2270 * qla2x00 local function return status code.
2271 *
2272 * Context:
2273 * Kernel context.
2274 */
2275int
2276qla24xx_link_initialize(scsi_qla_host_t *vha)
2277{
2278 int rval;
2279 mbx_cmd_t mc;
2280 mbx_cmd_t *mcp = &mc;
2281
2282 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1152,
2283 "Entered %s.\n", __func__);
2284
2285 if (!IS_FWI2_CAPABLE(vha->hw) || IS_CNA_CAPABLE(vha->hw))
2286 return QLA_FUNCTION_FAILED;
2287
2288 mcp->mb[0] = MBC_LINK_INITIALIZATION;
5a5c27b6
JC		 2289 mcp->mb[1] = BIT_4;
2290 if (vha->hw->operating_mode == LOOP)
2291 mcp->mb[1] |= BIT_6;
2292 else
2293 mcp->mb[1] |= BIT_5;
61e1b269
JC		 2294 mcp->mb[2] = 0;
2295 mcp->mb[3] = 0;
2296 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
2297 mcp->in_mb = MBX_0;
2298 mcp->tov = MBX_TOV_SECONDS;
2299 mcp->flags = 0;
2300 rval = qla2x00_mailbox_command(vha, mcp);
2301
2302 if (rval != QLA_SUCCESS) {
2303 ql_dbg(ql_dbg_mbx, vha, 0x1153, "Failed=%x.\n", rval);
2304 } else {
2305 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1154,
2306 "Done %s.\n", __func__);
2307 }
2308
2309 return rval;
2310}
2311
1da177e4
LT		 2312/*
2313 * qla2x00_lip_reset
2314 * Issue LIP reset mailbox command.
2315 *
2316 * Input:
2317 * ha = adapter block pointer.
2318 * TARGET_QUEUE_LOCK must be released.
2319 * ADAPTER_STATE_LOCK must be released.
2320 *
2321 * Returns:
2322 * qla2x00 local function return status code.
2323 *
2324 * Context:
2325 * Kernel context.
2326 */
2327int
7b867cf7 2328qla2x00_lip_reset(scsi_qla_host_t *vha)
1da177e4
LT		 2329{
2330 int rval;
2331 mbx_cmd_t mc;
2332 mbx_cmd_t *mcp = &mc;
2333
7f2a398d 2334 ql_dbg(ql_dbg_disc, vha, 0x105a,
5f28d2d7 2335 "Entered %s.\n", __func__);
1da177e4 2336
6246b8a1 2337 if (IS_CNA_CAPABLE(vha->hw)) {
3a03eb79
AV		 2338 /* Logout across all FCFs. */
2339 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
2340 mcp->mb[1] = BIT_1;
2341 mcp->mb[2] = 0;
2342 mcp->out_mb = MBX_2|MBX_1|MBX_0;
2343 } else if (IS_FWI2_CAPABLE(vha->hw)) {
1c7c6357 2344 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
87d6814a 2345 mcp->mb[1] = BIT_4;
0c8c39af 2346 mcp->mb[2] = 0;
7b867cf7 2347 mcp->mb[3] = vha->hw->loop_reset_delay;
1c7c6357 2348 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1da177e4 2349 } else {
1c7c6357
AV		 2350 mcp->mb[0] = MBC_LIP_RESET;
2351 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
7b867cf7 2352 if (HAS_EXTENDED_IDS(vha->hw)) {
1c7c6357
AV		 2353 mcp->mb[1] = 0x00ff;
2354 mcp->mb[10] = 0;
2355 mcp->out_mb |= MBX_10;
2356 } else {
2357 mcp->mb[1] = 0xff00;
2358 }
7b867cf7 2359 mcp->mb[2] = vha->hw->loop_reset_delay;
1c7c6357 2360 mcp->mb[3] = 0;
1da177e4 2361 }
1da177e4 2362 mcp->in_mb = MBX_0;
b93480e3 2363 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2364 mcp->flags = 0;
7b867cf7 2365 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2366
2367 if (rval != QLA_SUCCESS) {
2368 /*EMPTY*/
7c3df132 2369 ql_dbg(ql_dbg_mbx, vha, 0x105b, "Failed=%x.\n", rval);
1da177e4
LT		 2370 } else {
2371 /*EMPTY*/
5f28d2d7
SK		 2372 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105c,
2373 "Done %s.\n", __func__);
1da177e4
LT		 2374 }
2375
2376 return rval;
2377}
2378
2379/*
2380 * qla2x00_send_sns
2381 * Send SNS command.
2382 *
2383 * Input:
2384 * ha = adapter block pointer.
2385 * sns = pointer for command.
2386 * cmd_size = command size.
2387 * buf_size = response/command size.
2388 * TARGET_QUEUE_LOCK must be released.
2389 * ADAPTER_STATE_LOCK must be released.
2390 *
2391 * Returns:
2392 * qla2x00 local function return status code.
2393 *
2394 * Context:
2395 * Kernel context.
2396 */
2397int
7b867cf7 2398qla2x00_send_sns(scsi_qla_host_t *vha, dma_addr_t sns_phys_address,
1da177e4
LT		 2399 uint16_t cmd_size, size_t buf_size)
2400{
2401 int rval;
2402 mbx_cmd_t mc;
2403 mbx_cmd_t *mcp = &mc;
2404
5f28d2d7
SK		 2405 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105d,
2406 "Entered %s.\n", __func__);
1da177e4 2407
5f28d2d7 2408 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105e,
7c3df132
SK		 2409 "Retry cnt=%d ratov=%d total tov=%d.\n",
2410 vha->hw->retry_count, vha->hw->login_timeout, mcp->tov);
1da177e4
LT		 2411
2412 mcp->mb[0] = MBC_SEND_SNS_COMMAND;
2413 mcp->mb[1] = cmd_size;
2414 mcp->mb[2] = MSW(sns_phys_address);
2415 mcp->mb[3] = LSW(sns_phys_address);
2416 mcp->mb[6] = MSW(MSD(sns_phys_address));
2417 mcp->mb[7] = LSW(MSD(sns_phys_address));
2418 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
2419 mcp->in_mb = MBX_0|MBX_1;
2420 mcp->buf_size = buf_size;
2421 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN;
7b867cf7
AC		 2422 mcp->tov = (vha->hw->login_timeout * 2) + (vha->hw->login_timeout / 2);
2423 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2424
2425 if (rval != QLA_SUCCESS) {
2426 /*EMPTY*/
7c3df132
SK		 2427 ql_dbg(ql_dbg_mbx, vha, 0x105f,
2428 "Failed=%x mb[0]=%x mb[1]=%x.\n",
2429 rval, mcp->mb[0], mcp->mb[1]);
1da177e4
LT		 2430 } else {
2431 /*EMPTY*/
5f28d2d7
SK		 2432 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1060,
2433 "Done %s.\n", __func__);
1da177e4
LT		 2434 }
2435
2436 return rval;
2437}
2438
1c7c6357 2439int
7b867cf7 2440qla24xx_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
1c7c6357
AV		 2441 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
2442{
2443 int rval;
2444
2445 struct logio_entry_24xx *lg;
2446 dma_addr_t lg_dma;
2447 uint32_t iop[2];
7b867cf7 2448 struct qla_hw_data *ha = vha->hw;
2afa19a9 2449 struct req_que *req;
1c7c6357 2450
5f28d2d7
SK		 2451 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1061,
2452 "Entered %s.\n", __func__);
1c7c6357 2453
d7459527
MH		 2454 if (vha->vp_idx && vha->qpair)
2455 req = vha->qpair->req;
68ca949c 2456 else
d7459527 2457 req = ha->req_q_map[0];
2afa19a9 2458
08eb7f45 2459 lg = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
1c7c6357 2460 if (lg == NULL) {
7c3df132
SK		 2461 ql_log(ql_log_warn, vha, 0x1062,
2462 "Failed to allocate login IOCB.\n");
1c7c6357
AV		 2463 return QLA_MEMORY_ALLOC_FAILED;
2464 }
1c7c6357
AV		 2465
2466 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
2467 lg->entry_count = 1;
c25eb70a 2468 lg->handle = make_handle(req->id, lg->handle);
1c7c6357 2469 lg->nport_handle = cpu_to_le16(loop_id);
ad950360 2470 lg->control_flags = cpu_to_le16(LCF_COMMAND_PLOGI);
1c7c6357 2471 if (opt & BIT_0)
ad950360 2472 lg->control_flags |= cpu_to_le16(LCF_COND_PLOGI);
8baa51a6 2473 if (opt & BIT_1)
ad950360 2474 lg->control_flags |= cpu_to_le16(LCF_SKIP_PRLI);
1c7c6357
AV		 2475 lg->port_id[0] = al_pa;
2476 lg->port_id[1] = area;
2477 lg->port_id[2] = domain;
7b867cf7 2478 lg->vp_index = vha->vp_idx;
7f45dd0b
AV		 2479 rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0,
2480 (ha->r_a_tov / 10 * 2) + 2);
1c7c6357 2481 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2482 ql_dbg(ql_dbg_mbx, vha, 0x1063,
2483 "Failed to issue login IOCB (%x).\n", rval);
1c7c6357 2484 } else if (lg->entry_status != 0) {
7c3df132
SK		 2485 ql_dbg(ql_dbg_mbx, vha, 0x1064,
2486 "Failed to complete IOCB -- error status (%x).\n",
2487 lg->entry_status);
1c7c6357 2488 rval = QLA_FUNCTION_FAILED;
ad950360 2489 } else if (lg->comp_status != cpu_to_le16(CS_COMPLETE)) {
1c7c6357
AV		 2490 iop[0] = le32_to_cpu(lg->io_parameter[0]);
2491 iop[1] = le32_to_cpu(lg->io_parameter[1]);
2492
7c3df132
SK		 2493 ql_dbg(ql_dbg_mbx, vha, 0x1065,
2494 "Failed to complete IOCB -- completion status (%x) "
2495 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
2496 iop[0], iop[1]);
1c7c6357
AV		 2497
2498 switch (iop[0]) {
2499 case LSC_SCODE_PORTID_USED:
2500 mb[0] = MBS_PORT_ID_USED;
2501 mb[1] = LSW(iop[1]);
2502 break;
2503 case LSC_SCODE_NPORT_USED:
2504 mb[0] = MBS_LOOP_ID_USED;
2505 break;
2506 case LSC_SCODE_NOLINK:
2507 case LSC_SCODE_NOIOCB:
2508 case LSC_SCODE_NOXCB:
2509 case LSC_SCODE_CMD_FAILED:
2510 case LSC_SCODE_NOFABRIC:
2511 case LSC_SCODE_FW_NOT_READY:
2512 case LSC_SCODE_NOT_LOGGED_IN:
2513 case LSC_SCODE_NOPCB:
2514 case LSC_SCODE_ELS_REJECT:
2515 case LSC_SCODE_CMD_PARAM_ERR:
2516 case LSC_SCODE_NONPORT:
2517 case LSC_SCODE_LOGGED_IN:
2518 case LSC_SCODE_NOFLOGI_ACC:
2519 default:
2520 mb[0] = MBS_COMMAND_ERROR;
2521 break;
2522 }
2523 } else {
5f28d2d7
SK		 2524 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1066,
2525 "Done %s.\n", __func__);
1c7c6357
AV		 2526
2527 iop[0] = le32_to_cpu(lg->io_parameter[0]);
2528
2529 mb[0] = MBS_COMMAND_COMPLETE;
2530 mb[1] = 0;
2531 if (iop[0] & BIT_4) {
2532 if (iop[0] & BIT_8)
2533 mb[1] |= BIT_1;
2534 } else
2535 mb[1] = BIT_0;
ad3e0eda
AV		 2536
2537 /* Passback COS information. */
2538 mb[10] = 0;
2539 if (lg->io_parameter[7] || lg->io_parameter[8])
2540 mb[10] |= BIT_0; /* Class 2. */
2541 if (lg->io_parameter[9] || lg->io_parameter[10])
2542 mb[10] |= BIT_1; /* Class 3. */
ad950360 2543 if (lg->io_parameter[0] & cpu_to_le32(BIT_7))
2d70c103
NB		 2544 mb[10] |= BIT_7; /* Confirmed Completion
2545 * Allowed
2546 */
1c7c6357
AV		 2547 }
2548
2549 dma_pool_free(ha->s_dma_pool, lg, lg_dma);
2550
2551 return rval;
2552}
2553
1da177e4
LT		 2554/*
2555 * qla2x00_login_fabric
2556 * Issue login fabric port mailbox command.
2557 *
2558 * Input:
2559 * ha = adapter block pointer.
2560 * loop_id = device loop ID.
2561 * domain = device domain.
2562 * area = device area.
2563 * al_pa = device AL_PA.
2564 * status = pointer for return status.
2565 * opt = command options.
2566 * TARGET_QUEUE_LOCK must be released.
2567 * ADAPTER_STATE_LOCK must be released.
2568 *
2569 * Returns:
2570 * qla2x00 local function return status code.
2571 *
2572 * Context:
2573 * Kernel context.
2574 */
2575int
7b867cf7 2576qla2x00_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
1da177e4
LT		 2577 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
2578{
2579 int rval;
2580 mbx_cmd_t mc;
2581 mbx_cmd_t *mcp = &mc;
7b867cf7 2582 struct qla_hw_data *ha = vha->hw;
1da177e4 2583
5f28d2d7
SK		 2584 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1067,
2585 "Entered %s.\n", __func__);
1da177e4
LT		 2586
2587 mcp->mb[0] = MBC_LOGIN_FABRIC_PORT;
2588 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
2589 if (HAS_EXTENDED_IDS(ha)) {
2590 mcp->mb[1] = loop_id;
2591 mcp->mb[10] = opt;
2592 mcp->out_mb |= MBX_10;
2593 } else {
2594 mcp->mb[1] = (loop_id << 8) | opt;
2595 }
2596 mcp->mb[2] = domain;
2597 mcp->mb[3] = area << 8 | al_pa;
2598
2599 mcp->in_mb = MBX_7|MBX_6|MBX_2|MBX_1|MBX_0;
2600 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
2601 mcp->flags = 0;
7b867cf7 2602 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2603
2604 /* Return mailbox statuses. */
2605 if (mb != NULL) {
2606 mb[0] = mcp->mb[0];
2607 mb[1] = mcp->mb[1];
2608 mb[2] = mcp->mb[2];
2609 mb[6] = mcp->mb[6];
2610 mb[7] = mcp->mb[7];
ad3e0eda
AV		 2611 /* COS retrieved from Get-Port-Database mailbox command. */
2612 mb[10] = 0;
1da177e4
LT		 2613 }
2614
2615 if (rval != QLA_SUCCESS) {
2616 /* RLU tmp code: need to change main mailbox_command function to
2617 * return ok even when the mailbox completion value is not
2618 * SUCCESS. The caller needs to be responsible to interpret
2619 * the return values of this mailbox command if we're not
2620 * to change too much of the existing code.
2621 */
2622 if (mcp->mb[0] == 0x4001 || mcp->mb[0] == 0x4002 ||
2623 mcp->mb[0] == 0x4003 || mcp->mb[0] == 0x4005 ||
2624 mcp->mb[0] == 0x4006)
2625 rval = QLA_SUCCESS;
2626
2627 /*EMPTY*/
7c3df132
SK		 2628 ql_dbg(ql_dbg_mbx, vha, 0x1068,
2629 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
2630 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
1da177e4
LT		 2631 } else {
2632 /*EMPTY*/
5f28d2d7
SK		 2633 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1069,
2634 "Done %s.\n", __func__);
1da177e4
LT		 2635 }
2636
2637 return rval;
2638}
2639
2640/*
2641 * qla2x00_login_local_device
2642 * Issue login loop port mailbox command.
fa2a1ce5 2643 *
1da177e4
LT		 2644 * Input:
2645 * ha = adapter block pointer.
2646 * loop_id = device loop ID.
2647 * opt = command options.
fa2a1ce5 2648 *
1da177e4
LT		 2649 * Returns:
2650 * Return status code.
fa2a1ce5 2651 *
1da177e4
LT		 2652 * Context:
2653 * Kernel context.
fa2a1ce5 2654 *
1da177e4
LT		 2655 */
2656int
7b867cf7 2657qla2x00_login_local_device(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 2658 uint16_t *mb_ret, uint8_t opt)
2659{
2660 int rval;
2661 mbx_cmd_t mc;
2662 mbx_cmd_t *mcp = &mc;
7b867cf7 2663 struct qla_hw_data *ha = vha->hw;
1da177e4 2664
5f28d2d7
SK		 2665 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106a,
2666 "Entered %s.\n", __func__);
7c3df132 2667
e428924c 2668 if (IS_FWI2_CAPABLE(ha))
7b867cf7 2669 return qla24xx_login_fabric(vha, fcport->loop_id,
9a52a57c
AV		 2670 fcport->d_id.b.domain, fcport->d_id.b.area,
2671 fcport->d_id.b.al_pa, mb_ret, opt);
2672
1da177e4
LT		 2673 mcp->mb[0] = MBC_LOGIN_LOOP_PORT;
2674 if (HAS_EXTENDED_IDS(ha))
9a52a57c 2675 mcp->mb[1] = fcport->loop_id;
1da177e4 2676 else
9a52a57c 2677 mcp->mb[1] = fcport->loop_id << 8;
1da177e4
LT		 2678 mcp->mb[2] = opt;
2679 mcp->out_mb = MBX_2|MBX_1|MBX_0;
2680 mcp->in_mb = MBX_7|MBX_6|MBX_1|MBX_0;
2681 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
2682 mcp->flags = 0;
7b867cf7 2683 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2684
2685 /* Return mailbox statuses. */
2686 if (mb_ret != NULL) {
2687 mb_ret[0] = mcp->mb[0];
2688 mb_ret[1] = mcp->mb[1];
2689 mb_ret[6] = mcp->mb[6];
2690 mb_ret[7] = mcp->mb[7];
2691 }
2692
2693 if (rval != QLA_SUCCESS) {
2694 /* AV tmp code: need to change main mailbox_command function to
2695 * return ok even when the mailbox completion value is not
2696 * SUCCESS. The caller needs to be responsible to interpret
2697 * the return values of this mailbox command if we're not
2698 * to change too much of the existing code.
2699 */
2700 if (mcp->mb[0] == 0x4005 || mcp->mb[0] == 0x4006)
2701 rval = QLA_SUCCESS;
2702
7c3df132
SK		 2703 ql_dbg(ql_dbg_mbx, vha, 0x106b,
2704 "Failed=%x mb[0]=%x mb[1]=%x mb[6]=%x mb[7]=%x.\n",
2705 rval, mcp->mb[0], mcp->mb[1], mcp->mb[6], mcp->mb[7]);
1da177e4
LT		 2706 } else {
2707 /*EMPTY*/
5f28d2d7
SK		 2708 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106c,
2709 "Done %s.\n", __func__);
1da177e4
LT		 2710 }
2711
2712 return (rval);
2713}
2714
1c7c6357 2715int
7b867cf7 2716qla24xx_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
1c7c6357
AV		 2717 uint8_t area, uint8_t al_pa)
2718{
2719 int rval;
2720 struct logio_entry_24xx *lg;
2721 dma_addr_t lg_dma;
7b867cf7 2722 struct qla_hw_data *ha = vha->hw;
2afa19a9 2723 struct req_que *req;
1c7c6357 2724
5f28d2d7
SK		 2725 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106d,
2726 "Entered %s.\n", __func__);
1c7c6357 2727
08eb7f45 2728 lg = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
1c7c6357 2729 if (lg == NULL) {
7c3df132
SK		 2730 ql_log(ql_log_warn, vha, 0x106e,
2731 "Failed to allocate logout IOCB.\n");
1c7c6357
AV		 2732 return QLA_MEMORY_ALLOC_FAILED;
2733 }
1c7c6357 2734
d7459527 2735 req = vha->req;
1c7c6357
AV		 2736 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
2737 lg->entry_count = 1;
c25eb70a 2738 lg->handle = make_handle(req->id, lg->handle);
1c7c6357
AV		 2739 lg->nport_handle = cpu_to_le16(loop_id);
2740 lg->control_flags =
ad950360 2741 cpu_to_le16(LCF_COMMAND_LOGO|LCF_IMPL_LOGO|
c8d6691b 2742 LCF_FREE_NPORT);
1c7c6357
AV		 2743 lg->port_id[0] = al_pa;
2744 lg->port_id[1] = area;
2745 lg->port_id[2] = domain;
7b867cf7 2746 lg->vp_index = vha->vp_idx;
7f45dd0b
AV		 2747 rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0,
2748 (ha->r_a_tov / 10 * 2) + 2);
1c7c6357 2749 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2750 ql_dbg(ql_dbg_mbx, vha, 0x106f,
2751 "Failed to issue logout IOCB (%x).\n", rval);
1c7c6357 2752 } else if (lg->entry_status != 0) {
7c3df132
SK		 2753 ql_dbg(ql_dbg_mbx, vha, 0x1070,
2754 "Failed to complete IOCB -- error status (%x).\n",
2755 lg->entry_status);
1c7c6357 2756 rval = QLA_FUNCTION_FAILED;
ad950360 2757 } else if (lg->comp_status != cpu_to_le16(CS_COMPLETE)) {
7c3df132
SK		 2758 ql_dbg(ql_dbg_mbx, vha, 0x1071,
2759 "Failed to complete IOCB -- completion status (%x) "
2760 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
1c7c6357 2761 le32_to_cpu(lg->io_parameter[0]),
7c3df132 2762 le32_to_cpu(lg->io_parameter[1]));
1c7c6357
AV		 2763 } else {
2764 /*EMPTY*/
5f28d2d7
SK		 2765 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1072,
2766 "Done %s.\n", __func__);
1c7c6357
AV		 2767 }
2768
2769 dma_pool_free(ha->s_dma_pool, lg, lg_dma);
2770
2771 return rval;
2772}
2773
1da177e4
LT		 2774/*
2775 * qla2x00_fabric_logout
2776 * Issue logout fabric port mailbox command.
2777 *
2778 * Input:
2779 * ha = adapter block pointer.
2780 * loop_id = device loop ID.
2781 * TARGET_QUEUE_LOCK must be released.
2782 * ADAPTER_STATE_LOCK must be released.
2783 *
2784 * Returns:
2785 * qla2x00 local function return status code.
2786 *
2787 * Context:
2788 * Kernel context.
2789 */
2790int
7b867cf7 2791qla2x00_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
1c7c6357 2792 uint8_t area, uint8_t al_pa)
1da177e4
LT		 2793{
2794 int rval;
2795 mbx_cmd_t mc;
2796 mbx_cmd_t *mcp = &mc;
2797
5f28d2d7
SK		 2798 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1073,
2799 "Entered %s.\n", __func__);
1da177e4
LT		 2800
2801 mcp->mb[0] = MBC_LOGOUT_FABRIC_PORT;
2802 mcp->out_mb = MBX_1|MBX_0;
7b867cf7 2803 if (HAS_EXTENDED_IDS(vha->hw)) {
1da177e4
LT		 2804 mcp->mb[1] = loop_id;
2805 mcp->mb[10] = 0;
2806 mcp->out_mb |= MBX_10;
2807 } else {
2808 mcp->mb[1] = loop_id << 8;
2809 }
2810
2811 mcp->in_mb = MBX_1|MBX_0;
b93480e3 2812 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2813 mcp->flags = 0;
7b867cf7 2814 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2815
2816 if (rval != QLA_SUCCESS) {
2817 /*EMPTY*/
7c3df132
SK		 2818 ql_dbg(ql_dbg_mbx, vha, 0x1074,
2819 "Failed=%x mb[1]=%x.\n", rval, mcp->mb[1]);
1da177e4
LT		 2820 } else {
2821 /*EMPTY*/
5f28d2d7
SK		 2822 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1075,
2823 "Done %s.\n", __func__);
1da177e4
LT		 2824 }
2825
2826 return rval;
2827}
2828
2829/*
2830 * qla2x00_full_login_lip
2831 * Issue full login LIP mailbox command.
2832 *
2833 * Input:
2834 * ha = adapter block pointer.
2835 * TARGET_QUEUE_LOCK must be released.
2836 * ADAPTER_STATE_LOCK must be released.
2837 *
2838 * Returns:
2839 * qla2x00 local function return status code.
2840 *
2841 * Context:
2842 * Kernel context.
2843 */
2844int
7b867cf7 2845qla2x00_full_login_lip(scsi_qla_host_t *vha)
1da177e4
LT		 2846{
2847 int rval;
2848 mbx_cmd_t mc;
2849 mbx_cmd_t *mcp = &mc;
2850
5f28d2d7
SK		 2851 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1076,
2852 "Entered %s.\n", __func__);
1da177e4
LT		 2853
2854 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
87d6814a 2855 mcp->mb[1] = IS_FWI2_CAPABLE(vha->hw) ? BIT_4 : 0;
0c8c39af 2856 mcp->mb[2] = 0;
1da177e4
LT		 2857 mcp->mb[3] = 0;
2858 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
2859 mcp->in_mb = MBX_0;
b93480e3 2860 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2861 mcp->flags = 0;
7b867cf7 2862 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2863
2864 if (rval != QLA_SUCCESS) {
2865 /*EMPTY*/
7c3df132 2866 ql_dbg(ql_dbg_mbx, vha, 0x1077, "Failed=%x.\n", rval);
1da177e4
LT		 2867 } else {
2868 /*EMPTY*/
5f28d2d7
SK		 2869 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1078,
2870 "Done %s.\n", __func__);
1da177e4
LT		 2871 }
2872
2873 return rval;
2874}
2875
2876/*
2877 * qla2x00_get_id_list
2878 *
2879 * Input:
2880 * ha = adapter block pointer.
2881 *
2882 * Returns:
2883 * qla2x00 local function return status code.
2884 *
2885 * Context:
2886 * Kernel context.
2887 */
2888int
7b867cf7 2889qla2x00_get_id_list(scsi_qla_host_t *vha, void *id_list, dma_addr_t id_list_dma,
1da177e4
LT		 2890 uint16_t *entries)
2891{
2892 int rval;
2893 mbx_cmd_t mc;
2894 mbx_cmd_t *mcp = &mc;
2895
5f28d2d7
SK		 2896 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1079,
2897 "Entered %s.\n", __func__);
1da177e4
LT		 2898
2899 if (id_list == NULL)
2900 return QLA_FUNCTION_FAILED;
2901
2902 mcp->mb[0] = MBC_GET_ID_LIST;
1c7c6357 2903 mcp->out_mb = MBX_0;
7b867cf7 2904 if (IS_FWI2_CAPABLE(vha->hw)) {
1c7c6357
AV		 2905 mcp->mb[2] = MSW(id_list_dma);
2906 mcp->mb[3] = LSW(id_list_dma);
2907 mcp->mb[6] = MSW(MSD(id_list_dma));
2908 mcp->mb[7] = LSW(MSD(id_list_dma));
247ec457 2909 mcp->mb[8] = 0;
7b867cf7 2910 mcp->mb[9] = vha->vp_idx;
2c3dfe3f 2911 mcp->out_mb |= MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2;
1c7c6357
AV		 2912 } else {
2913 mcp->mb[1] = MSW(id_list_dma);
2914 mcp->mb[2] = LSW(id_list_dma);
2915 mcp->mb[3] = MSW(MSD(id_list_dma));
2916 mcp->mb[6] = LSW(MSD(id_list_dma));
2917 mcp->out_mb |= MBX_6|MBX_3|MBX_2|MBX_1;
2918 }
1da177e4 2919 mcp->in_mb = MBX_1|MBX_0;
b93480e3 2920 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2921 mcp->flags = 0;
7b867cf7 2922 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2923
2924 if (rval != QLA_SUCCESS) {
2925 /*EMPTY*/
7c3df132 2926 ql_dbg(ql_dbg_mbx, vha, 0x107a, "Failed=%x.\n", rval);
1da177e4
LT		 2927 } else {
2928 *entries = mcp->mb[1];
5f28d2d7
SK		 2929 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107b,
2930 "Done %s.\n", __func__);
1da177e4
LT		 2931 }
2932
2933 return rval;
2934}
2935
2936/*
2937 * qla2x00_get_resource_cnts
2938 * Get current firmware resource counts.
2939 *
2940 * Input:
2941 * ha = adapter block pointer.
2942 *
2943 * Returns:
2944 * qla2x00 local function return status code.
2945 *
2946 * Context:
2947 * Kernel context.
2948 */
2949int
03e8c680 2950qla2x00_get_resource_cnts(scsi_qla_host_t *vha)
1da177e4 2951{
03e8c680 2952 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2953 int rval;
2954 mbx_cmd_t mc;
2955 mbx_cmd_t *mcp = &mc;
2956
5f28d2d7
SK		 2957 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107c,
2958 "Entered %s.\n", __func__);
1da177e4
LT		 2959
2960 mcp->mb[0] = MBC_GET_RESOURCE_COUNTS;
2961 mcp->out_mb = MBX_0;
4d0ea247 2962 mcp->in_mb = MBX_11|MBX_10|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
ecc89f25
JC		 2963 if (IS_QLA81XX(ha) || IS_QLA83XX(ha) ||
2964 IS_QLA27XX(ha) || IS_QLA28XX(ha))
f3a0a77e 2965 mcp->in_mb |= MBX_12;
b93480e3 2966 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2967 mcp->flags = 0;
7b867cf7 2968 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2969
2970 if (rval != QLA_SUCCESS) {
2971 /*EMPTY*/
7c3df132
SK		 2972 ql_dbg(ql_dbg_mbx, vha, 0x107d,
2973 "Failed mb[0]=%x.\n", mcp->mb[0]);
1da177e4 2974 } else {
5f28d2d7 2975 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107e,
7c3df132
SK		 2976 "Done %s mb1=%x mb2=%x mb3=%x mb6=%x mb7=%x mb10=%x "
2977 "mb11=%x mb12=%x.\n", __func__, mcp->mb[1], mcp->mb[2],
2978 mcp->mb[3], mcp->mb[6], mcp->mb[7], mcp->mb[10],
2979 mcp->mb[11], mcp->mb[12]);
1da177e4 2980
03e8c680
QT		 2981 ha->orig_fw_tgt_xcb_count = mcp->mb[1];
2982 ha->cur_fw_tgt_xcb_count = mcp->mb[2];
2983 ha->cur_fw_xcb_count = mcp->mb[3];
2984 ha->orig_fw_xcb_count = mcp->mb[6];
2985 ha->cur_fw_iocb_count = mcp->mb[7];
2986 ha->orig_fw_iocb_count = mcp->mb[10];
2987 if (ha->flags.npiv_supported)
2988 ha->max_npiv_vports = mcp->mb[11];
ecc89f25
JC		 2989 if (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
2990 IS_QLA28XX(ha))
03e8c680 2991 ha->fw_max_fcf_count = mcp->mb[12];
1da177e4
LT		 2992 }
2993
2994 return (rval);
2995}
2996
1da177e4
LT		 2997/*
2998 * qla2x00_get_fcal_position_map
2999 * Get FCAL (LILP) position map using mailbox command
3000 *
3001 * Input:
3002 * ha = adapter state pointer.
3003 * pos_map = buffer pointer (can be NULL).
3004 *
3005 * Returns:
3006 * qla2x00 local function return status code.
3007 *
3008 * Context:
3009 * Kernel context.
3010 */
3011int
7b867cf7 3012qla2x00_get_fcal_position_map(scsi_qla_host_t *vha, char *pos_map)
1da177e4
LT		 3013{
3014 int rval;
3015 mbx_cmd_t mc;
3016 mbx_cmd_t *mcp = &mc;
3017 char *pmap;
3018 dma_addr_t pmap_dma;
7b867cf7 3019 struct qla_hw_data *ha = vha->hw;
1da177e4 3020
5f28d2d7
SK		 3021 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107f,
3022 "Entered %s.\n", __func__);
7c3df132 3023
08eb7f45 3024 pmap = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &pmap_dma);
1da177e4 3025 if (pmap == NULL) {
7c3df132
SK		 3026 ql_log(ql_log_warn, vha, 0x1080,
3027 "Memory alloc failed.\n");
1da177e4
LT		 3028 return QLA_MEMORY_ALLOC_FAILED;
3029 }
1da177e4
LT		 3030
3031 mcp->mb[0] = MBC_GET_FC_AL_POSITION_MAP;
3032 mcp->mb[2] = MSW(pmap_dma);
3033 mcp->mb[3] = LSW(pmap_dma);
3034 mcp->mb[6] = MSW(MSD(pmap_dma));
3035 mcp->mb[7] = LSW(MSD(pmap_dma));
3036 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
3037 mcp->in_mb = MBX_1|MBX_0;
3038 mcp->buf_size = FCAL_MAP_SIZE;
3039 mcp->flags = MBX_DMA_IN;
3040 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
7b867cf7 3041 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 3042
3043 if (rval == QLA_SUCCESS) {
5f28d2d7 3044 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1081,
7c3df132
SK		 3045 "mb0/mb1=%x/%X FC/AL position map size (%x).\n",
3046 mcp->mb[0], mcp->mb[1], (unsigned)pmap[0]);
3047 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111d,
3048 pmap, pmap[0] + 1);
1da177e4
LT		 3049
3050 if (pos_map)
3051 memcpy(pos_map, pmap, FCAL_MAP_SIZE);
3052 }
3053 dma_pool_free(ha->s_dma_pool, pmap, pmap_dma);
3054
3055 if (rval != QLA_SUCCESS) {
7c3df132 3056 ql_dbg(ql_dbg_mbx, vha, 0x1082, "Failed=%x.\n", rval);
1da177e4 3057 } else {
5f28d2d7
SK		 3058 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1083,
3059 "Done %s.\n", __func__);
1da177e4
LT		 3060 }
3061
3062 return rval;
3063}
392e2f65
AV		 3064
3065/*
3066 * qla2x00_get_link_status
3067 *
3068 * Input:
3069 * ha = adapter block pointer.
3070 * loop_id = device loop ID.
3071 * ret_buf = pointer to link status return buffer.
3072 *
3073 * Returns:
3074 * 0 = success.
3075 * BIT_0 = mem alloc error.
3076 * BIT_1 = mailbox error.
3077 */
3078int
7b867cf7 3079qla2x00_get_link_status(scsi_qla_host_t *vha, uint16_t loop_id,
43ef0580 3080 struct link_statistics *stats, dma_addr_t stats_dma)
392e2f65
AV		 3081{
3082 int rval;
3083 mbx_cmd_t mc;
3084 mbx_cmd_t *mcp = &mc;
ab053c09 3085 uint32_t *iter = (uint32_t *)stats;
c6dc9905 3086 ushort dwords = offsetof(typeof(*stats), link_up_cnt)/sizeof(*iter);
7b867cf7 3087 struct qla_hw_data *ha = vha->hw;
392e2f65 3088
5f28d2d7
SK		 3089 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1084,
3090 "Entered %s.\n", __func__);
392e2f65 3091
392e2f65 3092 mcp->mb[0] = MBC_GET_LINK_STATUS;
c6dc9905
JC		 3093 mcp->mb[2] = MSW(LSD(stats_dma));
3094 mcp->mb[3] = LSW(LSD(stats_dma));
43ef0580
AV		 3095 mcp->mb[6] = MSW(MSD(stats_dma));
3096 mcp->mb[7] = LSW(MSD(stats_dma));
392e2f65
AV		 3097 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
3098 mcp->in_mb = MBX_0;
e428924c 3099 if (IS_FWI2_CAPABLE(ha)) {
392e2f65
AV		 3100 mcp->mb[1] = loop_id;
3101 mcp->mb[4] = 0;
3102 mcp->mb[10] = 0;
3103 mcp->out_mb |= MBX_10|MBX_4|MBX_1;
3104 mcp->in_mb |= MBX_1;
3105 } else if (HAS_EXTENDED_IDS(ha)) {
3106 mcp->mb[1] = loop_id;
3107 mcp->mb[10] = 0;
3108 mcp->out_mb |= MBX_10|MBX_1;
3109 } else {
3110 mcp->mb[1] = loop_id << 8;
3111 mcp->out_mb |= MBX_1;
3112 }
b93480e3 3113 mcp->tov = MBX_TOV_SECONDS;
392e2f65 3114 mcp->flags = IOCTL_CMD;
7b867cf7 3115 rval = qla2x00_mailbox_command(vha, mcp);
392e2f65
AV		 3116
3117 if (rval == QLA_SUCCESS) {
3118 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
7c3df132
SK		 3119 ql_dbg(ql_dbg_mbx, vha, 0x1085,
3120 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
43ef0580 3121 rval = QLA_FUNCTION_FAILED;
392e2f65 3122 } else {
c6dc9905 3123 /* Re-endianize - firmware data is le32. */
5f28d2d7
SK		 3124 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1086,
3125 "Done %s.\n", __func__);
da08ef5c
JC		 3126 for ( ; dwords--; iter++)
3127 le32_to_cpus(iter);
392e2f65
AV		 3128 }
3129 } else {
3130 /* Failed. */
7c3df132 3131 ql_dbg(ql_dbg_mbx, vha, 0x1087, "Failed=%x.\n", rval);
392e2f65
AV		 3132 }
3133
392e2f65
AV		 3134 return rval;
3135}
3136
3137int
7b867cf7 3138qla24xx_get_isp_stats(scsi_qla_host_t *vha, struct link_statistics *stats,
15f30a57 3139 dma_addr_t stats_dma, uint16_t options)
1c7c6357
AV		 3140{
3141 int rval;
3142 mbx_cmd_t mc;
3143 mbx_cmd_t *mcp = &mc;
ab053c09 3144 uint32_t *iter = (uint32_t *)stats;
818c7f87 3145 ushort dwords = sizeof(*stats)/sizeof(*iter);
1c7c6357 3146
5f28d2d7
SK		 3147 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1088,
3148 "Entered %s.\n", __func__);
1c7c6357 3149
15f30a57
QT		 3150 memset(&mc, 0, sizeof(mc));
3151 mc.mb[0] = MBC_GET_LINK_PRIV_STATS;
818c7f87
JC		 3152 mc.mb[2] = MSW(LSD(stats_dma));
3153 mc.mb[3] = LSW(LSD(stats_dma));
15f30a57
QT		 3154 mc.mb[6] = MSW(MSD(stats_dma));
3155 mc.mb[7] = LSW(MSD(stats_dma));
818c7f87 3156 mc.mb[8] = dwords;
7ffa5b93
BVA		 3157 mc.mb[9] = vha->vp_idx;
3158 mc.mb[10] = options;
15f30a57
QT		 3159
3160 rval = qla24xx_send_mb_cmd(vha, &mc);
1c7c6357
AV		 3161
3162 if (rval == QLA_SUCCESS) {
3163 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
7c3df132
SK		 3164 ql_dbg(ql_dbg_mbx, vha, 0x1089,
3165 "Failed mb[0]=%x.\n", mcp->mb[0]);
43ef0580 3166 rval = QLA_FUNCTION_FAILED;
1c7c6357 3167 } else {
5f28d2d7
SK		 3168 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108a,
3169 "Done %s.\n", __func__);
c6dc9905 3170 /* Re-endianize - firmware data is le32. */
da08ef5c
JC		 3171 for ( ; dwords--; iter++)
3172 le32_to_cpus(iter);
1c7c6357
AV		 3173 }
3174 } else {
3175 /* Failed. */
7c3df132 3176 ql_dbg(ql_dbg_mbx, vha, 0x108b, "Failed=%x.\n", rval);
1c7c6357
AV		 3177 }
3178
1c7c6357
AV		 3179 return rval;
3180}
1c7c6357
AV		 3181
3182int
2afa19a9 3183qla24xx_abort_command(srb_t *sp)
1c7c6357
AV		 3184{
3185 int rval;
1c7c6357
AV		 3186 unsigned long flags = 0;
3187
3188 struct abort_entry_24xx *abt;
3189 dma_addr_t abt_dma;
3190 uint32_t handle;
2afa19a9
AC		 3191 fc_port_t *fcport = sp->fcport;
3192 struct scsi_qla_host *vha = fcport->vha;
7b867cf7 3193 struct qla_hw_data *ha = vha->hw;
67c2e93a 3194 struct req_que *req = vha->req;
585def9b 3195 struct qla_qpair *qpair = sp->qpair;
1c7c6357 3196
5f28d2d7
SK		 3197 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108c,
3198 "Entered %s.\n", __func__);
1c7c6357 3199
45a76264 3200 if (sp->qpair)
d7459527 3201 req = sp->qpair->req;
585def9b
QT		 3202 else
3203 return QLA_FUNCTION_FAILED;
d7459527 3204
4440e46d
AB		 3205 if (ql2xasynctmfenable)
3206 return qla24xx_async_abort_command(sp);
3207
585def9b 3208 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
8d93f550 3209 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
7b867cf7 3210 if (req->outstanding_cmds[handle] == sp)
1c7c6357
AV		 3211 break;
3212 }
585def9b 3213 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
8d93f550 3214 if (handle == req->num_outstanding_cmds) {
1c7c6357
AV		 3215 /* Command not found. */
3216 return QLA_FUNCTION_FAILED;
3217 }
3218
08eb7f45 3219 abt = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &abt_dma);
1c7c6357 3220 if (abt == NULL) {
7c3df132
SK		 3221 ql_log(ql_log_warn, vha, 0x108d,
3222 "Failed to allocate abort IOCB.\n");
1c7c6357
AV		 3223 return QLA_MEMORY_ALLOC_FAILED;
3224 }
1c7c6357
AV		 3225
3226 abt->entry_type = ABORT_IOCB_TYPE;
3227 abt->entry_count = 1;
c25eb70a 3228 abt->handle = make_handle(req->id, abt->handle);
1c7c6357 3229 abt->nport_handle = cpu_to_le16(fcport->loop_id);
c25eb70a 3230 abt->handle_to_abort = make_handle(req->id, handle);
1c7c6357
AV		 3231 abt->port_id[0] = fcport->d_id.b.al_pa;
3232 abt->port_id[1] = fcport->d_id.b.area;
3233 abt->port_id[2] = fcport->d_id.b.domain;
c6d39e23 3234 abt->vp_index = fcport->vha->vp_idx;
73208dfd
AC		 3235
3236 abt->req_que_no = cpu_to_le16(req->id);
3237
7b867cf7 3238 rval = qla2x00_issue_iocb(vha, abt, abt_dma, 0);
1c7c6357 3239 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3240 ql_dbg(ql_dbg_mbx, vha, 0x108e,
3241 "Failed to issue IOCB (%x).\n", rval);
1c7c6357 3242 } else if (abt->entry_status != 0) {
7c3df132
SK		 3243 ql_dbg(ql_dbg_mbx, vha, 0x108f,
3244 "Failed to complete IOCB -- error status (%x).\n",
3245 abt->entry_status);
1c7c6357 3246 rval = QLA_FUNCTION_FAILED;
ad950360 3247 } else if (abt->nport_handle != cpu_to_le16(0)) {
7c3df132
SK		 3248 ql_dbg(ql_dbg_mbx, vha, 0x1090,
3249 "Failed to complete IOCB -- completion status (%x).\n",
3250 le16_to_cpu(abt->nport_handle));
7ffa5b93 3251 if (abt->nport_handle == cpu_to_le16(CS_IOCB_ERROR))
f934c9d0
CD		 3252 rval = QLA_FUNCTION_PARAMETER_ERROR;
3253 else
3254 rval = QLA_FUNCTION_FAILED;
1c7c6357 3255 } else {
5f28d2d7
SK		 3256 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1091,
3257 "Done %s.\n", __func__);
1c7c6357
AV		 3258 }
3259
3260 dma_pool_free(ha->s_dma_pool, abt, abt_dma);
3261
3262 return rval;
3263}
3264
3265struct tsk_mgmt_cmd {
3266 union {
3267 struct tsk_mgmt_entry tsk;
3268 struct sts_entry_24xx sts;
3269 } p;
3270};
3271
523ec773
AV		 3272static int
3273__qla24xx_issue_tmf(char *name, uint32_t type, struct fc_port *fcport,
9cb78c16 3274 uint64_t l, int tag)
1c7c6357 3275{
523ec773 3276 int rval, rval2;
1c7c6357 3277 struct tsk_mgmt_cmd *tsk;
9ca1d01f 3278 struct sts_entry_24xx *sts;
1c7c6357 3279 dma_addr_t tsk_dma;
7b867cf7
AC		 3280 scsi_qla_host_t *vha;
3281 struct qla_hw_data *ha;
73208dfd 3282 struct req_que *req;
d7459527 3283 struct qla_qpair *qpair;
1c7c6357 3284
7b867cf7
AC		 3285 vha = fcport->vha;
3286 ha = vha->hw;
2afa19a9 3287 req = vha->req;
7c3df132 3288
5f28d2d7
SK		 3289 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1092,
3290 "Entered %s.\n", __func__);
7c3df132 3291
d7459527
MH		 3292 if (vha->vp_idx && vha->qpair) {
3293 /* NPIV port */
3294 qpair = vha->qpair;
d7459527 3295 req = qpair->req;
d7459527
MH		 3296 }
3297
08eb7f45 3298 tsk = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &tsk_dma);
1c7c6357 3299 if (tsk == NULL) {
7c3df132
SK		 3300 ql_log(ql_log_warn, vha, 0x1093,
3301 "Failed to allocate task management IOCB.\n");
1c7c6357
AV		 3302 return QLA_MEMORY_ALLOC_FAILED;
3303 }
1c7c6357
AV		 3304
3305 tsk->p.tsk.entry_type = TSK_MGMT_IOCB_TYPE;
3306 tsk->p.tsk.entry_count = 1;
c25eb70a 3307 tsk->p.tsk.handle = make_handle(req->id, tsk->p.tsk.handle);
1c7c6357 3308 tsk->p.tsk.nport_handle = cpu_to_le16(fcport->loop_id);
00a537b8 3309 tsk->p.tsk.timeout = cpu_to_le16(ha->r_a_tov / 10 * 2);
523ec773 3310 tsk->p.tsk.control_flags = cpu_to_le32(type);
1c7c6357
AV		 3311 tsk->p.tsk.port_id[0] = fcport->d_id.b.al_pa;
3312 tsk->p.tsk.port_id[1] = fcport->d_id.b.area;
3313 tsk->p.tsk.port_id[2] = fcport->d_id.b.domain;
c6d39e23 3314 tsk->p.tsk.vp_index = fcport->vha->vp_idx;
523ec773
AV		 3315 if (type == TCF_LUN_RESET) {
3316 int_to_scsilun(l, &tsk->p.tsk.lun);
3317 host_to_fcp_swap((uint8_t *)&tsk->p.tsk.lun,
3318 sizeof(tsk->p.tsk.lun));
3319 }
2c3dfe3f 3320
9ca1d01f 3321 sts = &tsk->p.sts;
7b867cf7 3322 rval = qla2x00_issue_iocb(vha, tsk, tsk_dma, 0);
1c7c6357 3323 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3324 ql_dbg(ql_dbg_mbx, vha, 0x1094,
3325 "Failed to issue %s reset IOCB (%x).\n", name, rval);
9ca1d01f 3326 } else if (sts->entry_status != 0) {
7c3df132
SK		 3327 ql_dbg(ql_dbg_mbx, vha, 0x1095,
3328 "Failed to complete IOCB -- error status (%x).\n",
3329 sts->entry_status);
1c7c6357 3330 rval = QLA_FUNCTION_FAILED;
ad950360 3331 } else if (sts->comp_status != cpu_to_le16(CS_COMPLETE)) {
7c3df132
SK		 3332 ql_dbg(ql_dbg_mbx, vha, 0x1096,
3333 "Failed to complete IOCB -- completion status (%x).\n",
3334 le16_to_cpu(sts->comp_status));
9ca1d01f 3335 rval = QLA_FUNCTION_FAILED;
97dec564
AV		 3336 } else if (le16_to_cpu(sts->scsi_status) &
3337 SS_RESPONSE_INFO_LEN_VALID) {
3338 if (le32_to_cpu(sts->rsp_data_len) < 4) {
5f28d2d7 3339 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1097,
7c3df132
SK		 3340 "Ignoring inconsistent data length -- not enough "
3341 "response info (%d).\n",
3342 le32_to_cpu(sts->rsp_data_len));
97dec564 3343 } else if (sts->data[3]) {
7c3df132
SK		 3344 ql_dbg(ql_dbg_mbx, vha, 0x1098,
3345 "Failed to complete IOCB -- response (%x).\n",
3346 sts->data[3]);
97dec564
AV		 3347 rval = QLA_FUNCTION_FAILED;
3348 }
1c7c6357
AV		 3349 }
3350
3351 /* Issue marker IOCB. */
9eb9c6dc 3352 rval2 = qla2x00_marker(vha, ha->base_qpair, fcport->loop_id, l,
58e2753c 3353 type == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
523ec773 3354 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 3355 ql_dbg(ql_dbg_mbx, vha, 0x1099,
3356 "Failed to issue marker IOCB (%x).\n", rval2);
1c7c6357 3357 } else {
5f28d2d7
SK		 3358 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109a,
3359 "Done %s.\n", __func__);
1c7c6357
AV		 3360 }
3361
7b867cf7 3362 dma_pool_free(ha->s_dma_pool, tsk, tsk_dma);
1c7c6357
AV		 3363
3364 return rval;
3365}
3366
523ec773 3367int
9cb78c16 3368qla24xx_abort_target(struct fc_port *fcport, uint64_t l, int tag)
523ec773 3369{
3822263e
MI		 3370 struct qla_hw_data *ha = fcport->vha->hw;
3371
3372 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
3373 return qla2x00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag);
3374
2afa19a9 3375 return __qla24xx_issue_tmf("Target", TCF_TARGET_RESET, fcport, l, tag);
523ec773
AV		 3376}
3377
3378int
9cb78c16 3379qla24xx_lun_reset(struct fc_port *fcport, uint64_t l, int tag)
523ec773 3380{
3822263e
MI		 3381 struct qla_hw_data *ha = fcport->vha->hw;
3382
3383 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
3384 return qla2x00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag);
3385
2afa19a9 3386 return __qla24xx_issue_tmf("Lun", TCF_LUN_RESET, fcport, l, tag);
523ec773
AV		 3387}
3388
1c7c6357 3389int
7b867cf7 3390qla2x00_system_error(scsi_qla_host_t *vha)
1c7c6357
AV		 3391{
3392 int rval;
3393 mbx_cmd_t mc;
3394 mbx_cmd_t *mcp = &mc;
7b867cf7 3395 struct qla_hw_data *ha = vha->hw;
1c7c6357 3396
68af0811 3397 if (!IS_QLA23XX(ha) && !IS_FWI2_CAPABLE(ha))
1c7c6357
AV		 3398 return QLA_FUNCTION_FAILED;
3399
5f28d2d7
SK		 3400 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109b,
3401 "Entered %s.\n", __func__);
1c7c6357
AV		 3402
3403 mcp->mb[0] = MBC_GEN_SYSTEM_ERROR;
3404 mcp->out_mb = MBX_0;
3405 mcp->in_mb = MBX_0;
3406 mcp->tov = 5;
3407 mcp->flags = 0;
7b867cf7 3408 rval = qla2x00_mailbox_command(vha, mcp);
1c7c6357
AV		 3409
3410 if (rval != QLA_SUCCESS) {
7c3df132 3411 ql_dbg(ql_dbg_mbx, vha, 0x109c, "Failed=%x.\n", rval);
1c7c6357 3412 } else {
5f28d2d7
SK		 3413 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109d,
3414 "Done %s.\n", __func__);
1c7c6357
AV		 3415 }
3416
3417 return rval;
3418}
3419
db64e930
JC		 3420int
3421qla2x00_write_serdes_word(scsi_qla_host_t *vha, uint16_t addr, uint16_t data)
3422{
3423 int rval;
3424 mbx_cmd_t mc;
3425 mbx_cmd_t *mcp = &mc;
3426
f299c7c2 3427 if (!IS_QLA25XX(vha->hw) && !IS_QLA2031(vha->hw) &&
ecc89f25 3428 !IS_QLA27XX(vha->hw) && !IS_QLA28XX(vha->hw))
db64e930
JC		 3429 return QLA_FUNCTION_FAILED;
3430
3431 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1182,
3432 "Entered %s.\n", __func__);
3433
3434 mcp->mb[0] = MBC_WRITE_SERDES;
3435 mcp->mb[1] = addr;
064135e0
AV		 3436 if (IS_QLA2031(vha->hw))
3437 mcp->mb[2] = data & 0xff;
3438 else
3439 mcp->mb[2] = data;
3440
db64e930
JC		 3441 mcp->mb[3] = 0;
3442 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
3443 mcp->in_mb = MBX_0;
3444 mcp->tov = MBX_TOV_SECONDS;
3445 mcp->flags = 0;
3446 rval = qla2x00_mailbox_command(vha, mcp);
3447
3448 if (rval != QLA_SUCCESS) {
3449 ql_dbg(ql_dbg_mbx, vha, 0x1183,
3450 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3451 } else {
3452 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1184,
3453 "Done %s.\n", __func__);
3454 }
3455
3456 return rval;
3457}
3458
3459int
3460qla2x00_read_serdes_word(scsi_qla_host_t *vha, uint16_t addr, uint16_t *data)
3461{
3462 int rval;
3463 mbx_cmd_t mc;
3464 mbx_cmd_t *mcp = &mc;
3465
f299c7c2 3466 if (!IS_QLA25XX(vha->hw) && !IS_QLA2031(vha->hw) &&
ecc89f25 3467 !IS_QLA27XX(vha->hw) && !IS_QLA28XX(vha->hw))
db64e930
JC		 3468 return QLA_FUNCTION_FAILED;
3469
3470 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1185,
3471 "Entered %s.\n", __func__);
3472
3473 mcp->mb[0] = MBC_READ_SERDES;
3474 mcp->mb[1] = addr;
3475 mcp->mb[3] = 0;
3476 mcp->out_mb = MBX_3|MBX_1|MBX_0;
3477 mcp->in_mb = MBX_1|MBX_0;
3478 mcp->tov = MBX_TOV_SECONDS;
3479 mcp->flags = 0;
3480 rval = qla2x00_mailbox_command(vha, mcp);
3481
064135e0
AV		 3482 if (IS_QLA2031(vha->hw))
3483 *data = mcp->mb[1] & 0xff;
3484 else
3485 *data = mcp->mb[1];
db64e930
JC		 3486
3487 if (rval != QLA_SUCCESS) {
3488 ql_dbg(ql_dbg_mbx, vha, 0x1186,
3489 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3490 } else {
3491 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1187,
3492 "Done %s.\n", __func__);
3493 }
3494
3495 return rval;
3496}
3497
e8887c51
JC		 3498int
3499qla8044_write_serdes_word(scsi_qla_host_t *vha, uint32_t addr, uint32_t data)
3500{
3501 int rval;
3502 mbx_cmd_t mc;
3503 mbx_cmd_t *mcp = &mc;
3504
3505 if (!IS_QLA8044(vha->hw))
3506 return QLA_FUNCTION_FAILED;
3507
83548fe2 3508 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x11a0,
e8887c51
JC		 3509 "Entered %s.\n", __func__);
3510
3511 mcp->mb[0] = MBC_SET_GET_ETH_SERDES_REG;
3512 mcp->mb[1] = HCS_WRITE_SERDES;
3513 mcp->mb[3] = LSW(addr);
3514 mcp->mb[4] = MSW(addr);
3515 mcp->mb[5] = LSW(data);
3516 mcp->mb[6] = MSW(data);
3517 mcp->out_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_1|MBX_0;
3518 mcp->in_mb = MBX_0;
3519 mcp->tov = MBX_TOV_SECONDS;
3520 mcp->flags = 0;
3521 rval = qla2x00_mailbox_command(vha, mcp);
3522
3523 if (rval != QLA_SUCCESS) {
83548fe2 3524 ql_dbg(ql_dbg_mbx, vha, 0x11a1,
e8887c51
JC		 3525 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3526 } else {
3527 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1188,
3528 "Done %s.\n", __func__);
3529 }
3530
3531 return rval;
3532}
3533
3534int
3535qla8044_read_serdes_word(scsi_qla_host_t *vha, uint32_t addr, uint32_t *data)
3536{
3537 int rval;
3538 mbx_cmd_t mc;
3539 mbx_cmd_t *mcp = &mc;
3540
3541 if (!IS_QLA8044(vha->hw))
3542 return QLA_FUNCTION_FAILED;
3543
3544 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1189,
3545 "Entered %s.\n", __func__);
3546
3547 mcp->mb[0] = MBC_SET_GET_ETH_SERDES_REG;
3548 mcp->mb[1] = HCS_READ_SERDES;
3549 mcp->mb[3] = LSW(addr);
3550 mcp->mb[4] = MSW(addr);
3551 mcp->out_mb = MBX_4|MBX_3|MBX_1|MBX_0;
3552 mcp->in_mb = MBX_2|MBX_1|MBX_0;
3553 mcp->tov = MBX_TOV_SECONDS;
3554 mcp->flags = 0;
3555 rval = qla2x00_mailbox_command(vha, mcp);
3556
3557 *data = mcp->mb[2] << 16 | mcp->mb[1];
3558
3559 if (rval != QLA_SUCCESS) {
3560 ql_dbg(ql_dbg_mbx, vha, 0x118a,
3561 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3562 } else {
3563 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118b,
3564 "Done %s.\n", __func__);
3565 }
3566
3567 return rval;
3568}
3569
1c7c6357
AV		 3570/**
3571 * qla2x00_set_serdes_params() -
2db6228d 3572 * @vha: HA context
807eb907
BVA		 3573 * @sw_em_1g: serial link options
3574 * @sw_em_2g: serial link options
3575 * @sw_em_4g: serial link options
1c7c6357
AV		 3576 *
3577 * Returns
3578 */
3579int
7b867cf7 3580qla2x00_set_serdes_params(scsi_qla_host_t *vha, uint16_t sw_em_1g,
1c7c6357
AV		 3581 uint16_t sw_em_2g, uint16_t sw_em_4g)
3582{
3583 int rval;
3584 mbx_cmd_t mc;
3585 mbx_cmd_t *mcp = &mc;
3586
5f28d2d7
SK		 3587 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109e,
3588 "Entered %s.\n", __func__);
1c7c6357
AV		 3589
3590 mcp->mb[0] = MBC_SERDES_PARAMS;
3591 mcp->mb[1] = BIT_0;
fdbc6833
AV		 3592 mcp->mb[2] = sw_em_1g | BIT_15;
3593 mcp->mb[3] = sw_em_2g | BIT_15;
3594 mcp->mb[4] = sw_em_4g | BIT_15;
1c7c6357
AV		 3595 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
3596 mcp->in_mb = MBX_0;
b93480e3 3597 mcp->tov = MBX_TOV_SECONDS;
1c7c6357 3598 mcp->flags = 0;
7b867cf7 3599 rval = qla2x00_mailbox_command(vha, mcp);
1c7c6357
AV		 3600
3601 if (rval != QLA_SUCCESS) {
3602 /*EMPTY*/
7c3df132
SK		 3603 ql_dbg(ql_dbg_mbx, vha, 0x109f,
3604 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
1c7c6357
AV		 3605 } else {
3606 /*EMPTY*/
5f28d2d7
SK		 3607 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a0,
3608 "Done %s.\n", __func__);
1c7c6357
AV		 3609 }
3610
3611 return rval;
3612}
f6ef3b18
AV		 3613
3614int
7b867cf7 3615qla2x00_stop_firmware(scsi_qla_host_t *vha)
f6ef3b18
AV		 3616{
3617 int rval;
3618 mbx_cmd_t mc;
3619 mbx_cmd_t *mcp = &mc;
3620
7b867cf7 3621 if (!IS_FWI2_CAPABLE(vha->hw))
f6ef3b18
AV		 3622 return QLA_FUNCTION_FAILED;
3623
5f28d2d7
SK		 3624 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a1,
3625 "Entered %s.\n", __func__);
f6ef3b18
AV		 3626
3627 mcp->mb[0] = MBC_STOP_FIRMWARE;
4ba988db
AV		 3628 mcp->mb[1] = 0;
3629 mcp->out_mb = MBX_1|MBX_0;
f6ef3b18
AV		 3630 mcp->in_mb = MBX_0;
3631 mcp->tov = 5;
3632 mcp->flags = 0;
7b867cf7 3633 rval = qla2x00_mailbox_command(vha, mcp);
f6ef3b18
AV		 3634
3635 if (rval != QLA_SUCCESS) {
7c3df132 3636 ql_dbg(ql_dbg_mbx, vha, 0x10a2, "Failed=%x.\n", rval);
b469a7cb
AV		 3637 if (mcp->mb[0] == MBS_INVALID_COMMAND)
3638 rval = QLA_INVALID_COMMAND;
f6ef3b18 3639 } else {
5f28d2d7
SK		 3640 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a3,
3641 "Done %s.\n", __func__);
f6ef3b18
AV		 3642 }
3643
3644 return rval;
3645}
a7a167bf
AV		 3646
3647int
7b867cf7 3648qla2x00_enable_eft_trace(scsi_qla_host_t *vha, dma_addr_t eft_dma,
a7a167bf
AV		 3649 uint16_t buffers)
3650{
3651 int rval;
3652 mbx_cmd_t mc;
3653 mbx_cmd_t *mcp = &mc;
3654
5f28d2d7
SK		 3655 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a4,
3656 "Entered %s.\n", __func__);
7c3df132 3657
7b867cf7 3658 if (!IS_FWI2_CAPABLE(vha->hw))
a7a167bf
AV		 3659 return QLA_FUNCTION_FAILED;
3660
85880801
AV		 3661 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3662 return QLA_FUNCTION_FAILED;
3663
a7a167bf 3664 mcp->mb[0] = MBC_TRACE_CONTROL;
00b6bd25
AV		 3665 mcp->mb[1] = TC_EFT_ENABLE;
3666 mcp->mb[2] = LSW(eft_dma);
3667 mcp->mb[3] = MSW(eft_dma);
3668 mcp->mb[4] = LSW(MSD(eft_dma));
3669 mcp->mb[5] = MSW(MSD(eft_dma));
3670 mcp->mb[6] = buffers;
3671 mcp->mb[7] = TC_AEN_DISABLE;
3672 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
a7a167bf 3673 mcp->in_mb = MBX_1|MBX_0;
b93480e3 3674 mcp->tov = MBX_TOV_SECONDS;
a7a167bf 3675 mcp->flags = 0;
7b867cf7 3676 rval = qla2x00_mailbox_command(vha, mcp);
00b6bd25 3677 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3678 ql_dbg(ql_dbg_mbx, vha, 0x10a5,
3679 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3680 rval, mcp->mb[0], mcp->mb[1]);
00b6bd25 3681 } else {
5f28d2d7
SK		 3682 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a6,
3683 "Done %s.\n", __func__);
00b6bd25
AV		 3684 }
3685
3686 return rval;
3687}
a7a167bf 3688
00b6bd25 3689int
7b867cf7 3690qla2x00_disable_eft_trace(scsi_qla_host_t *vha)
00b6bd25
AV		 3691{
3692 int rval;
3693 mbx_cmd_t mc;
3694 mbx_cmd_t *mcp = &mc;
3695
5f28d2d7
SK		 3696 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a7,
3697 "Entered %s.\n", __func__);
7c3df132 3698
7b867cf7 3699 if (!IS_FWI2_CAPABLE(vha->hw))
00b6bd25
AV		 3700 return QLA_FUNCTION_FAILED;
3701
85880801
AV		 3702 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3703 return QLA_FUNCTION_FAILED;
3704
00b6bd25
AV		 3705 mcp->mb[0] = MBC_TRACE_CONTROL;
3706 mcp->mb[1] = TC_EFT_DISABLE;
3707 mcp->out_mb = MBX_1|MBX_0;
3708 mcp->in_mb = MBX_1|MBX_0;
b93480e3 3709 mcp->tov = MBX_TOV_SECONDS;
00b6bd25 3710 mcp->flags = 0;
7b867cf7 3711 rval = qla2x00_mailbox_command(vha, mcp);
a7a167bf 3712 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3713 ql_dbg(ql_dbg_mbx, vha, 0x10a8,
3714 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3715 rval, mcp->mb[0], mcp->mb[1]);
a7a167bf 3716 } else {
5f28d2d7
SK		 3717 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a9,
3718 "Done %s.\n", __func__);
a7a167bf
AV		 3719 }
3720
3721 return rval;
3722}
3723
df613b96 3724int
7b867cf7 3725qla2x00_enable_fce_trace(scsi_qla_host_t *vha, dma_addr_t fce_dma,
df613b96
AV		 3726 uint16_t buffers, uint16_t *mb, uint32_t *dwords)
3727{
3728 int rval;
3729 mbx_cmd_t mc;
3730 mbx_cmd_t *mcp = &mc;
3731
5f28d2d7
SK		 3732 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10aa,
3733 "Entered %s.\n", __func__);
7c3df132 3734
6246b8a1 3735 if (!IS_QLA25XX(vha->hw) && !IS_QLA81XX(vha->hw) &&
ecc89f25
JC		 3736 !IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw) &&
3737 !IS_QLA28XX(vha->hw))
df613b96
AV		 3738 return QLA_FUNCTION_FAILED;
3739
85880801
AV		 3740 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3741 return QLA_FUNCTION_FAILED;
3742
df613b96
AV		 3743 mcp->mb[0] = MBC_TRACE_CONTROL;
3744 mcp->mb[1] = TC_FCE_ENABLE;
3745 mcp->mb[2] = LSW(fce_dma);
3746 mcp->mb[3] = MSW(fce_dma);
3747 mcp->mb[4] = LSW(MSD(fce_dma));
3748 mcp->mb[5] = MSW(MSD(fce_dma));
3749 mcp->mb[6] = buffers;
3750 mcp->mb[7] = TC_AEN_DISABLE;
3751 mcp->mb[8] = 0;
3752 mcp->mb[9] = TC_FCE_DEFAULT_RX_SIZE;
3753 mcp->mb[10] = TC_FCE_DEFAULT_TX_SIZE;
3754 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
3755 MBX_1|MBX_0;
3756 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
b93480e3 3757 mcp->tov = MBX_TOV_SECONDS;
df613b96 3758 mcp->flags = 0;
7b867cf7 3759 rval = qla2x00_mailbox_command(vha, mcp);
df613b96 3760 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3761 ql_dbg(ql_dbg_mbx, vha, 0x10ab,
3762 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3763 rval, mcp->mb[0], mcp->mb[1]);
df613b96 3764 } else {
5f28d2d7
SK		 3765 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ac,
3766 "Done %s.\n", __func__);
df613b96
AV		 3767
3768 if (mb)
3769 memcpy(mb, mcp->mb, 8 * sizeof(*mb));
3770 if (dwords)
fa0926df 3771 *dwords = buffers;
df613b96
AV		 3772 }
3773
3774 return rval;
3775}
3776
3777int
7b867cf7 3778qla2x00_disable_fce_trace(scsi_qla_host_t *vha, uint64_t *wr, uint64_t *rd)
df613b96
AV		 3779{
3780 int rval;
3781 mbx_cmd_t mc;
3782 mbx_cmd_t *mcp = &mc;
3783
5f28d2d7
SK		 3784 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ad,
3785 "Entered %s.\n", __func__);
7c3df132 3786
7b867cf7 3787 if (!IS_FWI2_CAPABLE(vha->hw))
df613b96
AV		 3788 return QLA_FUNCTION_FAILED;
3789
85880801
AV		 3790 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3791 return QLA_FUNCTION_FAILED;
3792
df613b96
AV		 3793 mcp->mb[0] = MBC_TRACE_CONTROL;
3794 mcp->mb[1] = TC_FCE_DISABLE;
3795 mcp->mb[2] = TC_FCE_DISABLE_TRACE;
3796 mcp->out_mb = MBX_2|MBX_1|MBX_0;
3797 mcp->in_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
3798 MBX_1|MBX_0;
b93480e3 3799 mcp->tov = MBX_TOV_SECONDS;
df613b96 3800 mcp->flags = 0;
7b867cf7 3801 rval = qla2x00_mailbox_command(vha, mcp);
df613b96 3802 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3803 ql_dbg(ql_dbg_mbx, vha, 0x10ae,
3804 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3805 rval, mcp->mb[0], mcp->mb[1]);
df613b96 3806 } else {
5f28d2d7
SK		 3807 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10af,
3808 "Done %s.\n", __func__);
df613b96
AV		 3809
3810 if (wr)
3811 *wr = (uint64_t) mcp->mb[5] << 48 |
3812 (uint64_t) mcp->mb[4] << 32 |
3813 (uint64_t) mcp->mb[3] << 16 |
3814 (uint64_t) mcp->mb[2];
3815 if (rd)
3816 *rd = (uint64_t) mcp->mb[9] << 48 |
3817 (uint64_t) mcp->mb[8] << 32 |
3818 (uint64_t) mcp->mb[7] << 16 |
3819 (uint64_t) mcp->mb[6];
3820 }
3821
3822 return rval;
3823}
3824
6e98016c
GM		 3825int
3826qla2x00_get_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
3827 uint16_t *port_speed, uint16_t *mb)
3828{
3829 int rval;
3830 mbx_cmd_t mc;
3831 mbx_cmd_t *mcp = &mc;
3832
5f28d2d7
SK		 3833 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b0,
3834 "Entered %s.\n", __func__);
7c3df132 3835
6e98016c
GM		 3836 if (!IS_IIDMA_CAPABLE(vha->hw))
3837 return QLA_FUNCTION_FAILED;
3838
6e98016c
GM		 3839 mcp->mb[0] = MBC_PORT_PARAMS;
3840 mcp->mb[1] = loop_id;
3841 mcp->mb[2] = mcp->mb[3] = 0;
3842 mcp->mb[9] = vha->vp_idx;
3843 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
3844 mcp->in_mb = MBX_3|MBX_1|MBX_0;
3845 mcp->tov = MBX_TOV_SECONDS;
3846 mcp->flags = 0;
3847 rval = qla2x00_mailbox_command(vha, mcp);
3848
3849 /* Return mailbox statuses. */
2a3192a3 3850 if (mb) {
6e98016c
GM		 3851 mb[0] = mcp->mb[0];
3852 mb[1] = mcp->mb[1];
3853 mb[3] = mcp->mb[3];
3854 }
3855
3856 if (rval != QLA_SUCCESS) {
7c3df132 3857 ql_dbg(ql_dbg_mbx, vha, 0x10b1, "Failed=%x.\n", rval);
6e98016c 3858 } else {
5f28d2d7
SK		 3859 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b2,
3860 "Done %s.\n", __func__);
6e98016c
GM		 3861 if (port_speed)
3862 *port_speed = mcp->mb[3];
3863 }
3864
3865 return rval;
3866}
3867
d8b45213 3868int
7b867cf7 3869qla2x00_set_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
d8b45213
AV		 3870 uint16_t port_speed, uint16_t *mb)
3871{
3872 int rval;
3873 mbx_cmd_t mc;
3874 mbx_cmd_t *mcp = &mc;
3875
5f28d2d7
SK		 3876 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b3,
3877 "Entered %s.\n", __func__);
7c3df132 3878
7b867cf7 3879 if (!IS_IIDMA_CAPABLE(vha->hw))
d8b45213
AV		 3880 return QLA_FUNCTION_FAILED;
3881
d8b45213
AV		 3882 mcp->mb[0] = MBC_PORT_PARAMS;
3883 mcp->mb[1] = loop_id;
3884 mcp->mb[2] = BIT_0;
2a3192a3 3885 mcp->mb[3] = port_speed & 0x3F;
1bb39548
HZ		 3886 mcp->mb[9] = vha->vp_idx;
3887 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
3888 mcp->in_mb = MBX_3|MBX_1|MBX_0;
b93480e3 3889 mcp->tov = MBX_TOV_SECONDS;
d8b45213 3890 mcp->flags = 0;
7b867cf7 3891 rval = qla2x00_mailbox_command(vha, mcp);
d8b45213
AV		 3892
3893 /* Return mailbox statuses. */
2a3192a3 3894 if (mb) {
d8b45213
AV		 3895 mb[0] = mcp->mb[0];
3896 mb[1] = mcp->mb[1];
3897 mb[3] = mcp->mb[3];
d8b45213
AV		 3898 }
3899
3900 if (rval != QLA_SUCCESS) {
5f28d2d7
SK		 3901 ql_dbg(ql_dbg_mbx, vha, 0x10b4,
3902 "Failed=%x.\n", rval);
d8b45213 3903 } else {
5f28d2d7
SK		 3904 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b5,
3905 "Done %s.\n", __func__);
d8b45213
AV		 3906 }
3907
3908 return rval;
3909}
2c3dfe3f 3910
2c3dfe3f 3911void
7b867cf7 3912qla24xx_report_id_acquisition(scsi_qla_host_t *vha,
2c3dfe3f
SJ		 3913 struct vp_rpt_id_entry_24xx *rptid_entry)
3914{
7b867cf7 3915 struct qla_hw_data *ha = vha->hw;
41dc529a 3916 scsi_qla_host_t *vp = NULL;
feafb7b1 3917 unsigned long flags;
4ac8d4ca 3918 int found;
482c9dc7 3919 port_id_t id;
9cd883f0 3920 struct fc_port *fcport;
2c3dfe3f 3921
5f28d2d7
SK		 3922 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b6,
3923 "Entered %s.\n", __func__);
7c3df132 3924
2c3dfe3f
SJ		 3925 if (rptid_entry->entry_status != 0)
3926 return;
2c3dfe3f 3927
482c9dc7
QT		 3928 id.b.domain = rptid_entry->port_id[2];
3929 id.b.area = rptid_entry->port_id[1];
3930 id.b.al_pa = rptid_entry->port_id[0];
3931 id.b.rsvd_1 = 0;
1763c1fd 3932 ha->flags.n2n_ae = 0;
482c9dc7 3933
2c3dfe3f 3934 if (rptid_entry->format == 0) {
41dc529a 3935 /* loop */
ec7193e2 3936 ql_dbg(ql_dbg_async, vha, 0x10b7,
7c3df132 3937 "Format 0 : Number of VPs setup %d, number of "
41dc529a
QT		 3938 "VPs acquired %d.\n", rptid_entry->vp_setup,
3939 rptid_entry->vp_acquired);
ec7193e2 3940 ql_dbg(ql_dbg_async, vha, 0x10b8,
7c3df132
SK		 3941 "Primary port id %02x%02x%02x.\n",
3942 rptid_entry->port_id[2], rptid_entry->port_id[1],
3943 rptid_entry->port_id[0]);
9cd883f0 3944 ha->current_topology = ISP_CFG_NL;
482c9dc7 3945 qlt_update_host_map(vha, id);
41dc529a 3946
2c3dfe3f 3947 } else if (rptid_entry->format == 1) {
41dc529a 3948 /* fabric */
ec7193e2 3949 ql_dbg(ql_dbg_async, vha, 0x10b9,
7c3df132 3950 "Format 1: VP[%d] enabled - status %d - with "
41dc529a
QT		 3951 "port id %02x%02x%02x.\n", rptid_entry->vp_idx,
3952 rptid_entry->vp_status,
2c3dfe3f 3953 rptid_entry->port_id[2], rptid_entry->port_id[1],
7c3df132 3954 rptid_entry->port_id[0]);
edd05de1
DG		 3955 ql_dbg(ql_dbg_async, vha, 0x5075,
3956 "Format 1: Remote WWPN %8phC.\n",
3957 rptid_entry->u.f1.port_name);
3958
3959 ql_dbg(ql_dbg_async, vha, 0x5075,
3960 "Format 1: WWPN %8phC.\n",
3961 vha->port_name);
3962
8777e431
QT		 3963 switch (rptid_entry->u.f1.flags & TOPO_MASK) {
3964 case TOPO_N2N:
3965 ha->current_topology = ISP_CFG_N;
3966 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
7f2a398d
QT		 3967 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3968 fcport->scan_state = QLA_FCPORT_SCAN;
3969 fcport->n2n_flag = 0;
3970 }
ad8a260a
QT		 3971 id.b24 = 0;
3972 if (wwn_to_u64(vha->port_name) >
3973 wwn_to_u64(rptid_entry->u.f1.port_name)) {
3974 vha->d_id.b24 = 0;
3975 vha->d_id.b.al_pa = 1;
3976 ha->flags.n2n_bigger = 1;
3977
3978 id.b.al_pa = 2;
3979 ql_dbg(ql_dbg_async, vha, 0x5075,
3980 "Format 1: assign local id %x remote id %x\n",
3981 vha->d_id.b24, id.b24);
3982 } else {
3983 ql_dbg(ql_dbg_async, vha, 0x5075,
3984 "Format 1: Remote login - Waiting for WWPN %8phC.\n",
3985 rptid_entry->u.f1.port_name);
3986 ha->flags.n2n_bigger = 0;
3987 }
7f2a398d 3988
8777e431
QT		 3989 fcport = qla2x00_find_fcport_by_wwpn(vha,
3990 rptid_entry->u.f1.port_name, 1);
3991 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
3992
ad8a260a 3993
8777e431
QT		 3994 if (fcport) {
3995 fcport->plogi_nack_done_deadline = jiffies + HZ;
94eda271
AE		 3996 fcport->dm_login_expire = jiffies +
3997 QLA_N2N_WAIT_TIME * HZ;
8777e431 3998 fcport->scan_state = QLA_FCPORT_FOUND;
7f2a398d 3999 fcport->n2n_flag = 1;
f3f1938b 4000 fcport->keep_nport_handle = 1;
7f2a398d 4001
ad8a260a
QT		 4002 if (wwn_to_u64(vha->port_name) >
4003 wwn_to_u64(fcport->port_name)) {
4004 fcport->d_id = id;
4005 }
4006
8777e431
QT		 4007 switch (fcport->disc_state) {
4008 case DSC_DELETED:
4009 set_bit(RELOGIN_NEEDED,
4010 &vha->dpc_flags);
4011 break;
4012 case DSC_DELETE_PEND:
4013 break;
4014 default:
4015 qlt_schedule_sess_for_deletion(fcport);
4016 break;
4017 }
edd05de1 4018 } else {
8777e431
QT		 4019 qla24xx_post_newsess_work(vha, &id,
4020 rptid_entry->u.f1.port_name,
4021 rptid_entry->u.f1.node_name,
4022 NULL,
7f2a398d 4023 FS_FCP_IS_N2N);
edd05de1
DG		 4024 }
4025
8777e431
QT		 4026 /* if our portname is higher then initiate N2N login */
4027
edd05de1 4028 set_bit(N2N_LOGIN_NEEDED, &vha->dpc_flags);
edd05de1 4029 return;
8777e431
QT		 4030 case TOPO_FL:
4031 ha->current_topology = ISP_CFG_FL;
4032 break;
4033 case TOPO_F:
4034 ha->current_topology = ISP_CFG_F;
4035 break;
4036 default:
4037 break;
edd05de1 4038 }
531a82d1 4039
9cd883f0
QT		 4040 ha->flags.gpsc_supported = 1;
4041 ha->current_topology = ISP_CFG_F;
969a6199 4042 /* buffer to buffer credit flag */
41dc529a
QT		 4043 vha->flags.bbcr_enable = (rptid_entry->u.f1.bbcr & 0xf) != 0;
4044
4045 if (rptid_entry->vp_idx == 0) {
4046 if (rptid_entry->vp_status == VP_STAT_COMPL) {
4047 /* FA-WWN is only for physical port */
4048 if (qla_ini_mode_enabled(vha) &&
4049 ha->flags.fawwpn_enabled &&
4050 (rptid_entry->u.f1.flags &
fcc5b5cd 4051 BIT_6)) {
41dc529a
QT		 4052 memcpy(vha->port_name,
4053 rptid_entry->u.f1.port_name,
4054 WWN_SIZE);
4055 }
7c9c4766 4056
482c9dc7 4057 qlt_update_host_map(vha, id);
7c9c4766 4058 }
41dc529a 4059
41dc529a
QT		 4060 set_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags);
4061 set_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags);
4062 } else {
4063 if (rptid_entry->vp_status != VP_STAT_COMPL &&
4064 rptid_entry->vp_status != VP_STAT_ID_CHG) {
4065 ql_dbg(ql_dbg_mbx, vha, 0x10ba,
4066 "Could not acquire ID for VP[%d].\n",
4067 rptid_entry->vp_idx);
4068 return;
4ac8d4ca 4069 }
feafb7b1 4070
41dc529a
QT		 4071 found = 0;
4072 spin_lock_irqsave(&ha->vport_slock, flags);
4073 list_for_each_entry(vp, &ha->vp_list, list) {
4074 if (rptid_entry->vp_idx == vp->vp_idx) {
4075 found = 1;
4076 break;
4077 }
4078 }
4079 spin_unlock_irqrestore(&ha->vport_slock, flags);
2c3dfe3f 4080
41dc529a
QT		 4081 if (!found)
4082 return;
2c3dfe3f 4083
482c9dc7 4084 qlt_update_host_map(vp, id);
2c3dfe3f 4085
41dc529a
QT		 4086 /*
4087 * Cannot configure here as we are still sitting on the
4088 * response queue. Handle it in dpc context.
4089 */
4090 set_bit(VP_IDX_ACQUIRED, &vp->vp_flags);
4091 set_bit(REGISTER_FC4_NEEDED, &vp->dpc_flags);
4092 set_bit(REGISTER_FDMI_NEEDED, &vp->dpc_flags);
4093 }
531a82d1 4094 set_bit(VP_DPC_NEEDED, &vha->dpc_flags);
7b867cf7 4095 qla2xxx_wake_dpc(vha);
41dc529a 4096 } else if (rptid_entry->format == 2) {
83548fe2 4097 ql_dbg(ql_dbg_async, vha, 0x505f,
41dc529a
QT		 4098 "RIDA: format 2/N2N Primary port id %02x%02x%02x.\n",
4099 rptid_entry->port_id[2], rptid_entry->port_id[1],
4100 rptid_entry->port_id[0]);
4101
83548fe2 4102 ql_dbg(ql_dbg_async, vha, 0x5075,
41dc529a
QT		 4103 "N2N: Remote WWPN %8phC.\n",
4104 rptid_entry->u.f2.port_name);
4105
4106 /* N2N. direct connect */
9cd883f0
QT		 4107 ha->current_topology = ISP_CFG_N;
4108 ha->flags.rida_fmt2 = 1;
41dc529a
QT		 4109 vha->d_id.b.domain = rptid_entry->port_id[2];
4110 vha->d_id.b.area = rptid_entry->port_id[1];
4111 vha->d_id.b.al_pa = rptid_entry->port_id[0];
4112
1763c1fd 4113 ha->flags.n2n_ae = 1;
41dc529a
QT		 4114 spin_lock_irqsave(&ha->vport_slock, flags);
4115 qlt_update_vp_map(vha, SET_AL_PA);
4116 spin_unlock_irqrestore(&ha->vport_slock, flags);
9cd883f0
QT		 4117
4118 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4119 fcport->scan_state = QLA_FCPORT_SCAN;
7f2a398d 4120 fcport->n2n_flag = 0;
9cd883f0
QT		 4121 }
4122
4123 fcport = qla2x00_find_fcport_by_wwpn(vha,
4124 rptid_entry->u.f2.port_name, 1);
4125
4126 if (fcport) {
23dd98a6 4127 fcport->login_retry = vha->hw->login_retry_count;
9cd883f0
QT		 4128 fcport->plogi_nack_done_deadline = jiffies + HZ;
4129 fcport->scan_state = QLA_FCPORT_FOUND;
f3f1938b 4130 fcport->keep_nport_handle = 1;
7f2a398d
QT		 4131 fcport->n2n_flag = 1;
4132 fcport->d_id.b.domain =
4133 rptid_entry->u.f2.remote_nport_id[2];
4134 fcport->d_id.b.area =
4135 rptid_entry->u.f2.remote_nport_id[1];
4136 fcport->d_id.b.al_pa =
4137 rptid_entry->u.f2.remote_nport_id[0];
9cd883f0 4138 }
2c3dfe3f
SJ		 4139 }
4140}
4141
4142/*
4143 * qla24xx_modify_vp_config
4144 * Change VP configuration for vha
4145 *
4146 * Input:
4147 * vha = adapter block pointer.
4148 *
4149 * Returns:
4150 * qla2xxx local function return status code.
4151 *
4152 * Context:
4153 * Kernel context.
4154 */
4155int
4156qla24xx_modify_vp_config(scsi_qla_host_t *vha)
4157{
4158 int rval;
4159 struct vp_config_entry_24xx *vpmod;
4160 dma_addr_t vpmod_dma;
7b867cf7
AC		 4161 struct qla_hw_data *ha = vha->hw;
4162 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2c3dfe3f
SJ		 4163
4164 /* This can be called by the parent */
2c3dfe3f 4165
5f28d2d7
SK		 4166 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10bb,
4167 "Entered %s.\n", __func__);
7c3df132 4168
08eb7f45 4169 vpmod = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &vpmod_dma);
2c3dfe3f 4170 if (!vpmod) {
7c3df132
SK		 4171 ql_log(ql_log_warn, vha, 0x10bc,
4172 "Failed to allocate modify VP IOCB.\n");
2c3dfe3f
SJ		 4173 return QLA_MEMORY_ALLOC_FAILED;
4174 }
4175
2c3dfe3f
SJ		 4176 vpmod->entry_type = VP_CONFIG_IOCB_TYPE;
4177 vpmod->entry_count = 1;
4178 vpmod->command = VCT_COMMAND_MOD_ENABLE_VPS;
4179 vpmod->vp_count = 1;
4180 vpmod->vp_index1 = vha->vp_idx;
4181 vpmod->options_idx1 = BIT_3|BIT_4|BIT_5;
2d70c103
NB		 4182
4183 qlt_modify_vp_config(vha, vpmod);
4184
2c3dfe3f
SJ		 4185 memcpy(vpmod->node_name_idx1, vha->node_name, WWN_SIZE);
4186 memcpy(vpmod->port_name_idx1, vha->port_name, WWN_SIZE);
4187 vpmod->entry_count = 1;
4188
7b867cf7 4189 rval = qla2x00_issue_iocb(base_vha, vpmod, vpmod_dma, 0);
2c3dfe3f 4190 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4191 ql_dbg(ql_dbg_mbx, vha, 0x10bd,
4192 "Failed to issue VP config IOCB (%x).\n", rval);
2c3dfe3f 4193 } else if (vpmod->comp_status != 0) {
7c3df132
SK		 4194 ql_dbg(ql_dbg_mbx, vha, 0x10be,
4195 "Failed to complete IOCB -- error status (%x).\n",
4196 vpmod->comp_status);
2c3dfe3f 4197 rval = QLA_FUNCTION_FAILED;
ad950360 4198 } else if (vpmod->comp_status != cpu_to_le16(CS_COMPLETE)) {
7c3df132
SK		 4199 ql_dbg(ql_dbg_mbx, vha, 0x10bf,
4200 "Failed to complete IOCB -- completion status (%x).\n",
4201 le16_to_cpu(vpmod->comp_status));
2c3dfe3f
SJ		 4202 rval = QLA_FUNCTION_FAILED;
4203 } else {
4204 /* EMPTY */
5f28d2d7
SK		 4205 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c0,
4206 "Done %s.\n", __func__);
2c3dfe3f
SJ		 4207 fc_vport_set_state(vha->fc_vport, FC_VPORT_INITIALIZING);
4208 }
7b867cf7 4209 dma_pool_free(ha->s_dma_pool, vpmod, vpmod_dma);
2c3dfe3f
SJ		 4210
4211 return rval;
4212}
4213
2c3dfe3f
SJ		 4214/*
4215 * qla2x00_send_change_request
4216 * Receive or disable RSCN request from fabric controller
4217 *
4218 * Input:
4219 * ha = adapter block pointer
4220 * format = registration format:
4221 * 0 - Reserved
4222 * 1 - Fabric detected registration
4223 * 2 - N_port detected registration
4224 * 3 - Full registration
4225 * FF - clear registration
4226 * vp_idx = Virtual port index
4227 *
4228 * Returns:
4229 * qla2x00 local function return status code.
4230 *
4231 * Context:
4232 * Kernel Context
4233 */
4234
4235int
7b867cf7 4236qla2x00_send_change_request(scsi_qla_host_t *vha, uint16_t format,
2c3dfe3f
SJ		 4237 uint16_t vp_idx)
4238{
4239 int rval;
4240 mbx_cmd_t mc;
4241 mbx_cmd_t *mcp = &mc;
4242
5f28d2d7
SK		 4243 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c7,
4244 "Entered %s.\n", __func__);
7c3df132 4245
2c3dfe3f
SJ		 4246 mcp->mb[0] = MBC_SEND_CHANGE_REQUEST;
4247 mcp->mb[1] = format;
4248 mcp->mb[9] = vp_idx;
4249 mcp->out_mb = MBX_9|MBX_1|MBX_0;
4250 mcp->in_mb = MBX_0|MBX_1;
4251 mcp->tov = MBX_TOV_SECONDS;
4252 mcp->flags = 0;
7b867cf7 4253 rval = qla2x00_mailbox_command(vha, mcp);
2c3dfe3f
SJ		 4254
4255 if (rval == QLA_SUCCESS) {
4256 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
4257 rval = BIT_1;
4258 }
4259 } else
4260 rval = BIT_1;
4261
4262 return rval;
4263}
338c9161
AV		 4264
4265int
7b867cf7 4266qla2x00_dump_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr,
338c9161
AV		 4267 uint32_t size)
4268{
4269 int rval;
4270 mbx_cmd_t mc;
4271 mbx_cmd_t *mcp = &mc;
4272
5f28d2d7
SK		 4273 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1009,
4274 "Entered %s.\n", __func__);
338c9161 4275
7b867cf7 4276 if (MSW(addr) || IS_FWI2_CAPABLE(vha->hw)) {
338c9161
AV		 4277 mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED;
4278 mcp->mb[8] = MSW(addr);
28db7c1f
QT		 4279 mcp->mb[10] = 0;
4280 mcp->out_mb = MBX_10|MBX_8|MBX_0;
338c9161
AV		 4281 } else {
4282 mcp->mb[0] = MBC_DUMP_RISC_RAM;
4283 mcp->out_mb = MBX_0;
4284 }
4285 mcp->mb[1] = LSW(addr);
4286 mcp->mb[2] = MSW(req_dma);
4287 mcp->mb[3] = LSW(req_dma);
4288 mcp->mb[6] = MSW(MSD(req_dma));
4289 mcp->mb[7] = LSW(MSD(req_dma));
4290 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
7b867cf7 4291 if (IS_FWI2_CAPABLE(vha->hw)) {
338c9161
AV		 4292 mcp->mb[4] = MSW(size);
4293 mcp->mb[5] = LSW(size);
4294 mcp->out_mb |= MBX_5|MBX_4;
4295 } else {
4296 mcp->mb[4] = LSW(size);
4297 mcp->out_mb |= MBX_4;
4298 }
4299
4300 mcp->in_mb = MBX_0;
b93480e3 4301 mcp->tov = MBX_TOV_SECONDS;
338c9161 4302 mcp->flags = 0;
7b867cf7 4303 rval = qla2x00_mailbox_command(vha, mcp);
338c9161
AV		 4304
4305 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4306 ql_dbg(ql_dbg_mbx, vha, 0x1008,
4307 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
338c9161 4308 } else {
5f28d2d7
SK		 4309 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1007,
4310 "Done %s.\n", __func__);
338c9161
AV		 4311 }
4312
4313 return rval;
4314}
4d4df193
HK		 4315/* 84XX Support **************************************************************/
4316
4317struct cs84xx_mgmt_cmd {
4318 union {
4319 struct verify_chip_entry_84xx req;
4320 struct verify_chip_rsp_84xx rsp;
4321 } p;
4322};
4323
4324int
7b867cf7 4325qla84xx_verify_chip(struct scsi_qla_host *vha, uint16_t *status)
4d4df193
HK		 4326{
4327 int rval, retry;
4328 struct cs84xx_mgmt_cmd *mn;
4329 dma_addr_t mn_dma;
4330 uint16_t options;
4331 unsigned long flags;
7b867cf7 4332 struct qla_hw_data *ha = vha->hw;
4d4df193 4333
5f28d2d7
SK		 4334 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c8,
4335 "Entered %s.\n", __func__);
4d4df193
HK		 4336
4337 mn = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &mn_dma);
4338 if (mn == NULL) {
4d4df193
HK		 4339 return QLA_MEMORY_ALLOC_FAILED;
4340 }
4341
4342 /* Force Update? */
4343 options = ha->cs84xx->fw_update ? VCO_FORCE_UPDATE : 0;
4344 /* Diagnostic firmware? */
4345 /* options |= MENLO_DIAG_FW; */
4346 /* We update the firmware with only one data sequence. */
4347 options |= VCO_END_OF_DATA;
4348
4d4df193 4349 do {
c1ec1f1b 4350 retry = 0;
4d4df193
HK		 4351 memset(mn, 0, sizeof(*mn));
4352 mn->p.req.entry_type = VERIFY_CHIP_IOCB_TYPE;
4353 mn->p.req.entry_count = 1;
4354 mn->p.req.options = cpu_to_le16(options);
4355
7c3df132
SK		 4356 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111c,
4357 "Dump of Verify Request.\n");
4358 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111e,
f8f97b0c 4359 mn, sizeof(*mn));
4d4df193 4360
7b867cf7 4361 rval = qla2x00_issue_iocb_timeout(vha, mn, mn_dma, 0, 120);
4d4df193 4362 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4363 ql_dbg(ql_dbg_mbx, vha, 0x10cb,
4364 "Failed to issue verify IOCB (%x).\n", rval);
4d4df193
HK		 4365 goto verify_done;
4366 }
4367
7c3df132
SK		 4368 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1110,
4369 "Dump of Verify Response.\n");
4370 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1118,
f8f97b0c 4371 mn, sizeof(*mn));
4d4df193
HK		 4372
4373 status[0] = le16_to_cpu(mn->p.rsp.comp_status);
4374 status[1] = status[0] == CS_VCS_CHIP_FAILURE ?
4375 le16_to_cpu(mn->p.rsp.failure_code) : 0;
5f28d2d7 4376 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ce,
7c3df132 4377 "cs=%x fc=%x.\n", status[0], status[1]);
4d4df193
HK		 4378
4379 if (status[0] != CS_COMPLETE) {
4380 rval = QLA_FUNCTION_FAILED;
4381 if (!(options & VCO_DONT_UPDATE_FW)) {
7c3df132
SK		 4382 ql_dbg(ql_dbg_mbx, vha, 0x10cf,
4383 "Firmware update failed. Retrying "
4384 "without update firmware.\n");
4d4df193
HK		 4385 options |= VCO_DONT_UPDATE_FW;
4386 options &= ~VCO_FORCE_UPDATE;
4387 retry = 1;
4388 }
4389 } else {
5f28d2d7 4390 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d0,
7c3df132
SK		 4391 "Firmware updated to %x.\n",
4392 le32_to_cpu(mn->p.rsp.fw_ver));
4d4df193
HK		 4393
4394 /* NOTE: we only update OP firmware. */
4395 spin_lock_irqsave(&ha->cs84xx->access_lock, flags);
4396 ha->cs84xx->op_fw_version =
4397 le32_to_cpu(mn->p.rsp.fw_ver);
4398 spin_unlock_irqrestore(&ha->cs84xx->access_lock,
4399 flags);
4400 }
4401 } while (retry);
4402
4403verify_done:
4404 dma_pool_free(ha->s_dma_pool, mn, mn_dma);
4405
4406 if (rval != QLA_SUCCESS) {
5f28d2d7
SK		 4407 ql_dbg(ql_dbg_mbx, vha, 0x10d1,
4408 "Failed=%x.\n", rval);
4d4df193 4409 } else {
5f28d2d7
SK		 4410 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d2,
4411 "Done %s.\n", __func__);
4d4df193
HK		 4412 }
4413
4414 return rval;
4415}
73208dfd
AC		 4416
4417int
618a7523 4418qla25xx_init_req_que(struct scsi_qla_host *vha, struct req_que *req)
73208dfd
AC		 4419{
4420 int rval;
4421 unsigned long flags;
4422 mbx_cmd_t mc;
4423 mbx_cmd_t *mcp = &mc;
73208dfd
AC		 4424 struct qla_hw_data *ha = vha->hw;
4425
45235022
QT		 4426 if (!ha->flags.fw_started)
4427 return QLA_SUCCESS;
4428
5f28d2d7
SK		 4429 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d3,
4430 "Entered %s.\n", __func__);
7c3df132 4431
7c6300e3
JC		 4432 if (IS_SHADOW_REG_CAPABLE(ha))
4433 req->options |= BIT_13;
4434
73208dfd 4435 mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
618a7523 4436 mcp->mb[1] = req->options;
73208dfd
AC		 4437 mcp->mb[2] = MSW(LSD(req->dma));
4438 mcp->mb[3] = LSW(LSD(req->dma));
4439 mcp->mb[6] = MSW(MSD(req->dma));
4440 mcp->mb[7] = LSW(MSD(req->dma));
4441 mcp->mb[5] = req->length;
4442 if (req->rsp)
4443 mcp->mb[10] = req->rsp->id;
4444 mcp->mb[12] = req->qos;
4445 mcp->mb[11] = req->vp_idx;
4446 mcp->mb[13] = req->rid;
ecc89f25 4447 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
6246b8a1 4448 mcp->mb[15] = 0;
73208dfd 4449
73208dfd
AC		 4450 mcp->mb[4] = req->id;
4451 /* que in ptr index */
4452 mcp->mb[8] = 0;
4453 /* que out ptr index */
7c6300e3 4454 mcp->mb[9] = *req->out_ptr = 0;
73208dfd
AC		 4455 mcp->out_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|MBX_7|
4456 MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4457 mcp->in_mb = MBX_0;
4458 mcp->flags = MBX_DMA_OUT;
6246b8a1
GM		 4459 mcp->tov = MBX_TOV_SECONDS * 2;
4460
ecc89f25
JC		 4461 if (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
4462 IS_QLA28XX(ha))
6246b8a1 4463 mcp->in_mb |= MBX_1;
ecc89f25 4464 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
6246b8a1
GM		 4465 mcp->out_mb |= MBX_15;
4466 /* debug q create issue in SR-IOV */
4467 mcp->in_mb |= MBX_9 | MBX_8 | MBX_7;
4468 }
73208dfd
AC		 4469
4470 spin_lock_irqsave(&ha->hardware_lock, flags);
618a7523 4471 if (!(req->options & BIT_0)) {
04474d3a 4472 wrt_reg_dword(req->req_q_in, 0);
ecc89f25 4473 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
04474d3a 4474 wrt_reg_dword(req->req_q_out, 0);
73208dfd
AC		 4475 }
4476 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4477
17d98630 4478 rval = qla2x00_mailbox_command(vha, mcp);
7c3df132
SK		 4479 if (rval != QLA_SUCCESS) {
4480 ql_dbg(ql_dbg_mbx, vha, 0x10d4,
4481 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4482 } else {
5f28d2d7
SK		 4483 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d5,
4484 "Done %s.\n", __func__);
7c3df132
SK		 4485 }
4486
73208dfd
AC		 4487 return rval;
4488}
4489
4490int
618a7523 4491qla25xx_init_rsp_que(struct scsi_qla_host *vha, struct rsp_que *rsp)
73208dfd
AC		 4492{
4493 int rval;
4494 unsigned long flags;
4495 mbx_cmd_t mc;
4496 mbx_cmd_t *mcp = &mc;
73208dfd
AC		 4497 struct qla_hw_data *ha = vha->hw;
4498
45235022
QT		 4499 if (!ha->flags.fw_started)
4500 return QLA_SUCCESS;
4501
5f28d2d7
SK		 4502 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d6,
4503 "Entered %s.\n", __func__);
7c3df132 4504
7c6300e3
JC		 4505 if (IS_SHADOW_REG_CAPABLE(ha))
4506 rsp->options |= BIT_13;
4507
73208dfd 4508 mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
618a7523 4509 mcp->mb[1] = rsp->options;
73208dfd
AC		 4510 mcp->mb[2] = MSW(LSD(rsp->dma));
4511 mcp->mb[3] = LSW(LSD(rsp->dma));
4512 mcp->mb[6] = MSW(MSD(rsp->dma));
4513 mcp->mb[7] = LSW(MSD(rsp->dma));
4514 mcp->mb[5] = rsp->length;
444786d7 4515 mcp->mb[14] = rsp->msix->entry;
73208dfd 4516 mcp->mb[13] = rsp->rid;
ecc89f25 4517 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
6246b8a1 4518 mcp->mb[15] = 0;
73208dfd 4519
73208dfd
AC		 4520 mcp->mb[4] = rsp->id;
4521 /* que in ptr index */
7c6300e3 4522 mcp->mb[8] = *rsp->in_ptr = 0;
73208dfd
AC		 4523 /* que out ptr index */
4524 mcp->mb[9] = 0;
2afa19a9 4525 mcp->out_mb = MBX_14|MBX_13|MBX_9|MBX_8|MBX_7
73208dfd
AC		 4526 |MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4527 mcp->in_mb = MBX_0;
4528 mcp->flags = MBX_DMA_OUT;
6246b8a1
GM		 4529 mcp->tov = MBX_TOV_SECONDS * 2;
4530
4531 if (IS_QLA81XX(ha)) {
4532 mcp->out_mb |= MBX_12|MBX_11|MBX_10;
4533 mcp->in_mb |= MBX_1;
ecc89f25 4534 } else if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
6246b8a1
GM		 4535 mcp->out_mb |= MBX_15|MBX_12|MBX_11|MBX_10;
4536 mcp->in_mb |= MBX_1;
4537 /* debug q create issue in SR-IOV */
4538 mcp->in_mb |= MBX_9 | MBX_8 | MBX_7;
4539 }
73208dfd
AC		 4540
4541 spin_lock_irqsave(&ha->hardware_lock, flags);
618a7523 4542 if (!(rsp->options & BIT_0)) {
04474d3a 4543 wrt_reg_dword(rsp->rsp_q_out, 0);
ecc89f25 4544 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
04474d3a 4545 wrt_reg_dword(rsp->rsp_q_in, 0);
73208dfd
AC		 4546 }
4547
4548 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4549
17d98630 4550 rval = qla2x00_mailbox_command(vha, mcp);
7c3df132
SK		 4551 if (rval != QLA_SUCCESS) {
4552 ql_dbg(ql_dbg_mbx, vha, 0x10d7,
4553 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4554 } else {
5f28d2d7
SK		 4555 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d8,
4556 "Done %s.\n", __func__);
7c3df132
SK		 4557 }
4558
73208dfd
AC		 4559 return rval;
4560}
4561
8a659571
AV		 4562int
4563qla81xx_idc_ack(scsi_qla_host_t *vha, uint16_t *mb)
4564{
4565 int rval;
4566 mbx_cmd_t mc;
4567 mbx_cmd_t *mcp = &mc;
4568
5f28d2d7
SK		 4569 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d9,
4570 "Entered %s.\n", __func__);
8a659571
AV		 4571
4572 mcp->mb[0] = MBC_IDC_ACK;
4573 memcpy(&mcp->mb[1], mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
4574 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4575 mcp->in_mb = MBX_0;
4576 mcp->tov = MBX_TOV_SECONDS;
4577 mcp->flags = 0;
4578 rval = qla2x00_mailbox_command(vha, mcp);
4579
4580 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4581 ql_dbg(ql_dbg_mbx, vha, 0x10da,
4582 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
8a659571 4583 } else {
5f28d2d7
SK		 4584 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10db,
4585 "Done %s.\n", __func__);
8a659571
AV		 4586 }
4587
4588 return rval;
4589}
1d2874de
JC		 4590
4591int
4592qla81xx_fac_get_sector_size(scsi_qla_host_t *vha, uint32_t *sector_size)
4593{
4594 int rval;
4595 mbx_cmd_t mc;
4596 mbx_cmd_t *mcp = &mc;
4597
5f28d2d7
SK		 4598 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10dc,
4599 "Entered %s.\n", __func__);
7c3df132 4600
f73cb695 4601 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
ecc89f25 4602 !IS_QLA27XX(vha->hw) && !IS_QLA28XX(vha->hw))
1d2874de
JC		 4603 return QLA_FUNCTION_FAILED;
4604
1d2874de
JC		 4605 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
4606 mcp->mb[1] = FAC_OPT_CMD_GET_SECTOR_SIZE;
4607 mcp->out_mb = MBX_1|MBX_0;
4608 mcp->in_mb = MBX_1|MBX_0;
4609 mcp->tov = MBX_TOV_SECONDS;
4610 mcp->flags = 0;
4611 rval = qla2x00_mailbox_command(vha, mcp);
4612
4613 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4614 ql_dbg(ql_dbg_mbx, vha, 0x10dd,
4615 "Failed=%x mb[0]=%x mb[1]=%x.\n",
4616 rval, mcp->mb[0], mcp->mb[1]);
1d2874de 4617 } else {
5f28d2d7
SK		 4618 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10de,
4619 "Done %s.\n", __func__);
1d2874de
JC		 4620 *sector_size = mcp->mb[1];
4621 }
4622
4623 return rval;
4624}
4625
4626int
4627qla81xx_fac_do_write_enable(scsi_qla_host_t *vha, int enable)
4628{
4629 int rval;
4630 mbx_cmd_t mc;
4631 mbx_cmd_t *mcp = &mc;
4632
f73cb695 4633 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
ecc89f25 4634 !IS_QLA27XX(vha->hw) && !IS_QLA28XX(vha->hw))
1d2874de
JC		 4635 return QLA_FUNCTION_FAILED;
4636
5f28d2d7
SK		 4637 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10df,
4638 "Entered %s.\n", __func__);
1d2874de
JC		 4639
4640 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
4641 mcp->mb[1] = enable ? FAC_OPT_CMD_WRITE_ENABLE :
4642 FAC_OPT_CMD_WRITE_PROTECT;
4643 mcp->out_mb = MBX_1|MBX_0;
4644 mcp->in_mb = MBX_1|MBX_0;
4645 mcp->tov = MBX_TOV_SECONDS;
4646 mcp->flags = 0;
4647 rval = qla2x00_mailbox_command(vha, mcp);
4648
4649 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4650 ql_dbg(ql_dbg_mbx, vha, 0x10e0,
4651 "Failed=%x mb[0]=%x mb[1]=%x.\n",
4652 rval, mcp->mb[0], mcp->mb[1]);
1d2874de 4653 } else {
5f28d2d7
SK		 4654 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e1,
4655 "Done %s.\n", __func__);
1d2874de
JC		 4656 }
4657
4658 return rval;
4659}
4660
4661int
4662qla81xx_fac_erase_sector(scsi_qla_host_t *vha, uint32_t start, uint32_t finish)
4663{
4664 int rval;
4665 mbx_cmd_t mc;
4666 mbx_cmd_t *mcp = &mc;
4667
f73cb695 4668 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
ecc89f25 4669 !IS_QLA27XX(vha->hw) && !IS_QLA28XX(vha->hw))
1d2874de
JC		 4670 return QLA_FUNCTION_FAILED;
4671
5f28d2d7
SK		 4672 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e2,
4673 "Entered %s.\n", __func__);
1d2874de
JC		 4674
4675 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
4676 mcp->mb[1] = FAC_OPT_CMD_ERASE_SECTOR;
4677 mcp->mb[2] = LSW(start);
4678 mcp->mb[3] = MSW(start);
4679 mcp->mb[4] = LSW(finish);
4680 mcp->mb[5] = MSW(finish);
4681 mcp->out_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4682 mcp->in_mb = MBX_2|MBX_1|MBX_0;
4683 mcp->tov = MBX_TOV_SECONDS;
4684 mcp->flags = 0;
4685 rval = qla2x00_mailbox_command(vha, mcp);
4686
4687 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4688 ql_dbg(ql_dbg_mbx, vha, 0x10e3,
4689 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
4690 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
1d2874de 4691 } else {
5f28d2d7
SK		 4692 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e4,
4693 "Done %s.\n", __func__);
1d2874de
JC		 4694 }
4695
4696 return rval;
4697}
6e181be5 4698
3f006ac3
MH		 4699int
4700qla81xx_fac_semaphore_access(scsi_qla_host_t *vha, int lock)
4701{
4702 int rval = QLA_SUCCESS;
4703 mbx_cmd_t mc;
4704 mbx_cmd_t *mcp = &mc;
4705 struct qla_hw_data *ha = vha->hw;
4706
4707 if (!IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
4708 !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
4709 return rval;
4710
4711 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e2,
4712 "Entered %s.\n", __func__);
4713
4714 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
4715 mcp->mb[1] = (lock ? FAC_OPT_CMD_LOCK_SEMAPHORE :
4716 FAC_OPT_CMD_UNLOCK_SEMAPHORE);
4717 mcp->out_mb = MBX_1|MBX_0;
4718 mcp->in_mb = MBX_1|MBX_0;
4719 mcp->tov = MBX_TOV_SECONDS;
4720 mcp->flags = 0;
4721 rval = qla2x00_mailbox_command(vha, mcp);
4722
4723 if (rval != QLA_SUCCESS) {
4724 ql_dbg(ql_dbg_mbx, vha, 0x10e3,
4725 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
4726 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
4727 } else {
4728 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e4,
4729 "Done %s.\n", __func__);
4730 }
4731
4732 return rval;
4733}
4734
6e181be5
LC		 4735int
4736qla81xx_restart_mpi_firmware(scsi_qla_host_t *vha)
4737{
4738 int rval = 0;
4739 mbx_cmd_t mc;
4740 mbx_cmd_t *mcp = &mc;
4741
5f28d2d7
SK		 4742 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e5,
4743 "Entered %s.\n", __func__);
6e181be5
LC		 4744
4745 mcp->mb[0] = MBC_RESTART_MPI_FW;
4746 mcp->out_mb = MBX_0;
4747 mcp->in_mb = MBX_0|MBX_1;
4748 mcp->tov = MBX_TOV_SECONDS;
4749 mcp->flags = 0;
4750 rval = qla2x00_mailbox_command(vha, mcp);
4751
4752 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4753 ql_dbg(ql_dbg_mbx, vha, 0x10e6,
4754 "Failed=%x mb[0]=%x mb[1]=%x.\n",
4755 rval, mcp->mb[0], mcp->mb[1]);
6e181be5 4756 } else {
5f28d2d7
SK		 4757 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e7,
4758 "Done %s.\n", __func__);
6e181be5
LC		 4759 }
4760
4761 return rval;
4762}
ad0ecd61 4763
c46e65c7
JC		 4764int
4765qla82xx_set_driver_version(scsi_qla_host_t *vha, char *version)
4766{
4767 int rval;
4768 mbx_cmd_t mc;
4769 mbx_cmd_t *mcp = &mc;
4770 int i;
4771 int len;
7ffa5b93 4772 __le16 *str;
c46e65c7
JC		 4773 struct qla_hw_data *ha = vha->hw;
4774
4775 if (!IS_P3P_TYPE(ha))
4776 return QLA_FUNCTION_FAILED;
4777
4778 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117b,
4779 "Entered %s.\n", __func__);
4780
7ffa5b93 4781 str = (__force __le16 *)version;
c46e65c7
JC		 4782 len = strlen(version);
4783
4784 mcp->mb[0] = MBC_SET_RNID_PARAMS;
4785 mcp->mb[1] = RNID_TYPE_SET_VERSION << 8;
4786 mcp->out_mb = MBX_1|MBX_0;
4787 for (i = 4; i < 16 && len; i++, str++, len -= 2) {
7ffa5b93 4788 mcp->mb[i] = le16_to_cpup(str);
c46e65c7
JC		 4789 mcp->out_mb |= 1<<i;
4790 }
4791 for (; i < 16; i++) {
4792 mcp->mb[i] = 0;
4793 mcp->out_mb |= 1<<i;
4794 }
4795 mcp->in_mb = MBX_1|MBX_0;
4796 mcp->tov = MBX_TOV_SECONDS;
4797 mcp->flags = 0;
4798 rval = qla2x00_mailbox_command(vha, mcp);
4799
4800 if (rval != QLA_SUCCESS) {
4801 ql_dbg(ql_dbg_mbx, vha, 0x117c,
4802 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
4803 } else {
4804 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117d,
4805 "Done %s.\n", __func__);
4806 }
4807
4808 return rval;
4809}
4810
4811int
4812qla25xx_set_driver_version(scsi_qla_host_t *vha, char *version)
4813{
4814 int rval;
4815 mbx_cmd_t mc;
4816 mbx_cmd_t *mcp = &mc;
4817 int len;
4818 uint16_t dwlen;
4819 uint8_t *str;
4820 dma_addr_t str_dma;
4821 struct qla_hw_data *ha = vha->hw;
4822
4823 if (!IS_FWI2_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA81XX(ha) ||
4824 IS_P3P_TYPE(ha))
4825 return QLA_FUNCTION_FAILED;
4826
4827 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117e,
4828 "Entered %s.\n", __func__);
4829
4830 str = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &str_dma);
4831 if (!str) {
4832 ql_log(ql_log_warn, vha, 0x117f,
4833 "Failed to allocate driver version param.\n");
4834 return QLA_MEMORY_ALLOC_FAILED;
4835 }
4836
4837 memcpy(str, "\x7\x3\x11\x0", 4);
4838 dwlen = str[0];
4839 len = dwlen * 4 - 4;
4840 memset(str + 4, 0, len);
4841 if (len > strlen(version))
4842 len = strlen(version);
4843 memcpy(str + 4, version, len);
4844
4845 mcp->mb[0] = MBC_SET_RNID_PARAMS;
4846 mcp->mb[1] = RNID_TYPE_SET_VERSION << 8 | dwlen;
4847 mcp->mb[2] = MSW(LSD(str_dma));
4848 mcp->mb[3] = LSW(LSD(str_dma));
4849 mcp->mb[6] = MSW(MSD(str_dma));
4850 mcp->mb[7] = LSW(MSD(str_dma));
4851 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
4852 mcp->in_mb = MBX_1|MBX_0;
4853 mcp->tov = MBX_TOV_SECONDS;
4854 mcp->flags = 0;
4855 rval = qla2x00_mailbox_command(vha, mcp);
4856
4857 if (rval != QLA_SUCCESS) {
4858 ql_dbg(ql_dbg_mbx, vha, 0x1180,
4859 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
4860 } else {
4861 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1181,
4862 "Done %s.\n", __func__);
4863 }
4864
4865 dma_pool_free(ha->s_dma_pool, str, str_dma);
4866
4867 return rval;
4868}
4869
edd05de1
DG		 4870int
4871qla24xx_get_port_login_templ(scsi_qla_host_t *vha, dma_addr_t buf_dma,
4872 void *buf, uint16_t bufsiz)
4873{
4874 int rval, i;
4875 mbx_cmd_t mc;
4876 mbx_cmd_t *mcp = &mc;
4877 uint32_t *bp;
4878
4879 if (!IS_FWI2_CAPABLE(vha->hw))
4880 return QLA_FUNCTION_FAILED;
4881
4882 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1159,
4883 "Entered %s.\n", __func__);
4884
4885 mcp->mb[0] = MBC_GET_RNID_PARAMS;
4886 mcp->mb[1] = RNID_TYPE_PORT_LOGIN << 8;
4887 mcp->mb[2] = MSW(buf_dma);
4888 mcp->mb[3] = LSW(buf_dma);
4889 mcp->mb[6] = MSW(MSD(buf_dma));
4890 mcp->mb[7] = LSW(MSD(buf_dma));
4891 mcp->mb[8] = bufsiz/4;
4892 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4893 mcp->in_mb = MBX_1|MBX_0;
4894 mcp->tov = MBX_TOV_SECONDS;
4895 mcp->flags = 0;
4896 rval = qla2x00_mailbox_command(vha, mcp);
4897
4898 if (rval != QLA_SUCCESS) {
4899 ql_dbg(ql_dbg_mbx, vha, 0x115a,
4900 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
4901 } else {
4902 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x115b,
4903 "Done %s.\n", __func__);
4904 bp = (uint32_t *) buf;
4905 for (i = 0; i < (bufsiz-4)/4; i++, bp++)
7ffa5b93 4906 *bp = le32_to_cpu((__force __le32)*bp);
edd05de1
DG		 4907 }
4908
4909 return rval;
4910}
4911
62e9dd17 4912#define PUREX_CMD_COUNT 2
d83a80ee
JC		 4913int
4914qla25xx_set_els_cmds_supported(scsi_qla_host_t *vha)
4915{
4916 int rval;
4917 mbx_cmd_t mc;
4918 mbx_cmd_t *mcp = &mc;
4919 uint8_t *els_cmd_map;
4920 dma_addr_t els_cmd_map_dma;
62e9dd17
SS		 4921 uint8_t cmd_opcode[PUREX_CMD_COUNT];
4922 uint8_t i, index, purex_bit;
d83a80ee
JC		 4923 struct qla_hw_data *ha = vha->hw;
4924
62e9dd17
SS		 4925 if (!IS_QLA25XX(ha) && !IS_QLA2031(ha) &&
4926 !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
d83a80ee
JC		 4927 return QLA_SUCCESS;
4928
4929 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1197,
4930 "Entered %s.\n", __func__);
4931
4932 els_cmd_map = dma_alloc_coherent(&ha->pdev->dev, ELS_CMD_MAP_SIZE,
4933 &els_cmd_map_dma, GFP_KERNEL);
4934 if (!els_cmd_map) {
4935 ql_log(ql_log_warn, vha, 0x7101,
4936 "Failed to allocate RDP els command param.\n");
4937 return QLA_MEMORY_ALLOC_FAILED;
4938 }
4939
62e9dd17
SS		 4940 /* List of Purex ELS */
4941 cmd_opcode[0] = ELS_FPIN;
4942 cmd_opcode[1] = ELS_RDP;
4943
4944 for (i = 0; i < PUREX_CMD_COUNT; i++) {
4945 index = cmd_opcode[i] / 8;
4946 purex_bit = cmd_opcode[i] % 8;
4947 els_cmd_map[index] |= 1 << purex_bit;
4948 }
d83a80ee
JC		 4949
4950 mcp->mb[0] = MBC_SET_RNID_PARAMS;
4951 mcp->mb[1] = RNID_TYPE_ELS_CMD << 8;
4952 mcp->mb[2] = MSW(LSD(els_cmd_map_dma));
4953 mcp->mb[3] = LSW(LSD(els_cmd_map_dma));
4954 mcp->mb[6] = MSW(MSD(els_cmd_map_dma));
4955 mcp->mb[7] = LSW(MSD(els_cmd_map_dma));
4956 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
4957 mcp->in_mb = MBX_1|MBX_0;
4958 mcp->tov = MBX_TOV_SECONDS;
4959 mcp->flags = MBX_DMA_OUT;
4960 mcp->buf_size = ELS_CMD_MAP_SIZE;
4961 rval = qla2x00_mailbox_command(vha, mcp);
4962
4963 if (rval != QLA_SUCCESS) {
4964 ql_dbg(ql_dbg_mbx, vha, 0x118d,
4965 "Failed=%x (%x,%x).\n", rval, mcp->mb[0], mcp->mb[1]);
4966 } else {
4967 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118c,
4968 "Done %s.\n", __func__);
4969 }
4970
650b323c 4971 dma_free_coherent(&ha->pdev->dev, ELS_CMD_MAP_SIZE,
d83a80ee
JC		 4972 els_cmd_map, els_cmd_map_dma);
4973
4974 return rval;
4975}
4976
fe52f6e1
JC		 4977static int
4978qla2x00_read_asic_temperature(scsi_qla_host_t *vha, uint16_t *temp)
4979{
4980 int rval;
4981 mbx_cmd_t mc;
4982 mbx_cmd_t *mcp = &mc;
4983
4984 if (!IS_FWI2_CAPABLE(vha->hw))
4985 return QLA_FUNCTION_FAILED;
4986
4987 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1159,
4988 "Entered %s.\n", __func__);
4989
4990 mcp->mb[0] = MBC_GET_RNID_PARAMS;
4991 mcp->mb[1] = RNID_TYPE_ASIC_TEMP << 8;
4992 mcp->out_mb = MBX_1|MBX_0;
4993 mcp->in_mb = MBX_1|MBX_0;
4994 mcp->tov = MBX_TOV_SECONDS;
4995 mcp->flags = 0;
4996 rval = qla2x00_mailbox_command(vha, mcp);
4997 *temp = mcp->mb[1];
4998
4999 if (rval != QLA_SUCCESS) {
5000 ql_dbg(ql_dbg_mbx, vha, 0x115a,
5001 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
5002 } else {
5003 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x115b,
5004 "Done %s.\n", __func__);
5005 }
5006
5007 return rval;
5008}
5009
ad0ecd61 5010int
6766df9e
JC		 5011qla2x00_read_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
5012 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
ad0ecd61
JC		 5013{
5014 int rval;
5015 mbx_cmd_t mc;
5016 mbx_cmd_t *mcp = &mc;
6766df9e
JC		 5017 struct qla_hw_data *ha = vha->hw;
5018
5f28d2d7
SK		 5019 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e8,
5020 "Entered %s.\n", __func__);
7c3df132 5021
6766df9e
JC		 5022 if (!IS_FWI2_CAPABLE(ha))
5023 return QLA_FUNCTION_FAILED;
ad0ecd61 5024
6766df9e
JC		 5025 if (len == 1)
5026 opt |= BIT_0;
5027
ad0ecd61
JC		 5028 mcp->mb[0] = MBC_READ_SFP;
5029 mcp->mb[1] = dev;
818c7f87
JC		 5030 mcp->mb[2] = MSW(LSD(sfp_dma));
5031 mcp->mb[3] = LSW(LSD(sfp_dma));
ad0ecd61
JC		 5032 mcp->mb[6] = MSW(MSD(sfp_dma));
5033 mcp->mb[7] = LSW(MSD(sfp_dma));
5034 mcp->mb[8] = len;
6766df9e 5035 mcp->mb[9] = off;
ad0ecd61
JC		 5036 mcp->mb[10] = opt;
5037 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1bff6cc8 5038 mcp->in_mb = MBX_1|MBX_0;
ad0ecd61
JC		 5039 mcp->tov = MBX_TOV_SECONDS;
5040 mcp->flags = 0;
5041 rval = qla2x00_mailbox_command(vha, mcp);
5042
5043 if (opt & BIT_0)
6766df9e 5044 *sfp = mcp->mb[1];
ad0ecd61
JC		 5045
5046 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5047 ql_dbg(ql_dbg_mbx, vha, 0x10e9,
5048 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
2a3192a3 5049 if (mcp->mb[0] == MBS_COMMAND_ERROR && mcp->mb[1] == 0x22) {
e4e3a2ce
QT		 5050 /* sfp is not there */
5051 rval = QLA_INTERFACE_ERROR;
2a3192a3 5052 }
ad0ecd61 5053 } else {
5f28d2d7
SK		 5054 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea,
5055 "Done %s.\n", __func__);
ad0ecd61
JC		 5056 }
5057
5058 return rval;
5059}
5060
5061int
6766df9e
JC		 5062qla2x00_write_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
5063 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
ad0ecd61
JC		 5064{
5065 int rval;
5066 mbx_cmd_t mc;
5067 mbx_cmd_t *mcp = &mc;
6766df9e
JC		 5068 struct qla_hw_data *ha = vha->hw;
5069
5f28d2d7
SK		 5070 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10eb,
5071 "Entered %s.\n", __func__);
7c3df132 5072
6766df9e
JC		 5073 if (!IS_FWI2_CAPABLE(ha))
5074 return QLA_FUNCTION_FAILED;
ad0ecd61 5075
6766df9e
JC		 5076 if (len == 1)
5077 opt |= BIT_0;
5078
ad0ecd61 5079 if (opt & BIT_0)
6766df9e 5080 len = *sfp;
ad0ecd61
JC		 5081
5082 mcp->mb[0] = MBC_WRITE_SFP;
5083 mcp->mb[1] = dev;
818c7f87
JC		 5084 mcp->mb[2] = MSW(LSD(sfp_dma));
5085 mcp->mb[3] = LSW(LSD(sfp_dma));
ad0ecd61
JC		 5086 mcp->mb[6] = MSW(MSD(sfp_dma));
5087 mcp->mb[7] = LSW(MSD(sfp_dma));
5088 mcp->mb[8] = len;
6766df9e 5089 mcp->mb[9] = off;
ad0ecd61
JC		 5090 mcp->mb[10] = opt;
5091 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
6766df9e 5092 mcp->in_mb = MBX_1|MBX_0;
ad0ecd61
JC		 5093 mcp->tov = MBX_TOV_SECONDS;
5094 mcp->flags = 0;
5095 rval = qla2x00_mailbox_command(vha, mcp);
5096
5097 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5098 ql_dbg(ql_dbg_mbx, vha, 0x10ec,
5099 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
ad0ecd61 5100 } else {
5f28d2d7
SK		 5101 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ed,
5102 "Done %s.\n", __func__);
ad0ecd61
JC		 5103 }
5104
5105 return rval;
5106}
ce0423f4
AV		 5107
5108int
5109qla2x00_get_xgmac_stats(scsi_qla_host_t *vha, dma_addr_t stats_dma,
5110 uint16_t size_in_bytes, uint16_t *actual_size)
5111{
5112 int rval;
5113 mbx_cmd_t mc;
5114 mbx_cmd_t *mcp = &mc;
5115
5f28d2d7
SK		 5116 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ee,
5117 "Entered %s.\n", __func__);
7c3df132 5118
6246b8a1 5119 if (!IS_CNA_CAPABLE(vha->hw))
ce0423f4
AV		 5120 return QLA_FUNCTION_FAILED;
5121
ce0423f4
AV		 5122 mcp->mb[0] = MBC_GET_XGMAC_STATS;
5123 mcp->mb[2] = MSW(stats_dma);
5124 mcp->mb[3] = LSW(stats_dma);
5125 mcp->mb[6] = MSW(MSD(stats_dma));
5126 mcp->mb[7] = LSW(MSD(stats_dma));
5127 mcp->mb[8] = size_in_bytes >> 2;
5128 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
5129 mcp->in_mb = MBX_2|MBX_1|MBX_0;
5130 mcp->tov = MBX_TOV_SECONDS;
5131 mcp->flags = 0;
5132 rval = qla2x00_mailbox_command(vha, mcp);
5133
5134 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5135 ql_dbg(ql_dbg_mbx, vha, 0x10ef,
5136 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
5137 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
ce0423f4 5138 } else {
5f28d2d7
SK		 5139 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f0,
5140 "Done %s.\n", __func__);
7c3df132 5141
ce0423f4
AV		 5142
5143 *actual_size = mcp->mb[2] << 2;
5144 }
5145
5146 return rval;
5147}
11bbc1d8
AV		 5148
5149int
5150qla2x00_get_dcbx_params(scsi_qla_host_t *vha, dma_addr_t tlv_dma,
5151 uint16_t size)
5152{
5153 int rval;
5154 mbx_cmd_t mc;
5155 mbx_cmd_t *mcp = &mc;
5156
5f28d2d7
SK		 5157 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f1,
5158 "Entered %s.\n", __func__);
7c3df132 5159
6246b8a1 5160 if (!IS_CNA_CAPABLE(vha->hw))
11bbc1d8
AV		 5161 return QLA_FUNCTION_FAILED;
5162
11bbc1d8
AV		 5163 mcp->mb[0] = MBC_GET_DCBX_PARAMS;
5164 mcp->mb[1] = 0;
5165 mcp->mb[2] = MSW(tlv_dma);
5166 mcp->mb[3] = LSW(tlv_dma);
5167 mcp->mb[6] = MSW(MSD(tlv_dma));
5168 mcp->mb[7] = LSW(MSD(tlv_dma));
5169 mcp->mb[8] = size;
5170 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
5171 mcp->in_mb = MBX_2|MBX_1|MBX_0;
5172 mcp->tov = MBX_TOV_SECONDS;
5173 mcp->flags = 0;
5174 rval = qla2x00_mailbox_command(vha, mcp);
5175
5176 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5177 ql_dbg(ql_dbg_mbx, vha, 0x10f2,
5178 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
5179 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
11bbc1d8 5180 } else {
5f28d2d7
SK		 5181 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f3,
5182 "Done %s.\n", __func__);
11bbc1d8
AV		 5183 }
5184
5185 return rval;
5186}
18e7555a
AV		 5187
5188int
5189qla2x00_read_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t *data)
5190{
5191 int rval;
5192 mbx_cmd_t mc;
5193 mbx_cmd_t *mcp = &mc;
5194
5f28d2d7
SK		 5195 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f4,
5196 "Entered %s.\n", __func__);
7c3df132 5197
18e7555a
AV		 5198 if (!IS_FWI2_CAPABLE(vha->hw))
5199 return QLA_FUNCTION_FAILED;
5200
18e7555a
AV		 5201 mcp->mb[0] = MBC_READ_RAM_EXTENDED;
5202 mcp->mb[1] = LSW(risc_addr);
5203 mcp->mb[8] = MSW(risc_addr);
5204 mcp->out_mb = MBX_8|MBX_1|MBX_0;
5205 mcp->in_mb = MBX_3|MBX_2|MBX_0;
c314a014 5206 mcp->tov = MBX_TOV_SECONDS;
18e7555a
AV		 5207 mcp->flags = 0;
5208 rval = qla2x00_mailbox_command(vha, mcp);
5209 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5210 ql_dbg(ql_dbg_mbx, vha, 0x10f5,
5211 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
18e7555a 5212 } else {
5f28d2d7
SK		 5213 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f6,
5214 "Done %s.\n", __func__);
18e7555a
AV		 5215 *data = mcp->mb[3] << 16 | mcp->mb[2];
5216 }
5217
5218 return rval;
5219}
5220
9a069e19 5221int
a9083016
GM		 5222qla2x00_loopback_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
5223 uint16_t *mresp)
9a069e19
GM		 5224{
5225 int rval;
5226 mbx_cmd_t mc;
5227 mbx_cmd_t *mcp = &mc;
9a069e19 5228
5f28d2d7
SK		 5229 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f7,
5230 "Entered %s.\n", __func__);
9a069e19
GM		 5231
5232 memset(mcp->mb, 0 , sizeof(mcp->mb));
5233 mcp->mb[0] = MBC_DIAGNOSTIC_LOOP_BACK;
5234 mcp->mb[1] = mreq->options | BIT_6; // BIT_6 specifies 64 bit addressing
5235
5236 /* transfer count */
5237 mcp->mb[10] = LSW(mreq->transfer_size);
5238 mcp->mb[11] = MSW(mreq->transfer_size);
5239
5240 /* send data address */
5241 mcp->mb[14] = LSW(mreq->send_dma);
5242 mcp->mb[15] = MSW(mreq->send_dma);
5243 mcp->mb[20] = LSW(MSD(mreq->send_dma));
5244 mcp->mb[21] = MSW(MSD(mreq->send_dma));
5245
25985edc 5246 /* receive data address */
9a069e19
GM		 5247 mcp->mb[16] = LSW(mreq->rcv_dma);
5248 mcp->mb[17] = MSW(mreq->rcv_dma);
5249 mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
5250 mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
5251
5252 /* Iteration count */
1b98b421
JC		 5253 mcp->mb[18] = LSW(mreq->iteration_count);
5254 mcp->mb[19] = MSW(mreq->iteration_count);
9a069e19
GM		 5255
5256 mcp->out_mb = MBX_21|MBX_20|MBX_19|MBX_18|MBX_17|MBX_16|MBX_15|
5257 MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
6246b8a1 5258 if (IS_CNA_CAPABLE(vha->hw))
9a069e19
GM		 5259 mcp->out_mb |= MBX_2;
5260 mcp->in_mb = MBX_19|MBX_18|MBX_3|MBX_2|MBX_1|MBX_0;
5261
5262 mcp->buf_size = mreq->transfer_size;
5263 mcp->tov = MBX_TOV_SECONDS;
5264 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
5265
5266 rval = qla2x00_mailbox_command(vha, mcp);
5267
5268 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5269 ql_dbg(ql_dbg_mbx, vha, 0x10f8,
5270 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[18]=%x "
5271 "mb[19]=%x.\n", rval, mcp->mb[0], mcp->mb[1], mcp->mb[2],
5272 mcp->mb[3], mcp->mb[18], mcp->mb[19]);
9a069e19 5273 } else {
5f28d2d7
SK		 5274 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f9,
5275 "Done %s.\n", __func__);
9a069e19
GM		 5276 }
5277
5278 /* Copy mailbox information */
5279 memcpy( mresp, mcp->mb, 64);
9a069e19
GM		 5280 return rval;
5281}
5282
5283int
a9083016
GM		 5284qla2x00_echo_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
5285 uint16_t *mresp)
9a069e19
GM		 5286{
5287 int rval;
5288 mbx_cmd_t mc;
5289 mbx_cmd_t *mcp = &mc;
5290 struct qla_hw_data *ha = vha->hw;
5291
5f28d2d7
SK		 5292 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fa,
5293 "Entered %s.\n", __func__);
9a069e19
GM		 5294
5295 memset(mcp->mb, 0 , sizeof(mcp->mb));
5296 mcp->mb[0] = MBC_DIAGNOSTIC_ECHO;
1d634965
JC		 5297 /* BIT_6 specifies 64bit address */
5298 mcp->mb[1] = mreq->options | BIT_15 | BIT_6;
6246b8a1 5299 if (IS_CNA_CAPABLE(ha)) {
a9083016
GM		 5300 mcp->mb[2] = vha->fcoe_fcf_idx;
5301 }
9a069e19
GM		 5302 mcp->mb[16] = LSW(mreq->rcv_dma);
5303 mcp->mb[17] = MSW(mreq->rcv_dma);
5304 mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
5305 mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
5306
5307 mcp->mb[10] = LSW(mreq->transfer_size);
5308
5309 mcp->mb[14] = LSW(mreq->send_dma);
5310 mcp->mb[15] = MSW(mreq->send_dma);
5311 mcp->mb[20] = LSW(MSD(mreq->send_dma));
5312 mcp->mb[21] = MSW(MSD(mreq->send_dma));
5313
5314 mcp->out_mb = MBX_21|MBX_20|MBX_17|MBX_16|MBX_15|
5315 MBX_14|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
6246b8a1 5316 if (IS_CNA_CAPABLE(ha))
9a069e19
GM		 5317 mcp->out_mb |= MBX_2;
5318
5319 mcp->in_mb = MBX_0;
83cfd3dc
JC		 5320 if (IS_CNA_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha) ||
5321 IS_QLA2031(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
9a069e19 5322 mcp->in_mb |= MBX_1;
83cfd3dc
JC		 5323 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
5324 IS_QLA28XX(ha))
9a069e19
GM		 5325 mcp->in_mb |= MBX_3;
5326
5327 mcp->tov = MBX_TOV_SECONDS;
5328 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
5329 mcp->buf_size = mreq->transfer_size;
5330
5331 rval = qla2x00_mailbox_command(vha, mcp);
5332
5333 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5334 ql_dbg(ql_dbg_mbx, vha, 0x10fb,
5335 "Failed=%x mb[0]=%x mb[1]=%x.\n",
5336 rval, mcp->mb[0], mcp->mb[1]);
9a069e19 5337 } else {
5f28d2d7
SK		 5338 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fc,
5339 "Done %s.\n", __func__);
9a069e19
GM		 5340 }
5341
5342 /* Copy mailbox information */
6dbdda4d 5343 memcpy(mresp, mcp->mb, 64);
9a069e19
GM		 5344 return rval;
5345}
6dbdda4d 5346
9a069e19 5347int
7c3df132 5348qla84xx_reset_chip(scsi_qla_host_t *vha, uint16_t enable_diagnostic)
9a069e19
GM		 5349{
5350 int rval;
5351 mbx_cmd_t mc;
5352 mbx_cmd_t *mcp = &mc;
5353
5f28d2d7 5354 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fd,
7c3df132 5355 "Entered %s enable_diag=%d.\n", __func__, enable_diagnostic);
9a069e19
GM		 5356
5357 mcp->mb[0] = MBC_ISP84XX_RESET;
5358 mcp->mb[1] = enable_diagnostic;
5359 mcp->out_mb = MBX_1|MBX_0;
5360 mcp->in_mb = MBX_1|MBX_0;
5361 mcp->tov = MBX_TOV_SECONDS;
5362 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
7c3df132 5363 rval = qla2x00_mailbox_command(vha, mcp);
9a069e19 5364
9a069e19 5365 if (rval != QLA_SUCCESS)
7c3df132 5366 ql_dbg(ql_dbg_mbx, vha, 0x10fe, "Failed=%x.\n", rval);
9a069e19 5367 else
5f28d2d7
SK		 5368 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ff,
5369 "Done %s.\n", __func__);
9a069e19
GM		 5370
5371 return rval;
5372}
5373
18e7555a
AV		 5374int
5375qla2x00_write_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t data)
5376{
5377 int rval;
5378 mbx_cmd_t mc;
5379 mbx_cmd_t *mcp = &mc;
5380
5f28d2d7
SK		 5381 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1100,
5382 "Entered %s.\n", __func__);
7c3df132 5383
18e7555a 5384 if (!IS_FWI2_CAPABLE(vha->hw))
6c452a45 5385 return QLA_FUNCTION_FAILED;
18e7555a 5386
18e7555a
AV		 5387 mcp->mb[0] = MBC_WRITE_RAM_WORD_EXTENDED;
5388 mcp->mb[1] = LSW(risc_addr);
5389 mcp->mb[2] = LSW(data);
5390 mcp->mb[3] = MSW(data);
5391 mcp->mb[8] = MSW(risc_addr);
5392 mcp->out_mb = MBX_8|MBX_3|MBX_2|MBX_1|MBX_0;
2a3192a3 5393 mcp->in_mb = MBX_1|MBX_0;
c314a014 5394 mcp->tov = MBX_TOV_SECONDS;
18e7555a
AV		 5395 mcp->flags = 0;
5396 rval = qla2x00_mailbox_command(vha, mcp);
5397 if (rval != QLA_SUCCESS) {
7c3df132 5398 ql_dbg(ql_dbg_mbx, vha, 0x1101,
2a3192a3
JC		 5399 "Failed=%x mb[0]=%x mb[1]=%x.\n",
5400 rval, mcp->mb[0], mcp->mb[1]);
18e7555a 5401 } else {
5f28d2d7
SK		 5402 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1102,
5403 "Done %s.\n", __func__);
18e7555a
AV		 5404 }
5405
5406 return rval;
5407}
3064ff39 5408
b1d46989
MI		 5409int
5410qla81xx_write_mpi_register(scsi_qla_host_t *vha, uint16_t *mb)
5411{
5412 int rval;
5413 uint32_t stat, timer;
5414 uint16_t mb0 = 0;
5415 struct qla_hw_data *ha = vha->hw;
5416 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
5417
5418 rval = QLA_SUCCESS;
5419
5f28d2d7
SK		 5420 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1103,
5421 "Entered %s.\n", __func__);
b1d46989
MI		 5422
5423 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
5424
5425 /* Write the MBC data to the registers */
04474d3a
BVA		 5426 wrt_reg_word(&reg->mailbox0, MBC_WRITE_MPI_REGISTER);
5427 wrt_reg_word(&reg->mailbox1, mb[0]);
5428 wrt_reg_word(&reg->mailbox2, mb[1]);
5429 wrt_reg_word(&reg->mailbox3, mb[2]);
5430 wrt_reg_word(&reg->mailbox4, mb[3]);
b1d46989 5431
04474d3a 5432 wrt_reg_dword(&reg->hccr, HCCRX_SET_HOST_INT);
b1d46989
MI		 5433
5434 /* Poll for MBC interrupt */
5435 for (timer = 6000000; timer; timer--) {
5436 /* Check for pending interrupts. */
04474d3a 5437 stat = rd_reg_dword(&reg->host_status);
b1d46989
MI		 5438 if (stat & HSRX_RISC_INT) {
5439 stat &= 0xff;
5440
5441 if (stat == 0x1 || stat == 0x2 ||
5442 stat == 0x10 || stat == 0x11) {
5443 set_bit(MBX_INTERRUPT,
5444 &ha->mbx_cmd_flags);
04474d3a
BVA		 5445 mb0 = rd_reg_word(&reg->mailbox0);
5446 wrt_reg_dword(&reg->hccr,
b1d46989 5447 HCCRX_CLR_RISC_INT);
04474d3a 5448 rd_reg_dword(&reg->hccr);
b1d46989
MI		 5449 break;
5450 }
5451 }
5452 udelay(5);
5453 }
5454
5455 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags))
5456 rval = mb0 & MBS_MASK;
5457 else
5458 rval = QLA_FUNCTION_FAILED;
5459
5460 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5461 ql_dbg(ql_dbg_mbx, vha, 0x1104,
5462 "Failed=%x mb[0]=%x.\n", rval, mb[0]);
b1d46989 5463 } else {
5f28d2d7
SK		 5464 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1105,
5465 "Done %s.\n", __func__);
b1d46989
MI		 5466 }
5467
5468 return rval;
5469}
6246b8a1 5470
4910b524
AG		 5471/* Set the specified data rate */
5472int
5473qla2x00_set_data_rate(scsi_qla_host_t *vha, uint16_t mode)
5474{
5475 int rval;
5476 mbx_cmd_t mc;
5477 mbx_cmd_t *mcp = &mc;
5478 struct qla_hw_data *ha = vha->hw;
5479 uint16_t val;
5480
5481 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1106,
5482 "Entered %s speed:0x%x mode:0x%x.\n", __func__, ha->set_data_rate,
5483 mode);
5484
5485 if (!IS_FWI2_CAPABLE(ha))
5486 return QLA_FUNCTION_FAILED;
5487
5488 memset(mcp, 0, sizeof(*mcp));
5489 switch (ha->set_data_rate) {
5490 case PORT_SPEED_AUTO:
5491 case PORT_SPEED_4GB:
5492 case PORT_SPEED_8GB:
5493 case PORT_SPEED_16GB:
5494 case PORT_SPEED_32GB:
5495 val = ha->set_data_rate;
5496 break;
5497 default:
5498 ql_log(ql_log_warn, vha, 0x1199,
5499 "Unrecognized speed setting:%d. Setting Autoneg\n",
5500 ha->set_data_rate);
5501 val = ha->set_data_rate = PORT_SPEED_AUTO;
5502 break;
5503 }
5504
5505 mcp->mb[0] = MBC_DATA_RATE;
5506 mcp->mb[1] = mode;
5507 mcp->mb[2] = val;
5508
5509 mcp->out_mb = MBX_2|MBX_1|MBX_0;
5510 mcp->in_mb = MBX_2|MBX_1|MBX_0;
ecc89f25 5511 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
4910b524
AG		 5512 mcp->in_mb |= MBX_4|MBX_3;
5513 mcp->tov = MBX_TOV_SECONDS;
5514 mcp->flags = 0;
5515 rval = qla2x00_mailbox_command(vha, mcp);
5516 if (rval != QLA_SUCCESS) {
5517 ql_dbg(ql_dbg_mbx, vha, 0x1107,
5518 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5519 } else {
5520 if (mcp->mb[1] != 0x7)
5521 ql_dbg(ql_dbg_mbx, vha, 0x1179,
5522 "Speed set:0x%x\n", mcp->mb[1]);
5523
5524 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1108,
5525 "Done %s.\n", __func__);
5526 }
5527
5528 return rval;
5529}
5530
3064ff39
MH		 5531int
5532qla2x00_get_data_rate(scsi_qla_host_t *vha)
5533{
5534 int rval;
5535 mbx_cmd_t mc;
5536 mbx_cmd_t *mcp = &mc;
5537 struct qla_hw_data *ha = vha->hw;
5538
5f28d2d7
SK		 5539 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1106,
5540 "Entered %s.\n", __func__);
7c3df132 5541
3064ff39
MH		 5542 if (!IS_FWI2_CAPABLE(ha))
5543 return QLA_FUNCTION_FAILED;
5544
3064ff39 5545 mcp->mb[0] = MBC_DATA_RATE;
4910b524 5546 mcp->mb[1] = QLA_GET_DATA_RATE;
3064ff39
MH		 5547 mcp->out_mb = MBX_1|MBX_0;
5548 mcp->in_mb = MBX_2|MBX_1|MBX_0;
ecc89f25 5549 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
6246b8a1 5550 mcp->in_mb |= MBX_3;
3064ff39
MH		 5551 mcp->tov = MBX_TOV_SECONDS;
5552 mcp->flags = 0;
5553 rval = qla2x00_mailbox_command(vha, mcp);
5554 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5555 ql_dbg(ql_dbg_mbx, vha, 0x1107,
5556 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3064ff39 5557 } else {
75666f4a
HM		 5558 if (mcp->mb[1] != 0x7)
5559 ha->link_data_rate = mcp->mb[1];
5560
5561 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
5562 if (mcp->mb[4] & BIT_0)
5563 ql_log(ql_log_info, vha, 0x11a2,
5564 "FEC=enabled (data rate).\n");
5565 }
5566
5f28d2d7
SK		 5567 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1108,
5568 "Done %s.\n", __func__);
3064ff39
MH		 5569 if (mcp->mb[1] != 0x7)
5570 ha->link_data_rate = mcp->mb[1];
5571 }
5572
5573 return rval;
5574}
09ff701a 5575
23f2ebd1
SR		 5576int
5577qla81xx_get_port_config(scsi_qla_host_t *vha, uint16_t *mb)
5578{
5579 int rval;
5580 mbx_cmd_t mc;
5581 mbx_cmd_t *mcp = &mc;
5582 struct qla_hw_data *ha = vha->hw;
5583
5f28d2d7
SK		 5584 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1109,
5585 "Entered %s.\n", __func__);
23f2ebd1 5586
f73cb695 5587 if (!IS_QLA81XX(ha) && !IS_QLA83XX(ha) && !IS_QLA8044(ha) &&
ecc89f25 5588 !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
23f2ebd1
SR		 5589 return QLA_FUNCTION_FAILED;
5590 mcp->mb[0] = MBC_GET_PORT_CONFIG;
5591 mcp->out_mb = MBX_0;
5592 mcp->in_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5593 mcp->tov = MBX_TOV_SECONDS;
5594 mcp->flags = 0;
5595
5596 rval = qla2x00_mailbox_command(vha, mcp);
5597
5598 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5599 ql_dbg(ql_dbg_mbx, vha, 0x110a,
5600 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
23f2ebd1
SR		 5601 } else {
5602 /* Copy all bits to preserve original value */
5603 memcpy(mb, &mcp->mb[1], sizeof(uint16_t) * 4);
5604
5f28d2d7
SK		 5605 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110b,
5606 "Done %s.\n", __func__);
23f2ebd1
SR		 5607 }
5608 return rval;
5609}
5610
5611int
5612qla81xx_set_port_config(scsi_qla_host_t *vha, uint16_t *mb)
5613{
5614 int rval;
5615 mbx_cmd_t mc;
5616 mbx_cmd_t *mcp = &mc;
5617
5f28d2d7
SK		 5618 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110c,
5619 "Entered %s.\n", __func__);
23f2ebd1
SR		 5620
5621 mcp->mb[0] = MBC_SET_PORT_CONFIG;
5622 /* Copy all bits to preserve original setting */
5623 memcpy(&mcp->mb[1], mb, sizeof(uint16_t) * 4);
5624 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5625 mcp->in_mb = MBX_0;
5626 mcp->tov = MBX_TOV_SECONDS;
5627 mcp->flags = 0;
5628 rval = qla2x00_mailbox_command(vha, mcp);
5629
5630 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5631 ql_dbg(ql_dbg_mbx, vha, 0x110d,
5632 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
23f2ebd1 5633 } else
5f28d2d7
SK		 5634 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110e,
5635 "Done %s.\n", __func__);
23f2ebd1
SR		 5636
5637 return rval;
5638}
5639
5640
09ff701a
SR		 5641int
5642qla24xx_set_fcp_prio(scsi_qla_host_t *vha, uint16_t loop_id, uint16_t priority,
5643 uint16_t *mb)
5644{
5645 int rval;
5646 mbx_cmd_t mc;
5647 mbx_cmd_t *mcp = &mc;
5648 struct qla_hw_data *ha = vha->hw;
5649
5f28d2d7
SK		 5650 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110f,
5651 "Entered %s.\n", __func__);
7c3df132 5652
09ff701a
SR		 5653 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha))
5654 return QLA_FUNCTION_FAILED;
5655
09ff701a
SR		 5656 mcp->mb[0] = MBC_PORT_PARAMS;
5657 mcp->mb[1] = loop_id;
5658 if (ha->flags.fcp_prio_enabled)
5659 mcp->mb[2] = BIT_1;
5660 else
5661 mcp->mb[2] = BIT_2;
5662 mcp->mb[4] = priority & 0xf;
5663 mcp->mb[9] = vha->vp_idx;
5664 mcp->out_mb = MBX_9|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5665 mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0;
c314a014 5666 mcp->tov = MBX_TOV_SECONDS;
09ff701a
SR		 5667 mcp->flags = 0;
5668 rval = qla2x00_mailbox_command(vha, mcp);
5669 if (mb != NULL) {
5670 mb[0] = mcp->mb[0];
5671 mb[1] = mcp->mb[1];
5672 mb[3] = mcp->mb[3];
5673 mb[4] = mcp->mb[4];
5674 }
5675
5676 if (rval != QLA_SUCCESS) {
7c3df132 5677 ql_dbg(ql_dbg_mbx, vha, 0x10cd, "Failed=%x.\n", rval);
09ff701a 5678 } else {
5f28d2d7
SK		 5679 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10cc,
5680 "Done %s.\n", __func__);
09ff701a
SR		 5681 }
5682
5683 return rval;
5684}
a9083016 5685
794a5691 5686int
fe52f6e1 5687qla2x00_get_thermal_temp(scsi_qla_host_t *vha, uint16_t *temp)
794a5691 5688{
fe52f6e1 5689 int rval = QLA_FUNCTION_FAILED;
794a5691 5690 struct qla_hw_data *ha = vha->hw;
fe52f6e1 5691 uint8_t byte;
794a5691 5692
1ae47cf3
JC		 5693 if (!IS_FWI2_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA81XX(ha)) {
5694 ql_dbg(ql_dbg_mbx, vha, 0x1150,
5695 "Thermal not supported by this card.\n");
5696 return rval;
5697 }
5698
5699 if (IS_QLA25XX(ha)) {
5700 if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
5701 ha->pdev->subsystem_device == 0x0175) {
5702 rval = qla2x00_read_sfp(vha, 0, &byte,
5703 0x98, 0x1, 1, BIT_13|BIT_0);
5704 *temp = byte;
5705 return rval;
5706 }
5707 if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
5708 ha->pdev->subsystem_device == 0x338e) {
5709 rval = qla2x00_read_sfp(vha, 0, &byte,
5710 0x98, 0x1, 1, BIT_15|BIT_14|BIT_0);
5711 *temp = byte;
5712 return rval;
5713 }
5714 ql_dbg(ql_dbg_mbx, vha, 0x10c9,
5715 "Thermal not supported by this card.\n");
5716 return rval;
794a5691 5717 }
794a5691 5718
1ae47cf3
JC		 5719 if (IS_QLA82XX(ha)) {
5720 *temp = qla82xx_read_temperature(vha);
5721 rval = QLA_SUCCESS;
5722 return rval;
5723 } else if (IS_QLA8044(ha)) {
5724 *temp = qla8044_read_temperature(vha);
5725 rval = QLA_SUCCESS;
5726 return rval;
794a5691 5727 }
794a5691 5728
1ae47cf3 5729 rval = qla2x00_read_asic_temperature(vha, temp);
794a5691
AV		 5730 return rval;
5731}
5732
a9083016
GM		 5733int
5734qla82xx_mbx_intr_enable(scsi_qla_host_t *vha)
5735{
5736 int rval;
5737 struct qla_hw_data *ha = vha->hw;
5738 mbx_cmd_t mc;
5739 mbx_cmd_t *mcp = &mc;
5740
5f28d2d7
SK		 5741 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1017,
5742 "Entered %s.\n", __func__);
7c3df132 5743
a9083016
GM		 5744 if (!IS_FWI2_CAPABLE(ha))
5745 return QLA_FUNCTION_FAILED;
5746
a9083016 5747 memset(mcp, 0, sizeof(mbx_cmd_t));
3711333d 5748 mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
a9083016
GM		 5749 mcp->mb[1] = 1;
5750
5751 mcp->out_mb = MBX_1|MBX_0;
5752 mcp->in_mb = MBX_0;
c314a014 5753 mcp->tov = MBX_TOV_SECONDS;
a9083016
GM		 5754 mcp->flags = 0;
5755
5756 rval = qla2x00_mailbox_command(vha, mcp);
5757 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5758 ql_dbg(ql_dbg_mbx, vha, 0x1016,
5759 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
a9083016 5760 } else {
5f28d2d7
SK		 5761 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100e,
5762 "Done %s.\n", __func__);
a9083016
GM		 5763 }
5764
5765 return rval;
5766}
5767
5768int
5769qla82xx_mbx_intr_disable(scsi_qla_host_t *vha)
5770{
5771 int rval;
5772 struct qla_hw_data *ha = vha->hw;
5773 mbx_cmd_t mc;
5774 mbx_cmd_t *mcp = &mc;
5775
5f28d2d7
SK		 5776 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100d,
5777 "Entered %s.\n", __func__);
7c3df132 5778
7ec0effd 5779 if (!IS_P3P_TYPE(ha))
a9083016
GM		 5780 return QLA_FUNCTION_FAILED;
5781
a9083016 5782 memset(mcp, 0, sizeof(mbx_cmd_t));
3711333d 5783 mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
a9083016
GM		 5784 mcp->mb[1] = 0;
5785
5786 mcp->out_mb = MBX_1|MBX_0;
5787 mcp->in_mb = MBX_0;
c314a014 5788 mcp->tov = MBX_TOV_SECONDS;
a9083016
GM		 5789 mcp->flags = 0;
5790
5791 rval = qla2x00_mailbox_command(vha, mcp);
5792 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5793 ql_dbg(ql_dbg_mbx, vha, 0x100c,
5794 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
a9083016 5795 } else {
5f28d2d7
SK		 5796 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100b,
5797 "Done %s.\n", __func__);
a9083016
GM		 5798 }
5799
5800 return rval;
5801}
08de2844
GM		 5802
5803int
5804qla82xx_md_get_template_size(scsi_qla_host_t *vha)
5805{
5806 struct qla_hw_data *ha = vha->hw;
5807 mbx_cmd_t mc;
5808 mbx_cmd_t *mcp = &mc;
5809 int rval = QLA_FUNCTION_FAILED;
5810
5f28d2d7
SK		 5811 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111f,
5812 "Entered %s.\n", __func__);
08de2844
GM		 5813
5814 memset(mcp->mb, 0 , sizeof(mcp->mb));
5815 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5816 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5817 mcp->mb[2] = LSW(RQST_TMPLT_SIZE);
5818 mcp->mb[3] = MSW(RQST_TMPLT_SIZE);
5819
5820 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
5821 mcp->in_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
5822 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5823
5824 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
5825 mcp->tov = MBX_TOV_SECONDS;
5826 rval = qla2x00_mailbox_command(vha, mcp);
5827
5828 /* Always copy back return mailbox values. */
5829 if (rval != QLA_SUCCESS) {
5830 ql_dbg(ql_dbg_mbx, vha, 0x1120,
5831 "mailbox command FAILED=0x%x, subcode=%x.\n",
5832 (mcp->mb[1] << 16) | mcp->mb[0],
5833 (mcp->mb[3] << 16) | mcp->mb[2]);
5834 } else {
5f28d2d7
SK		 5835 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1121,
5836 "Done %s.\n", __func__);
08de2844
GM		 5837 ha->md_template_size = ((mcp->mb[3] << 16) | mcp->mb[2]);
5838 if (!ha->md_template_size) {
5839 ql_dbg(ql_dbg_mbx, vha, 0x1122,
5840 "Null template size obtained.\n");
5841 rval = QLA_FUNCTION_FAILED;
5842 }
5843 }
5844 return rval;
5845}
5846
5847int
5848qla82xx_md_get_template(scsi_qla_host_t *vha)
5849{
5850 struct qla_hw_data *ha = vha->hw;
5851 mbx_cmd_t mc;
5852 mbx_cmd_t *mcp = &mc;
5853 int rval = QLA_FUNCTION_FAILED;
5854
5f28d2d7
SK		 5855 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1123,
5856 "Entered %s.\n", __func__);
08de2844
GM		 5857
5858 ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev,
5859 ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL);
5860 if (!ha->md_tmplt_hdr) {
5861 ql_log(ql_log_warn, vha, 0x1124,
5862 "Unable to allocate memory for Minidump template.\n");
5863 return rval;
5864 }
5865
5866 memset(mcp->mb, 0 , sizeof(mcp->mb));
5867 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5868 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5869 mcp->mb[2] = LSW(RQST_TMPLT);
5870 mcp->mb[3] = MSW(RQST_TMPLT);
5871 mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma));
5872 mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma));
5873 mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma));
5874 mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma));
5875 mcp->mb[8] = LSW(ha->md_template_size);
5876 mcp->mb[9] = MSW(ha->md_template_size);
5877
5878 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
5879 mcp->tov = MBX_TOV_SECONDS;
5880 mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8|
5881 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5882 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
5883 rval = qla2x00_mailbox_command(vha, mcp);
5884
5885 if (rval != QLA_SUCCESS) {
5886 ql_dbg(ql_dbg_mbx, vha, 0x1125,
5887 "mailbox command FAILED=0x%x, subcode=%x.\n",
5888 ((mcp->mb[1] << 16) | mcp->mb[0]),
5889 ((mcp->mb[3] << 16) | mcp->mb[2]));
5890 } else
5f28d2d7
SK		 5891 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1126,
5892 "Done %s.\n", __func__);
08de2844
GM		 5893 return rval;
5894}
999916dc 5895
7ec0effd
AD		 5896int
5897qla8044_md_get_template(scsi_qla_host_t *vha)
5898{
5899 struct qla_hw_data *ha = vha->hw;
5900 mbx_cmd_t mc;
5901 mbx_cmd_t *mcp = &mc;
5902 int rval = QLA_FUNCTION_FAILED;
5903 int offset = 0, size = MINIDUMP_SIZE_36K;
bd432bb5 5904
7ec0effd
AD		 5905 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11f,
5906 "Entered %s.\n", __func__);
5907
5908 ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev,
5909 ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL);
5910 if (!ha->md_tmplt_hdr) {
5911 ql_log(ql_log_warn, vha, 0xb11b,
5912 "Unable to allocate memory for Minidump template.\n");
5913 return rval;
5914 }
5915
5916 memset(mcp->mb, 0 , sizeof(mcp->mb));
5917 while (offset < ha->md_template_size) {
5918 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5919 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5920 mcp->mb[2] = LSW(RQST_TMPLT);
5921 mcp->mb[3] = MSW(RQST_TMPLT);
5922 mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma + offset));
5923 mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma + offset));
5924 mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma + offset));
5925 mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma + offset));
5926 mcp->mb[8] = LSW(size);
5927 mcp->mb[9] = MSW(size);
5928 mcp->mb[10] = offset & 0x0000FFFF;
5929 mcp->mb[11] = offset & 0xFFFF0000;
5930 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
5931 mcp->tov = MBX_TOV_SECONDS;
5932 mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8|
5933 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5934 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
5935 rval = qla2x00_mailbox_command(vha, mcp);
5936
5937 if (rval != QLA_SUCCESS) {
5938 ql_dbg(ql_dbg_mbx, vha, 0xb11c,
5939 "mailbox command FAILED=0x%x, subcode=%x.\n",
5940 ((mcp->mb[1] << 16) | mcp->mb[0]),
5941 ((mcp->mb[3] << 16) | mcp->mb[2]));
5942 return rval;
5943 } else
5944 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11d,
5945 "Done %s.\n", __func__);
5946 offset = offset + size;
5947 }
5948 return rval;
5949}
5950
6246b8a1
GM		 5951int
5952qla81xx_set_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg)
5953{
5954 int rval;
5955 struct qla_hw_data *ha = vha->hw;
5956 mbx_cmd_t mc;
5957 mbx_cmd_t *mcp = &mc;
5958
5959 if (!IS_QLA81XX(ha) && !IS_QLA8031(ha))
5960 return QLA_FUNCTION_FAILED;
5961
5f28d2d7
SK		 5962 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1133,
5963 "Entered %s.\n", __func__);
6246b8a1
GM		 5964
5965 memset(mcp, 0, sizeof(mbx_cmd_t));
5966 mcp->mb[0] = MBC_SET_LED_CONFIG;
5967 mcp->mb[1] = led_cfg[0];
5968 mcp->mb[2] = led_cfg[1];
5969 if (IS_QLA8031(ha)) {
5970 mcp->mb[3] = led_cfg[2];
5971 mcp->mb[4] = led_cfg[3];
5972 mcp->mb[5] = led_cfg[4];
5973 mcp->mb[6] = led_cfg[5];
5974 }
5975
5976 mcp->out_mb = MBX_2|MBX_1|MBX_0;
5977 if (IS_QLA8031(ha))
5978 mcp->out_mb |= MBX_6|MBX_5|MBX_4|MBX_3;
5979 mcp->in_mb = MBX_0;
c314a014 5980 mcp->tov = MBX_TOV_SECONDS;
6246b8a1
GM		 5981 mcp->flags = 0;
5982
5983 rval = qla2x00_mailbox_command(vha, mcp);
5984 if (rval != QLA_SUCCESS) {
5985 ql_dbg(ql_dbg_mbx, vha, 0x1134,
5986 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5987 } else {
5f28d2d7
SK		 5988 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1135,
5989 "Done %s.\n", __func__);
6246b8a1
GM		 5990 }
5991
5992 return rval;
5993}
5994
5995int
5996qla81xx_get_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg)
5997{
5998 int rval;
5999 struct qla_hw_data *ha = vha->hw;
6000 mbx_cmd_t mc;
6001 mbx_cmd_t *mcp = &mc;
6002
6003 if (!IS_QLA81XX(ha) && !IS_QLA8031(ha))
6004 return QLA_FUNCTION_FAILED;
6005
5f28d2d7
SK		 6006 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1136,
6007 "Entered %s.\n", __func__);
6246b8a1
GM		 6008
6009 memset(mcp, 0, sizeof(mbx_cmd_t));
6010 mcp->mb[0] = MBC_GET_LED_CONFIG;
6011
6012 mcp->out_mb = MBX_0;
6013 mcp->in_mb = MBX_2|MBX_1|MBX_0;
6014 if (IS_QLA8031(ha))
6015 mcp->in_mb |= MBX_6|MBX_5|MBX_4|MBX_3;
c314a014 6016 mcp->tov = MBX_TOV_SECONDS;
6246b8a1
GM		 6017 mcp->flags = 0;
6018
6019 rval = qla2x00_mailbox_command(vha, mcp);
6020 if (rval != QLA_SUCCESS) {
6021 ql_dbg(ql_dbg_mbx, vha, 0x1137,
6022 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
6023 } else {
6024 led_cfg[0] = mcp->mb[1];
6025 led_cfg[1] = mcp->mb[2];
6026 if (IS_QLA8031(ha)) {
6027 led_cfg[2] = mcp->mb[3];
6028 led_cfg[3] = mcp->mb[4];
6029 led_cfg[4] = mcp->mb[5];
6030 led_cfg[5] = mcp->mb[6];
6031 }
5f28d2d7
SK		 6032 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1138,
6033 "Done %s.\n", __func__);
6246b8a1
GM		 6034 }
6035
6036 return rval;
6037}
6038
999916dc
SK		 6039int
6040qla82xx_mbx_beacon_ctl(scsi_qla_host_t *vha, int enable)
6041{
6042 int rval;
6043 struct qla_hw_data *ha = vha->hw;
6044 mbx_cmd_t mc;
6045 mbx_cmd_t *mcp = &mc;
6046
7ec0effd 6047 if (!IS_P3P_TYPE(ha))
999916dc
SK		 6048 return QLA_FUNCTION_FAILED;
6049
5f28d2d7 6050 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1127,
999916dc
SK		 6051 "Entered %s.\n", __func__);
6052
6053 memset(mcp, 0, sizeof(mbx_cmd_t));
6054 mcp->mb[0] = MBC_SET_LED_CONFIG;
6055 if (enable)
6056 mcp->mb[7] = 0xE;
6057 else
6058 mcp->mb[7] = 0xD;
6059
6060 mcp->out_mb = MBX_7|MBX_0;
6061 mcp->in_mb = MBX_0;
6246b8a1 6062 mcp->tov = MBX_TOV_SECONDS;
999916dc
SK		 6063 mcp->flags = 0;
6064
6065 rval = qla2x00_mailbox_command(vha, mcp);
6066 if (rval != QLA_SUCCESS) {
6067 ql_dbg(ql_dbg_mbx, vha, 0x1128,
6068 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
6069 } else {
5f28d2d7 6070 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1129,
999916dc
SK		 6071 "Done %s.\n", __func__);
6072 }
6073
6074 return rval;
6075}
6246b8a1
GM		 6076
6077int
7d613ac6 6078qla83xx_wr_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t data)
6246b8a1
GM		 6079{
6080 int rval;
6081 struct qla_hw_data *ha = vha->hw;
6082 mbx_cmd_t mc;
6083 mbx_cmd_t *mcp = &mc;
6084
ecc89f25 6085 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
6246b8a1
GM		 6086 return QLA_FUNCTION_FAILED;
6087
5f28d2d7
SK		 6088 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1130,
6089 "Entered %s.\n", __func__);
6246b8a1
GM		 6090
6091 mcp->mb[0] = MBC_WRITE_REMOTE_REG;
6092 mcp->mb[1] = LSW(reg);
6093 mcp->mb[2] = MSW(reg);
6094 mcp->mb[3] = LSW(data);
6095 mcp->mb[4] = MSW(data);
6096 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
6097
6098 mcp->in_mb = MBX_1|MBX_0;
6099 mcp->tov = MBX_TOV_SECONDS;
6100 mcp->flags = 0;
6101 rval = qla2x00_mailbox_command(vha, mcp);
6102
6103 if (rval != QLA_SUCCESS) {
6104 ql_dbg(ql_dbg_mbx, vha, 0x1131,
6105 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
6106 } else {
5f28d2d7 6107 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1132,
6246b8a1
GM		 6108 "Done %s.\n", __func__);
6109 }
af11f64d 6110
6246b8a1
GM		 6111 return rval;
6112}
af11f64d
AV		 6113
6114int
6115qla2x00_port_logout(scsi_qla_host_t *vha, struct fc_port *fcport)
6116{
6117 int rval;
6118 struct qla_hw_data *ha = vha->hw;
6119 mbx_cmd_t mc;
6120 mbx_cmd_t *mcp = &mc;
6121
6122 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
5f28d2d7 6123 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113b,
af11f64d
AV		 6124 "Implicit LOGO Unsupported.\n");
6125 return QLA_FUNCTION_FAILED;
6126 }
6127
6128
5f28d2d7
SK		 6129 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113c,
6130 "Entering %s.\n", __func__);
af11f64d
AV		 6131
6132 /* Perform Implicit LOGO. */
6133 mcp->mb[0] = MBC_PORT_LOGOUT;
6134 mcp->mb[1] = fcport->loop_id;
6135 mcp->mb[10] = BIT_15;
6136 mcp->out_mb = MBX_10|MBX_1|MBX_0;
6137 mcp->in_mb = MBX_0;
6138 mcp->tov = MBX_TOV_SECONDS;
6139 mcp->flags = 0;
6140 rval = qla2x00_mailbox_command(vha, mcp);
6141 if (rval != QLA_SUCCESS)
6142 ql_dbg(ql_dbg_mbx, vha, 0x113d,
6143 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
6144 else
5f28d2d7
SK		 6145 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113e,
6146 "Done %s.\n", __func__);
af11f64d
AV		 6147
6148 return rval;
6149}
6150
7d613ac6
SV		 6151int
6152qla83xx_rd_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t *data)
6153{
6154 int rval;
6155 mbx_cmd_t mc;
6156 mbx_cmd_t *mcp = &mc;
6157 struct qla_hw_data *ha = vha->hw;
6158 unsigned long retry_max_time = jiffies + (2 * HZ);
6159
ecc89f25 6160 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
7d613ac6
SV		 6161 return QLA_FUNCTION_FAILED;
6162
6163 ql_dbg(ql_dbg_mbx, vha, 0x114b, "Entered %s.\n", __func__);
6164
6165retry_rd_reg:
6166 mcp->mb[0] = MBC_READ_REMOTE_REG;
6167 mcp->mb[1] = LSW(reg);
6168 mcp->mb[2] = MSW(reg);
6169 mcp->out_mb = MBX_2|MBX_1|MBX_0;
6170 mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0;
6171 mcp->tov = MBX_TOV_SECONDS;
6172 mcp->flags = 0;
6173 rval = qla2x00_mailbox_command(vha, mcp);
6174
6175 if (rval != QLA_SUCCESS) {
6176 ql_dbg(ql_dbg_mbx, vha, 0x114c,
6177 "Failed=%x mb[0]=%x mb[1]=%x.\n",
6178 rval, mcp->mb[0], mcp->mb[1]);
6179 } else {
6180 *data = (mcp->mb[3] | (mcp->mb[4] << 16));
6181 if (*data == QLA8XXX_BAD_VALUE) {
6182 /*
6183 * During soft-reset CAMRAM register reads might
6184 * return 0xbad0bad0. So retry for MAX of 2 sec
6185 * while reading camram registers.
6186 */
6187 if (time_after(jiffies, retry_max_time)) {
6188 ql_dbg(ql_dbg_mbx, vha, 0x1141,
6189 "Failure to read CAMRAM register. "
6190 "data=0x%x.\n", *data);
6191 return QLA_FUNCTION_FAILED;
6192 }
6193 msleep(100);
6194 goto retry_rd_reg;
6195 }
6196 ql_dbg(ql_dbg_mbx, vha, 0x1142, "Done %s.\n", __func__);
6197 }
6198
6199 return rval;
6200}
6201
6202int
6203qla83xx_restart_nic_firmware(scsi_qla_host_t *vha)
6204{
6205 int rval;
6206 mbx_cmd_t mc;
6207 mbx_cmd_t *mcp = &mc;
6208 struct qla_hw_data *ha = vha->hw;
6209
ecc89f25 6210 if (!IS_QLA83XX(ha))
7d613ac6
SV		 6211 return QLA_FUNCTION_FAILED;
6212
6213 ql_dbg(ql_dbg_mbx, vha, 0x1143, "Entered %s.\n", __func__);
6214
6215 mcp->mb[0] = MBC_RESTART_NIC_FIRMWARE;
6216 mcp->out_mb = MBX_0;
6217 mcp->in_mb = MBX_1|MBX_0;
6218 mcp->tov = MBX_TOV_SECONDS;
6219 mcp->flags = 0;
6220 rval = qla2x00_mailbox_command(vha, mcp);
6221
6222 if (rval != QLA_SUCCESS) {
6223 ql_dbg(ql_dbg_mbx, vha, 0x1144,
6224 "Failed=%x mb[0]=%x mb[1]=%x.\n",
6225 rval, mcp->mb[0], mcp->mb[1]);
8ae17876 6226 qla2xxx_dump_fw(vha);
7d613ac6
SV		 6227 } else {
6228 ql_dbg(ql_dbg_mbx, vha, 0x1145, "Done %s.\n", __func__);
6229 }
6230
6231 return rval;
6232}
6233
6234int
6235qla83xx_access_control(scsi_qla_host_t *vha, uint16_t options,
6236 uint32_t start_addr, uint32_t end_addr, uint16_t *sector_size)
6237{
6238 int rval;
6239 mbx_cmd_t mc;
6240 mbx_cmd_t *mcp = &mc;
6241 uint8_t subcode = (uint8_t)options;
6242 struct qla_hw_data *ha = vha->hw;
6243
6244 if (!IS_QLA8031(ha))
6245 return QLA_FUNCTION_FAILED;
6246
6247 ql_dbg(ql_dbg_mbx, vha, 0x1146, "Entered %s.\n", __func__);
6248
6249 mcp->mb[0] = MBC_SET_ACCESS_CONTROL;
6250 mcp->mb[1] = options;
6251 mcp->out_mb = MBX_1|MBX_0;
6252 if (subcode & BIT_2) {
6253 mcp->mb[2] = LSW(start_addr);
6254 mcp->mb[3] = MSW(start_addr);
6255 mcp->mb[4] = LSW(end_addr);
6256 mcp->mb[5] = MSW(end_addr);
6257 mcp->out_mb |= MBX_5|MBX_4|MBX_3|MBX_2;
6258 }
6259 mcp->in_mb = MBX_2|MBX_1|MBX_0;
6260 if (!(subcode & (BIT_2 | BIT_5)))
6261 mcp->in_mb |= MBX_4|MBX_3;
6262 mcp->tov = MBX_TOV_SECONDS;
6263 mcp->flags = 0;
6264 rval = qla2x00_mailbox_command(vha, mcp);
6265
6266 if (rval != QLA_SUCCESS) {
6267 ql_dbg(ql_dbg_mbx, vha, 0x1147,
6268 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[4]=%x.\n",
6269 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3],
6270 mcp->mb[4]);
8ae17876 6271 qla2xxx_dump_fw(vha);
7d613ac6
SV		 6272 } else {
6273 if (subcode & BIT_5)
6274 *sector_size = mcp->mb[1];
6275 else if (subcode & (BIT_6 | BIT_7)) {
6276 ql_dbg(ql_dbg_mbx, vha, 0x1148,
6277 "Driver-lock id=%x%x", mcp->mb[4], mcp->mb[3]);
6278 } else if (subcode & (BIT_3 | BIT_4)) {
6279 ql_dbg(ql_dbg_mbx, vha, 0x1149,
6280 "Flash-lock id=%x%x", mcp->mb[4], mcp->mb[3]);
6281 }
6282 ql_dbg(ql_dbg_mbx, vha, 0x114a, "Done %s.\n", __func__);
6283 }
6284
6285 return rval;
6286}
81178772
SK		 6287
6288int
6289qla2x00_dump_mctp_data(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr,
6290 uint32_t size)
6291{
6292 int rval;
6293 mbx_cmd_t mc;
6294 mbx_cmd_t *mcp = &mc;
6295
6296 if (!IS_MCTP_CAPABLE(vha->hw))
6297 return QLA_FUNCTION_FAILED;
6298
6299 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114f,
6300 "Entered %s.\n", __func__);
6301
6302 mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED;
6303 mcp->mb[1] = LSW(addr);
6304 mcp->mb[2] = MSW(req_dma);
6305 mcp->mb[3] = LSW(req_dma);
6306 mcp->mb[4] = MSW(size);
6307 mcp->mb[5] = LSW(size);
6308 mcp->mb[6] = MSW(MSD(req_dma));
6309 mcp->mb[7] = LSW(MSD(req_dma));
6310 mcp->mb[8] = MSW(addr);
6311 /* Setting RAM ID to valid */
81178772 6312 /* For MCTP RAM ID is 0x40 */
641e0efd 6313 mcp->mb[10] = BIT_7 | 0x40;
81178772
SK		 6314
6315 mcp->out_mb |= MBX_10|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|
6316 MBX_0;
6317
6318 mcp->in_mb = MBX_0;
6319 mcp->tov = MBX_TOV_SECONDS;
6320 mcp->flags = 0;
6321 rval = qla2x00_mailbox_command(vha, mcp);
6322
6323 if (rval != QLA_SUCCESS) {
6324 ql_dbg(ql_dbg_mbx, vha, 0x114e,
6325 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
6326 } else {
6327 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114d,
6328 "Done %s.\n", __func__);
6329 }
6330
6331 return rval;
6332}
ec891462
JC		 6333
6334int
6335qla26xx_dport_diagnostics(scsi_qla_host_t *vha,
6336 void *dd_buf, uint size, uint options)
6337{
6338 int rval;
6339 mbx_cmd_t mc;
6340 mbx_cmd_t *mcp = &mc;
6341 dma_addr_t dd_dma;
6342
ecc89f25
JC		 6343 if (!IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw) &&
6344 !IS_QLA28XX(vha->hw))
ec891462
JC		 6345 return QLA_FUNCTION_FAILED;
6346
83548fe2 6347 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x119f,
ec891462
JC		 6348 "Entered %s.\n", __func__);
6349
ec891462
JC		 6350 dd_dma = dma_map_single(&vha->hw->pdev->dev,
6351 dd_buf, size, DMA_FROM_DEVICE);
0b2ce198 6352 if (dma_mapping_error(&vha->hw->pdev->dev, dd_dma)) {
ec891462
JC		 6353 ql_log(ql_log_warn, vha, 0x1194, "Failed to map dma buffer.\n");
6354 return QLA_MEMORY_ALLOC_FAILED;
6355 }
6356
6357 memset(dd_buf, 0, size);
6358
6359 mcp->mb[0] = MBC_DPORT_DIAGNOSTICS;
6360 mcp->mb[1] = options;
6361 mcp->mb[2] = MSW(LSD(dd_dma));
6362 mcp->mb[3] = LSW(LSD(dd_dma));
6363 mcp->mb[6] = MSW(MSD(dd_dma));
6364 mcp->mb[7] = LSW(MSD(dd_dma));
6365 mcp->mb[8] = size;
6366 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
6367 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
6368 mcp->buf_size = size;
6369 mcp->flags = MBX_DMA_IN;
6370 mcp->tov = MBX_TOV_SECONDS * 4;
6371 rval = qla2x00_mailbox_command(vha, mcp);
6372
6373 if (rval != QLA_SUCCESS) {
6374 ql_dbg(ql_dbg_mbx, vha, 0x1195, "Failed=%x.\n", rval);
6375 } else {
6376 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1196,
6377 "Done %s.\n", __func__);
6378 }
6379
6380 dma_unmap_single(&vha->hw->pdev->dev, dd_dma,
6381 size, DMA_FROM_DEVICE);
6382
6383 return rval;
6384}
15f30a57 6385
6c18a43e 6386static void qla2x00_async_mb_sp_done(srb_t *sp, int res)
15f30a57 6387{
15f30a57
QT		 6388 sp->u.iocb_cmd.u.mbx.rc = res;
6389
6390 complete(&sp->u.iocb_cmd.u.mbx.comp);
6391 /* don't free sp here. Let the caller do the free */
6392}
6393
6394/*
6395 * This mailbox uses the iocb interface to send MB command.
6396 * This allows non-critial (non chip setup) command to go
6397 * out in parrallel.
6398 */
6399int qla24xx_send_mb_cmd(struct scsi_qla_host *vha, mbx_cmd_t *mcp)
6400{
6401 int rval = QLA_FUNCTION_FAILED;
6402 srb_t *sp;
6403 struct srb_iocb *c;
6404
6405 if (!vha->hw->flags.fw_started)
6406 goto done;
6407
6408 sp = qla2x00_get_sp(vha, NULL, GFP_KERNEL);
6409 if (!sp)
6410 goto done;
6411
6412 sp->type = SRB_MB_IOCB;
6413 sp->name = mb_to_str(mcp->mb[0]);
6414
15f30a57
QT		 6415 c = &sp->u.iocb_cmd;
6416 c->timeout = qla2x00_async_iocb_timeout;
6417 init_completion(&c->u.mbx.comp);
6418
e74e7d95
BH		 6419 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
6420
6421 memcpy(sp->u.iocb_cmd.u.mbx.out_mb, mcp->mb, SIZEOF_IOCB_MB_REG);
6422
15f30a57
QT		 6423 sp->done = qla2x00_async_mb_sp_done;
6424
6425 rval = qla2x00_start_sp(sp);
6426 if (rval != QLA_SUCCESS) {
83548fe2 6427 ql_dbg(ql_dbg_mbx, vha, 0x1018,
15f30a57
QT		 6428 "%s: %s Failed submission. %x.\n",
6429 __func__, sp->name, rval);
6430 goto done_free_sp;
6431 }
6432
83548fe2 6433 ql_dbg(ql_dbg_mbx, vha, 0x113f, "MB:%s hndl %x submitted\n",
15f30a57
QT		 6434 sp->name, sp->handle);
6435
6436 wait_for_completion(&c->u.mbx.comp);
6437 memcpy(mcp->mb, sp->u.iocb_cmd.u.mbx.in_mb, SIZEOF_IOCB_MB_REG);
6438
6439 rval = c->u.mbx.rc;
6440 switch (rval) {
6441 case QLA_FUNCTION_TIMEOUT:
83548fe2 6442 ql_dbg(ql_dbg_mbx, vha, 0x1140, "%s: %s Timeout. %x.\n",
15f30a57
QT		 6443 __func__, sp->name, rval);
6444 break;
6445 case QLA_SUCCESS:
83548fe2 6446 ql_dbg(ql_dbg_mbx, vha, 0x119d, "%s: %s done.\n",
15f30a57 6447 __func__, sp->name);
15f30a57
QT		 6448 break;
6449 default:
83548fe2 6450 ql_dbg(ql_dbg_mbx, vha, 0x119e, "%s: %s Failed. %x.\n",
15f30a57 6451 __func__, sp->name, rval);
15f30a57
QT		 6452 break;
6453 }
6454
15f30a57
QT		 6455done_free_sp:
6456 sp->free(sp);
6457done:
6458 return rval;
6459}
6460
6461/*
6462 * qla24xx_gpdb_wait
6463 * NOTE: Do not call this routine from DPC thread
6464 */
6465int qla24xx_gpdb_wait(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt)
6466{
6467 int rval = QLA_FUNCTION_FAILED;
6468 dma_addr_t pd_dma;
6469 struct port_database_24xx *pd;
6470 struct qla_hw_data *ha = vha->hw;
6471 mbx_cmd_t mc;
6472
6473 if (!vha->hw->flags.fw_started)
6474 goto done;
6475
08eb7f45 6476 pd = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
15f30a57 6477 if (pd == NULL) {
83548fe2
QT		 6478 ql_log(ql_log_warn, vha, 0xd047,
6479 "Failed to allocate port database structure.\n");
15f30a57
QT		 6480 goto done_free_sp;
6481 }
15f30a57
QT		 6482
6483 memset(&mc, 0, sizeof(mc));
6484 mc.mb[0] = MBC_GET_PORT_DATABASE;
7ffa5b93 6485 mc.mb[1] = fcport->loop_id;
15f30a57
QT		 6486 mc.mb[2] = MSW(pd_dma);
6487 mc.mb[3] = LSW(pd_dma);
6488 mc.mb[6] = MSW(MSD(pd_dma));
6489 mc.mb[7] = LSW(MSD(pd_dma));
7ffa5b93
BVA		 6490 mc.mb[9] = vha->vp_idx;
6491 mc.mb[10] = opt;
15f30a57
QT		 6492
6493 rval = qla24xx_send_mb_cmd(vha, &mc);
6494 if (rval != QLA_SUCCESS) {
83548fe2 6495 ql_dbg(ql_dbg_mbx, vha, 0x1193,
15f30a57
QT		 6496 "%s: %8phC fail\n", __func__, fcport->port_name);
6497 goto done_free_sp;
6498 }
6499
6500 rval = __qla24xx_parse_gpdb(vha, fcport, pd);
6501
83548fe2 6502 ql_dbg(ql_dbg_mbx, vha, 0x1197, "%s: %8phC done\n",
15f30a57
QT		 6503 __func__, fcport->port_name);
6504
6505done_free_sp:
6506 if (pd)
6507 dma_pool_free(ha->s_dma_pool, pd, pd_dma);
6508done:
6509 return rval;
6510}
6511
6512int __qla24xx_parse_gpdb(struct scsi_qla_host *vha, fc_port_t *fcport,
6513 struct port_database_24xx *pd)
6514{
6515 int rval = QLA_SUCCESS;
6516 uint64_t zero = 0;
a5d42f4c
DG		 6517 u8 current_login_state, last_login_state;
6518
84ed362a 6519 if (NVME_TARGET(vha->hw, fcport)) {
a5d42f4c
DG		 6520 current_login_state = pd->current_login_state >> 4;
6521 last_login_state = pd->last_login_state >> 4;
6522 } else {
6523 current_login_state = pd->current_login_state & 0xf;
6524 last_login_state = pd->last_login_state & 0xf;
6525 }
15f30a57
QT		 6526
6527 /* Check for logged in state. */
23c64559 6528 if (current_login_state != PDS_PRLI_COMPLETE) {
83548fe2
QT		 6529 ql_dbg(ql_dbg_mbx, vha, 0x119a,
6530 "Unable to verify login-state (%x/%x) for loop_id %x.\n",
a5d42f4c 6531 current_login_state, last_login_state, fcport->loop_id);
15f30a57
QT		 6532 rval = QLA_FUNCTION_FAILED;
6533 goto gpd_error_out;
6534 }
6535
6536 if (fcport->loop_id == FC_NO_LOOP_ID ||
6537 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
6538 memcmp(fcport->port_name, pd->port_name, 8))) {
6539 /* We lost the device mid way. */
6540 rval = QLA_NOT_LOGGED_IN;
6541 goto gpd_error_out;
6542 }
6543
6544 /* Names are little-endian. */
6545 memcpy(fcport->node_name, pd->node_name, WWN_SIZE);
6546 memcpy(fcport->port_name, pd->port_name, WWN_SIZE);
6547
6548 /* Get port_id of device. */
6549 fcport->d_id.b.domain = pd->port_id[0];
6550 fcport->d_id.b.area = pd->port_id[1];
6551 fcport->d_id.b.al_pa = pd->port_id[2];
6552 fcport->d_id.b.rsvd_1 = 0;
6553
84ed362a
MH		 6554 if (NVME_TARGET(vha->hw, fcport)) {
6555 fcport->port_type = FCT_NVME;
a6a6d058
HR		 6556 if ((pd->prli_svc_param_word_3[0] & BIT_5) == 0)
6557 fcport->port_type |= FCT_NVME_INITIATOR;
6558 if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0)
6559 fcport->port_type |= FCT_NVME_TARGET;
6560 if ((pd->prli_svc_param_word_3[0] & BIT_3) == 0)
6561 fcport->port_type |= FCT_NVME_DISCOVERY;
a5d42f4c
DG		 6562 } else {
6563 /* If not target must be initiator or unknown type. */
6564 if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0)
6565 fcport->port_type = FCT_INITIATOR;
6566 else
6567 fcport->port_type = FCT_TARGET;
6568 }
15f30a57
QT		 6569 /* Passback COS information. */
6570 fcport->supported_classes = (pd->flags & PDF_CLASS_2) ?
6571 FC_COS_CLASS2 : FC_COS_CLASS3;
6572
6573 if (pd->prli_svc_param_word_3[0] & BIT_7) {
6574 fcport->flags |= FCF_CONF_COMP_SUPPORTED;
6575 fcport->conf_compl_supported = 1;
6576 }
6577
6578gpd_error_out:
6579 return rval;
6580}
6581
6582/*
6583 * qla24xx_gidlist__wait
6584 * NOTE: don't call this routine from DPC thread.
6585 */
6586int qla24xx_gidlist_wait(struct scsi_qla_host *vha,
6587 void *id_list, dma_addr_t id_list_dma, uint16_t *entries)
6588{
6589 int rval = QLA_FUNCTION_FAILED;
6590 mbx_cmd_t mc;
6591
6592 if (!vha->hw->flags.fw_started)
6593 goto done;
6594
6595 memset(&mc, 0, sizeof(mc));
6596 mc.mb[0] = MBC_GET_ID_LIST;
6597 mc.mb[2] = MSW(id_list_dma);
6598 mc.mb[3] = LSW(id_list_dma);
6599 mc.mb[6] = MSW(MSD(id_list_dma));
6600 mc.mb[7] = LSW(MSD(id_list_dma));
6601 mc.mb[8] = 0;
7ffa5b93 6602 mc.mb[9] = vha->vp_idx;
15f30a57
QT		 6603
6604 rval = qla24xx_send_mb_cmd(vha, &mc);
6605 if (rval != QLA_SUCCESS) {
83548fe2
QT		 6606 ql_dbg(ql_dbg_mbx, vha, 0x119b,
6607 "%s: fail\n", __func__);
15f30a57
QT		 6608 } else {
6609 *entries = mc.mb[1];
83548fe2
QT		 6610 ql_dbg(ql_dbg_mbx, vha, 0x119c,
6611 "%s: done\n", __func__);
15f30a57
QT		 6612 }
6613done:
6614 return rval;
6615}
deeae7a6
DG		 6616
6617int qla27xx_set_zio_threshold(scsi_qla_host_t *vha, uint16_t value)
6618{
6619 int rval;
6620 mbx_cmd_t mc;
6621 mbx_cmd_t *mcp = &mc;
6622
6623 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1200,
6624 "Entered %s\n", __func__);
6625
6626 memset(mcp->mb, 0 , sizeof(mcp->mb));
6627 mcp->mb[0] = MBC_GET_SET_ZIO_THRESHOLD;
7ffa5b93
BVA		 6628 mcp->mb[1] = 1;
6629 mcp->mb[2] = value;
deeae7a6
DG		 6630 mcp->out_mb = MBX_2 | MBX_1 | MBX_0;
6631 mcp->in_mb = MBX_2 | MBX_0;
6632 mcp->tov = MBX_TOV_SECONDS;
6633 mcp->flags = 0;
6634
6635 rval = qla2x00_mailbox_command(vha, mcp);
6636
6637 ql_dbg(ql_dbg_mbx, vha, 0x1201, "%s %x\n",
6638 (rval != QLA_SUCCESS) ? "Failed" : "Done", rval);
6639
6640 return rval;
6641}
6642
6643int qla27xx_get_zio_threshold(scsi_qla_host_t *vha, uint16_t *value)
6644{
6645 int rval;
6646 mbx_cmd_t mc;
6647 mbx_cmd_t *mcp = &mc;
6648
6649 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1203,
6650 "Entered %s\n", __func__);
6651
6652 memset(mcp->mb, 0, sizeof(mcp->mb));
6653 mcp->mb[0] = MBC_GET_SET_ZIO_THRESHOLD;
7ffa5b93 6654 mcp->mb[1] = 0;
deeae7a6
DG		 6655 mcp->out_mb = MBX_1 | MBX_0;
6656 mcp->in_mb = MBX_2 | MBX_0;
6657 mcp->tov = MBX_TOV_SECONDS;
6658 mcp->flags = 0;
6659
6660 rval = qla2x00_mailbox_command(vha, mcp);
6661 if (rval == QLA_SUCCESS)
6662 *value = mc.mb[2];
6663
6664 ql_dbg(ql_dbg_mbx, vha, 0x1205, "%s %x\n",
6665 (rval != QLA_SUCCESS) ? "Failed" : "Done", rval);
6666
6667 return rval;
6668}
e4e3a2ce
QT		 6669
6670int
6671qla2x00_read_sfp_dev(struct scsi_qla_host *vha, char *buf, int count)
6672{
6673 struct qla_hw_data *ha = vha->hw;
6674 uint16_t iter, addr, offset;
6675 dma_addr_t phys_addr;
6676 int rval, c;
6677 u8 *sfp_data;
6678
6679 memset(ha->sfp_data, 0, SFP_DEV_SIZE);
6680 addr = 0xa0;
6681 phys_addr = ha->sfp_data_dma;
6682 sfp_data = ha->sfp_data;
6683 offset = c = 0;
6684
6685 for (iter = 0; iter < SFP_DEV_SIZE / SFP_BLOCK_SIZE; iter++) {
6686 if (iter == 4) {
6687 /* Skip to next device address. */
6688 addr = 0xa2;
6689 offset = 0;
6690 }
6691
6692 rval = qla2x00_read_sfp(vha, phys_addr, sfp_data,
6693 addr, offset, SFP_BLOCK_SIZE, BIT_1);
6694 if (rval != QLA_SUCCESS) {
6695 ql_log(ql_log_warn, vha, 0x706d,
6696 "Unable to read SFP data (%x/%x/%x).\n", rval,
6697 addr, offset);
6698
6699 return rval;
6700 }
6701
6702 if (buf && (c < count)) {
6703 u16 sz;
6704
6705 if ((count - c) >= SFP_BLOCK_SIZE)
6706 sz = SFP_BLOCK_SIZE;
6707 else
6708 sz = count - c;
6709
6710 memcpy(buf, sfp_data, sz);
6711 buf += SFP_BLOCK_SIZE;
6712 c += sz;
6713 }
6714 phys_addr += SFP_BLOCK_SIZE;
6715 sfp_data += SFP_BLOCK_SIZE;
6716 offset += SFP_BLOCK_SIZE;
6717 }
6718
6719 return rval;
6720}
94d83e36
QT		 6721
6722int qla24xx_res_count_wait(struct scsi_qla_host *vha,
6723 uint16_t *out_mb, int out_mb_sz)
6724{
6725 int rval = QLA_FUNCTION_FAILED;
6726 mbx_cmd_t mc;
6727
6728 if (!vha->hw->flags.fw_started)
6729 goto done;
6730
6731 memset(&mc, 0, sizeof(mc));
6732 mc.mb[0] = MBC_GET_RESOURCE_COUNTS;
6733
6734 rval = qla24xx_send_mb_cmd(vha, &mc);
6735 if (rval != QLA_SUCCESS) {
6736 ql_dbg(ql_dbg_mbx, vha, 0xffff,
6737 "%s: fail\n", __func__);
6738 } else {
6739 if (out_mb_sz <= SIZEOF_IOCB_MB_REG)
6740 memcpy(out_mb, mc.mb, out_mb_sz);
6741 else
6742 memcpy(out_mb, mc.mb, SIZEOF_IOCB_MB_REG);
6743
6744 ql_dbg(ql_dbg_mbx, vha, 0xffff,
6745 "%s: done\n", __func__);
6746 }
6747done:
6748 return rval;
6749}
3f006ac3
MH		 6750
6751int qla28xx_secure_flash_update(scsi_qla_host_t *vha, uint16_t opts,
6752 uint16_t region, uint32_t len, dma_addr_t sfub_dma_addr,
6753 uint32_t sfub_len)
6754{
6755 int rval;
6756 mbx_cmd_t mc;
6757 mbx_cmd_t *mcp = &mc;
6758
6759 mcp->mb[0] = MBC_SECURE_FLASH_UPDATE;
6760 mcp->mb[1] = opts;
6761 mcp->mb[2] = region;
6762 mcp->mb[3] = MSW(len);
6763 mcp->mb[4] = LSW(len);
6764 mcp->mb[5] = MSW(sfub_dma_addr);
6765 mcp->mb[6] = LSW(sfub_dma_addr);
6766 mcp->mb[7] = MSW(MSD(sfub_dma_addr));
6767 mcp->mb[8] = LSW(MSD(sfub_dma_addr));
6768 mcp->mb[9] = sfub_len;
6769 mcp->out_mb =
6770 MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
6771 mcp->in_mb = MBX_2|MBX_1|MBX_0;
6772 mcp->tov = MBX_TOV_SECONDS;
6773 mcp->flags = 0;
6774 rval = qla2x00_mailbox_command(vha, mcp);
6775
6776 if (rval != QLA_SUCCESS) {
6777 ql_dbg(ql_dbg_mbx, vha, 0xffff, "%s(%ld): failed rval 0x%x, %x %x %x",
6778 __func__, vha->host_no, rval, mcp->mb[0], mcp->mb[1],
6779 mcp->mb[2]);
6780 }
6781
6782 return rval;
6783}
6784
6785int qla2xxx_write_remote_register(scsi_qla_host_t *vha, uint32_t addr,
6786 uint32_t data)
6787{
6788 int rval;
6789 mbx_cmd_t mc;
6790 mbx_cmd_t *mcp = &mc;
6791
6792 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e8,
6793 "Entered %s.\n", __func__);
6794
6795 mcp->mb[0] = MBC_WRITE_REMOTE_REG;
6796 mcp->mb[1] = LSW(addr);
6797 mcp->mb[2] = MSW(addr);
6798 mcp->mb[3] = LSW(data);
6799 mcp->mb[4] = MSW(data);
6800 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
6801 mcp->in_mb = MBX_1|MBX_0;
6802 mcp->tov = MBX_TOV_SECONDS;
6803 mcp->flags = 0;
6804 rval = qla2x00_mailbox_command(vha, mcp);
6805
6806 if (rval != QLA_SUCCESS) {
6807 ql_dbg(ql_dbg_mbx, vha, 0x10e9,
6808 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
6809 } else {
6810 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea,
6811 "Done %s.\n", __func__);
6812 }
6813
6814 return rval;
6815}
6816
6817int qla2xxx_read_remote_register(scsi_qla_host_t *vha, uint32_t addr,
6818 uint32_t *data)
6819{
6820 int rval;
6821 mbx_cmd_t mc;
6822 mbx_cmd_t *mcp = &mc;
6823
6824 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e8,
6825 "Entered %s.\n", __func__);
6826
6827 mcp->mb[0] = MBC_READ_REMOTE_REG;
6828 mcp->mb[1] = LSW(addr);
6829 mcp->mb[2] = MSW(addr);
6830 mcp->out_mb = MBX_2|MBX_1|MBX_0;
6831 mcp->in_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
6832 mcp->tov = MBX_TOV_SECONDS;
6833 mcp->flags = 0;
6834 rval = qla2x00_mailbox_command(vha, mcp);
6835
6836 *data = (uint32_t)((((uint32_t)mcp->mb[4]) << 16) | mcp->mb[3]);
6837
6838 if (rval != QLA_SUCCESS) {
6839 ql_dbg(ql_dbg_mbx, vha, 0x10e9,
6840 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
6841 } else {
6842 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea,
6843 "Done %s.\n", __func__);
6844 }
6845
6846 return rval;
6847}
07553b1e
JC		 6848
6849int
6850ql26xx_led_config(scsi_qla_host_t *vha, uint16_t options, uint16_t *led)
6851{
6852 struct qla_hw_data *ha = vha->hw;
6853 mbx_cmd_t mc;
6854 mbx_cmd_t *mcp = &mc;
6855 int rval;
6856
6857 if (!IS_QLA2031(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
6858 return QLA_FUNCTION_FAILED;
6859
6860 ql_dbg(ql_dbg_mbx, vha, 0x7070, "Entered %s (options=%x).\n",
6861 __func__, options);
6862
6863 mcp->mb[0] = MBC_SET_GET_FC_LED_CONFIG;
6864 mcp->mb[1] = options;
6865 mcp->out_mb = MBX_1|MBX_0;
6866 mcp->in_mb = MBX_1|MBX_0;
6867 if (options & BIT_0) {
6868 if (options & BIT_1) {
6869 mcp->mb[2] = led[2];
6870 mcp->out_mb |= MBX_2;
6871 }
6872 if (options & BIT_2) {
6873 mcp->mb[3] = led[0];
6874 mcp->out_mb |= MBX_3;
6875 }
6876 if (options & BIT_3) {
6877 mcp->mb[4] = led[1];
6878 mcp->out_mb |= MBX_4;
6879 }
6880 } else {
6881 mcp->in_mb |= MBX_4|MBX_3|MBX_2;
6882 }
6883 mcp->tov = MBX_TOV_SECONDS;
6884 mcp->flags = 0;
6885 rval = qla2x00_mailbox_command(vha, mcp);
6886 if (rval) {
6887 ql_dbg(ql_dbg_mbx, vha, 0x7071, "Failed %s %x (mb=%x,%x)\n",
6888 __func__, rval, mcp->mb[0], mcp->mb[1]);
6889 return rval;
6890 }
6891
6892 if (options & BIT_0) {
6893 ha->beacon_blink_led = 0;
6894 ql_dbg(ql_dbg_mbx, vha, 0x7072, "Done %s\n", __func__);
6895 } else {
6896 led[2] = mcp->mb[2];
6897 led[0] = mcp->mb[3];
6898 led[1] = mcp->mb[4];
6899 ql_dbg(ql_dbg_mbx, vha, 0x7073, "Done %s (led=%x,%x,%x)\n",
6900 __func__, led[0], led[1], led[2]);
6901 }
6902
6903 return rval;
6904}
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