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qla2xxx: Replace QLA_TGT_STATE_ABORTED with a bit.
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
1da177e4
LT		 16#include <scsi/scsi_tcq.h>
17#include <scsi/scsicam.h>
18#include <scsi/scsi_transport.h>
19#include <scsi/scsi_transport_fc.h>
20
2d70c103
NB		 21#include "qla_target.h"
22
1da177e4
LT		 23/*
24 * Driver version
25 */
26char qla2x00_version_str[40];
27
6a03b4cd
HZ		 28static int apidev_major;
29
1da177e4
LT		 30/*
31 * SRB allocation cache
32 */
e18b890b 33static struct kmem_cache *srb_cachep;
1da177e4 34
a9083016
GM		 35/*
36 * CT6 CTX allocation cache
37 */
38static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 39/*
40 * error level for logging
41 */
42int ql_errlev = ql_log_all;
a9083016 43
fa492630 44static int ql2xenableclass2;
2d70c103
NB		 45module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
46MODULE_PARM_DESC(ql2xenableclass2,
47 "Specify if Class 2 operations are supported from the very "
48 "beginning. Default is 0 - class 2 not supported.");
49
8ae6d9c7 50
1da177e4 51int ql2xlogintimeout = 20;
f2019cb1 52module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 53MODULE_PARM_DESC(ql2xlogintimeout,
54 "Login timeout value in seconds.");
55
a7b61842 56int qlport_down_retry;
f2019cb1 57module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 58MODULE_PARM_DESC(qlport_down_retry,
900d9f98 59 "Maximum number of command retries to a port that returns "
1da177e4
LT		 60 "a PORT-DOWN status.");
61
1da177e4
LT		 62int ql2xplogiabsentdevice;
63module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
64MODULE_PARM_DESC(ql2xplogiabsentdevice,
65 "Option to enable PLOGI to devices that are not present after "
900d9f98 66 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 67 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
68
1da177e4 69int ql2xloginretrycount = 0;
f2019cb1 70module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 71MODULE_PARM_DESC(ql2xloginretrycount,
72 "Specify an alternate value for the NVRAM login retry count.");
73
a7a167bf 74int ql2xallocfwdump = 1;
f2019cb1 75module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 76MODULE_PARM_DESC(ql2xallocfwdump,
77 "Option to enable allocation of memory for a firmware dump "
78 "during HBA initialization. Memory allocation requirements "
79 "vary by ISP type. Default is 1 - allocate memory.");
80
11010fec 81int ql2xextended_error_logging;
27d94035 82module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 83MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 84 "Option to enable extended error logging,\n"
85 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
86 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
87 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
88 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
89 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
90 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
91 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
92 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 93 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
94 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 95 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 96 "\t\t0x1e400000 - Preferred value for capturing essential "
97 "debug information (equivalent to old "
98 "ql2xextended_error_logging=1).\n"
3ce8866c 99 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 100
a9083016 101int ql2xshiftctondsd = 6;
f2019cb1 102module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 103MODULE_PARM_DESC(ql2xshiftctondsd,
104 "Set to control shifting of command type processing "
105 "based on total number of SG elements.");
106
7e47e5ca 107int ql2xfdmienable=1;
de187df8 108module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
cca5335c 109MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 110 "Enables FDMI registrations. "
111 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 112
50280c01
CD		 113#define MAX_Q_DEPTH 32
114static int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 115module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
116MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f
CD		 117 "Maximum queue depth to set for each LUN. "
118 "Default is 32.");
df7baa50 119
9e522cd8
AE		 120int ql2xenabledif = 2;
121module_param(ql2xenabledif, int, S_IRUGO);
bad75002 122MODULE_PARM_DESC(ql2xenabledif,
b97f5d0b
SM		 123 " Enable T10-CRC-DIF:\n"
124 " Default is 2.\n"
125 " 0 -- No DIF Support\n"
126 " 1 -- Enable DIF for all types\n"
127 " 2 -- Enable DIF for all types, except Type 0.\n");
bad75002 128
8cb2049c 129int ql2xenablehba_err_chk = 2;
bad75002
AE		 130module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
131MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c 132 " Enable T10-CRC-DIF Error isolation by HBA:\n"
b97f5d0b 133 " Default is 2.\n"
8cb2049c
AE		 134 " 0 -- Error isolation disabled\n"
135 " 1 -- Error isolation enabled only for DIX Type 0\n"
136 " 2 -- Error isolation enabled for all Types\n");
bad75002 137
e5896bd5 138int ql2xiidmaenable=1;
f2019cb1 139module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 140MODULE_PARM_DESC(ql2xiidmaenable,
141 "Enables iIDMA settings "
142 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
143
73208dfd 144int ql2xmaxqueues = 1;
f2019cb1 145module_param(ql2xmaxqueues, int, S_IRUGO);
73208dfd
AC		 146MODULE_PARM_DESC(ql2xmaxqueues,
147 "Enables MQ settings "
ae68230c
JP		 148 "Default is 1 for single queue. Set it to number "
149 "of queues in MQ mode.");
68ca949c
AC		 150
151int ql2xmultique_tag;
f2019cb1 152module_param(ql2xmultique_tag, int, S_IRUGO);
68ca949c
AC		 153MODULE_PARM_DESC(ql2xmultique_tag,
154 "Enables CPU affinity settings for the driver "
155 "Default is 0 for no affinity of request and response IO. "
156 "Set it to 1 to turn on the cpu affinity.");
e337d907
AV		 157
158int ql2xfwloadbin;
86e45bf6 159module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 160MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 161 "Option to specify location from which to load ISP firmware:.\n"
162 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 163 " interface.\n"
164 " 1 -- load firmware from flash.\n"
165 " 0 -- use default semantics.\n");
166
ae97c91e 167int ql2xetsenable;
f2019cb1 168module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 169MODULE_PARM_DESC(ql2xetsenable,
170 "Enables firmware ETS burst."
171 "Default is 0 - skip ETS enablement.");
172
6907869d 173int ql2xdbwr = 1;
86e45bf6 174module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 175MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 176 "Option to specify scheme for request queue posting.\n"
177 " 0 -- Regular doorbell.\n"
178 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 179
f4c496c1 180int ql2xtargetreset = 1;
f2019cb1 181module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 182MODULE_PARM_DESC(ql2xtargetreset,
183 "Enable target reset."
184 "Default is 1 - use hw defaults.");
185
4da26e16 186int ql2xgffidenable;
f2019cb1 187module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 188MODULE_PARM_DESC(ql2xgffidenable,
189 "Enables GFF_ID checks of port type. "
190 "Default is 0 - Do not use GFF_ID information.");
a9083016 191
3822263e 192int ql2xasynctmfenable;
f2019cb1 193module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 194MODULE_PARM_DESC(ql2xasynctmfenable,
195 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
196 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 197
198int ql2xdontresethba;
86e45bf6 199module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 200MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 201 "Option to specify reset behaviour.\n"
202 " 0 (Default) -- Reset on failure.\n"
203 " 1 -- Do not reset on failure.\n");
ed0de87c 204
1abf635d
HR		 205uint64_t ql2xmaxlun = MAX_LUNS;
206module_param(ql2xmaxlun, ullong, S_IRUGO);
82515920
AV		 207MODULE_PARM_DESC(ql2xmaxlun,
208 "Defines the maximum LU number to register with the SCSI "
209 "midlayer. Default is 65535.");
210
08de2844
GM		 211int ql2xmdcapmask = 0x1F;
212module_param(ql2xmdcapmask, int, S_IRUGO);
213MODULE_PARM_DESC(ql2xmdcapmask,
214 "Set the Minidump driver capture mask level. "
6e96fa7b 215 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 216
3aadff35 217int ql2xmdenable = 1;
08de2844
GM		 218module_param(ql2xmdenable, int, S_IRUGO);
219MODULE_PARM_DESC(ql2xmdenable,
220 "Enable/disable MiniDump. "
3aadff35
GM		 221 "0 - MiniDump disabled. "
222 "1 (Default) - MiniDump enabled.");
08de2844 223
b0d6cabd
HM		 224int ql2xexlogins = 0;
225module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
226MODULE_PARM_DESC(ql2xexlogins,
227 "Number of extended Logins. "
228 "0 (Default)- Disabled.");
229
2f56a7f1
HM		 230int ql2xexchoffld = 0;
231module_param(ql2xexchoffld, uint, S_IRUGO|S_IWUSR);
232MODULE_PARM_DESC(ql2xexchoffld,
233 "Number of exchanges to offload. "
234 "0 (Default)- Disabled.");
235
1da177e4 236/*
fa2a1ce5 237 * SCSI host template entry points
1da177e4
LT		 238 */
239static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 240static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 241static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
242static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 243static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 244static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 245static int qla2xxx_eh_abort(struct scsi_cmnd *);
246static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 247static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 248static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
249static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 250
1a2fbf18 251static void qla2x00_clear_drv_active(struct qla_hw_data *);
3491255e 252static void qla2x00_free_device(scsi_qla_host_t *);
2d5a4c34 253static void qla83xx_disable_laser(scsi_qla_host_t *vha);
ce7e4af7 254
a5326f86 255struct scsi_host_template qla2xxx_driver_template = {
1da177e4 256 .module = THIS_MODULE,
cb63067a 257 .name = QLA2XXX_DRIVER_NAME,
a5326f86 258 .queuecommand = qla2xxx_queuecommand,
fca29703
AV		 259
260 .eh_abort_handler = qla2xxx_eh_abort,
261 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 262 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 263 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
264 .eh_host_reset_handler = qla2xxx_eh_host_reset,
265
266 .slave_configure = qla2xxx_slave_configure,
267
268 .slave_alloc = qla2xxx_slave_alloc,
269 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 270 .scan_finished = qla2xxx_scan_finished,
271 .scan_start = qla2xxx_scan_start,
db5ed4df 272 .change_queue_depth = scsi_change_queue_depth,
fca29703
AV		 273 .this_id = -1,
274 .cmd_per_lun = 3,
275 .use_clustering = ENABLE_CLUSTERING,
276 .sg_tablesize = SG_ALL,
277
278 .max_sectors = 0xFFFF,
afb046e2 279 .shost_attrs = qla2x00_host_attrs,
2d70c103
NB		 280
281 .supported_mode = MODE_INITIATOR,
c40ecc12 282 .track_queue_depth = 1,
fca29703
AV		 283};
284
1da177e4 285static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 286struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 287
1da177e4
LT		 288/* TODO Convert to inlines
289 *
290 * Timer routines
291 */
1da177e4 292
2c3dfe3f 293__inline__ void
e315cd28 294qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
1da177e4 295{
e315cd28
AC		 296 init_timer(&vha->timer);
297 vha->timer.expires = jiffies + interval * HZ;
298 vha->timer.data = (unsigned long)vha;
299 vha->timer.function = (void (*)(unsigned long))func;
300 add_timer(&vha->timer);
301 vha->timer_active = 1;
1da177e4
LT		 302}
303
304static inline void
e315cd28 305qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 306{
a9083016 307 /* Currently used for 82XX only. */
7c3df132
SK		 308 if (vha->device_flags & DFLG_DEV_FAILED) {
309 ql_dbg(ql_dbg_timer, vha, 0x600d,
310 "Device in a failed state, returning.\n");
a9083016 311 return;
7c3df132 312 }
a9083016 313
e315cd28 314 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 315}
316
a824ebb3 317static __inline__ void
e315cd28 318qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 319{
e315cd28
AC		 320 del_timer_sync(&vha->timer);
321 vha->timer_active = 0;
1da177e4
LT		 322}
323
1da177e4
LT		 324static int qla2x00_do_dpc(void *data);
325
326static void qla2x00_rst_aen(scsi_qla_host_t *);
327
73208dfd
AC		 328static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
329 struct req_que **, struct rsp_que **);
e30d1756 330static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 331static void qla2x00_mem_free(struct qla_hw_data *);
1da177e4 332
1da177e4 333/* -------------------------------------------------------------------------- */
9a347ff4
CD		 334static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
335 struct rsp_que *rsp)
73208dfd 336{
7c3df132 337 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2afa19a9 338 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
73208dfd
AC		 339 GFP_KERNEL);
340 if (!ha->req_q_map) {
7c3df132
SK		 341 ql_log(ql_log_fatal, vha, 0x003b,
342 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 343 goto fail_req_map;
344 }
345
2afa19a9 346 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
73208dfd
AC		 347 GFP_KERNEL);
348 if (!ha->rsp_q_map) {
7c3df132
SK		 349 ql_log(ql_log_fatal, vha, 0x003c,
350 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 351 goto fail_rsp_map;
352 }
9a347ff4
CD		 353 /*
354 * Make sure we record at least the request and response queue zero in
355 * case we need to free them if part of the probe fails.
356 */
357 ha->rsp_q_map[0] = rsp;
358 ha->req_q_map[0] = req;
73208dfd
AC		 359 set_bit(0, ha->rsp_qid_map);
360 set_bit(0, ha->req_qid_map);
361 return 1;
362
363fail_rsp_map:
364 kfree(ha->req_q_map);
365 ha->req_q_map = NULL;
366fail_req_map:
367 return -ENOMEM;
368}
369
2afa19a9 370static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 371{
8ae6d9c7
GM		 372 if (IS_QLAFX00(ha)) {
373 if (req && req->ring_fx00)
374 dma_free_coherent(&ha->pdev->dev,
375 (req->length_fx00 + 1) * sizeof(request_t),
376 req->ring_fx00, req->dma_fx00);
377 } else if (req && req->ring)
73208dfd
AC		 378 dma_free_coherent(&ha->pdev->dev,
379 (req->length + 1) * sizeof(request_t),
380 req->ring, req->dma);
381
8d93f550
CD		 382 if (req)
383 kfree(req->outstanding_cmds);
384
73208dfd
AC		 385 kfree(req);
386 req = NULL;
387}
388
2afa19a9
AC		 389static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
390{
8ae6d9c7
GM		 391 if (IS_QLAFX00(ha)) {
392 if (rsp && rsp->ring)
393 dma_free_coherent(&ha->pdev->dev,
394 (rsp->length_fx00 + 1) * sizeof(request_t),
395 rsp->ring_fx00, rsp->dma_fx00);
396 } else if (rsp && rsp->ring) {
2afa19a9
AC		 397 dma_free_coherent(&ha->pdev->dev,
398 (rsp->length + 1) * sizeof(response_t),
399 rsp->ring, rsp->dma);
8ae6d9c7 400 }
2afa19a9
AC		 401 kfree(rsp);
402 rsp = NULL;
403}
404
73208dfd
AC		 405static void qla2x00_free_queues(struct qla_hw_data *ha)
406{
407 struct req_que *req;
408 struct rsp_que *rsp;
409 int cnt;
410
2afa19a9 411 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
73208dfd 412 req = ha->req_q_map[cnt];
2afa19a9 413 qla2x00_free_req_que(ha, req);
73208dfd 414 }
73208dfd
AC		 415 kfree(ha->req_q_map);
416 ha->req_q_map = NULL;
2afa19a9
AC		 417
418 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
419 rsp = ha->rsp_q_map[cnt];
420 qla2x00_free_rsp_que(ha, rsp);
421 }
422 kfree(ha->rsp_q_map);
423 ha->rsp_q_map = NULL;
73208dfd
AC		 424}
425
68ca949c
AC		 426static int qla25xx_setup_mode(struct scsi_qla_host *vha)
427{
428 uint16_t options = 0;
429 int ques, req, ret;
430 struct qla_hw_data *ha = vha->hw;
431
7163ea81 432 if (!(ha->fw_attributes & BIT_6)) {
7c3df132
SK		 433 ql_log(ql_log_warn, vha, 0x00d8,
434 "Firmware is not multi-queue capable.\n");
7163ea81
AC		 435 goto fail;
436 }
68ca949c 437 if (ql2xmultique_tag) {
68ca949c
AC		 438 /* create a request queue for IO */
439 options |= BIT_7;
440 req = qla25xx_create_req_que(ha, options, 0, 0, -1,
441 QLA_DEFAULT_QUE_QOS);
442 if (!req) {
7c3df132
SK		 443 ql_log(ql_log_warn, vha, 0x00e0,
444 "Failed to create request queue.\n");
68ca949c
AC		 445 goto fail;
446 }
278274d5 447 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
68ca949c
AC		 448 vha->req = ha->req_q_map[req];
449 options |= BIT_1;
450 for (ques = 1; ques < ha->max_rsp_queues; ques++) {
451 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
452 if (!ret) {
7c3df132
SK		 453 ql_log(ql_log_warn, vha, 0x00e8,
454 "Failed to create response queue.\n");
68ca949c
AC		 455 goto fail2;
456 }
457 }
7163ea81 458 ha->flags.cpu_affinity_enabled = 1;
7c3df132 459 ql_dbg(ql_dbg_multiq, vha, 0xc007,
6ef68da7 460 "CPU affinity mode enabled, "
7c3df132
SK		 461 "no. of response queues:%d no. of request queues:%d.\n",
462 ha->max_rsp_queues, ha->max_req_queues);
463 ql_dbg(ql_dbg_init, vha, 0x00e9,
6ef68da7 464 "CPU affinity mode enabled, "
7c3df132
SK		 465 "no. of response queues:%d no. of request queues:%d.\n",
466 ha->max_rsp_queues, ha->max_req_queues);
68ca949c
AC		 467 }
468 return 0;
469fail2:
470 qla25xx_delete_queues(vha);
7163ea81
AC		 471 destroy_workqueue(ha->wq);
472 ha->wq = NULL;
0cd33fcf 473 vha->req = ha->req_q_map[0];
68ca949c
AC		 474fail:
475 ha->mqenable = 0;
7163ea81
AC		 476 kfree(ha->req_q_map);
477 kfree(ha->rsp_q_map);
478 ha->max_req_queues = ha->max_rsp_queues = 1;
68ca949c
AC		 479 return 1;
480}
481
1da177e4 482static char *
e315cd28 483qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 484{
e315cd28 485 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 486 static char *pci_bus_modes[] = {
487 "33", "66", "100", "133",
488 };
489 uint16_t pci_bus;
490
491 strcpy(str, "PCI");
492 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
493 if (pci_bus) {
494 strcat(str, "-X (");
495 strcat(str, pci_bus_modes[pci_bus]);
496 } else {
497 pci_bus = (ha->pci_attr & BIT_8) >> 8;
498 strcat(str, " (");
499 strcat(str, pci_bus_modes[pci_bus]);
500 }
501 strcat(str, " MHz)");
502
503 return (str);
504}
505
fca29703 506static char *
e315cd28 507qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 508{
509 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 510 struct qla_hw_data *ha = vha->hw;
fca29703 511 uint32_t pci_bus;
fca29703 512
62a276f8 513 if (pci_is_pcie(ha->pdev)) {
fca29703 514 char lwstr[6];
62a276f8 515 uint32_t lstat, lspeed, lwidth;
fca29703 516
62a276f8
BH		 517 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
518 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
519 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
fca29703
AV		 520
521 strcpy(str, "PCIe (");
49300af7
SK		 522 switch (lspeed) {
523 case 1:
c87a0d8c 524 strcat(str, "2.5GT/s ");
49300af7
SK		 525 break;
526 case 2:
c87a0d8c 527 strcat(str, "5.0GT/s ");
49300af7
SK		 528 break;
529 case 3:
530 strcat(str, "8.0GT/s ");
531 break;
532 default:
fca29703 533 strcat(str, "<unknown> ");
49300af7
SK		 534 break;
535 }
fca29703
AV		 536 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
537 strcat(str, lwstr);
538
539 return str;
540 }
541
542 strcpy(str, "PCI");
543 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
544 if (pci_bus == 0 || pci_bus == 8) {
545 strcat(str, " (");
546 strcat(str, pci_bus_modes[pci_bus >> 3]);
547 } else {
548 strcat(str, "-X ");
549 if (pci_bus & BIT_2)
550 strcat(str, "Mode 2");
551 else
552 strcat(str, "Mode 1");
553 strcat(str, " (");
554 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
555 }
556 strcat(str, " MHz)");
557
558 return str;
559}
560
e5f82ab8 561static char *
df57caba 562qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
1da177e4
LT		 563{
564 char un_str[10];
e315cd28 565 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 566
df57caba
HM		 567 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
568 ha->fw_minor_version, ha->fw_subminor_version);
1da177e4
LT		 569
570 if (ha->fw_attributes & BIT_9) {
571 strcat(str, "FLX");
572 return (str);
573 }
574
575 switch (ha->fw_attributes & 0xFF) {
576 case 0x7:
577 strcat(str, "EF");
578 break;
579 case 0x17:
580 strcat(str, "TP");
581 break;
582 case 0x37:
583 strcat(str, "IP");
584 break;
585 case 0x77:
586 strcat(str, "VI");
587 break;
588 default:
589 sprintf(un_str, "(%x)", ha->fw_attributes);
590 strcat(str, un_str);
591 break;
592 }
593 if (ha->fw_attributes & 0x100)
594 strcat(str, "X");
595
596 return (str);
597}
598
e5f82ab8 599static char *
df57caba 600qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
fca29703 601{
e315cd28 602 struct qla_hw_data *ha = vha->hw;
f0883ac6 603
df57caba 604 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
3a03eb79 605 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 606 return str;
fca29703
AV		 607}
608
9ba56b95
GM		 609void
610qla2x00_sp_free_dma(void *vha, void *ptr)
fca29703 611{
9ba56b95
GM		 612 srb_t *sp = (srb_t *)ptr;
613 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
614 struct qla_hw_data *ha = sp->fcport->vha->hw;
615 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 616
9ba56b95
GM		 617 if (sp->flags & SRB_DMA_VALID) {
618 scsi_dma_unmap(cmd);
619 sp->flags &= ~SRB_DMA_VALID;
7c3df132 620 }
fca29703 621
9ba56b95
GM		 622 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
623 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
624 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
625 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
626 }
627
628 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
629 /* List assured to be having elements */
f83adb61 630 qla2x00_clean_dsd_pool(ha, sp, NULL);
9ba56b95
GM		 631 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
632 }
633
634 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
635 dma_pool_free(ha->dl_dma_pool, ctx,
636 ((struct crc_context *)ctx)->crc_ctx_dma);
637 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
638 }
639
640 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
641 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
fca29703 642
9ba56b95
GM		 643 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
644 ctx1->fcp_cmnd_dma);
645 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
646 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
647 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
648 mempool_free(ctx1, ha->ctx_mempool);
649 ctx1 = NULL;
650 }
651
652 CMD_SP(cmd) = NULL;
b00ee7d7 653 qla2x00_rel_sp(sp->fcport->vha, sp);
9ba56b95
GM		 654}
655
14b06808 656static void
9ba56b95
GM		 657qla2x00_sp_compl(void *data, void *ptr, int res)
658{
659 struct qla_hw_data *ha = (struct qla_hw_data *)data;
660 srb_t *sp = (srb_t *)ptr;
661 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
662
663 cmd->result = res;
664
665 if (atomic_read(&sp->ref_count) == 0) {
666 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015,
667 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
668 sp, GET_CMD_SP(sp));
669 if (ql2xextended_error_logging & ql_dbg_io)
8fbdac8c 670 WARN_ON(atomic_read(&sp->ref_count) == 0);
9ba56b95
GM		 671 return;
672 }
673 if (!atomic_dec_and_test(&sp->ref_count))
674 return;
675
676 qla2x00_sp_free_dma(ha, sp);
677 cmd->scsi_done(cmd);
fca29703
AV		 678}
679
8ae6d9c7
GM		 680/* If we are SP1 here, we need to still take and release the host_lock as SP1
681 * does not have the changes necessary to avoid taking host->host_lock.
682 */
1da177e4 683static int
f5e3e40b 684qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 685{
134ae078 686 scsi_qla_host_t *vha = shost_priv(host);
fca29703 687 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 688 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 689 struct qla_hw_data *ha = vha->hw;
690 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 691 srb_t *sp;
692 int rval;
693
85880801 694 if (ha->flags.eeh_busy) {
7c3df132 695 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 696 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 697 "PCI Channel IO permanent failure, exiting "
698 "cmd=%p.\n", cmd);
b9b12f73 699 cmd->result = DID_NO_CONNECT << 16;
7c3df132 700 } else {
5f28d2d7 701 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 702 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 703 cmd->result = DID_REQUEUE << 16;
7c3df132 704 }
14e660e6
SJ		 705 goto qc24_fail_command;
706 }
707
19a7b4ae
JSEC		 708 rval = fc_remote_port_chkready(rport);
709 if (rval) {
710 cmd->result = rval;
5f28d2d7 711 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 712 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
713 cmd, rval);
fca29703
AV		 714 goto qc24_fail_command;
715 }
716
bad75002
AE		 717 if (!vha->flags.difdix_supported &&
718 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 719 ql_dbg(ql_dbg_io, vha, 0x3004,
720 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
721 cmd);
bad75002
AE		 722 cmd->result = DID_NO_CONNECT << 16;
723 goto qc24_fail_command;
724 }
aa651be8
CD		 725
726 if (!fcport) {
727 cmd->result = DID_NO_CONNECT << 16;
728 goto qc24_fail_command;
729 }
730
fca29703
AV		 731 if (atomic_read(&fcport->state) != FCS_ONLINE) {
732 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 733 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 734 ql_dbg(ql_dbg_io, vha, 0x3005,
735 "Returning DNC, fcport_state=%d loop_state=%d.\n",
736 atomic_read(&fcport->state),
737 atomic_read(&base_vha->loop_state));
fca29703
AV		 738 cmd->result = DID_NO_CONNECT << 16;
739 goto qc24_fail_command;
740 }
7b594131 741 goto qc24_target_busy;
fca29703
AV		 742 }
743
e05fe292
CD		 744 /*
745 * Return target busy if we've received a non-zero retry_delay_timer
746 * in a FCP_RSP.
747 */
975f7d46
BP		 748 if (fcport->retry_delay_timestamp == 0) {
749 /* retry delay not set */
750 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
e05fe292
CD		 751 fcport->retry_delay_timestamp = 0;
752 else
753 goto qc24_target_busy;
754
b00ee7d7 755 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
50280c01 756 if (!sp)
f5e3e40b 757 goto qc24_host_busy;
fca29703 758
9ba56b95
GM		 759 sp->u.scmd.cmd = cmd;
760 sp->type = SRB_SCSI_CMD;
761 atomic_set(&sp->ref_count, 1);
762 CMD_SP(cmd) = (void *)sp;
763 sp->free = qla2x00_sp_free_dma;
764 sp->done = qla2x00_sp_compl;
765
e315cd28 766 rval = ha->isp_ops->start_scsi(sp);
7c3df132 767 if (rval != QLA_SUCCESS) {
53016ed3 768 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 769 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 770 goto qc24_host_busy_free_sp;
7c3df132 771 }
fca29703 772
fca29703
AV		 773 return 0;
774
775qc24_host_busy_free_sp:
9ba56b95 776 qla2x00_sp_free_dma(ha, sp);
fca29703 777
f5e3e40b 778qc24_host_busy:
fca29703
AV		 779 return SCSI_MLQUEUE_HOST_BUSY;
780
7b594131
MC		 781qc24_target_busy:
782 return SCSI_MLQUEUE_TARGET_BUSY;
783
fca29703 784qc24_fail_command:
f5e3e40b 785 cmd->scsi_done(cmd);
fca29703
AV		 786
787 return 0;
788}
789
1da177e4
LT		 790/*
791 * qla2x00_eh_wait_on_command
792 * Waits for the command to be returned by the Firmware for some
793 * max time.
794 *
795 * Input:
1da177e4 796 * cmd = Scsi Command to wait on.
1da177e4
LT		 797 *
798 * Return:
799 * Not Found : 0
800 * Found : 1
801 */
802static int
e315cd28 803qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 804{
fe74c71f 805#define ABORT_POLLING_PERIOD 1000
478c3b03 806#define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 807 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 808 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
809 struct qla_hw_data *ha = vha->hw;
f4f051eb 810 int ret = QLA_SUCCESS;
1da177e4 811
85880801 812 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 813 ql_dbg(ql_dbg_taskm, vha, 0x8005,
814 "Return:eh_wait.\n");
85880801
AV		 815 return ret;
816 }
817
d970432c 818 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 819 msleep(ABORT_POLLING_PERIOD);
f4f051eb
AV		 820 }
821 if (CMD_SP(cmd))
822 ret = QLA_FUNCTION_FAILED;
1da177e4 823
f4f051eb 824 return ret;
1da177e4
LT		 825}
826
827/*
828 * qla2x00_wait_for_hba_online
fa2a1ce5 829 * Wait till the HBA is online after going through
1da177e4
LT		 830 * <= MAX_RETRIES_OF_ISP_ABORT or
831 * finally HBA is disabled ie marked offline
832 *
833 * Input:
834 * ha - pointer to host adapter structure
fa2a1ce5
AV		 835 *
836 * Note:
1da177e4
LT		 837 * Does context switching-Release SPIN_LOCK
838 * (if any) before calling this routine.
839 *
840 * Return:
841 * Success (Adapter is online) : 0
842 * Failed (Adapter is offline/disabled) : 1
843 */
854165f4 844int
e315cd28 845qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 846{
fca29703
AV		 847 int return_status;
848 unsigned long wait_online;
e315cd28
AC		 849 struct qla_hw_data *ha = vha->hw;
850 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 851
fa2a1ce5 852 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 853 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
854 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
855 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
856 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 857
858 msleep(1000);
859 }
e315cd28 860 if (base_vha->flags.online)
fa2a1ce5 861 return_status = QLA_SUCCESS;
1da177e4
LT		 862 else
863 return_status = QLA_FUNCTION_FAILED;
864
1da177e4
LT		 865 return (return_status);
866}
867
86fbee86 868/*
638a1a01
SC		 869 * qla2x00_wait_for_hba_ready
870 * Wait till the HBA is ready before doing driver unload
86fbee86
LC		 871 *
872 * Input:
873 * ha - pointer to host adapter structure
874 *
875 * Note:
876 * Does context switching-Release SPIN_LOCK
877 * (if any) before calling this routine.
878 *
86fbee86 879 */
638a1a01
SC		 880static void
881qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
86fbee86 882{
86fbee86 883 struct qla_hw_data *ha = vha->hw;
86fbee86 884
9d35894d
SC		 885 while (((qla2x00_reset_active(vha)) || ha->dpc_active ||
886 ha->flags.mbox_busy) ||
887 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
888 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags))
86fbee86 889 msleep(1000);
86fbee86
LC		 890}
891
2533cf67
LC		 892int
893qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
894{
895 int return_status;
896 unsigned long wait_reset;
897 struct qla_hw_data *ha = vha->hw;
898 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
899
900 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
901 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
902 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
903 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
904 ha->dpc_active) && time_before(jiffies, wait_reset)) {
905
906 msleep(1000);
907
908 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
909 ha->flags.chip_reset_done)
910 break;
911 }
912 if (ha->flags.chip_reset_done)
913 return_status = QLA_SUCCESS;
914 else
915 return_status = QLA_FUNCTION_FAILED;
916
917 return return_status;
918}
919
083a469d
GM		 920static void
921sp_get(struct srb *sp)
922{
923 atomic_inc(&sp->ref_count);
924}
925
1da177e4
LT		 926/**************************************************************************
927* qla2xxx_eh_abort
928*
929* Description:
930* The abort function will abort the specified command.
931*
932* Input:
933* cmd = Linux SCSI command packet to be aborted.
934*
935* Returns:
936* Either SUCCESS or FAILED.
937*
938* Note:
2ea00202 939* Only return FAILED if command not returned by firmware.
1da177e4 940**************************************************************************/
e5f82ab8 941static int
1da177e4
LT		 942qla2xxx_eh_abort(struct scsi_cmnd *cmd)
943{
e315cd28 944 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 945 srb_t *sp;
4e98d3b8 946 int ret;
9cb78c16
HR		 947 unsigned int id;
948 uint64_t lun;
18e144d3 949 unsigned long flags;
f934c9d0 950 int rval, wait = 0;
e315cd28 951 struct qla_hw_data *ha = vha->hw;
1da177e4 952
f4f051eb 953 if (!CMD_SP(cmd))
2ea00202 954 return SUCCESS;
1da177e4 955
4e98d3b8
AV		 956 ret = fc_block_scsi_eh(cmd);
957 if (ret != 0)
958 return ret;
959 ret = SUCCESS;
960
f4f051eb
AV		 961 id = cmd->device->id;
962 lun = cmd->device->lun;
1da177e4 963
e315cd28 964 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 965 sp = (srb_t *) CMD_SP(cmd);
966 if (!sp) {
967 spin_unlock_irqrestore(&ha->hardware_lock, flags);
968 return SUCCESS;
969 }
1da177e4 970
7c3df132 971 ql_dbg(ql_dbg_taskm, vha, 0x8002,
c7bc4cae
CD		 972 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
973 vha->host_no, id, lun, sp, cmd, sp->handle);
17d98630 974
170babc3
MC		 975 /* Get a reference to the sp and drop the lock.*/
976 sp_get(sp);
083a469d 977
e315cd28 978 spin_unlock_irqrestore(&ha->hardware_lock, flags);
f934c9d0
CD		 979 rval = ha->isp_ops->abort_command(sp);
980 if (rval) {
96219424 981 if (rval == QLA_FUNCTION_PARAMETER_ERROR)
f934c9d0 982 ret = SUCCESS;
96219424 983 else
f934c9d0
CD		 984 ret = FAILED;
985
7c3df132 986 ql_dbg(ql_dbg_taskm, vha, 0x8003,
f934c9d0 987 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval);
170babc3 988 } else {
7c3df132 989 ql_dbg(ql_dbg_taskm, vha, 0x8004,
cfb0919c 990 "Abort command mbx success cmd=%p.\n", cmd);
170babc3
MC		 991 wait = 1;
992 }
75942064
SK		 993
994 spin_lock_irqsave(&ha->hardware_lock, flags);
9ba56b95 995 sp->done(ha, sp, 0);
75942064 996 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 997
bc91ade9
CD		 998 /* Did the command return during mailbox execution? */
999 if (ret == FAILED && !CMD_SP(cmd))
1000 ret = SUCCESS;
1001
f4f051eb 1002 /* Wait for the command to be returned. */
2ea00202 1003 if (wait) {
e315cd28 1004 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132 1005 ql_log(ql_log_warn, vha, 0x8006,
cfb0919c 1006 "Abort handler timed out cmd=%p.\n", cmd);
2ea00202 1007 ret = FAILED;
f4f051eb 1008 }
1da177e4 1009 }
1da177e4 1010
7c3df132 1011 ql_log(ql_log_info, vha, 0x801c,
9cb78c16 1012 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n",
cfb0919c 1013 vha->host_no, id, lun, wait, ret);
1da177e4 1014
f4f051eb
AV		 1015 return ret;
1016}
1da177e4 1017
4d78c973 1018int
e315cd28 1019qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
9cb78c16 1020 uint64_t l, enum nexus_wait_type type)
f4f051eb 1021{
17d98630 1022 int cnt, match, status;
18e144d3 1023 unsigned long flags;
e315cd28 1024 struct qla_hw_data *ha = vha->hw;
73208dfd 1025 struct req_que *req;
4d78c973 1026 srb_t *sp;
9ba56b95 1027 struct scsi_cmnd *cmd;
1da177e4 1028
523ec773 1029 status = QLA_SUCCESS;
17d98630 1030
e315cd28 1031 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1032 req = vha->req;
17d98630 1033 for (cnt = 1; status == QLA_SUCCESS &&
8d93f550 1034 cnt < req->num_outstanding_cmds; cnt++) {
17d98630
AC		 1035 sp = req->outstanding_cmds[cnt];
1036 if (!sp)
523ec773 1037 continue;
9ba56b95 1038 if (sp->type != SRB_SCSI_CMD)
cf53b069 1039 continue;
17d98630
AC		 1040 if (vha->vp_idx != sp->fcport->vha->vp_idx)
1041 continue;
1042 match = 0;
9ba56b95 1043 cmd = GET_CMD_SP(sp);
17d98630
AC		 1044 switch (type) {
1045 case WAIT_HOST:
1046 match = 1;
1047 break;
1048 case WAIT_TARGET:
9ba56b95 1049 match = cmd->device->id == t;
17d98630
AC		 1050 break;
1051 case WAIT_LUN:
9ba56b95
GM		 1052 match = (cmd->device->id == t &&
1053 cmd->device->lun == l);
17d98630 1054 break;
73208dfd 1055 }
17d98630
AC		 1056 if (!match)
1057 continue;
1058
1059 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1060 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1061 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1062 }
e315cd28 1063 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1064
1065 return status;
1da177e4
LT		 1066}
1067
523ec773
AV		 1068static char *reset_errors[] = {
1069 "HBA not online",
1070 "HBA not ready",
1071 "Task management failed",
1072 "Waiting for command completions",
1073};
1da177e4 1074
e5f82ab8 1075static int
523ec773 1076__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
9cb78c16 1077 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1da177e4 1078{
e315cd28 1079 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1080 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1081 int err;
1da177e4 1082
7c3df132 1083 if (!fcport) {
523ec773 1084 return FAILED;
7c3df132 1085 }
1da177e4 1086
4e98d3b8
AV		 1087 err = fc_block_scsi_eh(cmd);
1088 if (err != 0)
1089 return err;
1090
7c3df132 1091 ql_log(ql_log_info, vha, 0x8009,
9cb78c16 1092 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
7c3df132 1093 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1094
523ec773 1095 err = 0;
7c3df132
SK		 1096 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1097 ql_log(ql_log_warn, vha, 0x800a,
1098 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1099 goto eh_reset_failed;
7c3df132 1100 }
523ec773 1101 err = 2;
2afa19a9 1102 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1103 != QLA_SUCCESS) {
1104 ql_log(ql_log_warn, vha, 0x800c,
1105 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1106 goto eh_reset_failed;
7c3df132 1107 }
523ec773 1108 err = 3;
e315cd28 1109 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1110 cmd->device->lun, type) != QLA_SUCCESS) {
1111 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1112 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1113 goto eh_reset_failed;
7c3df132 1114 }
523ec773 1115
7c3df132 1116 ql_log(ql_log_info, vha, 0x800e,
9cb78c16 1117 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
cfb0919c 1118 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1119
1120 return SUCCESS;
1121
4d78c973 1122eh_reset_failed:
7c3df132 1123 ql_log(ql_log_info, vha, 0x800f,
9cb78c16 1124 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
cfb0919c
CD		 1125 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1126 cmd);
523ec773
AV		 1127 return FAILED;
1128}
1da177e4 1129
523ec773
AV		 1130static int
1131qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1132{
e315cd28
AC		 1133 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1134 struct qla_hw_data *ha = vha->hw;
1da177e4 1135
523ec773
AV		 1136 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1137 ha->isp_ops->lun_reset);
1da177e4
LT		 1138}
1139
1da177e4 1140static int
523ec773 1141qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1142{
e315cd28
AC		 1143 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1144 struct qla_hw_data *ha = vha->hw;
1da177e4 1145
523ec773
AV		 1146 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1147 ha->isp_ops->target_reset);
1da177e4
LT		 1148}
1149
1da177e4
LT		 1150/**************************************************************************
1151* qla2xxx_eh_bus_reset
1152*
1153* Description:
1154* The bus reset function will reset the bus and abort any executing
1155* commands.
1156*
1157* Input:
1158* cmd = Linux SCSI command packet of the command that cause the
1159* bus reset.
1160*
1161* Returns:
1162* SUCCESS/FAILURE (defined as macro in scsi.h).
1163*
1164**************************************************************************/
e5f82ab8 1165static int
1da177e4
LT		 1166qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1167{
e315cd28 1168 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1169 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1170 int ret = FAILED;
9cb78c16
HR		 1171 unsigned int id;
1172 uint64_t lun;
f4f051eb 1173
f4f051eb
AV		 1174 id = cmd->device->id;
1175 lun = cmd->device->lun;
1da177e4 1176
7c3df132 1177 if (!fcport) {
f4f051eb 1178 return ret;
7c3df132 1179 }
1da177e4 1180
4e98d3b8
AV		 1181 ret = fc_block_scsi_eh(cmd);
1182 if (ret != 0)
1183 return ret;
1184 ret = FAILED;
1185
7c3df132 1186 ql_log(ql_log_info, vha, 0x8012,
9cb78c16 1187 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1188
e315cd28 1189 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1190 ql_log(ql_log_fatal, vha, 0x8013,
1191 "Wait for hba online failed board disabled.\n");
f4f051eb 1192 goto eh_bus_reset_done;
1da177e4
LT		 1193 }
1194
ad537689
SK		 1195 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1196 ret = SUCCESS;
1197
f4f051eb
AV		 1198 if (ret == FAILED)
1199 goto eh_bus_reset_done;
1da177e4 1200
9a41a62b 1201 /* Flush outstanding commands. */
4d78c973 1202 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1203 QLA_SUCCESS) {
1204 ql_log(ql_log_warn, vha, 0x8014,
1205 "Wait for pending commands failed.\n");
9a41a62b 1206 ret = FAILED;
7c3df132 1207 }
1da177e4 1208
f4f051eb 1209eh_bus_reset_done:
7c3df132 1210 ql_log(ql_log_warn, vha, 0x802b,
9cb78c16 1211 "BUS RESET %s nexus=%ld:%d:%llu.\n",
d6a03581 1212 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1213
f4f051eb 1214 return ret;
1da177e4
LT		 1215}
1216
1217/**************************************************************************
1218* qla2xxx_eh_host_reset
1219*
1220* Description:
1221* The reset function will reset the Adapter.
1222*
1223* Input:
1224* cmd = Linux SCSI command packet of the command that cause the
1225* adapter reset.
1226*
1227* Returns:
1228* Either SUCCESS or FAILED.
1229*
1230* Note:
1231**************************************************************************/
e5f82ab8 1232static int
1da177e4
LT		 1233qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1234{
e315cd28 1235 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1236 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1237 int ret = FAILED;
9cb78c16
HR		 1238 unsigned int id;
1239 uint64_t lun;
e315cd28 1240 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1241
f4f051eb
AV		 1242 id = cmd->device->id;
1243 lun = cmd->device->lun;
f4f051eb 1244
7c3df132 1245 ql_log(ql_log_info, vha, 0x8018,
9cb78c16 1246 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1247
63ee7072
CD		 1248 /*
1249 * No point in issuing another reset if one is active. Also do not
1250 * attempt a reset if we are updating flash.
1251 */
1252 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
f4f051eb 1253 goto eh_host_reset_lock;
1da177e4 1254
e315cd28
AC		 1255 if (vha != base_vha) {
1256 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1257 goto eh_host_reset_lock;
e315cd28 1258 } else {
7ec0effd 1259 if (IS_P3P_TYPE(vha->hw)) {
a9083016
GM		 1260 if (!qla82xx_fcoe_ctx_reset(vha)) {
1261 /* Ctx reset success */
1262 ret = SUCCESS;
1263 goto eh_host_reset_lock;
1264 }
1265 /* fall thru if ctx reset failed */
1266 }
68ca949c
AC		 1267 if (ha->wq)
1268 flush_workqueue(ha->wq);
1269
e315cd28 1270 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1271 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1272 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1273 /* failed. schedule dpc to try */
1274 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1275
7c3df132
SK		 1276 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1277 ql_log(ql_log_warn, vha, 0x802a,
1278 "wait for hba online failed.\n");
e315cd28 1279 goto eh_host_reset_lock;
7c3df132 1280 }
e315cd28
AC		 1281 }
1282 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1283 }
1da177e4 1284
e315cd28 1285 /* Waiting for command to be returned to OS.*/
4d78c973 1286 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1287 QLA_SUCCESS)
f4f051eb 1288 ret = SUCCESS;
1da177e4 1289
f4f051eb 1290eh_host_reset_lock:
cfb0919c 1291 ql_log(ql_log_info, vha, 0x8017,
9cb78c16 1292 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
cfb0919c 1293 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1294
f4f051eb
AV		 1295 return ret;
1296}
1da177e4
LT		 1297
1298/*
1299* qla2x00_loop_reset
1300* Issue loop reset.
1301*
1302* Input:
1303* ha = adapter block pointer.
1304*
1305* Returns:
1306* 0 = success
1307*/
a4722cf2 1308int
e315cd28 1309qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1310{
0c8c39af 1311 int ret;
bdf79621 1312 struct fc_port *fcport;
e315cd28 1313 struct qla_hw_data *ha = vha->hw;
1da177e4 1314
5854771e
AB		 1315 if (IS_QLAFX00(ha)) {
1316 return qlafx00_loop_reset(vha);
1317 }
1318
f4c496c1 1319 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1320 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1321 if (fcport->port_type != FCT_TARGET)
1322 continue;
1323
1324 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1325 if (ret != QLA_SUCCESS) {
7c3df132 1326 ql_dbg(ql_dbg_taskm, vha, 0x802c,
5854771e 1327 "Bus Reset failed: Reset=%d "
7c3df132 1328 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1329 }
1330 }
1331 }
1332
8ae6d9c7 1333
6246b8a1 1334 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1335 atomic_set(&vha->loop_state, LOOP_DOWN);
1336 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1337 qla2x00_mark_all_devices_lost(vha, 0);
e315cd28 1338 ret = qla2x00_full_login_lip(vha);
0c8c39af 1339 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1340 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1341 "full_login_lip=%d.\n", ret);
749af3d5 1342 }
0c8c39af
AV		 1343 }
1344
0d6e61bc 1345 if (ha->flags.enable_lip_reset) {
e315cd28 1346 ret = qla2x00_lip_reset(vha);
ad537689 1347 if (ret != QLA_SUCCESS)
7c3df132
SK		 1348 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1349 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1350 }
1351
1da177e4 1352 /* Issue marker command only when we are going to start the I/O */
e315cd28 1353 vha->marker_needed = 1;
1da177e4 1354
0c8c39af 1355 return QLA_SUCCESS;
1da177e4
LT		 1356}
1357
df4bf0bb 1358void
e315cd28 1359qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
df4bf0bb 1360{
73208dfd 1361 int que, cnt;
df4bf0bb
AV		 1362 unsigned long flags;
1363 srb_t *sp;
e315cd28 1364 struct qla_hw_data *ha = vha->hw;
73208dfd 1365 struct req_que *req;
df4bf0bb 1366
c0cb4496
AE		 1367 qlt_host_reset_handler(ha);
1368
df4bf0bb 1369 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 1370 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 1371 req = ha->req_q_map[que];
73208dfd
AC		 1372 if (!req)
1373 continue;
8d93f550
CD		 1374 if (!req->outstanding_cmds)
1375 continue;
1376 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
73208dfd 1377 sp = req->outstanding_cmds[cnt];
e612d465 1378 if (sp) {
73208dfd 1379 req->outstanding_cmds[cnt] = NULL;
9ba56b95 1380 sp->done(vha, sp, res);
73208dfd 1381 }
df4bf0bb
AV		 1382 }
1383 }
1384 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1385}
1386
f4f051eb
AV		 1387static int
1388qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1389{
bdf79621 1390 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1391
19a7b4ae 1392 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1393 return -ENXIO;
bdf79621 1394
19a7b4ae 1395 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1396
f4f051eb
AV		 1397 return 0;
1398}
1da177e4 1399
f4f051eb
AV		 1400static int
1401qla2xxx_slave_configure(struct scsi_device *sdev)
1402{
e315cd28 1403 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1404 struct req_que *req = vha->req;
8482e118 1405
9e522cd8
AE		 1406 if (IS_T10_PI_CAPABLE(vha->hw))
1407 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1408
db5ed4df 1409 scsi_change_queue_depth(sdev, req->max_q_depth);
f4f051eb
AV		 1410 return 0;
1411}
1da177e4 1412
f4f051eb
AV		 1413static void
1414qla2xxx_slave_destroy(struct scsi_device *sdev)
1415{
1416 sdev->hostdata = NULL;
1da177e4
LT		 1417}
1418
1419/**
1420 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1421 * @ha: HA context
1422 *
1423 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1424 * supported addressing method.
1425 */
1426static void
53303c42 1427qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1428{
7524f9b9 1429 /* Assume a 32bit DMA mask. */
1da177e4 1430 ha->flags.enable_64bit_addressing = 0;
1da177e4 1431
6a35528a 1432 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1433 /* Any upper-dword bits set? */
1434 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1435 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1436 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1437 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1438 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1439 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1440 return;
1da177e4 1441 }
1da177e4 1442 }
7524f9b9 1443
284901a9
YH		 1444 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1445 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1446}
1447
fd34f556 1448static void
e315cd28 1449qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1450{
1451 unsigned long flags = 0;
1452 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1453
1454 spin_lock_irqsave(&ha->hardware_lock, flags);
1455 ha->interrupts_on = 1;
1456 /* enable risc and host interrupts */
1457 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1458 RD_REG_WORD(&reg->ictrl);
1459 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1460
1461}
1462
1463static void
e315cd28 1464qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1465{
1466 unsigned long flags = 0;
1467 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1468
1469 spin_lock_irqsave(&ha->hardware_lock, flags);
1470 ha->interrupts_on = 0;
1471 /* disable risc and host interrupts */
1472 WRT_REG_WORD(&reg->ictrl, 0);
1473 RD_REG_WORD(&reg->ictrl);
1474 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1475}
1476
1477static void
e315cd28 1478qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1479{
1480 unsigned long flags = 0;
1481 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1482
1483 spin_lock_irqsave(&ha->hardware_lock, flags);
1484 ha->interrupts_on = 1;
1485 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1486 RD_REG_DWORD(&reg->ictrl);
1487 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1488}
1489
1490static void
e315cd28 1491qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1492{
1493 unsigned long flags = 0;
1494 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1495
124f85e6
AV		 1496 if (IS_NOPOLLING_TYPE(ha))
1497 return;
fd34f556
AV		 1498 spin_lock_irqsave(&ha->hardware_lock, flags);
1499 ha->interrupts_on = 0;
1500 WRT_REG_DWORD(&reg->ictrl, 0);
1501 RD_REG_DWORD(&reg->ictrl);
1502 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1503}
1504
706f457d
GM		 1505static int
1506qla2x00_iospace_config(struct qla_hw_data *ha)
1507{
1508 resource_size_t pio;
1509 uint16_t msix;
1510 int cpus;
1511
706f457d
GM		 1512 if (pci_request_selected_regions(ha->pdev, ha->bars,
1513 QLA2XXX_DRIVER_NAME)) {
1514 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1515 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1516 pci_name(ha->pdev));
1517 goto iospace_error_exit;
1518 }
1519 if (!(ha->bars & 1))
1520 goto skip_pio;
1521
1522 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1523 pio = pci_resource_start(ha->pdev, 0);
1524 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1525 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1526 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1527 "Invalid pci I/O region size (%s).\n",
1528 pci_name(ha->pdev));
1529 pio = 0;
1530 }
1531 } else {
1532 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1533 "Region #0 no a PIO resource (%s).\n",
1534 pci_name(ha->pdev));
1535 pio = 0;
1536 }
1537 ha->pio_address = pio;
1538 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1539 "PIO address=%llu.\n",
1540 (unsigned long long)ha->pio_address);
1541
1542skip_pio:
1543 /* Use MMIO operations for all accesses. */
1544 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1545 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1546 "Region #1 not an MMIO resource (%s), aborting.\n",
1547 pci_name(ha->pdev));
1548 goto iospace_error_exit;
1549 }
1550 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1551 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1552 "Invalid PCI mem region size (%s), aborting.\n",
1553 pci_name(ha->pdev));
1554 goto iospace_error_exit;
1555 }
1556
1557 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1558 if (!ha->iobase) {
1559 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1560 "Cannot remap MMIO (%s), aborting.\n",
1561 pci_name(ha->pdev));
1562 goto iospace_error_exit;
1563 }
1564
1565 /* Determine queue resources */
1566 ha->max_req_queues = ha->max_rsp_queues = 1;
1567 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
1568 (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
1569 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
1570 goto mqiobase_exit;
1571
1572 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1573 pci_resource_len(ha->pdev, 3));
1574 if (ha->mqiobase) {
1575 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1576 "MQIO Base=%p.\n", ha->mqiobase);
1577 /* Read MSIX vector size of the board */
1578 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
1579 ha->msix_count = msix;
1580 /* Max queues are bounded by available msix vectors */
1581 /* queue 0 uses two msix vectors */
1582 if (ql2xmultique_tag) {
1583 cpus = num_online_cpus();
1584 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1585 (cpus + 1) : (ha->msix_count - 1);
1586 ha->max_req_queues = 2;
1587 } else if (ql2xmaxqueues > 1) {
1588 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1589 QLA_MQ_SIZE : ql2xmaxqueues;
1590 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008,
1591 "QoS mode set, max no of request queues:%d.\n",
1592 ha->max_req_queues);
1593 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019,
1594 "QoS mode set, max no of request queues:%d.\n",
1595 ha->max_req_queues);
1596 }
1597 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
1598 "MSI-X vector count: %d.\n", msix);
1599 } else
1600 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1601 "BAR 3 not enabled.\n");
1602
1603mqiobase_exit:
1604 ha->msix_count = ha->max_rsp_queues + 1;
1605 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
1606 "MSIX Count:%d.\n", ha->msix_count);
1607 return (0);
1608
1609iospace_error_exit:
1610 return (-ENOMEM);
1611}
1612
1613
6246b8a1
GM		 1614static int
1615qla83xx_iospace_config(struct qla_hw_data *ha)
1616{
1617 uint16_t msix;
1618 int cpus;
1619
1620 if (pci_request_selected_regions(ha->pdev, ha->bars,
1621 QLA2XXX_DRIVER_NAME)) {
1622 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
1623 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1624 pci_name(ha->pdev));
1625
1626 goto iospace_error_exit;
1627 }
1628
1629 /* Use MMIO operations for all accesses. */
1630 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1631 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
1632 "Invalid pci I/O region size (%s).\n",
1633 pci_name(ha->pdev));
1634 goto iospace_error_exit;
1635 }
1636 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1637 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
1638 "Invalid PCI mem region size (%s), aborting\n",
1639 pci_name(ha->pdev));
1640 goto iospace_error_exit;
1641 }
1642
1643 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
1644 if (!ha->iobase) {
1645 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
1646 "Cannot remap MMIO (%s), aborting.\n",
1647 pci_name(ha->pdev));
1648 goto iospace_error_exit;
1649 }
1650
1651 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
1652 /* 83XX 26XX always use MQ type access for queues
1653 * - mbar 2, a.k.a region 4 */
1654 ha->max_req_queues = ha->max_rsp_queues = 1;
1655 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
1656 pci_resource_len(ha->pdev, 4));
1657
1658 if (!ha->mqiobase) {
1659 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
1660 "BAR2/region4 not enabled\n");
1661 goto mqiobase_exit;
1662 }
1663
1664 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
1665 pci_resource_len(ha->pdev, 2));
1666 if (ha->msixbase) {
1667 /* Read MSIX vector size of the board */
1668 pci_read_config_word(ha->pdev,
1669 QLA_83XX_PCI_MSIX_CONTROL, &msix);
1670 ha->msix_count = msix;
1671 /* Max queues are bounded by available msix vectors */
1672 /* queue 0 uses two msix vectors */
1673 if (ql2xmultique_tag) {
1674 cpus = num_online_cpus();
1675 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1676 (cpus + 1) : (ha->msix_count - 1);
1677 ha->max_req_queues = 2;
1678 } else if (ql2xmaxqueues > 1) {
1679 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1680 QLA_MQ_SIZE : ql2xmaxqueues;
1681 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c,
1682 "QoS mode set, max no of request queues:%d.\n",
1683 ha->max_req_queues);
1684 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
1685 "QoS mode set, max no of request queues:%d.\n",
1686 ha->max_req_queues);
1687 }
1688 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
1689 "MSI-X vector count: %d.\n", msix);
1690 } else
1691 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
1692 "BAR 1 not enabled.\n");
1693
1694mqiobase_exit:
1695 ha->msix_count = ha->max_rsp_queues + 1;
aa230bc5
AE		 1696
1697 qlt_83xx_iospace_config(ha);
1698
6246b8a1
GM		 1699 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
1700 "MSIX Count:%d.\n", ha->msix_count);
1701 return 0;
1702
1703iospace_error_exit:
1704 return -ENOMEM;
1705}
1706
fd34f556
AV		 1707static struct isp_operations qla2100_isp_ops = {
1708 .pci_config = qla2100_pci_config,
1709 .reset_chip = qla2x00_reset_chip,
1710 .chip_diag = qla2x00_chip_diag,
1711 .config_rings = qla2x00_config_rings,
1712 .reset_adapter = qla2x00_reset_adapter,
1713 .nvram_config = qla2x00_nvram_config,
1714 .update_fw_options = qla2x00_update_fw_options,
1715 .load_risc = qla2x00_load_risc,
1716 .pci_info_str = qla2x00_pci_info_str,
1717 .fw_version_str = qla2x00_fw_version_str,
1718 .intr_handler = qla2100_intr_handler,
1719 .enable_intrs = qla2x00_enable_intrs,
1720 .disable_intrs = qla2x00_disable_intrs,
1721 .abort_command = qla2x00_abort_command,
523ec773
AV		 1722 .target_reset = qla2x00_abort_target,
1723 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1724 .fabric_login = qla2x00_login_fabric,
1725 .fabric_logout = qla2x00_fabric_logout,
1726 .calc_req_entries = qla2x00_calc_iocbs_32,
1727 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1728 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1729 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1730 .read_nvram = qla2x00_read_nvram_data,
1731 .write_nvram = qla2x00_write_nvram_data,
1732 .fw_dump = qla2100_fw_dump,
1733 .beacon_on = NULL,
1734 .beacon_off = NULL,
1735 .beacon_blink = NULL,
1736 .read_optrom = qla2x00_read_optrom_data,
1737 .write_optrom = qla2x00_write_optrom_data,
1738 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1739 .start_scsi = qla2x00_start_scsi,
a9083016 1740 .abort_isp = qla2x00_abort_isp,
706f457d 1741 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1742 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1743};
1744
1745static struct isp_operations qla2300_isp_ops = {
1746 .pci_config = qla2300_pci_config,
1747 .reset_chip = qla2x00_reset_chip,
1748 .chip_diag = qla2x00_chip_diag,
1749 .config_rings = qla2x00_config_rings,
1750 .reset_adapter = qla2x00_reset_adapter,
1751 .nvram_config = qla2x00_nvram_config,
1752 .update_fw_options = qla2x00_update_fw_options,
1753 .load_risc = qla2x00_load_risc,
1754 .pci_info_str = qla2x00_pci_info_str,
1755 .fw_version_str = qla2x00_fw_version_str,
1756 .intr_handler = qla2300_intr_handler,
1757 .enable_intrs = qla2x00_enable_intrs,
1758 .disable_intrs = qla2x00_disable_intrs,
1759 .abort_command = qla2x00_abort_command,
523ec773
AV		 1760 .target_reset = qla2x00_abort_target,
1761 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1762 .fabric_login = qla2x00_login_fabric,
1763 .fabric_logout = qla2x00_fabric_logout,
1764 .calc_req_entries = qla2x00_calc_iocbs_32,
1765 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1766 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1767 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1768 .read_nvram = qla2x00_read_nvram_data,
1769 .write_nvram = qla2x00_write_nvram_data,
1770 .fw_dump = qla2300_fw_dump,
1771 .beacon_on = qla2x00_beacon_on,
1772 .beacon_off = qla2x00_beacon_off,
1773 .beacon_blink = qla2x00_beacon_blink,
1774 .read_optrom = qla2x00_read_optrom_data,
1775 .write_optrom = qla2x00_write_optrom_data,
1776 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1777 .start_scsi = qla2x00_start_scsi,
a9083016 1778 .abort_isp = qla2x00_abort_isp,
7ec0effd 1779 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1780 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1781};
1782
1783static struct isp_operations qla24xx_isp_ops = {
1784 .pci_config = qla24xx_pci_config,
1785 .reset_chip = qla24xx_reset_chip,
1786 .chip_diag = qla24xx_chip_diag,
1787 .config_rings = qla24xx_config_rings,
1788 .reset_adapter = qla24xx_reset_adapter,
1789 .nvram_config = qla24xx_nvram_config,
1790 .update_fw_options = qla24xx_update_fw_options,
1791 .load_risc = qla24xx_load_risc,
1792 .pci_info_str = qla24xx_pci_info_str,
1793 .fw_version_str = qla24xx_fw_version_str,
1794 .intr_handler = qla24xx_intr_handler,
1795 .enable_intrs = qla24xx_enable_intrs,
1796 .disable_intrs = qla24xx_disable_intrs,
1797 .abort_command = qla24xx_abort_command,
523ec773
AV		 1798 .target_reset = qla24xx_abort_target,
1799 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 1800 .fabric_login = qla24xx_login_fabric,
1801 .fabric_logout = qla24xx_fabric_logout,
1802 .calc_req_entries = NULL,
1803 .build_iocbs = NULL,
1804 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1805 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1806 .read_nvram = qla24xx_read_nvram_data,
1807 .write_nvram = qla24xx_write_nvram_data,
1808 .fw_dump = qla24xx_fw_dump,
1809 .beacon_on = qla24xx_beacon_on,
1810 .beacon_off = qla24xx_beacon_off,
1811 .beacon_blink = qla24xx_beacon_blink,
1812 .read_optrom = qla24xx_read_optrom_data,
1813 .write_optrom = qla24xx_write_optrom_data,
1814 .get_flash_version = qla24xx_get_flash_version,
e315cd28 1815 .start_scsi = qla24xx_start_scsi,
a9083016 1816 .abort_isp = qla2x00_abort_isp,
7ec0effd 1817 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1818 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1819};
1820
c3a2f0df
AV		 1821static struct isp_operations qla25xx_isp_ops = {
1822 .pci_config = qla25xx_pci_config,
1823 .reset_chip = qla24xx_reset_chip,
1824 .chip_diag = qla24xx_chip_diag,
1825 .config_rings = qla24xx_config_rings,
1826 .reset_adapter = qla24xx_reset_adapter,
1827 .nvram_config = qla24xx_nvram_config,
1828 .update_fw_options = qla24xx_update_fw_options,
1829 .load_risc = qla24xx_load_risc,
1830 .pci_info_str = qla24xx_pci_info_str,
1831 .fw_version_str = qla24xx_fw_version_str,
1832 .intr_handler = qla24xx_intr_handler,
1833 .enable_intrs = qla24xx_enable_intrs,
1834 .disable_intrs = qla24xx_disable_intrs,
1835 .abort_command = qla24xx_abort_command,
523ec773
AV		 1836 .target_reset = qla24xx_abort_target,
1837 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 1838 .fabric_login = qla24xx_login_fabric,
1839 .fabric_logout = qla24xx_fabric_logout,
1840 .calc_req_entries = NULL,
1841 .build_iocbs = NULL,
1842 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1843 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1844 .read_nvram = qla25xx_read_nvram_data,
1845 .write_nvram = qla25xx_write_nvram_data,
1846 .fw_dump = qla25xx_fw_dump,
1847 .beacon_on = qla24xx_beacon_on,
1848 .beacon_off = qla24xx_beacon_off,
1849 .beacon_blink = qla24xx_beacon_blink,
338c9161 1850 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 1851 .write_optrom = qla24xx_write_optrom_data,
1852 .get_flash_version = qla24xx_get_flash_version,
bad75002 1853 .start_scsi = qla24xx_dif_start_scsi,
a9083016 1854 .abort_isp = qla2x00_abort_isp,
7ec0effd 1855 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1856 .initialize_adapter = qla2x00_initialize_adapter,
c3a2f0df
AV		 1857};
1858
3a03eb79
AV		 1859static struct isp_operations qla81xx_isp_ops = {
1860 .pci_config = qla25xx_pci_config,
1861 .reset_chip = qla24xx_reset_chip,
1862 .chip_diag = qla24xx_chip_diag,
1863 .config_rings = qla24xx_config_rings,
1864 .reset_adapter = qla24xx_reset_adapter,
1865 .nvram_config = qla81xx_nvram_config,
1866 .update_fw_options = qla81xx_update_fw_options,
eaac30be 1867 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 1868 .pci_info_str = qla24xx_pci_info_str,
1869 .fw_version_str = qla24xx_fw_version_str,
1870 .intr_handler = qla24xx_intr_handler,
1871 .enable_intrs = qla24xx_enable_intrs,
1872 .disable_intrs = qla24xx_disable_intrs,
1873 .abort_command = qla24xx_abort_command,
1874 .target_reset = qla24xx_abort_target,
1875 .lun_reset = qla24xx_lun_reset,
1876 .fabric_login = qla24xx_login_fabric,
1877 .fabric_logout = qla24xx_fabric_logout,
1878 .calc_req_entries = NULL,
1879 .build_iocbs = NULL,
1880 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1881 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 1882 .read_nvram = NULL,
1883 .write_nvram = NULL,
3a03eb79
AV		 1884 .fw_dump = qla81xx_fw_dump,
1885 .beacon_on = qla24xx_beacon_on,
1886 .beacon_off = qla24xx_beacon_off,
6246b8a1 1887 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 1888 .read_optrom = qla25xx_read_optrom_data,
1889 .write_optrom = qla24xx_write_optrom_data,
1890 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 1891 .start_scsi = qla24xx_dif_start_scsi,
a9083016 1892 .abort_isp = qla2x00_abort_isp,
7ec0effd 1893 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1894 .initialize_adapter = qla2x00_initialize_adapter,
a9083016
GM		 1895};
1896
1897static struct isp_operations qla82xx_isp_ops = {
1898 .pci_config = qla82xx_pci_config,
1899 .reset_chip = qla82xx_reset_chip,
1900 .chip_diag = qla24xx_chip_diag,
1901 .config_rings = qla82xx_config_rings,
1902 .reset_adapter = qla24xx_reset_adapter,
1903 .nvram_config = qla81xx_nvram_config,
1904 .update_fw_options = qla24xx_update_fw_options,
1905 .load_risc = qla82xx_load_risc,
9d55ca66 1906 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 1907 .fw_version_str = qla24xx_fw_version_str,
1908 .intr_handler = qla82xx_intr_handler,
1909 .enable_intrs = qla82xx_enable_intrs,
1910 .disable_intrs = qla82xx_disable_intrs,
1911 .abort_command = qla24xx_abort_command,
1912 .target_reset = qla24xx_abort_target,
1913 .lun_reset = qla24xx_lun_reset,
1914 .fabric_login = qla24xx_login_fabric,
1915 .fabric_logout = qla24xx_fabric_logout,
1916 .calc_req_entries = NULL,
1917 .build_iocbs = NULL,
1918 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1919 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1920 .read_nvram = qla24xx_read_nvram_data,
1921 .write_nvram = qla24xx_write_nvram_data,
a1b23c5a 1922 .fw_dump = qla82xx_fw_dump,
999916dc
SK		 1923 .beacon_on = qla82xx_beacon_on,
1924 .beacon_off = qla82xx_beacon_off,
1925 .beacon_blink = NULL,
a9083016
GM		 1926 .read_optrom = qla82xx_read_optrom_data,
1927 .write_optrom = qla82xx_write_optrom_data,
7ec0effd 1928 .get_flash_version = qla82xx_get_flash_version,
a9083016
GM		 1929 .start_scsi = qla82xx_start_scsi,
1930 .abort_isp = qla82xx_abort_isp,
706f457d 1931 .iospace_config = qla82xx_iospace_config,
8ae6d9c7 1932 .initialize_adapter = qla2x00_initialize_adapter,
3a03eb79
AV		 1933};
1934
7ec0effd
AD		 1935static struct isp_operations qla8044_isp_ops = {
1936 .pci_config = qla82xx_pci_config,
1937 .reset_chip = qla82xx_reset_chip,
1938 .chip_diag = qla24xx_chip_diag,
1939 .config_rings = qla82xx_config_rings,
1940 .reset_adapter = qla24xx_reset_adapter,
1941 .nvram_config = qla81xx_nvram_config,
1942 .update_fw_options = qla24xx_update_fw_options,
1943 .load_risc = qla82xx_load_risc,
1944 .pci_info_str = qla24xx_pci_info_str,
1945 .fw_version_str = qla24xx_fw_version_str,
1946 .intr_handler = qla8044_intr_handler,
1947 .enable_intrs = qla82xx_enable_intrs,
1948 .disable_intrs = qla82xx_disable_intrs,
1949 .abort_command = qla24xx_abort_command,
1950 .target_reset = qla24xx_abort_target,
1951 .lun_reset = qla24xx_lun_reset,
1952 .fabric_login = qla24xx_login_fabric,
1953 .fabric_logout = qla24xx_fabric_logout,
1954 .calc_req_entries = NULL,
1955 .build_iocbs = NULL,
1956 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1957 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1958 .read_nvram = NULL,
1959 .write_nvram = NULL,
a1b23c5a 1960 .fw_dump = qla8044_fw_dump,
7ec0effd
AD		 1961 .beacon_on = qla82xx_beacon_on,
1962 .beacon_off = qla82xx_beacon_off,
1963 .beacon_blink = NULL,
888e639d 1964 .read_optrom = qla8044_read_optrom_data,
7ec0effd
AD		 1965 .write_optrom = qla8044_write_optrom_data,
1966 .get_flash_version = qla82xx_get_flash_version,
1967 .start_scsi = qla82xx_start_scsi,
1968 .abort_isp = qla8044_abort_isp,
1969 .iospace_config = qla82xx_iospace_config,
1970 .initialize_adapter = qla2x00_initialize_adapter,
1971};
1972
6246b8a1
GM		 1973static struct isp_operations qla83xx_isp_ops = {
1974 .pci_config = qla25xx_pci_config,
1975 .reset_chip = qla24xx_reset_chip,
1976 .chip_diag = qla24xx_chip_diag,
1977 .config_rings = qla24xx_config_rings,
1978 .reset_adapter = qla24xx_reset_adapter,
1979 .nvram_config = qla81xx_nvram_config,
1980 .update_fw_options = qla81xx_update_fw_options,
1981 .load_risc = qla81xx_load_risc,
1982 .pci_info_str = qla24xx_pci_info_str,
1983 .fw_version_str = qla24xx_fw_version_str,
1984 .intr_handler = qla24xx_intr_handler,
1985 .enable_intrs = qla24xx_enable_intrs,
1986 .disable_intrs = qla24xx_disable_intrs,
1987 .abort_command = qla24xx_abort_command,
1988 .target_reset = qla24xx_abort_target,
1989 .lun_reset = qla24xx_lun_reset,
1990 .fabric_login = qla24xx_login_fabric,
1991 .fabric_logout = qla24xx_fabric_logout,
1992 .calc_req_entries = NULL,
1993 .build_iocbs = NULL,
1994 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1995 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1996 .read_nvram = NULL,
1997 .write_nvram = NULL,
1998 .fw_dump = qla83xx_fw_dump,
1999 .beacon_on = qla24xx_beacon_on,
2000 .beacon_off = qla24xx_beacon_off,
2001 .beacon_blink = qla83xx_beacon_blink,
2002 .read_optrom = qla25xx_read_optrom_data,
2003 .write_optrom = qla24xx_write_optrom_data,
2004 .get_flash_version = qla24xx_get_flash_version,
2005 .start_scsi = qla24xx_dif_start_scsi,
2006 .abort_isp = qla2x00_abort_isp,
2007 .iospace_config = qla83xx_iospace_config,
8ae6d9c7
GM		 2008 .initialize_adapter = qla2x00_initialize_adapter,
2009};
2010
2011static struct isp_operations qlafx00_isp_ops = {
2012 .pci_config = qlafx00_pci_config,
2013 .reset_chip = qlafx00_soft_reset,
2014 .chip_diag = qlafx00_chip_diag,
2015 .config_rings = qlafx00_config_rings,
2016 .reset_adapter = qlafx00_soft_reset,
2017 .nvram_config = NULL,
2018 .update_fw_options = NULL,
2019 .load_risc = NULL,
2020 .pci_info_str = qlafx00_pci_info_str,
2021 .fw_version_str = qlafx00_fw_version_str,
2022 .intr_handler = qlafx00_intr_handler,
2023 .enable_intrs = qlafx00_enable_intrs,
2024 .disable_intrs = qlafx00_disable_intrs,
4440e46d 2025 .abort_command = qla24xx_async_abort_command,
8ae6d9c7
GM		 2026 .target_reset = qlafx00_abort_target,
2027 .lun_reset = qlafx00_lun_reset,
2028 .fabric_login = NULL,
2029 .fabric_logout = NULL,
2030 .calc_req_entries = NULL,
2031 .build_iocbs = NULL,
2032 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2033 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2034 .read_nvram = qla24xx_read_nvram_data,
2035 .write_nvram = qla24xx_write_nvram_data,
2036 .fw_dump = NULL,
2037 .beacon_on = qla24xx_beacon_on,
2038 .beacon_off = qla24xx_beacon_off,
2039 .beacon_blink = NULL,
2040 .read_optrom = qla24xx_read_optrom_data,
2041 .write_optrom = qla24xx_write_optrom_data,
2042 .get_flash_version = qla24xx_get_flash_version,
2043 .start_scsi = qlafx00_start_scsi,
2044 .abort_isp = qlafx00_abort_isp,
2045 .iospace_config = qlafx00_iospace_config,
2046 .initialize_adapter = qlafx00_initialize_adapter,
6246b8a1
GM		 2047};
2048
f73cb695
CD		 2049static struct isp_operations qla27xx_isp_ops = {
2050 .pci_config = qla25xx_pci_config,
2051 .reset_chip = qla24xx_reset_chip,
2052 .chip_diag = qla24xx_chip_diag,
2053 .config_rings = qla24xx_config_rings,
2054 .reset_adapter = qla24xx_reset_adapter,
2055 .nvram_config = qla81xx_nvram_config,
2056 .update_fw_options = qla81xx_update_fw_options,
2057 .load_risc = qla81xx_load_risc,
2058 .pci_info_str = qla24xx_pci_info_str,
2059 .fw_version_str = qla24xx_fw_version_str,
2060 .intr_handler = qla24xx_intr_handler,
2061 .enable_intrs = qla24xx_enable_intrs,
2062 .disable_intrs = qla24xx_disable_intrs,
2063 .abort_command = qla24xx_abort_command,
2064 .target_reset = qla24xx_abort_target,
2065 .lun_reset = qla24xx_lun_reset,
2066 .fabric_login = qla24xx_login_fabric,
2067 .fabric_logout = qla24xx_fabric_logout,
2068 .calc_req_entries = NULL,
2069 .build_iocbs = NULL,
2070 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2071 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2072 .read_nvram = NULL,
2073 .write_nvram = NULL,
2074 .fw_dump = qla27xx_fwdump,
2075 .beacon_on = qla24xx_beacon_on,
2076 .beacon_off = qla24xx_beacon_off,
2077 .beacon_blink = qla83xx_beacon_blink,
2078 .read_optrom = qla25xx_read_optrom_data,
2079 .write_optrom = qla24xx_write_optrom_data,
2080 .get_flash_version = qla24xx_get_flash_version,
2081 .start_scsi = qla24xx_dif_start_scsi,
2082 .abort_isp = qla2x00_abort_isp,
2083 .iospace_config = qla83xx_iospace_config,
2084 .initialize_adapter = qla2x00_initialize_adapter,
2085};
2086
ea5b6382 2087static inline void
e315cd28 2088qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382
AV		 2089{
2090 ha->device_type = DT_EXTENDED_IDS;
2091 switch (ha->pdev->device) {
2092 case PCI_DEVICE_ID_QLOGIC_ISP2100:
2093 ha->device_type |= DT_ISP2100;
2094 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2095 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2096 break;
2097 case PCI_DEVICE_ID_QLOGIC_ISP2200:
2098 ha->device_type |= DT_ISP2200;
2099 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2100 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2101 break;
2102 case PCI_DEVICE_ID_QLOGIC_ISP2300:
2103 ha->device_type |= DT_ISP2300;
4a59f71d 2104 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2105 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2106 break;
2107 case PCI_DEVICE_ID_QLOGIC_ISP2312:
2108 ha->device_type |= DT_ISP2312;
4a59f71d 2109 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2110 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2111 break;
2112 case PCI_DEVICE_ID_QLOGIC_ISP2322:
2113 ha->device_type |= DT_ISP2322;
4a59f71d 2114 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382
AV		 2115 if (ha->pdev->subsystem_vendor == 0x1028 &&
2116 ha->pdev->subsystem_device == 0x0170)
2117 ha->device_type |= DT_OEM_001;
441d1072 2118 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2119 break;
2120 case PCI_DEVICE_ID_QLOGIC_ISP6312:
2121 ha->device_type |= DT_ISP6312;
441d1072 2122 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2123 break;
2124 case PCI_DEVICE_ID_QLOGIC_ISP6322:
2125 ha->device_type |= DT_ISP6322;
441d1072 2126 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2127 break;
2128 case PCI_DEVICE_ID_QLOGIC_ISP2422:
2129 ha->device_type |= DT_ISP2422;
4a59f71d 2130 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2131 ha->device_type |= DT_FWI2;
c76f2c01 2132 ha->device_type |= DT_IIDMA;
441d1072 2133 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382
AV		 2134 break;
2135 case PCI_DEVICE_ID_QLOGIC_ISP2432:
2136 ha->device_type |= DT_ISP2432;
4a59f71d 2137 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2138 ha->device_type |= DT_FWI2;
c76f2c01 2139 ha->device_type |= DT_IIDMA;
441d1072 2140 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2141 break;
4d4df193
HK		 2142 case PCI_DEVICE_ID_QLOGIC_ISP8432:
2143 ha->device_type |= DT_ISP8432;
2144 ha->device_type |= DT_ZIO_SUPPORTED;
2145 ha->device_type |= DT_FWI2;
2146 ha->device_type |= DT_IIDMA;
2147 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2148 break;
044cc6c8
AV		 2149 case PCI_DEVICE_ID_QLOGIC_ISP5422:
2150 ha->device_type |= DT_ISP5422;
e428924c 2151 ha->device_type |= DT_FWI2;
441d1072 2152 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2153 break;
044cc6c8
AV		 2154 case PCI_DEVICE_ID_QLOGIC_ISP5432:
2155 ha->device_type |= DT_ISP5432;
e428924c 2156 ha->device_type |= DT_FWI2;
441d1072 2157 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2158 break;
c3a2f0df
AV		 2159 case PCI_DEVICE_ID_QLOGIC_ISP2532:
2160 ha->device_type |= DT_ISP2532;
2161 ha->device_type |= DT_ZIO_SUPPORTED;
2162 ha->device_type |= DT_FWI2;
2163 ha->device_type |= DT_IIDMA;
441d1072 2164 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2165 break;
3a03eb79
AV		 2166 case PCI_DEVICE_ID_QLOGIC_ISP8001:
2167 ha->device_type |= DT_ISP8001;
2168 ha->device_type |= DT_ZIO_SUPPORTED;
2169 ha->device_type |= DT_FWI2;
2170 ha->device_type |= DT_IIDMA;
2171 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2172 break;
a9083016
GM		 2173 case PCI_DEVICE_ID_QLOGIC_ISP8021:
2174 ha->device_type |= DT_ISP8021;
2175 ha->device_type |= DT_ZIO_SUPPORTED;
2176 ha->device_type |= DT_FWI2;
2177 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2178 /* Initialize 82XX ISP flags */
2179 qla82xx_init_flags(ha);
2180 break;
7ec0effd
AD		 2181 case PCI_DEVICE_ID_QLOGIC_ISP8044:
2182 ha->device_type |= DT_ISP8044;
2183 ha->device_type |= DT_ZIO_SUPPORTED;
2184 ha->device_type |= DT_FWI2;
2185 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2186 /* Initialize 82XX ISP flags */
2187 qla82xx_init_flags(ha);
2188 break;
6246b8a1
GM		 2189 case PCI_DEVICE_ID_QLOGIC_ISP2031:
2190 ha->device_type |= DT_ISP2031;
2191 ha->device_type |= DT_ZIO_SUPPORTED;
2192 ha->device_type |= DT_FWI2;
2193 ha->device_type |= DT_IIDMA;
2194 ha->device_type |= DT_T10_PI;
2195 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2196 break;
2197 case PCI_DEVICE_ID_QLOGIC_ISP8031:
2198 ha->device_type |= DT_ISP8031;
2199 ha->device_type |= DT_ZIO_SUPPORTED;
2200 ha->device_type |= DT_FWI2;
2201 ha->device_type |= DT_IIDMA;
2202 ha->device_type |= DT_T10_PI;
2203 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2204 break;
8ae6d9c7
GM		 2205 case PCI_DEVICE_ID_QLOGIC_ISPF001:
2206 ha->device_type |= DT_ISPFX00;
2207 break;
f73cb695
CD		 2208 case PCI_DEVICE_ID_QLOGIC_ISP2071:
2209 ha->device_type |= DT_ISP2071;
2210 ha->device_type |= DT_ZIO_SUPPORTED;
2211 ha->device_type |= DT_FWI2;
2212 ha->device_type |= DT_IIDMA;
2213 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2214 break;
2c5bbbb2
JC		 2215 case PCI_DEVICE_ID_QLOGIC_ISP2271:
2216 ha->device_type |= DT_ISP2271;
2217 ha->device_type |= DT_ZIO_SUPPORTED;
2218 ha->device_type |= DT_FWI2;
2219 ha->device_type |= DT_IIDMA;
2220 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2221 break;
2b48992f
SC		 2222 case PCI_DEVICE_ID_QLOGIC_ISP2261:
2223 ha->device_type |= DT_ISP2261;
2224 ha->device_type |= DT_ZIO_SUPPORTED;
2225 ha->device_type |= DT_FWI2;
2226 ha->device_type |= DT_IIDMA;
2227 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2228 break;
ea5b6382 2229 }
e5b68a61 2230
a9083016 2231 if (IS_QLA82XX(ha))
43a9c38b 2232 ha->port_no = ha->portnum & 1;
f73cb695 2233 else {
a9083016
GM		 2234 /* Get adapter physical port no from interrupt pin register. */
2235 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
f73cb695
CD		 2236 if (IS_QLA27XX(ha))
2237 ha->port_no--;
2238 else
2239 ha->port_no = !(ha->port_no & 1);
2240 }
a9083016 2241
7c3df132 2242 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2243 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
f73cb695 2244 ha->device_type, ha->port_no, ha->fw_srisc_address);
ea5b6382
AV		 2245}
2246
1e99e33a
AV		 2247static void
2248qla2xxx_scan_start(struct Scsi_Host *shost)
2249{
e315cd28 2250 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2251
cbc8eb67
AV		 2252 if (vha->hw->flags.running_gold_fw)
2253 return;
2254
e315cd28
AC		 2255 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2256 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2257 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2258 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2259}
2260
2261static int
2262qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2263{
e315cd28 2264 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2265
e315cd28 2266 if (!vha->host)
1e99e33a 2267 return 1;
e315cd28 2268 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2269 return 1;
2270
e315cd28 2271 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2272}
2273
1da177e4
LT		 2274/*
2275 * PCI driver interface
2276 */
6f039790 2277static int
7ee61397 2278qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2279{
a1541d5a 2280 int ret = -ENODEV;
1da177e4 2281 struct Scsi_Host *host;
e315cd28
AC		 2282 scsi_qla_host_t *base_vha = NULL;
2283 struct qla_hw_data *ha;
29856e28 2284 char pci_info[30];
7d613ac6 2285 char fw_str[30], wq_name[30];
5433383e 2286 struct scsi_host_template *sht;
642ef983 2287 int bars, mem_only = 0;
e315cd28 2288 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2289 struct req_que *req = NULL;
2290 struct rsp_que *rsp = NULL;
285d0321 2291 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2292 sht = &qla2xxx_driver_template;
5433383e 2293 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2294 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2295 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2296 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2297 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2298 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2299 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2300 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2301 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
8ae6d9c7 2302 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
7ec0effd 2303 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
f73cb695 2304 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2c5bbbb2 2305 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2b48992f
SC		 2306 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
2307 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) {
285d0321 2308 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2309 mem_only = 1;
7c3df132
SK		 2310 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2311 "Mem only adapter.\n");
285d0321 2312 }
7c3df132
SK		 2313 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2314 "Bars=%d.\n", bars);
285d0321 2315
09483916
BH		 2316 if (mem_only) {
2317 if (pci_enable_device_mem(pdev))
2318 goto probe_out;
2319 } else {
2320 if (pci_enable_device(pdev))
2321 goto probe_out;
2322 }
285d0321 2323
0927678f
JB		 2324 /* This may fail but that's ok */
2325 pci_enable_pcie_error_reporting(pdev);
285d0321 2326
e315cd28
AC		 2327 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2328 if (!ha) {
7c3df132
SK		 2329 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2330 "Unable to allocate memory for ha.\n");
e315cd28 2331 goto probe_out;
1da177e4 2332 }
7c3df132
SK		 2333 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2334 "Memory allocated for ha=%p.\n", ha);
e315cd28 2335 ha->pdev = pdev;
2d70c103 2336 ha->tgt.enable_class_2 = ql2xenableclass2;
33e79977
QT		 2337 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2338 spin_lock_init(&ha->tgt.q_full_lock);
1da177e4
LT		 2339
2340 /* Clear our data area */
285d0321 2341 ha->bars = bars;
09483916 2342 ha->mem_only = mem_only;
df4bf0bb 2343 spin_lock_init(&ha->hardware_lock);
339aa70e 2344 spin_lock_init(&ha->vport_slock);
a9b6f722 2345 mutex_init(&ha->selflogin_lock);
7a8ab9c8 2346 mutex_init(&ha->optrom_mutex);
1da177e4 2347
ea5b6382
AV		 2348 /* Set ISP-type information. */
2349 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2350
2351 /* Set EEH reset type to fundamental if required by hba */
95676112 2352 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
f73cb695 2353 IS_QLA83XX(ha) || IS_QLA27XX(ha))
ca79cf66 2354 pdev->needs_freset = 1;
ca79cf66 2355
cba1e47f
CD		 2356 ha->prev_topology = 0;
2357 ha->init_cb_size = sizeof(init_cb_t);
2358 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2359 ha->optrom_size = OPTROM_SIZE_2300;
2360
abbd8870 2361 /* Assign ISP specific operations. */
1da177e4 2362 if (IS_QLA2100(ha)) {
642ef983 2363 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2364 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2365 req_length = REQUEST_ENTRY_CNT_2100;
2366 rsp_length = RESPONSE_ENTRY_CNT_2100;
2367 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2368 ha->gid_list_info_size = 4;
3a03eb79
AV		 2369 ha->flash_conf_off = ~0;
2370 ha->flash_data_off = ~0;
2371 ha->nvram_conf_off = ~0;
2372 ha->nvram_data_off = ~0;
fd34f556 2373 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2374 } else if (IS_QLA2200(ha)) {
642ef983 2375 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2376 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2377 req_length = REQUEST_ENTRY_CNT_2200;
2378 rsp_length = RESPONSE_ENTRY_CNT_2100;
2379 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2380 ha->gid_list_info_size = 4;
3a03eb79
AV		 2381 ha->flash_conf_off = ~0;
2382 ha->flash_data_off = ~0;
2383 ha->nvram_conf_off = ~0;
2384 ha->nvram_data_off = ~0;
fd34f556 2385 ha->isp_ops = &qla2100_isp_ops;
fca29703 2386 } else if (IS_QLA23XX(ha)) {
642ef983 2387 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2388 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2389 req_length = REQUEST_ENTRY_CNT_2200;
2390 rsp_length = RESPONSE_ENTRY_CNT_2300;
2391 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2392 ha->gid_list_info_size = 6;
854165f4
AV		 2393 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2394 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2395 ha->flash_conf_off = ~0;
2396 ha->flash_data_off = ~0;
2397 ha->nvram_conf_off = ~0;
2398 ha->nvram_data_off = ~0;
fd34f556 2399 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2400 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2401 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2402 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2403 req_length = REQUEST_ENTRY_CNT_24XX;
2404 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2405 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2406 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2407 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2408 ha->gid_list_info_size = 8;
854165f4 2409 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2410 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2411 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2412 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2413 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2414 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2415 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2416 } else if (IS_QLA25XX(ha)) {
642ef983 2417 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2418 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2419 req_length = REQUEST_ENTRY_CNT_24XX;
2420 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2421 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2422 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2423 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2424 ha->gid_list_info_size = 8;
2425 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2426 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2427 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2428 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2429 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2430 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2431 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2432 } else if (IS_QLA81XX(ha)) {
642ef983 2433 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2434 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2435 req_length = REQUEST_ENTRY_CNT_24XX;
2436 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 2437 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 2438 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2439 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2440 ha->gid_list_info_size = 8;
2441 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2442 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2443 ha->isp_ops = &qla81xx_isp_ops;
2444 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2445 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2446 ha->nvram_conf_off = ~0;
2447 ha->nvram_data_off = ~0;
a9083016 2448 } else if (IS_QLA82XX(ha)) {
642ef983 2449 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2450 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2451 req_length = REQUEST_ENTRY_CNT_82XX;
2452 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2453 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2454 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2455 ha->gid_list_info_size = 8;
2456 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2457 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2458 ha->isp_ops = &qla82xx_isp_ops;
2459 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2460 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2461 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2462 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
7ec0effd
AD		 2463 } else if (IS_QLA8044(ha)) {
2464 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2465 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2466 req_length = REQUEST_ENTRY_CNT_82XX;
2467 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2468 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2469 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2470 ha->gid_list_info_size = 8;
2471 ha->optrom_size = OPTROM_SIZE_83XX;
2472 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2473 ha->isp_ops = &qla8044_isp_ops;
2474 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2475 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2476 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2477 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 2478 } else if (IS_QLA83XX(ha)) {
7d613ac6 2479 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 2480 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1 2481 ha->mbx_count = MAILBOX_REGISTER_COUNT;
f2ea653f 2482 req_length = REQUEST_ENTRY_CNT_83XX;
6246b8a1 2483 rsp_length = RESPONSE_ENTRY_CNT_2300;
b8aa4bdf 2484 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 2485 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2486 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2487 ha->gid_list_info_size = 8;
2488 ha->optrom_size = OPTROM_SIZE_83XX;
2489 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2490 ha->isp_ops = &qla83xx_isp_ops;
2491 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2492 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2493 ha->nvram_conf_off = ~0;
2494 ha->nvram_data_off = ~0;
8ae6d9c7
GM		 2495 } else if (IS_QLAFX00(ha)) {
2496 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2497 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2498 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2499 req_length = REQUEST_ENTRY_CNT_FX00;
2500 rsp_length = RESPONSE_ENTRY_CNT_FX00;
8ae6d9c7
GM		 2501 ha->isp_ops = &qlafx00_isp_ops;
2502 ha->port_down_retry_count = 30; /* default value */
2503 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2504 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
71e56003 2505 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
8ae6d9c7 2506 ha->mr.fw_hbt_en = 1;
e8f5e95d
AB		 2507 ha->mr.host_info_resend = false;
2508 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
f73cb695
CD		 2509 } else if (IS_QLA27XX(ha)) {
2510 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2511 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2512 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2513 req_length = REQUEST_ENTRY_CNT_24XX;
2514 rsp_length = RESPONSE_ENTRY_CNT_2300;
b20f02e1 2515 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
f73cb695
CD		 2516 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2517 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2518 ha->gid_list_info_size = 8;
2519 ha->optrom_size = OPTROM_SIZE_83XX;
2520 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2521 ha->isp_ops = &qla27xx_isp_ops;
2522 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2523 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2524 ha->nvram_conf_off = ~0;
2525 ha->nvram_data_off = ~0;
1da177e4 2526 }
6246b8a1 2527
7c3df132
SK		 2528 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2529 "mbx_count=%d, req_length=%d, "
2530 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 2531 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2532 "max_fibre_devices=%d.\n",
7c3df132
SK		 2533 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2534 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 2535 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 2536 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2537 "isp_ops=%p, flash_conf_off=%d, "
2538 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2539 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2540 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 2541
2542 /* Configure PCI I/O space */
2543 ret = ha->isp_ops->iospace_config(ha);
2544 if (ret)
0a63ad12 2545 goto iospace_config_failed;
706f457d
GM		 2546
2547 ql_log_pci(ql_log_info, pdev, 0x001d,
2548 "Found an ISP%04X irq %d iobase 0x%p.\n",
2549 pdev->device, pdev->irq, ha->iobase);
6c2f527c 2550 mutex_init(&ha->vport_lock);
0b05a1f0
MB		 2551 init_completion(&ha->mbx_cmd_comp);
2552 complete(&ha->mbx_cmd_comp);
2553 init_completion(&ha->mbx_intr_comp);
23f2ebd1 2554 init_completion(&ha->dcbx_comp);
f356bef1 2555 init_completion(&ha->lb_portup_comp);
1da177e4 2556
2c3dfe3f 2557 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 2558
53303c42 2559 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 2560 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2561 "64 Bit addressing is %s.\n",
2562 ha->flags.enable_64bit_addressing ? "enable" :
2563 "disable");
73208dfd 2564 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
b2a72ec3 2565 if (ret) {
7c3df132
SK		 2566 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2567 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 2568
e315cd28
AC		 2569 goto probe_hw_failed;
2570 }
2571
73208dfd 2572 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 2573 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 2574 req->max_q_depth = ql2xmaxqdepth;
2575
e315cd28
AC		 2576
2577 base_vha = qla2x00_create_host(sht, ha);
2578 if (!base_vha) {
a1541d5a 2579 ret = -ENOMEM;
6e9f21f3 2580 qla2x00_mem_free(ha);
2afa19a9
AC		 2581 qla2x00_free_req_que(ha, req);
2582 qla2x00_free_rsp_que(ha, rsp);
e315cd28 2583 goto probe_hw_failed;
1da177e4
LT		 2584 }
2585
e315cd28 2586 pci_set_drvdata(pdev, base_vha);
6b383979 2587 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
e315cd28 2588
e315cd28 2589 host = base_vha->host;
2afa19a9 2590 base_vha->req = req;
73208dfd 2591 if (IS_QLA2XXX_MIDTYPE(ha))
e315cd28 2592 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
73208dfd 2593 else
e315cd28
AC		 2594 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2595 base_vha->vp_idx;
58548cb5 2596
8ae6d9c7
GM		 2597 /* Setup fcport template structure. */
2598 ha->mr.fcport.vha = base_vha;
2599 ha->mr.fcport.port_type = FCT_UNKNOWN;
2600 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
2601 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
2602 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
2603 ha->mr.fcport.scan_state = 1;
2604
58548cb5
GM		 2605 /* Set the SG table size based on ISP type */
2606 if (!IS_FWI2_CAPABLE(ha)) {
2607 if (IS_QLA2100(ha))
2608 host->sg_tablesize = 32;
2609 } else {
2610 if (!IS_QLA82XX(ha))
2611 host->sg_tablesize = QLA_SG_ALL;
2612 }
642ef983 2613 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 2614 host->cmd_per_lun = 3;
2615 host->unique_id = host->host_no;
e02587d7 2616 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 2617 host->max_cmd_len = 32;
2618 else
2619 host->max_cmd_len = MAX_CMDSZ;
e315cd28 2620 host->max_channel = MAX_BUSES - 1;
755f516b
HR		 2621 /* Older HBAs support only 16-bit LUNs */
2622 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
2623 ql2xmaxlun > 0xffff)
2624 host->max_lun = 0xffff;
2625 else
2626 host->max_lun = ql2xmaxlun;
e315cd28 2627 host->transportt = qla2xxx_transport_template;
9a069e19 2628 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 2629
7c3df132
SK		 2630 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2631 "max_id=%d this_id=%d "
2632 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
1abf635d 2633 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 2634 host->this_id, host->cmd_per_lun, host->unique_id,
2635 host->max_cmd_len, host->max_channel, host->max_lun,
2636 host->transportt, sht->vendor_id);
2637
9a347ff4
CD		 2638que_init:
2639 /* Alloc arrays of request and response ring ptrs */
2640 if (!qla2x00_alloc_queues(ha, req, rsp)) {
2641 ql_log(ql_log_fatal, base_vha, 0x003d,
2642 "Failed to allocate memory for queue pointers..."
2643 "aborting.\n");
2644 goto probe_init_failed;
2645 }
2646
2d70c103 2647 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 2648
73208dfd
AC		 2649 /* Set up the irqs */
2650 ret = qla2x00_request_irqs(ha, rsp);
2651 if (ret)
6e9f21f3 2652 goto probe_init_failed;
90a86fc0
JC		 2653
2654 pci_save_state(pdev);
2655
9a347ff4 2656 /* Assign back pointers */
2afa19a9
AC		 2657 rsp->req = req;
2658 req->rsp = rsp;
9a347ff4 2659
8ae6d9c7
GM		 2660 if (IS_QLAFX00(ha)) {
2661 ha->rsp_q_map[0] = rsp;
2662 ha->req_q_map[0] = req;
2663 set_bit(0, ha->req_qid_map);
2664 set_bit(0, ha->rsp_qid_map);
2665 }
2666
08029990
AV		 2667 /* FWI2-capable only. */
2668 req->req_q_in = &ha->iobase->isp24.req_q_in;
2669 req->req_q_out = &ha->iobase->isp24.req_q_out;
2670 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2671 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
f73cb695 2672 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
08029990
AV		 2673 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2674 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2675 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
2676 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 2677 }
2678
8ae6d9c7
GM		 2679 if (IS_QLAFX00(ha)) {
2680 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
2681 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
2682 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
2683 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
2684 }
2685
7ec0effd 2686 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 2687 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
2688 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
2689 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
2690 }
2691
7c3df132
SK		 2692 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
2693 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2694 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2695 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
2696 "req->req_q_in=%p req->req_q_out=%p "
2697 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2698 req->req_q_in, req->req_q_out,
2699 rsp->rsp_q_in, rsp->rsp_q_out);
2700 ql_dbg(ql_dbg_init, base_vha, 0x003e,
2701 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2702 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2703 ql_dbg(ql_dbg_init, base_vha, 0x003f,
2704 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2705 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 2706
8ae6d9c7 2707 if (ha->isp_ops->initialize_adapter(base_vha)) {
7c3df132
SK		 2708 ql_log(ql_log_fatal, base_vha, 0x00d6,
2709 "Failed to initialize adapter - Adapter flags %x.\n",
2710 base_vha->device_flags);
1da177e4 2711
a9083016
GM		 2712 if (IS_QLA82XX(ha)) {
2713 qla82xx_idc_lock(ha);
2714 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 2715 QLA8XXX_DEV_FAILED);
a9083016 2716 qla82xx_idc_unlock(ha);
7c3df132
SK		 2717 ql_log(ql_log_fatal, base_vha, 0x00d7,
2718 "HW State: FAILED.\n");
7ec0effd
AD		 2719 } else if (IS_QLA8044(ha)) {
2720 qla8044_idc_lock(ha);
2721 qla8044_wr_direct(base_vha,
2722 QLA8044_CRB_DEV_STATE_INDEX,
2723 QLA8XXX_DEV_FAILED);
2724 qla8044_idc_unlock(ha);
2725 ql_log(ql_log_fatal, base_vha, 0x0150,
2726 "HW State: FAILED.\n");
a9083016
GM		 2727 }
2728
a1541d5a 2729 ret = -ENODEV;
1da177e4
LT		 2730 goto probe_failed;
2731 }
2732
3b1bef64
CD		 2733 if (IS_QLAFX00(ha))
2734 host->can_queue = QLAFX00_MAX_CANQUEUE;
2735 else
2736 host->can_queue = req->num_outstanding_cmds - 10;
2737
2738 ql_dbg(ql_dbg_init, base_vha, 0x0032,
2739 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
2740 host->can_queue, base_vha->req,
2741 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
2742
7163ea81
AC		 2743 if (ha->mqenable) {
2744 if (qla25xx_setup_mode(base_vha)) {
7c3df132
SK		 2745 ql_log(ql_log_warn, base_vha, 0x00ec,
2746 "Failed to create queues, falling back to single queue mode.\n");
7163ea81
AC		 2747 goto que_init;
2748 }
2749 }
68ca949c 2750
cbc8eb67
AV		 2751 if (ha->flags.running_gold_fw)
2752 goto skip_dpc;
2753
1da177e4
LT		 2754 /*
2755 * Startup the kernel thread for this host adapter
2756 */
39a11240 2757 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 2758 "%s_dpc", base_vha->host_str);
39a11240 2759 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 2760 ql_log(ql_log_fatal, base_vha, 0x00ed,
2761 "Failed to start DPC thread.\n");
39a11240 2762 ret = PTR_ERR(ha->dpc_thread);
1da177e4
LT		 2763 goto probe_failed;
2764 }
7c3df132
SK		 2765 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
2766 "DPC thread started successfully.\n");
1da177e4 2767
2d70c103
NB		 2768 /*
2769 * If we're not coming up in initiator mode, we might sit for
2770 * a while without waking up the dpc thread, which leads to a
2771 * stuck process warning. So just kick the dpc once here and
2772 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
2773 */
2774 qla2xxx_wake_dpc(base_vha);
2775
f3ddac19
CD		 2776 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
2777
81178772
SK		 2778 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
2779 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
2780 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
2781 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
2782
2783 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
2784 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
2785 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
2786 INIT_WORK(&ha->idc_state_handler,
2787 qla83xx_idc_state_handler_work);
2788 INIT_WORK(&ha->nic_core_unrecoverable,
2789 qla83xx_nic_core_unrecoverable_work);
2790 }
2791
cbc8eb67 2792skip_dpc:
e315cd28
AC		 2793 list_add_tail(&base_vha->list, &ha->vp_list);
2794 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 2795
2796 /* Initialized the timer */
e315cd28 2797 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
7c3df132
SK		 2798 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
2799 "Started qla2x00_timer with "
2800 "interval=%d.\n", WATCH_INTERVAL);
2801 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
2802 "Detected hba at address=%p.\n",
2803 ha);
d19044c3 2804
e02587d7 2805 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 2806 if (ha->fw_attributes & BIT_4) {
9e522cd8 2807 int prot = 0, guard;
bad75002 2808 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 2809 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
2810 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 2811 if (ql2xenabledif == 1)
2812 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 2813 scsi_host_set_prot(host,
8cb2049c 2814 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 2815 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 2816 | SHOST_DIF_TYPE3_PROTECTION
2817 | SHOST_DIX_TYPE1_PROTECTION
0c470874 2818 | SHOST_DIX_TYPE2_PROTECTION
bad75002 2819 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 2820
2821 guard = SHOST_DIX_GUARD_CRC;
2822
2823 if (IS_PI_IPGUARD_CAPABLE(ha) &&
2824 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
2825 guard |= SHOST_DIX_GUARD_IP;
2826
2827 scsi_host_set_guard(host, guard);
bad75002
AE		 2828 } else
2829 base_vha->flags.difdix_supported = 0;
2830 }
2831
a9083016
GM		 2832 ha->isp_ops->enable_intrs(ha);
2833
1fe19ee4
AB		 2834 if (IS_QLAFX00(ha)) {
2835 ret = qlafx00_fx_disc(base_vha,
2836 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
2837 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
2838 QLA_SG_ALL : 128;
2839 }
2840
a1541d5a
AV		 2841 ret = scsi_add_host(host, &pdev->dev);
2842 if (ret)
2843 goto probe_failed;
2844
1486400f
MR		 2845 base_vha->flags.init_done = 1;
2846 base_vha->flags.online = 1;
edaa5c74 2847 ha->prev_minidump_failed = 0;
1486400f 2848
7c3df132
SK		 2849 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
2850 "Init done and hba is online.\n");
2851
2d70c103
NB		 2852 if (qla_ini_mode_enabled(base_vha))
2853 scsi_scan_host(host);
2854 else
2855 ql_dbg(ql_dbg_init, base_vha, 0x0122,
2856 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 2857
e315cd28 2858 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 2859
8ae6d9c7 2860 if (IS_QLAFX00(ha)) {
8ae6d9c7
GM		 2861 ret = qlafx00_fx_disc(base_vha,
2862 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
2863
2864 /* Register system information */
2865 ret = qlafx00_fx_disc(base_vha,
2866 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
2867 }
2868
e315cd28 2869 qla2x00_init_host_attr(base_vha);
a1541d5a 2870
e315cd28 2871 qla2x00_dfs_setup(base_vha);
df613b96 2872
03eb912a
AB		 2873 ql_log(ql_log_info, base_vha, 0x00fb,
2874 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
7c3df132
SK		 2875 ql_log(ql_log_info, base_vha, 0x00fc,
2876 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
2877 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
2878 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
2879 base_vha->host_no,
df57caba 2880 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
1da177e4 2881
2d70c103
NB		 2882 qlt_add_target(ha, base_vha);
2883
6b383979 2884 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
1da177e4
LT		 2885 return 0;
2886
6e9f21f3 2887probe_init_failed:
2afa19a9 2888 qla2x00_free_req_que(ha, req);
9a347ff4
CD		 2889 ha->req_q_map[0] = NULL;
2890 clear_bit(0, ha->req_qid_map);
2afa19a9 2891 qla2x00_free_rsp_que(ha, rsp);
9a347ff4
CD		 2892 ha->rsp_q_map[0] = NULL;
2893 clear_bit(0, ha->rsp_qid_map);
2afa19a9 2894 ha->max_req_queues = ha->max_rsp_queues = 0;
6e9f21f3 2895
1da177e4 2896probe_failed:
b9978769
AV		 2897 if (base_vha->timer_active)
2898 qla2x00_stop_timer(base_vha);
2899 base_vha->flags.online = 0;
2900 if (ha->dpc_thread) {
2901 struct task_struct *t = ha->dpc_thread;
2902
2903 ha->dpc_thread = NULL;
2904 kthread_stop(t);
2905 }
2906
e315cd28 2907 qla2x00_free_device(base_vha);
1da177e4 2908
e315cd28 2909 scsi_host_put(base_vha->host);
1da177e4 2910
e315cd28 2911probe_hw_failed:
1a2fbf18
JL		 2912 qla2x00_clear_drv_active(ha);
2913
0a63ad12 2914iospace_config_failed:
7ec0effd 2915 if (IS_P3P_TYPE(ha)) {
0a63ad12 2916 if (!ha->nx_pcibase)
f73cb695 2917 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 2918 if (!ql2xdbwr)
f73cb695 2919 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 2920 } else {
2921 if (ha->iobase)
2922 iounmap(ha->iobase);
8ae6d9c7
GM		 2923 if (ha->cregbase)
2924 iounmap(ha->cregbase);
a9083016 2925 }
e315cd28
AC		 2926 pci_release_selected_regions(ha->pdev, ha->bars);
2927 kfree(ha);
2928 ha = NULL;
1da177e4 2929
a1541d5a 2930probe_out:
e315cd28 2931 pci_disable_device(pdev);
a1541d5a 2932 return ret;
1da177e4 2933}
1da177e4 2934
e30d1756
MI		 2935static void
2936qla2x00_shutdown(struct pci_dev *pdev)
2937{
2938 scsi_qla_host_t *vha;
2939 struct qla_hw_data *ha;
2940
552f3f9a
MI		 2941 if (!atomic_read(&pdev->enable_cnt))
2942 return;
2943
e30d1756
MI		 2944 vha = pci_get_drvdata(pdev);
2945 ha = vha->hw;
2946
42479343
AB		 2947 /* Notify ISPFX00 firmware */
2948 if (IS_QLAFX00(ha))
2949 qlafx00_driver_shutdown(vha, 20);
2950
e30d1756
MI		 2951 /* Turn-off FCE trace */
2952 if (ha->flags.fce_enabled) {
2953 qla2x00_disable_fce_trace(vha, NULL, NULL);
2954 ha->flags.fce_enabled = 0;
2955 }
2956
2957 /* Turn-off EFT trace */
2958 if (ha->eft)
2959 qla2x00_disable_eft_trace(vha);
2960
2961 /* Stop currently executing firmware. */
2962 qla2x00_try_to_stop_firmware(vha);
2963
2964 /* Turn adapter off line */
2965 vha->flags.online = 0;
2966
2967 /* turn-off interrupts on the card */
2968 if (ha->interrupts_on) {
2969 vha->flags.init_done = 0;
2970 ha->isp_ops->disable_intrs(ha);
2971 }
2972
2973 qla2x00_free_irqs(vha);
2974
2975 qla2x00_free_fw_dump(ha);
61d41f61
CD		 2976
2977 pci_disable_pcie_error_reporting(pdev);
2978 pci_disable_device(pdev);
e30d1756
MI		 2979}
2980
fe1b806f 2981/* Deletes all the virtual ports for a given ha */
4c993f76 2982static void
fe1b806f 2983qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
1da177e4 2984{
fe1b806f 2985 scsi_qla_host_t *vha;
feafb7b1 2986 unsigned long flags;
e315cd28 2987
43ebf16d
AE		 2988 mutex_lock(&ha->vport_lock);
2989 while (ha->cur_vport_count) {
43ebf16d 2990 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 2991
43ebf16d
AE		 2992 BUG_ON(base_vha->list.next == &ha->vp_list);
2993 /* This assumes first entry in ha->vp_list is always base vha */
2994 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
52c82823 2995 scsi_host_get(vha->host);
feafb7b1 2996
43ebf16d
AE		 2997 spin_unlock_irqrestore(&ha->vport_slock, flags);
2998 mutex_unlock(&ha->vport_lock);
2999
3000 fc_vport_terminate(vha->fc_vport);
3001 scsi_host_put(vha->host);
feafb7b1 3002
43ebf16d 3003 mutex_lock(&ha->vport_lock);
e315cd28 3004 }
43ebf16d 3005 mutex_unlock(&ha->vport_lock);
fe1b806f 3006}
1da177e4 3007
fe1b806f
CD		 3008/* Stops all deferred work threads */
3009static void
3010qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3011{
68ca949c
AC		 3012 /* Flush the work queue and remove it */
3013 if (ha->wq) {
3014 flush_workqueue(ha->wq);
3015 destroy_workqueue(ha->wq);
3016 ha->wq = NULL;
3017 }
3018
7d613ac6
SV		 3019 /* Cancel all work and destroy DPC workqueues */
3020 if (ha->dpc_lp_wq) {
3021 cancel_work_sync(&ha->idc_aen);
3022 destroy_workqueue(ha->dpc_lp_wq);
3023 ha->dpc_lp_wq = NULL;
3024 }
3025
3026 if (ha->dpc_hp_wq) {
3027 cancel_work_sync(&ha->nic_core_reset);
3028 cancel_work_sync(&ha->idc_state_handler);
3029 cancel_work_sync(&ha->nic_core_unrecoverable);
3030 destroy_workqueue(ha->dpc_hp_wq);
3031 ha->dpc_hp_wq = NULL;
3032 }
3033
b9978769
AV		 3034 /* Kill the kernel thread for this host */
3035 if (ha->dpc_thread) {
3036 struct task_struct *t = ha->dpc_thread;
3037
3038 /*
3039 * qla2xxx_wake_dpc checks for ->dpc_thread
3040 * so we need to zero it out.
3041 */
3042 ha->dpc_thread = NULL;
3043 kthread_stop(t);
3044 }
fe1b806f 3045}
1da177e4 3046
fe1b806f
CD		 3047static void
3048qla2x00_unmap_iobases(struct qla_hw_data *ha)
3049{
a9083016 3050 if (IS_QLA82XX(ha)) {
b963752f 3051
f73cb695 3052 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3053 if (!ql2xdbwr)
f73cb695 3054 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3055 } else {
3056 if (ha->iobase)
3057 iounmap(ha->iobase);
1da177e4 3058
8ae6d9c7
GM		 3059 if (ha->cregbase)
3060 iounmap(ha->cregbase);
3061
a9083016
GM		 3062 if (ha->mqiobase)
3063 iounmap(ha->mqiobase);
6246b8a1 3064
f73cb695 3065 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase)
6246b8a1 3066 iounmap(ha->msixbase);
a9083016 3067 }
fe1b806f
CD		 3068}
3069
3070static void
db7157d4 3071qla2x00_clear_drv_active(struct qla_hw_data *ha)
fe1b806f 3072{
fe1b806f
CD		 3073 if (IS_QLA8044(ha)) {
3074 qla8044_idc_lock(ha);
c41afc9a 3075 qla8044_clear_drv_active(ha);
fe1b806f
CD		 3076 qla8044_idc_unlock(ha);
3077 } else if (IS_QLA82XX(ha)) {
3078 qla82xx_idc_lock(ha);
3079 qla82xx_clear_drv_active(ha);
3080 qla82xx_idc_unlock(ha);
3081 }
3082}
3083
3084static void
3085qla2x00_remove_one(struct pci_dev *pdev)
3086{
3087 scsi_qla_host_t *base_vha;
3088 struct qla_hw_data *ha;
3089
beb9e315
JL		 3090 base_vha = pci_get_drvdata(pdev);
3091 ha = base_vha->hw;
3092
3093 /* Indicate device removal to prevent future board_disable and wait
3094 * until any pending board_disable has completed. */
3095 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3096 cancel_work_sync(&ha->board_disable);
3097
fe1b806f 3098 /*
beb9e315
JL		 3099 * If the PCI device is disabled then there was a PCI-disconnect and
3100 * qla2x00_disable_board_on_pci_error has taken care of most of the
3101 * resources.
fe1b806f 3102 */
beb9e315
JL		 3103 if (!atomic_read(&pdev->enable_cnt)) {
3104 scsi_host_put(base_vha->host);
3105 kfree(ha);
3106 pci_set_drvdata(pdev, NULL);
fe1b806f 3107 return;
beb9e315 3108 }
fe1b806f 3109
638a1a01
SC		 3110 qla2x00_wait_for_hba_ready(base_vha);
3111
fe1b806f
CD		 3112 set_bit(UNLOADING, &base_vha->dpc_flags);
3113
3114 if (IS_QLAFX00(ha))
3115 qlafx00_driver_shutdown(base_vha, 20);
3116
3117 qla2x00_delete_all_vps(ha, base_vha);
3118
3119 if (IS_QLA8031(ha)) {
3120 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3121 "Clearing fcoe driver presence.\n");
3122 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3123 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3124 "Error while clearing DRV-Presence.\n");
3125 }
3126
3127 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3128
3129 qla2x00_dfs_remove(base_vha);
3130
3131 qla84xx_put_chip(base_vha);
3132
2d5a4c34
HM		 3133 /* Laser should be disabled only for ISP2031 */
3134 if (IS_QLA2031(ha))
3135 qla83xx_disable_laser(base_vha);
3136
fe1b806f
CD		 3137 /* Disable timer */
3138 if (base_vha->timer_active)
3139 qla2x00_stop_timer(base_vha);
3140
3141 base_vha->flags.online = 0;
3142
b0d6cabd
HM		 3143 /* free DMA memory */
3144 if (ha->exlogin_buf)
3145 qla2x00_free_exlogin_buffer(ha);
3146
2f56a7f1
HM		 3147 /* free DMA memory */
3148 if (ha->exchoffld_buf)
3149 qla2x00_free_exchoffld_buffer(ha);
3150
fe1b806f
CD		 3151 qla2x00_destroy_deferred_work(ha);
3152
3153 qlt_remove_target(ha, base_vha);
3154
3155 qla2x00_free_sysfs_attr(base_vha, true);
3156
3157 fc_remove_host(base_vha->host);
3158
3159 scsi_remove_host(base_vha->host);
3160
3161 qla2x00_free_device(base_vha);
3162
db7157d4 3163 qla2x00_clear_drv_active(ha);
fe1b806f 3164
d2749ffa
AE		 3165 scsi_host_put(base_vha->host);
3166
fe1b806f 3167 qla2x00_unmap_iobases(ha);
73208dfd 3168
e315cd28
AC		 3169 pci_release_selected_regions(ha->pdev, ha->bars);
3170 kfree(ha);
3171 ha = NULL;
1da177e4 3172
90a86fc0
JC		 3173 pci_disable_pcie_error_reporting(pdev);
3174
665db93b 3175 pci_disable_device(pdev);
1da177e4 3176}
1da177e4
LT		 3177
3178static void
e315cd28 3179qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 3180{
e315cd28 3181 struct qla_hw_data *ha = vha->hw;
1da177e4 3182
85880801
AV		 3183 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3184
3185 /* Disable timer */
3186 if (vha->timer_active)
3187 qla2x00_stop_timer(vha);
3188
2afa19a9 3189 qla25xx_delete_queues(vha);
fe1b806f 3190
df613b96 3191 if (ha->flags.fce_enabled)
e315cd28 3192 qla2x00_disable_fce_trace(vha, NULL, NULL);
df613b96 3193
a7a167bf 3194 if (ha->eft)
e315cd28 3195 qla2x00_disable_eft_trace(vha);
a7a167bf 3196
f6ef3b18 3197 /* Stop currently executing firmware. */
e315cd28 3198 qla2x00_try_to_stop_firmware(vha);
1da177e4 3199
85880801
AV		 3200 vha->flags.online = 0;
3201
f6ef3b18 3202 /* turn-off interrupts on the card */
a9083016
GM		 3203 if (ha->interrupts_on) {
3204 vha->flags.init_done = 0;
fd34f556 3205 ha->isp_ops->disable_intrs(ha);
a9083016 3206 }
f6ef3b18 3207
e315cd28 3208 qla2x00_free_irqs(vha);
1da177e4 3209
8867048b
CD		 3210 qla2x00_free_fcports(vha);
3211
e315cd28 3212 qla2x00_mem_free(ha);
73208dfd 3213
08de2844
GM		 3214 qla82xx_md_free(vha);
3215
73208dfd 3216 qla2x00_free_queues(ha);
1da177e4
LT		 3217}
3218
8867048b
CD		 3219void qla2x00_free_fcports(struct scsi_qla_host *vha)
3220{
3221 fc_port_t *fcport, *tfcport;
3222
3223 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3224 list_del(&fcport->list);
5f16b331 3225 qla2x00_clear_loop_id(fcport);
8867048b
CD		 3226 kfree(fcport);
3227 fcport = NULL;
3228 }
3229}
3230
d97994dc 3231static inline void
e315cd28 3232qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc
AV		 3233 int defer)
3234{
d97994dc 3235 struct fc_rport *rport;
67becc00 3236 scsi_qla_host_t *base_vha;
044d78e1 3237 unsigned long flags;
d97994dc
AV		 3238
3239 if (!fcport->rport)
3240 return;
3241
3242 rport = fcport->rport;
3243 if (defer) {
67becc00 3244 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 3245 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 3246 fcport->drport = rport;
044d78e1 3247 spin_unlock_irqrestore(vha->host->host_lock, flags);
df673274 3248 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen);
67becc00
AV		 3249 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3250 qla2xxx_wake_dpc(base_vha);
2d70c103 3251 } else {
df673274 3252 int now;
d20ed91b
AP		 3253 if (rport)
3254 fc_remote_port_delete(rport);
df673274
AP		 3255 qlt_do_generation_tick(vha, &now);
3256 qlt_fc_port_deleted(vha, fcport, now);
2d70c103 3257 }
d97994dc
AV		 3258}
3259
1da177e4
LT		 3260/*
3261 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3262 *
3263 * Input: ha = adapter block pointer. fcport = port structure pointer.
3264 *
3265 * Return: None.
3266 *
3267 * Context:
3268 */
e315cd28 3269void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 3270 int do_login, int defer)
1da177e4 3271{
8ae6d9c7
GM		 3272 if (IS_QLAFX00(vha->hw)) {
3273 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3274 qla2x00_schedule_rport_del(vha, fcport, defer);
3275 return;
3276 }
3277
2c3dfe3f 3278 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 3279 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 3280 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 3281 qla2x00_schedule_rport_del(vha, fcport, defer);
3282 }
fa2a1ce5 3283 /*
1da177e4
LT		 3284 * We may need to retry the login, so don't change the state of the
3285 * port but do the retries.
3286 */
3287 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 3288 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3289
3290 if (!do_login)
3291 return;
3292
a1d0285e
AE		 3293 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3294
1da177e4 3295 if (fcport->login_retry == 0) {
e315cd28 3296 fcport->login_retry = vha->hw->login_retry_count;
1da177e4 3297
7c3df132 3298 ql_dbg(ql_dbg_disc, vha, 0x2067,
7b833558
OK		 3299 "Port login retry %8phN, id = 0x%04x retry cnt=%d.\n",
3300 fcport->port_name, fcport->loop_id, fcport->login_retry);
1da177e4
LT		 3301 }
3302}
3303
3304/*
3305 * qla2x00_mark_all_devices_lost
3306 * Updates fcport state when device goes offline.
3307 *
3308 * Input:
3309 * ha = adapter block pointer.
3310 * fcport = port structure pointer.
3311 *
3312 * Return:
3313 * None.
3314 *
3315 * Context:
3316 */
3317void
e315cd28 3318qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3319{
3320 fc_port_t *fcport;
3321
e315cd28 3322 list_for_each_entry(fcport, &vha->vp_fcports, list) {
c6d39e23 3323 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3324 continue;
0d6e61bc 3325
1da177e4
LT		 3326 /*
3327 * No point in marking the device as lost, if the device is
3328 * already DEAD.
3329 */
3330 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3331 continue;
e315cd28 3332 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3333 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3334 if (defer)
3335 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3336 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3337 qla2x00_schedule_rport_del(vha, fcport, defer);
3338 }
1da177e4
LT		 3339 }
3340}
3341
3342/*
3343* qla2x00_mem_alloc
3344* Allocates adapter memory.
3345*
3346* Returns:
3347* 0 = success.
e8711085 3348* !0 = failure.
1da177e4 3349*/
e8711085 3350static int
73208dfd
AC		 3351qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3352 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3353{
3354 char name[16];
1da177e4 3355
e8711085 3356 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3357 &ha->init_cb_dma, GFP_KERNEL);
e8711085 3358 if (!ha->init_cb)
e315cd28 3359 goto fail;
e8711085 3360
2d70c103
NB		 3361 if (qlt_mem_alloc(ha) < 0)
3362 goto fail_free_init_cb;
3363
642ef983
CD		 3364 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3365 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 3366 if (!ha->gid_list)
2d70c103 3367 goto fail_free_tgt_mem;
1da177e4 3368
e8711085
AV		 3369 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3370 if (!ha->srb_mempool)
e315cd28 3371 goto fail_free_gid_list;
e8711085 3372
7ec0effd 3373 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3374 /* Allocate cache for CT6 Ctx. */
3375 if (!ctx_cachep) {
3376 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3377 sizeof(struct ct6_dsd), 0,
3378 SLAB_HWCACHE_ALIGN, NULL);
3379 if (!ctx_cachep)
3380 goto fail_free_gid_list;
3381 }
3382 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3383 ctx_cachep);
3384 if (!ha->ctx_mempool)
3385 goto fail_free_srb_mempool;
7c3df132
SK		 3386 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3387 "ctx_cachep=%p ctx_mempool=%p.\n",
3388 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 3389 }
3390
e8711085
AV		 3391 /* Get memory for cached NVRAM */
3392 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3393 if (!ha->nvram)
a9083016 3394 goto fail_free_ctx_mempool;
e8711085 3395
e315cd28
AC		 3396 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3397 ha->pdev->device);
3398 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3399 DMA_POOL_SIZE, 8, 0);
3400 if (!ha->s_dma_pool)
3401 goto fail_free_nvram;
3402
7c3df132
SK		 3403 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3404 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3405 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3406
7ec0effd 3407 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
a9083016
GM		 3408 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3409 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3410 if (!ha->dl_dma_pool) {
7c3df132
SK		 3411 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3412 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 3413 goto fail_s_dma_pool;
3414 }
3415
3416 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3417 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3418 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 3419 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3420 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 3421 goto fail_dl_dma_pool;
3422 }
7c3df132
SK		 3423 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3424 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3425 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 3426 }
3427
e8711085
AV		 3428 /* Allocate memory for SNS commands */
3429 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 3430 /* Get consistent memory allocated for SNS commands */
e8711085 3431 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3432 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 3433 if (!ha->sns_cmd)
e315cd28 3434 goto fail_dma_pool;
7c3df132 3435 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 3436 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 3437 } else {
e315cd28 3438 /* Get consistent memory allocated for MS IOCB */
e8711085 3439 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 3440 &ha->ms_iocb_dma);
e8711085 3441 if (!ha->ms_iocb)
e315cd28
AC		 3442 goto fail_dma_pool;
3443 /* Get consistent memory allocated for CT SNS commands */
e8711085 3444 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3445 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 3446 if (!ha->ct_sns)
3447 goto fail_free_ms_iocb;
7c3df132
SK		 3448 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3449 "ms_iocb=%p ct_sns=%p.\n",
3450 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 3451 }
3452
e315cd28 3453 /* Allocate memory for request ring */
73208dfd
AC		 3454 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3455 if (!*req) {
7c3df132
SK		 3456 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3457 "Failed to allocate memory for req.\n");
e315cd28
AC		 3458 goto fail_req;
3459 }
73208dfd
AC		 3460 (*req)->length = req_len;
3461 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3462 ((*req)->length + 1) * sizeof(request_t),
3463 &(*req)->dma, GFP_KERNEL);
3464 if (!(*req)->ring) {
7c3df132
SK		 3465 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3466 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 3467 goto fail_req_ring;
3468 }
3469 /* Allocate memory for response ring */
73208dfd
AC		 3470 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3471 if (!*rsp) {
7c3df132
SK		 3472 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3473 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 3474 goto fail_rsp;
3475 }
73208dfd
AC		 3476 (*rsp)->hw = ha;
3477 (*rsp)->length = rsp_len;
3478 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3479 ((*rsp)->length + 1) * sizeof(response_t),
3480 &(*rsp)->dma, GFP_KERNEL);
3481 if (!(*rsp)->ring) {
7c3df132
SK		 3482 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3483 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 3484 goto fail_rsp_ring;
3485 }
73208dfd
AC		 3486 (*req)->rsp = *rsp;
3487 (*rsp)->req = *req;
7c3df132
SK		 3488 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3489 "req=%p req->length=%d req->ring=%p rsp=%p "
3490 "rsp->length=%d rsp->ring=%p.\n",
3491 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3492 (*rsp)->ring);
73208dfd
AC		 3493 /* Allocate memory for NVRAM data for vports */
3494 if (ha->nvram_npiv_size) {
3495 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
7c3df132 3496 ha->nvram_npiv_size, GFP_KERNEL);
73208dfd 3497 if (!ha->npiv_info) {
7c3df132
SK		 3498 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3499 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 3500 goto fail_npiv_info;
3501 }
3502 } else
3503 ha->npiv_info = NULL;
e8711085 3504
b64b0e8f 3505 /* Get consistent memory allocated for EX-INIT-CB. */
f73cb695 3506 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
b64b0e8f
AV		 3507 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3508 &ha->ex_init_cb_dma);
3509 if (!ha->ex_init_cb)
3510 goto fail_ex_init_cb;
7c3df132
SK		 3511 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
3512 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 3513 }
3514
a9083016
GM		 3515 INIT_LIST_HEAD(&ha->gbl_dsd_list);
3516
5ff1d584
AV		 3517 /* Get consistent memory allocated for Async Port-Database. */
3518 if (!IS_FWI2_CAPABLE(ha)) {
3519 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3520 &ha->async_pd_dma);
3521 if (!ha->async_pd)
3522 goto fail_async_pd;
7c3df132
SK		 3523 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
3524 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 3525 }
3526
e315cd28 3527 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 3528
3529 /* Allocate memory for our loop_id bitmap */
3530 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
3531 GFP_KERNEL);
3532 if (!ha->loop_id_map)
3533 goto fail_async_pd;
3534 else {
3535 qla2x00_set_reserved_loop_ids(ha);
3536 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
b2a72ec3 3537 "loop_id_map=%p.\n", ha->loop_id_map);
5f16b331
CD		 3538 }
3539
b2a72ec3 3540 return 0;
e315cd28 3541
5ff1d584
AV		 3542fail_async_pd:
3543 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 3544fail_ex_init_cb:
3545 kfree(ha->npiv_info);
73208dfd
AC		 3546fail_npiv_info:
3547 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
3548 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
3549 (*rsp)->ring = NULL;
3550 (*rsp)->dma = 0;
e315cd28 3551fail_rsp_ring:
73208dfd 3552 kfree(*rsp);
e315cd28 3553fail_rsp:
73208dfd
AC		 3554 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
3555 sizeof(request_t), (*req)->ring, (*req)->dma);
3556 (*req)->ring = NULL;
3557 (*req)->dma = 0;
e315cd28 3558fail_req_ring:
73208dfd 3559 kfree(*req);
e315cd28
AC		 3560fail_req:
3561 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3562 ha->ct_sns, ha->ct_sns_dma);
3563 ha->ct_sns = NULL;
3564 ha->ct_sns_dma = 0;
e8711085
AV		 3565fail_free_ms_iocb:
3566 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3567 ha->ms_iocb = NULL;
3568 ha->ms_iocb_dma = 0;
e315cd28 3569fail_dma_pool:
bad75002 3570 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3571 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3572 ha->fcp_cmnd_dma_pool = NULL;
3573 }
3574fail_dl_dma_pool:
bad75002 3575 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3576 dma_pool_destroy(ha->dl_dma_pool);
3577 ha->dl_dma_pool = NULL;
3578 }
3579fail_s_dma_pool:
e315cd28
AC		 3580 dma_pool_destroy(ha->s_dma_pool);
3581 ha->s_dma_pool = NULL;
e8711085
AV		 3582fail_free_nvram:
3583 kfree(ha->nvram);
3584 ha->nvram = NULL;
a9083016
GM		 3585fail_free_ctx_mempool:
3586 mempool_destroy(ha->ctx_mempool);
3587 ha->ctx_mempool = NULL;
e8711085
AV		 3588fail_free_srb_mempool:
3589 mempool_destroy(ha->srb_mempool);
3590 ha->srb_mempool = NULL;
e8711085 3591fail_free_gid_list:
642ef983
CD		 3592 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3593 ha->gid_list,
e315cd28 3594 ha->gid_list_dma);
e8711085
AV		 3595 ha->gid_list = NULL;
3596 ha->gid_list_dma = 0;
2d70c103
NB		 3597fail_free_tgt_mem:
3598 qlt_mem_free(ha);
e315cd28
AC		 3599fail_free_init_cb:
3600 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3601 ha->init_cb_dma);
3602 ha->init_cb = NULL;
3603 ha->init_cb_dma = 0;
e8711085 3604fail:
7c3df132
SK		 3605 ql_log(ql_log_fatal, NULL, 0x0030,
3606 "Memory allocation failure.\n");
e8711085 3607 return -ENOMEM;
1da177e4
LT		 3608}
3609
b0d6cabd
HM		 3610int
3611qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
3612{
3613 int rval;
3614 uint16_t size, max_cnt, temp;
3615 struct qla_hw_data *ha = vha->hw;
3616
3617 /* Return if we don't need to alloacate any extended logins */
3618 if (!ql2xexlogins)
3619 return QLA_SUCCESS;
3620
3621 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
3622 max_cnt = 0;
3623 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
3624 if (rval != QLA_SUCCESS) {
3625 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
3626 "Failed to get exlogin status.\n");
3627 return rval;
3628 }
3629
3630 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
3631 ha->exlogin_size = (size * temp);
3632 ql_log(ql_log_info, vha, 0xd024,
3633 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
3634 max_cnt, size, temp);
3635
3636 ql_log(ql_log_info, vha, 0xd025, "EXLOGIN: requested size=0x%x\n",
3637 ha->exlogin_size);
3638
3639 /* Get consistent memory for extended logins */
3640 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
3641 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
3642 if (!ha->exlogin_buf) {
3643 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
3644 "Failed to allocate memory for exlogin_buf_dma.\n");
3645 return -ENOMEM;
3646 }
3647
3648 /* Now configure the dma buffer */
3649 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
3650 if (rval) {
3651 ql_log(ql_log_fatal, vha, 0x00cf,
3652 "Setup extended login buffer ****FAILED****.\n");
3653 qla2x00_free_exlogin_buffer(ha);
3654 }
3655
3656 return rval;
3657}
3658
3659/*
3660* qla2x00_free_exlogin_buffer
3661*
3662* Input:
3663* ha = adapter block pointer
3664*/
3665void
3666qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
3667{
3668 if (ha->exlogin_buf) {
3669 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
3670 ha->exlogin_buf, ha->exlogin_buf_dma);
3671 ha->exlogin_buf = NULL;
3672 ha->exlogin_size = 0;
3673 }
3674}
3675
2f56a7f1
HM		 3676int
3677qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
3678{
3679 int rval;
3680 uint16_t size, max_cnt, temp;
3681 struct qla_hw_data *ha = vha->hw;
3682
3683 /* Return if we don't need to alloacate any extended logins */
3684 if (!ql2xexchoffld)
3685 return QLA_SUCCESS;
3686
3687 ql_log(ql_log_info, vha, 0xd014,
3688 "Exchange offload count: %d.\n", ql2xexlogins);
3689
3690 max_cnt = 0;
3691 rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
3692 if (rval != QLA_SUCCESS) {
3693 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
3694 "Failed to get exlogin status.\n");
3695 return rval;
3696 }
3697
3698 temp = (ql2xexchoffld > max_cnt) ? max_cnt : ql2xexchoffld;
3699 ha->exchoffld_size = (size * temp);
3700 ql_log(ql_log_info, vha, 0xd016,
3701 "Exchange offload: max_count=%d, buffers=0x%x, total=%d.\n",
3702 max_cnt, size, temp);
3703
3704 ql_log(ql_log_info, vha, 0xd017,
3705 "Exchange Buffers requested size = 0x%x\n", ha->exchoffld_size);
3706
3707 /* Get consistent memory for extended logins */
3708 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
3709 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
3710 if (!ha->exchoffld_buf) {
3711 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
3712 "Failed to allocate memory for exchoffld_buf_dma.\n");
3713 return -ENOMEM;
3714 }
3715
3716 /* Now configure the dma buffer */
3717 rval = qla_set_exchoffld_mem_cfg(vha, ha->exchoffld_buf_dma);
3718 if (rval) {
3719 ql_log(ql_log_fatal, vha, 0xd02e,
3720 "Setup exchange offload buffer ****FAILED****.\n");
3721 qla2x00_free_exchoffld_buffer(ha);
3722 }
3723
3724 return rval;
3725}
3726
3727/*
3728* qla2x00_free_exchoffld_buffer
3729*
3730* Input:
3731* ha = adapter block pointer
3732*/
3733void
3734qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
3735{
3736 if (ha->exchoffld_buf) {
3737 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
3738 ha->exchoffld_buf, ha->exchoffld_buf_dma);
3739 ha->exchoffld_buf = NULL;
3740 ha->exchoffld_size = 0;
3741 }
3742}
3743
1da177e4 3744/*
e30d1756
MI		 3745* qla2x00_free_fw_dump
3746* Frees fw dump stuff.
1da177e4
LT		 3747*
3748* Input:
7ec0effd 3749* ha = adapter block pointer
1da177e4 3750*/
a824ebb3 3751static void
e30d1756 3752qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 3753{
df613b96 3754 if (ha->fce)
f73cb695
CD		 3755 dma_free_coherent(&ha->pdev->dev,
3756 FCE_SIZE, ha->fce, ha->fce_dma);
df613b96 3757
f73cb695
CD		 3758 if (ha->eft)
3759 dma_free_coherent(&ha->pdev->dev,
3760 EFT_SIZE, ha->eft, ha->eft_dma);
3761
3762 if (ha->fw_dump)
a7a167bf 3763 vfree(ha->fw_dump);
f73cb695
CD		 3764 if (ha->fw_dump_template)
3765 vfree(ha->fw_dump_template);
3766
e30d1756
MI		 3767 ha->fce = NULL;
3768 ha->fce_dma = 0;
3769 ha->eft = NULL;
3770 ha->eft_dma = 0;
e30d1756 3771 ha->fw_dumped = 0;
61f098dd 3772 ha->fw_dump_cap_flags = 0;
e30d1756 3773 ha->fw_dump_reading = 0;
f73cb695
CD		 3774 ha->fw_dump = NULL;
3775 ha->fw_dump_len = 0;
3776 ha->fw_dump_template = NULL;
3777 ha->fw_dump_template_len = 0;
e30d1756
MI		 3778}
3779
3780/*
3781* qla2x00_mem_free
3782* Frees all adapter allocated memory.
3783*
3784* Input:
3785* ha = adapter block pointer.
3786*/
3787static void
3788qla2x00_mem_free(struct qla_hw_data *ha)
3789{
3790 qla2x00_free_fw_dump(ha);
3791
81178772
SK		 3792 if (ha->mctp_dump)
3793 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
3794 ha->mctp_dump_dma);
3795
e30d1756
MI		 3796 if (ha->srb_mempool)
3797 mempool_destroy(ha->srb_mempool);
a7a167bf 3798
11bbc1d8
AV		 3799 if (ha->dcbx_tlv)
3800 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
3801 ha->dcbx_tlv, ha->dcbx_tlv_dma);
3802
ce0423f4
AV		 3803 if (ha->xgmac_data)
3804 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
3805 ha->xgmac_data, ha->xgmac_data_dma);
3806
1da177e4
LT		 3807 if (ha->sns_cmd)
3808 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 3809 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 3810
3811 if (ha->ct_sns)
3812 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 3813 ha->ct_sns, ha->ct_sns_dma);
1da177e4 3814
88729e53
AV		 3815 if (ha->sfp_data)
3816 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
3817
1da177e4
LT		 3818 if (ha->ms_iocb)
3819 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3820
b64b0e8f 3821 if (ha->ex_init_cb)
a9083016
GM		 3822 dma_pool_free(ha->s_dma_pool,
3823 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 3824
5ff1d584
AV		 3825 if (ha->async_pd)
3826 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
3827
1da177e4
LT		 3828 if (ha->s_dma_pool)
3829 dma_pool_destroy(ha->s_dma_pool);
3830
1da177e4 3831 if (ha->gid_list)
642ef983
CD		 3832 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3833 ha->gid_list, ha->gid_list_dma);
1da177e4 3834
a9083016
GM		 3835 if (IS_QLA82XX(ha)) {
3836 if (!list_empty(&ha->gbl_dsd_list)) {
3837 struct dsd_dma *dsd_ptr, *tdsd_ptr;
3838
3839 /* clean up allocated prev pool */
3840 list_for_each_entry_safe(dsd_ptr,
3841 tdsd_ptr, &ha->gbl_dsd_list, list) {
3842 dma_pool_free(ha->dl_dma_pool,
3843 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
3844 list_del(&dsd_ptr->list);
3845 kfree(dsd_ptr);
3846 }
3847 }
3848 }
3849
3850 if (ha->dl_dma_pool)
3851 dma_pool_destroy(ha->dl_dma_pool);
3852
3853 if (ha->fcp_cmnd_dma_pool)
3854 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3855
3856 if (ha->ctx_mempool)
3857 mempool_destroy(ha->ctx_mempool);
3858
2d70c103
NB		 3859 qlt_mem_free(ha);
3860
e315cd28
AC		 3861 if (ha->init_cb)
3862 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 3863 ha->init_cb, ha->init_cb_dma);
e315cd28
AC		 3864 vfree(ha->optrom_buffer);
3865 kfree(ha->nvram);
73208dfd 3866 kfree(ha->npiv_info);
7a67735b 3867 kfree(ha->swl);
5f16b331 3868 kfree(ha->loop_id_map);
1da177e4 3869
e8711085 3870 ha->srb_mempool = NULL;
a9083016 3871 ha->ctx_mempool = NULL;
1da177e4
LT		 3872 ha->sns_cmd = NULL;
3873 ha->sns_cmd_dma = 0;
3874 ha->ct_sns = NULL;
3875 ha->ct_sns_dma = 0;
3876 ha->ms_iocb = NULL;
3877 ha->ms_iocb_dma = 0;
1da177e4
LT		 3878 ha->init_cb = NULL;
3879 ha->init_cb_dma = 0;
b64b0e8f
AV		 3880 ha->ex_init_cb = NULL;
3881 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 3882 ha->async_pd = NULL;
3883 ha->async_pd_dma = 0;
1da177e4
LT		 3884
3885 ha->s_dma_pool = NULL;
a9083016
GM		 3886 ha->dl_dma_pool = NULL;
3887 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 3888
1da177e4
LT		 3889 ha->gid_list = NULL;
3890 ha->gid_list_dma = 0;
2d70c103
NB		 3891
3892 ha->tgt.atio_ring = NULL;
3893 ha->tgt.atio_dma = 0;
3894 ha->tgt.tgt_vp_map = NULL;
e315cd28 3895}
1da177e4 3896
e315cd28
AC		 3897struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
3898 struct qla_hw_data *ha)
3899{
3900 struct Scsi_Host *host;
3901 struct scsi_qla_host *vha = NULL;
854165f4 3902
e315cd28
AC		 3903 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
3904 if (host == NULL) {
7c3df132
SK		 3905 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
3906 "Failed to allocate host from the scsi layer, aborting.\n");
e315cd28
AC		 3907 goto fail;
3908 }
3909
3910 /* Clear our data area */
3911 vha = shost_priv(host);
3912 memset(vha, 0, sizeof(scsi_qla_host_t));
3913
3914 vha->host = host;
3915 vha->host_no = host->host_no;
3916 vha->hw = ha;
3917
3918 INIT_LIST_HEAD(&vha->vp_fcports);
3919 INIT_LIST_HEAD(&vha->work_list);
3920 INIT_LIST_HEAD(&vha->list);
8b2f5ff3
SN		 3921 INIT_LIST_HEAD(&vha->qla_cmd_list);
3922 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list);
71cdc079 3923 INIT_LIST_HEAD(&vha->logo_list);
b7bd104e 3924 INIT_LIST_HEAD(&vha->plogi_ack_list);
e315cd28 3925
f999f4c1 3926 spin_lock_init(&vha->work_lock);
8b2f5ff3 3927 spin_lock_init(&vha->cmd_list_lock);
f999f4c1 3928
e315cd28 3929 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 3930 ql_dbg(ql_dbg_init, vha, 0x0041,
3931 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
3932 vha->host, vha->hw, vha,
3933 dev_name(&(ha->pdev->dev)));
3934
e315cd28
AC		 3935 return vha;
3936
3937fail:
3938 return vha;
1da177e4
LT		 3939}
3940
01ef66bb 3941static struct qla_work_evt *
f999f4c1 3942qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 3943{
3944 struct qla_work_evt *e;
feafb7b1
AE		 3945 uint8_t bail;
3946
3947 QLA_VHA_MARK_BUSY(vha, bail);
3948 if (bail)
3949 return NULL;
0971de7f 3950
f999f4c1 3951 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 3952 if (!e) {
3953 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 3954 return NULL;
feafb7b1 3955 }
0971de7f
AV		 3956
3957 INIT_LIST_HEAD(&e->list);
3958 e->type = type;
3959 e->flags = QLA_EVT_FLAG_FREE;
3960 return e;
3961}
3962
01ef66bb 3963static int
f999f4c1 3964qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 3965{
f999f4c1 3966 unsigned long flags;
0971de7f 3967
f999f4c1 3968 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 3969 list_add_tail(&e->list, &vha->work_list);
f999f4c1 3970 spin_unlock_irqrestore(&vha->work_lock, flags);
e315cd28 3971 qla2xxx_wake_dpc(vha);
f999f4c1 3972
0971de7f
AV		 3973 return QLA_SUCCESS;
3974}
3975
3976int
e315cd28 3977qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 3978 u32 data)
3979{
3980 struct qla_work_evt *e;
3981
f999f4c1 3982 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 3983 if (!e)
3984 return QLA_FUNCTION_FAILED;
3985
3986 e->u.aen.code = code;
3987 e->u.aen.data = data;
f999f4c1 3988 return qla2x00_post_work(vha, e);
0971de7f
AV		 3989}
3990
8a659571
AV		 3991int
3992qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
3993{
3994 struct qla_work_evt *e;
3995
f999f4c1 3996 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 3997 if (!e)
3998 return QLA_FUNCTION_FAILED;
3999
4000 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 4001 return qla2x00_post_work(vha, e);
8a659571
AV		 4002}
4003
ac280b67
AV		 4004#define qla2x00_post_async_work(name, type) \
4005int qla2x00_post_async_##name##_work( \
4006 struct scsi_qla_host *vha, \
4007 fc_port_t *fcport, uint16_t *data) \
4008{ \
4009 struct qla_work_evt *e; \
4010 \
4011 e = qla2x00_alloc_work(vha, type); \
4012 if (!e) \
4013 return QLA_FUNCTION_FAILED; \
4014 \
4015 e->u.logio.fcport = fcport; \
4016 if (data) { \
4017 e->u.logio.data[0] = data[0]; \
4018 e->u.logio.data[1] = data[1]; \
4019 } \
4020 return qla2x00_post_work(vha, e); \
4021}
4022
4023qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
4024qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
4025qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
4026qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 4027qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
4028qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
ac280b67 4029
3420d36c
AV		 4030int
4031qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
4032{
4033 struct qla_work_evt *e;
4034
4035 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
4036 if (!e)
4037 return QLA_FUNCTION_FAILED;
4038
4039 e->u.uevent.code = code;
4040 return qla2x00_post_work(vha, e);
4041}
4042
4043static void
4044qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
4045{
4046 char event_string[40];
4047 char *envp[] = { event_string, NULL };
4048
4049 switch (code) {
4050 case QLA_UEVENT_CODE_FW_DUMP:
4051 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
4052 vha->host_no);
4053 break;
4054 default:
4055 /* do nothing */
4056 break;
4057 }
4058 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
4059}
4060
8ae6d9c7
GM		 4061int
4062qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
4063 uint32_t *data, int cnt)
4064{
4065 struct qla_work_evt *e;
4066
4067 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
4068 if (!e)
4069 return QLA_FUNCTION_FAILED;
4070
4071 e->u.aenfx.evtcode = evtcode;
4072 e->u.aenfx.count = cnt;
4073 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
4074 return qla2x00_post_work(vha, e);
4075}
4076
ac280b67 4077void
e315cd28 4078qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 4079{
f999f4c1
AV		 4080 struct qla_work_evt *e, *tmp;
4081 unsigned long flags;
4082 LIST_HEAD(work);
0971de7f 4083
f999f4c1
AV		 4084 spin_lock_irqsave(&vha->work_lock, flags);
4085 list_splice_init(&vha->work_list, &work);
4086 spin_unlock_irqrestore(&vha->work_lock, flags);
4087
4088 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 4089 list_del_init(&e->list);
0971de7f
AV		 4090
4091 switch (e->type) {
4092 case QLA_EVT_AEN:
e315cd28 4093 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 4094 e->u.aen.code, e->u.aen.data);
4095 break;
8a659571
AV		 4096 case QLA_EVT_IDC_ACK:
4097 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
4098 break;
ac280b67
AV		 4099 case QLA_EVT_ASYNC_LOGIN:
4100 qla2x00_async_login(vha, e->u.logio.fcport,
4101 e->u.logio.data);
4102 break;
4103 case QLA_EVT_ASYNC_LOGIN_DONE:
4104 qla2x00_async_login_done(vha, e->u.logio.fcport,
4105 e->u.logio.data);
4106 break;
4107 case QLA_EVT_ASYNC_LOGOUT:
4108 qla2x00_async_logout(vha, e->u.logio.fcport);
4109 break;
4110 case QLA_EVT_ASYNC_LOGOUT_DONE:
4111 qla2x00_async_logout_done(vha, e->u.logio.fcport,
4112 e->u.logio.data);
4113 break;
5ff1d584
AV		 4114 case QLA_EVT_ASYNC_ADISC:
4115 qla2x00_async_adisc(vha, e->u.logio.fcport,
4116 e->u.logio.data);
4117 break;
4118 case QLA_EVT_ASYNC_ADISC_DONE:
4119 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
4120 e->u.logio.data);
4121 break;
3420d36c
AV		 4122 case QLA_EVT_UEVENT:
4123 qla2x00_uevent_emit(vha, e->u.uevent.code);
4124 break;
8ae6d9c7
GM		 4125 case QLA_EVT_AENFX:
4126 qlafx00_process_aen(vha, e);
4127 break;
0971de7f
AV		 4128 }
4129 if (e->flags & QLA_EVT_FLAG_FREE)
4130 kfree(e);
feafb7b1
AE		 4131
4132 /* For each work completed decrement vha ref count */
4133 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 4134 }
e315cd28 4135}
f999f4c1 4136
e315cd28
AC		 4137/* Relogins all the fcports of a vport
4138 * Context: dpc thread
4139 */
4140void qla2x00_relogin(struct scsi_qla_host *vha)
4141{
4142 fc_port_t *fcport;
c6b2fca8 4143 int status;
e315cd28
AC		 4144 uint16_t next_loopid = 0;
4145 struct qla_hw_data *ha = vha->hw;
ac280b67 4146 uint16_t data[2];
e315cd28
AC		 4147
4148 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4149 /*
4150 * If the port is not ONLINE then try to login
4151 * to it if we haven't run out of retries.
4152 */
5ff1d584
AV		 4153 if (atomic_read(&fcport->state) != FCS_ONLINE &&
4154 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
ac280b67 4155 fcport->login_retry--;
e315cd28 4156 if (fcport->flags & FCF_FABRIC_DEVICE) {
f08b7251 4157 if (fcport->flags & FCF_FCP2_DEVICE)
e315cd28
AC		 4158 ha->isp_ops->fabric_logout(vha,
4159 fcport->loop_id,
4160 fcport->d_id.b.domain,
4161 fcport->d_id.b.area,
4162 fcport->d_id.b.al_pa);
4163
03bcfb57
JC		 4164 if (fcport->loop_id == FC_NO_LOOP_ID) {
4165 fcport->loop_id = next_loopid =
4166 ha->min_external_loopid;
4167 status = qla2x00_find_new_loop_id(
4168 vha, fcport);
4169 if (status != QLA_SUCCESS) {
4170 /* Ran out of IDs to use */
4171 break;
4172 }
4173 }
4174
ac280b67 4175 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584 4176 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 4177 data[0] = 0;
4178 data[1] = QLA_LOGIO_LOGIN_RETRIED;
4179 status = qla2x00_post_async_login_work(
4180 vha, fcport, data);
4181 if (status == QLA_SUCCESS)
4182 continue;
4183 /* Attempt a retry. */
4184 status = 1;
aaf4d3e2 4185 } else {
ac280b67
AV		 4186 status = qla2x00_fabric_login(vha,
4187 fcport, &next_loopid);
aaf4d3e2
SK		 4188 if (status == QLA_SUCCESS) {
4189 int status2;
4190 uint8_t opts;
4191
4192 opts = 0;
4193 if (fcport->flags &
4194 FCF_FCP2_DEVICE)
4195 opts |= BIT_1;
03003960
SK		 4196 status2 =
4197 qla2x00_get_port_database(
4198 vha, fcport, opts);
aaf4d3e2
SK		 4199 if (status2 != QLA_SUCCESS)
4200 status = 1;
4201 }
4202 }
e315cd28
AC		 4203 } else
4204 status = qla2x00_local_device_login(vha,
4205 fcport);
4206
e315cd28
AC		 4207 if (status == QLA_SUCCESS) {
4208 fcport->old_loop_id = fcport->loop_id;
4209
7c3df132
SK		 4210 ql_dbg(ql_dbg_disc, vha, 0x2003,
4211 "Port login OK: logged in ID 0x%x.\n",
4212 fcport->loop_id);
e315cd28
AC		 4213
4214 qla2x00_update_fcport(vha, fcport);
4215
4216 } else if (status == 1) {
4217 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4218 /* retry the login again */
7c3df132
SK		 4219 ql_dbg(ql_dbg_disc, vha, 0x2007,
4220 "Retrying %d login again loop_id 0x%x.\n",
4221 fcport->login_retry, fcport->loop_id);
e315cd28
AC		 4222 } else {
4223 fcport->login_retry = 0;
4224 }
4225
4226 if (fcport->login_retry == 0 && status != QLA_SUCCESS)
5f16b331 4227 qla2x00_clear_loop_id(fcport);
e315cd28
AC		 4228 }
4229 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4230 break;
0971de7f 4231 }
0971de7f
AV		 4232}
4233
7d613ac6
SV		 4234/* Schedule work on any of the dpc-workqueues */
4235void
4236qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
4237{
4238 struct qla_hw_data *ha = base_vha->hw;
4239
4240 switch (work_code) {
4241 case MBA_IDC_AEN: /* 0x8200 */
4242 if (ha->dpc_lp_wq)
4243 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
4244 break;
4245
4246 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
4247 if (!ha->flags.nic_core_reset_hdlr_active) {
4248 if (ha->dpc_hp_wq)
4249 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
4250 } else
4251 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
4252 "NIC Core reset is already active. Skip "
4253 "scheduling it again.\n");
4254 break;
4255 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
4256 if (ha->dpc_hp_wq)
4257 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
4258 break;
4259 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
4260 if (ha->dpc_hp_wq)
4261 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
4262 break;
4263 default:
4264 ql_log(ql_log_warn, base_vha, 0xb05f,
d939be3a 4265 "Unknown work-code=0x%x.\n", work_code);
7d613ac6
SV		 4266 }
4267
4268 return;
4269}
4270
4271/* Work: Perform NIC Core Unrecoverable state handling */
4272void
4273qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
4274{
4275 struct qla_hw_data *ha =
2ad1b67c 4276 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 4277 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4278 uint32_t dev_state = 0;
4279
4280 qla83xx_idc_lock(base_vha, 0);
4281 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4282 qla83xx_reset_ownership(base_vha);
4283 if (ha->flags.nic_core_reset_owner) {
4284 ha->flags.nic_core_reset_owner = 0;
4285 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4286 QLA8XXX_DEV_FAILED);
4287 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
4288 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4289 }
4290 qla83xx_idc_unlock(base_vha, 0);
4291}
4292
4293/* Work: Execute IDC state handler */
4294void
4295qla83xx_idc_state_handler_work(struct work_struct *work)
4296{
4297 struct qla_hw_data *ha =
2ad1b67c 4298 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 4299 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4300 uint32_t dev_state = 0;
4301
4302 qla83xx_idc_lock(base_vha, 0);
4303 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4304 if (dev_state == QLA8XXX_DEV_FAILED ||
4305 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
4306 qla83xx_idc_state_handler(base_vha);
4307 qla83xx_idc_unlock(base_vha, 0);
4308}
4309
fa492630 4310static int
7d613ac6
SV		 4311qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
4312{
4313 int rval = QLA_SUCCESS;
4314 unsigned long heart_beat_wait = jiffies + (1 * HZ);
4315 uint32_t heart_beat_counter1, heart_beat_counter2;
4316
4317 do {
4318 if (time_after(jiffies, heart_beat_wait)) {
4319 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
4320 "Nic Core f/w is not alive.\n");
4321 rval = QLA_FUNCTION_FAILED;
4322 break;
4323 }
4324
4325 qla83xx_idc_lock(base_vha, 0);
4326 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4327 &heart_beat_counter1);
4328 qla83xx_idc_unlock(base_vha, 0);
4329 msleep(100);
4330 qla83xx_idc_lock(base_vha, 0);
4331 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4332 &heart_beat_counter2);
4333 qla83xx_idc_unlock(base_vha, 0);
4334 } while (heart_beat_counter1 == heart_beat_counter2);
4335
4336 return rval;
4337}
4338
4339/* Work: Perform NIC Core Reset handling */
4340void
4341qla83xx_nic_core_reset_work(struct work_struct *work)
4342{
4343 struct qla_hw_data *ha =
4344 container_of(work, struct qla_hw_data, nic_core_reset);
4345 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4346 uint32_t dev_state = 0;
4347
81178772
SK		 4348 if (IS_QLA2031(ha)) {
4349 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
4350 ql_log(ql_log_warn, base_vha, 0xb081,
4351 "Failed to dump mctp\n");
4352 return;
4353 }
4354
7d613ac6
SV		 4355 if (!ha->flags.nic_core_reset_hdlr_active) {
4356 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
4357 qla83xx_idc_lock(base_vha, 0);
4358 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4359 &dev_state);
4360 qla83xx_idc_unlock(base_vha, 0);
4361 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
4362 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
4363 "Nic Core f/w is alive.\n");
4364 return;
4365 }
4366 }
4367
4368 ha->flags.nic_core_reset_hdlr_active = 1;
4369 if (qla83xx_nic_core_reset(base_vha)) {
4370 /* NIC Core reset failed. */
4371 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
4372 "NIC Core reset failed.\n");
4373 }
4374 ha->flags.nic_core_reset_hdlr_active = 0;
4375 }
4376}
4377
4378/* Work: Handle 8200 IDC aens */
4379void
4380qla83xx_service_idc_aen(struct work_struct *work)
4381{
4382 struct qla_hw_data *ha =
4383 container_of(work, struct qla_hw_data, idc_aen);
4384 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4385 uint32_t dev_state, idc_control;
4386
4387 qla83xx_idc_lock(base_vha, 0);
4388 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4389 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
4390 qla83xx_idc_unlock(base_vha, 0);
4391 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
4392 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
4393 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
4394 "Application requested NIC Core Reset.\n");
4395 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4396 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
4397 QLA_SUCCESS) {
4398 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
4399 "Other protocol driver requested NIC Core Reset.\n");
4400 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4401 }
4402 } else if (dev_state == QLA8XXX_DEV_FAILED ||
4403 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
4404 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4405 }
4406}
4407
4408static void
4409qla83xx_wait_logic(void)
4410{
4411 int i;
4412
4413 /* Yield CPU */
4414 if (!in_interrupt()) {
4415 /*
4416 * Wait about 200ms before retrying again.
4417 * This controls the number of retries for single
4418 * lock operation.
4419 */
4420 msleep(100);
4421 schedule();
4422 } else {
4423 for (i = 0; i < 20; i++)
4424 cpu_relax(); /* This a nop instr on i386 */
4425 }
4426}
4427
fa492630 4428static int
7d613ac6
SV		 4429qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
4430{
4431 int rval;
4432 uint32_t data;
4433 uint32_t idc_lck_rcvry_stage_mask = 0x3;
4434 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
4435 struct qla_hw_data *ha = base_vha->hw;
6c315553
SK		 4436 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
4437 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 4438
4439 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
4440 if (rval)
4441 return rval;
4442
4443 if ((data & idc_lck_rcvry_stage_mask) > 0) {
4444 return QLA_SUCCESS;
4445 } else {
4446 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
4447 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4448 data);
4449 if (rval)
4450 return rval;
4451
4452 msleep(200);
4453
4454 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4455 &data);
4456 if (rval)
4457 return rval;
4458
4459 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
4460 data &= (IDC_LOCK_RECOVERY_STAGE2 |
4461 ~(idc_lck_rcvry_stage_mask));
4462 rval = qla83xx_wr_reg(base_vha,
4463 QLA83XX_IDC_LOCK_RECOVERY, data);
4464 if (rval)
4465 return rval;
4466
4467 /* Forcefully perform IDC UnLock */
4468 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
4469 &data);
4470 if (rval)
4471 return rval;
4472 /* Clear lock-id by setting 0xff */
4473 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4474 0xff);
4475 if (rval)
4476 return rval;
4477 /* Clear lock-recovery by setting 0x0 */
4478 rval = qla83xx_wr_reg(base_vha,
4479 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
4480 if (rval)
4481 return rval;
4482 } else
4483 return QLA_SUCCESS;
4484 }
4485
4486 return rval;
4487}
4488
fa492630 4489static int
7d613ac6
SV		 4490qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
4491{
4492 int rval = QLA_SUCCESS;
4493 uint32_t o_drv_lockid, n_drv_lockid;
4494 unsigned long lock_recovery_timeout;
4495
4496 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
4497retry_lockid:
4498 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
4499 if (rval)
4500 goto exit;
4501
4502 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
4503 if (time_after_eq(jiffies, lock_recovery_timeout)) {
4504 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
4505 return QLA_SUCCESS;
4506 else
4507 return QLA_FUNCTION_FAILED;
4508 }
4509
4510 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
4511 if (rval)
4512 goto exit;
4513
4514 if (o_drv_lockid == n_drv_lockid) {
4515 qla83xx_wait_logic();
4516 goto retry_lockid;
4517 } else
4518 return QLA_SUCCESS;
4519
4520exit:
4521 return rval;
4522}
4523
4524void
4525qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4526{
4527 uint16_t options = (requester_id << 15) | BIT_6;
4528 uint32_t data;
6c315553 4529 uint32_t lock_owner;
7d613ac6
SV		 4530 struct qla_hw_data *ha = base_vha->hw;
4531
4532 /* IDC-lock implementation using driver-lock/lock-id remote registers */
4533retry_lock:
4534 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
4535 == QLA_SUCCESS) {
4536 if (data) {
4537 /* Setting lock-id to our function-number */
4538 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4539 ha->portnum);
4540 } else {
6c315553
SK		 4541 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4542 &lock_owner);
7d613ac6 4543 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 4544 "Failed to acquire IDC lock, acquired by %d, "
4545 "retrying...\n", lock_owner);
7d613ac6
SV		 4546
4547 /* Retry/Perform IDC-Lock recovery */
4548 if (qla83xx_idc_lock_recovery(base_vha)
4549 == QLA_SUCCESS) {
4550 qla83xx_wait_logic();
4551 goto retry_lock;
4552 } else
4553 ql_log(ql_log_warn, base_vha, 0xb075,
4554 "IDC Lock recovery FAILED.\n");
4555 }
4556
4557 }
4558
4559 return;
4560
4561 /* XXX: IDC-lock implementation using access-control mbx */
4562retry_lock2:
4563 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4564 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
4565 "Failed to acquire IDC lock. retrying...\n");
4566 /* Retry/Perform IDC-Lock recovery */
4567 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
4568 qla83xx_wait_logic();
4569 goto retry_lock2;
4570 } else
4571 ql_log(ql_log_warn, base_vha, 0xb076,
4572 "IDC Lock recovery FAILED.\n");
4573 }
4574
4575 return;
4576}
4577
4578void
4579qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4580{
5897cb2f
BVA		 4581#if 0
4582 uint16_t options = (requester_id << 15) | BIT_7;
4583#endif
4584 uint16_t retry;
7d613ac6
SV		 4585 uint32_t data;
4586 struct qla_hw_data *ha = base_vha->hw;
4587
4588 /* IDC-unlock implementation using driver-unlock/lock-id
4589 * remote registers
4590 */
4591 retry = 0;
4592retry_unlock:
4593 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
4594 == QLA_SUCCESS) {
4595 if (data == ha->portnum) {
4596 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
4597 /* Clearing lock-id by setting 0xff */
4598 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
4599 } else if (retry < 10) {
4600 /* SV: XXX: IDC unlock retrying needed here? */
4601
4602 /* Retry for IDC-unlock */
4603 qla83xx_wait_logic();
4604 retry++;
4605 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
4606 "Failed to release IDC lock, retyring=%d\n", retry);
4607 goto retry_unlock;
4608 }
4609 } else if (retry < 10) {
4610 /* Retry for IDC-unlock */
4611 qla83xx_wait_logic();
4612 retry++;
4613 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
4614 "Failed to read drv-lockid, retyring=%d\n", retry);
4615 goto retry_unlock;
4616 }
4617
4618 return;
4619
5897cb2f 4620#if 0
7d613ac6
SV		 4621 /* XXX: IDC-unlock implementation using access-control mbx */
4622 retry = 0;
4623retry_unlock2:
4624 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4625 if (retry < 10) {
4626 /* Retry for IDC-unlock */
4627 qla83xx_wait_logic();
4628 retry++;
4629 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
4630 "Failed to release IDC lock, retyring=%d\n", retry);
4631 goto retry_unlock2;
4632 }
4633 }
4634
4635 return;
5897cb2f 4636#endif
7d613ac6
SV		 4637}
4638
4639int
4640__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4641{
4642 int rval = QLA_SUCCESS;
4643 struct qla_hw_data *ha = vha->hw;
4644 uint32_t drv_presence;
4645
4646 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4647 if (rval == QLA_SUCCESS) {
4648 drv_presence |= (1 << ha->portnum);
4649 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4650 drv_presence);
4651 }
4652
4653 return rval;
4654}
4655
4656int
4657qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4658{
4659 int rval = QLA_SUCCESS;
4660
4661 qla83xx_idc_lock(vha, 0);
4662 rval = __qla83xx_set_drv_presence(vha);
4663 qla83xx_idc_unlock(vha, 0);
4664
4665 return rval;
4666}
4667
4668int
4669__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4670{
4671 int rval = QLA_SUCCESS;
4672 struct qla_hw_data *ha = vha->hw;
4673 uint32_t drv_presence;
4674
4675 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4676 if (rval == QLA_SUCCESS) {
4677 drv_presence &= ~(1 << ha->portnum);
4678 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4679 drv_presence);
4680 }
4681
4682 return rval;
4683}
4684
4685int
4686qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4687{
4688 int rval = QLA_SUCCESS;
4689
4690 qla83xx_idc_lock(vha, 0);
4691 rval = __qla83xx_clear_drv_presence(vha);
4692 qla83xx_idc_unlock(vha, 0);
4693
4694 return rval;
4695}
4696
fa492630 4697static void
7d613ac6
SV		 4698qla83xx_need_reset_handler(scsi_qla_host_t *vha)
4699{
4700 struct qla_hw_data *ha = vha->hw;
4701 uint32_t drv_ack, drv_presence;
4702 unsigned long ack_timeout;
4703
4704 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
4705 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
4706 while (1) {
4707 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4708 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 4709 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 4710 break;
4711
4712 if (time_after_eq(jiffies, ack_timeout)) {
4713 ql_log(ql_log_warn, vha, 0xb067,
4714 "RESET ACK TIMEOUT! drv_presence=0x%x "
4715 "drv_ack=0x%x\n", drv_presence, drv_ack);
4716 /*
4717 * The function(s) which did not ack in time are forced
4718 * to withdraw any further participation in the IDC
4719 * reset.
4720 */
4721 if (drv_ack != drv_presence)
4722 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4723 drv_ack);
4724 break;
4725 }
4726
4727 qla83xx_idc_unlock(vha, 0);
4728 msleep(1000);
4729 qla83xx_idc_lock(vha, 0);
4730 }
4731
4732 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
4733 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
4734}
4735
fa492630 4736static int
7d613ac6
SV		 4737qla83xx_device_bootstrap(scsi_qla_host_t *vha)
4738{
4739 int rval = QLA_SUCCESS;
4740 uint32_t idc_control;
4741
4742 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
4743 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
4744
4745 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
4746 __qla83xx_get_idc_control(vha, &idc_control);
4747 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
4748 __qla83xx_set_idc_control(vha, 0);
4749
4750 qla83xx_idc_unlock(vha, 0);
4751 rval = qla83xx_restart_nic_firmware(vha);
4752 qla83xx_idc_lock(vha, 0);
4753
4754 if (rval != QLA_SUCCESS) {
4755 ql_log(ql_log_fatal, vha, 0xb06a,
4756 "Failed to restart NIC f/w.\n");
4757 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
4758 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
4759 } else {
4760 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
4761 "Success in restarting nic f/w.\n");
4762 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
4763 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
4764 }
4765
4766 return rval;
4767}
4768
4769/* Assumes idc_lock always held on entry */
4770int
4771qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
4772{
4773 struct qla_hw_data *ha = base_vha->hw;
4774 int rval = QLA_SUCCESS;
4775 unsigned long dev_init_timeout;
4776 uint32_t dev_state;
4777
4778 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
4779 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
4780
4781 while (1) {
4782
4783 if (time_after_eq(jiffies, dev_init_timeout)) {
4784 ql_log(ql_log_warn, base_vha, 0xb06e,
4785 "Initialization TIMEOUT!\n");
4786 /* Init timeout. Disable further NIC Core
4787 * communication.
4788 */
4789 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4790 QLA8XXX_DEV_FAILED);
4791 ql_log(ql_log_info, base_vha, 0xb06f,
4792 "HW State: FAILED.\n");
4793 }
4794
4795 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4796 switch (dev_state) {
4797 case QLA8XXX_DEV_READY:
4798 if (ha->flags.nic_core_reset_owner)
4799 qla83xx_idc_audit(base_vha,
4800 IDC_AUDIT_COMPLETION);
4801 ha->flags.nic_core_reset_owner = 0;
4802 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
4803 "Reset_owner reset by 0x%x.\n",
4804 ha->portnum);
4805 goto exit;
4806 case QLA8XXX_DEV_COLD:
4807 if (ha->flags.nic_core_reset_owner)
4808 rval = qla83xx_device_bootstrap(base_vha);
4809 else {
4810 /* Wait for AEN to change device-state */
4811 qla83xx_idc_unlock(base_vha, 0);
4812 msleep(1000);
4813 qla83xx_idc_lock(base_vha, 0);
4814 }
4815 break;
4816 case QLA8XXX_DEV_INITIALIZING:
4817 /* Wait for AEN to change device-state */
4818 qla83xx_idc_unlock(base_vha, 0);
4819 msleep(1000);
4820 qla83xx_idc_lock(base_vha, 0);
4821 break;
4822 case QLA8XXX_DEV_NEED_RESET:
4823 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
4824 qla83xx_need_reset_handler(base_vha);
4825 else {
4826 /* Wait for AEN to change device-state */
4827 qla83xx_idc_unlock(base_vha, 0);
4828 msleep(1000);
4829 qla83xx_idc_lock(base_vha, 0);
4830 }
4831 /* reset timeout value after need reset handler */
4832 dev_init_timeout = jiffies +
4833 (ha->fcoe_dev_init_timeout * HZ);
4834 break;
4835 case QLA8XXX_DEV_NEED_QUIESCENT:
4836 /* XXX: DEBUG for now */
4837 qla83xx_idc_unlock(base_vha, 0);
4838 msleep(1000);
4839 qla83xx_idc_lock(base_vha, 0);
4840 break;
4841 case QLA8XXX_DEV_QUIESCENT:
4842 /* XXX: DEBUG for now */
4843 if (ha->flags.quiesce_owner)
4844 goto exit;
4845
4846 qla83xx_idc_unlock(base_vha, 0);
4847 msleep(1000);
4848 qla83xx_idc_lock(base_vha, 0);
4849 dev_init_timeout = jiffies +
4850 (ha->fcoe_dev_init_timeout * HZ);
4851 break;
4852 case QLA8XXX_DEV_FAILED:
4853 if (ha->flags.nic_core_reset_owner)
4854 qla83xx_idc_audit(base_vha,
4855 IDC_AUDIT_COMPLETION);
4856 ha->flags.nic_core_reset_owner = 0;
4857 __qla83xx_clear_drv_presence(base_vha);
4858 qla83xx_idc_unlock(base_vha, 0);
4859 qla8xxx_dev_failed_handler(base_vha);
4860 rval = QLA_FUNCTION_FAILED;
4861 qla83xx_idc_lock(base_vha, 0);
4862 goto exit;
4863 case QLA8XXX_BAD_VALUE:
4864 qla83xx_idc_unlock(base_vha, 0);
4865 msleep(1000);
4866 qla83xx_idc_lock(base_vha, 0);
4867 break;
4868 default:
4869 ql_log(ql_log_warn, base_vha, 0xb071,
d939be3a 4870 "Unknown Device State: %x.\n", dev_state);
7d613ac6
SV		 4871 qla83xx_idc_unlock(base_vha, 0);
4872 qla8xxx_dev_failed_handler(base_vha);
4873 rval = QLA_FUNCTION_FAILED;
4874 qla83xx_idc_lock(base_vha, 0);
4875 goto exit;
4876 }
4877 }
4878
4879exit:
4880 return rval;
4881}
4882
f3ddac19
CD		 4883void
4884qla2x00_disable_board_on_pci_error(struct work_struct *work)
4885{
4886 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
4887 board_disable);
4888 struct pci_dev *pdev = ha->pdev;
4889 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4890
4891 ql_log(ql_log_warn, base_vha, 0x015b,
4892 "Disabling adapter.\n");
4893
4894 set_bit(UNLOADING, &base_vha->dpc_flags);
4895
4896 qla2x00_delete_all_vps(ha, base_vha);
4897
4898 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
4899
4900 qla2x00_dfs_remove(base_vha);
4901
4902 qla84xx_put_chip(base_vha);
4903
4904 if (base_vha->timer_active)
4905 qla2x00_stop_timer(base_vha);
4906
4907 base_vha->flags.online = 0;
4908
4909 qla2x00_destroy_deferred_work(ha);
4910
4911 /*
4912 * Do not try to stop beacon blink as it will issue a mailbox
4913 * command.
4914 */
4915 qla2x00_free_sysfs_attr(base_vha, false);
4916
4917 fc_remove_host(base_vha->host);
4918
4919 scsi_remove_host(base_vha->host);
4920
4921 base_vha->flags.init_done = 0;
4922 qla25xx_delete_queues(base_vha);
4923 qla2x00_free_irqs(base_vha);
4924 qla2x00_free_fcports(base_vha);
4925 qla2x00_mem_free(ha);
4926 qla82xx_md_free(base_vha);
4927 qla2x00_free_queues(ha);
4928
f3ddac19
CD		 4929 qla2x00_unmap_iobases(ha);
4930
4931 pci_release_selected_regions(ha->pdev, ha->bars);
f3ddac19
CD		 4932 pci_disable_pcie_error_reporting(pdev);
4933 pci_disable_device(pdev);
f3ddac19 4934
beb9e315
JL		 4935 /*
4936 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
4937 */
f3ddac19
CD		 4938}
4939
1da177e4
LT		 4940/**************************************************************************
4941* qla2x00_do_dpc
4942* This kernel thread is a task that is schedule by the interrupt handler
4943* to perform the background processing for interrupts.
4944*
4945* Notes:
4946* This task always run in the context of a kernel thread. It
4947* is kick-off by the driver's detect code and starts up
4948* up one per adapter. It immediately goes to sleep and waits for
4949* some fibre event. When either the interrupt handler or
4950* the timer routine detects a event it will one of the task
4951* bits then wake us up.
4952**************************************************************************/
4953static int
4954qla2x00_do_dpc(void *data)
4955{
e315cd28
AC		 4956 scsi_qla_host_t *base_vha;
4957 struct qla_hw_data *ha;
1da177e4 4958
e315cd28
AC		 4959 ha = (struct qla_hw_data *)data;
4960 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 4961
8698a745 4962 set_user_nice(current, MIN_NICE);
1da177e4 4963
563585ec 4964 set_current_state(TASK_INTERRUPTIBLE);
39a11240 4965 while (!kthread_should_stop()) {
7c3df132
SK		 4966 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
4967 "DPC handler sleeping.\n");
1da177e4 4968
39a11240 4969 schedule();
1da177e4 4970
c142caf0
AV		 4971 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
4972 goto end_loop;
1da177e4 4973
85880801 4974 if (ha->flags.eeh_busy) {
7c3df132
SK		 4975 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
4976 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 4977 goto end_loop;
85880801
AV		 4978 }
4979
1da177e4
LT		 4980 ha->dpc_active = 1;
4981
5f28d2d7
SK		 4982 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
4983 "DPC handler waking up, dpc_flags=0x%lx.\n",
4984 base_vha->dpc_flags);
1da177e4 4985
e315cd28 4986 qla2x00_do_work(base_vha);
0971de7f 4987
7ec0effd
AD		 4988 if (IS_P3P_TYPE(ha)) {
4989 if (IS_QLA8044(ha)) {
4990 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4991 &base_vha->dpc_flags)) {
4992 qla8044_idc_lock(ha);
4993 qla8044_wr_direct(base_vha,
4994 QLA8044_CRB_DEV_STATE_INDEX,
4995 QLA8XXX_DEV_FAILED);
4996 qla8044_idc_unlock(ha);
4997 ql_log(ql_log_info, base_vha, 0x4004,
4998 "HW State: FAILED.\n");
4999 qla8044_device_state_handler(base_vha);
5000 continue;
5001 }
5002
5003 } else {
5004 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5005 &base_vha->dpc_flags)) {
5006 qla82xx_idc_lock(ha);
5007 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5008 QLA8XXX_DEV_FAILED);
5009 qla82xx_idc_unlock(ha);
5010 ql_log(ql_log_info, base_vha, 0x0151,
5011 "HW State: FAILED.\n");
5012 qla82xx_device_state_handler(base_vha);
5013 continue;
5014 }
a9083016
GM		 5015 }
5016
5017 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
5018 &base_vha->dpc_flags)) {
5019
7c3df132
SK		 5020 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
5021 "FCoE context reset scheduled.\n");
a9083016
GM		 5022 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
5023 &base_vha->dpc_flags))) {
5024 if (qla82xx_fcoe_ctx_reset(base_vha)) {
5025 /* FCoE-ctx reset failed.
5026 * Escalate to chip-reset
5027 */
5028 set_bit(ISP_ABORT_NEEDED,
5029 &base_vha->dpc_flags);
5030 }
5031 clear_bit(ABORT_ISP_ACTIVE,
5032 &base_vha->dpc_flags);
5033 }
5034
7c3df132
SK		 5035 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
5036 "FCoE context reset end.\n");
a9083016 5037 }
8ae6d9c7
GM		 5038 } else if (IS_QLAFX00(ha)) {
5039 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5040 &base_vha->dpc_flags)) {
5041 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
5042 "Firmware Reset Recovery\n");
5043 if (qlafx00_reset_initialize(base_vha)) {
5044 /* Failed. Abort isp later. */
5045 if (!test_bit(UNLOADING,
f92f82d6 5046 &base_vha->dpc_flags)) {
8ae6d9c7
GM		 5047 set_bit(ISP_UNRECOVERABLE,
5048 &base_vha->dpc_flags);
5049 ql_dbg(ql_dbg_dpc, base_vha,
5050 0x4021,
5051 "Reset Recovery Failed\n");
f92f82d6 5052 }
8ae6d9c7
GM		 5053 }
5054 }
5055
5056 if (test_and_clear_bit(FX00_TARGET_SCAN,
5057 &base_vha->dpc_flags)) {
5058 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
5059 "ISPFx00 Target Scan scheduled\n");
5060 if (qlafx00_rescan_isp(base_vha)) {
5061 if (!test_bit(UNLOADING,
5062 &base_vha->dpc_flags))
5063 set_bit(ISP_UNRECOVERABLE,
5064 &base_vha->dpc_flags);
5065 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
5066 "ISPFx00 Target Scan Failed\n");
5067 }
5068 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
5069 "ISPFx00 Target Scan End\n");
5070 }
e8f5e95d
AB		 5071 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
5072 &base_vha->dpc_flags)) {
5073 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
5074 "ISPFx00 Host Info resend scheduled\n");
5075 qlafx00_fx_disc(base_vha,
5076 &base_vha->hw->mr.fcport,
5077 FXDISC_REG_HOST_INFO);
5078 }
a9083016
GM		 5079 }
5080
e315cd28
AC		 5081 if (test_and_clear_bit(ISP_ABORT_NEEDED,
5082 &base_vha->dpc_flags)) {
1da177e4 5083
7c3df132
SK		 5084 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
5085 "ISP abort scheduled.\n");
1da177e4 5086 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 5087 &base_vha->dpc_flags))) {
1da177e4 5088
a9083016 5089 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 5090 /* failed. retry later */
5091 set_bit(ISP_ABORT_NEEDED,
e315cd28 5092 &base_vha->dpc_flags);
99363ef8 5093 }
e315cd28
AC		 5094 clear_bit(ABORT_ISP_ACTIVE,
5095 &base_vha->dpc_flags);
99363ef8
SJ		 5096 }
5097
7c3df132
SK		 5098 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
5099 "ISP abort end.\n");
1da177e4
LT		 5100 }
5101
a394aac8
DJ		 5102 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
5103 &base_vha->dpc_flags)) {
e315cd28 5104 qla2x00_update_fcports(base_vha);
c9c5ced9 5105 }
d97994dc 5106
2d70c103
NB		 5107 if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) {
5108 int ret;
5109 ret = qla2x00_send_change_request(base_vha, 0x3, 0);
5110 if (ret != QLA_SUCCESS)
5111 ql_log(ql_log_warn, base_vha, 0x121,
5112 "Failed to enable receiving of RSCN "
5113 "requests: 0x%x.\n", ret);
5114 clear_bit(SCR_PENDING, &base_vha->dpc_flags);
5115 }
5116
8ae6d9c7
GM		 5117 if (IS_QLAFX00(ha))
5118 goto loop_resync_check;
5119
579d12b5 5120 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 5121 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
5122 "Quiescence mode scheduled.\n");
7ec0effd
AD		 5123 if (IS_P3P_TYPE(ha)) {
5124 if (IS_QLA82XX(ha))
5125 qla82xx_device_state_handler(base_vha);
5126 if (IS_QLA8044(ha))
5127 qla8044_device_state_handler(base_vha);
8fcd6b8b
CD		 5128 clear_bit(ISP_QUIESCE_NEEDED,
5129 &base_vha->dpc_flags);
5130 if (!ha->flags.quiesce_owner) {
5131 qla2x00_perform_loop_resync(base_vha);
7ec0effd
AD		 5132 if (IS_QLA82XX(ha)) {
5133 qla82xx_idc_lock(ha);
5134 qla82xx_clear_qsnt_ready(
5135 base_vha);
5136 qla82xx_idc_unlock(ha);
5137 } else if (IS_QLA8044(ha)) {
5138 qla8044_idc_lock(ha);
5139 qla8044_clear_qsnt_ready(
5140 base_vha);
5141 qla8044_idc_unlock(ha);
5142 }
8fcd6b8b
CD		 5143 }
5144 } else {
5145 clear_bit(ISP_QUIESCE_NEEDED,
5146 &base_vha->dpc_flags);
5147 qla2x00_quiesce_io(base_vha);
579d12b5 5148 }
7c3df132
SK		 5149 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
5150 "Quiescence mode end.\n");
579d12b5
SK		 5151 }
5152
e315cd28 5153 if (test_and_clear_bit(RESET_MARKER_NEEDED,
8ae6d9c7 5154 &base_vha->dpc_flags) &&
e315cd28 5155 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 5156
7c3df132
SK		 5157 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
5158 "Reset marker scheduled.\n");
e315cd28
AC		 5159 qla2x00_rst_aen(base_vha);
5160 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 5161 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
5162 "Reset marker end.\n");
1da177e4
LT		 5163 }
5164
5165 /* Retry each device up to login retry count */
e315cd28
AC		 5166 if ((test_and_clear_bit(RELOGIN_NEEDED,
5167 &base_vha->dpc_flags)) &&
5168 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
5169 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 5170
7c3df132
SK		 5171 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
5172 "Relogin scheduled.\n");
e315cd28 5173 qla2x00_relogin(base_vha);
7c3df132
SK		 5174 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
5175 "Relogin end.\n");
1da177e4 5176 }
8ae6d9c7 5177loop_resync_check:
e315cd28 5178 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
8ae6d9c7 5179 &base_vha->dpc_flags)) {
1da177e4 5180
7c3df132
SK		 5181 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
5182 "Loop resync scheduled.\n");
1da177e4
LT		 5183
5184 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 5185 &base_vha->dpc_flags))) {
1da177e4 5186
52c82823 5187 qla2x00_loop_resync(base_vha);
1da177e4 5188
e315cd28
AC		 5189 clear_bit(LOOP_RESYNC_ACTIVE,
5190 &base_vha->dpc_flags);
1da177e4
LT		 5191 }
5192
7c3df132
SK		 5193 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
5194 "Loop resync end.\n");
1da177e4
LT		 5195 }
5196
8ae6d9c7
GM		 5197 if (IS_QLAFX00(ha))
5198 goto intr_on_check;
5199
e315cd28
AC		 5200 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
5201 atomic_read(&base_vha->loop_state) == LOOP_READY) {
5202 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
5203 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 5204 }
5205
8ae6d9c7 5206intr_on_check:
1da177e4 5207 if (!ha->interrupts_on)
fd34f556 5208 ha->isp_ops->enable_intrs(ha);
1da177e4 5209
e315cd28 5210 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
90b604f2
HM		 5211 &base_vha->dpc_flags)) {
5212 if (ha->beacon_blink_led == 1)
5213 ha->isp_ops->beacon_blink(base_vha);
5214 }
f6df144c 5215
8ae6d9c7
GM		 5216 if (!IS_QLAFX00(ha))
5217 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 5218
1da177e4 5219 ha->dpc_active = 0;
c142caf0 5220end_loop:
563585ec 5221 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 5222 } /* End of while(1) */
563585ec 5223 __set_current_state(TASK_RUNNING);
1da177e4 5224
7c3df132
SK		 5225 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
5226 "DPC handler exiting.\n");
1da177e4
LT		 5227
5228 /*
5229 * Make sure that nobody tries to wake us up again.
5230 */
1da177e4
LT		 5231 ha->dpc_active = 0;
5232
ac280b67
AV		 5233 /* Cleanup any residual CTX SRBs. */
5234 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5235
39a11240
CH		 5236 return 0;
5237}
5238
5239void
e315cd28 5240qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 5241{
e315cd28 5242 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 5243 struct task_struct *t = ha->dpc_thread;
5244
e315cd28 5245 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 5246 wake_up_process(t);
1da177e4
LT		 5247}
5248
1da177e4
LT		 5249/*
5250* qla2x00_rst_aen
5251* Processes asynchronous reset.
5252*
5253* Input:
5254* ha = adapter block pointer.
5255*/
5256static void
e315cd28 5257qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 5258{
e315cd28
AC		 5259 if (vha->flags.online && !vha->flags.reset_active &&
5260 !atomic_read(&vha->loop_down_timer) &&
5261 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 5262 do {
e315cd28 5263 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 5264
5265 /*
5266 * Issue marker command only when we are going to start
5267 * the I/O.
5268 */
e315cd28
AC		 5269 vha->marker_needed = 1;
5270 } while (!atomic_read(&vha->loop_down_timer) &&
5271 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 5272 }
5273}
5274
1da177e4
LT		 5275/**************************************************************************
5276* qla2x00_timer
5277*
5278* Description:
5279* One second timer
5280*
5281* Context: Interrupt
5282***************************************************************************/
2c3dfe3f 5283void
e315cd28 5284qla2x00_timer(scsi_qla_host_t *vha)
1da177e4 5285{
1da177e4 5286 unsigned long cpu_flags = 0;
1da177e4
LT		 5287 int start_dpc = 0;
5288 int index;
5289 srb_t *sp;
85880801 5290 uint16_t w;
e315cd28 5291 struct qla_hw_data *ha = vha->hw;
73208dfd 5292 struct req_que *req;
85880801 5293
a5b36321 5294 if (ha->flags.eeh_busy) {
7c3df132
SK		 5295 ql_dbg(ql_dbg_timer, vha, 0x6000,
5296 "EEH = %d, restarting timer.\n",
5297 ha->flags.eeh_busy);
a5b36321
LC		 5298 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5299 return;
5300 }
5301
f3ddac19
CD		 5302 /*
5303 * Hardware read to raise pending EEH errors during mailbox waits. If
5304 * the read returns -1 then disable the board.
5305 */
5306 if (!pci_channel_offline(ha->pdev)) {
85880801 5307 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
c821e0d5 5308 qla2x00_check_reg16_for_disconnect(vha, w);
f3ddac19 5309 }
1da177e4 5310
cefcaba6 5311 /* Make sure qla82xx_watchdog is run only for physical port */
7ec0effd 5312 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
579d12b5
SK		 5313 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
5314 start_dpc++;
7ec0effd
AD		 5315 if (IS_QLA82XX(ha))
5316 qla82xx_watchdog(vha);
5317 else if (IS_QLA8044(ha))
5318 qla8044_watchdog(vha);
579d12b5
SK		 5319 }
5320
8ae6d9c7
GM		 5321 if (!vha->vp_idx && IS_QLAFX00(ha))
5322 qlafx00_timer_routine(vha);
5323
1da177e4 5324 /* Loop down handler. */
e315cd28 5325 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 5326 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
5327 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 5328 && vha->flags.online) {
1da177e4 5329
e315cd28
AC		 5330 if (atomic_read(&vha->loop_down_timer) ==
5331 vha->loop_down_abort_time) {
1da177e4 5332
7c3df132
SK		 5333 ql_log(ql_log_info, vha, 0x6008,
5334 "Loop down - aborting the queues before time expires.\n");
1da177e4 5335
e315cd28
AC		 5336 if (!IS_QLA2100(ha) && vha->link_down_timeout)
5337 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 5338
f08b7251
AV		 5339 /*
5340 * Schedule an ISP abort to return any FCP2-device
5341 * commands.
5342 */
2c3dfe3f 5343 /* NPIV - scan physical port only */
e315cd28 5344 if (!vha->vp_idx) {
2c3dfe3f
SJ		 5345 spin_lock_irqsave(&ha->hardware_lock,
5346 cpu_flags);
73208dfd 5347 req = ha->req_q_map[0];
2c3dfe3f 5348 for (index = 1;
8d93f550 5349 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 5350 index++) {
5351 fc_port_t *sfcp;
5352
e315cd28 5353 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 5354 if (!sp)
5355 continue;
9ba56b95 5356 if (sp->type != SRB_SCSI_CMD)
cf53b069 5357 continue;
2c3dfe3f 5358 sfcp = sp->fcport;
f08b7251 5359 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 5360 continue;
bdf79621 5361
8f7daead
GM		 5362 if (IS_QLA82XX(ha))
5363 set_bit(FCOE_CTX_RESET_NEEDED,
5364 &vha->dpc_flags);
5365 else
5366 set_bit(ISP_ABORT_NEEDED,
e315cd28 5367 &vha->dpc_flags);
2c3dfe3f
SJ		 5368 break;
5369 }
5370 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 5371 cpu_flags);
1da177e4 5372 }
1da177e4
LT		 5373 start_dpc++;
5374 }
5375
5376 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 5377 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 5378 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 5379 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 5380 "Loop down - aborting ISP.\n");
5381
8f7daead
GM		 5382 if (IS_QLA82XX(ha))
5383 set_bit(FCOE_CTX_RESET_NEEDED,
5384 &vha->dpc_flags);
5385 else
5386 set_bit(ISP_ABORT_NEEDED,
5387 &vha->dpc_flags);
1da177e4
LT		 5388 }
5389 }
7c3df132
SK		 5390 ql_dbg(ql_dbg_timer, vha, 0x600a,
5391 "Loop down - seconds remaining %d.\n",
5392 atomic_read(&vha->loop_down_timer));
1da177e4 5393 }
cefcaba6
SK		 5394 /* Check if beacon LED needs to be blinked for physical host only */
5395 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc 5396 /* There is no beacon_blink function for ISP82xx */
7ec0effd 5397 if (!IS_P3P_TYPE(ha)) {
999916dc
SK		 5398 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
5399 start_dpc++;
5400 }
f6df144c
AV		 5401 }
5402
550bf57d 5403 /* Process any deferred work. */
e315cd28 5404 if (!list_empty(&vha->work_list))
550bf57d
AV		 5405 start_dpc++;
5406
1da177e4 5407 /* Schedule the DPC routine if needed */
e315cd28
AC		 5408 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
5409 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
5410 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 5411 start_dpc ||
e315cd28
AC		 5412 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
5413 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 5414 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
5415 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 5416 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
50280c01 5417 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
7c3df132
SK		 5418 ql_dbg(ql_dbg_timer, vha, 0x600b,
5419 "isp_abort_needed=%d loop_resync_needed=%d "
5420 "fcport_update_needed=%d start_dpc=%d "
5421 "reset_marker_needed=%d",
5422 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
5423 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
5424 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
5425 start_dpc,
5426 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
5427 ql_dbg(ql_dbg_timer, vha, 0x600c,
5428 "beacon_blink_needed=%d isp_unrecoverable=%d "
5429 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
50280c01 5430 "relogin_needed=%d.\n",
7c3df132
SK		 5431 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
5432 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
5433 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
5434 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
50280c01 5435 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 5436 qla2xxx_wake_dpc(vha);
7c3df132 5437 }
1da177e4 5438
e315cd28 5439 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 5440}
5441
5433383e
AV		 5442/* Firmware interface routines. */
5443
f73cb695 5444#define FW_BLOBS 11
5433383e
AV		 5445#define FW_ISP21XX 0
5446#define FW_ISP22XX 1
5447#define FW_ISP2300 2
5448#define FW_ISP2322 3
48c02fde 5449#define FW_ISP24XX 4
c3a2f0df 5450#define FW_ISP25XX 5
3a03eb79 5451#define FW_ISP81XX 6
a9083016 5452#define FW_ISP82XX 7
6246b8a1
GM		 5453#define FW_ISP2031 8
5454#define FW_ISP8031 9
2c5bbbb2 5455#define FW_ISP27XX 10
5433383e 5456
bb8ee499
AV		 5457#define FW_FILE_ISP21XX "ql2100_fw.bin"
5458#define FW_FILE_ISP22XX "ql2200_fw.bin"
5459#define FW_FILE_ISP2300 "ql2300_fw.bin"
5460#define FW_FILE_ISP2322 "ql2322_fw.bin"
5461#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 5462#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 5463#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 5464#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 5465#define FW_FILE_ISP2031 "ql2600_fw.bin"
5466#define FW_FILE_ISP8031 "ql8300_fw.bin"
2c5bbbb2 5467#define FW_FILE_ISP27XX "ql2700_fw.bin"
f73cb695 5468
bb8ee499 5469
e1e82b6f 5470static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 5471
5472static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 5473 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
5474 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
5475 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
5476 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
5477 { .name = FW_FILE_ISP24XX, },
c3a2f0df 5478 { .name = FW_FILE_ISP25XX, },
3a03eb79 5479 { .name = FW_FILE_ISP81XX, },
a9083016 5480 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 5481 { .name = FW_FILE_ISP2031, },
5482 { .name = FW_FILE_ISP8031, },
2c5bbbb2 5483 { .name = FW_FILE_ISP27XX, },
5433383e
AV		 5484};
5485
5486struct fw_blob *
e315cd28 5487qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 5488{
e315cd28 5489 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 5490 struct fw_blob *blob;
5491
5433383e
AV		 5492 if (IS_QLA2100(ha)) {
5493 blob = &qla_fw_blobs[FW_ISP21XX];
5494 } else if (IS_QLA2200(ha)) {
5495 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 5496 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 5497 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 5498 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 5499 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 5500 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 5501 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 5502 } else if (IS_QLA25XX(ha)) {
5503 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 5504 } else if (IS_QLA81XX(ha)) {
5505 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 5506 } else if (IS_QLA82XX(ha)) {
5507 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 5508 } else if (IS_QLA2031(ha)) {
5509 blob = &qla_fw_blobs[FW_ISP2031];
5510 } else if (IS_QLA8031(ha)) {
5511 blob = &qla_fw_blobs[FW_ISP8031];
2c5bbbb2
JC		 5512 } else if (IS_QLA27XX(ha)) {
5513 blob = &qla_fw_blobs[FW_ISP27XX];
8a655229
DC		 5514 } else {
5515 return NULL;
5433383e
AV		 5516 }
5517
e1e82b6f 5518 mutex_lock(&qla_fw_lock);
5433383e
AV		 5519 if (blob->fw)
5520 goto out;
5521
5522 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 5523 ql_log(ql_log_warn, vha, 0x0063,
5524 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 5525 blob->fw = NULL;
5526 blob = NULL;
5527 goto out;
5528 }
5529
5530out:
e1e82b6f 5531 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5532 return blob;
5533}
5534
5535static void
5536qla2x00_release_firmware(void)
5537{
5538 int idx;
5539
e1e82b6f 5540 mutex_lock(&qla_fw_lock);
5433383e 5541 for (idx = 0; idx < FW_BLOBS; idx++)
cf92549f 5542 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 5543 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5544}
5545
14e660e6
SJ		 5546static pci_ers_result_t
5547qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5548{
85880801
AV		 5549 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
5550 struct qla_hw_data *ha = vha->hw;
5551
7c3df132
SK		 5552 ql_dbg(ql_dbg_aer, vha, 0x9000,
5553 "PCI error detected, state %x.\n", state);
b9b12f73 5554
14e660e6
SJ		 5555 switch (state) {
5556 case pci_channel_io_normal:
85880801 5557 ha->flags.eeh_busy = 0;
14e660e6
SJ		 5558 return PCI_ERS_RESULT_CAN_RECOVER;
5559 case pci_channel_io_frozen:
85880801 5560 ha->flags.eeh_busy = 1;
a5b36321
LC		 5561 /* For ISP82XX complete any pending mailbox cmd */
5562 if (IS_QLA82XX(ha)) {
7190575f 5563 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 5564 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
5565 qla82xx_clear_pending_mbx(vha);
a5b36321 5566 }
90a86fc0 5567 qla2x00_free_irqs(vha);
14e660e6 5568 pci_disable_device(pdev);
bddd2d65
LC		 5569 /* Return back all IOs */
5570 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
14e660e6
SJ		 5571 return PCI_ERS_RESULT_NEED_RESET;
5572 case pci_channel_io_perm_failure:
85880801
AV		 5573 ha->flags.pci_channel_io_perm_failure = 1;
5574 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
14e660e6
SJ		 5575 return PCI_ERS_RESULT_DISCONNECT;
5576 }
5577 return PCI_ERS_RESULT_NEED_RESET;
5578}
5579
5580static pci_ers_result_t
5581qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
5582{
5583 int risc_paused = 0;
5584 uint32_t stat;
5585 unsigned long flags;
e315cd28
AC		 5586 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5587 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 5588 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
5589 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
5590
bcc5b6d3
SK		 5591 if (IS_QLA82XX(ha))
5592 return PCI_ERS_RESULT_RECOVERED;
5593
14e660e6
SJ		 5594 spin_lock_irqsave(&ha->hardware_lock, flags);
5595 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
5596 stat = RD_REG_DWORD(&reg->hccr);
5597 if (stat & HCCR_RISC_PAUSE)
5598 risc_paused = 1;
5599 } else if (IS_QLA23XX(ha)) {
5600 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
5601 if (stat & HSR_RISC_PAUSED)
5602 risc_paused = 1;
5603 } else if (IS_FWI2_CAPABLE(ha)) {
5604 stat = RD_REG_DWORD(&reg24->host_status);
5605 if (stat & HSRX_RISC_PAUSED)
5606 risc_paused = 1;
5607 }
5608 spin_unlock_irqrestore(&ha->hardware_lock, flags);
5609
5610 if (risc_paused) {
7c3df132
SK		 5611 ql_log(ql_log_info, base_vha, 0x9003,
5612 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 5613 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 5614
5615 return PCI_ERS_RESULT_NEED_RESET;
5616 } else
5617 return PCI_ERS_RESULT_RECOVERED;
5618}
5619
fa492630
SK		 5620static uint32_t
5621qla82xx_error_recovery(scsi_qla_host_t *base_vha)
a5b36321
LC		 5622{
5623 uint32_t rval = QLA_FUNCTION_FAILED;
5624 uint32_t drv_active = 0;
5625 struct qla_hw_data *ha = base_vha->hw;
5626 int fn;
5627 struct pci_dev *other_pdev = NULL;
5628
7c3df132
SK		 5629 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
5630 "Entered %s.\n", __func__);
a5b36321
LC		 5631
5632 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5633
5634 if (base_vha->flags.online) {
5635 /* Abort all outstanding commands,
5636 * so as to be requeued later */
5637 qla2x00_abort_isp_cleanup(base_vha);
5638 }
5639
5640
5641 fn = PCI_FUNC(ha->pdev->devfn);
5642 while (fn > 0) {
5643 fn--;
7c3df132
SK		 5644 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
5645 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 5646 other_pdev =
5647 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
5648 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
5649 fn));
5650
5651 if (!other_pdev)
5652 continue;
5653 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 5654 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
5655 "Found PCI func available and enable at 0x%x.\n",
5656 fn);
a5b36321
LC		 5657 pci_dev_put(other_pdev);
5658 break;
5659 }
5660 pci_dev_put(other_pdev);
5661 }
5662
5663 if (!fn) {
5664 /* Reset owner */
7c3df132
SK		 5665 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
5666 "This devfn is reset owner = 0x%x.\n",
5667 ha->pdev->devfn);
a5b36321
LC		 5668 qla82xx_idc_lock(ha);
5669
5670 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5671 QLA8XXX_DEV_INITIALIZING);
a5b36321
LC		 5672
5673 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
5674 QLA82XX_IDC_VERSION);
5675
5676 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 5677 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
5678 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 5679
5680 qla82xx_idc_unlock(ha);
5681 /* Reset if device is not already reset
5682 * drv_active would be 0 if a reset has already been done
5683 */
5684 if (drv_active)
5685 rval = qla82xx_start_firmware(base_vha);
5686 else
5687 rval = QLA_SUCCESS;
5688 qla82xx_idc_lock(ha);
5689
5690 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5691 ql_log(ql_log_info, base_vha, 0x900b,
5692 "HW State: FAILED.\n");
a5b36321
LC		 5693 qla82xx_clear_drv_active(ha);
5694 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5695 QLA8XXX_DEV_FAILED);
a5b36321 5696 } else {
7c3df132
SK		 5697 ql_log(ql_log_info, base_vha, 0x900c,
5698 "HW State: READY.\n");
a5b36321 5699 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5700 QLA8XXX_DEV_READY);
a5b36321 5701 qla82xx_idc_unlock(ha);
7190575f 5702 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 5703 rval = qla82xx_restart_isp(base_vha);
5704 qla82xx_idc_lock(ha);
5705 /* Clear driver state register */
5706 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
5707 qla82xx_set_drv_active(base_vha);
5708 }
5709 qla82xx_idc_unlock(ha);
5710 } else {
7c3df132
SK		 5711 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
5712 "This devfn is not reset owner = 0x%x.\n",
5713 ha->pdev->devfn);
a5b36321 5714 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
7d613ac6 5715 QLA8XXX_DEV_READY)) {
7190575f 5716 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 5717 rval = qla82xx_restart_isp(base_vha);
5718 qla82xx_idc_lock(ha);
5719 qla82xx_set_drv_active(base_vha);
5720 qla82xx_idc_unlock(ha);
5721 }
5722 }
5723 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5724
5725 return rval;
5726}
5727
14e660e6
SJ		 5728static pci_ers_result_t
5729qla2xxx_pci_slot_reset(struct pci_dev *pdev)
5730{
5731 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 5732 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5733 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 5734 struct rsp_que *rsp;
5735 int rc, retries = 10;
09483916 5736
7c3df132
SK		 5737 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
5738 "Slot Reset.\n");
85880801 5739
90a86fc0
JC		 5740 /* Workaround: qla2xxx driver which access hardware earlier
5741 * needs error state to be pci_channel_io_online.
5742 * Otherwise mailbox command timesout.
5743 */
5744 pdev->error_state = pci_channel_io_normal;
5745
5746 pci_restore_state(pdev);
5747
8c1496bd
RL		 5748 /* pci_restore_state() clears the saved_state flag of the device
5749 * save restored state which resets saved_state flag
5750 */
5751 pci_save_state(pdev);
5752
09483916
BH		 5753 if (ha->mem_only)
5754 rc = pci_enable_device_mem(pdev);
5755 else
5756 rc = pci_enable_device(pdev);
14e660e6 5757
09483916 5758 if (rc) {
7c3df132 5759 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 5760 "Can't re-enable PCI device after reset.\n");
a5b36321 5761 goto exit_slot_reset;
14e660e6 5762 }
14e660e6 5763
90a86fc0
JC		 5764 rsp = ha->rsp_q_map[0];
5765 if (qla2x00_request_irqs(ha, rsp))
a5b36321 5766 goto exit_slot_reset;
90a86fc0 5767
e315cd28 5768 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 5769 goto exit_slot_reset;
5770
5771 if (IS_QLA82XX(ha)) {
5772 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
5773 ret = PCI_ERS_RESULT_RECOVERED;
5774 goto exit_slot_reset;
5775 } else
5776 goto exit_slot_reset;
5777 }
14e660e6 5778
90a86fc0
JC		 5779 while (ha->flags.mbox_busy && retries--)
5780 msleep(1000);
85880801 5781
e315cd28 5782 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 5783 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 5784 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 5785 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 5786
90a86fc0 5787
a5b36321 5788exit_slot_reset:
7c3df132
SK		 5789 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
5790 "slot_reset return %x.\n", ret);
85880801 5791
14e660e6
SJ		 5792 return ret;
5793}
5794
5795static void
5796qla2xxx_pci_resume(struct pci_dev *pdev)
5797{
e315cd28
AC		 5798 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5799 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 5800 int ret;
5801
7c3df132
SK		 5802 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
5803 "pci_resume.\n");
85880801 5804
e315cd28 5805 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 5806 if (ret != QLA_SUCCESS) {
7c3df132
SK		 5807 ql_log(ql_log_fatal, base_vha, 0x9002,
5808 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 5809 }
85880801 5810
3e46f031
LC		 5811 pci_cleanup_aer_uncorrect_error_status(pdev);
5812
85880801 5813 ha->flags.eeh_busy = 0;
14e660e6
SJ		 5814}
5815
2d5a4c34
HM		 5816static void
5817qla83xx_disable_laser(scsi_qla_host_t *vha)
5818{
5819 uint32_t reg, data, fn;
5820 struct qla_hw_data *ha = vha->hw;
5821 struct device_reg_24xx __iomem *isp_reg = &ha->iobase->isp24;
5822
5823 /* pci func #/port # */
5824 ql_dbg(ql_dbg_init, vha, 0x004b,
5825 "Disabling Laser for hba: %p\n", vha);
5826
5827 fn = (RD_REG_DWORD(&isp_reg->ctrl_status) &
5828 (BIT_15|BIT_14|BIT_13|BIT_12));
5829
5830 fn = (fn >> 12);
5831
5832 if (fn & 1)
5833 reg = PORT_1_2031;
5834 else
5835 reg = PORT_0_2031;
5836
5837 data = LASER_OFF_2031;
5838
5839 qla83xx_wr_reg(vha, reg, data);
5840}
5841
a55b2d21 5842static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 5843 .error_detected = qla2xxx_pci_error_detected,
5844 .mmio_enabled = qla2xxx_pci_mmio_enabled,
5845 .slot_reset = qla2xxx_pci_slot_reset,
5846 .resume = qla2xxx_pci_resume,
5847};
5848
5433383e 5849static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 5850 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
5851 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
5852 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
5853 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
5854 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
5855 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
5856 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
5857 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
5858 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 5859 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 5860 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
5861 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 5862 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 5863 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 5864 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 5865 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 5866 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8ae6d9c7 5867 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7ec0effd 5868 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
f73cb695 5869 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
2c5bbbb2 5870 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
2b48992f 5871 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
5433383e
AV		 5872 { 0 },
5873};
5874MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
5875
fca29703 5876static struct pci_driver qla2xxx_pci_driver = {
cb63067a 5877 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 5878 .driver = {
5879 .owner = THIS_MODULE,
5880 },
fca29703 5881 .id_table = qla2xxx_pci_tbl,
7ee61397 5882 .probe = qla2x00_probe_one,
4c993f76 5883 .remove = qla2x00_remove_one,
e30d1756 5884 .shutdown = qla2x00_shutdown,
14e660e6 5885 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 5886};
5887
75ef9de1 5888static const struct file_operations apidev_fops = {
6a03b4cd 5889 .owner = THIS_MODULE,
6038f373 5890 .llseek = noop_llseek,
6a03b4cd
HZ		 5891};
5892
1da177e4
LT		 5893/**
5894 * qla2x00_module_init - Module initialization.
5895 **/
5896static int __init
5897qla2x00_module_init(void)
5898{
fca29703
AV		 5899 int ret = 0;
5900
1da177e4 5901 /* Allocate cache for SRBs. */
354d6b21 5902 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 5903 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 5904 if (srb_cachep == NULL) {
7c3df132
SK		 5905 ql_log(ql_log_fatal, NULL, 0x0001,
5906 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 5907 return -ENOMEM;
5908 }
5909
2d70c103
NB		 5910 /* Initialize target kmem_cache and mem_pools */
5911 ret = qlt_init();
5912 if (ret < 0) {
5913 kmem_cache_destroy(srb_cachep);
5914 return ret;
5915 } else if (ret > 0) {
5916 /*
5917 * If initiator mode is explictly disabled by qlt_init(),
5918 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
5919 * performing scsi_scan_target() during LOOP UP event.
5920 */
5921 qla2xxx_transport_functions.disable_target_scan = 1;
5922 qla2xxx_transport_vport_functions.disable_target_scan = 1;
5923 }
5924
1da177e4
LT		 5925 /* Derive version string. */
5926 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 5927 if (ql2xextended_error_logging)
0181944f
AV		 5928 strcat(qla2x00_version_str, "-debug");
5929
1c97a12a
AV		 5930 qla2xxx_transport_template =
5931 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 5932 if (!qla2xxx_transport_template) {
5933 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 5934 ql_log(ql_log_fatal, NULL, 0x0002,
5935 "fc_attach_transport failed...Failing load!.\n");
2d70c103 5936 qlt_exit();
1da177e4 5937 return -ENODEV;
2c3dfe3f 5938 }
6a03b4cd
HZ		 5939
5940 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
5941 if (apidev_major < 0) {
7c3df132
SK		 5942 ql_log(ql_log_fatal, NULL, 0x0003,
5943 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 5944 }
5945
2c3dfe3f
SJ		 5946 qla2xxx_transport_vport_template =
5947 fc_attach_transport(&qla2xxx_transport_vport_functions);
5948 if (!qla2xxx_transport_vport_template) {
5949 kmem_cache_destroy(srb_cachep);
2d70c103 5950 qlt_exit();
2c3dfe3f 5951 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 5952 ql_log(ql_log_fatal, NULL, 0x0004,
5953 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 5954 return -ENODEV;
2c3dfe3f 5955 }
7c3df132
SK		 5956 ql_log(ql_log_info, NULL, 0x0005,
5957 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 5958 qla2x00_version_str);
7ee61397 5959 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 5960 if (ret) {
5961 kmem_cache_destroy(srb_cachep);
2d70c103 5962 qlt_exit();
fca29703 5963 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 5964 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 5965 ql_log(ql_log_fatal, NULL, 0x0006,
5966 "pci_register_driver failed...ret=%d Failing load!.\n",
5967 ret);
fca29703
AV		 5968 }
5969 return ret;
1da177e4
LT		 5970}
5971
5972/**
5973 * qla2x00_module_exit - Module cleanup.
5974 **/
5975static void __exit
5976qla2x00_module_exit(void)
5977{
6a03b4cd 5978 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 5979 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 5980 qla2x00_release_firmware();
354d6b21 5981 kmem_cache_destroy(srb_cachep);
2d70c103 5982 qlt_exit();
a9083016
GM		 5983 if (ctx_cachep)
5984 kmem_cache_destroy(ctx_cachep);
1da177e4 5985 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 5986 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 5987}
5988
5989module_init(qla2x00_module_init);
5990module_exit(qla2x00_module_exit);
5991
5992MODULE_AUTHOR("QLogic Corporation");
5993MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
5994MODULE_LICENSE("GPL");
5995MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 5996MODULE_FIRMWARE(FW_FILE_ISP21XX);
5997MODULE_FIRMWARE(FW_FILE_ISP22XX);
5998MODULE_FIRMWARE(FW_FILE_ISP2300);
5999MODULE_FIRMWARE(FW_FILE_ISP2322);
6000MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 6001MODULE_FIRMWARE(FW_FILE_ISP25XX);
f1458cda
SC		 6002MODULE_FIRMWARE(FW_FILE_ISP2031);
6003MODULE_FIRMWARE(FW_FILE_ISP8031);
6004MODULE_FIRMWARE(FW_FILE_ISP27XX);
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