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scsi: qla2xxx: Clear fc4f_nvme flag
[mirror_ubuntu-jammy-kernel.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
5601236b 16#include <linux/blk-mq-pci.h>
1da177e4
LT		 17#include <scsi/scsi_tcq.h>
18#include <scsi/scsicam.h>
19#include <scsi/scsi_transport.h>
20#include <scsi/scsi_transport_fc.h>
21
2d70c103
NB		 22#include "qla_target.h"
23
1da177e4
LT		 24/*
25 * Driver version
26 */
27char qla2x00_version_str[40];
28
6a03b4cd
HZ		 29static int apidev_major;
30
1da177e4
LT		 31/*
32 * SRB allocation cache
33 */
d7459527 34struct kmem_cache *srb_cachep;
1da177e4 35
a9083016
GM		 36/*
37 * CT6 CTX allocation cache
38 */
39static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 40/*
41 * error level for logging
42 */
43int ql_errlev = ql_log_all;
a9083016 44
fa492630 45static int ql2xenableclass2;
2d70c103
NB		 46module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
47MODULE_PARM_DESC(ql2xenableclass2,
48 "Specify if Class 2 operations are supported from the very "
49 "beginning. Default is 0 - class 2 not supported.");
50
8ae6d9c7 51
1da177e4 52int ql2xlogintimeout = 20;
f2019cb1 53module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 54MODULE_PARM_DESC(ql2xlogintimeout,
55 "Login timeout value in seconds.");
56
a7b61842 57int qlport_down_retry;
f2019cb1 58module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 59MODULE_PARM_DESC(qlport_down_retry,
900d9f98 60 "Maximum number of command retries to a port that returns "
1da177e4
LT		 61 "a PORT-DOWN status.");
62
1da177e4
LT		 63int ql2xplogiabsentdevice;
64module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
65MODULE_PARM_DESC(ql2xplogiabsentdevice,
66 "Option to enable PLOGI to devices that are not present after "
900d9f98 67 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 68 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
69
1da177e4 70int ql2xloginretrycount = 0;
f2019cb1 71module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 72MODULE_PARM_DESC(ql2xloginretrycount,
73 "Specify an alternate value for the NVRAM login retry count.");
74
a7a167bf 75int ql2xallocfwdump = 1;
f2019cb1 76module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 77MODULE_PARM_DESC(ql2xallocfwdump,
78 "Option to enable allocation of memory for a firmware dump "
79 "during HBA initialization. Memory allocation requirements "
80 "vary by ISP type. Default is 1 - allocate memory.");
81
11010fec 82int ql2xextended_error_logging;
27d94035 83module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
a2b3e01d 84module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 85MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 86 "Option to enable extended error logging,\n"
87 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
88 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
89 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
90 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
91 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
92 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
93 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
94 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 95 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
96 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 97 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 98 "\t\t0x1e400000 - Preferred value for capturing essential "
99 "debug information (equivalent to old "
100 "ql2xextended_error_logging=1).\n"
3ce8866c 101 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 102
a9083016 103int ql2xshiftctondsd = 6;
f2019cb1 104module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 105MODULE_PARM_DESC(ql2xshiftctondsd,
106 "Set to control shifting of command type processing "
107 "based on total number of SG elements.");
108
7e47e5ca 109int ql2xfdmienable=1;
de187df8 110module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
a2b3e01d 111module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
cca5335c 112MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 113 "Enables FDMI registrations. "
114 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 115
d213a4b7 116#define MAX_Q_DEPTH 64
50280c01 117static int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 118module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
119MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f 120 "Maximum queue depth to set for each LUN. "
d213a4b7 121 "Default is 64.");
df7baa50 122
e84067d7
DG		 123#if (IS_ENABLED(CONFIG_NVME_FC))
124int ql2xenabledif;
125#else
9e522cd8 126int ql2xenabledif = 2;
e84067d7 127#endif
9e522cd8 128module_param(ql2xenabledif, int, S_IRUGO);
bad75002 129MODULE_PARM_DESC(ql2xenabledif,
b97f5d0b
SM		 130 " Enable T10-CRC-DIF:\n"
131 " Default is 2.\n"
132 " 0 -- No DIF Support\n"
133 " 1 -- Enable DIF for all types\n"
134 " 2 -- Enable DIF for all types, except Type 0.\n");
bad75002 135
e84067d7
DG		 136#if (IS_ENABLED(CONFIG_NVME_FC))
137int ql2xnvmeenable = 1;
138#else
139int ql2xnvmeenable;
140#endif
141module_param(ql2xnvmeenable, int, 0644);
142MODULE_PARM_DESC(ql2xnvmeenable,
143 "Enables NVME support. "
144 "0 - no NVMe. Default is Y");
145
8cb2049c 146int ql2xenablehba_err_chk = 2;
bad75002
AE		 147module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
148MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c 149 " Enable T10-CRC-DIF Error isolation by HBA:\n"
b97f5d0b 150 " Default is 2.\n"
8cb2049c
AE		 151 " 0 -- Error isolation disabled\n"
152 " 1 -- Error isolation enabled only for DIX Type 0\n"
153 " 2 -- Error isolation enabled for all Types\n");
bad75002 154
e5896bd5 155int ql2xiidmaenable=1;
f2019cb1 156module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 157MODULE_PARM_DESC(ql2xiidmaenable,
158 "Enables iIDMA settings "
159 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
160
d7459527
MH		 161int ql2xmqsupport = 1;
162module_param(ql2xmqsupport, int, S_IRUGO);
163MODULE_PARM_DESC(ql2xmqsupport,
164 "Enable on demand multiple queue pairs support "
165 "Default is 1 for supported. "
166 "Set it to 0 to turn off mq qpair support.");
e337d907
AV		 167
168int ql2xfwloadbin;
86e45bf6 169module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
a2b3e01d 170module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 171MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 172 "Option to specify location from which to load ISP firmware:.\n"
173 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 174 " interface.\n"
175 " 1 -- load firmware from flash.\n"
176 " 0 -- use default semantics.\n");
177
ae97c91e 178int ql2xetsenable;
f2019cb1 179module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 180MODULE_PARM_DESC(ql2xetsenable,
181 "Enables firmware ETS burst."
182 "Default is 0 - skip ETS enablement.");
183
6907869d 184int ql2xdbwr = 1;
86e45bf6 185module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 186MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 187 "Option to specify scheme for request queue posting.\n"
188 " 0 -- Regular doorbell.\n"
189 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 190
f4c496c1 191int ql2xtargetreset = 1;
f2019cb1 192module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 193MODULE_PARM_DESC(ql2xtargetreset,
194 "Enable target reset."
195 "Default is 1 - use hw defaults.");
196
4da26e16 197int ql2xgffidenable;
f2019cb1 198module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 199MODULE_PARM_DESC(ql2xgffidenable,
200 "Enables GFF_ID checks of port type. "
201 "Default is 0 - Do not use GFF_ID information.");
a9083016 202
043dc1d7 203int ql2xasynctmfenable = 1;
f2019cb1 204module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 205MODULE_PARM_DESC(ql2xasynctmfenable,
206 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
207 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 208
209int ql2xdontresethba;
86e45bf6 210module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 211MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 212 "Option to specify reset behaviour.\n"
213 " 0 (Default) -- Reset on failure.\n"
214 " 1 -- Do not reset on failure.\n");
ed0de87c 215
1abf635d
HR		 216uint64_t ql2xmaxlun = MAX_LUNS;
217module_param(ql2xmaxlun, ullong, S_IRUGO);
82515920
AV		 218MODULE_PARM_DESC(ql2xmaxlun,
219 "Defines the maximum LU number to register with the SCSI "
220 "midlayer. Default is 65535.");
221
08de2844
GM		 222int ql2xmdcapmask = 0x1F;
223module_param(ql2xmdcapmask, int, S_IRUGO);
224MODULE_PARM_DESC(ql2xmdcapmask,
225 "Set the Minidump driver capture mask level. "
6e96fa7b 226 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 227
3aadff35 228int ql2xmdenable = 1;
08de2844
GM		 229module_param(ql2xmdenable, int, S_IRUGO);
230MODULE_PARM_DESC(ql2xmdenable,
231 "Enable/disable MiniDump. "
3aadff35
GM		 232 "0 - MiniDump disabled. "
233 "1 (Default) - MiniDump enabled.");
08de2844 234
b0d6cabd
HM		 235int ql2xexlogins = 0;
236module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
237MODULE_PARM_DESC(ql2xexlogins,
238 "Number of extended Logins. "
239 "0 (Default)- Disabled.");
240
99e1b683
QT		 241int ql2xexchoffld = 1024;
242module_param(ql2xexchoffld, uint, 0644);
2f56a7f1 243MODULE_PARM_DESC(ql2xexchoffld,
99e1b683
QT		 244 "Number of target exchanges.");
245
246int ql2xiniexchg = 1024;
247module_param(ql2xiniexchg, uint, 0644);
248MODULE_PARM_DESC(ql2xiniexchg,
249 "Number of initiator exchanges.");
2f56a7f1 250
f198cafa
HM		 251int ql2xfwholdabts = 0;
252module_param(ql2xfwholdabts, int, S_IRUGO);
253MODULE_PARM_DESC(ql2xfwholdabts,
254 "Allow FW to hold status IOCB until ABTS rsp received. "
255 "0 (Default) Do not set fw option. "
256 "1 - Set fw option to hold ABTS.");
257
41dc529a
QT		 258int ql2xmvasynctoatio = 1;
259module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR);
260MODULE_PARM_DESC(ql2xmvasynctoatio,
261 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ"
262 "0 (Default). Do not move IOCBs"
263 "1 - Move IOCBs.");
264
e4e3a2ce
QT		 265int ql2xautodetectsfp = 1;
266module_param(ql2xautodetectsfp, int, 0444);
267MODULE_PARM_DESC(ql2xautodetectsfp,
268 "Detect SFP range and set appropriate distance.\n"
269 "1 (Default): Enable\n");
270
1da177e4 271/*
fa2a1ce5 272 * SCSI host template entry points
1da177e4
LT		 273 */
274static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 275static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 276static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
277static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 278static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 279static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 280static int qla2xxx_eh_abort(struct scsi_cmnd *);
281static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 282static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 283static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
284static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 285
1a2fbf18 286static void qla2x00_clear_drv_active(struct qla_hw_data *);
3491255e 287static void qla2x00_free_device(scsi_qla_host_t *);
2d5a4c34 288static void qla83xx_disable_laser(scsi_qla_host_t *vha);
5601236b 289static int qla2xxx_map_queues(struct Scsi_Host *shost);
e84067d7 290static void qla2x00_destroy_deferred_work(struct qla_hw_data *);
ce7e4af7 291
a5326f86 292struct scsi_host_template qla2xxx_driver_template = {
1da177e4 293 .module = THIS_MODULE,
cb63067a 294 .name = QLA2XXX_DRIVER_NAME,
a5326f86 295 .queuecommand = qla2xxx_queuecommand,
fca29703 296
b6a05c82 297 .eh_timed_out = fc_eh_timed_out,
fca29703
AV		 298 .eh_abort_handler = qla2xxx_eh_abort,
299 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 300 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 301 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
302 .eh_host_reset_handler = qla2xxx_eh_host_reset,
303
304 .slave_configure = qla2xxx_slave_configure,
305
306 .slave_alloc = qla2xxx_slave_alloc,
307 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 308 .scan_finished = qla2xxx_scan_finished,
309 .scan_start = qla2xxx_scan_start,
db5ed4df 310 .change_queue_depth = scsi_change_queue_depth,
5601236b 311 .map_queues = qla2xxx_map_queues,
fca29703
AV		 312 .this_id = -1,
313 .cmd_per_lun = 3,
314 .use_clustering = ENABLE_CLUSTERING,
315 .sg_tablesize = SG_ALL,
316
317 .max_sectors = 0xFFFF,
afb046e2 318 .shost_attrs = qla2x00_host_attrs,
2d70c103
NB		 319
320 .supported_mode = MODE_INITIATOR,
c40ecc12 321 .track_queue_depth = 1,
fca29703
AV		 322};
323
1da177e4 324static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 325struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 326
1da177e4
LT		 327/* TODO Convert to inlines
328 *
329 * Timer routines
330 */
1da177e4 331
2c3dfe3f 332__inline__ void
e315cd28 333qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
1da177e4 334{
e315cd28
AC		 335 init_timer(&vha->timer);
336 vha->timer.expires = jiffies + interval * HZ;
337 vha->timer.data = (unsigned long)vha;
338 vha->timer.function = (void (*)(unsigned long))func;
339 add_timer(&vha->timer);
340 vha->timer_active = 1;
1da177e4
LT		 341}
342
343static inline void
e315cd28 344qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 345{
a9083016 346 /* Currently used for 82XX only. */
7c3df132
SK		 347 if (vha->device_flags & DFLG_DEV_FAILED) {
348 ql_dbg(ql_dbg_timer, vha, 0x600d,
349 "Device in a failed state, returning.\n");
a9083016 350 return;
7c3df132 351 }
a9083016 352
e315cd28 353 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 354}
355
a824ebb3 356static __inline__ void
e315cd28 357qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 358{
e315cd28
AC		 359 del_timer_sync(&vha->timer);
360 vha->timer_active = 0;
1da177e4
LT		 361}
362
1da177e4
LT		 363static int qla2x00_do_dpc(void *data);
364
365static void qla2x00_rst_aen(scsi_qla_host_t *);
366
73208dfd
AC		 367static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
368 struct req_que **, struct rsp_que **);
e30d1756 369static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 370static void qla2x00_mem_free(struct qla_hw_data *);
d7459527
MH		 371int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
372 struct qla_qpair *qpair);
1da177e4 373
1da177e4 374/* -------------------------------------------------------------------------- */
8abfa9e2
QT		 375static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req,
376 struct rsp_que *rsp)
377{
378 struct qla_hw_data *ha = vha->hw;
379 rsp->qpair = ha->base_qpair;
380 rsp->req = req;
381 ha->base_qpair->req = req;
382 ha->base_qpair->rsp = rsp;
383 ha->base_qpair->vha = vha;
384 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock;
385 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
386 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q];
387 INIT_LIST_HEAD(&ha->base_qpair->hints_list);
cf19c45d 388 INIT_LIST_HEAD(&ha->base_qpair->nvme_done_list);
8abfa9e2
QT		 389 ha->base_qpair->enable_class_2 = ql2xenableclass2;
390 /* init qpair to this cpu. Will adjust at run time. */
391 qla_cpu_update(rsp->qpair, smp_processor_id());
392 ha->base_qpair->pdev = ha->pdev;
393
394 if (IS_QLA27XX(ha) || IS_QLA83XX(ha))
395 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
396}
397
9a347ff4
CD		 398static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
399 struct rsp_que *rsp)
73208dfd 400{
7c3df132 401 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2afa19a9 402 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
73208dfd
AC		 403 GFP_KERNEL);
404 if (!ha->req_q_map) {
7c3df132
SK		 405 ql_log(ql_log_fatal, vha, 0x003b,
406 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 407 goto fail_req_map;
408 }
409
2afa19a9 410 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
73208dfd
AC		 411 GFP_KERNEL);
412 if (!ha->rsp_q_map) {
7c3df132
SK		 413 ql_log(ql_log_fatal, vha, 0x003c,
414 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 415 goto fail_rsp_map;
416 }
d7459527 417
e326d22a
QT		 418 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
419 if (ha->base_qpair == NULL) {
420 ql_log(ql_log_warn, vha, 0x00e0,
421 "Failed to allocate base queue pair memory.\n");
422 goto fail_base_qpair;
423 }
424
8abfa9e2 425 qla_init_base_qpair(vha, req, rsp);
e326d22a 426
d7459527
MH		 427 if (ql2xmqsupport && ha->max_qpairs) {
428 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *),
429 GFP_KERNEL);
430 if (!ha->queue_pair_map) {
431 ql_log(ql_log_fatal, vha, 0x0180,
432 "Unable to allocate memory for queue pair ptrs.\n");
433 goto fail_qpair_map;
434 }
d7459527
MH		 435 }
436
9a347ff4
CD		 437 /*
438 * Make sure we record at least the request and response queue zero in
439 * case we need to free them if part of the probe fails.
440 */
441 ha->rsp_q_map[0] = rsp;
442 ha->req_q_map[0] = req;
73208dfd
AC		 443 set_bit(0, ha->rsp_qid_map);
444 set_bit(0, ha->req_qid_map);
445 return 1;
446
d7459527 447fail_qpair_map:
82de802a
QT		 448 kfree(ha->base_qpair);
449 ha->base_qpair = NULL;
450fail_base_qpair:
d7459527
MH		 451 kfree(ha->rsp_q_map);
452 ha->rsp_q_map = NULL;
73208dfd
AC		 453fail_rsp_map:
454 kfree(ha->req_q_map);
455 ha->req_q_map = NULL;
456fail_req_map:
457 return -ENOMEM;
458}
459
2afa19a9 460static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 461{
8ae6d9c7
GM		 462 if (IS_QLAFX00(ha)) {
463 if (req && req->ring_fx00)
464 dma_free_coherent(&ha->pdev->dev,
465 (req->length_fx00 + 1) * sizeof(request_t),
466 req->ring_fx00, req->dma_fx00);
467 } else if (req && req->ring)
73208dfd
AC		 468 dma_free_coherent(&ha->pdev->dev,
469 (req->length + 1) * sizeof(request_t),
470 req->ring, req->dma);
471
8d93f550
CD		 472 if (req)
473 kfree(req->outstanding_cmds);
474
73208dfd 475 kfree(req);
73208dfd
AC		 476}
477
2afa19a9
AC		 478static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
479{
8ae6d9c7
GM		 480 if (IS_QLAFX00(ha)) {
481 if (rsp && rsp->ring)
482 dma_free_coherent(&ha->pdev->dev,
483 (rsp->length_fx00 + 1) * sizeof(request_t),
484 rsp->ring_fx00, rsp->dma_fx00);
485 } else if (rsp && rsp->ring) {
2afa19a9
AC		 486 dma_free_coherent(&ha->pdev->dev,
487 (rsp->length + 1) * sizeof(response_t),
488 rsp->ring, rsp->dma);
8ae6d9c7 489 }
2afa19a9 490 kfree(rsp);
2afa19a9
AC		 491}
492
73208dfd
AC		 493static void qla2x00_free_queues(struct qla_hw_data *ha)
494{
495 struct req_que *req;
496 struct rsp_que *rsp;
497 int cnt;
093df737 498 unsigned long flags;
73208dfd 499
82de802a
QT		 500 if (ha->queue_pair_map) {
501 kfree(ha->queue_pair_map);
502 ha->queue_pair_map = NULL;
503 }
504 if (ha->base_qpair) {
505 kfree(ha->base_qpair);
506 ha->base_qpair = NULL;
507 }
508
093df737 509 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 510 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
cb43285f
QT		 511 if (!test_bit(cnt, ha->req_qid_map))
512 continue;
513
73208dfd 514 req = ha->req_q_map[cnt];
093df737
QT		 515 clear_bit(cnt, ha->req_qid_map);
516 ha->req_q_map[cnt] = NULL;
517
518 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 519 qla2x00_free_req_que(ha, req);
093df737 520 spin_lock_irqsave(&ha->hardware_lock, flags);
73208dfd 521 }
093df737
QT		 522 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523
73208dfd
AC		 524 kfree(ha->req_q_map);
525 ha->req_q_map = NULL;
2afa19a9 526
093df737
QT		 527
528 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 529 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
cb43285f
QT		 530 if (!test_bit(cnt, ha->rsp_qid_map))
531 continue;
532
2afa19a9 533 rsp = ha->rsp_q_map[cnt];
c3c42394 534 clear_bit(cnt, ha->rsp_qid_map);
093df737
QT		 535 ha->rsp_q_map[cnt] = NULL;
536 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 537 qla2x00_free_rsp_que(ha, rsp);
093df737 538 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 539 }
093df737
QT		 540 spin_unlock_irqrestore(&ha->hardware_lock, flags);
541
2afa19a9
AC		 542 kfree(ha->rsp_q_map);
543 ha->rsp_q_map = NULL;
73208dfd
AC		 544}
545
1da177e4 546static char *
e315cd28 547qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 548{
e315cd28 549 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 550 static char *pci_bus_modes[] = {
551 "33", "66", "100", "133",
552 };
553 uint16_t pci_bus;
554
555 strcpy(str, "PCI");
556 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
557 if (pci_bus) {
558 strcat(str, "-X (");
559 strcat(str, pci_bus_modes[pci_bus]);
560 } else {
561 pci_bus = (ha->pci_attr & BIT_8) >> 8;
562 strcat(str, " (");
563 strcat(str, pci_bus_modes[pci_bus]);
564 }
565 strcat(str, " MHz)");
566
567 return (str);
568}
569
fca29703 570static char *
e315cd28 571qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 572{
573 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 574 struct qla_hw_data *ha = vha->hw;
fca29703 575 uint32_t pci_bus;
fca29703 576
62a276f8 577 if (pci_is_pcie(ha->pdev)) {
fca29703 578 char lwstr[6];
62a276f8 579 uint32_t lstat, lspeed, lwidth;
fca29703 580
62a276f8
BH		 581 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
582 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
583 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
fca29703
AV		 584
585 strcpy(str, "PCIe (");
49300af7
SK		 586 switch (lspeed) {
587 case 1:
c87a0d8c 588 strcat(str, "2.5GT/s ");
49300af7
SK		 589 break;
590 case 2:
c87a0d8c 591 strcat(str, "5.0GT/s ");
49300af7
SK		 592 break;
593 case 3:
594 strcat(str, "8.0GT/s ");
595 break;
596 default:
fca29703 597 strcat(str, "<unknown> ");
49300af7
SK		 598 break;
599 }
fca29703
AV		 600 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
601 strcat(str, lwstr);
602
603 return str;
604 }
605
606 strcpy(str, "PCI");
607 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
608 if (pci_bus == 0 || pci_bus == 8) {
609 strcat(str, " (");
610 strcat(str, pci_bus_modes[pci_bus >> 3]);
611 } else {
612 strcat(str, "-X ");
613 if (pci_bus & BIT_2)
614 strcat(str, "Mode 2");
615 else
616 strcat(str, "Mode 1");
617 strcat(str, " (");
618 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
619 }
620 strcat(str, " MHz)");
621
622 return str;
623}
624
e5f82ab8 625static char *
df57caba 626qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
1da177e4
LT		 627{
628 char un_str[10];
e315cd28 629 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 630
df57caba
HM		 631 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
632 ha->fw_minor_version, ha->fw_subminor_version);
1da177e4
LT		 633
634 if (ha->fw_attributes & BIT_9) {
635 strcat(str, "FLX");
636 return (str);
637 }
638
639 switch (ha->fw_attributes & 0xFF) {
640 case 0x7:
641 strcat(str, "EF");
642 break;
643 case 0x17:
644 strcat(str, "TP");
645 break;
646 case 0x37:
647 strcat(str, "IP");
648 break;
649 case 0x77:
650 strcat(str, "VI");
651 break;
652 default:
653 sprintf(un_str, "(%x)", ha->fw_attributes);
654 strcat(str, un_str);
655 break;
656 }
657 if (ha->fw_attributes & 0x100)
658 strcat(str, "X");
659
660 return (str);
661}
662
e5f82ab8 663static char *
df57caba 664qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
fca29703 665{
e315cd28 666 struct qla_hw_data *ha = vha->hw;
f0883ac6 667
df57caba 668 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
3a03eb79 669 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 670 return str;
fca29703
AV		 671}
672
9ba56b95 673void
25ff6af1 674qla2x00_sp_free_dma(void *ptr)
fca29703 675{
25ff6af1
JC		 676 srb_t *sp = ptr;
677 struct qla_hw_data *ha = sp->vha->hw;
9ba56b95 678 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
9ba56b95 679 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 680
9ba56b95
GM		 681 if (sp->flags & SRB_DMA_VALID) {
682 scsi_dma_unmap(cmd);
683 sp->flags &= ~SRB_DMA_VALID;
7c3df132 684 }
fca29703 685
9ba56b95
GM		 686 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
687 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
688 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
689 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
690 }
691
d5ff0eed
JC		 692 if (!ctx)
693 goto end;
694
9ba56b95
GM		 695 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
696 /* List assured to be having elements */
d5ff0eed 697 qla2x00_clean_dsd_pool(ha, ctx);
9ba56b95
GM		 698 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
699 }
700
701 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
d5ff0eed
JC		 702 struct crc_context *ctx0 = ctx;
703
704 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
9ba56b95
GM		 705 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
706 }
707
708 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
d5ff0eed 709 struct ct6_dsd *ctx1 = ctx;
fca29703 710
9ba56b95 711 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
d5ff0eed 712 ctx1->fcp_cmnd_dma);
9ba56b95
GM		 713 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
714 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
715 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
716 mempool_free(ctx1, ha->ctx_mempool);
9ba56b95
GM		 717 }
718
d5ff0eed 719end:
6fcd98fd 720 if (sp->type != SRB_NVME_CMD && sp->type != SRB_NVME_LS) {
7401bc18
DG		 721 CMD_SP(cmd) = NULL;
722 qla2x00_rel_sp(sp);
723 }
9ba56b95
GM		 724}
725
d7459527 726void
25ff6af1 727qla2x00_sp_compl(void *ptr, int res)
9ba56b95 728{
25ff6af1 729 srb_t *sp = ptr;
9ba56b95
GM		 730 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
731
732 cmd->result = res;
733
734 if (atomic_read(&sp->ref_count) == 0) {
25ff6af1 735 ql_dbg(ql_dbg_io, sp->vha, 0x3015,
9ba56b95
GM		 736 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
737 sp, GET_CMD_SP(sp));
738 if (ql2xextended_error_logging & ql_dbg_io)
8fbdac8c 739 WARN_ON(atomic_read(&sp->ref_count) == 0);
9ba56b95
GM		 740 return;
741 }
742 if (!atomic_dec_and_test(&sp->ref_count))
743 return;
744
f3caa990 745 sp->free(sp);
9ba56b95 746 cmd->scsi_done(cmd);
fca29703
AV		 747}
748
d7459527 749void
25ff6af1 750qla2xxx_qpair_sp_free_dma(void *ptr)
d7459527
MH		 751{
752 srb_t *sp = (srb_t *)ptr;
753 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
754 struct qla_hw_data *ha = sp->fcport->vha->hw;
755 void *ctx = GET_CMD_CTX_SP(sp);
756
757 if (sp->flags & SRB_DMA_VALID) {
758 scsi_dma_unmap(cmd);
759 sp->flags &= ~SRB_DMA_VALID;
760 }
761
762 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
763 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
764 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
765 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
766 }
767
d5ff0eed
JC		 768 if (!ctx)
769 goto end;
770
d7459527
MH		 771 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
772 /* List assured to be having elements */
d5ff0eed 773 qla2x00_clean_dsd_pool(ha, ctx);
d7459527
MH		 774 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
775 }
776
777 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
d5ff0eed
JC		 778 struct crc_context *ctx0 = ctx;
779
780 dma_pool_free(ha->dl_dma_pool, ctx, ctx0->crc_ctx_dma);
d7459527
MH		 781 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
782 }
783
784 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
d5ff0eed 785 struct ct6_dsd *ctx1 = ctx;
d7459527
MH		 786 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
787 ctx1->fcp_cmnd_dma);
788 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
789 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
790 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
791 mempool_free(ctx1, ha->ctx_mempool);
792 }
d5ff0eed 793end:
d7459527
MH		 794 CMD_SP(cmd) = NULL;
795 qla2xxx_rel_qpair_sp(sp->qpair, sp);
796}
797
798void
25ff6af1 799qla2xxx_qpair_sp_compl(void *ptr, int res)
d7459527 800{
25ff6af1 801 srb_t *sp = ptr;
d7459527
MH		 802 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
803
804 cmd->result = res;
805
806 if (atomic_read(&sp->ref_count) == 0) {
807 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3079,
808 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
809 sp, GET_CMD_SP(sp));
810 if (ql2xextended_error_logging & ql_dbg_io)
811 WARN_ON(atomic_read(&sp->ref_count) == 0);
812 return;
813 }
814 if (!atomic_dec_and_test(&sp->ref_count))
815 return;
816
f3caa990 817 sp->free(sp);
d7459527
MH		 818 cmd->scsi_done(cmd);
819}
820
8ae6d9c7
GM		 821/* If we are SP1 here, we need to still take and release the host_lock as SP1
822 * does not have the changes necessary to avoid taking host->host_lock.
823 */
1da177e4 824static int
f5e3e40b 825qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 826{
134ae078 827 scsi_qla_host_t *vha = shost_priv(host);
fca29703 828 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 829 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 830 struct qla_hw_data *ha = vha->hw;
831 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 832 srb_t *sp;
833 int rval;
5601236b
MH		 834 struct qla_qpair *qpair = NULL;
835 uint32_t tag;
836 uint16_t hwq;
fca29703 837
04dfaa53
MFO		 838 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags))) {
839 cmd->result = DID_NO_CONNECT << 16;
840 goto qc24_fail_command;
841 }
842
5601236b
MH		 843 if (ha->mqenable) {
844 if (shost_use_blk_mq(vha->host)) {
845 tag = blk_mq_unique_tag(cmd->request);
846 hwq = blk_mq_unique_tag_to_hwq(tag);
847 qpair = ha->queue_pair_map[hwq];
848 } else if (vha->vp_idx && vha->qpair) {
849 qpair = vha->qpair;
850 }
851
852 if (qpair)
853 return qla2xxx_mqueuecommand(host, cmd, qpair);
d7459527
MH		 854 }
855
85880801 856 if (ha->flags.eeh_busy) {
7c3df132 857 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 858 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 859 "PCI Channel IO permanent failure, exiting "
860 "cmd=%p.\n", cmd);
b9b12f73 861 cmd->result = DID_NO_CONNECT << 16;
7c3df132 862 } else {
5f28d2d7 863 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 864 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 865 cmd->result = DID_REQUEUE << 16;
7c3df132 866 }
14e660e6
SJ		 867 goto qc24_fail_command;
868 }
869
19a7b4ae
JSEC		 870 rval = fc_remote_port_chkready(rport);
871 if (rval) {
872 cmd->result = rval;
5f28d2d7 873 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 874 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
875 cmd, rval);
fca29703
AV		 876 goto qc24_fail_command;
877 }
878
bad75002
AE		 879 if (!vha->flags.difdix_supported &&
880 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 881 ql_dbg(ql_dbg_io, vha, 0x3004,
882 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
883 cmd);
bad75002
AE		 884 cmd->result = DID_NO_CONNECT << 16;
885 goto qc24_fail_command;
886 }
aa651be8
CD		 887
888 if (!fcport) {
889 cmd->result = DID_NO_CONNECT << 16;
890 goto qc24_fail_command;
891 }
892
fca29703
AV		 893 if (atomic_read(&fcport->state) != FCS_ONLINE) {
894 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 895 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 896 ql_dbg(ql_dbg_io, vha, 0x3005,
897 "Returning DNC, fcport_state=%d loop_state=%d.\n",
898 atomic_read(&fcport->state),
899 atomic_read(&base_vha->loop_state));
fca29703
AV		 900 cmd->result = DID_NO_CONNECT << 16;
901 goto qc24_fail_command;
902 }
7b594131 903 goto qc24_target_busy;
fca29703
AV		 904 }
905
e05fe292
CD		 906 /*
907 * Return target busy if we've received a non-zero retry_delay_timer
908 * in a FCP_RSP.
909 */
975f7d46
BP		 910 if (fcport->retry_delay_timestamp == 0) {
911 /* retry delay not set */
912 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
e05fe292
CD		 913 fcport->retry_delay_timestamp = 0;
914 else
915 goto qc24_target_busy;
916
b00ee7d7 917 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
50280c01 918 if (!sp)
f5e3e40b 919 goto qc24_host_busy;
fca29703 920
9ba56b95
GM		 921 sp->u.scmd.cmd = cmd;
922 sp->type = SRB_SCSI_CMD;
923 atomic_set(&sp->ref_count, 1);
924 CMD_SP(cmd) = (void *)sp;
925 sp->free = qla2x00_sp_free_dma;
926 sp->done = qla2x00_sp_compl;
927
e315cd28 928 rval = ha->isp_ops->start_scsi(sp);
7c3df132 929 if (rval != QLA_SUCCESS) {
53016ed3 930 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 931 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 932 goto qc24_host_busy_free_sp;
7c3df132 933 }
fca29703 934
fca29703
AV		 935 return 0;
936
937qc24_host_busy_free_sp:
f3caa990 938 sp->free(sp);
fca29703 939
f5e3e40b 940qc24_host_busy:
fca29703
AV		 941 return SCSI_MLQUEUE_HOST_BUSY;
942
7b594131
MC		 943qc24_target_busy:
944 return SCSI_MLQUEUE_TARGET_BUSY;
945
fca29703 946qc24_fail_command:
f5e3e40b 947 cmd->scsi_done(cmd);
fca29703
AV		 948
949 return 0;
950}
951
d7459527
MH		 952/* For MQ supported I/O */
953int
954qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
955 struct qla_qpair *qpair)
956{
957 scsi_qla_host_t *vha = shost_priv(host);
958 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
959 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
960 struct qla_hw_data *ha = vha->hw;
961 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
962 srb_t *sp;
963 int rval;
964
965 rval = fc_remote_port_chkready(rport);
966 if (rval) {
967 cmd->result = rval;
968 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076,
969 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
970 cmd, rval);
971 goto qc24_fail_command;
972 }
973
974 if (!fcport) {
975 cmd->result = DID_NO_CONNECT << 16;
976 goto qc24_fail_command;
977 }
978
979 if (atomic_read(&fcport->state) != FCS_ONLINE) {
980 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
981 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
982 ql_dbg(ql_dbg_io, vha, 0x3077,
983 "Returning DNC, fcport_state=%d loop_state=%d.\n",
984 atomic_read(&fcport->state),
985 atomic_read(&base_vha->loop_state));
986 cmd->result = DID_NO_CONNECT << 16;
987 goto qc24_fail_command;
988 }
989 goto qc24_target_busy;
990 }
991
992 /*
993 * Return target busy if we've received a non-zero retry_delay_timer
994 * in a FCP_RSP.
995 */
996 if (fcport->retry_delay_timestamp == 0) {
997 /* retry delay not set */
998 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
999 fcport->retry_delay_timestamp = 0;
1000 else
1001 goto qc24_target_busy;
1002
1003 sp = qla2xxx_get_qpair_sp(qpair, fcport, GFP_ATOMIC);
1004 if (!sp)
1005 goto qc24_host_busy;
1006
1007 sp->u.scmd.cmd = cmd;
1008 sp->type = SRB_SCSI_CMD;
1009 atomic_set(&sp->ref_count, 1);
1010 CMD_SP(cmd) = (void *)sp;
1011 sp->free = qla2xxx_qpair_sp_free_dma;
1012 sp->done = qla2xxx_qpair_sp_compl;
1013 sp->qpair = qpair;
1014
1015 rval = ha->isp_ops->start_scsi_mq(sp);
1016 if (rval != QLA_SUCCESS) {
1017 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078,
1018 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
1019 if (rval == QLA_INTERFACE_ERROR)
1020 goto qc24_fail_command;
1021 goto qc24_host_busy_free_sp;
1022 }
1023
1024 return 0;
1025
1026qc24_host_busy_free_sp:
f3caa990 1027 sp->free(sp);
d7459527
MH		 1028
1029qc24_host_busy:
1030 return SCSI_MLQUEUE_HOST_BUSY;
1031
1032qc24_target_busy:
1033 return SCSI_MLQUEUE_TARGET_BUSY;
1034
1035qc24_fail_command:
1036 cmd->scsi_done(cmd);
1037
1038 return 0;
1039}
1040
1da177e4
LT		 1041/*
1042 * qla2x00_eh_wait_on_command
1043 * Waits for the command to be returned by the Firmware for some
1044 * max time.
1045 *
1046 * Input:
1da177e4 1047 * cmd = Scsi Command to wait on.
1da177e4
LT		 1048 *
1049 * Return:
1050 * Not Found : 0
1051 * Found : 1
1052 */
1053static int
e315cd28 1054qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 1055{
fe74c71f 1056#define ABORT_POLLING_PERIOD 1000
478c3b03 1057#define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 1058 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 1059 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1060 struct qla_hw_data *ha = vha->hw;
f4f051eb 1061 int ret = QLA_SUCCESS;
1da177e4 1062
85880801 1063 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 1064 ql_dbg(ql_dbg_taskm, vha, 0x8005,
1065 "Return:eh_wait.\n");
85880801
AV		 1066 return ret;
1067 }
1068
d970432c 1069 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 1070 msleep(ABORT_POLLING_PERIOD);
f4f051eb
AV		 1071 }
1072 if (CMD_SP(cmd))
1073 ret = QLA_FUNCTION_FAILED;
1da177e4 1074
f4f051eb 1075 return ret;
1da177e4
LT		 1076}
1077
1078/*
1079 * qla2x00_wait_for_hba_online
fa2a1ce5 1080 * Wait till the HBA is online after going through
1da177e4
LT		 1081 * <= MAX_RETRIES_OF_ISP_ABORT or
1082 * finally HBA is disabled ie marked offline
1083 *
1084 * Input:
1085 * ha - pointer to host adapter structure
fa2a1ce5
AV		 1086 *
1087 * Note:
1da177e4
LT		 1088 * Does context switching-Release SPIN_LOCK
1089 * (if any) before calling this routine.
1090 *
1091 * Return:
1092 * Success (Adapter is online) : 0
1093 * Failed (Adapter is offline/disabled) : 1
1094 */
854165f4 1095int
e315cd28 1096qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 1097{
fca29703
AV		 1098 int return_status;
1099 unsigned long wait_online;
e315cd28
AC		 1100 struct qla_hw_data *ha = vha->hw;
1101 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1102
fa2a1ce5 1103 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 1104 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1105 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1106 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1107 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 1108
1109 msleep(1000);
1110 }
e315cd28 1111 if (base_vha->flags.online)
fa2a1ce5 1112 return_status = QLA_SUCCESS;
1da177e4
LT		 1113 else
1114 return_status = QLA_FUNCTION_FAILED;
1115
1da177e4
LT		 1116 return (return_status);
1117}
1118
726b8548
QT		 1119static inline int test_fcport_count(scsi_qla_host_t *vha)
1120{
1121 struct qla_hw_data *ha = vha->hw;
1122 unsigned long flags;
1123 int res;
1124
1125 spin_lock_irqsave(&ha->tgt.sess_lock, flags);
83548fe2
QT		 1126 ql_dbg(ql_dbg_init, vha, 0x00ec,
1127 "tgt %p, fcport_count=%d\n",
1128 vha, vha->fcport_count);
726b8548
QT		 1129 res = (vha->fcport_count == 0);
1130 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);
1131
1132 return res;
1133}
1134
1135/*
1136 * qla2x00_wait_for_sess_deletion can only be called from remove_one.
1137 * it has dependency on UNLOADING flag to stop device discovery
1138 */
1139static void
1140qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha)
1141{
1142 qla2x00_mark_all_devices_lost(vha, 0);
1143
b85e0957 1144 wait_event_timeout(vha->fcport_waitQ, test_fcport_count(vha), 10*HZ);
726b8548
QT		 1145}
1146
86fbee86 1147/*
638a1a01
SC		 1148 * qla2x00_wait_for_hba_ready
1149 * Wait till the HBA is ready before doing driver unload
86fbee86
LC		 1150 *
1151 * Input:
1152 * ha - pointer to host adapter structure
1153 *
1154 * Note:
1155 * Does context switching-Release SPIN_LOCK
1156 * (if any) before calling this routine.
1157 *
86fbee86 1158 */
638a1a01
SC		 1159static void
1160qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
86fbee86 1161{
86fbee86 1162 struct qla_hw_data *ha = vha->hw;
783e0dc4 1163 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
86fbee86 1164
1d483901
DC		 1165 while ((qla2x00_reset_active(vha) || ha->dpc_active ||
1166 ha->flags.mbox_busy) ||
1167 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
1168 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
1169 if (test_bit(UNLOADING, &base_vha->dpc_flags))
1170 break;
86fbee86 1171 msleep(1000);
783e0dc4 1172 }
86fbee86
LC		 1173}
1174
2533cf67
LC		 1175int
1176qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
1177{
1178 int return_status;
1179 unsigned long wait_reset;
1180 struct qla_hw_data *ha = vha->hw;
1181 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1182
1183 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1184 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1185 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1186 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1187 ha->dpc_active) && time_before(jiffies, wait_reset)) {
1188
1189 msleep(1000);
1190
1191 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
1192 ha->flags.chip_reset_done)
1193 break;
1194 }
1195 if (ha->flags.chip_reset_done)
1196 return_status = QLA_SUCCESS;
1197 else
1198 return_status = QLA_FUNCTION_FAILED;
1199
1200 return return_status;
1201}
1202
083a469d
GM		 1203static void
1204sp_get(struct srb *sp)
1205{
1206 atomic_inc(&sp->ref_count);
1207}
1208
a465537a
SC		 1209#define ISP_REG_DISCONNECT 0xffffffffU
1210/**************************************************************************
1211* qla2x00_isp_reg_stat
1212*
1213* Description:
1214* Read the host status register of ISP before aborting the command.
1215*
1216* Input:
1217* ha = pointer to host adapter structure.
1218*
1219*
1220* Returns:
1221* Either true or false.
1222*
1223* Note: Return true if there is register disconnect.
1224**************************************************************************/
1225static inline
1226uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha)
1227{
1228 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
bf6061b1 1229 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
a465537a 1230
bf6061b1
SC		 1231 if (IS_P3P_TYPE(ha))
1232 return ((RD_REG_DWORD(&reg82->host_int)) == ISP_REG_DISCONNECT);
1233 else
1234 return ((RD_REG_DWORD(&reg->host_status)) ==
1235 ISP_REG_DISCONNECT);
a465537a
SC		 1236}
1237
1da177e4
LT		 1238/**************************************************************************
1239* qla2xxx_eh_abort
1240*
1241* Description:
1242* The abort function will abort the specified command.
1243*
1244* Input:
1245* cmd = Linux SCSI command packet to be aborted.
1246*
1247* Returns:
1248* Either SUCCESS or FAILED.
1249*
1250* Note:
2ea00202 1251* Only return FAILED if command not returned by firmware.
1da177e4 1252**************************************************************************/
e5f82ab8 1253static int
1da177e4
LT		 1254qla2xxx_eh_abort(struct scsi_cmnd *cmd)
1255{
e315cd28 1256 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 1257 srb_t *sp;
4e98d3b8 1258 int ret;
9cb78c16
HR		 1259 unsigned int id;
1260 uint64_t lun;
18e144d3 1261 unsigned long flags;
f934c9d0 1262 int rval, wait = 0;
e315cd28 1263 struct qla_hw_data *ha = vha->hw;
1da177e4 1264
a465537a
SC		 1265 if (qla2x00_isp_reg_stat(ha)) {
1266 ql_log(ql_log_info, vha, 0x8042,
1267 "PCI/Register disconnect, exiting.\n");
1268 return FAILED;
1269 }
f4f051eb 1270 if (!CMD_SP(cmd))
2ea00202 1271 return SUCCESS;
1da177e4 1272
4e98d3b8
AV		 1273 ret = fc_block_scsi_eh(cmd);
1274 if (ret != 0)
1275 return ret;
1276 ret = SUCCESS;
1277
f4f051eb
AV		 1278 id = cmd->device->id;
1279 lun = cmd->device->lun;
1da177e4 1280
e315cd28 1281 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 1282 sp = (srb_t *) CMD_SP(cmd);
1283 if (!sp) {
1284 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1285 return SUCCESS;
1286 }
1da177e4 1287
7c3df132 1288 ql_dbg(ql_dbg_taskm, vha, 0x8002,
c7bc4cae
CD		 1289 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1290 vha->host_no, id, lun, sp, cmd, sp->handle);
17d98630 1291
170babc3
MC		 1292 /* Get a reference to the sp and drop the lock.*/
1293 sp_get(sp);
083a469d 1294
e315cd28 1295 spin_unlock_irqrestore(&ha->hardware_lock, flags);
f934c9d0
CD		 1296 rval = ha->isp_ops->abort_command(sp);
1297 if (rval) {
96219424 1298 if (rval == QLA_FUNCTION_PARAMETER_ERROR)
f934c9d0 1299 ret = SUCCESS;
96219424 1300 else
f934c9d0
CD		 1301 ret = FAILED;
1302
7c3df132 1303 ql_dbg(ql_dbg_taskm, vha, 0x8003,
f934c9d0 1304 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval);
170babc3 1305 } else {
7c3df132 1306 ql_dbg(ql_dbg_taskm, vha, 0x8004,
cfb0919c 1307 "Abort command mbx success cmd=%p.\n", cmd);
170babc3
MC		 1308 wait = 1;
1309 }
75942064
SK		 1310
1311 spin_lock_irqsave(&ha->hardware_lock, flags);
25ff6af1 1312 sp->done(sp, 0);
75942064 1313 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 1314
bc91ade9
CD		 1315 /* Did the command return during mailbox execution? */
1316 if (ret == FAILED && !CMD_SP(cmd))
1317 ret = SUCCESS;
1318
f4f051eb 1319 /* Wait for the command to be returned. */
2ea00202 1320 if (wait) {
e315cd28 1321 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132 1322 ql_log(ql_log_warn, vha, 0x8006,
cfb0919c 1323 "Abort handler timed out cmd=%p.\n", cmd);
2ea00202 1324 ret = FAILED;
f4f051eb 1325 }
1da177e4 1326 }
1da177e4 1327
7c3df132 1328 ql_log(ql_log_info, vha, 0x801c,
9cb78c16 1329 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n",
cfb0919c 1330 vha->host_no, id, lun, wait, ret);
1da177e4 1331
f4f051eb
AV		 1332 return ret;
1333}
1da177e4 1334
4d78c973 1335int
e315cd28 1336qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
9cb78c16 1337 uint64_t l, enum nexus_wait_type type)
f4f051eb 1338{
17d98630 1339 int cnt, match, status;
18e144d3 1340 unsigned long flags;
e315cd28 1341 struct qla_hw_data *ha = vha->hw;
73208dfd 1342 struct req_que *req;
4d78c973 1343 srb_t *sp;
9ba56b95 1344 struct scsi_cmnd *cmd;
1da177e4 1345
523ec773 1346 status = QLA_SUCCESS;
17d98630 1347
e315cd28 1348 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1349 req = vha->req;
17d98630 1350 for (cnt = 1; status == QLA_SUCCESS &&
8d93f550 1351 cnt < req->num_outstanding_cmds; cnt++) {
17d98630
AC		 1352 sp = req->outstanding_cmds[cnt];
1353 if (!sp)
523ec773 1354 continue;
9ba56b95 1355 if (sp->type != SRB_SCSI_CMD)
cf53b069 1356 continue;
25ff6af1 1357 if (vha->vp_idx != sp->vha->vp_idx)
17d98630
AC		 1358 continue;
1359 match = 0;
9ba56b95 1360 cmd = GET_CMD_SP(sp);
17d98630
AC		 1361 switch (type) {
1362 case WAIT_HOST:
1363 match = 1;
1364 break;
1365 case WAIT_TARGET:
9ba56b95 1366 match = cmd->device->id == t;
17d98630
AC		 1367 break;
1368 case WAIT_LUN:
9ba56b95
GM		 1369 match = (cmd->device->id == t &&
1370 cmd->device->lun == l);
17d98630 1371 break;
73208dfd 1372 }
17d98630
AC		 1373 if (!match)
1374 continue;
1375
1376 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1377 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1378 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1379 }
e315cd28 1380 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1381
1382 return status;
1da177e4
LT		 1383}
1384
523ec773
AV		 1385static char *reset_errors[] = {
1386 "HBA not online",
1387 "HBA not ready",
1388 "Task management failed",
1389 "Waiting for command completions",
1390};
1da177e4 1391
e5f82ab8 1392static int
523ec773 1393__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
9cb78c16 1394 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1da177e4 1395{
e315cd28 1396 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1397 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1398 int err;
1da177e4 1399
7c3df132 1400 if (!fcport) {
523ec773 1401 return FAILED;
7c3df132 1402 }
1da177e4 1403
4e98d3b8
AV		 1404 err = fc_block_scsi_eh(cmd);
1405 if (err != 0)
1406 return err;
1407
7c3df132 1408 ql_log(ql_log_info, vha, 0x8009,
9cb78c16 1409 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
7c3df132 1410 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1411
523ec773 1412 err = 0;
7c3df132
SK		 1413 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1414 ql_log(ql_log_warn, vha, 0x800a,
1415 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1416 goto eh_reset_failed;
7c3df132 1417 }
523ec773 1418 err = 2;
2afa19a9 1419 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1420 != QLA_SUCCESS) {
1421 ql_log(ql_log_warn, vha, 0x800c,
1422 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1423 goto eh_reset_failed;
7c3df132 1424 }
523ec773 1425 err = 3;
e315cd28 1426 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1427 cmd->device->lun, type) != QLA_SUCCESS) {
1428 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1429 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1430 goto eh_reset_failed;
7c3df132 1431 }
523ec773 1432
7c3df132 1433 ql_log(ql_log_info, vha, 0x800e,
9cb78c16 1434 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
cfb0919c 1435 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1436
1437 return SUCCESS;
1438
4d78c973 1439eh_reset_failed:
7c3df132 1440 ql_log(ql_log_info, vha, 0x800f,
9cb78c16 1441 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
cfb0919c
CD		 1442 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1443 cmd);
523ec773
AV		 1444 return FAILED;
1445}
1da177e4 1446
523ec773
AV		 1447static int
1448qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1449{
e315cd28
AC		 1450 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1451 struct qla_hw_data *ha = vha->hw;
1da177e4 1452
a465537a
SC		 1453 if (qla2x00_isp_reg_stat(ha)) {
1454 ql_log(ql_log_info, vha, 0x803e,
1455 "PCI/Register disconnect, exiting.\n");
1456 return FAILED;
1457 }
1458
523ec773
AV		 1459 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1460 ha->isp_ops->lun_reset);
1da177e4
LT		 1461}
1462
1da177e4 1463static int
523ec773 1464qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1465{
e315cd28
AC		 1466 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1467 struct qla_hw_data *ha = vha->hw;
1da177e4 1468
a465537a
SC		 1469 if (qla2x00_isp_reg_stat(ha)) {
1470 ql_log(ql_log_info, vha, 0x803f,
1471 "PCI/Register disconnect, exiting.\n");
1472 return FAILED;
1473 }
1474
523ec773
AV		 1475 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1476 ha->isp_ops->target_reset);
1da177e4
LT		 1477}
1478
1da177e4
LT		 1479/**************************************************************************
1480* qla2xxx_eh_bus_reset
1481*
1482* Description:
1483* The bus reset function will reset the bus and abort any executing
1484* commands.
1485*
1486* Input:
1487* cmd = Linux SCSI command packet of the command that cause the
1488* bus reset.
1489*
1490* Returns:
1491* SUCCESS/FAILURE (defined as macro in scsi.h).
1492*
1493**************************************************************************/
e5f82ab8 1494static int
1da177e4
LT		 1495qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1496{
e315cd28 1497 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1498 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1499 int ret = FAILED;
9cb78c16
HR		 1500 unsigned int id;
1501 uint64_t lun;
a465537a
SC		 1502 struct qla_hw_data *ha = vha->hw;
1503
1504 if (qla2x00_isp_reg_stat(ha)) {
1505 ql_log(ql_log_info, vha, 0x8040,
1506 "PCI/Register disconnect, exiting.\n");
1507 return FAILED;
1508 }
f4f051eb 1509
f4f051eb
AV		 1510 id = cmd->device->id;
1511 lun = cmd->device->lun;
1da177e4 1512
7c3df132 1513 if (!fcport) {
f4f051eb 1514 return ret;
7c3df132 1515 }
1da177e4 1516
4e98d3b8
AV		 1517 ret = fc_block_scsi_eh(cmd);
1518 if (ret != 0)
1519 return ret;
1520 ret = FAILED;
1521
7c3df132 1522 ql_log(ql_log_info, vha, 0x8012,
9cb78c16 1523 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1524
e315cd28 1525 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1526 ql_log(ql_log_fatal, vha, 0x8013,
1527 "Wait for hba online failed board disabled.\n");
f4f051eb 1528 goto eh_bus_reset_done;
1da177e4
LT		 1529 }
1530
ad537689
SK		 1531 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1532 ret = SUCCESS;
1533
f4f051eb
AV		 1534 if (ret == FAILED)
1535 goto eh_bus_reset_done;
1da177e4 1536
9a41a62b 1537 /* Flush outstanding commands. */
4d78c973 1538 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1539 QLA_SUCCESS) {
1540 ql_log(ql_log_warn, vha, 0x8014,
1541 "Wait for pending commands failed.\n");
9a41a62b 1542 ret = FAILED;
7c3df132 1543 }
1da177e4 1544
f4f051eb 1545eh_bus_reset_done:
7c3df132 1546 ql_log(ql_log_warn, vha, 0x802b,
9cb78c16 1547 "BUS RESET %s nexus=%ld:%d:%llu.\n",
d6a03581 1548 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1549
f4f051eb 1550 return ret;
1da177e4
LT		 1551}
1552
1553/**************************************************************************
1554* qla2xxx_eh_host_reset
1555*
1556* Description:
1557* The reset function will reset the Adapter.
1558*
1559* Input:
1560* cmd = Linux SCSI command packet of the command that cause the
1561* adapter reset.
1562*
1563* Returns:
1564* Either SUCCESS or FAILED.
1565*
1566* Note:
1567**************************************************************************/
e5f82ab8 1568static int
1da177e4
LT		 1569qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1570{
e315cd28 1571 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1572 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1573 int ret = FAILED;
9cb78c16
HR		 1574 unsigned int id;
1575 uint64_t lun;
e315cd28 1576 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1577
a465537a
SC		 1578 if (qla2x00_isp_reg_stat(ha)) {
1579 ql_log(ql_log_info, vha, 0x8041,
1580 "PCI/Register disconnect, exiting.\n");
1581 schedule_work(&ha->board_disable);
1582 return SUCCESS;
1583 }
1584
f4f051eb
AV		 1585 id = cmd->device->id;
1586 lun = cmd->device->lun;
f4f051eb 1587
7c3df132 1588 ql_log(ql_log_info, vha, 0x8018,
9cb78c16 1589 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1590
63ee7072
CD		 1591 /*
1592 * No point in issuing another reset if one is active. Also do not
1593 * attempt a reset if we are updating flash.
1594 */
1595 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
f4f051eb 1596 goto eh_host_reset_lock;
1da177e4 1597
e315cd28
AC		 1598 if (vha != base_vha) {
1599 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1600 goto eh_host_reset_lock;
e315cd28 1601 } else {
7ec0effd 1602 if (IS_P3P_TYPE(vha->hw)) {
a9083016
GM		 1603 if (!qla82xx_fcoe_ctx_reset(vha)) {
1604 /* Ctx reset success */
1605 ret = SUCCESS;
1606 goto eh_host_reset_lock;
1607 }
1608 /* fall thru if ctx reset failed */
1609 }
68ca949c
AC		 1610 if (ha->wq)
1611 flush_workqueue(ha->wq);
1612
e315cd28 1613 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1614 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1615 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1616 /* failed. schedule dpc to try */
1617 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1618
7c3df132
SK		 1619 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1620 ql_log(ql_log_warn, vha, 0x802a,
1621 "wait for hba online failed.\n");
e315cd28 1622 goto eh_host_reset_lock;
7c3df132 1623 }
e315cd28
AC		 1624 }
1625 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1626 }
1da177e4 1627
e315cd28 1628 /* Waiting for command to be returned to OS.*/
4d78c973 1629 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1630 QLA_SUCCESS)
f4f051eb 1631 ret = SUCCESS;
1da177e4 1632
f4f051eb 1633eh_host_reset_lock:
cfb0919c 1634 ql_log(ql_log_info, vha, 0x8017,
9cb78c16 1635 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
cfb0919c 1636 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1637
f4f051eb
AV		 1638 return ret;
1639}
1da177e4
LT		 1640
1641/*
1642* qla2x00_loop_reset
1643* Issue loop reset.
1644*
1645* Input:
1646* ha = adapter block pointer.
1647*
1648* Returns:
1649* 0 = success
1650*/
a4722cf2 1651int
e315cd28 1652qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1653{
0c8c39af 1654 int ret;
bdf79621 1655 struct fc_port *fcport;
e315cd28 1656 struct qla_hw_data *ha = vha->hw;
1da177e4 1657
5854771e
AB		 1658 if (IS_QLAFX00(ha)) {
1659 return qlafx00_loop_reset(vha);
1660 }
1661
f4c496c1 1662 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1663 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1664 if (fcport->port_type != FCT_TARGET)
1665 continue;
1666
1667 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1668 if (ret != QLA_SUCCESS) {
7c3df132 1669 ql_dbg(ql_dbg_taskm, vha, 0x802c,
5854771e 1670 "Bus Reset failed: Reset=%d "
7c3df132 1671 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1672 }
1673 }
1674 }
1675
8ae6d9c7 1676
6246b8a1 1677 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1678 atomic_set(&vha->loop_state, LOOP_DOWN);
1679 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1680 qla2x00_mark_all_devices_lost(vha, 0);
e315cd28 1681 ret = qla2x00_full_login_lip(vha);
0c8c39af 1682 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1683 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1684 "full_login_lip=%d.\n", ret);
749af3d5 1685 }
0c8c39af
AV		 1686 }
1687
0d6e61bc 1688 if (ha->flags.enable_lip_reset) {
e315cd28 1689 ret = qla2x00_lip_reset(vha);
ad537689 1690 if (ret != QLA_SUCCESS)
7c3df132
SK		 1691 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1692 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1693 }
1694
1da177e4 1695 /* Issue marker command only when we are going to start the I/O */
e315cd28 1696 vha->marker_needed = 1;
1da177e4 1697
0c8c39af 1698 return QLA_SUCCESS;
1da177e4
LT		 1699}
1700
df4bf0bb 1701void
e315cd28 1702qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
df4bf0bb 1703{
4cd3b6eb 1704 int que, cnt, status;
df4bf0bb
AV		 1705 unsigned long flags;
1706 srb_t *sp;
e315cd28 1707 struct qla_hw_data *ha = vha->hw;
73208dfd 1708 struct req_que *req;
c5419e26
QT		 1709 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt;
1710 struct qla_tgt_cmd *cmd;
1711 uint8_t trace = 0;
c0cb4496 1712
df4bf0bb 1713 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 1714 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 1715 req = ha->req_q_map[que];
73208dfd
AC		 1716 if (!req)
1717 continue;
8d93f550
CD		 1718 if (!req->outstanding_cmds)
1719 continue;
1720 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
73208dfd 1721 sp = req->outstanding_cmds[cnt];
e612d465 1722 if (sp) {
c5419e26
QT		 1723 req->outstanding_cmds[cnt] = NULL;
1724 if (sp->cmd_type == TYPE_SRB) {
6fcd98fd 1725 if (sp->type == SRB_NVME_CMD ||
1726 sp->type == SRB_NVME_LS) {
e84067d7
DG		 1727 sp_get(sp);
1728 spin_unlock_irqrestore(
1729 &ha->hardware_lock, flags);
1730 qla_nvme_abort(ha, sp);
1731 spin_lock_irqsave(
1732 &ha->hardware_lock, flags);
1733 } else if (GET_CMD_SP(sp) &&
c5419e26 1734 !ha->flags.eeh_busy &&
d61cca60
SC		 1735 (!test_bit(ABORT_ISP_ACTIVE,
1736 &vha->dpc_flags)) &&
c5419e26
QT		 1737 (sp->type == SRB_SCSI_CMD)) {
1738 /*
e84067d7
DG		 1739 * Don't abort commands in
1740 * adapter during EEH
1741 * recovery as it's not
1742 * accessible/responding.
1743 *
c5419e26
QT		 1744 * Get a reference to the sp
1745 * and drop the lock. The
1746 * reference ensures this
1747 * sp->done() call and not the
1748 * call in qla2xxx_eh_abort()
1749 * ends the SCSI command (with
1750 * result 'res').
1751 */
1752 sp_get(sp);
1753 spin_unlock_irqrestore(
1754 &ha->hardware_lock, flags);
1755 status = qla2xxx_eh_abort(
1756 GET_CMD_SP(sp));
1757 spin_lock_irqsave(
1758 &ha->hardware_lock, flags);
1759 /*
1760 * Get rid of extra reference
1761 * if immediate exit from
1762 * ql2xxx_eh_abort
1763 */
1764 if (status == FAILED &&
1765 (qla2x00_isp_reg_stat(ha)))
1766 atomic_dec(
1767 &sp->ref_count);
1768 }
1769 sp->done(sp, res);
1770 } else {
1771 if (!vha->hw->tgt.tgt_ops || !tgt ||
1772 qla_ini_mode_enabled(vha)) {
1773 if (!trace)
1774 ql_dbg(ql_dbg_tgt_mgt,
1775 vha, 0xf003,
1776 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n",
1777 vha->dpc_flags);
1778 continue;
1779 }
1780 cmd = (struct qla_tgt_cmd *)sp;
1781 qlt_abort_cmd_on_host_reset(cmd->vha,
1782 cmd);
c733ab35 1783 }
73208dfd 1784 }
df4bf0bb
AV		 1785 }
1786 }
1787 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1788}
1789
f4f051eb
AV		 1790static int
1791qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1792{
bdf79621 1793 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1794
19a7b4ae 1795 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1796 return -ENXIO;
bdf79621 1797
19a7b4ae 1798 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1799
f4f051eb
AV		 1800 return 0;
1801}
1da177e4 1802
f4f051eb
AV		 1803static int
1804qla2xxx_slave_configure(struct scsi_device *sdev)
1805{
e315cd28 1806 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1807 struct req_que *req = vha->req;
8482e118 1808
9e522cd8
AE		 1809 if (IS_T10_PI_CAPABLE(vha->hw))
1810 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1811
db5ed4df 1812 scsi_change_queue_depth(sdev, req->max_q_depth);
f4f051eb
AV		 1813 return 0;
1814}
1da177e4 1815
f4f051eb
AV		 1816static void
1817qla2xxx_slave_destroy(struct scsi_device *sdev)
1818{
1819 sdev->hostdata = NULL;
1da177e4
LT		 1820}
1821
1822/**
1823 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1824 * @ha: HA context
1825 *
1826 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1827 * supported addressing method.
1828 */
1829static void
53303c42 1830qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1831{
7524f9b9 1832 /* Assume a 32bit DMA mask. */
1da177e4 1833 ha->flags.enable_64bit_addressing = 0;
1da177e4 1834
6a35528a 1835 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1836 /* Any upper-dword bits set? */
1837 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1838 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1839 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1840 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1841 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1842 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1843 return;
1da177e4 1844 }
1da177e4 1845 }
7524f9b9 1846
284901a9
YH		 1847 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1848 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1849}
1850
fd34f556 1851static void
e315cd28 1852qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1853{
1854 unsigned long flags = 0;
1855 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1856
1857 spin_lock_irqsave(&ha->hardware_lock, flags);
1858 ha->interrupts_on = 1;
1859 /* enable risc and host interrupts */
1860 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1861 RD_REG_WORD(&reg->ictrl);
1862 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1863
1864}
1865
1866static void
e315cd28 1867qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1868{
1869 unsigned long flags = 0;
1870 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1871
1872 spin_lock_irqsave(&ha->hardware_lock, flags);
1873 ha->interrupts_on = 0;
1874 /* disable risc and host interrupts */
1875 WRT_REG_WORD(&reg->ictrl, 0);
1876 RD_REG_WORD(&reg->ictrl);
1877 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1878}
1879
1880static void
e315cd28 1881qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1882{
1883 unsigned long flags = 0;
1884 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1885
1886 spin_lock_irqsave(&ha->hardware_lock, flags);
1887 ha->interrupts_on = 1;
1888 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1889 RD_REG_DWORD(&reg->ictrl);
1890 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1891}
1892
1893static void
e315cd28 1894qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1895{
1896 unsigned long flags = 0;
1897 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1898
124f85e6
AV		 1899 if (IS_NOPOLLING_TYPE(ha))
1900 return;
fd34f556
AV		 1901 spin_lock_irqsave(&ha->hardware_lock, flags);
1902 ha->interrupts_on = 0;
1903 WRT_REG_DWORD(&reg->ictrl, 0);
1904 RD_REG_DWORD(&reg->ictrl);
1905 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1906}
1907
706f457d
GM		 1908static int
1909qla2x00_iospace_config(struct qla_hw_data *ha)
1910{
1911 resource_size_t pio;
1912 uint16_t msix;
706f457d 1913
706f457d
GM		 1914 if (pci_request_selected_regions(ha->pdev, ha->bars,
1915 QLA2XXX_DRIVER_NAME)) {
1916 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1917 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1918 pci_name(ha->pdev));
1919 goto iospace_error_exit;
1920 }
1921 if (!(ha->bars & 1))
1922 goto skip_pio;
1923
1924 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1925 pio = pci_resource_start(ha->pdev, 0);
1926 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1927 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1928 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1929 "Invalid pci I/O region size (%s).\n",
1930 pci_name(ha->pdev));
1931 pio = 0;
1932 }
1933 } else {
1934 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1935 "Region #0 no a PIO resource (%s).\n",
1936 pci_name(ha->pdev));
1937 pio = 0;
1938 }
1939 ha->pio_address = pio;
1940 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1941 "PIO address=%llu.\n",
1942 (unsigned long long)ha->pio_address);
1943
1944skip_pio:
1945 /* Use MMIO operations for all accesses. */
1946 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1947 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1948 "Region #1 not an MMIO resource (%s), aborting.\n",
1949 pci_name(ha->pdev));
1950 goto iospace_error_exit;
1951 }
1952 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1953 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1954 "Invalid PCI mem region size (%s), aborting.\n",
1955 pci_name(ha->pdev));
1956 goto iospace_error_exit;
1957 }
1958
1959 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1960 if (!ha->iobase) {
1961 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1962 "Cannot remap MMIO (%s), aborting.\n",
1963 pci_name(ha->pdev));
1964 goto iospace_error_exit;
1965 }
1966
1967 /* Determine queue resources */
1968 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 1969 ha->msix_count = QLA_BASE_VECTORS;
d7459527 1970 if (!ql2xmqsupport || (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
706f457d
GM		 1971 goto mqiobase_exit;
1972
1973 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1974 pci_resource_len(ha->pdev, 3));
1975 if (ha->mqiobase) {
1976 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1977 "MQIO Base=%p.\n", ha->mqiobase);
1978 /* Read MSIX vector size of the board */
1979 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
d7459527 1980 ha->msix_count = msix + 1;
706f457d 1981 /* Max queues are bounded by available msix vectors */
d7459527
MH		 1982 /* MB interrupt uses 1 vector */
1983 ha->max_req_queues = ha->msix_count - 1;
1984 ha->max_rsp_queues = ha->max_req_queues;
1985 /* Queue pairs is the max value minus the base queue pair */
1986 ha->max_qpairs = ha->max_rsp_queues - 1;
1987 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
1988 "Max no of queues pairs: %d.\n", ha->max_qpairs);
1989
706f457d 1990 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
d7459527 1991 "MSI-X vector count: %d.\n", ha->msix_count);
706f457d
GM		 1992 } else
1993 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1994 "BAR 3 not enabled.\n");
1995
1996mqiobase_exit:
706f457d 1997 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
f54f2cb5 1998 "MSIX Count: %d.\n", ha->msix_count);
706f457d
GM		 1999 return (0);
2000
2001iospace_error_exit:
2002 return (-ENOMEM);
2003}
2004
2005
6246b8a1
GM		 2006static int
2007qla83xx_iospace_config(struct qla_hw_data *ha)
2008{
2009 uint16_t msix;
6246b8a1
GM		 2010
2011 if (pci_request_selected_regions(ha->pdev, ha->bars,
2012 QLA2XXX_DRIVER_NAME)) {
2013 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
2014 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
2015 pci_name(ha->pdev));
2016
2017 goto iospace_error_exit;
2018 }
2019
2020 /* Use MMIO operations for all accesses. */
2021 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
2022 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
2023 "Invalid pci I/O region size (%s).\n",
2024 pci_name(ha->pdev));
2025 goto iospace_error_exit;
2026 }
2027 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2028 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
2029 "Invalid PCI mem region size (%s), aborting\n",
2030 pci_name(ha->pdev));
2031 goto iospace_error_exit;
2032 }
2033
2034 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
2035 if (!ha->iobase) {
2036 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
2037 "Cannot remap MMIO (%s), aborting.\n",
2038 pci_name(ha->pdev));
2039 goto iospace_error_exit;
2040 }
2041
2042 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
2043 /* 83XX 26XX always use MQ type access for queues
2044 * - mbar 2, a.k.a region 4 */
2045 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 2046 ha->msix_count = QLA_BASE_VECTORS;
6246b8a1
GM		 2047 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
2048 pci_resource_len(ha->pdev, 4));
2049
2050 if (!ha->mqiobase) {
2051 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
2052 "BAR2/region4 not enabled\n");
2053 goto mqiobase_exit;
2054 }
2055
2056 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
2057 pci_resource_len(ha->pdev, 2));
2058 if (ha->msixbase) {
2059 /* Read MSIX vector size of the board */
2060 pci_read_config_word(ha->pdev,
2061 QLA_83XX_PCI_MSIX_CONTROL, &msix);
e326d22a 2062 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1;
093df737
QT		 2063 /*
2064 * By default, driver uses at least two msix vectors
2065 * (default & rspq)
2066 */
d7459527
MH		 2067 if (ql2xmqsupport) {
2068 /* MB interrupt uses 1 vector */
2069 ha->max_req_queues = ha->msix_count - 1;
093df737
QT		 2070
2071 /* ATIOQ needs 1 vector. That's 1 less QPair */
2072 if (QLA_TGT_MODE_ENABLED())
2073 ha->max_req_queues--;
2074
d0d2c68b
MH		 2075 ha->max_rsp_queues = ha->max_req_queues;
2076
d7459527
MH		 2077 /* Queue pairs is the max value minus
2078 * the base queue pair */
2079 ha->max_qpairs = ha->max_req_queues - 1;
83548fe2 2080 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3,
d7459527 2081 "Max no of queues pairs: %d.\n", ha->max_qpairs);
6246b8a1
GM		 2082 }
2083 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
d7459527 2084 "MSI-X vector count: %d.\n", ha->msix_count);
6246b8a1
GM		 2085 } else
2086 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
2087 "BAR 1 not enabled.\n");
2088
2089mqiobase_exit:
6246b8a1 2090 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
f54f2cb5 2091 "MSIX Count: %d.\n", ha->msix_count);
6246b8a1
GM		 2092 return 0;
2093
2094iospace_error_exit:
2095 return -ENOMEM;
2096}
2097
fd34f556
AV		 2098static struct isp_operations qla2100_isp_ops = {
2099 .pci_config = qla2100_pci_config,
2100 .reset_chip = qla2x00_reset_chip,
2101 .chip_diag = qla2x00_chip_diag,
2102 .config_rings = qla2x00_config_rings,
2103 .reset_adapter = qla2x00_reset_adapter,
2104 .nvram_config = qla2x00_nvram_config,
2105 .update_fw_options = qla2x00_update_fw_options,
2106 .load_risc = qla2x00_load_risc,
2107 .pci_info_str = qla2x00_pci_info_str,
2108 .fw_version_str = qla2x00_fw_version_str,
2109 .intr_handler = qla2100_intr_handler,
2110 .enable_intrs = qla2x00_enable_intrs,
2111 .disable_intrs = qla2x00_disable_intrs,
2112 .abort_command = qla2x00_abort_command,
523ec773
AV		 2113 .target_reset = qla2x00_abort_target,
2114 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2115 .fabric_login = qla2x00_login_fabric,
2116 .fabric_logout = qla2x00_fabric_logout,
2117 .calc_req_entries = qla2x00_calc_iocbs_32,
2118 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2119 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2120 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2121 .read_nvram = qla2x00_read_nvram_data,
2122 .write_nvram = qla2x00_write_nvram_data,
2123 .fw_dump = qla2100_fw_dump,
2124 .beacon_on = NULL,
2125 .beacon_off = NULL,
2126 .beacon_blink = NULL,
2127 .read_optrom = qla2x00_read_optrom_data,
2128 .write_optrom = qla2x00_write_optrom_data,
2129 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2130 .start_scsi = qla2x00_start_scsi,
d7459527 2131 .start_scsi_mq = NULL,
a9083016 2132 .abort_isp = qla2x00_abort_isp,
706f457d 2133 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2134 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2135};
2136
2137static struct isp_operations qla2300_isp_ops = {
2138 .pci_config = qla2300_pci_config,
2139 .reset_chip = qla2x00_reset_chip,
2140 .chip_diag = qla2x00_chip_diag,
2141 .config_rings = qla2x00_config_rings,
2142 .reset_adapter = qla2x00_reset_adapter,
2143 .nvram_config = qla2x00_nvram_config,
2144 .update_fw_options = qla2x00_update_fw_options,
2145 .load_risc = qla2x00_load_risc,
2146 .pci_info_str = qla2x00_pci_info_str,
2147 .fw_version_str = qla2x00_fw_version_str,
2148 .intr_handler = qla2300_intr_handler,
2149 .enable_intrs = qla2x00_enable_intrs,
2150 .disable_intrs = qla2x00_disable_intrs,
2151 .abort_command = qla2x00_abort_command,
523ec773
AV		 2152 .target_reset = qla2x00_abort_target,
2153 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2154 .fabric_login = qla2x00_login_fabric,
2155 .fabric_logout = qla2x00_fabric_logout,
2156 .calc_req_entries = qla2x00_calc_iocbs_32,
2157 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2158 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2159 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2160 .read_nvram = qla2x00_read_nvram_data,
2161 .write_nvram = qla2x00_write_nvram_data,
2162 .fw_dump = qla2300_fw_dump,
2163 .beacon_on = qla2x00_beacon_on,
2164 .beacon_off = qla2x00_beacon_off,
2165 .beacon_blink = qla2x00_beacon_blink,
2166 .read_optrom = qla2x00_read_optrom_data,
2167 .write_optrom = qla2x00_write_optrom_data,
2168 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2169 .start_scsi = qla2x00_start_scsi,
d7459527 2170 .start_scsi_mq = NULL,
a9083016 2171 .abort_isp = qla2x00_abort_isp,
7ec0effd 2172 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2173 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2174};
2175
2176static struct isp_operations qla24xx_isp_ops = {
2177 .pci_config = qla24xx_pci_config,
2178 .reset_chip = qla24xx_reset_chip,
2179 .chip_diag = qla24xx_chip_diag,
2180 .config_rings = qla24xx_config_rings,
2181 .reset_adapter = qla24xx_reset_adapter,
2182 .nvram_config = qla24xx_nvram_config,
2183 .update_fw_options = qla24xx_update_fw_options,
2184 .load_risc = qla24xx_load_risc,
2185 .pci_info_str = qla24xx_pci_info_str,
2186 .fw_version_str = qla24xx_fw_version_str,
2187 .intr_handler = qla24xx_intr_handler,
2188 .enable_intrs = qla24xx_enable_intrs,
2189 .disable_intrs = qla24xx_disable_intrs,
2190 .abort_command = qla24xx_abort_command,
523ec773
AV		 2191 .target_reset = qla24xx_abort_target,
2192 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 2193 .fabric_login = qla24xx_login_fabric,
2194 .fabric_logout = qla24xx_fabric_logout,
2195 .calc_req_entries = NULL,
2196 .build_iocbs = NULL,
2197 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2198 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2199 .read_nvram = qla24xx_read_nvram_data,
2200 .write_nvram = qla24xx_write_nvram_data,
2201 .fw_dump = qla24xx_fw_dump,
2202 .beacon_on = qla24xx_beacon_on,
2203 .beacon_off = qla24xx_beacon_off,
2204 .beacon_blink = qla24xx_beacon_blink,
2205 .read_optrom = qla24xx_read_optrom_data,
2206 .write_optrom = qla24xx_write_optrom_data,
2207 .get_flash_version = qla24xx_get_flash_version,
e315cd28 2208 .start_scsi = qla24xx_start_scsi,
d7459527 2209 .start_scsi_mq = NULL,
a9083016 2210 .abort_isp = qla2x00_abort_isp,
7ec0effd 2211 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2212 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2213};
2214
c3a2f0df
AV		 2215static struct isp_operations qla25xx_isp_ops = {
2216 .pci_config = qla25xx_pci_config,
2217 .reset_chip = qla24xx_reset_chip,
2218 .chip_diag = qla24xx_chip_diag,
2219 .config_rings = qla24xx_config_rings,
2220 .reset_adapter = qla24xx_reset_adapter,
2221 .nvram_config = qla24xx_nvram_config,
2222 .update_fw_options = qla24xx_update_fw_options,
2223 .load_risc = qla24xx_load_risc,
2224 .pci_info_str = qla24xx_pci_info_str,
2225 .fw_version_str = qla24xx_fw_version_str,
2226 .intr_handler = qla24xx_intr_handler,
2227 .enable_intrs = qla24xx_enable_intrs,
2228 .disable_intrs = qla24xx_disable_intrs,
2229 .abort_command = qla24xx_abort_command,
523ec773
AV		 2230 .target_reset = qla24xx_abort_target,
2231 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 2232 .fabric_login = qla24xx_login_fabric,
2233 .fabric_logout = qla24xx_fabric_logout,
2234 .calc_req_entries = NULL,
2235 .build_iocbs = NULL,
2236 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2237 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2238 .read_nvram = qla25xx_read_nvram_data,
2239 .write_nvram = qla25xx_write_nvram_data,
2240 .fw_dump = qla25xx_fw_dump,
2241 .beacon_on = qla24xx_beacon_on,
2242 .beacon_off = qla24xx_beacon_off,
2243 .beacon_blink = qla24xx_beacon_blink,
338c9161 2244 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 2245 .write_optrom = qla24xx_write_optrom_data,
2246 .get_flash_version = qla24xx_get_flash_version,
bad75002 2247 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2248 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2249 .abort_isp = qla2x00_abort_isp,
7ec0effd 2250 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2251 .initialize_adapter = qla2x00_initialize_adapter,
c3a2f0df
AV		 2252};
2253
3a03eb79
AV		 2254static struct isp_operations qla81xx_isp_ops = {
2255 .pci_config = qla25xx_pci_config,
2256 .reset_chip = qla24xx_reset_chip,
2257 .chip_diag = qla24xx_chip_diag,
2258 .config_rings = qla24xx_config_rings,
2259 .reset_adapter = qla24xx_reset_adapter,
2260 .nvram_config = qla81xx_nvram_config,
2261 .update_fw_options = qla81xx_update_fw_options,
eaac30be 2262 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 2263 .pci_info_str = qla24xx_pci_info_str,
2264 .fw_version_str = qla24xx_fw_version_str,
2265 .intr_handler = qla24xx_intr_handler,
2266 .enable_intrs = qla24xx_enable_intrs,
2267 .disable_intrs = qla24xx_disable_intrs,
2268 .abort_command = qla24xx_abort_command,
2269 .target_reset = qla24xx_abort_target,
2270 .lun_reset = qla24xx_lun_reset,
2271 .fabric_login = qla24xx_login_fabric,
2272 .fabric_logout = qla24xx_fabric_logout,
2273 .calc_req_entries = NULL,
2274 .build_iocbs = NULL,
2275 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2276 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 2277 .read_nvram = NULL,
2278 .write_nvram = NULL,
3a03eb79
AV		 2279 .fw_dump = qla81xx_fw_dump,
2280 .beacon_on = qla24xx_beacon_on,
2281 .beacon_off = qla24xx_beacon_off,
6246b8a1 2282 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 2283 .read_optrom = qla25xx_read_optrom_data,
2284 .write_optrom = qla24xx_write_optrom_data,
2285 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 2286 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2287 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2288 .abort_isp = qla2x00_abort_isp,
7ec0effd 2289 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2290 .initialize_adapter = qla2x00_initialize_adapter,
a9083016
GM		 2291};
2292
2293static struct isp_operations qla82xx_isp_ops = {
2294 .pci_config = qla82xx_pci_config,
2295 .reset_chip = qla82xx_reset_chip,
2296 .chip_diag = qla24xx_chip_diag,
2297 .config_rings = qla82xx_config_rings,
2298 .reset_adapter = qla24xx_reset_adapter,
2299 .nvram_config = qla81xx_nvram_config,
2300 .update_fw_options = qla24xx_update_fw_options,
2301 .load_risc = qla82xx_load_risc,
9d55ca66 2302 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 2303 .fw_version_str = qla24xx_fw_version_str,
2304 .intr_handler = qla82xx_intr_handler,
2305 .enable_intrs = qla82xx_enable_intrs,
2306 .disable_intrs = qla82xx_disable_intrs,
2307 .abort_command = qla24xx_abort_command,
2308 .target_reset = qla24xx_abort_target,
2309 .lun_reset = qla24xx_lun_reset,
2310 .fabric_login = qla24xx_login_fabric,
2311 .fabric_logout = qla24xx_fabric_logout,
2312 .calc_req_entries = NULL,
2313 .build_iocbs = NULL,
2314 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2315 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2316 .read_nvram = qla24xx_read_nvram_data,
2317 .write_nvram = qla24xx_write_nvram_data,
a1b23c5a 2318 .fw_dump = qla82xx_fw_dump,
999916dc
SK		 2319 .beacon_on = qla82xx_beacon_on,
2320 .beacon_off = qla82xx_beacon_off,
2321 .beacon_blink = NULL,
a9083016
GM		 2322 .read_optrom = qla82xx_read_optrom_data,
2323 .write_optrom = qla82xx_write_optrom_data,
7ec0effd 2324 .get_flash_version = qla82xx_get_flash_version,
a9083016 2325 .start_scsi = qla82xx_start_scsi,
d7459527 2326 .start_scsi_mq = NULL,
a9083016 2327 .abort_isp = qla82xx_abort_isp,
706f457d 2328 .iospace_config = qla82xx_iospace_config,
8ae6d9c7 2329 .initialize_adapter = qla2x00_initialize_adapter,
3a03eb79
AV		 2330};
2331
7ec0effd
AD		 2332static struct isp_operations qla8044_isp_ops = {
2333 .pci_config = qla82xx_pci_config,
2334 .reset_chip = qla82xx_reset_chip,
2335 .chip_diag = qla24xx_chip_diag,
2336 .config_rings = qla82xx_config_rings,
2337 .reset_adapter = qla24xx_reset_adapter,
2338 .nvram_config = qla81xx_nvram_config,
2339 .update_fw_options = qla24xx_update_fw_options,
2340 .load_risc = qla82xx_load_risc,
2341 .pci_info_str = qla24xx_pci_info_str,
2342 .fw_version_str = qla24xx_fw_version_str,
2343 .intr_handler = qla8044_intr_handler,
2344 .enable_intrs = qla82xx_enable_intrs,
2345 .disable_intrs = qla82xx_disable_intrs,
2346 .abort_command = qla24xx_abort_command,
2347 .target_reset = qla24xx_abort_target,
2348 .lun_reset = qla24xx_lun_reset,
2349 .fabric_login = qla24xx_login_fabric,
2350 .fabric_logout = qla24xx_fabric_logout,
2351 .calc_req_entries = NULL,
2352 .build_iocbs = NULL,
2353 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2354 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2355 .read_nvram = NULL,
2356 .write_nvram = NULL,
a1b23c5a 2357 .fw_dump = qla8044_fw_dump,
7ec0effd
AD		 2358 .beacon_on = qla82xx_beacon_on,
2359 .beacon_off = qla82xx_beacon_off,
2360 .beacon_blink = NULL,
888e639d 2361 .read_optrom = qla8044_read_optrom_data,
7ec0effd
AD		 2362 .write_optrom = qla8044_write_optrom_data,
2363 .get_flash_version = qla82xx_get_flash_version,
2364 .start_scsi = qla82xx_start_scsi,
d7459527 2365 .start_scsi_mq = NULL,
7ec0effd
AD		 2366 .abort_isp = qla8044_abort_isp,
2367 .iospace_config = qla82xx_iospace_config,
2368 .initialize_adapter = qla2x00_initialize_adapter,
2369};
2370
6246b8a1
GM		 2371static struct isp_operations qla83xx_isp_ops = {
2372 .pci_config = qla25xx_pci_config,
2373 .reset_chip = qla24xx_reset_chip,
2374 .chip_diag = qla24xx_chip_diag,
2375 .config_rings = qla24xx_config_rings,
2376 .reset_adapter = qla24xx_reset_adapter,
2377 .nvram_config = qla81xx_nvram_config,
2378 .update_fw_options = qla81xx_update_fw_options,
2379 .load_risc = qla81xx_load_risc,
2380 .pci_info_str = qla24xx_pci_info_str,
2381 .fw_version_str = qla24xx_fw_version_str,
2382 .intr_handler = qla24xx_intr_handler,
2383 .enable_intrs = qla24xx_enable_intrs,
2384 .disable_intrs = qla24xx_disable_intrs,
2385 .abort_command = qla24xx_abort_command,
2386 .target_reset = qla24xx_abort_target,
2387 .lun_reset = qla24xx_lun_reset,
2388 .fabric_login = qla24xx_login_fabric,
2389 .fabric_logout = qla24xx_fabric_logout,
2390 .calc_req_entries = NULL,
2391 .build_iocbs = NULL,
2392 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2393 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2394 .read_nvram = NULL,
2395 .write_nvram = NULL,
2396 .fw_dump = qla83xx_fw_dump,
2397 .beacon_on = qla24xx_beacon_on,
2398 .beacon_off = qla24xx_beacon_off,
2399 .beacon_blink = qla83xx_beacon_blink,
2400 .read_optrom = qla25xx_read_optrom_data,
2401 .write_optrom = qla24xx_write_optrom_data,
2402 .get_flash_version = qla24xx_get_flash_version,
2403 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2404 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
6246b8a1
GM		 2405 .abort_isp = qla2x00_abort_isp,
2406 .iospace_config = qla83xx_iospace_config,
8ae6d9c7
GM		 2407 .initialize_adapter = qla2x00_initialize_adapter,
2408};
2409
2410static struct isp_operations qlafx00_isp_ops = {
2411 .pci_config = qlafx00_pci_config,
2412 .reset_chip = qlafx00_soft_reset,
2413 .chip_diag = qlafx00_chip_diag,
2414 .config_rings = qlafx00_config_rings,
2415 .reset_adapter = qlafx00_soft_reset,
2416 .nvram_config = NULL,
2417 .update_fw_options = NULL,
2418 .load_risc = NULL,
2419 .pci_info_str = qlafx00_pci_info_str,
2420 .fw_version_str = qlafx00_fw_version_str,
2421 .intr_handler = qlafx00_intr_handler,
2422 .enable_intrs = qlafx00_enable_intrs,
2423 .disable_intrs = qlafx00_disable_intrs,
4440e46d 2424 .abort_command = qla24xx_async_abort_command,
8ae6d9c7
GM		 2425 .target_reset = qlafx00_abort_target,
2426 .lun_reset = qlafx00_lun_reset,
2427 .fabric_login = NULL,
2428 .fabric_logout = NULL,
2429 .calc_req_entries = NULL,
2430 .build_iocbs = NULL,
2431 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2432 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2433 .read_nvram = qla24xx_read_nvram_data,
2434 .write_nvram = qla24xx_write_nvram_data,
2435 .fw_dump = NULL,
2436 .beacon_on = qla24xx_beacon_on,
2437 .beacon_off = qla24xx_beacon_off,
2438 .beacon_blink = NULL,
2439 .read_optrom = qla24xx_read_optrom_data,
2440 .write_optrom = qla24xx_write_optrom_data,
2441 .get_flash_version = qla24xx_get_flash_version,
2442 .start_scsi = qlafx00_start_scsi,
d7459527 2443 .start_scsi_mq = NULL,
8ae6d9c7
GM		 2444 .abort_isp = qlafx00_abort_isp,
2445 .iospace_config = qlafx00_iospace_config,
2446 .initialize_adapter = qlafx00_initialize_adapter,
6246b8a1
GM		 2447};
2448
f73cb695
CD		 2449static struct isp_operations qla27xx_isp_ops = {
2450 .pci_config = qla25xx_pci_config,
2451 .reset_chip = qla24xx_reset_chip,
2452 .chip_diag = qla24xx_chip_diag,
2453 .config_rings = qla24xx_config_rings,
2454 .reset_adapter = qla24xx_reset_adapter,
2455 .nvram_config = qla81xx_nvram_config,
2456 .update_fw_options = qla81xx_update_fw_options,
2457 .load_risc = qla81xx_load_risc,
2458 .pci_info_str = qla24xx_pci_info_str,
2459 .fw_version_str = qla24xx_fw_version_str,
2460 .intr_handler = qla24xx_intr_handler,
2461 .enable_intrs = qla24xx_enable_intrs,
2462 .disable_intrs = qla24xx_disable_intrs,
2463 .abort_command = qla24xx_abort_command,
2464 .target_reset = qla24xx_abort_target,
2465 .lun_reset = qla24xx_lun_reset,
2466 .fabric_login = qla24xx_login_fabric,
2467 .fabric_logout = qla24xx_fabric_logout,
2468 .calc_req_entries = NULL,
2469 .build_iocbs = NULL,
2470 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2471 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2472 .read_nvram = NULL,
2473 .write_nvram = NULL,
2474 .fw_dump = qla27xx_fwdump,
2475 .beacon_on = qla24xx_beacon_on,
2476 .beacon_off = qla24xx_beacon_off,
2477 .beacon_blink = qla83xx_beacon_blink,
2478 .read_optrom = qla25xx_read_optrom_data,
2479 .write_optrom = qla24xx_write_optrom_data,
2480 .get_flash_version = qla24xx_get_flash_version,
2481 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2482 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
f73cb695
CD		 2483 .abort_isp = qla2x00_abort_isp,
2484 .iospace_config = qla83xx_iospace_config,
2485 .initialize_adapter = qla2x00_initialize_adapter,
2486};
2487
ea5b6382 2488static inline void
e315cd28 2489qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382
AV		 2490{
2491 ha->device_type = DT_EXTENDED_IDS;
2492 switch (ha->pdev->device) {
2493 case PCI_DEVICE_ID_QLOGIC_ISP2100:
9e052e2d 2494 ha->isp_type |= DT_ISP2100;
ea5b6382 2495 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2496 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2497 break;
2498 case PCI_DEVICE_ID_QLOGIC_ISP2200:
9e052e2d 2499 ha->isp_type |= DT_ISP2200;
ea5b6382 2500 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2501 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2502 break;
2503 case PCI_DEVICE_ID_QLOGIC_ISP2300:
9e052e2d 2504 ha->isp_type |= DT_ISP2300;
4a59f71d 2505 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2506 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2507 break;
2508 case PCI_DEVICE_ID_QLOGIC_ISP2312:
9e052e2d 2509 ha->isp_type |= DT_ISP2312;
4a59f71d 2510 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2511 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2512 break;
2513 case PCI_DEVICE_ID_QLOGIC_ISP2322:
9e052e2d 2514 ha->isp_type |= DT_ISP2322;
4a59f71d 2515 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382
AV		 2516 if (ha->pdev->subsystem_vendor == 0x1028 &&
2517 ha->pdev->subsystem_device == 0x0170)
2518 ha->device_type |= DT_OEM_001;
441d1072 2519 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2520 break;
2521 case PCI_DEVICE_ID_QLOGIC_ISP6312:
9e052e2d 2522 ha->isp_type |= DT_ISP6312;
441d1072 2523 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2524 break;
2525 case PCI_DEVICE_ID_QLOGIC_ISP6322:
9e052e2d 2526 ha->isp_type |= DT_ISP6322;
441d1072 2527 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2528 break;
2529 case PCI_DEVICE_ID_QLOGIC_ISP2422:
9e052e2d 2530 ha->isp_type |= DT_ISP2422;
4a59f71d 2531 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2532 ha->device_type |= DT_FWI2;
c76f2c01 2533 ha->device_type |= DT_IIDMA;
441d1072 2534 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382
AV		 2535 break;
2536 case PCI_DEVICE_ID_QLOGIC_ISP2432:
9e052e2d 2537 ha->isp_type |= DT_ISP2432;
4a59f71d 2538 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2539 ha->device_type |= DT_FWI2;
c76f2c01 2540 ha->device_type |= DT_IIDMA;
441d1072 2541 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2542 break;
4d4df193 2543 case PCI_DEVICE_ID_QLOGIC_ISP8432:
9e052e2d 2544 ha->isp_type |= DT_ISP8432;
4d4df193
HK		 2545 ha->device_type |= DT_ZIO_SUPPORTED;
2546 ha->device_type |= DT_FWI2;
2547 ha->device_type |= DT_IIDMA;
2548 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2549 break;
044cc6c8 2550 case PCI_DEVICE_ID_QLOGIC_ISP5422:
9e052e2d 2551 ha->isp_type |= DT_ISP5422;
e428924c 2552 ha->device_type |= DT_FWI2;
441d1072 2553 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2554 break;
044cc6c8 2555 case PCI_DEVICE_ID_QLOGIC_ISP5432:
9e052e2d 2556 ha->isp_type |= DT_ISP5432;
e428924c 2557 ha->device_type |= DT_FWI2;
441d1072 2558 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2559 break;
c3a2f0df 2560 case PCI_DEVICE_ID_QLOGIC_ISP2532:
9e052e2d 2561 ha->isp_type |= DT_ISP2532;
c3a2f0df
AV		 2562 ha->device_type |= DT_ZIO_SUPPORTED;
2563 ha->device_type |= DT_FWI2;
2564 ha->device_type |= DT_IIDMA;
441d1072 2565 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2566 break;
3a03eb79 2567 case PCI_DEVICE_ID_QLOGIC_ISP8001:
9e052e2d 2568 ha->isp_type |= DT_ISP8001;
3a03eb79
AV		 2569 ha->device_type |= DT_ZIO_SUPPORTED;
2570 ha->device_type |= DT_FWI2;
2571 ha->device_type |= DT_IIDMA;
2572 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2573 break;
a9083016 2574 case PCI_DEVICE_ID_QLOGIC_ISP8021:
9e052e2d 2575 ha->isp_type |= DT_ISP8021;
a9083016
GM		 2576 ha->device_type |= DT_ZIO_SUPPORTED;
2577 ha->device_type |= DT_FWI2;
2578 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2579 /* Initialize 82XX ISP flags */
2580 qla82xx_init_flags(ha);
2581 break;
7ec0effd 2582 case PCI_DEVICE_ID_QLOGIC_ISP8044:
9e052e2d 2583 ha->isp_type |= DT_ISP8044;
7ec0effd
AD		 2584 ha->device_type |= DT_ZIO_SUPPORTED;
2585 ha->device_type |= DT_FWI2;
2586 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2587 /* Initialize 82XX ISP flags */
2588 qla82xx_init_flags(ha);
2589 break;
6246b8a1 2590 case PCI_DEVICE_ID_QLOGIC_ISP2031:
9e052e2d 2591 ha->isp_type |= DT_ISP2031;
6246b8a1
GM		 2592 ha->device_type |= DT_ZIO_SUPPORTED;
2593 ha->device_type |= DT_FWI2;
2594 ha->device_type |= DT_IIDMA;
2595 ha->device_type |= DT_T10_PI;
2596 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2597 break;
2598 case PCI_DEVICE_ID_QLOGIC_ISP8031:
9e052e2d 2599 ha->isp_type |= DT_ISP8031;
6246b8a1
GM		 2600 ha->device_type |= DT_ZIO_SUPPORTED;
2601 ha->device_type |= DT_FWI2;
2602 ha->device_type |= DT_IIDMA;
2603 ha->device_type |= DT_T10_PI;
2604 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2605 break;
8ae6d9c7 2606 case PCI_DEVICE_ID_QLOGIC_ISPF001:
9e052e2d 2607 ha->isp_type |= DT_ISPFX00;
8ae6d9c7 2608 break;
f73cb695 2609 case PCI_DEVICE_ID_QLOGIC_ISP2071:
9e052e2d 2610 ha->isp_type |= DT_ISP2071;
f73cb695
CD		 2611 ha->device_type |= DT_ZIO_SUPPORTED;
2612 ha->device_type |= DT_FWI2;
2613 ha->device_type |= DT_IIDMA;
8ce3f570 2614 ha->device_type |= DT_T10_PI;
f73cb695
CD		 2615 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2616 break;
2c5bbbb2 2617 case PCI_DEVICE_ID_QLOGIC_ISP2271:
9e052e2d 2618 ha->isp_type |= DT_ISP2271;
2c5bbbb2
JC		 2619 ha->device_type |= DT_ZIO_SUPPORTED;
2620 ha->device_type |= DT_FWI2;
2621 ha->device_type |= DT_IIDMA;
8ce3f570 2622 ha->device_type |= DT_T10_PI;
2c5bbbb2
JC		 2623 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2624 break;
2b48992f 2625 case PCI_DEVICE_ID_QLOGIC_ISP2261:
9e052e2d 2626 ha->isp_type |= DT_ISP2261;
2b48992f
SC		 2627 ha->device_type |= DT_ZIO_SUPPORTED;
2628 ha->device_type |= DT_FWI2;
2629 ha->device_type |= DT_IIDMA;
8ce3f570 2630 ha->device_type |= DT_T10_PI;
2b48992f
SC		 2631 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2632 break;
ea5b6382 2633 }
e5b68a61 2634
a9083016 2635 if (IS_QLA82XX(ha))
43a9c38b 2636 ha->port_no = ha->portnum & 1;
f73cb695 2637 else {
a9083016
GM		 2638 /* Get adapter physical port no from interrupt pin register. */
2639 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
f73cb695
CD		 2640 if (IS_QLA27XX(ha))
2641 ha->port_no--;
2642 else
2643 ha->port_no = !(ha->port_no & 1);
2644 }
a9083016 2645
7c3df132 2646 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2647 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
f73cb695 2648 ha->device_type, ha->port_no, ha->fw_srisc_address);
ea5b6382
AV		 2649}
2650
1e99e33a
AV		 2651static void
2652qla2xxx_scan_start(struct Scsi_Host *shost)
2653{
e315cd28 2654 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2655
cbc8eb67
AV		 2656 if (vha->hw->flags.running_gold_fw)
2657 return;
2658
e315cd28
AC		 2659 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2660 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2661 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2662 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2663}
2664
2665static int
2666qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2667{
e315cd28 2668 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2669
a5dd506e
BK		 2670 if (test_bit(UNLOADING, &vha->dpc_flags))
2671 return 1;
e315cd28 2672 if (!vha->host)
1e99e33a 2673 return 1;
e315cd28 2674 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2675 return 1;
2676
e315cd28 2677 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2678}
2679
ec7193e2
QT		 2680static void qla2x00_iocb_work_fn(struct work_struct *work)
2681{
2682 struct scsi_qla_host *vha = container_of(work,
2683 struct scsi_qla_host, iocb_work);
2684 int cnt = 0;
2685
2686 while (!list_empty(&vha->work_list)) {
2687 qla2x00_do_work(vha);
2688 cnt++;
2689 if (cnt > 10)
2690 break;
2691 }
2692}
2693
1da177e4
LT		 2694/*
2695 * PCI driver interface
2696 */
6f039790 2697static int
7ee61397 2698qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2699{
a1541d5a 2700 int ret = -ENODEV;
1da177e4 2701 struct Scsi_Host *host;
e315cd28
AC		 2702 scsi_qla_host_t *base_vha = NULL;
2703 struct qla_hw_data *ha;
29856e28 2704 char pci_info[30];
7d613ac6 2705 char fw_str[30], wq_name[30];
5433383e 2706 struct scsi_host_template *sht;
642ef983 2707 int bars, mem_only = 0;
e315cd28 2708 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2709 struct req_que *req = NULL;
2710 struct rsp_que *rsp = NULL;
5601236b 2711 int i;
d7459527 2712
285d0321 2713 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2714 sht = &qla2xxx_driver_template;
5433383e 2715 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2716 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2717 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2718 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2719 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2720 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2721 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2722 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2723 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
8ae6d9c7 2724 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
7ec0effd 2725 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
f73cb695 2726 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2c5bbbb2 2727 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2b48992f
SC		 2728 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
2729 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) {
285d0321 2730 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2731 mem_only = 1;
7c3df132
SK		 2732 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2733 "Mem only adapter.\n");
285d0321 2734 }
7c3df132
SK		 2735 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2736 "Bars=%d.\n", bars);
285d0321 2737
09483916
BH		 2738 if (mem_only) {
2739 if (pci_enable_device_mem(pdev))
ddff7ed4 2740 return ret;
09483916
BH		 2741 } else {
2742 if (pci_enable_device(pdev))
ddff7ed4 2743 return ret;
09483916 2744 }
285d0321 2745
0927678f
JB		 2746 /* This may fail but that's ok */
2747 pci_enable_pcie_error_reporting(pdev);
285d0321 2748
e315cd28
AC		 2749 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2750 if (!ha) {
7c3df132
SK		 2751 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2752 "Unable to allocate memory for ha.\n");
ddff7ed4 2753 goto disable_device;
1da177e4 2754 }
7c3df132
SK		 2755 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2756 "Memory allocated for ha=%p.\n", ha);
e315cd28 2757 ha->pdev = pdev;
33e79977
QT		 2758 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2759 spin_lock_init(&ha->tgt.q_full_lock);
7560151b 2760 spin_lock_init(&ha->tgt.sess_lock);
2f424b9b
QT		 2761 spin_lock_init(&ha->tgt.atio_lock);
2762
deeae7a6 2763 atomic_set(&ha->nvme_active_aen_cnt, 0);
1da177e4
LT		 2764
2765 /* Clear our data area */
285d0321 2766 ha->bars = bars;
09483916 2767 ha->mem_only = mem_only;
df4bf0bb 2768 spin_lock_init(&ha->hardware_lock);
339aa70e 2769 spin_lock_init(&ha->vport_slock);
a9b6f722 2770 mutex_init(&ha->selflogin_lock);
7a8ab9c8 2771 mutex_init(&ha->optrom_mutex);
1da177e4 2772
ea5b6382
AV		 2773 /* Set ISP-type information. */
2774 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2775
2776 /* Set EEH reset type to fundamental if required by hba */
95676112 2777 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
f73cb695 2778 IS_QLA83XX(ha) || IS_QLA27XX(ha))
ca79cf66 2779 pdev->needs_freset = 1;
ca79cf66 2780
cba1e47f
CD		 2781 ha->prev_topology = 0;
2782 ha->init_cb_size = sizeof(init_cb_t);
2783 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2784 ha->optrom_size = OPTROM_SIZE_2300;
2785
abbd8870 2786 /* Assign ISP specific operations. */
1da177e4 2787 if (IS_QLA2100(ha)) {
642ef983 2788 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2789 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2790 req_length = REQUEST_ENTRY_CNT_2100;
2791 rsp_length = RESPONSE_ENTRY_CNT_2100;
2792 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2793 ha->gid_list_info_size = 4;
3a03eb79
AV		 2794 ha->flash_conf_off = ~0;
2795 ha->flash_data_off = ~0;
2796 ha->nvram_conf_off = ~0;
2797 ha->nvram_data_off = ~0;
fd34f556 2798 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2799 } else if (IS_QLA2200(ha)) {
642ef983 2800 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2801 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2802 req_length = REQUEST_ENTRY_CNT_2200;
2803 rsp_length = RESPONSE_ENTRY_CNT_2100;
2804 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2805 ha->gid_list_info_size = 4;
3a03eb79
AV		 2806 ha->flash_conf_off = ~0;
2807 ha->flash_data_off = ~0;
2808 ha->nvram_conf_off = ~0;
2809 ha->nvram_data_off = ~0;
fd34f556 2810 ha->isp_ops = &qla2100_isp_ops;
fca29703 2811 } else if (IS_QLA23XX(ha)) {
642ef983 2812 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2813 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2814 req_length = REQUEST_ENTRY_CNT_2200;
2815 rsp_length = RESPONSE_ENTRY_CNT_2300;
2816 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2817 ha->gid_list_info_size = 6;
854165f4
AV		 2818 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2819 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2820 ha->flash_conf_off = ~0;
2821 ha->flash_data_off = ~0;
2822 ha->nvram_conf_off = ~0;
2823 ha->nvram_data_off = ~0;
fd34f556 2824 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2825 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2826 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2827 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2828 req_length = REQUEST_ENTRY_CNT_24XX;
2829 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2830 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2831 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2832 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2833 ha->gid_list_info_size = 8;
854165f4 2834 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2835 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2836 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2837 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2838 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2839 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2840 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2841 } else if (IS_QLA25XX(ha)) {
642ef983 2842 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2843 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2844 req_length = REQUEST_ENTRY_CNT_24XX;
2845 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2846 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2847 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2848 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2849 ha->gid_list_info_size = 8;
2850 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2851 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2852 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2853 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2854 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2855 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2856 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2857 } else if (IS_QLA81XX(ha)) {
642ef983 2858 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2859 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2860 req_length = REQUEST_ENTRY_CNT_24XX;
2861 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 2862 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 2863 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2864 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2865 ha->gid_list_info_size = 8;
2866 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2867 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2868 ha->isp_ops = &qla81xx_isp_ops;
2869 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2870 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2871 ha->nvram_conf_off = ~0;
2872 ha->nvram_data_off = ~0;
a9083016 2873 } else if (IS_QLA82XX(ha)) {
642ef983 2874 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2875 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2876 req_length = REQUEST_ENTRY_CNT_82XX;
2877 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2878 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2879 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2880 ha->gid_list_info_size = 8;
2881 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2882 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2883 ha->isp_ops = &qla82xx_isp_ops;
2884 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2885 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2886 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2887 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
7ec0effd
AD		 2888 } else if (IS_QLA8044(ha)) {
2889 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2890 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2891 req_length = REQUEST_ENTRY_CNT_82XX;
2892 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2893 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2894 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2895 ha->gid_list_info_size = 8;
2896 ha->optrom_size = OPTROM_SIZE_83XX;
2897 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2898 ha->isp_ops = &qla8044_isp_ops;
2899 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2900 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2901 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2902 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 2903 } else if (IS_QLA83XX(ha)) {
7d613ac6 2904 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 2905 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1 2906 ha->mbx_count = MAILBOX_REGISTER_COUNT;
f2ea653f 2907 req_length = REQUEST_ENTRY_CNT_83XX;
e7b42e33 2908 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b8aa4bdf 2909 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 2910 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2911 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2912 ha->gid_list_info_size = 8;
2913 ha->optrom_size = OPTROM_SIZE_83XX;
2914 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2915 ha->isp_ops = &qla83xx_isp_ops;
2916 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2917 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2918 ha->nvram_conf_off = ~0;
2919 ha->nvram_data_off = ~0;
8ae6d9c7
GM		 2920 } else if (IS_QLAFX00(ha)) {
2921 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2922 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2923 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2924 req_length = REQUEST_ENTRY_CNT_FX00;
2925 rsp_length = RESPONSE_ENTRY_CNT_FX00;
8ae6d9c7
GM		 2926 ha->isp_ops = &qlafx00_isp_ops;
2927 ha->port_down_retry_count = 30; /* default value */
2928 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2929 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
71e56003 2930 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
8ae6d9c7 2931 ha->mr.fw_hbt_en = 1;
e8f5e95d
AB		 2932 ha->mr.host_info_resend = false;
2933 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
f73cb695
CD		 2934 } else if (IS_QLA27XX(ha)) {
2935 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2936 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2937 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e7b42e33
QT		 2938 req_length = REQUEST_ENTRY_CNT_83XX;
2939 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b20f02e1 2940 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
f73cb695
CD		 2941 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2942 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2943 ha->gid_list_info_size = 8;
2944 ha->optrom_size = OPTROM_SIZE_83XX;
2945 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2946 ha->isp_ops = &qla27xx_isp_ops;
2947 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2948 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2949 ha->nvram_conf_off = ~0;
2950 ha->nvram_data_off = ~0;
1da177e4 2951 }
6246b8a1 2952
7c3df132
SK		 2953 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2954 "mbx_count=%d, req_length=%d, "
2955 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 2956 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2957 "max_fibre_devices=%d.\n",
7c3df132
SK		 2958 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2959 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 2960 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 2961 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2962 "isp_ops=%p, flash_conf_off=%d, "
2963 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2964 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2965 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 2966
2967 /* Configure PCI I/O space */
2968 ret = ha->isp_ops->iospace_config(ha);
2969 if (ret)
0a63ad12 2970 goto iospace_config_failed;
706f457d
GM		 2971
2972 ql_log_pci(ql_log_info, pdev, 0x001d,
2973 "Found an ISP%04X irq %d iobase 0x%p.\n",
2974 pdev->device, pdev->irq, ha->iobase);
6c2f527c 2975 mutex_init(&ha->vport_lock);
d7459527 2976 mutex_init(&ha->mq_lock);
0b05a1f0
MB		 2977 init_completion(&ha->mbx_cmd_comp);
2978 complete(&ha->mbx_cmd_comp);
2979 init_completion(&ha->mbx_intr_comp);
23f2ebd1 2980 init_completion(&ha->dcbx_comp);
f356bef1 2981 init_completion(&ha->lb_portup_comp);
1da177e4 2982
2c3dfe3f 2983 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 2984
53303c42 2985 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 2986 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2987 "64 Bit addressing is %s.\n",
2988 ha->flags.enable_64bit_addressing ? "enable" :
2989 "disable");
73208dfd 2990 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
b2a72ec3 2991 if (ret) {
7c3df132
SK		 2992 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2993 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 2994
e315cd28
AC		 2995 goto probe_hw_failed;
2996 }
2997
73208dfd 2998 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 2999 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 3000 req->max_q_depth = ql2xmaxqdepth;
3001
e315cd28
AC		 3002
3003 base_vha = qla2x00_create_host(sht, ha);
3004 if (!base_vha) {
a1541d5a 3005 ret = -ENOMEM;
6e9f21f3 3006 qla2x00_mem_free(ha);
2afa19a9
AC		 3007 qla2x00_free_req_que(ha, req);
3008 qla2x00_free_rsp_que(ha, rsp);
e315cd28 3009 goto probe_hw_failed;
1da177e4
LT		 3010 }
3011
e315cd28 3012 pci_set_drvdata(pdev, base_vha);
6b383979 3013 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
e315cd28 3014
e315cd28 3015 host = base_vha->host;
2afa19a9 3016 base_vha->req = req;
73208dfd 3017 if (IS_QLA2XXX_MIDTYPE(ha))
e315cd28 3018 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
73208dfd 3019 else
e315cd28
AC		 3020 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
3021 base_vha->vp_idx;
58548cb5 3022
8ae6d9c7
GM		 3023 /* Setup fcport template structure. */
3024 ha->mr.fcport.vha = base_vha;
3025 ha->mr.fcport.port_type = FCT_UNKNOWN;
3026 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
3027 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
3028 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
3029 ha->mr.fcport.scan_state = 1;
3030
58548cb5
GM		 3031 /* Set the SG table size based on ISP type */
3032 if (!IS_FWI2_CAPABLE(ha)) {
3033 if (IS_QLA2100(ha))
3034 host->sg_tablesize = 32;
3035 } else {
3036 if (!IS_QLA82XX(ha))
3037 host->sg_tablesize = QLA_SG_ALL;
3038 }
642ef983 3039 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 3040 host->cmd_per_lun = 3;
3041 host->unique_id = host->host_no;
e02587d7 3042 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 3043 host->max_cmd_len = 32;
3044 else
3045 host->max_cmd_len = MAX_CMDSZ;
e315cd28 3046 host->max_channel = MAX_BUSES - 1;
755f516b
HR		 3047 /* Older HBAs support only 16-bit LUNs */
3048 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
3049 ql2xmaxlun > 0xffff)
3050 host->max_lun = 0xffff;
3051 else
3052 host->max_lun = ql2xmaxlun;
e315cd28 3053 host->transportt = qla2xxx_transport_template;
9a069e19 3054 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 3055
7c3df132
SK		 3056 ql_dbg(ql_dbg_init, base_vha, 0x0033,
3057 "max_id=%d this_id=%d "
3058 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
1abf635d 3059 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 3060 host->this_id, host->cmd_per_lun, host->unique_id,
3061 host->max_cmd_len, host->max_channel, host->max_lun,
3062 host->transportt, sht->vendor_id);
3063
d7459527
MH		 3064 /* Set up the irqs */
3065 ret = qla2x00_request_irqs(ha, rsp);
3066 if (ret)
3067 goto probe_init_failed;
3068
9a347ff4
CD		 3069 /* Alloc arrays of request and response ring ptrs */
3070 if (!qla2x00_alloc_queues(ha, req, rsp)) {
3071 ql_log(ql_log_fatal, base_vha, 0x003d,
3072 "Failed to allocate memory for queue pointers..."
3073 "aborting.\n");
3074 goto probe_init_failed;
3075 }
3076
5601236b
MH		 3077 if (ha->mqenable && shost_use_blk_mq(host)) {
3078 /* number of hardware queues supported by blk/scsi-mq*/
3079 host->nr_hw_queues = ha->max_qpairs;
3080
3081 ql_dbg(ql_dbg_init, base_vha, 0x0192,
3082 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues);
3083 } else
3084 ql_dbg(ql_dbg_init, base_vha, 0x0193,
3085 "blk/scsi-mq disabled.\n");
3086
2d70c103 3087 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 3088
90a86fc0
JC		 3089 pci_save_state(pdev);
3090
9a347ff4 3091 /* Assign back pointers */
2afa19a9
AC		 3092 rsp->req = req;
3093 req->rsp = rsp;
9a347ff4 3094
8ae6d9c7
GM		 3095 if (IS_QLAFX00(ha)) {
3096 ha->rsp_q_map[0] = rsp;
3097 ha->req_q_map[0] = req;
3098 set_bit(0, ha->req_qid_map);
3099 set_bit(0, ha->rsp_qid_map);
3100 }
3101
08029990
AV		 3102 /* FWI2-capable only. */
3103 req->req_q_in = &ha->iobase->isp24.req_q_in;
3104 req->req_q_out = &ha->iobase->isp24.req_q_out;
3105 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
3106 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
f73cb695 3107 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
08029990
AV		 3108 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
3109 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
3110 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
3111 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 3112 }
3113
8ae6d9c7
GM		 3114 if (IS_QLAFX00(ha)) {
3115 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
3116 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
3117 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
3118 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
3119 }
3120
7ec0effd 3121 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3122 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
3123 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
3124 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
3125 }
3126
7c3df132
SK		 3127 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
3128 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3129 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3130 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
3131 "req->req_q_in=%p req->req_q_out=%p "
3132 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3133 req->req_q_in, req->req_q_out,
3134 rsp->rsp_q_in, rsp->rsp_q_out);
3135 ql_dbg(ql_dbg_init, base_vha, 0x003e,
3136 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3137 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3138 ql_dbg(ql_dbg_init, base_vha, 0x003f,
3139 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3140 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 3141
8ae6d9c7 3142 if (ha->isp_ops->initialize_adapter(base_vha)) {
7c3df132
SK		 3143 ql_log(ql_log_fatal, base_vha, 0x00d6,
3144 "Failed to initialize adapter - Adapter flags %x.\n",
3145 base_vha->device_flags);
1da177e4 3146
a9083016
GM		 3147 if (IS_QLA82XX(ha)) {
3148 qla82xx_idc_lock(ha);
3149 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 3150 QLA8XXX_DEV_FAILED);
a9083016 3151 qla82xx_idc_unlock(ha);
7c3df132
SK		 3152 ql_log(ql_log_fatal, base_vha, 0x00d7,
3153 "HW State: FAILED.\n");
7ec0effd
AD		 3154 } else if (IS_QLA8044(ha)) {
3155 qla8044_idc_lock(ha);
3156 qla8044_wr_direct(base_vha,
3157 QLA8044_CRB_DEV_STATE_INDEX,
3158 QLA8XXX_DEV_FAILED);
3159 qla8044_idc_unlock(ha);
3160 ql_log(ql_log_fatal, base_vha, 0x0150,
3161 "HW State: FAILED.\n");
a9083016
GM		 3162 }
3163
a1541d5a 3164 ret = -ENODEV;
1da177e4
LT		 3165 goto probe_failed;
3166 }
3167
3b1bef64
CD		 3168 if (IS_QLAFX00(ha))
3169 host->can_queue = QLAFX00_MAX_CANQUEUE;
3170 else
3171 host->can_queue = req->num_outstanding_cmds - 10;
3172
3173 ql_dbg(ql_dbg_init, base_vha, 0x0032,
3174 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
3175 host->can_queue, base_vha->req,
3176 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
3177
e326d22a
QT		 3178 if (ha->mqenable) {
3179 bool mq = false;
3180 bool startit = false;
18ada18e 3181 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 0);
e326d22a
QT		 3182
3183 if (QLA_TGT_MODE_ENABLED()) {
3184 mq = true;
3185 startit = false;
3186 }
3187
3188 if ((ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED) &&
3189 shost_use_blk_mq(host)) {
3190 mq = true;
3191 startit = true;
3192 }
3193
3194 if (mq) {
3195 /* Create start of day qpairs for Block MQ */
5601236b 3196 for (i = 0; i < ha->max_qpairs; i++)
e326d22a 3197 qla2xxx_create_qpair(base_vha, 5, 0, startit);
5601236b
MH		 3198 }
3199 }
68ca949c 3200
cbc8eb67
AV		 3201 if (ha->flags.running_gold_fw)
3202 goto skip_dpc;
3203
1da177e4
LT		 3204 /*
3205 * Startup the kernel thread for this host adapter
3206 */
39a11240 3207 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 3208 "%s_dpc", base_vha->host_str);
39a11240 3209 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 3210 ql_log(ql_log_fatal, base_vha, 0x00ed,
3211 "Failed to start DPC thread.\n");
39a11240 3212 ret = PTR_ERR(ha->dpc_thread);
1da177e4
LT		 3213 goto probe_failed;
3214 }
7c3df132
SK		 3215 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
3216 "DPC thread started successfully.\n");
1da177e4 3217
2d70c103
NB		 3218 /*
3219 * If we're not coming up in initiator mode, we might sit for
3220 * a while without waking up the dpc thread, which leads to a
3221 * stuck process warning. So just kick the dpc once here and
3222 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
3223 */
3224 qla2xxx_wake_dpc(base_vha);
3225
ec7193e2 3226 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn);
f3ddac19
CD		 3227 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
3228
81178772
SK		 3229 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
3230 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
3231 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
3232 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
3233
3234 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
3235 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
3236 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
3237 INIT_WORK(&ha->idc_state_handler,
3238 qla83xx_idc_state_handler_work);
3239 INIT_WORK(&ha->nic_core_unrecoverable,
3240 qla83xx_nic_core_unrecoverable_work);
3241 }
3242
cbc8eb67 3243skip_dpc:
e315cd28
AC		 3244 list_add_tail(&base_vha->list, &ha->vp_list);
3245 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 3246
3247 /* Initialized the timer */
e315cd28 3248 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
7c3df132
SK		 3249 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
3250 "Started qla2x00_timer with "
3251 "interval=%d.\n", WATCH_INTERVAL);
3252 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
3253 "Detected hba at address=%p.\n",
3254 ha);
d19044c3 3255
e02587d7 3256 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 3257 if (ha->fw_attributes & BIT_4) {
9e522cd8 3258 int prot = 0, guard;
bad75002 3259 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 3260 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
3261 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 3262 if (ql2xenabledif == 1)
3263 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 3264 scsi_host_set_prot(host,
8cb2049c 3265 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 3266 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 3267 | SHOST_DIF_TYPE3_PROTECTION
3268 | SHOST_DIX_TYPE1_PROTECTION
0c470874 3269 | SHOST_DIX_TYPE2_PROTECTION
bad75002 3270 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 3271
3272 guard = SHOST_DIX_GUARD_CRC;
3273
3274 if (IS_PI_IPGUARD_CAPABLE(ha) &&
3275 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
3276 guard |= SHOST_DIX_GUARD_IP;
3277
3278 scsi_host_set_guard(host, guard);
bad75002
AE		 3279 } else
3280 base_vha->flags.difdix_supported = 0;
3281 }
3282
a9083016
GM		 3283 ha->isp_ops->enable_intrs(ha);
3284
1fe19ee4
AB		 3285 if (IS_QLAFX00(ha)) {
3286 ret = qlafx00_fx_disc(base_vha,
3287 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
3288 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
3289 QLA_SG_ALL : 128;
3290 }
3291
a1541d5a
AV		 3292 ret = scsi_add_host(host, &pdev->dev);
3293 if (ret)
3294 goto probe_failed;
3295
1486400f
MR		 3296 base_vha->flags.init_done = 1;
3297 base_vha->flags.online = 1;
edaa5c74 3298 ha->prev_minidump_failed = 0;
1486400f 3299
7c3df132
SK		 3300 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
3301 "Init done and hba is online.\n");
3302
726b8548
QT		 3303 if (qla_ini_mode_enabled(base_vha) ||
3304 qla_dual_mode_enabled(base_vha))
2d70c103
NB		 3305 scsi_scan_host(host);
3306 else
3307 ql_dbg(ql_dbg_init, base_vha, 0x0122,
3308 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 3309
e315cd28 3310 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 3311
8ae6d9c7 3312 if (IS_QLAFX00(ha)) {
8ae6d9c7
GM		 3313 ret = qlafx00_fx_disc(base_vha,
3314 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
3315
3316 /* Register system information */
3317 ret = qlafx00_fx_disc(base_vha,
3318 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
3319 }
3320
e315cd28 3321 qla2x00_init_host_attr(base_vha);
a1541d5a 3322
e315cd28 3323 qla2x00_dfs_setup(base_vha);
df613b96 3324
03eb912a
AB		 3325 ql_log(ql_log_info, base_vha, 0x00fb,
3326 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
7c3df132
SK		 3327 ql_log(ql_log_info, base_vha, 0x00fc,
3328 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
3329 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
3330 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
3331 base_vha->host_no,
df57caba 3332 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
1da177e4 3333
2d70c103
NB		 3334 qlt_add_target(ha, base_vha);
3335
6b383979 3336 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
a29b3dd7
JC		 3337
3338 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3339 return -ENODEV;
3340
e4e3a2ce
QT		 3341 if (ha->flags.detected_lr_sfp) {
3342 ql_log(ql_log_info, base_vha, 0xffff,
3343 "Reset chip to pick up LR SFP setting\n");
3344 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
3345 qla2xxx_wake_dpc(base_vha);
3346 }
3347
1da177e4
LT		 3348 return 0;
3349
6e9f21f3 3350probe_init_failed:
2afa19a9 3351 qla2x00_free_req_que(ha, req);
9a347ff4
CD		 3352 ha->req_q_map[0] = NULL;
3353 clear_bit(0, ha->req_qid_map);
2afa19a9 3354 qla2x00_free_rsp_que(ha, rsp);
9a347ff4
CD		 3355 ha->rsp_q_map[0] = NULL;
3356 clear_bit(0, ha->rsp_qid_map);
2afa19a9 3357 ha->max_req_queues = ha->max_rsp_queues = 0;
6e9f21f3 3358
1da177e4 3359probe_failed:
b9978769
AV		 3360 if (base_vha->timer_active)
3361 qla2x00_stop_timer(base_vha);
3362 base_vha->flags.online = 0;
3363 if (ha->dpc_thread) {
3364 struct task_struct *t = ha->dpc_thread;
3365
3366 ha->dpc_thread = NULL;
3367 kthread_stop(t);
3368 }
3369
e315cd28 3370 qla2x00_free_device(base_vha);
1da177e4 3371
e315cd28 3372 scsi_host_put(base_vha->host);
1da177e4 3373
e315cd28 3374probe_hw_failed:
1a2fbf18
JL		 3375 qla2x00_clear_drv_active(ha);
3376
0a63ad12 3377iospace_config_failed:
7ec0effd 3378 if (IS_P3P_TYPE(ha)) {
0a63ad12 3379 if (!ha->nx_pcibase)
f73cb695 3380 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3381 if (!ql2xdbwr)
f73cb695 3382 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3383 } else {
3384 if (ha->iobase)
3385 iounmap(ha->iobase);
8ae6d9c7
GM		 3386 if (ha->cregbase)
3387 iounmap(ha->cregbase);
a9083016 3388 }
e315cd28
AC		 3389 pci_release_selected_regions(ha->pdev, ha->bars);
3390 kfree(ha);
1da177e4 3391
ddff7ed4 3392disable_device:
e315cd28 3393 pci_disable_device(pdev);
a1541d5a 3394 return ret;
1da177e4 3395}
1da177e4 3396
e30d1756
MI		 3397static void
3398qla2x00_shutdown(struct pci_dev *pdev)
3399{
3400 scsi_qla_host_t *vha;
3401 struct qla_hw_data *ha;
3402
3403 vha = pci_get_drvdata(pdev);
3404 ha = vha->hw;
3405
efdb5760
SC		 3406 ql_log(ql_log_info, vha, 0xfffa,
3407 "Adapter shutdown\n");
3408
3409 /*
3410 * Prevent future board_disable and wait
3411 * until any pending board_disable has completed.
3412 */
3413 set_bit(PFLG_DRIVER_REMOVING, &vha->pci_flags);
3414 cancel_work_sync(&ha->board_disable);
3415
3416 if (!atomic_read(&pdev->enable_cnt))
3417 return;
3418
42479343
AB		 3419 /* Notify ISPFX00 firmware */
3420 if (IS_QLAFX00(ha))
3421 qlafx00_driver_shutdown(vha, 20);
3422
e30d1756
MI		 3423 /* Turn-off FCE trace */
3424 if (ha->flags.fce_enabled) {
3425 qla2x00_disable_fce_trace(vha, NULL, NULL);
3426 ha->flags.fce_enabled = 0;
3427 }
3428
3429 /* Turn-off EFT trace */
3430 if (ha->eft)
3431 qla2x00_disable_eft_trace(vha);
3432
3433 /* Stop currently executing firmware. */
3434 qla2x00_try_to_stop_firmware(vha);
3435
3436 /* Turn adapter off line */
3437 vha->flags.online = 0;
3438
3439 /* turn-off interrupts on the card */
3440 if (ha->interrupts_on) {
3441 vha->flags.init_done = 0;
3442 ha->isp_ops->disable_intrs(ha);
3443 }
3444
3445 qla2x00_free_irqs(vha);
3446
3447 qla2x00_free_fw_dump(ha);
61d41f61 3448
61d41f61 3449 pci_disable_device(pdev);
efdb5760
SC		 3450 ql_log(ql_log_info, vha, 0xfffe,
3451 "Adapter shutdown successfully.\n");
e30d1756
MI		 3452}
3453
fe1b806f 3454/* Deletes all the virtual ports for a given ha */
4c993f76 3455static void
fe1b806f 3456qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
1da177e4 3457{
fe1b806f 3458 scsi_qla_host_t *vha;
feafb7b1 3459 unsigned long flags;
e315cd28 3460
43ebf16d
AE		 3461 mutex_lock(&ha->vport_lock);
3462 while (ha->cur_vport_count) {
43ebf16d 3463 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 3464
43ebf16d
AE		 3465 BUG_ON(base_vha->list.next == &ha->vp_list);
3466 /* This assumes first entry in ha->vp_list is always base vha */
3467 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
52c82823 3468 scsi_host_get(vha->host);
feafb7b1 3469
43ebf16d
AE		 3470 spin_unlock_irqrestore(&ha->vport_slock, flags);
3471 mutex_unlock(&ha->vport_lock);
3472
3473 fc_vport_terminate(vha->fc_vport);
3474 scsi_host_put(vha->host);
feafb7b1 3475
43ebf16d 3476 mutex_lock(&ha->vport_lock);
e315cd28 3477 }
43ebf16d 3478 mutex_unlock(&ha->vport_lock);
fe1b806f 3479}
1da177e4 3480
fe1b806f
CD		 3481/* Stops all deferred work threads */
3482static void
3483qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3484{
7d613ac6
SV		 3485 /* Cancel all work and destroy DPC workqueues */
3486 if (ha->dpc_lp_wq) {
3487 cancel_work_sync(&ha->idc_aen);
3488 destroy_workqueue(ha->dpc_lp_wq);
3489 ha->dpc_lp_wq = NULL;
3490 }
3491
3492 if (ha->dpc_hp_wq) {
3493 cancel_work_sync(&ha->nic_core_reset);
3494 cancel_work_sync(&ha->idc_state_handler);
3495 cancel_work_sync(&ha->nic_core_unrecoverable);
3496 destroy_workqueue(ha->dpc_hp_wq);
3497 ha->dpc_hp_wq = NULL;
3498 }
3499
b9978769
AV		 3500 /* Kill the kernel thread for this host */
3501 if (ha->dpc_thread) {
3502 struct task_struct *t = ha->dpc_thread;
3503
3504 /*
3505 * qla2xxx_wake_dpc checks for ->dpc_thread
3506 * so we need to zero it out.
3507 */
3508 ha->dpc_thread = NULL;
3509 kthread_stop(t);
3510 }
fe1b806f 3511}
1da177e4 3512
fe1b806f
CD		 3513static void
3514qla2x00_unmap_iobases(struct qla_hw_data *ha)
3515{
a9083016 3516 if (IS_QLA82XX(ha)) {
b963752f 3517
f73cb695 3518 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3519 if (!ql2xdbwr)
f73cb695 3520 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3521 } else {
3522 if (ha->iobase)
3523 iounmap(ha->iobase);
1da177e4 3524
8ae6d9c7
GM		 3525 if (ha->cregbase)
3526 iounmap(ha->cregbase);
3527
a9083016
GM		 3528 if (ha->mqiobase)
3529 iounmap(ha->mqiobase);
6246b8a1 3530
f73cb695 3531 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase)
6246b8a1 3532 iounmap(ha->msixbase);
a9083016 3533 }
fe1b806f
CD		 3534}
3535
3536static void
db7157d4 3537qla2x00_clear_drv_active(struct qla_hw_data *ha)
fe1b806f 3538{
fe1b806f
CD		 3539 if (IS_QLA8044(ha)) {
3540 qla8044_idc_lock(ha);
c41afc9a 3541 qla8044_clear_drv_active(ha);
fe1b806f
CD		 3542 qla8044_idc_unlock(ha);
3543 } else if (IS_QLA82XX(ha)) {
3544 qla82xx_idc_lock(ha);
3545 qla82xx_clear_drv_active(ha);
3546 qla82xx_idc_unlock(ha);
3547 }
3548}
3549
3550static void
3551qla2x00_remove_one(struct pci_dev *pdev)
3552{
3553 scsi_qla_host_t *base_vha;
3554 struct qla_hw_data *ha;
3555
beb9e315
JL		 3556 base_vha = pci_get_drvdata(pdev);
3557 ha = base_vha->hw;
3558
3559 /* Indicate device removal to prevent future board_disable and wait
3560 * until any pending board_disable has completed. */
3561 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3562 cancel_work_sync(&ha->board_disable);
3563
fe1b806f 3564 /*
beb9e315
JL		 3565 * If the PCI device is disabled then there was a PCI-disconnect and
3566 * qla2x00_disable_board_on_pci_error has taken care of most of the
3567 * resources.
fe1b806f 3568 */
beb9e315 3569 if (!atomic_read(&pdev->enable_cnt)) {
726b8548
QT		 3570 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3571 base_vha->gnl.l, base_vha->gnl.ldma);
3572
beb9e315
JL		 3573 scsi_host_put(base_vha->host);
3574 kfree(ha);
3575 pci_set_drvdata(pdev, NULL);
fe1b806f 3576 return;
beb9e315 3577 }
638a1a01
SC		 3578 qla2x00_wait_for_hba_ready(base_vha);
3579
726b8548
QT		 3580 /*
3581 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 3582 * where it was set first.
3583 */
3584 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3585 return;
3586
fe1b806f 3587 set_bit(UNLOADING, &base_vha->dpc_flags);
e84067d7
DG		 3588
3589 qla_nvme_delete(base_vha);
3590
726b8548
QT		 3591 dma_free_coherent(&ha->pdev->dev,
3592 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma);
fe1b806f
CD		 3593
3594 if (IS_QLAFX00(ha))
3595 qlafx00_driver_shutdown(base_vha, 20);
3596
3597 qla2x00_delete_all_vps(ha, base_vha);
3598
3599 if (IS_QLA8031(ha)) {
3600 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3601 "Clearing fcoe driver presence.\n");
3602 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3603 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3604 "Error while clearing DRV-Presence.\n");
3605 }
3606
3607 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3608
3609 qla2x00_dfs_remove(base_vha);
3610
3611 qla84xx_put_chip(base_vha);
3612
2d5a4c34
HM		 3613 /* Laser should be disabled only for ISP2031 */
3614 if (IS_QLA2031(ha))
3615 qla83xx_disable_laser(base_vha);
3616
fe1b806f
CD		 3617 /* Disable timer */
3618 if (base_vha->timer_active)
3619 qla2x00_stop_timer(base_vha);
3620
3621 base_vha->flags.online = 0;
3622
b0d6cabd
HM		 3623 /* free DMA memory */
3624 if (ha->exlogin_buf)
3625 qla2x00_free_exlogin_buffer(ha);
3626
2f56a7f1
HM		 3627 /* free DMA memory */
3628 if (ha->exchoffld_buf)
3629 qla2x00_free_exchoffld_buffer(ha);
3630
fe1b806f
CD		 3631 qla2x00_destroy_deferred_work(ha);
3632
3633 qlt_remove_target(ha, base_vha);
3634
3635 qla2x00_free_sysfs_attr(base_vha, true);
3636
3637 fc_remove_host(base_vha->host);
482c9dc7 3638 qlt_remove_target_resources(ha);
fe1b806f
CD		 3639
3640 scsi_remove_host(base_vha->host);
3641
3642 qla2x00_free_device(base_vha);
3643
db7157d4 3644 qla2x00_clear_drv_active(ha);
fe1b806f 3645
d2749ffa
AE		 3646 scsi_host_put(base_vha->host);
3647
fe1b806f 3648 qla2x00_unmap_iobases(ha);
73208dfd 3649
e315cd28
AC		 3650 pci_release_selected_regions(ha->pdev, ha->bars);
3651 kfree(ha);
1da177e4 3652
90a86fc0
JC		 3653 pci_disable_pcie_error_reporting(pdev);
3654
665db93b 3655 pci_disable_device(pdev);
1da177e4 3656}
1da177e4
LT		 3657
3658static void
e315cd28 3659qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 3660{
e315cd28 3661 struct qla_hw_data *ha = vha->hw;
1da177e4 3662
85880801
AV		 3663 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3664
3665 /* Disable timer */
3666 if (vha->timer_active)
3667 qla2x00_stop_timer(vha);
3668
2afa19a9 3669 qla25xx_delete_queues(vha);
fe1b806f 3670
df613b96 3671 if (ha->flags.fce_enabled)
e315cd28 3672 qla2x00_disable_fce_trace(vha, NULL, NULL);
df613b96 3673
a7a167bf 3674 if (ha->eft)
e315cd28 3675 qla2x00_disable_eft_trace(vha);
a7a167bf 3676
f6ef3b18 3677 /* Stop currently executing firmware. */
e315cd28 3678 qla2x00_try_to_stop_firmware(vha);
1da177e4 3679
85880801
AV		 3680 vha->flags.online = 0;
3681
f6ef3b18 3682 /* turn-off interrupts on the card */
a9083016
GM		 3683 if (ha->interrupts_on) {
3684 vha->flags.init_done = 0;
fd34f556 3685 ha->isp_ops->disable_intrs(ha);
a9083016 3686 }
f6ef3b18 3687
093df737
QT		 3688 qla2x00_free_fcports(vha);
3689
e315cd28 3690 qla2x00_free_irqs(vha);
1da177e4 3691
093df737
QT		 3692 /* Flush the work queue and remove it */
3693 if (ha->wq) {
3694 flush_workqueue(ha->wq);
3695 destroy_workqueue(ha->wq);
3696 ha->wq = NULL;
3697 }
3698
8867048b 3699
e315cd28 3700 qla2x00_mem_free(ha);
73208dfd 3701
08de2844
GM		 3702 qla82xx_md_free(vha);
3703
73208dfd 3704 qla2x00_free_queues(ha);
1da177e4
LT		 3705}
3706
8867048b
CD		 3707void qla2x00_free_fcports(struct scsi_qla_host *vha)
3708{
3709 fc_port_t *fcport, *tfcport;
3710
3711 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3712 list_del(&fcport->list);
5f16b331 3713 qla2x00_clear_loop_id(fcport);
8867048b 3714 kfree(fcport);
8867048b
CD		 3715 }
3716}
3717
d97994dc 3718static inline void
e315cd28 3719qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc
AV		 3720 int defer)
3721{
d97994dc 3722 struct fc_rport *rport;
67becc00 3723 scsi_qla_host_t *base_vha;
044d78e1 3724 unsigned long flags;
d97994dc
AV		 3725
3726 if (!fcport->rport)
3727 return;
3728
3729 rport = fcport->rport;
3730 if (defer) {
67becc00 3731 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 3732 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 3733 fcport->drport = rport;
044d78e1 3734 spin_unlock_irqrestore(vha->host->host_lock, flags);
df673274 3735 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen);
67becc00
AV		 3736 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3737 qla2xxx_wake_dpc(base_vha);
2d70c103 3738 } else {
df673274 3739 int now;
726b8548 3740 if (rport) {
83548fe2
QT		 3741 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109,
3742 "%s %8phN. rport %p roles %x\n",
3743 __func__, fcport->port_name, rport,
3744 rport->roles);
d20ed91b 3745 fc_remote_port_delete(rport);
726b8548 3746 }
df673274 3747 qlt_do_generation_tick(vha, &now);
2d70c103 3748 }
d97994dc
AV		 3749}
3750
1da177e4
LT		 3751/*
3752 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3753 *
3754 * Input: ha = adapter block pointer. fcport = port structure pointer.
3755 *
3756 * Return: None.
3757 *
3758 * Context:
3759 */
e315cd28 3760void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 3761 int do_login, int defer)
1da177e4 3762{
8ae6d9c7
GM		 3763 if (IS_QLAFX00(vha->hw)) {
3764 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3765 qla2x00_schedule_rport_del(vha, fcport, defer);
3766 return;
3767 }
3768
2c3dfe3f 3769 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 3770 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 3771 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 3772 qla2x00_schedule_rport_del(vha, fcport, defer);
3773 }
fa2a1ce5 3774 /*
1da177e4
LT		 3775 * We may need to retry the login, so don't change the state of the
3776 * port but do the retries.
3777 */
3778 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 3779 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3780
3781 if (!do_login)
3782 return;
3783
a1d0285e
AE		 3784 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3785
1da177e4 3786 if (fcport->login_retry == 0) {
e315cd28 3787 fcport->login_retry = vha->hw->login_retry_count;
1da177e4 3788
83548fe2 3789 ql_dbg(ql_dbg_disc, vha, 0x20a3,
726b8548 3790 "Port login retry %8phN, lid 0x%04x retry cnt=%d.\n",
7b833558 3791 fcport->port_name, fcport->loop_id, fcport->login_retry);
1da177e4
LT		 3792 }
3793}
3794
3795/*
3796 * qla2x00_mark_all_devices_lost
3797 * Updates fcport state when device goes offline.
3798 *
3799 * Input:
3800 * ha = adapter block pointer.
3801 * fcport = port structure pointer.
3802 *
3803 * Return:
3804 * None.
3805 *
3806 * Context:
3807 */
3808void
e315cd28 3809qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3810{
3811 fc_port_t *fcport;
3812
83548fe2
QT		 3813 ql_dbg(ql_dbg_disc, vha, 0x20f1,
3814 "Mark all dev lost\n");
726b8548 3815
e315cd28 3816 list_for_each_entry(fcport, &vha->vp_fcports, list) {
726b8548
QT		 3817 fcport->scan_state = 0;
3818 qlt_schedule_sess_for_deletion_lock(fcport);
3819
c6d39e23 3820 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3821 continue;
0d6e61bc 3822
1da177e4
LT		 3823 /*
3824 * No point in marking the device as lost, if the device is
3825 * already DEAD.
3826 */
3827 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3828 continue;
e315cd28 3829 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3830 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3831 if (defer)
3832 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3833 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3834 qla2x00_schedule_rport_del(vha, fcport, defer);
3835 }
1da177e4
LT		 3836 }
3837}
3838
3839/*
3840* qla2x00_mem_alloc
3841* Allocates adapter memory.
3842*
3843* Returns:
3844* 0 = success.
e8711085 3845* !0 = failure.
1da177e4 3846*/
e8711085 3847static int
73208dfd
AC		 3848qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3849 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3850{
3851 char name[16];
1da177e4 3852
e8711085 3853 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3854 &ha->init_cb_dma, GFP_KERNEL);
e8711085 3855 if (!ha->init_cb)
e315cd28 3856 goto fail;
e8711085 3857
2d70c103
NB		 3858 if (qlt_mem_alloc(ha) < 0)
3859 goto fail_free_init_cb;
3860
642ef983
CD		 3861 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3862 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 3863 if (!ha->gid_list)
2d70c103 3864 goto fail_free_tgt_mem;
1da177e4 3865
e8711085
AV		 3866 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3867 if (!ha->srb_mempool)
e315cd28 3868 goto fail_free_gid_list;
e8711085 3869
7ec0effd 3870 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3871 /* Allocate cache for CT6 Ctx. */
3872 if (!ctx_cachep) {
3873 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3874 sizeof(struct ct6_dsd), 0,
3875 SLAB_HWCACHE_ALIGN, NULL);
3876 if (!ctx_cachep)
fc1ffd6c 3877 goto fail_free_srb_mempool;
a9083016
GM		 3878 }
3879 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3880 ctx_cachep);
3881 if (!ha->ctx_mempool)
3882 goto fail_free_srb_mempool;
7c3df132
SK		 3883 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3884 "ctx_cachep=%p ctx_mempool=%p.\n",
3885 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 3886 }
3887
e8711085
AV		 3888 /* Get memory for cached NVRAM */
3889 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3890 if (!ha->nvram)
a9083016 3891 goto fail_free_ctx_mempool;
e8711085 3892
e315cd28
AC		 3893 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3894 ha->pdev->device);
3895 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3896 DMA_POOL_SIZE, 8, 0);
3897 if (!ha->s_dma_pool)
3898 goto fail_free_nvram;
3899
7c3df132
SK		 3900 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3901 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3902 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3903
7ec0effd 3904 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
a9083016
GM		 3905 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3906 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3907 if (!ha->dl_dma_pool) {
7c3df132
SK		 3908 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3909 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 3910 goto fail_s_dma_pool;
3911 }
3912
3913 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3914 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3915 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 3916 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3917 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 3918 goto fail_dl_dma_pool;
3919 }
7c3df132
SK		 3920 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3921 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3922 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 3923 }
3924
e8711085
AV		 3925 /* Allocate memory for SNS commands */
3926 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 3927 /* Get consistent memory allocated for SNS commands */
e8711085 3928 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3929 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 3930 if (!ha->sns_cmd)
e315cd28 3931 goto fail_dma_pool;
7c3df132 3932 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 3933 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 3934 } else {
e315cd28 3935 /* Get consistent memory allocated for MS IOCB */
e8711085 3936 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 3937 &ha->ms_iocb_dma);
e8711085 3938 if (!ha->ms_iocb)
e315cd28
AC		 3939 goto fail_dma_pool;
3940 /* Get consistent memory allocated for CT SNS commands */
e8711085 3941 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3942 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 3943 if (!ha->ct_sns)
3944 goto fail_free_ms_iocb;
7c3df132
SK		 3945 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3946 "ms_iocb=%p ct_sns=%p.\n",
3947 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 3948 }
3949
e315cd28 3950 /* Allocate memory for request ring */
73208dfd
AC		 3951 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3952 if (!*req) {
7c3df132
SK		 3953 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3954 "Failed to allocate memory for req.\n");
e315cd28
AC		 3955 goto fail_req;
3956 }
73208dfd
AC		 3957 (*req)->length = req_len;
3958 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3959 ((*req)->length + 1) * sizeof(request_t),
3960 &(*req)->dma, GFP_KERNEL);
3961 if (!(*req)->ring) {
7c3df132
SK		 3962 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3963 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 3964 goto fail_req_ring;
3965 }
3966 /* Allocate memory for response ring */
73208dfd
AC		 3967 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3968 if (!*rsp) {
7c3df132
SK		 3969 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3970 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 3971 goto fail_rsp;
3972 }
73208dfd
AC		 3973 (*rsp)->hw = ha;
3974 (*rsp)->length = rsp_len;
3975 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3976 ((*rsp)->length + 1) * sizeof(response_t),
3977 &(*rsp)->dma, GFP_KERNEL);
3978 if (!(*rsp)->ring) {
7c3df132
SK		 3979 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3980 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 3981 goto fail_rsp_ring;
3982 }
73208dfd
AC		 3983 (*req)->rsp = *rsp;
3984 (*rsp)->req = *req;
7c3df132
SK		 3985 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3986 "req=%p req->length=%d req->ring=%p rsp=%p "
3987 "rsp->length=%d rsp->ring=%p.\n",
3988 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3989 (*rsp)->ring);
73208dfd
AC		 3990 /* Allocate memory for NVRAM data for vports */
3991 if (ha->nvram_npiv_size) {
3992 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
7c3df132 3993 ha->nvram_npiv_size, GFP_KERNEL);
73208dfd 3994 if (!ha->npiv_info) {
7c3df132
SK		 3995 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3996 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 3997 goto fail_npiv_info;
3998 }
3999 } else
4000 ha->npiv_info = NULL;
e8711085 4001
b64b0e8f 4002 /* Get consistent memory allocated for EX-INIT-CB. */
f73cb695 4003 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
b64b0e8f
AV		 4004 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4005 &ha->ex_init_cb_dma);
4006 if (!ha->ex_init_cb)
4007 goto fail_ex_init_cb;
7c3df132
SK		 4008 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
4009 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 4010 }
4011
a9083016
GM		 4012 INIT_LIST_HEAD(&ha->gbl_dsd_list);
4013
5ff1d584
AV		 4014 /* Get consistent memory allocated for Async Port-Database. */
4015 if (!IS_FWI2_CAPABLE(ha)) {
4016 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4017 &ha->async_pd_dma);
4018 if (!ha->async_pd)
4019 goto fail_async_pd;
7c3df132
SK		 4020 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
4021 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 4022 }
4023
e315cd28 4024 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 4025
4026 /* Allocate memory for our loop_id bitmap */
4027 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
4028 GFP_KERNEL);
4029 if (!ha->loop_id_map)
fc1ffd6c 4030 goto fail_loop_id_map;
5f16b331
CD		 4031 else {
4032 qla2x00_set_reserved_loop_ids(ha);
4033 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
b2a72ec3 4034 "loop_id_map=%p.\n", ha->loop_id_map);
5f16b331
CD		 4035 }
4036
e4e3a2ce
QT		 4037 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev,
4038 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL);
4039 if (!ha->sfp_data) {
4040 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4041 "Unable to allocate memory for SFP read-data.\n");
4042 goto fail_sfp_data;
4043 }
4044
b2a72ec3 4045 return 0;
e315cd28 4046
e4e3a2ce
QT		 4047fail_sfp_data:
4048 kfree(ha->loop_id_map);
fc1ffd6c
QT		 4049fail_loop_id_map:
4050 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
5ff1d584
AV		 4051fail_async_pd:
4052 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 4053fail_ex_init_cb:
4054 kfree(ha->npiv_info);
73208dfd
AC		 4055fail_npiv_info:
4056 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
4057 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
4058 (*rsp)->ring = NULL;
4059 (*rsp)->dma = 0;
e315cd28 4060fail_rsp_ring:
73208dfd 4061 kfree(*rsp);
e315cd28 4062fail_rsp:
73208dfd
AC		 4063 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
4064 sizeof(request_t), (*req)->ring, (*req)->dma);
4065 (*req)->ring = NULL;
4066 (*req)->dma = 0;
e315cd28 4067fail_req_ring:
73208dfd 4068 kfree(*req);
e315cd28
AC		 4069fail_req:
4070 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4071 ha->ct_sns, ha->ct_sns_dma);
4072 ha->ct_sns = NULL;
4073 ha->ct_sns_dma = 0;
e8711085
AV		 4074fail_free_ms_iocb:
4075 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4076 ha->ms_iocb = NULL;
4077 ha->ms_iocb_dma = 0;
fc1ffd6c
QT		 4078
4079 if (ha->sns_cmd)
4080 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4081 ha->sns_cmd, ha->sns_cmd_dma);
e315cd28 4082fail_dma_pool:
bad75002 4083 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 4084 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4085 ha->fcp_cmnd_dma_pool = NULL;
4086 }
4087fail_dl_dma_pool:
bad75002 4088 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 4089 dma_pool_destroy(ha->dl_dma_pool);
4090 ha->dl_dma_pool = NULL;
4091 }
4092fail_s_dma_pool:
e315cd28
AC		 4093 dma_pool_destroy(ha->s_dma_pool);
4094 ha->s_dma_pool = NULL;
e8711085
AV		 4095fail_free_nvram:
4096 kfree(ha->nvram);
4097 ha->nvram = NULL;
a9083016 4098fail_free_ctx_mempool:
fc1ffd6c
QT		 4099 if (ha->ctx_mempool)
4100 mempool_destroy(ha->ctx_mempool);
a9083016 4101 ha->ctx_mempool = NULL;
e8711085 4102fail_free_srb_mempool:
fc1ffd6c
QT		 4103 if (ha->srb_mempool)
4104 mempool_destroy(ha->srb_mempool);
e8711085 4105 ha->srb_mempool = NULL;
e8711085 4106fail_free_gid_list:
642ef983
CD		 4107 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4108 ha->gid_list,
e315cd28 4109 ha->gid_list_dma);
e8711085
AV		 4110 ha->gid_list = NULL;
4111 ha->gid_list_dma = 0;
2d70c103
NB		 4112fail_free_tgt_mem:
4113 qlt_mem_free(ha);
e315cd28
AC		 4114fail_free_init_cb:
4115 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
4116 ha->init_cb_dma);
4117 ha->init_cb = NULL;
4118 ha->init_cb_dma = 0;
e8711085 4119fail:
7c3df132
SK		 4120 ql_log(ql_log_fatal, NULL, 0x0030,
4121 "Memory allocation failure.\n");
e8711085 4122 return -ENOMEM;
1da177e4
LT		 4123}
4124
b0d6cabd
HM		 4125int
4126qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
4127{
4128 int rval;
4129 uint16_t size, max_cnt, temp;
4130 struct qla_hw_data *ha = vha->hw;
4131
4132 /* Return if we don't need to alloacate any extended logins */
4133 if (!ql2xexlogins)
4134 return QLA_SUCCESS;
4135
99e1b683
QT		 4136 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha))
4137 return QLA_SUCCESS;
4138
b0d6cabd
HM		 4139 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
4140 max_cnt = 0;
4141 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
4142 if (rval != QLA_SUCCESS) {
4143 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
4144 "Failed to get exlogin status.\n");
4145 return rval;
4146 }
4147
4148 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
99e1b683
QT		 4149 temp *= size;
4150
4151 if (temp != ha->exlogin_size) {
4152 qla2x00_free_exlogin_buffer(ha);
4153 ha->exlogin_size = temp;
4154
4155 ql_log(ql_log_info, vha, 0xd024,
4156 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
4157 max_cnt, size, temp);
4158
4159 ql_log(ql_log_info, vha, 0xd025,
4160 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size);
4161
4162 /* Get consistent memory for extended logins */
4163 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
4164 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
4165 if (!ha->exlogin_buf) {
4166 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
b0d6cabd 4167 "Failed to allocate memory for exlogin_buf_dma.\n");
99e1b683
QT		 4168 return -ENOMEM;
4169 }
b0d6cabd
HM		 4170 }
4171
4172 /* Now configure the dma buffer */
4173 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
4174 if (rval) {
83548fe2 4175 ql_log(ql_log_fatal, vha, 0xd033,
b0d6cabd
HM		 4176 "Setup extended login buffer ****FAILED****.\n");
4177 qla2x00_free_exlogin_buffer(ha);
4178 }
4179
4180 return rval;
4181}
4182
4183/*
4184* qla2x00_free_exlogin_buffer
4185*
4186* Input:
4187* ha = adapter block pointer
4188*/
4189void
4190qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
4191{
4192 if (ha->exlogin_buf) {
4193 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
4194 ha->exlogin_buf, ha->exlogin_buf_dma);
4195 ha->exlogin_buf = NULL;
4196 ha->exlogin_size = 0;
4197 }
4198}
4199
99e1b683
QT		 4200static void
4201qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt)
4202{
4203 u32 temp;
4204 *ret_cnt = FW_DEF_EXCHANGES_CNT;
4205
4206 if (qla_ini_mode_enabled(vha)) {
4207 if (ql2xiniexchg > max_cnt)
4208 ql2xiniexchg = max_cnt;
4209
4210 if (ql2xiniexchg > FW_DEF_EXCHANGES_CNT)
4211 *ret_cnt = ql2xiniexchg;
4212 } else if (qla_tgt_mode_enabled(vha)) {
4213 if (ql2xexchoffld > max_cnt)
4214 ql2xexchoffld = max_cnt;
4215
4216 if (ql2xexchoffld > FW_DEF_EXCHANGES_CNT)
4217 *ret_cnt = ql2xexchoffld;
4218 } else if (qla_dual_mode_enabled(vha)) {
4219 temp = ql2xiniexchg + ql2xexchoffld;
4220 if (temp > max_cnt) {
4221 ql2xiniexchg -= (temp - max_cnt)/2;
4222 ql2xexchoffld -= (((temp - max_cnt)/2) + 1);
4223 temp = max_cnt;
4224 }
4225
4226 if (temp > FW_DEF_EXCHANGES_CNT)
4227 *ret_cnt = temp;
4228 }
4229}
4230
2f56a7f1
HM		 4231int
4232qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
4233{
4234 int rval;
99e1b683
QT		 4235 u16 size, max_cnt;
4236 u32 temp;
2f56a7f1
HM		 4237 struct qla_hw_data *ha = vha->hw;
4238
99e1b683
QT		 4239 if (!ha->flags.exchoffld_enabled)
4240 return QLA_SUCCESS;
4241
4242 if (!IS_EXCHG_OFFLD_CAPABLE(ha))
2f56a7f1
HM		 4243 return QLA_SUCCESS;
4244
2f56a7f1
HM		 4245 max_cnt = 0;
4246 rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
4247 if (rval != QLA_SUCCESS) {
4248 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
4249 "Failed to get exlogin status.\n");
4250 return rval;
4251 }
4252
99e1b683
QT		 4253 qla2x00_number_of_exch(vha, &temp, max_cnt);
4254 temp *= size;
2f56a7f1 4255
99e1b683
QT		 4256 if (temp != ha->exchoffld_size) {
4257 qla2x00_free_exchoffld_buffer(ha);
4258 ha->exchoffld_size = temp;
4259
4260 ql_log(ql_log_info, vha, 0xd016,
4261 "Exchange offload: max_count=%d, buffers=0x%x, total=%d.\n",
4262 max_cnt, size, temp);
4263
4264 ql_log(ql_log_info, vha, 0xd017,
4265 "Exchange Buffers requested size = 0x%x\n",
4266 ha->exchoffld_size);
4267
4268 /* Get consistent memory for extended logins */
4269 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
4270 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
4271 if (!ha->exchoffld_buf) {
4272 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4273 "Failed to allocate memory for exchoffld_buf_dma.\n");
4274 return -ENOMEM;
4275 }
2f56a7f1
HM		 4276 }
4277
4278 /* Now configure the dma buffer */
99e1b683 4279 rval = qla_set_exchoffld_mem_cfg(vha);
2f56a7f1
HM		 4280 if (rval) {
4281 ql_log(ql_log_fatal, vha, 0xd02e,
4282 "Setup exchange offload buffer ****FAILED****.\n");
4283 qla2x00_free_exchoffld_buffer(ha);
99e1b683
QT		 4284 } else {
4285 /* re-adjust number of target exchange */
4286 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb;
4287
4288 if (qla_ini_mode_enabled(vha))
4289 icb->exchange_count = 0;
4290 else
4291 icb->exchange_count = cpu_to_le16(ql2xexchoffld);
2f56a7f1
HM		 4292 }
4293
4294 return rval;
4295}
4296
4297/*
4298* qla2x00_free_exchoffld_buffer
4299*
4300* Input:
4301* ha = adapter block pointer
4302*/
4303void
4304qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
4305{
4306 if (ha->exchoffld_buf) {
4307 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
4308 ha->exchoffld_buf, ha->exchoffld_buf_dma);
4309 ha->exchoffld_buf = NULL;
4310 ha->exchoffld_size = 0;
4311 }
4312}
4313
1da177e4 4314/*
e30d1756
MI		 4315* qla2x00_free_fw_dump
4316* Frees fw dump stuff.
1da177e4
LT		 4317*
4318* Input:
7ec0effd 4319* ha = adapter block pointer
1da177e4 4320*/
a824ebb3 4321static void
e30d1756 4322qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 4323{
df613b96 4324 if (ha->fce)
f73cb695
CD		 4325 dma_free_coherent(&ha->pdev->dev,
4326 FCE_SIZE, ha->fce, ha->fce_dma);
df613b96 4327
f73cb695
CD		 4328 if (ha->eft)
4329 dma_free_coherent(&ha->pdev->dev,
4330 EFT_SIZE, ha->eft, ha->eft_dma);
4331
4332 if (ha->fw_dump)
a7a167bf 4333 vfree(ha->fw_dump);
f73cb695
CD		 4334 if (ha->fw_dump_template)
4335 vfree(ha->fw_dump_template);
4336
e30d1756
MI		 4337 ha->fce = NULL;
4338 ha->fce_dma = 0;
4339 ha->eft = NULL;
4340 ha->eft_dma = 0;
e30d1756 4341 ha->fw_dumped = 0;
61f098dd 4342 ha->fw_dump_cap_flags = 0;
e30d1756 4343 ha->fw_dump_reading = 0;
f73cb695
CD		 4344 ha->fw_dump = NULL;
4345 ha->fw_dump_len = 0;
4346 ha->fw_dump_template = NULL;
4347 ha->fw_dump_template_len = 0;
e30d1756
MI		 4348}
4349
4350/*
4351* qla2x00_mem_free
4352* Frees all adapter allocated memory.
4353*
4354* Input:
4355* ha = adapter block pointer.
4356*/
4357static void
4358qla2x00_mem_free(struct qla_hw_data *ha)
4359{
4360 qla2x00_free_fw_dump(ha);
4361
81178772
SK		 4362 if (ha->mctp_dump)
4363 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
4364 ha->mctp_dump_dma);
4365
e30d1756
MI		 4366 if (ha->srb_mempool)
4367 mempool_destroy(ha->srb_mempool);
a7a167bf 4368
11bbc1d8
AV		 4369 if (ha->dcbx_tlv)
4370 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
4371 ha->dcbx_tlv, ha->dcbx_tlv_dma);
4372
ce0423f4
AV		 4373 if (ha->xgmac_data)
4374 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
4375 ha->xgmac_data, ha->xgmac_data_dma);
4376
1da177e4
LT		 4377 if (ha->sns_cmd)
4378 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 4379 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 4380
4381 if (ha->ct_sns)
4382 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 4383 ha->ct_sns, ha->ct_sns_dma);
1da177e4 4384
88729e53 4385 if (ha->sfp_data)
e4e3a2ce
QT		 4386 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data,
4387 ha->sfp_data_dma);
88729e53 4388
1da177e4
LT		 4389 if (ha->ms_iocb)
4390 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4391
b64b0e8f 4392 if (ha->ex_init_cb)
a9083016
GM		 4393 dma_pool_free(ha->s_dma_pool,
4394 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 4395
5ff1d584
AV		 4396 if (ha->async_pd)
4397 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4398
1da177e4
LT		 4399 if (ha->s_dma_pool)
4400 dma_pool_destroy(ha->s_dma_pool);
4401
1da177e4 4402 if (ha->gid_list)
642ef983
CD		 4403 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4404 ha->gid_list, ha->gid_list_dma);
1da177e4 4405
a9083016
GM		 4406 if (IS_QLA82XX(ha)) {
4407 if (!list_empty(&ha->gbl_dsd_list)) {
4408 struct dsd_dma *dsd_ptr, *tdsd_ptr;
4409
4410 /* clean up allocated prev pool */
4411 list_for_each_entry_safe(dsd_ptr,
4412 tdsd_ptr, &ha->gbl_dsd_list, list) {
4413 dma_pool_free(ha->dl_dma_pool,
4414 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
4415 list_del(&dsd_ptr->list);
4416 kfree(dsd_ptr);
4417 }
4418 }
4419 }
4420
4421 if (ha->dl_dma_pool)
4422 dma_pool_destroy(ha->dl_dma_pool);
4423
4424 if (ha->fcp_cmnd_dma_pool)
4425 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4426
4427 if (ha->ctx_mempool)
4428 mempool_destroy(ha->ctx_mempool);
4429
2d70c103
NB		 4430 qlt_mem_free(ha);
4431
e315cd28
AC		 4432 if (ha->init_cb)
4433 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 4434 ha->init_cb, ha->init_cb_dma);
e315cd28
AC		 4435 vfree(ha->optrom_buffer);
4436 kfree(ha->nvram);
73208dfd 4437 kfree(ha->npiv_info);
7a67735b 4438 kfree(ha->swl);
5f16b331 4439 kfree(ha->loop_id_map);
1da177e4 4440
e8711085 4441 ha->srb_mempool = NULL;
a9083016 4442 ha->ctx_mempool = NULL;
1da177e4
LT		 4443 ha->sns_cmd = NULL;
4444 ha->sns_cmd_dma = 0;
4445 ha->ct_sns = NULL;
4446 ha->ct_sns_dma = 0;
4447 ha->ms_iocb = NULL;
4448 ha->ms_iocb_dma = 0;
1da177e4
LT		 4449 ha->init_cb = NULL;
4450 ha->init_cb_dma = 0;
b64b0e8f
AV		 4451 ha->ex_init_cb = NULL;
4452 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 4453 ha->async_pd = NULL;
4454 ha->async_pd_dma = 0;
1da177e4
LT		 4455
4456 ha->s_dma_pool = NULL;
a9083016
GM		 4457 ha->dl_dma_pool = NULL;
4458 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 4459
1da177e4
LT		 4460 ha->gid_list = NULL;
4461 ha->gid_list_dma = 0;
2d70c103
NB		 4462
4463 ha->tgt.atio_ring = NULL;
4464 ha->tgt.atio_dma = 0;
4465 ha->tgt.tgt_vp_map = NULL;
e315cd28 4466}
1da177e4 4467
e315cd28
AC		 4468struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
4469 struct qla_hw_data *ha)
4470{
4471 struct Scsi_Host *host;
4472 struct scsi_qla_host *vha = NULL;
854165f4 4473
e315cd28 4474 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
41dc529a 4475 if (!host) {
7c3df132
SK		 4476 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
4477 "Failed to allocate host from the scsi layer, aborting.\n");
41dc529a 4478 return NULL;
e315cd28
AC		 4479 }
4480
4481 /* Clear our data area */
4482 vha = shost_priv(host);
4483 memset(vha, 0, sizeof(scsi_qla_host_t));
4484
4485 vha->host = host;
4486 vha->host_no = host->host_no;
4487 vha->hw = ha;
4488
4489 INIT_LIST_HEAD(&vha->vp_fcports);
4490 INIT_LIST_HEAD(&vha->work_list);
4491 INIT_LIST_HEAD(&vha->list);
8b2f5ff3
SN		 4492 INIT_LIST_HEAD(&vha->qla_cmd_list);
4493 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list);
71cdc079 4494 INIT_LIST_HEAD(&vha->logo_list);
b7bd104e 4495 INIT_LIST_HEAD(&vha->plogi_ack_list);
d7459527 4496 INIT_LIST_HEAD(&vha->qp_list);
41dc529a 4497 INIT_LIST_HEAD(&vha->gnl.fcports);
a5d42f4c 4498 INIT_LIST_HEAD(&vha->nvme_rport_list);
e315cd28 4499
f999f4c1 4500 spin_lock_init(&vha->work_lock);
8b2f5ff3 4501 spin_lock_init(&vha->cmd_list_lock);
726b8548 4502 init_waitqueue_head(&vha->fcport_waitQ);
c4a9b538 4503 init_waitqueue_head(&vha->vref_waitq);
f999f4c1 4504
2fdbc65e
BVA		 4505 vha->gnl.size = sizeof(struct get_name_list_extended) *
4506 (ha->max_loop_id + 1);
41dc529a
QT		 4507 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev,
4508 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL);
4509 if (!vha->gnl.l) {
83548fe2 4510 ql_log(ql_log_fatal, vha, 0xd04a,
41dc529a
QT		 4511 "Alloc failed for name list.\n");
4512 scsi_remove_host(vha->host);
4513 return NULL;
4514 }
f999f4c1 4515
e315cd28 4516 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 4517 ql_dbg(ql_dbg_init, vha, 0x0041,
4518 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
4519 vha->host, vha->hw, vha,
4520 dev_name(&(ha->pdev->dev)));
4521
e315cd28 4522 return vha;
1da177e4
LT		 4523}
4524
726b8548 4525struct qla_work_evt *
f999f4c1 4526qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 4527{
4528 struct qla_work_evt *e;
feafb7b1
AE		 4529 uint8_t bail;
4530
4531 QLA_VHA_MARK_BUSY(vha, bail);
4532 if (bail)
4533 return NULL;
0971de7f 4534
f999f4c1 4535 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 4536 if (!e) {
4537 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 4538 return NULL;
feafb7b1 4539 }
0971de7f
AV		 4540
4541 INIT_LIST_HEAD(&e->list);
4542 e->type = type;
4543 e->flags = QLA_EVT_FLAG_FREE;
4544 return e;
4545}
4546
726b8548 4547int
f999f4c1 4548qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 4549{
f999f4c1 4550 unsigned long flags;
0971de7f 4551
f999f4c1 4552 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 4553 list_add_tail(&e->list, &vha->work_list);
f999f4c1 4554 spin_unlock_irqrestore(&vha->work_lock, flags);
ec7193e2
QT		 4555
4556 if (QLA_EARLY_LINKUP(vha->hw))
4557 schedule_work(&vha->iocb_work);
4558 else
4559 qla2xxx_wake_dpc(vha);
f999f4c1 4560
0971de7f
AV		 4561 return QLA_SUCCESS;
4562}
4563
4564int
e315cd28 4565qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 4566 u32 data)
4567{
4568 struct qla_work_evt *e;
4569
f999f4c1 4570 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 4571 if (!e)
4572 return QLA_FUNCTION_FAILED;
4573
4574 e->u.aen.code = code;
4575 e->u.aen.data = data;
f999f4c1 4576 return qla2x00_post_work(vha, e);
0971de7f
AV		 4577}
4578
8a659571
AV		 4579int
4580qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
4581{
4582 struct qla_work_evt *e;
4583
f999f4c1 4584 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 4585 if (!e)
4586 return QLA_FUNCTION_FAILED;
4587
4588 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 4589 return qla2x00_post_work(vha, e);
8a659571
AV		 4590}
4591
ac280b67
AV		 4592#define qla2x00_post_async_work(name, type) \
4593int qla2x00_post_async_##name##_work( \
4594 struct scsi_qla_host *vha, \
4595 fc_port_t *fcport, uint16_t *data) \
4596{ \
4597 struct qla_work_evt *e; \
4598 \
4599 e = qla2x00_alloc_work(vha, type); \
4600 if (!e) \
4601 return QLA_FUNCTION_FAILED; \
4602 \
4603 e->u.logio.fcport = fcport; \
4604 if (data) { \
4605 e->u.logio.data[0] = data[0]; \
4606 e->u.logio.data[1] = data[1]; \
4607 } \
4608 return qla2x00_post_work(vha, e); \
4609}
4610
4611qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
ac280b67
AV		 4612qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
4613qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 4614qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
4615qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
ac280b67 4616
3420d36c
AV		 4617int
4618qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
4619{
4620 struct qla_work_evt *e;
4621
4622 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
4623 if (!e)
4624 return QLA_FUNCTION_FAILED;
4625
4626 e->u.uevent.code = code;
4627 return qla2x00_post_work(vha, e);
4628}
4629
4630static void
4631qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
4632{
4633 char event_string[40];
4634 char *envp[] = { event_string, NULL };
4635
4636 switch (code) {
4637 case QLA_UEVENT_CODE_FW_DUMP:
4638 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
4639 vha->host_no);
4640 break;
4641 default:
4642 /* do nothing */
4643 break;
4644 }
4645 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
4646}
4647
8ae6d9c7
GM		 4648int
4649qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
4650 uint32_t *data, int cnt)
4651{
4652 struct qla_work_evt *e;
4653
4654 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
4655 if (!e)
4656 return QLA_FUNCTION_FAILED;
4657
4658 e->u.aenfx.evtcode = evtcode;
4659 e->u.aenfx.count = cnt;
4660 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
4661 return qla2x00_post_work(vha, e);
4662}
4663
726b8548
QT		 4664int qla24xx_post_upd_fcport_work(struct scsi_qla_host *vha, fc_port_t *fcport)
4665{
4666 struct qla_work_evt *e;
4667
4668 e = qla2x00_alloc_work(vha, QLA_EVT_UPD_FCPORT);
4669 if (!e)
4670 return QLA_FUNCTION_FAILED;
4671
4672 e->u.fcport.fcport = fcport;
4673 return qla2x00_post_work(vha, e);
4674}
4675
4676static
4677void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e)
4678{
4679 unsigned long flags;
4680 fc_port_t *fcport = NULL;
4681 struct qlt_plogi_ack_t *pla =
4682 (struct qlt_plogi_ack_t *)e->u.new_sess.pla;
4683
4684 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
4685 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1);
4686 if (fcport) {
4687 fcport->d_id = e->u.new_sess.id;
4688 if (pla) {
4689 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
4690 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN);
4691 /* we took an extra ref_count to prevent PLOGI ACK when
4692 * fcport/sess has not been created.
4693 */
4694 pla->ref_count--;
4695 }
4696 } else {
4697 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
4698 if (fcport) {
4699 fcport->d_id = e->u.new_sess.id;
4700 fcport->scan_state = QLA_FCPORT_FOUND;
4701 fcport->flags |= FCF_FABRIC_DEVICE;
4702 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
4703
4704 memcpy(fcport->port_name, e->u.new_sess.port_name,
4705 WWN_SIZE);
4706 list_add_tail(&fcport->list, &vha->vp_fcports);
4707
4708 if (pla) {
4709 qlt_plogi_ack_link(vha, pla, fcport,
4710 QLT_PLOGI_LINK_SAME_WWN);
4711 pla->ref_count--;
4712 }
4713 }
4714 }
4715 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
4716
4717 if (fcport) {
4718 if (pla)
4719 qlt_plogi_ack_unref(vha, pla);
4720 else
4721 qla24xx_async_gnl(vha, fcport);
4722 }
4723}
4724
ac280b67 4725void
e315cd28 4726qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 4727{
f999f4c1
AV		 4728 struct qla_work_evt *e, *tmp;
4729 unsigned long flags;
4730 LIST_HEAD(work);
0971de7f 4731
f999f4c1
AV		 4732 spin_lock_irqsave(&vha->work_lock, flags);
4733 list_splice_init(&vha->work_list, &work);
4734 spin_unlock_irqrestore(&vha->work_lock, flags);
4735
4736 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 4737 list_del_init(&e->list);
0971de7f
AV		 4738
4739 switch (e->type) {
4740 case QLA_EVT_AEN:
e315cd28 4741 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 4742 e->u.aen.code, e->u.aen.data);
4743 break;
8a659571
AV		 4744 case QLA_EVT_IDC_ACK:
4745 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
4746 break;
ac280b67
AV		 4747 case QLA_EVT_ASYNC_LOGIN:
4748 qla2x00_async_login(vha, e->u.logio.fcport,
4749 e->u.logio.data);
4750 break;
ac280b67
AV		 4751 case QLA_EVT_ASYNC_LOGOUT:
4752 qla2x00_async_logout(vha, e->u.logio.fcport);
4753 break;
4754 case QLA_EVT_ASYNC_LOGOUT_DONE:
4755 qla2x00_async_logout_done(vha, e->u.logio.fcport,
4756 e->u.logio.data);
4757 break;
5ff1d584
AV		 4758 case QLA_EVT_ASYNC_ADISC:
4759 qla2x00_async_adisc(vha, e->u.logio.fcport,
4760 e->u.logio.data);
4761 break;
4762 case QLA_EVT_ASYNC_ADISC_DONE:
4763 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
4764 e->u.logio.data);
4765 break;
3420d36c
AV		 4766 case QLA_EVT_UEVENT:
4767 qla2x00_uevent_emit(vha, e->u.uevent.code);
4768 break;
8ae6d9c7
GM		 4769 case QLA_EVT_AENFX:
4770 qlafx00_process_aen(vha, e);
4771 break;
726b8548
QT		 4772 case QLA_EVT_GIDPN:
4773 qla24xx_async_gidpn(vha, e->u.fcport.fcport);
4774 break;
4775 case QLA_EVT_GPNID:
4776 qla24xx_async_gpnid(vha, &e->u.gpnid.id);
4777 break;
4778 case QLA_EVT_GPNID_DONE:
4779 qla24xx_async_gpnid_done(vha, e->u.iosb.sp);
4780 break;
4781 case QLA_EVT_NEW_SESS:
4782 qla24xx_create_new_sess(vha, e);
4783 break;
4784 case QLA_EVT_GPDB:
4785 qla24xx_async_gpdb(vha, e->u.fcport.fcport,
4786 e->u.fcport.opt);
4787 break;
a5d42f4c
DG		 4788 case QLA_EVT_PRLI:
4789 qla24xx_async_prli(vha, e->u.fcport.fcport);
4790 break;
726b8548
QT		 4791 case QLA_EVT_GPSC:
4792 qla24xx_async_gpsc(vha, e->u.fcport.fcport);
4793 break;
4794 case QLA_EVT_UPD_FCPORT:
4795 qla2x00_update_fcport(vha, e->u.fcport.fcport);
4796 break;
4797 case QLA_EVT_GNL:
4798 qla24xx_async_gnl(vha, e->u.fcport.fcport);
4799 break;
4800 case QLA_EVT_NACK:
4801 qla24xx_do_nack_work(vha, e);
4802 break;
0971de7f
AV		 4803 }
4804 if (e->flags & QLA_EVT_FLAG_FREE)
4805 kfree(e);
feafb7b1
AE		 4806
4807 /* For each work completed decrement vha ref count */
4808 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 4809 }
e315cd28 4810}
f999f4c1 4811
e315cd28
AC		 4812/* Relogins all the fcports of a vport
4813 * Context: dpc thread
4814 */
4815void qla2x00_relogin(struct scsi_qla_host *vha)
4816{
4817 fc_port_t *fcport;
c6b2fca8 4818 int status;
726b8548 4819 struct event_arg ea;
e315cd28
AC		 4820
4821 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4822 /*
4823 * If the port is not ONLINE then try to login
4824 * to it if we haven't run out of retries.
4825 */
5ff1d584
AV		 4826 if (atomic_read(&fcport->state) != FCS_ONLINE &&
4827 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
ac280b67 4828 fcport->login_retry--;
e315cd28 4829 if (fcport->flags & FCF_FABRIC_DEVICE) {
83548fe2 4830 ql_dbg(ql_dbg_disc, fcport->vha, 0x2108,
726b8548
QT		 4831 "%s %8phC DS %d LS %d\n", __func__,
4832 fcport->port_name, fcport->disc_state,
4833 fcport->fw_login_state);
4834 memset(&ea, 0, sizeof(ea));
4835 ea.event = FCME_RELOGIN;
4836 ea.fcport = fcport;
4837 qla2x00_fcport_event_handler(vha, &ea);
4838 } else {
e315cd28
AC		 4839 status = qla2x00_local_device_login(vha,
4840 fcport);
726b8548
QT		 4841 if (status == QLA_SUCCESS) {
4842 fcport->old_loop_id = fcport->loop_id;
4843 ql_dbg(ql_dbg_disc, vha, 0x2003,
4844 "Port login OK: logged in ID 0x%x.\n",
4845 fcport->loop_id);
4846 qla2x00_update_fcport(vha, fcport);
4847 } else if (status == 1) {
4848 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4849 /* retry the login again */
4850 ql_dbg(ql_dbg_disc, vha, 0x2007,
4851 "Retrying %d login again loop_id 0x%x.\n",
4852 fcport->login_retry,
4853 fcport->loop_id);
4854 } else {
4855 fcport->login_retry = 0;
4856 }
e315cd28 4857
726b8548
QT		 4858 if (fcport->login_retry == 0 &&
4859 status != QLA_SUCCESS)
4860 qla2x00_clear_loop_id(fcport);
e315cd28 4861 }
e315cd28
AC		 4862 }
4863 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4864 break;
0971de7f 4865 }
0971de7f
AV		 4866}
4867
7d613ac6
SV		 4868/* Schedule work on any of the dpc-workqueues */
4869void
4870qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
4871{
4872 struct qla_hw_data *ha = base_vha->hw;
4873
4874 switch (work_code) {
4875 case MBA_IDC_AEN: /* 0x8200 */
4876 if (ha->dpc_lp_wq)
4877 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
4878 break;
4879
4880 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
4881 if (!ha->flags.nic_core_reset_hdlr_active) {
4882 if (ha->dpc_hp_wq)
4883 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
4884 } else
4885 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
4886 "NIC Core reset is already active. Skip "
4887 "scheduling it again.\n");
4888 break;
4889 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
4890 if (ha->dpc_hp_wq)
4891 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
4892 break;
4893 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
4894 if (ha->dpc_hp_wq)
4895 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
4896 break;
4897 default:
4898 ql_log(ql_log_warn, base_vha, 0xb05f,
d939be3a 4899 "Unknown work-code=0x%x.\n", work_code);
7d613ac6
SV		 4900 }
4901
4902 return;
4903}
4904
4905/* Work: Perform NIC Core Unrecoverable state handling */
4906void
4907qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
4908{
4909 struct qla_hw_data *ha =
2ad1b67c 4910 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 4911 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4912 uint32_t dev_state = 0;
4913
4914 qla83xx_idc_lock(base_vha, 0);
4915 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4916 qla83xx_reset_ownership(base_vha);
4917 if (ha->flags.nic_core_reset_owner) {
4918 ha->flags.nic_core_reset_owner = 0;
4919 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4920 QLA8XXX_DEV_FAILED);
4921 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
4922 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4923 }
4924 qla83xx_idc_unlock(base_vha, 0);
4925}
4926
4927/* Work: Execute IDC state handler */
4928void
4929qla83xx_idc_state_handler_work(struct work_struct *work)
4930{
4931 struct qla_hw_data *ha =
2ad1b67c 4932 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 4933 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4934 uint32_t dev_state = 0;
4935
4936 qla83xx_idc_lock(base_vha, 0);
4937 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4938 if (dev_state == QLA8XXX_DEV_FAILED ||
4939 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
4940 qla83xx_idc_state_handler(base_vha);
4941 qla83xx_idc_unlock(base_vha, 0);
4942}
4943
fa492630 4944static int
7d613ac6
SV		 4945qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
4946{
4947 int rval = QLA_SUCCESS;
4948 unsigned long heart_beat_wait = jiffies + (1 * HZ);
4949 uint32_t heart_beat_counter1, heart_beat_counter2;
4950
4951 do {
4952 if (time_after(jiffies, heart_beat_wait)) {
4953 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
4954 "Nic Core f/w is not alive.\n");
4955 rval = QLA_FUNCTION_FAILED;
4956 break;
4957 }
4958
4959 qla83xx_idc_lock(base_vha, 0);
4960 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4961 &heart_beat_counter1);
4962 qla83xx_idc_unlock(base_vha, 0);
4963 msleep(100);
4964 qla83xx_idc_lock(base_vha, 0);
4965 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4966 &heart_beat_counter2);
4967 qla83xx_idc_unlock(base_vha, 0);
4968 } while (heart_beat_counter1 == heart_beat_counter2);
4969
4970 return rval;
4971}
4972
4973/* Work: Perform NIC Core Reset handling */
4974void
4975qla83xx_nic_core_reset_work(struct work_struct *work)
4976{
4977 struct qla_hw_data *ha =
4978 container_of(work, struct qla_hw_data, nic_core_reset);
4979 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4980 uint32_t dev_state = 0;
4981
81178772
SK		 4982 if (IS_QLA2031(ha)) {
4983 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
4984 ql_log(ql_log_warn, base_vha, 0xb081,
4985 "Failed to dump mctp\n");
4986 return;
4987 }
4988
7d613ac6
SV		 4989 if (!ha->flags.nic_core_reset_hdlr_active) {
4990 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
4991 qla83xx_idc_lock(base_vha, 0);
4992 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4993 &dev_state);
4994 qla83xx_idc_unlock(base_vha, 0);
4995 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
4996 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
4997 "Nic Core f/w is alive.\n");
4998 return;
4999 }
5000 }
5001
5002 ha->flags.nic_core_reset_hdlr_active = 1;
5003 if (qla83xx_nic_core_reset(base_vha)) {
5004 /* NIC Core reset failed. */
5005 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
5006 "NIC Core reset failed.\n");
5007 }
5008 ha->flags.nic_core_reset_hdlr_active = 0;
5009 }
5010}
5011
5012/* Work: Handle 8200 IDC aens */
5013void
5014qla83xx_service_idc_aen(struct work_struct *work)
5015{
5016 struct qla_hw_data *ha =
5017 container_of(work, struct qla_hw_data, idc_aen);
5018 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5019 uint32_t dev_state, idc_control;
5020
5021 qla83xx_idc_lock(base_vha, 0);
5022 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5023 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
5024 qla83xx_idc_unlock(base_vha, 0);
5025 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
5026 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
5027 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
5028 "Application requested NIC Core Reset.\n");
5029 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5030 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
5031 QLA_SUCCESS) {
5032 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
5033 "Other protocol driver requested NIC Core Reset.\n");
5034 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5035 }
5036 } else if (dev_state == QLA8XXX_DEV_FAILED ||
5037 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
5038 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5039 }
5040}
5041
5042static void
5043qla83xx_wait_logic(void)
5044{
5045 int i;
5046
5047 /* Yield CPU */
5048 if (!in_interrupt()) {
5049 /*
5050 * Wait about 200ms before retrying again.
5051 * This controls the number of retries for single
5052 * lock operation.
5053 */
5054 msleep(100);
5055 schedule();
5056 } else {
5057 for (i = 0; i < 20; i++)
5058 cpu_relax(); /* This a nop instr on i386 */
5059 }
5060}
5061
fa492630 5062static int
7d613ac6
SV		 5063qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
5064{
5065 int rval;
5066 uint32_t data;
5067 uint32_t idc_lck_rcvry_stage_mask = 0x3;
5068 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
5069 struct qla_hw_data *ha = base_vha->hw;
6c315553
SK		 5070 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
5071 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 5072
5073 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
5074 if (rval)
5075 return rval;
5076
5077 if ((data & idc_lck_rcvry_stage_mask) > 0) {
5078 return QLA_SUCCESS;
5079 } else {
5080 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
5081 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5082 data);
5083 if (rval)
5084 return rval;
5085
5086 msleep(200);
5087
5088 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5089 &data);
5090 if (rval)
5091 return rval;
5092
5093 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
5094 data &= (IDC_LOCK_RECOVERY_STAGE2 |
5095 ~(idc_lck_rcvry_stage_mask));
5096 rval = qla83xx_wr_reg(base_vha,
5097 QLA83XX_IDC_LOCK_RECOVERY, data);
5098 if (rval)
5099 return rval;
5100
5101 /* Forcefully perform IDC UnLock */
5102 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
5103 &data);
5104 if (rval)
5105 return rval;
5106 /* Clear lock-id by setting 0xff */
5107 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5108 0xff);
5109 if (rval)
5110 return rval;
5111 /* Clear lock-recovery by setting 0x0 */
5112 rval = qla83xx_wr_reg(base_vha,
5113 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
5114 if (rval)
5115 return rval;
5116 } else
5117 return QLA_SUCCESS;
5118 }
5119
5120 return rval;
5121}
5122
fa492630 5123static int
7d613ac6
SV		 5124qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
5125{
5126 int rval = QLA_SUCCESS;
5127 uint32_t o_drv_lockid, n_drv_lockid;
5128 unsigned long lock_recovery_timeout;
5129
5130 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
5131retry_lockid:
5132 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
5133 if (rval)
5134 goto exit;
5135
5136 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
5137 if (time_after_eq(jiffies, lock_recovery_timeout)) {
5138 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
5139 return QLA_SUCCESS;
5140 else
5141 return QLA_FUNCTION_FAILED;
5142 }
5143
5144 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
5145 if (rval)
5146 goto exit;
5147
5148 if (o_drv_lockid == n_drv_lockid) {
5149 qla83xx_wait_logic();
5150 goto retry_lockid;
5151 } else
5152 return QLA_SUCCESS;
5153
5154exit:
5155 return rval;
5156}
5157
5158void
5159qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5160{
5161 uint16_t options = (requester_id << 15) | BIT_6;
5162 uint32_t data;
6c315553 5163 uint32_t lock_owner;
7d613ac6
SV		 5164 struct qla_hw_data *ha = base_vha->hw;
5165
5166 /* IDC-lock implementation using driver-lock/lock-id remote registers */
5167retry_lock:
5168 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
5169 == QLA_SUCCESS) {
5170 if (data) {
5171 /* Setting lock-id to our function-number */
5172 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5173 ha->portnum);
5174 } else {
6c315553
SK		 5175 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5176 &lock_owner);
7d613ac6 5177 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 5178 "Failed to acquire IDC lock, acquired by %d, "
5179 "retrying...\n", lock_owner);
7d613ac6
SV		 5180
5181 /* Retry/Perform IDC-Lock recovery */
5182 if (qla83xx_idc_lock_recovery(base_vha)
5183 == QLA_SUCCESS) {
5184 qla83xx_wait_logic();
5185 goto retry_lock;
5186 } else
5187 ql_log(ql_log_warn, base_vha, 0xb075,
5188 "IDC Lock recovery FAILED.\n");
5189 }
5190
5191 }
5192
5193 return;
5194
5195 /* XXX: IDC-lock implementation using access-control mbx */
5196retry_lock2:
5197 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5198 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
5199 "Failed to acquire IDC lock. retrying...\n");
5200 /* Retry/Perform IDC-Lock recovery */
5201 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
5202 qla83xx_wait_logic();
5203 goto retry_lock2;
5204 } else
5205 ql_log(ql_log_warn, base_vha, 0xb076,
5206 "IDC Lock recovery FAILED.\n");
5207 }
5208
5209 return;
5210}
5211
5212void
5213qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5214{
5897cb2f
BVA		 5215#if 0
5216 uint16_t options = (requester_id << 15) | BIT_7;
5217#endif
5218 uint16_t retry;
7d613ac6
SV		 5219 uint32_t data;
5220 struct qla_hw_data *ha = base_vha->hw;
5221
5222 /* IDC-unlock implementation using driver-unlock/lock-id
5223 * remote registers
5224 */
5225 retry = 0;
5226retry_unlock:
5227 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
5228 == QLA_SUCCESS) {
5229 if (data == ha->portnum) {
5230 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
5231 /* Clearing lock-id by setting 0xff */
5232 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
5233 } else if (retry < 10) {
5234 /* SV: XXX: IDC unlock retrying needed here? */
5235
5236 /* Retry for IDC-unlock */
5237 qla83xx_wait_logic();
5238 retry++;
5239 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
ee6a8773 5240 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5241 goto retry_unlock;
5242 }
5243 } else if (retry < 10) {
5244 /* Retry for IDC-unlock */
5245 qla83xx_wait_logic();
5246 retry++;
5247 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
ee6a8773 5248 "Failed to read drv-lockid, retrying=%d\n", retry);
7d613ac6
SV		 5249 goto retry_unlock;
5250 }
5251
5252 return;
5253
5897cb2f 5254#if 0
7d613ac6
SV		 5255 /* XXX: IDC-unlock implementation using access-control mbx */
5256 retry = 0;
5257retry_unlock2:
5258 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5259 if (retry < 10) {
5260 /* Retry for IDC-unlock */
5261 qla83xx_wait_logic();
5262 retry++;
5263 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
ee6a8773 5264 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5265 goto retry_unlock2;
5266 }
5267 }
5268
5269 return;
5897cb2f 5270#endif
7d613ac6
SV		 5271}
5272
5273int
5274__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5275{
5276 int rval = QLA_SUCCESS;
5277 struct qla_hw_data *ha = vha->hw;
5278 uint32_t drv_presence;
5279
5280 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5281 if (rval == QLA_SUCCESS) {
5282 drv_presence |= (1 << ha->portnum);
5283 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5284 drv_presence);
5285 }
5286
5287 return rval;
5288}
5289
5290int
5291qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5292{
5293 int rval = QLA_SUCCESS;
5294
5295 qla83xx_idc_lock(vha, 0);
5296 rval = __qla83xx_set_drv_presence(vha);
5297 qla83xx_idc_unlock(vha, 0);
5298
5299 return rval;
5300}
5301
5302int
5303__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5304{
5305 int rval = QLA_SUCCESS;
5306 struct qla_hw_data *ha = vha->hw;
5307 uint32_t drv_presence;
5308
5309 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5310 if (rval == QLA_SUCCESS) {
5311 drv_presence &= ~(1 << ha->portnum);
5312 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5313 drv_presence);
5314 }
5315
5316 return rval;
5317}
5318
5319int
5320qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5321{
5322 int rval = QLA_SUCCESS;
5323
5324 qla83xx_idc_lock(vha, 0);
5325 rval = __qla83xx_clear_drv_presence(vha);
5326 qla83xx_idc_unlock(vha, 0);
5327
5328 return rval;
5329}
5330
fa492630 5331static void
7d613ac6
SV		 5332qla83xx_need_reset_handler(scsi_qla_host_t *vha)
5333{
5334 struct qla_hw_data *ha = vha->hw;
5335 uint32_t drv_ack, drv_presence;
5336 unsigned long ack_timeout;
5337
5338 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
5339 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
5340 while (1) {
5341 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
5342 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 5343 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 5344 break;
5345
5346 if (time_after_eq(jiffies, ack_timeout)) {
5347 ql_log(ql_log_warn, vha, 0xb067,
5348 "RESET ACK TIMEOUT! drv_presence=0x%x "
5349 "drv_ack=0x%x\n", drv_presence, drv_ack);
5350 /*
5351 * The function(s) which did not ack in time are forced
5352 * to withdraw any further participation in the IDC
5353 * reset.
5354 */
5355 if (drv_ack != drv_presence)
5356 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5357 drv_ack);
5358 break;
5359 }
5360
5361 qla83xx_idc_unlock(vha, 0);
5362 msleep(1000);
5363 qla83xx_idc_lock(vha, 0);
5364 }
5365
5366 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
5367 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
5368}
5369
fa492630 5370static int
7d613ac6
SV		 5371qla83xx_device_bootstrap(scsi_qla_host_t *vha)
5372{
5373 int rval = QLA_SUCCESS;
5374 uint32_t idc_control;
5375
5376 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
5377 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
5378
5379 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
5380 __qla83xx_get_idc_control(vha, &idc_control);
5381 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
5382 __qla83xx_set_idc_control(vha, 0);
5383
5384 qla83xx_idc_unlock(vha, 0);
5385 rval = qla83xx_restart_nic_firmware(vha);
5386 qla83xx_idc_lock(vha, 0);
5387
5388 if (rval != QLA_SUCCESS) {
5389 ql_log(ql_log_fatal, vha, 0xb06a,
5390 "Failed to restart NIC f/w.\n");
5391 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
5392 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
5393 } else {
5394 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
5395 "Success in restarting nic f/w.\n");
5396 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
5397 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
5398 }
5399
5400 return rval;
5401}
5402
5403/* Assumes idc_lock always held on entry */
5404int
5405qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
5406{
5407 struct qla_hw_data *ha = base_vha->hw;
5408 int rval = QLA_SUCCESS;
5409 unsigned long dev_init_timeout;
5410 uint32_t dev_state;
5411
5412 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
5413 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
5414
5415 while (1) {
5416
5417 if (time_after_eq(jiffies, dev_init_timeout)) {
5418 ql_log(ql_log_warn, base_vha, 0xb06e,
5419 "Initialization TIMEOUT!\n");
5420 /* Init timeout. Disable further NIC Core
5421 * communication.
5422 */
5423 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5424 QLA8XXX_DEV_FAILED);
5425 ql_log(ql_log_info, base_vha, 0xb06f,
5426 "HW State: FAILED.\n");
5427 }
5428
5429 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5430 switch (dev_state) {
5431 case QLA8XXX_DEV_READY:
5432 if (ha->flags.nic_core_reset_owner)
5433 qla83xx_idc_audit(base_vha,
5434 IDC_AUDIT_COMPLETION);
5435 ha->flags.nic_core_reset_owner = 0;
5436 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
5437 "Reset_owner reset by 0x%x.\n",
5438 ha->portnum);
5439 goto exit;
5440 case QLA8XXX_DEV_COLD:
5441 if (ha->flags.nic_core_reset_owner)
5442 rval = qla83xx_device_bootstrap(base_vha);
5443 else {
5444 /* Wait for AEN to change device-state */
5445 qla83xx_idc_unlock(base_vha, 0);
5446 msleep(1000);
5447 qla83xx_idc_lock(base_vha, 0);
5448 }
5449 break;
5450 case QLA8XXX_DEV_INITIALIZING:
5451 /* Wait for AEN to change device-state */
5452 qla83xx_idc_unlock(base_vha, 0);
5453 msleep(1000);
5454 qla83xx_idc_lock(base_vha, 0);
5455 break;
5456 case QLA8XXX_DEV_NEED_RESET:
5457 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
5458 qla83xx_need_reset_handler(base_vha);
5459 else {
5460 /* Wait for AEN to change device-state */
5461 qla83xx_idc_unlock(base_vha, 0);
5462 msleep(1000);
5463 qla83xx_idc_lock(base_vha, 0);
5464 }
5465 /* reset timeout value after need reset handler */
5466 dev_init_timeout = jiffies +
5467 (ha->fcoe_dev_init_timeout * HZ);
5468 break;
5469 case QLA8XXX_DEV_NEED_QUIESCENT:
5470 /* XXX: DEBUG for now */
5471 qla83xx_idc_unlock(base_vha, 0);
5472 msleep(1000);
5473 qla83xx_idc_lock(base_vha, 0);
5474 break;
5475 case QLA8XXX_DEV_QUIESCENT:
5476 /* XXX: DEBUG for now */
5477 if (ha->flags.quiesce_owner)
5478 goto exit;
5479
5480 qla83xx_idc_unlock(base_vha, 0);
5481 msleep(1000);
5482 qla83xx_idc_lock(base_vha, 0);
5483 dev_init_timeout = jiffies +
5484 (ha->fcoe_dev_init_timeout * HZ);
5485 break;
5486 case QLA8XXX_DEV_FAILED:
5487 if (ha->flags.nic_core_reset_owner)
5488 qla83xx_idc_audit(base_vha,
5489 IDC_AUDIT_COMPLETION);
5490 ha->flags.nic_core_reset_owner = 0;
5491 __qla83xx_clear_drv_presence(base_vha);
5492 qla83xx_idc_unlock(base_vha, 0);
5493 qla8xxx_dev_failed_handler(base_vha);
5494 rval = QLA_FUNCTION_FAILED;
5495 qla83xx_idc_lock(base_vha, 0);
5496 goto exit;
5497 case QLA8XXX_BAD_VALUE:
5498 qla83xx_idc_unlock(base_vha, 0);
5499 msleep(1000);
5500 qla83xx_idc_lock(base_vha, 0);
5501 break;
5502 default:
5503 ql_log(ql_log_warn, base_vha, 0xb071,
d939be3a 5504 "Unknown Device State: %x.\n", dev_state);
7d613ac6
SV		 5505 qla83xx_idc_unlock(base_vha, 0);
5506 qla8xxx_dev_failed_handler(base_vha);
5507 rval = QLA_FUNCTION_FAILED;
5508 qla83xx_idc_lock(base_vha, 0);
5509 goto exit;
5510 }
5511 }
5512
5513exit:
5514 return rval;
5515}
5516
f3ddac19
CD		 5517void
5518qla2x00_disable_board_on_pci_error(struct work_struct *work)
5519{
5520 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
5521 board_disable);
5522 struct pci_dev *pdev = ha->pdev;
5523 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5524
726b8548
QT		 5525 /*
5526 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 5527 * where it was set first.
5528 */
5529 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5530 return;
5531
f3ddac19
CD		 5532 ql_log(ql_log_warn, base_vha, 0x015b,
5533 "Disabling adapter.\n");
5534
efdb5760
SC		 5535 if (!atomic_read(&pdev->enable_cnt)) {
5536 ql_log(ql_log_info, base_vha, 0xfffc,
5537 "PCI device disabled, no action req for PCI error=%lx\n",
5538 base_vha->pci_flags);
5539 return;
5540 }
5541
726b8548
QT		 5542 qla2x00_wait_for_sess_deletion(base_vha);
5543
f3ddac19
CD		 5544 set_bit(UNLOADING, &base_vha->dpc_flags);
5545
5546 qla2x00_delete_all_vps(ha, base_vha);
5547
5548 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5549
5550 qla2x00_dfs_remove(base_vha);
5551
5552 qla84xx_put_chip(base_vha);
5553
5554 if (base_vha->timer_active)
5555 qla2x00_stop_timer(base_vha);
5556
5557 base_vha->flags.online = 0;
5558
5559 qla2x00_destroy_deferred_work(ha);
5560
5561 /*
5562 * Do not try to stop beacon blink as it will issue a mailbox
5563 * command.
5564 */
5565 qla2x00_free_sysfs_attr(base_vha, false);
5566
5567 fc_remove_host(base_vha->host);
5568
5569 scsi_remove_host(base_vha->host);
5570
5571 base_vha->flags.init_done = 0;
5572 qla25xx_delete_queues(base_vha);
f3ddac19 5573 qla2x00_free_fcports(base_vha);
093df737 5574 qla2x00_free_irqs(base_vha);
f3ddac19
CD		 5575 qla2x00_mem_free(ha);
5576 qla82xx_md_free(base_vha);
5577 qla2x00_free_queues(ha);
5578
f3ddac19
CD		 5579 qla2x00_unmap_iobases(ha);
5580
5581 pci_release_selected_regions(ha->pdev, ha->bars);
f3ddac19
CD		 5582 pci_disable_pcie_error_reporting(pdev);
5583 pci_disable_device(pdev);
f3ddac19 5584
beb9e315
JL		 5585 /*
5586 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
5587 */
f3ddac19
CD		 5588}
5589
1da177e4
LT		 5590/**************************************************************************
5591* qla2x00_do_dpc
5592* This kernel thread is a task that is schedule by the interrupt handler
5593* to perform the background processing for interrupts.
5594*
5595* Notes:
5596* This task always run in the context of a kernel thread. It
5597* is kick-off by the driver's detect code and starts up
5598* up one per adapter. It immediately goes to sleep and waits for
5599* some fibre event. When either the interrupt handler or
5600* the timer routine detects a event it will one of the task
5601* bits then wake us up.
5602**************************************************************************/
5603static int
5604qla2x00_do_dpc(void *data)
5605{
e315cd28
AC		 5606 scsi_qla_host_t *base_vha;
5607 struct qla_hw_data *ha;
d7459527
MH		 5608 uint32_t online;
5609 struct qla_qpair *qpair;
1da177e4 5610
e315cd28
AC		 5611 ha = (struct qla_hw_data *)data;
5612 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 5613
8698a745 5614 set_user_nice(current, MIN_NICE);
1da177e4 5615
563585ec 5616 set_current_state(TASK_INTERRUPTIBLE);
39a11240 5617 while (!kthread_should_stop()) {
7c3df132
SK		 5618 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
5619 "DPC handler sleeping.\n");
1da177e4 5620
39a11240 5621 schedule();
1da177e4 5622
c142caf0
AV		 5623 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
5624 goto end_loop;
1da177e4 5625
85880801 5626 if (ha->flags.eeh_busy) {
7c3df132
SK		 5627 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
5628 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 5629 goto end_loop;
85880801
AV		 5630 }
5631
1da177e4
LT		 5632 ha->dpc_active = 1;
5633
5f28d2d7
SK		 5634 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
5635 "DPC handler waking up, dpc_flags=0x%lx.\n",
5636 base_vha->dpc_flags);
1da177e4 5637
a29b3dd7
JC		 5638 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5639 break;
5640
e315cd28 5641 qla2x00_do_work(base_vha);
0971de7f 5642
7ec0effd
AD		 5643 if (IS_P3P_TYPE(ha)) {
5644 if (IS_QLA8044(ha)) {
5645 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5646 &base_vha->dpc_flags)) {
5647 qla8044_idc_lock(ha);
5648 qla8044_wr_direct(base_vha,
5649 QLA8044_CRB_DEV_STATE_INDEX,
5650 QLA8XXX_DEV_FAILED);
5651 qla8044_idc_unlock(ha);
5652 ql_log(ql_log_info, base_vha, 0x4004,
5653 "HW State: FAILED.\n");
5654 qla8044_device_state_handler(base_vha);
5655 continue;
5656 }
5657
5658 } else {
5659 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5660 &base_vha->dpc_flags)) {
5661 qla82xx_idc_lock(ha);
5662 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5663 QLA8XXX_DEV_FAILED);
5664 qla82xx_idc_unlock(ha);
5665 ql_log(ql_log_info, base_vha, 0x0151,
5666 "HW State: FAILED.\n");
5667 qla82xx_device_state_handler(base_vha);
5668 continue;
5669 }
a9083016
GM		 5670 }
5671
5672 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
5673 &base_vha->dpc_flags)) {
5674
7c3df132
SK		 5675 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
5676 "FCoE context reset scheduled.\n");
a9083016
GM		 5677 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
5678 &base_vha->dpc_flags))) {
5679 if (qla82xx_fcoe_ctx_reset(base_vha)) {
5680 /* FCoE-ctx reset failed.
5681 * Escalate to chip-reset
5682 */
5683 set_bit(ISP_ABORT_NEEDED,
5684 &base_vha->dpc_flags);
5685 }
5686 clear_bit(ABORT_ISP_ACTIVE,
5687 &base_vha->dpc_flags);
5688 }
5689
7c3df132
SK		 5690 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
5691 "FCoE context reset end.\n");
a9083016 5692 }
8ae6d9c7
GM		 5693 } else if (IS_QLAFX00(ha)) {
5694 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5695 &base_vha->dpc_flags)) {
5696 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
5697 "Firmware Reset Recovery\n");
5698 if (qlafx00_reset_initialize(base_vha)) {
5699 /* Failed. Abort isp later. */
5700 if (!test_bit(UNLOADING,
f92f82d6 5701 &base_vha->dpc_flags)) {
8ae6d9c7
GM		 5702 set_bit(ISP_UNRECOVERABLE,
5703 &base_vha->dpc_flags);
5704 ql_dbg(ql_dbg_dpc, base_vha,
5705 0x4021,
5706 "Reset Recovery Failed\n");
f92f82d6 5707 }
8ae6d9c7
GM		 5708 }
5709 }
5710
5711 if (test_and_clear_bit(FX00_TARGET_SCAN,
5712 &base_vha->dpc_flags)) {
5713 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
5714 "ISPFx00 Target Scan scheduled\n");
5715 if (qlafx00_rescan_isp(base_vha)) {
5716 if (!test_bit(UNLOADING,
5717 &base_vha->dpc_flags))
5718 set_bit(ISP_UNRECOVERABLE,
5719 &base_vha->dpc_flags);
5720 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
5721 "ISPFx00 Target Scan Failed\n");
5722 }
5723 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
5724 "ISPFx00 Target Scan End\n");
5725 }
e8f5e95d
AB		 5726 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
5727 &base_vha->dpc_flags)) {
5728 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
5729 "ISPFx00 Host Info resend scheduled\n");
5730 qlafx00_fx_disc(base_vha,
5731 &base_vha->hw->mr.fcport,
5732 FXDISC_REG_HOST_INFO);
5733 }
a9083016
GM		 5734 }
5735
e4e3a2ce
QT		 5736 if (test_and_clear_bit(DETECT_SFP_CHANGE,
5737 &base_vha->dpc_flags) &&
5738 !test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) {
5739 qla24xx_detect_sfp(base_vha);
5740
5741 if (ha->flags.detected_lr_sfp !=
5742 ha->flags.using_lr_setting)
5743 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
5744 }
5745
e315cd28
AC		 5746 if (test_and_clear_bit(ISP_ABORT_NEEDED,
5747 &base_vha->dpc_flags)) {
1da177e4 5748
7c3df132
SK		 5749 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
5750 "ISP abort scheduled.\n");
1da177e4 5751 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 5752 &base_vha->dpc_flags))) {
1da177e4 5753
a9083016 5754 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 5755 /* failed. retry later */
5756 set_bit(ISP_ABORT_NEEDED,
e315cd28 5757 &base_vha->dpc_flags);
99363ef8 5758 }
e315cd28
AC		 5759 clear_bit(ABORT_ISP_ACTIVE,
5760 &base_vha->dpc_flags);
99363ef8
SJ		 5761 }
5762
7c3df132
SK		 5763 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
5764 "ISP abort end.\n");
1da177e4
LT		 5765 }
5766
a394aac8
DJ		 5767 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
5768 &base_vha->dpc_flags)) {
e315cd28 5769 qla2x00_update_fcports(base_vha);
c9c5ced9 5770 }
d97994dc 5771
8ae6d9c7
GM		 5772 if (IS_QLAFX00(ha))
5773 goto loop_resync_check;
5774
579d12b5 5775 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 5776 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
5777 "Quiescence mode scheduled.\n");
7ec0effd
AD		 5778 if (IS_P3P_TYPE(ha)) {
5779 if (IS_QLA82XX(ha))
5780 qla82xx_device_state_handler(base_vha);
5781 if (IS_QLA8044(ha))
5782 qla8044_device_state_handler(base_vha);
8fcd6b8b
CD		 5783 clear_bit(ISP_QUIESCE_NEEDED,
5784 &base_vha->dpc_flags);
5785 if (!ha->flags.quiesce_owner) {
5786 qla2x00_perform_loop_resync(base_vha);
7ec0effd
AD		 5787 if (IS_QLA82XX(ha)) {
5788 qla82xx_idc_lock(ha);
5789 qla82xx_clear_qsnt_ready(
5790 base_vha);
5791 qla82xx_idc_unlock(ha);
5792 } else if (IS_QLA8044(ha)) {
5793 qla8044_idc_lock(ha);
5794 qla8044_clear_qsnt_ready(
5795 base_vha);
5796 qla8044_idc_unlock(ha);
5797 }
8fcd6b8b
CD		 5798 }
5799 } else {
5800 clear_bit(ISP_QUIESCE_NEEDED,
5801 &base_vha->dpc_flags);
5802 qla2x00_quiesce_io(base_vha);
579d12b5 5803 }
7c3df132
SK		 5804 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
5805 "Quiescence mode end.\n");
579d12b5
SK		 5806 }
5807
e315cd28 5808 if (test_and_clear_bit(RESET_MARKER_NEEDED,
8ae6d9c7 5809 &base_vha->dpc_flags) &&
e315cd28 5810 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 5811
7c3df132
SK		 5812 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
5813 "Reset marker scheduled.\n");
e315cd28
AC		 5814 qla2x00_rst_aen(base_vha);
5815 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 5816 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
5817 "Reset marker end.\n");
1da177e4
LT		 5818 }
5819
5820 /* Retry each device up to login retry count */
e315cd28
AC		 5821 if ((test_and_clear_bit(RELOGIN_NEEDED,
5822 &base_vha->dpc_flags)) &&
5823 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
5824 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 5825
7c3df132
SK		 5826 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
5827 "Relogin scheduled.\n");
e315cd28 5828 qla2x00_relogin(base_vha);
7c3df132
SK		 5829 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
5830 "Relogin end.\n");
1da177e4 5831 }
8ae6d9c7 5832loop_resync_check:
e315cd28 5833 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
8ae6d9c7 5834 &base_vha->dpc_flags)) {
1da177e4 5835
7c3df132
SK		 5836 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
5837 "Loop resync scheduled.\n");
1da177e4
LT		 5838
5839 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 5840 &base_vha->dpc_flags))) {
1da177e4 5841
52c82823 5842 qla2x00_loop_resync(base_vha);
1da177e4 5843
e315cd28
AC		 5844 clear_bit(LOOP_RESYNC_ACTIVE,
5845 &base_vha->dpc_flags);
1da177e4
LT		 5846 }
5847
7c3df132
SK		 5848 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
5849 "Loop resync end.\n");
1da177e4
LT		 5850 }
5851
8ae6d9c7
GM		 5852 if (IS_QLAFX00(ha))
5853 goto intr_on_check;
5854
e315cd28
AC		 5855 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
5856 atomic_read(&base_vha->loop_state) == LOOP_READY) {
5857 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
5858 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 5859 }
5860
8ae6d9c7 5861intr_on_check:
1da177e4 5862 if (!ha->interrupts_on)
fd34f556 5863 ha->isp_ops->enable_intrs(ha);
1da177e4 5864
e315cd28 5865 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
90b604f2
HM		 5866 &base_vha->dpc_flags)) {
5867 if (ha->beacon_blink_led == 1)
5868 ha->isp_ops->beacon_blink(base_vha);
5869 }
f6df144c 5870
d7459527
MH		 5871 /* qpair online check */
5872 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED,
5873 &base_vha->dpc_flags)) {
5874 if (ha->flags.eeh_busy ||
5875 ha->flags.pci_channel_io_perm_failure)
5876 online = 0;
5877 else
5878 online = 1;
5879
5880 mutex_lock(&ha->mq_lock);
5881 list_for_each_entry(qpair, &base_vha->qp_list,
5882 qp_list_elem)
5883 qpair->online = online;
5884 mutex_unlock(&ha->mq_lock);
5885 }
5886
deeae7a6
DG		 5887 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED, &base_vha->dpc_flags)) {
5888 ql_log(ql_log_info, base_vha, 0xffffff,
5889 "nvme: SET ZIO Activity exchange threshold to %d.\n",
5890 ha->nvme_last_rptd_aen);
5891 if (qla27xx_set_zio_threshold(base_vha, ha->nvme_last_rptd_aen)) {
5892 ql_log(ql_log_info, base_vha, 0xffffff,
5893 "nvme: Unable to SET ZIO Activity exchange threshold to %d.\n",
5894 ha->nvme_last_rptd_aen);
5895 }
5896 }
5897
8ae6d9c7
GM		 5898 if (!IS_QLAFX00(ha))
5899 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 5900
1da177e4 5901 ha->dpc_active = 0;
c142caf0 5902end_loop:
563585ec 5903 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 5904 } /* End of while(1) */
563585ec 5905 __set_current_state(TASK_RUNNING);
1da177e4 5906
7c3df132
SK		 5907 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
5908 "DPC handler exiting.\n");
1da177e4
LT		 5909
5910 /*
5911 * Make sure that nobody tries to wake us up again.
5912 */
1da177e4
LT		 5913 ha->dpc_active = 0;
5914
ac280b67
AV		 5915 /* Cleanup any residual CTX SRBs. */
5916 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5917
39a11240
CH		 5918 return 0;
5919}
5920
5921void
e315cd28 5922qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 5923{
e315cd28 5924 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 5925 struct task_struct *t = ha->dpc_thread;
5926
e315cd28 5927 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 5928 wake_up_process(t);
1da177e4
LT		 5929}
5930
1da177e4
LT		 5931/*
5932* qla2x00_rst_aen
5933* Processes asynchronous reset.
5934*
5935* Input:
5936* ha = adapter block pointer.
5937*/
5938static void
e315cd28 5939qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 5940{
e315cd28
AC		 5941 if (vha->flags.online && !vha->flags.reset_active &&
5942 !atomic_read(&vha->loop_down_timer) &&
5943 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 5944 do {
e315cd28 5945 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 5946
5947 /*
5948 * Issue marker command only when we are going to start
5949 * the I/O.
5950 */
e315cd28
AC		 5951 vha->marker_needed = 1;
5952 } while (!atomic_read(&vha->loop_down_timer) &&
5953 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 5954 }
5955}
5956
1da177e4
LT		 5957/**************************************************************************
5958* qla2x00_timer
5959*
5960* Description:
5961* One second timer
5962*
5963* Context: Interrupt
5964***************************************************************************/
2c3dfe3f 5965void
e315cd28 5966qla2x00_timer(scsi_qla_host_t *vha)
1da177e4 5967{
1da177e4 5968 unsigned long cpu_flags = 0;
1da177e4
LT		 5969 int start_dpc = 0;
5970 int index;
5971 srb_t *sp;
85880801 5972 uint16_t w;
e315cd28 5973 struct qla_hw_data *ha = vha->hw;
73208dfd 5974 struct req_que *req;
85880801 5975
a5b36321 5976 if (ha->flags.eeh_busy) {
7c3df132
SK		 5977 ql_dbg(ql_dbg_timer, vha, 0x6000,
5978 "EEH = %d, restarting timer.\n",
5979 ha->flags.eeh_busy);
a5b36321
LC		 5980 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5981 return;
5982 }
5983
f3ddac19
CD		 5984 /*
5985 * Hardware read to raise pending EEH errors during mailbox waits. If
5986 * the read returns -1 then disable the board.
5987 */
5988 if (!pci_channel_offline(ha->pdev)) {
85880801 5989 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
c821e0d5 5990 qla2x00_check_reg16_for_disconnect(vha, w);
f3ddac19 5991 }
1da177e4 5992
cefcaba6 5993 /* Make sure qla82xx_watchdog is run only for physical port */
7ec0effd 5994 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
579d12b5
SK		 5995 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
5996 start_dpc++;
7ec0effd
AD		 5997 if (IS_QLA82XX(ha))
5998 qla82xx_watchdog(vha);
5999 else if (IS_QLA8044(ha))
6000 qla8044_watchdog(vha);
579d12b5
SK		 6001 }
6002
8ae6d9c7
GM		 6003 if (!vha->vp_idx && IS_QLAFX00(ha))
6004 qlafx00_timer_routine(vha);
6005
1da177e4 6006 /* Loop down handler. */
e315cd28 6007 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 6008 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
6009 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 6010 && vha->flags.online) {
1da177e4 6011
e315cd28
AC		 6012 if (atomic_read(&vha->loop_down_timer) ==
6013 vha->loop_down_abort_time) {
1da177e4 6014
7c3df132
SK		 6015 ql_log(ql_log_info, vha, 0x6008,
6016 "Loop down - aborting the queues before time expires.\n");
1da177e4 6017
e315cd28
AC		 6018 if (!IS_QLA2100(ha) && vha->link_down_timeout)
6019 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 6020
f08b7251
AV		 6021 /*
6022 * Schedule an ISP abort to return any FCP2-device
6023 * commands.
6024 */
2c3dfe3f 6025 /* NPIV - scan physical port only */
e315cd28 6026 if (!vha->vp_idx) {
2c3dfe3f
SJ		 6027 spin_lock_irqsave(&ha->hardware_lock,
6028 cpu_flags);
73208dfd 6029 req = ha->req_q_map[0];
2c3dfe3f 6030 for (index = 1;
8d93f550 6031 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 6032 index++) {
6033 fc_port_t *sfcp;
6034
e315cd28 6035 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 6036 if (!sp)
6037 continue;
c5419e26
QT		 6038 if (sp->cmd_type != TYPE_SRB)
6039 continue;
9ba56b95 6040 if (sp->type != SRB_SCSI_CMD)
cf53b069 6041 continue;
2c3dfe3f 6042 sfcp = sp->fcport;
f08b7251 6043 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 6044 continue;
bdf79621 6045
8f7daead
GM		 6046 if (IS_QLA82XX(ha))
6047 set_bit(FCOE_CTX_RESET_NEEDED,
6048 &vha->dpc_flags);
6049 else
6050 set_bit(ISP_ABORT_NEEDED,
e315cd28 6051 &vha->dpc_flags);
2c3dfe3f
SJ		 6052 break;
6053 }
6054 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 6055 cpu_flags);
1da177e4 6056 }
1da177e4
LT		 6057 start_dpc++;
6058 }
6059
6060 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 6061 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 6062 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 6063 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 6064 "Loop down - aborting ISP.\n");
6065
8f7daead
GM		 6066 if (IS_QLA82XX(ha))
6067 set_bit(FCOE_CTX_RESET_NEEDED,
6068 &vha->dpc_flags);
6069 else
6070 set_bit(ISP_ABORT_NEEDED,
6071 &vha->dpc_flags);
1da177e4
LT		 6072 }
6073 }
7c3df132
SK		 6074 ql_dbg(ql_dbg_timer, vha, 0x600a,
6075 "Loop down - seconds remaining %d.\n",
6076 atomic_read(&vha->loop_down_timer));
1da177e4 6077 }
cefcaba6
SK		 6078 /* Check if beacon LED needs to be blinked for physical host only */
6079 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc 6080 /* There is no beacon_blink function for ISP82xx */
7ec0effd 6081 if (!IS_P3P_TYPE(ha)) {
999916dc
SK		 6082 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
6083 start_dpc++;
6084 }
f6df144c
AV		 6085 }
6086
550bf57d 6087 /* Process any deferred work. */
e315cd28 6088 if (!list_empty(&vha->work_list))
550bf57d
AV		 6089 start_dpc++;
6090
7401bc18
DG		 6091 /*
6092 * FC-NVME
6093 * see if the active AEN count has changed from what was last reported.
6094 */
deeae7a6
DG		 6095 if (!vha->vp_idx &&
6096 atomic_read(&ha->nvme_active_aen_cnt) != ha->nvme_last_rptd_aen &&
6097 ha->zio_mode == QLA_ZIO_MODE_6) {
7401bc18 6098 ql_log(ql_log_info, vha, 0x3002,
deeae7a6
DG		 6099 "nvme: Sched: Set ZIO exchange threshold to %d.\n",
6100 ha->nvme_last_rptd_aen);
6101 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt);
6102 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
6103 start_dpc++;
7401bc18
DG		 6104 }
6105
1da177e4 6106 /* Schedule the DPC routine if needed */
e315cd28
AC		 6107 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
6108 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
6109 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 6110 start_dpc ||
e315cd28
AC		 6111 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
6112 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 6113 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
6114 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 6115 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
50280c01 6116 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
7c3df132
SK		 6117 ql_dbg(ql_dbg_timer, vha, 0x600b,
6118 "isp_abort_needed=%d loop_resync_needed=%d "
6119 "fcport_update_needed=%d start_dpc=%d "
6120 "reset_marker_needed=%d",
6121 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
6122 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
6123 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
6124 start_dpc,
6125 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
6126 ql_dbg(ql_dbg_timer, vha, 0x600c,
6127 "beacon_blink_needed=%d isp_unrecoverable=%d "
6128 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
50280c01 6129 "relogin_needed=%d.\n",
7c3df132
SK		 6130 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
6131 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
6132 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
6133 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
50280c01 6134 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 6135 qla2xxx_wake_dpc(vha);
7c3df132 6136 }
1da177e4 6137
e315cd28 6138 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 6139}
6140
5433383e
AV		 6141/* Firmware interface routines. */
6142
f73cb695 6143#define FW_BLOBS 11
5433383e
AV		 6144#define FW_ISP21XX 0
6145#define FW_ISP22XX 1
6146#define FW_ISP2300 2
6147#define FW_ISP2322 3
48c02fde 6148#define FW_ISP24XX 4
c3a2f0df 6149#define FW_ISP25XX 5
3a03eb79 6150#define FW_ISP81XX 6
a9083016 6151#define FW_ISP82XX 7
6246b8a1
GM		 6152#define FW_ISP2031 8
6153#define FW_ISP8031 9
2c5bbbb2 6154#define FW_ISP27XX 10
5433383e 6155
bb8ee499
AV		 6156#define FW_FILE_ISP21XX "ql2100_fw.bin"
6157#define FW_FILE_ISP22XX "ql2200_fw.bin"
6158#define FW_FILE_ISP2300 "ql2300_fw.bin"
6159#define FW_FILE_ISP2322 "ql2322_fw.bin"
6160#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 6161#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 6162#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 6163#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 6164#define FW_FILE_ISP2031 "ql2600_fw.bin"
6165#define FW_FILE_ISP8031 "ql8300_fw.bin"
2c5bbbb2 6166#define FW_FILE_ISP27XX "ql2700_fw.bin"
f73cb695 6167
bb8ee499 6168
e1e82b6f 6169static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 6170
6171static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 6172 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
6173 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
6174 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
6175 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
6176 { .name = FW_FILE_ISP24XX, },
c3a2f0df 6177 { .name = FW_FILE_ISP25XX, },
3a03eb79 6178 { .name = FW_FILE_ISP81XX, },
a9083016 6179 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 6180 { .name = FW_FILE_ISP2031, },
6181 { .name = FW_FILE_ISP8031, },
2c5bbbb2 6182 { .name = FW_FILE_ISP27XX, },
5433383e
AV		 6183};
6184
6185struct fw_blob *
e315cd28 6186qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 6187{
e315cd28 6188 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 6189 struct fw_blob *blob;
6190
5433383e
AV		 6191 if (IS_QLA2100(ha)) {
6192 blob = &qla_fw_blobs[FW_ISP21XX];
6193 } else if (IS_QLA2200(ha)) {
6194 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 6195 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 6196 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 6197 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 6198 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 6199 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 6200 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 6201 } else if (IS_QLA25XX(ha)) {
6202 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 6203 } else if (IS_QLA81XX(ha)) {
6204 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 6205 } else if (IS_QLA82XX(ha)) {
6206 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 6207 } else if (IS_QLA2031(ha)) {
6208 blob = &qla_fw_blobs[FW_ISP2031];
6209 } else if (IS_QLA8031(ha)) {
6210 blob = &qla_fw_blobs[FW_ISP8031];
2c5bbbb2
JC		 6211 } else if (IS_QLA27XX(ha)) {
6212 blob = &qla_fw_blobs[FW_ISP27XX];
8a655229
DC		 6213 } else {
6214 return NULL;
5433383e
AV		 6215 }
6216
e1e82b6f 6217 mutex_lock(&qla_fw_lock);
5433383e
AV		 6218 if (blob->fw)
6219 goto out;
6220
6221 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 6222 ql_log(ql_log_warn, vha, 0x0063,
6223 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 6224 blob->fw = NULL;
6225 blob = NULL;
6226 goto out;
6227 }
6228
6229out:
e1e82b6f 6230 mutex_unlock(&qla_fw_lock);
5433383e
AV		 6231 return blob;
6232}
6233
6234static void
6235qla2x00_release_firmware(void)
6236{
6237 int idx;
6238
e1e82b6f 6239 mutex_lock(&qla_fw_lock);
5433383e 6240 for (idx = 0; idx < FW_BLOBS; idx++)
cf92549f 6241 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 6242 mutex_unlock(&qla_fw_lock);
5433383e
AV		 6243}
6244
14e660e6
SJ		 6245static pci_ers_result_t
6246qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
6247{
85880801
AV		 6248 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
6249 struct qla_hw_data *ha = vha->hw;
6250
7c3df132
SK		 6251 ql_dbg(ql_dbg_aer, vha, 0x9000,
6252 "PCI error detected, state %x.\n", state);
b9b12f73 6253
efdb5760
SC		 6254 if (!atomic_read(&pdev->enable_cnt)) {
6255 ql_log(ql_log_info, vha, 0xffff,
6256 "PCI device is disabled,state %x\n", state);
6257 return PCI_ERS_RESULT_NEED_RESET;
6258 }
6259
14e660e6
SJ		 6260 switch (state) {
6261 case pci_channel_io_normal:
85880801 6262 ha->flags.eeh_busy = 0;
d7459527
MH		 6263 if (ql2xmqsupport) {
6264 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6265 qla2xxx_wake_dpc(vha);
6266 }
14e660e6
SJ		 6267 return PCI_ERS_RESULT_CAN_RECOVER;
6268 case pci_channel_io_frozen:
85880801 6269 ha->flags.eeh_busy = 1;
a5b36321
LC		 6270 /* For ISP82XX complete any pending mailbox cmd */
6271 if (IS_QLA82XX(ha)) {
7190575f 6272 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 6273 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
6274 qla82xx_clear_pending_mbx(vha);
a5b36321 6275 }
90a86fc0 6276 qla2x00_free_irqs(vha);
14e660e6 6277 pci_disable_device(pdev);
bddd2d65
LC		 6278 /* Return back all IOs */
6279 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
d7459527
MH		 6280 if (ql2xmqsupport) {
6281 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6282 qla2xxx_wake_dpc(vha);
6283 }
14e660e6
SJ		 6284 return PCI_ERS_RESULT_NEED_RESET;
6285 case pci_channel_io_perm_failure:
85880801
AV		 6286 ha->flags.pci_channel_io_perm_failure = 1;
6287 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
d7459527
MH		 6288 if (ql2xmqsupport) {
6289 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6290 qla2xxx_wake_dpc(vha);
6291 }
14e660e6
SJ		 6292 return PCI_ERS_RESULT_DISCONNECT;
6293 }
6294 return PCI_ERS_RESULT_NEED_RESET;
6295}
6296
6297static pci_ers_result_t
6298qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
6299{
6300 int risc_paused = 0;
6301 uint32_t stat;
6302 unsigned long flags;
e315cd28
AC		 6303 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6304 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 6305 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
6306 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
6307
bcc5b6d3
SK		 6308 if (IS_QLA82XX(ha))
6309 return PCI_ERS_RESULT_RECOVERED;
6310
14e660e6
SJ		 6311 spin_lock_irqsave(&ha->hardware_lock, flags);
6312 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
6313 stat = RD_REG_DWORD(&reg->hccr);
6314 if (stat & HCCR_RISC_PAUSE)
6315 risc_paused = 1;
6316 } else if (IS_QLA23XX(ha)) {
6317 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
6318 if (stat & HSR_RISC_PAUSED)
6319 risc_paused = 1;
6320 } else if (IS_FWI2_CAPABLE(ha)) {
6321 stat = RD_REG_DWORD(&reg24->host_status);
6322 if (stat & HSRX_RISC_PAUSED)
6323 risc_paused = 1;
6324 }
6325 spin_unlock_irqrestore(&ha->hardware_lock, flags);
6326
6327 if (risc_paused) {
7c3df132
SK		 6328 ql_log(ql_log_info, base_vha, 0x9003,
6329 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 6330 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 6331
6332 return PCI_ERS_RESULT_NEED_RESET;
6333 } else
6334 return PCI_ERS_RESULT_RECOVERED;
6335}
6336
fa492630
SK		 6337static uint32_t
6338qla82xx_error_recovery(scsi_qla_host_t *base_vha)
a5b36321
LC		 6339{
6340 uint32_t rval = QLA_FUNCTION_FAILED;
6341 uint32_t drv_active = 0;
6342 struct qla_hw_data *ha = base_vha->hw;
6343 int fn;
6344 struct pci_dev *other_pdev = NULL;
6345
7c3df132
SK		 6346 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
6347 "Entered %s.\n", __func__);
a5b36321
LC		 6348
6349 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6350
6351 if (base_vha->flags.online) {
6352 /* Abort all outstanding commands,
6353 * so as to be requeued later */
6354 qla2x00_abort_isp_cleanup(base_vha);
6355 }
6356
6357
6358 fn = PCI_FUNC(ha->pdev->devfn);
6359 while (fn > 0) {
6360 fn--;
7c3df132
SK		 6361 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
6362 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 6363 other_pdev =
6364 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
6365 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
6366 fn));
6367
6368 if (!other_pdev)
6369 continue;
6370 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 6371 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
6372 "Found PCI func available and enable at 0x%x.\n",
6373 fn);
a5b36321
LC		 6374 pci_dev_put(other_pdev);
6375 break;
6376 }
6377 pci_dev_put(other_pdev);
6378 }
6379
6380 if (!fn) {
6381 /* Reset owner */
7c3df132
SK		 6382 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
6383 "This devfn is reset owner = 0x%x.\n",
6384 ha->pdev->devfn);
a5b36321
LC		 6385 qla82xx_idc_lock(ha);
6386
6387 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6388 QLA8XXX_DEV_INITIALIZING);
a5b36321
LC		 6389
6390 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
6391 QLA82XX_IDC_VERSION);
6392
6393 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 6394 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
6395 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 6396
6397 qla82xx_idc_unlock(ha);
6398 /* Reset if device is not already reset
6399 * drv_active would be 0 if a reset has already been done
6400 */
6401 if (drv_active)
6402 rval = qla82xx_start_firmware(base_vha);
6403 else
6404 rval = QLA_SUCCESS;
6405 qla82xx_idc_lock(ha);
6406
6407 if (rval != QLA_SUCCESS) {
7c3df132
SK		 6408 ql_log(ql_log_info, base_vha, 0x900b,
6409 "HW State: FAILED.\n");
a5b36321
LC		 6410 qla82xx_clear_drv_active(ha);
6411 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6412 QLA8XXX_DEV_FAILED);
a5b36321 6413 } else {
7c3df132
SK		 6414 ql_log(ql_log_info, base_vha, 0x900c,
6415 "HW State: READY.\n");
a5b36321 6416 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6417 QLA8XXX_DEV_READY);
a5b36321 6418 qla82xx_idc_unlock(ha);
7190575f 6419 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 6420 rval = qla82xx_restart_isp(base_vha);
6421 qla82xx_idc_lock(ha);
6422 /* Clear driver state register */
6423 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
6424 qla82xx_set_drv_active(base_vha);
6425 }
6426 qla82xx_idc_unlock(ha);
6427 } else {
7c3df132
SK		 6428 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
6429 "This devfn is not reset owner = 0x%x.\n",
6430 ha->pdev->devfn);
a5b36321 6431 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
7d613ac6 6432 QLA8XXX_DEV_READY)) {
7190575f 6433 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 6434 rval = qla82xx_restart_isp(base_vha);
6435 qla82xx_idc_lock(ha);
6436 qla82xx_set_drv_active(base_vha);
6437 qla82xx_idc_unlock(ha);
6438 }
6439 }
6440 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6441
6442 return rval;
6443}
6444
14e660e6
SJ		 6445static pci_ers_result_t
6446qla2xxx_pci_slot_reset(struct pci_dev *pdev)
6447{
6448 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 6449 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6450 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 6451 struct rsp_que *rsp;
6452 int rc, retries = 10;
09483916 6453
7c3df132
SK		 6454 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
6455 "Slot Reset.\n");
85880801 6456
90a86fc0
JC		 6457 /* Workaround: qla2xxx driver which access hardware earlier
6458 * needs error state to be pci_channel_io_online.
6459 * Otherwise mailbox command timesout.
6460 */
6461 pdev->error_state = pci_channel_io_normal;
6462
6463 pci_restore_state(pdev);
6464
8c1496bd
RL		 6465 /* pci_restore_state() clears the saved_state flag of the device
6466 * save restored state which resets saved_state flag
6467 */
6468 pci_save_state(pdev);
6469
09483916
BH		 6470 if (ha->mem_only)
6471 rc = pci_enable_device_mem(pdev);
6472 else
6473 rc = pci_enable_device(pdev);
14e660e6 6474
09483916 6475 if (rc) {
7c3df132 6476 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 6477 "Can't re-enable PCI device after reset.\n");
a5b36321 6478 goto exit_slot_reset;
14e660e6 6479 }
14e660e6 6480
90a86fc0
JC		 6481 rsp = ha->rsp_q_map[0];
6482 if (qla2x00_request_irqs(ha, rsp))
a5b36321 6483 goto exit_slot_reset;
90a86fc0 6484
e315cd28 6485 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 6486 goto exit_slot_reset;
6487
6488 if (IS_QLA82XX(ha)) {
6489 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
6490 ret = PCI_ERS_RESULT_RECOVERED;
6491 goto exit_slot_reset;
6492 } else
6493 goto exit_slot_reset;
6494 }
14e660e6 6495
90a86fc0
JC		 6496 while (ha->flags.mbox_busy && retries--)
6497 msleep(1000);
85880801 6498
e315cd28 6499 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 6500 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 6501 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 6502 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 6503
90a86fc0 6504
a5b36321 6505exit_slot_reset:
7c3df132
SK		 6506 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
6507 "slot_reset return %x.\n", ret);
85880801 6508
14e660e6
SJ		 6509 return ret;
6510}
6511
6512static void
6513qla2xxx_pci_resume(struct pci_dev *pdev)
6514{
e315cd28
AC		 6515 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6516 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 6517 int ret;
6518
7c3df132
SK		 6519 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
6520 "pci_resume.\n");
85880801 6521
e315cd28 6522 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 6523 if (ret != QLA_SUCCESS) {
7c3df132
SK		 6524 ql_log(ql_log_fatal, base_vha, 0x9002,
6525 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 6526 }
85880801 6527
3e46f031
LC		 6528 pci_cleanup_aer_uncorrect_error_status(pdev);
6529
85880801 6530 ha->flags.eeh_busy = 0;
14e660e6
SJ		 6531}
6532
2d5a4c34
HM		 6533static void
6534qla83xx_disable_laser(scsi_qla_host_t *vha)
6535{
6536 uint32_t reg, data, fn;
6537 struct qla_hw_data *ha = vha->hw;
6538 struct device_reg_24xx __iomem *isp_reg = &ha->iobase->isp24;
6539
6540 /* pci func #/port # */
6541 ql_dbg(ql_dbg_init, vha, 0x004b,
6542 "Disabling Laser for hba: %p\n", vha);
6543
6544 fn = (RD_REG_DWORD(&isp_reg->ctrl_status) &
6545 (BIT_15|BIT_14|BIT_13|BIT_12));
6546
6547 fn = (fn >> 12);
6548
6549 if (fn & 1)
6550 reg = PORT_1_2031;
6551 else
6552 reg = PORT_0_2031;
6553
6554 data = LASER_OFF_2031;
6555
6556 qla83xx_wr_reg(vha, reg, data);
6557}
6558
5601236b
MH		 6559static int qla2xxx_map_queues(struct Scsi_Host *shost)
6560{
6561 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata;
6562
6563 return blk_mq_pci_map_queues(&shost->tag_set, vha->hw->pdev);
6564}
6565
a55b2d21 6566static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 6567 .error_detected = qla2xxx_pci_error_detected,
6568 .mmio_enabled = qla2xxx_pci_mmio_enabled,
6569 .slot_reset = qla2xxx_pci_slot_reset,
6570 .resume = qla2xxx_pci_resume,
6571};
6572
5433383e 6573static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 6574 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
6575 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
6576 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
6577 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
6578 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
6579 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
6580 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
6581 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
6582 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 6583 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 6584 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
6585 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 6586 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 6587 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 6588 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 6589 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 6590 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8ae6d9c7 6591 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7ec0effd 6592 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
f73cb695 6593 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
2c5bbbb2 6594 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
2b48992f 6595 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
5433383e
AV		 6596 { 0 },
6597};
6598MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
6599
fca29703 6600static struct pci_driver qla2xxx_pci_driver = {
cb63067a 6601 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 6602 .driver = {
6603 .owner = THIS_MODULE,
6604 },
fca29703 6605 .id_table = qla2xxx_pci_tbl,
7ee61397 6606 .probe = qla2x00_probe_one,
4c993f76 6607 .remove = qla2x00_remove_one,
e30d1756 6608 .shutdown = qla2x00_shutdown,
14e660e6 6609 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 6610};
6611
75ef9de1 6612static const struct file_operations apidev_fops = {
6a03b4cd 6613 .owner = THIS_MODULE,
6038f373 6614 .llseek = noop_llseek,
6a03b4cd
HZ		 6615};
6616
1da177e4
LT		 6617/**
6618 * qla2x00_module_init - Module initialization.
6619 **/
6620static int __init
6621qla2x00_module_init(void)
6622{
fca29703
AV		 6623 int ret = 0;
6624
1da177e4 6625 /* Allocate cache for SRBs. */
354d6b21 6626 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 6627 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 6628 if (srb_cachep == NULL) {
7c3df132
SK		 6629 ql_log(ql_log_fatal, NULL, 0x0001,
6630 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 6631 return -ENOMEM;
6632 }
6633
2d70c103
NB		 6634 /* Initialize target kmem_cache and mem_pools */
6635 ret = qlt_init();
6636 if (ret < 0) {
6637 kmem_cache_destroy(srb_cachep);
6638 return ret;
6639 } else if (ret > 0) {
6640 /*
6641 * If initiator mode is explictly disabled by qlt_init(),
6642 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
6643 * performing scsi_scan_target() during LOOP UP event.
6644 */
6645 qla2xxx_transport_functions.disable_target_scan = 1;
6646 qla2xxx_transport_vport_functions.disable_target_scan = 1;
6647 }
6648
1da177e4
LT		 6649 /* Derive version string. */
6650 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 6651 if (ql2xextended_error_logging)
0181944f 6652 strcat(qla2x00_version_str, "-debug");
fed0f68a
JC		 6653 if (ql2xextended_error_logging == 1)
6654 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
0181944f 6655
1c97a12a
AV		 6656 qla2xxx_transport_template =
6657 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 6658 if (!qla2xxx_transport_template) {
6659 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 6660 ql_log(ql_log_fatal, NULL, 0x0002,
6661 "fc_attach_transport failed...Failing load!.\n");
2d70c103 6662 qlt_exit();
1da177e4 6663 return -ENODEV;
2c3dfe3f 6664 }
6a03b4cd
HZ		 6665
6666 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
6667 if (apidev_major < 0) {
7c3df132
SK		 6668 ql_log(ql_log_fatal, NULL, 0x0003,
6669 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 6670 }
6671
2c3dfe3f
SJ		 6672 qla2xxx_transport_vport_template =
6673 fc_attach_transport(&qla2xxx_transport_vport_functions);
6674 if (!qla2xxx_transport_vport_template) {
6675 kmem_cache_destroy(srb_cachep);
2d70c103 6676 qlt_exit();
2c3dfe3f 6677 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 6678 ql_log(ql_log_fatal, NULL, 0x0004,
6679 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 6680 return -ENODEV;
2c3dfe3f 6681 }
7c3df132
SK		 6682 ql_log(ql_log_info, NULL, 0x0005,
6683 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 6684 qla2x00_version_str);
7ee61397 6685 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 6686 if (ret) {
6687 kmem_cache_destroy(srb_cachep);
2d70c103 6688 qlt_exit();
fca29703 6689 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 6690 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 6691 ql_log(ql_log_fatal, NULL, 0x0006,
6692 "pci_register_driver failed...ret=%d Failing load!.\n",
6693 ret);
fca29703
AV		 6694 }
6695 return ret;
1da177e4
LT		 6696}
6697
6698/**
6699 * qla2x00_module_exit - Module cleanup.
6700 **/
6701static void __exit
6702qla2x00_module_exit(void)
6703{
6a03b4cd 6704 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 6705 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 6706 qla2x00_release_firmware();
354d6b21 6707 kmem_cache_destroy(srb_cachep);
2d70c103 6708 qlt_exit();
a9083016
GM		 6709 if (ctx_cachep)
6710 kmem_cache_destroy(ctx_cachep);
1da177e4 6711 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 6712 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 6713}
6714
6715module_init(qla2x00_module_init);
6716module_exit(qla2x00_module_exit);
6717
6718MODULE_AUTHOR("QLogic Corporation");
6719MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
6720MODULE_LICENSE("GPL");
6721MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 6722MODULE_FIRMWARE(FW_FILE_ISP21XX);
6723MODULE_FIRMWARE(FW_FILE_ISP22XX);
6724MODULE_FIRMWARE(FW_FILE_ISP2300);
6725MODULE_FIRMWARE(FW_FILE_ISP2322);
6726MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 6727MODULE_FIRMWARE(FW_FILE_ISP25XX);
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